NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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...............2............. 44 Scalar Conversions ............0 4.............................................5................ Texture.6..............................................................4..........................5.....4......................... 5...........................................................2...6..................4.4................................................................ Abstracting the ABI .............................................................................1.......................................................................................... State Spaces .. 38 Initializers ....... 6................................... and Surface Types ....... 47 Chapter 7............... 37 Array Declarations .................... 33 Restricted Use of Sub-Word Sizes ..............1..... 6..... 6.............. 5. 37 Variable Declarations .....................4.............................................................................................2...4.....1..................................................... 28 Constant State Space .......... 41 Destination Operands ..................................................4............................ 49 ii January 24.................................. 28 Special Register State Space ................................... Type Conversion..... 6...................5. 25 Chapter 5....5...........3........................................................................... 44 Rounding Modifiers ................................................. 29 Global State Space ..........................................................................................3............................................... 5...........................................................................................................3..................................................................................................1..PTX ISA Version 2. 43 6. Chapter 6......... 43 Labels and Function Names as Operands .................................. 5..... 6............ 32 Texture State Space (deprecated) ..... Operand Type Information ... 5........4......................1..................1. Function declarations and definitions ................... 5...6.................................................................. 41 Source Operands.................................... 5............................... Instruction Operands............................................................................................. 5.8.........................1....... 34 Variables ...............................................1...... 42 Arrays as Operands ........................................................................................... 29 Parameter State Space ......................................... 42 Addresses as Operands ............. 41 6.........2............................... 5................1........... 37 Vectors ...............................................7............................... Operand Costs .....................................3.............................1........2.....................4.......................................... Types.................................................................. 30 Shared State Space............................................................................................................5........ 5...................................2... 5... 5................................................ 2010 ... 49 7....................................................1..........1.......2.....1...4.............. 29 Local State Space ...........2............. 6................ State Spaces......1.................................... 39 5...................................................... Arrays. 33 Fundamental Types ...............4...... 43 Vectors as Operands ......... 33 5.......................... 32 5.................................... 39 Parameterized Variable Names . 27 5......4..... 5................... 41 Using Addresses.......... Types ......... and Vectors .. 5..................................... 27 Register State Space .................. 38 Alignment ........................ 6.. 5.....1............1................................ Sampler.....................2.. 6.................... and Variables ........................ 46 6.......4.............4..........6.................................. 6..................................4............................. Summary of Constant Expression Evaluation Rules ...................................................................................................3.............. 5.............................5.....

.................. 55 8................................................................................................................ 56 Comparisons .................. 2010 iii ............................................. 8.3...........3.................................................1..............2................................................................ 57 Manipulating Predicates .......2..................................3............... 108 Texture and Surface Instructions ................................... 54 Chapter 8........... 147 8............... 11. 157 Specifying Kernel Entry Points and Functions ..........4.......... 172 January 24........7..... 10...... 8........ Release Notes ............................................4........................................................................................................ 53 Alloca ........1.....................7..........................................7......... 8.......... Chapter 9.......................................................................... 8.........1...................................1.......................................... 55 Predicated Execution .................2....1.. 7......................... 8... 170 Semantic Changes and Clarifications .... 100 Logic and Shift Instructions ...........................1.............................. 63 Integer Arithmetic Instructions ........0 ........... 11.......................4........................................................ 11... 170 New Features ............. Instruction Set ........... 58 8.......2......................................... Directives .10............. 149 Chapter 10............................................................ 172 Unimplemented Features Remaining ..........7........... 8................x ............................................................3.................................................. PTX Version and Target Directives ............7........ 8.... 8..6. 8.............3............................................7.....................................................7.............7......................9............................................ 8........................6.................4..2..................5............................. 8.............................................................7......................................... 169 11....7................. 81 Comparison and Selection Instructions .... 55 PTX Instructions .........................1..............1...............................................................................................6................1.................................7............ 162 Debugging Directives .. 62 Semantics .........1..........................................7... 62 8............................. Instructions .................. 52 Variadic functions ............................. 10......................... 8................................................. 168 Chapter 11............................... 157 10............ 62 Machine-Specific Semantics of 16-bit Code .........................................5............. 8.................... 59 Operand Size Exceeding Instruction-Type Size ...................... 132 Video Instructions ........................... Format and Semantics of Instruction Descriptions ................................ 63 Floating-Point Instructions ...............................................................1...............................................................................3.......... Divergence of Threads in Control Constructs .......................6................8....... 8....................................................................................2................................................ 122 Control Flow Instructions ............................ 60 8.........................................1................... Changes in Version 2.... 8.. 129 Parallel Synchronization and Communication Instructions ..................... Special Registers .....7........................................... 10........... 8............................................................. Type Information for Instructions and Operands ..... 160 Performance-Tuning Directives .... Changes from PTX 1................................................. 104 Data Movement and Conversion Instructions .3....................... 10................. 7........ 166 Linking Directives ......................................1.................. 140 Miscellaneous Instructions....

..................... 173 iv January 24.....pragma Strings........... 2010 ............... Descriptions of ....PTX ISA Version 2.0 Appendix A...........

................................................. 23 Constant Expression Evaluation Rules ................................. Table 21........................................ Table 20......................................................... Table 8.................... Table 27.......................................................................... Table 23..................... PTX Directives ...................... Table 15........................................... 61 Integer Arithmetic Instructions: add ...... 66 Integer Arithmetic Instructions: mul . Table 25................................................cc ......................List of Tables Table 1...................................................................... 57 Floating-Point Comparison Operators Accepting NaN ...... Table 14................................................ 58 Floating-Point Comparison Operators Testing for NaN .. Table 17.......................... 27 Properties of State Spaces ......... Table 3................................................................ Table 24............ 35 Opaque Type Fields in Independent Texture Mode ............................................................................................................................................................................. Table 29......................... 33 Opaque Type Fields in Unified Texture Mode .............................................. 60 Relaxed Type-checking Rules for Destination Operands............................... Table 11......... 71 January 24........................................ 68 Integer Arithmetic Instructions: mul24 .. Table 32............................................... 67 Integer Arithmetic Instructions: mad .... 57 Floating-Point Comparison Operators .......... Table 7.......................................................................................................................... 58 Type Checking Rules .............................. Table 19...................... 69 Integer Arithmetic Instructions: mad24 ..... 46 Cost Estimates for Accessing State-Spaces ..... Table 2....................... Table 16..................................................................................................... Table 30. 20 Operator Precedence ......................................... Table 26.......... 35 Convert Instruction Precision and Format ................. 70 Integer Arithmetic Instructions: sad .................. Unsigned Integer.... Table 5............. 28 Fundamental Type Specifiers .................. 64 Integer Arithmetic Instructions: add.................................................................. Table 28.................................... 65 Integer Arithmetic Instructions: addc ................................ 46 Integer Rounding Modifiers ......... Table 12......... Table 10.............................. Table 22............................... Table 9................................. 45 Floating-Point Rounding Modifiers .................................................................................... 47 Operators for Signed Integer. and Bit-Size Types ................................... 59 Relaxed Type-checking Rules for Source Operands ...................................................cc ............. Table 6... 65 Integer Arithmetic Instructions: sub........................ Table 31........ 64 Integer Arithmetic Instructions: sub ................................................................................ Table 13.................... 25 State Spaces .......................... 66 Integer Arithmetic Instructions: subc .......... 19 Predefined Identifiers .................................. Table 4....................................... 2010 v ........................................................................................................ Table 18................................... 18 Reserved Instruction Keywords ...........................

..................................................................................................................................... 73 Integer Arithmetic Instructions: max ............. Table 62.............................................................................................................0 Table 33..... 84 Floating-Point Instructions: sub ........................ 72 Integer Arithmetic Instructions: neg ...... Table 35........................................................................... Table 59............. 92 Floating-Point Instructions: max ........................................................................................... 79 Summary of Floating-Point Instructions .................................................. 78 Integer Arithmetic Instructions: prmt ............... 86 Floating-Point Instructions: fma ............. Table 60...... 73 Integer Arithmetic Instructions: popc ....................... 83 Floating-Point Instructions: add ..... Table 65.......................................... 72 Integer Arithmetic Instructions: min .................................... Table 64................................. Table 41.... 71 Integer Arithmetic Instructions: abs ..... 95 Floating-Point Instructions: sin .. 101 Comparison and Selection Instructions: setp ....................................... 88 Floating-Point Instructions: div ........ Table 49.......................... Table 48.............. 92 Floating-Point Instructions: rcp .................... 74 Integer Arithmetic Instructions: clz .....................................PTX ISA Version 2....................... 85 Floating-Point Instructions: mul ............................................. 75 Integer Arithmetic Instructions: brev ............. 96 Floating-Point Instructions: cos ........... 103 vi January 24...... Table 52........................... Table 37......... Table 42.................................................................... Table 51............................................................................... Table 43............................... Table 68.............. Table 57.................... 71 Integer Arithmetic Instructions: rem ................ 74 Integer Arithmetic Instructions: bfind ................................................................... 76 Integer Arithmetic Instructions: bfe ................................................ Table 53.............................................. Table 69......................................... Table 46................................................................................................................................................ Table 66................................................................ Table 47.................................................. Table 38....................................................................... Table 36........................................ Table 40.................. 87 Floating-Point Instructions: mad ...... 93 Floating-Point Instructions: sqrt ............................................................. Table 56..................................... 2010 ...................................................................................................................................................................................... Table 50.................................................. 102 Comparison and Selection Instructions: selp . Table 44......... Table 55........................... 82 Floating-Point Instructions: testp ............................................................................. 99 Comparison and Selection Instructions: set ........................ Table 45......................................... 91 Floating-Point Instructions: neg ..................................... Table 39......... Table 67...................... 83 Floating-Point Instructions: copysign ............... Table 54........................ 77 Integer Arithmetic Instructions: bfi ........................... Table 63...................................... Table 61. 91 Floating-Point Instructions: min ........... 103 Comparison and Selection Instructions: slct ...................... 94 Floating-Point Instructions: rsqrt ............... Table 58......................................................................... Table 34.................................. 90 Floating-Point Instructions: abs ........................................... 98 Floating-Point Instructions: ex2 .... Integer Arithmetic Instructions: div ...... 97 Floating-Point Instructions: lg2 ......................................................................................................................

.............................. 111 Data Movement and Conversion Instructions: mov .............................................................................................. 124 Texture and Surface Instructions: suld ..................................................................... 116 Data Movement and Conversion Instructions: prefetch.................. 137 Parallel Synchronization and Communication Instructions: vote .... Table 84........................... Table 92.............. Table 71....... Table 74...... 134 Parallel Synchronization and Communication Instructions: atom ............................. Table 96............................................. 128 Control Flow Instructions: { } .................... vabsdiff.............................. Table 87... Table 100................................................................................................... vshr .......................................... Table 72...... 109 Cache Operators for Memory Store Instructions ....... 118 Data Movement and Conversion Instructions: isspacep ...................................... Table 86. 143 January 24.................. 2010 vii ............................................. 106 Logic and Shift Instructions: not .... 129 Control Flow Instructions: bra ............................................. Table 90.......................................... Table 91..... 120 Texture and Surface Instructions: tex ............... 125 Texture and Surface Instructions: sust ...................................................... Table 88....................... 129 Control Flow Instructions: @ ................ Table 85.... Table 79.............................. vmax ... 135 Parallel Synchronization and Communication Instructions: red ...... 105 Logic and Shift Instructions: or ................................................ Table 73....... 110 Data Movement and Conversion Instructions: mov ............................................ vmin................................. Table 97.............. 107 Cache Operators for Memory Load Instructions ................................................................... 113 Data Movement and Conversion Instructions: ldu .................................................................. 119 Data Movement and Conversion Instructions: cvta . Logic and Shift Instructions: and .. Table 82......................................................... 130 Control Flow Instructions: ret . Table 80.......................................... 105 Logic and Shift Instructions: xor ......... Table 77..... Table 102........................ 119 Data Movement and Conversion Instructions: cvt ................................ Table 78......................... Table 98......... 115 Data Movement and Conversion Instructions: st ..... Table 106................ vsub...... Table 83. 106 Logic and Shift Instructions: shl ........................... 133 Parallel Synchronization and Communication Instructions: membar .......................................................................................................... Table 104................. Table 103............................................. 131 Parallel Synchronization and Communication Instructions: bar ..Table 70...................................................... Table 94..... prefetchu ................................ 127 Texture and Surface Instructions: suq ......................................................... Table 93............................................... 106 Logic and Shift Instructions: cnot ....................................... Table 89............. 123 Texture and Surface Instructions: txq ......................................... Table 101........................ Table 99.............. Table 105...... Table 76........... 126 Texture and Surface Instructions: sured.. 142 Video Instructions: vshl............................. Table 75........................................................... 130 Control Flow Instructions: call .. Table 95. 112 Data Movement and Conversion Instructions: ld ..................................................................................... 131 Control Flow Instructions: exit ........................................................... 139 Video Instructions: vadd... Table 81................................... 107 Logic and Shift Instructions: shr .

........ 155 Special Registers: %lanemask_gt ...................... 167 Debugging Directives: ...loc ................. Table 128..........................target .....func ... 154 Special Registers: %lanemask_lt ........entry................................................................. 161 Performance-Tuning Directives: ..................... Table 120........................................................................................................ Table 132.................................................................... 2010 ....................................................... 150 Special Registers: %laneid ................................... %pm2.. Table 116.....maxnctapersm (deprecated) ......................................... 154 Special Registers: %lanemask_le ....................................... 164 Performance-Tuning Directives: ................... %pm1.........................................0 Table 107................ Table 134................................................................... 167 Debugging Directives: .............................. 160 Kernel and Function Directives: ................................................................................ Table 125... Table 137. 150 Special Registers: %ntid .............................................. Table 121................................................................................ Table 118.......................... 151 Special Registers: %ctaid ................. Table 140............ 157 PTX File Directives: ............................ Table 117......................... Table 114.............................. Table 143............... Table 112........ Table 110... 147 Miscellaneous Instructions: pmevent.............. Table 133......... 166 Debugging Directives: ........... Table 129....... 156 Special Registers: %pm0.......... 147 Miscellaneous Instructions: brkpt .. Table 111.....................................version.................................file ...............maxnreg ............................................... Table 124......minnctapersm .................................................................................................. 163 Performance-Tuning Directives: .................... %pm3 ........................ Video Instructions: vmad ....................................................................... Table 138....................... Table 108.... Table 113.............. 165 Debugging Directives: @@DWARF ..................... Table 136.... 156 PTX File Directives: .............................................................................. Table 131....................section .................................................... Table 122.......................... 154 Special Registers: %lanemask_ge ............................................................... 153 Special Registers: %gridid ....................................................maxntid ........................ 147 Special Registers: %tid ................... 155 Special Registers: %clock ................. 151 Special Registers: %nwarpid .........................................pragma ....................................PTX ISA Version 2.............................. 153 Special Registers: %nsmid .............. Table 127........ 151 Special Registers: %warpid ............. 158 Kernel and Function Directives: ...... Table 126................................................................................ 164 Performance-Tuning Directives: ........ Table 115......... 163 Performance-Tuning Directives: .............................................................................. 146 Miscellaneous Instructions: trap ....... 152 Special Registers: %smid ...................................................................................................................................................................................................................... 152 Special Registers: %nctaid ............................................ Table 123............. Table 130......... Table 142...extern......... Table 109..................................... 167 Linking Directives: ............. Table 119. 153 Special Registers: %lanemask_eq .......................... 168 viii January 24... 144 Video Instructions: vset........ Table 135........................................... 156 Special Registers: %clock64 ........ Table 141........ Table 139............................................................................

........................................Table 144.......visible.... Table 145................................. 168 Pragma Strings: “nounroll” ......................................................... Linking Directives: .......... 173 January 24.. 2010 ix ..................

0 x January 24. 2010 .PTX ISA Version 2.

many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. multithreaded. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture.2. PTX defines a virtual machine and ISA for general purpose parallel thread execution. video encoding and decoding. image and media processing applications such as post-processing of rendered images. from general signal processing or physics simulation to computational finance or computational biology. there is a lower requirement for sophisticated flow control. the memory access latency can be hidden with calculations instead of big data caches. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). 2010 1 . January 24. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. In fact. and because it is executed on many data elements and has high arithmetic intensity. 1.Chapter 1. image scaling. 1. Data-parallel processing maps data elements to parallel processing threads. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. the programmable GPU has evolved into a highly parallel. and pattern recognition can map image blocks and pixels to parallel processing threads.1. PTX exposes the GPU as a data-parallel computing device. Similarly. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. PTX programs are translated at install time to the target hardware instruction set. which are optimized for and translated to native target-architecture instructions. Introduction This document describes PTX. Because the same program is executed for each data element. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. high-definition 3D graphics. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. stereo vision. many-core processor with tremendous computational horsepower and very high memory bandwidth.

0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Achieve performance in compiled applications comparable to native GPU performance.x features are supported on the new sm_20 target. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.1. Both fma. and mul now support . PTX 2. The mad.3.0 is in improved support for the IEEE 754 floating-point standard. Legacy PTX 1.rm and . When code compiled for sm_1x is executed on sm_20 devices. • • • 2 January 24.f32 requires sm_20.f32 for sm_20 targets.ftz and . and architecture tests.sat modifiers. The mad. Facilitate hand-coding of libraries.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. fma. Instructions marked with .x code will continue to run on sm_1x targets as well.rn. addition of generic addressing to facilitate the use of general-purpose pointers.f32.x.0 is a superset of PTX 1.rp rounding modifiers for sm_20 targets. Provide a common source-level ISA for optimizing code generators and translators. Most of the new features require a sm_20 target.3.f32 instruction also supports . and video instructions.PTX ISA Version 2.f32 require a rounding modifier for sm_20 targets. including integer.0 PTX ISA Version 2. sub. and the introduction of many new instructions. 2010 .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. barrier.0 are improved support for IEEE 754 floating-point operations. memory. Improved Floating-Point Support A main area of change in PTX 2. A single-precision fused multiply-add (fma) instruction has been added. Single-precision add. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The main areas of change in PTX 2. performance kernels.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. 1. The changes from PTX ISA 1.f32 maps to fma. PTX ISA Version 2.f32 and mad. A “flush-to-zero” (. and all PTX 1. 1. The fma. Provide a machine-independent ISA for C/C++ and other compilers to target. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. reduction.ftz) modifier may be used to enforce backward compatibility with sm_1x. surface. atomic. mad.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Provide a code distribution ISA for application and middleware developers. which map PTX to specific target machines.

clamp and . prefetchu. stack layout. special registers. and shared state spaces.. so recursion is not yet supported. Generic addressing unifies the global. Surface Instructions • • Instruction sust now supports formatted surface stores.e. suld. 1. Instructions prefetch and prefetchu have been added.and double-precision div. Instruction cvta for converting global. and shared addresses to generic address and vice-versa has been added. Cache operations have been added to instructions ld. i. and directives are introduced in PTX 2. 2010 3 . Generic Addressing Another major change is the addition of generic addressing. These are indicated by the use of a rounding modifier and require sm_20.zero. . stack-based ABI. and vice versa. local. New Instructions The following new instructions. Surface instructions support additional clamp modifiers. NOTE: The current version of PTX does not implement the underlying. prefetch.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. • Taken as a whole.3. local. Introduction • Single. isspacep.0 closer to full compliance with the IEEE 754 standard. these changes bring PTX 2. January 24. st. and sust. st. atom. instructions ld.3.2.0. ldu. e. allowing memory instructions to access these spaces without needing to specify the state space. 1. rcp. and red now support generic addressing.3. and sqrt with IEEE 754 compliant rounding have been added.4.0. local. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.3. Support for an Application Binary Interface Rather than expose details of a particular calling convention. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. for prefetching to specified level of memory hierarchy.g. an address that is the same across all threads in a warp. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.Chapter 1. In PTX 2. and Application Binary Interface (ABI). 1. cvta. PTX 2. Instructions testp and copysign have been added. and shared addresses to generic addresses. A new cvta instruction has been added to convert global.

bar now supports an optional thread count and register operands.popc.arrive instruction has been added. Other Extensions • • • Video instructions (includes prmt) have been added.red}.gt} have been added.le.red. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.lt. has been added. membar.shared have been extended to handle 64-bit data types for sm_20 targets.pred have been added.f32 have been added. Instructions {atom.add.{and. 4 January 24. Reduction. bfi bit field extract and insert popc clz Atomic. %lanemask_{eq.section. Instructions bar.ge.ballot.red}.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.or}.red.sys. 2010 .PTX ISA Version 2. vote.b32. A new directive. .u32 and bar. A “vote ballot” instruction. and Vote Instructions • • • New atomic and reduction instructions {atom. New special registers %nsmid. A bar. %clock64. Barrier Instructions • • A system-level membar instruction.

0. Chapter 7 describes the function and call syntax. types. Chapter 4 describes the basic syntax of the PTX language. 2010 5 . Chapter 9 lists special registers. Chapter 10 lists the assembly directives supported in PTX. and variable declarations. Chapter 8 describes the instruction set.4. Chapter 11 provides release notes for PTX Version 2. Introduction 1. January 24. Chapter 5 describes state spaces. calling convention.Chapter 1. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 6 describes instruction operands. Chapter 3 gives an overview of the PTX virtual machine model. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.

PTX ISA Version 2.0 6 January 24. 2010 .

More precisely.x. It operates as a coprocessor to the main CPU. is an array of threads that execute a kernel concurrently or in parallel. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. compute addresses. Cooperative thread arrays (CTAs) implement CUDA thread blocks. Programming Model 2. 2010 7 . 2D. but independently on different data. and select work to perform. and tid. The vector ntid specifies the number of threads in each CTA dimension. The thread identifier is a three-element vector tid. and ntid. work. January 24.1. or CTA. Each CTA has a 1D. 2D. a portion of an application that is executed many times. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. compute-intensive portions of applications running on the host are off-loaded onto the device. or 3D shape specified by a three-element vector ntid (with elements ntid.2.z) that specifies the thread’s position within a 1D. and results across the threads of the CTA. Each CTA thread uses its thread identifier to determine its assigned role. can be isolated into a kernel function that is executed on the GPU as many different threads. To coordinate the communication of the threads within the CTA.Chapter 2. data-parallel. or 3D CTA. A cooperative thread array. (with elements tid. assign specific input and output positions. one can specify synchronization points where threads wait until all threads in the CTA have arrived. ntid.1. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Threads within a CTA can communicate with each other.z). To that effect.2. 2. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.y. Each thread has a unique thread identifier within the CTA. tid. Programs use a data parallel decomposition to partition inputs.y. or host: In other words. 2.x.

2. %ntid. This comes at the expense of reduced thread communication and synchronization. Each grid also has a unique temporal grid identifier (gridid). Multiple CTAs may execute concurrently and in parallel. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. a warp has 32 threads. read-only special registers %tid. Some applications may be able to maximize performance with knowledge of the warp size. The host issues a succession of kernel invocations to the device. or 3D shape specified by the parameter nctaid. Each grid of CTAs has a 1D. such that the threads execute the same instructions at the same time. Threads within a warp are sequentially numbered. multiple-thread) fashion in groups called warps. The warp size is a machine-dependent constant. WARP_SZ. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). 2D . and %gridid. depending on the platform.PTX ISA Version 2. so that the total number of threads that can be launched in a single kernel invocation is very large. Typically. 2. Threads may read and use these values through predefined. or sequentially.2. However. 2010 . because threads in different CTAs cannot communicate and synchronize with each other. CTAs that execute the same kernel can be batched together into a grid of CTAs.0 Threads within a CTA execute in SIMT (single-instruction. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. so PTX includes a run-time immediate constant. %nctaid. %ctaid. A warp is a maximal subset of threads from a single CTA. which may be used in any instruction where an immediate operand is allowed. 8 January 24.

0) Thread (4. 1) Thread (3. A grid is a set of CTAs that execute independently. Figure 1. 0) Thread (1. 1) Thread (4. 0) CTA (0. 1) Thread (1. 1) Thread (2. 1) Grid 2 Kernel 2 CTA (1. 1) Thread (0.Chapter 2. 0) CTA (1. 0) Thread (2. 2010 9 . 2) Thread (4. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (3. 1) CTA (1. 2) Thread (2. 1) CTA (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. Thread Batching January 24. 1) Thread (0. 2) Thread (1. 0) CTA (2. 0) Thread (3. 0) Thread (0.

0 2. Both the host and the device maintain their own local memory. as well as data filtering. respectively. and texture memory spaces are optimized for different memory usages. 10 January 24. constant. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. referred to as host memory and device memory. The device memory may be mapped and read or written by the host. Finally.PTX ISA Version 2. and texture memory spaces are persistent across kernel launches by the same application. constant. Texture memory also offers different addressing modes. Each thread has a private local memory.3. all threads have access to the same global memory. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. for some specific data formats. or. 2010 . There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. for more efficient transfer. The global.

Chapter 2. 0) Block (2. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (1. Memory Hierarchy January 24. 1) Block (1. 2010 11 . 1) Grid 1 Global memory Block (0. 1) Block (1. 0) Block (0. 1) Block (2. 1) Block (0. 0) Block (1. 2) Figure 2. 2) Block (1.

PTX ISA Version 2.0 12 January 24. 2010 .

disabling threads that are not on that path. and on-chip shared memory. and executes concurrent threads in hardware with zero scheduling overhead. the warp serially executes each branch path taken. schedules. The multiprocessor SIMT unit creates.Chapter 3. a multithreaded instruction unit. Parallel Thread Execution Machine Model 3. each warp contains threads of consecutive. increasing thread IDs with the first warp containing thread 0. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. As thread blocks terminate. The way a block is split into warps is always the same. If threads of a warp diverge via a data-dependent conditional branch. and executes threads in groups of parallel threads called warps. When a multiprocessor is given one or more thread blocks to execute. a cell in a grid-based computation). Branch divergence occurs only within a warp. January 24. At every instruction issue time.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). The multiprocessor maps each thread to one scalar processor core. it splits them into warps that get scheduled by the SIMT unit. It implements a single-instruction barrier synchronization. for example. and each scalar thread executes independently with its own instruction address and register state. different warps execute independently regardless of whether they are executing common or disjointed code paths. new blocks are launched on the vacated multiprocessors. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. so full efficiency is realized when all threads of a warp agree on their execution path. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. the threads converge back to the same execution path. To manage hundreds of threads running several different programs. A multiprocessor consists of multiple Scalar Processor (SP) cores. 2010 13 . allowing. The multiprocessor creates. a voxel in a volume. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. When a host program invokes a kernel grid. The threads of a thread block execute concurrently on one multiprocessor. manages.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. the multiprocessor employs a new architecture we call SIMT (single-instruction. and when all paths complete. A warp executes one common instruction at a time. (This term originates from weaving. the first parallel thread technology. multiple-thread). manages.

SIMT enables programmers to write thread-level parallel code for independent. scalar threads. If there are not enough registers or shared memory available per multiprocessor to process at least one block. which is a read-only region of device memory. the kernel will fail to launch. the number of serialized writes that occur to that location and the order in which they occur is undefined. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. In contrast with SIMD vector machines. Vector architectures. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. each read. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. require the software to coalesce loads into vectors and manage divergence manually. • The local and global memory spaces are read-write regions of device memory and are not cached. A key difference is that SIMD vector organizations expose the SIMD width to the software. but one of the writes is guaranteed to succeed. As illustrated by Figure 3. whereas SIMT instructions specify the execution and branching behavior of a single thread. which is a read-only region of device memory. modifies. but the order in which they occur is undefined. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. and writes to the same location in global memory for more than one of the threads of the warp.0 SIMT architecture is akin to SIMD (Single Instruction. as well as data-parallel code for coordinated threads. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. the programmer can essentially ignore the SIMT behavior. modify. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. write to that location occurs and they are all serialized. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. however. In practice. on the other hand.PTX ISA Version 2. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A multiprocessor can execute as many as eight thread blocks concurrently. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. 2010 . For the purposes of correctness. 14 January 24. If an atomic instruction executed by a warp reads.

Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 .Chapter 3. Hardware Model January 24.

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Lines beginning with # are preprocessor directives. Each PTX file must begin with a .2. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor.version directive specifying the PTX language version. 2010 17 .1. Source Format Source files are ASCII text. and using // to begin a comment that extends to the end of the current line. Comments in PTX are treated as whitespace.Chapter 4. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #else. followed by a . The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 4. PTX is case sensitive and uses lowercase for keywords. 4. Lines are separated by the newline character (‘\n’). See Section 9 for a more information on these directives. Comments Comments in PTX follow C/C++ syntax.target directive specifying the target architecture assumed. whitespace is ignored except for its use in separating tokens in the language. #ifdef. All whitespace characters are equivalent. January 24. #endif. Pseudo-operations specify symbol and addressing management. #line. The following are common preprocessor directives: #include. Syntax PTX programs are a collection of text source files. The C preprocessor cpp may be used to process PTX source files. #define. using non-nested /* and */ for comments that may span multiple lines. #if.

r1.target .func .visible 4. 18 January 24. . followed by source operands. 2010 .sreg .maxntid .f32 array[N]. %tid. shl.reg . The destination operand is first. Examples: . The guard predicate may be optionally negated.tex .global.2. Table 1.shared .section . address expressions. array[r1].pragma . r2. mov.entry .b32 add.global start: .b32 r1.version . Statements A PTX statement is either a directive or an instruction.const . The guard predicate follows the optional label and precedes the opcode. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. and terminated with a semicolon.3. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. .f32 r2.maxnctapersm . All instruction keywords are reserved tokens in PTX. constant expressions. ld. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.minnctapersm .3.x.PTX ISA Version 2. 0. so no conflict is possible with user-defined identifiers.align .b32 r1. where p is a predicate register. Instruction keywords are listed in Table 2. Instructions have an optional guard predicate which controls conditional execution.5.local . and is written as @p.global . or label names. Operands may be register variables.extern .file PTX Directives .1.maxnreg .b32 r1.loc . r2. Directive Statements Directive keywords begin with a dot. r2. 2.3. written as @!p.0 4.param .reg . Statements begin with an optional label and end with a semicolon.

2010 19 .Chapter 4. Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

0 4. The percentage sign can be used to avoid name conflicts. or percentage character followed by one or more letters. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. Table 3. digits. listed in Table 3. or they start with an underscore. dollar. or dollar characters.g. …. except that the percentage sign is not allowed. Many high-level languages such as C and C++ follow similar rules for identifier names. underscore. %pm3 WARP_SZ 20 January 24. e. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.4. PTX allows the percentage sign as the first character of an identifier. between user-defined variable names and compiler-generated names. PTX predefines one constant and a small number of special registers that begin with the percentage sign. 2010 . digits.PTX ISA Version 2. underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.

Chapter 4. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. To specify IEEE 754 single-precision floating point values.5. i.e. When used in an instruction or data initialization. To specify IEEE 754 doubleprecision floating point values.5. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. every integer constant has type .2.1. Unlike C and C++. integer constants are allowed and are interpreted as in C. Floating-point literals may be written with an optional decimal point and an optional signed exponent. literals are always represented in 64-bit double-precision format. in which case the literal is unsigned (. or binary notation.5. octal. These constants may be used in data initialization and as operands to instructions.u64). zero values are FALSE and non-zero values are TRUE. floating-point. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. the constant begins with 0d or 0D followed by 16 hex digits. For predicate-type data and instructions. Constants PTX supports integer and floating-point constants and constant expressions. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.. the constant begins with 0f or 0F followed by 8 hex digits. hexadecimal.s64 or the unsigned suffix is specified. i.s64) unless the value cannot be fully represented in .e. where the behavior of the operation depends on the operand types. Syntax 4.u64. 0[fF]{hexdigit}{8} // single-precision floating point January 24. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.. Type checking rules remain the same for integer. 2010 21 . there is no suffix letter to specify size. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. and bit-size types. 4. Integer literals may be written in decimal.s64 or . The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. 4. The syntax follows that of C. the sm_1x and sm_20 targets have a WARP_SZ value of 32. each integer constant is converted to the appropriate size based on the data or instruction type at its use.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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f64 : .f64 use usual conversions . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table. .u64 . or .f64 converted type .s64 .s64 .f64 use usual conversions .s64 .u64 same as 1st operand .u64. Table 5.s64.5.u64 .u64) (.s64 .f64 integer .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 use usual conversions .s64) + .f64 converted type constant literal + ! ~ Cast Binary (.u64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64 1st unchanged.Chapter 4.f64 same as source .s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 integer integer integer integer integer int ?.6. Syntax 4.s64 .s64 .s64 . 2nd is .u64 .f64 integer . 2010 25 .u64 .u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .

0 26 January 24.PTX ISA Version 2. 2010 .

and Variables While the specific resources available in a given target GPU will vary.param . State Spaces. and level of sharing between threads.shared .sreg .global . and properties of state spaces are shown in Table 5. Name State Spaces Description Registers. Global memory. platform-specific. Global texture memory (deprecated). shared by all threads. Kernel parameters.Chapter 5. defined per-grid. Local memory. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Types. 2010 27 . State Spaces A state space is a storage area with particular characteristics. Table 6. Addressable memory shared between threads in 1 CTA.const . All variables reside in some state space.1. the kinds of resources will be common across platforms. access rights. fast. defined per-thread. Shared. addressability. 5. access speed. The list of state spaces is shown in Table 4.local . pre-defined. Special registers. .tex January 24. The characteristics of a state space include its size. and these resources are abstracted in PTX through state spaces and data types. Read-only. read-only memory.reg . or Function or local parameters. private to each thread.

param (used in functions) . Registers differ from the other state spaces in that they are not fully addressable.PTX ISA Version 2.local state space.reg .1. Device function input parameters may have their address taken via mov. 3 Accessible only via the tex instruction. or as elements of vector tuples. i. or 128-bits. 64-.1. it is not possible to refer to the address of a register. Special Register State Space The special register (.0 Table 7. For each architecture. register variables will be spilled to memory. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). platform-specific registers.reg state space) are fast storage locations. The number of registers is limited.global . Register size is restricted. such as grid. clock counters. scalar registers have a width of 8-. and thread parameters.param instructions. 1 Accessible only via the ld.sreg . 5.const . 2 Accessible via ld.shared .sreg) state space holds predefined. aside from predicate registers which are 1-bit. unsigned integer. floating point. and performance monitoring registers. causing changes in performance. and vector registers have a width of 16-. the parameter is then located on the stack frame and its address is in the . All special registers are predefined.1. Register State Space Registers (. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. and will vary from platform to platform. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 2010 ..param instruction. and cvt instructions.param (as input to kernel) .local . st. 16-. When the limit is exceeded. CTA.e.param and st.2. or 64-bits. predicate) or untyped. The most common use of 8-bit registers is with ld.tex Restricted Yes No3 5. Registers may be typed (signed integer. Address may be taken via mov instruction. 32-. Registers may have alignment boundaries required by multi-word loads and stores. 32-. 28 January 24.

If another thread sees the variable b change. Local State Space The local state space (.1.Chapter 5. ld.global) state space is memory that is accessible by all threads in a context.extern . The size is limited.const[2] . and Variables 5. For the current devices. For example. the stack is in local memory. [const_buffer+4]. st.sync instruction are guaranteed to be visible to any reads after the barrier instruction. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. where the size is not known at compile time. By convention. Threads must be able to do their work without waiting for other threads to do theirs.extern . 5. for example). bank zero is used.global. all addresses are in global memory are shared. an incomplete array in bank 2 is accessed as follows: . It is the mechanism by which different CTAs and different grids can communicate. // load second word 5. as it must be allocated on a perthread basis.b32 const_buffer[]. Constant State Space The constant (. It is typically standard memory with cache. Global State Space The global (.3.5. as in lock-free and wait-free style programming. there are eleven 64KB banks. the store operation updating a may still be in flight. where bank ranges from 0 to 10.global to access global variables. Types.local and st.1. Threads wait at the barrier until all threads in the CTA have arrived.b32 %r1. This pointer can then be used to access the entire 64KB constant bank. Module-scoped local memory variables are stored at fixed addresses. the declaration . the bank number must be provided in the state space of the load instruction. results in const_buffer pointing to the start of constant bank two. Banks are specified using the . whereas local memory variables declared January 24. If no bank number is given. Global memory is not sequentially consistent.local) is private memory for each thread to keep its own data.const[2] . 2010 29 . Use ld. In implementations that support a stack.local to access local variables. initialized by the host.1.const[2].global. Consider the case where one thread executes the following two assignments: a = a + 1. Sequential consistency is provided by the bar. Use ld. This reiterates the kind of parallelism available in machines that run PTX. All memory writes prior to the bar. For any thread in a context.sync instruction.4.b32 const_buffer[]. Multiple incomplete array variables declared in the same bank become aliases. The remaining banks may be used to implement “incomplete” constant arrays (in C. The constant memory is organized into fixed size banks. b = b – 1. bank zero is used for all statically-sized constant variables.const[bank] modifier. State Spaces. To access data in contant banks 1 through 10. and atom.const) state space is a read-only memory. each pointing to the start address of the specified constant bank. For example.

The kernel parameter variables are shared across all CTAs within a grid.f64 %d. … 30 January 24. [%ptr].f64 %d. Therefore. Values passed from the host to the kernel are accessed through these parameter variables using ld.b8 buffer[64] ) { . Note: The location of parameter space is implementation specific.reg . [N]. For example.u32 %n. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. Example: . %n. read-only variables declared in the .param instructions. No access protection is provided between parameter and global space in this case. The address of a kernel parameter may be moved into a register using the mov instruction. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param state space and is accessed using ld.1. . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). ld. … Example: . all local memory variables are stored at fixed addresses and recursive function calls are not supported.param state space.1.0 within a function or kernel body are allocated on the stack. PTX code should make no assumptions about the relative locations or ordering of .param . 5.param space variables. typically for passing large structures by value to a function.align 8 . mov. ld. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. per-kernel versus per-thread).b32 N. In implementations that do not support a stack. 5. Parameter State Space The parameter (.param .u32 %ptr. Note that PTX ISA versions 1. The use of parameter state space for device function parameters is new to PTX ISA version 2. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.param) state space is used (1) to pass input arguments from the host to the kernel.reg .param instructions.1. The resulting address is in the .param. ld.x supports only kernel function parameters in .6. Similarly.reg .entry bar ( .PTX ISA Version 2. .u32 %n.param.param . [buffer].u32 %n.param.6.0 and requires target architecture sm_20.b32 len ) { . These parameters are addressable. len.u32 %ptr.entry foo ( . in some implementations kernel parameters reside in global memory.param space. device function parameters were previously restricted to the register state space. 2010 .

Device Function Parameters PTX ISA version 2. It is not possible to use mov to get the address of a return parameter or a locally-scoped .1. The most common use is for passing objects by value that do not fit within a PTX register. ld. the caller will declare a locally-scoped . [buffer+8].0 extends the use of parameter space to device function parameters. dbl.param.f64 %d. .param . [buffer]. x. Typically.b32 N.s32 x. … st.Chapter 5. } mystruct.b8 mystruct.2. such as C structures larger than 8 bytes. … See the section on function call syntax for more details. Function input parameters may be read via ld. In PTX. 2010 31 . State Spaces. .param. In this case. int y. call foo.reg . the address of a function input parameter may be moved into a register using the mov instruction.s32 [mystruct+8].param. ld.reg . is flattened.reg . .local state space and is accessed via ld.local instructions. This will be passed by value to a callee.param space is also required whenever a formal parameter has its address taken within the called function.6. Aside from passing structures by value. and Variables 5. mystruct). }.param and function return parameters may be written using st.s32 %y.reg .param.f64 [mystruct+0]. and so the address will be in the . Types. int y. which declares a . passed to foo … .align 8 .align 8 .param space variable. January 24.f64 dbl. . Note that the parameter will be copied to the stack if necessary.func foo ( . a byte array in parameter space is used.b8 buffer[12] ) { . … } // code snippet from the caller // struct { double d. Example: // pass object of type struct { double d.reg .param. .param formal parameter having the same size and alignment as the passed argument. it is illegal to write to an input parameter or read from a return parameter.f64 %d.local and st. (4.param byte array variable that represents a flattened C structure or union. st.param . .s32 %y.

2010 . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).shared) state space is a per-CTA region of memory for threads in a CTA to share data.7.u32 .tex . Multiple names may be bound to the same physical texture identifier. 32 January 24.tex directive is retained for backward compatibility. Shared memory typically has some optimizations to support the sharing.3 for the description of the . a legacy PTX definitions such as .tex .u32 tex_a. tex_f. tex_d. The . tex_d.u32 or . Shared State Space The shared (. Texture State Space (deprecated) The texture (.1. Use ld.u32 tex_a. Physical texture resources are allocated on a per-module granularity. where all threads read from the same address.shared to access shared variables.u32 . A texture’s base address is assumed to be aligned to a 16-byte boundary.texref tex_a. An address in shared memory can be read and written by any thread in a CTA. Another is sequential access from sequential threads. See Section 5. is equivalent to . For example. Example: .tex . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.tex state space are equivalent to module-scoped . It is shared by all threads in a context.texref type and Section 8.tex directive will bind the named texture memory variable to a hardware texture identifier.tex) state space is global memory accessed via the texture instruction. Texture memory is read-only.6 for its use in texture instructions.texref.7.0 5.PTX ISA Version 2. and .u32 . An error is generated if the maximum number of physical resources is exceeded.tex .1.global . where texture identifiers are allocated sequentially beginning with zero. and programs should instead reference texture memory through variables of type .tex .8. The .u64. tex_c.texref variables in the . and variables declared in the .shared and st. One example is broadcast. 5.tex variables are required to be defined in the global scope.global state space. The texture name must be of type .

. The following table lists the fundamental type specifiers for each basic type: Table 8.f32. stored.b8. The same typesize specifiers are used for both variable definitions and for typing instructions.u32. ld. .b32.s32. so their names are intentionally short. For example. . .2. . .u16.b64 . but typed variables enhance program readability and allow for better operand type checking. or converted to other types and sizes. and Variables 5.1.b8 instruction types are restricted to ld. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.s16. The . 2010 33 . st.s64 .b16. . and instructions operate on these types.u8. Restricted Use of Sub-Word Sizes The . Register variables are always of a fundamental type.f64 types. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . For convenience.s8. .Chapter 5. Operand types and sizes are checked against instruction types for compatibility. Fundamental Types In PTX. In principle.f32 and . .f16 floating-point type is allowed only in conversions to and from . . A fundamental type specifies both a basic type and a size.2. stored.u8. .f32 and .f16.2. and converted using regular-width registers. January 24. and . Signed and unsigned integer types are compatible if they have the same size. All floating-point instructions operate only on . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.2. . the fundamental types reflect the native data types supported by the target architectures. State Spaces. The bitsize type is compatible with any fundamental type having the same size.f64 types. Types 5.u64 . so that narrow values may be loaded. st. Types. all variables (aside from predicates) could be declared using only bit-size types.pred Most instructions have one or more type specifiers. needed to fully specify instruction behavior.f64 .s8. and cvt instructions. Two fundamental types are compatible if they have the same basic type and are the same size. 5.

Retrieving the value of a named member via query instructions (txq.0 5. sampler. allowing them to be defined separately and combined at the site of usage in the program.PTX ISA Version 2. These types have named fields similar to structures. In independent mode the fields of the .samplerref variables.texref type that describe sampler properties are ignored. texture and sampler information is accessed through a single . since these properties are defined by . passed as a parameter to functions. field ordering.samplerref. and . Creating pointers to opaque variables using mov. opaque_var.. Texture. and Surface Types PTX includes built-in “opaque” types for defining texture. and de-referenced by texture and surface load. and surface descriptor variables. but the pointer cannot otherwise be treated as an address. PTX has two modes of operation. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. For working with textures and samplers. In the unified mode. . The three built-in types are . suld. but all information about layout.texref handle. and overall size is hidden to a PTX program. 2010 . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. samplers.texref. suq). Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. 34 January 24. base address. and query instructions. sust. The following tables list the named members of each type for unified and independent texture modes.e. the resulting pointer may be stored to and loaded from memory. or surfaces via texture and surface load/store instructions (tex. accessing the pointer with ld and st instructions.{u32. texture and sampler information each have their own handle. Referencing textures. sured). Sampler. or performing pointer arithmetic will result in undefined results. In the independent mode. i.surfref.3.u64} reg. hence the term “opaque”. store.

surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. State Spaces. clamp_ogl. 2010 35 . clamp_to_border N/A N/A N/A N/A N/A . linear wrap.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_border 0.texref values . 1 ignored ignored ignored ignored . 1 nearest. clamp_ogl. Types.samplerref values N/A N/A N/A N/A nearest. Member width height depth Opaque Type Fields in Independent Texture Mode .Chapter 5. and Variables Table 9. linear wrap.texref values in elements in elements in elements 0. mirror. mirror. clamp_to_edge. clamp_to_edge. Member width height depth Opaque Type Fields in Unified Texture Mode .

these variables must be in the . .global state space.PTX ISA Version 2. these variables are declared in the .texref tex1. filter_mode = nearest }.global .texref my_texture_name.global . 36 January 24. As kernel parameters.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global .param state space. 2010 . Example: . . the types may be initialized using a list of static expressions assigning values to the named members.surfref my_surface_name. When declared at module scope.samplerref my_sampler_name. .global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. Example: .global . At module scope.

its name. 5. .shared . a variable declaration describes both the variable’s type and its state space.2.reg .global .struct float4 { . where the fourth element provides padding. etc. and Variables 5.global .0}. Variables In PTX. Vectors cannot exceed 128-bits in length.f32 V. In addition to fundamental types. A variable declaration names the space in which the variable resides.global .f64 is not allowed.reg .u32 loc.f32 bias[] = {-1.global .v4.v1. Three-element vectors may be handled by using a .4.v2 or . Vectors must be based on a fundamental type. an optional array size.s32 i. vector variables are aligned to a multiple of their overall size (vector length times base-type size).v4 . Predicate variables may only be declared in the register state space.u8 bg[4] = {0. an optional initializer.u16 uv.1.b8 v. 2010 37 . 0. Examples: . r. 5. and they may reside in the register space. // a length-4 vector of bytes By default.v4. This is a common case for three-dimensional grids. . Vectors Limited-length vector types are supported. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. Types. 0.Chapter 5.v4 .pred p. State Spaces. January 24.v2. textures.global .4. and an optional fixed address for the variable.4. // typedef . . .reg .const .0.v4 . q. .v3 }. PTX supports types for simple aggregate objects such as vectors and arrays.v2 .f32 accel. // a length-2 vector of unsigned ints . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .f32 v0. . // a length-4 vector of floats . its type and size. Variable Declarations All storage for data is specified with variable declarations. for example. 0}.struct float4 coord. .v4 vector. 1. Examples: . Every variable must reside in one of the state spaces enumerated in the previous section.

b32 ptr = rgba.0. 38 January 24.3. or is left empty.. Examples: .global . . Array Declarations Array declarations are provided to allow the programmer to reserve space. ...u16 kernel[19][19].PTX ISA Version 2.0.05. // address of rgba into ptr Currently. .05}. 0}. To declare an array. 5. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.1.4. 1} }. 0}.{.0.f16 and .global .1. {0. variable initialization is supported only for constant and global state spaces. 19*19 (361) halfwords are reserved (722 bytes).global . Variable names appearing in initializers represent the address of the variable.u32 or .0}. For the kernel declaration above. The size of the array specifies how many elements should be reserved. 2010 .4.pred.4. label names appearing in initializers represent the address of the next instruction following the label.0}}. {0. Initializers are allowed for all types except ..s32 offset[][] = { {-1.05}}.s32 n = 10..u64.1.local .f32 blur_kernel[][] = {{.05. {0.global . where the variable name is followed by an equals sign and the initial value or values for the variable. .v4 .shared .0 5.{. this can be used to statically initialize a pointer to a variable. A scalar takes a single value.u8 mailbox[128]. Here are some examples: . being determined by an array initializer.4. Similarly.1.0}.0. The size of the dimension is either a constant expression. this can be used to initialize a jump table to be used with indirect branches or calls.1. {1. .global .. Variables that hold addresses of variables or instructions should be of type . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). Initializers Declared variables may specify an initial value using a syntax similar to C/C++.u8 rgba[3] = {{1. -1}. {0.1}.

Parameterized Variable Names Since PTX supports virtual registers. Types. For example. and Variables 5.reg .6.. Rather than require explicit declaration of every name..2. Elements are bytes.0.align byte-count specifier immediately following the state-space specifier.0.0. 2010 39 .4. . For arrays. and may be preceded by an alignment specifier. named %r0. The default alignment for scalar and array variables is to a multiple of the base-type size. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. These 100 register variables can be declared as follows: . suppose a program uses a large number.0. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.const . January 24. of . %r1. Array variables cannot be declared this way.b8 bar[8] = {0.Chapter 5. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. // declare %r0. alignment specifies the address alignment for the starting address of the entire array. State Spaces.b32 %r<100>. Examples: // allocate array at 4-byte aligned address. %r99.align 4 . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.b32 variables. nor are initializers permitted. The variable will be aligned to an address which is an integer multiple of byte-count. it is quite common for a compiler frontend to generate a large number of register names.4. %r1. Alignment is specified using an optional . The default alignment for vector variables is to a multiple of the overall vector size. …..0.0}. not for individual elements. . say one hundred.5. 5.

0 40 January 24.PTX ISA Version 2. 2010 .

Predicate operands are denoted by the names p. so operands for ALU instructions must all be in variables declared in the . The bit-size type is compatible with every type having the same size. The cvt (convert) instruction takes a variety of operand types and sizes. r. 6. PTX describes a load-store machine.Chapter 6. Instruction Operands 6. The ld. as its job is to convert from nearly any data type to any other data type (and size). The result operand is a scalar or vector variable in the register state space. . Integer types of a common size are compatible with each other. Operand Type Information All operands in instructions have a known type from their declarations. b. the sizes of the operands must be consistent. 2010 41 .reg register state space. For most operations. s. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. and cvt instructions copy data from one location to another. and c.2. st.3. The mov instruction copies data between registers. and a few instructions have additional predicate source operands. January 24. Instructions ld and st move data from/to addressable state spaces to/from registers. q. There is no automatic conversion between types. Most instructions have an optional predicate guard that controls conditional execution. Each operand type must be compatible with the type determined by the instruction template and instruction type. Source Operands The source operands are denoted in the instruction descriptions by the names a. mov. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. 6.1.

v4 . r0. p. The address is an offset in the state space in which the variable is declared. .PTX ISA Version 2. tbl. there is no support for C-style pointer arithmetic.f32 ld.u16 r0.global . .const . [V]. and immediate address expressions which evaluate at compile-time to a constant address.f32 V.[x]. 6. Here are a few examples: .reg .shared .f32 W. and vectors.u32 42 January 24.gloal. ld.s32 q. address registers.0 6.v4 .s32 mov.s32 tbl[256].b32 p. arrays. address register plus byte offset. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. All addresses and address computations are byte-based.4.shared. Load and store operations move data between registers and locations in addressable state spaces. Examples include pointer arithmetic and pointer comparisons. . W. Arrays.u16 ld. 2010 .4. . Using Addresses. Address expressions include variable names. .reg .v4. The syntax is similar to that used in many assembly languages. and Vectors Using scalar variables as operands is straightforward. The interesting capabilities begin with addresses.u16 x. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.reg . The mov instruction can be used to move the address of a variable into a pointer.1.reg . q.const. [tbl+12]. .

f32 V. and the identifier becomes an address constant in the space where the array is declared.Chapter 6. // move address of a[1] into s 6.r V.b.c. [addr+offset2].2.4.4. and in move instructions to get the address of the label or function into a register.reg . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.x V. Rd}.w. a register variable. The registers in the load/store operations can be a vector.y V. it must be written as an address calculation prior to use. mov. for use in an indirect branch or call.u32 {a.u32 s.f32 a.v2. Here are examples: ld. If more complicated indexing is desired. say {Ra. mov.global. Array elements can be accessed using an explicitly calculated byte address.b and .c.a 6. st. [addr+offset]. . .f32 ld.g V. or by indexing into the array using square-bracket notation. 2010 43 . where the offset is a constant expression that is either added or subtracted from a register variable.v4. January 24. Arrays as Operands Arrays of all types can be declared. or a simple “register with constant offset” expression. Instruction Operands 6. c. Vectors may also be passed as arguments to called functions.r. The size of the array is a constant in the program. a[1]. V2. ld. Examples are ld. Rb.v4 . as well as the typical color fields . which include mov.f32 {a.b V.global.global. a[0].w = = = = V. . which may improve memory performance.v4.d}.g. Vector elements can be extracted from the vector with the suffixes .z V.global.z and .u32 s. d. or a braceenclosed list of similarly typed scalars.y. V. a[N-1]. Vector loads and stores can be used to implement wide loads and stores. Rc. . A brace-enclosed list is used for pattern matching to pull apart vectors.a.4. Elements in a brace-enclosed vector. b.3. and tex. .reg .b.d}. Vectors as Operands Vector operands are supported by a limited subset of instructions. The expression within square brackets is either a constant integer. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.x. .4. ld.u32 s.

and ~131.s32.0 6. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. the u16 is zero-extended to s32. 2010 . Type Conversion All operands to all arithmetic. For example. except for operations where changing the size and/or type is part of the definition of the instruction. 44 January 24.5.000 for f16). Operands of different sizes or types must be converted prior to the operation. and data movement instruction must be of the same type and size.PTX ISA Version 2. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.5.u16 instruction is given a u16 source operand and s32 as a destination operand. 6. logic. if a cvt.1.

2010 45 . f2u = float-to-unsigned. Instruction Operands Table 11. the result is extended to the destination register width after chopping. For example. s2f = signed-to-float. zext = zero-extend. Notes 1 If the destination register is wider than the destination format. f2s = float-to-signed.u32 targeting a 32-bit register will first chop to 16-bits. u2f = unsigned-to-float.s16. f2f = float-to-float. chop = keep only low bits that fit. then sign-extend to 32-bits. The type of extension (sign or zero) is based on the destination format.Chapter 6. January 24. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. cvt.

rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 . Rounding Modifiers Conversion instructions may specify a rounding modifier. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.0 6.rm .rmi . In PTX. Table 12.PTX ISA Version 2. Modifier .rz .rni .rn .5.rzi . Modifier . The following tables summarize the rounding modifiers.2. choosing even integer if source is equidistant between two integers.rpi Integer Rounding Modifiers Description round to nearest integer.

Instruction Operands 6. Table 11 gives estimates of the costs of using different kinds of memory. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. while global memory is slowest.Chapter 6. 2010 47 . first access is high Notes January 24. The register in a store operation is available much more quickly.6. Operand Costs Operands from different state spaces affect the speed of an operation. Table 14. Much of the delay to memory can be hidden in a number of ways. Another way to hide latency is to issue the load instructions as early as possible. Registers are fastest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.

PTX ISA Version 2. 2010 .0 48 January 24.

NOTE: The current version of PTX does not implement the underlying. Execution of the ret instruction within foo transfers control to the instruction following the call. parameter passing. In this section. 7. stack-based ABI. Abstracting the ABI Rather than expose details of a particular calling convention. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. A function definition specifies both the interface and the body of the function. execution of the call instruction transfers control to foo. implicitly saving the return address. so recursion is not yet supported. } … call foo. and is represented in PTX as follows: . January 24. A function declaration specifies an optional list of return parameters. Function declarations and definitions In PTX. and an optional list of input parameters. At the call. A function must be declared or defined prior to being called. … Here.1. support for variadic functions (“varargs”). 2010 49 . Scalar and vector base-type input and return parameters may be represented simply as register variables. functions are declared and defined using the . arguments may be register variables or constants. we describe the features of PTX needed to achieve this hiding of the ABI. These include syntax for function definitions.func foo { … ret. and memory allocated on the stack (“alloca”). and return values may be placed directly into register variables.Chapter 7. or prototype.func directive. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. The simplest function has no parameters or return values. stack layout. together these specify the function’s interface. and Application Binary Interface (ABI). function calls. the function name.

reg .reg . st. ld. passed by value to a function: struct { double dbl. For example. } { .f1.param space variables are used in two ways. %ptr. a . %rc1. [y+10].reg . 2010 .reg .b8 .c3. … ld.param.c1.u32 %ptr. Second. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . this structure will be flattened into a byte array.param.b8 c2. %rc2. ld. The . . … st. st.b8 [py+ 8].param .u32 %res.0 Example: . st.param. ret.b8 c3. [y+11].reg . ld.b8 .f64 field are aligned.reg .c4. First.param. } … call (%r1).func (.c2. . %rc2.u32 %inc ) { add.param. . … In this example. consider the following C structure.param variable y is used in function definition bar to represent a formal parameter.b32 c1.param. c3. note that .b64 [py+ 0].b8 c1. bumpptr. [y+9]. [y+8].param.align 8 py[12].s32 x. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .b8 [py+11]. py). [y+0]. c2. 50 January 24.4). %inc.u32 %res) inc_ptr ( . }.align 8 y[12]) { . char c[4]. byte array in .reg space.b8 [py+ 9].f64 f1.param.param. inc_ptr. %rd.param . … … // computation using x.b8 [py+10]. c4. %rc1.param. (%r1.func (. a .reg . st.param space memory.param state space is used to pass the structure by value: .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 c4. (%x. In PTX.f64 f1.PTX ISA Version 2. ld. Since memory accesses are required to be aligned to a multiple of the access size.s32 out) bar (.param space call (%out). // scalar args in .

and alignment of parameters.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. For a caller.reg state space can be used to receive and return base-type scalar and vector values. • • • Input and return parameters may be . For . a . or constants.param state space use in device functions.param memory must be aligned to a multiple of 1.param space formal parameters that are base-type scalar or vector variables.param byte array is used to collect together fields of a structure being passed by value. For a caller.param space byte array with matching type. • • • For a callee. For a callee. size. 2010 51 . the argument must also be a .reg space variable with matching type and size. or 16 bytes.reg space formal parameters. 4. 2.param space formal parameters that are byte arrays. In the case of . January 24. all st. 8.param variables.param or . The . • The . In the case of .reg space variable of matching type and size. Parameters in .param arguments. or a constant that can be represented in the type of the formal parameter. the corresponding argument may be either a .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.reg state space in this way provides legacy support.param state space is used to receive parameter values and/or pass return values back to the caller. the corresponding argument may be either a . The following restrictions apply to parameter passing. In the case of . Note that the choice of . and alignment.g. • • Arguments may be . ..param argument must be declared within the local scope of the caller. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. This enables backend optimization and ensures that the .reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. Abstracting the ABI The following is a conceptual way to think about the .Chapter 7.param variables or .reg or .param and ld.param or .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. • The . The . or a constant that can be represented in the type of the formal parameter. size.param instructions used for argument passing must be contained in the basic block with the call instruction. A .reg variables. Supporting the . Typically.

and . In PTX ISA version 2.0 7.param byte array should be used to return objects that do not fit into a register.reg or . formal parameters were restricted to .param space parameters support arrays. 52 January 24.0. PTX 2.x. PTX 2. 2010 .1. PTX 1.reg state space.param state space.1. and there was no support for array parameters.x In PTX ISA version 1.x supports multiple return values for this purpose. formal parameters may be in either . Objects such as C structures were flattened and passed or returned using multiple registers.PTX ISA Version 2. Changes from PTX 1.0 restricts functions to a single return value.0 continues to support multiple return registers for sm_1x targets. and a . For sm_2x targets.

u32 ap. 0.reg .s32 result.u32 a. . To support functions with a variable number of arguments.u32 ptr.reg .pred p. 2. following zero or more fixed parameters: . variadic functions are declared with an ellipsis at the end of the input parameter list. The function prototypes are defined as follows: .func %va_end (. setp. call (val). .b64 val) %va_arg64 (. 4. ctr. %r3).reg .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. (ap. %r1. This handle is then passed to the %va_arg and %va_arg64 built-in functions.2.u32 align) .h and varargs. val. ret.h headers in C. iteratively access. … %va_start returns Loop: @p Done: January 24. 4). .reg . ) { . max.func ( . %s2).b32 result.u32 b. or 16 bytes.Chapter 7.u32 align) . %va_end is called to free the variable argument list handle. Once all arguments have been processed.ge p. the size may be 1. and end access to a list of variable arguments. call (ap).s32 result ) maxN ( . maxN. PTX provides a high-level mechanism similar to the one provided by the stdarg.reg . %r2. In both cases.reg .u32 ptr. 4.func (.func (.u32 ptr) %va_start .u32 N. (2. // default to MININT mov.s32 val.reg .reg .reg . bra Done. N. %s1.func baz ( . . . the alignment may be 1. call %va_end. In PTX..u32 sz.reg . 2. . 0x8000000. or 4 bytes.u32.reg . Abstracting the ABI 7. mov.u32 sz. ctr.reg .reg .reg .b32 val) %va_arg (. … ) . 2. 4. (ap). or 8 bytes. for %va_arg64. along with the size and alignment of the next data value to be accessed. . } … call (%max). %va_start. %va_arg. .reg . For %va_arg. … call (%max). maxN..func okay ( … ) Built-in functions are provided to initialize. 8.func (. result.reg . (3.b32 ctr. 2010 53 . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . the size may be 1. bra Loop.

3.PTX ISA Version 2.local and st.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. To allocate memory. 54 January 24.reg . defined as follows: . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. Alloca NOTE: The current version of PTX does not support alloca.u32 ptr ) %alloca ( . The array is then accessed with ld.func ( . If a particular alignment is required.0 7. a function simply calls the built-in function %alloca.local instructions.reg . 2010 .

opcode A. C. opcode D. The setp instruction writes two destination registers. In addition to the name and the format of the instruction. January 24. B.lt p|q. // p = (a < b). Format and Semantics of Instruction Descriptions This section describes each PTX instruction. Instruction Set 8. the D operand is the destination operand. B. b.2. For some instructions the destination operand is optional. A. setp. opcode D. We use a ‘|’ symbol to separate multiple destination registers. while A.Chapter 8. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. 2010 55 . the semantics are described. For instructions that create a result value. A.s32. A. and C are the source operands. 8. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. PTX Instructions PTX instructions generally have from zero to four operands. a. opcode D. q = !(a < b).1. B. followed by some examples that attempt to show several possible instantiations of the instruction.

i. // p = (i < n) // if i < n. predicate registers can be declared as . j.s32 j. q. optionally negated.pred p. So. bra L1. predicate registers are virtual and have . 2010 .pred as the type specifier. i. n.lt. 1.lt. Predicated Execution In PTX. add. Predicates are most commonly set as the result of a comparison performed by the setp instruction. As an example. To implement the above example as a true conditional branch. This can be written in PTX as @p setp. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.s32 j. where p is a predicate variable. branch over 56 January 24. n.reg .0 8.PTX ISA Version 2. Instructions without a guard predicate are executed unconditionally. add.s32 p. j. … // compare i to n // if false. use a predicate to control the execution of the branch or call instructions. the following PTX instruction sequence might be used: @!p L1: setp. consider the high-level code if (i < n) j = j + 1. add 1 to j To get a conditional branch or conditional function call. 1.s32 p.3.

3. ordering comparisons are not defined for bit-size types. ne. Unsigned Integer. The bit-size comparisons are eq and ne. le (less-than-or-equal). Table 16. Comparisons 8. and hs (higher-or-same). Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). The unsigned comparisons are eq. The following table shows the operators for signed integer. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. the result is false.1. ne. unsigned integer. Table 15. le.Chapter 8. ge.3. lt.1. gt. lt (less-than). Instruction Set 8.2. and bitsize types. ls (lower-or-same). and ge (greater-than-or-equal). 2010 57 .3. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. gt (greater-than). hi (higher).1.1. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. lo (lower). ne (not-equal). If either operand is NaN.

xor. two operators num (numeric) and nan (isNaN) are provided.PTX ISA Version 2.3. neu. setp can be used to generate a predicate from an integer. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. There is no direct conversion between predicates and integer values.1. for example: selp. ltu. and no direct way to load or store predicate register values. or.%p. 2010 . gtu.0 To aid comparison operations in the presence of NaN values. and nan returns true if either operand is NaN. geu. and mov. Table 17. unordered versions are included: equ. If either operand is NaN. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. then the result of these comparisons is true. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. then these comparisons have the same result as their ordered counterparts. If both operands are numeric values (not NaN).u32 %r1. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.0. not. leu. Table 18. However. num returns true if both operands are numeric values (not NaN). // convert predicate to 32-bit value 58 January 24.2.

cvt. b. For example: . the add instruction requires type and size information to properly perform the addition operation (signed.fX ok inv inv ok Instruction Type .e.f32 d. Floating-point types agree only if they have the same size.fX ok ok ok ok January 24.reg . Signed and unsigned integer types agree provided they have the same size. .sX .f32.uX . i.u16 d. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. most notably the data conversion instruction cvt.bX ..u16 d.uX ok ok ok inv . and integer operands are silently cast to the instruction type if needed. a. Table 19. • The following table summarizes these type checking rules. It requires separate type-size modifiers for the result and source. a.bX . Example: . b.reg . Instruction Set 8.4.sX ok ok ok inv . they must match exactly. a. Type Checking Rules Operand Type . For example.Chapter 8. and this information must be specified as a suffix to the opcode. different sizes). add. 2010 59 .reg . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. unsigned. float. and these are placed in the same order as the operands. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.u16 a. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.u16 d. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. For example.

4.4. For example. st. so that narrow values may be loaded. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. and converted using regular-width registers. or converted to other types and sizes. the cvt instruction does not support .PTX ISA Version 2. the size must match exactly. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Bit-size source registers may be used with any appropriately-sized instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.bX instruction types. the data will be truncated. When used with a narrower bit-size type. unless the operand is of bit-size type. 1. parse error.1. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types.0 8. 2010 . inv = invalid. Table 20. When used with a floating-point instruction type. Note that some combinations may still be invalid for a particular instruction. Floating-point source registers can only be used with bit-size or floating-point instruction types. “-“ = allowed. The data is truncated to the instruction-type size and interpreted according to the instruction type. Source register size must be of equal or greater size than the instruction-type size. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Operand Size Exceeding Instruction-Type Size For convenience. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. Notes 3. for example. floating-point instruction types still require that the operand type-size matches exactly. so those rows are invalid for cvt. 2. stored. no conversion needed. The following table summarizes the relaxed type-checking rules for source operands. When a source operand has a size that exceeds the instruction-type size. ld. 60 January 24. stored. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize.

parse error. 1. When used with a narrower bit-size instruction type. and is zero-extended to the destination register width otherwise. The data is signextended to the destination register width for signed integer instruction types. “-“ = Allowed but no conversion needed. When used with a floatingpoint instruction type. The following table summarizes the relaxed type-checking rules for destination operands. the data will be zero-extended. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend.or sign-extended to the size of the destination register. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. the data is zeroextended. Instruction Set When a destination operand has a size that exceeds the instruction-type size. the size must match exactly. Bit-size destination registers may be used with any appropriately-sized instruction type. January 24. zext = zero-extend. 4. Notes 3. the destination data is zero. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type.Chapter 8. The data is sign-extended to the destination register width for signed integer instruction types. the data is sign-extended. Destination register size must be of equal or greater size than the instruction-type size. inv = Invalid. 2. 2010 61 . Table 21. otherwise. If the corresponding instruction type is signed integer. Floating-point destination registers can only be used with bit-size or floating-point instruction types.

0 8. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. A compiler or programmer may chose to enforce portable. Both situations occur often in programs.PTX ISA Version 2. The semantics are described using C. the semantics of 16-bit instructions in PTX is machine-specific. for many performance-critical applications.6. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. When executing on a 32-bit data path. 8.6. until C is not expressive enough. so it is important to have divergent threads re-converge as soon as possible. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. These extra precision bits can become visible at the application level. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. until they come to a conditional control construct such as a conditional branch. 8. Therefore. conditional function call. at least in appearance. the optimizing code generator automatically determines points of re-convergence. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. However. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. for example. the threads are called divergent. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. 62 January 24. For divergent control flow.1. 2010 . If all of the threads act in unison and follow a single control flow path. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. or conditional return. this is not desirable. and for many applications the difference in execution is preferable to limiting performance. the threads are called uniform. 16-bit registers in PTX are mapped to 32-bit physical registers. by a right-shift instruction. and 16-bit computations are “promoted” to 32-bit computations.5. Divergence of Threads in Control Constructs Threads in a CTA execute together. At the PTX language level. using the . one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. If threads execute down different control flow paths.uni suffix. a compiler or code author targeting PTX can ignore the issue of divergent threads.

the optional guard predicate is omitted from the syntax. 2010 63 .Chapter 8. The Integer arithmetic instructions are: add sub add.cc. 8.7. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8.7. Instructions All PTX instructions may be predicated. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. In the following descriptions.1.cc. addc sub.

s64 }.u32 x. Supported on all target architectures. .c.PTX ISA Version 2. a. add Syntax Integer Arithmetic Instructions: add Add two values. 2010 . .sat limits result to MININT.s32 .s32 c.a. d = a – b.. add.type sub{.0 Table 22.type = { . b. Applies only to . // . .u64.MAXINT (no overflow) for the size of the operation. .u32.z. @p add.sat. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. a.u16.s32 d.s32 type.sat applies only to .MAXINT (no overflow) for the size of the operation. PTX ISA Notes Target ISA Notes Examples Table 23.s16.type = { . a. Saturation modifier: . add.s32 type. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples 64 January 24. . .1. b.0. .s32. d. sub.s32.s32 c. // .s32 . Description Semantics Notes Performs addition and writes the resulting value into a destination register. Saturation modifier: .sat}.u16..u32.y.s64 }.sat}. sub. b. Applies only to . Introduced in PTX ISA version 1. a.u64. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.type add{.b.s16.sat limits result to MININT. b.sat applies only to . . d. .0.s32 d. d = a + b. Introduced in PTX ISA version 1. .

The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. Supported on all target architectures.b32 x1. . add.b32 addc. clearing.cc}.cc.type d.cc.z1. . d = a + b.type d. Introduced in PTX ISA version 1.cc.type = { . addc.u32. add.z4.cc. No saturation.CF) holding carry-in/carry-out or borrowin/borrow-out. x2.y1. Behavior is the same for unsigned and signed integers. Instruction Set Instructions add.y4. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. d = a + b + CC.y1.b32 addc.type = {.cc. x2.b32 addc. x3. 2010 65 .y2. No other instructions access the condition code. x3.y3. a. @p @p @p @p add.b32 addc.s32 }. Behavior is the same for unsigned and signed integers. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.z3. No saturation.b32 addc.CF No integer rounding modifiers. and there is no support for setting.y4. @p @p @p @p add. or testing the condition code.cc.cc Syntax Integer Arithmetic Instructions: add. These instructions support extended-precision integer addition and subtraction. carry-out written to CC.2.z4.cc specified. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.z1. Introduced in PTX ISA version 1.z2.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.CF. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. b.y3.Chapter 8.cc Add two values with carry-out. Table 24.z3. if . Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.z2. b. x4.y2. x4.u32.cc. .s32 }. addc{.CF No integer rounding modifiers.2.b32 addc. Supported on all target architectures. sub. carry-out written to CC. .cc.cc. a.b32 x1.cc.

u32. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. sub.b32 subc. borrow-out written to CC. . . Supported on all target architectures.b32 subc.cc.cc.cc}.cc Syntax Integer Arithmetic Instructions: sub. with borrow-out.s32 }.type d. a. Introduced in PTX ISA version 1.z3.s32 }. 2010 .z1.CF No integer rounding modifiers.z1.CF No integer rounding modifiers. subc{.type = { .type d.cc. No saturation. No saturation.z2.b32 subc. Introduced in PTX ISA version 1. if . subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.z2. d = a – b.z3.cc.type = {.y1. x2. b.0 Table 26.y2. x4.3.b32 x1. x3. @p @p @p @p sub.z4.cc.cc.y4. . Supported on all target architectures. x2. d = a .u32.cc specified. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.y2.CF).b32 subc.3. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.cc Subract one value from another. x3.y4.cc. Behavior is the same for unsigned and signed integers.cc. withborrow-in and optional borrow-out.z4.cc.y1. b.(b + CC. @p @p @p @p sub.PTX ISA Version 2. .y3. Behavior is the same for unsigned and signed integers. borrow-out written to CC. x4.b32 x1.y3. sub.b32 subc.b32 subc. a.

.u16. mul{. Supported on all target architectures. If .. t = a * b. then d is the same size as a and b.fxs.hi variant // for .u32. and either the upper or lower half of the result is written to the destination register. creates 64 bit result January 24.x. b.s16.lo is specified. mul.type = { .type d. Description Semantics Compute the product of two values. mul. .0>. The . // 16*16 bits yields 32 bits // 16*16 bits. d = t<n-1.. n = bitwidth of type. Instruction Set Table 28. .wide.0.lo.wide // for ..wide}.hi or . d = t<2n-1.s16 fa.wide suffix is supported only for 16.wide.hi. then d is twice as wide as a and b to receive the full result of the multiplication. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..lo.Chapter 8. .fys. mul.s16 fa. d = t. a.n>. .and 32-bit integer types. If .u64.fys. // for . save only the low 16 bits // 32*32 bits.lo variant Notes The type of the operation represents the types of the a and b operands.s32.s32 z. .s64 }. 2010 67 .wide is specified.y.fxs.

c. .lo.wide // for .lo variant Notes The type of the operation represents the types of the a and b operands.sat limits result to MININT. d.s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s16.sat.s32 d.s32 r. bitwidth of type..b.. The . a.wide is specified.type = { .. // for .. @p mad.and 32-bit integer types.wide}.hi mode. .a.s32 type in .wide suffix is supported only for 16. .u16. then d and c are the same size as a and b. and then writes the resulting value into a destination register. mad.lo.c.PTX ISA Version 2. If . Description Semantics Multiplies two values and adds a third. Supported on all target architectures.q..0.u32. t<n-1.n> + c.lo is specified.hi. a.type mad. .0 Table 29. 2010 . mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. t n d d d = = = = = a * b.MAXINT (no overflow) for the size of the operation.s32. c. Saturation modifier: . b. t<2n-1. and either the upper or lower half of the result is written to the destination register. mad{.lo.p. then d and c are twice as wide as a and b to receive the result of the multiplication.u64. .r. If . . 68 January 24.hi.hi or . t + c.hi variant // for .0> + c. Applies only to . b.s64 }.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo.Chapter 8. mul24{. mul24. Supported on all target architectures. // for . 48bits.b.0>. and return either the high or low 32-bits of the 48-bit result. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.0. January 24. . a.lo}.a...s32 }.type d.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.e.u32.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.type = { . mul24.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. 2010 69 . d = t<47. d = t<31.s32 d. t = a * b. .16>. b.. mul24. All operands are of the same type and size. i. Instruction Set Table 30.hi may be less efficient on machines without hardware support for 24-bit multiply.hi variant // for .hi. // low 32-bits of 24x24-bit signed multiply. mul24.

b.hi variant // for .. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. t = a * b. mad24{. Return either the high or low 32-bits of the 48-bit result.b. All operands are of the same type and size. d = t<47. Saturation modifier: . . d. // low 32-bits of 24x24-bit signed multiply.type = { .u32.a.16> + c. // for .lo.hi.c. Description Compute the product of two 24-bit integer values held in 32-bit source registers.e. a.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.PTX ISA Version 2. mad24.0> + c.s32 type in .MAXINT (no overflow).s32 d. .s32 d. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. mad24. 48bits. i.. mad24..type mad24. d = t<31. c. 70 January 24.hi mode. mad24.0 Table 31. c..hi may be less efficient on machines without hardware support for 24-bit multiply.hi. 32-bit value to either the high or low 32-bits of the 48-bit result. 2010 . and add a third. a.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.sat.sat limits result of 32-bit signed addition to MININT.lo}.s32 }.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. Applies only to .0. b. Supported on all target architectures.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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a = a << 1. . clz. while (a != 0) { if (a&0x1) d++. the number of leading zeros is between 0 and 32. For . } Introduced in PTX ISA version 2. a. popc requires sm_20 or later.b32 clz.type == . a. mask = 0x80000000.0. d = 0.b64 type. X.type = { . d = 0. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. if (.0.b32 type. cnt. popc Syntax Integer Arithmetic Instructions: popc Population count. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. a. cnt.PTX ISA Version 2. // cnt is . mask = 0x8000000000000000.u32 Semantics 74 January 24.type d.0 Table 39. . a = a >> 1. } while (d < max && (a&mask == 0) ) { d++. X. inclusively. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b64 d.b64 d.type d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else { max = 64. . For . inclusively. the number of leading zeros is between 0 and 64.b32.b64 }. popc. clz. // cnt is . .b64 }. popc. 2010 .u32 PTX ISA Notes Target ISA Notes Examples Table 40. clz requires sm_20 or later.b32) { max = 32.b32 popc.type = { .b32. a.

s64 }.u32. d = -1.type==. break. a. . For unsigned integers. a. bfind returns the bit position of the most significant “1”. bfind.type bfind.u32.Chapter 8. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.s64 cnt. . Instruction Set Table 41. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==.0.u32 January 24. a. bfind requires sm_20 or later. } } if (.shiftamt. i>=0.shiftamt. for (i=msb. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. d. and operand d has type . . Description Find the bit position of the most significant non-sign bit in a and place the result in d. If . For signed integers. Operand a has the instruction type. Semantics msb = (. i--) { if (a & (1<<i)) { d = i. .type d. // cnt is . bfind returns 0xFFFFFFFF if no non-sign bit is found. X. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.u32 || .s32) ? 31 : 63.u32 d. 2010 75 . bfind.s32.d.type = { . bfind.u64.shiftamt && d != -1) { d = msb .shiftamt is specified.

type==.0 Table 42. i<=msb.type d.0.b64 }. for (i=0.b32.b32) ? 31 : 63.type = { . i++) { d[i] = a[msb-i]. brev. a. brev. 2010 . . msb = (. 76 January 24.b32 d. .PTX ISA Version 2. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. brev requires sm_20 or later. a. Description Semantics Perform bitwise reversal of input. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.

u32 || . Operands a and d have the same type as the instruction type.a.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. 2010 77 . d = 0.u32. The destination d is padded with the sign bit of the extracted field.u32. a.0. b.u32 || . the result is zero.type==. The sign bit of the extracted field is defined as: . bfe. bfe.u64 || len==0) sbit = 0. Description Extract bit field from a and place the zero or sign-extended result in d. len = c.type = { . Source b gives the bit field starting bit position.msb)].u64: .s64 }. else sbit = a[min(pos+len-1. .type==.s32. January 24. bfe requires sm_20 or later.b32 d. pos = b.len. if (. If the start position is beyond the msb of the input.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. c. and operands b and c are type . the destination d is filled with the replicated sign bit of the extracted field.type d. . for (i=0. otherwise If the bit field length is zero. .s32. .s32) ? 31 : 63. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. Semantics msb = (.Chapter 8.start. .u32. i<=msb. and source c gives the bit field length in bits.u64.type==. . Instruction Set Table 43.

Source c gives the starting bit position for the insertion. 78 January 24. the result is b. i++) { f[pos+i] = a[i].start. Semantics msb = (. Description Align and insert a bit field from a into b.b32) ? 31 : 63.type==. the result is b.len. bfi.type f. b.0.a. i<len && pos+i<=msb. for (i=0. and place the result in f. . . d. and operands c and d are type .b32 d. f = b. pos = c.type = { . Operands a.b32. c.b. and f have the same type as the instruction type. If the bit field length is zero.b64 }. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.0 Table 44.u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 . bfi. If the start position is beyond the msb of the input. bfi requires sm_20 or later.PTX ISA Version 2. a. len = d. and source d gives the bit field length in bits. b.

.f4e. a} = {{b7. In the generic form (no mode specified). .Chapter 8.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.mode = { .ecr.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. msb=1 means replicate the sign. The msb defines if the byte value should be copied. .b1 source select c[7:4] d. b1.rc8. {b3. a. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. 2010 79 . The bytes in the two source registers are numbered from 0 to 7: {b. as a 16b permute code. b2.b32{. b0}}.b4e. . For each byte in the target register. default mode index d. b4}. the permute control consists of four 4-bit selection values.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.mode} d. and reassemble them into a 32-bit destination register. prmt.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. b. Thus. msb=0 means copy the literal value. a 4-bit selection value is defined. the four 4-bit values fully specify an arbitrary byte permute. .b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. Description Pick four arbitrary bytes from two 32-bit registers. b6.b3 source select c[15:12] d.ecl. c. Instruction Set Table 45. Note that the sign extension is only performed as part of generic form. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. . prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.rc16 }.b2 source select c[11:8] d. b5.

tmp[31:24] = ReadByte( mode.0. tmp[23:16] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp[15:08] = ReadByte( mode. prmt requires sm_20 or later. ctl[1]. tmp64 ). ctl[2] = (c >> 8) & 0xf. ctl[1] = (c >> 4) & 0xf. ctl[3]. r2. r1. r4. r2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r3. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.0 Semantics tmp64 = (b<<32) | a.PTX ISA Version 2.f4e r1. r4. ctl[0]. } tmp[07:00] = ReadByte( mode. 2010 . ctl[2]. tmp64 ).b32.b32 prmt. prmt. ctl[3] = (c >> 12) & 0xf. tmp64 ). r3. tmp64 ). 80 January 24.

2. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f32 and .7.Chapter 8. Floating-Point Instructions Floating-point instructions operate on . 2010 81 .f64 register operands and constant immediate values. Instruction Set 8.

sub.approx. and mad support saturation of results to the range [0.f64 div.rz .f64 rsqrt.rm . sub.lg2.min.mul}.rcp.rnd.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.neg.rn and instructions may be folded into a multiply-add. so PTX programs should not rely on the specific single-precision NaNs being generated.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 {add.ex2}.target sm_20 mad.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 rsqrt.rnd.f32 are the same.rn .approx.0 The following table summarizes floating-point instructions in PTX.rn and instructions may be folded into a multiply-add.f32 {div.f32 {div.approx. with NaNs being flushed to positive zero. . .32 and fma. default is . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f64 are the same.rcp.sqrt}. Single-precision add.target sm_20 . Double-precision instructions support subnormal inputs and results.f32 {mad.rnd.sub. Table 46. mul.rnd.f64 mad.max}.f32 .ftz .mul}. Note that future implementations may support NaN payloads for single-precision instructions. No rounding modifier.sqrt}. 82 January 24.max}.approx.0.f64 {abs.full. 2010 . NaN payloads are supported for double-precision instructions.cos.PTX ISA Version 2.fma}.f64 and fma.sat Notes If no rounding modifier is specified.rnd.rp . 1.f64 {sin. default is . {mad. Instruction Summary of Floating-Point Instructions .rcp.0].min. {add.f32 {div.neg.f32 {abs.rnd. If no rounding modifier is specified.fma}. The optional .sqrt}.target sm_1x No rounding modifier. but single-precision instructions return an unspecified NaN.

subnormal }. a.0. testp.pred = { . . copysign. .finite.finite testp.Chapter 8. testp Syntax Floating-Point Instructions: testp Test floating-point property.type = { . b.f32. January 24. Introduced in PTX ISA version 2. true if the input is a subnormal number (not NaN. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. copysign. z. X. Table 48.f32 copysign. f0. not infinity) As a special case.f32. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. . C.op. . y.normal testp. positive and negative zero are considered normal numbers. A.infinite testp. 2010 83 . . p.infinite. .notanumber testp.0.notanumber. testp requires sm_20 or later.infinite.f64 }.normal. testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. // result is .op p. not infinity). testp. .f64 }.type d.f32 testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.type = { . . Instruction Set Table 47.f64 x. B.type . and return the result as d. a.number.f64 isnan.number testp. copysign requires sm_20 or later.notanumber. .

rm mantissa LSB rounds towards negative infinity . . .ftz.f32 flushes subnormal inputs and results to sign-preserving zero.rz. Rounding modifiers (default is .f32.0f. add.f64 requires sm_13 or later. add Syntax Floating-Point Instructions: add Add two values. 1. .sat}.ftz}{. . NaN results are flushed to +0. b. requires sm_13 for add. Rounding modifiers have the following target requirements: .rn): .rz available for all targets .0]. . add. 84 January 24.rp }.PTX ISA Version 2. subnormal numbers are supported.0.rp for add. a.f64. In particular. requires sm_20 Examples @p add. add{. Description Semantics Notes Performs addition and writes the resulting value into a destination register. d = a + b.ftz. add.f32 flushes subnormal inputs and results to sign-preserving zero.f32 add{.sat.f3.f64 d.rm.rm. sm_1x: add.f2.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn. 2010 . .f64 supports subnormal numbers.rnd}{.rnd}. d. a.0.f32 clamps the result to [0. add.rz mantissa LSB rounds towards zero . b. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rnd = { . Saturation modifier: . An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. add.rn mantissa LSB rounds to nearest even . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 supported on all target architectures.0 Table 49.rz.f32 f1.

sat. Rounding modifiers (default is . sub{. subnormal numbers are supported. requires sm_20 Examples sub. .rn.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. In particular.ftz}{.b. Rounding modifiers have the following target requirements: . a.f32 flushes subnormal inputs and results to sign-preserving zero.rp }.sat}.rz available for all targets .f32 f1.ftz. . d.f32 clamps the result to [0. b. sub. sm_1x: sub. .f64 requires sm_13 or later. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub.rn): .rp for sub. .rn mantissa LSB rounds to nearest even .f64 d. sub.rz mantissa LSB rounds towards zero . Saturation modifier: sub. January 24. sub Syntax Floating-Point Instructions: sub Subtract one value from another. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.Chapter 8. NaN results are flushed to +0.rnd}.f32. Instruction Set Table 50.rnd = { . . 2010 85 .f32 c.a.rm. 1. requires sm_13 for sub.f32 supported on all target architectures. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. .f64.rnd}{.f3.f2.b. a.rn.rn.f64 supports subnormal numbers. sub.rz.0].0.rm mantissa LSB rounds towards negative infinity .rm. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. d = a . sub.0f. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f32 sub{.0.

f64 d. Rounding modifiers have the following target requirements: .rp }.f32 circumf.rp for mul.rn): . mul.f64 supports subnormal numbers. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Saturation modifier: mul. Rounding modifiers (default is . mul{.f64.rnd}{. . .rm. mul.f32 clamps the result to [0.f32 flushes subnormal inputs and results to sign-preserving zero.rz.rnd = { .f32 mul{.rz available for all targets . requires sm_20 Examples mul.ftz.PTX ISA Version 2. a. . b.radius. mul Syntax Floating-Point Instructions: mul Multiply two values. d = a * b.ftz.rz mantissa LSB rounds towards zero .sat}.f32 supported on all target architectures. For floating-point multiplication.rnd}.rn.pi // a single-precision multiply 86 January 24. mul. 2010 . all operands must be the same size.0. b. mul. subnormal numbers are supported. . sm_1x: mul. .sat.rn.0.f64 requires sm_13 or later. d. . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rm mantissa LSB rounds towards negative infinity . Description Semantics Notes Compute the product of two values.0 Table 51. NaN results are flushed to +0. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 flushes subnormal inputs and results to sign-preserving zero.0].rn mantissa LSB rounds to nearest even .f32. a. requires sm_13 for mul. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.ftz}{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. In particular. 1.0f.rm.

fma.rz.rnd{. .rm. The resulting value is then rounded to double precision using the rounding mode specified by .rz mantissa LSB rounds towards zero .ftz}{.f32 fma.f64 requires sm_13 or later. @p fma. again in infinite precision.f64.ftz.f64 introduced in PTX ISA version 1. again in infinite precision.rn mantissa LSB rounds to nearest even .rn.0. sm_1x: fma. d. NaN results are flushed to +0. fma.rnd.f32 is unimplemented in sm_1x.rm mantissa LSB rounds towards negative infinity .f64 computes the product of a and b to infinite precision and then adds c to this product.4.0.y. fma.rnd = { . a.f32 fma.z. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add. c. Instruction Set Table 52. b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.f64 d.f64 w.f32 clamps the result to [0. a.rn. 2010 87 .0f.sat}. PTX ISA Notes Target ISA Notes Examples January 24. Saturation: fma. . d = a*b + c. d.b. .f64 supports subnormal numbers.rnd. fma.f32 computes the product of a and b to infinite precision and then adds c to this product. fma. 1. The resulting value is then rounded to single precision using the rounding mode specified by . fma. Rounding modifiers (no default): .rp }.c.f32 introduced in PTX ISA version 2. .f64 is the same as mad. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.0]. fma.a.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. b.f32 requires sm_20 or later.x.Chapter 8. fma.sat.rnd. fma. c.

mad.target sm_20 d.f32 is when c = +/-0. subnormal numbers are supported. mad{. mad. // . a. // . mad.rnd.f32 clamps the result to [0. .rnd.f32 is identical to the result computed using separate mul and add instructions. The resulting value is then rounded to double precision using the rounding mode specified by . 88 January 24.f32 mad. The exception for mad.target sm_13 and later . For . a.f32 mad. Description Semantics Notes Multiplies two values and adds a third.f64} is the same as fma. the treatment of subnormal inputs and output follows IEEE 754 standard.PTX ISA Version 2. // .0 Table 53. and then the mantissa is truncated to 23 bits. where the mantissa can be rounded and the exponent will be clamped.f32 computes the product of a and b at double precision.rn.0].rnd = { .f64 computes the product of a and b to infinite precision and then adds c to this product. For .0. . mad.target sm_1x: mad. but the exponent is preserved. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. fma. When JIT-compiled for SM 2.rn mantissa LSB rounds to nearest even .rz mantissa LSB rounds towards zero .f32 computes the product of a and b to infinite precision and then adds c to this product.0f. b. c.e.{f32.0 devices. sm_1x: mad. mad.sat}.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.rm mantissa LSB rounds towards negative infinity .. c.rp }. again in infinite precision. b.{f32. a.f32. and then writes the resulting value into a destination register.rnd{. Saturation modifier: mad. again in infinite precision.ftz}{.f64}.ftz}{.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is implemented as a fused multiply-add (i.sat. The resulting value is then rounded to single precision using the rounding mode specified by . mad. Unlike mad.f64 supports subnormal numbers.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 d. c. The resulting value is then rounded to double precision using the rounding mode specified by .f64. Rounding modifiers (no default): . d = a*b + c. b.ftz. again in infinite precision. 2010 . mad.f32 flushes subnormal inputs and results to sign-preserving zero.rz.f32).target sm_1x d.sat}. Note that this is different from computing the product with mul.rnd.rnd.rn. 1. mad.f64 is the same as fma.target sm_20: mad.rm. .0.ftz. NaN results are flushed to +0. mad.f64 computes the product of a and b to infinite precision and then adds c to this product. In this case.

January 24.. 2010 89 . In PTX ISA versions 1..f64 instructions having no rounding modifier will map to mad.rp for mad. requires sm_13 .rz.f64 requires sm_13 or later. a rounding modifier is required for mad. requires sm_20 Examples @p mad. a rounding modifier is required for mad.rn.f32 supported on all target architectures.f32 for sm_20 targets.b. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. mad.rm.f64. Legacy mad.c.rz.Chapter 8...f32 d.0.rn.f64. In PTX ISA versions 2. Rounding modifiers have the following target requirements: .4 and later. Target ISA Notes mad..a.0 and later.rp for mad.f64.rn..f32.rm.

f32 and div.f64 diam.approx. div.ftz. the maximum ulp error is 2.f32 div. or .f64.rnd is required.full. Examples 90 January 24.rz mantissa LSB rounds towards zero . Fast. PTX ISA Notes div.approx. div. sm_1x: div. For PTX ISA version 1. b.0 Table 54.f32 and div.3.rnd = { .3. 2010 .f32 implements a relatively fast.rn mantissa LSB rounds to nearest even .full. The maximum ulp error is 2 across the full range of inputs.rp }.approx. Subnormal inputs and results are flushed to sign-preserving zero. Explicit modifiers . y. div. z. yd.full.rn.approx.ftz.ftz}.rnd{. . d. b.full.ftz.f64 defaults to div.rn.approx{. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . b. stores result in d. zd.full{. a.full. Fast. x. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . a.ftz. For b in [2-126.approx.f32 defaults to div. div.f32 supported on all target architectures.14159. div.f32 div. . Target ISA Notes div. a. and div.rn. For PTX ISA versions 1.rm mantissa LSB rounds towards negative infinity .0.{rz.rm.f64 supports subnormal numbers.f32 requires sm_20 or later. .rnd. and rounding introduced in PTX ISA version 1.ftz.circum.f64 requires sm_13 or later.f32.f32 div.0 through 1.approx. . Description Semantics Notes Divides a by b. . d. div.rnd.ftz}. 2126].4 and later.f32 implements a fast approximation to divide.f32 flushes subnormal inputs and results to sign-preserving zero.rz. approximate single-precision divides: div.f64 d.f64 requires sm_20 or later. div. xd.f32 flushes subnormal inputs and results to sign-preserving zero. d = a / b. approximate division by zero creates a value of infinity (with same sign as a). div.f32 div. a. . one of .4.rp}. full-range approximation that scales operands to achieve better accuracy.f64 introduced in PTX ISA version 1. d. but is not fully IEEE 754 compliant and does not support rounding modifiers. subnormal numbers are supported.ftz}.rm.f32 div. div Syntax Floating-Point Instructions: div Divide one value by another.PTX ISA Version 2. // // // // fast.rn. b. computed as d = a * (1/b). div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.

d = |a|.f64 supports subnormal numbers.f64 requires sm_13 or later. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. Negate the sign of a and store the result in d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 x.f0. a.0. 2010 91 . d = -a. Table 56.ftz. abs. sm_1x: abs.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. subnormal numbers are supported. neg.f32 supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later. neg{. Instruction Set Table 55. Take the absolute value of a and store the result in d. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs. Subnormal numbers: sm_20: By default.f64 supports subnormal numbers. d.f32 flushes subnormal inputs and results to sign-preserving zero. neg.f64 d.ftz.f32 neg.f32 x. NaN inputs yield an unspecified NaN. abs. a. a.ftz}. d. abs{. subnormal numbers are supported. NaN inputs yield an unspecified NaN. January 24.f32 abs.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.Chapter 8. neg. Subnormal numbers: sm_20: By default. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. neg. neg. abs.f0.ftz. abs. sm_1x: neg. a.f32 supported on all target architectures.0.

PTX ISA Version 2. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b. 92 January 24.f32 flushes subnormal inputs and results to sign-preserving zero. min.f1. a. min.0. Store the minimum of a and b in d.f64 supports subnormal numbers. 2010 . max.f2. max{. d. max.ftz}.f64 f0.f64 d. (a > b) ? a : b.ftz}. d d d d = = = = NaN.f64 supports subnormal numbers. a. a. subnormal numbers are supported. min.f32 supported on all target architectures. max. subnormal numbers are supported. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f32 flushes subnormal inputs and results to sign-preserving zero. Table 58.0. a.f64 d.f64 requires sm_13 or later.f32 max.ftz. max.c. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 requires sm_13 or later. min. b.z. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. sm_1x: min.b.f32 max.f32 flushes subnormal inputs and results to sign-preserving zero. @p min. d d d d = = = = NaN.f32 min. min{. max.x. b.f32 min. sm_1x: max.ftz. b. (a < b) ? a : b. d. b. b. a.f32 flushes subnormal inputs and results to sign-preserving zero.c.0 Table 57.f64 z. Store the maximum of a and b in d.f32 supported on all target architectures.ftz.ftz. a. a.

rnd.f64 ri. General rounding modifiers were added in PTX ISA version 2. a.approx.ftz.0 +0. For PTX ISA versions 1. a. The maximum absolute error is 2-23.0 -Inf -Inf +Inf +Inf +0. rcp. d = 1 / a. subnormal numbers are supported. one of .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 defaults to rcp.approx{.x.0 +subnormal +Inf NaN Result -0.rm.f64 d. rcp. rcp.0. rcp.rn mantissa LSB rounds to nearest even .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rnd is required.0 through 1. Instruction Set Table 59.f32 flushes subnormal inputs and results to sign-preserving zero.3.rnd = { .f64. rcp. For PTX ISA version 1.rm mantissa LSB rounds towards negative infinity .0 over the range 1.4 and later.f32 rcp.Chapter 8.{rz.rp}. store result in d.rz.rn.0. PTX ISA Notes rcp.approx and . Target ISA Notes rcp.approx. and rcp.f32 rcp. 2010 93 .approx or . rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f64 requires sm_20 or later. . rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f32 implements a fast approximation to reciprocal.f32 defaults to rcp.rnd.0.r.ftz}. sm_1x: rcp. xi.f32 supported on all target architectures.f64 requires sm_13 or later.rn. rcp.ftz were introduced in PTX ISA version 1.x.f32 flushes subnormal inputs and results to sign-preserving zero.f64 and explicit modifiers . xi. // fast.f32 requires sm_20 or later. rcp. rcp.rz mantissa LSB rounds towards zero .rn. a.ftz}.f32 rcp.f64 introduced in PTX ISA version 1.ftz.approx. d.ftz.rn.approx.0-2.f64 supports subnormal numbers.f32 and rcp. Description Semantics Notes Compute 1/a. rcp.f32. . Examples January 24.f32 rcp.rn.rn.ftz.rp }. . d.rnd{.rm.4. Input -Inf -subnormal -0.

approx.0 +0.f64 supports subnormal numbers.rm mantissa LSB rounds towards negative infinity .rn.rm. General rounding modifiers were added in PTX ISA version 2.rn.rm.f32 sqrt.rz mantissa LSB rounds towards zero .0 +0. sqrt.rn mantissa LSB rounds to nearest even .f32 sqrt.ftz. // IEEE 754 compliant rounding d.ftz were introduced in PTX ISA version 1. sqrt.approx or . // IEEE 754 compliant rounding .f32 and sqrt.rnd = { .ftz.rn.rz. sm_1x: sqrt. Target ISA Notes sqrt.{rz.f64 r.f64 requires sm_13 or later.f32 implements a fast approximation to square root.0 Table 60.rp}. Input -Inf -normal -subnormal -0. sqrt. r.4. and sqrt. one of . sqrt.approx and .rnd.x.PTX ISA Version 2. a. .0 through 1.x. store in d.rn.f64. r. a.f64 introduced in PTX ISA version 1.0. approximate square root d.x.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd is required. 2010 . sqrt. a.f32 is TBD.f32 defaults to sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. // fast.f64 requires sm_20 or later.approx. sqrt. Description Semantics Notes Compute sqrt(a).ftz.rn.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . The maximum absolute error for sqrt.approx. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. sqrt.ftz.3. sqrt.rn. .rnd.0 +0. Examples 94 January 24.f32 sqrt. .rp }.approx. sqrt.0 -0. sqrt.f32 sqrt.ftz}.approx{.f64 defaults to sqrt. For PTX ISA versions 1.f32.approx.ftz}. d = sqrt(a).f64 d.0. For PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.rnd{.f64 and explicit modifiers .0 +subnormal +Inf NaN Result NaN NaN -0.f32 requires sm_20 or later.f32 supported on all target architectures.4 and later. PTX ISA Notes sqrt.

f32 rsqrt.f64 requires sm_13 or later. Compute 1/sqrt(a).0 +0. For PTX ISA version 1. Target ISA Notes Examples rsqrt. and rsqrt.ftz were introduced in PTX ISA version 1. rsqrt.approx.approx. a.f32 flushes subnormal inputs and results to sign-preserving zero.0.approx.ftz. Instruction Set Table 61. the .approx.approx{. The maximum absolute error for rsqrt.0-4.ftz}. rsqrt.f32 and rsqrt.f64 isr.f32 rsqrt.0 through 1.f64 supports subnormal numbers. Subnormal numbers: sm_20: By default. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. rsqrt. x.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.0. rsqrt. rsqrt. January 24.f64 defaults to rsqrt. d. Input -Inf -normal -subnormal -0.approx. PTX ISA Notes rsqrt. Explicit modifiers .ftz.approx modifier is required.0 NaN The maximum absolute error for rsqrt.f32 defaults to rsqrt.4. rsqrt.4 over the range 1.4 and later.f64 were introduced in PTX ISA version 1. ISR. store the result in d. sm_1x: rsqrt. Note that rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. X.f32.approx.3.approx implements an approximation to the reciprocal square root. 2010 95 .f64 is emulated in software and are relatively slow.f64 is TBD.f32 supported on all target architectures.f64. d = 1/sqrt(a).ftz. a.f32 is 2-22. For PTX ISA versions 1.Chapter 8.approx and .f64 d. rsqrt.

approx modifier is required.4.0 through 1.ftz}.ftz introduced in PTX ISA version 1. subnormal numbers are supported.PTX ISA Version 2. 2010 .approx.f32 sa. a. a.f32.0 Table 62.f32 defaults to sin. sin. sm_1x: Subnormal inputs and results to sign-preserving zero. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. For PTX ISA version 1.0 NaN NaN The maximum absolute error is 2-20. sin.approx. Target ISA Notes Examples Supported on all target architectures. Subnormal numbers: sm_20: By default. Find the sine of the angle a (in radians). Input -Inf -subnormal -0.ftz. sin.approx and . Explicit modifiers . d = sin(a).3.approx.9 in quadrant 00.f32 introduced in PTX ISA version 1.f32 implements a fast approximation to sine. sin. For PTX ISA versions 1.f32 d.0 +0.ftz. sin.0 +subnormal +Inf NaN Result NaN -0. PTX ISA Notes sin.0 -0.0 +0.4 and later.f32 flushes subnormal inputs and results to sign-preserving zero.0.ftz. the . 96 January 24.0 +0.approx{.

ftz.0 +1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. d = cos(a).approx{. sm_1x: Subnormal inputs and results to sign-preserving zero.Chapter 8.0 +1. Explicit modifiers . cos. Input -Inf -subnormal -0.ftz introduced in PTX ISA version 1. 2010 97 . For PTX ISA versions 1.approx modifier is required.0.4 and later.0 +1.ftz}.f32 d. the .approx. For PTX ISA version 1.f32 defaults to cos.f32 flushes subnormal inputs and results to sign-preserving zero. cos. January 24. Find the cosine of the angle a (in radians). a.f32 ca.0 +0.approx.3. Target ISA Notes Examples Supported on all target architectures.f32.0 through 1.0 +subnormal +Inf NaN Result NaN +1.f32 introduced in PTX ISA version 1.4.f32 implements a fast approximation to cosine.0 NaN NaN The maximum absolute error is 2-20. cos.approx and . Subnormal numbers: sm_20: By default.ftz. cos. PTX ISA Notes cos. cos.ftz.9 in quadrant 00.approx. a. Instruction Set Table 63. subnormal numbers are supported.

lg2.0 Table 64.ftz}. a. Explicit modifiers .f32 implements a fast approximation to log2(a). 2010 .approx{. PTX ISA Notes lg2.4.approx. Input -Inf -subnormal -0. sm_1x: Subnormal inputs and results to sign-preserving zero. lg2.approx. The maximum absolute error is 2-22.f32 la.3.f32 introduced in PTX ISA version 1. 98 January 24.6 for mantissa. Target ISA Notes Examples Supported on all target architectures.f32 defaults to lg2.0.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.approx and . For PTX ISA version 1. lg2.PTX ISA Version 2. For PTX ISA versions 1. d = log(a) / log(2).ftz.0 +0. the .ftz.approx.approx modifier is required. lg2.ftz introduced in PTX ISA version 1.4 and later.f32 Determine the log2 of a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.f32. a. lg2.0 through 1. subnormal numbers are supported. Subnormal numbers: sm_20: By default. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

hs equ. The destinations p and q must be .dtype. The untyped. le. setp with .f64 supports subnormal numbers. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. and (optionally) combine this result with a predicate value by applying a Boolean operator.ftz}. ne. .f32 comparisons. ge.f32. then the result of these comparisons is true. p[|q].0 Table 67. p = BoolOp(t. To aid comparison operations in the presence of NaN values. lt. . The signed and unsigned comparison operators are eq. For unsigned values. . le. num. ls. {!}c.BoolOp{.B) is one of: and. le. unordered versions are included: equ.n. lt. Semantics t = (a CmpOp b) ? 1 : 0. If both operands are numeric values (not NaN).lt. lo.u32 p|q. The comparison operator is a suffix on the instruction. .f64 source type requires sm_13 or later.ftz. hi. gtu. higher. Subnormal numbers: sm_20: By default.u16. gt. ge.f32 flushes subnormal inputs to sign-preserving zero. and higher-or-same may be used instead of lt. gtu. or. 2010 . gt. p. q = BoolOp(!t. If either operand is NaN. Applies to all numeric types. loweror-same. c). gt.s32 setp.u32. ge. sm_1x: setp. ne.i. This result is written to the first destination operand. gt. neu. b. and nan returns true if either operand is NaN. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. setp.and. b. Modifier . a.eq. leu.s64.b32.0. ge.dtype.type = { . the result is false.type . bit-size comparisons are eq and ne.type setp.s16. p[|q].b64. geu. . 102 January 24.b. setp. ltu. nan The Boolean operator BoolOp(A. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. the comparison operators lo. .f32 flushes subnormal inputs to sign-preserving zero. neu. geu. then these comparisons have the same result as their ordered counterparts. ltu. and hs for lower.CmpOp.PTX ISA Version 2.r. and can be one of: eq. xor.s32.ftz applies only to . . Integer Notes Floating Point Notes The ordered comparisons are eq. ne. .a.u64.pred variables. If either operand is NaN. le. setp. leu. @q setp. A related value computed using the complement of the compare result is written to the second destination operand.f64 }. num returns true if both operands are numeric values (not NaN). hi.ftz}.dtype. a. subnormal numbers are supported. ls. . lt. . respectively.CmpOp{.b16. c).

.s64. . If c ≥ 0. selp Syntax Comparison and Selection Instructions: selp Select between source operands.s32 x.u32.r. .u32.s32 slct{.u64.f64 }. . selp.b16. . a is stored in d. . the comparison is unordered and operand b is selected.g.u64. If c is True. Table 69. fval.type = { . Operands d.b32.b64. C. . @q selp. z.s32. based on the sign of the third operand. a is stored in d. c. .f32 flushes subnormal values of operand c to sign-preserving zero. and operand a is selected. a. For .f32.s16.f64 requires sm_13 or later. slct.f32 d.s16. .f32 A. a. Subnormal numbers: sm_20: By default. a. b.f32 comparisons.u16.type d. . and b must be of the same type. and operand a is selected.f64 }. Semantics Floating Point Notes January 24. and b are treated as a bitsize type of the same width as the first instruction type.dtype = { . Description Conditional selection.b32.f32 flushes subnormal values of operand c to sign-preserving zero.ftz applies only to . otherwise b is stored in d.f64 requires sm_13 or later. sm_1x: slct. 2010 103 . a. based on the value of the predicate source operand. slct.f32 r0. . Modifier . . y.Chapter 8.t. val.f32. slct. . operand c must match the second instruction type. subnormal numbers are supported. . a.ftz. . Operands d. slct. Operand c is a predicate. b. d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. If operand c is NaN. .s64.ftz}.u32. negative zero equals zero.0. b otherwise.0. B.f32 comparisons. slct.u64.dtype.ftz. b. . c.s32. d = (c >= 0) ? a : b.p. c. .x. .dtype.u16. .b64. selp. Instruction Set Table 68.dtype. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.dtype. f0.xp.b16.s32 selp. d = (c == 1) ? a : b. Introduced in PTX ISA version 1. slct Syntax Comparison and Selection Instructions: slct Select one source operand. The selected input is copied to the output without modification. . .

provided the operands are of the same size.PTX ISA Version 2. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. This permits bit-wise operations on floating point values without having to define a union to access the bits. Instructions and. and not also operate on predicates.7.4. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. or.0 8. performing bit-wise operations on operands of any type. xor. 2010 .

pred. b. 2010 105 .fpvalue.pred. Supported on all target architectures. a. . or Syntax Logic and Shift Instructions: or Bitwise OR.b64 }.0. d = a | b.type = { . . January 24. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. but not necessarily the type. The size of the operands must match. Introduced in PTX ISA version 1.b16.type = { . Table 71. sign.type d. a. Allowed types include predicate registers.b32 and.b32. . Instruction Set Table 70. and. or.type d.r.b32. . b. The size of the operands must match.r. and. . .Chapter 8.0x00010001 or.pred p.q.b32 x. d = a & b. and Syntax Logic and Shift Instructions: and Bitwise AND. or.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.b16. Supported on all target architectures. but not necessarily the type.b32 mask mask. .0.0x80000000. Allowed types include predicate registers. Introduced in PTX ISA version 1.q.

a.mask. .pred p. Supported on all target architectures.b16 d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b32. The size of the operands must match. one’s complement. . 2010 .x.r. . Table 74. . . xor.type d. 106 January 24. but not necessarily the type.b32 xor.b32.b32 d. Supported on all target architectures.0x0001.type = { .0. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.type = { .0. d = ~a. . The size of the operands must match. a. Introduced in PTX ISA version 1.type d.b32 mask. cnot. b.b64 }. Allowed types include predicates.b32.q. .pred. not. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Supported on all target architectures. Table 73. d = a ^ b. but not necessarily the type.PTX ISA Version 2.b64 }. a. cnot. . not. .b16. d. Introduced in PTX ISA version 1. .b16. The size of the operands must match. but not necessarily the type. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). not Syntax Logic and Shift Instructions: not Bitwise negation. .q. xor.0 Table 72. a.b16.type = { . not.pred.0.type d.b64 }. Allowed types include predicate registers. d = (a==0) ? 1 : 0. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.

a. The b operand must be a 32-bit value. . Introduced in PTX ISA version 1.s16. .a. The sizes of the destination and first source operand must match.b16.s32. . . PTX ISA Notes Target ISA Notes Examples January 24.b16 c. Signed shifts fill with the sign bit. unsigned and untyped shifts fill with 0. regardless of the instruction type. . . Instruction Set Table 75. b.u16 shr.s32 shr. 2010 107 .Chapter 8. d = a << b.u32. k. regardless of the instruction type.i. b. zero-fill on right. shr. but not necessarily the type. shr. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.type = { . i. sign or zero fill on left. but not necessarily the type. shl. shl Syntax Logic and Shift Instructions: shl Shift bits left.s64 }.b32. a.i. shr Syntax Logic and Shift Instructions: shr Shift bits right.b32.b16.type d. Supported on all target architectures.2.type = { .b64. d = a >> b. The sizes of the destination and first source operand must match. Introduced in PTX ISA version 1. . . Shift amounts greater than the register width N are clamped to N. The b operand must be a 32-bit value.j. Shift amounts greater than the register width N are clamped to N. PTX ISA Notes Target ISA Notes Examples Table 76.2.u16. . Supported on all target architectures.1. . a.0.b32 q. shl.b64 }. Bit-size types are included for symmetry with SHL.0. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. .type d.u64. .

mov.PTX ISA Version 2. suld. Data Movement and Conversion Instructions These instructions copy data from place to place.5. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. possibly converting it from one format to another.7. ldu. prefetchu isspacep cvta cvt 108 January 24. The cvta instruction converts addresses between generic and global.0 8. ld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. st. and st operate on both scalar and vector types. 2010 . and from state space to state space. or shared state spaces. Instructions ld. local. and sust support optional cache operations.

to allow the thread program to poll a SysMem location written by the CPU.ca. The cache operators require a target architecture of sm_20 or later.Chapter 8.cs) on global addresses. invalidates (discards) the local L1 line following the load.cv to a frame buffer DRAM address is the same as ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.0 introduces optional cache operators on load and store instructions.cv Cache as volatile (consider cached system memory lines stale.cs. when applied to a local address. Global data is coherent at the L2 level. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. January 24. The default load instruction cache operation is ld.lu instruction performs a load cached streaming operation (ld. and cache only in the L2 cache. Use ld. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. the second thread may get stale L1 cache data.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. rather than the data stored by the first thread. it performs the ld. Operator . and a second thread loads that address via a second L1 cache with ld. bypassing the L1 cache.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. The ld. fetch again). Table 77. any existing cache lines that match the requested address in L1 will be evicted. Instruction Set 8.lu load last use operation. . The ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. . but multiple L1 caches are not coherent for global data. If one thread stores to global memory via one L1 cache. For sm_20 and later.lu operation. likely to be accessed once. When ld.cs Cache streaming. Cache Operators PTX 2.ca. not L1). The compiler / programmer may use ld. As a result of this request.cg Cache at global level (cache in L2 and below.7. 2010 109 . A ld. evict-first.1. likely to be accessed again. the cache operators have the following definitions and behavior. The ld. if the line is fully covered. The ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. .lu Last use. .cs is applied to a Local window address.ca loads cached in L1.cg to cache loads only globally.5.

Use st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. . and discard any L1 lines that match. Future GPUs may have globally-coherent L1 caches.wb for global data.wt. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.PTX ISA Version 2. bypassing its L1 cache. and cache only in the L2 cache. to allow a CPU program to poll a SysMem location written by the GPU with st. If one thread stores to global memory. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.wb. the second thread may get a hit on stale L1 cache data. which writes back cache lines of coherent cache levels with normal eviction policy. likely to be accessed once.cg Cache at global level (cache in L2 and below.wb could write-back global store data from L1. . However. Global stores bypass L1. The default store instruction cache operation is st. rather than get the data from L2 or memory stored by the first thread. regardless of the cache operation.0 Table 78. 110 January 24. st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. and marks local L1 lines evict-first. not L1). in which case st.ca loads. The st. .cg is the same as st. 2010 . The st. bypassing the L1 cache. Addresses not in System Memory use normal write-back. but st.wt store write-through operation applied to a global System Memory address writes through the L2 cache.cg to local memory uses the L1 cache.ca. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. In sm_20.cs Cache streaming.wt Cache write-through (to system memory).cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Operator . and a second thread in a different SM later loads from that address via a different L1 cache with ld.cg to cache global store data only globally.

local. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.s32.pred. k. d. . mov places the non-generic address of the variable (i.type mov.0.b64. . For variables declared in .Chapter 8. 2010 111 .e. .type = { . local.const.s16. d.u16 mov. i.. addr. mov.type d.u32 mov. or shared state space may be taken directly using the cvta instruction.b32. local. // get address of variable // get address of label or function . d = sreg. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.b16. and . Take the non-generic address of a variable in global. .0.u32. Description . alternately. within the variable’s declared state space Notes Although only predicate and bit-size types are required. the generic address of a variable declared in global.v. Introduced in PTX ISA version 1. mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.type mov.s64. . label. Note that if the address of a device function parameter is moved to a register.shared state spaces. a. immediate. // address is non-generic. variable in an addressable memory space. . d = &avar.global.u32 mov. mov. special register. Operand a may be a register.e. . the address of the variable in its state space) into the destination register. ptr. or shared state space.u64. u.1.u16.f32 mov. myFunc.f64 requires sm_13 or later. . Instruction Set Table 79.f64 }.local.f32 mov. label.. A[5]. .f32. The generic address of a variable in global. d = &label. Semantics d = a. sreg. A. the parameter will be copied onto the stack and the address will be in the local state space. Write register d with the value of a. avar. d. or function name.type mov.u32 d. .a. ptr. . . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.

x. d..7].b64 mov.b16 // pack four 8-bit elements into .31].b}.a}. a.. {lo.0 Table 80.y. Description Write scalar register d with the packed value of vector register a.b16 { d..{x.y.15] } // unpack 8-bit elements from .u32 x.y } = { a[0. %x. Semantics d = a. a[16. a[8.y << 32) // pack two 8-bit elements into .%r1. %r1. a[8.31] } // unpack 8-bit elements from .y.y } = { a[0.b32.type d. d. d. {r.b64 { d.x | (a.b. For bit-size types.a have type .w } = { a[0.31]. Supported on all target architectures.y << 16) d = a.b64 { d.g.hi}..47].b64 112 January 24.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // // // // a.7].type = { .w have type .0. mov.b32 // pack two 16-bit elements into .b32 mov.x. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.15].x | (a. a[16.y << 8) | (a..x | (a.hi are .b32 mov.y.u16 %x is a double.. .z << 32) | (a.b32 { d.w } = { a[0.y } = { a[0. 2010 .y << 8) d = a. a[32.PTX ISA Version 2.. d.x | (a.w << 48) d = a. a[32.b32 // pack four 16-bit elements into ..b64 }.z << 16) | (a.. a[24.z.b have type .z..x | (a. a[48. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b. d.23].w}.w << 24) d = a.b32 { d.15].x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b64 // pack two 32-bit elements into .b16. d.u8 // unpack 32-bit elements from . or write vector register d with the unpacked values from scalar register a.15]. . lo.b8 r.. d.y << 16) | (a. d.g. d. mov...{a.x.31] } // unpack 16-bit elements from ..x. .63] } // unpack 16-bit elements from . a[16.b32 %r1.z.z.

ld introduced in PTX ISA version 1. .volatile may be used with . . i.cg.f32. In generic addressing. Generic addressing may be used with ld. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The .const.type ld.param. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e. . [a].cop}. an address maps to global memory unless it falls within the local memory window or the shared memory window. d.b32.vec.1.type = { .Chapter 8.0. 32-bit).b16.volatile{.b16. ld. The value loaded is sign-extended to the destination register width for signed integers. Within these windows. Cache operations are not permitted with ld.volatile.global. . [a]. Description Load register variable d from the location specified by the source address operand a in specified state space.local.ca. Generic addressing and cache operations introduced in PTX ISA 2. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.s64.s8. the access may proceed by silently masking off low-order address bits to achieve proper rounding.cop = { .volatile. . The address size may be either 32-bit or 64-bit. If no state space is given. The address must be naturally aligned to a multiple of the access size. . .s16.volatile introduced in PTX ISA version 1. . Instruction Set Table 81. .f32 or . to enforce sequential consistency between threads accessing shared memory. i. .shared }. and is zeroextended to the destination register width for unsigned and bit-size types. Addresses are zero-extended to the specified width as needed. the resulting behavior is undefined. . . 2010 113 .lu.ss}{.type d. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. If an address is not properly aligned.type ld{.ss}. [a]. A destination register wider than the specified type may be used.b64.v4 }. .f64 }. or [immAddr] an immediate absolute byte address (unsigned. *a.e.. . PTX ISA Notes January 24. . perform the load using generic addressing. or the instruction may fault. [a].reg state space.cs.const space suffix may have an optional bank number to indicate constant banks other than bank zero.shared spaces to inhibit optimization of references to volatile memory.f16 data may be loaded using ld.ss = { . . . This may be used. . . .volatile{.b8.u16. for example.cv }. *(immAddr). d. ld.cop}. ld{. an integer or bit-size type register reg containing a byte address. *(a+immOff). . d.vec = { .0.ss}. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. .u32.s32. . 32-bit). . and then converted to . . an address maps to the corresponding location in local or shared memory.global and . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. .ss}{.u8.u64.vec.type . Semantics d d d d = = = = a.v2. and truncated if the register width exceeds the state space address width for the target architecture.f64 using cvt.

d. Generic addressing requires sm_20 or later.b16 cvt.[p+4].[p+-8].b32 ld.0 Target ISA Notes ld. // access incomplete array x.s32 ld.PTX ISA Version 2.local. // load .local. x.const.f32 ld.[p].[240].f64 requires sm_13 or later. Q.b64 ld.[fs]. 2010 .b32 ld. // negative offset %r. %r.v4. // immediate address %r.b32 ld. ld.[a].global.[buffer+64].const[4].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.shared.%r.f32.f16 d.global. Cache operations require sm_20 or later.

f32. Within these windows.Chapter 8.vec. . . and then converted to .u16. .f32 Q. ldu.global. i. . *(a+immOff). an address maps to the corresponding location in local or shared memory.s32. and truncated if the register width exceeds the state space address width for the target architecture. an address maps to global memory unless it falls within the local memory window or the shared memory window. . or [immAddr] an immediate absolute byte address (unsigned. // state space . [a].u64.f32 or .global.[a]. d.[p].e. Semantics d d d d = = = = a.b8. 2010 115 . Introduced in PTX ISA version 2.type d.b16. The address size may be either 32-bit or 64-bit.f16 data may be loaded using ldu.[p+4]. Addresses are zero-extended to the specified width as needed. If an address is not properly aligned. 32-bit). PTX ISA Notes Target ISA Notes Examples January 24.ss}. . ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. *(immAddr). [areg] a register reg containing a byte address. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. . A destination register wider than the specified type may be used. .type = { .b16.b64. or the instruction may fault. // load from address // vec load from address .type ldu{. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32. ldu.f64 using cvt.global }. [a]. The address must be naturally aligned to a multiple of the access size. *a.s64. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . where the address is guaranteed to be the same across all threads in the warp.reg state space. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. ldu. The data at the specified address must be read-only. only generic addresses that map to global memory are legal. ..f64 }. If no state space is given.v4.s16.v2.ss}. .f64 requires sm_13 or later.e.global. A register containing an address may be declared as a bit-size type or integer type.ss = { . i. In generic addressing. ldu.b32 d.0.f32 d.s8. ldu{.vec = { . The value loaded is sign-extended to the destination register width for signed integers.v4 }. the resulting behavior is undefined. The addressable operand a is one of: [avar] the name of an addressable variable var. . perform the load using generic addressing. . Instruction Set Table 82.u32. and is zeroextended to the destination register width for unsigned and bit-size types. 32-bit).u8. . For ldu. .

s16. perform the store using generic addressing. st.wb. 32-bit).ss}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type st. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.b64.v4 }. or the instruction may fault.cs. . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. . and truncated if the register width exceeds the state space address width for the target architecture.0.e.. the resulting behavior is undefined. b. .f64 }. The address must be naturally aligned to a multiple of the access size.cop}. . . an integer or bit-size type register reg containing a byte address.shared }.cg.b32.cop . Cache operations are not permitted with st.f16 data resulting from a cvt instruction may be stored using st.ss . st introduced in PTX ISA version 1. i. *(d+immOffset) = a.u8. b.global and . { . In generic addressing. for example. The lower n bits corresponding to the instruction-type width are stored to memory. .u64. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b16. PTX ISA Notes Target ISA Notes 116 January 24. { .v2.vec. .type = = = = {. .s32. Within these windows.e.volatile.s64. . Generic addressing requires sm_20 or later. . b. If no state space is given.cop}.b16.0. an address maps to global memory unless it falls within the local memory window or the shared memory window. .volatile may be used with .0 Table 83. If an address is not properly aligned. Generic addressing may be used with st.type st{.PTX ISA Version 2. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. [a].type .reg state space.vec . .f32.s8. 2010 . [a]. i.volatile{. . . The address size may be either 32-bit or 64-bit.type [a].volatile{. . . [a]. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. Generic addressing and cache operations introduced in PTX ISA 2. st.u16.1.vec. to enforce sequential consistency between threads accessing shared memory. Cache operations require sm_20 or later.u32. .shared spaces to inhibit optimization of references to volatile memory. *(immAddr) = a.wt }. Addresses are zero-extended to the specified width as needed. *d = a. .global. st{. 32-bit). . .ss}. an address maps to the corresponding location in local or shared memory. { . or [immAddr] an immediate absolute byte address (unsigned. st. This may be used.ss}{.volatile introduced in PTX ISA version 1.volatile. Semantics d = a.b8.local.ss}{. A source register wider than the specified type may be used.f64 requires sm_13 or later. b. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.

[q+4]. [p]. // immediate address %r.f16. 2010 117 .global. // negative offset [100].a.global.v4.%r.b.b32 st.Q.Chapter 8. [q+-8].a.local.s32 cvt.local.local. [fs]. // %r is 32-bit register // store lower 16 bits January 24.f32 st.s32 st.r7.f32 st.b16 [a]. Instruction Set Examples st.b32 st.%r.

level = { .local }. The address size may be either 32-bit or 64-bit. prefetch{.0.L1 [addr]. an address maps to global memory unless it falls within the local memory window or the shared memory window. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. A prefetch to a shared memory location performs no operation.level prefetchu. or [immAddr] an immediate absolute byte address (unsigned. i. In generic addressing. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. prefetch. . in specified state space. 118 January 24.space}. 32-bit). prefetchu.L1 [ptr]. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.global. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. and truncated if the register width exceeds the state space address width for the target architecture. the prefetch uses generic addressing.space = { . a register reg containing a byte address. an address maps to the corresponding location in local or shared memory. Within these windows. 2010 .global. prefetch and prefetchu require sm_20 or later. If no state space is given.0 Table 84. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. and no operation occurs if the address maps to a local or shared memory location.L1. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .e. 32-bit). Addresses are zero-extended to the specified width as needed.L2 }. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. A prefetch into the uniform cache requires a generic address.L1 [a]. [a]. // prefetch to data cache // prefetch to uniform cache .PTX ISA Version 2.

0. .size . isspacep. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. For variables declared in global. islcl. // result is . . a.shared }. // get generic address of svar cvta. local. Take the generic address of a variable declared in global. sptr. a.size cvta.u32 gptr. Description Convert a global.u32.global.to.global isspacep.pred . or shared address cvta.u32 or .space = { . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.shared isglbl.lptr.u32 to truncate or zero-extend addresses. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. The source address operand must be a register of type .u64 }. PTX ISA Notes Target ISA Notes Examples Table 86. The destination register must be of type . local. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. A program may use isspacep to guard against such incorrect behavior.0. p. cvta requires sm_20 or later. or vice-versa. .genptr.size p.space. cvta. . or shared state space.shared.local. local. or vice-versa.local isspacep. .local. isspacep requires sm_20 or later. .size = { .space. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. cvta. The source and destination addresses must be the same size.u32 p. gptr. the generic address of the variable may be taken using cvta. Instruction Set Table 85. var. or shared state space.pred.space = { .to. isspacep.u32.space. // local.space p. or shared state space to generic. svar. lptr. isshrd.Chapter 8. Introduced in PTX ISA version 2.shared }. local. January 24. // convert to generic address // get generic address of var // convert generic address to global.u64. 2010 119 .u64 or cvt.u64. or shared address. Use cvt.u32 p. local.global. a. or shared address to a generic address. When converting a generic address into a global.local. cvta. p.global.

rni.0 Table 87. . . the .s8.PTX ISA Version 2. sm_1x: For cvt. .sat}.sat For integer destination types.rn.dtype = . a.rp }. .u16. . 2010 . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.frnd = { .MAXINT for the size of the operation.frnd}{.ftz}{.f32 float-tofloat conversions with integer rounding.rpi }.rz. . . Note that saturation applies to both signed and unsigned integer types. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.4 and earlier.ftz. . For float-to-integer conversions.f32. .u32.u8. subnormal inputs are flushed to signpreserving zero. .f32 float-tofloat conversions with integer rounding.rm.dtype.sat limits the result to MININT. . subnormal inputs are flushed to signpreserving zero. Integer rounding is required for float-to-integer conversions. i.rmi round to nearest integer in direction of negative infinity . . .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. . a. The optional .s16. . i.sat is redundant.atype cvt{. cvt{.f32. d = convert(a). the result is clamped to the destination range by default.f16. d.dtype. .e.atype = { .ftz. subnormal numbers are supported.sat}.dtype.rmi. .ftz. For cvt.. choosing even integer if source is equidistant between two integers. and for same-size float-tofloat conversions where the value is rounded to an integer.irnd = { . .f32.f32 float-to-integer conversions and cvt.irnd}{. // integer rounding // fp rounding . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. .rzi round to nearest integer in the direction of zero .rni round to nearest integer.f64 }.ftz modifier may be specified in these cases for clarity. 120 January 24.s64.f32 float-to-integer conversions and cvt. Integer rounding is illegal in all other instances.u64. Note: In PTX ISA versions 1. The compiler will preserve this behavior for legacy PTX code. Integer rounding modifiers: .ftz.dtype.ftz}{.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. .s32.e.atype d. Saturation modifier: . .. Description Semantics Integer Notes Convert between different types and sizes.rzi.

f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. Specifically. // note .rn mantissa LSB rounds to nearest even .i. Floating-point rounding is illegal in all other instances.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). . The operands must be of the same size.f32. and for integer-to-float conversions. cvt. subnormal numbers are supported.version is 1.f64 j. cvt.4 or earlier.f32 instructions. Modifier .rz mantissa LSB rounds towards zero .0.f64 types.f32. Saturation modifier: . . // float-to-int saturates by default cvt.f32 x. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f32 x. Floating-point rounding modifiers: . 1.y. // round to nearest int.s32 f.f16.f32.f32. and cvt. The optional .rni. The compiler will preserve this behavior for legacy PTX code.ftz modifier may be specified in these cases for clarity.sat limits the result to the range [0. NaN results are flushed to positive zero. if the PTX .f16.f32. Applies to .0].f16. 2010 121 . cvt to or from .rm mantissa LSB rounds towards negative infinity . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.Chapter 8.r.4 and earlier.sat For floating-point destination types.f64 requires sm_13 or later. The result is an integral value. result is fp cvt.y. cvt.s32. Subnormal numbers: sm_20: By default. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.ftz behavior for sm_1x targets January 24. Introduced in PTX ISA version 1. stored in floating-point format. and . Note: In PTX ISA versions 1. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.0.f64.f32.

r5. r5. r2. In the unified mode.. Module-scope and per-entry scope definitions of texture. r1. r1.u32 r5.f32 r1. The advantage of unified mode is that it allows 128 samplers.width. Texture and Surface Instructions This section describes PTX instructions for accessing textures. // get tex1’s txq.global . [tex1].f32. and surface descriptors.r3.f32 {r1.texref tex1 ) { txq. 122 January 24. div. allowing them to be defined separately and combined at the site of usage in the program. but the number of samplers is greatly restricted to 16. and surfaces. sampler.target texmode_independent .6. } = clamp_to_border.b32 r6.f32 r1. sampler. [tex1.0 8. In the independent mode. and surface descriptors. mul.PTX ISA Version 2. If no texturing mode is declared. Ability to query fields within texture. Texturing modes For working with textures and samplers.7.r2. and surface descriptors. r3. PTX has two modes of operation. r1.. add. [tex1].entry compute_power ( . r4. r5.f32. with the restriction that they correspond 1-to-1 with the 128 possible textures. Example: calculate an element’s power contribution as element’s power/total number of elements. and surface descriptors: • • • Static initialization of texture.param . = nearest width height tsamp1.height. The advantage of independent mode is that textures and samplers can be mixed and matched. . 2010 . texture and sampler information is accessed through a single . The texturing mode is selected using . r3.f2}].samplerref tsamp1 = { addr_mode_0 filter_mode }. .f32 r3. // get tex1’s tex.texref handle. r6. sampler.f32 r1. add.v4.b32 r5. {f1.2d. sampler. . cvt. the file is assumed to use unified mode.target options ‘texmode_unified’ and ‘texmode_independent’. PTX supports the following operations on texture.u32 r5. samplers. A PTX module may declare only one texturing mode. texture and sampler information each have their own handle. add.r4}.

r3.r4}. c]..f4}]. with the extra elements being ignored. tex txq suld sust sured suq Table 88. The instruction always returns a four-element vector of 32-bit values. c]. Notes For compatibility with prior versions of PTX. //Example of unified mode texturing tex.f32 }.3d }.v4. b. . the resulting behavior is undefined. is a two-element vector for 2d textures.5. Instruction Set These instructions provide access to texture and surface memory.dtype = { . Unified mode texturing introduced in PTX ISA version 1. tex.r3.u32.1d.btype = { . .v4.s32. A texture base address is assumed to be aligned to a 16-byte address.s32. [tex_a. An optional texture sampler b may be specified. d. .f2.1d.f32 {r1.s32.s32. [a.geom.e.f3. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. [a. {f1. Description Texture lookup using a texture coordinate vector. .s32 {r1.0.dtype. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.btype d.r2. Operand c is a scalar or singleton tuple for 1d textures. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. [tex_a.btype tex. Supported on all target architectures.dtype. // explicit sampler .3d. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. If no sampler is specified.Chapter 8. the square brackets are not required and . and is a four-element vector for 3d textures.v4. PTX ISA Notes Target ISA Notes Examples January 24. // Example of independent mode texturing tex. sampler_x. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.f32 }. 2010 123 . . {f1}]. If an address is not properly aligned.r2. where the fourth element is ignored. the access may proceed by silently masking off low-order address bits to achieve proper rounding.2d. or the instruction may fault. .v4 coordinate vectors are allowed for any geometry.v4.geom. the sampler behavior is a property of the named texture.r4}. i.geom = { .

addr_mode_0.normalized_coords .tquery = { . [tex_A].b32 %r1. addr_mode_2 }. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. txq.width.width. [a].normalized_coords }. . .height.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).height . .samplerref variable.addr_mode_0 .texref or . Supported on all target architectures. and in independent mode sampler attributes are accessed via a separate samplerref argument. // unified mode // independent mode 124 January 24.b32 %r1. linear } Integer from enum { wrap.b32 txq.squery. txq. In unified mode.depth .addr_mode_0. . Query: . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.squery = { . addr_mode_1.tquery.filter_mode. d.0 Table 89.addr_mode_1 . .PTX ISA Version 2. clamp_ogl.b32 d. Integer from enum { nearest.filter_mode .filter_mode. [smpl_B]. txq. [tex_A]. // texture attributes // sampler attributes .depth. [a]. 2010 . txq.5. Operand a is a . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.b32 %r1.width . mirror. Description Query an attribute of a texture or sampler. clamp_to_edge. sampler attributes are also accessed via a texref argument.

trap .cg. .cs. and cache operations introduced in PTX ISA version 2. If the destination base type is .geom . SNORM.b64 }. [surf_B. additional clamp modifiers.p. the access may proceed by silently masking off low-order address bits to achieve proper rounding. suld.p requires sm_20 or later.3d.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.b supported on all target architectures. .b.p is currently unimplemented. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. size and type conversion is performed as needed to convert from the surface sample format to the destination type. i.Chapter 8.b.trap clamping modifier.v4 }.b64.y. // formatted .v4. // cache operation none. {x}].s32. suld. [surf_A. suld. .dtype .z. is a two-element vector for 2d surfaces.clamp field specifies how to handle out-of-bounds addresses: . Instruction Set Table 90. If an address is not properly aligned.1d. b].p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.dtype. . or FLOAT data. and the size of the data transfer matches the size of destination operand d.trap. // for suld. If the destination type is . and is a four-element vector for 3d surfaces. and A components of the surface format.clamp suld.f32. . b]. suld.1d.r2}.trap {r1.b .geom{.ca.clamp.s32. Cache operations require sm_20 or later.p . .b. {x. . suld.clamp = = = = = = { { { { { { d. . where the fourth element is ignored.u32 is returned.3d }.cop}.s32 is returned. Operand a is a . .f32.b32. Target ISA Notes Examples January 24.trap introduced in PTX ISA version 1.geom{. . 2010 125 . suld. then . then .f4}.f2.u32.v2.s32. suld.2d. . or .vec. Operand b is a scalar or singleton tuple for 1d surfaces. [a.u32. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. G.u32. Description Load from surface memory using a surface coordinate vector.clamp . The .cop}. // for suld.b8 .cv }. then . suld. if the surface format contains SINT data. [a.v4.b performs an unformatted load of binary data. .e.3d requires sm_20 or later. or the instruction may fault. {f1.dtype. Destination vector elements corresponding to components that do not appear in the surface format are not written. .surfref variable.0.vec .f3. . A surface base address is assumed to be aligned to a 16-byte address. . . suld.b16.dtype . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. . .cop . // unformatted d. if the surface format contains UINT data.. The lowest dimension coordinate represents a sample offset rather than a byte offset.b32.zero }. the resulting behavior is undefined.f32 based on the surface format as follows: If the surface format contains UNORM.w}].v2. the surface sample elements are converted to . suld Syntax Texture and Surface Instructions: suld Load from surface memory.trap suld. sm_1x targets support only the .5. B.b32.f32 is returned.clamp .s32.f32 }. Coordinate elements are of type . .p.p. or .

f32 }. the resulting behavior is undefined. size and type conversions are performed as needed between the surface sample format and the destination type.s32 is assumed.s32. .f32} are currently unimplemented.vec .geom ..b performs an unformatted store of binary data.p.cop . // for sust. [surf_B. . The size of the data transfer matches the size of source operand c. {x. sust.clamp = = = = = = { { { { { { [a.cop}. then .geom{. Surface sample components that do not occur in the source vector will be written with an unpredictable value. .w}].f32 is assumed. sust.trap . sm_1x targets support only the . Coordinate elements are of type .surfref variable. and A surface components. sust. .v2.5. Operand a is a .cop}.trap introduced in PTX ISA version 1.cg. then . .p. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. b].b supported on all target architectures. . sust. {x}].geom{.f2.u32.u32 is assumed. . sust. The lowest dimension coordinate represents a sample offset rather than a byte offset. . These elements are written to the corresponding surface sample components.ctype . if the surface format contains SINT data.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.clamp sust.p. sust Syntax Texture and Surface Instructions: sust Store to surface memory. or .vec.trap sust. and is a four-element vector for 3d surfaces.ctype . . .b64.s32. then .r2}.f32.vec.f3.3d requires sm_20 or later.f4}. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. .1d. If the source type is . SNORM. Cache operations require sm_20 or later. . c. and cache operations introduced in PTX ISA version 2.p performs a formatted store of a vector of 32-bit data values to a surface sample. The source vector elements are interpreted left-to-right as R.v4.clamp .b // for sust.ctype.b8 .v2.s32.PTX ISA Version 2.p requires sm_20 or later.z.p.b.p Description Store to surface memory using a surface coordinate vector.clamp . The source data is then converted from this type to the surface sample format. sust. . b]. {r1.clamp field specifies how to handle out-of-bounds addresses: .f32. The . If the source base type is . B.trap clamping modifier. is a two-element vector for 2d surfaces. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.wb.b. .trap. Source elements that do not occur in the surface sample are ignored. .b32.wt }.3d }. if the surface format contains UINT data.3d. c.clamp. 2010 . A surface base address is assumed to be aligned to a 16-byte address.ctype. or FLOAT data. . If an address is not properly aligned. none.zero }. G. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .b64 }.0. Target ISA Notes Examples 126 January 24.s32. // unformatted // formatted . Operand b is a scalar or singleton tuple for 1d surfaces.2d. . additional clamp modifiers. {f1. sust. sust. [a.u32. or the instruction may fault. .y.b32.{u32. where the fourth element is ignored.e.cs. i.b32. .0 Table 91.b16.trap [surf_A.b.v4 }. sust.1d.

. Coordinate elements are of type . sured.add.min.op.geom. If an address is not properly aligned.u32 is assumed. or . then .b32 }.b32 type.ctype. The . sured.s32.3d }. sured.u32.1d. . . if the surface format contains SINT data.b. 2010 127 . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b32.b]. r1. // for sured.clamp. Operations add applies to .op. r1. the resulting behavior is undefined.b performs an unformatted reduction on .b32. // byte addressing sured.Chapter 8.trap sured.trap .e. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.s32 is assumed.min.b. operations and and or apply to .add. min and max apply to .max. and the data is interpreted as .u32. .ctype. sured requires sm_20 or later.. is a two-element vector for 2d surfaces. . then .b]. . {x}]. . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. Operand a is a .c. A surface base address is assumed to be aligned to a 16-byte address.p.y}]. .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .u64 data. [surf_B.clamp .clamp field specifies how to handle out-of-bounds addresses: . .s32. sured.u32 based on the surface sample format as follows: if the surface format contains UINT data.u32. {x.and.ctype = { .zero }.geom = { .op = { . Operand b is a scalar or singleton tuple for 1d surfaces. Reduction to surface memory using a surface coordinate vector.surfref variable.p . and .p. The instruction type is restricted to . The lowest dimension coordinate represents a sample offset rather than a byte offset.trap.geom.u32 and .s32 types.u32.b32 }.b .or }. // sample addressing .1d.s32 or .clamp [a.trap [surf_A. or the instruction may fault.ctype = { .p performs a reduction on sample-addressed 32-bit data. where the fourth element is ignored.u64. .b32.clamp = { .0. . .u64. // for sured. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and is a four-element vector for 3d surfaces.s32 types. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Instruction Set Table 92. . i. . January 24.2d.c.clamp [a. .2d.s32.

[surf_A]. Description Query an attribute of a surface.width. Supported on all target architectures. suq. Operand a is a . suq. . [a].b32 %r1.surfref variable.depth }.query = { .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.query.b32 d. 128 January 24. Query: .width.PTX ISA Version 2.width .height .0 Table 93.height.5. 2010 . . .

Chapter 8.x.b. @{!}p instruction. mov.7. If {!}p then instruction Introduced in PTX ISA version 1. setp. { add. { instructionList } The curly braces create a group of instructions. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.f32 @q bra L23. Instruction Set 8.0.y. used primarily for defining a function body. Execute an instruction or instruction block for threads that have the guard predicate true. Supported on all target architectures.c. Threads with a false guard predicate do nothing.f32 @!p div. } PTX ISA Notes Target ISA Notes Examples Table 95. Introduced in PTX ISA version 1.0.a. p.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. 2010 129 . {} Syntax Description Control Flow Instructions: { } Instruction grouping. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.s32 d.s32 a.0. Supported on all target architectures.7. ratio.eq.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Since barriers are executed on a per-warp basis.Chapter 8. bar. threads within a CTA that wish to communicate via memory can store to memory. all-threads-true (.or }. if any thread in a warp executes a bar instruction.sync bar.sync 0. All threads in the warp are stalled until the barrier completes.sync and bar. bar. p.arrive does not cause any waiting by the executing threads. bar. operands p and c are predicates. and d have type . 2010 133 . d. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Barriers are executed on a per-warp basis as if all the threads in a warp are active.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. The result of .sync and bar..and. thread count. b}. Execution in this case is unpredictable.and and . bar.cta.red.and).red also guarantee memory ordering among threads identical to membar. January 24.sync) until the barrier count is met. Operands a. and any-thread-true (.sync without a thread count introduced in PTX ISA 1. all threads in the CTA participate in the barrier. {!}c. b.red are population-count (. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.version 2.red instruction. PTX ISA Notes Target ISA Notes Examples bar. Once the barrier count is reached. The barrier instructions signal the arrival of the executing threads at the named barrier.pred . Register operands. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). the final value is written to the destination register in all threads waiting at the barrier. and bar. Each CTA instance has sixteen barriers numbered 0. a{. b}.red delays the executing threads (similar to bar.op. Note that a non-zero thread count is required for bar.red} introduced in PTX .sync or bar.arrive.red.arrive using the same active barrier.popc. thread count. bar.0. bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.red performs a reduction operation across threads. Thus.arrive a{. In addition to signaling its arrival at the barrier. Description Performs barrier synchronization and communication within a CTA.{arrive.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. {!}c. the optional thread count must be a multiple of the warp size.u32 bar. When a barrier completes.{arrive.red} require sm_20 or later.0.red performs a predicate reduction across the threads participating in the barrier. and bar. b}. bar. In conditionally executed code. bar.sync with an immediate barrier number is supported for sm_1x targets. the waiting threads are restarted without delay. Operand b specifies the number of threads participating in the barrier.popc).or).popc is the number of threads with a true predicate. The reduction operations for bar. If no thread count is specified. the bar. Instruction Set Table 100. Thus. a{. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. while . bar. b. and the barrier is reinitialized so that it can be immediately reused. Register operands. it simply marks a thread's arrival at the barrier.op = { . a. it is as if all the threads in the warp have executed the bar instruction. . and then safely read values stored by other threads prior to the barrier. Only bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. execute a bar.sync or bar.red should not be intermixed with bar.15.u32.

gl} supported on all target architectures. membar. membar. . A memory write (e. this is the appropriate level of membar.gl} introduced in PTX . membar. red or atom) has been performed when the value written has become visible to other clients at the specified level.gl will typically have a longer latency than membar. that is. when the previous value can no longer be read.4.gl.PTX ISA Version 2.sys. membar. membar.g.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. PTX ISA Notes Target ISA Notes Examples membar. by st. For communication between threads in different CTAs or even different SMs. Waits until prior memory reads have been performed with respect to other threads in the CTA.version 2. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. global.cta.version 1. or system memory level.0 Table 101. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. and memory reads by this thread can no longer be affected by other thread writes.level.sys Waits until all prior memory requests have been performed with respect to all clients.cta. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. A memory read (e.sys }.0.level = { . 134 January 24. membar.sys will typically have much longer latency than membar. .g. including thoses communicating via PCI-E such as system and peer-to-peer memory.{cta. membar. membar. membar.sys introduced in PTX . membar. 2010 . level describes the scope of other clients for which membar is an ordering event. membar. membar.gl.cta Waits until all prior memory writes are visible to other threads in the same CTA.cta. .{cta.sys requires sm_20 or later.

b64. The address must be naturally aligned to a multiple of the access size. The floating-point operations are add. Instruction Set Table 102. and exch (exchange). .s32. perform the memory accesses using generic addressing. i.b32.u64.g.b32 only . an address maps to the corresponding location in local or shared memory. January 24.f32 Atomically loads the original value at location a into destination register d.. Description // // // // // . accesses to local memory are illegal..type = { . The address size may be either 32-bit or 64-bit.e.b64 . min. and max operations are single-precision. c.type atom{. Within these windows.min. . . the resulting behavior is undefined. [a]. . . overwriting the original value.type d. performs a reduction operation with operand b and the value in location a.e.op. a de-referenced register areg containing a byte address.xor.op. 32-bit operations. . 2010 135 . . and truncated if the register width exceeds the state space address width for the target architecture. Operand a specifies a location in the specified state space. i.op = { . . . Addresses are zero-extended to the specified width as needed. .and. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. min. .or.cas.Chapter 8. and max. cas (compare-and-swap). d. The inc and dec operations return a result in the range [0. max. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.add. . inc.f32.b]. .b32. The floating-point add.max }.f32 }. For atom. and stores the result of the specified operation at location a. . .s32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . The bit-size operations are and. In generic addressing.add. or by using atom. . an address maps to global memory unless it falls within the local memory window or the shared memory window.u32.space}. . If no state space is given. A register containing an address may be declared as a bit-size type or integer type. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.inc. or the instruction may fault. or. dec.shared }.space = { . . The integer operations are add. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. atom. atom{.u32 only . min. b.exch to store to locations accessed by other atomic operations. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. [a].s32. If an address is not properly aligned. xor.dec.exch.u64 . or [immAddr] an immediate absolute byte address.global. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. . .u32. by inserting barriers between normal stores and atomic operations to a common address.u32. e. .space}. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. . b.

0.shared operations require sm_20 or later.s. b. atom.add. 64-bit atom.max. 2010 . : r-1.f32 requires sm_20 or later. atom.{min.0.[a].add. d. c) operation(*a.s32 atom. Introduced in PTX ISA version 1.my_new_val.t) = (r == s) ? t operation(*a.[x+4].global. b). cas(r. atom. atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.PTX ISA Version 2.cas. s) = (r > s) ? s exch(r. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.f32 atom. d.my_val.max} are unimplemented.cas.shared requires sm_12 or later.1.f32. Release Notes Examples @p 136 January 24.global requires sm_11 or later.b32 d. 64-bit atom.exch} requires sm_12 or later.shared.0 Semantics atomic { d = *a. s) = s. : r+1. atom.{add. : r.[p]. s) = (r >= s) ? 0 dec(r. *a = (operation == cas) ? : } where inc(r. Use of generic addressing requires sm_20 or later.global.

s) = (r > s) ? s : r-1. The inc and dec operations return a result in the range [0.e. perform the memory accesses using generic addressing. Addresses are zero-extended to the specified width as needed.e.s32.g. .s32. e. . or [immAddr] an immediate absolute byte address. Within these windows. a de-referenced register areg containing a byte address. max. If an address is not properly aligned. The floating-point operations are add. . and max operations are single-precision. accesses to local memory are illegal.s32.and. and max.f32. or. . The floating-point add. .u32 only . Semantics *a = operation(*a.b]. 2010 137 .dec. .inc.add.b32 only . . In generic addressing.. dec. The address must be naturally aligned to a multiple of the access size.b64. . the resulting behavior is undefined. b.f32 }. min. and stores the result of the specified operation at location a. where inc(r. min.type [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. 32-bit operations.b32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . . red. . The integer operations are add.shared }. The bit-size operations are and. red{. i.u64 . . by inserting barriers between normal stores and reduction operations to a common address.min. .u32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. i. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Instruction Set Table 103. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.space = { .or. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. . . . Description // // // // . A register containing an address may be declared as a bit-size type or integer type. an address maps to the corresponding location in local or shared memory.Chapter 8.exch to store to locations accessed by other reduction operations. and truncated if the register width exceeds the state space address width for the target architecture.add. .f32 Performs a reduction operation with operand b and the value in location a. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.space}. dec(r.max }.op = { .global.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. January 24.u64. overwriting the original value. Notes Operand a must reside in either the global or shared state space. or the instruction may fault. s) = (r >= s) ? 0 : r+1. and xor. b). Operand a specifies a location in the specified state space.u32. or by using atom.type = { . The address size may be either 32-bit or 64-bit.op.xor. min. If no state space is given. . inc.. For red.u32.

red.shared requires sm_12 or later.my_val.max.add. Release Notes Examples @p 138 January 24. red.and. 2010 .PTX ISA Version 2.1. [x+4].global.{min.max} are unimplemented.add.2.global requires sm_11 or later red. 64-bit red. [p]. 64-bit red.f32.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. red. Use of generic addressing requires sm_20 or later.b32 [a].f32 requires sm_20 or later.0. red.global.shared.shared operations require sm_20 or later.f32 red.s32 red.add requires sm_12 or later.

Negating the source predicate also computes . r1. {!}a.all True if source predicate is True for all active threads in warp. // ‘ballot’ form.ballot. 2010 139 . not across an entire CTA.pred vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. Negate the source predicate to compute . vote. .mode. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.uni }.not_all.all.any.ballot.uni True if source predicate has the same value in all active threads in warp.uni. vote requires sm_12 or later. The reduction modes are: . returns bitmask . // get ‘ballot’ across warp January 24. where the bit position corresponds to the thread’s lane id. .all. vote.none.uni.mode = { . Note that vote applies to threads in a single warp.q.b32 requires sm_20 or later. .2. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.any True if source predicate is True for some active thread in warp. {!}a. vote.pred d.ballot. vote. The destination predicate value is the same across all threads in the warp.pred vote. In the ‘ballot’ form. vote.p.ballot.b32 p. Negate the source predicate to compute . p.b32 d.Chapter 8. . Instruction Set Table 104.q. Description Performs a reduction of the source predicate across threads in a warp.

.dtype. perform a scalar arithmetic operation to produce a signed 34-bit result.u32 or . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.b1. 2. vop. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).s32) is specified in the instruction type.bsel}.9. . Video Instructions All video instructions operate on 32-bit register operands. atype.sat} d.bsel}. .s32 }.secop = { . all combinations of dtype. .asel}.btype = { .b2.extended internally to . taking into account the subword destination size in the case of optional data merging.7. 4.b3.b0. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.bsel = { . c.atype.dtype. .s34 intermediate result. extract and sign.h1 }.dsel = .dtype = . and btype are valid. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. The sign of the intermediate result depends on dtype. .or zero-extend byte.h0. a{.0 8.btype{. . the input values are extracted and signor zero. The source and destination operands are all 32-bit registers.PTX ISA Version 2. 140 January 24. 2010 . with optional secondary operation vop.add. The type of each operand (.secop d. a{. half-word. optionally clamp the result to the range of the destination type. b{.dsel.atype. // 32-bit scalar operation. or word values from its source operands. The general format of video instructions is as follows: // 32-bit scalar operation. b{. Using the atype/btype and asel/bsel specifiers. . The primary operation is then performed to produce an .bsel}. .btype{.min. . with optional data merge vop.u32.btype{. .sat} d. c. to produce signed 33-bit input values. 3. a{. b{.atype = .dtype.sat}.asel}.max }.asel}.s33 values.asel = .atype.

.s33 optMerge( Modifier dsel. . default: return tmp. Bool sat.s33 tmp.b3: return ((tmp & 0xff) << 24) default: return tmp. c). Instruction Set .s33 c) { switch ( secop ) { . .b3: if ( sign ) return CLAMP( else return CLAMP( case .s34 tmp.b2.max return MAX(tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. .b1: return ((tmp & 0xff) << 8) case . U8_MAX. tmp.h0. c).b2: return ((tmp & 0xff) << 16) case . The lower 32-bits are then written to the destination operand.b0. .s33 optSecOp(Modifier secop. The sign of the c operand is based on dtype.b0: return ((tmp & 0xff) case . c). S16_MAX. U32_MIN ). . S32_MIN ). c). .h1: return ((tmp & 0xffff) << 16) case . tmp. tmp. . Bool sign. S8_MAX.Chapter 8. S32_MAX. U8_MIN ). Modifier dsel ) { if ( !sat ) return tmp. S16_MIN ).s33 c ) switch ( dsel ) { case . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. tmp. c).b1.s33 tmp.h0: return ((tmp & 0xffff) case . U16_MIN ). U32_MAX. 2010 141 .min: return MIN(tmp. tmp. switch ( dsel ) { case . S8_MIN ). } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). } } . .add: return tmp + c. c). c).s33 optSaturate( . . as shown in the following pseudocode. January 24. U16_MAX. .

bsel}.atype = .sat vsub. r3. isSigned(dtype). dsel ). vsub. tb ). vabsdiff. r3. bsel ). tmp = | ta – tb |.u32. b{. . r1. vmin. asel ).b2. tb = partSelectSignExtend( b. r3. b{.or zero-extend based on source operand type ta = partSelectSignExtend( a. .0. sat. vabsdiff. r1. .b0. vmin.s32.op2 Description = = = = { vadd. a{.max }. r1.0 Table 105.btype{. . vmax require sm_20 or later. a{. c ).sat vmin. . vsub vabsdiff vmin. . a{. vmin.atype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. with optional data merge vop. // optional merge with c operand 142 January 24. Integer byte/half-word/word minimum / maximum.h1. vmax }. vadd.s32. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.asel}. taking into account destination type and merge operations tmp = optSaturate( tmp.s32. with optional secondary operation vop. r2. .dtype. c ). Integer byte/half-word/word absolute value of difference. Video Instructions: vadd.sat.h0.bsel}.b2. . .h0.atype.b0.btype = { .s32. .add.asel}. tb ). { .s32. Perform scalar arithmetic operation with optional saturate.asel}.btype{. // optional secondary operation d = optMerge( dsel.s32. // extract byte/half-word/word and sign. b{.h0. atype.bsel = { . vop.vop . 2010 . btype. r2.s32.PTX ISA Version 2. c.h1 }.dtype. r2.sat} d.b0. .s32. vmax vadd. vabsdiff.sat} d.dtype . // 32-bit scalar operation. tmp.u32.op2 d.dtype.s32 }. vsub.min.sat}. // 32-bit scalar operation.dsel. c. tmp = MAX( ta.bsel}. c. r2.s32.s32.u32. Semantics // saturate.h1. vmax Syntax Integer byte/half-word/word addition / subtraction. and optional secondary arithmetic operation or subword data merge. r3.btype{. d = optSecondaryOp( op2.sat vabsdiff. vadd. tmp. c.b3.asel = . tmp = MIN( ta.atype.b1.dsel . vsub.add r1. tmp = ta – tb.

vshl: Shift a left by unsigned amount in b with optional saturate. . . } // saturate.0.or zero-extend based on source operand type ta = partSelectSignExtend( a.atype. .b3. tmp.u32.u32 vshr. c.asel}. . c ).clamp && tb > 32 ) tb = 32.h1 }.u32. r1.u32.wrap r1. tmp.u32.dtype. d = optSecondaryOp( op2. case vshr: tmp = ta >> tb. sat.u32. r2.max }. Left shift fills with zero. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.dsel . vshl. a{.asel = .h0. r3. Video Instructions: vshl. Semantics // extract byte/half-word/word and sign.bsel}. and optional secondary arithmetic operation or subword data merge.h1. vshr }.mode}.op2 Description = = = = = { vshl. b{. 2010 143 . January 24.asel}. a{.wrap ) tb = tb & 0x1f.dtype .add. r3. . vop.atype = { .u32{. Instruction Set Table 106.atype. { . switch ( vop ) { case vshl: tmp = ta << tb. r2. vshr: Shift a right by unsigned amount in b with optional saturate. if ( mode == . atype. { .dtype. with optional secondary operation vop. vshr Syntax Integer byte/half-word/word left / right shift.asel}.Chapter 8. asel ). // optional secondary operation d = optMerge( dsel. and optional secondary arithmetic operation or subword data merge.mode} d.s32 }.bsel}.dsel. c ). c.s32.bsel = { . b{. tb = partSelectSignExtend( b.op2 d.bsel}. vshl.b0. .mode . with optional data merge vop.wrap }.u32{. bsel ). a{. vshr vshl. dsel ). .u32.atype.vop . b{. . .sat}{. if ( mode == .mode} d.clamp. Signed shift fills with the sign bit.b1.clamp . isSigned(dtype). // 32-bit scalar operation.b2.dtype. taking into account destination type and merge operations tmp = optSaturate( tmp. vshr require sm_20 or later.u32{. // default is .sat}{. .min. unsigned shift fills with zero.sat}{. // 32-bit scalar operation. . .

final unsigned -(U32 * U32) + S32 // intermediate signed. this result is sign-extended if the final result is signed.shr15 }. The “plus one” mode (.dtype. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.b0. “plus one” mode.b1. otherwise. final signed (U32 * U32) .u32.btype = { . final signed (U32 * S32) + S32 // intermediate signed.sat}{. and the operand negates. (a*b) is negated if and only if exactly one of a or b is negated. and zero-extended otherwise.PTX ISA Version 2.atype.po{. . . final signed (S32 * U32) + S32 // intermediate signed. . c. final signed -(S32 * S32) + S32 // intermediate signed.b2.0 Table 107. internally this is represented as negation of the product (a*b).bsel}.bsel = { .btype{.scale = { .sat}{. final signed (U32 * S32) . with optional operand negates.scale} d.S32 // intermediate signed. That is. final signed -(S32 * U32) + S32 // intermediate signed. Input c has the same sign as the intermediate result. . which is used in computing averages. a{.shr7.po mode.asel}.btype. Description Calculate (a*b) + c.S32 // intermediate signed. {-}b{. Although PTX syntax allows separate negation of the a and b operands. . {-}c.scale} d.S32 // intermediate signed. 2010 .h0. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final signed (S32 * S32) + S32 // intermediate signed. . vmad. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed -(U32 * S32) + S32 // intermediate signed.dtype. the intermediate result is signed.bsel}.atype = .asel = . . {-}a{. ..h1 }.dtype = . 144 January 24. // 32-bit scalar operation vmad. final signed (S32 * U32) . final signed (S32 * S32) .atype. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. Source operands may not be negated in . b{. . The final result is unsigned if the intermediate result is unsigned and c is not negated. .s32 }. PTX allows negation of either (a*b) or c.U32 // intermediate unsigned. Depending on the sign of the a and b operands. and scaling.asel}.b3.po) computes (a*b) + c + 1. final signed The intermediate result is optionally scaled via right-shift. The source operands support optional negation with some restrictions.

vmad. Instruction Set Semantics // extract byte/half-word/word and sign. r1.s32.s32. asel ). r1. tb = partSelectSignExtend( b. else result = CLAMP(result.u32. r2.sat vmad.po ) { lsb = 1.negate) || c. case . U32_MIN).negate ^ b. U32_MAX. January 24.negate ) { tmp = ~tmp.u32.negate.0. signedFinal = isSigned(atype) || isSigned(btype) || (a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.or zero-extend based on source operand type ta = partSelectSignExtend( a. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). btype.sat ) { if (signedFinal) result = CLAMP(result. r3. atype.negate ) { c = ~c. lsb = 1. r2. -r3.u32. switch( scale ) { case . bsel ). vmad requires sm_20 or later. if ( . tmp[127:0] = ta * tb.h0. lsb = 1.negate ^ b. } else if ( c. lsb = 0. 2010 145 . tmp = tmp + c128 + lsb.u32. } else if ( a.Chapter 8. r0.h0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. } if ( .shr7: result = (tmp >> 7) & 0xffffffffffffffff. S32_MIN).shr15 r0. S32_MAX.

asel}. c ). with optional data merge vset.u32. .bsel}. a{. atype.b0.cmp d.asel}.atype.u32.dsel.atype .h1. . . r1.btype = { . c ).cmp.op2 Description = = = = .ne r1. c. asel ).btype. a{.0 Table 108. . 2010 . vset.lt vset. . . r2.le.add.b2. { .op2 d.min.s32 }. tmp = compare( ta. // 32-bit scalar operation. . tb = partSelectSignExtend( b. r3.btype. r2. tb. { . . vset requires sm_20 or later.atype. btype.u32. Semantics // extract byte/half-word/word and sign.u32.asel = .cmp . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.eq.bsel}. b{. and therefore the c operand and final result are also unsigned.btype.0.h0.bsel = { . The intermediate result of the comparison is always unsigned.cmp d. . . // optional secondary operation d = optMerge( dsel. .lt. tmp.b1.b3. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. cmp ) ? 1 : 0. with optional secondary operation vset. with optional secondary arithmetic operation or subword data merge. d = optSecondaryOp( op2.ge }. .h1 }. 146 January 24. . Compare input values using specified comparison.atype. a{.gt.asel}.bsel}. b{. vset.dsel . r3. c. // 32-bit scalar operation.s32. bsel ). tmp.or zero-extend based on source operand type ta = partSelectSignExtend( a. . .ne. b{.max }.PTX ISA Version 2.

The relationship between events and counters is programmed via API calls from the host. numbered 0 through 15.10. pmevent a. pmevent 7. with index specified by immediate operand a.0.4. there are sixteen performance monitor events. January 24. Table 111. brkpt. Instruction Set 8.7. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.Chapter 8. brkpt requires sm_11 or later. trap. 2010 147 .0. Table 110. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Examples Currently. Triggers one of a fixed number of performance monitor events. trap. brkpt. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. brkpt Suspends execution Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. trap Abort execution and generate an interrupt to the host CPU. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Supported on all target architectures. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. @p pmevent 1. Supported on all target architectures.

PTX ISA Version 2. 2010 .0 148 January 24.

Special Registers PTX includes a number of predefined.Chapter 9. %pm3 January 24. %lanemask_gt %clock. which are visible as special registers and accessed through mov or cvt instructions. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. …. read-only variables. %lanemask_ge. %lanemask_le. %lanemask_lt. 2010 149 . %clock64 %pm0.

sreg .%ntid. It is guaranteed that: 0 <= %tid.0.%tid.u16 %rh.sreg . cvt. The %tid special register contains a 1D.x.y < %ntid.x.z. . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u32 %r0. The total number of threads in a CTA is (%ntid.x. . %ntid.z). %tid.u32 type in PTX 2. %tid.y. %ntid. // zero-extend tid.0.y.sreg .%h1.v4 .x code accessing 16-bit component of %tid mov.u32 %r1. 2010 . Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.u16 %rh. %ntid.u32 %tid.%tid.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %ntid.%h2.u32.%ntid. Redefined as .z. Supported on all target architectures. %ntid. the fourth element is unused and always returns zero. %tid.sreg . Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.z to %r2 Table 113.y == %ntid. read-only.x.0 Table 112. %tid component values range from 0 through %ntid–1 in each CTA dimension.v4 . mov.0.z.u32 %h1. read-only special register initialized with the number of thread ids in each CTA dimension.0. mad.y.x.x code Target ISA Notes Examples 150 January 24. mov. Redefined as .y * %ntid.x < %ntid. per-thread special register initialized with the thread identifier within the CTA. The fourth element is unused and always returns zero. the %tid value in unused dimensions is 0. // CTA shape vector // CTA dimensions A predefined.%tid. . // move tid.y 0 <= %tid.x. mov. mov.z < %ntid.z == 1 in 2D CTAs.x.x * %ntid. // legacy PTX 1.x 0 <= %tid. CTA dimensions are non-zero. 2D. The number of threads in each dimension are specified by the predefined special register %ntid. or 3D vector to match the CTA shape.u32 %r0.y == %tid.u32 %h2.%r0. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u32 %ntid.u32 type in PTX 2.v4. // thread id vector // thread id components A predefined. Every thread in the CTA has a unique %tid. %tid.%tid.z == 0 in 1D CTAs.z == 0 in 2D CTAs.z == 1 in 1D CTAs.%tid.v4.u16 %r2.x to %rh Target ISA Notes Examples // legacy PTX 1.u32 %tid. Supported on all target architectures.PTX ISA Version 2. . PTX ISA Notes Introduced in PTX ISA version 1. // compute unified thread id for 2D CTA mov.

u32 %r.sreg . Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. January 24. A predefined. PTX ISA Notes Target ISA Notes Examples Table 116. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. %laneid. 2010 151 .u32 %r.0. mov. For this reason. read-only special register that returns the thread’s lane within the warp. Table 115. %nwarpid.Chapter 9. Supported on all target architectures. A predefined.sreg . Supported on all target architectures. mov. Introduced in PTX ISA version 2. read-only special register that returns the maximum number of warp identifiers. %nwarpid requires sm_20 or later. but its value may change during execution. read-only special register that returns the thread’s warp identifier.sreg . The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. %warpid.u32 %r. . Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Introduced in PTX ISA version 1. The lane identifier ranges from zero to WARP_SZ-1. Introduced in PTX ISA version 1. .3. The warp identifier will be the same for all threads within a single warp. Note that %warpid is volatile and returns the location of a thread at the moment when read.u32 %laneid.3. due to rescheduling of threads following preemption. mov.g. A predefined. Special Registers Table 114. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. e. .u32 %warpid.u32 %nwarpid.

Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. %rh.%nctaid.u16 %r0.x code Target ISA Notes Examples Table 118. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.%nctaid.y < %nctaid.x.x. 2D.v4 .y.u32 %ctaid. . or 3D vector.{x.u32 mov.x code Target ISA Notes Examples 152 January 24. depending on the shape and rank of the CTA grid.sreg . with each element having a value of at least 1. Each vector element value is >= 0 and < 65535. Supported on all target architectures.z < %nctaid. It is guaranteed that: 0 <= %ctaid. The fourth element is unused and always returns zero. It is guaranteed that: 1 <= %nctaid. read-only special register initialized with the number of CTAs in each grid dimension. // legacy PTX 1. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. mov.0 Table 117. // Grid shape vector // Grid dimensions A predefined. 2010 . %ctaid.y.y 0 <= %ctaid. // CTA id vector // CTA id components A predefined.u32 type in PTX 2.u32 %nctaid.u32 %ctaid.sreg .u32 mov.0.PTX ISA Version 2.x.v4. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.%ctaid.sreg .x. mov.%nctaid. %rh. Redefined as . Redefined as .y. // legacy PTX 1.x. Supported on all target architectures. The fourth element is unused and always returns zero. read-only special register initialized with the CTA identifier within the CTA grid.u16 %r0.z} < 65.z.v4.u32 %nctaid .x 0 <= %ctaid.%ctaid. %ctaid.0.y. .0.%nctaid.u32 type in PTX 2.x < %nctaid.z. The %nctaid special register contains a 3D grid shape vector.536 PTX ISA Notes Introduced in PTX ISA version 1.sreg .0. .v4 . The %ctaid special register contains a 1D.z PTX ISA Notes Introduced in PTX ISA version 1.

%smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %smid.sreg . A predefined. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. e.u32 %r.u32 %smid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Note that %smid is volatile and returns the location of a thread at the moment when read. The SM identifier numbering is not guaranteed to be contiguous. Notes PTX ISA Notes Target ISA Notes Examples Table 120. mov. mov. Introduced in PTX ISA version 1. A predefined.u32 %gridid. Introduced in PTX ISA version 1. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. where each launch starts a grid-of-CTAs.3. During execution.u32 %r.0. Special Registers Table 119. Introduced in PTX ISA version 2. so %nsmid may be larger than the physical number of SMs in the device.sreg . PTX ISA Notes Target ISA Notes Examples January 24. Supported on all target architectures.sreg . mov. . due to rescheduling of threads following preemption. Supported on all target architectures. but its value may change during execution. This variable provides the temporal grid launch number for this context. 2010 153 .Chapter 9. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.0. read-only special register initialized with the per-grid temporal grid identifier. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.u32 %r. // initialized at grid launch A predefined. %nsmid requires sm_20 or later. read-only special register that returns the maximum number of SM identifiers.g.u32 %nsmid. The SM identifier numbering is not guaranteed to be contiguous. %gridid. . %nsmid. repeated launches of programs may occur. PTX ISA Notes Target ISA Notes Examples Table 121. . The SM identifier ranges from 0 to %nsmid-1.

A predefined. %lanemask_lt requires sm_20 or later. A predefined. .sreg . Introduced in PTX ISA version 2.u32 %r. 2010 . %lanemask_lt. .0. %lanemask_eq. Table 124. 154 January 24. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. mov. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.PTX ISA Version 2. A predefined.0 Table 122. mov.u32 %lanemask_lt. .u32 %lanemask_le.u32 %r. mov. %lanemask_le. Introduced in PTX ISA version 2.0.sreg .u32 %r. %lanemask_eq requires sm_20 or later.0.u32 %lanemask_eq. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.sreg . Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_le requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. Table 123.

%lanemask_ge requires sm_20 or later. %lanemask_ge.u32 %r. %lanemask_gt requires sm_20 or later. A predefined.u32 %lanemask_ge. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.0. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.0. A predefined. Special Registers Table 125.Chapter 9. Table 126. mov. 2010 155 . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_gt.u32 %lanemask_gt. Introduced in PTX ISA version 2. . .u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.sreg . January 24. mov.sreg .

Special registers %pm0. Supported on all target architectures. %pm2. read-only 64-bit unsigned cycle counter. . %pm2. read-only 32-bit unsigned cycle counter. mov. Supported on all target architectures. Table 128.3. Introduced in PTX ISA version 1. 2010 . Introduced in PTX ISA version 1.u32 r1. %pm1. . The lower 32-bits of %clock64 are identical to %clock. .sreg . %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.sreg .u64 r1. Their behavior is currently undefined. and %pm3 are unsigned 32-bit read-only performance monitor counters.u64 %clock64.PTX ISA Version 2.0.%clock64. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.u32 %clock. 156 January 24. …. Table 129. %pm2. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u32 %pm0. mov. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm3.sreg . %pm1. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.%clock. mov. Special Registers: %pm0. %pm3 %pm0. Introduced in PTX ISA version 2.0.0 Table 127. %pm1.u32 r1. %clock64 requires sm_20 or later.%pm0.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures.version major.version . Each ptx file must begin with a .version Syntax Description Semantics PTX version number.0 . PTX File Directives: .4 January 24.1. 2010 157 . .Chapter 10.version 1.version directive.target Table 130.version 2. minor are integers Specifies the PTX language version number.0.version directives are allowed provided they match the original . . . Duplicate .version directive. and the target architecture for which the code was generated. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. Increments to the major number indicate incompatible changes to PTX. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.version . Directives 10.minor // major.

f64 instructions used. Description Specifies the set of features in the target architecture for which the current ptx code was generated.red}.version directive. In general.target directive containing a target architecture and optional platform options. The texturing mode is specified for an entire module and cannot be changed within the module. PTX features are checked against the specified target architecture.red}.global.f64 to . immediately followed by a .f64 storage remains as 64-bits. brkpt instructions. including expanded rounding modifiers.0.texref and .target directive specifies a single target architecture.5.texref descriptor. Texturing mode: (default is . Therefore.red}. but subsequent . Adds {atom. A . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.shared. The following table summarizes the features in PTX that vary according to target architecture.f64 instructions used. with only half being used by instructions converted from . vote instructions. 2010 . Supported on all target architectures.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Texturing mode introduced in PTX ISA version 1. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Requires map_f64_to_f32 if any . .PTX ISA Version 2. Adds double-precision support.texmode_unified) .f64 instructions used. 158 January 24. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Target sm_20 Description Baseline feature set for sm_20 architecture. Requires map_f64_to_f32 if any . sm_10. Disallows use of map_f64_to_f32. map_f64_to_f32 }. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. PTX File Directives: .f32.target Syntax Architecture and Platform target. sm_11. Requires map_f64_to_f32 if any . Each PTX file must begin with a .texmode_independent texture and sampler information is bound together and accessed via a single . sm_12. texmode_unified. texmode_independent. PTX code generated for a given target can be run on later generation devices.samplerref descriptors.target directives can be used to change the set of target features allowed during parsing. and an error is generated if an unsupported feature is used. A program with multiple .0 Table 131. where each generation adds new features and retains all features of previous generations.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Adds {atom. sm_13.target . Introduced in PTX ISA version 1.texmode_unified . Note that . 64-bit {atom. generations of SM architectures follow an “onion layer” model.global. texture and sampler information is referenced with independent .

2010 159 .Chapter 10. texmode_independent January 24.target sm_10 // baseline target architecture .target sm_13 // supports double-precision .target sm_20. Directives Examples .

ld.reg .3. and .5 and later.param instructions. ld. Parameters are passed via .entry filter ( . with optional parameters. Parameters may be referenced by name within the kernel body and loaded into registers using ld. and body for the kernel function.0 through 1.samplerref. e.surfref variables may be passed as parameters.2. the kernel dimensions and properties are established and made available via special registers. opaque .b32 %r3.entry Syntax Description Kernel entry point and body.entry . Supported on all target architectures. In addition to normal parameters. At kernel launch. [y].func Table 132. Semantics Specify the entry point for a kernel program. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. . These parameters can only be referenced by name within texture and surface load. store.PTX ISA Version 2. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. etc. Kernel and Function Directives: .entry kernel-name ( param-list ) kernel-body .param. parameter variables are declared in the kernel parameter list. 2010 .param instructions. ld. %nctaid.param. .b32 x. parameter variables are declared in the kernel body.b32 %r2.param.g. 160 January 24.texref. .0 through 1.b32 %r1.param { . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.param space memory and are listed within an optional parenthesized parameter list. . and query instructions and cannot be accessed via ld.4 and later. .b32 %r<99>. [z]. For PTX ISA versions 1.0 10.4.param . %ntid. PTX ISA Notes For PTX ISA version 1. … } . parameters.entry .param .entry kernel-name kernel-body Defines a kernel entry point name. .entry cta_fft .b32 y. The shape and size of the CTA executing the kernel are available in special registers.b32 z ) Target ISA Notes Examples [x].

func (.func definition with no body provides a function prototype.func (ret-param) fname (param-list) function-body Defines a function.param state space.func fname (param-list) function-body . … use N. The implementation of parameter passing is left to the optimizing translator. (val0. A . Parameters in . . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. implements an ABI with stack.0. Supported on all target architectures. Variadic functions are represented using ellipsis following the last fixed argument. PTX ISA 2. . there is no stack.b32 localVar.b32 rval) foo (. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Variadic functions are currently unimplemented. and supports recursion.result. other code.func .0 with target sm_20 allows parameters in the . } … call (fooval). 2010 161 . val1). .param space are accessed using ld. Directives Table 133. Parameters in register state space may be referenced directly within instructions in the function body.param instructions in the body. if any. dbl.Chapter 10.func Syntax Function definition. Kernel and Function Directives: .reg . Parameters must be base types in either the register or parameter state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 dbl) { .reg .reg .0 with target sm_20 supports at most one return value.b32 N. foo. and recursion is illegal.param and st. mov.func fname function-body .reg .b32 rval. Release Notes For PTX ISA version 1. The parameter lists define locally-scoped variables in the function body. ret. parameters must be in the register state space. PTX 2. which may use a combination of registers and stack locations to pass parameters. Parameter passing is call-by-value.x code. including input and return parameters and optional function body. … Description // return value in fooval January 24.2 for a description of variadic functions.

entry directive and its body.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.minnctapersm directives may be applied per-entry and must appear between an .pragma The .maxntid directive specifies the maximum number of threads in a thread block (CTA). at entry-scope. registers) to increase total thread count and provide a greater opportunity to hide memory latency. The directive passes a list of strings to the backend. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.maxntid . Currently. and . which pass information to the backend optimizing compiler.3. Note that .maxntid.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).maxnreg.maxnreg .maxntid and . The interpretation of . for example. . .PTX ISA Version 2. to throttle the resource requirements (e.minnctapersm .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. the . These can be used. the . or as statements within a kernel or device function body. and the strings have no semantics within the PTX virtual machine model. and the . 162 January 24.g. A general . The .pragma directive is supported for passing information to the PTX backend. 2010 .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. PTX supports the following directives. The directives take precedence over any module-level constraints passed to the optimizing backend.0 10. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxnctapersm (deprecated) . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.pragma directives may appear at module (file) scope.

maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid nx .3.maxntid nx.3.maxntid 256 .maxnreg .16. or 3D CTA. Performance-Tuning Directives: . Supported on all target architectures. 2D. the backend may be able to compile to fewer registers. Introduced in PTX ISA version 1.maxctapersm. or the maximum number of registers may be further constrained by .Chapter 10.entry foo .maxntid . for example. Exceeding any of these limits results in a runtime error or kernel launch failure. ny.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. ny .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. . This maximum is specified by giving the maximum extent of each dimention of the 1D. . . The actual number of registers used may be less.maxntid 16.entry foo .maxntid nx.maxntid Syntax Maximum number of threads in thread block (CTA).maxntid and .maxnreg n Declare the maximum number of registers per thread in a CTA. Directives Table 134. The maximum number of threads is the product of the maximum extent in each dimension. Supported on all target architectures. nz Declare the maximum number of threads in the thread block (CTA). The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Introduced in PTX ISA version 1. .entry bar . Performance-Tuning Directives: . 2010 163 . The compiler guarantees that this limit will not be exceeded.

0 Table 136. Optimizations based on .minnctapersm generally need . .minnctapersm 4 { … } 164 January 24. Performance-Tuning Directives: .0.maxnctapersm generally need .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).entry foo .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Supported on all target architectures.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxntid and .maxntid 256 .minnctapersm in PTX ISA version 2. Introduced in PTX ISA version 2. The optimizing backend compiler uses .maxntid to be specified as well. Performance-Tuning Directives: .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. 2010 .3. Deprecated in PTX ISA version 2.entry foo .maxntid 256 .maxnctapersm has been renamed to . . Optimizations based on . Supported on all target architectures.maxnctapersm (deprecated) .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. . Introduced in PTX ISA version 1.0.maxnctapersm. if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm . For this reason.PTX ISA Version 2. However.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. additional CTAs may be mapped to a single multiprocessor. .0 as a replacement for . .maxntid to be specified as well.

.pragma Syntax Description Pass directives to PTX backend compiler. Supported on all target architectures. . Directives Table 138. Introduced in PTX ISA version 2.entry foo . or statement-level directives to the PTX backend compiler. See Appendix A for descriptions of the pragma strings defined in ptxas. at entry-scope. or at statementlevel.pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma list-of-strings .pragma directive may occur at module-scope. The .Chapter 10. The interpretation of .pragma . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . entry-scoped. 2010 165 . Performance-Tuning Directives: .0. Pass module-scoped.pragma “nounroll”.pragma “nounroll”. { … } January 24.

0x00. replaced by .byte 0x00.4byte 0x6e69616d. “”.section directive is new in PTX ISA verison 2.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Table 139. 2010 . 0x00 166 January 24.loc The .byte byte-list // comma-separated hexadecimal byte values . 0x00. @progbits .4byte .. 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.debug_info . The @@DWARF syntax is deprecated as of PTX version 2.file . 0x02. 0x6150736f.quad int64-list // comma-separated hexadecimal integers in range [0.PTX ISA Version 2.. 0x00000364.4byte 0x000006b5. 0x736d6172 . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .x code.debug_pubnames. 0x00.byte 0x2b.2.section directive.232-1] . 0x61395a5f. 0x5f736f63 . @@DWARF dwarf-string dwarf-string may have one of the . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00. Introduced in PTX ISA version 1.264-1] . Deprecated as of PTX 2.section .4byte label .0. 0x00 . 0x00.section .0 and replaces the @@DWARF syntax.4.0 but is supported for legacy PTX version 1.0 10. 0x63613031. Supported on all target architectures.

0x00.b32 0x000006b5.b32 label ... 0x00. 0x5f736f63 0x6150736f. .232-1] . 0x00.b32 . Supported on all target architectures. Debugging Directives: .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures.b8 byte-list // comma-separated list of integers in range [0. replaces @@DWARF syntax. Source file location.loc line_number January 24.b8 0x2b.debug_info . .b32 0x6e69616d. Debugging Directives: . Source file information..section .section Syntax PTX section definition. .b8 0x00. Supported on all target architectures.264-1] .loc .debug_pubnames { . 0x00. 0x736d6172 0x00 Table 141. .file filename Table 142. } 0x02. Directives Table 140.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . 0x00000364.Chapter 10. 2010 167 .255] . 0x63613031.section .0. .b64 int64-list // comma-separated list of integers in range [0.file .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. Debugging Directives: . 0x00. .0.section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00.b32 int32-list // comma-separated list of integers in range [0. 0x00 0x61395a5f.

global . Linking Directives: .extern .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.0.visible .extern . 2010 . Introduced in PTX ISA version 1.0 10.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible Table 143. Linking Directives . Introduced in PTX ISA version 1.visible . .global .6. Supported on all target architectures.b32 foo. // foo will be externally visible 168 January 24.extern identifier Declares identifier to be defined externally. Linking Directives: . // foo is defined in another module Table 144. . .visible identifier Declares identifier to be externally visible. .extern .PTX ISA Version 2. Supported on all target architectures.b32 foo.0.

2010 169 .5 PTX ISA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2. CUDA Release CUDA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.4 PTX ISA 1.1 PTX ISA 1.Chapter 11.2 CUDA 2.0 January 24.0.0 CUDA 1.0 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1.2 PTX ISA 1. The release history is as follows.0 CUDA 2. and the remaining sections provide a record of changes in previous releases.3 PTX ISA 1.1 CUDA 2.1 CUDA 2.3 driver r190 CUDA 3.

0 11. and mul now support .f32 require a rounding modifier for sm_20 targets. The mad. Single-precision add. The mad. These are indicated by the use of a rounding modifier and require sm_20.f32 instruction also supports . with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rp rounding modifiers for sm_20 targets. Instructions testp and copysign have been added. The fma.1.f32. sub. rcp.0 11.f32 and mad. New Features 11. • • • • • 170 January 24.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.ftz modifier may be used to enforce backward compatibility with sm_1x. The .PTX ISA Version 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Changes in Version 2. while maximizing backward compatibility with legacy PTX 1.f32 requires sm_20.and double-precision div.x code and sm_1x targets.1. 2010 .1.1.1.sat modifiers. mad.ftz and . The goal is to achieve IEEE 754 compliance wherever possible. Floating-Point Extensions This section describes the floating-point changes in PTX 2.rm and .1.0 for sm_20 targets.f32 maps to fma.rn. and sqrt with IEEE 754 compliant rounding have been added.f32 for sm_20 targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added. When code compiled for sm_1x is executed on sm_20 devices. The changes from PTX ISA 1. Both fma. fma. Single.

A system-level membar instruction. e.u32 and bar. Instructions {atom. %lanemask_{eq.clamp and .2.minnctapersm to better match its behavior and usage. 11. for prefetching to specified level of memory hierarchy. . atom.section.pred have been added. st. has been added. Instructions prefetch and prefetchu have also been added. ldu. has been added. st.red. 2010 171 . vote. and sust.3.red}. Release Notes 11. January 24.ge.shared have been extended to handle 64-bit data types for sm_20 targets. and shared addresses to generic address and vice-versa has been added. ldu.g. Video instructions (includes prmt) have been added. The . has been added. popc.f32 have been implemented. %clock64. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.ballot.add. Surface instructions support additional .1. A “bit reversal” instruction.Chapter 11. A “population count” instruction. has been added. A new directive. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.red. bfe and bfi.clamp modifiers. .arrive instruction has been added.le. has been added. Other new features Instructions ld. A “find leading non-sign bit” instruction. has been added. local. Instructions bar. prefetch. clz. Instruction cvta for converting global. Instructions {atom. A “count leading zeros” instruction.maxnctapersm directive was deprecated and replaced with .gt} have been added. A “vote ballot” instruction. isspacep.or}.zero.popc.sys.1.b32. and red now support generic addressing. bar now supports optional thread count and register operands.1. Cache operations have been added to instructions ld. The bar instruction has been extended as follows: • • • A bar. Bit field extract and insert instructions. suld.1. New instructions A “load uniform” instruction. have been added.lt. brev.{and. New special registers %nsmid. cvta.red}. prefetchu. bfind. has been added. membar. Instruction sust now supports formatted surface stores.

single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.f32} atom.p.version is 1.target sm_1x.{u32.red}. if . Instruction bra.5 and later.0 11. cvt. {atom.4 or earlier. See individual instruction descriptions for details. or .3. To maintain compatibility with legacy PTX code. 11. stack-based ABI is unimplemented.p sust. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.4 and earlier. where .ftz (and cvt for . Formatted surface load is unimplemented. Support for variadic functions and alloca are unimplemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. Semantic Changes and Clarifications The errata in cvt.max} are not implemented. the correct number is sixteen.s32.u32. . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.1.f32.f32 type is unimplemented. In PTX version 1. Formatted surface store with . has been fixed.PTX ISA Version 2. 172 January 24.5. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.1. 2010 . call suld. The underlying.s32.{min.2.ftz for PTX ISA versions 1.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.

and statement levels. … @p bra L1_end. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. 2010 173 . including loops preceding the . .pragma “nounroll”. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. .pragma strings defined by ptxas. Ignored for sm_1x targets.pragma “nounroll”. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Table 145.pragma Strings This section describes the . { … } // do not unroll any loop in this function . Note that in order to have the desired effect at statement level.pragma. The “nounroll” pragma is allowed at module. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. disables unrolling of0 the loop for which the current block is the loop header.Appendix A.0. entry-function.func bar (…) { … L1_head: . disables unrolling for all loops in the entry function body. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. L1_end: … } // do not unroll this loop January 24. Supported only for sm_20 targets.entry foo (…) . L1_body: … L1_continue: bra L1_head. Descriptions of .pragma “nounroll”.

0 174 January 24. 2010 .PTX ISA Version 2.

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