NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

................ 5.........4.............................................1.....................6.......................................... Sampler................................................................... 6..8.............................................. State Spaces.....................5.......6....... 32 5.............................. 41 Source Operands.... Function declarations and definitions .................... Types..............................................1.. 37 Variable Declarations ........6..........................1................ 27 5....................................... Operand Type Information .2..... 34 Variables ... Chapter 6.....................4.....3.............. 6............................................................... Summary of Constant Expression Evaluation Rules ................ 49 ii January 24...............................................4.....................................................4.....................................................4................3..1..........................2...................................................... 33 Fundamental Types .............1...... 38 Initializers ....................... 37 Vectors .. 42 Arrays as Operands .......... 5.................. 39 Parameterized Variable Names ......................... Arrays.....................................................5............................................ 28 Constant State Space ........................................................................................4......................... 46 6. 43 Vectors as Operands ..................5............. Texture.. Type Conversion............................. 5....... 28 Special Register State Space ...1.................2.................... 39 5............................ State Spaces ....3......... 27 Register State Space .................................................................... Instruction Operands..... 5...................................................2.......................1..............2.............................. 6................... 5................................................................. 5...........3............................2........................................................... 33 Restricted Use of Sub-Word Sizes .............................................................. 5....................4.......................... 5............ Operand Costs ..................................................... 6.... 25 Chapter 5..............................4..........................2........................5....3....... 44 Rounding Modifiers .......... 5... 5............... 5.......................... 29 Local State Space ............. 49 7..................................................................................... and Surface Types ..............4...................4.............1.... 43 6..........4..................................1........... 6.........4............................................4............................................1........................ 41 Using Addresses............ 47 Chapter 7........ 5....................................................... 6...............1.................1........................................1.......... 42 Addresses as Operands ...........................................................2...... 38 Alignment .........................5..............................................................................1.... 37 Array Declarations ......1...................... 41 Destination Operands ................ and Variables ................... 5... 43 Labels and Function Names as Operands ..............................0 4......................................................PTX ISA Version 2............... 29 Global State Space ...........................2..... Types .................................... 41 6............................ Abstracting the ABI ....................................5................................4........... 6.....6.........................................................................................................................4...................................................................................................................... 6......................... 5.......... 32 Texture State Space (deprecated) .........7............. 29 Parameter State Space ........................................... 5................. and Vectors ....... 2010 ............ 6.................. 44 Scalar Conversions ................................................ 5.......... 33 5........ 30 Shared State Space...................1............

................................. 8... 122 Control Flow Instructions ..............3............................................. Directives ....... Release Notes ....... 63 Floating-Point Instructions ........2......................... 58 8............ 166 Linking Directives .............. Type Information for Instructions and Operands .7................................................9....10.... 62 Machine-Specific Semantics of 16-bit Code .......................................... 8.............. 147 8.................... 62 Semantics .........4.............7............ 168 Chapter 11............2...............4....................................................... Chapter 9............................................................. 2010 iii ..........3........ 8...............................................................1. 81 Comparison and Selection Instructions ...4........... 157 Specifying Kernel Entry Points and Functions ........... 62 8.......1...............................3......... 54 Chapter 8... 11............. PTX Version and Target Directives ...................... 8....................2........................................................................3.....................................................2. 52 Variadic functions ............................................................ 55 Predicated Execution ...... Instruction Set ...............7.....1.............................................. 10......... 8.............................1..2.............................................................................. 172 Unimplemented Features Remaining ... 149 Chapter 10..................7.. 11................... 172 January 24............................ 157 10...................................... Instructions .....6....................... 169 11.............2...................3........................................................................... 53 Alloca ...........................1....... 104 Data Movement and Conversion Instructions ..... 8...............................1........ 11...............................1... 8.... 10..7.......................................................................................... Special Registers .................6.................................................1..............................................................1.....................1............................................................ 56 Comparisons .............. 55 8......................7............... 8...............7........................7.........1....................7..........6................................... 140 Miscellaneous Instructions.. Format and Semantics of Instruction Descriptions ..............................5............ Changes from PTX 1.......................................................................6.....................8.. 132 Video Instructions .................... 10................................. 8....................................... 7............. 55 PTX Instructions ....................................... Divergence of Threads in Control Constructs ................7............................ 108 Texture and Surface Instructions ................................................... 10............3...........................5....................... Changes in Version 2...........................................................................7..................................... 170 Semantic Changes and Clarifications .............. 7........................................... 8................................................4.............................................. 8........................................................... 162 Debugging Directives ...............................................7......................... 160 Performance-Tuning Directives ........................ 57 Manipulating Predicates ...........1.................. 8...........0 ........................x .... 170 New Features ...... 100 Logic and Shift Instructions ........................................ 8.. 60 8................ 8................................... 63 Integer Arithmetic Instructions .................... 129 Parallel Synchronization and Communication Instructions .........................................7........1............... 8.......... 59 Operand Size Exceeding Instruction-Type Size ..................................................................................................................... 8............................3............

................ 2010 ..................................PTX ISA Version 2.... Descriptions of ......... 173 iv January 24..0 Appendix A..pragma Strings.

......................... Table 7................List of Tables Table 1......................... Table 22........................ 59 Relaxed Type-checking Rules for Source Operands .............. 67 Integer Arithmetic Instructions: mad ............... 45 Floating-Point Rounding Modifiers . Table 10................... Table 20.... Table 6.. 18 Reserved Instruction Keywords . 46 Cost Estimates for Accessing State-Spaces ........................ Table 18............................ 64 Integer Arithmetic Instructions: add....... Table 2.......................... 58 Type Checking Rules ................................................. 58 Floating-Point Comparison Operators Testing for NaN ............................................................ Table 16. Table 24......................................................................................... Table 30. Table 5...... Table 3.............. 46 Integer Rounding Modifiers ..... 57 Floating-Point Comparison Operators Accepting NaN ........... 65 Integer Arithmetic Instructions: sub........................................ Table 15.......... Table 13.. Table 29.................................. Table 11..................... Table 26................................................................................ 61 Integer Arithmetic Instructions: add ...................................................................... 64 Integer Arithmetic Instructions: sub ........................................................................................ 66 Integer Arithmetic Instructions: mul ...................... Table 8. Table 19.............................................................. Table 4.... 25 State Spaces ................................................. 57 Floating-Point Comparison Operators ................. Table 28.................................. Unsigned Integer................................. 71 January 24... 35 Opaque Type Fields in Independent Texture Mode .............. 20 Operator Precedence ............... and Bit-Size Types .......................................................................cc ........ 19 Predefined Identifiers ................................... PTX Directives ...................................................................................................................................................................................... Table 25.....................................................cc ............. 28 Fundamental Type Specifiers ................................................................ 27 Properties of State Spaces ..................................... 70 Integer Arithmetic Instructions: sad ........................................... Table 14..................................................................................................................... Table 32....... 23 Constant Expression Evaluation Rules .................................................................. 65 Integer Arithmetic Instructions: addc ................................................................................................... 35 Convert Instruction Precision and Format ............ Table 9...... 69 Integer Arithmetic Instructions: mad24 ................ Table 27. 68 Integer Arithmetic Instructions: mul24 .... 66 Integer Arithmetic Instructions: subc ........................... Table 12................. Table 17.......... Table 21.............................................................................................................................................. 60 Relaxed Type-checking Rules for Destination Operands............ Table 31............................................................................................. Table 23..................................... 33 Opaque Type Fields in Unified Texture Mode ................................. 2010 v ..... 47 Operators for Signed Integer......................................................

.................................. 94 Floating-Point Instructions: rsqrt ..... 74 Integer Arithmetic Instructions: clz .............. Table 66........................................................................................................................... Table 63.... Table 48............. Table 54.... Table 57.................................................... 79 Summary of Floating-Point Instructions ............. Table 67.... 102 Comparison and Selection Instructions: selp ..................................................... Table 34................................ Table 68........................................................................................................................................ 95 Floating-Point Instructions: sin ....................................................... 97 Floating-Point Instructions: lg2 ........... Table 62.................................... 91 Floating-Point Instructions: neg .............. 72 Integer Arithmetic Instructions: min .......... 76 Integer Arithmetic Instructions: bfe .............................................. Table 38...0 Table 33............................................................................................................. 96 Floating-Point Instructions: cos ............................................... Table 47............ 73 Integer Arithmetic Instructions: max . Table 41......... Table 42.... Table 44.................. Table 46.................................. 92 Floating-Point Instructions: rcp ........... 74 Integer Arithmetic Instructions: bfind ................................... 77 Integer Arithmetic Instructions: bfi ..................... 75 Integer Arithmetic Instructions: brev ..................................... Table 36.......... Table 56.. 2010 ........................................................................................................PTX ISA Version 2....................................... Table 50.............................................. Table 65................. Table 39............................................... Table 52.............. Table 43.............. Table 59.................................. Table 58........ Table 55..................................... 103 Comparison and Selection Instructions: slct ................................................................................................. 78 Integer Arithmetic Instructions: prmt ....... 71 Integer Arithmetic Instructions: abs ...................... 90 Floating-Point Instructions: abs ...... 98 Floating-Point Instructions: ex2 .............................. Integer Arithmetic Instructions: div ................................................................... 72 Integer Arithmetic Instructions: neg .......... Table 60.......................................... Table 35....................... 71 Integer Arithmetic Instructions: rem . 93 Floating-Point Instructions: sqrt ................................ Table 45......................... 88 Floating-Point Instructions: div ............................................... Table 53......................................................................................................... Table 69................. 91 Floating-Point Instructions: min .................................................................................................................................................. 83 Floating-Point Instructions: copysign ................................................................................. 99 Comparison and Selection Instructions: set ................................................................................................ 92 Floating-Point Instructions: max ........ 82 Floating-Point Instructions: testp ........................................... 87 Floating-Point Instructions: mad .............. Table 61... 86 Floating-Point Instructions: fma ......................................................................................................................................................................... Table 64................ 84 Floating-Point Instructions: sub .......... Table 49.................................. 85 Floating-Point Instructions: mul ..... 73 Integer Arithmetic Instructions: popc ....................................................... 83 Floating-Point Instructions: add ................................................................................................................................................................... 101 Comparison and Selection Instructions: setp ................ Table 40.... Table 51. 103 vi January 24.................. Table 37...........................

......................................................... Table 89.................................. 119 Data Movement and Conversion Instructions: cvta . Table 75.... 107 Cache Operators for Memory Load Instructions ................ 135 Parallel Synchronization and Communication Instructions: red .................................. 133 Parallel Synchronization and Communication Instructions: membar ............................................ Table 86............................... vmin............... 142 Video Instructions: vshl......................... Table 98........ 124 Texture and Surface Instructions: suld ............. Table 105........................................... 130 Control Flow Instructions: call ............... Table 106.................. 115 Data Movement and Conversion Instructions: st ............................................................ 2010 vii ........... 106 Logic and Shift Instructions: not ......... 131 Control Flow Instructions: exit ........................ Table 80........... 118 Data Movement and Conversion Instructions: isspacep ............. 107 Logic and Shift Instructions: shr ...... Table 72............ 128 Control Flow Instructions: { } .................................................... Table 100............... 123 Texture and Surface Instructions: txq .............Table 70.. vsub......... 109 Cache Operators for Memory Store Instructions ................................. 129 Control Flow Instructions: @ ........................... 111 Data Movement and Conversion Instructions: mov ........................................................ 105 Logic and Shift Instructions: xor ........ 126 Texture and Surface Instructions: sured.......................................... Table 90... 120 Texture and Surface Instructions: tex .................................... prefetchu .......................................................... Table 82................................. 119 Data Movement and Conversion Instructions: cvt ... Table 102.. 105 Logic and Shift Instructions: or ... 106 Logic and Shift Instructions: shl ................................................. vshr ............................................... 127 Texture and Surface Instructions: suq ............................ Table 71...................................... vabsdiff.................................. Table 103..................... Table 101................... Logic and Shift Instructions: and ................. 110 Data Movement and Conversion Instructions: mov ...................... Table 104.............. Table 84............................................ Table 81............................... Table 93...... 116 Data Movement and Conversion Instructions: prefetch................... Table 96...... Table 99......................... 137 Parallel Synchronization and Communication Instructions: vote .. Table 78................................................ Table 97....................................... Table 79.... Table 76............................................................................................ Table 77....................... 130 Control Flow Instructions: ret ............................. 139 Video Instructions: vadd........................................................ Table 95. Table 85............................................................. Table 92........ Table 87........... 129 Control Flow Instructions: bra ................................................................................................................................ 143 January 24.............. Table 73............... 125 Texture and Surface Instructions: sust ..... Table 94.................................... 106 Logic and Shift Instructions: cnot ....................................................................................................... Table 91........ 112 Data Movement and Conversion Instructions: ld .......... Table 88.............................. vmax ..... Table 74.......................................... 131 Parallel Synchronization and Communication Instructions: bar ..................................................................................... 134 Parallel Synchronization and Communication Instructions: atom ..... 113 Data Movement and Conversion Instructions: ldu ................. Table 83.................................

. Table 137..................... 158 Kernel and Function Directives: .............................................................................. Table 142............................ 167 Debugging Directives: ............... 2010 ................................................................. 150 Special Registers: %laneid ...... 153 Special Registers: %lanemask_eq ....... Table 134...........................PTX ISA Version 2..................................................................... 155 Special Registers: %lanemask_gt ...................................... 154 Special Registers: %lanemask_le ..... Table 124.............. 151 Special Registers: %ctaid ................ 153 Special Registers: %nsmid ........................................................................... Table 116..................................................................................target ......................................... Table 120......................... Table 135.. Table 119........................ 165 Debugging Directives: @@DWARF .......................................................................................... 154 Special Registers: %lanemask_lt ........ Table 117....................... Video Instructions: vmad .................... 152 Special Registers: %smid ..... Table 121.........................minnctapersm .................................................... Table 110....... 154 Special Registers: %lanemask_ge ..................................................... Table 126............... 150 Special Registers: %ntid ............... 164 Performance-Tuning Directives: .............loc ............................................................................version........ %pm2....................................... 151 Special Registers: %nwarpid .......................................... Table 143............................... 153 Special Registers: %gridid ....... Table 139...... Table 127............ 144 Video Instructions: vset..section ................. Table 111.......... 156 Special Registers: %clock64 ................... 167 Debugging Directives: ......................................... Table 123..... Table 108. 164 Performance-Tuning Directives: ..file ................................... 157 PTX File Directives: ......................... Table 133........................... 147 Miscellaneous Instructions: pmevent............................. 147 Special Registers: %tid ....... 161 Performance-Tuning Directives: .. 167 Linking Directives: .... Table 131.......................... Table 122............................0 Table 107.... 163 Performance-Tuning Directives: ..... Table 114..................func ... %pm1. 152 Special Registers: %nctaid ............................................................................................................................................ 163 Performance-Tuning Directives: ..................................................................................................................................................... Table 109.......................................................................................maxnctapersm (deprecated) ...maxntid .... 160 Kernel and Function Directives: ................................................................. 155 Special Registers: %clock .................................................................................pragma ........................... Table 112....................................................................... 166 Debugging Directives: ............................................................... 151 Special Registers: %warpid ............................................ Table 136......... Table 138................ Table 125..... Table 118............................................................................................................................ 156 PTX File Directives: ..extern............. Table 130......................................... Table 113..................................... %pm3 ............................ 147 Miscellaneous Instructions: brkpt .maxnreg . 168 viii January 24.................................................... Table 141...... Table 129................ 156 Special Registers: %pm0.....................entry........ Table 132. Table 128............ Table 140.......... 146 Miscellaneous Instructions: trap .................................................. Table 115........................................................

.......... Table 145................Table 144................................ Linking Directives: ......................................................................... 173 January 24.visible.................. 168 Pragma Strings: “nounroll” ........ 2010 ix .............

0 x January 24.PTX ISA Version 2. 2010 .

a low-level parallel thread execution virtual machine and instruction set architecture (ISA).1. video encoding and decoding.2. Because the same program is executed for each data element. PTX programs are translated at install time to the target hardware instruction set. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. which are optimized for and translated to native target-architecture instructions. PTX exposes the GPU as a data-parallel computing device. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. and pattern recognition can map image blocks and pixels to parallel processing threads. 2010 1 . In fact.Chapter 1. image and media processing applications such as post-processing of rendered images. high-definition 3D graphics. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. stereo vision. 1. from general signal processing or physics simulation to computational finance or computational biology. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. and because it is executed on many data elements and has high arithmetic intensity. Similarly. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. January 24. many-core processor with tremendous computational horsepower and very high memory bandwidth. the programmable GPU has evolved into a highly parallel. Introduction This document describes PTX. the memory access latency can be hidden with calculations instead of big data caches. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Data-parallel processing maps data elements to parallel processing threads. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. image scaling. PTX defines a virtual machine and ISA for general purpose parallel thread execution. 1. multithreaded. there is a lower requirement for sophisticated flow control.

Provide a common source-level ISA for optimizing code generators and translators. The fma. A “flush-to-zero” (. memory.f32 require a rounding modifier for sm_20 targets. Both fma. PTX 2.sat modifiers. sub.ftz and . The changes from PTX ISA 1.0 is in improved support for the IEEE 754 floating-point standard.f32 maps to fma.rm and .3.0 are improved support for IEEE 754 floating-point operations. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. and architecture tests.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.PTX ISA Version 2. The mad.f32 requires sm_20. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 instruction also supports . reduction.rp rounding modifiers for sm_20 targets. PTX ISA Version 2.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.x code will continue to run on sm_1x targets as well. and all PTX 1. • • • 2 January 24. Facilitate hand-coding of libraries. 1. The mad. and video instructions. Legacy PTX 1.rn. addition of generic addressing to facilitate the use of general-purpose pointers.1. Achieve performance in compiled applications comparable to native GPU performance.0 PTX ISA Version 2. barrier. Improved Floating-Point Support A main area of change in PTX 2.f32.3. The main areas of change in PTX 2. and mul now support . When code compiled for sm_1x is executed on sm_20 devices. Instructions marked with .f32 for sm_20 targets. 1.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Provide a machine-independent ISA for C/C++ and other compilers to target. which map PTX to specific target machines. Most of the new features require a sm_20 target. surface. Single-precision add.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 is a superset of PTX 1. mad.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. A single-precision fused multiply-add (fma) instruction has been added. atomic. 2010 . performance kernels. including integer. and the introduction of many new instructions.ftz) modifier may be used to enforce backward compatibility with sm_1x.x features are supported on the new sm_20 target. Provide a code distribution ISA for application and middleware developers.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.x.f32 and mad. fma.

local. so recursion is not yet supported. atom. Instruction cvta for converting global. e. st. . A new cvta instruction has been added to convert global. and sqrt with IEEE 754 compliant rounding have been added. allowing memory instructions to access these spaces without needing to specify the state space.Chapter 1.g. st. PTX 2. for prefetching to specified level of memory hierarchy.clamp and . isspacep.4.. suld. January 24. ldu. Support for an Application Binary Interface Rather than expose details of a particular calling convention. and shared state spaces. special registers. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.zero. Surface instructions support additional clamp modifiers. Surface Instructions • • Instruction sust now supports formatted surface stores. NOTE: The current version of PTX does not implement the underlying.and double-precision div. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Instructions prefetch and prefetchu have been added.0 closer to full compliance with the IEEE 754 standard. local. Cache operations have been added to instructions ld. and shared addresses to generic address and vice-versa has been added. 1. Generic Addressing Another major change is the addition of generic addressing. prefetchu. 1. local. These are indicated by the use of a rounding modifier and require sm_20. instructions ld. In PTX 2. prefetch. 2010 3 .0.0. stack-based ABI. and red now support generic addressing. stack layout. Instructions testp and copysign have been added. i.3.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.e. Introduction • Single.2. and shared addresses to generic addresses. an address that is the same across all threads in a warp.3.3. • Taken as a whole. these changes bring PTX 2. and directives are introduced in PTX 2. and sust. New Instructions The following new instructions. and vice versa. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. rcp. 1. Generic addressing unifies the global. and Application Binary Interface (ABI). cvta.3.

sys.pred have been added. Reduction. . New special registers %nsmid.ge.red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added. Instructions bar. 4 January 24. has been added.u32 and bar. bfi bit field extract and insert popc clz Atomic.add. Other Extensions • • • Video instructions (includes prmt) have been added. vote. membar.or}.red}.f32 have been added.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.red. A bar.{and.gt} have been added. Barrier Instructions • • A system-level membar instruction.popc.arrive instruction has been added.shared have been extended to handle 64-bit data types for sm_20 targets.b32.section. Instructions {atom.PTX ISA Version 2.ballot. bar now supports an optional thread count and register operands. 2010 .red}.le. %lanemask_{eq.lt. A new directive. and Vote Instructions • • • New atomic and reduction instructions {atom. %clock64. A “vote ballot” instruction.

The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.Chapter 1. Chapter 8 describes the instruction set. Chapter 9 lists special registers. Chapter 11 provides release notes for PTX Version 2.0. Introduction 1. Chapter 5 describes state spaces.4. calling convention. January 24. Chapter 3 gives an overview of the PTX virtual machine model. and PTX support for abstracting the Application Binary Interface (ABI). 2010 5 . Chapter 10 lists the assembly directives supported in PTX. types. Chapter 7 describes the function and call syntax. Chapter 6 describes instruction operands. and variable declarations. Chapter 4 describes the basic syntax of the PTX language.

PTX ISA Version 2. 2010 .0 6 January 24.

Each thread has a unique thread identifier within the CTA. A cooperative thread array. January 24. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. compute addresses. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Threads within a CTA can communicate with each other. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. 2D. 2010 7 . can be isolated into a kernel function that is executed on the GPU as many different threads. To that effect. or CTA. data-parallel. Cooperative thread arrays (CTAs) implement CUDA thread blocks. To coordinate the communication of the threads within the CTA.2. Programming Model 2. and tid. or host: In other words. one can specify synchronization points where threads wait until all threads in the CTA have arrived.y. 2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.x. assign specific input and output positions.1. and results across the threads of the CTA.1.x. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. or 3D CTA. ntid. (with elements tid.z).y.Chapter 2. The thread identifier is a three-element vector tid. is an array of threads that execute a kernel concurrently or in parallel. work. Each CTA thread uses its thread identifier to determine its assigned role. It operates as a coprocessor to the main CPU. 2. or 3D shape specified by a three-element vector ntid (with elements ntid. More precisely. tid. a portion of an application that is executed many times. and select work to perform.2. 2D.z) that specifies the thread’s position within a 1D. but independently on different data. Programs use a data parallel decomposition to partition inputs. compute-intensive portions of applications running on the host are off-loaded onto the device. and ntid. Each CTA has a 1D. The vector ntid specifies the number of threads in each CTA dimension.

depending on the platform. 2D . %ntid.0 Threads within a CTA execute in SIMT (single-instruction. read-only special registers %tid. Some applications may be able to maximize performance with knowledge of the warp size. Each grid of CTAs has a 1D. and %gridid.2. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. which may be used in any instruction where an immediate operand is allowed. such that the threads execute the same instructions at the same time. 8 January 24. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. 2. This comes at the expense of reduced thread communication and synchronization. The host issues a succession of kernel invocations to the device. or 3D shape specified by the parameter nctaid. Threads may read and use these values through predefined. so that the total number of threads that can be launched in a single kernel invocation is very large. Typically. a warp has 32 threads.PTX ISA Version 2.2. WARP_SZ. %ctaid. because threads in different CTAs cannot communicate and synchronize with each other. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). A warp is a maximal subset of threads from a single CTA. Each grid also has a unique temporal grid identifier (gridid). However. so PTX includes a run-time immediate constant. Threads within a warp are sequentially numbered. multiple-thread) fashion in groups called warps. The warp size is a machine-dependent constant. Multiple CTAs may execute concurrently and in parallel. 2010 . %nctaid. CTAs that execute the same kernel can be batched together into a grid of CTAs. or sequentially.

0) CTA (0. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (3. 0) Thread (2.Chapter 2. 2) Thread (4. 0) Thread (0. 1) CTA (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (0. 1) Thread (0. Figure 1. 0) CTA (2. Thread Batching January 24. 0) Thread (4. 1) CTA (2. 1) Thread (3. 1) Thread (2. 0) Thread (3. 1) Thread (4. 0) Thread (1. 2) Thread (2. 2) Thread (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) CTA (1. 2010 9 . A grid is a set of CTAs that execute independently. 1) Thread (1.

Both the host and the device maintain their own local memory. as well as data filtering. The global. Texture memory also offers different addressing modes.0 2. Finally. constant. constant. The global. 10 January 24. The device memory may be mapped and read or written by the host. 2010 . all threads have access to the same global memory.PTX ISA Version 2. referred to as host memory and device memory. or. for more efficient transfer. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. for some specific data formats. Each thread has a private local memory. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine.3. and texture memory spaces are optimized for different memory usages. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. and texture memory spaces are persistent across kernel launches by the same application. respectively.

2) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Figure 2. 1) Grid 1 Global memory Block (0. 0) Block (0. 0) Block (0. 0) Block (2. Memory Hierarchy January 24. 1) Block (1. 0) Block (1. 1) Block (2. 0) Block (1. 2010 11 . 1) Block (0.Chapter 2. 1) Block (1.

0 12 January 24.PTX ISA Version 2. 2010 .

and when all paths complete. disabling threads that are not on that path. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. At every instruction issue time. The multiprocessor maps each thread to one scalar processor core. each warp contains threads of consecutive. multiple-thread). allowing. schedules.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). Branch divergence occurs only within a warp. If threads of a warp diverge via a data-dependent conditional branch. When a host program invokes a kernel grid. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. It implements a single-instruction barrier synchronization. the multiprocessor employs a new architecture we call SIMT (single-instruction. and on-chip shared memory. manages.Chapter 3. and executes threads in groups of parallel threads called warps. manages. Parallel Thread Execution Machine Model 3. When a multiprocessor is given one or more thread blocks to execute. The multiprocessor SIMT unit creates. and each scalar thread executes independently with its own instruction address and register state. the warp serially executes each branch path taken. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. (This term originates from weaving. the first parallel thread technology. different warps execute independently regardless of whether they are executing common or disjointed code paths. A warp executes one common instruction at a time. 2010 13 . The threads of a thread block execute concurrently on one multiprocessor. The way a block is split into warps is always the same. increasing thread IDs with the first warp containing thread 0. To manage hundreds of threads running several different programs. new blocks are launched on the vacated multiprocessors.1. a voxel in a volume. January 24. the threads converge back to the same execution path. As thread blocks terminate. a cell in a grid-based computation). so full efficiency is realized when all threads of a warp agree on their execution path. and executes concurrent threads in hardware with zero scheduling overhead. it splits them into warps that get scheduled by the SIMT unit. a multithreaded instruction unit. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. A multiprocessor consists of multiple Scalar Processor (SP) cores. for example. The multiprocessor creates.

each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. modifies. as well as data-parallel code for coordinated threads. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. the number of serialized writes that occur to that location and the order in which they occur is undefined. each read. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. however. on the other hand. the programmer can essentially ignore the SIMT behavior. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space.PTX ISA Version 2. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. If there are not enough registers or shared memory available per multiprocessor to process at least one block.0 SIMT architecture is akin to SIMD (Single Instruction. but one of the writes is guaranteed to succeed. A multiprocessor can execute as many as eight thread blocks concurrently. • The local and global memory spaces are read-write regions of device memory and are not cached. In contrast with SIMD vector machines. In practice. but the order in which they occur is undefined. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. which is a read-only region of device memory. As illustrated by Figure 3. write to that location occurs and they are all serialized. SIMT enables programmers to write thread-level parallel code for independent. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. the kernel will fail to launch. For the purposes of correctness. 14 January 24. If an atomic instruction executed by a warp reads. which is a read-only region of device memory. scalar threads. A key difference is that SIMD vector organizations expose the SIMD width to the software. Vector architectures. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. 2010 . and writes to the same location in global memory for more than one of the threads of the warp. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. require the software to coalesce loads into vectors and manage divergence manually. whereas SIMT instructions specify the execution and branching behavior of a single thread. modify.

Hardware Model January 24. Figure 3.Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 .

PTX ISA Version 2.0 16 January 24. 2010 .

1. See Section 9 for a more information on these directives. The C preprocessor cpp may be used to process PTX source files.2. 4. #endif. Lines beginning with # are preprocessor directives. using non-nested /* and */ for comments that may span multiple lines. #ifdef. Comments Comments in PTX follow C/C++ syntax. #define. Syntax PTX programs are a collection of text source files. All whitespace characters are equivalent.target directive specifying the target architecture assumed. #if. January 24. whitespace is ignored except for its use in separating tokens in the language.Chapter 4. Source Format Source files are ASCII text. The following are common preprocessor directives: #include. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. followed by a . 4. #line. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.version directive specifying the PTX language version. and using // to begin a comment that extends to the end of the current line. Lines are separated by the newline character (‘\n’). #else. Pseudo-operations specify symbol and addressing management. 2010 17 . Each PTX file must begin with a . PTX is case sensitive and uses lowercase for keywords. Comments in PTX are treated as whitespace.

so no conflict is possible with user-defined identifiers.target .const . r2.visible 4. %tid.global.file PTX Directives .1.version . written as @!p.b32 r1.section .3. . address expressions. constant expressions. The guard predicate follows the optional label and precedes the opcode.reg .align .extern .func . r2.local .PTX ISA Version 2.shared .entry . 2. Directive Statements Directive keywords begin with a dot. 0. or label names. and is written as @p. Instructions have an optional guard predicate which controls conditional execution. r2. The guard predicate may be optionally negated. Operands may be register variables. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. shl. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. r1.maxnreg .b32 r1. ld.x. mov. 18 January 24.f32 array[N].0 4.maxntid .2.b32 add. Examples: .3. Statements begin with an optional label and end with a semicolon.pragma .sreg . array[r1].minnctapersm .param .global .global start: . followed by source operands.reg .loc . 2010 .b32 r1. where p is a predicate register. and terminated with a semicolon. All instruction keywords are reserved tokens in PTX.tex . Table 1.5. Statements A PTX statement is either a directive or an instruction.maxnctapersm . Instruction keywords are listed in Table 2.3. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. .f32 r2. The destination operand is first.

Syntax Table 2. 2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

2010 . or they start with an underscore. digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign. …. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. underscore. except that the percentage sign is not allowed. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. listed in Table 3.4.g.0 4. dollar. The percentage sign can be used to avoid name conflicts. underscore. e. PTX allows the percentage sign as the first character of an identifier. Many high-level languages such as C and C++ follow similar rules for identifier names. Table 3. digits. or dollar characters. or percentage character followed by one or more letters. %pm3 WARP_SZ 20 January 24. between user-defined variable names and compiler-generated names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.PTX ISA Version 2.

To specify IEEE 754 single-precision floating point values. 4. 2010 21 . To specify IEEE 754 doubleprecision floating point values. floating-point. integer constants are allowed and are interpreted as in C. 0[fF]{hexdigit}{8} // single-precision floating point January 24. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.s64) unless the value cannot be fully represented in . Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. zero values are FALSE and non-zero values are TRUE. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. i.Chapter 4. the constant begins with 0d or 0D followed by 16 hex digits. in which case the literal is unsigned (. every integer constant has type . and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. The syntax follows that of C. Type checking rules remain the same for integer. i.. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. the constant begins with 0f or 0F followed by 8 hex digits. Floating-point literals may be written with an optional decimal point and an optional signed exponent.2.s64 or the unsigned suffix is specified. 4. and bit-size types.1.s64 or . Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.5.e. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. hexadecimal. Integer literals may be written in decimal. When used in an instruction or data initialization. the sm_1x and sm_20 targets have a WARP_SZ value of 32. where the behavior of the operation depends on the operand types. These constants may be used in data initialization and as operands to instructions. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.u64. each integer constant is converted to the appropriate size based on the data or instruction type at its use. literals are always represented in 64-bit double-precision format. Constants PTX supports integer and floating-point constants and constant expressions. there is no suffix letter to specify size.e.5. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.5.. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. octal. Unlike C and C++.u64). Syntax 4. or binary notation. For predicate-type data and instructions.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

January 24, 2010

Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

January 24, 2010

23

PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

24

January 24, 2010

u64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .f64 converted type . Table 5.f64 integer integer integer integer integer int ?.s64.s64 .Chapter 4.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. or .s64 .f64 converted type constant literal + ! ~ Cast Binary (.5.f64 integer .u64 1st unchanged.u64. 2010 25 .f64 : . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .6.u64 .u64 same as 1st operand .f64 use usual conversions .u64) (.s64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .f64 use usual conversions . Syntax 4.f64 integer .s64 .s64) + .f64 same as source .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .f64 use usual conversions .u64 .s64 .u64 . .u64 . 2nd is .s64 .

0 26 January 24.PTX ISA Version 2. 2010 .

. the kinds of resources will be common across platforms. State Spaces. pre-defined.shared . Global texture memory (deprecated). or Function or local parameters.tex January 24.const .param . defined per-grid. fast. Read-only.reg . The characteristics of a state space include its size. Global memory. Local memory. and properties of state spaces are shown in Table 5. access speed. Types. Table 6. The list of state spaces is shown in Table 4. Special registers. platform-specific. defined per-thread. access rights. read-only memory. and Variables While the specific resources available in a given target GPU will vary. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Shared. private to each thread. All variables reside in some state space. and level of sharing between threads. addressability. 2010 27 .Chapter 5.sreg .1. State Spaces A state space is a storage area with particular characteristics. Kernel parameters. Addressable memory shared between threads in 1 CTA.global .local . Name State Spaces Description Registers. shared by all threads. 5. and these resources are abstracted in PTX through state spaces and data types.

and will vary from platform to platform.2. predicate) or untyped.1. 32-. aside from predicate registers which are 1-bit. 64-. and cvt instructions. and vector registers have a width of 16-. All special registers are predefined.tex Restricted Yes No3 5. clock counters.const . CTA. or 128-bits.e. 32-. 28 January 24. st.reg state space) are fast storage locations.shared .reg .sreg) state space holds predefined. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 1 Accessible only via the ld. 5. i.global .param instruction. or 64-bits. The most common use of 8-bit registers is with ld. and performance monitoring registers. Special Register State Space The special register (.local . unsigned integer.param and st. floating point. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.param (as input to kernel) . Register State Space Registers (. When the limit is exceeded.1. such as grid. Registers may be typed (signed integer. it is not possible to refer to the address of a register. Registers may have alignment boundaries required by multi-word loads and stores.local state space.1. platform-specific registers. For each architecture. causing changes in performance. the parameter is then located on the stack frame and its address is in the . 16-.. or as elements of vector tuples. 3 Accessible only via the tex instruction.0 Table 7.param instructions. Address may be taken via mov instruction. Device function input parameters may have their address taken via mov. scalar registers have a width of 8-. Registers differ from the other state spaces in that they are not fully addressable. register variables will be spilled to memory. The number of registers is limited. 2010 .sreg . Register size is restricted.param (used in functions) . 2 Accessible via ld. and thread parameters.PTX ISA Version 2.

whereas local memory variables declared January 24. each pointing to the start address of the specified constant bank.sync instruction. It is the mechanism by which different CTAs and different grids can communicate. The size is limited. there are eleven 64KB banks. where bank ranges from 0 to 10. For any thread in a context.b32 const_buffer[]. Constant State Space The constant (. For example. In implementations that support a stack. ld. Types. bank zero is used for all statically-sized constant variables. Banks are specified using the .sync instruction are guaranteed to be visible to any reads after the barrier instruction.b32 const_buffer[]. If another thread sees the variable b change.global. This reiterates the kind of parallelism available in machines that run PTX.1.5. The constant memory is organized into fixed size banks.global to access global variables.local) is private memory for each thread to keep its own data.local to access local variables.b32 %r1. It is typically standard memory with cache. as it must be allocated on a perthread basis. Threads wait at the barrier until all threads in the CTA have arrived.extern . Use ld. the bank number must be provided in the state space of the load instruction. State Spaces. Use ld. All memory writes prior to the bar. // load second word 5. the store operation updating a may still be in flight.extern . [const_buffer+4]. an incomplete array in bank 2 is accessed as follows: . and Variables 5. all addresses are in global memory are shared. 2010 29 . Sequential consistency is provided by the bar. For example.local and st.1. Threads must be able to do their work without waiting for other threads to do theirs. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.1. Module-scoped local memory variables are stored at fixed addresses.4.const[bank] modifier.global) state space is memory that is accessible by all threads in a context.const[2] .const[2] . Multiple incomplete array variables declared in the same bank become aliases. Global State Space The global (. the stack is in local memory. 5. Consider the case where one thread executes the following two assignments: a = a + 1. If no bank number is given. For the current devices.const) state space is a read-only memory.const[2].Chapter 5. To access data in contant banks 1 through 10. st. b = b – 1. the declaration . By convention. Global memory is not sequentially consistent. Local State Space The local state space (. as in lock-free and wait-free style programming. initialized by the host. The remaining banks may be used to implement “incomplete” constant arrays (in C. for example). results in const_buffer pointing to the start of constant bank two. bank zero is used.global. where the size is not known at compile time.3. This pointer can then be used to access the entire 64KB constant bank. and atom.

Kernel Function Parameters Each kernel function definition includes an optional list of parameters.x supports only kernel function parameters in . in some implementations kernel parameters reside in global memory. (2a) to declare formal input and return parameters for device functions called from within kernel execution. Note that PTX ISA versions 1. Values passed from the host to the kernel are accessed through these parameter variables using ld.param . device function parameters were previously restricted to the register state space.param space. ld. mov. In implementations that do not support a stack. The use of parameter state space for device function parameters is new to PTX ISA version 2. %n. … Example: .0 within a function or kernel body are allocated on the stack.reg .u32 %ptr. typically for passing large structures by value to a function.param. ld. len.reg .entry bar ( . ld. No access protection is provided between parameter and global space in this case.1. The resulting address is in the .param) state space is used (1) to pass input arguments from the host to the kernel. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). These parameters are addressable. Similarly.6.param .b8 buffer[64] ) { .1.u32 %n. 2010 . . [buffer]. Note: The location of parameter space is implementation specific.param. [%ptr]. 5. The address of a kernel parameter may be moved into a register using the mov instruction.param instructions. all local memory variables are stored at fixed addresses and recursive function calls are not supported.PTX ISA Version 2.param .param state space and is accessed using ld.param space variables.param state space.entry foo ( .b32 N. per-kernel versus per-thread).reg .align 8 . and (2b) to declare locally-scoped byte array variables that serve as function call arguments. … 30 January 24. [N]. Parameter State Space The parameter (.u32 %n.u32 %n.f64 %d.u32 %ptr. The kernel parameter variables are shared across all CTAs within a grid. 5.0 and requires target architecture sm_20. read-only variables declared in the .1. PTX code should make no assumptions about the relative locations or ordering of . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.b32 len ) { .f64 %d. . Therefore.param instructions. Example: .param. For example.6.

Function input parameters may be read via ld. }. dbl. [buffer+8]. This will be passed by value to a callee. it is illegal to write to an input parameter or read from a return parameter.2.b8 mystruct. The most common use is for passing objects by value that do not fit within a PTX register. the address of a function input parameter may be moved into a register using the mov instruction. int y. Typically.param byte array variable that represents a flattened C structure or union.param formal parameter having the same size and alignment as the passed argument.param .func foo ( . which declares a . It is not possible to use mov to get the address of a return parameter or a locally-scoped . . .reg . int y.param.s32 %y.Chapter 5.param and function return parameters may be written using st. passed to foo … . In this case. In PTX.param. .local and st.s32 [mystruct+8].0 extends the use of parameter space to device function parameters. .s32 %y. st.f64 %d.reg . call foo.param space variable. ld. 2010 31 .6. Types.local state space and is accessed via ld.b8 buffer[12] ) { . Device Function Parameters PTX ISA version 2. Note that the parameter will be copied to the stack if necessary. (4.param.f64 %d.param.param .f64 [mystruct+0]. Example: // pass object of type struct { double d. is flattened. … } // code snippet from the caller // struct { double d.reg . x. ld. … See the section on function call syntax for more details.param space is also required whenever a formal parameter has its address taken within the called function. a byte array in parameter space is used. such as C structures larger than 8 bytes.f64 dbl.reg .reg . and Variables 5. the caller will declare a locally-scoped .align 8 . } mystruct. mystruct).s32 x. State Spaces.align 8 . … st. and so the address will be in the . Aside from passing structures by value. [buffer].1.local instructions. . January 24.b32 N.param. .

shared and st.tex .tex . is equivalent to . Shared memory typically has some optimizations to support the sharing.1. where texture identifiers are allocated sequentially beginning with zero.tex . Texture State Space (deprecated) The texture (.u32 tex_a.global .tex variables are required to be defined in the global scope. The .shared to access shared variables.6 for its use in texture instructions.tex .u64. Shared State Space The shared (.PTX ISA Version 2. A texture’s base address is assumed to be aligned to a 16-byte boundary. An address in shared memory can be read and written by any thread in a CTA.tex . An error is generated if the maximum number of physical resources is exceeded. a legacy PTX definitions such as . It is shared by all threads in a context.7.texref tex_a.texref. and variables declared in the .tex directive will bind the named texture memory variable to a hardware texture identifier. Texture memory is read-only. and . Another is sequential access from sequential threads. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex directive is retained for backward compatibility. Example: .texref variables in the . where all threads read from the same address.u32 . 32 January 24. 5. The . 2010 . tex_c. and programs should instead reference texture memory through variables of type . One example is broadcast. tex_f.global state space. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). Use ld. Multiple names may be bound to the same physical texture identifier. For example.8.texref type and Section 8.u32 .u32 or .3 for the description of the .tex state space are equivalent to module-scoped .u32 .tex) state space is global memory accessed via the texture instruction. tex_d.1. tex_d.u32 tex_a.7. The texture name must be of type . See Section 5. Physical texture resources are allocated on a per-module granularity.0 5.

. All floating-point instructions operate only on . ld.1. January 24.u16. so that narrow values may be loaded. stored.f32 and .b32.f16 floating-point type is allowed only in conversions to and from . . . but typed variables enhance program readability and allow for better operand type checking. st.f32.u8.s8. and .b8 instruction types are restricted to ld. all variables (aside from predicates) could be declared using only bit-size types. and instructions operate on these types. A fundamental type specifies both a basic type and a size. .b16.b8. Types 5. stored. so their names are intentionally short.f64 types. Register variables are always of a fundamental type.s16. In principle. The bitsize type is compatible with any fundamental type having the same size. .u8. or converted to other types and sizes.2. . and cvt instructions permit source and destination data operands to be wider than the instruction-type size.f32 and . 5. Types.pred Most instructions have one or more type specifiers. . Operand types and sizes are checked against instruction types for compatibility. Signed and unsigned integer types are compatible if they have the same size. Restricted Use of Sub-Word Sizes The . st. and cvt instructions. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.s32. Two fundamental types are compatible if they have the same basic type and are the same size. needed to fully specify instruction behavior. .f64 types.2.s64 . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . the fundamental types reflect the native data types supported by the target architectures. 2010 33 .b64 . Fundamental Types In PTX. The . . For convenience.2.s8. State Spaces.2.f16. The following table lists the fundamental type specifiers for each basic type: Table 8. . For example.f64 .Chapter 5. .u32.u64 . The same typesize specifiers are used for both variable definitions and for typing instructions. and Variables 5. and converted using regular-width registers. .

and Surface Types PTX includes built-in “opaque” types for defining texture. opaque_var. and overall size is hidden to a PTX program. or surfaces via texture and surface load/store instructions (tex. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. and surface descriptor variables.texref handle.{u32. store. base address. and . field ordering. In the independent mode. since these properties are defined by . These types have named fields similar to structures. suq).texref type that describe sampler properties are ignored. suld.PTX ISA Version 2. but the pointer cannot otherwise be treated as an address. PTX has two modes of operation. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.samplerref.surfref. texture and sampler information is accessed through a single . and query instructions. i. or performing pointer arithmetic will result in undefined results. In the unified mode. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. The three built-in types are . Retrieving the value of a named member via query instructions (txq. passed as a parameter to functions. allowing them to be defined separately and combined at the site of usage in the program.e. In independent mode the fields of the . accessing the pointer with ld and st instructions. but all information about layout. hence the term “opaque”. samplers. Creating pointers to opaque variables using mov. sured).u64} reg.samplerref variables.texref. and de-referenced by texture and surface load. sampler.3. sust. the resulting pointer may be stored to and loaded from memory. Texture. Referencing textures. The following tables list the named members of each type for unified and independent texture modes. 2010 . Sampler. texture and sampler information each have their own handle. .0 5.. 34 January 24. For working with textures and samplers.

surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_border 0. clamp_ogl. 1 nearest. clamp_ogl.texref values in elements in elements in elements 0. Member width height depth Opaque Type Fields in Independent Texture Mode . 2010 35 . 1 ignored ignored ignored ignored . clamp_to_edge.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.samplerref values N/A N/A N/A N/A nearest. Member width height depth Opaque Type Fields in Unified Texture Mode . mirror. clamp_to_border N/A N/A N/A N/A N/A . mirror.Chapter 5. State Spaces. and Variables Table 9. linear wrap. Types.texref values . clamp_to_edge. linear wrap.

samplerref tsamp1 = { addr_mode_0 = clamp_to_border.param state space. .global .texref my_texture_name.samplerref my_sampler_name. . At module scope.global .global . these variables are declared in the . Example: . these variables must be in the . 36 January 24. As kernel parameters.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.texref tex1. .global state space. filter_mode = nearest }.PTX ISA Version 2.global . the types may be initialized using a list of static expressions assigning values to the named members. 2010 . When declared at module scope. Example: .global .surfref my_surface_name.

v4 .4.v1. Every variable must reside in one of the state spaces enumerated in the previous section. PTX supports types for simple aggregate objects such as vectors and arrays. 0.reg . Predicate variables may only be declared in the register state space. Examples: . r.f64 is not allowed. vector variables are aligned to a multiple of their overall size (vector length times base-type size). // typedef .u8 bg[4] = {0. where the fourth element provides padding. .global . its type and size.v3 }. and they may reside in the register space. and an optional fixed address for the variable. . Vectors must be based on a fundamental type. A variable declaration names the space in which the variable resides.1. 2010 37 .2.f32 V.v4 . 0}.u32 loc. .v4 . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .global . and Variables 5. a variable declaration describes both the variable’s type and its state space. 5.4. State Spaces. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. 5.struct float4 coord. Examples: .v4. January 24.v4 vector. q.b8 v.u16 uv. 1.f32 v0. an optional array size.f32 bias[] = {-1.v2 or .s32 i. Vectors cannot exceed 128-bits in length.f32 accel.reg . // a length-2 vector of unsigned ints .pred p. . // a length-4 vector of bytes By default. textures.0}.global . This is a common case for three-dimensional grids.global . its name. Three-element vectors may be handled by using a . Types. etc. an optional initializer. // a length-4 vector of floats .0. for example. . Variables In PTX. . 0. Variable Declarations All storage for data is specified with variable declarations.v2. Vectors Limited-length vector types are supported.4. .global .reg .v2 .shared .struct float4 { .Chapter 5.const . In addition to fundamental types.v4.

. 0}.0}. A scalar takes a single value. 5.PTX ISA Version 2. where the variable name is followed by an equals sign and the initial value or values for the variable.4. variable initialization is supported only for constant and global state spaces. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. Array Declarations Array declarations are provided to allow the programmer to reserve space. .u8 rgba[3] = {{1.1}..1. The size of the dimension is either a constant expression.0.global .0 5. Examples: .4. . Initializers Declared variables may specify an initial value using a syntax similar to C/C++. this can be used to statically initialize a pointer to a variable.u32 or .s32 offset[][] = { {-1. 0}. Here are some examples: .{.b32 ptr = rgba.0.3.s32 n = 10.f16 and . {0.v4 .05.05}}. 1} }. 19*19 (361) halfwords are reserved (722 bytes). {0.shared . To declare an array. {0.0..0}}.. .05.{.global . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). . Variable names appearing in initializers represent the address of the variable.4.u64.. For the kernel declaration above.local .f32 blur_kernel[][] = {{.u16 kernel[19][19]. 38 January 24. // address of rgba into ptr Currently.1. 2010 .global .u8 mailbox[128]. Initializers are allowed for all types except .1.global .0.global .0}. or is left empty. being determined by an array initializer. The size of the array specifies how many elements should be reserved.. this can be used to initialize a jump table to be used with indirect branches or calls.4. label names appearing in initializers represent the address of the next instruction following the label.pred.1. -1}.1. {0. {1. Similarly.05}. Variables that hold addresses of variables or instructions should be of type . .

State Spaces.4.. The default alignment for scalar and array variables is to a multiple of the base-type size. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.b32 %r<100>. not for individual elements.0. %r1. . Examples: // allocate array at 4-byte aligned address.6. Alignment is specified using an optional .5. The variable will be aligned to an address which is an integer multiple of byte-count. January 24.align byte-count specifier immediately following the state-space specifier. Types.b8 bar[8] = {0.Chapter 5. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. %r1. it is quite common for a compiler frontend to generate a large number of register names. For example. and may be preceded by an alignment specifier. …. For arrays. Rather than require explicit declaration of every name..2. named %r0.reg . Elements are bytes. of . Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.0.0}. 2010 39 . alignment specifies the address alignment for the starting address of the entire array.. and Variables 5. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.0.b32 variables. suppose a program uses a large number.4. These 100 register variables can be declared as follows: . say one hundred.align 4 . // declare %r0. 5. nor are initializers permitted.const . Parameterized Variable Names Since PTX supports virtual registers. The default alignment for vector variables is to a multiple of the overall vector size.0. %r99. .0. Array variables cannot be declared this way.

PTX ISA Version 2. 2010 .0 40 January 24.

Instructions ld and st move data from/to addressable state spaces to/from registers. Predicate operands are denoted by the names p. Each operand type must be compatible with the type determined by the instruction template and instruction type.1.2. . the sizes of the operands must be consistent. and c. 6. Most instructions have an optional predicate guard that controls conditional execution. st. Instruction Operands 6. b. Source Operands The source operands are denoted in the instruction descriptions by the names a. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The cvt (convert) instruction takes a variety of operand types and sizes. and cvt instructions copy data from one location to another. 2010 41 .3. q. mov. so operands for ALU instructions must all be in variables declared in the . The ld. r. The result operand is a scalar or vector variable in the register state space. 6. as its job is to convert from nearly any data type to any other data type (and size). Integer types of a common size are compatible with each other. s. The mov instruction copies data between registers. The bit-size type is compatible with every type having the same size.Chapter 6. and a few instructions have additional predicate source operands. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. PTX describes a load-store machine. January 24. There is no automatic conversion between types.reg register state space. For most operations. Operand Type Information All operands in instructions have a known type from their declarations.

address registers. Load and store operations move data between registers and locations in addressable state spaces. All addresses and address computations are byte-based. 2010 .const. [V]. there is no support for C-style pointer arithmetic.reg . .reg .f32 W. ld.u32 42 January 24.4.f32 V. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.b32 p.u16 x. W. . Examples include pointer arithmetic and pointer comparisons.0 6.[x].s32 q.gloal. and immediate address expressions which evaluate at compile-time to a constant address.u16 ld.v4 .v4. Address expressions include variable names.u16 r0. 6. and vectors.s32 mov. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.4.PTX ISA Version 2.shared. Using Addresses. [tbl+12].shared . address register plus byte offset. .s32 tbl[256].1.reg . q. The address is an offset in the state space in which the variable is declared. The interesting capabilities begin with addresses. and Vectors Using scalar variables as operands is straightforward. tbl.reg . . Arrays. arrays. p.f32 ld. . r0. Here are a few examples: .const . .global .v4 . The mov instruction can be used to move the address of a variable into a pointer. The syntax is similar to that used in many assembly languages.

Elements in a brace-enclosed vector. as well as the typical color fields . for use in an indirect branch or call. If more complicated indexing is desired. . . Vectors may also be passed as arguments to called functions. Vector elements can be extracted from the vector with the suffixes .f32 ld.v4. Here are examples: ld. .u32 s. Vector loads and stores can be used to implement wide loads and stores.global. Vectors as Operands Vector operands are supported by a limited subset of instructions.g V.v4.b.b V.4. The registers in the load/store operations can be a vector.g. The expression within square brackets is either a constant integer.y. A brace-enclosed list is used for pattern matching to pull apart vectors.d}.y V.z and . .a 6.x.c. mov. ld.r V. [addr+offset].4.u32 s. The size of the array is a constant in the program. b. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.4. mov.w = = = = V.b and . d. or a braceenclosed list of similarly typed scalars. Array elements can be accessed using an explicitly calculated byte address. Instruction Operands 6. a[0]. and in move instructions to get the address of the label or function into a register. c. a[1].u32 {a.r. V.global.3.x V.d}. Rc.c. which may improve memory performance. or by indexing into the array using square-bracket notation. Arrays as Operands Arrays of all types can be declared. // move address of a[1] into s 6. say {Ra. a[N-1]. 2010 43 .Chapter 6. Examples are ld. which include mov. .global. V2. Rd}.global.f32 V. where the offset is a constant expression that is either added or subtracted from a register variable.b. .v4 . ld. or a simple “register with constant offset” expression.reg . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. st. and the identifier becomes an address constant in the space where the array is declared.w. Rb. a register variable. it must be written as an address calculation prior to use.4.a.f32 {a.reg .2.v2. [addr+offset2]. January 24.u32 s. and tex.f32 a.z V.

if a cvt. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. Type Conversion All operands to all arithmetic. the u16 is zero-extended to s32. 6. and ~131.0 6. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. and data movement instruction must be of the same type and size.u16 instruction is given a u16 source operand and s32 as a destination operand. except for operations where changing the size and/or type is part of the definition of the instruction. 44 January 24. 2010 . For example.5.s32.1. logic.5.PTX ISA Version 2. Operands of different sizes or types must be converted prior to the operation.000 for f16).

u32 targeting a 32-bit register will first chop to 16-bits.Chapter 6. 2010 45 . f2s = float-to-signed. January 24. the result is extended to the destination register width after chopping. zext = zero-extend. For example. Notes 1 If the destination register is wider than the destination format. chop = keep only low bits that fit. s2f = signed-to-float. f2f = float-to-float.s16. Instruction Operands Table 11. cvt. The type of extension (sign or zero) is based on the destination format. f2u = float-to-unsigned. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. then sign-extend to 32-bits. u2f = unsigned-to-float.

5. 2010 . The following tables summarize the rounding modifiers. Modifier .0 6. there are four integer rounding modifiers and four floating-point rounding modifiers.rzi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rmi .PTX ISA Version 2. choosing even integer if source is equidistant between two integers.rz . Rounding Modifiers Conversion instructions may specify a rounding modifier.rm . Table 12.rpi Integer Rounding Modifiers Description round to nearest integer. In PTX. Modifier .rn .2.rni .

Chapter 6. The register in a store operation is available much more quickly. Table 11 gives estimates of the costs of using different kinds of memory. Much of the delay to memory can be hidden in a number of ways. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. first access is high Notes January 24. Registers are fastest. 2010 47 . as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Instruction Operands 6.6. Another way to hide latency is to issue the load instructions as early as possible. while global memory is slowest. Table 14. Operand Costs Operands from different state spaces affect the speed of an operation.

0 48 January 24.PTX ISA Version 2. 2010 .

1. and an optional list of input parameters. parameter passing. together these specify the function’s interface. NOTE: The current version of PTX does not implement the underlying. support for variadic functions (“varargs”).Chapter 7. function calls. 2010 49 . Function declarations and definitions In PTX. the function name. Execution of the ret instruction within foo transfers control to the instruction following the call. or prototype. implicitly saving the return address. A function must be declared or defined prior to being called. A function definition specifies both the interface and the body of the function. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. execution of the call instruction transfers control to foo.func foo { … ret. and is represented in PTX as follows: . 7. Scalar and vector base-type input and return parameters may be represented simply as register variables. These include syntax for function definitions.func directive. January 24. and Application Binary Interface (ABI). A function declaration specifies an optional list of return parameters. } … call foo. The simplest function has no parameters or return values. arguments may be register variables or constants. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. At the call. so recursion is not yet supported. functions are declared and defined using the . we describe the features of PTX needed to achieve this hiding of the ABI. stack layout. and memory allocated on the stack (“alloca”). In this section. … Here. and return values may be placed directly into register variables. Abstracting the ABI Rather than expose details of a particular calling convention. stack-based ABI.

b8 [py+11]. st.func (.param.param space variables are used in two ways. byte array in . For example. c3.PTX ISA Version 2. Since memory accesses are required to be aligned to a multiple of the access size.c4.u32 %res) inc_ptr ( . Second. ld.s32 x. %rc2.param. 2010 .s32 out) bar (. 50 January 24. . (%r1. ret.c3.param.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. … In this example. %rd.u32 %ptr. ld.c1. c2. %inc. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param state space is used to pass the structure by value: . passed by value to a function: struct { double dbl. … … // computation using x. st. .b8 c1. %rc1. inc_ptr.reg . First.reg .b8 [py+10].param . [y+0].param. The . }.param.f64 f1. … st.param.b8 c3.0 Example: .f1.f64 f1. ld.param space call (%out). a . (%x. consider the following C structure.reg .b8 . a . ld.param space memory.b8 [py+ 9].b8 [py+ 8]. [y+10].reg space.param. note that . st. // scalar args in .b64 [py+ 0]. .align 8 y[12]) { . %rc1. [y+11]. char c[4]. In PTX.param.param. %rc2.b32 c1. … ld.reg . } { . [y+9].u32 %inc ) { add.b8 c2.align 8 py[12].4). [y+8].reg . c4.f64 field are aligned.param .func (. st. %ptr. this structure will be flattened into a byte array.b8 c4.b8 .param. py). } … call (%r1).c2. bumpptr.param variable y is used in function definition bar to represent a formal parameter.reg .reg .u32 %res. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .

param and ld. For a caller.param instructions used for argument passing must be contained in the basic block with the call instruction. The .param state space use in device functions.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param byte array is used to collect together fields of a structure being passed by value. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. or a constant that can be represented in the type of the formal parameter. 2. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.Chapter 7. • • • For a callee. size.param arguments. Note that the choice of .param or .param memory must be aligned to a multiple of 1. January 24. • The .param variables. or 16 bytes.reg space variable with matching type and size. This enables backend optimization and ensures that the . For a callee.param space byte array with matching type.param or . • The . 4. In the case of . all st. the corresponding argument may be either a . In the case of .reg variables. 8.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg or .reg space variable of matching type and size. Parameters in .param variables or .reg state space can be used to receive and return base-type scalar and vector values. Supporting the . In the case of . The following restrictions apply to parameter passing. and alignment.param space formal parameters that are byte arrays. the argument must also be a .. 2010 51 .reg state space in this way provides legacy support.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. For . For a caller. size. Abstracting the ABI The following is a conceptual way to think about the .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param state space is used to receive parameter values and/or pass return values back to the caller.param argument must be declared within the local scope of the caller. or a constant that can be represented in the type of the formal parameter.reg space formal parameters. A .reg variables. • • Arguments may be . the corresponding argument may be either a . The . Typically. . a .g. or constants. and alignment of parameters. • • • Input and return parameters may be .param space formal parameters that are base-type scalar or vector variables.

Changes from PTX 1.0 7.PTX ISA Version 2. and there was no support for array parameters.reg state space.x supports multiple return values for this purpose.param space parameters support arrays.param byte array should be used to return objects that do not fit into a register. PTX 2. In PTX ISA version 2. PTX 1. Objects such as C structures were flattened and passed or returned using multiple registers.1.1.reg or . formal parameters may be in either .x.x In PTX ISA version 1. 52 January 24. PTX 2. formal parameters were restricted to . and .0 restricts functions to a single return value.param state space. and a . For sm_2x targets. 2010 .0.0 continues to support multiple return registers for sm_1x targets.

// default to MININT mov.func %va_end (. Variadic functions NOTE: The current version of PTX does not support variadic functions. This handle is then passed to the %va_arg and %va_arg64 built-in functions. PTX provides a high-level mechanism similar to the one provided by the stdarg.func baz ( . iteratively access. setp. mov. In both cases. call (val).u32 N. %va_end is called to free the variable argument list handle. or 4 bytes.reg . . 4. for %va_arg64.. (ap). %va_start. the size may be 1. or 8 bytes.s32 result ) maxN ( . (2.ge p. variadic functions are declared with an ellipsis at the end of the input parameter list.u32 ptr. … call (%max). %r2. 4.s32 result. To support functions with a variable number of arguments. .reg . .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 align) . 8.reg .s32 val. 0x8000000.reg . N. (ap.reg .reg .u32 a.b32 val) %va_arg (. following zero or more fixed parameters: . … %va_start returns Loop: @p Done: January 24.u32 ap.h headers in C. } … call (%max).h and varargs.reg .func (.reg . 2010 53 . 2. maxN. bra Done.reg .u32 ptr. Once all arguments have been processed.u32 b.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .b64 val) %va_arg64 (.u32 sz.reg .u32 align) .2. val. ) { .func okay ( … ) Built-in functions are provided to initialize. call (ap).reg . Abstracting the ABI 7. 4). bra Loop. The function prototypes are defined as follows: . For %va_arg. 2. .reg . along with the size and alignment of the next data value to be accessed. max. and end access to a list of variable arguments. %r1. .. %r3).Chapter 7. ctr. ret. ctr. or 16 bytes. result. %va_arg.reg . … ) .b32 result.b32 ctr. maxN.reg .func (.pred p. (3.u32 ptr) %va_start .func (.u32. In PTX.func ( . . .u32 sz.reg .reg . 2. the size may be 1. call %va_end. %s2). %s1. 0. the alignment may be 1. 4. .

54 January 24.0 7. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.local and st.u32 ptr ) %alloca ( .reg . If a particular alignment is required. Alloca NOTE: The current version of PTX does not support alloca. To allocate memory. The array is then accessed with ld.3.local instructions.PTX ISA Version 2. 2010 .func ( .reg . defined as follows: . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. a function simply calls the built-in function %alloca.

8. b. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. followed by some examples that attempt to show several possible instantiations of the instruction.Chapter 8. We use a ‘|’ symbol to separate multiple destination registers. 2010 55 . plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. C. // p = (a < b). In addition to the name and the format of the instruction. For instructions that create a result value. opcode D. the D operand is the destination operand.s32. January 24. A. and C are the source operands. PTX Instructions PTX instructions generally have from zero to four operands.2. setp. The setp instruction writes two destination registers. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. A.1. opcode A. For some instructions the destination operand is optional.lt p|q. q = !(a < b). opcode D. A. a. B. B. opcode D. the semantics are described. B. Instruction Set 8. while A.

3. 1.s32 p.lt. consider the high-level code if (i < n) j = j + 1. Instructions without a guard predicate are executed unconditionally. i. … // compare i to n // if false.s32 j. // p = (i < n) // if i < n. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.s32 j. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. add 1 to j To get a conditional branch or conditional function call. predicate registers can be declared as . j. 1. As an example. 2010 .pred p. This can be written in PTX as @p setp.lt. branch over 56 January 24. predicate registers are virtual and have . add. optionally negated. use a predicate to control the execution of the branch or call instructions. where p is a predicate variable. Predicates are most commonly set as the result of a comparison performed by the setp instruction. i.0 8. bra L1. So. add.s32 p. the following PTX instruction sequence might be used: @!p L1: setp. j.reg . n. q. n.PTX ISA Version 2. To implement the above example as a true conditional branch.pred as the type specifier. Predicated Execution In PTX.

Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.3.1.1. and bitsize types. gt. unsigned integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). The bit-size comparisons are eq and ne. Unsigned Integer. le (less-than-or-equal). The following table shows the operators for signed integer. the result is false.Chapter 8.1. ge. 2010 57 . lt.2. and hs (higher-or-same). The unsigned comparisons are eq. Table 15. lo (lower). hi (higher).1. gt (greater-than). lt (less-than). Comparisons 8. Table 16. ordering comparisons are not defined for bit-size types. ne (not-equal). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. ls (lower-or-same). Instruction Set 8.3.3. le. If either operand is NaN. ne. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. ne. and ge (greater-than-or-equal).

xor. and mov. unordered versions are included: equ.0. Table 18. num returns true if both operands are numeric values (not NaN).0 To aid comparison operations in the presence of NaN values.u32 %r1.%p. setp can be used to generate a predicate from an integer. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. However. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. for example: selp. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. If both operands are numeric values (not NaN).PTX ISA Version 2. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.2.3. then the result of these comparisons is true. leu. There is no direct conversion between predicates and integer values. ltu. gtu. or. geu. 2010 . not.1. two operators num (numeric) and nan (isNaN) are provided. and nan returns true if either operand is NaN. Table 17. If either operand is NaN. // convert predicate to 32-bit value 58 January 24. and no direct way to load or store predicate register values. then these comparisons have the same result as their ordered counterparts. neu.

It requires separate type-size modifiers for the result and source. the add instruction requires type and size information to properly perform the addition operation (signed. and integer operands are silently cast to the instruction type if needed.bX . • The following table summarizes these type checking rules. add.fX ok inv inv ok Instruction Type .Chapter 8.e. For example. Floating-point types agree only if they have the same size.u16 d.bX .reg .f32 d. they must match exactly. Example: .u16 d.reg . most notably the data conversion instruction cvt.sX . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. i. cvt. 2010 59 .u16 a. a.. and these are placed in the same order as the operands. a. a.fX ok ok ok ok January 24. Table 19.sX ok ok ok inv . .uX ok ok ok inv . Instruction Set 8. different sizes).reg . For example.4.uX . float. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. For example: . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.u16 d. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. b.f32. unsigned. Signed and unsigned integer types agree provided they have the same size. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. and this information must be specified as a suffix to the opcode. Type Checking Rules Operand Type . b.

Operand Size Exceeding Instruction-Type Size For convenience. for example.0 8. 60 January 24. Note that some combinations may still be invalid for a particular instruction. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Table 20. Floating-point source registers can only be used with bit-size or floating-point instruction types. or converted to other types and sizes. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. Bit-size source registers may be used with any appropriately-sized instruction type. “-“ = allowed. and converted using regular-width registers. the size must match exactly. The following table summarizes the relaxed type-checking rules for source operands. floating-point instruction types still require that the operand type-size matches exactly. st. Notes 3.1. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. unless the operand is of bit-size type. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. so those rows are invalid for cvt. For example. 4. The data is truncated to the instruction-type size and interpreted according to the instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.PTX ISA Version 2. the data will be truncated. 2. Source register size must be of equal or greater size than the instruction-type size. 2010 . parse error. inv = invalid. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. 1. the cvt instruction does not support . When used with a floating-point instruction type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types.4. stored. When used with a narrower bit-size type. no conversion needed. so that narrow values may be loaded. ld.bX instruction types. When a source operand has a size that exceeds the instruction-type size. stored.

2. The data is sign-extended to the destination register width for signed integer instruction types. inv = Invalid. the data will be zero-extended. Table 21. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. zext = zero-extend. the data is zeroextended. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. The following table summarizes the relaxed type-checking rules for destination operands. otherwise. parse error. If the corresponding instruction type is signed integer. Bit-size destination registers may be used with any appropriately-sized instruction type. Destination register size must be of equal or greater size than the instruction-type size. the data is sign-extended. 1. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. and is zero-extended to the destination register width otherwise. “-“ = Allowed but no conversion needed. January 24. When used with a floatingpoint instruction type. Notes 3.or sign-extended to the size of the destination register.Chapter 8. The data is signextended to the destination register width for signed integer instruction types. the destination data is zero. 2010 61 . 4. When used with a narrower bit-size instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the size must match exactly.

using the . 2010 . 8. If all of the threads act in unison and follow a single control flow path. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path.0 8. the optimizing code generator automatically determines points of re-convergence. and for many applications the difference in execution is preferable to limiting performance. 8. If threads execute down different control flow paths. or conditional return. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. These extra precision bits can become visible at the application level. until C is not expressive enough.PTX ISA Version 2. for example.5. the semantics of 16-bit instructions in PTX is machine-specific. conditional function call.1. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. so it is important to have divergent threads re-converge as soon as possible. Divergence of Threads in Control Constructs Threads in a CTA execute together. When executing on a 32-bit data path. for many performance-critical applications. A compiler or programmer may chose to enforce portable. However. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. a compiler or code author targeting PTX can ignore the issue of divergent threads. the threads are called uniform. For divergent control flow. At the PTX language level. 16-bit registers in PTX are mapped to 32-bit physical registers. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.6. the threads are called divergent. and 16-bit computations are “promoted” to 32-bit computations. The semantics are described using C.6. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. by a right-shift instruction.uni suffix. 62 January 24. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. at least in appearance. Both situations occur often in programs. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. this is not desirable. Therefore. until they come to a conditional control construct such as a conditional branch. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine.

cc.Chapter 8. addc sub. 8.1. Instructions All PTX instructions may be predicated. the optional guard predicate is omitted from the syntax. 2010 63 . Instruction Set 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. In the following descriptions. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7.cc. The Integer arithmetic instructions are: add sub add.7.

u32. Supported on all target architectures.type = { .sat applies only to .type = { . d = a + b. a. Introduced in PTX ISA version 1.sat limits result to MININT. b.type sub{.sat}.c.s32 .0.s32 c.u64.s32 type. .s32 d. .sat}.s16.1. // . sub. PTX ISA Notes Target ISA Notes Examples 64 January 24. d. d. sub.sat limits result to MININT. .s32. .u32 x.s64 }. add.u64.s32.type add{.PTX ISA Version 2. PTX ISA Notes Target ISA Notes Examples Table 23. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another..s64 }.. Applies only to .MAXINT (no overflow) for the size of the operation. 2010 .sat applies only to . b.0. .u32. add. Introduced in PTX ISA version 1. Applies only to .a. .s32 . .0 Table 22. Supported on all target architectures.z. .s32 d. b. . Saturation modifier: .y. @p add.s16.s32 type. a. Description Semantics Notes Performs addition and writes the resulting value into a destination register. // . add Syntax Integer Arithmetic Instructions: add Add two values. d = a – b.u16.s32 c. Saturation modifier: . b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. a.sat. a.u16.MAXINT (no overflow) for the size of the operation.b. .

cc}.z2. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc. addc{. . clearing.2. No saturation. d = a + b + CC. Introduced in PTX ISA version 1.y2.type d. .CF No integer rounding modifiers.u32. b. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. @p @p @p @p add.cc.CF) holding carry-in/carry-out or borrowin/borrow-out. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.CF No integer rounding modifiers.cc. x2. Introduced in PTX ISA version 1.cc Syntax Integer Arithmetic Instructions: add. a. Behavior is the same for unsigned and signed integers. x3. Table 24.cc. add. carry-out written to CC. or testing the condition code.z3. if .z2.y4.z4.z4.cc. Behavior is the same for unsigned and signed integers.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. b. . // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. a.cc.y3. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.b32 addc.cc. Instruction Set Instructions add.z1.2. No saturation.CF. Supported on all target architectures. x2.cc. d = a + b. add.cc Add two values with carry-out.type = {.z1. and there is no support for setting.u32.cc.s32 }.y1.b32 addc.b32 addc.y3.b32 addc. @p @p @p @p add. No other instructions access the condition code. addc.y4. x3.b32 x1.Chapter 8. Supported on all target architectures. 2010 65 .type = { .b32 addc. .s32 }. These instructions support extended-precision integer addition and subtraction.b32 x1.z3. sub.y1.cc.y2. carry-out written to CC.b32 addc.cc specified. x4. x4.type d.

y1. .PTX ISA Version 2. if . Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. borrow-out written to CC.z3. x4. No saturation. @p @p @p @p sub.y1.(b + CC.type = { .b32 subc.cc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. x3.b32 subc.y4. . subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. @p @p @p @p sub. x4. No saturation. d = a – b. borrow-out written to CC. .cc.u32. x2.type d.CF).y3. subc{. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.0 Table 26.z4.cc. Supported on all target architectures.type = {.u32. Supported on all target architectures.cc Syntax Integer Arithmetic Instructions: sub. withborrow-in and optional borrow-out.CF No integer rounding modifiers.cc specified.3.b32 subc.b32 subc.y4. with borrow-out. b.cc}.b32 x1.z1.cc.z2. d = a . sub. a. Introduced in PTX ISA version 1.z1.s32 }. sub. x2.3.s32 }.cc. Introduced in PTX ISA version 1.cc.b32 x1.cc Subract one value from another. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.b32 subc.y2.z4. b. Behavior is the same for unsigned and signed integers. Behavior is the same for unsigned and signed integers.z2.CF No integer rounding modifiers.z3.b32 subc.y2. a. x3.y3.cc. 2010 .type d. .cc.cc.

a. The .fys. n = bitwidth of type. .u32.fxs. save only the low 16 bits // 32*32 bits.wide // for . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.. then d is the same size as a and b.s16. Description Semantics Compute the product of two values.wide suffix is supported only for 16.fxs.u64. d = t<n-1.y. t = a * b.type = { .type d..s16 fa. // for .0>.Chapter 8. 2010 67 . mul.wide is specified. then d is twice as wide as a and b to receive the full result of the multiplication. mul..s32 z. If .0.and 32-bit integer types.wide. // 16*16 bits yields 32 bits // 16*16 bits.hi. Instruction Set Table 28. b.s32.hi or .lo.lo variant Notes The type of the operation represents the types of the a and b operands.hi variant // for . . . ..lo. If .s16 fa. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.x. . d = t<2n-1.s64 }.fys. mul{.lo is specified. Supported on all target architectures. and either the upper or lower half of the result is written to the destination register.wide}. mul.wide.n>.u16. d = t. creates 64 bit result January 24. .

b.0. mad{. Saturation modifier: .wide is specified.u64.and 32-bit integer types. t<2n-1. and then writes the resulting value into a destination register.s32 type in ..wide // for .b. t + c.wide suffix is supported only for 16. @p mad.sat limits result to MININT. Supported on all target architectures.s32 r.lo.wide}.MAXINT (no overflow) for the size of the operation.sat.hi or . t<n-1. .. d.type = { .s16. .hi..0> + c.type mad. // for . The .a. c. .u32. .q. Description Semantics Multiplies two values and adds a third. then d and c are the same size as a and b.r.s32 d.s64 }. b. . 68 January 24. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.lo variant Notes The type of the operation represents the types of the a and b operands.p.s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.c. Applies only to .0 Table 29. mad.. t n d d d = = = = = a * b.hi variant // for . If .PTX ISA Version 2. and either the upper or lower half of the result is written to the destination register. 2010 .hi.lo.lo. c. a.n> + c. a.hi mode. If . bitwidth of type. then d and c are twice as wide as a and b to receive the result of the multiplication.u16.lo is specified.. .s32.

hi. and return either the high or low 32-bits of the 48-bit result.s32 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.. i.u32. t = a * b. mul24.lo. . d = t<47.. All operands are of the same type and size.hi may be less efficient on machines without hardware support for 24-bit multiply.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. mul24.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.s32 d.0.a. b. // low 32-bits of 24x24-bit signed multiply. a. d = t<31. mul24{. January 24. 48bits. mul24.b.type d.. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.hi variant // for . 2010 69 . // for . .Chapter 8.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.e.type = { .lo}. Supported on all target architectures.0>.16>. Instruction Set Table 30. mul24. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.

c.hi variant // for . i.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. d = t<47. and add a third.lo}. 2010 . b. Saturation modifier: . 32-bit value to either the high or low 32-bits of the 48-bit result.hi.s32 }.sat limits result of 32-bit signed addition to MININT.lo.0> + c. All operands are of the same type and size.c.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. // low 32-bits of 24x24-bit signed multiply.hi mode.sat. mad24..hi may be less efficient on machines without hardware support for 24-bit multiply..PTX ISA Version 2.. Applies only to .0 Table 31.hi. b. // for . . 48bits. mad24.s32 d.16> + c. mad24. d. Return either the high or low 32-bits of the 48-bit result. c.u32.s32 d.a.0.type = { .type mad24. a. mad24{. . 70 January 24.e. Description Compute the product of two 24-bit integer values held in 32-bit source registers.b.MAXINT (no overflow). Supported on all target architectures.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. d = t<31.. t = a * b.s32 type in . mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

January 24, 2010

71

PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

72

January 24, 2010

Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

January 24, 2010

73

popc. popc Syntax Integer Arithmetic Instructions: popc Population count.u32 Semantics 74 January 24. } while (d < max && (a&mask == 0) ) { d++. a = a << 1. inclusively. mask = 0x80000000.b64 type.0.type == . .b64 d.0 Table 39. the number of leading zeros is between 0 and 64. d = 0. mask = 0x8000000000000000. a. X. popc requires sm_20 or later. a = a >> 1. cnt. } Introduced in PTX ISA version 2. if (. while (a != 0) { if (a&0x1) d++.b32 clz. the number of leading zeros is between 0 and 32. // cnt is .u32 PTX ISA Notes Target ISA Notes Examples Table 40.b64 d. } else { max = 64. For . clz requires sm_20 or later.b64 }.0.type = { .b64 }. 2010 . popc. inclusively.type d. . .type d.PTX ISA Version 2. // cnt is . Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b32) { max = 32.b32 type. a. d = 0. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. For . X. cnt.type = { . a. clz. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.b32 popc.b32. . a.b32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz.

a. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.s64 }.u32 d.u32 || . i--) { if (a & (1<<i)) { d = i. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.shiftamt. For unsigned integers.s32.shiftamt && d != -1) { d = msb .Chapter 8. .type==. . bfind. 2010 75 . a.s64 cnt. If . X. Operand a has the instruction type. bfind. break. d = -1.type = { .u32 January 24. bfind returns 0xFFFFFFFF if no non-sign bit is found. Semantics msb = (.u32. bfind requires sm_20 or later.type d.type==. bfind returns the bit position of the most significant “1”. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.type bfind. for (i=msb. For signed integers. .s32) ? 31 : 63.d. .0. and operand d has type . Description Find the bit position of the most significant non-sign bit in a and place the result in d.shiftamt is specified. bfind.shiftamt. } } if (. i>=0. Instruction Set Table 41. // cnt is .u32.u64. d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a.

0 Table 42.type = { . for (i=0. a.b32. 76 January 24. brev. 2010 . a. i++) { d[i] = a[msb-i].b32 d. .type==.type d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.PTX ISA Version 2. brev requires sm_20 or later. .0.b32) ? 31 : 63. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.b64 }. Description Semantics Perform bitwise reversal of input. i<=msb. brev. msb = (.

i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. Operands a and d have the same type as the instruction type.u32.a. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. a.u64. the result is zero. len = c. If the start position is beyond the msb of the input.type d.u64 || len==0) sbit = 0. bfe requires sm_20 or later. January 24. 2010 77 .Chapter 8.b32 d. otherwise If the bit field length is zero.0. i<=msb.type = { . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfe. . Description Extract bit field from a and place the zero or sign-extended result in d.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.len. Instruction Set Table 43. The destination d is padded with the sign bit of the extracted field. and operands b and c are type .msb)].u32. pos = b. .type==. Source b gives the bit field starting bit position.s32. the destination d is filled with the replicated sign bit of the extracted field. c.s32. .type==.type==.u32 || . if (. d = 0.type==. else sbit = a[min(pos+len-1.s64 }. and source c gives the bit field length in bits. bfe. The sign bit of the extracted field is defined as: . b.start. for (i=0.u64: .u32.s32) ? 31 : 63.u32 || . . . . Semantics msb = (.

bfi.0. len = d. for (i=0. and operands c and d are type .b32 d. . Operands a.u32. 2010 . b. .b32. Description Align and insert a bit field from a into b.a. the result is b. the result is b. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.b.type = { . i++) { f[pos+i] = a[i]. If the bit field length is zero.len. 78 January 24.b32) ? 31 : 63. Semantics msb = (.PTX ISA Version 2.type f.b64 }. and place the result in f. and source d gives the bit field length in bits. bfi. pos = c. Source c gives the starting bit position for the insertion. If the start position is beyond the msb of the input. i<len && pos+i<=msb. d. a. f = b. and f have the same type as the instruction type. b.start. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfi requires sm_20 or later. c.type==.0 Table 44.

the four 4-bit values fully specify an arbitrary byte permute. The bytes in the two source registers are numbered from 0 to 7: {b. For each byte in the target register.ecl. b2.Chapter 8. as a 16b permute code.rc16 }.rc8.mode} d.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. . . Instruction Set Table 45.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. . b4}.ecr. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. a} = {{b7.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. a 4-bit selection value is defined. b1.b32{.b1 source select c[7:4] d. 2010 79 . b5. {b3. msb=1 means replicate the sign. In the generic form (no mode specified).b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. The msb defines if the byte value should be copied.mode = { . and reassemble them into a 32-bit destination register. Note that the sign extension is only performed as part of generic form. . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). a. Description Pick four arbitrary bytes from two 32-bit registers. b0}}. .b4e.b2 source select c[11:8] d. b.b3 source select c[15:12] d. msb=0 means copy the literal value. Thus. the permute control consists of four 4-bit selection values.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. c.f4e. . b6. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. default mode index d. prmt.

// create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r4. ctl[3]. ctl[3] = (c >> 12) & 0xf. tmp64 ). tmp64 ). tmp[23:16] = ReadByte( mode. tmp[31:24] = ReadByte( mode. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. } tmp[07:00] = ReadByte( mode. r3.f4e r1. tmp64 ). ctl[0]. r1.PTX ISA Version 2. r2. ctl[2]. r4. 2010 . ctl[1] = (c >> 4) & 0xf.b32 prmt.0 Semantics tmp64 = (b<<32) | a. tmp64 ).0. r2. ctl[1]. prmt requires sm_20 or later. r3. 80 January 24. ctl[2] = (c >> 8) & 0xf.b32. tmp[15:08] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prmt.

2010 81 .2.f32 and . Floating-Point Instructions Floating-point instructions operate on .Chapter 8.7. Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values.

approx. If no rounding modifier is specified.f32 {add. Double-precision instructions support subnormal inputs and results.rnd.approx. sub. {add.target sm_20 .lg2. The optional . default is .rn .sqrt}. and mad support saturation of results to the range [0. but single-precision instructions return an unspecified NaN.sub.f32 {mad. Table 46.cos.rnd.approx.fma}. default is .f64 {sin. 82 January 24.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.rz .sub.f64 are the same.f32 {div. {mad.sqrt}.target sm_20 mad.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 rsqrt.0 The following table summarizes floating-point instructions in PTX.0. so PTX programs should not rely on the specific single-precision NaNs being generated.rcp. with NaNs being flushed to positive zero.f32 {div.0]. .max}.f64 mad.target sm_1x No rounding modifier. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.fma}. 2010 .neg.rnd.f32 {abs.f32 {div.max}.rn and instructions may be folded into a multiply-add.mul}.f64 and fma.sqrt}.rnd.f32 .rn and instructions may be folded into a multiply-add.full. Instruction Summary of Floating-Point Instructions .rm . NaN payloads are supported for double-precision instructions. Single-precision add.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.neg.sat Notes If no rounding modifier is specified. 1. No rounding modifier.min.rnd.rp .mul}. mul.min.PTX ISA Version 2.ftz .rnd.32 and fma.f64 {abs.ex2}. .f32 are the same.approx.f64 rsqrt. Note that future implementations may support NaN payloads for single-precision instructions.rcp.rcp.f64 div.

infinite.pred = { . true if the input is a subnormal number (not NaN.number testp.type = { . Instruction Set Table 47. X.notanumber.f64 }. A. C. testp Syntax Floating-Point Instructions: testp Test floating-point property. and return the result as d.normal.op.finite.notanumber. a. positive and negative zero are considered normal numbers.f32. f0. z.infinite testp. .Chapter 8.0.finite testp. . Table 48. testp requires sm_20 or later.type = { .normal testp. copysign. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. testp.subnormal }.f64 }. . .op p. .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. // result is . Introduced in PTX ISA version 2. . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.f32 copysign. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.notanumber testp.infinite. January 24. not infinity).f64 x. testp.type . .number. copysign requires sm_20 or later. testp. a. . . B.f32.0. copysign.f32 testp. p. not infinity) As a special case. 2010 83 .type d. b.f64 isnan. y.

rnd}{.rp }.0 Table 49. d = a + b. Saturation modifier: . Description Semantics Notes Performs addition and writes the resulting value into a destination register.rn mantissa LSB rounds to nearest even . . . add.rm.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0.f32 supported on all target architectures. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 1.0f. b.ftz}{.f32 add{. subnormal numbers are supported. requires sm_20 Examples @p add.rnd}. add{.rz mantissa LSB rounds towards zero .f64 supports subnormal numbers. In particular. a. .sat}. d.f32 flushes subnormal inputs and results to sign-preserving zero. Rounding modifiers (default is . 84 January 24. Rounding modifiers have the following target requirements: .rz.f32 f1. 2010 .rp for add. add. . add.f64 d. . sm_1x: add.sat.PTX ISA Version 2. a. add.f3.rn.f64. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0.rm.rn. requires sm_13 for add.rnd = { . add.f32. NaN results are flushed to +0. .ftz.rn): .f32 flushes subnormal inputs and results to sign-preserving zero. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.rz.rz available for all targets . b.0].f32 clamps the result to [0.f2.ftz. add Syntax Floating-Point Instructions: add Add two values.f64 requires sm_13 or later.

rm.rz mantissa LSB rounds towards zero .rn): . January 24. b. NaN results are flushed to +0.0. sub{. subnormal numbers are supported. requires sm_20 Examples sub.f64 d.b. a.rnd}{.sat.rz.sat}.ftz}{.rm. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. . .rn. 2010 85 . 1.rnd = { . Rounding modifiers have the following target requirements: . . sub. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0]. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f2.f32.rm mantissa LSB rounds towards negative infinity . d. sub.f32 sub{.f32 c.rn. Saturation modifier: sub.rn.0f. Rounding modifiers (default is .f3.b.f32 f1.f32 supported on all target architectures. sub.a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub. sm_1x: sub.rnd}. sub Syntax Floating-Point Instructions: sub Subtract one value from another. sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 flushes subnormal inputs and results to sign-preserving zero. b.f32 clamps the result to [0.ftz.Chapter 8. .rp }. .ftz.f64 requires sm_13 or later. In particular. a.0. requires sm_13 for sub.rz available for all targets . Instruction Set Table 50.rp for sub.rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. d = a .

rz. mul.0]. mul{. . mul.f64 d. . a. mul.f32 clamps the result to [0. d = a * b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. For floating-point multiplication. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. b. Description Semantics Notes Compute the product of two values.f32 flushes subnormal inputs and results to sign-preserving zero.f64. In particular.0 Table 51. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn mantissa LSB rounds to nearest even . .radius.sat. mul.rn.f32 mul{. subnormal numbers are supported.rp for mul.pi // a single-precision multiply 86 January 24. . .rm. a.rm.ftz.rz available for all targets .rnd}.0. Rounding modifiers (default is .rp }. d. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.f32 circumf.rn): .rn.f32.ftz}{. mul Syntax Floating-Point Instructions: mul Multiply two values.f32 flushes subnormal inputs and results to sign-preserving zero.sat}. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.ftz.0f. sm_1x: mul. 1.rm mantissa LSB rounds towards negative infinity . Saturation modifier: mul. . Rounding modifiers have the following target requirements: .rnd}{. b.0.f32 supported on all target architectures. 2010 .rnd = { . requires sm_20 Examples mul.PTX ISA Version 2.f64 supports subnormal numbers. all operands must be the same size.rz mantissa LSB rounds towards zero . NaN results are flushed to +0. requires sm_13 for mul.f64 requires sm_13 or later.

d = a*b + c.rn. Instruction Set Table 52.rn. Saturation: fma.f64 is the same as mad.ftz. subnormal numbers are supported. fma.rp }. NaN results are flushed to +0. fma. 1. c.Chapter 8.rz mantissa LSB rounds towards zero .f64 requires sm_13 or later.rm.f32 clamps the result to [0.f32 introduced in PTX ISA version 2. 2010 87 . fma. The resulting value is then rounded to single precision using the rounding mode specified by .x. .rnd = { .f32 is unimplemented in sm_1x. PTX ISA Notes Target ISA Notes Examples January 24.f32 fma.c.ftz.z.rn. .f32 fma.0].ftz}{. d.a. fma.f32 flushes subnormal inputs and results to sign-preserving zero. d.f64 supports subnormal numbers.rnd. .sat}.rnd{.f64 w. fma. again in infinite precision.f64 introduced in PTX ISA version 1. fma.sat. fma.y.0f.rm mantissa LSB rounds towards negative infinity .rn mantissa LSB rounds to nearest even .rnd. Rounding modifiers (no default): .0.f64 d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 computes the product of a and b to infinite precision and then adds c to this product. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rnd. b.0.f32 requires sm_20 or later. sm_1x: fma. a.4. b. fma. a.b.rz. fma. again in infinite precision. @p fma.f64 computes the product of a and b to infinite precision and then adds c to this product. The resulting value is then rounded to double precision using the rounding mode specified by . fma.f64. fma Syntax Floating-Point Instructions: fma Fused multiply-add. c. .

0 devices. b.f32 flushes subnormal inputs and results to sign-preserving zero. NaN results are flushed to +0.f32 mad. mad.f32). and then writes the resulting value into a destination register.f32 mad.f32 flushes subnormal inputs and results to sign-preserving zero. d = a*b + c. again in infinite precision. mad. Unlike mad. a.f32. The resulting value is then rounded to single precision using the rounding mode specified by .sat. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f32 is when c = +/-0. a.rnd.ftz}{.PTX ISA Version 2. b.{f32.ftz}{.target sm_20 d. mad. c.sat}. but the exponent is preserved. c. where the mantissa can be rounded and the exponent will be clamped. c. a. mad.{f32. Note that this is different from computing the product with mul. again in infinite precision. mad.0.rz. Description Semantics Notes Multiplies two values and adds a third. mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn. 2010 .rm. In this case.f64. 1.rnd.rnd.0].ftz. The resulting value is then rounded to double precision using the rounding mode specified by .rn mantissa LSB rounds to nearest even . // . When JIT-compiled for SM 2.rnd.target sm_13 and later . b. sm_1x: mad.f64 d.f64} is the same as fma.f64 supports subnormal numbers.rm mantissa LSB rounds towards negative infinity .f64}. // .f32 clamps the result to [0. mad. .f64 is the same as fma.f32 computes the product of a and b to infinite precision and then adds c to this product. again in infinite precision. and then the mantissa is truncated to 23 bits.f32 is implemented as a fused multiply-add (i. .rn. .f32 computes the product of a and b at double precision..0.rnd = { . Saturation modifier: mad.rp }. For . mad.target sm_20: mad.e. For . // .f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.0 Table 53. mad. 88 January 24. subnormal numbers are supported. Rounding modifiers (no default): .0f.f64 computes the product of a and b to infinite precision and then adds c to this product. the treatment of subnormal inputs and output follows IEEE 754 standard.target sm_1x: mad.f64 computes the product of a and b to infinite precision and then adds c to this product. The resulting value is then rounded to double precision using the rounding mode specified by . fma. mad{.sat}.ftz.rz mantissa LSB rounds towards zero . The exception for mad.target sm_1x d.f32 is identical to the result computed using separate mul and add instructions.rnd{.

rm.rz.Chapter 8.a. January 24.f64 requires sm_13 or later. requires sm_20 Examples @p mad. mad. a rounding modifier is required for mad.rz.c. In PTX ISA versions 1..f64 instructions having no rounding modifier will map to mad.b.4 and later.rp for mad.f32 d.0. Target ISA Notes mad. 2010 89 .f64.f64.0 and later.f64.f32 supported on all target architectures. a rounding modifier is required for mad. Rounding modifiers have the following target requirements: .rn. requires sm_13 .. In PTX ISA versions 2..rp for mad....f32 for sm_20 targets.rm. Legacy mad.rn.f32.rn. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.

rn.f64 d. div. div.full.approx. div.f32 implements a relatively fast.f32 div.rm mantissa LSB rounds towards negative infinity . Explicit modifiers . Examples 90 January 24. yd.rm.f32 div. For b in [2-126. div Syntax Floating-Point Instructions: div Divide one value by another. div. PTX ISA Notes div.f32 div. . Subnormal inputs and results are flushed to sign-preserving zero.3. b. y. and rounding introduced in PTX ISA version 1.ftz.PTX ISA Version 2.full.rn.approx{. The maximum ulp error is 2 across the full range of inputs. .3. approximate single-precision divides: div.4 and later.approx.rnd{. but is not fully IEEE 754 compliant and does not support rounding modifiers.rp}.f32. b.circum. and div.full. zd.rnd.rnd. div.ftz.14159.f32 defaults to div. div.f64 requires sm_13 or later. approximate division by zero creates a value of infinity (with same sign as a).rz. div. subnormal numbers are supported. the maximum ulp error is 2.f32 implements a fast approximation to divide.approx. b.f64 diam. For PTX ISA version 1.ftz.rn. stores result in d.f64.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 div.rz mantissa LSB rounds towards zero .rnd is required.rp }. d. x. For PTX ISA versions 1. computed as d = a * (1/b). one of .rm.full{.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_20 or later. d.ftz}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn mantissa LSB rounds to nearest even . a.4. a. full-range approximation that scales operands to achieve better accuracy. or . .f32 and div.approx. Fast.f32 div.f32 requires sm_20 or later.full.0 Table 54.0. div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . z. // // // // fast. d.f32 and div.f64 introduced in PTX ISA version 1. Description Semantics Notes Divides a by b. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . Target ISA Notes div. d = a / b. .ftz}.f64 supports subnormal numbers. xd.rn.ftz.{rz.f32 supported on all target architectures.ftz. .full. . 2126]. b. a.0 through 1.ftz}.f64 defaults to div. Fast. sm_1x: div. 2010 .approx. div.approx.

Subnormal numbers: sm_20: By default. Table 56.ftz. d.f32 supported on all target architectures. abs{. abs. d = -a. d.0.f32 x. 2010 91 . neg.f0. abs. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. sm_1x: neg. a. neg{.f64 requires sm_13 or later. NaN inputs yield an unspecified NaN.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero. Take the absolute value of a and store the result in d. neg.f32 neg.ftz}. abs. NaN inputs yield an unspecified NaN.0. Instruction Set Table 55. January 24.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. neg.f32 flushes subnormal inputs and results to sign-preserving zero. neg. Subnormal numbers: sm_20: By default. a. subnormal numbers are supported.ftz. abs. a. neg.f64 supports subnormal numbers. d = |a|.f32 x. sm_1x: abs. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. subnormal numbers are supported. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. Negate the sign of a and store the result in d. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f0.f32 abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 d.f64 supports subnormal numbers.f32 supported on all target architectures.ftz.ftz.ftz}. abs.f64 d.f64 requires sm_13 or later.

max.f32 flushes subnormal inputs and results to sign-preserving zero.f64 z.f32 min. Store the minimum of a and b in d. 92 January 24. max. (a > b) ? a : b.f32 max.PTX ISA Version 2.f2. a.f32 max. b. max{. Table 58.x.c. @p min.ftz.b. d d d d = = = = NaN.f32 min. d d d d = = = = NaN. min.0.0 Table 57. a.f64 f0. (a < b) ? a : b. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.f64 supports subnormal numbers.f32 supported on all target architectures. max. sm_1x: max.ftz}. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.ftz.b.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 flushes subnormal inputs and results to sign-preserving zero. a. b. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. 2010 . a.f64 d. min. a.f64 requires sm_13 or later.ftz}. min.ftz. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. a. b.f64 d. max. subnormal numbers are supported. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f1. a. Store the maximum of a and b in d. sm_1x: min. d.f64 supports subnormal numbers. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. min.z.f32 flushes subnormal inputs and results to sign-preserving zero. d. b.0. max.ftz.f64 requires sm_13 or later. subnormal numbers are supported.c. min{.

f64 requires sm_13 or later.approx. rcp. rcp.ftz.f64 supports subnormal numbers.r.rnd.rm.approx. a.Chapter 8. one of .rz mantissa LSB rounds towards zero . // fast.f64 defaults to rcp.f32.rn.f32 supported on all target architectures.4 and later. d.rz. .rnd is required.0-2. rcp. For PTX ISA versions 1.approx{.0. rcp. rcp.approx.0 +subnormal +Inf NaN Result -0.x.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . a.0.rnd{. subnormal numbers are supported.rp}.approx.f32 flushes subnormal inputs and results to sign-preserving zero.rn. rcp.0 over the range 1.f32 rcp.f64 ri. General rounding modifiers were added in PTX ISA version 2.f32 rcp. The maximum absolute error is 2-23.ftz}. Description Semantics Notes Compute 1/a. 2010 93 .ftz. For PTX ISA version 1.rn. xi. .rn.rm.f32 implements a fast approximation to reciprocal.0 through 1. PTX ISA Notes rcp.f32 rcp. sm_1x: rcp. Input -Inf -subnormal -0.f32 flushes subnormal inputs and results to sign-preserving zero. d.ftz}.rn.0 +0.rn.rn mantissa LSB rounds to nearest even .approx and .ftz.0.f32 defaults to rcp. xi. d = 1 / a.rp }.3.rnd = { . rcp.x. store result in d. Examples January 24. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 requires sm_20 or later.f32 rcp. rcp. Target ISA Notes rcp.f64 d.f64 introduced in PTX ISA version 1. Instruction Set Table 59.ftz.0 -Inf -Inf +Inf +Inf +0.rnd.rm mantissa LSB rounds towards negative infinity . and rcp.f32 and rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. rcp.{rz. a.approx or . rcp. .f64 and explicit modifiers .f32 requires sm_20 or later.f64.ftz were introduced in PTX ISA version 1.4.

Description Semantics Notes Compute sqrt(a). sqrt.f64 r. Examples 94 January 24.f32 flushes subnormal inputs and results to sign-preserving zero.f32.rn mantissa LSB rounds to nearest even .3.0 -0.ftz.0 Table 60.rm.f32 sqrt. PTX ISA Notes sqrt. sqrt. and sqrt.f32 sqrt.approx or .0.rn.f32 sqrt.x.rz mantissa LSB rounds towards zero .f64 introduced in PTX ISA version 1. General rounding modifiers were added in PTX ISA version 2.rnd.{rz.f64 requires sm_13 or later.f32 is TBD. 2010 .rz.4.x.f32 sqrt.ftz.0 +0. sqrt. a.f32 defaults to sqrt.0 +0.rn.f32 implements a fast approximation to square root.f64 defaults to sqrt.rm.rp }.f32 and sqrt.rn. Input -Inf -normal -subnormal -0. The maximum absolute error for sqrt.approx.f64 d.ftz were introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { .rn.approx{. r.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}.approx.PTX ISA Version 2. // fast.ftz. .f64. approximate square root d.rnd is required.0 +0.x.f32 supported on all target architectures.0 +subnormal +Inf NaN Result NaN NaN -0. a. sm_1x: sqrt.ftz. sqrt. sqrt. .0. sqrt. For PTX ISA version 1.f32 requires sm_20 or later. sqrt. sqrt. sqrt.rm mantissa LSB rounds towards negative infinity .f64 and explicit modifiers . a.f64 requires sm_20 or later. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.ftz}.approx. r. sqrt. . store in d.rnd{.4 and later.approx.f64 supports subnormal numbers. For PTX ISA versions 1.rn. // IEEE 754 compliant rounding d. one of .approx and .approx. // IEEE 754 compliant rounding .rn.0 through 1.rnd.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . d = sqrt(a). Target ISA Notes sqrt. subnormal numbers are supported.rp}.

subnormal numbers are supported.4 over the range 1. Explicit modifiers .ftz were introduced in PTX ISA version 1. a. store the result in d.approx.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.approx. rsqrt. PTX ISA Notes rsqrt.approx.f32 rsqrt. d = 1/sqrt(a). Input -Inf -normal -subnormal -0.f64 is emulated in software and are relatively slow.ftz. rsqrt.0. Note that rsqrt. ISR.approx and .f32 supported on all target architectures.f64 defaults to rsqrt.0.f32 is 2-22.f32 rsqrt. Instruction Set Table 61.approx implements an approximation to the reciprocal square root.f32.ftz.f64 were introduced in PTX ISA version 1.approx. rsqrt. the .ftz}. a.f64 d.f64 requires sm_13 or later. The maximum absolute error for rsqrt. x. For PTX ISA version 1.0 through 1.f64 is TBD.approx{.approx.3.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. d. X. rsqrt. Compute 1/sqrt(a).0-4. sm_1x: rsqrt. For PTX ISA versions 1.f64.approx modifier is required. rsqrt.ftz.f32 defaults to rsqrt.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero. and rsqrt.4. January 24. 2010 95 .4 and later. rsqrt.0 +0. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. rsqrt.f64 isr.f32 and rsqrt.approx.0 NaN The maximum absolute error for rsqrt. Subnormal numbers: sm_20: By default. Target ISA Notes Examples rsqrt.

0 -0. For PTX ISA version 1.PTX ISA Version 2. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. sin.approx. the . 2010 .0 +0.approx{.f32 implements a fast approximation to sine. d = sin(a).0.ftz. Target ISA Notes Examples Supported on all target architectures.3. Explicit modifiers .0 Table 62.f32 introduced in PTX ISA version 1.approx.0 +subnormal +Inf NaN Result NaN -0. a. For PTX ISA versions 1. PTX ISA Notes sin.0 through 1. a.9 in quadrant 00. Find the sine of the angle a (in radians). sin.ftz introduced in PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +0.approx modifier is required.f32.f32 sa. Subnormal numbers: sm_20: By default.ftz. 96 January 24.approx and .f32 flushes subnormal inputs and results to sign-preserving zero. Input -Inf -subnormal -0. sin.4.4 and later. subnormal numbers are supported.f32 defaults to sin.f32 d. sin. sin.0 NaN NaN The maximum absolute error is 2-20.ftz.0 +0.approx.ftz}.

Target ISA Notes Examples Supported on all target architectures.0 +1.f32 introduced in PTX ISA version 1.0 through 1.0 +1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz.0 NaN NaN The maximum absolute error is 2-20.f32 d. d = cos(a). Subnormal numbers: sm_20: By default. PTX ISA Notes cos.4.f32 defaults to cos.f32 implements a fast approximation to cosine. cos. the . For PTX ISA version 1.approx.0. Explicit modifiers .ftz.9 in quadrant 00. a.0 +subnormal +Inf NaN Result NaN +1. Instruction Set Table 63. cos.Chapter 8.approx.approx.3. cos. cos. a.ftz introduced in PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 ca.0 +1. cos.approx and . 2010 97 .approx modifier is required.approx{.f32.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.ftz. For PTX ISA versions 1.ftz}. Input -Inf -subnormal -0. Find the cosine of the angle a (in radians).0 +0. January 24.4 and later.

0.f32 introduced in PTX ISA version 1.ftz. d = log(a) / log(2). Input -Inf -subnormal -0.0 Table 64. lg2. a.0 +0.f32 defaults to lg2.approx{.6 for mantissa. lg2.f32 implements a fast approximation to log2(a). lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. the .0 through 1. Subnormal numbers: sm_20: By default.ftz introduced in PTX ISA version 1.approx. lg2.ftz.approx.f32.f32 la. lg2. subnormal numbers are supported.4. The maximum absolute error is 2-22. Explicit modifiers . 2010 . 98 January 24.ftz}.approx. a. PTX ISA Notes lg2. Target ISA Notes Examples Supported on all target architectures.4 and later.3. For PTX ISA versions 1.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.f32 Determine the log2 of a.approx and . lg2.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.PTX ISA Version 2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

January 24, 2010

99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

January 24, 2010

Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

January 24, 2010

101

Subnormal numbers: sm_20: By default.s16. Modifier .f64 supports subnormal numbers. ne. q = BoolOp(!t. setp. p[|q]. bit-size comparisons are eq and ne. lo. loweror-same.f64 source type requires sm_13 or later. c). setp. and (optionally) combine this result with a predicate value by applying a Boolean operator.f32 comparisons. leu. hs equ. neu. and hs for lower. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. p = BoolOp(t. p. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. .CmpOp. Applies to all numeric types.b16. then these comparisons have the same result as their ordered counterparts. ne. ge. {!}c.lt. . b. 2010 . For unsigned values. gt. ne. @q setp. .f32.type = { . Semantics t = (a CmpOp b) ? 1 : 0. le.ftz}.dtype. then the result of these comparisons is true.n. le. gt.ftz applies only to .s64.u64.u32. leu. . ge. le. sm_1x: setp. lt.ftz. lt. ltu.s32 setp.B) is one of: and. nan The Boolean operator BoolOp(A. ls. the comparison operators lo. geu. . xor. setp with . and higher-or-same may be used instead of lt. If either operand is NaN. gt. ge. le. hi. b. c).and.i. This result is written to the first destination operand. The untyped. The comparison operator is a suffix on the instruction.f32 flushes subnormal inputs to sign-preserving zero. If both operands are numeric values (not NaN). geu. the result is false. 102 January 24. lt. A related value computed using the complement of the compare result is written to the second destination operand. a.r.f32 flushes subnormal inputs to sign-preserving zero.PTX ISA Version 2. gt.u16. setp.ftz}. The destinations p and q must be . The signed and unsigned comparison operators are eq. ge.CmpOp{. and nan returns true if either operand is NaN. To aid comparison operations in the presence of NaN values. hi. unordered versions are included: equ.0. num. If either operand is NaN. Integer Notes Floating Point Notes The ordered comparisons are eq. respectively. .type .s32.0 Table 67. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. ls.type setp. .BoolOp{.dtype.b64. neu.eq. subnormal numbers are supported. . . or. p[|q].pred variables.dtype.b.a.f64 }. gtu. higher. and can be one of: eq. ltu.b32.u32 p|q. a. num returns true if both operands are numeric values (not NaN). . gtu.

. otherwise b is stored in d. Semantics Floating Point Notes January 24. Subnormal numbers: sm_20: By default. b.b64.u16. operand c must match the second instruction type. b otherwise. . If operand c is NaN.ftz. and operand a is selected. Instruction Set Table 68. .xp. . selp Syntax Comparison and Selection Instructions: selp Select between source operands.f64 requires sm_13 or later.u32. .dtype.f32 d.f32. c. . and operand a is selected. slct Syntax Comparison and Selection Instructions: slct Select one source operand. slct.b16.x.f32 A. the comparison is unordered and operand b is selected. . a. based on the value of the predicate source operand. negative zero equals zero. slct.f64 }.0.s16. Operands d. z.u64. c. If c ≥ 0. @q selp. slct.s32 selp. For . a is stored in d. selp. .u64. c.s64. a.f32 r0. . C.dtype = { . . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. a. b.f32 flushes subnormal values of operand c to sign-preserving zero.g.dtype. .u16. and b must be of the same type.s32.type = { .s32 x. selp.b64. a.p. .ftz applies only to .f32 flushes subnormal values of operand c to sign-preserving zero. d.u32. .ftz}.type d.b32. 2010 103 . . b. slct. f0.f64 }. Modifier .f32 comparisons. . If c is True. The selected input is copied to the output without modification. Description Conditional selection.f64 requires sm_13 or later. Operands d.f32 comparisons. sm_1x: slct.0. B. val.b32. d = (c >= 0) ? a : b.s64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a is stored in d.s32 slct{. Table 69.u32.b16.t.r. .u64.f32.dtype. . fval. a. . . d = (c == 1) ? a : b.Chapter 8.ftz. based on the sign of the third operand. Introduced in PTX ISA version 1. . subnormal numbers are supported. slct.s16. . . y. Operand c is a predicate.dtype.s32. and b are treated as a bitsize type of the same width as the first instruction type.

or.4.PTX ISA Version 2. and not also operate on predicates. xor. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. Instructions and. This permits bit-wise operations on floating point values without having to define a union to access the bits. provided the operands are of the same size. performing bit-wise operations on operands of any type. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.0 8. 2010 .7.

Allowed types include predicate registers.q. .q.Chapter 8.0x80000000. and Syntax Logic and Shift Instructions: and Bitwise AND. Allowed types include predicate registers. Introduced in PTX ISA version 1.pred p. Supported on all target architectures. b. and. or. . sign.type = { .b32 mask mask. but not necessarily the type.r.type d.b16.fpvalue.0. 2010 105 . b. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. . Introduced in PTX ISA version 1. or Syntax Logic and Shift Instructions: or Bitwise OR. a.type d. Table 71. Supported on all target architectures. a.b64 }.pred.b32 x. .b32 and.b32. d = a & b. but not necessarily the type. .0. January 24. d = a | b.type = { . . or.b32. and. . The size of the operands must match.0x00010001 or. Instruction Set Table 70.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.pred.r. The size of the operands must match.b16.

Table 73.b16 d. not.type = { .q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. a.b32 xor. Introduced in PTX ISA version 1.type = { . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.0x0001. . not.b32 d. cnot. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. d. 2010 . a. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). . Allowed types include predicates. Supported on all target architectures. but not necessarily the type.b32. xor.mask. Introduced in PTX ISA version 1. Table 74.type = { . d = ~a.b64 }.0. d = a ^ b.b16.pred.b16. The size of the operands must match. but not necessarily the type. Introduced in PTX ISA version 1. not Syntax Logic and Shift Instructions: not Bitwise negation. but not necessarily the type. .b32 mask. . cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.0. . Supported on all target architectures.PTX ISA Version 2. Supported on all target architectures.b32. d = (a==0) ? 1 : 0.q. cnot. . . .b32.pred.type d. The size of the operands must match. Allowed types include predicate registers.x. .a.b16. one’s complement. The size of the operands must match. . 106 January 24.type d.r. not.b64 }.type d.0 Table 72. .pred p.b64 }. a.0. b. xor.

but not necessarily the type.Chapter 8.b16. i.type d. . shl. but not necessarily the type. Supported on all target architectures. shl. The b operand must be a 32-bit value.type = { . . shr.u32. Introduced in PTX ISA version 1. a. d = a >> b. b. The sizes of the destination and first source operand must match. regardless of the instruction type. k. unsigned and untyped shifts fill with 0. PTX ISA Notes Target ISA Notes Examples Table 76. .2.u64. zero-fill on right.b64. d = a << b. .a. Introduced in PTX ISA version 1. Signed shifts fill with the sign bit.b32 q. regardless of the instruction type. The b operand must be a 32-bit value. . . .type = { . sign or zero fill on left.a.b64 }.0.u16.1. Shift amounts greater than the register width N are clamped to N. Instruction Set Table 75.b16. Supported on all target architectures. shr. . . a. PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.b32.u16 shr.s32.2.i. . .i.type d. . The sizes of the destination and first source operand must match. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.0. b. Shift amounts greater than the register width N are clamped to N.j. Bit-size types are included for symmetry with SHL. 2010 107 .b16 c. shl Syntax Logic and Shift Instructions: shl Shift bits left.s32 shr.b32.s16.s64 }. shr Syntax Logic and Shift Instructions: shr Shift bits right.

ldu. suld.5. and st operate on both scalar and vector types. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. prefetchu isspacep cvta cvt 108 January 24. mov. st.0 8. ld. and sust support optional cache operations.PTX ISA Version 2. possibly converting it from one format to another. Instructions ld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.7. Data Movement and Conversion Instructions These instructions copy data from place to place. and from state space to state space. local. 2010 . or shared state spaces. The cvta instruction converts addresses between generic and global.

cs) on global addresses. If one thread stores to global memory via one L1 cache. any existing cache lines that match the requested address in L1 will be evicted. Use ld.lu Last use. The ld. Operator . and a second thread loads that address via a second L1 cache with ld. The ld.cg Cache at global level (cache in L2 and below.cv Cache as volatile (consider cached system memory lines stale.cv to a frame buffer DRAM address is the same as ld. Instruction Set 8. The ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. likely to be accessed again.0 introduces optional cache operators on load and store instructions. the cache operators have the following definitions and behavior. . Table 77.7. if the line is fully covered. the second thread may get stale L1 cache data. when applied to a local address. likely to be accessed once. but multiple L1 caches are not coherent for global data. to allow the thread program to poll a SysMem location written by the CPU.cg to cache loads only globally. The compiler / programmer may use ld.ca.cs is applied to a Local window address.5. Global data is coherent at the L2 level. The ld.1. For sm_20 and later. and cache only in the L2 cache. When ld. not L1). it performs the ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. . . The cache operators require a target architecture of sm_20 or later.lu load last use operation.lu instruction performs a load cached streaming operation (ld. 2010 109 . January 24.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. invalidates (discards) the local L1 line following the load.ca. bypassing the L1 cache. .ca loads cached in L1.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.cs Cache streaming. Cache Operators PTX 2. rather than the data stored by the first thread. The default load instruction cache operation is ld. fetch again).cs. evict-first. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. A ld.Chapter 8.lu operation. As a result of this request. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.

ca. but st. st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.cg to local memory uses the L1 cache.0 Table 78. rather than get the data from L2 or memory stored by the first thread. . and cache only in the L2 cache. The default store instruction cache operation is st.wb for global data. However.wb could write-back global store data from L1. and discard any L1 lines that match.cg is the same as st.wt Cache write-through (to system memory).cg Cache at global level (cache in L2 and below. the second thread may get a hit on stale L1 cache data.cs Cache streaming. Global stores bypass L1. in which case st. bypassing its L1 cache. . The driver must invalidate global L1 cache lines between dependent grids of thread arrays. bypassing the L1 cache. and marks local L1 lines evict-first.cg to cache global store data only globally. The st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. not L1).ca loads.PTX ISA Version 2. 110 January 24. to allow a CPU program to poll a SysMem location written by the GPU with st. Use st. which writes back cache lines of coherent cache levels with normal eviction policy. Future GPUs may have globally-coherent L1 caches.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Addresses not in System Memory use normal write-back. The st. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. likely to be accessed once. If one thread stores to global memory. 2010 . Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wt store write-through operation applied to a global System Memory address writes through the L2 cache.wb. In sm_20.wt. Operator . and a second thread in a different SM later loads from that address via a different L1 cache with ld. . regardless of the cache operation.

Description .pred. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. d. mov places the non-generic address of the variable (i.v. d = &avar.b32. .e. ptr. or shared state space may be taken directly using the cvta instruction.f64 requires sm_13 or later.s16. alternately.Chapter 8.0. mov. or function name. and . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. . .type mov.. Write register d with the value of a.s64.u32.type mov. // get address of variable // get address of label or function .s32. Instruction Set Table 79.global. . a. Note that if the address of a device function parameter is moved to a register.u16. . local.b16.type mov. Take the non-generic address of a variable in global.f32.f64 }. local. .shared state spaces. avar. special register. . mov.type d. ptr. myFunc.a. variable in an addressable memory space. u. The generic address of a variable in global.1.type = { . i.u32 d. d = &label. 2010 111 . A.local. . sreg. within the variable’s declared state space Notes Although only predicate and bit-size types are required. A[5]. Semantics d = a. d.const. k. the parameter will be copied onto the stack and the address will be in the local state space. d = sreg. the address of the variable in its state space) into the destination register.f32 mov.u64.u16 mov.. . local. label.u32 mov.f32 mov. . // address is non-generic. immediate. addr. or shared state space.e. d. the generic address of a variable declared in global. . Operand a may be a register.b64.u32 mov. . label. For variables declared in . mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. Introduced in PTX ISA version 1.0. mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.

7].b}.hi are .15]. For bit-size types.w have type .y } = { a[0. %x.x | (a. d.y } = { a[0. a[16.u32 x.b.0. a.z. mov.x | (a.31].b16 { d.hi}.y } = { a[0.y. or write vector register d with the unpacked values from scalar register a.PTX ISA Version 2.y << 32) // pack two 8-bit elements into .b64 // pack two 32-bit elements into . mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).31] } // unpack 16-bit elements from .b64 }. d..7].y.b8 r.w << 48) d = a.w } = { a[0.31] } // unpack 8-bit elements from ..b.x.x | (a.b32 // pack two 16-bit elements into .z.15].b64 { d.u16 %x is a double. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.g.b have type .b32 // pack four 16-bit elements into .y.y << 16) d = a.. d. Supported on all target architectures.g.w << 24) d = a.b16 // pack four 8-bit elements into .y << 8) | (a.type = { . d.b64 112 January 24..type d.15]..x.b32 %r1.b64 { d..{a. d.z. . mov. a[16.b32 mov. 2010 .15] } // unpack 8-bit elements from .b32 mov.z. a[48.0 Table 80.x.z << 16) | (a.x | (a. Semantics d = a.b32...x. {r. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.x.y. a[24. a[8..b32 { d.u8 // unpack 32-bit elements from . d.31]. %r1.a}.. {lo. a[8.y << 16) | (a.23]. d.47]. a[32..63] } // unpack 16-bit elements from . d. lo. d. // // // // a.. .y << 8) d = a.x | (a.%r1..b64 mov. Description Write scalar register d with the packed value of vector register a.b16.b32 { d. a[32.a have type .w}.{x.z << 32) | (a. a[16.w } = { a[0. ..63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

cop}..reg state space.v4 }.type ld.shared spaces to inhibit optimization of references to volatile memory. A destination register wider than the specified type may be used.f16 data may be loaded using ld.s16. ld introduced in PTX ISA version 1. . .const space suffix may have an optional bank number to indicate constant banks other than bank zero.global.volatile. or [immAddr] an immediate absolute byte address (unsigned.ss}. an address maps to global memory unless it falls within the local memory window or the shared memory window.volatile{.f64 }. . ld{. Generic addressing and cache operations introduced in PTX ISA 2. an address maps to the corresponding location in local or shared memory.param.e. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . . *(a+immOff).type . . perform the load using generic addressing. 2010 113 .ss = { . and is zeroextended to the destination register width for unsigned and bit-size types. Within these windows. .b16.1.b64.const.type d. i.u8. .b16.shared }. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.type = { . and truncated if the register width exceeds the state space address width for the target architecture. ld.volatile may be used with . . In generic addressing.Chapter 8. 32-bit). d. *(immAddr). [a]. Semantics d d d d = = = = a.s32.b8. . i. The address size may be either 32-bit or 64-bit. If an address is not properly aligned. *a. . Cache operations are not permitted with ld. .cg. d. [a].u32. .vec. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. .cop = { . . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.lu. . The .f32. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . .f64 using cvt.cv }. Addresses are zero-extended to the specified width as needed.cop}.s8. .ss}{. d.cs. for example.type ld{.0. If no state space is given. Description Load register variable d from the location specified by the source address operand a in specified state space.local. or the instruction may fault. .volatile introduced in PTX ISA version 1.e. This may be used. [a].v2. to enforce sequential consistency between threads accessing shared memory.volatile.b32. an integer or bit-size type register reg containing a byte address. PTX ISA Notes January 24.u16. .volatile{.global and . . and then converted to . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . ld.ss}{. [a].ss}.ca. the resulting behavior is undefined. The value loaded is sign-extended to the destination register width for signed integers. 32-bit). .u64.vec = { . . . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.f32 or .s64. Generic addressing may be used with ld. The address must be naturally aligned to a multiple of the access size.vec.0. Instruction Set Table 81.

f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.b32 ld.s32 ld.f64 requires sm_13 or later. d. // immediate address %r.global.local.%r.f32 ld.f32. Q.const.[fs].const[4]. // access incomplete array x. %r.0 Target ISA Notes ld.global.v4. Generic addressing requires sm_20 or later.[p+-8].PTX ISA Version 2.b16 cvt. // load . x.f16 d.b64 ld.shared. Cache operations require sm_20 or later.local.[p+4].b32 ld.[240].[buffer+64].[p]. ld.[a]. 2010 . // negative offset %r.b32 ld.

where the address is guaranteed to be the same across all threads in the warp.v4 }.b8. . .b16. // load from address // vec load from address .s8.f16 data may be loaded using ldu. In generic addressing. an address maps to the corresponding location in local or shared memory. If an address is not properly aligned.f64 }.[p].s32. For ldu.u32. The data at the specified address must be read-only.b16. or the instruction may fault. Instruction Set Table 82.ss}. an address maps to global memory unless it falls within the local memory window or the shared memory window. 32-bit).f32 or . perform the load using generic addressing.b32 d.e. .b32. *(a+immOff).[p+4].ss = { . and is zeroextended to the destination register width for unsigned and bit-size types. . the resulting behavior is undefined.u64. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type = { . ldu.reg state space. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . If no state space is given. d. The address size may be either 32-bit or 64-bit. i. A destination register wider than the specified type may be used. 32-bit). . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.s64.type d.b64.s16. ldu.u16. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .v2.vec = { . . only generic addresses that map to global memory are legal. *a. A register containing an address may be declared as a bit-size type or integer type. Within these windows.v4. The address must be naturally aligned to a multiple of the access size.. Addresses are zero-extended to the specified width as needed. . [a]. . *(immAddr). ldu{.f64 requires sm_13 or later. ldu.global }. . .f32 d. Introduced in PTX ISA version 2. [areg] a register reg containing a byte address. and truncated if the register width exceeds the state space address width for the target architecture.f32 Q. .vec.e. ldu. . [a]. The value loaded is sign-extended to the destination register width for signed integers. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.[a]. // state space .f32. PTX ISA Notes Target ISA Notes Examples January 24. The addressable operand a is one of: [avar] the name of an addressable variable var.f64 using cvt. .0. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.global. i.type ldu{.ss}. or [immAddr] an immediate absolute byte address (unsigned. . Semantics d d d d = = = = a. and then converted to .global.u8.Chapter 8. 2010 115 .global.

This may be used.0 Table 83. .1.s16.ss}. . Cache operations require sm_20 or later.type st{. .volatile{. .b64. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. .f64 }. [a].b8. .global. Generic addressing may be used with st.ss}{. perform the store using generic addressing.0. . The address size may be either 32-bit or 64-bit. b. 2010 .e. an integer or bit-size type register reg containing a byte address.ss}. . If no state space is given. the resulting behavior is undefined. If an address is not properly aligned.0. *(immAddr) = a.wt }. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. . for example.e.f64 requires sm_13 or later.shared spaces to inhibit optimization of references to volatile memory.b16.u16.f32.type = = = = {. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.. an address maps to the corresponding location in local or shared memory. In generic addressing. Generic addressing and cache operations introduced in PTX ISA 2.b32. . { . [a].cop}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.volatile introduced in PTX ISA version 1. . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. or the instruction may fault. st introduced in PTX ISA version 1. Within these windows.shared }.cop}. PTX ISA Notes Target ISA Notes 116 January 24. b.vec .s64.global and .reg state space.u32.cs. i.ss . 32-bit). the access may proceed by silently masking off low-order address bits to achieve proper rounding.volatile{. .volatile.vec.cop .volatile may be used with . . and truncated if the register width exceeds the state space address width for the target architecture.local. *(d+immOffset) = a. .type st.volatile. st. st. [a]. *d = a.s8. 32-bit). Addresses are zero-extended to the specified width as needed. st{. { . A source register wider than the specified type may be used. .type [a].cg. or [immAddr] an immediate absolute byte address (unsigned. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.ss}{. an address maps to global memory unless it falls within the local memory window or the shared memory window. { .type . to enforce sequential consistency between threads accessing shared memory.f16 data resulting from a cvt instruction may be stored using st. b. The address must be naturally aligned to a multiple of the access size. The lower n bits corresponding to the instruction-type width are stored to memory.vec.v4 }.wb.b16.s32. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .u8.PTX ISA Version 2. Generic addressing requires sm_20 or later. . . st. . Semantics d = a. i.v2.u64. Cache operations are not permitted with st. . b.

Chapter 8.v4. Instruction Set Examples st.b32 st. // %r is 32-bit register // store lower 16 bits January 24.s32 cvt.a.b32 st.global. // immediate address %r.b. // negative offset [100].f32 st.f16.r7.local. [q+-8].f32 st.%r. [p]. [fs].s32 st. 2010 117 .local.a.b16 [a]. [q+4].global.%r.local.Q.

space}. A prefetch into the uniform cache requires a generic address. an address maps to the corresponding location in local or shared memory. If no state space is given.L1.L1 [addr]. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.e. .level prefetchu. and no operation occurs if the address maps to a local or shared memory location.PTX ISA Version 2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. prefetch. prefetch{. Addresses are zero-extended to the specified width as needed. and truncated if the register width exceeds the state space address width for the target architecture. .local }.space = { . . A prefetch to a shared memory location performs no operation. 118 January 24. 32-bit). prefetch and prefetchu require sm_20 or later. i. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.0. or [immAddr] an immediate absolute byte address (unsigned. a register reg containing a byte address. 32-bit). // prefetch to data cache // prefetch to uniform cache . [a].L2 }.L1 [a]. The address size may be either 32-bit or 64-bit. prefetchu. Within these windows.0 Table 84. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. In generic addressing. in specified state space. an address maps to global memory unless it falls within the local memory window or the shared memory window. 2010 .L1 [ptr].global. the prefetch uses generic addressing.level = { .global. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.

local. sptr.pred. islcl.global. local.space p. local. cvta.space.shared }.size . Description Convert a global. the generic address of the variable may be taken using cvta.space = { . local. January 24. // local.u32 or .lptr. a. or shared state space. // get generic address of svar cvta.u64 or cvt. A program may use isspacep to guard against such incorrect behavior.global. gptr. svar. The source address operand must be a register of type . lptr. or shared address to a generic address. isspacep.u32 to truncate or zero-extend addresses.space = { . isspacep. Take the generic address of a variable declared in global. or shared state space to generic.size p.size = { . or shared address cvta. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or shared state space. cvta requires sm_20 or later. // convert to generic address // get generic address of var // convert generic address to global.u32 p.Chapter 8.u64. or vice-versa. isspacep requires sm_20 or later. . a. cvta. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u64. isshrd.local isspacep. . // result is . cvta.0. Instruction Set Table 85.to. . local.genptr.space. or vice-versa.global.u64 }. .u32 gptr. When converting a generic address into a global.pred .shared. or shared address. p.global isspacep.to.local. PTX ISA Notes Target ISA Notes Examples Table 86.shared }. p. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a. local.local. .0. Introduced in PTX ISA version 2. Use cvt. For variables declared in global.u32 p.size cvta. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. 2010 119 .u32. The destination register must be of type . var.space. The source and destination addresses must be the same size.shared isglbl.u32. .

.rm. Description Semantics Integer Notes Convert between different types and sizes. The compiler will preserve this behavior for legacy PTX code. .atype d.dtype = .e. Integer rounding is required for float-to-integer conversions.rp }.f32. . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.dtype.s16. a.. .rpi }. subnormal inputs are flushed to signpreserving zero.atype = { . Saturation modifier: .ftz.u32. . The optional .f16.s8. .u16.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.sat is redundant.rz.. .sat}. .irnd}{.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. 120 January 24.sat}. subnormal numbers are supported. the result is clamped to the destination range by default.atype cvt{. a. .irnd = { .rn.frnd}{.0 Table 87. For float-to-integer conversions. i.s32. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rzi round to nearest integer in the direction of zero . Note: In PTX ISA versions 1. .rni round to nearest integer. d = convert(a).sat limits the result to MININT.ftz. Integer rounding modifiers: .u8. . subnormal inputs are flushed to signpreserving zero.rni.ftz}{. sm_1x: For cvt. .PTX ISA Version 2. the .dtype. . 2010 .f32.ftz}{. . .ftz. Note that saturation applies to both signed and unsigned integer types. // integer rounding // fp rounding .MAXINT for the size of the operation. and for same-size float-tofloat conversions where the value is rounded to an integer. .f32 float-tofloat conversions with integer rounding.u64.rzi.rmi. For cvt.ftz. choosing even integer if source is equidistant between two integers.f32 float-to-integer conversions and cvt. i. cvt{.f32 float-tofloat conversions with integer rounding. .dtype. . .f64 }.s64. Integer rounding is illegal in all other instances.e.ftz modifier may be specified in these cases for clarity. d.sat For integer destination types. .f32.4 and earlier.dtype.f32 float-to-integer conversions and cvt.frnd = { .rmi round to nearest integer in direction of negative infinity . .

rn mantissa LSB rounds to nearest even . The operands must be of the same size.f32 instructions.f32.Chapter 8.0.rm mantissa LSB rounds towards negative infinity .f32.0. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f32 x.sat limits the result to the range [0. Floating-point rounding is illegal in all other instances.f16. // float-to-int saturates by default cvt. The optional .f64 types. cvt to or from . .r.i. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .ftz behavior for sm_1x targets January 24. cvt.f32.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).4 and earlier. and cvt. Introduced in PTX ISA version 1.f32. Applies to . 1. The result is an integral value. subnormal numbers are supported. Modifier .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.rz mantissa LSB rounds towards zero .f16. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. Subnormal numbers: sm_20: By default.y. and for integer-to-float conversions.ftz modifier may be specified in these cases for clarity. 2010 121 . and .s32. Note: In PTX ISA versions 1.y.f64 j. // note . Floating-point rounding modifiers: . // round to nearest int. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. cvt.f32 x.f64. .sat For floating-point destination types.rni.0].f32.f32. result is fp cvt.version is 1. Specifically.f16.f64 requires sm_13 or later.s32 f. if the PTX . The compiler will preserve this behavior for legacy PTX code.4 or earlier. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. stored in floating-point format.f32. cvt. Saturation modifier: . NaN results are flushed to positive zero.

entry compute_power ( . and surface descriptors.height.width. sampler.f32 {r1. r1.7. but the number of samplers is greatly restricted to 16.b32 r5. In the independent mode. If no texturing mode is declared. mul. r5. and surfaces.texref tex1 ) { txq. and surface descriptors. r3. A PTX module may declare only one texturing mode.f32 r1. r3. r5. r4.param .target texmode_independent . r1. 122 January 24. } = clamp_to_border.b32 r6. The texturing mode is selected using .0 8. sampler. Texture and Surface Instructions This section describes PTX instructions for accessing textures.2d. . = nearest width height tsamp1.target options ‘texmode_unified’ and ‘texmode_independent’.u32 r5.v4..f32 r3.6. [tex1]. // get tex1’s txq.f2}]. texture and sampler information is accessed through a single . 2010 . [tex1.u32 r5. Example: calculate an element’s power contribution as element’s power/total number of elements. and surface descriptors.global .r4}.f32 r1. samplers. texture and sampler information each have their own handle. The advantage of unified mode is that it allows 128 samplers. sampler. [tex1]. Texturing modes For working with textures and samplers. and surface descriptors: • • • Static initialization of texture. with the restriction that they correspond 1-to-1 with the 128 possible textures.f32 r1. PTX supports the following operations on texture. PTX has two modes of operation..f32. // get tex1’s tex. . sampler. Module-scope and per-entry scope definitions of texture. add.r2. The advantage of independent mode is that textures and samplers can be mixed and matched. cvt. allowing them to be defined separately and combined at the site of usage in the program.texref handle. r6.r3. add. {f1. Ability to query fields within texture. r1.PTX ISA Version 2. add.samplerref tsamp1 = { addr_mode_0 filter_mode }. r2. r5. In the unified mode.f32. . the file is assumed to use unified mode. div.

If an address is not properly aligned. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. If no sampler is specified. where the fourth element is ignored. 2010 123 .f3. the resulting behavior is undefined.1d. d.s32.geom.0. [tex_a. . {f1.r2. // Example of independent mode texturing tex. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.e. c].geom = { .v4. //Example of unified mode texturing tex.btype tex.f4}]. A texture base address is assumed to be aligned to a 16-byte address.r3. i. . . tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. The instruction always returns a four-element vector of 32-bit values. the sampler behavior is a property of the named texture. // explicit sampler .f32 {r1.f32 }.5.r2. and is a four-element vector for 3d textures. the square brackets are not required and .. Supported on all target architectures.dtype. . {f1}].v4 coordinate vectors are allowed for any geometry. Operand c is a scalar or singleton tuple for 1d textures. [tex_a. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.v4. . .v4. An optional texture sampler b may be specified.r4}.3d. or the instruction may fault.btype d.s32.s32. tex txq suld sust sured suq Table 88. Notes For compatibility with prior versions of PTX. b.2d. [a.u32.3d }. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32 {r1. PTX ISA Notes Target ISA Notes Examples January 24.v4.btype = { . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. .r4}.geom. tex.r3. with the extra elements being ignored.1d.dtype = { .f2.s32. Instruction Set These instructions provide access to texture and surface memory. c]. [a. sampler_x. is a two-element vector for 2d textures. Description Texture lookup using a texture coordinate vector.f32 }. Unified mode texturing introduced in PTX ISA version 1.dtype.Chapter 8.

linear } Integer from enum { wrap.addr_mode_0 . Integer from enum { nearest.tquery. txq. Supported on all target architectures. . [tex_A]. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. txq. txq.0 Table 89.squery = { .normalized_coords .filter_mode . // texture attributes // sampler attributes .PTX ISA Version 2. Description Query an attribute of a texture or sampler.b32 %r1. addr_mode_2 }. . and in independent mode sampler attributes are accessed via a separate samplerref argument.depth. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. [smpl_B].width. . .tquery = { .addr_mode_0. In unified mode.b32 %r1. txq.5.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).height. Operand a is a .width .addr_mode_1 .filter_mode. [a].texref or .squery. .b32 %r1. d.filter_mode. [a].b32 txq. addr_mode_1. clamp_to_edge.b32 d.depth . sampler attributes are also accessed via a texref argument. Query: .height .width.samplerref variable.normalized_coords }.addr_mode_0. clamp_ogl. // unified mode // independent mode 124 January 24. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. mirror. 2010 . [tex_A].

w}].cv }.trap {r1. if the surface format contains UINT data.b .v4. or FLOAT data. // unformatted d. suld Syntax Texture and Surface Instructions: suld Load from surface memory. suld. suld. suld.b64.cop}.v2.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. or . . The lowest dimension coordinate represents a sample offset rather than a byte offset. SNORM.1d. Instruction Set Table 90. The .u32. size and type conversion is performed as needed to convert from the surface sample format to the destination type. the surface sample elements are converted to .dtype . . suld.b64 }.f32. . [surf_B. Coordinate elements are of type . Destination vector elements corresponding to components that do not appear in the surface format are not written.zero }.trap.clamp = = = = = = { { { { { { d.s32 is returned. . suld. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.trap . 2010 125 .u32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . A surface base address is assumed to be aligned to a 16-byte address. .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. then .geom{.geom{.1d.5.0. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. [surf_A. If the destination base type is .b supported on all target architectures.vec.b performs an unformatted load of binary data. and the size of the data transfer matches the size of destination operand d. G. .3d }.v2. .clamp . additional clamp modifiers.ca.Chapter 8.geom . [a.b.b8 .b32..v4.trap suld. or the instruction may fault. and A components of the surface format.cop}. B. suld. Cache operations require sm_20 or later. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.dtype. suld.2d. the resulting behavior is undefined. then . Operand a is a .cg.f2. i.f32 }.cop . {x}]. and cache operations introduced in PTX ISA version 2. suld.vec . If an address is not properly aligned. then . .b16. [a. // formatted .p.f32 based on the surface format as follows: If the surface format contains UNORM. and is a four-element vector for 3d surfaces. .e.f32 is returned.r2}.p.p requires sm_20 or later.s32. Description Load from surface memory using a surface coordinate vector. b].clamp field specifies how to handle out-of-bounds addresses: . {f1. sm_1x targets support only the .clamp. // for suld.s32. . . . or .v4 }.u32.b32. .dtype .p is currently unimplemented.cs. . .dtype.trap clamping modifier.surfref variable.p .z. {x. // cache operation none. suld. .f4}.clamp suld. Target ISA Notes Examples January 24.b.p. If the destination type is .s32. where the fourth element is ignored.3d.y.clamp .f3.trap introduced in PTX ISA version 1.s32. if the surface format contains SINT data. . Operand b is a scalar or singleton tuple for 1d surfaces. is a two-element vector for 2d surfaces.f32.u32 is returned.b.3d requires sm_20 or later. b].b32. // for suld.

[surf_B.s32. 2010 . then . b].3d. SNORM.s32.u32.v4.b64.b supported on all target architectures.ctype .z.f32 }.clamp = = = = = = { { { { { { [a.clamp sust. Surface sample components that do not occur in the source vector will be written with an unpredictable value.cop}. sust.b32.cg.2d. sust. sust. {x.f2. .b.0 Table 91.0. and is a four-element vector for 3d surfaces. .f4}. B. [a.vec. sust.5.s32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.cop . Operand a is a . c. Coordinate elements are of type .cop}. These elements are written to the corresponding surface sample components. .b32. sust.geom . .1d. or .y.geom{.b64 }. {f1. c. sust.b.v4 }.ctype .f32. The source data is then converted from this type to the surface sample format.b performs an unformatted store of binary data. // for sust. A surface base address is assumed to be aligned to a 16-byte address.p. then .trap .3d }. is a two-element vector for 2d surfaces. if the surface format contains SINT data. b].f32 is assumed. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. sust.cs.b32. where the fourth element is ignored.{u32. . . .u32 is assumed. The . and cache operations introduced in PTX ISA version 2. G.1d. none.trap [surf_A.f32} are currently unimplemented.p.w}].ctype. The size of the data transfer matches the size of source operand c.u32.v2.vec. Cache operations require sm_20 or later.b // for sust. .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. Target ISA Notes Examples 126 January 24.e.s32. . The source vector elements are interpreted left-to-right as R. .trap sust.. // unformatted // formatted . sust. .clamp field specifies how to handle out-of-bounds addresses: . then .wt }. additional clamp modifiers. size and type conversions are performed as needed between the surface sample format and the destination type. If the source base type is .s32 is assumed.b16.p requires sm_20 or later. or FLOAT data. the resulting behavior is undefined.f32.r2}.v2.geom{.clamp.vec . .surfref variable.trap.p. .PTX ISA Version 2. The lowest dimension coordinate represents a sample offset rather than a byte offset. and A surface components. sm_1x targets support only the .p Description Store to surface memory using a surface coordinate vector. . .3d requires sm_20 or later. Operand b is a scalar or singleton tuple for 1d surfaces. . .zero }.b8 .b. if the surface format contains UINT data.clamp . Source elements that do not occur in the surface sample are ignored. {x}]. .p performs a formatted store of a vector of 32-bit data values to a surface sample.trap introduced in PTX ISA version 1. the access may proceed by silently masking off low-order address bits to achieve proper rounding. sust Syntax Texture and Surface Instructions: sust Store to surface memory. or the instruction may fault. If an address is not properly aligned.ctype.wb. {r1.clamp . If the source type is . sust.trap clamping modifier. .f3. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.p. i. .

operations and and or apply to .3d }.1d.p performs a reduction on sample-addressed 32-bit data. If an address is not properly aligned.and.1d. Operand a is a . then . [surf_B. r1. and . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. // for sured.clamp. .ctype = { .b].u64. where the fourth element is ignored.b.u32 and . and is a four-element vector for 3d surfaces.u32. 2010 127 .e.u32. .y}].clamp field specifies how to handle out-of-bounds addresses: .2d.p .surfref variable.s32 types. . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. The .geom = { . . .op. the resulting behavior is undefined.u32 based on the surface sample format as follows: if the surface format contains UINT data.c. sured requires sm_20 or later. sured. or the instruction may fault.u32.trap [surf_A. Reduction to surface memory using a surface coordinate vector.op = { .max. January 24. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. sured. . r1.trap .geom. or . // byte addressing sured. Coordinate elements are of type . .u64.ctype. .s32 or . . i. {x.p.ctype = { .b32 }. min and max apply to .or }. Operations add applies to .b32. .u64 data.s32 types.s32.trap sured. .u32 is assumed.Chapter 8. sured.2d.clamp [a.b32..clamp = { .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .b performs an unformatted reduction on . and the data is interpreted as . The instruction type is restricted to .b32 type.ctype.b].geom. A surface base address is assumed to be aligned to a 16-byte address. The lowest dimension coordinate represents a sample offset rather than a byte offset. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. . .min.add. if the surface format contains SINT data. Operand b is a scalar or singleton tuple for 1d surfaces. .b .b32 }. then .s32 is assumed.s32.op. .0.clamp .zero }.trap. // sample addressing .add.b32. is a two-element vector for 2d surfaces.min.b.p. Instruction Set Table 92. {x}].c.clamp [a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. sured.u32. // for sured.s32.

2010 .b32 %r1.height . Supported on all target architectures.5. 128 January 24.height. . .width. Operand a is a .depth }.width .b32 d. Query: .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.width. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.surfref variable.query. . suq. suq.0 Table 93. Description Query an attribute of a surface. [surf_A].query = { . [a].PTX ISA Version 2.

{} Syntax Description Control Flow Instructions: { } Instruction grouping.0. Supported on all target architectures. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.x. mov.f32 @!p div.s32 d. used primarily for defining a function body.b.0. setp. { instructionList } The curly braces create a group of instructions. @{!}p instruction.c. Execute an instruction or instruction block for threads that have the guard predicate true.7. ratio. Threads with a false guard predicate do nothing.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Supported on all target architectures.s32 a. Introduced in PTX ISA version 1. 2010 129 .y.eq. { add. Instruction Set 8.a.f32 @q bra L23.Chapter 8.0. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. } PTX ISA Notes Target ISA Notes Examples Table 95.7. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. p. If {!}p then instruction Introduced in PTX ISA version 1.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

130

January 24, 2010

Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

January 24, 2010

131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

132

January 24, 2010

red.arrive.red instruction. Register operands.cta.red performs a predicate reduction across the threads participating in the barrier. Each CTA instance has sixteen barriers numbered 0. b. Operand b specifies the number of threads participating in the barrier.red performs a reduction operation across threads.and and . Instruction Set Table 100.arrive a{. bar.popc. execute a bar.or }.pred . all-threads-true (. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Thus. {!}c. Operands a.op = { .sync) until the barrier count is met. bar.u32 bar. Thus. If no thread count is specified. Barriers are executed on a per-warp basis as if all the threads in a warp are active. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). Execution in this case is unpredictable. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. threads within a CTA that wish to communicate via memory can store to memory. bar. bar. The result of . a{.arrive using the same active barrier. January 24. When a barrier completes. and bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. the waiting threads are restarted without delay.u32..red} introduced in PTX . it simply marks a thread's arrival at the barrier. . the bar.0.sync and bar.{arrive. d. bar.Chapter 8. thread count.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. b}. and any-thread-true (. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. The reduction operations for bar. all threads in the CTA participate in the barrier.op. The barrier instructions signal the arrival of the executing threads at the named barrier. b}.popc is the number of threads with a true predicate.red are population-count (.{arrive.popc).sync and bar. Since barriers are executed on a per-warp basis. if any thread in a warp executes a bar instruction. it is as if all the threads in the warp have executed the bar instruction. bar. p.sync or bar. Register operands.sync with an immediate barrier number is supported for sm_1x targets. bar.red delays the executing threads (similar to bar. PTX ISA Notes Target ISA Notes Examples bar. and the barrier is reinitialized so that it can be immediately reused. while .red also guarantee memory ordering among threads identical to membar.red} require sm_20 or later.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. bar.and.sync without a thread count introduced in PTX ISA 1.sync 0. Note that a non-zero thread count is required for bar. 2010 133 . the optional thread count must be a multiple of the warp size.0. and bar. In conditionally executed code. a.red. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. All threads in the warp are stalled until the barrier completes.sync or bar. In addition to signaling its arrival at the barrier. a{. Only bar. the final value is written to the destination register in all threads waiting at the barrier. Once the barrier count is reached.arrive does not cause any waiting by the executing threads. b}. and then safely read values stored by other threads prior to the barrier.15.red should not be intermixed with bar.version 2. thread count. bar.and).or).sync bar. {!}c. operands p and c are predicates. and d have type . Description Performs barrier synchronization and communication within a CTA. b.

that is.version 2.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. or system memory level.level. . Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar. by st. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar.gl. . and memory reads by this thread can no longer be affected by other thread writes.sys will typically have much longer latency than membar.sys introduced in PTX . membar. membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar. global. this is the appropriate level of membar. including thoses communicating via PCI-E such as system and peer-to-peer memory. .cta Waits until all prior memory writes are visible to other threads in the same CTA. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.gl.g. level describes the scope of other clients for which membar is an ordering event.sys Waits until all prior memory requests have been performed with respect to all clients.gl will typically have a longer latency than membar.cta.gl} supported on all target architectures. 2010 .g. membar. membar. membar. 134 January 24. membar. PTX ISA Notes Target ISA Notes Examples membar.4. membar.sys.PTX ISA Version 2.{cta.cta. when the previous value can no longer be read.sys requires sm_20 or later. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.gl} introduced in PTX . membar.cta. A memory read (e.sys }.gl.0.{cta. Waits until prior memory reads have been performed with respect to other threads in the CTA.0 Table 101. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. A memory write (e. For communication between threads in different CTAs or even different SMs.level = { .version 1.

.g. . . 2010 135 . Operand a specifies a location in the specified state space. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.b32 only . [a]. . a de-referenced register areg containing a byte address. cas (compare-and-swap).b64 .space}. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.Chapter 8. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. January 24. the access may proceed by silently masking off low-order address bits to achieve proper rounding. or the instruction may fault. or.op. The integer operations are add.f32.max }. by inserting barriers between normal stores and atomic operations to a common address. atom. d. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. min. . If no state space is given. and max.global.s32.b64.u64. .f32 Atomically loads the original value at location a into destination register d. [a]. . Instruction Set Table 102.e. A register containing an address may be declared as a bit-size type or integer type. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.type atom{.space = { . . c. or by using atom. min.add. atom{. . . For atom. and exch (exchange).or.u32. In generic addressing. . inc.dec.inc. . or [immAddr] an immediate absolute byte address. . and max operations are single-precision.op. Within these windows. .exch to store to locations accessed by other atomic operations. The floating-point add. e. accesses to local memory are illegal.shared }.b32...cas.e. b.s32. .space}.xor. . . min. an address maps to the corresponding location in local or shared memory.add. Description // // // // // .b].b32. and stores the result of the specified operation at location a.and.s32. . 32-bit operations. The floating-point operations are add.type d.type = { . . Addresses are zero-extended to the specified width as needed. overwriting the original value. i. . The inc and dec operations return a result in the range [0.u32. b.u32 only . i. . an address maps to global memory unless it falls within the local memory window or the shared memory window. performs a reduction operation with operand b and the value in location a.op = { . perform the memory accesses using generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The address must be naturally aligned to a multiple of the access size. xor.u32. . the resulting behavior is undefined.exch. dec. and truncated if the register width exceeds the state space address width for the target architecture.u64 .f32 }. max. . The address size may be either 32-bit or 64-bit.min. . The bit-size operations are and. If an address is not properly aligned.

b.f32 atom.{min.cas.t) = (r == s) ? t operation(*a. cas(r. *a = (operation == cas) ? : } where inc(r. Introduced in PTX ISA version 1.s.{add.global.add. : r-1. c) operation(*a. s) = (r > s) ? s exch(r.my_val.max. atom. : r.max} are unimplemented. atom. 64-bit atom.[x+4]. 2010 .1.[a]. Release Notes Examples @p 136 January 24.f32.add. d.b32 d.0.exch} requires sm_12 or later.global. atom.0 Semantics atomic { d = *a.shared operations require sm_20 or later. 64-bit atom.my_new_val.cas. atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. s) = s.global requires sm_11 or later. s) = (r >= s) ? 0 dec(r. : r+1.[p]. atom.PTX ISA Version 2. Use of generic addressing requires sm_20 or later. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.f32 requires sm_20 or later. d.shared requires sm_12 or later. b).s32 atom.0.shared.

. . The integer operations are add. and truncated if the register width exceeds the state space address width for the target architecture. an address maps to global memory unless it falls within the local memory window or the shared memory window. .b32. red.u32. . and max operations are single-precision. s) = (r > s) ? s : r-1. For red. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.u64. .add. and max. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. or [immAddr] an immediate absolute byte address.f32 Performs a reduction operation with operand b and the value in location a.. and stores the result of the specified operation at location a. . the resulting behavior is undefined. overwriting the original value. A register containing an address may be declared as a bit-size type or integer type. or by using atom.and.min.op = { . . i. Addresses are zero-extended to the specified width as needed. dec. The bit-size operations are and.or. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. or the instruction may fault. i.type = { . The address must be naturally aligned to a multiple of the access size. January 24.op. The floating-point add.dec. min. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . max. e.b]. dec(r.space}.xor.u32. min. .b64.add.global.u32 only .f32 }.b32 only .e.max }.f32. Description // // // // . .type [a]. inc..e. . perform the memory accesses using generic addressing. or.g. b).Chapter 8. Semantics *a = operation(*a. The address size may be either 32-bit or 64-bit. If an address is not properly aligned. The inc and dec operations return a result in the range [0. . . 32-bit operations. Instruction Set Table 103.shared }. . a de-referenced register areg containing a byte address.u64 . 2010 137 . accesses to local memory are illegal. min.s32. by inserting barriers between normal stores and reduction operations to a common address. b. . . . In generic addressing.space = { . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. s) = (r >= s) ? 0 : r+1. Notes Operand a must reside in either the global or shared state space. . . and xor.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . where inc(r. . The floating-point operations are add. Operand a specifies a location in the specified state space.exch to store to locations accessed by other reduction operations.inc.s32.s32. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding. red{. If no state space is given. an address maps to the corresponding location in local or shared memory.u32. Within these windows.

b32 [a].global.add requires sm_12 or later.max.PTX ISA Version 2. red.global requires sm_11 or later red.f32. [p].add. Use of generic addressing requires sm_20 or later.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 red.global.1.my_val.f32 requires sm_20 or later.0.shared requires sm_12 or later.2.shared operations require sm_20 or later. red. 2010 . red.shared.{min. Release Notes Examples @p 138 January 24.s32 red.and.max} are unimplemented. red. 64-bit red. 64-bit red.add. [x+4].

all.all True if source predicate is True for all active threads in warp.any. vote.uni.uni. // ‘ballot’ form. vote. not across an entire CTA.ballot. .all. vote requires sm_12 or later. returns bitmask . 2010 139 .mode = { . . The destination predicate value is the same across all threads in the warp. Negate the source predicate to compute .ballot.p. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. Note that vote applies to threads in a single warp.q.mode. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.b32 requires sm_20 or later. // get ‘ballot’ across warp January 24. {!}a.pred vote. . In the ‘ballot’ form.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.uni True if source predicate has the same value in all active threads in warp.q.2. r1.any True if source predicate is True for some active thread in warp. . p.ballot. Negating the source predicate also computes .Chapter 8.pred vote. where the bit position corresponds to the thread’s lane id.uni }.not_all.pred d.b32 p. The reduction modes are: . vote. {!}a.b32 d. Description Performs a reduction of the source predicate across threads in a warp. vote. Negate the source predicate to compute .ballot.none. Instruction Set Table 104. vote.

btype{. b{.secop = { .s32) is specified in the instruction type.atype. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).b2. The sign of the intermediate result depends on dtype. 2. c. . . . half-word. a{. . perform a scalar arithmetic operation to produce a signed 34-bit result.asel}. extract and sign. // 32-bit scalar operation.s34 intermediate result.btype = { . all combinations of dtype.u32. The primary operation is then performed to produce an .dtype.s33 values. or word values from its source operands.7.u32 or . 3. b{.h0. vop. a{. the input values are extracted and signor zero.atype.bsel}.extended internally to . with optional secondary operation vop.0 8. . optionally clamp the result to the range of the destination type.or zero-extend byte. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.dtype = .secop d.sat} d. b{.PTX ISA Version 2. .asel}.bsel}. Video Instructions All video instructions operate on 32-bit register operands. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.btype{.9.b1.dtype. 140 January 24.asel = .b0. and btype are valid.atype = .min. taking into account the subword destination size in the case of optional data merging. . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.add.dsel = . to produce signed 33-bit input values. The source and destination operands are all 32-bit registers.max }. with optional data merge vop.btype{. .atype.dtype.asel}.bsel}.bsel = { .sat} d. Using the atype/btype and asel/bsel specifiers. The type of each operand (.dsel.b3. The general format of video instructions is as follows: // 32-bit scalar operation. . 4. . atype.s32 }. c. .h1 }. a{.sat}. 2010 .

as shown in the following pseudocode.b3: if ( sign ) return CLAMP( else return CLAMP( case .s33 optSecOp(Modifier secop.add: return tmp + c.min: return MIN(tmp. c). U8_MIN ). 2010 141 .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. . S16_MAX.b2: return ((tmp & 0xff) << 16) case . . . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). } } . U16_MAX. tmp.b1: return ((tmp & 0xff) << 8) case .s33 tmp. The sign of the c operand is based on dtype.b3: return ((tmp & 0xff) << 24) default: return tmp.h0. . . tmp. c). S32_MAX. The lower 32-bits are then written to the destination operand. S16_MIN ). January 24. S8_MAX. . . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. . U8_MAX.b0: return ((tmp & 0xff) case .Chapter 8. U32_MIN ). tmp. Bool sat.b1.s33 optMerge( Modifier dsel. tmp.s33 c ) switch ( dsel ) { case . S8_MIN ). c). tmp.b0.s33 optSaturate( . U32_MAX.b2.s34 tmp. Bool sign.h0: return ((tmp & 0xffff) case . . Modifier dsel ) { if ( !sat ) return tmp. c). .max return MAX(tmp.s33 c) { switch ( secop ) { . . c).s33 tmp.h1: return ((tmp & 0xffff) << 16) case . U16_MIN ). S32_MIN ). c). Instruction Set . switch ( dsel ) { case . c). default: return tmp.

c.asel}.op2 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat vmin.u32. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. Integer byte/half-word/word minimum / maximum. vmin. r3. b{.b1. r2.min.atype = . c ). tmp. // optional merge with c operand 142 January 24.s32.atype. Perform scalar arithmetic operation with optional saturate. .sat} d.sat. vmin. . r1. Semantics // saturate.op2 Description = = = = { vadd. .h1. tmp.add.s32. vmax }.b0. taking into account destination type and merge operations tmp = optSaturate( tmp. tb = partSelectSignExtend( b. asel ).sat vabsdiff. vop. r2. // 32-bit scalar operation. vmax Syntax Integer byte/half-word/word addition / subtraction.atype.dtype. vmax vadd. tmp = ta – tb.asel}.dtype.s32. // extract byte/half-word/word and sign. tmp = MAX( ta.sat}. . d = optSecondaryOp( op2.or zero-extend based on source operand type ta = partSelectSignExtend( a. vadd.bsel}. .PTX ISA Version 2.h0. vmax require sm_20 or later. vabsdiff.h0.u32. with optional secondary operation vop. a{. tb ). r2.b3.b2.h1.h0. .dtype .b0.b0. vabsdiff. tmp = | ta – tb |. c ). vmin.asel = .add r1. tb ). vabsdiff. // 32-bit scalar operation.0 Table 105.h1 }. sat.b2. c. r3. . 2010 . .bsel}.bsel}. bsel ). . vsub. // optional secondary operation d = optMerge( dsel.s32. c. btype.s32.asel}.s32. and optional secondary arithmetic operation or subword data merge. dsel ).u32.btype{. a{.dsel. Integer byte/half-word/word absolute value of difference.atype. vadd. r1. r3.s32. vsub vabsdiff vmin.s32. Video Instructions: vadd.dtype. r3.s32.vop . atype.s32.sat vsub. . with optional data merge vop. r1.btype{. isSigned(dtype). . vsub.max }. r2. a{. tmp = MIN( ta. c. b{. { .0.dsel . b{.bsel = { .btype{.sat} d.s32 }.btype = { . vsub.

bsel ).wrap r1.asel}.b0.u32. atype. vshl. . . r2. . .dtype.clamp .sat}{. . and optional secondary arithmetic operation or subword data merge.atype = { . with optional data merge vop.s32. . a{.u32.h0. b{.u32{. with optional secondary operation vop. .dtype.bsel}. vop.min. vshr vshl.asel}. c ).u32{.atype.asel = . if ( mode == . Instruction Set Table 106.mode . if ( mode == . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. isSigned(dtype).sat}{. // optional secondary operation d = optMerge( dsel. switch ( vop ) { case vshl: tmp = ta << tb. vshr }.mode}. a{. r3.b2. r1. d = optSecondaryOp( op2. . tmp. // default is .mode} d. Left shift fills with zero. asel ). a{. r2.u32{.sat}{.b3. c ).wrap }.atype.dsel. { . r3. unsigned shift fills with zero. b{.bsel}. . and optional secondary arithmetic operation or subword data merge.atype. Signed shift fills with the sign bit.or zero-extend based on source operand type ta = partSelectSignExtend( a.h1 }.u32 vshr. case vshr: tmp = ta >> tb. sat. . vshr Syntax Integer byte/half-word/word left / right shift.clamp. dsel ).s32 }. tmp.h1. // 32-bit scalar operation.op2 Description = = = = = { vshl.max }.clamp && tb > 32 ) tb = 32. taking into account destination type and merge operations tmp = optSaturate( tmp.op2 d.Chapter 8.add. vshr: Shift a right by unsigned amount in b with optional saturate.dtype . vshl.mode} d. Semantics // extract byte/half-word/word and sign. // 32-bit scalar operation.vop . . c.u32.bsel = { .u32. } // saturate.asel}. January 24. vshl: Shift a left by unsigned amount in b with optional saturate. 2010 143 .dsel .0. .u32.wrap ) tb = tb & 0x1f. b{. { .u32. Video Instructions: vshl. tb = partSelectSignExtend( b. vshr require sm_20 or later.b1.dtype. c.bsel}.

b0. Source operands may not be negated in .dtype. with optional operand negates. {-}a{.atype = . The source operands support optional negation with some restrictions. final signed -(S32 * U32) + S32 // intermediate signed. a{. b{.bsel}. final signed (S32 * S32) . and scaling. . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.0 Table 107.bsel}.btype. PTX allows negation of either (a*b) or c. The “plus one” mode (. final signed (S32 * U32) . final signed -(S32 * S32) + S32 // intermediate signed.U32 // intermediate unsigned. 2010 .asel = . {-}c. this result is sign-extended if the final result is signed.atype.btype{. and zero-extended otherwise.scale} d.po) computes (a*b) + c + 1. final signed (U32 * U32) .s32 }. (a*b) is negated if and only if exactly one of a or b is negated. which is used in computing averages.dtype = . final signed (S32 * U32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift. vmad.shr7. final signed (S32 * S32) + S32 // intermediate signed. . // 32-bit scalar operation vmad.S32 // intermediate signed. .S32 // intermediate signed. and the operand negates.scale} d. .PTX ISA Version 2. .asel}. .sat}{.shr15 }.asel}. The final result is unsigned if the intermediate result is unsigned and c is not negated. Input c has the same sign as the intermediate result. final signed (U32 * S32) + S32 // intermediate signed.bsel = { . 144 January 24. “plus one” mode. . {-}b{. otherwise.b2. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. internally this is represented as negation of the product (a*b). final signed -(U32 * S32) + S32 // intermediate signed. Description Calculate (a*b) + c. the intermediate result is signed.dtype. Although PTX syntax allows separate negation of the a and b operands.h1 }.h0. c.S32 // intermediate signed. .btype = { . . That is.sat}{. final signed (U32 * S32) .b3.u32.atype.b1. Depending on the sign of the a and b operands. . final unsigned -(U32 * U32) + S32 // intermediate signed. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.scale = { .po{..po mode.

atype. r3.shr15 r0. signedFinal = isSigned(atype) || isSigned(btype) || (a. U32_MIN).or zero-extend based on source operand type ta = partSelectSignExtend( a. r2. S32_MIN).0.h0. tb = partSelectSignExtend( b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32. r0. tmp = tmp + c128 + lsb.negate. vmad. bsel ).shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate ^ b. if ( . switch( scale ) { case . case .negate ^ b.negate ) { c = ~c. tmp[127:0] = ta * tb. } else if ( a. S32_MAX.negate ) { tmp = ~tmp. Instruction Set Semantics // extract byte/half-word/word and sign.Chapter 8. 2010 145 .s32.sat vmad.u32. -r3.shr7: result = (tmp >> 7) & 0xffffffffffffffff. lsb = 1. else result = CLAMP(result. r1. vmad requires sm_20 or later. asel ). lsb = 0.po ) { lsb = 1. January 24. r2. r1. lsb = 1. } if ( .u32.sat ) { if (signedFinal) result = CLAMP(result. U32_MAX. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). } else if ( c.u32.negate) || c. btype.h0.u32.

cmp d. vset.u32.h1 }. tmp.asel}.btype. Compare input values using specified comparison.btype. c ).atype .atype.or zero-extend based on source operand type ta = partSelectSignExtend( a.cmp. . vset requires sm_20 or later. with optional secondary arithmetic operation or subword data merge.b0.b3. 146 January 24. tmp. a{. tb = partSelectSignExtend( b. . // optional secondary operation d = optMerge( dsel.btype.asel}. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. b{. { .ge }.asel}. r3. r3.s32 }.op2 d. .max }. cmp ) ? 1 : 0. c.dsel. c ).u32.h0.bsel}. . . // 32-bit scalar operation.gt. with optional data merge vset. r1.lt. tmp = compare( ta.min. r2. . vset. . with optional secondary operation vset.cmp . { . bsel ).u32. // 32-bit scalar operation.bsel = { . a{.cmp d.atype. . . . r2. btype. .btype = { .add. atype. tb. b{. and therefore the c operand and final result are also unsigned. .dsel . c.bsel}. a{.asel = .PTX ISA Version 2. Semantics // extract byte/half-word/word and sign.atype.ne.h1. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 .le. asel ).ne r1. .s32. d = optSecondaryOp( op2.u32. . b{. .op2 Description = = = = . The intermediate result of the comparison is always unsigned.b2.lt vset.bsel}.0 Table 108.0.eq.b1.

10. trap Abort execution and generate an interrupt to the host CPU. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. with index specified by immediate operand a. The relationship between events and counters is programmed via API calls from the host.Chapter 8. Table 110. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. trap. pmevent 7. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. pmevent a.0. Introduced in PTX ISA version 1. @p pmevent 1. brkpt. Supported on all target architectures. 2010 147 . there are sixteen performance monitor events.0. Notes PTX ISA Notes Target ISA Notes Examples Currently. brkpt Suspends execution Introduced in PTX ISA version 1. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. January 24. brkpt. Supported on all target architectures. numbered 0 through 15. Introduced in PTX ISA version 1. Triggers one of a fixed number of performance monitor events. brkpt requires sm_11 or later.7. Instruction Set 8.4. Table 111. trap. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.

PTX ISA Version 2. 2010 .0 148 January 24.

%lanemask_ge. %lanemask_lt. Special Registers PTX includes a number of predefined. which are visible as special registers and accessed through mov or cvt instructions. 2010 149 . %lanemask_le. %pm3 January 24.Chapter 9. %clock64 %pm0. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. …. read-only variables. %lanemask_gt %clock.

Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. %ntid. Supported on all target architectures. // move tid. Supported on all target architectures. %ntid. // legacy PTX 1. read-only. %tid. The number of threads in each dimension are specified by the predefined special register %ntid.u32 %ntid.u16 %r2.sreg .0.y.v4 .u32 %tid. %ntid. %tid.z < %ntid. CTA dimensions are non-zero.x 0 <= %tid.u32 %r0.u32.y * %ntid. mov. the %tid value in unused dimensions is 0. mov.%h2.%tid.z. mov.u32 %r0.v4.z == 1 in 1D CTAs.x < %ntid. cvt. mov.y 0 <= %tid. . Every thread in the CTA has a unique %tid. . It is guaranteed that: 0 <= %tid. %ntid.x to %rh Target ISA Notes Examples // legacy PTX 1.z == 0 in 1D CTAs.x. %tid.%ntid.u32 %ntid.y. .%tid.x * %ntid. per-thread special register initialized with the thread identifier within the CTA.x.%h1.0.z == 1 in 2D CTAs.y == %ntid. 2010 .sreg .x code Target ISA Notes Examples 150 January 24.x. %tid component values range from 0 through %ntid–1 in each CTA dimension. // compute unified thread id for 2D CTA mov.v4 .u32 %r1.sreg . 2D. or 3D vector to match the CTA shape. // zero-extend tid.z.u32 type in PTX 2. mad. PTX ISA Notes Introduced in PTX ISA version 1. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.0 Table 112. read-only special register initialized with the number of thread ids in each CTA dimension.x code accessing 16-bit component of %tid mov.u16 %rh.sreg .x. Redefined as . Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.u16 %rh.%tid.z). The total number of threads in a CTA is (%ntid.x. The fourth element is unused and always returns zero.y < %ntid.z.z PTX ISA Notes Introduced in PTX ISA version 1. The %tid special register contains a 1D.%tid. // thread id vector // thread id components A predefined.u32 type in PTX 2.%ntid.z to %r2 Table 113.u32 %tid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.y.x.u32 %h2.z == 0 in 2D CTAs.0. %tid.PTX ISA Version 2.v4. the fourth element is unused and always returns zero. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.%r0.0.x.u32 %h1. Redefined as . . // CTA shape vector // CTA dimensions A predefined.%tid.y == %tid.

u32 %warpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.3. Special Registers Table 114. .sreg . 2010 151 .0. read-only special register that returns the thread’s lane within the warp.sreg . Supported on all target architectures. Table 115. %nwarpid requires sm_20 or later. mov. read-only special register that returns the thread’s warp identifier.u32 %nwarpid. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.sreg . PTX ISA Notes Target ISA Notes Examples Table 116. Note that %warpid is volatile and returns the location of a thread at the moment when read. .u32 %laneid. but its value may change during execution. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. January 24.u32 %r. mov.3. Introduced in PTX ISA version 1. . due to rescheduling of threads following preemption. The warp identifier will be the same for all threads within a single warp. %laneid. mov. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. A predefined. %warpid. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. e. Introduced in PTX ISA version 1.g.u32 %r. The lane identifier ranges from zero to WARP_SZ-1. A predefined.Chapter 9.u32 %r. For this reason. Supported on all target architectures. A predefined. read-only special register that returns the maximum number of warp identifiers. Introduced in PTX ISA version 2. %nwarpid. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.

u32 %nctaid .x. %ctaid. read-only special register initialized with the CTA identifier within the CTA grid.u32 mov. . Redefined as .y 0 <= %ctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.x code Target ISA Notes Examples Table 118.v4 .sreg . // CTA id vector // CTA id components A predefined. mov. The %ctaid special register contains a 1D.y. // legacy PTX 1. read-only special register initialized with the number of CTAs in each grid dimension.%nctaid.{x. // legacy PTX 1.z < %nctaid.0. The fourth element is unused and always returns zero.z} < 65.z. .536 PTX ISA Notes Introduced in PTX ISA version 1.sreg . with each element having a value of at least 1.u32 %ctaid.y < %nctaid. %rh.u32 type in PTX 2.%ctaid.sreg .u16 %r0. %rh.y. 2010 .0.0 Table 117.x < %nctaid.sreg .0.u32 %nctaid.v4 . depending on the shape and rank of the CTA grid. . Supported on all target architectures. // Grid shape vector // Grid dimensions A predefined. 2D.%nctaid.u16 %r0.x.x. or 3D vector.u32 mov.z PTX ISA Notes Introduced in PTX ISA version 1. mov.PTX ISA Version 2. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.v4.0.v4.%ctaid.%nctaid.%nctaid.x.u32 %ctaid.x code Target ISA Notes Examples 152 January 24. Each vector element value is >= 0 and < 65535. %ctaid. Redefined as .u32 type in PTX 2.y. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. Supported on all target architectures. It is guaranteed that: 1 <= %nctaid.x 0 <= %ctaid.y. It is guaranteed that: 0 <= %ctaid.z.x. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. The %nctaid special register contains a 3D grid shape vector. The fourth element is unused and always returns zero.

u32 %r. . Special Registers Table 119. // initialized at grid launch A predefined. mov.u32 %r. %smid.sreg . Notes PTX ISA Notes Target ISA Notes Examples Table 120. A predefined. Supported on all target architectures. e. This variable provides the temporal grid launch number for this context. . During execution. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %nsmid requires sm_20 or later. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. mov.u32 %nsmid. Supported on all target architectures.sreg . Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Note that %smid is volatile and returns the location of a thread at the moment when read. Introduced in PTX ISA version 2.0. %gridid. Introduced in PTX ISA version 1.u32 %smid. due to rescheduling of threads following preemption. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. %nsmid.0.g.Chapter 9. A predefined. read-only special register initialized with the per-grid temporal grid identifier. so %nsmid may be larger than the physical number of SMs in the device. read-only special register that returns the maximum number of SM identifiers. The SM identifier ranges from 0 to %nsmid-1. . The SM identifier numbering is not guaranteed to be contiguous. The SM identifier numbering is not guaranteed to be contiguous. but its value may change during execution. PTX ISA Notes Target ISA Notes Examples Table 121.sreg .3. where each launch starts a grid-of-CTAs.u32 %r. mov. repeated launches of programs may occur. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.u32 %gridid. Introduced in PTX ISA version 1. 2010 153 . PTX ISA Notes Target ISA Notes Examples January 24.

A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Table 123.sreg . A predefined. Introduced in PTX ISA version 2.0 Table 122.PTX ISA Version 2. mov.0.u32 %r. Introduced in PTX ISA version 2.0. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later. 2010 .u32 %r.u32 %r.u32 %lanemask_eq. . %lanemask_lt.sreg . . 154 January 24. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. %lanemask_le. mov. %lanemask_le requires sm_20 or later. mov. %lanemask_eq. A predefined. %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %lanemask_lt. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg .u32 %lanemask_le. . Table 124.0. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.

0. mov.sreg . A predefined. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt. %lanemask_ge.sreg . %lanemask_gt requires sm_20 or later. 2010 155 .u32 %r.Chapter 9. A predefined. Introduced in PTX ISA version 2.u32 %lanemask_ge. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.0. Special Registers Table 125. mov. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Introduced in PTX ISA version 2. Table 126.u32 %lanemask_gt.u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. . %lanemask_ge requires sm_20 or later. . January 24.

0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. %pm3. Introduced in PTX ISA version 1. Special Registers: %pm0. . %clock64 requires sm_20 or later.0 Table 127.u64 r1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. . Table 128. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Supported on all target architectures. Introduced in PTX ISA version 1. mov. Special registers %pm0. Table 129.u32 r1. mov. %pm2. ….%clock64.%clock.u64 %clock64. Supported on all target architectures. read-only 64-bit unsigned cycle counter. 156 January 24. %pm2.sreg . Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Introduced in PTX ISA version 2.sreg . read-only 32-bit unsigned cycle counter. . Their behavior is currently undefined.%pm0.u32 %clock. %pm2. mov. %pm1. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. and %pm3 are unsigned 32-bit read-only performance monitor counters.PTX ISA Version 2.3. 2010 .sreg . %pm1.u32 r1. %pm3 %pm0. The lower 32-bits of %clock64 are identical to %clock. %pm1.0.u32 %pm0.

0.version 1.4 January 24.version Syntax Description Semantics PTX version number.version .version . minor are integers Specifies the PTX language version number.target Table 130. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and the target architecture for which the code was generated.version 2.version directive. . PTX File Directives: . . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. 2010 157 . .1.0 . Increments to the major number indicate incompatible changes to PTX.version directives are allowed provided they match the original . Directives 10.version directive. Each ptx file must begin with a .version major.minor // major. Duplicate .Chapter 10. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.

158 January 24. Target sm_20 Description Baseline feature set for sm_20 architecture. vote instructions. Requires map_f64_to_f32 if any . PTX File Directives: . Requires map_f64_to_f32 if any . with only half being used by instructions converted from .target directives can be used to change the set of target features allowed during parsing. A . In general.f64 instructions used. PTX features are checked against the specified target architecture. Therefore. Texturing mode: (default is . Each PTX file must begin with a .texmode_independent texture and sampler information is bound together and accessed via a single .red}.texmode_unified . but subsequent .target Syntax Architecture and Platform target.f64 instructions used.f64 instructions used.f64 storage remains as 64-bits. Supported on all target architectures. Adds {atom. Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_12.version directive.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. including expanded rounding modifiers. The following table summarizes the features in PTX that vary according to target architecture.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.red}.texmode_unified) . PTX code generated for a given target can be run on later generation devices. brkpt instructions. Texturing mode introduced in PTX ISA version 1. and an error is generated if an unsupported feature is used. generations of SM architectures follow an “onion layer” model. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. texmode_unified.global. Note that . Requires map_f64_to_f32 if any . Adds {atom.f32.target . sm_11.f64 to .target directive containing a target architecture and optional platform options. sm_13.PTX ISA Version 2.5. texture and sampler information is referenced with independent .0 Table 131. immediately followed by a . Disallows use of map_f64_to_f32. . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. texmode_independent.global.shared.samplerref descriptors. map_f64_to_f32 }. A program with multiple . The texturing mode is specified for an entire module and cannot be changed within the module.0. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.texref and .target directive specifies a single target architecture. Adds double-precision support. 2010 . 64-bit {atom.red}. sm_10. where each generation adds new features and retains all features of previous generations.texref descriptor.

target sm_13 // supports double-precision .target sm_10 // baseline target architecture .Chapter 10.target sm_20. texmode_independent January 24. Directives Examples . 2010 159 .

parameters. ld.entry filter ( . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. Supported on all target architectures.param.func Table 132. and query instructions and cannot be accessed via ld. PTX ISA Notes For PTX ISA version 1. etc.param .param.param { .entry . Parameters may be referenced by name within the kernel body and loaded into registers using ld.0 10. %nctaid. [z]. At kernel launch.5 and later.0 through 1. Semantics Specify the entry point for a kernel program. The shape and size of the CTA executing the kernel are available in special registers.entry kernel-name kernel-body Defines a kernel entry point name. and body for the kernel function. opaque . the kernel dimensions and properties are established and made available via special registers. %ntid.reg . [y]. 2010 .entry Syntax Description Kernel entry point and body.entry kernel-name ( param-list ) kernel-body . In addition to normal parameters.4 and later.b32 %r3.2.3.b32 z ) Target ISA Notes Examples [x]. For PTX ISA versions 1.texref. ld. … } . parameter variables are declared in the kernel parameter list. 160 January 24. . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. store.g.PTX ISA Version 2. These parameters can only be referenced by name within texture and surface load. . e.surfref variables may be passed as parameters. Kernel and Function Directives: . ld. Parameters are passed via .4.0 through 1.b32 y.param space memory and are listed within an optional parenthesized parameter list.param .b32 %r<99>.b32 x. .b32 %r1. and .param instructions. with optional parameters. parameter variables are declared in the kernel body.param instructions.b32 %r2. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. .param.entry . .samplerref.entry cta_fft . .

The parameter lists define locally-scoped variables in the function body. Parameters in register state space may be referenced directly within instructions in the function body.reg .param state space. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.reg . foo. mov. including input and return parameters and optional function body. Parameters must be base types in either the register or parameter state space. if any.func .func Syntax Function definition. parameters must be in the register state space. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.func definition with no body provides a function prototype. and recursion is illegal. and supports recursion.0 with target sm_20 allows parameters in the . … Description // return value in fooval January 24.b32 rval) foo (. PTX ISA 2. Directives Table 133.func (. Parameter passing is call-by-value.x code. other code. Variadic functions are currently unimplemented.0.0 with target sm_20 supports at most one return value. (val0.b32 N.func (ret-param) fname (param-list) function-body Defines a function.func fname (param-list) function-body . ret.f64 dbl) { .Chapter 10.reg . Supported on all target architectures. } … call (fooval).param instructions in the body.func fname function-body .b32 rval. PTX 2. Kernel and Function Directives: . Release Notes For PTX ISA version 1. 2010 161 . … use N. Variadic functions are represented using ellipsis following the last fixed argument.result. there is no stack. dbl.param and st. . Parameters in . . val1). which may use a combination of registers and stack locations to pass parameters.reg . .2 for a description of variadic functions. A .param space are accessed using ld. The implementation of parameter passing is left to the optimizing translator. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. implements an ABI with stack.b32 localVar.

and . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.pragma directive is supported for passing information to the PTX backend. registers) to increase total thread count and provide a greater opportunity to hide memory latency.maxnctapersm (deprecated) . . A general .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. and the strings have no semantics within the PTX virtual machine model.minnctapersm . for example. at entry-scope.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). 2010 . Note that . These can be used. The interpretation of . and the . to throttle the resource requirements (e.minnctapersm directives may be applied per-entry and must appear between an . or as statements within a kernel or device function body. the . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. The directive passes a list of strings to the backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. 162 January 24. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.PTX ISA Version 2.maxntid directive specifies the maximum number of threads in a thread block (CTA).0 10. . Currently.maxntid.maxnreg.pragma directives may appear at module (file) scope. which pass information to the backend optimizing compiler.g.3.pragma The . The directives take precedence over any module-level constraints passed to the optimizing backend.maxntid and . the .maxnreg .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. PTX supports the following directives. The .entry directive and its body.maxntid .

maxntid nx.maxnreg n Declare the maximum number of registers per thread in a CTA.entry foo .maxntid 16. . ny .maxntid and . Supported on all target architectures. for example.maxntid Syntax Maximum number of threads in thread block (CTA).entry bar . nz Declare the maximum number of threads in the thread block (CTA).maxntid . Performance-Tuning Directives: .3. The compiler guarantees that this limit will not be exceeded. .entry foo . Exceeding any of these limits results in a runtime error or kernel launch failure.16. or 3D CTA.3. or the maximum number of registers may be further constrained by . This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid nx. Directives Table 134. . Introduced in PTX ISA version 1.maxntid 256 . 2D. Supported on all target architectures.maxntid nx .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.Chapter 10. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. The maximum number of threads is the product of the maximum extent in each dimension.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxctapersm. The actual number of registers used may be less. ny. Performance-Tuning Directives: . 2010 163 . . the backend may be able to compile to fewer registers. Introduced in PTX ISA version 1.maxnreg .

maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Performance-Tuning Directives: . Optimizations based on .maxntid 256 .0.minnctapersm 4 { … } 164 January 24.maxnctapersm generally need . Introduced in PTX ISA version 2.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid 256 . . Supported on all target architectures.3.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.0.minnctapersm generally need .maxnctapersm. Optimizations based on .maxntid and .maxnctapersm (deprecated) .0 as a replacement for .PTX ISA Version 2.maxntid to be specified as well. Deprecated in PTX ISA version 2.0 Table 136.entry foo . 2010 . if the number of registers used by the backend is sufficiently lower than this bound. . However.maxnctapersm has been renamed to . Supported on all target architectures. Performance-Tuning Directives: .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. .minnctapersm in PTX ISA version 2. Introduced in PTX ISA version 1. .entry foo . For this reason. The optimizing backend compiler uses . additional CTAs may be mapped to a single multiprocessor. .maxntid to be specified as well.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.minnctapersm .

The interpretation of . Performance-Tuning Directives: . at entry-scope. . Pass module-scoped.entry foo . Directives Table 138. entry-scoped.pragma Syntax Description Pass directives to PTX backend compiler.pragma “nounroll”.pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma . or statement-level directives to the PTX backend compiler.pragma “nounroll”. Supported on all target architectures. { … } January 24. . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma list-of-strings . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma directive may occur at module-scope.0. or at statementlevel. Introduced in PTX ISA version 2.Chapter 10. 2010 165 . The .

0 10.0 but is supported for legacy PTX version 1. Supported on all target architectures. 0x00 166 January 24.loc The .section ..232-1] . 2010 . “”. Deprecated as of PTX 2.4. 0x61395a5f.2.4byte 0x6e69616d. 0x02. 0x63613031.0 and replaces the @@DWARF syntax.debug_pubnames. 0x6150736f. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x00. replaced by .4byte int32-list // comma-separated hexadecimal integers in range [0.byte byte-list // comma-separated hexadecimal byte values .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. The @@DWARF syntax is deprecated as of PTX version 2.section directive is new in PTX ISA verison 2.section directive..section . 0x00 .x code. 0x00. @progbits . 0x00. 0x00. 0x5f736f63 . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . Introduced in PTX ISA version 1. 0x736d6172 .4byte 0x000006b5. Table 139.debug_info .file .PTX ISA Version 2.4byte label .byte 0x2b.quad int64-list // comma-separated hexadecimal integers in range [0. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. @@DWARF dwarf-string dwarf-string may have one of the . 0x00.byte 0x00. 0x00000364.4byte . 0x00.264-1] .0.

. .232-1] .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x5f736f63 0x6150736f. 0x00. Debugging Directives: .b8 byte-list // comma-separated list of integers in range [0. Debugging Directives: . .section section_name { dwarf-lines } dwarf-lines have the following formats: .264-1] .b64 int64-list // comma-separated list of integers in range [0.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .loc . 0x63613031.b32 label . replaces @@DWARF syntax.debug_info . 0x00000364. 0x00.b32 0x000006b5. Supported on all target architectures.. 0x00. 2010 167 .b8 0x00.0.section . 0x00.Chapter 10..file . Supported on all target architectures.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Source file location. Supported on all target architectures. 0x00 0x61395a5f.b8 0x2b. 0x00.loc line_number January 24. .b32 0x6e69616d.b32 int32-list // comma-separated list of integers in range [0.b32 . } 0x02.255] . . Directives Table 140.debug_pubnames { ..0. Source file information.section .0.file filename Table 142. . Debugging Directives: . 0x736d6172 0x00 Table 141.section Syntax PTX section definition. 0x00.

visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. // foo is defined in another module Table 144. Linking Directives: .visible identifier Declares identifier to be externally visible. Introduced in PTX ISA version 1.0. Linking Directives: .6.PTX ISA Version 2. // foo will be externally visible 168 January 24.0 10. Introduced in PTX ISA version 1.visible .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Linking Directives .extern .b32 foo.extern identifier Declares identifier to be defined externally. .b32 foo. 2010 .visible .global . .global .extern . .0.extern . . Supported on all target architectures. Supported on all target architectures.visible Table 143.

3 PTX ISA 1.Chapter 11. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 1.0 CUDA 2.0 January 24. The release history is as follows.2 PTX ISA 1.1 PTX ISA 1.1 CUDA 2. and the remaining sections provide a record of changes in previous releases. CUDA Release CUDA 1.5 PTX ISA 2.2 CUDA 2.0.0 driver r195 PTX ISA Version PTX ISA 1.3 driver r190 CUDA 3.4 PTX ISA 1. 2010 169 . The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 PTX ISA 1.1 CUDA 2.

When code compiled for sm_1x is executed on sm_20 devices. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. These are indicated by the use of a rounding modifier and require sm_20.f32. A single-precision fused multiply-add (fma) instruction has been added. Changes in Version 2. while maximizing backward compatibility with legacy PTX 1.f32 for sm_20 targets. The changes from PTX ISA 1.0 for sm_20 targets. Both fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2.rm and .ftz and . Instructions testp and copysign have been added.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The goal is to achieve IEEE 754 compliance wherever possible.f32 require a rounding modifier for sm_20 targets.PTX ISA Version 2.f32 maps to fma.1. • • • • • 170 January 24.sat modifiers.f32 and mad. Single. The mad.ftz modifier may be used to enforce backward compatibility with sm_1x.x code and sm_1x targets. The . 2010 .rn.rp rounding modifiers for sm_20 targets.1.and double-precision div. Single-precision add.0 11. and mul now support .f32 instruction also supports . rcp.1.f32 requires sm_20. The mad.1. New Features 11. sub. and sqrt with IEEE 754 compliant rounding have been added.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 11. mad. fma. The fma.1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.1.

1.1. has been added. Other new features Instructions ld. clz.gt} have been added. isspacep.arrive instruction has been added. e.Chapter 11. Instruction sust now supports formatted surface stores. Video instructions (includes prmt) have been added.add. %lanemask_{eq. prefetchu. brev. has been added.ballot. January 24.ge.b32. .2. has been added.maxnctapersm directive was deprecated and replaced with . bfe and bfi.clamp modifiers.red}. Instructions bar. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. has been added. and red now support generic addressing. and shared addresses to generic address and vice-versa has been added. .1.red. ldu. vote.{and. membar. Instruction cvta for converting global. popc. have been added.3. A “count leading zeros” instruction. has been added. Release Notes 11. ldu. Cache operations have been added to instructions ld. New special registers %nsmid. cvta. Surface instructions support additional .minnctapersm to better match its behavior and usage. Instructions prefetch and prefetchu have also been added. prefetch. 11.pred have been added. A “vote ballot” instruction. bfind. 2010 171 .or}. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.le. bar now supports optional thread count and register operands. The bar instruction has been extended as follows: • • • A bar. has been added. A “find leading non-sign bit” instruction.popc.u32 and bar.shared have been extended to handle 64-bit data types for sm_20 targets.sys.lt. has been added. The .red}.section. New instructions A “load uniform” instruction. %clock64. Bit field extract and insert instructions. A “bit reversal” instruction. A system-level membar instruction. A “population count” instruction.1.zero.red. st. A new directive. atom.clamp and . and sust. suld. local. Instructions {atom.g. st. Instructions {atom.f32 have been implemented. for prefetching to specified level of memory hierarchy.

5 and later. See individual instruction descriptions for details.5. 172 January 24.version is 1. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. . call suld.p sust. has been fixed. stack-based ABI is unimplemented.max} are not implemented.1.p. the correct number is sixteen. Instruction bra.3.u32. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. Formatted surface store with .4 and earlier. The underlying.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. if . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. Semantic Changes and Clarifications The errata in cvt.red}. 2010 . cvt.0 11.f32 type is unimplemented.1. To maintain compatibility with legacy PTX code.{u32. {atom.ftz for PTX ISA versions 1. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. or .PTX ISA Version 2. where .f32. Support for variadic functions and alloca are unimplemented.s32.target sm_1x.{min.f32} atom.2. Formatted surface load is unimplemented.4 or earlier. In PTX version 1.s32. 11.ftz (and cvt for .

with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. { … } // do not unroll any loop in this function . Ignored for sm_1x targets. … @p bra L1_end. L1_end: … } // do not unroll this loop January 24. 2010 173 . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma Strings This section describes the . The “nounroll” pragma is allowed at module. including loops preceding the . and statement levels.entry foo (…) .pragma. disables unrolling of0 the loop for which the current block is the loop header. . Table 145. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.0. . Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.pragma “nounroll”. Supported only for sm_20 targets. L1_body: … L1_continue: bra L1_head. Descriptions of . entry-function.pragma strings defined by ptxas. Note that in order to have the desired effect at statement level.pragma “nounroll”.pragma “nounroll”.func bar (…) { … L1_head: .Appendix A. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. disables unrolling for all loops in the entry function body.

0 174 January 24. 2010 .PTX ISA Version 2.

This publication supersedes and replaces all information previously supplied. Specifications mentioned in this publication are subject to change without notice. DIAGNOSTICS. CUDA. NVIDIA Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation. MERCHANTABILITY. DRAWINGS. “MATERIALS”) ARE BEING PROVIDED “AS IS. AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT. Other company and product names may be trademarks of the respective companies with which they are associated. NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use. and Tesla are trademarks or registered trademarks of NVIDIA Corporation in the United States and other countries. Copyright © 2010 NVIDIA Corporation. . AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY. No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation. EXPRESSED. REFERENCE BOARDS.Notice ALL NVIDIA DESIGN SPECIFICATIONS. AND FITNESS FOR A PARTICULAR PURPOSE. LISTS. Information furnished is believed to be accurate and reliable. However. Trademarks NVIDIA. the NVIDIA logo.” NVIDIA MAKES NO WARRANTIES. IMPLIED. All rights reserved. OR OTHERWISE WITH RESPECT TO THE MATERIALS. FILES. STATUTORY.

Sign up to vote on this title
UsefulNot useful