NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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............................ 43 6.....2..................................................................... 5.......................................... 41 Source Operands............................ 41 Using Addresses............................. 42 Addresses as Operands ...........................4...... Texture.............. 38 Initializers ........................................................................................5...............................2.......... 6................................. 5....................3.............................................................................. 5.... 2010 ............................. Type Conversion......................................5.... 33 5... 33 Fundamental Types ............................ 27 5...................2....................................................................... 28 Constant State Space .............................................................................................. 29 Parameter State Space ......4.................................4........ Types.............. 47 Chapter 7.........1................................... Abstracting the ABI ................................... 5................................... 38 Alignment .5............................................. 5.............1...................6.............. Operand Type Information .............3............................................... State Spaces....... State Spaces ............................ and Surface Types ....4........................ 6...................................... 44 Scalar Conversions ........ 41 Destination Operands ....3..........4.1..........5.............. 5............................... 44 Rounding Modifiers ..................................... Operand Costs ................................ 37 Array Declarations ..........1....4................................................................5...................... 25 Chapter 5..................................................................... 5....... 42 Arrays as Operands ..................................................................4................................. 6.................. 41 6...........6.. 6................................. and Variables ...... 5.....................2.................... Sampler.......................4.............5....................................................3............... 32 Texture State Space (deprecated) ................................... 28 Special Register State Space . 29 Local State Space ............... 32 5..................................................... Instruction Operands..6.............2........................ Chapter 6.......... 37 Vectors ....................................... 5................................................................................................................................................4......................1.. Summary of Constant Expression Evaluation Rules .................................................................. 6.....6.... Types ..........................1........................... 39 5....................................................... 39 Parameterized Variable Names ...............4........................................ 30 Shared State Space...... 46 6......... Arrays.....................................PTX ISA Version 2........................1...........1...............................................................................................................7..................................0 4............1................ 33 Restricted Use of Sub-Word Sizes ... 6..................... 49 7.............4...4.1..1........4. Function declarations and definitions .. 5........1....................................4....................................1.......... 43 Labels and Function Names as Operands ............................... 37 Variable Declarations .1............ 34 Variables ........ 27 Register State Space ............... 6.8...............1..... 49 ii January 24..................................................................................... and Vectors .................................. 6......2.... 6........ 5..................................... 29 Global State Space .......... 5.........2....................................... 5........................ 5..................................................1.......2. 5............................................................. 5....................................................................3.......................... 43 Vectors as Operands .4...................2.....................................................

.................. Instructions ........................... 100 Logic and Shift Instructions ............................9.................................. 8.... 55 Predicated Execution .6...................1..................................5......................................... 8.............................................................. 157 Specifying Kernel Entry Points and Functions ........................ 8.................. 56 Comparisons .2............................. 62 Machine-Specific Semantics of 16-bit Code ...................................... Instruction Set ................................. 55 PTX Instructions ..............7.............................. 104 Data Movement and Conversion Instructions .... 8........................................................ 11...7.......................................... 81 Comparison and Selection Instructions ............................... 140 Miscellaneous Instructions. 8.......... 8......................2........................................................................... 55 8.... 58 8...............2... 10......................................7...4......7.................... 8............... 8.................2......................................... Special Registers ...................... 170 New Features ............... 8.1....6..1........................................................................................................................................................................................................... 160 Performance-Tuning Directives ... Chapter 9........... 8... 10...............................................................................3.......4............ 63 Floating-Point Instructions ...........4............................. Divergence of Threads in Control Constructs ................................... Format and Semantics of Instruction Descriptions .... 57 Manipulating Predicates .......................................................................................1......................................................... 11.....7.. 8...7.3..... 162 Debugging Directives ........................................................................................................ 8........................................................................8.....................1...7...............0 ............................................. 10..............................................7. 166 Linking Directives ....... 172 January 24...............................................................................3.................................... 8......... 169 11...... 129 Parallel Synchronization and Communication Instructions .................... 62 8.................................................. Release Notes ......4........ PTX Version and Target Directives .... Changes from PTX 1..........................................3........................1.....................7................................... 122 Control Flow Instructions ....... 10... 108 Texture and Surface Instructions ................................. 132 Video Instructions ................ 149 Chapter 10........................................... Type Information for Instructions and Operands ......................................7....................................................1................ 11. 8............................... 7........ 168 Chapter 11................................2.. 7............................5.................. 2010 iii ...... 60 8...........3......................... Directives ......3................................... 157 10............................................. 59 Operand Size Exceeding Instruction-Type Size .............1.................. 62 Semantics ......................... 53 Alloca ...........................................1........................................2... 54 Chapter 8...........................................................1.....6..................................... 147 8....... 8......1.......1......7...........................................................................1.............. 172 Unimplemented Features Remaining ................ 8............ 52 Variadic functions .................... Changes in Version 2......7................10........x ................................................6..... 63 Integer Arithmetic Instructions ......7..................................................................3...... 170 Semantic Changes and Clarifications ..........................

..................pragma Strings................ 2010 ............. Descriptions of ...0 Appendix A..... 173 iv January 24...PTX ISA Version 2..........

Table 24.............................................................................. 18 Reserved Instruction Keywords .......................................................................... 68 Integer Arithmetic Instructions: mul24 ... Table 21................................. Table 27... Table 22............ 66 Integer Arithmetic Instructions: mul .............................. Table 20........................... Table 3....................... 27 Properties of State Spaces ................................................ Table 4................................... Table 13....... 58 Floating-Point Comparison Operators Testing for NaN ............ Table 10.............................cc ........ Table 25.................................................................................. 46 Cost Estimates for Accessing State-Spaces .............................................................................. Table 26.......................... Table 31........................ 58 Type Checking Rules ............................................. Table 8...cc ........... 59 Relaxed Type-checking Rules for Source Operands ................................ 67 Integer Arithmetic Instructions: mad ................. Table 16........................ 57 Floating-Point Comparison Operators Accepting NaN ...................... Unsigned Integer.......... 33 Opaque Type Fields in Unified Texture Mode .......................... 71 January 24....... 19 Predefined Identifiers ...... 69 Integer Arithmetic Instructions: mad24 .. and Bit-Size Types .......... 57 Floating-Point Comparison Operators ......................................................... Table 23........................................................... 66 Integer Arithmetic Instructions: subc . Table 2.. PTX Directives ................... 45 Floating-Point Rounding Modifiers ......................... Table 14................. 65 Integer Arithmetic Instructions: addc ...................................................................................................................................................................................................................... 2010 v ............................. Table 5.... Table 18............... Table 11............... Table 6...................................................................................................................................List of Tables Table 1............ 35 Opaque Type Fields in Independent Texture Mode ....................................... Table 28. Table 7........................................... Table 30................................................................................................................................................................ 64 Integer Arithmetic Instructions: add... 28 Fundamental Type Specifiers .............................................................................. 65 Integer Arithmetic Instructions: sub............... Table 19............................... 64 Integer Arithmetic Instructions: sub ..................... 70 Integer Arithmetic Instructions: sad ............. 20 Operator Precedence .......... Table 29..................................................................... Table 15......................................................... Table 32...... 25 State Spaces .... 47 Operators for Signed Integer.... 60 Relaxed Type-checking Rules for Destination Operands.............................................. 46 Integer Rounding Modifiers ..... 35 Convert Instruction Precision and Format .......... Table 17....................................................................................................................... Table 9............................... Table 12....... 61 Integer Arithmetic Instructions: add ...................................................................................... 23 Constant Expression Evaluation Rules .........................

........................ 74 Integer Arithmetic Instructions: clz . Table 59........................................................................... 88 Floating-Point Instructions: div .................................................................... 83 Floating-Point Instructions: add ..................... Table 40..............0 Table 33... 93 Floating-Point Instructions: sqrt ...............................................................PTX ISA Version 2.............................................................................................................................. 73 Integer Arithmetic Instructions: max .................................................. Table 47........................................................ 78 Integer Arithmetic Instructions: prmt ....... 79 Summary of Floating-Point Instructions ............................................................ Table 66....................... Table 42.............. 103 Comparison and Selection Instructions: slct ......... 102 Comparison and Selection Instructions: selp ............ 71 Integer Arithmetic Instructions: abs ............................... 75 Integer Arithmetic Instructions: brev .................................... 94 Floating-Point Instructions: rsqrt ..................................... 95 Floating-Point Instructions: sin ............................................................... 90 Floating-Point Instructions: abs ........... Table 53.... Table 67.......... Table 48................ Table 46.......................... Table 50...................... Table 35............................................ Table 55....... Table 45............................................................ 103 vi January 24... Table 36.............................................................................................................................. Table 41............... 86 Floating-Point Instructions: fma ........................... 72 Integer Arithmetic Instructions: min ......................................................................................................................... Table 54........ 84 Floating-Point Instructions: sub ........................................ Table 68..... Table 37..... 82 Floating-Point Instructions: testp ... Table 58...................................... Table 56................... Table 38........................................................................................... 98 Floating-Point Instructions: ex2 ................................ Table 64............................ 97 Floating-Point Instructions: lg2 . Table 49.. 96 Floating-Point Instructions: cos ...... 85 Floating-Point Instructions: mul ............................... 87 Floating-Point Instructions: mad ................................................................. 77 Integer Arithmetic Instructions: bfi ....................... Table 69.................... Table 65.................................................................................................. Table 62........................................................................................ 2010 ....................................................................................... 91 Floating-Point Instructions: neg ..... 74 Integer Arithmetic Instructions: bfind ............................................. Table 61. 92 Floating-Point Instructions: max .......... Integer Arithmetic Instructions: div .................................................... 99 Comparison and Selection Instructions: set ................................................. 71 Integer Arithmetic Instructions: rem ............................... Table 52.............................................................................. 83 Floating-Point Instructions: copysign ......................... 101 Comparison and Selection Instructions: setp ................... 73 Integer Arithmetic Instructions: popc ......................................................... Table 34................... Table 63............................ Table 57....................................... Table 51..... Table 44............................................................ 91 Floating-Point Instructions: min ........................................ 76 Integer Arithmetic Instructions: bfe ... Table 43........................................................................................... Table 60.................... 92 Floating-Point Instructions: rcp ................ 72 Integer Arithmetic Instructions: neg ....................................................................................... Table 39.........................................................

............................................................................................. Table 99........................... Table 103................... 129 Control Flow Instructions: @ ................ Table 97.......... 134 Parallel Synchronization and Communication Instructions: atom ....... Table 91............ 120 Texture and Surface Instructions: tex .......................... Table 87................. 105 Logic and Shift Instructions: xor .................................................. 130 Control Flow Instructions: call .............. Table 106..................... Table 79................ 125 Texture and Surface Instructions: sust .......................... 106 Logic and Shift Instructions: not ..... 130 Control Flow Instructions: ret ...................... Table 78...... 107 Cache Operators for Memory Load Instructions ..................... 119 Data Movement and Conversion Instructions: cvt ........... Table 96............ vmin..................... Table 92...... 142 Video Instructions: vshl....... Table 77................... Table 98....................................................................... Table 89.......... 107 Logic and Shift Instructions: shr .................................. prefetchu ........................................ Logic and Shift Instructions: and ........................................ Table 85....................................................................................... 124 Texture and Surface Instructions: suld ...................... 133 Parallel Synchronization and Communication Instructions: membar .......... 137 Parallel Synchronization and Communication Instructions: vote ............................ Table 73.................. 129 Control Flow Instructions: bra ...................... Table 83....................................... Table 75......... Table 93.......................................................................... 131 Control Flow Instructions: exit ............... Table 71...... vshr ......... Table 94......... 111 Data Movement and Conversion Instructions: mov ................. 106 Logic and Shift Instructions: cnot ............................ 135 Parallel Synchronization and Communication Instructions: red ................. Table 72.......... vmax .Table 70............................... Table 88................... Table 105........................................................................ 109 Cache Operators for Memory Store Instructions ......... 127 Texture and Surface Instructions: suq ................................................... 115 Data Movement and Conversion Instructions: st .................... 118 Data Movement and Conversion Instructions: isspacep .. 131 Parallel Synchronization and Communication Instructions: bar ........................................................................................................ vabsdiff...................................................... Table 82.... 106 Logic and Shift Instructions: shl .... 2010 vii .......................................................... vsub........................................................................ Table 74... Table 90................................................................................................................................................................ 112 Data Movement and Conversion Instructions: ld . Table 86............................................................. 110 Data Movement and Conversion Instructions: mov ........ Table 84........ Table 101........... Table 102... 113 Data Movement and Conversion Instructions: ldu ....... Table 76...... 116 Data Movement and Conversion Instructions: prefetch............................................................. 126 Texture and Surface Instructions: sured........... 128 Control Flow Instructions: { } ... Table 95........... 123 Texture and Surface Instructions: txq . 139 Video Instructions: vadd................................... Table 81.... Table 104......................... Table 80...................................................................... Table 100.......................................................... 119 Data Movement and Conversion Instructions: cvta ....................... 143 January 24......................................................... 105 Logic and Shift Instructions: or ..

.......... 152 Special Registers: %smid .... Table 133................................ 156 Special Registers: %pm0................................file .............................maxntid ...... 154 Special Registers: %lanemask_ge .......................... 163 Performance-Tuning Directives: ................... 167 Linking Directives: ....... 161 Performance-Tuning Directives: ....................... Table 117.................................................... Table 125.PTX ISA Version 2... Table 137...................extern......................................... 150 Special Registers: %laneid .................... 147 Special Registers: %tid .................................................................................. 163 Performance-Tuning Directives: .......... 158 Kernel and Function Directives: .. Table 135....................................................... Table 141......maxnctapersm (deprecated) ............................... 167 Debugging Directives: .......... Table 142.............. 147 Miscellaneous Instructions: pmevent.................................. 153 Special Registers: %lanemask_eq ..........version...... 157 PTX File Directives: ............................................................................................................. Table 116......... 154 Special Registers: %lanemask_lt ............................................... 167 Debugging Directives: .............................. 166 Debugging Directives: .............. 150 Special Registers: %ntid ..func ............................................................................................................ Table 134............. Table 143............... 165 Debugging Directives: @@DWARF ........................................................... Table 115......................... 147 Miscellaneous Instructions: brkpt ........ 156 Special Registers: %clock64 ......... 168 viii January 24.......................................................minnctapersm .............................................................................................................. Table 110....................... Table 108..... 146 Miscellaneous Instructions: trap ........... Table 122............... 2010 ............................................................. Table 123.................................................................... 151 Special Registers: %ctaid . %pm1.................... 156 PTX File Directives: ........................................................................................ Table 128.................. Table 114...... Table 131............. 155 Special Registers: %clock ........................................... Table 121.................................... Table 113. Table 136...entry.......... Table 124................................................................................................................................................................. Table 126..... Table 109.......................... Table 130........................... %pm2....... 153 Special Registers: %gridid ........................................................................................................................................................... Table 118... %pm3 ...................................................... 151 Special Registers: %warpid ..... Table 140................. Table 120...................... 164 Performance-Tuning Directives: ........ 144 Video Instructions: vset....................... Table 129...... Table 119......pragma ............................ Table 139...................................................................................................................................... Table 112...............maxnreg ......................... Table 111........................... 153 Special Registers: %nsmid ............................. 151 Special Registers: %nwarpid .............................. 164 Performance-Tuning Directives: ...... 154 Special Registers: %lanemask_le .......................................section ......... Table 132........................................................0 Table 107............ 152 Special Registers: %nctaid ........... Table 127.....................................................................target .....................loc ..................................................................... Video Instructions: vmad ... 155 Special Registers: %lanemask_gt .. Table 138..... 160 Kernel and Function Directives: ......

.................visible....................... 168 Pragma Strings: “nounroll” ....................................................... 173 January 24... Linking Directives: ......... 2010 ix .................................. Table 145................Table 144..............

0 x January 24.PTX ISA Version 2. 2010 .

PTX defines a virtual machine and ISA for general purpose parallel thread execution. the memory access latency can be hidden with calculations instead of big data caches. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. January 24. multithreaded.1. PTX exposes the GPU as a data-parallel computing device. there is a lower requirement for sophisticated flow control. In fact. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. 1. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. and because it is executed on many data elements and has high arithmetic intensity. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers.Chapter 1. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. 2010 1 . Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Similarly. image and media processing applications such as post-processing of rendered images. video encoding and decoding. from general signal processing or physics simulation to computational finance or computational biology. and pattern recognition can map image blocks and pixels to parallel processing threads.2. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. the programmable GPU has evolved into a highly parallel. image scaling. which are optimized for and translated to native target-architecture instructions. 1. Because the same program is executed for each data element. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Introduction This document describes PTX. PTX programs are translated at install time to the target hardware instruction set. Data-parallel processing maps data elements to parallel processing threads. many-core processor with tremendous computational horsepower and very high memory bandwidth. high-definition 3D graphics. stereo vision.

Most of the new features require a sm_20 target.rp rounding modifiers for sm_20 targets. performance kernels. Improved Floating-Point Support A main area of change in PTX 2. including integer.sat modifiers. 1. Provide a code distribution ISA for application and middleware developers. addition of generic addressing to facilitate the use of general-purpose pointers. Provide a machine-independent ISA for C/C++ and other compilers to target.0 PTX ISA Version 2.x features are supported on the new sm_20 target. Facilitate hand-coding of libraries. fma. Single-precision add. which map PTX to specific target machines. reduction. and the introduction of many new instructions.x code will continue to run on sm_1x targets as well. The mad.x. barrier.3.f32 requires sm_20. The changes from PTX ISA 1. The main areas of change in PTX 2.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.rn. • • • 2 January 24.f32 instruction also supports .3.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. PTX 2.0 are improved support for IEEE 754 floating-point operations. When code compiled for sm_1x is executed on sm_20 devices. sub.f32 require a rounding modifier for sm_20 targets.1. and mul now support .rm and .0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. The mad. Legacy PTX 1. and all PTX 1. A “flush-to-zero” (.ftz and .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. and architecture tests. memory.0 is in improved support for the IEEE 754 floating-point standard. Provide a common source-level ISA for optimizing code generators and translators.f32 and mad.f32.PTX ISA Version 2. Both fma. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. and video instructions. mad.f32 maps to fma.0 is a superset of PTX 1. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. A single-precision fused multiply-add (fma) instruction has been added. Achieve performance in compiled applications comparable to native GPU performance. atomic.f32 for sm_20 targets. 2010 . 1. Instructions marked with . surface.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.ftz) modifier may be used to enforce backward compatibility with sm_1x. PTX ISA Version 2. The fma.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.

allowing memory instructions to access these spaces without needing to specify the state space. rcp. Surface instructions support additional clamp modifiers. Instruction cvta for converting global. e. local. PTX 2. and shared state spaces.0. • Taken as a whole. and sqrt with IEEE 754 compliant rounding have been added. i.2.zero. so recursion is not yet supported. and vice versa. 2010 3 .. ldu.3. and Application Binary Interface (ABI). atom.0. 1. New Instructions The following new instructions. and shared addresses to generic addresses. suld. prefetch.3.3. 1.3. st. local. These are indicated by the use of a rounding modifier and require sm_20. Introduction • Single.and double-precision div. January 24. for prefetching to specified level of memory hierarchy. cvta. . Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. In PTX 2. these changes bring PTX 2. st.4. Surface Instructions • • Instruction sust now supports formatted surface stores.Chapter 1. special registers. Generic addressing unifies the global.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Cache operations have been added to instructions ld. local. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.0 closer to full compliance with the IEEE 754 standard. Instructions prefetch and prefetchu have been added. prefetchu. Generic Addressing Another major change is the addition of generic addressing. isspacep. stack-based ABI.clamp and . instructions ld. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. an address that is the same across all threads in a warp. NOTE: The current version of PTX does not implement the underlying. and directives are introduced in PTX 2. stack layout. 1. and sust. and red now support generic addressing. Support for an Application Binary Interface Rather than expose details of a particular calling convention. A new cvta instruction has been added to convert global. Instructions testp and copysign have been added. and shared addresses to generic address and vice-versa has been added.g.e.

New special registers %nsmid. Instructions {atom. Other Extensions • • • Video instructions (includes prmt) have been added. 4 January 24.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. %clock64. bar now supports an optional thread count and register operands.or}. . A bar. Barrier Instructions • • A system-level membar instruction.add.sys. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.red}. A “vote ballot” instruction.u32 and bar.red.ballot.b32.lt.f32 have been added.red.section. vote.gt} have been added.le. bfi bit field extract and insert popc clz Atomic. and Vote Instructions • • • New atomic and reduction instructions {atom.red}. %lanemask_{eq.arrive instruction has been added.shared have been extended to handle 64-bit data types for sm_20 targets. A new directive. 2010 .popc.PTX ISA Version 2. Instructions bar. has been added. membar.{and. Reduction.ge.pred have been added. has been added.

Chapter 3 gives an overview of the PTX virtual machine model.Chapter 1. Chapter 8 describes the instruction set. Chapter 5 describes state spaces. Chapter 7 describes the function and call syntax. calling convention. Chapter 6 describes instruction operands. Chapter 11 provides release notes for PTX Version 2.4. Introduction 1. types.0. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. January 24. and variable declarations. Chapter 9 lists special registers. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 10 lists the assembly directives supported in PTX. 2010 5 . Chapter 4 describes the basic syntax of the PTX language.

PTX ISA Version 2. 2010 .0 6 January 24.

Each thread has a unique thread identifier within the CTA. tid. To coordinate the communication of the threads within the CTA. (with elements tid. a portion of an application that is executed many times. Threads within a CTA can communicate with each other. Each CTA has a 1D. A cooperative thread array. 2010 7 . ntid.1. or host: In other words. 2D. and select work to perform. compute-intensive portions of applications running on the host are off-loaded onto the device. January 24. 2.z). Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2D. compute addresses. work.y. Each CTA thread uses its thread identifier to determine its assigned role. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. It operates as a coprocessor to the main CPU.2. or CTA. Programs use a data parallel decomposition to partition inputs. data-parallel. is an array of threads that execute a kernel concurrently or in parallel. or 3D CTA. To that effect. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Programming Model 2. but independently on different data. The thread identifier is a three-element vector tid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. and results across the threads of the CTA.2.x. The vector ntid specifies the number of threads in each CTA dimension.z) that specifies the thread’s position within a 1D.x. More precisely.y.Chapter 2. assign specific input and output positions. and tid. and ntid. 2. can be isolated into a kernel function that is executed on the GPU as many different threads. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. or 3D shape specified by a three-element vector ntid (with elements ntid. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.1.

A warp is a maximal subset of threads from a single CTA. because threads in different CTAs cannot communicate and synchronize with each other. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. 2. so PTX includes a run-time immediate constant. 2D . %ntid. Each grid of CTAs has a 1D.2. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. such that the threads execute the same instructions at the same time.0 Threads within a CTA execute in SIMT (single-instruction. so that the total number of threads that can be launched in a single kernel invocation is very large. multiple-thread) fashion in groups called warps. Typically. CTAs that execute the same kernel can be batched together into a grid of CTAs. Each grid also has a unique temporal grid identifier (gridid). The warp size is a machine-dependent constant. read-only special registers %tid.PTX ISA Version 2. Some applications may be able to maximize performance with knowledge of the warp size. or sequentially.2. WARP_SZ. 2010 . However. This comes at the expense of reduced thread communication and synchronization. a warp has 32 threads. 8 January 24. and %gridid. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). or 3D shape specified by the parameter nctaid. Threads within a warp are sequentially numbered. depending on the platform. Multiple CTAs may execute concurrently and in parallel. The host issues a succession of kernel invocations to the device. which may be used in any instruction where an immediate operand is allowed. Threads may read and use these values through predefined. %ctaid. %nctaid.

2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (0. 1) Thread (1. 1) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2010 9 . 0) CTA (1. 0) Thread (3. 2) Thread (1. 2) Thread (4. Thread Batching January 24. 1) Thread (4. A grid is a set of CTAs that execute independently. 0) Thread (1. 0) CTA (2. Figure 1. 0) CTA (0. 0) Thread (0. 0) Thread (2. 1) Thread (0. 2) Thread (2. 1) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (3.Chapter 2. 0) Thread (4. 1) CTA (2. 1) CTA (1.

Finally. constant. or.PTX ISA Version 2. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.3. respectively. The global. Each thread has a private local memory. and texture memory spaces are persistent across kernel launches by the same application. Both the host and the device maintain their own local memory. The device memory may be mapped and read or written by the host. 2010 . as well as data filtering. for some specific data formats. referred to as host memory and device memory. all threads have access to the same global memory. and texture memory spaces are optimized for different memory usages. The global. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.0 2. 10 January 24. Texture memory also offers different addressing modes. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant. for more efficient transfer.

2) Block (1. 0) Block (0. 1) Block (1. 0) Block (1. Memory Hierarchy January 24. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (0. 1) Block (1. 1) Block (2.Chapter 2. 0) Block (2. 2010 11 . 1) Grid 1 Global memory Block (0. 2) Figure 2. 0) Block (1. 0) Block (0.

PTX ISA Version 2. 2010 .0 12 January 24.

and on-chip shared memory. so full efficiency is realized when all threads of a warp agree on their execution path. a voxel in a volume. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and executes concurrent threads in hardware with zero scheduling overhead. the warp serially executes each branch path taken. The multiprocessor maps each thread to one scalar processor core. (This term originates from weaving. A warp executes one common instruction at a time. To manage hundreds of threads running several different programs. the threads converge back to the same execution path. and each scalar thread executes independently with its own instruction address and register state. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). January 24. and when all paths complete. a cell in a grid-based computation). it splits them into warps that get scheduled by the SIMT unit. It implements a single-instruction barrier synchronization. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. 2010 13 .Chapter 3. manages. The way a block is split into warps is always the same. As thread blocks terminate.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. the multiprocessor employs a new architecture we call SIMT (single-instruction. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. If threads of a warp diverge via a data-dependent conditional branch. each warp contains threads of consecutive. new blocks are launched on the vacated multiprocessors.1. schedules. disabling threads that are not on that path. multiple-thread). the first parallel thread technology. Parallel Thread Execution Machine Model 3. Branch divergence occurs only within a warp. The threads of a thread block execute concurrently on one multiprocessor. a multithreaded instruction unit. increasing thread IDs with the first warp containing thread 0. manages. allowing. When a multiprocessor is given one or more thread blocks to execute. A multiprocessor consists of multiple Scalar Processor (SP) cores. When a host program invokes a kernel grid. The multiprocessor SIMT unit creates. The multiprocessor creates. and executes threads in groups of parallel threads called warps. At every instruction issue time. different warps execute independently regardless of whether they are executing common or disjointed code paths. for example.

Vector architectures. the kernel will fail to launch. whereas SIMT instructions specify the execution and branching behavior of a single thread. For the purposes of correctness. If there are not enough registers or shared memory available per multiprocessor to process at least one block. write to that location occurs and they are all serialized. In practice. modifies. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks.PTX ISA Version 2. • The local and global memory spaces are read-write regions of device memory and are not cached. scalar threads. each read. the programmer can essentially ignore the SIMT behavior.0 SIMT architecture is akin to SIMD (Single Instruction. the number of serialized writes that occur to that location and the order in which they occur is undefined. SIMT enables programmers to write thread-level parallel code for independent. A key difference is that SIMD vector organizations expose the SIMD width to the software. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. A multiprocessor can execute as many as eight thread blocks concurrently. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. modify. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. however. and writes to the same location in global memory for more than one of the threads of the warp. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. on the other hand. As illustrated by Figure 3. 2010 . which is a read-only region of device memory. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. 14 January 24. In contrast with SIMD vector machines. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. but the order in which they occur is undefined. If an atomic instruction executed by a warp reads. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. but one of the writes is guaranteed to succeed. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. as well as data-parallel code for coordinated threads. require the software to coalesce loads into vectors and manage divergence manually. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. which is a read-only region of device memory.

2010 15 .Chapter 3. Hardware Model January 24. Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

PTX ISA Version 2.0 16 January 24. 2010 .

Each PTX file must begin with a .target directive specifying the target architecture assumed. Syntax PTX programs are a collection of text source files. The C preprocessor cpp may be used to process PTX source files.2. Comments Comments in PTX follow C/C++ syntax. #endif. and using // to begin a comment that extends to the end of the current line. All whitespace characters are equivalent. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. using non-nested /* and */ for comments that may span multiple lines. Lines beginning with # are preprocessor directives. 4. Source Format Source files are ASCII text. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #ifdef. #if. #line. #else. #define. January 24. The following are common preprocessor directives: #include. PTX is case sensitive and uses lowercase for keywords. See Section 9 for a more information on these directives.version directive specifying the PTX language version. 4. Lines are separated by the newline character (‘\n’).Chapter 4. followed by a . Pseudo-operations specify symbol and addressing management. whitespace is ignored except for its use in separating tokens in the language.1. 2010 17 . Comments in PTX are treated as whitespace. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor.

ld.f32 array[N]. shl.3. All instruction keywords are reserved tokens in PTX.PTX ISA Version 2.3. address expressions.tex . r1. Table 1.3.local .maxntid . The guard predicate follows the optional label and precedes the opcode.minnctapersm . mov.1.sreg . and terminated with a semicolon. Directive Statements Directive keywords begin with a dot. . followed by source operands. 18 January 24. The guard predicate may be optionally negated. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. 2. or label names. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.5.b32 r1. where p is a predicate register.f32 r2.b32 add.global.maxnctapersm .shared . constant expressions.global . r2. The destination operand is first. array[r1].extern . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.b32 r1. written as @!p. Statements begin with an optional label and end with a semicolon.entry .visible 4. Instructions have an optional guard predicate which controls conditional execution. . r2.param .pragma . Statements A PTX statement is either a directive or an instruction.func . so no conflict is possible with user-defined identifiers.2.file PTX Directives .global start: . r2.reg .section .version . Operands may be register variables.align .reg .maxnreg . Instruction keywords are listed in Table 2.const .target . 0.b32 r1. and is written as @p. %tid. Examples: .loc .x. 2010 .0 4.

Chapter 4. Syntax Table 2. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. Table 3.0 4. except that the percentage sign is not allowed. PTX allows the percentage sign as the first character of an identifier. underscore. PTX predefines one constant and a small number of special registers that begin with the percentage sign. 2010 . %pm3 WARP_SZ 20 January 24. e. digits.g. Many high-level languages such as C and C++ follow similar rules for identifier names. digits. or percentage character followed by one or more letters. …. between user-defined variable names and compiler-generated names. listed in Table 3.4. or they start with an underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. dollar. The percentage sign can be used to avoid name conflicts.PTX ISA Version 2. or dollar characters.

u64. where the behavior of the operation depends on the operand types. 2010 21 . Unlike C and C++. and bit-size types. literals are always represented in 64-bit double-precision format. 4. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. These constants may be used in data initialization and as operands to instructions. octal.5. every integer constant has type .5. zero values are FALSE and non-zero values are TRUE.s64 or . Type checking rules remain the same for integer. the sm_1x and sm_20 targets have a WARP_SZ value of 32. To specify IEEE 754 doubleprecision floating point values. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. When used in an instruction or data initialization.1.s64) unless the value cannot be fully represented in . Syntax 4. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. For predicate-type data and instructions.2. hexadecimal. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. or binary notation. Constants PTX supports integer and floating-point constants and constant expressions. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. the constant begins with 0d or 0D followed by 16 hex digits. floating-point. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. Integer literals may be written in decimal. The syntax follows that of C.e. To specify IEEE 754 single-precision floating point values. 0[fF]{hexdigit}{8} // single-precision floating point January 24.Chapter 4. Floating-point literals may be written with an optional decimal point and an optional signed exponent. 4..s64 or the unsigned suffix is specified.5. integer constants are allowed and are interpreted as in C. the constant begins with 0f or 0F followed by 8 hex digits. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned..u64). The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. i. each integer constant is converted to the appropriate size based on the data or instruction type at its use. i. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. there is no suffix letter to specify size. in which case the literal is unsigned (.e.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64.u64 .u64) (. 2010 25 . Syntax 4.f64 integer .s64 .f64 same as source .f64 use usual conversions .Chapter 4.u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 converted type constant literal + ! ~ Cast Binary (. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 integer . or .u64 .f64 use usual conversions .6.u64 . Table 5.f64 converted type .f64 integer integer integer integer integer int ?.s64 .f64 : . .u64 same as 1st operand .s64.s64 .s64 .s64 . 2nd is .u64 .u64 .u64 1st unchanged.f64 use usual conversions .s64 .u64 .s64) + .s64 .s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .5.

2010 .PTX ISA Version 2.0 26 January 24.

pre-defined. Read-only. The list of state spaces is shown in Table 4. Types.reg . Addressable memory shared between threads in 1 CTA. Special registers. platform-specific. or Function or local parameters. access rights. 5.sreg . . 2010 27 . access speed. defined per-grid.const . State Spaces A state space is a storage area with particular characteristics.global . addressability. defined per-thread. Global texture memory (deprecated).tex January 24.1. and level of sharing between threads. Name State Spaces Description Registers. Kernel parameters. and these resources are abstracted in PTX through state spaces and data types. State Spaces.local . shared by all threads. private to each thread.Chapter 5. Global memory. and properties of state spaces are shown in Table 5. fast. Local memory. Shared. and Variables While the specific resources available in a given target GPU will vary.shared . read-only memory. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. All variables reside in some state space. The characteristics of a state space include its size. the kinds of resources will be common across platforms. Table 6.param .

2 Accessible via ld.param (used in functions) . or 128-bits. Registers differ from the other state spaces in that they are not fully addressable. causing changes in performance. and cvt instructions. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.1. 5. 28 January 24.local state space. When the limit is exceeded. it is not possible to refer to the address of a register. Register size is restricted.sreg) state space holds predefined.const . unsigned integer.global . register variables will be spilled to memory. The most common use of 8-bit registers is with ld. 32-. 2010 . the parameter is then located on the stack frame and its address is in the . For each architecture. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). Address may be taken via mov instruction. platform-specific registers.e. The number of registers is limited. Device function input parameters may have their address taken via mov. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . and will vary from platform to platform. Registers may have alignment boundaries required by multi-word loads and stores.param instructions.shared . clock counters. All special registers are predefined. Special Register State Space The special register (.PTX ISA Version 2. st. aside from predicate registers which are 1-bit. scalar registers have a width of 8-. 64-. Registers may be typed (signed integer.reg . floating point. and thread parameters. 1 Accessible only via the ld.1. Register State Space Registers (.param (as input to kernel) .2. CTA.0 Table 7. 16-.tex Restricted Yes No3 5.1.. or 64-bits. 3 Accessible only via the tex instruction. and performance monitoring registers. such as grid. predicate) or untyped.reg state space) are fast storage locations.param and st. 32-. i.param instruction. and vector registers have a width of 16-.sreg . or as elements of vector tuples.local .

For the current devices. Global memory is not sequentially consistent. Constant State Space The constant (. If no bank number is given.const[bank] modifier.Chapter 5. as in lock-free and wait-free style programming. Use ld. Global State Space The global (. Sequential consistency is provided by the bar. all addresses are in global memory are shared.const[2].1. Consider the case where one thread executes the following two assignments: a = a + 1.extern . The constant memory is organized into fixed size banks. the bank number must be provided in the state space of the load instruction. The size is limited. initialized by the host. For any thread in a context. and atom. For example. each pointing to the start address of the specified constant bank.sync instruction are guaranteed to be visible to any reads after the barrier instruction. st.global. Threads wait at the barrier until all threads in the CTA have arrived. It is the mechanism by which different CTAs and different grids can communicate. To access data in contant banks 1 through 10.const) state space is a read-only memory. ld. bank zero is used.const[2] . Module-scoped local memory variables are stored at fixed addresses.sync instruction.5.extern .b32 const_buffer[].const[2] . 2010 29 . Types. results in const_buffer pointing to the start of constant bank two. In implementations that support a stack. the store operation updating a may still be in flight. the stack is in local memory. Multiple incomplete array variables declared in the same bank become aliases. Threads must be able to do their work without waiting for other threads to do theirs.global) state space is memory that is accessible by all threads in a context.3. All memory writes prior to the bar. It is typically standard memory with cache. For example. and Variables 5.1. State Spaces. If another thread sees the variable b change. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.global to access global variables. whereas local memory variables declared January 24. Use ld. bank zero is used for all statically-sized constant variables. Banks are specified using the . [const_buffer+4]. where the size is not known at compile time. This reiterates the kind of parallelism available in machines that run PTX.b32 const_buffer[].1. The remaining banks may be used to implement “incomplete” constant arrays (in C. b = b – 1. This pointer can then be used to access the entire 64KB constant bank.local to access local variables.local and st. there are eleven 64KB banks.4.global. for example).b32 %r1. as it must be allocated on a perthread basis.local) is private memory for each thread to keep its own data. an incomplete array in bank 2 is accessed as follows: . 5. the declaration . where bank ranges from 0 to 10. By convention. Local State Space The local state space (. // load second word 5.

reg . Kernel Function Parameters Each kernel function definition includes an optional list of parameters. Parameter State Space The parameter (. These parameters are addressable.x supports only kernel function parameters in . In implementations that do not support a stack.6.PTX ISA Version 2. device function parameters were previously restricted to the register state space. all local memory variables are stored at fixed addresses and recursive function calls are not supported.u32 %ptr. %n.param . PTX code should make no assumptions about the relative locations or ordering of .param space variables. 2010 .param) state space is used (1) to pass input arguments from the host to the kernel.u32 %n.param instructions. The resulting address is in the .1.param.align 8 .u32 %n. (2a) to declare formal input and return parameters for device functions called from within kernel execution. Note: The location of parameter space is implementation specific.reg .u32 %ptr. For example. Note that PTX ISA versions 1. Values passed from the host to the kernel are accessed through these parameter variables using ld.6. No access protection is provided between parameter and global space in this case.param instructions.param .entry foo ( .u32 %n. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. 5. The kernel parameter variables are shared across all CTAs within a grid. Similarly. typically for passing large structures by value to a function.b32 len ) { .0 and requires target architecture sm_20. [%ptr].param . … 30 January 24.param. ld.param space.1. in some implementations kernel parameters reside in global memory.param.1.entry bar ( . The address of a kernel parameter may be moved into a register using the mov instruction.param state space and is accessed using ld.param state space. [N]. [buffer]. read-only variables declared in the . per-kernel versus per-thread). Therefore. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. … Example: . Example: .0 within a function or kernel body are allocated on the stack. ld.b8 buffer[64] ) { .f64 %d. 5. ld.b32 N. . The use of parameter state space for device function parameters is new to PTX ISA version 2. len.reg .f64 %d. mov. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). .

Function input parameters may be read via ld. Types. Aside from passing structures by value. st. It is not possible to use mov to get the address of a return parameter or a locally-scoped .s32 x.2.param. 2010 31 .b8 mystruct. is flattened.param space variable. dbl. it is illegal to write to an input parameter or read from a return parameter.b32 N.align 8 . . which declares a . .s32 [mystruct+8]. State Spaces. … } // code snippet from the caller // struct { double d.s32 %y. such as C structures larger than 8 bytes. the caller will declare a locally-scoped .param. Device Function Parameters PTX ISA version 2. a byte array in parameter space is used. }.reg .reg .reg .func foo ( .param. (4.0 extends the use of parameter space to device function parameters.param . . call foo. Note that the parameter will be copied to the stack if necessary. and Variables 5.f64 [mystruct+0]. The most common use is for passing objects by value that do not fit within a PTX register.param.b8 buffer[12] ) { . int y.reg . In this case. This will be passed by value to a callee.local and st.6. In PTX. ld.param byte array variable that represents a flattened C structure or union.1.local state space and is accessed via ld. January 24. … See the section on function call syntax for more details. Example: // pass object of type struct { double d.param space is also required whenever a formal parameter has its address taken within the called function.param formal parameter having the same size and alignment as the passed argument. and so the address will be in the .align 8 .param. x. the address of a function input parameter may be moved into a register using the mov instruction.param . } mystruct.f64 %d. ld.Chapter 5.reg .f64 %d. [buffer]. … st. Typically. mystruct).s32 %y.f64 dbl. . [buffer+8].local instructions. passed to foo … . . int y.param and function return parameters may be written using st. .

// // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.3 for the description of the . The . Shared State Space The shared (. For example. One example is broadcast. tex_d. Use ld.6 for its use in texture instructions. It is shared by all threads in a context. tex_f. 2010 . Shared memory typically has some optimizations to support the sharing.tex state space are equivalent to module-scoped .shared and st.tex . tex_c. The texture name must be of type . Physical texture resources are allocated on a per-module granularity. A texture’s base address is assumed to be aligned to a 16-byte boundary.tex . The . is equivalent to . a legacy PTX definitions such as . 32 January 24. An address in shared memory can be read and written by any thread in a CTA.tex directive will bind the named texture memory variable to a hardware texture identifier.u32 . Example: .8.u64. Another is sequential access from sequential threads.shared to access shared variables.texref variables in the .tex .PTX ISA Version 2. and programs should instead reference texture memory through variables of type .tex variables are required to be defined in the global scope.texref.texref tex_a. An error is generated if the maximum number of physical resources is exceeded.tex .u32 tex_a. Texture memory is read-only. 5.tex) state space is global memory accessed via the texture instruction.shared) state space is a per-CTA region of memory for threads in a CTA to share data. See Section 5. Texture State Space (deprecated) The texture (. tex_d.7. where all threads read from the same address. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 tex_a. and .1. and variables declared in the .1.u32 .u32 or .texref type and Section 8.0 5. Multiple names may be bound to the same physical texture identifier.tex .tex directive is retained for backward compatibility.u32 .7.global state space. where texture identifiers are allocated sequentially beginning with zero.global .

Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . so their names are intentionally short.f64 types. Types 5.pred Most instructions have one or more type specifiers.b8.2.u32. Types. .2.u8.b16. needed to fully specify instruction behavior. State Spaces. . 5.b32. . and instructions operate on these types. st. Two fundamental types are compatible if they have the same basic type and are the same size. .2.1. but typed variables enhance program readability and allow for better operand type checking. 2010 33 .f32 and .s16.u8.f32. and Variables 5. and converted using regular-width registers. Register variables are always of a fundamental type. .s64 . For convenience. A fundamental type specifies both a basic type and a size. Fundamental Types In PTX.f64 types.2. Operand types and sizes are checked against instruction types for compatibility. . stored. January 24. . In principle. and cvt instructions. .u16. All floating-point instructions operate only on .u64 .f16 floating-point type is allowed only in conversions to and from . stored. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.b8 instruction types are restricted to ld. . For example. all variables (aside from predicates) could be declared using only bit-size types. . The bitsize type is compatible with any fundamental type having the same size.b64 . and . The following table lists the fundamental type specifiers for each basic type: Table 8.s8. Restricted Use of Sub-Word Sizes The . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. so that narrow values may be loaded. Signed and unsigned integer types are compatible if they have the same size. st. .f64 . or converted to other types and sizes.Chapter 5.f32 and .s32. The same typesize specifiers are used for both variable definitions and for typing instructions.s8. The . the fundamental types reflect the native data types supported by the target architectures. .f16. ld.

In independent mode the fields of the . or performing pointer arithmetic will result in undefined results.texref handle.0 5. and query instructions. Creating pointers to opaque variables using mov.texref. and overall size is hidden to a PTX program. Referencing textures. and de-referenced by texture and surface load. Texture. In the unified mode. texture and sampler information is accessed through a single . base address. These types have named fields similar to structures. suld. Retrieving the value of a named member via query instructions (txq. texture and sampler information each have their own handle.PTX ISA Version 2.. passed as a parameter to functions. Sampler.e. samplers.samplerref variables. 34 January 24. allowing them to be defined separately and combined at the site of usage in the program.surfref. and Surface Types PTX includes built-in “opaque” types for defining texture. since these properties are defined by . accessing the pointer with ld and st instructions. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. or surfaces via texture and surface load/store instructions (tex. but the pointer cannot otherwise be treated as an address. i. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. 2010 . The following tables list the named members of each type for unified and independent texture modes. . sured). suq).3. the resulting pointer may be stored to and loaded from memory. hence the term “opaque”. opaque_var. For working with textures and samplers. sust. In the independent mode. but all information about layout.samplerref. field ordering. and surface descriptor variables.{u32.texref type that describe sampler properties are ignored. The three built-in types are . and .u64} reg. sampler. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. PTX has two modes of operation. store.

State Spaces.samplerref values N/A N/A N/A N/A nearest. clamp_to_edge. clamp_to_border 0. linear wrap. linear wrap. mirror. clamp_to_border N/A N/A N/A N/A N/A . 1 nearest. clamp_ogl. mirror. and Variables Table 9. 1 ignored ignored ignored ignored . 2010 35 .Chapter 5. clamp_to_edge.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Types.texref values .texref values in elements in elements in elements 0. Member width height depth Opaque Type Fields in Independent Texture Mode . clamp_ogl. Member width height depth Opaque Type Fields in Unified Texture Mode .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.

samplerref tsamp1 = { addr_mode_0 = clamp_to_border. the types may be initialized using a list of static expressions assigning values to the named members. When declared at module scope.global . filter_mode = nearest }.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.texref my_texture_name. . these variables are declared in the . 2010 .global .surfref my_surface_name. As kernel parameters.texref tex1.global . Example: .PTX ISA Version 2. . these variables must be in the .samplerref my_sampler_name. 36 January 24. At module scope.global .global .global state space.param state space. Example: . .

1.f32 accel. // typedef .Chapter 5. Variable Declarations All storage for data is specified with variable declarations. .4. textures. A variable declaration names the space in which the variable resides.global .1.struct float4 coord.const . Examples: .v4 . State Spaces. Vectors Limited-length vector types are supported.reg . Examples: . In addition to fundamental types.v4. .global . its name.b8 v.f64 is not allowed. .u32 loc.4. Three-element vectors may be handled by using a .v1. 0}. . and an optional fixed address for the variable. Every variable must reside in one of the state spaces enumerated in the previous section. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v2 . r. January 24.0}.2. 2010 37 .shared .reg . // a length-4 vector of bytes By default.f32 bias[] = {-1.global . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . . q. where the fourth element provides padding. 5. 0.struct float4 { . and Variables 5.global . vector variables are aligned to a multiple of their overall size (vector length times base-type size). an optional array size. Variables In PTX.v2 or .u16 uv.v3 }. 0.f32 V.s32 i.0. // a length-2 vector of unsigned ints . a variable declaration describes both the variable’s type and its state space.v4 vector.v4 .reg .v2. and they may reside in the register space. . 5. an optional initializer. PTX supports types for simple aggregate objects such as vectors and arrays.v4. Vectors cannot exceed 128-bits in length. . This is a common case for three-dimensional grids. Predicate variables may only be declared in the register state space.f32 v0. // a length-4 vector of floats .u8 bg[4] = {0. Vectors must be based on a fundamental type. its type and size.v4 .pred p.global . etc. Types. for example.4.

A scalar takes a single value.1. {0.05}. Array Declarations Array declarations are provided to allow the programmer to reserve space.1. For the kernel declaration above.v4 . .4.0}}.0.global . Similarly. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. {0. this can be used to statically initialize a pointer to a variable. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).f32 blur_kernel[][] = {{.0}..{.global . 19*19 (361) halfwords are reserved (722 bytes).1}.global .0. . // address of rgba into ptr Currently.u64.pred.global .u16 kernel[19][19]. . 0}.shared .05}}. 0}. Variables that hold addresses of variables or instructions should be of type . {0.4.{. or is left empty.1. Examples: .. 38 January 24. {1.0}.f16 and . variable initialization is supported only for constant and global state spaces.0 5.4. {0.1. this can be used to initialize a jump table to be used with indirect branches or calls.3. 2010 ..PTX ISA Version 2.0.. 5.4.. 1} }.global . label names appearing in initializers represent the address of the next instruction following the label.05.b32 ptr = rgba. The size of the dimension is either a constant expression. Initializers are allowed for all types except . The size of the array specifies how many elements should be reserved.s32 n = 10. Here are some examples: . To declare an array. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. where the variable name is followed by an equals sign and the initial value or values for the variable. -1}. Variable names appearing in initializers represent the address of the variable. ..u8 rgba[3] = {{1. . being determined by an array initializer.1.05.s32 offset[][] = { {-1.local .u8 mailbox[128].u32 or .0.

4.0.b8 bar[8] = {0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. %r1. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Parameterized Variable Names Since PTX supports virtual registers. . 2010 39 . State Spaces. …. Examples: // allocate array at 4-byte aligned address. For example.. named %r0. The variable will be aligned to an address which is an integer multiple of byte-count.const . %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. %r1. alignment specifies the address alignment for the starting address of the entire array. .b32 variables. The default alignment for scalar and array variables is to a multiple of the base-type size. and may be preceded by an alignment specifier. Rather than require explicit declaration of every name. %r99. These 100 register variables can be declared as follows: . say one hundred.0}.reg . January 24. not for individual elements. and Variables 5.0..4. Types. Array variables cannot be declared this way.6. // declare %r0. Elements are bytes. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. For arrays. 5.0.5. The default alignment for vector variables is to a multiple of the overall vector size. Alignment is specified using an optional .align byte-count specifier immediately following the state-space specifier.align 4 .0. of .0.Chapter 5. nor are initializers permitted.b32 %r<100>. suppose a program uses a large number.2.. it is quite common for a compiler frontend to generate a large number of register names.

PTX ISA Version 2. 2010 .0 40 January 24.

Chapter 6. The ld. and cvt instructions copy data from one location to another. and c.2. mov. q. Integer types of a common size are compatible with each other. and a few instructions have additional predicate source operands. The bit-size type is compatible with every type having the same size. The mov instruction copies data between registers.3. s.1.reg register state space. Instruction Operands 6. The result operand is a scalar or vector variable in the register state space. so operands for ALU instructions must all be in variables declared in the . Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. There is no automatic conversion between types. 6. The cvt (convert) instruction takes a variety of operand types and sizes. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. For most operations. 6. January 24. 2010 41 . Each operand type must be compatible with the type determined by the instruction template and instruction type. as its job is to convert from nearly any data type to any other data type (and size). Operand Type Information All operands in instructions have a known type from their declarations. Predicate operands are denoted by the names p. Source Operands The source operands are denoted in the instruction descriptions by the names a. Instructions ld and st move data from/to addressable state spaces to/from registers. . b. r. the sizes of the operands must be consistent. PTX describes a load-store machine. st. Most instructions have an optional predicate guard that controls conditional execution.

b32 p. The mov instruction can be used to move the address of a variable into a pointer.s32 q. . The address is an offset in the state space in which the variable is declared. p.reg .const. and immediate address expressions which evaluate at compile-time to a constant address.PTX ISA Version 2.f32 ld. . .f32 W. and vectors. q. The syntax is similar to that used in many assembly languages.s32 tbl[256]. Here are a few examples: . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.s32 mov.u16 ld.u16 r0.v4.f32 V. All addresses and address computations are byte-based. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.u16 x. [V]. . .u32 42 January 24.v4 . address register plus byte offset. there is no support for C-style pointer arithmetic. Address expressions include variable names. Examples include pointer arithmetic and pointer comparisons. and Vectors Using scalar variables as operands is straightforward. tbl. arrays.4. Load and store operations move data between registers and locations in addressable state spaces.reg .shared. ld.reg . 6.reg . Using Addresses.[x]. W.4. Arrays.gloal.1. The interesting capabilities begin with addresses. 2010 . [tbl+12].v4 . r0. address registers.shared . .global .const .0 6.

st. and in move instructions to get the address of the label or function into a register. The size of the array is a constant in the program.4.f32 ld.b V. .2. V2. . Instruction Operands 6. Vectors as Operands Vector operands are supported by a limited subset of instructions.global.r.f32 V. A brace-enclosed list is used for pattern matching to pull apart vectors. Vector elements can be extracted from the vector with the suffixes .g V. Arrays as Operands Arrays of all types can be declared.4.u32 {a.f32 {a.x.y. and the identifier becomes an address constant in the space where the array is declared.u32 s. which may improve memory performance. or a simple “register with constant offset” expression.b. it must be written as an address calculation prior to use. and tex. a[0]. Examples are ld. . Vector loads and stores can be used to implement wide loads and stores. The expression within square brackets is either a constant integer.w = = = = V.a. for use in an indirect branch or call. c.4.reg .v4.c.b and . a[N-1].r V. Rb. . V. ld.3. Array elements can be accessed using an explicitly calculated byte address.g.d}.global. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. a register variable. or by indexing into the array using square-bracket notation. d.v4. Elements in a brace-enclosed vector. If more complicated indexing is desired.v2. January 24. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.b.y V. [addr+offset].z and .u32 s. where the offset is a constant expression that is either added or subtracted from a register variable.w. [addr+offset2].4.a 6. or a braceenclosed list of similarly typed scalars.global. .c. a[1].u32 s.z V. Vectors may also be passed as arguments to called functions. Here are examples: ld.reg . .x V. // move address of a[1] into s 6. which include mov. mov.f32 a. mov. b.d}. 2010 43 . The registers in the load/store operations can be a vector.v4 . as well as the typical color fields . say {Ra.global. ld. Rc. Rd}.Chapter 6.

0 6. and ~131.1. Type Conversion All operands to all arithmetic. logic.u16 instruction is given a u16 source operand and s32 as a destination operand. Operands of different sizes or types must be converted prior to the operation.s32. 2010 . For example.5. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.5. 6. the u16 is zero-extended to s32. and data movement instruction must be of the same type and size. 44 January 24.PTX ISA Version 2. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. if a cvt. except for operations where changing the size and/or type is part of the definition of the instruction.000 for f16).

then sign-extend to 32-bits.s16. Notes 1 If the destination register is wider than the destination format. January 24. 2010 45 . The type of extension (sign or zero) is based on the destination format. f2u = float-to-unsigned. f2f = float-to-float. chop = keep only low bits that fit. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. the result is extended to the destination register width after chopping. f2s = float-to-signed. u2f = unsigned-to-float.u32 targeting a 32-bit register will first chop to 16-bits. s2f = signed-to-float. Instruction Operands Table 11. zext = zero-extend. For example.Chapter 6. cvt.

The following tables summarize the rounding modifiers.rn . Modifier . 2010 .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rz .rni . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rmi .2.0 6.5.rm . Rounding Modifiers Conversion instructions may specify a rounding modifier. Table 12.rzi .PTX ISA Version 2. Modifier . In PTX.rpi Integer Rounding Modifiers Description round to nearest integer. there are four integer rounding modifiers and four floating-point rounding modifiers. choosing even integer if source is equidistant between two integers.

2010 47 . Much of the delay to memory can be hidden in a number of ways. The register in a store operation is available much more quickly. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Table 14. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Instruction Operands 6.Chapter 6. while global memory is slowest. first access is high Notes January 24. Table 11 gives estimates of the costs of using different kinds of memory. Registers are fastest.6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Operand Costs Operands from different state spaces affect the speed of an operation. Another way to hide latency is to issue the load instructions as early as possible.

2010 .0 48 January 24.PTX ISA Version 2.

A function definition specifies both the interface and the body of the function. together these specify the function’s interface.func directive.1. stack-based ABI. 2010 49 . or prototype. A function declaration specifies an optional list of return parameters. A function must be declared or defined prior to being called. so recursion is not yet supported. support for variadic functions (“varargs”). Execution of the ret instruction within foo transfers control to the instruction following the call. January 24. NOTE: The current version of PTX does not implement the underlying. parameter passing. Function declarations and definitions In PTX. … Here. The simplest function has no parameters or return values. 7. and Application Binary Interface (ABI). and an optional list of input parameters. } … call foo. and is represented in PTX as follows: . execution of the call instruction transfers control to foo. implicitly saving the return address. stack layout.func foo { … ret. and memory allocated on the stack (“alloca”). and return values may be placed directly into register variables. These include syntax for function definitions. At the call. arguments may be register variables or constants. function calls.Chapter 7. Scalar and vector base-type input and return parameters may be represented simply as register variables. the function name. In this section. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. we describe the features of PTX needed to achieve this hiding of the ABI. Abstracting the ABI Rather than expose details of a particular calling convention. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. functions are declared and defined using the .

s32 out) bar (. a .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.reg .b8 [py+ 8]. %inc.PTX ISA Version 2.b8 [py+ 9].b8 c2.b8 c3.f1. c4. st. bumpptr. … In this example.u32 %res.param space memory. passed by value to a function: struct { double dbl.reg space.param. Since memory accesses are required to be aligned to a multiple of the access size. [y+11].4). … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param.b8 c1. First.b8 .param. inc_ptr. %rc2. note that . } { . . For example.reg .reg .f64 f1.param variable y is used in function definition bar to represent a formal parameter.c1.0 Example: .param.param. In PTX. st.u32 %ptr.f64 field are aligned. // scalar args in . ld. 50 January 24.reg . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . ld. consider the following C structure. [y+8].param.param.f64 f1. st. py). this structure will be flattened into a byte array. %rc1.c2. ret. ld.func (.b64 [py+ 0].b8 c4. 2010 .b8 [py+11].param. st. } … call (%r1). [y+0]. . … … // computation using x. [y+10]. c2. }.reg . (%x.reg .param . %rd. The . Second. (%r1.align 8 y[12]) { .s32 x.func (. … st.b32 c1.b8 [py+10]. … ld. byte array in .c4.b8 .u32 %inc ) { add. a .c3. char c[4]. %rc2.param state space is used to pass the structure by value: .align 8 py[12]. %rc1. .param space call (%out).param . [y+9]. ld.param space variables are used in two ways.param.reg .u32 %res) inc_ptr ( .param. %ptr. c3.

param variables. January 24. size.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. and alignment of parameters.reg space variable with matching type and size. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. all st.reg variables.param space formal parameters that are byte arrays. • The .reg state space can be used to receive and return base-type scalar and vector values.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. In the case of . The . a .Chapter 7. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. and alignment. 2.reg or . In the case of . or constants.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param space formal parameters that are base-type scalar or vector variables. the argument must also be a .param state space is used to receive parameter values and/or pass return values back to the caller. Abstracting the ABI The following is a conceptual way to think about the . the corresponding argument may be either a . For a caller. or 16 bytes.param space byte array with matching type.. For .param variables or .param argument must be declared within the local scope of the caller. 2010 51 . Typically.param memory must be aligned to a multiple of 1. the corresponding argument may be either a . 8.param state space use in device functions.param arguments.param or .param or .reg space formal parameters. Parameters in .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. • • Arguments may be . . or a constant that can be represented in the type of the formal parameter. The following restrictions apply to parameter passing.reg state space in this way provides legacy support.param and ld. or a constant that can be represented in the type of the formal parameter.g. size. • • • For a callee. For a caller. Supporting the . 4.reg variables. Note that the choice of . The .reg space variable of matching type and size. • • • Input and return parameters may be . This enables backend optimization and ensures that the . A .param instructions used for argument passing must be contained in the basic block with the call instruction. For a callee.param byte array is used to collect together fields of a structure being passed by value. • The . In the case of .

0.1. and .x supports multiple return values for this purpose. PTX 2.param byte array should be used to return objects that do not fit into a register. Objects such as C structures were flattened and passed or returned using multiple registers. and there was no support for array parameters. 52 January 24. PTX 2.PTX ISA Version 2.x. 2010 . In PTX ISA version 2.0 7. PTX 1.reg or .param space parameters support arrays.reg state space.0 continues to support multiple return registers for sm_1x targets.1. formal parameters may be in either .param state space. formal parameters were restricted to . and a .x In PTX ISA version 1. Changes from PTX 1.0 restricts functions to a single return value. For sm_2x targets.

reg .reg . and end access to a list of variable arguments. max.u32 ptr. . 0x8000000. . %va_start. or 8 bytes.u32 sz. setp.func okay ( … ) Built-in functions are provided to initialize.b32 result.u32 sz.reg . the size may be 1.reg . (3. %s2).s32 val.reg . The function prototypes are defined as follows: . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .s32 result.pred p. 2010 53 . call (ap). ctr. … ) .2. … %va_start returns Loop: @p Done: January 24. iteratively access. Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . Once all arguments have been processed. or 16 bytes.h and varargs. ctr. %r3). along with the size and alignment of the next data value to be accessed. ) { . . 2. .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. 8. N.u32 b. This handle is then passed to the %va_arg and %va_arg64 built-in functions. result.u32 ptr.b32 ctr. call (val). bra Done. In both cases. 4. variadic functions are declared with an ellipsis at the end of the input parameter list. val.u32 N. for %va_arg64.func ( .reg . the alignment may be 1. // default to MININT mov.u32 align) . ret. maxN.h headers in C.reg .u32 ptr) %va_start .s32 result ) maxN ( . %s1. .func (.u32 align) .reg . 0. %r1.reg .Chapter 7. .func (. 2. 4).. 4.reg . mov. } … call (%max). 4. . (2. (ap).u32 a.b32 val) %va_arg (. PTX provides a high-level mechanism similar to the one provided by the stdarg. or 4 bytes.reg . bra Loop.reg . To support functions with a variable number of arguments. the size may be 1. .reg ..b64 val) %va_arg64 (. In PTX. … call (%max). %va_arg. %va_end is called to free the variable argument list handle.func (.func %va_end (. For %va_arg. (ap. %r2. following zero or more fixed parameters: .u32. call %va_end.ge p.reg . Abstracting the ABI 7. maxN.reg .u32 ap.func baz ( . 2.reg .

u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.reg . defined as follows: .3. 2010 .0 7.local instructions.PTX ISA Version 2.func ( .reg . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. a function simply calls the built-in function %alloca. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. Alloca NOTE: The current version of PTX does not support alloca. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.u32 ptr ) %alloca ( . 54 January 24. The array is then accessed with ld. To allocate memory. If a particular alignment is required.local and st.

A. C. PTX Instructions PTX instructions generally have from zero to four operands. and C are the source operands. opcode A. For instructions that create a result value.1. a. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. 2010 55 . B.s32. B. January 24. We use a ‘|’ symbol to separate multiple destination registers. opcode D. B. q = !(a < b). the semantics are described.2. while A. setp. A.lt p|q. the D operand is the destination operand. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. 8. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. // p = (a < b). In addition to the name and the format of the instruction. A. b.Chapter 8. opcode D. For some instructions the destination operand is optional. The setp instruction writes two destination registers. Instruction Set 8. followed by some examples that attempt to show several possible instantiations of the instruction.

i. the following PTX instruction sequence might be used: @!p L1: setp.s32 j. … // compare i to n // if false. Predicated Execution In PTX.reg . i. bra L1. n. add. add 1 to j To get a conditional branch or conditional function call.lt.pred p.pred as the type specifier. q.s32 p. j. // p = (i < n) // if i < n. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. This can be written in PTX as @p setp.PTX ISA Version 2. 1.s32 j.3. Instructions without a guard predicate are executed unconditionally. add.lt. consider the high-level code if (i < n) j = j + 1. use a predicate to control the execution of the branch or call instructions. predicate registers are virtual and have .s32 p. 1. where p is a predicate variable. j. 2010 . So. Predicates are most commonly set as the result of a comparison performed by the setp instruction. predicate registers can be declared as . As an example. n. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. branch over 56 January 24.0 8. To implement the above example as a true conditional branch. optionally negated.

Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.1. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). ne. The bit-size comparisons are eq and ne.3. The unsigned comparisons are eq. the result is false. unsigned integer. hi (higher). and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. gt (greater-than). lt (less-than).1. The following table shows the operators for signed integer.2.1. le. and bitsize types. Table 16. ordering comparisons are not defined for bit-size types. and ge (greater-than-or-equal).3.1. ge. If either operand is NaN.3. ne (not-equal). Table 15. lo (lower). gt. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. 2010 57 . Instruction Set 8.Chapter 8. and hs (higher-or-same). le (less-than-or-equal). Unsigned Integer. ne. Comparisons 8. ls (lower-or-same). lt.

not. leu. then the result of these comparisons is true. If either operand is NaN.1.PTX ISA Version 2. unordered versions are included: equ.%p. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. then these comparisons have the same result as their ordered counterparts. If both operands are numeric values (not NaN). num returns true if both operands are numeric values (not NaN). Table 17. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. geu. gtu. ltu. setp can be used to generate a predicate from an integer. Table 18. two operators num (numeric) and nan (isNaN) are provided. There is no direct conversion between predicates and integer values. and mov. for example: selp. However. // convert predicate to 32-bit value 58 January 24. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.2. or. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.0. and no direct way to load or store predicate register values.0 To aid comparison operations in the presence of NaN values.u32 %r1. 2010 . neu.3. and nan returns true if either operand is NaN. xor.

Example: .reg .sX ok ok ok inv .bX . Type Checking Rules Operand Type .uX ok ok ok inv . a. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. and these are placed in the same order as the operands. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. b. most notably the data conversion instruction cvt. Floating-point types agree only if they have the same size. unsigned. . For example.e..f32 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. and this information must be specified as a suffix to the opcode. • The following table summarizes these type checking rules. For example. they must match exactly. a.reg .f32.fX ok inv inv ok Instruction Type .u16 a.reg . b. For example: . the add instruction requires type and size information to properly perform the addition operation (signed.u16 d. a.4. Instruction Set 8. and integer operands are silently cast to the instruction type if needed. add. cvt. Table 19. different sizes). 2010 59 . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. It requires separate type-size modifiers for the result and source. float.uX . i.u16 d.u16 d. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.bX .fX ok ok ok ok January 24.Chapter 8. Signed and unsigned integer types agree provided they have the same size.sX .

for example. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. stored. When used with a floating-point instruction type. “-“ = allowed. inv = invalid. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Bit-size source registers may be used with any appropriately-sized instruction type. 60 January 24. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. The following table summarizes the relaxed type-checking rules for source operands. floating-point instruction types still require that the operand type-size matches exactly.bX instruction types. ld. Table 20. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.4. or converted to other types and sizes. so those rows are invalid for cvt. 2010 . 4.0 8. The data is truncated to the instruction-type size and interpreted according to the instruction type. st. parse error. 2. unless the operand is of bit-size type. so that narrow values may be loaded. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. the data will be truncated. Notes 3.PTX ISA Version 2.1. the size must match exactly. Note that some combinations may still be invalid for a particular instruction. When used with a narrower bit-size type. For example. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. 1. the cvt instruction does not support . Floating-point source registers can only be used with bit-size or floating-point instruction types. When a source operand has a size that exceeds the instruction-type size. Operand Size Exceeding Instruction-Type Size For convenience. stored. Source register size must be of equal or greater size than the instruction-type size. no conversion needed. and converted using regular-width registers.

or sign-extended to the size of the destination register. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. “-“ = Allowed but no conversion needed. Table 21. The data is sign-extended to the destination register width for signed integer instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. the size must match exactly. the data is sign-extended. When used with a floatingpoint instruction type. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size. 4. Notes 3. Floating-point destination registers can only be used with bit-size or floating-point instruction types. If the corresponding instruction type is signed integer. Destination register size must be of equal or greater size than the instruction-type size. inv = Invalid. otherwise. Bit-size destination registers may be used with any appropriately-sized instruction type. The data is signextended to the destination register width for signed integer instruction types. and is zero-extended to the destination register width otherwise. parse error. the data is zeroextended. The following table summarizes the relaxed type-checking rules for destination operands. the data will be zero-extended. January 24. the destination data is zero.Chapter 8. 2. When used with a narrower bit-size instruction type. zext = zero-extend. 2010 61 . 1.

This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. for many performance-critical applications. until they come to a conditional control construct such as a conditional branch. at least in appearance. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 16-bit registers in PTX are mapped to 32-bit physical registers. the optimizing code generator automatically determines points of re-convergence. for example. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Divergence of Threads in Control Constructs Threads in a CTA execute together. until C is not expressive enough. If all of the threads act in unison and follow a single control flow path. Therefore. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. Both situations occur often in programs. For divergent control flow.6. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. 62 January 24. 8. a compiler or code author targeting PTX can ignore the issue of divergent threads. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. or conditional return. However. When executing on a 32-bit data path. and 16-bit computations are “promoted” to 32-bit computations.PTX ISA Version 2. using the . The semantics are described using C. If threads execute down different control flow paths.uni suffix. 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs.6.5. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. A compiler or programmer may chose to enforce portable. and for many applications the difference in execution is preferable to limiting performance.0 8. the threads are called uniform. this is not desirable. by a right-shift instruction. At the PTX language level. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. 2010 . but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. so it is important to have divergent threads re-converge as soon as possible. conditional function call.1. the semantics of 16-bit instructions in PTX is machine-specific. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. the threads are called divergent. These extra precision bits can become visible at the application level.

the optional guard predicate is omitted from the syntax.Chapter 8.1.7. Instructions All PTX instructions may be predicated. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. 8. The Integer arithmetic instructions are: add sub add.7. In the following descriptions. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.cc.cc. addc sub. Instruction Set 8. 2010 63 .

// .s64 }.s64 }.type sub{.PTX ISA Version 2.0.sat. Supported on all target architectures. sub. . Description Semantics Notes Performs addition and writes the resulting value into a destination register. . // .s32 type.s32. add Syntax Integer Arithmetic Instructions: add Add two values..u32 x. .z.s16. @p add. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.MAXINT (no overflow) for the size of the operation. b.s32 d. Introduced in PTX ISA version 1. 2010 .1. a. .y. add. Introduced in PTX ISA version 1.type = { . add.MAXINT (no overflow) for the size of the operation.sat applies only to .c. b.0 Table 22.s32 type.sat}. . .sat limits result to MININT.sat applies only to .s32 d. PTX ISA Notes Target ISA Notes Examples Table 23. Saturation modifier: . Saturation modifier: .b. . d.u32.s32 .s32 c.u16.s32. a. Supported on all target architectures.u32. d. b.0.s32 . Applies only to .type add{.sat limits result to MININT. a. a. b. d = a – b.u16. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.sat}.. d = a + b.type = { . .s32 c. . Applies only to .u64. .u64.s16.a. PTX ISA Notes Target ISA Notes Examples 64 January 24. sub.

x3.u32.y4.cc Add two values with carry-out.cc Syntax Integer Arithmetic Instructions: add.type d.cc. .cc. 2010 65 .y2.y4.s32 }. .cc}. Behavior is the same for unsigned and signed integers.b32 addc.type = {. b.2. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.z1. Introduced in PTX ISA version 1.CF) holding carry-in/carry-out or borrowin/borrow-out.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. x4. carry-out written to CC.cc. @p @p @p @p add.z2.u32. if . The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y1.type d.z1. carry-out written to CC.2. x3.z3. Behavior is the same for unsigned and signed integers. Table 24. addc{. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. a. Supported on all target architectures.cc specified. clearing.cc. Introduced in PTX ISA version 1. add. Supported on all target architectures.z3.cc.y3. No other instructions access the condition code.z4.b32 addc.b32 x1.y1.cc.cc. x2. x2.cc.CF No integer rounding modifiers.CF. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.CF No integer rounding modifiers. No saturation.b32 addc. Instruction Set Instructions add.cc. d = a + b. or testing the condition code.y3.y2. add.Chapter 8.b32 addc.cc. @p @p @p @p add. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. addc.b32 addc. a. x4. d = a + b + CC.z4.s32 }.z2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. b.type = { . No saturation.b32 addc. . These instructions support extended-precision integer addition and subtraction.b32 x1. and there is no support for setting. . sub.

cc Subract one value from another.z1. No saturation.b32 subc.CF No integer rounding modifiers.s32 }. borrow-out written to CC.cc}.cc.b32 x1. x2.type = { .3.cc.type d. .z2.type d. with borrow-out. x4. x2.z3.z4. d = a – b.b32 subc. .cc.b32 subc. .y1. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. Introduced in PTX ISA version 1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.CF No integer rounding modifiers. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y4.b32 subc. a.y4.cc.u32.cc. Supported on all target architectures.y3.b32 x1.z2.cc. @p @p @p @p sub. sub.b32 subc.(b + CC. Behavior is the same for unsigned and signed integers.z3. d = a . sub. Supported on all target architectures.cc.3. withborrow-in and optional borrow-out. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. No saturation.s32 }. .CF).PTX ISA Version 2.0 Table 26.z4.cc Syntax Integer Arithmetic Instructions: sub. 2010 .y1. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. x3.y3.cc.cc. Behavior is the same for unsigned and signed integers. @p @p @p @p sub. x4. x3. b.y2. subc{.y2. a.cc specified. borrow-out written to CC. Introduced in PTX ISA version 1. b. if .b32 subc.z1.type = {.u32.

. save only the low 16 bits // 32*32 bits. d = t<n-1.y.u32.fxs. // 16*16 bits yields 32 bits // 16*16 bits.fys.wide}.hi or . .fxs.s32.fys.type = { .n>.lo is specified.0.type d.lo. mul.0>. Description Semantics Compute the product of two values.hi variant // for . d = t<2n-1. mul{. n = bitwidth of type.s16. mul. If .and 32-bit integer types. The . b. Supported on all target architectures.s64 }. then d is twice as wide as a and b to receive the full result of the multiplication. and either the upper or lower half of the result is written to the destination register.wide is specified. . t = a * b. then d is the same size as a and b. Instruction Set Table 28. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32 z.u16.x. // for .wide suffix is supported only for 16.hi. If .s16 fa. mul Syntax Integer Arithmetic Instructions: mul Multiply two values..u64.Chapter 8. .. a.wide // for .lo.s16 fa.. 2010 67 .wide. . d = t..wide.lo variant Notes The type of the operation represents the types of the a and b operands. creates 64 bit result January 24. mul. .

t n d d d = = = = = a * b.u64. @p mad.u16.a.s32 d..type mad. bitwidth of type. b. a. Supported on all target architectures. 2010 .0 Table 29. t<2n-1.wide // for . c. mad. .s32 type in .. then d and c are twice as wide as a and b to receive the result of the multiplication. If . // for .lo. c.lo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . Description Semantics Multiplies two values and adds a third. d.lo is specified. b. .s32 r. 68 January 24. t + c.wide is specified.hi or . . .hi. then d and c are the same size as a and b.lo.s64 }.and 32-bit integer types.sat limits result to MININT. t<n-1..sat.lo variant Notes The type of the operation represents the types of the a and b operands.c.0.wide}.wide suffix is supported only for 16.r..hi mode. a. Saturation modifier: . and either the upper or lower half of the result is written to the destination register.b. and then writes the resulting value into a destination register. The . .. mad{. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.s32 d.hi variant // for .PTX ISA Version 2.s32. Applies only to .u32.q.0> + c.p.n> + c.hi. If .s16.type = { .MAXINT (no overflow) for the size of the operation.

Supported on all target architectures.b. // for .. a. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. and return either the high or low 32-bits of the 48-bit result.type = { .hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.Chapter 8. d = t<47.lo}. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers..0>. ..lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24.hi may be less efficient on machines without hardware support for 24-bit multiply. t = a * b. mul24{.16>. d = t<31. Instruction Set Table 30.hi. All operands are of the same type and size.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. .lo.s32 }.e.type d.u32.a. mul24. January 24.s32 d. 2010 69 . mul24. // low 32-bits of 24x24-bit signed multiply. b.0. i. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi variant // for . mul24. 48bits.

70 January 24.. 48bits.s32 d.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.lo}. mad24.b.hi variant // for ..type mad24. c.hi may be less efficient on machines without hardware support for 24-bit multiply.e.PTX ISA Version 2. mad24{.c. Description Compute the product of two 24-bit integer values held in 32-bit source registers.MAXINT (no overflow). mad24.hi. d = t<47. mad24. i.. Saturation modifier: .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. t = a * b.a.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.type = { .hi mode. . // low 32-bits of 24x24-bit signed multiply.s32 }. d = t<31. b.s32 type in . a.lo. b. a. . Applies only to . Supported on all target architectures.sat.16> + c. 2010 . c. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. All operands are of the same type and size. d.0> + c.0 Table 31.hi.sat limits result of 32-bit signed addition to MININT. and add a third.. Return either the high or low 32-bits of the 48-bit result. // for .u32.s32 d. mad24. 32-bit value to either the high or low 32-bits of the 48-bit result.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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type = { . X.b64 d. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.u32 PTX ISA Notes Target ISA Notes Examples Table 40. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 popc. . d = 0. popc Syntax Integer Arithmetic Instructions: popc Population count. cnt.0 Table 39. mask = 0x80000000. d = 0. a = a >> 1. // cnt is .b64 }.b32) { max = 32. popc. the number of leading zeros is between 0 and 64. } else { max = 64. a. } Introduced in PTX ISA version 2. a. . inclusively.0. a = a << 1.0. // cnt is . inclusively. cnt. mask = 0x8000000000000000. For . For . the number of leading zeros is between 0 and 32. if (. clz.type d.b64 }.type d.b64 d. a. 2010 .b32 type.PTX ISA Version 2.u32 Semantics 74 January 24. .b64 type. popc requires sm_20 or later.b32. } while (d < max && (a&mask == 0) ) { d++.b32. clz. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.b32 clz. X. popc.type = { .type == . clz requires sm_20 or later. a. . while (a != 0) { if (a&0x1) d++. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.

bfind.Chapter 8. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.u32. bfind returns 0xFFFFFFFF if no non-sign bit is found. 2010 75 .0.s32. If . . a. Operand a has the instruction type. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u64. break. a. Semantics msb = (.s64 }. i--) { if (a & (1<<i)) { d = i.type d.u32 January 24. For unsigned integers.type bfind. Description Find the bit position of the most significant non-sign bit in a and place the result in d.u32 || . bfind.type==. . . . // cnt is . bfind returns the bit position of the most significant “1”.shiftamt.u32 d. d = -1. } } if (.type==. and operand d has type . bfind. X. for (i=msb. Instruction Set Table 41. a.shiftamt is specified. For signed integers.s32) ? 31 : 63.s64 cnt. i>=0.shiftamt.type = { .d.u32. bfind requires sm_20 or later.shiftamt && d != -1) { d = msb . d. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.

b32. Description Semantics Perform bitwise reversal of input.type = { .0. msb = (. a. for (i=0. i++) { d[i] = a[msb-i].b32) ? 31 : 63. brev. i<=msb. a.type==.b64 }. brev requires sm_20 or later.b32 d. 76 January 24.type d. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. . 2010 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 42. brev. .PTX ISA Version 2.

type = { . The destination d is padded with the sign bit of the extracted field. January 24. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfe requires sm_20 or later.s32. . .a.Chapter 8.u32. .type==.s64 }.msb)]. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.type d.0.u32 || . and operands b and c are type . and source c gives the bit field length in bits.u64: . . bfe.u64 || len==0) sbit = 0. . b.type==.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. Semantics msb = (.s32) ? 31 : 63. for (i=0. 2010 77 . otherwise If the bit field length is zero.u64. a.len. the destination d is filled with the replicated sign bit of the extracted field.type==. If the start position is beyond the msb of the input. bfe. else sbit = a[min(pos+len-1. len = c. the result is zero.start. c.u32. The sign bit of the extracted field is defined as: .b32 d. Description Extract bit field from a and place the zero or sign-extended result in d.u32. Operands a and d have the same type as the instruction type. pos = b.type==. d = 0. . Instruction Set Table 43.s32. i<=msb. Source b gives the bit field starting bit position. if (. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u32 || .

d.a. Description Align and insert a bit field from a into b. and place the result in f. b.type==. 2010 .b64 }.b32) ? 31 : 63.PTX ISA Version 2. f = b. the result is b. Operands a. the result is b.len. and source d gives the bit field length in bits. Semantics msb = (. a.u32. . bfi. bfi.0 Table 44.b32. b. 78 January 24.b32 d.0. and operands c and d are type . i++) { f[pos+i] = a[i]. c. i<len && pos+i<=msb. for (i=0.type = { . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type f.start.b. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. . pos = c. bfi requires sm_20 or later. len = d. If the start position is beyond the msb of the input. and f have the same type as the instruction type. Source c gives the starting bit position for the insertion. If the bit field length is zero.

.b2 source select c[11:8] d. The msb defines if the byte value should be copied.f4e.b4e. b6. default mode index d.Chapter 8. the permute control consists of four 4-bit selection values.mode = { . {b3. b4}. .b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b1 source select c[7:4] d. a 4-bit selection value is defined. Note that the sign extension is only performed as part of generic form. the four 4-bit values fully specify an arbitrary byte permute. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. Thus. b0}}. a. The bytes in the two source registers are numbered from 0 to 7: {b. Instruction Set Table 45. a} = {{b7. msb=1 means replicate the sign.ecl. Description Pick four arbitrary bytes from two 32-bit registers. . prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. 2010 79 .mode} d. . and reassemble them into a 32-bit destination register.b3 source select c[15:12] d. b5.ecr. b1. . msb=0 means copy the literal value. as a 16b permute code. . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.rc8.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. c.b32{. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b2.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. b.rc16 }. In the generic form (no mode specified). For each byte in the target register.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. prmt.

ctl[3] = (c >> 12) & 0xf. prmt. 80 January 24. ctl[0]. r3. ctl[3]. r2. ctl[2]. tmp64 ).f4e r1. tmp64 ). ctl[1] = (c >> 4) & 0xf. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. } tmp[07:00] = ReadByte( mode. r4. tmp[23:16] = ReadByte( mode. tmp[15:08] = ReadByte( mode.b32. r2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ).b32 prmt. r4. r1. ctl[2] = (c >> 8) & 0xf.PTX ISA Version 2.0 Semantics tmp64 = (b<<32) | a. 2010 . tmp[31:24] = ReadByte( mode. tmp64 ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prmt requires sm_20 or later. ctl[1].0. r3.

7.2.f32 and .Chapter 8. 2010 81 . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8.

f64 div.rnd.f32 {div.rn .0].f32 are the same. . Double-precision instructions support subnormal inputs and results.rnd. so PTX programs should not rely on the specific single-precision NaNs being generated.rnd. but single-precision instructions return an unspecified NaN. Table 46. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.PTX ISA Version 2. Single-precision add.mul}.f64 are the same. default is .0 The following table summarizes floating-point instructions in PTX.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.max}. Note that future implementations may support NaN payloads for single-precision instructions.min.rcp.sub.f64 and fma. 82 January 24. No rounding modifier.target sm_20 mad.f64 mad.f32 {mad.f64 {sin. with NaNs being flushed to positive zero.rz .neg.rnd.rnd.sqrt}.sqrt}.fma}. The optional .full. 1.neg.sqrt}. NaN payloads are supported for double-precision instructions.32 and fma.f64 rsqrt.approx.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.approx.target sm_1x No rounding modifier.lg2. If no rounding modifier is specified. 2010 . default is . {add.rp .sat Notes If no rounding modifier is specified. sub.f32 {div.cos.f32 .rn and instructions may be folded into a multiply-add. mul.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.ftz .rcp.rm .0.rcp. {mad.f32 {add.max}.rnd. . and mad support saturation of results to the range [0.min.fma}.f32 {abs. Instruction Summary of Floating-Point Instructions .approx.f64 {abs.target sm_20 .rn and instructions may be folded into a multiply-add.sub.mul}.ex2}.f32 {div.approx.f32 rsqrt.

not infinity). f0.op.type = { . . copysign requires sm_20 or later.f32 testp.type d.infinite. b. . A. testp. and return the result as d. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f32. Introduced in PTX ISA version 2.f32. .subnormal }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . 2010 83 . testp. testp. testp requires sm_20 or later. testp Syntax Floating-Point Instructions: testp Test floating-point property.finite testp.Chapter 8.notanumber. positive and negative zero are considered normal numbers.infinite testp. // result is . January 24. . z. Instruction Set Table 47. a. true if the input is a subnormal number (not NaN.normal.f64 x.notanumber.infinite.normal testp.op p.0. Table 48.pred = { . not infinity) As a special case.0. .type = { .number testp.finite. . copysign.f64 }. p. .type .f32 copysign.notanumber testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.number. a. B.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.f64 }. y. . C.f64 isnan. copysign. X. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.

requires sm_13 for add.f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. b.PTX ISA Version 2. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.ftz}{.rn. requires sm_20 Examples @p add.f32 f1. 84 January 24. sm_1x: add. NaN results are flushed to +0. .rp }. a.rnd = { . add. Saturation modifier: .rm mantissa LSB rounds towards negative infinity .ftz.0.0 Table 49. subnormal numbers are supported.rnd}. Rounding modifiers (default is . add.rz. a. . add.0. . In particular.rz mantissa LSB rounds towards zero . add Syntax Floating-Point Instructions: add Add two values. Rounding modifiers have the following target requirements: .f3.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 clamps the result to [0. Description Semantics Notes Performs addition and writes the resulting value into a destination register. .rn mantissa LSB rounds to nearest even .rn.rm.rn): . add.0f.rz available for all targets .0]. d = a + b.f64 d.rm. add.sat}. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 supported on all target architectures.rnd}{.f32.f64 requires sm_13 or later.f32 add{. b. . d.ftz.f64 supports subnormal numbers.rz.f64.f2. 2010 .sat.f32 flushes subnormal inputs and results to sign-preserving zero. 1. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. add{. .rp for add.

sat. .b. d = a .f64.f64 supports subnormal numbers. subnormal numbers are supported. a. .ftz. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rp }. In particular. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. NaN results are flushed to +0.0.f2. b.f32 c.0]. sub.ftz.0f. requires sm_13 for sub.f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples sub.rn): .f32 f1. sub.rp for sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another.rm. a. b. Saturation modifier: sub.f32 supported on all target architectures.sat}.rz. d.ftz}{.rz available for all targets . sm_1x: sub. sub.f32 flushes subnormal inputs and results to sign-preserving zero.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .rn. sub{.rz mantissa LSB rounds towards zero . January 24.rm.f64 d.f32 clamps the result to [0. . Instruction Set Table 50.f32 sub{. 2010 85 . Rounding modifiers have the following target requirements: .rnd}.f32. . 1.rn.b. . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm mantissa LSB rounds towards negative infinity .rn.a.f64 requires sm_13 or later. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rnd}{.rnd = { . sub.0. Rounding modifiers (default is .Chapter 8.rn mantissa LSB rounds to nearest even . sub.f3. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.

sm_1x: mul.f32 flushes subnormal inputs and results to sign-preserving zero.0].rp }. 2010 .0 Table 51.0.f64 requires sm_13 or later.rp for mul. Rounding modifiers (default is . NaN results are flushed to +0. d. all operands must be the same size. Rounding modifiers have the following target requirements: .f64.pi // a single-precision multiply 86 January 24.f64 d. mul. In particular. . requires sm_20 Examples mul.f32 supported on all target architectures.rnd = { .rm.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero. mul.rn mantissa LSB rounds to nearest even . mul. a.sat. Description Semantics Notes Compute the product of two values.0. .rz available for all targets .f32 circumf.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn): .ftz}{.rnd}. requires sm_13 for mul. mul. b. .f32.rz. .rn.f64 supports subnormal numbers. b.f32 mul{.rn. Saturation modifier: mul. a. mul{.sat}. For floating-point multiplication. mul Syntax Floating-Point Instructions: mul Multiply two values. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 clamps the result to [0.radius.ftz.0f. . subnormal numbers are supported.rm.rz mantissa LSB rounds towards zero . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. .ftz. 1.rm mantissa LSB rounds towards negative infinity .rnd}{. d = a * b.

y. a.0].Chapter 8. .rn.0f. d.a. @p fma. PTX ISA Notes Target ISA Notes Examples January 24.b.rnd = { .rz. fma.4.rz mantissa LSB rounds towards zero . d = a*b + c. fma Syntax Floating-Point Instructions: fma Fused multiply-add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f32 is unimplemented in sm_1x. 1.f32 clamps the result to [0. subnormal numbers are supported. fma.rn. fma. b.rnd.f64.f64 supports subnormal numbers. fma. fma.f32 computes the product of a and b to infinite precision and then adds c to this product. Rounding modifiers (no default): .sat}.ftz. fma. The resulting value is then rounded to double precision using the rounding mode specified by . .ftz. .rp }.f64 requires sm_13 or later.rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity . sm_1x: fma. fma.rm. .f64 introduced in PTX ISA version 1.0. Instruction Set Table 52.rnd. a. b. d.0. The resulting value is then rounded to single precision using the rounding mode specified by .f64 w. NaN results are flushed to +0. fma.f32 introduced in PTX ISA version 2. again in infinite precision. Saturation: fma.f32 fma.c.rnd.f64 d. c. c.rnd{.rn. again in infinite precision.z.x.f32 flushes subnormal inputs and results to sign-preserving zero. fma. fma.f64 is the same as mad.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 fma. 2010 87 .ftz}{.sat.f32 requires sm_20 or later.

mad. again in infinite precision. mad. where the mantissa can be rounded and the exponent will be clamped.f64 computes the product of a and b to infinite precision and then adds c to this product. // .0f.sat. . mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz mantissa LSB rounds towards zero .f64 supports subnormal numbers.rp }. . c. c.ftz}{.f32 flushes subnormal inputs and results to sign-preserving zero. For . When JIT-compiled for SM 2. Unlike mad. The exception for mad.f32). In this case.rnd. For .0 devices.f64}.f32 computes the product of a and b to infinite precision and then adds c to this product. Note that this is different from computing the product with mul. d = a*b + c.f32 is implemented as a fused multiply-add (i. sm_1x: mad.rn. mad. a. mad. b.rm.0 Table 53.f32.rz. mad.0].f32 mad.rn mantissa LSB rounds to nearest even .sat}.f64} is the same as fma. the treatment of subnormal inputs and output follows IEEE 754 standard.f32 computes the product of a and b at double precision. // . mad. and then writes the resulting value into a destination register.f64 computes the product of a and b to infinite precision and then adds c to this product.target sm_20 d.f32 is when c = +/-0. again in infinite precision.{f32. mad{.target sm_13 and later .rnd. b. b.f32 flushes subnormal inputs and results to sign-preserving zero. Description Semantics Notes Multiplies two values and adds a third. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f64 is the same as fma.f32 mad.0.ftz}{. The resulting value is then rounded to double precision using the rounding mode specified by .ftz. mad.PTX ISA Version 2. // . subnormal numbers are supported. a.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.rn. c.f64 d.target sm_20: mad. 1. a.rnd. .f64.rm mantissa LSB rounds towards negative infinity .ftz.rnd{. Saturation modifier: mad. 2010 . and then the mantissa is truncated to 23 bits.rnd = { . but the exponent is preserved..rnd. The resulting value is then rounded to single precision using the rounding mode specified by . again in infinite precision.sat}. 88 January 24.target sm_1x d.e.f32 clamps the result to [0. The resulting value is then rounded to double precision using the rounding mode specified by .f32 is identical to the result computed using separate mul and add instructions. fma.{f32. mad.target sm_1x: mad.0. Rounding modifiers (no default): . NaN results are flushed to +0.

f32 d.f64 requires sm_13 or later.f32. In PTX ISA versions 2. requires sm_20 Examples @p mad.a.0. Legacy mad. January 24..rp for mad..rn..rn..4 and later. mad.f64 instructions having no rounding modifier will map to mad.rz.f32 for sm_20 targets.. In PTX ISA versions 1. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. a rounding modifier is required for mad.rm.b.f32 supported on all target architectures..0 and later.Chapter 8.f64.f64. 2010 89 . Target ISA Notes mad.rp for mad.c. a rounding modifier is required for mad.rm.f64. requires sm_13 .rz. Rounding modifiers have the following target requirements: .rn.

the maximum ulp error is 2. b.f32 defaults to div.rm.full. div. yd.circum. y.f32 and div. stores result in d. Examples 90 January 24.rn. b.rm mantissa LSB rounds towards negative infinity . Description Semantics Notes Divides a by b.rnd = { . and rounding introduced in PTX ISA version 1. The maximum ulp error is 2 across the full range of inputs.3. b. For b in [2-126. z.rnd.f32 implements a fast approximation to divide. For PTX ISA versions 1. Fast.f32 supported on all target architectures.f32 div. PTX ISA Notes div. div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 div. b.rn mantissa LSB rounds to nearest even .f32 requires sm_20 or later.rn.{rz.0.0 through 1.rnd is required. .approx.PTX ISA Version 2. d. .full.approx{. a. d.full.f32 implements a relatively fast. div. .ftz.approx. d. and div. div.rm.ftz.rz.f64 diam.full.ftz}. . zd. approximate division by zero creates a value of infinity (with same sign as a). .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}. but is not fully IEEE 754 compliant and does not support rounding modifiers. Fast. or . div.f32 flushes subnormal inputs and results to sign-preserving zero.f32 div.3.approx.full{.f32 and div. div. a.ftz}. d = a / b.0 Table 54.rp}.f64 introduced in PTX ISA version 1. approximate single-precision divides: div. div. // // // // fast.f64 supports subnormal numbers. Explicit modifiers . a.ftz. For PTX ISA version 1. Target ISA Notes div.f64 requires sm_20 or later. 2010 . sm_1x: div. div.full.f32 div. div.f32 div. subnormal numbers are supported.4 and later.f64 defaults to div. computed as d = a * (1/b).ftz.4. x.ftz. one of .f64 requires sm_13 or later.approx.approx.14159.rn. div Syntax Floating-Point Instructions: div Divide one value by another.rn. 2126].rz mantissa LSB rounds towards zero . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32.rnd{.f64.rnd. Subnormal inputs and results are flushed to sign-preserving zero. full-range approximation that scales operands to achieve better accuracy.rp }.approx.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. . xd. a.

ftz.ftz. Instruction Set Table 55. Subnormal numbers: sm_20: By default.f64 supports subnormal numbers. Negate the sign of a and store the result in d. 2010 91 .f64 d. a.f32 flushes subnormal inputs and results to sign-preserving zero. d. January 24. d = |a|.f0. a. a.f32 x.ftz. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs.f32 abs. neg.0. sm_1x: neg. subnormal numbers are supported.f32 supported on all target architectures. subnormal numbers are supported.f64 requires sm_13 or later. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Take the absolute value of a and store the result in d.f32 x.0. NaN inputs yield an unspecified NaN.Chapter 8.f64 requires sm_13 or later.f32 neg. abs{. neg{. abs. abs.f0.f32 flushes subnormal inputs and results to sign-preserving zero. neg.f64 d. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f64 supports subnormal numbers. Table 56. NaN inputs yield an unspecified NaN. d = -a.f32 supported on all target architectures. sm_1x: abs. abs.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. d.ftz. Subnormal numbers: sm_20: By default.ftz}. a. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.

min. min. max. min{. min.f32 flushes subnormal inputs and results to sign-preserving zero. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.ftz. d.f32 max.b.ftz}. Table 58.c. a.f64 d.f64 f0. 2010 .f64 requires sm_13 or later.ftz}.0.f32 flushes subnormal inputs and results to sign-preserving zero. max{.b. b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. sm_1x: min. Store the maximum of a and b in d.x.ftz. d d d d = = = = NaN.ftz.f32 min. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. 92 January 24.f64 requires sm_13 or later. max. max.f32 supported on all target architectures. b.f1. min. subnormal numbers are supported. (a < b) ? a : b.f32 flushes subnormal inputs and results to sign-preserving zero. d d d d = = = = NaN.f32 supported on all target architectures.f32 max.0. max. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. d. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.f64 supports subnormal numbers. (a > b) ? a : b. a. a. a.f32 min. subnormal numbers are supported.f64 supports subnormal numbers.ftz.z.0 Table 57. Store the minimum of a and b in d.c. a. @p min. b.f32 flushes subnormal inputs and results to sign-preserving zero. b.f64 z. sm_1x: max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. max. b.f2.f64 d.PTX ISA Version 2. b.

rcp.rm mantissa LSB rounds towards negative infinity .f64 introduced in PTX ISA version 1.approx and .0 +subnormal +Inf NaN Result -0. rcp.f32 rcp.4. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rm.f32 rcp.4 and later.approx.3. .f64 requires sm_20 or later.0.rp }.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA versions 1. // fast. rcp. Target ISA Notes rcp.rm. rcp.rn.rn.approx{.x.ftz. a. Instruction Set Table 59.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .ftz were introduced in PTX ISA version 1.approx.rn.ftz. store result in d.rz.0 -Inf -Inf +Inf +Inf +0. d = 1 / a.f64 requires sm_13 or later.rn.rnd = { .f32 requires sm_20 or later.0.f32 defaults to rcp.f32 rcp. subnormal numbers are supported.approx.f64 and explicit modifiers . 2010 93 .rn mantissa LSB rounds to nearest even . xi. rcp.approx or .0 over the range 1.0 +0.ftz.rnd. d. a. For PTX ISA version 1.rp}. rcp.rnd{.f32. The maximum absolute error is 2-23. rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. and rcp. .x.Chapter 8.f32 rcp. d.f64 d. Input -Inf -subnormal -0. sm_1x: rcp.f64 supports subnormal numbers.f32 implements a fast approximation to reciprocal.approx.rnd.f64.f32 flushes subnormal inputs and results to sign-preserving zero.0-2. PTX ISA Notes rcp. rcp. xi.rz mantissa LSB rounds towards zero . rcp.0.f64 ri.ftz. one of . rcp.f64 defaults to rcp. General rounding modifiers were added in PTX ISA version 2. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . Description Semantics Notes Compute 1/a. a.0 through 1. Examples January 24.rn.{rz.rn. .r.ftz}.f32 supported on all target architectures.f32 and rcp.rnd is required.

sqrt. // fast.ftz were introduced in PTX ISA version 1.0.f32 supported on all target architectures.x.x. store in d.approx. sqrt. Target ISA Notes sqrt. . sm_1x: sqrt.f32 defaults to sqrt.f64. sqrt.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rp}.approx{.f32 implements a fast approximation to square root.rn.0 through 1. Examples 94 January 24.ftz}.approx or . d = sqrt(a).approx.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 defaults to sqrt. sqrt.approx.0 +0.x.0 +subnormal +Inf NaN Result NaN NaN -0. Input -Inf -normal -subnormal -0.rn.f32 is TBD. The maximum absolute error for sqrt.rnd.rm.rz.f32 sqrt. r.0 -0.0 Table 60. one of .rm mantissa LSB rounds towards negative infinity .{rz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 and sqrt.f64 supports subnormal numbers. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.rn.4. // IEEE 754 compliant rounding .f64 d. For PTX ISA versions 1. sqrt.ftz.ftz. PTX ISA Notes sqrt. sqrt. a. approximate square root d. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero. General rounding modifiers were added in PTX ISA version 2. Description Semantics Notes Compute sqrt(a).rp }.approx.f32.4 and later. a.0 +0. // IEEE 754 compliant rounding d. sqrt.f32 requires sm_20 or later.0.PTX ISA Version 2.rz mantissa LSB rounds towards zero . r. a.approx and .f64 introduced in PTX ISA version 1.rnd = { .rm.f64 requires sm_13 or later.rn. sqrt.rn mantissa LSB rounds to nearest even .f64 and explicit modifiers . and sqrt.ftz}.ftz.0 +0. .f64 requires sm_20 or later.rnd is required.f32 sqrt.rnd{.3. For PTX ISA version 1.approx.f64 r.f32 sqrt.ftz.rn. .rnd.f32 sqrt. sqrt.rn. subnormal numbers are supported. sqrt.

0 through 1.approx.f32 defaults to rsqrt.approx modifier is required.f32 rsqrt.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.4 and later.f64 d. d = 1/sqrt(a).approx and .4 over the range 1.f64 were introduced in PTX ISA version 1.f32 supported on all target architectures.4. x. PTX ISA Notes rsqrt. d.0 NaN The maximum absolute error for rsqrt.f64 isr.approx. rsqrt.approx implements an approximation to the reciprocal square root. a.0 +0. Instruction Set Table 61. the . subnormal numbers are supported. The maximum absolute error for rsqrt.Chapter 8.0. store the result in d.f64. and rsqrt. Compute 1/sqrt(a).approx. Target ISA Notes Examples rsqrt.approx. Subnormal numbers: sm_20: By default.ftz}. Note that rsqrt. rsqrt.f32 rsqrt. rsqrt.f64 supports subnormal numbers.0-4. Explicit modifiers .f32 is 2-22. For PTX ISA versions 1. rsqrt. For PTX ISA version 1.approx.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. a. 2010 95 . ISR.f64 is emulated in software and are relatively slow. rsqrt.ftz. rsqrt. January 24. X.f64 is TBD. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f64 defaults to rsqrt.f32. sm_1x: rsqrt.ftz. Input -Inf -normal -subnormal -0.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.f32 and rsqrt.3.ftz were introduced in PTX ISA version 1. rsqrt.0.approx{.approx.

0 +0.0.approx. sin. a. the .approx and .f32 sa.f32 introduced in PTX ISA version 1.ftz.ftz introduced in PTX ISA version 1.approx. 2010 . PTX ISA Notes sin. For PTX ISA versions 1. For PTX ISA version 1.4.0 -0. 96 January 24. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. sin.ftz}.0 +0.9 in quadrant 00.approx{. Explicit modifiers . Find the sine of the angle a (in radians).0 Table 62.f32 flushes subnormal inputs and results to sign-preserving zero. sin.0 +0.ftz.f32 d.ftz. d = sin(a). sm_1x: Subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default. Target ISA Notes Examples Supported on all target architectures. subnormal numbers are supported.f32 defaults to sin.PTX ISA Version 2.approx modifier is required. sin. a.4 and later.0 +subnormal +Inf NaN Result NaN -0.approx. Input -Inf -subnormal -0.3.0 through 1.f32 implements a fast approximation to sine.0 NaN NaN The maximum absolute error is 2-20.f32. sin.

approx.Chapter 8. cos.4. the . cos. 2010 97 . Target ISA Notes Examples Supported on all target architectures. a. cos.approx modifier is required.0 +0. a.0.0 NaN NaN The maximum absolute error is 2-20.f32 d. d = cos(a). January 24. Find the cosine of the angle a (in radians).approx{. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to cosine.approx and . cos. Input -Inf -subnormal -0. For PTX ISA version 1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. Subnormal numbers: sm_20: By default.0 +subnormal +Inf NaN Result NaN +1.f32 defaults to cos.ftz}.approx.ftz introduced in PTX ISA version 1.0 +1. PTX ISA Notes cos.ftz.9 in quadrant 00.f32 flushes subnormal inputs and results to sign-preserving zero.f32 introduced in PTX ISA version 1.0 +1.ftz. Instruction Set Table 63.f32 ca.f32. For PTX ISA versions 1.3.4 and later. subnormal numbers are supported.approx.ftz. Explicit modifiers .0 +1. cos.0 through 1.

2010 .0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. The maximum absolute error is 2-22. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.0 +0.f32 Determine the log2 of a. lg2. 98 January 24.0 Table 64. Subnormal numbers: sm_20: By default.ftz}. lg2.approx modifier is required. Explicit modifiers . lg2. a.f32 la.f32 flushes subnormal inputs and results to sign-preserving zero.f32. PTX ISA Notes lg2. d = log(a) / log(2). For PTX ISA versions 1.f32 implements a fast approximation to log2(a).ftz introduced in PTX ISA version 1.ftz.approx.approx.4 and later.6 for mantissa.0 through 1.ftz. the . subnormal numbers are supported.3.f32 defaults to lg2.approx. sm_1x: Subnormal inputs and results to sign-preserving zero.approx{. a. lg2. Input -Inf -subnormal -0. lg2.ftz. For PTX ISA version 1.PTX ISA Version 2.4.f32 introduced in PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures.approx and .0.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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sm_1x: setp. {!}c.u32 p|q.b32. The destinations p and q must be . and nan returns true if either operand is NaN. gt. and higher-or-same may be used instead of lt.r. num. q = BoolOp(!t.type setp.s64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The untyped. . b. lo. p. lt. If either operand is NaN. This result is written to the first destination operand. .pred variables.B) is one of: and. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. c). If either operand is NaN. gtu.n. and can be one of: eq. Semantics t = (a CmpOp b) ? 1 : 0. ge. The comparison operator is a suffix on the instruction.ftz}.eq.u16. hi. 102 January 24.s32.lt. . neu. Subnormal numbers: sm_20: By default.b16.f64 source type requires sm_13 or later. 2010 . gtu. ls. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. ge.PTX ISA Version 2. the comparison operators lo.type . and hs for lower. lt. lt. . and (optionally) combine this result with a predicate value by applying a Boolean operator. higher.u64. To aid comparison operations in the presence of NaN values.f32 comparisons. @q setp. subnormal numbers are supported.f32 flushes subnormal inputs to sign-preserving zero.dtype. gt.dtype.CmpOp.b. The signed and unsigned comparison operators are eq. setp. setp with . Applies to all numeric types. gt.f32 flushes subnormal inputs to sign-preserving zero.u32. . loweror-same. ltu.0.BoolOp{. nan The Boolean operator BoolOp(A.ftz}. ge.i.0 Table 67. leu.f64 supports subnormal numbers. bit-size comparisons are eq and ne. .s32 setp. hs equ. neu. leu. le. ne. xor. A related value computed using the complement of the compare result is written to the second destination operand. le. respectively.s16.b64.ftz applies only to . Modifier .dtype. For unsigned values. b. geu. c). . p[|q].type = { . hi. ne.f64 }. If both operands are numeric values (not NaN). the result is false. le.CmpOp{. Integer Notes Floating Point Notes The ordered comparisons are eq. .a. p[|q]. p = BoolOp(t.ftz.f32. geu. unordered versions are included: equ. . ls. then the result of these comparisons is true. ltu. a. gt. ge. . setp. num returns true if both operands are numeric values (not NaN). or. setp. then these comparisons have the same result as their ordered counterparts.and. ne. a. le.

s16.dtype.b16.dtype.0. The selected input is copied to the output without modification. a. slct. based on the value of the predicate source operand.s32 x.t. . slct. b.f32 r0. a is stored in d. operand c must match the second instruction type. val.s32. . b otherwise.s32 slct{.u64. fval.b16.f32 d. .u64.f64 requires sm_13 or later. slct Syntax Comparison and Selection Instructions: slct Select one source operand. f0.s16.dtype = { . . selp. and b must be of the same type. negative zero equals zero. sm_1x: slct. Operand c is a predicate. a. Modifier . otherwise b is stored in d.b64.f64 }.f64 requires sm_13 or later. and operand a is selected. z.ftz applies only to . .g. based on the sign of the third operand. . slct. Description Conditional selection. . C. and b are treated as a bitsize type of the same width as the first instruction type. If c is True. .p. c. . . @q selp.dtype. a is stored in d.u32. selp.dtype.f32 flushes subnormal values of operand c to sign-preserving zero.s32 selp. Subnormal numbers: sm_20: By default.s64. If operand c is NaN.u16.b32. and operand a is selected.f32.Chapter 8. .0.f32 flushes subnormal values of operand c to sign-preserving zero. d.b32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u32.b64.f32 A. slct.f64 }.s32.u64. Operands d. . If c ≥ 0.ftz. a. a.type d. . Semantics Floating Point Notes January 24.u16. a. selp Syntax Comparison and Selection Instructions: selp Select between source operands. 2010 103 . subnormal numbers are supported. the comparison is unordered and operand b is selected.s64. . Operands d. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.f32 comparisons.u32. c.ftz}. . . For . b.ftz. d = (c >= 0) ? a : b. B.r. y. . .f32 comparisons. . Instruction Set Table 68.type = { . Table 69. slct. b. Introduced in PTX ISA version 1. .xp.f32.x. . c. d = (c == 1) ? a : b. .

Instructions and. performing bit-wise operations on operands of any type. and not also operate on predicates. This permits bit-wise operations on floating point values without having to define a union to access the bits.0 8.7. xor. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.PTX ISA Version 2. or. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. provided the operands are of the same size.4. 2010 .

pred. The size of the operands must match. Allowed types include predicate registers.q. Supported on all target architectures.b32 and.b16. b. .type d. or. . Table 71.b16. sign. d = a & b. Introduced in PTX ISA version 1. . . Instruction Set Table 70.fpvalue.b64 }.r.Chapter 8.pred p. a. a.type = { . but not necessarily the type. and.0. January 24. d = a | b.b32 mask mask.r. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.type d. and. or. . The size of the operands must match.0.0x00010001 or. . and Syntax Logic and Shift Instructions: and Bitwise AND.b32 x. Supported on all target architectures. or Syntax Logic and Shift Instructions: or Bitwise OR.b32. .b64 }.0x80000000.b32. b. but not necessarily the type. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.pred. 2010 105 .q. .type = { .

. d.q. Allowed types include predicates. xor. not. 2010 . Introduced in PTX ISA version 1.pred. cnot.pred.b64 }. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). . Introduced in PTX ISA version 1.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b32.type d. one’s complement. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. .b64 }. but not necessarily the type. d = ~a. The size of the operands must match.0x0001.type = { .x. Supported on all target architectures.b32 xor. . but not necessarily the type. The size of the operands must match.r. cnot. Table 74.mask.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b16. . . Introduced in PTX ISA version 1. a. not Syntax Logic and Shift Instructions: not Bitwise negation.type = { . . . .0.type = { . xor. d = a ^ b.b32. Allowed types include predicate registers. Table 73. not.b16. 106 January 24.q.b16.a.pred p. a. The size of the operands must match.0. b.b32 mask. Supported on all target architectures.PTX ISA Version 2. Supported on all target architectures. but not necessarily the type. not.0. d = (a==0) ? 1 : 0.b16 d.b32 d.type d. a.type d. .0 Table 72. .

PTX ISA Notes Target ISA Notes Examples January 24. shl. shr.s32. shr Syntax Logic and Shift Instructions: shr Shift bits right.b16.b64 }. zero-fill on right. .0. but not necessarily the type.type = { . . a. d = a >> b. Bit-size types are included for symmetry with SHL. Instruction Set Table 75.1.j.i.a. regardless of the instruction type.u32. Shift amounts greater than the register width N are clamped to N. Supported on all target architectures.0.b32. k.u16. . unsigned and untyped shifts fill with 0. but not necessarily the type. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. The b operand must be a 32-bit value.s32 shr.b32 q.a. shr. a. . .i.type d. Signed shifts fill with the sign bit. sign or zero fill on left. Introduced in PTX ISA version 1. shl.type = { .Chapter 8. b. d = a << b. i. regardless of the instruction type. Supported on all target architectures. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. The sizes of the destination and first source operand must match.u16 shr. .s16. .2.b16 c.u64. 2010 107 . . .s64 }.type d. . The b operand must be a 32-bit value. .b64. shl Syntax Logic and Shift Instructions: shl Shift bits left. b. . PTX ISA Notes Target ISA Notes Examples Table 76.b16. Introduced in PTX ISA version 1.b32. The sizes of the destination and first source operand must match. Shift amounts greater than the register width N are clamped to N.2.

ld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. st. Data Movement and Conversion Instructions These instructions copy data from place to place. possibly converting it from one format to another. or shared state spaces. and sust support optional cache operations. mov. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.7.PTX ISA Version 2. The cvta instruction converts addresses between generic and global. local. prefetchu isspacep cvta cvt 108 January 24.5. suld. and st operate on both scalar and vector types. and from state space to state space. 2010 . Instructions ld.0 8. ldu.

Operator .5.ca. rather than the data stored by the first thread.cs Cache streaming. bypassing the L1 cache.ca. The ld.lu instruction performs a load cached streaming operation (ld.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. When ld. January 24. A ld. not L1).cv to a frame buffer DRAM address is the same as ld. The cache operators require a target architecture of sm_20 or later. Global data is coherent at the L2 level. Cache Operators PTX 2.lu load last use operation.cs is applied to a Local window address. Use ld. but multiple L1 caches are not coherent for global data. the second thread may get stale L1 cache data. The ld.0 introduces optional cache operators on load and store instructions.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. and a second thread loads that address via a second L1 cache with ld. If one thread stores to global memory via one L1 cache.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. .Chapter 8. The default load instruction cache operation is ld. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. Instruction Set 8. to allow the thread program to poll a SysMem location written by the CPU.cv Cache as volatile (consider cached system memory lines stale. Table 77.lu operation.cg Cache at global level (cache in L2 and below. if the line is fully covered. . fetch again).7.cg to cache loads only globally. . evict-first. likely to be accessed once.cs) on global addresses.1. invalidates (discards) the local L1 line following the load. The ld. 2010 109 . The ld.ca loads cached in L1.cs. likely to be accessed again. the cache operators have the following definitions and behavior. The compiler / programmer may use ld. For sm_20 and later.lu Last use.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. any existing cache lines that match the requested address in L1 will be evicted. . it performs the ld. and cache only in the L2 cache. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. when applied to a local address. As a result of this request.

0 Table 78.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. and marks local L1 lines evict-first. Use st.cg to local memory uses the L1 cache. The default store instruction cache operation is st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. 2010 . rather than get the data from L2 or memory stored by the first thread. and discard any L1 lines that match. the second thread may get a hit on stale L1 cache data. which writes back cache lines of coherent cache levels with normal eviction policy. However.cg to cache global store data only globally.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. and cache only in the L2 cache. In sm_20.ca.wb for global data. . in which case st.PTX ISA Version 2. and a second thread in a different SM later loads from that address via a different L1 cache with ld.wb. to allow a CPU program to poll a SysMem location written by the GPU with st. Addresses not in System Memory use normal write-back. likely to be accessed once. If one thread stores to global memory. 110 January 24. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wt Cache write-through (to system memory).wb could write-back global store data from L1.cs Cache streaming. but st.ca loads. regardless of the cache operation. bypassing the L1 cache. .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. The st. st.wt. bypassing its L1 cache. not L1). The st.cg is the same as st. Global stores bypass L1. Future GPUs may have globally-coherent L1 caches.cg Cache at global level (cache in L2 and below. Operator .

.a. A[5].const.type d.u32 mov. .f64 requires sm_13 or later.u16.type = { .u16 mov. mov. or function name. Semantics d = a.global.shared state spaces. d = &avar. . Instruction Set Table 79.u64.e. myFunc. sreg.s32. . alternately.u32 mov. . For variables declared in . d = &label.local. 2010 111 . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. d = sreg. or shared state space. mov places the non-generic address of the variable (i. d.. label. k.b64. mov. d. the address of the variable in its state space) into the destination register. // get address of variable // get address of label or function . Operand a may be a register. mov. within the variable’s declared state space Notes Although only predicate and bit-size types are required. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. local. . Description .f32 mov. label.f32.Chapter 8. the generic address of a variable declared in global. a. special register. Write register d with the value of a.e.type mov.type mov. or shared state space may be taken directly using the cvta instruction. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.b32. avar.pred. .v.type mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. the parameter will be copied onto the stack and the address will be in the local state space. . .1. Note that if the address of a device function parameter is moved to a register.f32 mov. local. immediate.b16. addr.u32.u32 d.0. . d. // address is non-generic. . ptr. A.f64 }.s16. and . local. . . u. variable in an addressable memory space. Introduced in PTX ISA version 1.0. The generic address of a variable in global. Take the non-generic address of a variable in global. i.s64. ptr.

y << 16) | (a.b8 r.b64 { d. d.x | (a. // // // // a.b32 // pack two 16-bit elements into .w}. a[16..b32 mov..hi}..type = { .y.b32 // pack four 16-bit elements into .47].PTX ISA Version 2..x.w have type .31].x.31]. d.b16. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.x | (a.b64 // pack two 32-bit elements into .63] } // unpack 16-bit elements from . a[16. .b. a[16.7].y.b.w } = { a[0. d. d.z..z.z << 16) | (a.15] } // unpack 8-bit elements from .31] } // unpack 8-bit elements from . d.g.x | (a.hi are . Supported on all target architectures.b32 { d.b32..b16 { d.%r1.b}.z.{a. a.b64 112 January 24.y } = { a[0. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b32 mov. .type d.b32 %r1.x..b64 }.b32 { d. a[24. {lo. %r1.z << 32) | (a. a[32.w << 48) d = a. d.b have type .x. d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mov..x | (a.g. d. {r. a[32..y << 32) // pack two 8-bit elements into . Description Write scalar register d with the packed value of vector register a. %x.a have type .y << 8) d = a.{x.u16 %x is a double.u8 // unpack 32-bit elements from . lo.31] } // unpack 16-bit elements from .z.y.0.15].b64 { d.23]. . or write vector register d with the unpacked values from scalar register a. a[8. d.y.y } = { a[0.0 Table 80..b16 // pack four 8-bit elements into . mov.15]. 2010 ..w << 24) d = a.b64 mov. For bit-size types.7].x | (a.15]..y } = { a[0.u32 x..a}. Semantics d = a. a[48.w } = { a[0.x..y << 8) | (a. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).y << 16) d = a. a[8.

If no state space is given.volatile.volatile{. d. 2010 113 .volatile.e. .volatile introduced in PTX ISA version 1. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. *(immAddr).local. . 32-bit).b16. d. an address maps to global memory unless it falls within the local memory window or the shared memory window.ss = { . ld{. Generic addressing and cache operations introduced in PTX ISA 2. [a]. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .u32.u16. or [immAddr] an immediate absolute byte address (unsigned.v4 }.f64 using cvt. . for example. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Generic addressing may be used with ld.b16.s16.b32.shared spaces to inhibit optimization of references to volatile memory. Description Load register variable d from the location specified by the source address operand a in specified state space. and is zeroextended to the destination register width for unsigned and bit-size types.volatile{.global. .0. . . .b64.f16 data may be loaded using ld.type = { . Addresses are zero-extended to the specified width as needed. an address maps to the corresponding location in local or shared memory. If an address is not properly aligned.f64 }. . .ss}.e. and then converted to . the resulting behavior is undefined. The value loaded is sign-extended to the destination register width for signed integers. This may be used.vec.type ld{.Chapter 8.type d. and truncated if the register width exceeds the state space address width for the target architecture. Within these windows. . . ld. Cache operations are not permitted with ld. Semantics d d d d = = = = a.. The address must be naturally aligned to a multiple of the access size. . In generic addressing.u8. PTX ISA Notes January 24.b8.ss}{.v2. .ss}. . . The address size may be either 32-bit or 64-bit.s32. ld.0.cop}. .type ld.global and . i. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .cop}. to enforce sequential consistency between threads accessing shared memory. perform the load using generic addressing.lu. .reg state space.cv }. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. The .cg.f32 or . . [a].vec = { .cs. 32-bit).const. .type . A destination register wider than the specified type may be used.ss}{. or the instruction may fault.s8. [a]. ld introduced in PTX ISA version 1. an integer or bit-size type register reg containing a byte address. . Instruction Set Table 81.s64.const space suffix may have an optional bank number to indicate constant banks other than bank zero. .ca. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. i.1.cop = { .volatile may be used with .u64. . . .f32. *(a+immOff).vec.shared }. *a. . d.param. [a]. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.

[p+4]. ld.const[4].const.%r. Cache operations require sm_20 or later. // access incomplete array x.s32 ld.[p+-8].[p]. Q.global. %r. // load .f32 ld.local.[a].f32.b64 ld. // negative offset %r. 2010 .[fs].0 Target ISA Notes ld.b32 ld.PTX ISA Version 2.f64 requires sm_13 or later. // immediate address %r.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.b32 ld.f16 d. Generic addressing requires sm_20 or later. d.[buffer+64].local.v4.[240]. x.b32 ld.b16 cvt.global.shared.

2010 115 . PTX ISA Notes Target ISA Notes Examples January 24.[p+4].s32. 32-bit). . the resulting behavior is undefined. or the instruction may fault.e.type = { .global.s64. .b16. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.global }. // state space .u8.Chapter 8. Addresses are zero-extended to the specified width as needed.. . [a]. perform the load using generic addressing. 32-bit). and is zeroextended to the destination register width for unsigned and bit-size types. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . ldu. If an address is not properly aligned. d.ss}. where the address is guaranteed to be the same across all threads in the warp. *(a+immOff).v2.f32 or . A destination register wider than the specified type may be used. Semantics d d d d = = = = a. The data at the specified address must be read-only. *a. . ldu.global.b8. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.f32 Q.f64 using cvt. an address maps to global memory unless it falls within the local memory window or the shared memory window.type ldu{. .b16.b64. ldu{. The address size may be either 32-bit or 64-bit. Within these windows. i.u16.f32 d.v4. . The address must be naturally aligned to a multiple of the access size.s16. and truncated if the register width exceeds the state space address width for the target architecture. only generic addresses that map to global memory are legal. ldu. // load from address // vec load from address . ldu.ss}. or [immAddr] an immediate absolute byte address (unsigned.[p]. . . For ldu. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.e. A register containing an address may be declared as a bit-size type or integer type.ss = { . [a].v4 }. *(immAddr). the access may proceed by silently masking off low-order address bits to achieve proper rounding. i.vec = { . Introduced in PTX ISA version 2. Instruction Set Table 82. If no state space is given.b32.global.u64. . In generic addressing. . an address maps to the corresponding location in local or shared memory.s8.b32 d. and then converted to . .type d.[a]. The addressable operand a is one of: [avar] the name of an addressable variable var.f16 data may be loaded using ldu.reg state space.u32.f64 requires sm_13 or later.f64 }. .f32. . [areg] a register reg containing a byte address.vec. . The value loaded is sign-extended to the destination register width for signed integers.0. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. .

s16. to enforce sequential consistency between threads accessing shared memory.b8. st introduced in PTX ISA version 1.cop}. The address size may be either 32-bit or 64-bit. PTX ISA Notes Target ISA Notes 116 January 24.wt }.global. . an address maps to global memory unless it falls within the local memory window or the shared memory window. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.vec. . .ss}{.shared spaces to inhibit optimization of references to volatile memory. *(d+immOffset) = a. b. The address must be naturally aligned to a multiple of the access size. { .global and .e. Cache operations are not permitted with st. .s32.volatile introduced in PTX ISA version 1.0. . In generic addressing. .u64. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.v2.ss .f32.cop}.ss}.volatile. This may be used.1.u32.b32. or the instruction may fault.v4 }.u8.s8.type . .ss}. st.. 32-bit).b64.volatile{. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . i. { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. 32-bit).e. the resulting behavior is undefined. . . 2010 .type = = = = {.type [a]. .f64 requires sm_13 or later.f16 data resulting from a cvt instruction may be stored using st. If no state space is given. b. Cache operations require sm_20 or later. .cop . st. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. .s64.b16. st{. The lower n bits corresponding to the instruction-type width are stored to memory. { . for example.PTX ISA Version 2.volatile.reg state space. Generic addressing and cache operations introduced in PTX ISA 2. b. [a].vec . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. *(immAddr) = a.b16. .type st. .cg.local. i. Semantics d = a. Generic addressing requires sm_20 or later.u16. A source register wider than the specified type may be used. [a].shared }. . . Generic addressing may be used with st.wb. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .vec. If an address is not properly aligned. .volatile{. Within these windows. Addresses are zero-extended to the specified width as needed. or [immAddr] an immediate absolute byte address (unsigned.f64 }. perform the store using generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. st.0 Table 83.cs. an integer or bit-size type register reg containing a byte address. [a].0.volatile may be used with . . an address maps to the corresponding location in local or shared memory.type st{. . b.ss}{. *d = a. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.

f16. Instruction Set Examples st. [fs].f32 st. // immediate address %r. 2010 117 .%r.b32 st.local.a.local. [q+4]. // negative offset [100]. // %r is 32-bit register // store lower 16 bits January 24.s32 st.global.%r.a.global. [q+-8]. [p].b32 st.Chapter 8.f32 st.b.local.Q.b16 [a].r7.v4.s32 cvt.

in specified state space. [a].PTX ISA Version 2.L1 [ptr].global.space = { . or [immAddr] an immediate absolute byte address (unsigned. The address size may be either 32-bit or 64-bit. a register reg containing a byte address. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. an address maps to global memory unless it falls within the local memory window or the shared memory window.L1 [a]. 2010 . the prefetch uses generic addressing.global. 32-bit). and truncated if the register width exceeds the state space address width for the target architecture. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. If no state space is given.L1 [addr].L1.level = { .e.space}. In generic addressing. prefetch and prefetchu require sm_20 or later. . // prefetch to data cache // prefetch to uniform cache .local }. prefetchu. 32-bit). i. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 84.0. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L2 }. an address maps to the corresponding location in local or shared memory. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. prefetch. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. A prefetch to a shared memory location performs no operation. Addresses are zero-extended to the specified width as needed. . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. prefetch{. A prefetch into the uniform cache requires a generic address. Within these windows. and no operation occurs if the address maps to a local or shared memory location. 118 January 24.level prefetchu. .

u32 or .u32 p.space = { . gptr.size p. January 24. cvta.local.u32 to truncate or zero-extend addresses.u64 or cvt. // local. p.pred. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The source address operand must be a register of type . or shared state space.global isspacep.global.shared isglbl.0. cvta requires sm_20 or later.space = { .0. isspacep.space p. a. or shared state space. 2010 119 .local. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. Introduced in PTX ISA version 2. local.size . . .shared. local. or shared state space to generic. // convert to generic address // get generic address of var // convert generic address to global. isspacep requires sm_20 or later.global.space. PTX ISA Notes Target ISA Notes Examples Table 86. local. A program may use isspacep to guard against such incorrect behavior. p. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.lptr.u32 p. svar.u32 gptr. cvta.genptr. . or shared address.space.Chapter 8.size = { . islcl. lptr. The source and destination addresses must be the same size.local. isspacep.local isspacep.size cvta.to. // get generic address of svar cvta. or vice-versa.u32. cvta. When converting a generic address into a global.pred . var. a. isshrd. local.space. Take the generic address of a variable declared in global. or vice-versa.shared }. a. .u64. the generic address of the variable may be taken using cvta. or shared address cvta.shared }.to. Instruction Set Table 85. For variables declared in global.u64. or shared address to a generic address. // result is . isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. .global. . local. Description Convert a global.u64 }. Use cvt. sptr.u32. The destination register must be of type .

. . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. .f64 }.ftz}{.rpi }. .f16. Integer rounding is illegal in all other instances. . . Note that saturation applies to both signed and unsigned integer types. .f32.rzi. subnormal inputs are flushed to signpreserving zero. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.0 Table 87. choosing even integer if source is equidistant between two integers.s64.sat}.ftz. d = convert(a).s16. and for same-size float-tofloat conversions where the value is rounded to an integer. // integer rounding // fp rounding .dtype = .dtype.u16. .sat}. Saturation modifier: .u64. subnormal numbers are supported.rni. .atype = { .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.s8. Integer rounding modifiers: .e. d.rmi round to nearest integer in direction of negative infinity . i.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.atype d.atype cvt{.rzi round to nearest integer in the direction of zero .frnd = { . .dtype. For cvt.f32 float-to-integer conversions and cvt. the result is clamped to the destination range by default.irnd = { .MAXINT for the size of the operation. the . . 2010 . The compiler will preserve this behavior for legacy PTX code.ftz.rz.rni round to nearest integer.f32.f32 float-tofloat conversions with integer rounding. For float-to-integer conversions.rp }.f32 float-to-integer conversions and cvt.u32. The optional .e.rmi.s32.4 and earlier..sat limits the result to MININT. . .sat is redundant. .frnd}{. .dtype.f32 float-tofloat conversions with integer rounding. .u8.ftz}{.PTX ISA Version 2. cvt{. a. 120 January 24. sm_1x: For cvt.sat For integer destination types. Integer rounding is required for float-to-integer conversions. . Note: In PTX ISA versions 1. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. a.irnd}{. .rn.. . subnormal inputs are flushed to signpreserving zero. .dtype.ftz.rm.ftz. .f32. Description Semantics Integer Notes Convert between different types and sizes. i.ftz modifier may be specified in these cases for clarity.

4 or earlier.0. result is fp cvt. subnormal numbers are supported.sat For floating-point destination types.f32 x.rm mantissa LSB rounds towards negative infinity . 1.f64. 2010 121 .f32 instructions.rni. if the PTX .f64 j. The result is an integral value. and cvt. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. // float-to-int saturates by default cvt.s32 f. Applies to .f32.rn mantissa LSB rounds to nearest even .i. The operands must be of the same size.0]. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. // round to nearest int.s32.y.f64 requires sm_13 or later. Modifier . .version is 1.f16.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. .f32.r. Introduced in PTX ISA version 1. cvt to or from . The compiler will preserve this behavior for legacy PTX code.f32.f32 x. cvt. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64 types. cvt. // note .f32.0.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Subnormal numbers: sm_20: By default.4 and earlier. Note: In PTX ISA versions 1.f16.ftz modifier may be specified in these cases for clarity.f32. cvt.f32.y. and for integer-to-float conversions. Floating-point rounding is illegal in all other instances. stored in floating-point format. Specifically.sat limits the result to the range [0. and .rz mantissa LSB rounds towards zero .f32. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f16.Chapter 8. Saturation modifier: .ftz behavior for sm_1x targets January 24. Floating-point rounding modifiers: . The optional . NaN results are flushed to positive zero.

f32 r1. 2010 . add. Example: calculate an element’s power contribution as element’s power/total number of elements.entry compute_power ( . texture and sampler information each have their own handle. r3. mul. r5. Module-scope and per-entry scope definitions of texture. r3.u32 r5. and surface descriptors. div.f32 r1. // get tex1’s tex. If no texturing mode is declared. {f1. .target options ‘texmode_unified’ and ‘texmode_independent’. In the independent mode.samplerref tsamp1 = { addr_mode_0 filter_mode }.6. sampler. sampler. // get tex1’s txq. r1. The advantage of unified mode is that it allows 128 samplers. [tex1].f32 r3. allowing them to be defined separately and combined at the site of usage in the program.v4. sampler. Texture and Surface Instructions This section describes PTX instructions for accessing textures.texref handle. = nearest width height tsamp1. add.b32 r5. samplers. r1. and surface descriptors: • • • Static initialization of texture. r5. . but the number of samplers is greatly restricted to 16. } = clamp_to_border.f32 r1. r2.u32 r5.texref tex1 ) { txq. The advantage of independent mode is that textures and samplers can be mixed and matched. Texturing modes For working with textures and samplers.f2}]. sampler. r1. with the restriction that they correspond 1-to-1 with the 128 possible textures. [tex1].f32.b32 r6.target texmode_independent . r5. and surface descriptors.global . add. 122 January 24. and surface descriptors. A PTX module may declare only one texturing mode.f32 {r1. Ability to query fields within texture.r4}. texture and sampler information is accessed through a single ..2d.r3. and surfaces. [tex1.r2. cvt. The texturing mode is selected using . In the unified mode.height.0 8.PTX ISA Version 2. . r6..7. r4. PTX has two modes of operation. the file is assumed to use unified mode.width.param . PTX supports the following operations on texture.f32.

f2.v4. [a. // Example of independent mode texturing tex.s32. //Example of unified mode texturing tex.r4}. i. . or the instruction may fault. Operand c is a scalar or singleton tuple for 1d textures.s32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Unified mode texturing introduced in PTX ISA version 1. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.f3. Supported on all target architectures. .2d. [tex_a.f32 }. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. .s32 {r1. The instruction always returns a four-element vector of 32-bit values. An optional texture sampler b may be specified.5.3d.dtype.f32 {r1.r2. the sampler behavior is a property of the named texture.geom = { . d. . c]. Notes For compatibility with prior versions of PTX.e. where the fourth element is ignored.r3.v4.f32 }. 2010 123 .u32. [tex_a. // explicit sampler .v4. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.btype = { . [a. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.v4. A texture base address is assumed to be aligned to a 16-byte address. with the extra elements being ignored. {f1.r2. the square brackets are not required and .s32.geom. sampler_x.s32.r4}. the resulting behavior is undefined.Chapter 8. .btype tex.1d. is a two-element vector for 2d textures.f4}].0.1d.. b. tex.r3. PTX ISA Notes Target ISA Notes Examples January 24. If an address is not properly aligned.dtype = { . tex txq suld sust sured suq Table 88. Description Texture lookup using a texture coordinate vector. . {f1}].3d }.v4 coordinate vectors are allowed for any geometry. . Instruction Set These instructions provide access to texture and surface memory.geom. c]. and is a four-element vector for 3d textures. If no sampler is specified.dtype.btype d.

filter_mode.height . clamp_ogl.b32 d. [tex_A].addr_mode_0.0 Table 89.addr_mode_0 . Integer from enum { nearest.normalized_coords .tquery.PTX ISA Version 2. [tex_A]. Query: . mirror. addr_mode_2 }. txq.texref or .squery.b32 %r1. In unified mode. Supported on all target architectures. // texture attributes // sampler attributes .depth. [a]. Description Query an attribute of a texture or sampler. .addr_mode_1 . // unified mode // independent mode 124 January 24.width .filter_mode . [a].depth .addr_mode_0.samplerref variable. txq. linear } Integer from enum { wrap.b32 %r1.width. .b32 txq. clamp_to_edge.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d. 2010 .width.filter_mode.normalized_coords }.b32 %r1. sampler attributes are also accessed via a texref argument. txq. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. .tquery = { . [smpl_B].5.height.squery = { . . txq. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. and in independent mode sampler attributes are accessed via a separate samplerref argument. addr_mode_1. . Operand a is a .

p. is a two-element vector for 2d surfaces.b.b performs an unformatted load of binary data.f32 }. .r2}. 2010 125 . If the destination type is .s32 is returned.b8 . . and is a four-element vector for 3d surfaces.cs. .v4.geom{.cop . // for suld. G. sm_1x targets support only the .clamp. .b .w}]. Operand b is a scalar or singleton tuple for 1d surfaces.clamp field specifies how to handle out-of-bounds addresses: . the surface sample elements are converted to . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. SNORM.1d. .b16.dtype.surfref variable.u32. The lowest dimension coordinate represents a sample offset rather than a byte offset. // for suld. then . and cache operations introduced in PTX ISA version 2.f3.b.vec . .1d.e. suld.trap introduced in PTX ISA version 1.dtype .Chapter 8.clamp . Coordinate elements are of type .b32.v4. suld.trap {r1. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. or FLOAT data. suld Syntax Texture and Surface Instructions: suld Load from surface memory. A surface base address is assumed to be aligned to a 16-byte address. If the destination base type is . B. {f1. .f32.v2. .p.clamp = = = = = = { { { { { { d.u32. the resulting behavior is undefined. .b64 }. then .u32. then . {x. suld.trap suld. Target ISA Notes Examples January 24.s32.cop}. Destination vector elements corresponding to components that do not appear in the surface format are not written. // cache operation none. The . suld. .s32.cop}. or .0.y. additional clamp modifiers. . {x}]. if the surface format contains SINT data.p requires sm_20 or later.f2.vec. Instruction Set Table 90. and the size of the data transfer matches the size of destination operand d.f32 is returned. . b].s32.trap. i.b32.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. Description Load from surface memory using a surface coordinate vector.z.b supported on all target architectures.3d requires sm_20 or later.geom .geom{. if the surface format contains UINT data.b. .s32. Cache operations require sm_20 or later.cv }.v2. suld. .p .f32.3d. . suld.zero }. [a. and A components of the surface format.ca. b].3d }.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. [a. [surf_A. . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. or . // unformatted d.5.b32. Operand a is a . size and type conversion is performed as needed to convert from the surface sample format to the destination type.f4}.trap clamping modifier..2d. . suld.f32 based on the surface format as follows: If the surface format contains UNORM. the access may proceed by silently masking off low-order address bits to achieve proper rounding.cg. .clamp suld.v4 }.p is currently unimplemented. or the instruction may fault. suld. suld. If an address is not properly aligned.b64.clamp .u32 is returned.p.dtype . where the fourth element is ignored. // formatted .trap . [surf_B. .dtype.

cop}.s32. Coordinate elements are of type . . .clamp . or FLOAT data. sust. .b8 . size and type conversions are performed as needed between the surface sample format and the destination type.geom . The source vector elements are interpreted left-to-right as R.p requires sm_20 or later.ctype . The lowest dimension coordinate represents a sample offset rather than a byte offset.b.surfref variable. or . .f4}. B. or the instruction may fault.wt }. sust.b64 }. Cache operations require sm_20 or later. i.b // for sust. . 2010 .geom{.b.w}]. . A surface base address is assumed to be aligned to a 16-byte address. Operand a is a .b32.u32 is assumed. then .b supported on all target architectures. .v4.b32. . if the surface format contains UINT data. {r1. is a two-element vector for 2d surfaces. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.. .cop . b].zero }.f32 }.2d. The source data is then converted from this type to the surface sample format. .3d requires sm_20 or later. .f32 is assumed.v4 }.s32.f32} are currently unimplemented.geom{.s32.cop}. G.b32. .z.trap introduced in PTX ISA version 1. c.u32.v2. and cache operations introduced in PTX ISA version 2.p. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.e.p. none.trap clamping modifier. If an address is not properly aligned. if the surface format contains SINT data. sust. The size of the data transfer matches the size of source operand c. then .r2}. sust.3d. . [surf_B.b.{u32. The .PTX ISA Version 2. where the fourth element is ignored. {f1.f2.u32. the resulting behavior is undefined.s32.5.b16. . SNORM.trap sust.ctype.trap.b64.vec.f32. and is a four-element vector for 3d surfaces. {x}]. Surface sample components that do not occur in the source vector will be written with an unpredictable value. If the source type is . . b]. [a.clamp = = = = = = { { { { { { [a. . c.b performs an unformatted store of binary data.trap .f3.s32 is assumed.1d.clamp . // for sust.vec.trap [surf_A.ctype . sust. then .v2.vec . {x.clamp.0 Table 91. sust. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . sust Syntax Texture and Surface Instructions: sust Store to surface memory.p.3d }. sust. and A surface components. sust.f32.ctype. .cg. .1d.y.clamp field specifies how to handle out-of-bounds addresses: .0. Source elements that do not occur in the surface sample are ignored. additional clamp modifiers. If the source base type is . sm_1x targets support only the .wb. .p performs a formatted store of a vector of 32-bit data values to a surface sample. sust. // unformatted // formatted .p Description Store to surface memory using a surface coordinate vector. Operand b is a scalar or singleton tuple for 1d surfaces.clamp sust.p. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. Target ISA Notes Examples 126 January 24.cs.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. These elements are written to the corresponding surface sample components.

the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom = { .trap [surf_A. i.clamp [a. {x}]. where the fourth element is ignored. Coordinate elements are of type . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.min. sured.add.u64.p.surfref variable. The .u32. .1d. sured.u32 and . .Chapter 8.ctype = { . .ctype = { .0.b .clamp. Instruction Set Table 92.p performs a reduction on sample-addressed 32-bit data.u64 data.clamp [a.b]. // for sured.max. .or }.1d.2d.clamp . and the data is interpreted as . . and .3d }. .geom.b32 }.b.clamp field specifies how to handle out-of-bounds addresses: . // for sured. A surface base address is assumed to be aligned to a 16-byte address. 2010 127 . January 24. . . If an address is not properly aligned. and is a four-element vector for 3d surfaces. The lowest dimension coordinate represents a sample offset rather than a byte offset. . Operations add applies to .y}]. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.trap .op = { .b performs an unformatted reduction on .min. Reduction to surface memory using a surface coordinate vector.e.b]. min and max apply to .s32 types.b32. or .s32 is assumed. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32. the resulting behavior is undefined.b32 }.p.add. . .p .clamp = { . operations and and or apply to . .s32.s32. [surf_B.u32. or the instruction may fault. then .ctype. if the surface format contains SINT data.s32 types.2d.zero }.u32.ctype.op. sured.c.trap. // sample addressing .b32..b. .u32 based on the surface sample format as follows: if the surface format contains UINT data. is a two-element vector for 2d surfaces. sured.op.u32 is assumed. {x. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.c. r1. . r1. // byte addressing sured.b32. .u64.and. Operand a is a . .b32 type.u32.s32 or .trap sured. sured requires sm_20 or later. Operand b is a scalar or singleton tuple for 1d surfaces.geom.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. then . The instruction type is restricted to .

. 128 January 24.width . Supported on all target architectures. 2010 .5.query.height.0 Table 93.height . suq.width.surfref variable. [surf_A].b32 d. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute. Description Query an attribute of a surface. [a].width.query = { .depth }. Query: .PTX ISA Version 2.b32 %r1. . Operand a is a .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq.

The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Supported on all target architectures.0. ratio. } PTX ISA Notes Target ISA Notes Examples Table 95.f32 @q bra L23. p.s32 d. { add.c. Introduced in PTX ISA version 1. used primarily for defining a function body. @{!}p instruction. Instruction Set 8. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.b.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.0. Supported on all target architectures.x.s32 a.y.7. If {!}p then instruction Introduced in PTX ISA version 1. Execute an instruction or instruction block for threads that have the guard predicate true. { instructionList } The curly braces create a group of instructions.7.0.f32 @!p div. setp.eq. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. mov. {} Syntax Description Control Flow Instructions: { } Instruction grouping.Chapter 8. Threads with a false guard predicate do nothing.a. 2010 129 .

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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or }. all threads in the CTA participate in the barrier.red performs a predicate reduction across the threads participating in the barrier.sync without a thread count introduced in PTX ISA 1. bar.op. and then safely read values stored by other threads prior to the barrier.sync with an immediate barrier number is supported for sm_1x targets. bar. {!}c. . PTX ISA Notes Target ISA Notes Examples bar. Once the barrier count is reached.version 2. bar. d.red are population-count (. Since barriers are executed on a per-warp basis. bar. In conditionally executed code. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. January 24.red also guarantee memory ordering among threads identical to membar. and bar. Operand b specifies the number of threads participating in the barrier.Chapter 8. operands p and c are predicates.op = { .arrive. If no thread count is specified. bar. a{.0.sync 0. 2010 133 . and any-thread-true (. bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.red should not be intermixed with bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. b}. a.red instruction.u32 bar.sync) until the barrier count is met. {!}c. all-threads-true (.u32.cta. The result of . Each CTA instance has sixteen barriers numbered 0.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.red performs a reduction operation across threads. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). b}. Execution in this case is unpredictable. Description Performs barrier synchronization and communication within a CTA. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. Instruction Set Table 100.red.arrive does not cause any waiting by the executing threads. the final value is written to the destination register in all threads waiting at the barrier. The barrier instructions signal the arrival of the executing threads at the named barrier. Operands a. thread count. In addition to signaling its arrival at the barrier.{arrive. All threads in the warp are stalled until the barrier completes. the bar. When a barrier completes..sync or bar. Register operands. Only bar.red} introduced in PTX .and). it simply marks a thread's arrival at the barrier. it is as if all the threads in the warp have executed the bar instruction.{arrive.0. b.sync and bar. the optional thread count must be a multiple of the warp size.15.red} require sm_20 or later. threads within a CTA that wish to communicate via memory can store to memory. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).red. thread count.popc is the number of threads with a true predicate.arrive using the same active barrier. bar.red delays the executing threads (similar to bar.or). Note that a non-zero thread count is required for bar. and d have type .popc. execute a bar.sync bar. Register operands. Barriers are executed on a per-warp basis as if all the threads in a warp are active. The reduction operations for bar.pred . and the barrier is reinitialized so that it can be immediately reused.sync or bar. b. the waiting threads are restarted without delay. bar. if any thread in a warp executes a bar instruction. Thus.and. while .and and . a{. p.arrive a{.popc). Thus. bar. and bar.sync and bar. b}.

membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.gl.0. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.sys }.cta. including thoses communicating via PCI-E such as system and peer-to-peer memory. membar. . 134 January 24.gl} supported on all target architectures. membar. and memory reads by this thread can no longer be affected by other thread writes.gl} introduced in PTX .gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.sys. red or atom) has been performed when the value written has become visible to other clients at the specified level.PTX ISA Version 2. membar.cta. when the previous value can no longer be read. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar. membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. A memory write (e.{cta.cta Waits until all prior memory writes are visible to other threads in the same CTA.4. this is the appropriate level of membar.cta.level = { . 2010 .g. by st. membar. global.version 2.gl.sys introduced in PTX .gl will typically have a longer latency than membar.sys requires sm_20 or later. . membar.sys Waits until all prior memory requests have been performed with respect to all clients. that is.version 1. membar. . or system memory level.level.0 Table 101. level describes the scope of other clients for which membar is an ordering event. membar.{cta.g. For communication between threads in different CTAs or even different SMs. membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl.sys will typically have much longer latency than membar. membar. A memory read (e. PTX ISA Notes Target ISA Notes Examples membar.

by inserting barriers between normal stores and atomic operations to a common address.inc. min. atom. d. If no state space is given. or the instruction may fault. . Description // // // // // . For atom. the access may proceed by silently masking off low-order address bits to achieve proper rounding. 2010 135 .s32.g. . . atom{. perform the memory accesses using generic addressing. .and. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. i.u32.max }.exch.b32. or.u32. or [immAddr] an immediate absolute byte address.f32. min.min.s32. . . 32-bit operations.add. . Within these windows.b]. cas (compare-and-swap).space}.. and max.s32. an address maps to global memory unless it falls within the local memory window or the shared memory window. .op. .space}. . In generic addressing. performs a reduction operation with operand b and the value in location a.shared }. [a].f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. an address maps to the corresponding location in local or shared memory.u64.space = { .exch to store to locations accessed by other atomic operations. .u32 only .global. max. . min. b.op = { . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. The address must be naturally aligned to a multiple of the access size. .e.b32 only . A register containing an address may be declared as a bit-size type or integer type.type = { . [a]. . Operand a specifies a location in the specified state space.b32.f32 }. . . c. a de-referenced register areg containing a byte address. accesses to local memory are illegal. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.Chapter 8. January 24. . overwriting the original value. . The integer operations are add. the resulting behavior is undefined. . .add. and truncated if the register width exceeds the state space address width for the target architecture.or. The floating-point add.type atom{.type d. or by using atom. . and max operations are single-precision.e.op. The address size may be either 32-bit or 64-bit.dec. .cas. xor.b64 . The bit-size operations are and. e. If an address is not properly aligned. Addresses are zero-extended to the specified width as needed.. The inc and dec operations return a result in the range [0. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. .u32. .xor.f32 Atomically loads the original value at location a into destination register d. b. and exch (exchange). The floating-point operations are add. Instruction Set Table 102. i.u64 . and stores the result of the specified operation at location a. dec.b64. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. inc.

[x+4]. 2010 .f32. s) = (r > s) ? s exch(r.[p].cas.f32 atom.s. c) operation(*a. : r+1.PTX ISA Version 2. s) = s. atom. 64-bit atom. atom. : r-1.t) = (r == s) ? t operation(*a.my_new_val. atom.s32 atom.shared requires sm_12 or later. 64-bit atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.b32 d. b).[a].shared.max} are unimplemented. d. : r.{add.add. atom.1.max. atom.cas. Release Notes Examples @p 136 January 24. d.global.{min.my_val.0 Semantics atomic { d = *a. Introduced in PTX ISA version 1. b. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. cas(r.0.global requires sm_11 or later. *a = (operation == cas) ? : } where inc(r. s) = (r >= s) ? 0 dec(r.f32 requires sm_20 or later.0.exch} requires sm_12 or later.global.add. Use of generic addressing requires sm_20 or later.shared operations require sm_20 or later.

. . s) = (r >= s) ? 0 : r+1. min. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. min..b32. .add. dec(r. and max.or.u64 . or. Within these windows. Description // // // // .f32 Performs a reduction operation with operand b and the value in location a. and truncated if the register width exceeds the state space address width for the target architecture. and max operations are single-precision. .s32.type [a].type = { . . . accesses to local memory are illegal. an address maps to the corresponding location in local or shared memory. . or by using atom. The floating-point operations are add.exch to store to locations accessed by other reduction operations.op. a de-referenced register areg containing a byte address.u32. Semantics *a = operation(*a. . If no state space is given. Instruction Set Table 103. January 24. In generic addressing.global. The address must be naturally aligned to a multiple of the access size.b64. red. i. A register containing an address may be declared as a bit-size type or integer type.xor. or the instruction may fault.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.g.and.u32 only . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u32. The floating-point add. max. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. . . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The address size may be either 32-bit or 64-bit.add. b). dec. 32-bit operations.s32. . The integer operations are add. 2010 137 .f32. Notes Operand a must reside in either the global or shared state space. inc. i. .max }. s) = (r > s) ? s : r-1. perform the memory accesses using generic addressing.u32. . .b].f32 }. Operand a specifies a location in the specified state space.op = { . For red. an address maps to global memory unless it falls within the local memory window or the shared memory window. .e..u64. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. by inserting barriers between normal stores and reduction operations to a common address. where inc(r. Addresses are zero-extended to the specified width as needed. .Chapter 8. If an address is not properly aligned.space}.min. or [immAddr] an immediate absolute byte address. . The inc and dec operations return a result in the range [0. and stores the result of the specified operation at location a. .dec.inc.space = { .shared }. .e. .b32 only . b. overwriting the original value. . e. min. red{.s32. the resulting behavior is undefined. and xor. The bit-size operations are and. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.

max. Use of generic addressing requires sm_20 or later.f32.global.{min.add. red.shared requires sm_12 or later.add. Release Notes Examples @p 138 January 24.f32 red. 2010 . [p].0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [x+4].max} are unimplemented.shared. red. 64-bit red.global requires sm_11 or later red.PTX ISA Version 2. 64-bit red. red.add requires sm_12 or later. red.s32 red.my_val.1.f32 requires sm_20 or later.shared operations require sm_20 or later.0.global.2.and.b32 [a].

The destination predicate value is the same across all threads in the warp. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. .uni }.all. vote. {!}a.mode = { . Negate the source predicate to compute .uni. r1.pred vote.ballot.ballot. 2010 139 .pred vote. . vote requires sm_12 or later. not across an entire CTA. .p. {!}a.pred d.b32 p. Description Performs a reduction of the source predicate across threads in a warp.any True if source predicate is True for some active thread in warp.Chapter 8. p. vote. // get ‘ballot’ across warp January 24.ballot. In the ‘ballot’ form. vote.b32 requires sm_20 or later.all. Negating the source predicate also computes .any. The reduction modes are: . Note that vote applies to threads in a single warp.mode. .2.b32 d.uni. Instruction Set Table 104.none.not_all.q. vote. returns bitmask .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.ballot. Negate the source predicate to compute .q.all True if source predicate is True for all active threads in warp. vote. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. where the bit position corresponds to the thread’s lane id.uni True if source predicate has the same value in all active threads in warp. // ‘ballot’ form.

atype. 3. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). atype. perform a scalar arithmetic operation to produce a signed 34-bit result. 140 January 24. a{.s32) is specified in the instruction type. with optional data merge vop.sat}.dsel. b{.or zero-extend byte. taking into account the subword destination size in the case of optional data merging. .s33 values.secop = { .atype. Video Instructions All video instructions operate on 32-bit register operands. .b0.secop d.bsel}. .btype{.s32 }.sat} d. .dtype. 2. vop. extract and sign. c.sat} d. a{.bsel}. the input values are extracted and signor zero.extended internally to .bsel = { .btype{.dtype = .9.dsel = .atype.h0. . c. .u32. to produce signed 33-bit input values. b{.b3.btype = { . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. // 32-bit scalar operation.asel = . and btype are valid. Using the atype/btype and asel/bsel specifiers.asel}. .h1 }. 2010 . . The primary operation is then performed to produce an .b2.add.asel}.asel}. The type of each operand (. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. The general format of video instructions is as follows: // 32-bit scalar operation.min. a{.u32 or .0 8.7. optionally clamp the result to the range of the destination type. .dtype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. with optional secondary operation vop.dtype. 4. The sign of the intermediate result depends on dtype.btype{. or word values from its source operands.PTX ISA Version 2. .bsel}.max }. b{.s34 intermediate result. half-word.b1.atype = . The source and destination operands are all 32-bit registers. . all combinations of dtype.

S8_MIN ). .b1. c).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.max return MAX(tmp. tmp. c). U8_MAX. U16_MAX. S16_MIN ).min: return MIN(tmp. default: return tmp.s33 optSecOp(Modifier secop. tmp. Bool sign. c). U8_MIN ).b1: return ((tmp & 0xff) << 8) case . c). January 24.s33 c) { switch ( secop ) { . The lower 32-bits are then written to the destination operand. S8_MAX. c). U32_MIN ). S32_MIN ).s33 tmp. tmp. . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). 2010 141 . switch ( dsel ) { case . S16_MAX. } } .b3: if ( sign ) return CLAMP( else return CLAMP( case . Modifier dsel ) { if ( !sat ) return tmp. .s33 tmp. Instruction Set . The sign of the c operand is based on dtype. . tmp.b0. c). .h0. U16_MIN ). tmp. . S32_MAX.h0: return ((tmp & 0xffff) case .b2: return ((tmp & 0xff) << 16) case .s33 optSaturate( . .s34 tmp. Bool sat. as shown in the following pseudocode. .b3: return ((tmp & 0xff) << 24) default: return tmp. U32_MAX.b2.add: return tmp + c. .b0: return ((tmp & 0xff) case . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. .Chapter 8.s33 c ) switch ( dsel ) { case .h1: return ((tmp & 0xffff) << 16) case .s33 optMerge( Modifier dsel. c). .

r3. // 32-bit scalar operation.asel}.dtype. dsel ).h0. vabsdiff. a{. tmp = | ta – tb |. tmp.b0. a{.min.max }.u32.asel}.bsel = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. taking into account destination type and merge operations tmp = optSaturate( tmp. . . vabsdiff.h1.dtype. r2. btype. Perform scalar arithmetic operation with optional saturate.s32. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. r2. sat. . r3.asel = . vmax Syntax Integer byte/half-word/word addition / subtraction.s32. . r1.sat. r1.s32 }. { .btype{. . tmp = ta – tb.s32.h0. c. . // 32-bit scalar operation. vmin.sat vmin. and optional secondary arithmetic operation or subword data merge. r3.op2 d.h1. with optional secondary operation vop.b0.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32.btype{. vmin.btype{.h1 }. b{.atype = . c ). tmp = MAX( ta.sat} d. tmp.dsel. . c.b0. with optional data merge vop. .dtype. vmax vadd. d = optSecondaryOp( op2. a{. atype.h0. // extract byte/half-word/word and sign. . isSigned(dtype).u32.vop . r2.s32.add r1.s32.atype. vabsdiff.op2 Description = = = = { vadd. tb ).bsel}. tb = partSelectSignExtend( b. // optional secondary operation d = optMerge( dsel. asel ).btype = { . r3.atype. Semantics // saturate.s32. 2010 . vsub. r2. vsub.sat vsub. tmp = MIN( ta. b{.bsel}. c.s32. vop.sat} d. . b{.s32.dsel .u32. vmax require sm_20 or later. Integer byte/half-word/word absolute value of difference. vmin. Integer byte/half-word/word minimum / maximum.dtype .atype. vmax }.sat}. tb ). // optional merge with c operand 142 January 24.b3. r1.PTX ISA Version 2.b1. vsub. bsel ).add. c.b2.asel}.sat vabsdiff. Video Instructions: vadd.b2. vsub vabsdiff vmin.0.0 Table 105. c ). vadd.s32. vadd. .bsel}.

vshr }. taking into account destination type and merge operations tmp = optSaturate( tmp.sat}{.bsel}. .asel}. a{. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } // saturate.op2 d. vshl. Semantics // extract byte/half-word/word and sign. a{. // default is . bsel ). b{.s32 }. atype. // 32-bit scalar operation.dsel. r1.u32.dtype . .u32{.b0.sat}{. vshl. . Signed shift fills with the sign bit.dtype. a{. vshr: Shift a right by unsigned amount in b with optional saturate.clamp.clamp && tb > 32 ) tb = 32. and optional secondary arithmetic operation or subword data merge.wrap r1. unsigned shift fills with zero.or zero-extend based on source operand type ta = partSelectSignExtend( a. with optional secondary operation vop.atype. with optional data merge vop. tb = partSelectSignExtend( b. b{. if ( mode == . vshr vshl. . r3. . .b1.mode . vop.atype.mode} d. vshr Syntax Integer byte/half-word/word left / right shift.atype. sat.asel = . r3.vop .bsel}.b3.wrap ) tb = tb & 0x1f.0. c ). d = optSecondaryOp( op2.u32{. r2. c.asel}.sat}{. c ). asel ). dsel ).h1 }. // 32-bit scalar operation.dtype.h1.dsel . vshr require sm_20 or later. vshl: Shift a left by unsigned amount in b with optional saturate.u32.dtype.bsel = { .b2.atype = { .u32. c.clamp . and optional secondary arithmetic operation or subword data merge. isSigned(dtype).wrap }.u32.mode} d. // optional secondary operation d = optMerge( dsel. if ( mode == .op2 Description = = = = = { vshl. r2. Left shift fills with zero.max }.Chapter 8.add.u32 vshr. { .u32{. { . 2010 143 . switch ( vop ) { case vshl: tmp = ta << tb. Instruction Set Table 106. .bsel}.u32. case vshr: tmp = ta >> tb.min.s32. . January 24.asel}. . b{.u32. Video Instructions: vshl.h0. . tmp. tmp. .mode}.

(a*b) is negated if and only if exactly one of a or b is negated. final signed (U32 * S32) . {-}c.PTX ISA Version 2. otherwise.shr7. which is used in computing averages. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.dtype = . final signed (S32 * U32) .S32 // intermediate signed. .btype{.bsel = { .. .h1 }. // 32-bit scalar operation vmad.u32. c.sat}{.scale} d.btype. “plus one” mode. and scaling. the intermediate result is signed. a{. . final signed (S32 * S32) + S32 // intermediate signed.po mode. . final signed -(U32 * S32) + S32 // intermediate signed. internally this is represented as negation of the product (a*b). .atype. final signed -(S32 * U32) + S32 // intermediate signed. 2010 . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. .sat}{.atype = . 144 January 24.shr15 }. with optional operand negates.asel = . Depending on the sign of the a and b operands. this result is sign-extended if the final result is signed.U32 // intermediate unsigned. {-}a{. final signed -(S32 * S32) + S32 // intermediate signed.btype = { .h0. Description Calculate (a*b) + c. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.0 Table 107.asel}.S32 // intermediate signed.b1. Input c has the same sign as the intermediate result. .atype. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.scale = { . Source operands may not be negated in . final unsigned -(U32 * U32) + S32 // intermediate signed.b3. final signed The intermediate result is optionally scaled via right-shift. b{. vmad.dtype. {-}b{. The “plus one” mode (.asel}. final signed (U32 * S32) + S32 // intermediate signed. and zero-extended otherwise. .b0. final signed (S32 * S32) . . and the operand negates.po) computes (a*b) + c + 1. .dtype. Although PTX syntax allows separate negation of the a and b operands. That is.bsel}.scale} d. PTX allows negation of either (a*b) or c. The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed (S32 * U32) + S32 // intermediate signed.bsel}.s32 }.b2. final signed (U32 * U32) .S32 // intermediate signed.po{. The source operands support optional negation with some restrictions.

2010 145 . vmad requires sm_20 or later. S32_MIN). } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). if ( .0.negate ^ b. } else if ( c.u32. r2. atype. switch( scale ) { case . case . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. S32_MAX.shr15 r0. r2. January 24.h0.u32.u32. asel ). r1.sat ) { if (signedFinal) result = CLAMP(result.po ) { lsb = 1. lsb = 1. lsb = 1. bsel ).sat vmad. } if ( .negate.s32. signedFinal = isSigned(atype) || isSigned(btype) || (a.negate ) { c = ~c. r1.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate ^ b.u32. r3.s32. tmp = tmp + c128 + lsb. U32_MAX.negate) || c. else result = CLAMP(result. r0. btype.or zero-extend based on source operand type ta = partSelectSignExtend( a. vmad.h0. lsb = 0. U32_MIN).shr7: result = (tmp >> 7) & 0xffffffffffffffff. tb = partSelectSignExtend( b.negate ) { tmp = ~tmp. -r3. Instruction Set Semantics // extract byte/half-word/word and sign.Chapter 8. } else if ( a. tmp[127:0] = ta * tb.

r1.u32.lt.op2 Description = = = = . asel ). r2.u32. r3.asel = . vset. . . with optional data merge vset.u32.btype. r2.op2 d.btype. r3. The intermediate result of the comparison is always unsigned.asel}. tmp. . c ). vset requires sm_20 or later. btype.h1.atype. bsel ). // 32-bit scalar operation.ne. d = optSecondaryOp( op2.min. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c ). .s32. // 32-bit scalar operation.0. 2010 . . . Semantics // extract byte/half-word/word and sign. tb = partSelectSignExtend( b.cmp d.cmp d. 146 January 24. .dsel . with optional secondary arithmetic operation or subword data merge.cmp.btype = { . tb.ge }.bsel}. vset. b{.dsel. a{. tmp.le.h0. . with optional secondary operation vset.asel}.eq. { . Compare input values using specified comparison.PTX ISA Version 2. atype. b{.max }.ne r1. a{.b3.atype. c. . . and therefore the c operand and final result are also unsigned. tmp = compare( ta.b0. .lt vset.btype. // optional secondary operation d = optMerge( dsel.atype .cmp .or zero-extend based on source operand type ta = partSelectSignExtend( a.bsel = { .add.bsel}. . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.h1 }. c.bsel}.s32 }.asel}.gt.atype.u32. . b{. . a{.b1. { . cmp ) ? 1 : 0.b2.0 Table 108. .

with index specified by immediate operand a.Chapter 8. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. pmevent 7. trap Abort execution and generate an interrupt to the host CPU.4. The relationship between events and counters is programmed via API calls from the host. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. January 24. brkpt. Table 111.0. numbered 0 through 15. trap. Supported on all target architectures. Supported on all target architectures. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. there are sixteen performance monitor events. Table 110. Introduced in PTX ISA version 1. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Instruction Set 8. Triggers one of a fixed number of performance monitor events. brkpt. trap. 2010 147 . brkpt Suspends execution Introduced in PTX ISA version 1.0. @p pmevent 1. pmevent a.7. Introduced in PTX ISA version 1. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. brkpt requires sm_11 or later.10.

0 148 January 24.PTX ISA Version 2. 2010 .

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_gt %clock. Special Registers PTX includes a number of predefined. …. %lanemask_lt. 2010 149 . %lanemask_le. %lanemask_ge. %clock64 %pm0.Chapter 9. %pm3 January 24. read-only variables.

%tid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. PTX ISA Notes Introduced in PTX ISA version 1.y.y == %tid.z PTX ISA Notes Introduced in PTX ISA version 1. // zero-extend tid.u32 %r1. . Redefined as . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u16 %rh.z == 1 in 1D CTAs. Supported on all target architectures.0.u32 %tid.u32 %h2.x. %tid.z < %ntid.u32 %ntid. per-thread special register initialized with the thread identifier within the CTA.%tid.z to %r2 Table 113.sreg .%tid.u32 %r0.y * %ntid.u32 type in PTX 2.v4.v4 . The total number of threads in a CTA is (%ntid. read-only.PTX ISA Version 2.y. CTA dimensions are non-zero.x.z). // legacy PTX 1. %ntid. The fourth element is unused and always returns zero. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. . Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.x.x 0 <= %tid. Redefined as . %tid.%tid. or 3D vector to match the CTA shape.z == 0 in 2D CTAs. Every thread in the CTA has a unique %tid. It is guaranteed that: 0 <= %tid. %ntid.x code Target ISA Notes Examples 150 January 24.y.sreg .%h2.z. The number of threads in each dimension are specified by the predefined special register %ntid.z == 0 in 1D CTAs.u32 %tid. 2010 . mov.y == %ntid.x.v4.x code accessing 16-bit component of %tid mov. // compute unified thread id for 2D CTA mov. read-only special register initialized with the number of thread ids in each CTA dimension.sreg . %ntid. 2D.0 Table 112.u16 %rh. the fourth element is unused and always returns zero.x * %ntid. Supported on all target architectures.x to %rh Target ISA Notes Examples // legacy PTX 1.u32 %h1.%ntid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.x. %tid. The %tid special register contains a 1D.z.u32 type in PTX 2. .u32 %ntid.u32. // move tid. // CTA shape vector // CTA dimensions A predefined.0.sreg . // thread id vector // thread id components A predefined. cvt.0. mov. %tid. mov. the %tid value in unused dimensions is 0.u32 %r0.%ntid. mov.v4 .u16 %r2.%h1.y 0 <= %tid.x.z == 1 in 2D CTAs.%tid.x.0. %tid component values range from 0 through %ntid–1 in each CTA dimension.%r0. mad.x < %ntid. %ntid.y < %ntid.z. .

3.u32 %r. PTX ISA Notes Target ISA Notes Examples Table 116. but its value may change during execution.g.sreg . A predefined.0. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.u32 %warpid. Introduced in PTX ISA version 1. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.3. Table 115. Supported on all target architectures. A predefined. read-only special register that returns the thread’s warp identifier. mov.u32 %r. Introduced in PTX ISA version 1. mov. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. . . 2010 151 . January 24. Introduced in PTX ISA version 2. Supported on all target architectures. Special Registers Table 114. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. For this reason. read-only special register that returns the thread’s lane within the warp. The lane identifier ranges from zero to WARP_SZ-1. %warpid. due to rescheduling of threads following preemption. Note that %warpid is volatile and returns the location of a thread at the moment when read. . %nwarpid requires sm_20 or later. read-only special register that returns the maximum number of warp identifiers. e. mov.Chapter 9.u32 %r. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.sreg .u32 %laneid. %laneid.u32 %nwarpid.sreg . A predefined. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. %nwarpid. The warp identifier will be the same for all threads within a single warp.

%ctaid.x < %nctaid. The %ctaid special register contains a 1D. %rh. .x code Target ISA Notes Examples Table 118. Each vector element value is >= 0 and < 65535. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.sreg . // legacy PTX 1.v4 .%nctaid. Supported on all target architectures. depending on the shape and rank of the CTA grid.v4.u32 type in PTX 2. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.x code Target ISA Notes Examples 152 January 24.u32 %nctaid . 2010 .%nctaid.z PTX ISA Notes Introduced in PTX ISA version 1. read-only special register initialized with the number of CTAs in each grid dimension.x. The %nctaid special register contains a 3D grid shape vector. Supported on all target architectures.x. mov.x 0 <= %ctaid.x.z} < 65.u16 %r0.sreg .536 PTX ISA Notes Introduced in PTX ISA version 1.u32 %ctaid.y.u32 %nctaid.v4 .y.%nctaid. or 3D vector.z. %rh.%ctaid.x.%nctaid. with each element having a value of at least 1. mov.0.0.%ctaid. It is guaranteed that: 1 <= %nctaid.u16 %r0.y. read-only special register initialized with the CTA identifier within the CTA grid.0 Table 117. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. 2D.0.sreg .sreg .y < %nctaid. Redefined as .z. .x. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.PTX ISA Version 2. It is guaranteed that: 0 <= %ctaid.u32 mov. // legacy PTX 1.y. .u32 type in PTX 2.z < %nctaid.y 0 <= %ctaid. %ctaid. // CTA id vector // CTA id components A predefined. Redefined as .u32 %ctaid. // Grid shape vector // Grid dimensions A predefined.0.{x.u32 mov. The fourth element is unused and always returns zero. The fourth element is unused and always returns zero.v4.

mov.u32 %r. where each launch starts a grid-of-CTAs. Introduced in PTX ISA version 1.3. Note that %smid is volatile and returns the location of a thread at the moment when read. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. read-only special register initialized with the per-grid temporal grid identifier. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.sreg . %smid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. %nsmid. e. PTX ISA Notes Target ISA Notes Examples Table 121. A predefined. PTX ISA Notes Target ISA Notes Examples January 24.g. Introduced in PTX ISA version 2. mov. During execution. %gridid. but its value may change during execution. Special Registers Table 119. %nsmid requires sm_20 or later. due to rescheduling of threads following preemption.u32 %nsmid. so %nsmid may be larger than the physical number of SMs in the device.sreg . mov. 2010 153 . Supported on all target architectures. The SM identifier numbering is not guaranteed to be contiguous.sreg .u32 %r. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Supported on all target architectures.0.u32 %r. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. read-only special register that returns the maximum number of SM identifiers. // initialized at grid launch A predefined. repeated launches of programs may occur. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. . read-only special register that returns the processor (SM) identifier on which a particular thread is executing.u32 %smid.0. . The SM identifier numbering is not guaranteed to be contiguous. A predefined. .u32 %gridid.Chapter 9. Introduced in PTX ISA version 1. This variable provides the temporal grid launch number for this context. The SM identifier ranges from 0 to %nsmid-1.

Introduced in PTX ISA version 2.0. %lanemask_eq requires sm_20 or later. %lanemask_le requires sm_20 or later.0.u32 %lanemask_le.u32 %lanemask_lt.sreg .u32 %lanemask_eq. .u32 %r. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. mov. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.PTX ISA Version 2.u32 %r. . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. 154 January 24. Introduced in PTX ISA version 2. A predefined. %lanemask_lt. %lanemask_lt requires sm_20 or later. Table 123.u32 %r. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. mov.sreg .0 Table 122. mov.sreg . Introduced in PTX ISA version 2. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. A predefined. %lanemask_eq.0. %lanemask_le. Table 124. 2010 .

Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov.0. Special Registers Table 125.u32 %r. .u32 %lanemask_gt. %lanemask_ge requires sm_20 or later.u32 %r. Introduced in PTX ISA version 2. %lanemask_ge. %lanemask_gt requires sm_20 or later. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. A predefined. January 24. A predefined. %lanemask_gt.sreg .0. Table 126.sreg . read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. mov.u32 %lanemask_ge. .Chapter 9. 2010 155 .

Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u32 %pm0. mov. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Table 129. Special Registers: %pm0.%pm0. read-only 64-bit unsigned cycle counter. %pm2.%clock64. The lower 32-bits of %clock64 are identical to %clock. mov.0.0. . Special registers %pm0. %clock64 requires sm_20 or later. Table 128. …. %pm3 %pm0. %pm1. 156 January 24. %pm1. Supported on all target architectures. %pm2. . %pm2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. 2010 . read-only 32-bit unsigned cycle counter.3.PTX ISA Version 2. Their behavior is currently undefined.u64 r1. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Introduced in PTX ISA version 1. Supported on all target architectures. Introduced in PTX ISA version 2.u64 %clock64. and %pm3 are unsigned 32-bit read-only performance monitor counters. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.sreg . mov.u32 %clock.%clock.u32 r1. .u32 r1. %pm3. %pm1.sreg .sreg . Introduced in PTX ISA version 1.0 Table 127.

.version Syntax Description Semantics PTX version number. Each ptx file must begin with a . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.4 January 24. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. Increments to the major number indicate incompatible changes to PTX. . minor are integers Specifies the PTX language version number.version .version 1. 2010 157 . .version directive.version directives are allowed provided they match the original . Directives 10.version 2. PTX File Directives: .version major. Duplicate . and the target architecture for which the code was generated. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version directive.0.Chapter 10.version .target Table 130.1.minor // major. Supported on all target architectures.0 .

texmode_unified.0. A program with multiple . In general.texmode_independent texture and sampler information is bound together and accessed via a single .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.target directives can be used to change the set of target features allowed during parsing.global. PTX code generated for a given target can be run on later generation devices.red}. . map_f64_to_f32 }. but subsequent .f32.PTX ISA Version 2. Requires map_f64_to_f32 if any .shared. texture and sampler information is referenced with independent . A . Adds {atom. The following table summarizes the features in PTX that vary according to target architecture.target . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Introduced in PTX ISA version 1.f64 instructions used.texmode_unified) .global. Adds {atom. PTX features are checked against the specified target architecture. immediately followed by a . Texturing mode introduced in PTX ISA version 1.f64 to .version directive.target Syntax Architecture and Platform target. texmode_independent.target directive containing a target architecture and optional platform options. Requires map_f64_to_f32 if any . Supported on all target architectures. 158 January 24.samplerref descriptors. PTX File Directives: . including expanded rounding modifiers. sm_12. Texturing mode: (default is . Each PTX file must begin with a . vote instructions. Requires map_f64_to_f32 if any . with only half being used by instructions converted from . Therefore. brkpt instructions.texref and . and an error is generated if an unsupported feature is used.f64 instructions used.texmode_unified . where each generation adds new features and retains all features of previous generations. 2010 . sm_10.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.f64 storage remains as 64-bits.f64 instructions used. Adds double-precision support. sm_13. Description Specifies the set of features in the target architecture for which the current ptx code was generated. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.0 Table 131. sm_11. The texturing mode is specified for an entire module and cannot be changed within the module.texref descriptor. Target sm_20 Description Baseline feature set for sm_20 architecture. Note that .target directive specifies a single target architecture. 64-bit {atom. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.red}. generations of SM architectures follow an “onion layer” model.5. Disallows use of map_f64_to_f32.red}.

Directives Examples .target sm_20.Chapter 10. 2010 159 . texmode_independent January 24.target sm_10 // baseline target architecture .target sm_13 // supports double-precision .

2.param. .param space memory and are listed within an optional parenthesized parameter list. ld. … } . Supported on all target architectures.surfref variables may be passed as parameters. etc.b32 y. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Parameters are passed via .b32 %r1.samplerref. Kernel and Function Directives: . 2010 .g.param { .param . PTX ISA Notes For PTX ISA version 1. %ntid. .param instructions. .func Table 132.entry Syntax Description Kernel entry point and body.0 through 1. .b32 z ) Target ISA Notes Examples [x].entry kernel-name kernel-body Defines a kernel entry point name.reg . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. parameter variables are declared in the kernel parameter list. with optional parameters. At kernel launch.param. .0 through 1. e.b32 %r3.b32 %r2. 160 January 24.entry .entry cta_fft . In addition to normal parameters. opaque . For PTX ISA versions 1. and query instructions and cannot be accessed via ld.param instructions.entry . and . [y]. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.entry kernel-name ( param-list ) kernel-body . the kernel dimensions and properties are established and made available via special registers. The shape and size of the CTA executing the kernel are available in special registers. parameters.4 and later.param . .texref.3. [z]. parameter variables are declared in the kernel body.0 10. ld. These parameters can only be referenced by name within texture and surface load.5 and later.param. Parameters may be referenced by name within the kernel body and loaded into registers using ld. ld.4. store.entry filter ( .b32 %r<99>.b32 x. and body for the kernel function. Semantics Specify the entry point for a kernel program. %nctaid.PTX ISA Version 2.

Directives Table 133.func . … use N.reg .func Syntax Function definition.2 for a description of variadic functions. if any. A .reg . parameters must be in the register state space. . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.x code. and recursion is illegal. PTX 2. Variadic functions are currently unimplemented. 2010 161 .func fname (param-list) function-body .func fname function-body . (val0.param space are accessed using ld. mov. } … call (fooval).param state space. other code. Release Notes For PTX ISA version 1.result.f64 dbl) { . Semantics The PTX syntax hides all details of the underlying calling convention and ABI.b32 rval. dbl. … Description // return value in fooval January 24. which may use a combination of registers and stack locations to pass parameters.0 with target sm_20 supports at most one return value.reg . Parameters in . Parameters must be base types in either the register or parameter state space. The implementation of parameter passing is left to the optimizing translator. Parameter passing is call-by-value.b32 localVar. . implements an ABI with stack. . Parameters in register state space may be referenced directly within instructions in the function body. Variadic functions are represented using ellipsis following the last fixed argument. ret.func definition with no body provides a function prototype.param instructions in the body. and supports recursion.reg .param and st.0 with target sm_20 allows parameters in the .b32 N. there is no stack. val1). The parameter lists define locally-scoped variables in the function body. foo. Supported on all target architectures.func (ret-param) fname (param-list) function-body Defines a function.func (. Kernel and Function Directives: .Chapter 10.b32 rval) foo (.0. PTX ISA 2. including input and return parameters and optional function body. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

maxnreg directive specifies the maximum number of registers to be allocated to a single thread.maxnctapersm (deprecated) . PTX supports the following directives.maxntid .pragma directive is supported for passing information to the PTX backend.0 10. 2010 . The interpretation of . the . A general .entry directive and its body.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).minnctapersm directives may be applied per-entry and must appear between an . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. and .pragma directives may appear at module (file) scope.maxntid and . The directive passes a list of strings to the backend.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. registers) to increase total thread count and provide a greater opportunity to hide memory latency. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. which pass information to the backend optimizing compiler. at entry-scope.3. .maxnreg.PTX ISA Version 2. . to throttle the resource requirements (e.maxnreg . the . The . The directives take precedence over any module-level constraints passed to the optimizing backend. Note that .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. and the strings have no semantics within the PTX virtual machine model. Currently. These can be used.g.pragma The .maxntid directive specifies the maximum number of threads in a thread block (CTA). and the . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. for example.minnctapersm .maxntid. 162 January 24. or as statements within a kernel or device function body.

Performance-Tuning Directives: . the backend may be able to compile to fewer registers. Supported on all target architectures. nz Declare the maximum number of threads in the thread block (CTA).entry bar . ny. Introduced in PTX ISA version 1. The actual number of registers used may be less.3. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. . 2010 163 . Performance-Tuning Directives: . ny . The maximum number of threads is the product of the maximum extent in each dimension. Introduced in PTX ISA version 1.16.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Exceeding any of these limits results in a runtime error or kernel launch failure. or the maximum number of registers may be further constrained by .maxntid nx .3.maxntid and .maxntid 16.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. This maximum is specified by giving the maximum extent of each dimention of the 1D. .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. or 3D CTA.maxntid Syntax Maximum number of threads in thread block (CTA). The compiler guarantees that this limit will not be exceeded.maxntid 256 .maxnreg n Declare the maximum number of registers per thread in a CTA.entry foo . . .maxntid nx.maxntid nx.entry foo .maxntid . 2D.maxnreg . Directives Table 134. Supported on all target architectures.maxctapersm.Chapter 10. for example.

Optimizations based on .maxnctapersm.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. .0 as a replacement for . Optimizations based on .entry foo .minnctapersm generally need .0.maxntid and .entry foo .0 Table 136.PTX ISA Version 2. Deprecated in PTX ISA version 2. 2010 .maxntid to be specified as well. Introduced in PTX ISA version 2. Performance-Tuning Directives: .0.minnctapersm in PTX ISA version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. . Supported on all target architectures.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Performance-Tuning Directives: .minnctapersm .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). However.maxnctapersm (deprecated) .maxntid to be specified as well. For this reason.maxnctapersm has been renamed to . Introduced in PTX ISA version 1.maxntid 256 . additional CTAs may be mapped to a single multiprocessor.maxntid 256 .maxnctapersm generally need . The optimizing backend compiler uses .minnctapersm 4 { … } 164 January 24. .3. Supported on all target architectures.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. if the number of registers used by the backend is sufficiently lower than this bound. .

Pass module-scoped. Supported on all target architectures.pragma . entry-scoped. The interpretation of . . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma “nounroll”. or statement-level directives to the PTX backend compiler. Directives Table 138. { … } January 24.pragma Syntax Description Pass directives to PTX backend compiler. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma directive may occur at module-scope.Chapter 10. Introduced in PTX ISA version 2. 2010 165 .0. or at statementlevel. .pragma list-of-strings . at entry-scope. The .pragma directive strings is implementation-specific and has no impact on PTX semantics.entry foo . Performance-Tuning Directives: .pragma “nounroll”.

byte 0x2b.264-1] . 0x00. 2010 . @progbits .byte byte-list // comma-separated hexadecimal byte values . 0x00.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.x code. 0x00 .0 10. “”.quad int64-list // comma-separated hexadecimal integers in range [0.4byte 0x000006b5. 0x61395a5f.232-1] . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.0.0 and replaces the @@DWARF syntax. replaced by . 0x6150736f. Introduced in PTX ISA version 1. The @@DWARF syntax is deprecated as of PTX version 2..section directive is new in PTX ISA verison 2. 0x00000364.2. 0x63613031.4byte int32-list // comma-separated hexadecimal integers in range [0. 0x00 166 January 24. 0x00.4. 0x00. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .section directive.section .4byte label . 0x00.section .loc The . @@DWARF dwarf-string dwarf-string may have one of the . Table 139. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x736d6172 .file .4byte .byte 0x00.4byte 0x6e69616d.PTX ISA Version 2..0 but is supported for legacy PTX version 1.debug_pubnames. 0x00. Supported on all target architectures.debug_info . 0x5f736f63 . 0x02. Deprecated as of PTX 2.

. replaces @@DWARF syntax. Debugging Directives: .debug_pubnames { . Supported on all target architectures. 0x00.. 0x5f736f63 0x6150736f.section Syntax PTX section definition.section . .debug_info .232-1] . Source file information.b32 . 0x00000364. 0x00. . Source file location. .loc line_number January 24. .file filename Table 142. 0x00.b64 int64-list // comma-separated list of integers in range [0.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .0.0. Debugging Directives: .Chapter 10..b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.section .loc .file .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. Debugging Directives: .255] .264-1] . 0x00. 0x736d6172 0x00 Table 141.b32 0x6e69616d. 2010 167 . . 0x00.b8 byte-list // comma-separated list of integers in range [0. Supported on all target architectures. Directives Table 140.b8 0x00. } 0x02.section section_name { dwarf-lines } dwarf-lines have the following formats: .b8 0x2b. 0x63613031.b32 label .b32 0x000006b5.b32 int32-list // comma-separated list of integers in range [0. 0x00 0x61395a5f. Supported on all target architectures.. 0x00.

visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Linking Directives .0. Supported on all target architectures.visible identifier Declares identifier to be externally visible.extern . Introduced in PTX ISA version 1.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. // foo will be externally visible 168 January 24. Supported on all target architectures.global . . . // foo is defined in another module Table 144. Introduced in PTX ISA version 1.visible Table 143. Linking Directives: .0 10. .PTX ISA Version 2.extern . Linking Directives: .b32 foo.global .extern identifier Declares identifier to be defined externally.visible .extern .6.visible . 2010 .0. .b32 foo.

The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.1 CUDA 2.2 PTX ISA 1.4 PTX ISA 1. CUDA Release CUDA 1.0 January 24. 2010 169 .0 CUDA 1.0.5 PTX ISA 2.3 driver r190 CUDA 3.1 CUDA 2.0 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.1 PTX ISA 1.Chapter 11.2 CUDA 2.0 driver r195 PTX ISA Version PTX ISA 1. The release history is as follows.3 PTX ISA 1.

PTX ISA Version 2. Instructions testp and copysign have been added.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The fma.f32 and mad.f32. The . A single-precision fused multiply-add (fma) instruction has been added.f32 require a rounding modifier for sm_20 targets.0 for sm_20 targets.x code and sm_1x targets.and double-precision div.f32 maps to fma. The mad. rcp. Both fma. 2010 . sub.0 11.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 11. • • • • • 170 January 24.1.1. mad.sat modifiers. These are indicated by the use of a rounding modifier and require sm_20.1. Single. Changes in Version 2. The changes from PTX ISA 1. and sqrt with IEEE 754 compliant rounding have been added. The goal is to achieve IEEE 754 compliance wherever possible.1.1. and mul now support . When code compiled for sm_1x is executed on sm_20 devices.1. New Features 11.ftz modifier may be used to enforce backward compatibility with sm_1x. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.ftz and . while maximizing backward compatibility with legacy PTX 1. The mad.rm and . Floating-Point Extensions This section describes the floating-point changes in PTX 2.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.rp rounding modifiers for sm_20 targets.f32 instruction also supports .f32 for sm_20 targets.rn.f32 requires sm_20. fma. Single-precision add.

%lanemask_{eq. ldu. A “find leading non-sign bit” instruction.or}. Cache operations have been added to instructions ld. Release Notes 11. cvta. for prefetching to specified level of memory hierarchy. A system-level membar instruction. have been added.pred have been added.popc. Bit field extract and insert instructions. vote. 2010 171 .2. st. .1.shared have been extended to handle 64-bit data types for sm_20 targets. popc. ldu.arrive instruction has been added. prefetch. Surface instructions support additional .zero. The . Instruction sust now supports formatted surface stores. has been added.maxnctapersm directive was deprecated and replaced with .3.ge.u32 and bar.clamp modifiers. A “population count” instruction. Instruction cvta for converting global.lt. %clock64. brev.section.b32.gt} have been added. . local.g.sys.red}. New special registers %nsmid. has been added.{and.1. membar.red. Instructions prefetch and prefetchu have also been added. bfind. atom. A new directive. A “count leading zeros” instruction.red}. clz. New instructions A “load uniform” instruction.1. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. and red now support generic addressing. has been added.minnctapersm to better match its behavior and usage. A “bit reversal” instruction. suld. Instructions {atom. Instructions bar. 11.ballot. Instructions {atom. bar now supports optional thread count and register operands. and shared addresses to generic address and vice-versa has been added. has been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. January 24. has been added. The bar instruction has been extended as follows: • • • A bar.le.red. e.1.f32 have been implemented. Other new features Instructions ld. prefetchu.Chapter 11. has been added. A “vote ballot” instruction. isspacep. bfe and bfi. st.clamp and . Video instructions (includes prmt) have been added. and sust.add.

u32. 2010 .ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.f32 type is unimplemented.version is 1.0 11. where . To maintain compatibility with legacy PTX code. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. 172 January 24.3.4 or earlier.1.1.2.ftz for PTX ISA versions 1.{u32. cvt.red}. Formatted surface load is unimplemented.f32} atom.p. In PTX version 1. 11. call suld. or . The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. The underlying.s32. if .ftz (and cvt for . See individual instruction descriptions for details. the correct number is sixteen. {atom. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. stack-based ABI is unimplemented.5 and later.p sust.s32.4 and earlier. .f32. Formatted surface store with .5.{min.target sm_1x.max} are not implemented. Support for variadic functions and alloca are unimplemented.PTX ISA Version 2. Instruction bra. Semantic Changes and Clarifications The errata in cvt. has been fixed. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Note that in order to have the desired effect at statement level. . { … } // do not unroll any loop in this function . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.entry foo (…) .0. Supported only for sm_20 targets.pragma “nounroll”.pragma strings defined by ptxas.pragma “nounroll”. . Ignored for sm_1x targets. including loops preceding the . L1_end: … } // do not unroll this loop January 24. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. Table 145. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. entry-function. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma “nounroll”.pragma Strings This section describes the . 2010 173 . … @p bra L1_end. L1_body: … L1_continue: bra L1_head. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. The “nounroll” pragma is allowed at module. Descriptions of . disables unrolling for all loops in the entry function body.pragma. and statement levels.func bar (…) { … L1_head: . disables unrolling of0 the loop for which the current block is the loop header.Appendix A.

0 174 January 24.PTX ISA Version 2. 2010 .

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