NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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.................................. 47 Chapter 7......1...............................................................................................4. 6..............................3.............................. 6................ 5...............................................1.... Chapter 6.............................5...... 37 Variable Declarations ......1.....5......2............................................................................................................1............... 5...........6... 29 Parameter State Space ...............5.................................................................................................... 6...................... 33 5........................... 5.........4................. 41 Using Addresses..................1...................1... 32 5..................................... 5.............................1.......................4................................................................................ 44 Rounding Modifiers ........................................4...2......... Arrays.............4.................1....................... 30 Shared State Space.............................. 5.......................... and Variables ......................1..... 29 Local State Space ...........4..................................4....................................7............................. Texture..........5....................................... Operand Type Information .... 38 Alignment . 5.... 5....................................................5.........4............. 43 6........................................... 32 Texture State Space (deprecated) ...................... 6.................................... Types....2.....................................6...................... 2010 ... 6............... State Spaces ............................................. State Spaces..................2............ 41 Source Operands........ 6.......... 28 Constant State Space ............................................2..............4.... Summary of Constant Expression Evaluation Rules ................0 4.............................. 6......... 39 Parameterized Variable Names ....................4.................................1...1...4.......................... 5.........2.....3.........................................4....2.. 5...................................... Instruction Operands......................................... 5............................. 5.............3............................................. 41 6.....................8.................................... 43 Vectors as Operands .............................................................................. Operand Costs ............................... Types ..............4.. 41 Destination Operands ..................................................................... 29 Global State Space ............................................ 27 5................... 37 Vectors ................. 49 ii January 24.6.......... Function declarations and definitions ........................ 5.......1.............................................................2......................................... 38 Initializers ...................................... Abstracting the ABI ...................................1................. 39 5.................. Sampler........5.............................. 34 Variables .......... 5.............6...............................................................................................................1........... 27 Register State Space ................................ 44 Scalar Conversions ...... 42 Addresses as Operands ...................................... 49 7.......1............. 5.....2.......1........... 33 Restricted Use of Sub-Word Sizes ...........4................................... 6. Type Conversion.................... and Vectors ................................................................................3............................... 25 Chapter 5........................................PTX ISA Version 2................................................ 37 Array Declarations ......... 43 Labels and Function Names as Operands ...... 46 6...... 33 Fundamental Types .......... 6......... and Surface Types ...... 28 Special Register State Space .......4............................................. 5......................................................3................................................................................................................................. 5.................... 42 Arrays as Operands .........................................................

.........3........... 108 Texture and Surface Instructions ...................1..0 ................... 149 Chapter 10......................................... PTX Version and Target Directives .................................. 8...4.................7... 10................................. 62 Machine-Specific Semantics of 16-bit Code .....................................4................. 157 10.......4........................................................................................... Directives ..................2........... 157 Specifying Kernel Entry Points and Functions ................................... 55 Predicated Execution ...7.................... 8.........................................6................................ 8...........1................................. 55 8.......7............................ 170 New Features .............................. Type Information for Instructions and Operands ........................1........................... 132 Video Instructions ..............................................1................... 58 8....................5...... 11........... 8.......... 7............ 8........................1.................................. 53 Alloca .......... 63 Integer Arithmetic Instructions .................................5.......7..............4............................ 60 8....... 8................................................................................................. Instructions ..........................................1................... 8........... 8.................................... 160 Performance-Tuning Directives ............................................................................1............................ 8......................................7.......................................6.. 54 Chapter 8..........................................................................1................................1........................................................... 57 Manipulating Predicates ....7...........................3................7.............6. 55 PTX Instructions ................ Changes in Version 2.........................7............................ 169 11................ 8.............2.............. Instruction Set ...................................................2...................................................... 8............................................................ 8..................................................................1............................................................... 100 Logic and Shift Instructions .................... 62 8......................... 140 Miscellaneous Instructions.............................7.........7...... Release Notes ........... 52 Variadic functions ........9............................................ 166 Linking Directives .........................................2.........................................................................................................................................2...3............1........................................... 63 Floating-Point Instructions .1.......... 11................................................... 10.... 168 Chapter 11...6........... 11..............................3................... 2010 iii .7......... Changes from PTX 1.. 10...........................................................3....... 8...................... 170 Semantic Changes and Clarifications ....................... 172 January 24. 8...................................................3............... 8. Special Registers .. 172 Unimplemented Features Remaining ......................... Chapter 9..................................................x ........................2........7................................................ 8........... 7.... Divergence of Threads in Control Constructs ...... 10............................................. Format and Semantics of Instruction Descriptions .......3. 59 Operand Size Exceeding Instruction-Type Size ............ 104 Data Movement and Conversion Instructions ........................ 129 Parallel Synchronization and Communication Instructions .........................8................. 81 Comparison and Selection Instructions .......................... 122 Control Flow Instructions .....10................. 62 Semantics .......... 147 8.....................7....................1.................................................................... 162 Debugging Directives ......... 56 Comparisons ........

......pragma Strings. 2010 ........ Descriptions of ..................0 Appendix A......PTX ISA Version 2........................... 173 iv January 24..

...................................... 33 Opaque Type Fields in Unified Texture Mode . 58 Floating-Point Comparison Operators Testing for NaN ............................... Table 19........... Table 8..................................................................... 67 Integer Arithmetic Instructions: mad ................................... 64 Integer Arithmetic Instructions: sub ............................. 47 Operators for Signed Integer.......................... Table 11...................................................................... 57 Floating-Point Comparison Operators .... Table 32............................................................. 19 Predefined Identifiers ............ 18 Reserved Instruction Keywords ............................... Table 3.................... Table 24..........List of Tables Table 1....................................... 65 Integer Arithmetic Instructions: addc ... Table 12........ 61 Integer Arithmetic Instructions: add ............................. 57 Floating-Point Comparison Operators Accepting NaN ............................... Table 20.... Table 22.. Table 26............................... 20 Operator Precedence .......................................................................................... 64 Integer Arithmetic Instructions: add.............................................. Table 14............ 66 Integer Arithmetic Instructions: mul ....................................... 59 Relaxed Type-checking Rules for Source Operands .................................... Table 23.. 60 Relaxed Type-checking Rules for Destination Operands................................................. Table 21....... Table 6.. Table 18.... Table 25............................ Table 9........................................................................cc ..... PTX Directives ............. Table 5....... 28 Fundamental Type Specifiers ....... 27 Properties of State Spaces .......................... Table 2.......................................................................................................................................... 65 Integer Arithmetic Instructions: sub.................................................... Table 7............................... 58 Type Checking Rules ........................cc ....... Table 16................................................... Table 28........................... 23 Constant Expression Evaluation Rules ................................................................................... Table 10.............................................. 71 January 24................................................................ 46 Cost Estimates for Accessing State-Spaces ............................ 46 Integer Rounding Modifiers ....................................................................................... 35 Opaque Type Fields in Independent Texture Mode ............................ 25 State Spaces .. Unsigned Integer.................................................................................................... Table 31...... 2010 v ............................... 68 Integer Arithmetic Instructions: mul24 ............................................................................................... 45 Floating-Point Rounding Modifiers .......... Table 4........................................... Table 27............................. 35 Convert Instruction Precision and Format .................... Table 29..................................... 66 Integer Arithmetic Instructions: subc ................................................................................................. Table 30................................................ Table 15....... Table 13........... and Bit-Size Types ........... Table 17.............................................. 70 Integer Arithmetic Instructions: sad .. 69 Integer Arithmetic Instructions: mad24 .............................

...................................................................... 74 Integer Arithmetic Instructions: bfind .................................... 103 vi January 24................ Table 42...... 90 Floating-Point Instructions: abs .................. Table 63.................................................................. Table 54..........0 Table 33..................................................................................... 101 Comparison and Selection Instructions: setp ............ 83 Floating-Point Instructions: add ................................ Table 58...................................... Table 43............................................... 78 Integer Arithmetic Instructions: prmt ................................ 84 Floating-Point Instructions: sub ........................................... Table 67.................................................................... Table 52........................................ 2010 ....... 91 Floating-Point Instructions: neg ....................................... Table 55... Table 38................. 96 Floating-Point Instructions: cos ........ 72 Integer Arithmetic Instructions: neg ....... 76 Integer Arithmetic Instructions: bfe ... 94 Floating-Point Instructions: rsqrt ............................... Table 45................................................................................ Table 47......................................................................................................... Table 69....................... Table 53........................... Table 59................. 87 Floating-Point Instructions: mad ... 74 Integer Arithmetic Instructions: clz . 71 Integer Arithmetic Instructions: abs ... Table 51........................... 85 Floating-Point Instructions: mul .............................................. Table 50............................................. 75 Integer Arithmetic Instructions: brev ...................................................................................................... Table 41............................. Table 60....................................................................................................... 73 Integer Arithmetic Instructions: popc .............. 98 Floating-Point Instructions: ex2 ......................... Table 64............................................................................. Integer Arithmetic Instructions: div ...... Table 49....................... Table 34................... Table 35. Table 48............. 86 Floating-Point Instructions: fma ......................................................................................................................... 77 Integer Arithmetic Instructions: bfi ................. Table 46..... Table 68................................................................................................................................ 97 Floating-Point Instructions: lg2 .............. 95 Floating-Point Instructions: sin ...................................................................... Table 57. Table 39................................................................................... Table 40.......................................................... Table 37.......................... 92 Floating-Point Instructions: rcp ......................................................... 71 Integer Arithmetic Instructions: rem .................................................... Table 66......................................... 82 Floating-Point Instructions: testp .......... 72 Integer Arithmetic Instructions: min ............................................................................................ 88 Floating-Point Instructions: div . Table 65.......................................................................................................................................... Table 62............................................................................................................... 103 Comparison and Selection Instructions: slct ............................................. 73 Integer Arithmetic Instructions: max .... Table 44........ 79 Summary of Floating-Point Instructions ............. 93 Floating-Point Instructions: sqrt ................ 99 Comparison and Selection Instructions: set .PTX ISA Version 2............... Table 61..................................................... 102 Comparison and Selection Instructions: selp ............ 83 Floating-Point Instructions: copysign ... 91 Floating-Point Instructions: min ..... Table 36........................... 92 Floating-Point Instructions: max .......................................... Table 56....................

........................................................................................ Table 97........ Table 91.............................................................. Table 90...... Table 84.......... 2010 vii ............................ 106 Logic and Shift Instructions: not ............................................................................................. Table 93........... 107 Logic and Shift Instructions: shr ................................................... 123 Texture and Surface Instructions: txq ............................................... Table 105.. 142 Video Instructions: vshl... Table 89........................................................................................................ Table 77................. 124 Texture and Surface Instructions: suld .............. Table 82........................................................................... Table 75................................................... 128 Control Flow Instructions: { } ........................... 106 Logic and Shift Instructions: shl ......................... 120 Texture and Surface Instructions: tex .. Table 80................. 127 Texture and Surface Instructions: suq .................... vsub................... Table 87... 118 Data Movement and Conversion Instructions: isspacep ................ Table 92.... 112 Data Movement and Conversion Instructions: ld ..................................... 129 Control Flow Instructions: bra .... Table 76............................................ Table 99.................................................................................. 115 Data Movement and Conversion Instructions: st ............................................... Table 88........... vabsdiff.............. Table 96................................................................. Table 83.. 107 Cache Operators for Memory Load Instructions .............Table 70...... vmin......................................................................... 109 Cache Operators for Memory Store Instructions ............................................................................. 111 Data Movement and Conversion Instructions: mov .................................................... Table 71............................................. Table 85.. Table 100.......... prefetchu ........ Table 103. 139 Video Instructions: vadd..... 134 Parallel Synchronization and Communication Instructions: atom ....... vmax .............. Table 73............. Table 81............................................................ Table 106.................... 131 Parallel Synchronization and Communication Instructions: bar ................................. 119 Data Movement and Conversion Instructions: cvta ................. Table 78. Table 101. 106 Logic and Shift Instructions: cnot ......................................................................................................... 131 Control Flow Instructions: exit ....................................... Table 72.......... 110 Data Movement and Conversion Instructions: mov ........ 105 Logic and Shift Instructions: or ................ 113 Data Movement and Conversion Instructions: ldu ........ Table 102............. Table 95..................... 133 Parallel Synchronization and Communication Instructions: membar ..................... 130 Control Flow Instructions: call ................. Table 74...................................... 135 Parallel Synchronization and Communication Instructions: red ......... 129 Control Flow Instructions: @ ............. Logic and Shift Instructions: and ............... 105 Logic and Shift Instructions: xor ................. Table 104.................. 130 Control Flow Instructions: ret ...... Table 86.......... Table 79................................... Table 94............................................................. 126 Texture and Surface Instructions: sured................................................................................ Table 98. 119 Data Movement and Conversion Instructions: cvt ....... 125 Texture and Surface Instructions: sust ............... vshr ................... 137 Parallel Synchronization and Communication Instructions: vote ............................ 143 January 24...................... 116 Data Movement and Conversion Instructions: prefetch..........

................ Table 121....................................... 153 Special Registers: %nsmid ..................................... 165 Debugging Directives: @@DWARF ..................................................................................... 166 Debugging Directives: ................................................................... Table 114. 150 Special Registers: %laneid ...................... 156 Special Registers: %pm0.................. Table 113................................................................ 2010 ...... 154 Special Registers: %lanemask_lt ................................................................... Table 122.............................. Table 128............... Table 141....... 164 Performance-Tuning Directives: ....................... 155 Special Registers: %clock ................................................................. 144 Video Instructions: vset............................................. Table 127...... Table 140................................................................................ Table 111................ Table 133. Table 143.................... Table 132...................... Table 109..................version......extern............... 154 Special Registers: %lanemask_ge ............................pragma .......... Table 137............................................ Table 108...maxnctapersm (deprecated) ...................................................................................................... Table 110........... 160 Kernel and Function Directives: .................. 161 Performance-Tuning Directives: ........................................................................................................................... 157 PTX File Directives: . Table 118................target ..................................................... Table 119............. Table 129........................................ 151 Special Registers: %ctaid ............................................. %pm2...... Table 134.... 151 Special Registers: %warpid ......maxntid .entry............................................................. 151 Special Registers: %nwarpid . 146 Miscellaneous Instructions: trap ............ 167 Debugging Directives: ............. Table 136........................................................................... Table 135...... 147 Miscellaneous Instructions: brkpt ... 156 PTX File Directives: ........................................................... 164 Performance-Tuning Directives: ..................................................................................... Table 139............................................ 147 Special Registers: %tid ..................... 163 Performance-Tuning Directives: ....... 156 Special Registers: %clock64 ...................................maxnreg ............................................................ 168 viii January 24........... Video Instructions: vmad ..............0 Table 107........................ Table 126...........section ............................................................................................................................................................................................. 150 Special Registers: %ntid .............. 153 Special Registers: %gridid ........ 155 Special Registers: %lanemask_gt ................................................file ........... 167 Debugging Directives: ................... 158 Kernel and Function Directives: ........... Table 138..............func ....................loc .... Table 120............... 152 Special Registers: %nctaid ....... Table 142....................................................................................... Table 123.............. 153 Special Registers: %lanemask_eq .......................... Table 131......................minnctapersm ... 167 Linking Directives: .................................... 163 Performance-Tuning Directives: .......................................... %pm3 ......................................................... Table 124............. 154 Special Registers: %lanemask_le ................................... 152 Special Registers: %smid . Table 117...... Table 130.......................................... 147 Miscellaneous Instructions: pmevent......................................... %pm1................. Table 115.PTX ISA Version 2............................... Table 125.... Table 116............................................ Table 112.

.Table 144............................................... Table 145.................................... 2010 ix ........ 173 January 24..................................... Linking Directives: ............visible.......................... 168 Pragma Strings: “nounroll” ....

PTX ISA Version 2. 2010 .0 x January 24.

the programmable GPU has evolved into a highly parallel. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. high-definition 3D graphics.Chapter 1. multithreaded. video encoding and decoding. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. from general signal processing or physics simulation to computational finance or computational biology.2. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). image and media processing applications such as post-processing of rendered images. PTX exposes the GPU as a data-parallel computing device. 1. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. In fact. stereo vision. 2010 1 . Data-parallel processing maps data elements to parallel processing threads. the memory access latency can be hidden with calculations instead of big data caches. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions.1. there is a lower requirement for sophisticated flow control. which are optimized for and translated to native target-architecture instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth. 1. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Similarly. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. PTX defines a virtual machine and ISA for general purpose parallel thread execution. PTX programs are translated at install time to the target hardware instruction set. and because it is executed on many data elements and has high arithmetic intensity. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Because the same program is executed for each data element. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. image scaling. and pattern recognition can map image blocks and pixels to parallel processing threads. Introduction This document describes PTX. January 24.

Instructions marked with .f32 instruction also supports . addition of generic addressing to facilitate the use of general-purpose pointers.x features are supported on the new sm_20 target.f32 for sm_20 targets. Legacy PTX 1. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.1. and all PTX 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.0 is a superset of PTX 1. PTX 2. The mad. Facilitate hand-coding of libraries. which map PTX to specific target machines.x code will continue to run on sm_1x targets as well. Single-precision add.f32 and mad.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.PTX ISA Version 2. and the introduction of many new instructions. PTX ISA Version 2. sub.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Both fma. memory. atomic. Most of the new features require a sm_20 target.rn. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. surface. The main areas of change in PTX 2. and video instructions. Provide a machine-independent ISA for C/C++ and other compilers to target.0 are improved support for IEEE 754 floating-point operations.rp rounding modifiers for sm_20 targets.ftz and .0 is in improved support for the IEEE 754 floating-point standard. 1.f32 requires sm_20. Achieve performance in compiled applications comparable to native GPU performance. including integer. 1.f32 maps to fma. The mad. fma.sat modifiers. Provide a common source-level ISA for optimizing code generators and translators. performance kernels.0 PTX ISA Version 2. and mul now support .rm and . 2010 . When code compiled for sm_1x is executed on sm_20 devices.x.f32 require a rounding modifier for sm_20 targets. The fma. • • • 2 January 24.ftz) modifier may be used to enforce backward compatibility with sm_1x. Improved Floating-Point Support A main area of change in PTX 2.f32. reduction. barrier. Provide a code distribution ISA for application and middleware developers.3. The changes from PTX ISA 1. A single-precision fused multiply-add (fma) instruction has been added. and architecture tests.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.3.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. A “flush-to-zero” (. mad.

i. prefetchu.3.3.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Support for an Application Binary Interface Rather than expose details of a particular calling convention. stack layout. rcp. and vice versa.g.clamp and .4. These are indicated by the use of a rounding modifier and require sm_20. an address that is the same across all threads in a warp.Chapter 1. cvta. 1. local. Cache operations have been added to instructions ld. .2. Generic Addressing Another major change is the addition of generic addressing.0 closer to full compliance with the IEEE 754 standard. atom. and shared state spaces.. st. so recursion is not yet supported. 1. January 24. and directives are introduced in PTX 2. prefetch. local. special registers. A new cvta instruction has been added to convert global. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. New Instructions The following new instructions. 1. these changes bring PTX 2. isspacep. and sqrt with IEEE 754 compliant rounding have been added. for prefetching to specified level of memory hierarchy. allowing memory instructions to access these spaces without needing to specify the state space. NOTE: The current version of PTX does not implement the underlying. instructions ld.zero. In PTX 2. Surface instructions support additional clamp modifiers. Generic addressing unifies the global. Introduction • Single. e.0. and red now support generic addressing.3. and shared addresses to generic address and vice-versa has been added. ldu. • Taken as a whole. 2010 3 . Instructions prefetch and prefetchu have been added. and shared addresses to generic addresses. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Instructions testp and copysign have been added. PTX 2.and double-precision div. local.3. st. and Application Binary Interface (ABI).e. Surface Instructions • • Instruction sust now supports formatted surface stores. suld. stack-based ABI. and sust. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. Instruction cvta for converting global.0.

. %lanemask_{eq. has been added. bfi bit field extract and insert popc clz Atomic.f32 have been added.red. Reduction.u32 and bar. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Instructions {atom.red.ge. A “vote ballot” instruction.sys.le.b32. vote.arrive instruction has been added. Instructions bar.shared have been extended to handle 64-bit data types for sm_20 targets.lt. has been added.popc.PTX ISA Version 2.red}.pred have been added.ballot.red}.gt} have been added. A new directive. A bar. Barrier Instructions • • A system-level membar instruction. bar now supports an optional thread count and register operands.or}. membar.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. 2010 .section. 4 January 24. %clock64. New special registers %nsmid. Other Extensions • • • Video instructions (includes prmt) have been added.add. and Vote Instructions • • • New atomic and reduction instructions {atom.{and.

Chapter 9 lists special registers. Chapter 7 describes the function and call syntax. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and variable declarations.Chapter 1. and PTX support for abstracting the Application Binary Interface (ABI). 2010 5 . types. Chapter 4 describes the basic syntax of the PTX language. calling convention. Introduction 1. Chapter 10 lists the assembly directives supported in PTX.4. January 24. Chapter 6 describes instruction operands. Chapter 11 provides release notes for PTX Version 2. Chapter 8 describes the instruction set. Chapter 3 gives an overview of the PTX virtual machine model.0. Chapter 5 describes state spaces.

0 6 January 24.PTX ISA Version 2. 2010 .

z). The thread identifier is a three-element vector tid. data-parallel. Each CTA thread uses its thread identifier to determine its assigned role. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. or 3D shape specified by a three-element vector ntid (with elements ntid. A cooperative thread array. 2. Programming Model 2.z) that specifies the thread’s position within a 1D. Each CTA has a 1D. or host: In other words.Chapter 2. Threads within a CTA can communicate with each other.1. ntid. More precisely. but independently on different data. Programs use a data parallel decomposition to partition inputs. 2. Cooperative thread arrays (CTAs) implement CUDA thread blocks. Each thread has a unique thread identifier within the CTA. January 24. It operates as a coprocessor to the main CPU. or CTA. compute addresses. The vector ntid specifies the number of threads in each CTA dimension. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. and tid. can be isolated into a kernel function that is executed on the GPU as many different threads. compute-intensive portions of applications running on the host are off-loaded onto the device.2. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. a portion of an application that is executed many times. tid. and select work to perform.2. or 3D CTA. work.y. (with elements tid.x. 2D. assign specific input and output positions. 2D.y. To that effect. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. and ntid. and results across the threads of the CTA. is an array of threads that execute a kernel concurrently or in parallel. To coordinate the communication of the threads within the CTA. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.x.1. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2010 7 .

2.0 Threads within a CTA execute in SIMT (single-instruction. A warp is a maximal subset of threads from a single CTA. 2. Multiple CTAs may execute concurrently and in parallel. The host issues a succession of kernel invocations to the device. 8 January 24. so PTX includes a run-time immediate constant. which may be used in any instruction where an immediate operand is allowed. such that the threads execute the same instructions at the same time.PTX ISA Version 2. Each grid also has a unique temporal grid identifier (gridid). Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Each grid of CTAs has a 1D. Threads within a warp are sequentially numbered. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). The warp size is a machine-dependent constant. Typically. a warp has 32 threads. multiple-thread) fashion in groups called warps. depending on the platform. WARP_SZ. %ctaid. read-only special registers %tid. Threads may read and use these values through predefined. This comes at the expense of reduced thread communication and synchronization. %ntid. Some applications may be able to maximize performance with knowledge of the warp size. or sequentially. so that the total number of threads that can be launched in a single kernel invocation is very large. 2D . 2010 . because threads in different CTAs cannot communicate and synchronize with each other.2. However. CTAs that execute the same kernel can be batched together into a grid of CTAs. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. or 3D shape specified by the parameter nctaid. %nctaid. and %gridid.

0) CTA (1. A grid is a set of CTAs that execute independently. 0) CTA (0. 1) Thread (3. 0) Thread (2. 2010 9 . 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) CTA (2. Thread Batching January 24. 2) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 1) Thread (2. 1) Thread (4. 1) CTA (1. 2) Thread (1. 1) Thread (0. Figure 1. 0) Thread (4. 0) Thread (1. 2) Thread (4. 1) Thread (1. 0) Thread (0. 0) Thread (3. 1) Thread (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (2. 1) CTA (2.Chapter 2.

all threads have access to the same global memory. and texture memory spaces are persistent across kernel launches by the same application. constant. respectively. 2010 . constant. referred to as host memory and device memory.PTX ISA Version 2. as well as data filtering. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. for more efficient transfer. or. 10 January 24. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Both the host and the device maintain their own local memory. Texture memory also offers different addressing modes. The device memory may be mapped and read or written by the host. and texture memory spaces are optimized for different memory usages. Finally. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. for some specific data formats. The global. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Each thread has a private local memory.0 2.3.

1) Block (2.Chapter 2. Memory Hierarchy January 24. 0) Block (0. 2) Block (1. 0) Block (2. 2) Figure 2. 0) Block (0. 1) Grid 1 Global memory Block (0. 0) Block (1. 1) Block (1. 2010 11 . 1) Block (1. 0) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0.

0 12 January 24.PTX ISA Version 2. 2010 .

A multiprocessor consists of multiple Scalar Processor (SP) cores. The multiprocessor creates. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. Branch divergence occurs only within a warp. It implements a single-instruction barrier synchronization. The way a block is split into warps is always the same. manages. The multiprocessor maps each thread to one scalar processor core. When a host program invokes a kernel grid. increasing thread IDs with the first warp containing thread 0. the warp serially executes each branch path taken. disabling threads that are not on that path. To manage hundreds of threads running several different programs. manages. so full efficiency is realized when all threads of a warp agree on their execution path. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and on-chip shared memory. At every instruction issue time. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. January 24. schedules. If threads of a warp diverge via a data-dependent conditional branch.Chapter 3. a cell in a grid-based computation).) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. each warp contains threads of consecutive. a voxel in a volume. allowing. and each scalar thread executes independently with its own instruction address and register state. The threads of a thread block execute concurrently on one multiprocessor. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. new blocks are launched on the vacated multiprocessors. the first parallel thread technology. a multithreaded instruction unit. and executes threads in groups of parallel threads called warps.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). (This term originates from weaving. When a multiprocessor is given one or more thread blocks to execute. the multiprocessor employs a new architecture we call SIMT (single-instruction. 2010 13 . the threads converge back to the same execution path. A warp executes one common instruction at a time. Parallel Thread Execution Machine Model 3. and executes concurrent threads in hardware with zero scheduling overhead. for example. As thread blocks terminate. different warps execute independently regardless of whether they are executing common or disjointed code paths. and when all paths complete. The multiprocessor SIMT unit creates. it splits them into warps that get scheduled by the SIMT unit. multiple-thread).

A multiprocessor can execute as many as eight thread blocks concurrently. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. modifies. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. on the other hand. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. the kernel will fail to launch. which is a read-only region of device memory. In contrast with SIMD vector machines. In practice.PTX ISA Version 2. the number of serialized writes that occur to that location and the order in which they occur is undefined. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. whereas SIMT instructions specify the execution and branching behavior of a single thread. • The local and global memory spaces are read-write regions of device memory and are not cached. 2010 . each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. write to that location occurs and they are all serialized. as well as data-parallel code for coordinated threads. but one of the writes is guaranteed to succeed. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. Vector architectures. however. the programmer can essentially ignore the SIMT behavior. which is a read-only region of device memory. and writes to the same location in global memory for more than one of the threads of the warp. SIMT enables programmers to write thread-level parallel code for independent. scalar threads. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. As illustrated by Figure 3. For the purposes of correctness. modify. If an atomic instruction executed by a warp reads.0 SIMT architecture is akin to SIMD (Single Instruction. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each read. require the software to coalesce loads into vectors and manage divergence manually. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. but the order in which they occur is undefined. A key difference is that SIMD vector organizations expose the SIMD width to the software. If there are not enough registers or shared memory available per multiprocessor to process at least one block. 14 January 24. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge.

Hardware Model January 24. Figure 3.Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 .

0 16 January 24.PTX ISA Version 2. 2010 .

The following are common preprocessor directives: #include. Syntax PTX programs are a collection of text source files. January 24. #ifdef. #endif. The C preprocessor cpp may be used to process PTX source files. Lines beginning with # are preprocessor directives.version directive specifying the PTX language version.Chapter 4. #define. #if. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Each PTX file must begin with a . The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 2010 17 . See Section 9 for a more information on these directives. #line.2. All whitespace characters are equivalent. Comments Comments in PTX follow C/C++ syntax. 4. using non-nested /* and */ for comments that may span multiple lines.1. PTX is case sensitive and uses lowercase for keywords. Source Format Source files are ASCII text. followed by a . whitespace is ignored except for its use in separating tokens in the language. Pseudo-operations specify symbol and addressing management. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. 4. #else. Lines are separated by the newline character (‘\n’). Comments in PTX are treated as whitespace. and using // to begin a comment that extends to the end of the current line.target directive specifying the target architecture assumed.

All instruction keywords are reserved tokens in PTX. The destination operand is first. address expressions. .b32 r1.f32 r2.reg .b32 r1. and is written as @p. r1.file PTX Directives . Examples: .0 4. r2.minnctapersm .const .maxnctapersm .global. shl. written as @!p.func . r2. mov. 2010 .target .local . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. The guard predicate may be optionally negated. array[r1]. where p is a predicate register.entry .1. 18 January 24. %tid.reg .PTX ISA Version 2. The guard predicate follows the optional label and precedes the opcode. Table 1. so no conflict is possible with user-defined identifiers.x. Instructions have an optional guard predicate which controls conditional execution.3. or label names.global start: .5. followed by source operands. r2.global . constant expressions. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.extern . and terminated with a semicolon. .maxnreg .2. ld.f32 array[N].maxntid .3. Statements A PTX statement is either a directive or an instruction.param .loc . 2.version . 0.3. Directive Statements Directive keywords begin with a dot.tex .sreg .visible 4.shared .align .b32 add. Statements begin with an optional label and end with a semicolon.section .pragma .b32 r1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. Operands may be register variables. Instruction keywords are listed in Table 2.

Chapter 4. Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .

PTX allows the percentage sign as the first character of an identifier. Table 3. %pm3 WARP_SZ 20 January 24. Many high-level languages such as C and C++ follow similar rules for identifier names. digits. underscore. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. PTX predefines one constant and a small number of special registers that begin with the percentage sign. …. dollar.0 4. or percentage character followed by one or more letters. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. The percentage sign can be used to avoid name conflicts. or they start with an underscore. or dollar characters. listed in Table 3.4. e.g.PTX ISA Version 2. except that the percentage sign is not allowed. 2010 . %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. digits. between user-defined variable names and compiler-generated names. underscore.

Unlike C and C++. the sm_1x and sm_20 targets have a WARP_SZ value of 32. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. The syntax follows that of C. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. where the behavior of the operation depends on the operand types.1. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. the constant begins with 0f or 0F followed by 8 hex digits. To specify IEEE 754 doubleprecision floating point values. zero values are FALSE and non-zero values are TRUE. each integer constant is converted to the appropriate size based on the data or instruction type at its use. literals are always represented in 64-bit double-precision format. Syntax 4. 2010 21 .u64. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Floating-point literals may be written with an optional decimal point and an optional signed exponent. 4. and bit-size types. Integer literals may be written in decimal. Type checking rules remain the same for integer. every integer constant has type . Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. 0[fF]{hexdigit}{8} // single-precision floating point January 24.u64). Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. i.Chapter 4. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. Constants PTX supports integer and floating-point constants and constant expressions. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. in which case the literal is unsigned (. When used in an instruction or data initialization.s64 or the unsigned suffix is specified. there is no suffix letter to specify size.. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.s64) unless the value cannot be fully represented in . or binary notation.s64 or . the constant begins with 0d or 0D followed by 16 hex digits. hexadecimal. These constants may be used in data initialization and as operands to instructions. 4. octal. floating-point. i.5.5.5.e.e. To specify IEEE 754 single-precision floating point values. integer constants are allowed and are interpreted as in C.2. For predicate-type data and instructions.. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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2nd is .f64 use usual conversions .f64 same as source .s64 .u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .s64 .u64.u64 same as 1st operand .f64 use usual conversions .u64 .u64 .Chapter 4.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .u64 1st unchanged.f64 integer integer integer integer integer int ?.s64 .f64 integer .s64 . Syntax 4.f64 integer . Table 5.s64 .s64.5.f64 converted type .s64) + .s64 .s64 .6.u64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 converted type constant literal + ! ~ Cast Binary (.u64) (. .f64 use usual conversions .f64 : . 2010 25 .u64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. or .

PTX ISA Version 2.0 26 January 24. 2010 .

param . Global texture memory (deprecated).const . platform-specific. Table 6. defined per-grid.tex January 24. State Spaces A state space is a storage area with particular characteristics. access rights. 5. Types. defined per-thread. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.sreg .shared . State Spaces. Kernel parameters. Special registers. or Function or local parameters. and properties of state spaces are shown in Table 5. Addressable memory shared between threads in 1 CTA. . Read-only. the kinds of resources will be common across platforms. and these resources are abstracted in PTX through state spaces and data types.Chapter 5. The list of state spaces is shown in Table 4. and level of sharing between threads. and Variables While the specific resources available in a given target GPU will vary. shared by all threads. Local memory.reg .local . access speed. fast. All variables reside in some state space. addressability.global . Global memory. The characteristics of a state space include its size.1. Name State Spaces Description Registers. private to each thread. pre-defined. read-only memory. 2010 27 . Shared.

Special Register State Space The special register (. causing changes in performance. clock counters. 2010 .local .1. Device function input parameters may have their address taken via mov. and cvt instructions. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.PTX ISA Version 2. scalar registers have a width of 8-. The number of registers is limited.global .local state space. floating point. Registers may be typed (signed integer. 2 Accessible via ld. or 64-bits. Registers differ from the other state spaces in that they are not fully addressable.sreg . 16-. CTA.param and st. unsigned integer. Registers may have alignment boundaries required by multi-word loads and stores.param (used in functions) .1. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 28 January 24.shared . st.param (as input to kernel) .e. or 128-bits. and thread parameters. 1 Accessible only via the ld. 5. i.. or as elements of vector tuples.reg state space) are fast storage locations. predicate) or untyped. For each architecture. All special registers are predefined. and vector registers have a width of 16-.reg . the parameter is then located on the stack frame and its address is in the . aside from predicate registers which are 1-bit. 3 Accessible only via the tex instruction.2. and will vary from platform to platform. Register size is restricted. platform-specific registers. register variables will be spilled to memory.param instruction. 32-.tex Restricted Yes No3 5.0 Table 7.const .1.param instructions. it is not possible to refer to the address of a register. 32-. and performance monitoring registers. The most common use of 8-bit registers is with ld.sreg) state space holds predefined. Address may be taken via mov instruction. Register State Space Registers (. such as grid. 64-. When the limit is exceeded. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .

Multiple incomplete array variables declared in the same bank become aliases. the declaration . whereas local memory variables declared January 24. the stack is in local memory. For any thread in a context. 5. The size is limited. By convention.global) state space is memory that is accessible by all threads in a context.b32 %r1.1. Constant State Space The constant (. and atom. In implementations that support a stack. the bank number must be provided in the state space of the load instruction.local to access local variables. If another thread sees the variable b change. there are eleven 64KB banks.extern .b32 const_buffer[]. Threads wait at the barrier until all threads in the CTA have arrived.sync instruction.global to access global variables.Chapter 5. Use ld. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. This reiterates the kind of parallelism available in machines that run PTX.local) is private memory for each thread to keep its own data.4.5.const[bank] modifier. where the size is not known at compile time. The remaining banks may be used to implement “incomplete” constant arrays (in C. as it must be allocated on a perthread basis. For the current devices.const[2] . b = b – 1. For example. This pointer can then be used to access the entire 64KB constant bank. and Variables 5. For example. State Spaces. an incomplete array in bank 2 is accessed as follows: .const[2]. st. All memory writes prior to the bar.const[2] . bank zero is used.extern .global.1. Use ld. Threads must be able to do their work without waiting for other threads to do theirs.3. To access data in contant banks 1 through 10. Local State Space The local state space (. Types. Consider the case where one thread executes the following two assignments: a = a + 1. for example).local and st. Global State Space The global (. The constant memory is organized into fixed size banks. 2010 29 . each pointing to the start address of the specified constant bank. It is typically standard memory with cache. all addresses are in global memory are shared.sync instruction are guaranteed to be visible to any reads after the barrier instruction.b32 const_buffer[]. Module-scoped local memory variables are stored at fixed addresses. Sequential consistency is provided by the bar. It is the mechanism by which different CTAs and different grids can communicate. If no bank number is given.1. bank zero is used for all statically-sized constant variables. // load second word 5. Global memory is not sequentially consistent. as in lock-free and wait-free style programming. ld. Banks are specified using the . where bank ranges from 0 to 10. results in const_buffer pointing to the start of constant bank two.const) state space is a read-only memory.global. initialized by the host. the store operation updating a may still be in flight. [const_buffer+4].

ld.6. The address of a kernel parameter may be moved into a register using the mov instruction. %n. [buffer]. mov.align 8 .b32 len ) { .param . per-kernel versus per-thread).b32 N.1.x supports only kernel function parameters in . 5. device function parameters were previously restricted to the register state space. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. Values passed from the host to the kernel are accessed through these parameter variables using ld.b8 buffer[64] ) { .0 within a function or kernel body are allocated on the stack. in some implementations kernel parameters reside in global memory. [N]. [%ptr]. read-only variables declared in the . Therefore. Note that PTX ISA versions 1. … 30 January 24. These parameters are addressable.param space. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. PTX code should make no assumptions about the relative locations or ordering of . ld. 2010 .u32 %n.reg .param.param instructions.1.0 and requires target architecture sm_20. For example.f64 %d.entry bar ( .6.u32 %n.param.PTX ISA Version 2. The resulting address is in the .u32 %n.param state space. No access protection is provided between parameter and global space in this case. .param .param .reg . Note: The location of parameter space is implementation specific.u32 %ptr.param) state space is used (1) to pass input arguments from the host to the kernel. Example: . Similarly.1. The use of parameter state space for device function parameters is new to PTX ISA version 2.param space variables. The kernel parameter variables are shared across all CTAs within a grid.reg . . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). len. ld. In implementations that do not support a stack.param state space and is accessed using ld.entry foo ( .param. typically for passing large structures by value to a function. all local memory variables are stored at fixed addresses and recursive function calls are not supported. Parameter State Space The parameter (.f64 %d.u32 %ptr.param instructions. … Example: . 5. (2a) to declare formal input and return parameters for device functions called from within kernel execution.

param. Function input parameters may be read via ld.local and st. Note that the parameter will be copied to the stack if necessary.2.6. (4.reg .param.param.param . [buffer+8]. int y.param .local state space and is accessed via ld. Example: // pass object of type struct { double d. }. int y.reg . ld. .align 8 .s32 %y.param.reg . mystruct). .param byte array variable that represents a flattened C structure or union.param.f64 [mystruct+0].f64 %d. In this case. … } // code snippet from the caller // struct { double d.s32 [mystruct+8]. 2010 31 . } mystruct. In PTX. call foo.s32 x. . [buffer]. … See the section on function call syntax for more details. Typically.Chapter 5. January 24.param space is also required whenever a formal parameter has its address taken within the called function. This will be passed by value to a callee. it is illegal to write to an input parameter or read from a return parameter. dbl.1.func foo ( .b32 N. Types. and Variables 5.b8 buffer[12] ) { . passed to foo … .align 8 . the address of a function input parameter may be moved into a register using the mov instruction. It is not possible to use mov to get the address of a return parameter or a locally-scoped . Device Function Parameters PTX ISA version 2.s32 %y. a byte array in parameter space is used.param space variable.local instructions. st.f64 %d. … st. . such as C structures larger than 8 bytes. Aside from passing structures by value. The most common use is for passing objects by value that do not fit within a PTX register. the caller will declare a locally-scoped .0 extends the use of parameter space to device function parameters.reg .b8 mystruct. is flattened. . which declares a . x. and so the address will be in the .param formal parameter having the same size and alignment as the passed argument. ld.reg .param and function return parameters may be written using st.f64 dbl. State Spaces. .

Use ld.tex) state space is global memory accessed via the texture instruction.u32 . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).1. Texture State Space (deprecated) The texture (. where texture identifiers are allocated sequentially beginning with zero. The . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.texref variables in the . tex_d.tex .shared to access shared variables.global state space. Texture memory is read-only.u64. where all threads read from the same address.7. Example: .texref. is equivalent to .u32 . 2010 .shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex . Physical texture resources are allocated on a per-module granularity.tex state space are equivalent to module-scoped . For example. An error is generated if the maximum number of physical resources is exceeded. tex_d.0 5. Another is sequential access from sequential threads.tex directive is retained for backward compatibility.u32 tex_a. One example is broadcast. It is shared by all threads in a context.shared and st.1.tex . 32 January 24.global .texref tex_a.texref type and Section 8. Multiple names may be bound to the same physical texture identifier. and .7.u32 . An address in shared memory can be read and written by any thread in a CTA.tex .tex directive will bind the named texture memory variable to a hardware texture identifier.6 for its use in texture instructions. See Section 5. and variables declared in the . The texture name must be of type . a legacy PTX definitions such as . and programs should instead reference texture memory through variables of type .tex variables are required to be defined in the global scope. Shared memory typically has some optimizations to support the sharing.tex .u32 or . tex_f.8. 5. The . A texture’s base address is assumed to be aligned to a 16-byte boundary. Shared State Space The shared (.u32 tex_a. tex_c.3 for the description of the .PTX ISA Version 2.

and converted using regular-width registers. stored. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. needed to fully specify instruction behavior.s64 . A fundamental type specifies both a basic type and a size. 5. Signed and unsigned integer types are compatible if they have the same size.u32. Types 5. all variables (aside from predicates) could be declared using only bit-size types. . In principle.f32 and . Restricted Use of Sub-Word Sizes The .s8. . Register variables are always of a fundamental type.s16. and . ld. . Types. .b16.f64 types. All floating-point instructions operate only on .2. For example.f64 .s32. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . .u64 .f16 floating-point type is allowed only in conversions to and from . The . and cvt instructions.u16. . so their names are intentionally short. and instructions operate on these types. . or converted to other types and sizes.b64 .2. stored. but typed variables enhance program readability and allow for better operand type checking. Operand types and sizes are checked against instruction types for compatibility.Chapter 5. st. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. so that narrow values may be loaded. Two fundamental types are compatible if they have the same basic type and are the same size. The following table lists the fundamental type specifiers for each basic type: Table 8. 2010 33 . Fundamental Types In PTX. . st.f32 and .u8. .f64 types. .s8.1. The bitsize type is compatible with any fundamental type having the same size.b8. the fundamental types reflect the native data types supported by the target architectures.b8 instruction types are restricted to ld. State Spaces. For convenience.u8. The same typesize specifiers are used for both variable definitions and for typing instructions.f32.f16.2.b32.2. . . January 24. and Variables 5.pred Most instructions have one or more type specifiers.

accessing the pointer with ld and st instructions. These types have named fields similar to structures.{u32. store.PTX ISA Version 2. and .texref handle.u64} reg.surfref.samplerref. sured). The three built-in types are . and Surface Types PTX includes built-in “opaque” types for defining texture. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. Sampler. but the pointer cannot otherwise be treated as an address. 2010 . These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. texture and sampler information is accessed through a single . suld. Creating pointers to opaque variables using mov. base address. In the independent mode. sampler. For working with textures and samplers. Texture. samplers. allowing them to be defined separately and combined at the site of usage in the program.texref. 34 January 24. i.samplerref variables. In the unified mode. Referencing textures. texture and sampler information each have their own handle. suq). passed as a parameter to functions. since these properties are defined by . the resulting pointer may be stored to and loaded from memory. and surface descriptor variables. but all information about layout.3. opaque_var. and de-referenced by texture and surface load. The following tables list the named members of each type for unified and independent texture modes. or surfaces via texture and surface load/store instructions (tex. or performing pointer arithmetic will result in undefined results. In independent mode the fields of the . sust. PTX has two modes of operation.0 5. hence the term “opaque”. and overall size is hidden to a PTX program.texref type that describe sampler properties are ignored.e.. and query instructions. Retrieving the value of a named member via query instructions (txq. . field ordering. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.

Chapter 5.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. and Variables Table 9.texref values . mirror. Member width height depth Opaque Type Fields in Independent Texture Mode .samplerref values N/A N/A N/A N/A nearest. clamp_to_edge. 2010 35 . linear wrap. mirror. Types. Member width height depth Opaque Type Fields in Unified Texture Mode . State Spaces. linear wrap. clamp_to_border 0.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge.texref values in elements in elements in elements 0. 1 ignored ignored ignored ignored . clamp_to_border N/A N/A N/A N/A N/A . clamp_ogl. 1 nearest. clamp_ogl.

param state space. . When declared at module scope.global . the types may be initialized using a list of static expressions assigning values to the named members. these variables are declared in the .global . Example: .global state space. Example: .texref tex1. 36 January 24.global .PTX ISA Version 2.surfref my_surface_name. these variables must be in the . At module scope.texref my_texture_name.samplerref my_sampler_name. .global . 2010 . .0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global . filter_mode = nearest }. As kernel parameters.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.

5. q. // a length-2 vector of unsigned ints . and Variables 5.v4.reg .4.v4. where the fourth element provides padding. 0}. .struct float4 { .global . an optional initializer. January 24. 0.f32 V. 1.global . and they may reside in the register space. Variable Declarations All storage for data is specified with variable declarations.reg .u16 uv. 0.v3 }.1.v1. a variable declaration describes both the variable’s type and its state space.global . A variable declaration names the space in which the variable resides.pred p. 5.Chapter 5.v4 . Variables In PTX. Types. . State Spaces. . for example. Vectors must be based on a fundamental type. . .shared .2. Examples: .reg .f32 accel. Vectors Limited-length vector types are supported. etc. This is a common case for three-dimensional grids.0}. // a length-4 vector of bytes By default.v4 . In addition to fundamental types.v4 .0.4. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. // typedef . Vectors cannot exceed 128-bits in length.f32 v0. vector variables are aligned to a multiple of their overall size (vector length times base-type size).v2 or . PTX supports types for simple aggregate objects such as vectors and arrays. its name. .b8 v.v4 vector. 2010 37 . Three-element vectors may be handled by using a .const . r.u8 bg[4] = {0. its type and size.f64 is not allowed.s32 i. Predicate variables may only be declared in the register state space.v2.v2 . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . an optional array size. Every variable must reside in one of the state spaces enumerated in the previous section. . and an optional fixed address for the variable.global . textures. Examples: .global . // a length-4 vector of floats .struct float4 coord.u32 loc.f32 bias[] = {-1.4.

u64.f16 and .05. 1} }.v4 . 0}. The size of the array specifies how many elements should be reserved.. 0}. Similarly. being determined by an array initializer. 5. label names appearing in initializers represent the address of the next instruction following the label.1.u32 or . // address of rgba into ptr Currently. To declare an array. {0. For the kernel declaration above.1.s32 n = 10.global . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.0.1}.4.4. this can be used to initialize a jump table to be used with indirect branches or calls.PTX ISA Version 2. . 19*19 (361) halfwords are reserved (722 bytes). {0. Here are some examples: . .0.local .4. Variables that hold addresses of variables or instructions should be of type .0}.05}}.pred. . .s32 offset[][] = { {-1.shared . {1.{. Initializers are allowed for all types except .0}.05}..global .0. this can be used to statically initialize a pointer to a variable.u8 rgba[3] = {{1.05. Variable names appearing in initializers represent the address of the variable. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. 2010 .0}}. A scalar takes a single value..0 5.global .global .4.1. Array Declarations Array declarations are provided to allow the programmer to reserve space.0.. variable initialization is supported only for constant and global state spaces. {0.f32 blur_kernel[][] = {{. .u8 mailbox[128]. 38 January 24.{. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). Examples: .1.3.u16 kernel[19][19].b32 ptr = rgba.global .. -1}. or is left empty. {0.1. The size of the dimension is either a constant expression.. where the variable name is followed by an equals sign and the initial value or values for the variable.

. For arrays.0. January 24.Chapter 5. State Spaces.0..b32 variables. For example. Alignment is specified using an optional . %r1. and may be preceded by an alignment specifier.0. Parameterized Variable Names Since PTX supports virtual registers. Array variables cannot be declared this way.0.reg . %r1. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. it is quite common for a compiler frontend to generate a large number of register names. Elements are bytes. // declare %r0. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. suppose a program uses a large number. The default alignment for vector variables is to a multiple of the overall vector size. not for individual elements. named %r0.b32 %r<100>.0. and Variables 5. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.align 4 .align byte-count specifier immediately following the state-space specifier. . alignment specifies the address alignment for the starting address of the entire array. These 100 register variables can be declared as follows: . The variable will be aligned to an address which is an integer multiple of byte-count. say one hundred. . The default alignment for scalar and array variables is to a multiple of the base-type size.5. Types. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.4.b8 bar[8] = {0.. of .const . nor are initializers permitted.4.2. Examples: // allocate array at 4-byte aligned address. 5. ….0}. 2010 39 . %r99. Rather than require explicit declaration of every name.6.

PTX ISA Version 2.0 40 January 24. 2010 .

There is no automatic conversion between types. Instruction Operands 6. the sizes of the operands must be consistent. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. and cvt instructions copy data from one location to another. s. st. and c. The bit-size type is compatible with every type having the same size. Most instructions have an optional predicate guard that controls conditional execution. . The result operand is a scalar or vector variable in the register state space. Operand Type Information All operands in instructions have a known type from their declarations.Chapter 6. 2010 41 . PTX describes a load-store machine. Each operand type must be compatible with the type determined by the instruction template and instruction type. Source Operands The source operands are denoted in the instruction descriptions by the names a. For most operations. Instructions ld and st move data from/to addressable state spaces to/from registers. Predicate operands are denoted by the names p. The cvt (convert) instruction takes a variety of operand types and sizes. mov. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Integer types of a common size are compatible with each other. The mov instruction copies data between registers. and a few instructions have additional predicate source operands. 6.3. q. January 24.1. r. as its job is to convert from nearly any data type to any other data type (and size). The ld. 6.reg register state space. b. so operands for ALU instructions must all be in variables declared in the .2.

u32 42 January 24. Examples include pointer arithmetic and pointer comparisons. Arrays. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.0 6.v4. All addresses and address computations are byte-based.v4 . . q. Here are a few examples: . address register plus byte offset. . The mov instruction can be used to move the address of a variable into a pointer.global .reg .gloal.u16 x. . [tbl+12].s32 q. W.reg . .u16 r0.f32 W. address registers.s32 tbl[256]. Using Addresses. Address expressions include variable names.shared . and vectors. .4. The address is an offset in the state space in which the variable is declared. The syntax is similar to that used in many assembly languages. tbl.s32 mov.f32 V. arrays.PTX ISA Version 2. 6.reg .v4 .[x]. .u16 ld.b32 p. r0.const . there is no support for C-style pointer arithmetic. and immediate address expressions which evaluate at compile-time to a constant address.f32 ld. 2010 . and Vectors Using scalar variables as operands is straightforward. The interesting capabilities begin with addresses.4. [V]. ld.shared. p.1.reg . Load and store operations move data between registers and locations in addressable state spaces.const.

and tex.y V.d}.c. [addr+offset2]. [addr+offset]. where the offset is a constant expression that is either added or subtracted from a register variable.u32 s. mov. . // move address of a[1] into s 6. Rd}.a.b.z and . c. say {Ra. or a braceenclosed list of similarly typed scalars. it must be written as an address calculation prior to use. d. The expression within square brackets is either a constant integer.a 6.global. st. a register variable.global. Rc.g. Vectors may also be passed as arguments to called functions.b V.z V. or by indexing into the array using square-bracket notation. . . Vector elements can be extracted from the vector with the suffixes .4.x.u32 s. b.f32 {a. as well as the typical color fields .x V. V. a[1].global.u32 {a. January 24.b. for use in an indirect branch or call.w.v2.v4.reg . A brace-enclosed list is used for pattern matching to pull apart vectors. Examples are ld. a[N-1]. . which may improve memory performance. The registers in the load/store operations can be a vector. and the identifier becomes an address constant in the space where the array is declared.r.f32 ld.g V.v4. The size of the array is a constant in the program. Rb.3.d}. mov.c. ld.Chapter 6. .f32 V. which include mov.2.v4 . Array elements can be accessed using an explicitly calculated byte address. a[0].f32 a. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Vectors as Operands Vector operands are supported by a limited subset of instructions. 2010 43 . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.4. . Instruction Operands 6.u32 s. and in move instructions to get the address of the label or function into a register. or a simple “register with constant offset” expression. Here are examples: ld. Vector loads and stores can be used to implement wide loads and stores.w = = = = V.reg .y.b and . Elements in a brace-enclosed vector. If more complicated indexing is desired.4.4. V2. Arrays as Operands Arrays of all types can be declared.r V.global. ld.

For example.0 6.s32.1. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. except for operations where changing the size and/or type is part of the definition of the instruction.000 for f16). 2010 . 6. 44 January 24. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. if a cvt.5. and data movement instruction must be of the same type and size. Type Conversion All operands to all arithmetic.PTX ISA Version 2. and ~131.u16 instruction is given a u16 source operand and s32 as a destination operand.5. logic. the u16 is zero-extended to s32. Operands of different sizes or types must be converted prior to the operation.

January 24. For example. Notes 1 If the destination register is wider than the destination format.Chapter 6. f2f = float-to-float. s2f = signed-to-float. Instruction Operands Table 11. the result is extended to the destination register width after chopping. u2f = unsigned-to-float. then sign-extend to 32-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2u = float-to-unsigned.u32 targeting a 32-bit register will first chop to 16-bits.s16. The type of extension (sign or zero) is based on the destination format. zext = zero-extend. 2010 45 . f2s = float-to-signed. cvt. chop = keep only low bits that fit.

Modifier .rz .PTX ISA Version 2. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. In PTX.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rn .rzi .rni .5. The following tables summarize the rounding modifiers. Table 12.rmi .2. Rounding Modifiers Conversion instructions may specify a rounding modifier. choosing even integer if source is equidistant between two integers.rpi Integer Rounding Modifiers Description round to nearest integer.rm .0 6. Modifier . there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 .

Much of the delay to memory can be hidden in a number of ways. 2010 47 . The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Registers are fastest. first access is high Notes January 24.6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Table 14. while global memory is slowest. Another way to hide latency is to issue the load instructions as early as possible. Operand Costs Operands from different state spaces affect the speed of an operation. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Table 11 gives estimates of the costs of using different kinds of memory. The register in a store operation is available much more quickly.Chapter 6. Instruction Operands 6.

PTX ISA Version 2. 2010 .0 48 January 24.

A function must be declared or defined prior to being called. Function declarations and definitions In PTX. … Here. NOTE: The current version of PTX does not implement the underlying. we describe the features of PTX needed to achieve this hiding of the ABI. execution of the call instruction transfers control to foo. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. 7. stack layout. January 24. and an optional list of input parameters. Scalar and vector base-type input and return parameters may be represented simply as register variables. and is represented in PTX as follows: . These include syntax for function definitions. and return values may be placed directly into register variables. A function declaration specifies an optional list of return parameters. function calls. In this section. } … call foo. support for variadic functions (“varargs”). so recursion is not yet supported. parameter passing. The simplest function has no parameters or return values. and Application Binary Interface (ABI). and memory allocated on the stack (“alloca”). together these specify the function’s interface. or prototype. 2010 49 . arguments may be register variables or constants.func foo { … ret.1. Abstracting the ABI Rather than expose details of a particular calling convention. At the call. Execution of the ret instruction within foo transfers control to the instruction following the call. implicitly saving the return address.Chapter 7. A function definition specifies both the interface and the body of the function. stack-based ABI.func directive. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. the function name. functions are declared and defined using the .

b8 [py+10]. ld.s32 out) bar (. In PTX.u32 %res) inc_ptr ( . inc_ptr. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .b8 .reg .f64 f1.param. The .f64 field are aligned. st. c2. [y+8]. st.param. ld.align 8 py[12]. 50 January 24. this structure will be flattened into a byte array.u32 %res. %rc1.c4.b64 [py+ 0]. 2010 . c3. py).param space call (%out). a . First.c1. char c[4].reg .b8 [py+ 9].f1.param state space is used to pass the structure by value: . passed by value to a function: struct { double dbl.func (.param space memory.u32 %ptr. (%r1.param . [y+0].b8 c1. … st.param.reg space.b8 .b8 c3.param.0 Example: . ld. %inc. … … // computation using x.param variable y is used in function definition bar to represent a formal parameter. ret. [y+9]. ld. note that . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . [y+11].param. c4.reg .s32 x.c3.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.param.b8 [py+11]. st.param.align 8 y[12]) { .b32 c1. bumpptr.param.param . For example.b8 [py+ 8]. %ptr.f64 f1.reg . . a .param space variables are used in two ways. %rc2. … ld. [y+10].param. %rd. (%x. // scalar args in . } … call (%r1).c2. … In this example.PTX ISA Version 2. . Since memory accesses are required to be aligned to a multiple of the access size.u32 %inc ) { add. Second.4). } { .b8 c2. %rc1.b8 c4.reg .param. st. consider the following C structure.reg . }. . byte array in .func (. %rc2.reg .

param space formal parameters that are base-type scalar or vector variables.reg variables. Supporting the .param argument must be declared within the local scope of the caller.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.reg space variable with matching type and size. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. a . For a callee.Chapter 7.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. The . all st. and alignment.param state space use in device functions. or constants. .param or .. • The . • • • For a callee. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.reg state space can be used to receive and return base-type scalar and vector values.param space byte array with matching type. the corresponding argument may be either a . This enables backend optimization and ensures that the . or 16 bytes. In the case of .reg variables. 2010 51 .param variables or . In the case of .g. Abstracting the ABI The following is a conceptual way to think about the .param state space is used to receive parameter values and/or pass return values back to the caller.param arguments.reg state space in this way provides legacy support. • • • Input and return parameters may be .param and ld.reg space variable of matching type and size.param or .reg space formal parameters.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. 8. A . 2. • • Arguments may be . the argument must also be a . and alignment of parameters. For .param space formal parameters that are byte arrays. In the case of .param instructions used for argument passing must be contained in the basic block with the call instruction. size. • The . Note that the choice of . January 24. or a constant that can be represented in the type of the formal parameter. or a constant that can be represented in the type of the formal parameter. Parameters in . the corresponding argument may be either a .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. The following restrictions apply to parameter passing.param memory must be aligned to a multiple of 1. For a caller. size. 4.param variables.param byte array is used to collect together fields of a structure being passed by value. For a caller. Typically.reg or . The .

1.x In PTX ISA version 1. PTX 2. formal parameters may be in either . PTX 1.PTX ISA Version 2. For sm_2x targets.1. formal parameters were restricted to . 52 January 24.0 restricts functions to a single return value. and there was no support for array parameters. Objects such as C structures were flattened and passed or returned using multiple registers.param byte array should be used to return objects that do not fit into a register.0 7.param state space. PTX 2.reg state space.reg or .param space parameters support arrays. and a .x. Changes from PTX 1.0 continues to support multiple return registers for sm_1x targets.x supports multiple return values for this purpose. 2010 .0. and . In PTX ISA version 2.

%s1. %va_end is called to free the variable argument list handle.reg . … ) . In both cases. // default to MININT mov. and end access to a list of variable arguments. maxN. variadic functions are declared with an ellipsis at the end of the input parameter list.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. 4.func (.u32 ptr. %r3).func (. bra Loop.reg .reg . 4). Abstracting the ABI 7.reg . setp. max. This handle is then passed to the %va_arg and %va_arg64 built-in functions. . .reg . the alignment may be 1.reg .u32 sz. %r1.u32 align) . 4.u32 a. . 2.u32 ptr. … %va_start returns Loop: @p Done: January 24. 2010 53 .b32 result. 2. bra Done.s32 result ) maxN ( .. iteratively access. the size may be 1. the size may be 1.b64 val) %va_arg64 (. maxN. %r2.reg .reg . or 16 bytes.func baz ( . %s2).u32 sz. or 8 bytes. call (ap). 4.Chapter 7. 0x8000000. The function prototypes are defined as follows: . … call (%max).func (. For %va_arg. N. To support functions with a variable number of arguments.2.b32 ctr.. %va_arg.ge p. call (val). ret. mov.pred p.s32 result. } … call (%max).s32 val. (2. ) { . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . ctr.reg . (ap. or 4 bytes. . following zero or more fixed parameters: . In PTX. call %va_end.u32 ap.reg . Once all arguments have been processed.func okay ( … ) Built-in functions are provided to initialize.reg . 0.u32 ptr) %va_start . . 2. for %va_arg64.u32 b.reg .reg .u32.u32 N. result. val. along with the size and alignment of the next data value to be accessed.reg .b32 val) %va_arg (.reg . PTX provides a high-level mechanism similar to the one provided by the stdarg.u32 align) . ctr.h and varargs. .h headers in C.func ( .reg . Variadic functions NOTE: The current version of PTX does not support variadic functions. (ap). 8. %va_start.reg .func %va_end (. . . (3.

a function simply calls the built-in function %alloca. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.u32 ptr ) %alloca ( .local and st.0 7.PTX ISA Version 2. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. 2010 . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( . 54 January 24. If a particular alignment is required.local instructions.3. The array is then accessed with ld.reg . Alloca NOTE: The current version of PTX does not support alloca.reg . defined as follows: . To allocate memory.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.

B. We use a ‘|’ symbol to separate multiple destination registers. January 24. opcode D. In addition to the name and the format of the instruction. 8. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. setp. For some instructions the destination operand is optional. q = !(a < b). For instructions that create a result value. A. opcode D. A. while A. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode.lt p|q. and C are the source operands. Instruction Set 8. B. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. b. opcode A.Chapter 8. a. The setp instruction writes two destination registers. C.2. 2010 55 . the semantics are described.s32. B. PTX Instructions PTX instructions generally have from zero to four operands. A. // p = (a < b). followed by some examples that attempt to show several possible instantiations of the instruction. opcode D. the D operand is the destination operand.1.

where p is a predicate variable.s32 p. q.0 8.pred p. j.s32 p.pred as the type specifier. predicate registers are virtual and have . As an example. This can be written in PTX as @p setp.s32 j.lt. Predicates are most commonly set as the result of a comparison performed by the setp instruction. branch over 56 January 24.PTX ISA Version 2. i.3. add. the following PTX instruction sequence might be used: @!p L1: setp. 1. add 1 to j To get a conditional branch or conditional function call. consider the high-level code if (i < n) j = j + 1. … // compare i to n // if false. use a predicate to control the execution of the branch or call instructions. // p = (i < n) // if i < n. j. n.lt. bra L1. To implement the above example as a true conditional branch. i. Predicated Execution In PTX. 2010 .s32 j. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. add. 1. optionally negated. Instructions without a guard predicate are executed unconditionally. predicate registers can be declared as . r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.reg . n. So.

If either operand is NaN.Chapter 8. The unsigned comparisons are eq. Table 16.1. ne.1. le. Unsigned Integer. The following table shows the operators for signed integer. gt (greater-than). Comparisons 8. and ge (greater-than-or-equal). ne. ls (lower-or-same).1. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. 2010 57 .3. lt (less-than). ne (not-equal). le (less-than-or-equal).1. lt. gt. The bit-size comparisons are eq and ne.2. the result is false. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. ordering comparisons are not defined for bit-size types. Table 15. ge. and hs (higher-or-same). unsigned integer. and bitsize types.3. hi (higher). Instruction Set 8.3. lo (lower). and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.

However.3. Table 18. There is no direct conversion between predicates and integer values. geu. // convert predicate to 32-bit value 58 January 24. neu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.u32 %r1. and nan returns true if either operand is NaN. 2010 . then the result of these comparisons is true.%p. unordered versions are included: equ. and no direct way to load or store predicate register values. not.1. or. xor. and mov. setp can be used to generate a predicate from an integer. If either operand is NaN.PTX ISA Version 2. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. leu.0 To aid comparison operations in the presence of NaN values. for example: selp.0.2. num returns true if both operands are numeric values (not NaN). Table 17. then these comparisons have the same result as their ordered counterparts. two operators num (numeric) and nan (isNaN) are provided. If both operands are numeric values (not NaN). ltu. gtu.

most notably the data conversion instruction cvt. 2010 59 .sX ok ok ok inv .4. Instruction Set 8.u16 d. Floating-point types agree only if they have the same size.e.reg . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. Signed and unsigned integer types agree provided they have the same size. a. For example: . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.reg . add. For example.uX . It requires separate type-size modifiers for the result and source. float..u16 d. i. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.uX ok ok ok inv . unsigned. a.fX ok ok ok ok January 24.bX . cvt. Table 19. Example: . . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. different sizes).u16 a.f32. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.sX . the add instruction requires type and size information to properly perform the addition operation (signed.bX . and integer operands are silently cast to the instruction type if needed. and this information must be specified as a suffix to the opcode.f32 d. a.u16 d. For example. they must match exactly.Chapter 8.reg . b. • The following table summarizes these type checking rules. Type Checking Rules Operand Type . b. and these are placed in the same order as the operands.fX ok inv inv ok Instruction Type .

no conversion needed. unless the operand is of bit-size type. Floating-point source registers can only be used with bit-size or floating-point instruction types.PTX ISA Version 2. stored. inv = invalid. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. and converted using regular-width registers. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Operand Size Exceeding Instruction-Type Size For convenience. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. 2010 . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.4. the size must match exactly. When used with a floating-point instruction type. Notes 3. Table 20. 60 January 24. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. Bit-size source registers may be used with any appropriately-sized instruction type. When used with a narrower bit-size type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. When a source operand has a size that exceeds the instruction-type size. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. st. “-“ = allowed. 4. Source register size must be of equal or greater size than the instruction-type size. parse error. Note that some combinations may still be invalid for a particular instruction. The following table summarizes the relaxed type-checking rules for source operands. so those rows are invalid for cvt. for example. The data is truncated to the instruction-type size and interpreted according to the instruction type. stored.0 8. so that narrow values may be loaded.bX instruction types.1. ld. floating-point instruction types still require that the operand type-size matches exactly. 1. 2. the data will be truncated. or converted to other types and sizes. For example. the cvt instruction does not support .

Instruction Set When a destination operand has a size that exceeds the instruction-type size. January 24. and is zero-extended to the destination register width otherwise.or sign-extended to the size of the destination register. parse error. Notes 3.Chapter 8. 4. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Destination register size must be of equal or greater size than the instruction-type size. The data is sign-extended to the destination register width for signed integer instruction types. When used with a narrower bit-size instruction type. the destination data is zero. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Table 21. Bit-size destination registers may be used with any appropriately-sized instruction type. inv = Invalid. When used with a floatingpoint instruction type. zext = zero-extend. 1. the data is sign-extended. Floating-point destination registers can only be used with bit-size or floating-point instruction types. The following table summarizes the relaxed type-checking rules for destination operands. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. If the corresponding instruction type is signed integer. the size must match exactly. “-“ = Allowed but no conversion needed. otherwise. the data is zeroextended. the data will be zero-extended. 2. 2010 61 . The data is signextended to the destination register width for signed integer instruction types.

since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. this is not desirable. A compiler or programmer may chose to enforce portable.0 8.PTX ISA Version 2. the optimizing code generator automatically determines points of re-convergence. until they come to a conditional control construct such as a conditional branch. Divergence of Threads in Control Constructs Threads in a CTA execute together. until C is not expressive enough. The semantics are described using C. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. When executing on a 32-bit data path. the threads are called uniform. or conditional return. using the . For divergent control flow.6. for example.1. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. a compiler or code author targeting PTX can ignore the issue of divergent threads. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs.5. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. At the PTX language level. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. so it is important to have divergent threads re-converge as soon as possible.6. and 16-bit computations are “promoted” to 32-bit computations. Therefore. conditional function call. If all of the threads act in unison and follow a single control flow path. for many performance-critical applications. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. and for many applications the difference in execution is preferable to limiting performance. Both situations occur often in programs. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. by a right-shift instruction. 16-bit registers in PTX are mapped to 32-bit physical registers. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. 8. 2010 . If threads execute down different control flow paths. 8.uni suffix. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. However. the threads are called divergent. the semantics of 16-bit instructions in PTX is machine-specific. These extra precision bits can become visible at the application level. at least in appearance. 62 January 24.

In the following descriptions. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. Instructions All PTX instructions may be predicated. 2010 63 . 8.7. the optional guard predicate is omitted from the syntax. The Integer arithmetic instructions are: add sub add.Chapter 8. Instruction Set 8.cc.7. addc sub. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.cc.1.

u16.type = { . a.s32 . .u16.. d..sat limits result to MININT. Applies only to . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.0 Table 22.s16.s32. add Syntax Integer Arithmetic Instructions: add Add two values. b. b.MAXINT (no overflow) for the size of the operation. .sat}. a.s32 .u64. .type = { .c. d = a + b. PTX ISA Notes Target ISA Notes Examples 64 January 24. add.sat limits result to MININT. d. sub. 2010 .sat applies only to . Saturation modifier: .a. // . . @p add.u32 x.s32 c. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Introduced in PTX ISA version 1. a.s64 }.sat}. // .s32 d.type add{.sat. Applies only to .s64 }. . .s32.sat applies only to .u32. .PTX ISA Version 2.MAXINT (no overflow) for the size of the operation. Introduced in PTX ISA version 1. Saturation modifier: .0.s16. Description Semantics Notes Performs addition and writes the resulting value into a destination register.y. . d = a – b. . sub.s32 c.1.s32 type. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Table 23. b. add.0.s32 d. Supported on all target architectures. .type sub{.s32 type.z.u64.u32. b. a.b.

z2. addc.y4.type d.2. @p @p @p @p add. x4.cc.type = {. Instruction Set Instructions add. carry-out written to CC.z4.type = { . d = a + b. Supported on all target architectures. No other instructions access the condition code. x4. x2.z1.CF) holding carry-in/carry-out or borrowin/borrow-out. .cc Add two values with carry-out.z4. or testing the condition code.b32 x1.y2.z3.b32 addc.b32 addc. Behavior is the same for unsigned and signed integers. 2010 65 .cc. add.cc specified.z3.y3. Table 24. b. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. No saturation.y1. a.b32 addc.Chapter 8.cc Syntax Integer Arithmetic Instructions: add. clearing. These instructions support extended-precision integer addition and subtraction.y1.cc.cc.y2. @p @p @p @p add. .y3. carry-out written to CC. x3.b32 addc.cc}. d = a + b + CC.type d.CF.cc.u32.z1. if . x3.CF No integer rounding modifiers. x2. sub. and there is no support for setting.y4.z2. .s32 }. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. Introduced in PTX ISA version 1. add.cc. addc{. b. Introduced in PTX ISA version 1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.b32 addc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. Supported on all target architectures. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.b32 addc. .cc.2. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers. a.b32 x1.s32 }.cc.u32. No saturation.cc.

@p @p @p @p sub.3. No saturation.cc specified.u32.CF).b32 subc.(b + CC. b. d = a – b.y2.cc.z4.y1.z4. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.y4.cc. .cc. Introduced in PTX ISA version 1. No saturation. Behavior is the same for unsigned and signed integers. x4.b32 subc. borrow-out written to CC. .z3. with borrow-out.b32 subc.y2.type d. subc{. b.CF No integer rounding modifiers. x4.s32 }. Introduced in PTX ISA version 1.b32 x1.z2. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. x2.b32 subc.s32 }. a.3. sub. 2010 . Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. @p @p @p @p sub.y1.b32 subc.cc.b32 subc. Supported on all target architectures. if .cc. d = a .type = {. x2.type = { . .cc Syntax Integer Arithmetic Instructions: sub. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.z3.z1.cc.PTX ISA Version 2. withborrow-in and optional borrow-out. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.z1.cc}. a.y3. borrow-out written to CC.y4.0 Table 26.type d.b32 x1.u32. Behavior is the same for unsigned and signed integers. sub. x3. . Supported on all target architectures. x3.cc Subract one value from another.cc.y3.CF No integer rounding modifiers.cc.z2.cc.

s64 }.lo variant Notes The type of the operation represents the types of the a and b operands. If .type = { .type d. Instruction Set Table 28.hi or .x. // 16*16 bits yields 32 bits // 16*16 bits.fys.fxs. mul. n = bitwidth of type. save only the low 16 bits // 32*32 bits.Chapter 8. d = t<2n-1.s32.n>... If .lo.s16 fa.u32.wide}. mul. 2010 67 .wide.wide suffix is supported only for 16.and 32-bit integer types. . .0.hi variant // for . mul{.fys.s16 fa.lo is specified. mul. Supported on all target architectures.fxs. . a.wide // for . t = a * b. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.hi.wide is specified.. . b.u16. and either the upper or lower half of the result is written to the destination register.wide.s32 z. The . d = t<n-1..y. // for .s16. then d is the same size as a and b. . . creates 64 bit result January 24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0>. d = t. Description Semantics Compute the product of two values. then d is twice as wide as a and b to receive the full result of the multiplication.u64.lo.

c. and either the upper or lower half of the result is written to the destination register.s32 d.and 32-bit integer types.PTX ISA Version 2.hi mode.n> + c.a. c. then d and c are the same size as a and b.lo. Supported on all target architectures.b.hi or .s16.type mad. t + c. c. t<n-1. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.sat. If .sat limits result to MININT.p. @p mad.MAXINT (no overflow) for the size of the operation. . 68 January 24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .hi.wide suffix is supported only for 16. a.u16. mad{.lo variant Notes The type of the operation represents the types of the a and b operands. then d and c are twice as wide as a and b to receive the result of the multiplication.0> + c. t<2n-1.hi variant // for .0 Table 29. Applies only to . a. and then writes the resulting value into a destination register. t n d d d = = = = = a * b.. bitwidth of type.lo. .u32.u64. Saturation modifier: .s32. mad. b. ..type = { .. d. // for .s32 type in .s64 }.s32 r. Description Semantics Multiplies two values and adds a third.s32 d. b.wide is specified.wide}.0.lo.hi.q.wide // for . The . .lo is specified..r. . If . 2010 ..

mul24. and return either the high or low 32-bits of the 48-bit result.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. 48bits. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24.Chapter 8.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. // for .type d. t = a * b. All operands are of the same type and size. Supported on all target architectures.s32 }. mul24{. mul24. .0. .u32. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. 2010 69 . Instruction Set Table 30.a.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.s32 d.type = { . January 24.e.hi may be less efficient on machines without hardware support for 24-bit multiply.b.. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. a. // low 32-bits of 24x24-bit signed multiply.16>. mul24.lo}. d = t<47..lo.hi.0>. i. d = t<31.. b.hi variant // for .

b. b. Applies only to . mad24. Return either the high or low 32-bits of the 48-bit result.c.hi mode.s32 }. 70 January 24.lo}. mad24..0 Table 31.u32. and add a third. Saturation modifier: .hi. b. // for .0> + c. mad24. c.hi may be less efficient on machines without hardware support for 24-bit multiply. a.a.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.sat.s32 d.. d. d = t<31. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..s32 type in . // low 32-bits of 24x24-bit signed multiply.e.PTX ISA Version 2. t = a * b. mad24. .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. Supported on all target architectures. 48bits.type mad24.type = { .sat limits result of 32-bit signed addition to MININT. c. Description Compute the product of two 24-bit integer values held in 32-bit source registers. a.s32 d. All operands are of the same type and size.hi. 2010 . 32-bit value to either the high or low 32-bits of the 48-bit result.lo.. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.MAXINT (no overflow). i.0.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. d = t<47. .16> + c. mad24{.hi variant // for .

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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} Introduced in PTX ISA version 2.type = { . . a = a >> 1.b32 type.b32 popc.b64 }.b64 d. d = 0.b32 clz. cnt. . popc Syntax Integer Arithmetic Instructions: popc Population count. popc. the number of leading zeros is between 0 and 32. For . mask = 0x8000000000000000. popc. } while (d < max && (a&mask == 0) ) { d++.type d. a. cnt. a. For .b32) { max = 32. d = 0. clz. 2010 . popc requires sm_20 or later.PTX ISA Version 2. // cnt is . X.0. inclusively. if (. // cnt is .type d. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. X.b64 }.0 Table 39.0.b32. .u32 Semantics 74 January 24.type = { .b64 type. mask = 0x80000000. a. clz. while (a != 0) { if (a&0x1) d++. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . a = a << 1.u32 PTX ISA Notes Target ISA Notes Examples Table 40. clz requires sm_20 or later. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.b64 d. } else { max = 64. a.type == .b32. the number of leading zeros is between 0 and 64. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. inclusively.

d. . If . Instruction Set Table 41. and operand d has type .type bfind. a. 2010 75 .shiftamt.type==. bfind. a.type = { .shiftamt. For signed integers.shiftamt && d != -1) { d = msb .s64 cnt.type==. bfind requires sm_20 or later. a.u64.u32 || . Semantics msb = (. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind.s32. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.s32) ? 31 : 63. d = -1. i--) { if (a & (1<<i)) { d = i.0. i>=0.u32 January 24. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. X. bfind. // cnt is . For unsigned integers. } } if (.Chapter 8.u32. . break. Operand a has the instruction type.shiftamt is specified.u32. . bfind returns the bit position of the most significant “1”.d. . bfind returns 0xFFFFFFFF if no non-sign bit is found.type d. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.s64 }.u32 d. for (i=msb. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

.b32) ? 31 : 63.type d. i++) { d[i] = a[msb-i]. 76 January 24.PTX ISA Version 2. a. msb = (. for (i=0. . 2010 . Description Semantics Perform bitwise reversal of input.b32 d.0 Table 42.b32.0. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b64 }.type = { . brev.type==. i<=msb. brev requires sm_20 or later. a. brev.

Source b gives the bit field starting bit position. else sbit = a[min(pos+len-1. The sign bit of the extracted field is defined as: .u64.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. a.u32 || .u32. len = c.type = { .u64 || len==0) sbit = 0. i<=msb. 2010 77 . for (i=0.u32. pos = b. .s32) ? 31 : 63.type==.a.s32.msb)]. bfe. .type==. If the start position is beyond the msb of the input.s64 }. Instruction Set Table 43. if (. Semantics msb = (. The destination d is padded with the sign bit of the extracted field.start. January 24. .0. otherwise If the bit field length is zero.type d. Operands a and d have the same type as the instruction type. bfe requires sm_20 or later. and source c gives the bit field length in bits.Chapter 8. the destination d is filled with the replicated sign bit of the extracted field. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. . .u64: . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and operands b and c are type .u32. Description Extract bit field from a and place the zero or sign-extended result in d. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.b32 d.len.type==.u32 || . the result is zero. b. bfe. d = 0.type==. .s32. c.

. If the start position is beyond the msb of the input. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. for (i=0. and f have the same type as the instruction type. i<len && pos+i<=msb.type f. len = d.0 Table 44. .0. If the bit field length is zero. 78 January 24. 2010 .u32. bfi.start. b. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.type = { . Source c gives the starting bit position for the insertion. pos = c.a. bfi. Semantics msb = (.b64 }.b32 d. Operands a. the result is b. i++) { f[pos+i] = a[i]. the result is b. c. Description Align and insert a bit field from a into b.b.PTX ISA Version 2. and place the result in f.type==. d. b. a. and operands c and d are type . f = b.b32.b32) ? 31 : 63.len. bfi requires sm_20 or later. and source d gives the bit field length in bits.

b. b5.rc8. In the generic form (no mode specified). and reassemble them into a 32-bit destination register. Note that the sign extension is only performed as part of generic form.mode = { .Chapter 8.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. Instruction Set Table 45. as a 16b permute code. msb=1 means replicate the sign. b4}. 2010 79 . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. default mode index d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.b32{.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. b6. b1. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.b4e.ecr. the permute control consists of four 4-bit selection values.b3 source select c[15:12] d. . a. . a 4-bit selection value is defined.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. . b2. . c. .b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.f4e. . msb=0 means copy the literal value.b2 source select c[11:8] d. The msb defines if the byte value should be copied.ecl. Description Pick four arbitrary bytes from two 32-bit registers. The bytes in the two source registers are numbered from 0 to 7: {b. {b3. a} = {{b7. Thus.mode} d.rc16 }. prmt. For each byte in the target register. b0}}. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). the four 4-bit values fully specify an arbitrary byte permute.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b1 source select c[7:4] d.

r1.PTX ISA Version 2. ctl[3] = (c >> 12) & 0xf. tmp[31:24] = ReadByte( mode. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r2. ctl[2] = (c >> 8) & 0xf.f4e r1. r4. 80 January 24. r3. r2. r3. prmt requires sm_20 or later. ctl[1] = (c >> 4) & 0xf. ctl[0].b32.0. 2010 . ctl[1]. prmt. tmp[23:16] = ReadByte( mode. tmp64 ).b32 prmt.0 Semantics tmp64 = (b<<32) | a. ctl[3]. tmp64 ). r4. tmp64 ). tmp[15:08] = ReadByte( mode. } tmp[07:00] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[2].

f32 and . 2010 81 .Chapter 8.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2.7. Instruction Set 8.

but single-precision instructions return an unspecified NaN.lg2.f32 {add.f32 {div. Single-precision add. so PTX programs should not rely on the specific single-precision NaNs being generated.max}.f64 div.f64 {abs.f32 {div.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. 82 January 24.f32 are the same.fma}. default is .rnd.0.rp .rcp. Note that future implementations may support NaN payloads for single-precision instructions.f64 and fma.f64 mad.sat Notes If no rounding modifier is specified. and mad support saturation of results to the range [0.f64 are the same. {add.32 and fma.sqrt}.f64 {sin.f32 {abs.mul}.mul}.approx.sub.sqrt}.f32 rsqrt.cos. Instruction Summary of Floating-Point Instructions . .rz .target sm_1x No rounding modifier. No rounding modifier.rnd.f32 {div. default is .rn .f64 rsqrt.f32 {mad. If no rounding modifier is specified.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.approx.full.sub. sub. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. Double-precision instructions support subnormal inputs and results. 2010 .rn and instructions may be folded into a multiply-add.rnd.target sm_20 mad.target sm_20 .approx.ex2}. Table 46.rnd.sqrt}. The optional . {mad.0 The following table summarizes floating-point instructions in PTX.ftz .max}.min. .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.0].rnd. with NaNs being flushed to positive zero.min.rnd.rn and instructions may be folded into a multiply-add.fma}.PTX ISA Version 2.neg. 1.approx.neg.rcp.f32 .rcp. mul. NaN payloads are supported for double-precision instructions.rm .

copysign. A. a. 2010 83 . testp Syntax Floating-Point Instructions: testp Test floating-point property.f32.infinite testp.notanumber.f32.infinite. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type . a. not infinity) As a special case. Instruction Set Table 47.f64 }.finite.f64 }. . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.0.type = { . . . copysign. y. January 24. . testp. X. . testp requires sm_20 or later.pred = { .finite testp.Chapter 8.op.notanumber. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.type d.number testp. true if the input is a subnormal number (not NaN.f32 testp.infinite.subnormal }.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. b. .op p.f64 x. C. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. p. testp. and return the result as d. positive and negative zero are considered normal numbers.f32 copysign.notanumber testp. .normal testp. Introduced in PTX ISA version 2. // result is . .0. f0. B. copysign requires sm_20 or later.type = { . z. testp. not infinity). Table 48.number.f64 isnan.normal.

An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. add{.f64 requires sm_13 or later.0f.rm. . requires sm_20 Examples @p add. .rm mantissa LSB rounds towards negative infinity .rn. .rnd}{. add.ftz.sat}.rz.f3.rz available for all targets .f32 clamps the result to [0.rp }. add.0.f32 f1.f32 add{.f32.f32 supported on all target architectures. add. requires sm_13 for add.rn mantissa LSB rounds to nearest even . add Syntax Floating-Point Instructions: add Add two values. sm_1x: add.0].PTX ISA Version 2. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. d. In particular. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 d. 2010 . a. Description Semantics Notes Performs addition and writes the resulting value into a destination register. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers have the following target requirements: . a. .rp for add. Rounding modifiers (default is .rnd}. subnormal numbers are supported.ftz}{.rm.0. b.rz.0 Table 49.sat.rn): .ftz. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn.rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero. .f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. 84 January 24. add.f64. b.rnd = { . d = a + b. . Saturation modifier: .f2. NaN results are flushed to +0. add.

rm mantissa LSB rounds towards negative infinity . sub.rn.f32 c. Rounding modifiers have the following target requirements: . Rounding modifiers (default is .b.sat}.rz available for all targets .sat.b.rz.rnd}{. requires sm_13 for sub.rm.rnd = { .ftz. sub.rz mantissa LSB rounds towards zero .rp }.f32 flushes subnormal inputs and results to sign-preserving zero.rn. Instruction Set Table 50.rn): . Saturation modifier: sub. .f32 clamps the result to [0. . sm_1x: sub. subnormal numbers are supported. NaN results are flushed to +0.Chapter 8. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rn. sub{.f32 flushes subnormal inputs and results to sign-preserving zero.f2.f32 sub{. d = a . a. sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_20 Examples sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. a. b.f32. .a.0.rn mantissa LSB rounds to nearest even .rnd}.0f.f3.0. 1.f64.f64 supports subnormal numbers. January 24.f32 supported on all target architectures.0].ftz}{. sub. b.f64 requires sm_13 or later. .rm.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . 2010 85 . d.ftz. .rp for sub. In particular. sub Syntax Floating-Point Instructions: sub Subtract one value from another.f32 f1.f64 d. sub.

. mul. Rounding modifiers (default is . 2010 . a. Saturation modifier: mul.f64 d.pi // a single-precision multiply 86 January 24.rnd}{.sat}. d = a * b.f32 flushes subnormal inputs and results to sign-preserving zero. For floating-point multiplication.rn): . .f32 mul{.rp }. d. mul Syntax Floating-Point Instructions: mul Multiply two values.rp for mul. mul{.rnd}. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rz available for all targets .0.rn.f32. 1.ftz. mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rn.sat. .rn mantissa LSB rounds to nearest even . requires sm_20 Examples mul.0.rm. b. sm_1x: mul. a.f64. requires sm_13 for mul. Description Semantics Notes Compute the product of two values.0 Table 51.rm. all operands must be the same size.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .f32 supported on all target architectures.ftz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rnd = { . .f32 clamps the result to [0.rz. NaN results are flushed to +0.f32 circumf.0]. mul. mul. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero. b.rm mantissa LSB rounds towards negative infinity . subnormal numbers are supported.0f. .rz mantissa LSB rounds towards zero .f64 requires sm_13 or later.f64 supports subnormal numbers. Rounding modifiers have the following target requirements: . In particular.radius.ftz}{.

f32 fma. again in infinite precision.rn.f32 computes the product of a and b to infinite precision and then adds c to this product. PTX ISA Notes Target ISA Notes Examples January 24.rnd = { .ftz}{.0]. . The resulting value is then rounded to single precision using the rounding mode specified by .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 fma.ftz.sat.y. a.rz mantissa LSB rounds towards zero .rm mantissa LSB rounds towards negative infinity .rnd.f32 clamps the result to [0. 1. b.f64 w. d. subnormal numbers are supported.rm.c.0f. b. Rounding modifiers (no default): . fma. @p fma. Instruction Set Table 52.4.0.x. NaN results are flushed to +0.rn mantissa LSB rounds to nearest even .rn.Chapter 8.f64 d. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f64 is the same as mad. c. fma.f64 requires sm_13 or later. fma.f32 requires sm_20 or later. fma.z. . fma Syntax Floating-Point Instructions: fma Fused multiply-add.rp }.rnd.rnd.rn.f32 flushes subnormal inputs and results to sign-preserving zero. a. fma. sm_1x: fma.f64 introduced in PTX ISA version 1. fma. .f32 introduced in PTX ISA version 2. again in infinite precision. c.sat}. d = a*b + c. fma.f64. 2010 87 . fma. .b.rz.ftz. d.f64 supports subnormal numbers.0.f32 is unimplemented in sm_1x. fma.a. Saturation: fma.f64 computes the product of a and b to infinite precision and then adds c to this product.rnd{. fma. The resulting value is then rounded to double precision using the rounding mode specified by .

// . Note that this is different from computing the product with mul. b. mad. . mad.rnd.target sm_20: mad.f64 computes the product of a and b to infinite precision and then adds c to this product. again in infinite precision. NaN results are flushed to +0. Rounding modifiers (no default): . a.rnd = { . sm_1x: mad.sat.f32 flushes subnormal inputs and results to sign-preserving zero.f64}.rm mantissa LSB rounds towards negative infinity .target sm_20 d.rn.{f32. .f64 d.rp }. a.sat}. mad{.target sm_1x d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm.0.f32 clamps the result to [0. b. c. The resulting value is then rounded to single precision using the rounding mode specified by . . Description Semantics Notes Multiplies two values and adds a third. mad. In this case.f32 computes the product of a and b to infinite precision and then adds c to this product.target sm_1x: mad.rnd.0].f64. The resulting value is then rounded to double precision using the rounding mode specified by .{f32.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. and then the mantissa is truncated to 23 bits. but the exponent is preserved.f32 is when c = +/-0. b.0. c. Unlike mad. The resulting value is then rounded to double precision using the rounding mode specified by . again in infinite precision.e. where the mantissa can be rounded and the exponent will be clamped.PTX ISA Version 2.0 devices.rz.ftz. fma.rnd.0 Table 53.target sm_13 and later . mad. subnormal numbers are supported. 1.f32).rn mantissa LSB rounds to nearest even .rnd{.f32 flushes subnormal inputs and results to sign-preserving zero. again in infinite precision. // . mad.rz mantissa LSB rounds towards zero .f32 is implemented as a fused multiply-add (i.f64 is the same as fma. d = a*b + c.ftz.f32 computes the product of a and b at double precision.rnd. the treatment of subnormal inputs and output follows IEEE 754 standard.rn.f32 mad. 88 January 24. mad.0f. When JIT-compiled for SM 2.f64 computes the product of a and b to infinite precision and then adds c to this product.sat}. mad.f64 supports subnormal numbers. and then writes the resulting value into a destination register.f32 is identical to the result computed using separate mul and add instructions. For . // .f64} is the same as fma. Saturation modifier: mad. c. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. The exception for mad.f32. For . mad.f32 mad.ftz}{.. a. 2010 .ftz}{. mad.

In PTX ISA versions 2.rn.f32 for sm_20 targets.f64. Target ISA Notes mad. Rounding modifiers have the following target requirements: .c. 2010 89 . requires sm_13 .. a rounding modifier is required for mad.f32.f32 supported on all target architectures. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.b.rm.4 and later.rn.. In PTX ISA versions 1.rn.rm.rz.f64. a rounding modifier is required for mad. mad.. January 24.rz..f64 instructions having no rounding modifier will map to mad..rp for mad.. requires sm_20 Examples @p mad.rp for mad.f64 requires sm_13 or later.f32 d. Legacy mad.0.a.Chapter 8.0 and later.f64.

ftz}.rn mantissa LSB rounds to nearest even .rnd{.rnd = { .rn.f32 and div.ftz. zd.ftz}. div. Examples 90 January 24.approx.rn.f32 supported on all target architectures. full-range approximation that scales operands to achieve better accuracy. and rounding introduced in PTX ISA version 1. y.14159.0 Table 54.f32 implements a fast approximation to divide.0 through 1.f64 d.0.PTX ISA Version 2. x. Subnormal inputs and results are flushed to sign-preserving zero. b. but is not fully IEEE 754 compliant and does not support rounding modifiers. d. .f64 requires sm_13 or later. a.approx{.rz mantissa LSB rounds towards zero . .full.f32 div.f64 requires sm_20 or later.rnd. The maximum ulp error is 2 across the full range of inputs.{rz. div.3. div.ftz. and div. b. div.f64 introduced in PTX ISA version 1.circum. xd. PTX ISA Notes div. Target ISA Notes div. div. .f32 div. // // // // fast.3. .rm mantissa LSB rounds towards negative infinity .f32 requires sm_20 or later.full{. Explicit modifiers . .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. a.rp}. div.ftz. div. Fast. 2010 . computed as d = a * (1/b).ftz. .approx.rnd is required.f32 div.approx. div.approx.ftz}. stores result in d.f32 div.rnd.full.f32 div. approximate division by zero creates a value of infinity (with same sign as a).rz. yd. div. b. For b in [2-126. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .full.f32.approx. b.approx.rm. div Syntax Floating-Point Instructions: div Divide one value by another. z.rp }.f64 supports subnormal numbers.ftz.rm.4. d.f64 diam.f64 defaults to div.f32 flushes subnormal inputs and results to sign-preserving zero. a. d = a / b.f32 implements a relatively fast. For PTX ISA versions 1.full. approximate single-precision divides: div.f32 defaults to div.f32 flushes subnormal inputs and results to sign-preserving zero. a. sm_1x: div. 2126]. Fast. For PTX ISA version 1.4 and later. or . d. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .rn. the maximum ulp error is 2.rn.f64. one of . subnormal numbers are supported.full. Description Semantics Notes Divides a by b.f32 and div.

f64 requires sm_13 or later. d. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. subnormal numbers are supported. abs.f64 d.ftz. neg{. abs.f64 supports subnormal numbers.f32 supported on all target architectures.0. sm_1x: abs. neg.Chapter 8. abs. neg. Negate the sign of a and store the result in d. Subnormal numbers: sm_20: By default. Instruction Set Table 55. NaN inputs yield an unspecified NaN.f32 neg.f64 requires sm_13 or later. sm_1x: neg.ftz}. Subnormal numbers: sm_20: By default. Take the absolute value of a and store the result in d. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.ftz. Table 56.f64 supports subnormal numbers. a. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f0. neg. d = |a|.f64 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero. abs.f0. a. a. a.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero.f32 x. d = -a. abs{.f32 supported on all target architectures.ftz.ftz. January 24.f32 abs. NaN inputs yield an unspecified NaN. subnormal numbers are supported. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 91 . neg. abs. neg.ftz}.0.f32 flushes subnormal inputs and results to sign-preserving zero. d.f32 flushes subnormal inputs and results to sign-preserving zero.

c.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 d. subnormal numbers are supported. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. sm_1x: max. a.f64 f0.0 Table 57.ftz. (a > b) ? a : b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 requires sm_13 or later. (a < b) ? a : b.ftz.f1.f64 requires sm_13 or later.z.b. a. max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b. b.f32 min. max. a. 2010 .f64 d. max.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. d. d d d d = = = = NaN. min.f32 supported on all target architectures.f32 min.f64 z. a. max{.f32 max. @p min. subnormal numbers are supported. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. min.PTX ISA Version 2. a. min.x.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. b. max.c. min{. a. Table 58. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f32 max.f64 supports subnormal numbers. sm_1x: min. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.ftz. a.0.f2. d. b.f32 supported on all target architectures. b.0.ftz}. 92 January 24. d d d d = = = = NaN. Store the maximum of a and b in d. a. min. max. Store the minimum of a and b in d.f32 flushes subnormal inputs and results to sign-preserving zero.

rnd = { .0 -Inf -Inf +Inf +Inf +0.rn.rz. rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . For PTX ISA versions 1. rcp. rcp.f32 defaults to rcp. . rcp.approx{.4 and later.f64 d.f64.0. .f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero.f32 rcp.rp }.rnd{.ftz.rn mantissa LSB rounds to nearest even .rnd.{rz.f32 requires sm_20 or later.f64 supports subnormal numbers.approx. Input -Inf -subnormal -0.f64 requires sm_13 or later.ftz.4. a. d = 1 / a. one of .Chapter 8. rcp.f32 flushes subnormal inputs and results to sign-preserving zero.rn.f64 and explicit modifiers .f32 and rcp. Target ISA Notes rcp. and rcp. d.rz mantissa LSB rounds towards zero .f32 implements a fast approximation to reciprocal.f32 rcp.ftz}. rcp.approx and . General rounding modifiers were added in PTX ISA version 2. Examples January 24.r.f32 rcp.0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}.rn. For PTX ISA version 1. d.rnd.f32 rcp.0. . xi. 2010 93 .0-2. sm_1x: rcp.ftz were introduced in PTX ISA version 1. rcp.rm mantissa LSB rounds towards negative infinity . PTX ISA Notes rcp.f64 introduced in PTX ISA version 1.0 through 1.ftz.approx.rm.rnd is required. a. a.ftz.0 +subnormal +Inf NaN Result -0. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. subnormal numbers are supported.f64 requires sm_20 or later.rm.rp}.x. Instruction Set Table 59.x. rcp.approx or . rcp.rn.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . The maximum absolute error is 2-23.approx. Description Semantics Notes Compute 1/a. store result in d.0 +0. rcp. // fast.f32.rn.rn.3. xi.f64 ri.0 over the range 1.f64 defaults to rcp.approx.

sqrt. General rounding modifiers were added in PTX ISA version 2.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rnd is required.rz.PTX ISA Version 2.f32 sqrt.f32 requires sm_20 or later.0 +0.f64 and explicit modifiers . .rn. // IEEE 754 compliant rounding d. sqrt.f32. sqrt.3. 2010 .f64 d.f64 defaults to sqrt.approx.ftz.f32 defaults to sqrt. r.0 +subnormal +Inf NaN Result NaN NaN -0.rp}. sqrt. .f64 r.f32 implements a fast approximation to square root. The maximum absolute error for sqrt.rz mantissa LSB rounds towards zero .f64 requires sm_20 or later.f32 is TBD. a. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.approx.ftz}.approx and .ftz.f64 supports subnormal numbers. one of .f32 sqrt. sqrt. . Examples 94 January 24.rnd. sqrt.0.0 +0.approx{. a. subnormal numbers are supported. sqrt.approx.x.ftz.rm.x. approximate square root d. For PTX ISA version 1. Target ISA Notes sqrt.rm.rm mantissa LSB rounds towards negative infinity .rp }.rnd{. // fast. Input -Inf -normal -subnormal -0. sqrt.0 through 1.approx or .f32 supported on all target architectures.rn mantissa LSB rounds to nearest even .rnd.f64 requires sm_13 or later. // IEEE 754 compliant rounding .rn.rn.0 Table 60.rnd = { .approx. sm_1x: sqrt. and sqrt.ftz}.approx.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.rn.x.ftz.0 +0.{rz.4 and later. sqrt.0 -0. r. For PTX ISA versions 1.f32 flushes subnormal inputs and results to sign-preserving zero.ftz were introduced in PTX ISA version 1.4. store in d. PTX ISA Notes sqrt.0.f64 introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.rn. sqrt. Description Semantics Notes Compute sqrt(a).f32 sqrt.f64.f32 sqrt.f32 and sqrt. a. d = sqrt(a).

f64 isr.approx modifier is required. a.Chapter 8.f64 is emulated in software and are relatively slow.f64 d. the .f32.0.approx and . Explicit modifiers .approx. and rsqrt.f32 supported on all target architectures.0 NaN The maximum absolute error for rsqrt. Compute 1/sqrt(a).ftz.ftz.ftz were introduced in PTX ISA version 1. rsqrt.approx{.3. January 24. rsqrt.4 and later.approx.f32 rsqrt.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero. X.f64 requires sm_13 or later.f32 defaults to rsqrt. 2010 95 . rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. rsqrt.ftz}. Subnormal numbers: sm_20: By default. Note that rsqrt.0-4.f32 rsqrt. For PTX ISA version 1.f64 is TBD.f64 were introduced in PTX ISA version 1. a. The maximum absolute error for rsqrt. Target ISA Notes Examples rsqrt.approx. sm_1x: rsqrt. d = 1/sqrt(a).4 over the range 1.f64.approx. Instruction Set Table 61. PTX ISA Notes rsqrt. subnormal numbers are supported.approx.f32 is 2-22. d.0 +0. rsqrt. store the result in d. rsqrt. ISR. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f64 defaults to rsqrt.ftz.f64 supports subnormal numbers. x. rsqrt.4. For PTX ISA versions 1.0.approx implements an approximation to the reciprocal square root.f32 and rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. Input -Inf -normal -subnormal -0.approx.

approx and . the .f32 flushes subnormal inputs and results to sign-preserving zero.4 and later.ftz}.0 NaN NaN The maximum absolute error is 2-20. 2010 .0 +0.9 in quadrant 00. For PTX ISA version 1.0.ftz introduced in PTX ISA version 1.f32 d.4. sm_1x: Subnormal inputs and results to sign-preserving zero.0 Table 62.approx{.0 through 1.approx.f32 sa. d = sin(a). subnormal numbers are supported. Target ISA Notes Examples Supported on all target architectures.approx modifier is required.f32 introduced in PTX ISA version 1. sin.3.ftz. PTX ISA Notes sin. For PTX ISA versions 1. sin.f32 defaults to sin. sin.approx.0 +subnormal +Inf NaN Result NaN -0. Explicit modifiers .approx.PTX ISA Version 2.0 +0. Find the sine of the angle a (in radians).ftz. a.0 +0.f32 implements a fast approximation to sine. sin.f32. Subnormal numbers: sm_20: By default. 96 January 24.0 -0. a. Input -Inf -subnormal -0. sin.ftz. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.

Instruction Set Table 63.0 +1. PTX ISA Notes cos. a.ftz. cos. Input -Inf -subnormal -0. For PTX ISA versions 1. cos. a.4 and later.0.0 +0.ftz introduced in PTX ISA version 1. cos. subnormal numbers are supported. sm_1x: Subnormal inputs and results to sign-preserving zero.9 in quadrant 00. d = cos(a). 2010 97 .approx{. Target ISA Notes Examples Supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. the .approx modifier is required.f32 defaults to cos. Find the cosine of the angle a (in radians).f32. For PTX ISA version 1.approx.0 NaN NaN The maximum absolute error is 2-20.approx and . Explicit modifiers .ftz.f32 d.ftz. cos.0 +1.ftz}.4. cos.approx.0 +1.0 through 1.3. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. January 24.f32 introduced in PTX ISA version 1.0 +subnormal +Inf NaN Result NaN +1. Subnormal numbers: sm_20: By default.approx.f32 implements a fast approximation to cosine.f32 ca.Chapter 8.

lg2.f32 implements a fast approximation to log2(a). lg2.0.0 Table 64. d = log(a) / log(2). 2010 .f32 la.approx.ftz. 98 January 24. Explicit modifiers . lg2. lg2.4 and later. the .f32 flushes subnormal inputs and results to sign-preserving zero. a. For PTX ISA version 1. a. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz introduced in PTX ISA version 1.f32 Determine the log2 of a.6 for mantissa.f32 defaults to lg2.approx. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. The maximum absolute error is 2-22.ftz.3. subnormal numbers are supported. Target ISA Notes Examples Supported on all target architectures.approx{.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.0 +0. Input -Inf -subnormal -0. lg2. Subnormal numbers: sm_20: By default.ftz.f32 introduced in PTX ISA version 1. For PTX ISA versions 1.approx and .f32.4.approx modifier is required.ftz}.PTX ISA Version 2.approx.0 through 1. PTX ISA Notes lg2.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

u16. {!}c. ne.u64. lt. respectively. 2010 . The comparison operator is a suffix on the instruction.dtype.b16. To aid comparison operations in the presence of NaN values. .b64. ltu. sm_1x: setp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.and. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.f32 flushes subnormal inputs to sign-preserving zero.BoolOp{. If either operand is NaN.type = { .s64. then the result of these comparisons is true. b.f32 comparisons. a.s32. A related value computed using the complement of the compare result is written to the second destination operand. geu.pred variables. gt. ge. hs equ.0 Table 67. num returns true if both operands are numeric values (not NaN).r. hi.PTX ISA Version 2.b32. subnormal numbers are supported.i. leu.eq. le.0. le. ne. .type . .f32.s16.ftz. ge. If both operands are numeric values (not NaN). neu.type setp. ne. lt. gtu. c). le.CmpOp{.f64 supports subnormal numbers. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. neu.B) is one of: and. c).u32 p|q. gt.ftz}. lo. leu. . The destinations p and q must be . @q setp. The untyped. num. Modifier . p = BoolOp(t.CmpOp.n. Applies to all numeric types. setp. ls.s32 setp.ftz}.a. or. the comparison operators lo. The signed and unsigned comparison operators are eq. p. then these comparisons have the same result as their ordered counterparts. . a. . setp. b.dtype. unordered versions are included: equ.lt. setp with .dtype. p[|q]. and hs for lower.f64 }. p[|q]. and can be one of: eq. Semantics t = (a CmpOp b) ? 1 : 0. q = BoolOp(!t. 102 January 24. xor. This result is written to the first destination operand. . setp.b. bit-size comparisons are eq and ne. geu. For unsigned values. Integer Notes Floating Point Notes The ordered comparisons are eq. higher. ge. Subnormal numbers: sm_20: By default. ltu. le. nan The Boolean operator BoolOp(A. ls.f32 flushes subnormal inputs to sign-preserving zero. ge. gt. lt.ftz applies only to . . loweror-same. and nan returns true if either operand is NaN.u32. and higher-or-same may be used instead of lt. hi. and (optionally) combine this result with a predicate value by applying a Boolean operator. gtu. . . If either operand is NaN. gt.f64 source type requires sm_13 or later. the result is false.

s64. . If c ≥ 0.s32 slct{. . .p.f64 }. 2010 103 .u64. and operand a is selected.u32. c.0.xp.dtype.b64. subnormal numbers are supported.f32 r0. and b must be of the same type. otherwise b is stored in d. d = (c == 1) ? a : b.ftz}. a. a.f32. fval. selp Syntax Comparison and Selection Instructions: selp Select between source operands. selp.s16. . For . a. slct.Chapter 8.s32.f32 d.dtype = { . Description Conditional selection. sm_1x: slct.u32. The selected input is copied to the output without modification.f32 flushes subnormal values of operand c to sign-preserving zero. Operand c is a predicate.b16.b16. .s64.dtype. If operand c is NaN. and operand a is selected.u64.f32 A.f32 flushes subnormal values of operand c to sign-preserving zero. Operands d. c.f32 comparisons. . Modifier . . operand c must match the second instruction type. Introduced in PTX ISA version 1.f32 comparisons. . Operands d.dtype. a is stored in d.ftz applies only to .s32. Semantics Floating Point Notes January 24.f32. the comparison is unordered and operand b is selected. .b32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later.b64. a.g. slct.ftz. slct. . If c is True. b otherwise.ftz.type = { .dtype.u16.u64. b. .s32 selp. . . Subnormal numbers: sm_20: By default. based on the value of the predicate source operand. b. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. f0. .f64 }. C. b.f64 requires sm_13 or later. Table 69. . y. . negative zero equals zero.x. a. . . based on the sign of the third operand. Instruction Set Table 68. . selp.t. z. . a is stored in d. c.r. @q selp.type d. . B. d = (c >= 0) ? a : b. d.b32.u32. slct Syntax Comparison and Selection Instructions: slct Select one source operand.0.s16.u16. and b are treated as a bitsize type of the same width as the first instruction type. slct. slct. .s32 x. val.

or. This permits bit-wise operations on floating point values without having to define a union to access the bits. performing bit-wise operations on operands of any type.4. xor. provided the operands are of the same size. 2010 .0 8. Instructions and. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. and not also operate on predicates.7.PTX ISA Version 2. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.

.0x00010001 or.pred p.type d.0x80000000.q. b.b32 mask mask. and.b32 x.b16. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. . 2010 105 . a. . .type d. . . or Syntax Logic and Shift Instructions: or Bitwise OR.b64 }.r. or. Table 71.b32. b. . Introduced in PTX ISA version 1. d = a & b.0. sign. and.q. The size of the operands must match.pred. Introduced in PTX ISA version 1.b64 }. but not necessarily the type. The size of the operands must match.0. but not necessarily the type. d = a | b. Supported on all target architectures. Supported on all target architectures.Chapter 8. a.type = { . or. .b32.r. and Syntax Logic and Shift Instructions: and Bitwise AND.b16. Instruction Set Table 70.type = { .pred.fpvalue.b32 and. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. January 24. Allowed types include predicate registers.

b32. .b32.b32 mask. . but not necessarily the type.b16. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. a.b32 xor. Supported on all target architectures. d = (a==0) ? 1 : 0. Supported on all target architectures.a. b. .q.b16 d. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). d = a ^ b. not.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. cnot. The size of the operands must match. The size of the operands must match. .b16.pred.type = { . xor.0. 106 January 24. Introduced in PTX ISA version 1. a. not.0.pred p. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.0x0001. Allowed types include predicate registers. Table 73. but not necessarily the type. .q. xor.type = { .r. but not necessarily the type. Table 74. .0. . .PTX ISA Version 2. Introduced in PTX ISA version 1. not. d. Allowed types include predicates.type d. a.b16. 2010 . . not Syntax Logic and Shift Instructions: not Bitwise negation. one’s complement.b32.pred. The size of the operands must match.b64 }.b32 d. cnot. Supported on all target architectures.type = { . Introduced in PTX ISA version 1.b64 }.type d. .0 Table 72. d = ~a.x.mask.type d. .

s64 }.s32.s32 shr. Instruction Set Table 75. sign or zero fill on left. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Shift amounts greater than the register width N are clamped to N.2. The b operand must be a 32-bit value.b64.b32 q. . d = a >> b. Signed shifts fill with the sign bit. . Bit-size types are included for symmetry with SHL.u16. .2. Supported on all target architectures.i. a.b16 c. b.u32.b16. The sizes of the destination and first source operand must match. . Supported on all target architectures. but not necessarily the type. PTX ISA Notes Target ISA Notes Examples Table 76.a. 2010 107 .u16 shr. . shr. Introduced in PTX ISA version 1.b32. Shift amounts greater than the register width N are clamped to N.1.a. shr.s16.u64. . a. shr Syntax Logic and Shift Instructions: shr Shift bits right.type = { . regardless of the instruction type.type = { .0.type d. d = a << b. The sizes of the destination and first source operand must match. regardless of the instruction type. k. . shl. shl Syntax Logic and Shift Instructions: shl Shift bits left. but not necessarily the type.b64 }.j.Chapter 8. PTX ISA Notes Target ISA Notes Examples January 24. . Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.i. shl. zero-fill on right. . . b. . i.b32.type d. unsigned and untyped shifts fill with 0.b16. Introduced in PTX ISA version 1.0. . The b operand must be a 32-bit value.

ld. Instructions ld. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. Data Movement and Conversion Instructions These instructions copy data from place to place.7. local. and from state space to state space. suld. and sust support optional cache operations. st. prefetchu isspacep cvta cvt 108 January 24. ldu. The cvta instruction converts addresses between generic and global. and st operate on both scalar and vector types. possibly converting it from one format to another. 2010 .5. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.PTX ISA Version 2.0 8. mov. or shared state spaces.

cv to a frame buffer DRAM address is the same as ld.1. evict-first.7. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. to allow the thread program to poll a SysMem location written by the CPU. Table 77.Chapter 8. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cg to cache loads only globally.ca loads cached in L1.cv Cache as volatile (consider cached system memory lines stale.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. The ld.5. Operator . 2010 109 . Use ld. The compiler / programmer may use ld.lu Last use. and cache only in the L2 cache.0 introduces optional cache operators on load and store instructions.cs) on global addresses. rather than the data stored by the first thread.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The cache operators require a target architecture of sm_20 or later.cs is applied to a Local window address.cs. .lu load last use operation. The ld. . When ld. Cache Operators PTX 2. If one thread stores to global memory via one L1 cache. likely to be accessed again. . bypassing the L1 cache. the second thread may get stale L1 cache data. fetch again). any existing cache lines that match the requested address in L1 will be evicted. The ld. it performs the ld. The default load instruction cache operation is ld. if the line is fully covered. and a second thread loads that address via a second L1 cache with ld.lu operation. . January 24.lu instruction performs a load cached streaming operation (ld. Global data is coherent at the L2 level. but multiple L1 caches are not coherent for global data.ca. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.ca.cg Cache at global level (cache in L2 and below. Instruction Set 8. invalidates (discards) the local L1 line following the load. the cache operators have the following definitions and behavior. A ld. not L1). likely to be accessed once. when applied to a local address.cs Cache streaming. The ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. As a result of this request. For sm_20 and later.

st. . . If one thread stores to global memory.wb for global data. and discard any L1 lines that match.cg Cache at global level (cache in L2 and below.ca. Operator . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.cg to cache global store data only globally. and cache only in the L2 cache. bypassing its L1 cache. In sm_20.ca loads. likely to be accessed once. and a second thread in a different SM later loads from that address via a different L1 cache with ld. rather than get the data from L2 or memory stored by the first thread. Use st. The st.cg is the same as st. Future GPUs may have globally-coherent L1 caches.wb. in which case st. to allow a CPU program to poll a SysMem location written by the GPU with st.wb could write-back global store data from L1. but st. the second thread may get a hit on stale L1 cache data. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.PTX ISA Version 2.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Global stores bypass L1. The st.cs Cache streaming. which writes back cache lines of coherent cache levels with normal eviction policy.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. However. 2010 . Addresses not in System Memory use normal write-back. and marks local L1 lines evict-first. The default store instruction cache operation is st. .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cg to local memory uses the L1 cache.0 Table 78. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. regardless of the cache operation. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wt Cache write-through (to system memory).wt. not L1). bypassing the L1 cache. 110 January 24.

e. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.f64 }. . the generic address of a variable declared in global. the parameter will be copied onto the stack and the address will be in the local state space. avar.s64. . d. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.u64. For variables declared in .f64 requires sm_13 or later. The generic address of a variable in global. within the variable’s declared state space Notes Although only predicate and bit-size types are required.Chapter 8. Description . immediate. Write register d with the value of a.u32 mov. Introduced in PTX ISA version 1. mov. special register.a. .1.e.type = { . // get address of variable // get address of label or function . or shared state space may be taken directly using the cvta instruction.shared state spaces. mov. A[5].const.u32.type mov. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. . Instruction Set Table 79.u16. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. d = sreg. . local. u. Semantics d = a. .f32 mov.pred. Take the non-generic address of a variable in global.0.. i.b16. . label. 2010 111 .type mov. the address of the variable in its state space) into the destination register.type d.s16. Note that if the address of a device function parameter is moved to a register. d = &label. a. or shared state space. local. d. local. myFunc.b32. d. Operand a may be a register.u16 mov.s32. . // address is non-generic.type mov. . .v.f32. k. alternately. mov places the non-generic address of the variable (i. . mov.local. d = &avar. and .global. or function name. .0.b64.u32 mov. A.f32 mov.. variable in an addressable memory space. label.u32 d. ptr. addr. sreg. ptr.

..b.b64 mov.y << 16) | (a.23].y. a[16. .b64 112 January 24.x | (a.x. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.z << 16) | (a.b8 r. .b.0 Table 80....b16.y } = { a[0.. a[32. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. a[24. d. Semantics d = a. Description Write scalar register d with the packed value of vector register a.b32 // pack four 16-bit elements into .y } = { a[0.y << 8) | (a.7]. Supported on all target architectures.b64 { d. a[8.y << 8) d = a.b32 { d.a}.hi}..w have type .0. 2010 .b64 { d.w}.b16 { d. a[8. a[48.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.31] } // unpack 8-bit elements from .x | (a.31].a have type .b32 mov. a[32.b32 { d. %x.63] } // unpack 16-bit elements from .y } = { a[0.7].w } = { a[0.b have type .x | (a.g.b32 %r1.. {lo.x. a.b64 }.b32 mov.15].31].x. mov.w } = { a[0.x.type d.. .y << 32) // pack two 8-bit elements into .b16 // pack four 8-bit elements into . a[16.15]. d.z.{a. {r.31] } // unpack 16-bit elements from ..b32 // pack two 16-bit elements into .u32 x.z << 32) | (a. a[16.y.PTX ISA Version 2.w << 24) d = a. // // // // a.u8 // unpack 32-bit elements from . d. d.w << 48) d = a.b64 // pack two 32-bit elements into . d.z.y << 16) d = a.%r1.type = { .15].x | (a. d.15] } // unpack 8-bit elements from .hi are .x.z.z.b}. or write vector register d with the unpacked values from scalar register a.. d. d.. %r1.{x. For bit-size types.. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b32. d. lo..u16 %x is a double. mov.y.x | (a.g.47].y.

The value loaded is sign-extended to the destination register width for signed integers. or [immAddr] an immediate absolute byte address (unsigned. . . . .0.f32 or . the access may proceed by silently masking off low-order address bits to achieve proper rounding.ss = { . and truncated if the register width exceeds the state space address width for the target architecture.ss}. [a].global.volatile.s16. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Description Load register variable d from the location specified by the source address operand a in specified state space.vec.f16 data may be loaded using ld. . an address maps to global memory unless it falls within the local memory window or the shared memory window. and is zeroextended to the destination register width for unsigned and bit-size types. . PTX ISA Notes January 24.cop = { . . *(a+immOff).shared }. *a.cs. The .Chapter 8. for example. Addresses are zero-extended to the specified width as needed. Within these windows. to enforce sequential consistency between threads accessing shared memory. . . 32-bit).f64 using cvt.s64. .0. ld.type ld. d.lu.ca. . Instruction Set Table 81.global and .volatile may be used with . 2010 113 .s32. . . In generic addressing. . [a]. Generic addressing may be used with ld. Generic addressing and cache operations introduced in PTX ISA 2.cg.volatile{.type ld{. the resulting behavior is undefined.type d.type = { . [a].b64.volatile. 32-bit).u16. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .b32. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. If no state space is given.type . d. The address must be naturally aligned to a multiple of the access size.vec = { .cop}.b8.b16. i. .volatile introduced in PTX ISA version 1.b16. d.f32. and then converted to . i.e.u32.const space suffix may have an optional bank number to indicate constant banks other than bank zero. . Cache operations are not permitted with ld.ss}{. ld introduced in PTX ISA version 1.ss}{. *(immAddr). . [a]. This may be used.const. . ld{.shared spaces to inhibit optimization of references to volatile memory.volatile{.u8.vec.local.1. If an address is not properly aligned.ss}. .f64 }.param. . an address maps to the corresponding location in local or shared memory.v4 }. an integer or bit-size type register reg containing a byte address. . The address size may be either 32-bit or 64-bit. .s8.reg state space. ld. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.cv }. A destination register wider than the specified type may be used. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .cop}.v2. Semantics d d d d = = = = a.u64. perform the load using generic addressing..e. or the instruction may fault.

local.f32 ld.const[4].[p+4]. ld.PTX ISA Version 2.f64 requires sm_13 or later.global.local. %r.[buffer+64]. 2010 . Q.f16 d. // access incomplete array x.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[p+-8].b16 cvt.b32 ld. // load .b64 ld.const.b32 ld.s32 ld. x.f32. Generic addressing requires sm_20 or later.b32 ld. d.%r. // immediate address %r.0 Target ISA Notes ld.[p].v4.[240]. Cache operations require sm_20 or later.[a].[fs]. // negative offset %r.shared.global.

. *(immAddr).e.[p+4].ss = { . The data at the specified address must be read-only. [a]. ldu.b16. 2010 115 .f64 requires sm_13 or later. ldu.[a].global.type d. . d.global }. . an address maps to global memory unless it falls within the local memory window or the shared memory window. .type ldu{.u32.v4 }.f64 }.b16. Introduced in PTX ISA version 2.s64.ss}. i. the resulting behavior is undefined. PTX ISA Notes Target ISA Notes Examples January 24.[p].u16. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.f32 Q.0.global. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. 32-bit).e.global.u8.reg state space. . . The address size may be either 32-bit or 64-bit. A destination register wider than the specified type may be used. ldu. ldu. .ss}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . .s8.f64 using cvt. The value loaded is sign-extended to the destination register width for signed integers.s16. A register containing an address may be declared as a bit-size type or integer type. Addresses are zero-extended to the specified width as needed. If an address is not properly aligned. ldu{. only generic addresses that map to global memory are legal. *a. Instruction Set Table 82. . or the instruction may fault. The address must be naturally aligned to a multiple of the access size. Within these windows. // load from address // vec load from address . // state space . 32-bit).f16 data may be loaded using ldu. . . an address maps to the corresponding location in local or shared memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding. perform the load using generic addressing.Chapter 8.f32 or .v4.f32. i. .vec. [areg] a register reg containing a byte address.b32.b32 d.b64. Semantics d d d d = = = = a. If no state space is given. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. [a].s32.f32 d.. and then converted to . .vec = { . . For ldu.type = { . *(a+immOff).b8. and is zeroextended to the destination register width for unsigned and bit-size types.u64. or [immAddr] an immediate absolute byte address (unsigned.v2. In generic addressing. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . and truncated if the register width exceeds the state space address width for the target architecture. where the address is guaranteed to be the same across all threads in the warp. The addressable operand a is one of: [avar] the name of an addressable variable var.

. A source register wider than the specified type may be used. b.e.volatile.vec . or [immAddr] an immediate absolute byte address (unsigned. The lower n bits corresponding to the instruction-type width are stored to memory.ss . .u8.volatile{. 2010 . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. the access may proceed by silently masking off low-order address bits to achieve proper rounding.type [a]. [a].shared }. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. an integer or bit-size type register reg containing a byte address. st.0 Table 83. Semantics d = a. to enforce sequential consistency between threads accessing shared memory. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . an address maps to global memory unless it falls within the local memory window or the shared memory window.global.v2. . b.u32.volatile. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. b. perform the store using generic addressing.. The address must be naturally aligned to a multiple of the access size.local. . .ss}. . and truncated if the register width exceeds the state space address width for the target architecture. 32-bit).f64 }.f32. *(d+immOffset) = a. . *d = a.vec.f16 data resulting from a cvt instruction may be stored using st. or the instruction may fault. b. In generic addressing.ss}{.reg state space.f64 requires sm_13 or later.ss}. st.u16. . . st introduced in PTX ISA version 1.v4 }.1. Generic addressing may be used with st.type st.s64.0.PTX ISA Version 2.s8. .wt }. .b16. *(immAddr) = a. st{. Within these windows. Generic addressing and cache operations introduced in PTX ISA 2.cop}. st. . 32-bit). [a].volatile introduced in PTX ISA version 1.shared spaces to inhibit optimization of references to volatile memory.wb.b8. .type . . The address size may be either 32-bit or 64-bit. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.e.cg.cop . .b32. the resulting behavior is undefined. Generic addressing requires sm_20 or later. .s32. . . Cache operations are not permitted with st. an address maps to the corresponding location in local or shared memory.b16.b64. If an address is not properly aligned.s16. Addresses are zero-extended to the specified width as needed. i. { .cop}. i. Cache operations require sm_20 or later. { . { . .0.cs.volatile{.volatile may be used with . for example.vec.type = = = = {.ss}{.global and . The addressable operand a is one of: [var] [reg] the name of an addressable variable var. .type st{. This may be used. PTX ISA Notes Target ISA Notes 116 January 24. [a]. If no state space is given.u64. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.

%r.global.a.Chapter 8.f16. [p].b.%r.b16 [a].a.Q. Instruction Set Examples st. [q+4].f32 st.f32 st.v4.local. [fs].local. // %r is 32-bit register // store lower 16 bits January 24.local. 2010 117 . [q+-8].b32 st.s32 st.b32 st.global.s32 cvt.r7. // immediate address %r. // negative offset [100].

L2 }. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. the prefetch uses generic addressing. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. an address maps to global memory unless it falls within the local memory window or the shared memory window. 2010 . . prefetch.0.L1 [addr]. 32-bit).level prefetchu.local }. an address maps to the corresponding location in local or shared memory.level = { . i.space}.space = { . prefetch{.e. and no operation occurs if the address maps to a local or shared memory location. If no state space is given. prefetch and prefetchu require sm_20 or later. In generic addressing. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. A prefetch into the uniform cache requires a generic address. and truncated if the register width exceeds the state space address width for the target architecture. [a]. // prefetch to data cache // prefetch to uniform cache . 118 January 24. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The address size may be either 32-bit or 64-bit. Addresses are zero-extended to the specified width as needed.L1. .0 Table 84. Within these windows.L1 [ptr].global.global. in specified state space. or [immAddr] an immediate absolute byte address (unsigned. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L1 [a]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetchu. . A prefetch to a shared memory location performs no operation. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 32-bit). a register reg containing a byte address.PTX ISA Version 2.

global.u32.size cvta. or shared state space.genptr. p. isshrd. When converting a generic address into a global. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. the generic address of the variable may be taken using cvta. The source address operand must be a register of type . or shared address to a generic address. or vice-versa. Take the generic address of a variable declared in global. Description Convert a global. // get generic address of svar cvta.space.u32 or .space p. // local.u64. local.shared isglbl. . cvta. a. The destination register must be of type . local.local.space.pred .global.Chapter 8.to.size p.shared.u32 p. local.space. Introduced in PTX ISA version 2.global.local isspacep. isspacep. or vice-versa. lptr.u64.u32. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. For variables declared in global. var. isspacep requires sm_20 or later. islcl.size = { .0. or shared address cvta. local. Instruction Set Table 85. isspacep.global isspacep. The source and destination addresses must be the same size. or shared state space to generic. a. // convert to generic address // get generic address of var // convert generic address to global. local. svar. cvta requires sm_20 or later. . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.u32 gptr. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.space = { .shared }.local. or shared state space. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.0.u64 or cvt.shared }. . 2010 119 . PTX ISA Notes Target ISA Notes Examples Table 86. .lptr. gptr.size . a. cvta. // result is . A program may use isspacep to guard against such incorrect behavior.pred.u32 p.u64 }. January 24. or shared address. .u32 to truncate or zero-extend addresses.to. Use cvt.space = { .local. p. . cvta. sptr.

120 January 24.frnd}{.ftz.s64. . Saturation modifier: . .4 and earlier.dtype.dtype.sat}.PTX ISA Version 2. .rmi. sm_1x: For cvt.f32 float-tofloat conversions with integer rounding. .s8.f32. the result is clamped to the destination range by default.sat limits the result to MININT.sat}. Integer rounding modifiers: . Integer rounding is illegal in all other instances. i. .rpi }.rp }. The optional .f32..e.s16.MAXINT for the size of the operation.f64 }.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.u32. . .dtype. The compiler will preserve this behavior for legacy PTX code. . // integer rounding // fp rounding .sat is redundant.f32 float-to-integer conversions and cvt.rni. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. . the .rni round to nearest integer.ftz.ftz}{.rmi round to nearest integer in direction of negative infinity . and for same-size float-tofloat conversions where the value is rounded to an integer.f32.s32.atype = { . . .u8. For cvt.ftz. subnormal inputs are flushed to signpreserving zero. .ftz modifier may be specified in these cases for clarity. choosing even integer if source is equidistant between two integers.sat For integer destination types. .u16. subnormal numbers are supported. . . Description Semantics Integer Notes Convert between different types and sizes.rm.atype d.irnd}{. subnormal inputs are flushed to signpreserving zero.f32 float-to-integer conversions and cvt. .dtype..0 Table 87. d = convert(a).u64.rzi. cvt{.ftz}{. d. For float-to-integer conversions. Note that saturation applies to both signed and unsigned integer types.ftz.irnd = { . a. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32 float-tofloat conversions with integer rounding. . . 2010 . Note: In PTX ISA versions 1.rz.dtype = .atype cvt{. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. .rn.rzi round to nearest integer in the direction of zero . i.f16. .frnd = { .e. . Integer rounding is required for float-to-integer conversions.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. a.

0.r. // float-to-int saturates by default cvt. 2010 121 . // note .f64. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.0].f32.f64 j.rni.f16.f64 types. Applies to .ftz modifier may be specified in these cases for clarity.f32 instructions. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. The operands must be of the same size. NaN results are flushed to positive zero.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later. Subnormal numbers: sm_20: By default.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32.f32.0. The compiler will preserve this behavior for legacy PTX code. result is fp cvt. Introduced in PTX ISA version 1. Specifically. Note: In PTX ISA versions 1. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.sat limits the result to the range [0.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).4 or earlier.ftz behavior for sm_1x targets January 24.i. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f32. Floating-point rounding is illegal in all other instances. cvt.f32. The optional . // round to nearest int. Modifier . The result is an integral value. Saturation modifier: .rz mantissa LSB rounds towards zero .s32. cvt to or from .version is 1. and cvt.y. cvt.f16.rn mantissa LSB rounds to nearest even .f32 x. stored in floating-point format. .sat For floating-point destination types. . if the PTX . subnormal numbers are supported.f32.f32 x. Floating-point rounding modifiers: . 1.4 and earlier. and . and for integer-to-float conversions.Chapter 8.f32.f16.y. cvt.s32 f.

the file is assumed to use unified mode. with the restriction that they correspond 1-to-1 with the 128 possible textures. } = clamp_to_border. sampler. texture and sampler information is accessed through a single . .PTX ISA Version 2.texref tex1 ) { txq. r5. r5. sampler.f32. add.2d. r3.samplerref tsamp1 = { addr_mode_0 filter_mode }. The texturing mode is selected using .r2. samplers.f32 r3. // get tex1’s tex.u32 r5. Texture and Surface Instructions This section describes PTX instructions for accessing textures. {f1. . 122 January 24. In the independent mode. and surface descriptors. In the unified mode. 2010 . allowing them to be defined separately and combined at the site of usage in the program. PTX has two modes of operation. The advantage of independent mode is that textures and samplers can be mixed and matched.f32 r1.7. Ability to query fields within texture. A PTX module may declare only one texturing mode. r5.u32 r5. cvt. mul.r4}. and surface descriptors.f32. If no texturing mode is declared. Texturing modes For working with textures and samplers. // get tex1’s txq.r3.b32 r6.target texmode_independent . r1. [tex1. add.param . Module-scope and per-entry scope definitions of texture. r2.global . PTX supports the following operations on texture. r6.. Example: calculate an element’s power contribution as element’s power/total number of elements. texture and sampler information each have their own handle.f32 r1. and surface descriptors. .target options ‘texmode_unified’ and ‘texmode_independent’.b32 r5. r1. r4. div. r3. add.6.texref handle. [tex1]. r1.f32 r1.entry compute_power ( . sampler. and surface descriptors: • • • Static initialization of texture.height. sampler. = nearest width height tsamp1.f32 {r1. [tex1]. but the number of samplers is greatly restricted to 16.f2}]..v4. and surfaces.width. The advantage of unified mode is that it allows 128 samplers.0 8.

tex. . Description Texture lookup using a texture coordinate vector. the resulting behavior is undefined. is a two-element vector for 2d textures.5.s32. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. c]. b.s32. the square brackets are not required and .r4}. . [a.0.f2. i. . d. or the instruction may fault.f3. A texture base address is assumed to be aligned to a 16-byte address. c]. Supported on all target architectures.r2.3d. .v4.3d }.. {f1.v4 coordinate vectors are allowed for any geometry. with the extra elements being ignored.f32 {r1.btype tex.v4. Notes For compatibility with prior versions of PTX.f32 }. Unified mode texturing introduced in PTX ISA version 1.1d. {f1}]. .dtype.v4.s32 {r1.btype = { . [a. PTX ISA Notes Target ISA Notes Examples January 24.f32 }. If an address is not properly aligned. the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom = { .2d. The instruction always returns a four-element vector of 32-bit values. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. If no sampler is specified. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. 2010 123 . sampler_x. Operand c is a scalar or singleton tuple for 1d textures.e.u32.f4}]. An optional texture sampler b may be specified.r4}.s32. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. where the fourth element is ignored.dtype = { .1d. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. . Instruction Set These instructions provide access to texture and surface memory. //Example of unified mode texturing tex.geom.Chapter 8.r3.geom.s32.r3.btype d. the sampler behavior is a property of the named texture. [tex_a. [tex_a.dtype. // explicit sampler .r2. // Example of independent mode texturing tex. and is a four-element vector for 3d textures. .v4. tex txq suld sust sured suq Table 88.

txq. txq.squery = { .filter_mode. Query: . mirror. // unified mode // independent mode 124 January 24. sampler attributes are also accessed via a texref argument.addr_mode_0 .width. [smpl_B].PTX ISA Version 2.normalized_coords }.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). txq. [tex_A]. clamp_to_edge. .squery. addr_mode_1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.height.depth.filter_mode. clamp_ogl.width .5. [a].height . [tex_A]. . .addr_mode_1 . .samplerref variable. In unified mode.normalized_coords .filter_mode .addr_mode_0.b32 txq.0 Table 89. Integer from enum { nearest. and in independent mode sampler attributes are accessed via a separate samplerref argument. [a].b32 %r1. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.b32 %r1. addr_mode_2 }. d. linear } Integer from enum { wrap. . Supported on all target architectures. Operand a is a . 2010 . txq.width.texref or .b32 %r1. Description Query an attribute of a texture or sampler. // texture attributes // sampler attributes .b32 d.tquery.addr_mode_0.depth .tquery = { .

s32 is returned. suld.dtype.clamp. . and the size of the data transfer matches the size of destination operand d.p . {x}]. Cache operations require sm_20 or later.geom{.trap clamping modifier. The lowest dimension coordinate represents a sample offset rather than a byte offset.trap . // unformatted d. . // formatted . suld.f32.p.b. and is a four-element vector for 3d surfaces. .f4}. . A surface base address is assumed to be aligned to a 16-byte address. or the instruction may fault.1d.b performs an unformatted load of binary data.clamp .p requires sm_20 or later. suld.dtype . i. suld. b]. If the destination type is . .b8 . If an address is not properly aligned.cop}. // for suld.cv }. or . .vec. or .clamp = = = = = = { { { { { { d. 2010 125 .3d requires sm_20 or later.b32.ca. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f32 is returned.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. If the destination base type is . Destination vector elements corresponding to components that do not appear in the surface format are not written.5..u32 is returned.e.geom{.z.1d.dtype .vec .surfref variable. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b32. [surf_A.v4.geom .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. .y.f32 based on the surface format as follows: If the surface format contains UNORM. // for suld.r2}. . Operand a is a .clamp field specifies how to handle out-of-bounds addresses: .b.p.v4. if the surface format contains SINT data. G. {x.trap {r1.p.s32.3d. // cache operation none.s32. .b16. .s32. then .v2. size and type conversion is performed as needed to convert from the surface sample format to the destination type.b . Instruction Set Table 90.cop .p is currently unimplemented. Description Load from surface memory using a surface coordinate vector. then .v4 }. b].b32. SNORM.0. Operand b is a scalar or singleton tuple for 1d surfaces. Coordinate elements are of type . suld.f3.2d.trap suld. .cs. is a two-element vector for 2d surfaces. and A components of the surface format.clamp . B.f32 }. .b supported on all target architectures.w}].3d }.u32. Target ISA Notes Examples January 24.clamp suld. additional clamp modifiers.cop}. The . or FLOAT data. . . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. the resulting behavior is undefined. . [a. {f1. .u32.dtype.v2. and cache operations introduced in PTX ISA version 2. sm_1x targets support only the . the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32. the surface sample elements are converted to .trap introduced in PTX ISA version 1.b. suld. suld. if the surface format contains UINT data.f2. . suld.zero }.s32. .trap.f32. . suld. then .b64 }. where the fourth element is ignored. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. [a. [surf_B.Chapter 8.cg.b64.

s32.b. Target ISA Notes Examples 126 January 24. 2010 .v4.trap.trap clamping modifier.r2}. b].zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. is a two-element vector for 2d surfaces. Coordinate elements are of type . then . The size of the data transfer matches the size of source operand c.PTX ISA Version 2.y. The .b // for sust. then .vec.u32.b8 .s32. If the source base type is .p.b32. .trap . if the surface format contains UINT data.wb.f32. // unformatted // formatted . . sust.cg.ctype .f2. .0.1d.0 Table 91.ctype . .ctype. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.cs.3d }. G. . where the fourth element is ignored.e. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. additional clamp modifiers.cop}.p. Cache operations require sm_20 or later. . and A surface components. sust.ctype. and cache operations introduced in PTX ISA version 2.p. {f1.f4}. SNORM.wt }.b32. Surface sample components that do not occur in the source vector will be written with an unpredictable value.w}].cop}.v4 }.b64.b supported on all target architectures. .vec.f32. . [surf_B. .geom{.clamp.s32.s32. {x.f32} are currently unimplemented. .geom . size and type conversions are performed as needed between the surface sample format and the destination type. .p requires sm_20 or later. [a. or the instruction may fault. sust. . .3d requires sm_20 or later. . .f32 }. If the source type is . These elements are written to the corresponding surface sample components. sust.f32 is assumed. and is a four-element vector for 3d surfaces.b16.b.b32.trap introduced in PTX ISA version 1.u32. sust. sust. if the surface format contains SINT data.3d.clamp . or FLOAT data. {r1.vec . The source data is then converted from this type to the surface sample format.1d.p. B.s32 is assumed. // for sust.clamp sust. If an address is not properly aligned.clamp field specifies how to handle out-of-bounds addresses: .z.p performs a formatted store of a vector of 32-bit data values to a surface sample.clamp . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. c. {x}]. . none.f3. sust Syntax Texture and Surface Instructions: sust Store to surface memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding. sm_1x targets support only the . sust.{u32. .b64 }.zero }.cop . sust. . b].geom{.b.. Operand b is a scalar or singleton tuple for 1d surfaces. The source vector elements are interpreted left-to-right as R.v2.clamp = = = = = = { { { { { { [a.u32 is assumed. i. . .surfref variable.p Description Store to surface memory using a surface coordinate vector.b performs an unformatted store of binary data.5. A surface base address is assumed to be aligned to a 16-byte address. Operand a is a .v2.2d. sust.trap sust. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Source elements that do not occur in the surface sample are ignored. the resulting behavior is undefined. The lowest dimension coordinate represents a sample offset rather than a byte offset. or . then . c.trap [surf_A.

ctype = { . .u32 and .op.clamp = { . .c. . and is a four-element vector for 3d surfaces.u64.add. .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.max. and the data is interpreted as .e. operations and and or apply to . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.s32 types.and.u32.u64.b32. 2010 127 .geom. A surface base address is assumed to be aligned to a 16-byte address.b .s32.b].clamp [a. .b32. min and max apply to . then . The . .2d. where the fourth element is ignored. // for sured.u64 data. Operand a is a .geom.c. then . .2d. i.s32 types. sured.trap [surf_A. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.min.Chapter 8.y}]. . the resulting behavior is undefined. r1.trap. {x}]. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. and .geom = { .s32. .ctype.u32.add. .clamp [a.u32.s32 is assumed.u32. is a two-element vector for 2d surfaces. sured.1d.or }.b performs an unformatted reduction on .b. .ctype = { . Instruction Set Table 92. .0. if the surface format contains SINT data.clamp.b32 type. [surf_B.clamp . .3d }.p.p .op = { .s32 or .b32 }. or .b32.trap . If an address is not properly aligned. // for sured. // sample addressing . Reduction to surface memory using a surface coordinate vector. .op. sured. Operand b is a scalar or singleton tuple for 1d surfaces. or the instruction may fault.u32 based on the surface sample format as follows: if the surface format contains UINT data.p performs a reduction on sample-addressed 32-bit data. .b32 }.b. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. {x.surfref variable.zero }. The instruction type is restricted to . The lowest dimension coordinate represents a sample offset rather than a byte offset. r1. // byte addressing sured.trap sured.ctype.. . Operations add applies to .clamp field specifies how to handle out-of-bounds addresses: .u32 is assumed. January 24. the access may proceed by silently masking off low-order address bits to achieve proper rounding. sured requires sm_20 or later.s32. Coordinate elements are of type .p. sured.b].min.1d.

query.height .query = { . Description Query an attribute of a surface. .width. Supported on all target architectures.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. 128 January 24. suq.depth }. Query: . [a].height. Operand a is a .0 Table 93. 2010 .width.PTX ISA Version 2. .b32 %r1.surfref variable.width . . suq. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.b32 d.5. [surf_A].

2010 129 . @{!}p instruction.7.y.s32 d. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.0.c. { instructionList } The curly braces create a group of instructions. } PTX ISA Notes Target ISA Notes Examples Table 95.f32 @!p div. Supported on all target architectures. Instruction Set 8.0. If {!}p then instruction Introduced in PTX ISA version 1. {} Syntax Description Control Flow Instructions: { } Instruction grouping.eq. Introduced in PTX ISA version 1.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. p. setp. used primarily for defining a function body. Supported on all target architectures.x.7. Execute an instruction or instruction block for threads that have the guard predicate true. { add.a.0. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. Threads with a false guard predicate do nothing. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.b.s32 a.f32 @q bra L23. ratio. mov.Chapter 8.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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the optional thread count must be a multiple of the warp size. {!}c. In addition to signaling its arrival at the barrier. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.arrive does not cause any waiting by the executing threads.popc).arrive using the same active barrier.Chapter 8.u32 bar.{arrive.red performs a predicate reduction across the threads participating in the barrier. The barrier instructions signal the arrival of the executing threads at the named barrier.or).or }. operands p and c are predicates.red} introduced in PTX . a{. d. b}. 2010 133 .arrive.red delays the executing threads (similar to bar.u32. Thus. Thus. Since barriers are executed on a per-warp basis. and then safely read values stored by other threads prior to the barrier.. and the barrier is reinitialized so that it can be immediately reused. bar.red should not be intermixed with bar.sync with an immediate barrier number is supported for sm_1x targets. Register operands. b. In conditionally executed code. b. bar. threads within a CTA that wish to communicate via memory can store to memory.and and .pred . b}.red. The result of .or indicate if all the threads had a true predicate or if any of the threads had a true predicate. a. bar. bar. All threads in the warp are stalled until the barrier completes.red instruction. Execution in this case is unpredictable.sync or bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. b}. When a barrier completes. January 24.sync) until the barrier count is met. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). the bar. all threads in the CTA participate in the barrier. The reduction operations for bar.0.sync bar. {!}c. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. Instruction Set Table 100.red are population-count (. Once the barrier count is reached.0. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). Each CTA instance has sixteen barriers numbered 0. Operands a. bar. the waiting threads are restarted without delay.red} require sm_20 or later. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. Operand b specifies the number of threads participating in the barrier.and).{arrive. the final value is written to the destination register in all threads waiting at the barrier.15. thread count. and bar.sync without a thread count introduced in PTX ISA 1.sync and bar. thread count. bar. Description Performs barrier synchronization and communication within a CTA. If no thread count is specified.red also guarantee memory ordering among threads identical to membar.sync and bar.op. and bar.and. all-threads-true (. Only bar.popc is the number of threads with a true predicate. execute a bar. it is as if all the threads in the warp have executed the bar instruction. it simply marks a thread's arrival at the barrier. bar.red performs a reduction operation across threads. PTX ISA Notes Target ISA Notes Examples bar. Note that a non-zero thread count is required for bar. bar. .red.popc. bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. while .arrive a{. p.op = { . if any thread in a warp executes a bar instruction. a{. Register operands.cta.version 2. and any-thread-true (. and d have type .sync or bar.sync 0.

membar. membar.gl will typically have a longer latency than membar.0.gl.cta. global. that is. this is the appropriate level of membar.gl} introduced in PTX .4. PTX ISA Notes Target ISA Notes Examples membar. membar. A memory write (e.PTX ISA Version 2.cta Waits until all prior memory writes are visible to other threads in the same CTA.sys introduced in PTX . membar.sys Waits until all prior memory requests have been performed with respect to all clients.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.gl} supported on all target architectures.level = { . . membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar.level. membar. 134 January 24.cta. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. For communication between threads in different CTAs or even different SMs. membar.sys will typically have much longer latency than membar.sys requires sm_20 or later. or system memory level.g.0 Table 101.sys }. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. Waits until prior memory reads have been performed with respect to other threads in the CTA. membar. 2010 . Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level.cta.sys.g. including thoses communicating via PCI-E such as system and peer-to-peer memory. membar. A memory read (e.gl. membar. by st.version 1.{cta.{cta. when the previous value can no longer be read. and memory reads by this thread can no longer be affected by other thread writes.version 2. . Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. level describes the scope of other clients for which membar is an ordering event. .gl.

perform the memory accesses using generic addressing.s32. e. The bit-size operations are and.dec. . . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. .op = { .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. overwriting the original value.add.s32. . min.exch. and max operations are single-precision. . by inserting barriers between normal stores and atomic operations to a common address. .space}. A register containing an address may be declared as a bit-size type or integer type. For atom. min. In generic addressing. . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. or the instruction may fault. The address must be naturally aligned to a multiple of the access size.s32. . January 24.add. 2010 135 . Within these windows. cas (compare-and-swap). .g. the resulting behavior is undefined. or. and exch (exchange).or. min. The inc and dec operations return a result in the range [0.u32.Chapter 8. .u64. dec.type = { .global.inc. Addresses are zero-extended to the specified width as needed. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. atom{. Instruction Set Table 102. 32-bit operations. max. b. The address size may be either 32-bit or 64-bit. c.cas. If an address is not properly aligned.f32 Atomically loads the original value at location a into destination register d. . . . . .b].u32. .type d. i. and max. an address maps to global memory unless it falls within the local memory window or the shared memory window. or [immAddr] an immediate absolute byte address. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. and truncated if the register width exceeds the state space address width for the target architecture. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ..and.e. inc.type atom{. a de-referenced register areg containing a byte address. Operand a specifies a location in the specified state space.space}.f32 }. or by using atom.b64.e.b32 only .b32. . xor.u32 only .op.b64 .max }. accesses to local memory are illegal. The floating-point add.shared }.exch to store to locations accessed by other atomic operations. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.space = { . The floating-point operations are add. atom.u32. [a]. . [a]. . i. an address maps to the corresponding location in local or shared memory. If no state space is given. d.b32. Description // // // // // . . b.xor. performs a reduction operation with operand b and the value in location a. .f32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.. .min. The integer operations are add.u64 .op. and stores the result of the specified operation at location a.

Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. 64-bit atom.0.max. *a = (operation == cas) ? : } where inc(r.{add.global. atom. : r.cas.[a]. d.global. Introduced in PTX ISA version 1.shared. d.shared requires sm_12 or later.f32 atom.f32.exch} requires sm_12 or later.add. : r+1.my_val.cas. : r-1.t) = (r == s) ? t operation(*a. b).{min. atom.s.shared operations require sm_20 or later.1.max} are unimplemented. Use of generic addressing requires sm_20 or later. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom. atom.add. s) = s. b.[p].b32 d.0 Semantics atomic { d = *a.my_new_val. cas(r.f32 requires sm_20 or later. 64-bit atom. c) operation(*a. s) = (r >= s) ? 0 dec(r.0. atom. 2010 .[x+4]. Release Notes Examples @p 136 January 24.s32 atom.PTX ISA Version 2. s) = (r > s) ? s exch(r.global requires sm_11 or later.

b64.shared }. Within these windows. max.f32 }.e. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.u32 only .space = { . dec(r. If no state space is given. or. The floating-point operations are add. s) = (r >= s) ? 0 : r+1. Semantics *a = operation(*a.Chapter 8. . . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Instruction Set Table 103. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. or [immAddr] an immediate absolute byte address.f32 Performs a reduction operation with operand b and the value in location a. by inserting barriers between normal stores and reduction operations to a common address. . The floating-point add. min. inc. If an address is not properly aligned. . . red.inc. The address size may be either 32-bit or 64-bit. i. and max operations are single-precision. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.u32. or the instruction may fault. min. and truncated if the register width exceeds the state space address width for the target architecture.xor.op. Notes Operand a must reside in either the global or shared state space.exch to store to locations accessed by other reduction operations. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.min. red{. s) = (r > s) ? s : r-1.type [a].e..add.and.u64 . The integer operations are add.space}.global. and stores the result of the specified operation at location a.. and max. min.s32. January 24. or by using atom. b). . e.s32. The bit-size operations are and.s32. . the resulting behavior is undefined. . For red. an address maps to global memory unless it falls within the local memory window or the shared memory window.type = { . an address maps to the corresponding location in local or shared memory. . . overwriting the original value. perform the memory accesses using generic addressing. and xor.u32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .or. . a de-referenced register areg containing a byte address. In generic addressing.dec. 32-bit operations. dec.u32. . i. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.u64.b32 only . where inc(r. Operand a specifies a location in the specified state space. accesses to local memory are illegal.add. . A register containing an address may be declared as a bit-size type or integer type.b]. . .max }. The inc and dec operations return a result in the range [0. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Addresses are zero-extended to the specified width as needed. Description // // // // . 2010 137 . .f32. b.op = { .b32.g. . . The address must be naturally aligned to a multiple of the access size.

max} are unimplemented. red.max.my_val.and. Use of generic addressing requires sm_20 or later. Release Notes Examples @p 138 January 24.add requires sm_12 or later.f32 red.f32 requires sm_20 or later.shared operations require sm_20 or later.f32. red.add. 64-bit red.b32 [a].0.shared requires sm_12 or later. red.s32 red. 2010 .global requires sm_11 or later red.global.shared.add.{min.2. red.global. [p]. 64-bit red.1.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [x+4].PTX ISA Version 2.

The destination predicate value is the same across all threads in the warp. . where the bit position corresponds to the thread’s lane id. Note that vote applies to threads in a single warp.ballot. . vote.q.all.mode.b32 p. p.uni.ballot.q. .Chapter 8. .ballot. Description Performs a reduction of the source predicate across threads in a warp. 2010 139 .uni.all. Instruction Set Table 104.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. vote. r1.all True if source predicate is True for all active threads in warp.any. In the ‘ballot’ form.pred vote. {!}a. // get ‘ballot’ across warp January 24. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. {!}a.ballot. Negate the source predicate to compute . vote. // ‘ballot’ form. not across an entire CTA. The reduction modes are: .not_all. vote.uni }. Negate the source predicate to compute .none.pred vote.any True if source predicate is True for some active thread in warp.pred d.p.b32 d. vote requires sm_12 or later. returns bitmask . Negating the source predicate also computes .2.uni True if source predicate has the same value in all active threads in warp.b32 requires sm_20 or later.mode = { . vote.

bsel}.or zero-extend byte. or word values from its source operands. a{. with optional data merge vop. to produce signed 33-bit input values. the input values are extracted and signor zero.sat}.7. .atype. 3. Video Instructions All video instructions operate on 32-bit register operands.extended internally to .s32 }.sat} d. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.sat} d.bsel}. . .asel = .btype = { .bsel}. .asel}.s33 values.atype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. perform a scalar arithmetic operation to produce a signed 34-bit result. b{.b2.btype{. The primary operation is then performed to produce an . with optional secondary operation vop. . . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.u32 or .s32) is specified in the instruction type. a{. The sign of the intermediate result depends on dtype. vop. atype. 4. The general format of video instructions is as follows: // 32-bit scalar operation. b{.s34 intermediate result. 2. half-word.b1. Using the atype/btype and asel/bsel specifiers.add.PTX ISA Version 2. . 2010 .b3.min.dsel = . optionally clamp the result to the range of the destination type.asel}.btype{. .0 8.h1 }. 140 January 24.dtype = . taking into account the subword destination size in the case of optional data merging.atype = .secop = { . c.max }.bsel = { .secop d. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). b{. all combinations of dtype. and btype are valid.btype{.h0. .dtype.9. The source and destination operands are all 32-bit registers.dtype.atype. The type of each operand (. . // 32-bit scalar operation. c.b0. extract and sign. .dsel. a{.u32.dtype.asel}.

b0: return ((tmp & 0xff) case . } } .h0.h1: return ((tmp & 0xffff) << 16) case . U32_MIN ). tmp. c). c).s33 c ) switch ( dsel ) { case . . tmp. Modifier dsel ) { if ( !sat ) return tmp. Bool sat. Bool sign.b0.b1. S16_MAX. as shown in the following pseudocode. S16_MIN ). tmp. S8_MAX. default: return tmp.s33 optSecOp(Modifier secop. U32_MAX. S32_MIN ). tmp. U16_MAX. .b3: return ((tmp & 0xff) << 24) default: return tmp.h0: return ((tmp & 0xffff) case . The sign of the c operand is based on dtype. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.b2.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.s33 c) { switch ( secop ) { .s34 tmp.s33 optSaturate( .s33 optMerge( Modifier dsel.add: return tmp + c.Chapter 8. Instruction Set . c). 2010 141 . c).max return MAX(tmp.b1: return ((tmp & 0xff) << 8) case . U8_MAX.min: return MIN(tmp.s33 tmp. U8_MIN ). . The lower 32-bits are then written to the destination operand. . . . c). c). S8_MIN ).s33 tmp. . S32_MAX. . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). January 24. . . tmp.b2: return ((tmp & 0xff) << 16) case . switch ( dsel ) { case . c). U16_MIN ). .b3: if ( sign ) return CLAMP( else return CLAMP( case .

d = optSecondaryOp( op2.s32. isSigned(dtype).sat vsub.dtype . Integer byte/half-word/word minimum / maximum.vop . with optional secondary operation vop.sat} d.b1.s32. . tmp.bsel}. asel ).sat vabsdiff. and optional secondary arithmetic operation or subword data merge. Integer byte/half-word/word absolute value of difference.atype.op2 Description = = = = { vadd.s32. vmin.b2. c. a{.btype = { . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. c.u32. b{.atype = .bsel}. vadd. btype.0.b0. .dtype.op2 d. // optional secondary operation d = optMerge( dsel.PTX ISA Version 2.s32.h0.s32. a{. // extract byte/half-word/word and sign. b{.atype.or zero-extend based on source operand type ta = partSelectSignExtend( a. . sat. tb ). Perform scalar arithmetic operation with optional saturate.sat vmin. tb ). // optional merge with c operand 142 January 24.b0.asel = .s32. bsel ). .btype{.dsel .asel}.0 Table 105. { . vabsdiff. vmax Syntax Integer byte/half-word/word addition / subtraction.b3.s32 }. r3.dtype. vabsdiff.s32.b0. vmax require sm_20 or later. tmp = ta – tb. vsub. r3. c. // 32-bit scalar operation. Video Instructions: vadd.dtype. r1. vmin. r1.s32. vabsdiff. vsub. vmax vadd.min.bsel}. atype. tb = partSelectSignExtend( b. // 32-bit scalar operation. tmp = MIN( ta. vadd.u32. . r2.sat} d.asel}. vsub vabsdiff vmin.dsel.asel}. r2.sat}.h0.btype{. vop. Semantics // saturate. vmax }. .add r1. tmp = | ta – tb |. c ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b2. 2010 . . dsel ).s32. r3.btype{. c ). vmin. . a{. with optional data merge vop.s32.sat. .max }. taking into account destination type and merge operations tmp = optSaturate( tmp. vsub. b{. .h1. .bsel = { .u32.add. c.h1. r2. r3. r1. r2.atype.h0. tmp.h1 }. tmp = MAX( ta.

vop . c ).clamp.b0. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tb = partSelectSignExtend( b. tmp. { . . with optional secondary operation vop.asel}.0.op2 d. January 24.Chapter 8.dsel.u32{.asel = . and optional secondary arithmetic operation or subword data merge.mode .wrap r1.u32. if ( mode == . vshl.u32. and optional secondary arithmetic operation or subword data merge. taking into account destination type and merge operations tmp = optSaturate( tmp.bsel = { . Instruction Set Table 106.atype. vop.mode}.dtype . r3.min. Video Instructions: vshl.max }.u32.b2. tmp.u32. . vshr Syntax Integer byte/half-word/word left / right shift.bsel}.asel}. 2010 143 .mode} d.bsel}. r3.clamp . .bsel}. a{.dtype.b1.or zero-extend based on source operand type ta = partSelectSignExtend( a.b3. } // saturate. unsigned shift fills with zero. vshr }.u32. // 32-bit scalar operation.h1 }. r1.u32{. vshl. atype.u32. // default is . . vshl: Shift a left by unsigned amount in b with optional saturate.mode} d. b{. bsel ). sat.dsel . Left shift fills with zero. c. . vshr vshl.sat}{. . Signed shift fills with the sign bit. a{.u32 vshr. // optional secondary operation d = optMerge( dsel.wrap }. asel ). . dsel ). c. . vshr: Shift a right by unsigned amount in b with optional saturate.wrap ) tb = tb & 0x1f.clamp && tb > 32 ) tb = 32. .atype.sat}{.dtype. r2. b{. with optional data merge vop.op2 Description = = = = = { vshl. { .s32 }.atype.atype = { . a{.add. c ).dtype. switch ( vop ) { case vshl: tmp = ta << tb. vshr require sm_20 or later. b{. r2. isSigned(dtype).h1. .h0. // 32-bit scalar operation.s32. if ( mode == .asel}. . .sat}{.u32{. Semantics // extract byte/half-word/word and sign. case vshr: tmp = ta >> tb. d = optSecondaryOp( op2.

scale} d. with optional operand negates.b2. 2010 . 144 January 24.bsel = { . Although PTX syntax allows separate negation of the a and b operands. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.bsel}.po mode. final signed (S32 * U32) .scale} d.po{.U32 // intermediate unsigned. final signed (U32 * S32) + S32 // intermediate signed. Depending on the sign of the a and b operands.h0. and zero-extended otherwise. final signed -(U32 * S32) + S32 // intermediate signed. “plus one” mode. which is used in computing averages.shr15 }.sat}{. .u32. c. . final signed -(S32 * U32) + S32 // intermediate signed. . // 32-bit scalar operation vmad. .atype = . final signed (S32 * S32) . final unsigned -(U32 * U32) + S32 // intermediate signed.dtype. and scaling.b3. That is.s32 }.PTX ISA Version 2. The source operands support optional negation with some restrictions.0 Table 107. (a*b) is negated if and only if exactly one of a or b is negated. final signed (U32 * U32) .b1.po) computes (a*b) + c + 1. {-}a{.S32 // intermediate signed. {-}b{. the intermediate result is signed.scale = { . The final result is unsigned if the intermediate result is unsigned and c is not negated. . a{. internally this is represented as negation of the product (a*b). Source operands may not be negated in . The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. this result is sign-extended if the final result is signed.btype{.S32 // intermediate signed.dtype = . otherwise.asel}.b0. b{. . . final signed -(S32 * S32) + S32 // intermediate signed.atype. Input c has the same sign as the intermediate result. The “plus one” mode (.sat}{.shr7.atype.bsel}.btype.btype = { .dtype.asel}. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. {-}c.. final signed (S32 * S32) + S32 // intermediate signed.h1 }. PTX allows negation of either (a*b) or c. and the operand negates. . final signed (U32 * S32) . vmad. final signed (S32 * U32) + S32 // intermediate signed.asel = .S32 // intermediate signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. . final signed The intermediate result is optionally scaled via right-shift. Description Calculate (a*b) + c. .

po ) { lsb = 1. U32_MAX. tb = partSelectSignExtend( b. } if ( .u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else if ( a. S32_MIN). r2. case . if ( .sat ) { if (signedFinal) result = CLAMP(result. lsb = 1.negate) || c.u32. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). U32_MIN). signedFinal = isSigned(atype) || isSigned(btype) || (a. r1. January 24.negate ) { c = ~c.h0.shr7: result = (tmp >> 7) & 0xffffffffffffffff. tmp[127:0] = ta * tb.sat vmad.Chapter 8. r3.negate ^ b.s32.s32. r1. Instruction Set Semantics // extract byte/half-word/word and sign. r2. else result = CLAMP(result. r0. asel ). lsb = 0. } else if ( c. tmp = tmp + c128 + lsb. 2010 145 .or zero-extend based on source operand type ta = partSelectSignExtend( a. btype.negate ) { tmp = ~tmp. switch( scale ) { case . lsb = 1.shr15 r0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. S32_MAX.u32. bsel ). -r3. vmad.h0.0.negate.u32.negate ^ b. vmad requires sm_20 or later. atype.

r3. { .min.lt.dsel. r1. vset. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.ne r1.h1 }.bsel}. .dsel .ge }.btype.atype .btype.asel}. .op2 d.atype. r2.u32. // 32-bit scalar operation.asel}. . tmp.gt.bsel}. a{. .b1. vset requires sm_20 or later.asel = .btype.b0.b2. a{. c ). The intermediate result of the comparison is always unsigned. .u32. . tmp. asel ).u32.ne.asel}. r2. . .eq.0.cmp . c. tb = partSelectSignExtend( b.cmp d.atype. { . c. with optional data merge vset. d = optSecondaryOp( op2.s32. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. btype. Compare input values using specified comparison.btype = { . tmp = compare( ta. vset. Semantics // extract byte/half-word/word and sign.bsel = { . 2010 .lt vset.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32 }. . .h0. cmp ) ? 1 : 0. b{. a{.u32. . b{.bsel}. b{. . with optional secondary arithmetic operation or subword data merge.op2 Description = = = = .0 Table 108. r3.atype. 146 January 24. bsel ). .PTX ISA Version 2. // optional secondary operation d = optMerge( dsel.h1.le. . // 32-bit scalar operation. c ). and therefore the c operand and final result are also unsigned. atype.b3.add. . tb.cmp d.max }. with optional secondary operation vset.cmp.

trap Abort execution and generate an interrupt to the host CPU. brkpt. January 24. numbered 0 through 15. there are sixteen performance monitor events. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.10. Table 110. pmevent a. brkpt. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.4. Triggers one of a fixed number of performance monitor events. brkpt Suspends execution Introduced in PTX ISA version 1. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.7. Notes PTX ISA Notes Target ISA Notes Examples Currently. with index specified by immediate operand a. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. brkpt requires sm_11 or later.Chapter 8. trap. 2010 147 . @p pmevent 1. trap. pmevent 7.0. Introduced in PTX ISA version 1. Supported on all target architectures. Supported on all target architectures. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Instruction Set 8. Introduced in PTX ISA version 1. The relationship between events and counters is programmed via API calls from the host.0. Table 111.

0 148 January 24.PTX ISA Version 2. 2010 .

which are visible as special registers and accessed through mov or cvt instructions. %clock64 %pm0. Special Registers PTX includes a number of predefined. %lanemask_gt %clock. %lanemask_le. %lanemask_ge. 2010 149 .Chapter 9. …. %pm3 January 24. read-only variables. %lanemask_lt. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq.

mov. The total number of threads in a CTA is (%ntid.0. mov. .y 0 <= %tid.x.x code Target ISA Notes Examples 150 January 24.0.sreg .sreg .z PTX ISA Notes Introduced in PTX ISA version 1. .v4 . %ntid.x. The fourth element is unused and always returns zero. 2D.x * %ntid.PTX ISA Version 2.x code accessing 16-bit component of %tid mov. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.0.z == 0 in 1D CTAs.0.y.sreg . %ntid.%tid.%h2.u16 %rh. Every thread in the CTA has a unique %tid.x.u32.x.u16 %r2.z). mov.z < %ntid. read-only special register initialized with the number of thread ids in each CTA dimension. // compute unified thread id for 2D CTA mov. Redefined as . %ntid. Supported on all target architectures. the %tid value in unused dimensions is 0. 2010 .%tid.u16 %rh. %tid.y * %ntid.x < %ntid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u32 %ntid.v4. read-only. // thread id vector // thread id components A predefined. Supported on all target architectures. The %tid special register contains a 1D. %tid.v4.x 0 <= %tid.u32 %tid.%r0.sreg .u32 %ntid.x. %tid.%ntid.%tid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. mad.z == 0 in 2D CTAs. // move tid.u32 %tid.u32 %h2. %tid component values range from 0 through %ntid–1 in each CTA dimension.x. // CTA shape vector // CTA dimensions A predefined.u32 %h1. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.%tid.%ntid.z == 1 in 2D CTAs.y.z.v4 . It is guaranteed that: 0 <= %tid.u32 %r0. mov.y == %tid.%tid.u32 %r1. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. or 3D vector to match the CTA shape.y. the fourth element is unused and always returns zero.y == %ntid. %ntid.z == 1 in 1D CTAs.z. The number of threads in each dimension are specified by the predefined special register %ntid.u32 %r0.u32 type in PTX 2. CTA dimensions are non-zero.z. cvt. Redefined as . .z to %r2 Table 113.x to %rh Target ISA Notes Examples // legacy PTX 1.y < %ntid. PTX ISA Notes Introduced in PTX ISA version 1.0 Table 112. per-thread special register initialized with the thread identifier within the CTA. %tid.u32 type in PTX 2. // legacy PTX 1. .x. // zero-extend tid.%h1.

u32 %laneid. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Introduced in PTX ISA version 1. mov. The warp identifier will be the same for all threads within a single warp.g. Note that %warpid is volatile and returns the location of a thread at the moment when read. A predefined. e.u32 %r. . Introduced in PTX ISA version 2. read-only special register that returns the maximum number of warp identifiers. For this reason.3. read-only special register that returns the thread’s lane within the warp. Special Registers Table 114. %nwarpid.Chapter 9.3. January 24. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %nwarpid.sreg . mov. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. %nwarpid requires sm_20 or later. but its value may change during execution.sreg . The lane identifier ranges from zero to WARP_SZ-1. Table 115.u32 %warpid. PTX ISA Notes Target ISA Notes Examples Table 116. Supported on all target architectures. A predefined.sreg . 2010 151 . A predefined. . Introduced in PTX ISA version 1. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %r. %laneid. due to rescheduling of threads following preemption. %warpid. read-only special register that returns the thread’s warp identifier.0. Supported on all target architectures. mov.u32 %r. . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.

The %nctaid special register contains a 3D grid shape vector. The fourth element is unused and always returns zero.v4.%nctaid.u32 %ctaid.u16 %r0. Supported on all target architectures.{x.u32 %nctaid. Supported on all target architectures.z PTX ISA Notes Introduced in PTX ISA version 1.v4 .sreg .z < %nctaid.PTX ISA Version 2. The %ctaid special register contains a 1D.y. %rh.sreg . Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.%nctaid.z} < 65.u16 %r0.z. Each vector element value is >= 0 and < 65535. read-only special register initialized with the number of CTAs in each grid dimension. or 3D vector. depending on the shape and rank of the CTA grid. The fourth element is unused and always returns zero.x.x code Target ISA Notes Examples 152 January 24.u32 %ctaid.y.%nctaid.0 Table 117.u32 %nctaid .0.536 PTX ISA Notes Introduced in PTX ISA version 1.v4.0.y. // CTA id vector // CTA id components A predefined. Redefined as .y 0 <= %ctaid. // legacy PTX 1.0. %rh.u32 type in PTX 2. . mov.x. // legacy PTX 1.x. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. mov.x 0 <= %ctaid. . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. 2D.sreg . // Grid shape vector // Grid dimensions A predefined.y < %nctaid.x < %nctaid.x code Target ISA Notes Examples Table 118.sreg . It is guaranteed that: 1 <= %nctaid.x.z.u32 type in PTX 2. with each element having a value of at least 1.%nctaid.u32 mov.y.0. It is guaranteed that: 0 <= %ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. %ctaid.x.%ctaid. 2010 . .%ctaid. read-only special register initialized with the CTA identifier within the CTA grid. Redefined as .u32 mov. %ctaid.v4 .

u32 %smid.u32 %r. so %nsmid may be larger than the physical number of SMs in the device. .sreg .Chapter 9.u32 %r. Notes PTX ISA Notes Target ISA Notes Examples Table 120.0. %nsmid. e. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %r.g. Introduced in PTX ISA version 2. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. .0. where each launch starts a grid-of-CTAs. Supported on all target architectures. A predefined. but its value may change during execution. Introduced in PTX ISA version 1. Note that %smid is volatile and returns the location of a thread at the moment when read. mov.3. A predefined. read-only special register initialized with the per-grid temporal grid identifier.sreg . PTX ISA Notes Target ISA Notes Examples Table 121. This variable provides the temporal grid launch number for this context. During execution.u32 %gridid. The SM identifier ranges from 0 to %nsmid-1. The SM identifier numbering is not guaranteed to be contiguous. PTX ISA Notes Target ISA Notes Examples January 24. %gridid. . The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.u32 %nsmid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Supported on all target architectures. 2010 153 . read-only special register that returns the maximum number of SM identifiers.sreg . %nsmid requires sm_20 or later. due to rescheduling of threads following preemption. mov. Special Registers Table 119. %smid. // initialized at grid launch A predefined. mov. The SM identifier numbering is not guaranteed to be contiguous. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Introduced in PTX ISA version 1. repeated launches of programs may occur. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.

sreg .sreg .u32 %lanemask_le. %lanemask_lt requires sm_20 or later. A predefined.u32 %r. %lanemask_le. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. .u32 %r. Introduced in PTX ISA version 2.sreg . A predefined. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. 154 January 24. %lanemask_eq. %lanemask_lt. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.0. . mov. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.0 Table 122. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Table 124.PTX ISA Version 2. 2010 . mov. Introduced in PTX ISA version 2.u32 %r. %lanemask_eq requires sm_20 or later. .0. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_eq. %lanemask_le requires sm_20 or later. mov.u32 %lanemask_lt. Table 123. A predefined.0.

read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt. 2010 155 . Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. January 24.u32 %r. Introduced in PTX ISA version 2.sreg . mov. A predefined. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %lanemask_gt. .sreg .Chapter 9. %lanemask_ge requires sm_20 or later. %lanemask_ge. Table 126.u32 %r. mov. A predefined.u32 %lanemask_ge.0. Special Registers Table 125. %lanemask_gt requires sm_20 or later.0. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. .

%clock64 requires sm_20 or later.u32 %clock.sreg . %pm1. %pm3. Introduced in PTX ISA version 1. %pm2. ….%clock64.u32 r1. 2010 .0 Table 127. %pm1. Supported on all target architectures. %pm1. . The lower 32-bits of %clock64 are identical to %clock. Introduced in PTX ISA version 2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Their behavior is currently undefined.u32 r1.%pm0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Introduced in PTX ISA version 1. Special Registers: %pm0. mov. Special registers %pm0. 156 January 24.PTX ISA Version 2. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Table 128.u64 %clock64. %pm2.sreg .0.u32 %pm0.3. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. mov. mov. Supported on all target architectures. %pm2. and %pm3 are unsigned 32-bit read-only performance monitor counters. . .u64 r1.0.sreg . read-only 32-bit unsigned cycle counter. %pm3 %pm0. read-only 64-bit unsigned cycle counter. Table 129.%clock.

version Syntax Description Semantics PTX version number.0 .1.version . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version . PTX File Directives: . Increments to the major number indicate incompatible changes to PTX.target Table 130.version 2. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.4 January 24. 2010 157 . Directives 10.0. Duplicate . .Chapter 10. .version directives are allowed provided they match the original .version directive. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. minor are integers Specifies the PTX language version number.version 1.version directive. . Each ptx file must begin with a .version major. Supported on all target architectures.minor // major. and the target architecture for which the code was generated.

0. Introduced in PTX ISA version 1. Texturing mode: (default is .5.texmode_unified . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.samplerref descriptors. PTX code generated for a given target can be run on later generation devices. 64-bit {atom. brkpt instructions. PTX File Directives: . including expanded rounding modifiers. In general. 2010 .global. Target sm_20 Description Baseline feature set for sm_20 architecture.version directive.target directive specifies a single target architecture. sm_11. A program with multiple .shared. . map_f64_to_f32 }.f64 instructions used. Requires map_f64_to_f32 if any . Adds {atom. Adds double-precision support. Texturing mode introduced in PTX ISA version 1. texmode_unified. where each generation adds new features and retains all features of previous generations.f32. Adds {atom.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 storage remains as 64-bits. Description Specifies the set of features in the target architecture for which the current ptx code was generated. PTX features are checked against the specified target architecture. immediately followed by a . 158 January 24.target . Requires map_f64_to_f32 if any . Supported on all target architectures. Requires map_f64_to_f32 if any . The texturing mode is specified for an entire module and cannot be changed within the module.target directive containing a target architecture and optional platform options.texmode_independent texture and sampler information is bound together and accessed via a single . sm_12. and an error is generated if an unsupported feature is used.PTX ISA Version 2. but subsequent . generations of SM architectures follow an “onion layer” model. vote instructions.f64 to .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. The following table summarizes the features in PTX that vary according to target architecture. Note that .red}. texture and sampler information is referenced with independent .texref descriptor. A .global. texmode_independent.target Syntax Architecture and Platform target.red}.target directives can be used to change the set of target features allowed during parsing. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Each PTX file must begin with a . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. sm_13.f64 instructions used.texmode_unified) . sm_10. Therefore.red}. with only half being used by instructions converted from .0 Table 131. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.texref and .f64 instructions used. Disallows use of map_f64_to_f32.

target sm_10 // baseline target architecture . texmode_independent January 24. Directives Examples .Chapter 10. 2010 159 .target sm_20.target sm_13 // supports double-precision .

2.param . At kernel launch.g.3. and body for the kernel function. Parameters may be referenced by name within the kernel body and loaded into registers using ld.PTX ISA Version 2. with optional parameters.0 through 1.5 and later. Parameters are passed via .entry cta_fft .param. These parameters can only be referenced by name within texture and surface load. ld. Supported on all target architectures. opaque . . [y]. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. 2010 .entry . [z].param.entry kernel-name kernel-body Defines a kernel entry point name.param .b32 x.surfref variables may be passed as parameters.entry kernel-name ( param-list ) kernel-body . PTX ISA Notes For PTX ISA version 1.param instructions.func Table 132.b32 %r2. etc.entry Syntax Description Kernel entry point and body. . The shape and size of the CTA executing the kernel are available in special registers.4 and later. ld. parameter variables are declared in the kernel body. e. 160 January 24.4. . Semantics Specify the entry point for a kernel program. %nctaid.param instructions. parameter variables are declared in the kernel parameter list.entry filter ( .b32 %r<99>. Kernel and Function Directives: . . the kernel dimensions and properties are established and made available via special registers. %ntid.0 10.entry . and query instructions and cannot be accessed via ld. . In addition to normal parameters.b32 y. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.0 through 1.param { .samplerref. and .reg .param. ld.b32 z ) Target ISA Notes Examples [x].b32 %r1. store.texref.param space memory and are listed within an optional parenthesized parameter list. parameters. . … } . For PTX ISA versions 1. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.b32 %r3.

func . and supports recursion.reg . The parameter lists define locally-scoped variables in the function body. A . including input and return parameters and optional function body. PTX 2. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. parameters must be in the register state space.Chapter 10. there is no stack. (val0.b32 localVar. Release Notes For PTX ISA version 1.reg .param and st. The implementation of parameter passing is left to the optimizing translator.func (ret-param) fname (param-list) function-body Defines a function. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Variadic functions are represented using ellipsis following the last fixed argument. .b32 N.param space are accessed using ld. Parameter passing is call-by-value. dbl.0 with target sm_20 supports at most one return value.b32 rval) foo (. PTX ISA 2. if any. val1). mov. … use N.reg . ret.func definition with no body provides a function prototype. implements an ABI with stack.func Syntax Function definition. 2010 161 . and recursion is illegal.0. Variadic functions are currently unimplemented.result.2 for a description of variadic functions. .func (.func fname function-body .b32 rval.param state space. Parameters in register state space may be referenced directly within instructions in the function body. Kernel and Function Directives: . .param instructions in the body. Supported on all target architectures.0 with target sm_20 allows parameters in the . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. … Description // return value in fooval January 24. Parameters in .x code.f64 dbl) { . } … call (fooval). Directives Table 133. foo. Parameters must be base types in either the register or parameter state space. other code.func fname (param-list) function-body .reg . which may use a combination of registers and stack locations to pass parameters.

and .pragma The .g.maxntid . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. the . the . 162 January 24.maxnreg . Currently. 2010 . registers) to increase total thread count and provide a greater opportunity to hide memory latency. The directives take precedence over any module-level constraints passed to the optimizing backend. and the strings have no semantics within the PTX virtual machine model.pragma directives may appear at module (file) scope. . and the .maxntid. Note that .maxnctapersm (deprecated) .maxnreg. . The directive passes a list of strings to the backend.0 10. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. to throttle the resource requirements (e. for example. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. which pass information to the backend optimizing compiler. PTX supports the following directives.maxntid and .minnctapersm .entry directive and its body.3.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.minnctapersm directives may be applied per-entry and must appear between an .maxntid directive specifies the maximum number of threads in a thread block (CTA). A general .PTX ISA Version 2.pragma directive is supported for passing information to the PTX backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). The interpretation of . at entry-scope. or as statements within a kernel or device function body. The .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. These can be used.

ny . Supported on all target architectures. Introduced in PTX ISA version 1. .16. Introduced in PTX ISA version 1. nz Declare the maximum number of threads in the thread block (CTA).3.maxntid . The actual number of registers used may be less. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid 256 .maxntid nx. The maximum number of threads is the product of the maximum extent in each dimension. 2010 163 .3. Performance-Tuning Directives: . or 3D CTA. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxctapersm. . The compiler guarantees that this limit will not be exceeded.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid nx .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. the backend may be able to compile to fewer registers.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. ny. .Chapter 10. Exceeding any of these limits results in a runtime error or kernel launch failure. Directives Table 134. 2D.maxntid 16.entry foo .maxnreg n Declare the maximum number of registers per thread in a CTA.entry bar .maxntid Syntax Maximum number of threads in thread block (CTA).maxntid and . Performance-Tuning Directives: . for example.entry foo .maxnreg . .maxntid nx. Supported on all target architectures. or the maximum number of registers may be further constrained by .

if the number of registers used by the backend is sufficiently lower than this bound.maxnctapersm has been renamed to . Supported on all target architectures.minnctapersm in PTX ISA version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. 2010 .0 Table 136. Introduced in PTX ISA version 1. .PTX ISA Version 2. Optimizations based on .maxnctapersm generally need .maxnctapersm.maxntid and . The optimizing backend compiler uses . . Supported on all target architectures.minnctapersm generally need . Introduced in PTX ISA version 2. .3.minnctapersm 4 { … } 164 January 24.maxntid 256 .maxntid 256 . For this reason.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxnctapersm (deprecated) . Performance-Tuning Directives: .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Performance-Tuning Directives: .entry foo .minnctapersm . Deprecated in PTX ISA version 2.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0. .maxntid to be specified as well. Optimizations based on .0 as a replacement for .maxntid to be specified as well. additional CTAs may be mapped to a single multiprocessor.0.entry foo . However. .

pragma Syntax Description Pass directives to PTX backend compiler. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . or at statementlevel.pragma “nounroll”. Performance-Tuning Directives: .Chapter 10. or statement-level directives to the PTX backend compiler. 2010 165 . entry-scoped.pragma directive may occur at module-scope. The interpretation of . { … } January 24. Pass module-scoped. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma “nounroll”.0. at entry-scope. . . Directives Table 138. Introduced in PTX ISA version 2.entry foo .pragma list-of-strings . Supported on all target architectures.pragma . The .

4byte label . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . “”.2.4byte 0x000006b5.0. 0x00. 0x00000364. @@DWARF dwarf-string dwarf-string may have one of the .4.debug_pubnames. replaced by .x code.byte 0x00. 0x00 ..232-1] . 0x02. Table 139. 0x6150736f. 0x00.0 but is supported for legacy PTX version 1. The @@DWARF syntax is deprecated as of PTX version 2.file .section . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x00..section directive is new in PTX ISA verison 2.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.byte 0x2b. 0x63613031.4byte . Supported on all target architectures.4byte 0x6e69616d. 0x5f736f63 .quad int64-list // comma-separated hexadecimal integers in range [0. 0x00. 2010 . 0x00.loc The . 0x00.0 10. @progbits . Deprecated as of PTX 2.0 and replaces the @@DWARF syntax. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . Introduced in PTX ISA version 1.byte byte-list // comma-separated hexadecimal byte values .debug_info .section .4byte int32-list // comma-separated hexadecimal integers in range [0. 0x00 166 January 24. 0x61395a5f.section directive.264-1] .PTX ISA Version 2. 0x736d6172 .

loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 int32-list // comma-separated list of integers in range [0.0.b64 int64-list // comma-separated list of integers in range [0.Chapter 10. 0x00000364. Source file information.b32 0x6e69616d. 0x00.debug_info .b32 label .section .b32 0x000006b5. Supported on all target architectures. .. . 0x00. } 0x02. 0x5f736f63 0x6150736f. 0x00. 2010 167 .232-1] . Debugging Directives: .section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00..b32 .loc . Supported on all target architectures. Supported on all target architectures. .file .loc line_number January 24. 0x00.section .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b8 0x2b.debug_pubnames { . 0x00 0x61395a5f.. 0x63613031. . replaces @@DWARF syntax. Debugging Directives: . 0x736d6172 0x00 Table 141.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Debugging Directives: . .0. Source file location.0.b8 byte-list // comma-separated list of integers in range [0.section Syntax PTX section definition.264-1] . .b8 0x00.file filename Table 142. 0x00. Directives Table 140. .255] .

Supported on all target architectures.0.global .0 10.6.visible .extern identifier Declares identifier to be defined externally.visible . Linking Directives: .b32 foo. Linking Directives: .extern .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. . Introduced in PTX ISA version 1.b32 foo. // foo is defined in another module Table 144.visible Table 143. 2010 .visible identifier Declares identifier to be externally visible.extern . .0. . Linking Directives .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.global . . Introduced in PTX ISA version 1.extern . // foo will be externally visible 168 January 24. Supported on all target architectures.PTX ISA Version 2.

5 PTX ISA 2. 2010 169 . Release Notes This section describes the history of change in the PTX ISA and implementation.Chapter 11.1 PTX ISA 1.3 PTX ISA 1.0 January 24.1 CUDA 2.0 CUDA 2.2 PTX ISA 1.2 CUDA 2.3 driver r190 CUDA 3. The release history is as follows.1 CUDA 2.0. and the remaining sections provide a record of changes in previous releases.0 PTX ISA 1.4 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 CUDA 1. CUDA Release CUDA 1.0 driver r195 PTX ISA Version PTX ISA 1.

fma.rn. Instructions testp and copysign have been added.x code and sm_1x targets. The goal is to achieve IEEE 754 compliance wherever possible.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 requires sm_20.0 11.ftz and .f32 instruction also supports .1. New Features 11.0 11.1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. rcp. The changes from PTX ISA 1.rm and .1.and double-precision div.1. The .f32 require a rounding modifier for sm_20 targets. A single-precision fused multiply-add (fma) instruction has been added. The fma.sat modifiers. Both fma.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.ftz modifier may be used to enforce backward compatibility with sm_1x. Single. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The mad. sub. When code compiled for sm_1x is executed on sm_20 devices.PTX ISA Version 2. These are indicated by the use of a rounding modifier and require sm_20. Floating-Point Extensions This section describes the floating-point changes in PTX 2. Single-precision add.f32 maps to fma. 2010 .1.1. while maximizing backward compatibility with legacy PTX 1. Changes in Version 2. • • • • • 170 January 24.f32. and sqrt with IEEE 754 compliant rounding have been added.0 for sm_20 targets.f32 for sm_20 targets. The mad.f32 and mad. mad.rp rounding modifiers for sm_20 targets. and mul now support .

red}. and red now support generic addressing. for prefetching to specified level of memory hierarchy.Chapter 11. has been added.red. A “count leading zeros” instruction. isspacep.lt.1.minnctapersm to better match its behavior and usage. has been added.le. Instructions {atom.gt} have been added. New special registers %nsmid. Video instructions (includes prmt) have been added.ge. cvta. ldu. %clock64. . Other new features Instructions ld. bfind. e. A new directive. brev. clz. prefetch. Cache operations have been added to instructions ld.1.clamp and . Surface instructions support additional .arrive instruction has been added. popc.maxnctapersm directive was deprecated and replaced with . Instruction sust now supports formatted surface stores. ldu. has been added. The . prefetchu.u32 and bar.red. st.3. %lanemask_{eq.red}.section. A “population count” instruction. has been added. have been added.shared have been extended to handle 64-bit data types for sm_20 targets.b32. A system-level membar instruction. Release Notes 11. 2010 171 . has been added. atom. Instructions prefetch and prefetchu have also been added.ballot. Bit field extract and insert instructions.sys.zero. membar.or}. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. January 24. and sust.1. 11.add. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. suld. A “vote ballot” instruction. A “find leading non-sign bit” instruction. vote.g. and shared addresses to generic address and vice-versa has been added.f32 have been implemented.2. Instructions bar. local. . st. has been added. bar now supports optional thread count and register operands.popc.clamp modifiers. Instruction cvta for converting global.{and. Instructions {atom. The bar instruction has been extended as follows: • • • A bar. New instructions A “load uniform” instruction. A “bit reversal” instruction.1. bfe and bfi. has been added.pred have been added.

Unimplemented Features Remaining The following table summarizes unimplemented instruction features.4 or earlier.ftz (and cvt for . where .s32. call suld. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.1.3.f32} atom.version is 1. 172 January 24. Semantic Changes and Clarifications The errata in cvt. has been fixed. 2010 .red}. or .p.1.{min. See individual instruction descriptions for details. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. Formatted surface load is unimplemented.0 11.5 and later.4 and earlier. In PTX version 1.p sust. the correct number is sixteen. stack-based ABI is unimplemented. Instruction bra. if . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.ftz for PTX ISA versions 1. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. {atom.max} are not implemented. Support for variadic functions and alloca are unimplemented.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. To maintain compatibility with legacy PTX code.u32.{u32.s32.target sm_1x. cvt. 11.f32 type is unimplemented. The underlying. .5.f32.2. Formatted surface store with .PTX ISA Version 2.

entry-function.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.pragma Strings This section describes the . Supported only for sm_20 targets.pragma “nounroll”. 2010 173 . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.Appendix A. Ignored for sm_1x targets. Descriptions of . Table 145. disables unrolling for all loops in the entry function body. disables unrolling of0 the loop for which the current block is the loop header.pragma “nounroll”. L1_end: … } // do not unroll this loop January 24. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma “nounroll”. { … } // do not unroll any loop in this function .func bar (…) { … L1_head: . … @p bra L1_end.entry foo (…) . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. and statement levels. L1_body: … L1_continue: bra L1_head. . The “nounroll” pragma is allowed at module. including loops preceding the . Note that in order to have the desired effect at statement level. .pragma. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma strings defined by ptxas.

0 174 January 24. 2010 .PTX ISA Version 2.

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