NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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..... 5........... Types.............................................................................4........................ 5................ 29 Parameter State Space ............................................................................................... 5............................................................................................................. Arrays......................................................................... 5...........................................................1......................................4........... 30 Shared State Space........... 6.............................................................2....................................................................1...................................... Texture............................... Types ....4...................................4............... 44 Rounding Modifiers .......... 5....2...................................................... 29 Local State Space ....... 37 Array Declarations ..4...................................4................ 38 Alignment .......................6.... 5.............................................1........................PTX ISA Version 2............................................................ 47 Chapter 7................................. 34 Variables ..... Abstracting the ABI .................... 5....... and Vectors ....... 6... 6... 41 Source Operands........5.............................................................4........................5.......................................................... 5....6.2. 41 Destination Operands ...................... Chapter 6. 5......7.......... and Variables ....................... 37 Variable Declarations ......5........4....1..........................4...................... 38 Initializers ..................4....... 27 Register State Space .............................................. 6.......4........................................ 37 Vectors ... Operand Costs ......... 28 Special Register State Space .....1...................2............2.....................3.................................................................5.. 5................. 5................. 42 Arrays as Operands ......................................... 29 Global State Space ......6....................... State Spaces ....2........................ 46 6.....1.. 33 Fundamental Types ........ 33 5. 6....... 43 Vectors as Operands .........................................................3........................0 4. 32 Texture State Space (deprecated) ............................................. Sampler...4................................................. 6.................1..............................4................... 2010 ...... 43 6............1....... 6...5................. 49 7.....................................5..................................1..........................................................4............................................................................ Summary of Constant Expression Evaluation Rules ............................................................................................3....................... 41 6..... 5....................1............................ 5.3.........................................................................................................4...................................................... and Surface Types ........... 42 Addresses as Operands .............................................2................................ Function declarations and definitions ......1................ 28 Constant State Space ........... 27 5..............................1............................................ 44 Scalar Conversions .............1.............................. 6............................. 33 Restricted Use of Sub-Word Sizes . 39 5................................................. Operand Type Information ..................................... State Spaces............ Type Conversion...............1..1..... 39 Parameterized Variable Names ..3........................................ 49 ii January 24...2.................................................................... 43 Labels and Function Names as Operands .. 5......................................... 5............................................................................ 41 Using Addresses........................................... 5..... 6... 25 Chapter 5.............................................2.....................6.............................................. 32 5............ Instruction Operands.........1.......................8.......

.......2.............................. 10.. 8.......... 7................2.0 .. 132 Video Instructions .7.........4............................ 52 Variadic functions ......3......... Changes from PTX 1............. 56 Comparisons ........9. 63 Floating-Point Instructions .............................7...........................3........3........................................... Type Information for Instructions and Operands ... 149 Chapter 10.............................. 172 Unimplemented Features Remaining ......................... 55 Predicated Execution ..........4...............................5.....................................................................................................................................................7.....1.......8............................. 170 New Features ........... 11.......................... 57 Manipulating Predicates ............ 8..............................................................................................................1.......................... Instruction Set ....................................... 10.......................................... Format and Semantics of Instruction Descriptions ...1.......................1............... 122 Control Flow Instructions ....................... 8.........................................4..........................................6.... 58 8............ 108 Texture and Surface Instructions .......................1...................7.................................................................................................................................................................................... 104 Data Movement and Conversion Instructions ......................... 100 Logic and Shift Instructions ........1......... 8.................................................................3.........7..7...................................................... 8..... 8.......................1.............................. 170 Semantic Changes and Clarifications ......................................................................5........6........... 53 Alloca .........................2............. Release Notes ................ 8... 168 Chapter 11................................................................ 8.......... Special Registers .........................................4................................................................................. 54 Chapter 8......................... 11..................................... 162 Debugging Directives ...3......6................................................. 62 8........ 172 January 24..... 55 PTX Instructions ................................................... 8......... 8..........................................................2. Divergence of Threads in Control Constructs ................. Changes in Version 2..... Chapter 9.6............... 8........................................................................................... 10.......................... 157 Specifying Kernel Entry Points and Functions ..... 55 8...................2........ 8................7............................ 2010 iii .......................................... 62 Machine-Specific Semantics of 16-bit Code ............................1........ Directives .............. Instructions ........................ 157 10................... 160 Performance-Tuning Directives ........ 140 Miscellaneous Instructions.........................................1............... 147 8...............x .........2. 8........ 8.........................................................7................................. 11. 7.......................... 166 Linking Directives ........................................ 129 Parallel Synchronization and Communication Instructions ...7...................................................1.3...............3..................................................7....................... 59 Operand Size Exceeding Instruction-Type Size ..............................................................7.............. PTX Version and Target Directives ........1...10....................................................................1.............. 8.......................... 81 Comparison and Selection Instructions .......1.....7............... 62 Semantics ......................................................... 60 8..................... 8...... 63 Integer Arithmetic Instructions ..................... 10.......................7............. 169 11.........................

................pragma Strings...... 173 iv January 24.....0 Appendix A.......PTX ISA Version 2.. Descriptions of .................... 2010 ............

.................................................. Table 13............................................... Table 23............................................................................. Table 21....... 66 Integer Arithmetic Instructions: mul .............. 67 Integer Arithmetic Instructions: mad ...... and Bit-Size Types ............................................................ Table 24.... 33 Opaque Type Fields in Unified Texture Mode ............................................................................................................................................... 58 Floating-Point Comparison Operators Testing for NaN .......................... 60 Relaxed Type-checking Rules for Destination Operands....................... Table 16........... Table 26....................... 65 Integer Arithmetic Instructions: addc ............................ 66 Integer Arithmetic Instructions: subc ....................................................... Table 11............................... Table 17............................................................................................ 23 Constant Expression Evaluation Rules ....................................................................... 69 Integer Arithmetic Instructions: mad24 ...................... Table 8........................ Table 30..... 57 Floating-Point Comparison Operators ................ Table 27..................................... 35 Convert Instruction Precision and Format .......List of Tables Table 1.............. 35 Opaque Type Fields in Independent Texture Mode ...... Table 6..... 19 Predefined Identifiers ..................... Table 10........ 64 Integer Arithmetic Instructions: add.................................. 45 Floating-Point Rounding Modifiers ...................................................................... Table 25........................................ 20 Operator Precedence ................................................................ Table 9............................................................................................. Table 20.............. Table 18..... Table 5........ Table 14........................................ Table 4........................................................................................ Table 32............................................. Table 19....................... 65 Integer Arithmetic Instructions: sub.......cc ...................cc ................................. Table 31................. Table 15..... 28 Fundamental Type Specifiers .................... 61 Integer Arithmetic Instructions: add .... 47 Operators for Signed Integer........................................................................................... 46 Integer Rounding Modifiers ............. Table 22....................................................... 18 Reserved Instruction Keywords .......................................................................... 71 January 24........................................... Table 7.............. 57 Floating-Point Comparison Operators Accepting NaN ............ 58 Type Checking Rules ............ 64 Integer Arithmetic Instructions: sub ....................................................................... Table 29............. Table 12.... Table 3......... 27 Properties of State Spaces ..... PTX Directives ............................................... 25 State Spaces ......................................... 59 Relaxed Type-checking Rules for Source Operands .............................. Unsigned Integer............................................................. 68 Integer Arithmetic Instructions: mul24 ........... Table 2......... 46 Cost Estimates for Accessing State-Spaces ............................. Table 28.................................................. 2010 v ............. 70 Integer Arithmetic Instructions: sad .............................................................

................................... 72 Integer Arithmetic Instructions: min ..................... 102 Comparison and Selection Instructions: selp ................ 71 Integer Arithmetic Instructions: rem ... Table 64.............................................................................. Table 59........................................................................ 86 Floating-Point Instructions: fma ............................... Table 57................................................... 92 Floating-Point Instructions: rcp .................... Table 34....................................... Table 46............................................................ Table 61........................... 72 Integer Arithmetic Instructions: neg ................. 84 Floating-Point Instructions: sub ........ 73 Integer Arithmetic Instructions: max ........... 95 Floating-Point Instructions: sin .... Table 67........................................ Table 62........... 2010 ...................................................................... Table 66.......................... Table 65.................... 83 Floating-Point Instructions: copysign .................................... 92 Floating-Point Instructions: max ...... 90 Floating-Point Instructions: abs ................ Table 36............. Table 53........... Table 49...................................... Table 55....................................................................................... 74 Integer Arithmetic Instructions: bfind ...................... 82 Floating-Point Instructions: testp ............................................................................................ 83 Floating-Point Instructions: add .................................... Table 51................................... Table 63.................................................... 96 Floating-Point Instructions: cos ......................... Table 50............................. 103 Comparison and Selection Instructions: slct ..PTX ISA Version 2................................ 73 Integer Arithmetic Instructions: popc ..................................................... 94 Floating-Point Instructions: rsqrt .......................................................... 77 Integer Arithmetic Instructions: bfi ............................... 74 Integer Arithmetic Instructions: clz ............ 91 Floating-Point Instructions: min ............. Table 44.................................................................................................................................. Integer Arithmetic Instructions: div ............................. Table 47...................... Table 40.................................................................................................................................................................................................................. 99 Comparison and Selection Instructions: set ........................... Table 52......... Table 39............................................................................................ 71 Integer Arithmetic Instructions: abs ...................................... 98 Floating-Point Instructions: ex2 .... 75 Integer Arithmetic Instructions: brev ... 101 Comparison and Selection Instructions: setp ........... 93 Floating-Point Instructions: sqrt .......................................... Table 56.................. 87 Floating-Point Instructions: mad .................................. Table 38.. Table 35......................................................................................................... 103 vi January 24........... Table 37................................. 79 Summary of Floating-Point Instructions ............................................................................. Table 69............... Table 45....................... Table 48......................................... 78 Integer Arithmetic Instructions: prmt ...................... Table 68................................................... Table 41............................. Table 54................... Table 42.............................. 88 Floating-Point Instructions: div .0 Table 33............................................................... Table 43................. 76 Integer Arithmetic Instructions: bfe ............ 85 Floating-Point Instructions: mul ................... 91 Floating-Point Instructions: neg ................................................................................ Table 60.................................. Table 58... 97 Floating-Point Instructions: lg2 .................................................................................................

........................ 143 January 24.............. 142 Video Instructions: vshl............... 2010 vii ...... 105 Logic and Shift Instructions: xor ......................................................................................... Table 72.............. 139 Video Instructions: vadd..................................... 109 Cache Operators for Memory Store Instructions ......... 123 Texture and Surface Instructions: txq ................................................. Table 99.......................................................................... Table 96................. 129 Control Flow Instructions: @ ....................... Table 80......................................... Table 92.. Table 93...... Table 86................................................. Table 73......................... 113 Data Movement and Conversion Instructions: ldu ................ 115 Data Movement and Conversion Instructions: st ................... prefetchu . vmax ................................................................................... Table 82............................................. 130 Control Flow Instructions: call ........... 111 Data Movement and Conversion Instructions: mov ................... 135 Parallel Synchronization and Communication Instructions: red ..................................................................................... 106 Logic and Shift Instructions: cnot .................................... 125 Texture and Surface Instructions: sust ................................................. 129 Control Flow Instructions: bra ....................... vshr .................................. Table 95.... Table 75....... Table 100........ Table 106................. 105 Logic and Shift Instructions: or .............. Table 77.. vmin.......... 112 Data Movement and Conversion Instructions: ld ............................. Table 97...................................... Table 89...................................... Table 105........... Table 83... 131 Control Flow Instructions: exit .............. 128 Control Flow Instructions: { } ..... 131 Parallel Synchronization and Communication Instructions: bar ..................................................... Logic and Shift Instructions: and ..... 130 Control Flow Instructions: ret ................................................................................. 116 Data Movement and Conversion Instructions: prefetch..... Table 84............................. Table 98.................................. 124 Texture and Surface Instructions: suld .................................. 134 Parallel Synchronization and Communication Instructions: atom ........ Table 88........... Table 90............................. Table 78................................................ 127 Texture and Surface Instructions: suq .......... vabsdiff........ Table 101....... Table 76......................... Table 79........ Table 74................. Table 91................................................................................... 119 Data Movement and Conversion Instructions: cvta ................ 137 Parallel Synchronization and Communication Instructions: vote .... Table 94... 110 Data Movement and Conversion Instructions: mov ............................. Table 87........................................................................................................ Table 102....... 119 Data Movement and Conversion Instructions: cvt ............................. 118 Data Movement and Conversion Instructions: isspacep ...................................... 133 Parallel Synchronization and Communication Instructions: membar .......... 106 Logic and Shift Instructions: not .....................................................................................................Table 70.......... Table 104..................................................... Table 85..... 107 Cache Operators for Memory Load Instructions ................... 107 Logic and Shift Instructions: shr .. Table 103...... Table 71........................... 126 Texture and Surface Instructions: sured............................................................ vsub............................... Table 81..... 120 Texture and Surface Instructions: tex ...................................... 106 Logic and Shift Instructions: shl ......................

.............target ............................................................ Table 124.................................................................................................. 168 viii January 24............................................................... 157 PTX File Directives: ...................................... 154 Special Registers: %lanemask_ge ................................................................................................................................................................. 153 Special Registers: %nsmid ...................................................................................................................... 164 Performance-Tuning Directives: .............................................................minnctapersm ................... Table 136........................................................................................................... 153 Special Registers: %lanemask_eq ...........maxntid .. Table 115....... 167 Debugging Directives: ...............................loc ....... 154 Special Registers: %lanemask_le ......... 163 Performance-Tuning Directives: ................... 166 Debugging Directives: .....................entry..................................... %pm3 ...................................................................... 156 Special Registers: %pm0.... Table 131.......................section ..................... 152 Special Registers: %nctaid ..... 151 Special Registers: %ctaid ................. %pm1........................................... 156 PTX File Directives: . 164 Performance-Tuning Directives: ............. 147 Miscellaneous Instructions: brkpt ... Table 132.............................. 151 Special Registers: %warpid .... Table 135............................................................................................ Table 140................................................... Table 141.......... 156 Special Registers: %clock64 ................ Table 139.............version...........................file ...... Table 129............... Table 111..... Table 138.................................. Table 119......... 153 Special Registers: %gridid ...............................................................................................................0 Table 107...... 151 Special Registers: %nwarpid .............. Table 120.......................... Table 128...............................................extern.................................. 167 Debugging Directives: ................ Table 114.. 152 Special Registers: %smid .......... Video Instructions: vmad ................................. 147 Miscellaneous Instructions: pmevent................................maxnreg ................................ 161 Performance-Tuning Directives: ................ Table 130..... Table 133.............................................................................pragma ..... %pm2.... 167 Linking Directives: ...................... 144 Video Instructions: vset..... Table 116...................................................................................................................... Table 137........ Table 142.................................................. Table 143............. Table 123..... Table 126.................................. Table 110........... Table 122.................... 165 Debugging Directives: @@DWARF ............................................... 158 Kernel and Function Directives: ............... 150 Special Registers: %ntid ...................................... 160 Kernel and Function Directives: ......................... Table 121... Table 125....................................................... 146 Miscellaneous Instructions: trap ....................... 163 Performance-Tuning Directives: .................................. Table 134........................................................................... 155 Special Registers: %lanemask_gt .............. Table 112....................... Table 118......... 2010 . 150 Special Registers: %laneid ............................... 154 Special Registers: %lanemask_lt ... Table 117....... Table 113............................................... 147 Special Registers: %tid ......... Table 108.........maxnctapersm (deprecated) ...... 155 Special Registers: %clock .................PTX ISA Version 2................................ Table 127.................................. Table 109...func ..............................

........... 173 January 24....................................visible................................................. Linking Directives: .................................... 2010 ix ........ 168 Pragma Strings: “nounroll” .... Table 145............Table 144...............

PTX ISA Version 2. 2010 .0 x January 24.

Chapter 1. many-core processor with tremendous computational horsepower and very high memory bandwidth. and because it is executed on many data elements and has high arithmetic intensity. image scaling. which are optimized for and translated to native target-architecture instructions. there is a lower requirement for sophisticated flow control. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. 1. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. from general signal processing or physics simulation to computational finance or computational biology. video encoding and decoding. and pattern recognition can map image blocks and pixels to parallel processing threads. 1. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. January 24. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Introduction This document describes PTX. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. high-definition 3D graphics. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Similarly. multithreaded. the programmable GPU has evolved into a highly parallel. PTX exposes the GPU as a data-parallel computing device. image and media processing applications such as post-processing of rendered images. PTX defines a virtual machine and ISA for general purpose parallel thread execution. PTX programs are translated at install time to the target hardware instruction set.2. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. 2010 1 . stereo vision. In fact. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. the memory access latency can be hidden with calculations instead of big data caches. Because the same program is executed for each data element. Many applications that process large data sets can use a data-parallel programming model to speed up the computations.1. Data-parallel processing maps data elements to parallel processing threads.

and the introduction of many new instructions.f32 for sm_20 targets.0 are improved support for IEEE 754 floating-point operations.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. PTX ISA Version 2.rp rounding modifiers for sm_20 targets.f32 and mad.3.sat modifiers. addition of generic addressing to facilitate the use of general-purpose pointers. Both fma. A single-precision fused multiply-add (fma) instruction has been added. memory. including integer. 2010 .ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. The mad. Single-precision add. surface. 1.0 is in improved support for the IEEE 754 floating-point standard. Instructions marked with .f32 require a rounding modifier for sm_20 targets. and video instructions.PTX ISA Version 2.f32 instruction also supports .rn. Provide a common source-level ISA for optimizing code generators and translators.0 PTX ISA Version 2.f32.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. sub.rm and . fma.3. and architecture tests. When code compiled for sm_1x is executed on sm_20 devices. mad. atomic. Provide a code distribution ISA for application and middleware developers.f32 requires sm_20.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The changes from PTX ISA 1. A “flush-to-zero” (.1. Achieve performance in compiled applications comparable to native GPU performance.0 is a superset of PTX 1.x. reduction. • • • 2 January 24. which map PTX to specific target machines.x features are supported on the new sm_20 target. Facilitate hand-coding of libraries.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. 1.ftz) modifier may be used to enforce backward compatibility with sm_1x. Improved Floating-Point Support A main area of change in PTX 2.f32 maps to fma. The main areas of change in PTX 2.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. performance kernels. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. barrier. Provide a machine-independent ISA for C/C++ and other compilers to target. The fma.x code will continue to run on sm_1x targets as well. The mad. Most of the new features require a sm_20 target. and all PTX 1.ftz and . Legacy PTX 1. and mul now support . PTX 2. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.

Instructions prefetch and prefetchu have been added. for prefetching to specified level of memory hierarchy.0 closer to full compliance with the IEEE 754 standard. • Taken as a whole. local. Surface instructions support additional clamp modifiers.Chapter 1. st. and sqrt with IEEE 754 compliant rounding have been added.4. A new cvta instruction has been added to convert global. .0. atom. and shared addresses to generic address and vice-versa has been added. In PTX 2. i. Cache operations have been added to instructions ld. prefetch. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.0. and vice versa. st. local. Instructions testp and copysign have been added. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. suld.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. NOTE: The current version of PTX does not implement the underlying. These are indicated by the use of a rounding modifier and require sm_20. PTX 2. local. 2010 3 . an address that is the same across all threads in a warp. prefetchu. and Application Binary Interface (ABI).zero. e. allowing memory instructions to access these spaces without needing to specify the state space.3.2. Generic addressing unifies the global.clamp and .e. and sust. cvta..3. Introduction • Single.3. so recursion is not yet supported. Generic Addressing Another major change is the addition of generic addressing. 1. Surface Instructions • • Instruction sust now supports formatted surface stores. isspacep.3. Support for an Application Binary Interface Rather than expose details of a particular calling convention.g. and shared addresses to generic addresses. January 24. special registers. and red now support generic addressing. Instruction cvta for converting global. and shared state spaces. 1. stack layout. rcp.and double-precision div. New Instructions The following new instructions. 1. stack-based ABI. ldu. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. instructions ld. and directives are introduced in PTX 2. these changes bring PTX 2.

add.{and. %lanemask_{eq. New special registers %nsmid.shared have been extended to handle 64-bit data types for sm_20 targets.popc.red. has been added. Reduction. Instructions bar. vote.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.pred have been added.gt} have been added. A “vote ballot” instruction.red.u32 and bar. 4 January 24.lt. %clock64. has been added. A bar. Other Extensions • • • Video instructions (includes prmt) have been added.sys. Instructions {atom. bfi bit field extract and insert popc clz Atomic.red}. A new directive.f32 have been added.PTX ISA Version 2. 2010 . membar. .b32.ballot. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.section.le. Barrier Instructions • • A system-level membar instruction.or}.ge. bar now supports an optional thread count and register operands.arrive instruction has been added.red}. and Vote Instructions • • • New atomic and reduction instructions {atom.

2010 5 .Chapter 1.0. January 24. Chapter 6 describes instruction operands. and variable declarations. Chapter 11 provides release notes for PTX Version 2. types. Chapter 3 gives an overview of the PTX virtual machine model. calling convention. Introduction 1. Chapter 9 lists special registers. Chapter 5 describes state spaces. Chapter 10 lists the assembly directives supported in PTX. Chapter 7 describes the function and call syntax.4. and PTX support for abstracting the Application Binary Interface (ABI). The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 4 describes the basic syntax of the PTX language. Chapter 8 describes the instruction set.

PTX ISA Version 2. 2010 .0 6 January 24.

and ntid. Each thread has a unique thread identifier within the CTA. and tid.y. Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2D.1. January 24.x. Each CTA has a 1D. or 3D CTA. one can specify synchronization points where threads wait until all threads in the CTA have arrived. To coordinate the communication of the threads within the CTA.2. The thread identifier is a three-element vector tid. (with elements tid. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. or CTA. 2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.1. or 3D shape specified by a three-element vector ntid (with elements ntid. can be isolated into a kernel function that is executed on the GPU as many different threads. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. Each CTA thread uses its thread identifier to determine its assigned role. work.z). To that effect. Programming Model 2. but independently on different data.2. ntid. or host: In other words.y. and select work to perform. compute-intensive portions of applications running on the host are off-loaded onto the device. data-parallel. assign specific input and output positions. is an array of threads that execute a kernel concurrently or in parallel. 2D. compute addresses. 2. More precisely. tid. A cooperative thread array.x. a portion of an application that is executed many times. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Programs use a data parallel decomposition to partition inputs.z) that specifies the thread’s position within a 1D. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. The vector ntid specifies the number of threads in each CTA dimension. 2010 7 . and results across the threads of the CTA. It operates as a coprocessor to the main CPU.Chapter 2. Threads within a CTA can communicate with each other.

A warp is a maximal subset of threads from a single CTA. %nctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Multiple CTAs may execute concurrently and in parallel. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Typically. multiple-thread) fashion in groups called warps. depending on the platform. %ntid. 8 January 24. or 3D shape specified by the parameter nctaid.0 Threads within a CTA execute in SIMT (single-instruction. because threads in different CTAs cannot communicate and synchronize with each other. Threads may read and use these values through predefined. a warp has 32 threads. such that the threads execute the same instructions at the same time. Each grid of CTAs has a 1D. CTAs that execute the same kernel can be batched together into a grid of CTAs. The host issues a succession of kernel invocations to the device. 2D . so that the total number of threads that can be launched in a single kernel invocation is very large. Some applications may be able to maximize performance with knowledge of the warp size. which may be used in any instruction where an immediate operand is allowed. 2010 . and %gridid. %ctaid.2. read-only special registers %tid. However. Threads within a warp are sequentially numbered. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. WARP_SZ.PTX ISA Version 2. 2. This comes at the expense of reduced thread communication and synchronization. or sequentially. Each grid also has a unique temporal grid identifier (gridid).2. The warp size is a machine-dependent constant. so PTX includes a run-time immediate constant.

2010 9 . 0) CTA (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (3. 0) CTA (1. 2) Thread (4. 2) Thread (3. 2) Thread (1. 1) Thread (1. Figure 1. Thread Batching January 24. 0) Thread (3.Chapter 2. 0) Thread (0. 1) Thread (0. A grid is a set of CTAs that execute independently. 1) CTA (2. 0) Thread (2. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (1. 1) CTA (1. 0) Thread (4. 0) CTA (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (2. 1) Thread (4. 2) Thread (2. 1) Thread (0.

The global. The device memory may be mapped and read or written by the host.PTX ISA Version 2. Both the host and the device maintain their own local memory. 2010 . copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. and texture memory spaces are optimized for different memory usages. Finally. constant. Texture memory also offers different addressing modes. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. as well as data filtering.3. all threads have access to the same global memory. respectively. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. or.0 2. for more efficient transfer. and texture memory spaces are persistent across kernel launches by the same application. The global. Each thread has a private local memory. for some specific data formats. 10 January 24. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. constant. referred to as host memory and device memory.

2010 11 . 0) Block (0. 0) Block (0. 1) Block (0. 0) Block (2. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (1. 1) Block (1. Memory Hierarchy January 24. 2) Block (1. 1) Block (2. 0) Block (1.Chapter 2. 2) Figure 2. 1) Grid 1 Global memory Block (0. 1) Block (1.

0 12 January 24. 2010 .PTX ISA Version 2.

(This term originates from weaving. new blocks are launched on the vacated multiprocessors. A multiprocessor consists of multiple Scalar Processor (SP) cores. The way a block is split into warps is always the same. The threads of a thread block execute concurrently on one multiprocessor. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. a cell in a grid-based computation). allowing. schedules. If threads of a warp diverge via a data-dependent conditional branch.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. The multiprocessor creates. and each scalar thread executes independently with its own instruction address and register state. and when all paths complete. multiple-thread). so full efficiency is realized when all threads of a warp agree on their execution path. A warp executes one common instruction at a time. the threads converge back to the same execution path. Parallel Thread Execution Machine Model 3. It implements a single-instruction barrier synchronization. As thread blocks terminate. the warp serially executes each branch path taken. The multiprocessor SIMT unit creates. When a host program invokes a kernel grid. increasing thread IDs with the first warp containing thread 0. manages. each warp contains threads of consecutive. At every instruction issue time. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. manages. a voxel in a volume. 2010 13 . January 24. the first parallel thread technology. a multithreaded instruction unit. Branch divergence occurs only within a warp. To manage hundreds of threads running several different programs. and executes concurrent threads in hardware with zero scheduling overhead. it splits them into warps that get scheduled by the SIMT unit. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). disabling threads that are not on that path. different warps execute independently regardless of whether they are executing common or disjointed code paths. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. the multiprocessor employs a new architecture we call SIMT (single-instruction. and executes threads in groups of parallel threads called warps. When a multiprocessor is given one or more thread blocks to execute. for example. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp.Chapter 3. The multiprocessor maps each thread to one scalar processor core.1. and on-chip shared memory.

on the other hand. If an atomic instruction executed by a warp reads. however. but one of the writes is guaranteed to succeed. SIMT enables programmers to write thread-level parallel code for independent. modifies. whereas SIMT instructions specify the execution and branching behavior of a single thread.PTX ISA Version 2. each read. but the order in which they occur is undefined. A key difference is that SIMD vector organizations expose the SIMD width to the software.0 SIMT architecture is akin to SIMD (Single Instruction. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. which is a read-only region of device memory. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. Vector architectures. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. the kernel will fail to launch. the number of serialized writes that occur to that location and the order in which they occur is undefined. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. For the purposes of correctness. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. modify. 14 January 24. require the software to coalesce loads into vectors and manage divergence manually. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. In practice. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. scalar threads. A multiprocessor can execute as many as eight thread blocks concurrently. the programmer can essentially ignore the SIMT behavior. and writes to the same location in global memory for more than one of the threads of the warp. As illustrated by Figure 3. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. which is a read-only region of device memory. write to that location occurs and they are all serialized. 2010 . as well as data-parallel code for coordinated threads. If there are not enough registers or shared memory available per multiprocessor to process at least one block. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. In contrast with SIMD vector machines. • The local and global memory spaces are read-write regions of device memory and are not cached.

Chapter 3. Figure 3. Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 .

0 16 January 24. 2010 .PTX ISA Version 2.

#endif.1. 2010 17 . Comments Comments in PTX follow C/C++ syntax. PTX is case sensitive and uses lowercase for keywords. #define. #else. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. The following are common preprocessor directives: #include. Source Format Source files are ASCII text. Comments in PTX are treated as whitespace. #ifdef.target directive specifying the target architecture assumed.2. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. using non-nested /* and */ for comments that may span multiple lines. The C preprocessor cpp may be used to process PTX source files. followed by a .version directive specifying the PTX language version. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 4. All whitespace characters are equivalent.Chapter 4. Lines are separated by the newline character (‘\n’). Syntax PTX programs are a collection of text source files. #if. and using // to begin a comment that extends to the end of the current line. January 24. Pseudo-operations specify symbol and addressing management. Lines beginning with # are preprocessor directives. #line. See Section 9 for a more information on these directives. 4. whitespace is ignored except for its use in separating tokens in the language. Each PTX file must begin with a .

Table 1.reg .1.section .0 4. address expressions.minnctapersm . r2. where p is a predicate register.loc . ld. and terminated with a semicolon.b32 r1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.2.align .entry .f32 r2.param . . shl.global.x.global start: . 0.local . 18 January 24.file PTX Directives . 2010 . All instruction keywords are reserved tokens in PTX. Directive Statements Directive keywords begin with a dot.extern .b32 r1.3. 2. Instruction keywords are listed in Table 2. r2. Operands may be register variables.func . followed by source operands.b32 add.shared . The guard predicate follows the optional label and precedes the opcode. Statements begin with an optional label and end with a semicolon. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.sreg . or label names. mov. so no conflict is possible with user-defined identifiers. Statements A PTX statement is either a directive or an instruction.tex .visible 4.maxnreg .const . %tid.reg . The destination operand is first.maxntid .3. r2. written as @!p. The guard predicate may be optionally negated.f32 array[N]. array[r1].global .PTX ISA Version 2. constant expressions.version . and is written as @p.5. r1.b32 r1. .3. Instructions have an optional guard predicate which controls conditional execution.maxnctapersm .pragma . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.target . Examples: .

Syntax Table 2. 2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

digits. 2010 . Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or percentage character followed by one or more letters. or they start with an underscore. dollar. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. PTX predefines one constant and a small number of special registers that begin with the percentage sign.0 4. Table 3.PTX ISA Version 2. PTX allows the percentage sign as the first character of an identifier. except that the percentage sign is not allowed. digits. %pm3 WARP_SZ 20 January 24. e. underscore.4. between user-defined variable names and compiler-generated names. listed in Table 3. Many high-level languages such as C and C++ follow similar rules for identifier names.g. underscore. The percentage sign can be used to avoid name conflicts. …. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or dollar characters.

Constants PTX supports integer and floating-point constants and constant expressions. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. i. the sm_1x and sm_20 targets have a WARP_SZ value of 32.. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. These constants may be used in data initialization and as operands to instructions.e. Integer literals may be written in decimal. To specify IEEE 754 single-precision floating point values. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.1. zero values are FALSE and non-zero values are TRUE. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.2.. every integer constant has type . the constant begins with 0d or 0D followed by 16 hex digits. integer constants are allowed and are interpreted as in C.u64. there is no suffix letter to specify size. floating-point. 2010 21 . Type checking rules remain the same for integer.5. 4. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. hexadecimal. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.s64) unless the value cannot be fully represented in .s64 or . and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. 4. When used in an instruction or data initialization. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. where the behavior of the operation depends on the operand types. literals are always represented in 64-bit double-precision format. and bit-size types. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.Chapter 4. in which case the literal is unsigned (.5.s64 or the unsigned suffix is specified. i. Unlike C and C++. The syntax follows that of C. the constant begins with 0f or 0F followed by 8 hex digits.5. Syntax 4. or binary notation. To specify IEEE 754 doubleprecision floating point values.e. Floating-point literals may be written with an optional decimal point and an optional signed exponent. 0[fF]{hexdigit}{8} // single-precision floating point January 24. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. For predicate-type data and instructions. each integer constant is converted to the appropriate size based on the data or instruction type at its use.u64). The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. octal.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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2nd is .s64 .f64 converted type constant literal + ! ~ Cast Binary (.f64 : .u64 .u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 .s64 .u64.u64 1st unchanged.u64) (.u64 same as 1st operand .6.u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 use usual conversions .s64) + . 2010 25 .f64 use usual conversions .s64 .5.s64 .u64 .f64 integer .f64 converted type .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 integer .s64 .s64 .s64 . or .f64 integer integer integer integer integer int ?.u64 . Syntax 4. .f64 use usual conversions .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .f64 same as source .u64 .Chapter 4.s64. Table 5. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.

2010 .PTX ISA Version 2.0 26 January 24.

and level of sharing between threads.reg . pre-defined. Types. Name State Spaces Description Registers. 2010 27 . Addressable memory shared between threads in 1 CTA.param . defined per-grid. and properties of state spaces are shown in Table 5. defined per-thread.sreg . private to each thread.1. platform-specific. Global texture memory (deprecated). Read-only. and these resources are abstracted in PTX through state spaces and data types. Global memory.local . .tex January 24. access rights. Shared.global . or Function or local parameters. shared by all threads. 5. and Variables While the specific resources available in a given target GPU will vary. the kinds of resources will be common across platforms. fast. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Table 6. Local memory.const . State Spaces. The characteristics of a state space include its size. read-only memory. Special registers.shared . State Spaces A state space is a storage area with particular characteristics. access speed. The list of state spaces is shown in Table 4.Chapter 5. Kernel parameters. addressability. All variables reside in some state space.

it is not possible to refer to the address of a register. The most common use of 8-bit registers is with ld. and will vary from platform to platform.global .. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 28 January 24.PTX ISA Version 2.1. Register State Space Registers (. Device function input parameters may have their address taken via mov.shared .local . aside from predicate registers which are 1-bit.2. register variables will be spilled to memory.param and st. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .1.0 Table 7. or 128-bits. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.param instruction.param instructions. i. and vector registers have a width of 16-. 32-. 32-. 16-. or 64-bits.sreg) state space holds predefined. such as grid. predicate) or untyped. 64-. Special Register State Space The special register (. 2010 . 3 Accessible only via the tex instruction.param (used in functions) . platform-specific registers. Registers may have alignment boundaries required by multi-word loads and stores. The number of registers is limited. st.tex Restricted Yes No3 5. unsigned integer. causing changes in performance.1. and thread parameters. the parameter is then located on the stack frame and its address is in the . floating point. When the limit is exceeded.local state space.const . CTA.reg state space) are fast storage locations. clock counters. and performance monitoring registers. For each architecture. 5. 1 Accessible only via the ld.e.reg .sreg . Registers may be typed (signed integer.param (as input to kernel) . and cvt instructions. All special registers are predefined. Address may be taken via mov instruction. scalar registers have a width of 8-. Register size is restricted. Registers differ from the other state spaces in that they are not fully addressable. or as elements of vector tuples. 2 Accessible via ld.

Types. Module-scoped local memory variables are stored at fixed addresses. an incomplete array in bank 2 is accessed as follows: . Local State Space The local state space (.global) state space is memory that is accessible by all threads in a context. bank zero is used. For example. Use ld. It is the mechanism by which different CTAs and different grids can communicate. for example).global. the stack is in local memory. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. the store operation updating a may still be in flight.sync instruction.const) state space is a read-only memory. Consider the case where one thread executes the following two assignments: a = a + 1. there are eleven 64KB banks. To access data in contant banks 1 through 10. This reiterates the kind of parallelism available in machines that run PTX. Multiple incomplete array variables declared in the same bank become aliases. By convention. Use ld. This pointer can then be used to access the entire 64KB constant bank. If another thread sees the variable b change.extern . In implementations that support a stack. and Variables 5. ld. where the size is not known at compile time. Constant State Space The constant (.3.1. st. b = b – 1.sync instruction are guaranteed to be visible to any reads after the barrier instruction. results in const_buffer pointing to the start of constant bank two. Global State Space The global (. For example. For any thread in a context.local and st. Global memory is not sequentially consistent.const[2] .b32 const_buffer[]. as in lock-free and wait-free style programming.global to access global variables. Threads wait at the barrier until all threads in the CTA have arrived.1. The remaining banks may be used to implement “incomplete” constant arrays (in C. The constant memory is organized into fixed size banks. Threads must be able to do their work without waiting for other threads to do theirs.local to access local variables.const[bank] modifier. initialized by the host.global.Chapter 5.const[2] .extern .local) is private memory for each thread to keep its own data. Sequential consistency is provided by the bar. as it must be allocated on a perthread basis. and atom. [const_buffer+4].4. It is typically standard memory with cache. For the current devices.b32 const_buffer[]. 5. 2010 29 . all addresses are in global memory are shared.5.const[2]. Banks are specified using the . bank zero is used for all statically-sized constant variables. All memory writes prior to the bar. State Spaces. If no bank number is given. each pointing to the start address of the specified constant bank. The size is limited.1. the bank number must be provided in the state space of the load instruction. the declaration .b32 %r1. where bank ranges from 0 to 10. // load second word 5. whereas local memory variables declared January 24.

Therefore. 2010 .param instructions.b8 buffer[64] ) { . read-only variables declared in the .u32 %ptr.reg .u32 %n. . per-kernel versus per-thread).param space. These parameters are addressable. Example: . No access protection is provided between parameter and global space in this case. [buffer].param . Note that PTX ISA versions 1. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. The use of parameter state space for device function parameters is new to PTX ISA version 2.x supports only kernel function parameters in .param. %n. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param state space and is accessed using ld. in some implementations kernel parameters reside in global memory.6. 5.f64 %d. For example.0 within a function or kernel body are allocated on the stack. The address of a kernel parameter may be moved into a register using the mov instruction.align 8 . 5. device function parameters were previously restricted to the register state space. len.b32 N.PTX ISA Version 2.param) state space is used (1) to pass input arguments from the host to the kernel. [N]. ld.param.entry foo ( . Note: The location of parameter space is implementation specific.param . ld.1. Similarly. (2a) to declare formal input and return parameters for device functions called from within kernel execution.1. The kernel parameter variables are shared across all CTAs within a grid. . … 30 January 24.reg . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).reg .6. mov. The resulting address is in the . PTX code should make no assumptions about the relative locations or ordering of .param. Values passed from the host to the kernel are accessed through these parameter variables using ld.param . typically for passing large structures by value to a function.u32 %ptr.param state space. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.1. In implementations that do not support a stack. ld.param instructions.param space variables. all local memory variables are stored at fixed addresses and recursive function calls are not supported.u32 %n.f64 %d.u32 %n. … Example: . [%ptr].0 and requires target architecture sm_20.b32 len ) { . Parameter State Space The parameter (.entry bar ( .

Note that the parameter will be copied to the stack if necessary. [buffer+8]. .param . it is illegal to write to an input parameter or read from a return parameter. . which declares a .s32 %y.reg . .Chapter 5.local state space and is accessed via ld.param space is also required whenever a formal parameter has its address taken within the called function.f64 [mystruct+0].reg .param space variable. The most common use is for passing objects by value that do not fit within a PTX register. passed to foo … . . Aside from passing structures by value.f64 dbl. int y.param.1. In this case. the caller will declare a locally-scoped . … } // code snippet from the caller // struct { double d.reg . It is not possible to use mov to get the address of a return parameter or a locally-scoped . Device Function Parameters PTX ISA version 2. ld.b32 N.s32 [mystruct+8]. x. } mystruct. 2010 31 .0 extends the use of parameter space to device function parameters.param and function return parameters may be written using st. such as C structures larger than 8 bytes.2.align 8 . Function input parameters may be read via ld.param.param. . Typically. State Spaces. Example: // pass object of type struct { double d. is flattened.local instructions. ld.param formal parameter having the same size and alignment as the passed argument. .func foo ( . … See the section on function call syntax for more details. This will be passed by value to a callee.s32 %y. dbl.align 8 .b8 buffer[12] ) { . … st.param.b8 mystruct. call foo.param byte array variable that represents a flattened C structure or union. the address of a function input parameter may be moved into a register using the mov instruction. int y.reg . (4. [buffer]. a byte array in parameter space is used.f64 %d.param . Types. mystruct). January 24.param. and so the address will be in the .6. st. In PTX.s32 x.f64 %d.local and st.reg . }. and Variables 5.

0 5. where texture identifiers are allocated sequentially beginning with zero. Physical texture resources are allocated on a per-module granularity.1.6 for its use in texture instructions. 2010 .PTX ISA Version 2. tex_d. where all threads read from the same address. Another is sequential access from sequential threads.texref. Multiple names may be bound to the same physical texture identifier.tex state space are equivalent to module-scoped . tex_c.global .u64.tex .shared and st.tex . See Section 5. and programs should instead reference texture memory through variables of type .tex) state space is global memory accessed via the texture instruction. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. a legacy PTX definitions such as .u32 or . Texture memory is read-only.global state space. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). and .tex directive will bind the named texture memory variable to a hardware texture identifier. Use ld. 32 January 24.7. The .tex .8. One example is broadcast. Example: .tex .tex .texref type and Section 8. The texture name must be of type . The .tex variables are required to be defined in the global scope.tex directive is retained for backward compatibility.u32 tex_a. 5.u32 . tex_d.texref tex_a.texref variables in the . and variables declared in the .u32 tex_a. Shared State Space The shared (.shared) state space is a per-CTA region of memory for threads in a CTA to share data. Texture State Space (deprecated) The texture (. Shared memory typically has some optimizations to support the sharing.3 for the description of the .u32 .7. For example. is equivalent to . An address in shared memory can be read and written by any thread in a CTA. It is shared by all threads in a context. An error is generated if the maximum number of physical resources is exceeded.shared to access shared variables. tex_f.1.u32 . A texture’s base address is assumed to be aligned to a 16-byte boundary.

All floating-point instructions operate only on . .f32. stored. and Variables 5.f64 types.s64 . .2. January 24. The following table lists the fundamental type specifiers for each basic type: Table 8.f64 types.f32 and .b8 instruction types are restricted to ld.s8. Register variables are always of a fundamental type. all variables (aside from predicates) could be declared using only bit-size types. Two fundamental types are compatible if they have the same basic type and are the same size. needed to fully specify instruction behavior. and cvt instructions.u8. 5.2.b32.f32 and . The same typesize specifiers are used for both variable definitions and for typing instructions. so their names are intentionally short. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. 2010 33 . Fundamental Types In PTX. Types 5. . the fundamental types reflect the native data types supported by the target architectures. . Operand types and sizes are checked against instruction types for compatibility. and instructions operate on these types.f16 floating-point type is allowed only in conversions to and from .s16. .b64 .u8. .2. stored. st.u16.s32. st.f64 . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. For example. .f16.u64 .Chapter 5.s8. but typed variables enhance program readability and allow for better operand type checking. The . Restricted Use of Sub-Word Sizes The . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . . Signed and unsigned integer types are compatible if they have the same size. Types.pred Most instructions have one or more type specifiers.u32.b16.2. In principle.1. and converted using regular-width registers. The bitsize type is compatible with any fundamental type having the same size. For convenience. so that narrow values may be loaded. . ld.b8. . A fundamental type specifies both a basic type and a size. or converted to other types and sizes. and . . State Spaces.

surfref. Sampler. The three built-in types are . sured). and surface descriptor variables. opaque_var. texture and sampler information each have their own handle. . or performing pointer arithmetic will result in undefined results.3. base address. samplers. In the unified mode. In independent mode the fields of the . These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.PTX ISA Version 2. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists.samplerref variables. the resulting pointer may be stored to and loaded from memory. i.u64} reg. passed as a parameter to functions. 34 January 24. For working with textures and samplers. These types have named fields similar to structures. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.texref type that describe sampler properties are ignored.texref handle. The following tables list the named members of each type for unified and independent texture modes. suq). and .0 5.. Referencing textures. and de-referenced by texture and surface load. but all information about layout. store. Texture. Retrieving the value of a named member via query instructions (txq. sampler. allowing them to be defined separately and combined at the site of usage in the program. and Surface Types PTX includes built-in “opaque” types for defining texture. field ordering. and query instructions. 2010 . but the pointer cannot otherwise be treated as an address.samplerref. In the independent mode. suld. hence the term “opaque”. since these properties are defined by . and overall size is hidden to a PTX program. sust. or surfaces via texture and surface load/store instructions (tex.e. Creating pointers to opaque variables using mov. accessing the pointer with ld and st instructions. PTX has two modes of operation.texref.{u32. texture and sampler information is accessed through a single .

mirror. linear wrap. Member width height depth Opaque Type Fields in Independent Texture Mode . Types. clamp_to_border N/A N/A N/A N/A N/A .texref values in elements in elements in elements 0. clamp_ogl. 1 nearest. clamp_to_edge. Member width height depth Opaque Type Fields in Unified Texture Mode .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. 1 ignored ignored ignored ignored . clamp_to_edge. clamp_ogl. State Spaces.texref values . mirror. 2010 35 .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. and Variables Table 9. linear wrap.Chapter 5. clamp_to_border 0.samplerref values N/A N/A N/A N/A nearest.

2010 .global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists.samplerref my_sampler_name. Example: .texref tex1. filter_mode = nearest }. these variables must be in the . . .param state space.PTX ISA Version 2.surfref my_surface_name. these variables are declared in the . When declared at module scope. Example: .global .global . the types may be initialized using a list of static expressions assigning values to the named members. . As kernel parameters.texref my_texture_name. 36 January 24. At module scope.global state space.global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global .

0}. 5.f64 is not allowed. This is a common case for three-dimensional grids.global . 2010 37 .u8 bg[4] = {0.f32 accel.v4 vector. In addition to fundamental types. .v2. and they may reside in the register space. 1. Predicate variables may only be declared in the register state space.2. Vectors Limited-length vector types are supported.v4.v2 . Examples: .0. for example. . Every variable must reside in one of the state spaces enumerated in the previous section.v4 . Variables In PTX. its type and size.f32 v0. PTX supports types for simple aggregate objects such as vectors and arrays. an optional initializer. Variable Declarations All storage for data is specified with variable declarations. where the fourth element provides padding. . Types.pred p. 0}. . // typedef . Three-element vectors may be handled by using a .reg . 5. // a length-4 vector of bytes By default.global .4. Vectors must be based on a fundamental type. textures. January 24. 0. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.reg . an optional array size.1. . and an optional fixed address for the variable. its name. State Spaces.f32 bias[] = {-1.shared .v4 .struct float4 coord. a variable declaration describes both the variable’s type and its state space. // a length-4 vector of floats .4.s32 i.global .Chapter 5. A variable declaration names the space in which the variable resides. Examples: . .v1.b8 v. etc. . 0.v2 or .struct float4 { . vector variables are aligned to a multiple of their overall size (vector length times base-type size).reg .global . r.u16 uv. q.u32 loc. // a length-2 vector of unsigned ints . Vectors cannot exceed 128-bits in length.global . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .const .v4.v4 .v3 }.f32 V.4. and Variables 5.

{0.s32 offset[][] = { {-1.0 5..f16 and .4.global . {0. being determined by an array initializer. Variable names appearing in initializers represent the address of the variable. .4.1}.u64.local . Initializers are allowed for all types except . where the variable name is followed by an equals sign and the initial value or values for the variable. . {0. // address of rgba into ptr Currently. Examples: .1.global .05}}. 2010 . 1} }.0.v4 . .4. . Here are some examples: ..shared .{. 0}. Array Declarations Array declarations are provided to allow the programmer to reserve space.global .1.. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). The size of the array specifies how many elements should be reserved.u16 kernel[19][19].global .. 0}.s32 n = 10.0}}.u32 or .u8 rgba[3] = {{1.global . 38 January 24. To declare an array.1. label names appearing in initializers represent the address of the next instruction following the label. or is left empty. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. 19*19 (361) halfwords are reserved (722 bytes).b32 ptr = rgba.PTX ISA Version 2.0.f32 blur_kernel[][] = {{. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.05.05}.1. Variables that hold addresses of variables or instructions should be of type . A scalar takes a single value.0}.u8 mailbox[128].pred. Similarly.. this can be used to statically initialize a pointer to a variable.3. -1}.0. For the kernel declaration above. {0. 5.1. this can be used to initialize a jump table to be used with indirect branches or calls. {1. . The size of the dimension is either a constant expression.4.0}.0.05..{. variable initialization is supported only for constant and global state spaces.

State Spaces. nor are initializers permitted.5. say one hundred. For example. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Types. …. and Variables 5. of . Rather than require explicit declaration of every name. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. These 100 register variables can be declared as follows: . Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. // declare %r0. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.b32 variables. .2..0.align 4 . %r99.Chapter 5.0.reg .0. 5. Elements are bytes.0. 2010 39 .6.0. The variable will be aligned to an address which is an integer multiple of byte-count. alignment specifies the address alignment for the starting address of the entire array.4.align byte-count specifier immediately following the state-space specifier. not for individual elements. January 24.const . %r1..0}. . it is quite common for a compiler frontend to generate a large number of register names. Alignment is specified using an optional . For arrays. suppose a program uses a large number. named %r0. The default alignment for scalar and array variables is to a multiple of the base-type size. Parameterized Variable Names Since PTX supports virtual registers. Examples: // allocate array at 4-byte aligned address.b32 %r<100>. Array variables cannot be declared this way. and may be preceded by an alignment specifier.4.. The default alignment for vector variables is to a multiple of the overall vector size. %r1.b8 bar[8] = {0.

2010 .0 40 January 24.PTX ISA Version 2.

The result operand is a scalar or vector variable in the register state space. Integer types of a common size are compatible with each other. as its job is to convert from nearly any data type to any other data type (and size). Instruction Operands 6. Instructions ld and st move data from/to addressable state spaces to/from registers. Predicate operands are denoted by the names p. The mov instruction copies data between registers.3. 2010 41 . The cvt (convert) instruction takes a variety of operand types and sizes. There is no automatic conversion between types. the sizes of the operands must be consistent. Each operand type must be compatible with the type determined by the instruction template and instruction type. mov. q.reg register state space. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. 6. st. r. Operand Type Information All operands in instructions have a known type from their declarations. For most operations.1. PTX describes a load-store machine. The ld. January 24. and cvt instructions copy data from one location to another. so operands for ALU instructions must all be in variables declared in the . s. and a few instructions have additional predicate source operands.Chapter 6. . 6. b. Most instructions have an optional predicate guard that controls conditional execution.2. Source Operands The source operands are denoted in the instruction descriptions by the names a. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The bit-size type is compatible with every type having the same size. and c.

. W.v4 .u32 42 January 24. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.reg . there is no support for C-style pointer arithmetic. Arrays. arrays. . The interesting capabilities begin with addresses. Examples include pointer arithmetic and pointer comparisons.gloal. .0 6.4. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.f32 ld.const . q.s32 tbl[256]. Here are a few examples: .PTX ISA Version 2.s32 mov.reg . and vectors.b32 p. 2010 . address register plus byte offset.u16 ld.u16 x. .v4. All addresses and address computations are byte-based.reg . Address expressions include variable names.shared .f32 W. Load and store operations move data between registers and locations in addressable state spaces. address registers. 6. and Vectors Using scalar variables as operands is straightforward.shared. The mov instruction can be used to move the address of a variable into a pointer. [V].const. tbl. The address is an offset in the state space in which the variable is declared. r0. [tbl+12].4. . .global .u16 r0.s32 q.v4 . and immediate address expressions which evaluate at compile-time to a constant address.reg .f32 V. The syntax is similar to that used in many assembly languages. ld.[x]. Using Addresses. p.1.

f32 a.f32 ld.global.c.global. mov.global. which may improve memory performance.g V. or a braceenclosed list of similarly typed scalars.reg . 2010 43 . it must be written as an address calculation prior to use. say {Ra. Vectors as Operands Vector operands are supported by a limited subset of instructions.global.c.3. a[1].b. Instruction Operands 6.a.y. c.v4. a[N-1]. .f32 {a. ld. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. // move address of a[1] into s 6.u32 {a. Array elements can be accessed using an explicitly calculated byte address.4. a[0].u32 s.u32 s. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. for use in an indirect branch or call.d}. . The size of the array is a constant in the program. and the identifier becomes an address constant in the space where the array is declared.r. . a register variable. and in move instructions to get the address of the label or function into a register. Examples are ld.f32 V. V2. . Elements in a brace-enclosed vector. If more complicated indexing is desired.u32 s.r V. ld.z V. where the offset is a constant expression that is either added or subtracted from a register variable. and tex. or by indexing into the array using square-bracket notation. [addr+offset2].x V.x. mov.a 6.b V.4. The expression within square brackets is either a constant integer. b.y V.v4 . . V.g. .b. Rc. Vectors may also be passed as arguments to called functions. The registers in the load/store operations can be a vector. as well as the typical color fields .Chapter 6. January 24.v2. A brace-enclosed list is used for pattern matching to pull apart vectors.z and . [addr+offset].4. Rb. Rd}. st.b and . which include mov.d}.2.v4. Vector elements can be extracted from the vector with the suffixes . Arrays as Operands Arrays of all types can be declared. d. Vector loads and stores can be used to implement wide loads and stores.w. or a simple “register with constant offset” expression.reg . Here are examples: ld.4.w = = = = V.

logic. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 44 January 24. if a cvt.s32.1. and ~131.PTX ISA Version 2.0 6. Type Conversion All operands to all arithmetic. the u16 is zero-extended to s32.5. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.u16 instruction is given a u16 source operand and s32 as a destination operand. For example.5. 2010 . and data movement instruction must be of the same type and size. except for operations where changing the size and/or type is part of the definition of the instruction.000 for f16). 6. Operands of different sizes or types must be converted prior to the operation.

cvt. f2u = float-to-unsigned.s16. zext = zero-extend.Chapter 6. f2f = float-to-float. Instruction Operands Table 11. January 24. chop = keep only low bits that fit. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.u32 targeting a 32-bit register will first chop to 16-bits. f2s = float-to-signed. u2f = unsigned-to-float. The type of extension (sign or zero) is based on the destination format. 2010 45 . the result is extended to the destination register width after chopping. s2f = signed-to-float. Notes 1 If the destination register is wider than the destination format. then sign-extend to 32-bits. For example.

0 6. choosing even integer if source is equidistant between two integers. Modifier . Rounding Modifiers Conversion instructions may specify a rounding modifier.2. In PTX.rpi Integer Rounding Modifiers Description round to nearest integer.rni .PTX ISA Version 2. Modifier .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.5.rzi . 2010 .rn . The following tables summarize the rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rm .rmi . there are four integer rounding modifiers and four floating-point rounding modifiers. Table 12.rz .

first access is high Notes January 24. The register in a store operation is available much more quickly. Instruction Operands 6.6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Much of the delay to memory can be hidden in a number of ways. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. 2010 47 . while global memory is slowest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Table 14.Chapter 6. Registers are fastest. Table 11 gives estimates of the costs of using different kinds of memory. Another way to hide latency is to issue the load instructions as early as possible. Operand Costs Operands from different state spaces affect the speed of an operation.

PTX ISA Version 2.0 48 January 24. 2010 .

Chapter 7. implicitly saving the return address. and is represented in PTX as follows: . Abstracting the ABI Rather than expose details of a particular calling convention. Function declarations and definitions In PTX.1. we describe the features of PTX needed to achieve this hiding of the ABI. functions are declared and defined using the . stack layout.func directive. A function definition specifies both the interface and the body of the function. NOTE: The current version of PTX does not implement the underlying. } … call foo. These include syntax for function definitions. At the call. together these specify the function’s interface. or prototype. and Application Binary Interface (ABI). and return values may be placed directly into register variables. Scalar and vector base-type input and return parameters may be represented simply as register variables. so recursion is not yet supported.func foo { … ret. execution of the call instruction transfers control to foo. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. 7. A function must be declared or defined prior to being called. support for variadic functions (“varargs”). Execution of the ret instruction within foo transfers control to the instruction following the call. The simplest function has no parameters or return values. and memory allocated on the stack (“alloca”). In this section. the function name. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. parameter passing. stack-based ABI. arguments may be register variables or constants. and an optional list of input parameters. 2010 49 . function calls. January 24. … Here. A function declaration specifies an optional list of return parameters.

%rc1.param.4).reg .b8 . 50 January 24.b8 [py+11].param. [y+10]. .s32 x.param space memory.reg .param. this structure will be flattened into a byte array. ret. … st.b8 [py+10].reg space.c2. %rc2. … … // computation using x.f64 f1.s32 out) bar (.reg .b8 [py+ 9]. c3. [y+0].c4. note that . st.u32 %inc ) { add.reg . bumpptr. st.u32 %res.b64 [py+ 0]. The . In PTX.param. // scalar args in . ld. … ld. %inc.PTX ISA Version 2. ld. ld. . (%r1. a .param space variables are used in two ways.param. [y+9]. %rc1.align 8 py[12]. For example. … In this example. byte array in . %rd. a . } … call (%r1).reg . inc_ptr.param space call (%out).b32 c1. }.param.u32 %res) inc_ptr ( .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.0 Example: . First. c2.b8 .align 8 y[12]) { . 2010 .param variable y is used in function definition bar to represent a formal parameter.b8 c1. char c[4]. st.f1.b8 c2. ld. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . [y+11]. passed by value to a function: struct { double dbl.b8 [py+ 8]. c4. . } { . [y+8].b8 c4. (%x.c3.reg .c1.func (.reg .func (.f64 f1. %ptr.param . %rc2.param. consider the following C structure.param state space is used to pass the structure by value: .f64 field are aligned.param.u32 %ptr. Second. py).param. Since memory accesses are required to be aligned to a multiple of the access size.param . st.b8 c3.param.

reg or .param space byte array with matching type.param instructions used for argument passing must be contained in the basic block with the call instruction. or a constant that can be represented in the type of the formal parameter. Note that the choice of . In the case of . The following restrictions apply to parameter passing. In the case of .reg state space can be used to receive and return base-type scalar and vector values. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. Supporting the . size. 2010 51 .param space formal parameters that are byte arrays. Abstracting the ABI The following is a conceptual way to think about the . or 16 bytes.param byte array is used to collect together fields of a structure being passed by value. Typically. • The . 2.Chapter 7. For .reg variables.param variables..reg state space in this way provides legacy support. . the corresponding argument may be either a . the argument must also be a . size. or constants.reg space formal parameters. For a caller.param or . The . and alignment of parameters.param memory must be aligned to a multiple of 1.param and ld. • • • Input and return parameters may be .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg space variable with matching type and size. a .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. Parameters in . • • • For a callee. 8. January 24.param state space use in device functions.param arguments.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. • The . • • Arguments may be . all st.g.param variables or . and alignment.param space formal parameters that are base-type scalar or vector variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. For a caller. For a callee. A .param state space is used to receive parameter values and/or pass return values back to the caller. This enables backend optimization and ensures that the .reg space variable of matching type and size.reg variables. the corresponding argument may be either a . The .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. or a constant that can be represented in the type of the formal parameter.param or . In the case of . 4.param argument must be declared within the local scope of the caller.

x supports multiple return values for this purpose. formal parameters were restricted to . Changes from PTX 1. formal parameters may be in either . For sm_2x targets.1.0. 2010 . and there was no support for array parameters.0 continues to support multiple return registers for sm_1x targets. PTX 2.PTX ISA Version 2. Objects such as C structures were flattened and passed or returned using multiple registers.reg or .0 7.param byte array should be used to return objects that do not fit into a register.x.param space parameters support arrays. 52 January 24. In PTX ISA version 2. PTX 2.0 restricts functions to a single return value. and .x In PTX ISA version 1.param state space. PTX 1.1.reg state space. and a .

%va_end is called to free the variable argument list handle. bra Loop.u32 sz.reg .s32 result ) maxN ( .2. 0x8000000.h and varargs.pred p. ) { . // default to MININT mov. 4. 2. or 4 bytes. %r1. (2. For %va_arg.func ( . . The function prototypes are defined as follows: .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32. mov.reg .reg . PTX provides a high-level mechanism similar to the one provided by the stdarg. %va_arg.u32 b.ge p.u32 ptr) %va_start . %r3).reg . variadic functions are declared with an ellipsis at the end of the input parameter list.func (.u32 sz. N. maxN.reg . . Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . %va_start. To support functions with a variable number of arguments. 2. ret.u32 align) .b32 ctr. (ap). (3.. %r2. ctr. maxN. (ap. .u32 align) . setp. ctr. call (ap).u32 ap. bra Done.b64 val) %va_arg64 (. … call (%max).s32 result. result. In both cases.reg .reg . and end access to a list of variable arguments.h headers in C.func %va_end (. or 8 bytes. the size may be 1.reg ..func (.reg . call %va_end. %s1.b32 result. 0. for %va_arg64. 2010 53 . 2. This handle is then passed to the %va_arg and %va_arg64 built-in functions. or 16 bytes.reg . Once all arguments have been processed. following zero or more fixed parameters: . 8.reg .func baz ( . iteratively access.u32 ptr.reg .u32 a. … %va_start returns Loop: @p Done: January 24.u32 ptr.s32 val. } … call (%max).b32 val) %va_arg (. along with the size and alignment of the next data value to be accessed.reg . In PTX. val. the size may be 1.reg . … ) . .u32 N. .reg . . max. Abstracting the ABI 7. . call (val). Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . 4. %s2). the alignment may be 1.reg . 4). 4.func (.Chapter 7. .func okay ( … ) Built-in functions are provided to initialize.

2010 .local and st.local instructions. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. The array is then accessed with ld.u32 ptr ) %alloca ( .3.PTX ISA Version 2.func ( . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. To allocate memory. 54 January 24. Alloca NOTE: The current version of PTX does not support alloca.reg . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.reg .0 7. If a particular alignment is required. defined as follows: .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. a function simply calls the built-in function %alloca.

the semantics are described. // p = (a < b). A. We use a ‘|’ symbol to separate multiple destination registers. Format and Semantics of Instruction Descriptions This section describes each PTX instruction.2. opcode A. For instructions that create a result value. opcode D. 2010 55 . A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.s32. and C are the source operands. q = !(a < b). January 24.Chapter 8. A. setp. opcode D. a. A. b. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. B. Instruction Set 8. while A.lt p|q. opcode D. PTX Instructions PTX instructions generally have from zero to four operands. In addition to the name and the format of the instruction. B. B. followed by some examples that attempt to show several possible instantiations of the instruction. C. The setp instruction writes two destination registers. the D operand is the destination operand.1. 8. For some instructions the destination operand is optional.

add.pred as the type specifier. j. optionally negated. Instructions without a guard predicate are executed unconditionally. add. As an example.0 8. the following PTX instruction sequence might be used: @!p L1: setp. j. // p = (i < n) // if i < n. predicate registers are virtual and have . r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. use a predicate to control the execution of the branch or call instructions. branch over 56 January 24.s32 p.s32 p. consider the high-level code if (i < n) j = j + 1. Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 j. So. add 1 to j To get a conditional branch or conditional function call. 1. Predicated Execution In PTX.reg .PTX ISA Version 2.pred p. q. To implement the above example as a true conditional branch. 1.lt. n.lt. i. where p is a predicate variable. n.s32 j. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. This can be written in PTX as @p setp. predicate registers can be declared as . i.3. … // compare i to n // if false. 2010 . bra L1.

lt.3. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).1. Table 15. and hs (higher-or-same).1. ordering comparisons are not defined for bit-size types. and bitsize types. The unsigned comparisons are eq. lt (less-than). unsigned integer. If either operand is NaN. ge. the result is false.1. ne. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. le (less-than-or-equal). le. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. The following table shows the operators for signed integer. hi (higher). 2010 57 .2.3. gt (greater-than). lo (lower). Comparisons 8. ne (not-equal). The bit-size comparisons are eq and ne. ls (lower-or-same). Instruction Set 8. Table 16. Unsigned Integer. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. ne.Chapter 8. gt.3. and ge (greater-than-or-equal).1.

and no direct way to load or store predicate register values. If both operands are numeric values (not NaN).1. xor. 2010 . Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. However. two operators num (numeric) and nan (isNaN) are provided. leu. setp can be used to generate a predicate from an integer. for example: selp.0.3. Table 18. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. Table 17. There is no direct conversion between predicates and integer values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.%p. not. then the result of these comparisons is true. and mov. unordered versions are included: equ. or. ltu.u32 %r1.2. num returns true if both operands are numeric values (not NaN). If either operand is NaN. // convert predicate to 32-bit value 58 January 24. then these comparisons have the same result as their ordered counterparts.0 To aid comparison operations in the presence of NaN values. geu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.PTX ISA Version 2. neu. and nan returns true if either operand is NaN. gtu.

bX . unsigned.u16 a. It requires separate type-size modifiers for the result and source. Table 19. float. cvt.u16 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction..reg . a. Example: . a.u16 d. For example: .bX .u16 d.Chapter 8.fX ok inv inv ok Instruction Type . Signed and unsigned integer types agree provided they have the same size. For example.reg .reg . most notably the data conversion instruction cvt. and this information must be specified as a suffix to the opcode. the add instruction requires type and size information to properly perform the addition operation (signed.fX ok ok ok ok January 24.uX ok ok ok inv . Floating-point types agree only if they have the same size. they must match exactly. For example. 2010 59 . different sizes). and integer operands are silently cast to the instruction type if needed. i.sX . • The following table summarizes these type checking rules. . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.e.sX ok ok ok inv . Instruction Set 8.f32 d. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. b. add.uX . and these are placed in the same order as the operands. a. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.f32.4. Type Checking Rules Operand Type . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. b.

Floating-point source registers can only be used with bit-size or floating-point instruction types. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. the data will be truncated. When used with a narrower bit-size type.PTX ISA Version 2. stored. When used with a floating-point instruction type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Table 20. Source register size must be of equal or greater size than the instruction-type size. Note that some combinations may still be invalid for a particular instruction. so those rows are invalid for cvt. For example. no conversion needed. Notes 3. When a source operand has a size that exceeds the instruction-type size. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 2010 . 2.bX instruction types. Operand Size Exceeding Instruction-Type Size For convenience. 1.0 8. Bit-size source registers may be used with any appropriately-sized instruction type. or converted to other types and sizes. so that narrow values may be loaded. parse error. unless the operand is of bit-size type. ld. inv = invalid. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. the size must match exactly. The following table summarizes the relaxed type-checking rules for source operands. the cvt instruction does not support . “-“ = allowed. 4. st. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. for example. stored. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. The data is truncated to the instruction-type size and interpreted according to the instruction type. floating-point instruction types still require that the operand type-size matches exactly.4. 60 January 24. and converted using regular-width registers.1. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.

the data will be zero-extended. parse error. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type.Chapter 8. the data is zeroextended. the data is sign-extended. 4. If the corresponding instruction type is signed integer. zext = zero-extend. otherwise. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. 2. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. When used with a narrower bit-size instruction type. The data is sign-extended to the destination register width for signed integer instruction types. When used with a floatingpoint instruction type. Bit-size destination registers may be used with any appropriately-sized instruction type. January 24.or sign-extended to the size of the destination register. Notes 3. Floating-point destination registers can only be used with bit-size or floating-point instruction types. The following table summarizes the relaxed type-checking rules for destination operands. The data is signextended to the destination register width for signed integer instruction types. inv = Invalid. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Destination register size must be of equal or greater size than the instruction-type size. the destination data is zero. 2010 61 . “-“ = Allowed but no conversion needed. 1. Table 21. and is zero-extended to the destination register width otherwise. the size must match exactly.

If threads execute down different control flow paths. 2010 . Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. and 16-bit computations are “promoted” to 32-bit computations. At the PTX language level. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. conditional function call. A compiler or programmer may chose to enforce portable. 8. 8. the threads are called divergent. However.PTX ISA Version 2. Both situations occur often in programs. a compiler or code author targeting PTX can ignore the issue of divergent threads.1.5. for many performance-critical applications. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. or conditional return.0 8. 62 January 24. for example. at least in appearance. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. so it is important to have divergent threads re-converge as soon as possible. the semantics of 16-bit instructions in PTX is machine-specific. and for many applications the difference in execution is preferable to limiting performance. until C is not expressive enough. If all of the threads act in unison and follow a single control flow path. using the . until they come to a conditional control construct such as a conditional branch.uni suffix. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. the optimizing code generator automatically determines points of re-convergence. this is not desirable. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers.6. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. by a right-shift instruction. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. Therefore. Divergence of Threads in Control Constructs Threads in a CTA execute together. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. When executing on a 32-bit data path. The semantics are described using C. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. 16-bit registers in PTX are mapped to 32-bit physical registers.6. the threads are called uniform. These extra precision bits can become visible at the application level. For divergent control flow.

subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 8.Chapter 8.7.1. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. In the following descriptions. The Integer arithmetic instructions are: add sub add.cc. 2010 63 . Instructions All PTX instructions may be predicated.cc. Instruction Set 8. addc sub.7. the optional guard predicate is omitted from the syntax.

sub. b. PTX ISA Notes Target ISA Notes Examples Table 23.b.s32.type = { .. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.type = { . // . . . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.z. Description Semantics Notes Performs addition and writes the resulting value into a destination register. d = a + b.s64 }.y.sat limits result to MININT.s32 . b.sat limits result to MININT. add. . Introduced in PTX ISA version 1. Applies only to . Supported on all target architectures.s32 type. PTX ISA Notes Target ISA Notes Examples 64 January 24.0 Table 22. b.c.MAXINT (no overflow) for the size of the operation.. .sat}.type add{. Introduced in PTX ISA version 1. . a.u64. a. 2010 . // . d = a – b. Saturation modifier: .0.s32 d. add. add Syntax Integer Arithmetic Instructions: add Add two values. d. .s32.s32 c. a. a.u32.sat applies only to .u16.s16. Applies only to .sat.u32 x. Saturation modifier: .sat}.u16. Supported on all target architectures.sat applies only to .s32 d.0.s16.s32 .s32 type.type sub{. d.s32 c. sub. .PTX ISA Version 2.s64 }.1.u64.u32. . b.MAXINT (no overflow) for the size of the operation. @p add. . .a.

b32 addc.b32 x1.cc. Introduced in PTX ISA version 1.cc.y2. No saturation.2.cc. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. sub.CF) holding carry-in/carry-out or borrowin/borrow-out. x4. No saturation. add. if . . . No other instructions access the condition code.cc Syntax Integer Arithmetic Instructions: add.z3.u32. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.b32 addc. x3. x2. or testing the condition code. clearing.s32 }.z4. a.y1. carry-out written to CC.y4.cc. Behavior is the same for unsigned and signed integers. 2010 65 . addc.cc. . x4. Supported on all target architectures.cc Add two values with carry-out.b32 addc. Table 24.CF No integer rounding modifiers.y3. d = a + b + CC. .y1. a. b.2. Introduced in PTX ISA version 1.b32 addc.b32 addc.b32 x1.cc}.s32 }.u32.CF. Behavior is the same for unsigned and signed integers.z4.z1. add.y3.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. b.y2.type = {.type = { . @p @p @p @p add.CF No integer rounding modifiers. Supported on all target architectures.cc. @p @p @p @p add.z1.type d. d = a + b. x2. and there is no support for setting.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.type d.z3. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.b32 addc.y4. addc{.z2.cc specified.cc.cc. Instruction Set Instructions add.cc.Chapter 8. These instructions support extended-precision integer addition and subtraction. carry-out written to CC. x3.z2.

cc.z3.cc.cc Subract one value from another.b32 subc.z4.z1.z4. b.b32 x1. Introduced in PTX ISA version 1. Supported on all target architectures.y4. if . .z2.PTX ISA Version 2.cc. Behavior is the same for unsigned and signed integers.y1.z1. a.(b + CC. . Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. Supported on all target architectures.3.z3.cc. d = a .cc. borrow-out written to CC.b32 subc. sub. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. No saturation.cc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. x2. .y3. x3.cc specified.y1.type = { .type = {.s32 }. x4.s32 }. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.b32 subc. withborrow-in and optional borrow-out.cc. x2.y4. .b32 subc. 2010 .3.u32.y2.CF No integer rounding modifiers. b. a. with borrow-out. d = a – b.CF No integer rounding modifiers.z2.CF).type d. Introduced in PTX ISA version 1.b32 x1. No saturation.type d. x4.b32 subc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.y3.0 Table 26. sub. x3. subc{.b32 subc. Behavior is the same for unsigned and signed integers.cc}.cc.cc. borrow-out written to CC. @p @p @p @p sub.u32.y2.cc Syntax Integer Arithmetic Instructions: sub. @p @p @p @p sub.

If . n = bitwidth of type.lo. Instruction Set Table 28.s64 }.u64.hi. mul.s32 z.n>. // 16*16 bits yields 32 bits // 16*16 bits. d = t. creates 64 bit result January 24. . and either the upper or lower half of the result is written to the destination register. Description Semantics Compute the product of two values. d = t<2n-1.fys. then d is twice as wide as a and b to receive the full result of the multiplication. a.u32. .s16 fa.y.lo.fys. . save only the low 16 bits // 32*32 bits.type = { . .hi or .type d. mul.. . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.s32. // for .s16 fa. t = a * b..lo variant Notes The type of the operation represents the types of the a and b operands.0. If .fxs.lo is specified. Supported on all target architectures. mul{.wide is specified.s16.wide. b.. The .Chapter 8.wide.fxs. 2010 67 .u16. . then d is the same size as a and b.wide suffix is supported only for 16.x. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..and 32-bit integer types.wide}. d = t<n-1. mul.wide // for .hi variant // for .0>.

. If ..lo variant Notes The type of the operation represents the types of the a and b operands.hi variant // for .and 32-bit integer types. b. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. b.MAXINT (no overflow) for the size of the operation. a.s16. . If . t + c.hi mode. 68 January 24.0.sat. . .c.type = { .sat limits result to MININT.hi or .lo.r.0> + c. Description Semantics Multiplies two values and adds a third.. and either the upper or lower half of the result is written to the destination register. .hi. d.q.s32 r. mad. t<n-1. // for . 2010 .wide suffix is supported only for 16. a. t<2n-1. mad{.wide // for .b.hi. Supported on all target architectures.s32 type in . Saturation modifier: . then d and c are twice as wide as a and b to receive the result of the multiplication.wide}.type mad. bitwidth of type. ..lo. Applies only to .n> + c. @p mad.s64 }..u64.lo is specified.u16.s32 d.wide is specified. t n d d d = = = = = a * b. then d and c are the same size as a and b.a.lo. and then writes the resulting value into a destination register. The . c. c.p.s32 d.PTX ISA Version 2.u32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32.0 Table 29..

lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. January 24.. . and return either the high or low 32-bits of the 48-bit result. d = t<31. mul24{. // for . Instruction Set Table 30.type = { . mul24.b. d = t<47.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. t = a * b.Chapter 8. // low 32-bits of 24x24-bit signed multiply.u32..0.hi. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.hi may be less efficient on machines without hardware support for 24-bit multiply. mul24..0>. All operands are of the same type and size.lo. .16>.hi variant // for . i. 48bits.type d. a.s32 }. mul24.e.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.lo}. mul24. Supported on all target architectures.a. 2010 69 . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d.

d = t<47.0> + c. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. 2010 . d = t<31.16> + c. mad24. t = a * b.hi. All operands are of the same type and size.hi variant // for . b.type mad24.hi.0 Table 31. 70 January 24. b. Return either the high or low 32-bits of the 48-bit result.0.s32 }.PTX ISA Version 2.s32 d. .lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. .lo}.sat. 32-bit value to either the high or low 32-bits of the 48-bit result.hi mode. a...lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.sat limits result of 32-bit signed addition to MININT.e. Description Compute the product of two 24-bit integer values held in 32-bit source registers.a.. Applies only to . mad24.type = { . c.lo. and add a third. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b. a. Supported on all target architectures.s32 type in .c.s32 d. mad24. 48bits. mad24{.MAXINT (no overflow).hi may be less efficient on machines without hardware support for 24-bit multiply.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. Saturation modifier: . d. i. // for . // low 32-bits of 24x24-bit signed multiply. mad24..u32. c.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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} Introduced in PTX ISA version 2. a = a >> 1. 2010 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 PTX ISA Notes Target ISA Notes Examples Table 40.b32.b32 type. cnt. } while (d < max && (a&mask == 0) ) { d++.b64 d. d = 0. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. . . popc. inclusively. a. popc.type == . d = 0.type d.u32 Semantics 74 January 24. For . X. a = a << 1. clz. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. a.b32.b64 }. while (a != 0) { if (a&0x1) d++.b64 d.PTX ISA Version 2.b64 }. popc Syntax Integer Arithmetic Instructions: popc Population count.b32 clz.b64 type. // cnt is . } else { max = 64. mask = 0x8000000000000000. For . if (. mask = 0x80000000. // cnt is . cnt. inclusively.b32) { max = 32. popc requires sm_20 or later. X. clz requires sm_20 or later.b32 popc. .0 Table 39. the number of leading zeros is between 0 and 64.0. . a.type = { .0. a. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. clz.type d.type = { . the number of leading zeros is between 0 and 32.

X. . break. .0. For unsigned integers.shiftamt. bfind. Semantics msb = (.u32 d. bfind returns 0xFFFFFFFF if no non-sign bit is found.shiftamt is specified. a. a. . Description Find the bit position of the most significant non-sign bit in a and place the result in d. // cnt is .d.type==. bfind requires sm_20 or later.s64 cnt. and operand d has type .s32. i>=0.u32. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.type==.type = { . bfind. d. .shiftamt && d != -1) { d = msb .s32) ? 31 : 63.u64. Instruction Set Table 41. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.shiftamt. Operand a has the instruction type.type bfind.u32 January 24.u32.Chapter 8. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type d. i--) { if (a & (1<<i)) { d = i. For signed integers.u32 || . for (i=msb. a. bfind returns the bit position of the most significant “1”. bfind. d = -1.s64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If . } } if (. 2010 75 .

.b64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i++) { d[i] = a[msb-i].b32) ? 31 : 63. brev.0 Table 42. a.type = { .b32. . brev requires sm_20 or later.type==. for (i=0. i<=msb. Description Semantics Perform bitwise reversal of input.type d.0. brev.b32 d. a. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. 2010 . msb = (.PTX ISA Version 2. 76 January 24.

bfe. d = 0. len = c.start. 2010 77 . The sign bit of the extracted field is defined as: .s32. c. for (i=0.u64: .u32 || . Description Extract bit field from a and place the zero or sign-extended result in d.s64 }. and source c gives the bit field length in bits. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.type = { . . Operands a and d have the same type as the instruction type.msb)]. . January 24. . b.len.u32 || . Semantics msb = (. . otherwise If the bit field length is zero. . If the start position is beyond the msb of the input. .type==. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.u32.u32.s32. else sbit = a[min(pos+len-1. i<=msb.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. Source b gives the bit field starting bit position. the destination d is filled with the replicated sign bit of the extracted field. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Instruction Set Table 43.Chapter 8.u64.u32.type==.u64 || len==0) sbit = 0. if (.s32) ? 31 : 63. a. and operands b and c are type . bfe.type==. pos = b.b32 d.a.type==.type d. bfe requires sm_20 or later.0. The destination d is padded with the sign bit of the extracted field. the result is zero.

If the start position is beyond the msb of the input.type = { . 78 January 24. bfi. and operands c and d are type .a. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. . Operands a.b32. i<len && pos+i<=msb. If the bit field length is zero. the result is b. pos = c.b64 }. len = d.b32) ? 31 : 63. the result is b. and place the result in f.type==.0.b32 d. bfi. f = b.type f. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.PTX ISA Version 2. Semantics msb = (. b. and source d gives the bit field length in bits. .0 Table 44. Description Align and insert a bit field from a into b. 2010 .u32. c.start. bfi requires sm_20 or later. i++) { f[pos+i] = a[i]. a.b. and f have the same type as the instruction type. for (i=0. d. b.len. Source c gives the starting bit position for the insertion.

default mode index d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.mode} d. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).rc16 }. b0}}. b2. b. b6.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. Instruction Set Table 45. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. The bytes in the two source registers are numbered from 0 to 7: {b.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. The msb defines if the byte value should be copied. Thus. a} = {{b7. a 4-bit selection value is defined. msb=1 means replicate the sign.b4e. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.rc8. and reassemble them into a 32-bit destination register. the four 4-bit values fully specify an arbitrary byte permute.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. In the generic form (no mode specified). Description Pick four arbitrary bytes from two 32-bit registers. 2010 79 . b4}.ecl. as a 16b permute code.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.Chapter 8. msb=0 means copy the literal value.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b2 source select c[11:8] d. b1. Note that the sign extension is only performed as part of generic form.mode = { . . b5. .ecr.b3 source select c[15:12] d. a. . For each byte in the target register. .f4e. c.b32{. {b3.b1 source select c[7:4] d. the permute control consists of four 4-bit selection values. . . prmt.

b32. prmt requires sm_20 or later. r1. 80 January 24.PTX ISA Version 2. ctl[1]. tmp[31:24] = ReadByte( mode. ctl[2]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[0].0. tmp[23:16] = ReadByte( mode. ctl[3].0 Semantics tmp64 = (b<<32) | a. ctl[1] = (c >> 4) & 0xf. r2. tmp[15:08] = ReadByte( mode. tmp64 ).f4e r1. ctl[3] = (c >> 12) & 0xf. tmp64 ). } tmp[07:00] = ReadByte( mode. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r2. prmt. tmp64 ). r4. r3. 2010 . r3.b32 prmt. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r4. tmp64 ). ctl[2] = (c >> 8) & 0xf.

7. Floating-Point Instructions Floating-point instructions operate on .f32 and .Chapter 8.f64 register operands and constant immediate values.2. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Instruction Set 8. 2010 81 .

f64 {sin.lg2.ex2}.approx. Table 46.f64 are the same.32 and fma. 1.0 The following table summarizes floating-point instructions in PTX. with NaNs being flushed to positive zero.f32 {div.rp .f32 {div. The optional .cos. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f32 {abs.0.f32 {div.target sm_20 .sub.sat Notes If no rounding modifier is specified.mul}.max}.max}.f64 rsqrt. mul.f32 rsqrt. Instruction Summary of Floating-Point Instructions . {mad.sub. but single-precision instructions return an unspecified NaN.rn .f64 mad.rnd. .min.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. default is .rnd. sub.ftz .rnd.target sm_1x No rounding modifier. Note that future implementations may support NaN payloads for single-precision instructions. so PTX programs should not rely on the specific single-precision NaNs being generated.rn and instructions may be folded into a multiply-add. 2010 .rnd. {add.approx. NaN payloads are supported for double-precision instructions.rnd.f32 are the same.neg. No rounding modifier. . 82 January 24.fma}.0].rnd.rcp.PTX ISA Version 2.sqrt}.rz .approx.rn and instructions may be folded into a multiply-add.f64 div.fma}.sqrt}. Single-precision add.approx. If no rounding modifier is specified.rm .mul}.f64 {abs. default is .min.full. Double-precision instructions support subnormal inputs and results.f32 {mad.f64 and fma.neg.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. and mad support saturation of results to the range [0.rcp.f32 .ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.rcp.sqrt}.target sm_20 mad.f32 {add.

C.normal testp. Table 48. . copysign. not infinity) As a special case.f64 x. A. X. and return the result as d.finite.pred = { .op p.infinite. not infinity). testp. . Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. testp requires sm_20 or later.f32.type .f32. January 24. 2010 83 .f64 }. b.notanumber. copysign requires sm_20 or later.type = { . Introduced in PTX ISA version 2.infinite testp.f32 copysign.subnormal }.f32 testp. B. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.notanumber testp.0.f64 isnan. y.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.finite testp.f64 }. testp.Chapter 8. positive and negative zero are considered normal numbers. testp.op. . // result is .type = { .number.infinite. testp Syntax Floating-Point Instructions: testp Test floating-point property.notanumber.normal. z. a. . copysign.number testp. . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.0. f0. p. Instruction Set Table 47. true if the input is a subnormal number (not NaN.type d. . . a.

84 January 24. .f3.ftz}{. add. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.rp for add.rz. .f32.ftz. . Rounding modifiers have the following target requirements: . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rnd = { .rnd}.0].ftz.rn): .f64. d. requires sm_20 Examples @p add.0.f64 requires sm_13 or later. b.f64 supports subnormal numbers. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. .f32 clamps the result to [0. d = a + b.rm. add{. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. add.rp }.0 Table 49.0f. 2010 . b. subnormal numbers are supported. Saturation modifier: . .rm mantissa LSB rounds towards negative infinity .PTX ISA Version 2. .rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero. Description Semantics Notes Performs addition and writes the resulting value into a destination register.sat}. add. a.f32 f1. add. sm_1x: add. add Syntax Floating-Point Instructions: add Add two values.rn.rn mantissa LSB rounds to nearest even . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.0. NaN results are flushed to +0.f32 add{.f32 flushes subnormal inputs and results to sign-preserving zero.rm.sat.f2. add.rz.rz available for all targets . Rounding modifiers (default is .f32 supported on all target architectures. In particular.f64 d. requires sm_13 for add.rnd}{. a.

rp }.rp for sub. .sat}. .rz mantissa LSB rounds towards zero . . sub.f32 c.f32 clamps the result to [0. Saturation modifier: sub.0.ftz}{. d. sub{.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.rn mantissa LSB rounds to nearest even .b.rm.rn. 2010 85 .a.ftz.rm.rnd}{. sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. Rounding modifiers (default is . sm_1x: sub.rn.b. a. b.0f. .f64 supports subnormal numbers. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . b.rm mantissa LSB rounds towards negative infinity . . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. NaN results are flushed to +0.f64 requires sm_13 or later.f3.0. subnormal numbers are supported.rnd = { .f32 sub{. requires sm_13 for sub. 1.rnd}. sub Syntax Floating-Point Instructions: sub Subtract one value from another.0]. sub.rn): . Instruction Set Table 50. requires sm_20 Examples sub. In particular.f32.f32 supported on all target architectures. January 24.f2.sat.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Rounding modifiers have the following target requirements: .rn.rz available for all targets .ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f64. d = a .f32 f1. sub. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sub.Chapter 8. a.

2010 . requires sm_13 for mul.rnd}{. .0.0.ftz}{. mul.f64.ftz. sm_1x: mul.rm mantissa LSB rounds towards negative infinity .rm.f32 circumf. . d. . Description Semantics Notes Compute the product of two values. a.sat}.rz.f32 supported on all target architectures. .rp }.ftz. mul.rnd = { .rn. b.sat. subnormal numbers are supported. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. mul.f64 requires sm_13 or later.pi // a single-precision multiply 86 January 24. requires sm_20 Examples mul.f32 flushes subnormal inputs and results to sign-preserving zero.radius. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. NaN results are flushed to +0. For floating-point multiplication. mul.f32. .rnd}.rn.0 Table 51.f64 supports subnormal numbers. . a.PTX ISA Version 2.f64 d.f32 mul{.rn): .rn mantissa LSB rounds to nearest even .0]. 1. all operands must be the same size.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. mul{. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Rounding modifiers have the following target requirements: . Saturation modifier: mul. mul Syntax Floating-Point Instructions: mul Multiply two values.rp for mul.rm.f32 flushes subnormal inputs and results to sign-preserving zero. b.rz available for all targets .rz mantissa LSB rounds towards zero . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. In particular. d = a * b. Rounding modifiers (default is .f32 clamps the result to [0.0f.

a.ftz}{. .sat}.Chapter 8.rp }.rz. The resulting value is then rounded to single precision using the rounding mode specified by . subnormal numbers are supported. sm_1x: fma.0.f64 computes the product of a and b to infinite precision and then adds c to this product.rm. Saturation: fma.f32 requires sm_20 or later. fma.a.f64 d. 2010 87 .rn.x. .f64 supports subnormal numbers.rnd = { . Instruction Set Table 52.0f. @p fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.z.rm mantissa LSB rounds towards negative infinity . NaN results are flushed to +0. fma.rn. fma. . fma Syntax Floating-Point Instructions: fma Fused multiply-add.f32 is unimplemented in sm_1x. 1.4.0].f64 w. d = a*b + c.rnd{.0. fma.f32 fma. . b.f64.ftz. fma. b.rnd. a. c.f64 introduced in PTX ISA version 1. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f32 flushes subnormal inputs and results to sign-preserving zero.rn mantissa LSB rounds to nearest even .c. PTX ISA Notes Target ISA Notes Examples January 24.f64 requires sm_13 or later.rnd.f32 fma.f32 clamps the result to [0. fma. again in infinite precision.sat. d.rz mantissa LSB rounds towards zero .f32 introduced in PTX ISA version 2. Rounding modifiers (no default): .rnd.f64 is the same as mad. fma. again in infinite precision. fma.f32 computes the product of a and b to infinite precision and then adds c to this product.ftz. fma.y. c.b. The resulting value is then rounded to double precision using the rounding mode specified by . d.rn. fma.

rnd.f64 computes the product of a and b to infinite precision and then adds c to this product. 2010 .rp }. c. a.0]. and then the mantissa is truncated to 23 bits. 1. again in infinite precision. In this case. the treatment of subnormal inputs and output follows IEEE 754 standard. fma. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. mad.rm. mad.ftz}{.f32).f64 d. again in infinite precision.sat.sat}.0 devices.f32 is implemented as a fused multiply-add (i.f32 is when c = +/-0.ftz.. // .sat}.{f32.target sm_20: mad. mad. Saturation modifier: mad. NaN results are flushed to +0. When JIT-compiled for SM 2.{f32.rz mantissa LSB rounds towards zero .f32 mad. again in infinite precision.f64}. subnormal numbers are supported. For .rn. // .rnd{. b. The exception for mad. mad.target sm_20 d.target sm_1x d. .f32.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. but the exponent is preserved.f32 flushes subnormal inputs and results to sign-preserving zero. d = a*b + c. sm_1x: mad.rm mantissa LSB rounds towards negative infinity .rn mantissa LSB rounds to nearest even . Unlike mad. .rz. mad.f64 supports subnormal numbers.target sm_13 and later . Note that this is different from computing the product with mul. mad. b. mad{.ftz}{.rnd. The resulting value is then rounded to single precision using the rounding mode specified by . mad. .f32 clamps the result to [0.f32 mad. For .rnd = { . // .f32 flushes subnormal inputs and results to sign-preserving zero.0.f64 is the same as fma. where the mantissa can be rounded and the exponent will be clamped.e. The resulting value is then rounded to double precision using the rounding mode specified by .0.rn. c. Rounding modifiers (no default): .target sm_1x: mad.f32 is identical to the result computed using separate mul and add instructions. mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Description Semantics Notes Multiplies two values and adds a third. a. c.f64.f32 computes the product of a and b at double precision.rnd. and then writes the resulting value into a destination register. 88 January 24.f64} is the same as fma.ftz. b.f64 computes the product of a and b to infinite precision and then adds c to this product. The resulting value is then rounded to double precision using the rounding mode specified by .0 Table 53.PTX ISA Version 2.rnd. mad.f32 computes the product of a and b to infinite precision and then adds c to this product.0f. a.

..c. a rounding modifier is required for mad.rp for mad.. Rounding modifiers have the following target requirements: . Legacy mad.. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f64 requires sm_13 or later.f32. January 24.rz.rp for mad.0 and later.f32 for sm_20 targets. a rounding modifier is required for mad. Target ISA Notes mad. requires sm_20 Examples @p mad.4 and later. mad.a..Chapter 8. 2010 89 . requires sm_13 .rn.f64 instructions having no rounding modifier will map to mad. In PTX ISA versions 1.0.rm.rz.f64.b.rm.f64.f32 d.f64..rn. In PTX ISA versions 2.rn.f32 supported on all target architectures.

ftz}. div. a.ftz.rnd.f32 div. Subnormal inputs and results are flushed to sign-preserving zero.rn. For PTX ISA versions 1. but is not fully IEEE 754 compliant and does not support rounding modifiers.rz. or .f64 d. d. div.rnd.ftz}. a. PTX ISA Notes div. y. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .0 Table 54.3.14159. For b in [2-126.f32 flushes subnormal inputs and results to sign-preserving zero.rn. a.full.{rz.full.rn mantissa LSB rounds to nearest even .rn. zd.rp }.rm.f32 div.rm mantissa LSB rounds towards negative infinity .rnd{. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 div.f64.4.f32. computed as d = a * (1/b).3.ftz.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.approx. x.approx. div. Fast. d. Target ISA Notes div. div.f32 supported on all target architectures. Examples 90 January 24. // // // // fast.approx. b.0 through 1. For PTX ISA version 1. b. .full{.ftz}. subnormal numbers are supported. z. div. xd. .PTX ISA Version 2. a. b. . Explicit modifiers .circum.f64 supports subnormal numbers.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.full.f32 defaults to div.0.f32 requires sm_20 or later. one of . The maximum ulp error is 2 across the full range of inputs. 2126]. Description Semantics Notes Divides a by b. div. div. . stores result in d. Fast. d = a / b. . b. div.full.rz mantissa LSB rounds towards zero .rnd is required. the maximum ulp error is 2.approx{.4 and later.approx. approximate division by zero creates a value of infinity (with same sign as a). and rounding introduced in PTX ISA version 1. full-range approximation that scales operands to achieve better accuracy. div Syntax Floating-Point Instructions: div Divide one value by another. div.f32 implements a fast approximation to divide. d.f64 requires sm_20 or later. yd.f32 div.f64 defaults to div.rn.f64 diam.rm.f32 div.f32 implements a relatively fast. sm_1x: div. . 2010 .f32 and div.f32 and div.approx.ftz.f64 requires sm_13 or later.full.f64 introduced in PTX ISA version 1.approx.rnd = { . and div.rp}. approximate single-precision divides: div.

Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. neg. sm_1x: neg. abs. 2010 91 . Subnormal numbers: sm_20: By default.f0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.ftz.ftz. neg. neg. d = |a|. d = -a.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. sm_1x: abs. a.ftz}.f32 supported on all target architectures. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f64 supports subnormal numbers.f64 requires sm_13 or later. neg{. NaN inputs yield an unspecified NaN.f64 d. Negate the sign of a and store the result in d.f64 requires sm_13 or later. abs. Table 56. neg.ftz.f32 neg. subnormal numbers are supported.ftz. NaN inputs yield an unspecified NaN.f64 supports subnormal numbers. a.f32 supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. January 24. d.ftz}.0.f0. subnormal numbers are supported. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. a.0.Chapter 8. abs{. abs. abs.f64 d.f32 abs. abs.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 x. neg.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero. Take the absolute value of a and store the result in d. d. Instruction Set Table 55.

sm_1x: max. a. sm_1x: min. max.f32 flushes subnormal inputs and results to sign-preserving zero. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. min.c. max. (a < b) ? a : b.f64 requires sm_13 or later. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.b.ftz}. b. b. a.x.f64 supports subnormal numbers. 92 January 24.f1.0 Table 57. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.0. d. Store the maximum of a and b in d. min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. max. subnormal numbers are supported.f64 z. Store the minimum of a and b in d. d.f32 supported on all target architectures.f32 min. max. a.f64 requires sm_13 or later.f64 f0.ftz. a. max{. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. d d d d = = = = NaN. d d d d = = = = NaN.z.f64 d. max.f32 max.PTX ISA Version 2.0.f32 flushes subnormal inputs and results to sign-preserving zero. Table 58. b.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.ftz.f32 max. @p min. a. b.f2.f64 supports subnormal numbers. b. (a > b) ? a : b. subnormal numbers are supported.b.c.f64 d. 2010 .f32 min. min.f32 supported on all target architectures. b. min{.ftz.

ftz. General rounding modifiers were added in PTX ISA version 2. rcp.{rz. sm_1x: rcp. rcp.f64 d. The maximum absolute error is 2-23.f32.f32 implements a fast approximation to reciprocal. xi.f64 requires sm_20 or later.3. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . store result in d. subnormal numbers are supported.f32 rcp.f64 introduced in PTX ISA version 1. rcp. Examples January 24.4. // fast.rn.ftz.rnd is required. xi. rcp.0.0 over the range 1.approx or .f32 flushes subnormal inputs and results to sign-preserving zero.f32 requires sm_20 or later. rcp.approx. .4 and later.f32 and rcp.Chapter 8.rnd.f32 rcp. . Target ISA Notes rcp. Description Semantics Notes Compute 1/a.x.r.ftz}.approx.rp}.ftz.f64 requires sm_13 or later. d.rn.x. rcp.f64 defaults to rcp.rn.rnd{. a.0 -Inf -Inf +Inf +Inf +0.0. 2010 93 .0 +subnormal +Inf NaN Result -0. rcp.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. a.rz mantissa LSB rounds towards zero .f32 defaults to rcp.approx.rn mantissa LSB rounds to nearest even .0 +0.rp }. PTX ISA Notes rcp. one of .approx and .rm.ftz.rz. For PTX ISA version 1.rm mantissa LSB rounds towards negative infinity .rnd = { . Input -Inf -subnormal -0.f32 rcp. d = 1 / a. For PTX ISA versions 1.0.f32 supported on all target architectures.f64 supports subnormal numbers.0-2. rcp.rm.0 through 1. a.f32 rcp.f64. rcp. Instruction Set Table 59.approx{.ftz were introduced in PTX ISA version 1.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn. d.f64 ri. .rn.rnd. rcp. and rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx.f64 and explicit modifiers .

f32 and sqrt.approx.f32 supported on all target architectures. General rounding modifiers were added in PTX ISA version 2. For PTX ISA versions 1. a. // IEEE 754 compliant rounding d.0 +0.f32 implements a fast approximation to square root.ftz.{rz.rnd.approx. . a.f32 defaults to sqrt.rn. sqrt.f64 supports subnormal numbers.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . Examples 94 January 24. Target ISA Notes sqrt. Input -Inf -normal -subnormal -0.rz.rn. . a.f32 sqrt.rp}.rn.ftz}. Description Semantics Notes Compute sqrt(a). r.f64 requires sm_20 or later. sqrt.0 +0.f64 r.rn mantissa LSB rounds to nearest even . subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 introduced in PTX ISA version 1. For PTX ISA version 1.f64 d. store in d. // IEEE 754 compliant rounding . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f64 and explicit modifiers .0.approx{.f32 sqrt. and sqrt.rm.4 and later.f64 requires sm_13 or later.rm.f32 sqrt. d = sqrt(a). sqrt.f32 requires sm_20 or later.3.x. r.0 through 1.rn.ftz. sqrt.4.rn.x.approx. sqrt.0 +0. one of .rnd = { .rn.0.x.rp }.approx.f32 is TBD. PTX ISA Notes sqrt. sqrt.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: sqrt. sqrt. sqrt. approximate square root d.PTX ISA Version 2.approx or . The maximum absolute error for sqrt. .f32. sqrt. 2010 .f64.rm mantissa LSB rounds towards negative infinity .0 -0.rnd.rz mantissa LSB rounds towards zero .0 Table 60.approx.f32 sqrt. // fast.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.ftz were introduced in PTX ISA version 1.rnd is required.f64 defaults to sqrt.0 +subnormal +Inf NaN Result NaN NaN -0.approx and .rnd{.ftz}. sqrt.

approx.approx{. PTX ISA Notes rsqrt.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers .Chapter 8. sm_1x: rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt.4 over the range 1. d.f32 is 2-22.f64.4 and later.f32 defaults to rsqrt.ftz. a.approx.f64 d. rsqrt.f64 supports subnormal numbers. rsqrt. Subnormal numbers: sm_20: By default.ftz. Note that rsqrt.f64 defaults to rsqrt.ftz}. 2010 95 .f32 and rsqrt.approx. Compute 1/sqrt(a). The maximum absolute error for rsqrt. x.3.ftz were introduced in PTX ISA version 1.ftz.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. For PTX ISA version 1. January 24.f64 isr. and rsqrt.0-4.f32 rsqrt.f64 is TBD. rsqrt.f32 supported on all target architectures. Instruction Set Table 61. Input -Inf -normal -subnormal -0.approx implements an approximation to the reciprocal square root. ISR.approx.0. X.approx modifier is required.approx. For PTX ISA versions 1.f32.f64 is emulated in software and are relatively slow.0 NaN The maximum absolute error for rsqrt.f64 were introduced in PTX ISA version 1. a. rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. the . d = 1/sqrt(a).approx and . store the result in d.4.approx.0. rsqrt. subnormal numbers are supported.0 +0.f32 rsqrt. Target ISA Notes Examples rsqrt. rsqrt.f64 requires sm_13 or later.

approx. Subnormal numbers: sm_20: By default.4 and later.ftz. 96 January 24. sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. Find the sine of the angle a (in radians).ftz.f32 implements a fast approximation to sine. Input -Inf -subnormal -0.0 NaN NaN The maximum absolute error is 2-20.ftz.9 in quadrant 00. sin.0 +subnormal +Inf NaN Result NaN -0.0 -0. sin.0 +0.0 +0.approx. sm_1x: Subnormal inputs and results to sign-preserving zero.approx modifier is required. the .3.f32. 2010 .0 Table 62.approx and . sin.PTX ISA Version 2. subnormal numbers are supported.ftz}.0. Target ISA Notes Examples Supported on all target architectures.ftz introduced in PTX ISA version 1.f32 defaults to sin. For PTX ISA versions 1.4. PTX ISA Notes sin.f32 introduced in PTX ISA version 1. a.0 +0.f32 d.f32 flushes subnormal inputs and results to sign-preserving zero.approx{. d = sin(a). For PTX ISA version 1. sin. Explicit modifiers .approx.0 through 1. a.f32 sa.

Input -Inf -subnormal -0. cos.approx. cos. sm_1x: Subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.0 NaN NaN The maximum absolute error is 2-20. cos.ftz. PTX ISA Notes cos.approx modifier is required.ftz. a.ftz}.4 and later.approx. a.f32 flushes subnormal inputs and results to sign-preserving zero.0 +1.f32 implements a fast approximation to cosine. Explicit modifiers . Find the cosine of the angle a (in radians).ftz introduced in PTX ISA version 1.f32 ca. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. the . For PTX ISA version 1.9 in quadrant 00.0 +1.f32 d. cos.approx and .3.f32 defaults to cos.f32.0.0 +subnormal +Inf NaN Result NaN +1.approx{.0 +1. 2010 97 . d = cos(a).Chapter 8.approx.0 through 1.0 +0.f32 introduced in PTX ISA version 1. January 24. Subnormal numbers: sm_20: By default. Instruction Set Table 63.ftz. Target ISA Notes Examples Supported on all target architectures. cos.4. For PTX ISA versions 1.

Input -Inf -subnormal -0. 2010 .ftz introduced in PTX ISA version 1.0.f32 implements a fast approximation to log2(a).ftz. lg2.ftz.approx.f32 Determine the log2 of a. PTX ISA Notes lg2.4 and later.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.0 through 1. Target ISA Notes Examples Supported on all target architectures.f32 introduced in PTX ISA version 1. a. the . Explicit modifiers . For PTX ISA version 1.approx and .3. For PTX ISA versions 1.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero.approx. lg2. a.approx{. 98 January 24. The maximum absolute error is 2-22.f32 la.6 for mantissa. d = log(a) / log(2).ftz. lg2.f32 flushes subnormal inputs and results to sign-preserving zero.0 +0. subnormal numbers are supported. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. lg2.0 Table 64.f32. lg2.ftz}.approx. Subnormal numbers: sm_20: By default.f32 defaults to lg2.PTX ISA Version 2.4.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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gt. {!}c. b. lo.f64 supports subnormal numbers. lt. ge. gtu.n. then the result of these comparisons is true. The comparison operator is a suffix on the instruction.u16. . lt.eq. and can be one of: eq. b. ltu. .i. the result is false.b32. q = BoolOp(!t.type .ftz. num. lt. setp with . The destinations p and q must be . . p. c). If either operand is NaN. setp. p[|q]. num returns true if both operands are numeric values (not NaN). Modifier .PTX ISA Version 2. @q setp.dtype. then these comparisons have the same result as their ordered counterparts.r.ftz applies only to . ge.f32 comparisons. Integer Notes Floating Point Notes The ordered comparisons are eq. and nan returns true if either operand is NaN. hi.ftz}. .pred variables. gt. If both operands are numeric values (not NaN). To aid comparison operations in the presence of NaN values. le.s16.f32 flushes subnormal inputs to sign-preserving zero. ge. setp.0. and (optionally) combine this result with a predicate value by applying a Boolean operator. .CmpOp. p[|q]. If either operand is NaN.BoolOp{. The signed and unsigned comparison operators are eq. p = BoolOp(t. respectively. ge.type = { . geu. Semantics t = (a CmpOp b) ? 1 : 0. leu.b. xor. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. neu. Applies to all numeric types. the comparison operators lo. loweror-same.s32 setp. . gtu.and. ltu.s32.b16. le. ne. 102 January 24. unordered versions are included: equ. and higher-or-same may be used instead of lt.b64. subnormal numbers are supported. setp.ftz}.dtype.f64 source type requires sm_13 or later.dtype. a.f32. le. leu. le. . The untyped.f64 }. bit-size comparisons are eq and ne.a.type setp. or. a. 2010 . A related value computed using the complement of the compare result is written to the second destination operand. .s64. .lt. ne. Subnormal numbers: sm_20: By default. ls. . c). hs equ.u32. hi. gt. and hs for lower. sm_1x: setp. ls. nan The Boolean operator BoolOp(A. geu. neu.B) is one of: and. higher. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.CmpOp{.f32 flushes subnormal inputs to sign-preserving zero. ne.0 Table 67. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u32 p|q. gt.u64. For unsigned values. This result is written to the first destination operand.

a is stored in d. z. . sm_1x: slct.u16.f32 A. Operands d. If c ≥ 0. . Instruction Set Table 68. . b otherwise.b16. .s32. . selp Syntax Comparison and Selection Instructions: selp Select between source operands. selp. .u64. Modifier . operand c must match the second instruction type. val.dtype = { . selp.0. .t. Description Conditional selection.f32.f32 comparisons. For . a.f64 requires sm_13 or later.ftz applies only to .b64.b64. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.f32 r0. d = (c >= 0) ? a : b. Table 69.p.b32.s64. .type d. .type = { . C.ftz}.dtype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. fval.u16. negative zero equals zero.s64. Semantics Floating Point Notes January 24.0. .r. slct. and operand a is selected. Operand c is a predicate. y.f64 requires sm_13 or later. Subnormal numbers: sm_20: By default. a is stored in d. .s16.g. b. . f0.Chapter 8. Operands d. and b are treated as a bitsize type of the same width as the first instruction type. a. @q selp. the comparison is unordered and operand b is selected.u32.dtype.b32.u64.s32.f32 comparisons.f32 flushes subnormal values of operand c to sign-preserving zero.f64 }.f64 }.b16. B. b. If operand c is NaN. . slct. .xp. . b. based on the sign of the third operand.f32 d.ftz. . 2010 103 . c. and b must be of the same type. slct. slct Syntax Comparison and Selection Instructions: slct Select one source operand. . a. d. a. Introduced in PTX ISA version 1. subnormal numbers are supported.dtype.s32 slct{.f32 flushes subnormal values of operand c to sign-preserving zero.u32. slct.f32. . The selected input is copied to the output without modification. c. .u32. based on the value of the predicate source operand. .s32 selp.ftz. . slct.dtype. If c is True.u64.s32 x. a. d = (c == 1) ? a : b.s16. c. and operand a is selected. . otherwise b is stored in d.x.

Instructions and. or. xor.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.4. and not also operate on predicates. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. provided the operands are of the same size. This permits bit-wise operations on floating point values without having to define a union to access the bits.0 8. performing bit-wise operations on operands of any type.PTX ISA Version 2.

and. January 24. . .r. .type d. . Supported on all target architectures.0x80000000. Introduced in PTX ISA version 1.b64 }.q.pred p. or Syntax Logic and Shift Instructions: or Bitwise OR.b32 x. Allowed types include predicate registers.b32.b32 mask mask.0x00010001 or. b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.fpvalue. Instruction Set Table 70.type = { .0.pred. d = a | b.r. sign.pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. The size of the operands must match. a. or.b32. Introduced in PTX ISA version 1.type = { . . .b16. Table 71. but not necessarily the type. and Syntax Logic and Shift Instructions: and Bitwise AND.b64 }. a.0.b16. Allowed types include predicate registers. but not necessarily the type. b. 2010 105 .b32 and.type d. d = a & b. or. Supported on all target architectures. . and. .q. The size of the operands must match.Chapter 8.

type = { . Table 74. cnot.mask.b64 }. . The size of the operands must match.type d. Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.0.x. a. .b64 }.type = { .type d. not.q. . Allowed types include predicates. Supported on all target architectures.b32 xor. Supported on all target architectures.type d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Introduced in PTX ISA version 1. d. Table 73.b32. a.0. .q.pred p.b64 }. . xor.b16. Introduced in PTX ISA version 1. cnot.b16. The size of the operands must match. d = ~a.b32 mask. . xor. but not necessarily the type.0 Table 72.0.r.b16. . b. Introduced in PTX ISA version 1. but not necessarily the type.b32. a.0x0001. d = (a==0) ? 1 : 0.PTX ISA Version 2. The size of the operands must match. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. not. 106 January 24. .a.type = { . d = a ^ b. not Syntax Logic and Shift Instructions: not Bitwise negation.pred. one’s complement. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).pred. but not necessarily the type. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b32 d.b16 d. . not. Allowed types include predicate registers. 2010 .b32. .

type = { . k.b32. The b operand must be a 32-bit value.u32. shl Syntax Logic and Shift Instructions: shl Shift bits left.Chapter 8. The b operand must be a 32-bit value. . The sizes of the destination and first source operand must match. . b. b.u16 shr. . d = a << b.j. Introduced in PTX ISA version 1. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. but not necessarily the type.0. . shr. Bit-size types are included for symmetry with SHL.b32 q.u16. shr.1. . . Shift amounts greater than the register width N are clamped to N. PTX ISA Notes Target ISA Notes Examples January 24. shl.s64 }.s32. sign or zero fill on left.type = { . .s32 shr. .u64.i.b16 c.b32. 2010 107 . Introduced in PTX ISA version 1. zero-fill on right.b16. regardless of the instruction type. unsigned and untyped shifts fill with 0. but not necessarily the type. Instruction Set Table 75. shr Syntax Logic and Shift Instructions: shr Shift bits right. PTX ISA Notes Target ISA Notes Examples Table 76. Signed shifts fill with the sign bit. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. .type d. Supported on all target architectures. regardless of the instruction type.b64. Shift amounts greater than the register width N are clamped to N. a.type d. i.b16.a. The sizes of the destination and first source operand must match.2. Supported on all target architectures. d = a >> b. . shl. .a.0.b64 }. .2.s16. a.i.

The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. and st operate on both scalar and vector types. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. prefetchu isspacep cvta cvt 108 January 24. local. suld. or shared state spaces. st. The cvta instruction converts addresses between generic and global.5. ld.PTX ISA Version 2. and sust support optional cache operations. 2010 .0 8. and from state space to state space. ldu. mov.7. possibly converting it from one format to another. Instructions ld. Data Movement and Conversion Instructions These instructions copy data from place to place.

The ld.lu operation.lu Last use. rather than the data stored by the first thread. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cg to cache loads only globally. January 24. A ld.lu load last use operation. The ld.cs is applied to a Local window address.5. and a second thread loads that address via a second L1 cache with ld.ca. . The default load instruction cache operation is ld. As a result of this request.cs. . it performs the ld. bypassing the L1 cache. fetch again). When ld. 2010 109 . if the line is fully covered. . The ld. the cache operators have the following definitions and behavior.Chapter 8.ca. The cache operators require a target architecture of sm_20 or later. to allow the thread program to poll a SysMem location written by the CPU. not L1).lu instruction performs a load cached streaming operation (ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. Instruction Set 8. evict-first. Table 77. and cache only in the L2 cache. invalidates (discards) the local L1 line following the load.cs Cache streaming. likely to be accessed again.cg Cache at global level (cache in L2 and below. any existing cache lines that match the requested address in L1 will be evicted. likely to be accessed once.ca loads cached in L1. Global data is coherent at the L2 level.0 introduces optional cache operators on load and store instructions. If one thread stores to global memory via one L1 cache.7. .cs) on global addresses. but multiple L1 caches are not coherent for global data. For sm_20 and later.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. the second thread may get stale L1 cache data.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. Operator . when applied to a local address. Use ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.cv to a frame buffer DRAM address is the same as ld. Cache Operators PTX 2.cv Cache as volatile (consider cached system memory lines stale. The compiler / programmer may use ld. The ld.1. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.

cg to local memory uses the L1 cache. the second thread may get a hit on stale L1 cache data. and a second thread in a different SM later loads from that address via a different L1 cache with ld.cg to cache global store data only globally.ca loads.cg is the same as st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. and cache only in the L2 cache. Global stores bypass L1.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Operator .0 Table 78.wt Cache write-through (to system memory). . st.wb. to allow a CPU program to poll a SysMem location written by the GPU with st. and discard any L1 lines that match.wb could write-back global store data from L1. Future GPUs may have globally-coherent L1 caches.wt. likely to be accessed once.cg Cache at global level (cache in L2 and below. Addresses not in System Memory use normal write-back.wt store write-through operation applied to a global System Memory address writes through the L2 cache. not L1).wb for global data. 2010 .cs Cache streaming. 110 January 24. . in which case st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. Use st. . rather than get the data from L2 or memory stored by the first thread. bypassing the L1 cache. and marks local L1 lines evict-first. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. The default store instruction cache operation is st. but st. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. The st. In sm_20. bypassing its L1 cache. regardless of the cache operation. If one thread stores to global memory. However.ca. which writes back cache lines of coherent cache levels with normal eviction policy.PTX ISA Version 2. The st.

pred. d. and . special register. or shared state space.u16. d = &avar.type mov.u64. addr..b16. i. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.local. . or shared state space may be taken directly using the cvta instruction. the address of the variable in its state space) into the destination register. mov. mov places the non-generic address of the variable (i. a. .f32.0. d. mov. 2010 111 .b64. or function name. A.global. Semantics d = a.s32. u. mov. . . the parameter will be copied onto the stack and the address will be in the local state space. Operand a may be a register. . local. local.u32 d. // address is non-generic. label. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. avar.f64 requires sm_13 or later. the generic address of a variable declared in global.type d. Take the non-generic address of a variable in global. myFunc.u32. . Introduced in PTX ISA version 1. sreg. ptr.shared state spaces.f32 mov. The generic address of a variable in global. // get address of variable // get address of label or function . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. local. .type mov. d = &label.u32 mov.v.type mov. d = sreg.type = { .b32. For variables declared in . d. label. . Description .u16 mov. .Chapter 8. ptr.1. variable in an addressable memory space. Instruction Set Table 79.0.s16. alternately. . . Write register d with the value of a. Note that if the address of a device function parameter is moved to a register.e. immediate. A[5].const. k.s64.f32 mov.e.u32 mov.. .a. within the variable’s declared state space Notes Although only predicate and bit-size types are required.f64 }.

b64 112 January 24.7].b.b32 %r1. d.w have type . {r.y << 16) | (a.b}. a[8.y } = { a[0.z << 32) | (a.x.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d.31]. or write vector register d with the unpacked values from scalar register a.7].z..b have type . a[48..type d. d.b16 { d. a[16. a[16..x | (a.y << 8) | (a.b32 mov.x. d.b32 { d.x | (a.u16 %x is a double.b64 // pack two 32-bit elements into .b64 { d..y. a.z. Supported on all target architectures. .0.. a[8. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.{a. Semantics d = a.w << 48) d = a.b32 mov.a}.b.hi}.23].a have type . 2010 . mov..g.b32 { d.b64 mov. .b8 r.y << 16) d = a..x. // // // // a.y } = { a[0.15]. d.y << 8) d = a.u8 // unpack 32-bit elements from .hi are ..15].u32 x.b32 // pack two 16-bit elements into .w}..y } = { a[0.b64 }.b32 // pack four 16-bit elements into .w } = { a[0..PTX ISA Version 2.47]..31]. d.x | (a.y << 32) // pack two 8-bit elements into . mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).z. .x.b64 { d.31] } // unpack 8-bit elements from .b16.y. a[16.{x.15] } // unpack 8-bit elements from .x | (a. %r1.x | (a.0 Table 80.63] } // unpack 16-bit elements from . lo.. Description Write scalar register d with the packed value of vector register a. a[24. %x.y. d.b16 // pack four 8-bit elements into . mov.z << 16) | (a.w << 24) d = a...b32.z. a[32.%r1. d. d.x.g.type = { .w } = { a[0. a[32.y.15]. {lo.31] } // unpack 16-bit elements from . For bit-size types. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.

f64 }. an integer or bit-size type register reg containing a byte address. d. [a]. .b32. *(immAddr). If an address is not properly aligned. d. ld introduced in PTX ISA version 1. . or [immAddr] an immediate absolute byte address (unsigned. . Description Load register variable d from the location specified by the source address operand a in specified state space.e. an address maps to global memory unless it falls within the local memory window or the shared memory window.ss = { ..lu. for example. 32-bit). *a. . . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. .b64.f64 using cvt.e.type = { .v2.type d. . perform the load using generic addressing. d. .s64. The address size may be either 32-bit or 64-bit.s8.f32 or . 2010 113 .ca. ld.reg state space.vec.Chapter 8.vec.1.cop = { .f16 data may be loaded using ld. [a]. [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .cg. The value loaded is sign-extended to the destination register width for signed integers.ss}{. Generic addressing may be used with ld.ss}{.u32.param.0. . 32-bit). .local. or the instruction may fault. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.const. i.v4 }.volatile may be used with . If no state space is given.shared }. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .f32.cv }.b16.b16. Cache operations are not permitted with ld. an address maps to the corresponding location in local or shared memory. ld. This may be used. i. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .volatile{. Within these windows. A destination register wider than the specified type may be used.u16.ss}.type ld{.u64. . Semantics d d d d = = = = a.ss}.0.volatile introduced in PTX ISA version 1.volatile{.cop}. . [a]. The . . .type ld. . Addresses are zero-extended to the specified width as needed. to enforce sequential consistency between threads accessing shared memory. and then converted to . Instruction Set Table 81. ld{.cs.u8.cop}. . *(a+immOff). Generic addressing and cache operations introduced in PTX ISA 2.const space suffix may have an optional bank number to indicate constant banks other than bank zero. In generic addressing. . the resulting behavior is undefined. .s16. .volatile. the access may proceed by silently masking off low-order address bits to achieve proper rounding.global.type . PTX ISA Notes January 24.volatile. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. and truncated if the register width exceeds the state space address width for the target architecture. .s32. and is zeroextended to the destination register width for unsigned and bit-size types.shared spaces to inhibit optimization of references to volatile memory.b8. . The address must be naturally aligned to a multiple of the access size. .vec = { . .global and .

f32 ld.local.f32.v4. // negative offset %r. x.b32 ld.b64 ld.shared.b32 ld.b16 cvt.s32 ld.[a].[p].%r. ld.global.0 Target ISA Notes ld.[p+-8].[p+4].[fs].b32 ld.f16 d. Cache operations require sm_20 or later. // load .f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. // immediate address %r.[240]. %r. Generic addressing requires sm_20 or later. Q. d. // access incomplete array x.PTX ISA Version 2.const.global.local. 2010 .f64 requires sm_13 or later.[buffer+64].const[4].

ldu.0. the access may proceed by silently masking off low-order address bits to achieve proper rounding. // load from address // vec load from address .b16.Chapter 8. A destination register wider than the specified type may be used.v4.f32 d. The address size may be either 32-bit or 64-bit. . and then converted to . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .type d.f64 }. . .[p+4]. *(immAddr). an address maps to global memory unless it falls within the local memory window or the shared memory window. i.s64. . [areg] a register reg containing a byte address. and truncated if the register width exceeds the state space address width for the target architecture. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.vec = { . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.e. .global.b32. an address maps to the corresponding location in local or shared memory.type = { . ldu.b64. Introduced in PTX ISA version 2.u64. .ss = { .global.s32. only generic addresses that map to global memory are legal. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. . *a. 32-bit). d. ldu{. .u16. Within these windows. i.u32.b32 d.f64 using cvt. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .v4 }.f32. In generic addressing.reg state space. and is zeroextended to the destination register width for unsigned and bit-size types. the resulting behavior is undefined.type ldu{.ss}.v2. If no state space is given.u8.f32 Q. .f16 data may be loaded using ldu. *(a+immOff). . . perform the load using generic addressing. . . .global }. The data at the specified address must be read-only. The addressable operand a is one of: [avar] the name of an addressable variable var.e.ss}.f64 requires sm_13 or later. where the address is guaranteed to be the same across all threads in the warp. [a]..s16. 2010 115 . or the instruction may fault. . The value loaded is sign-extended to the destination register width for signed integers. ldu. Addresses are zero-extended to the specified width as needed. A register containing an address may be declared as a bit-size type or integer type. If an address is not properly aligned. Instruction Set Table 82.b16. Semantics d d d d = = = = a. or [immAddr] an immediate absolute byte address (unsigned. [a]. PTX ISA Notes Target ISA Notes Examples January 24. For ldu.vec.b8.global. // state space .[p].[a].s8.f32 or . 32-bit). ldu. The address must be naturally aligned to a multiple of the access size.

shared spaces to inhibit optimization of references to volatile memory.f16 data resulting from a cvt instruction may be stored using st.ss}. . . . { .volatile{. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. an address maps to global memory unless it falls within the local memory window or the shared memory window. { . . Addresses are zero-extended to the specified width as needed.u8. .b16.volatile. ..vec . 2010 . . an integer or bit-size type register reg containing a byte address.ss}{. Generic addressing and cache operations introduced in PTX ISA 2. .type st{.v4 }. . *d = a. [a]. perform the store using generic addressing. st{. .u64.s16. b.0. b.volatile may be used with .ss}.global.cg. . st. This may be used. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. [a]. If an address is not properly aligned. In generic addressing.PTX ISA Version 2.b64. *(immAddr) = a.cop}. The lower n bits corresponding to the instruction-type width are stored to memory. .v2. st introduced in PTX ISA version 1. and truncated if the register width exceeds the state space address width for the target architecture. or [immAddr] an immediate absolute byte address (unsigned.volatile{.type .s64.e. .cop}. 32-bit). for example.volatile.cop .e. st.reg state space.u16.shared }.type [a]. A source register wider than the specified type may be used. .wt }.vec.0. to enforce sequential consistency between threads accessing shared memory.b16. If no state space is given. b. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st. i.volatile introduced in PTX ISA version 1.s8. { . Semantics d = a. .type = = = = {.0 Table 83. Within these windows.cs.u32. 32-bit).b8.f64 }.s32. Generic addressing may be used with st.ss . [a]. . or the instruction may fault. Cache operations are not permitted with st.vec. PTX ISA Notes Target ISA Notes 116 January 24.global and . The addressable operand a is one of: [var] [reg] the name of an addressable variable var.local. the resulting behavior is undefined. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.f64 requires sm_13 or later. an address maps to the corresponding location in local or shared memory. Cache operations require sm_20 or later. *(d+immOffset) = a. The address must be naturally aligned to a multiple of the access size.ss}{. b. . .1.wb. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. i. The address size may be either 32-bit or 64-bit. Generic addressing requires sm_20 or later. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32.f32. .type st. .

b32 st.%r.s32 cvt.r7.v4.%r.f32 st.f16. // %r is 32-bit register // store lower 16 bits January 24.b32 st.a. 2010 117 .global. [p].s32 st.global.local.b16 [a].Q.local. [q+4]. // immediate address %r.a. Instruction Set Examples st. [fs]. [q+-8].b.local.f32 st.Chapter 8. // negative offset [100].

the prefetch uses generic addressing. or [immAddr] an immediate absolute byte address (unsigned.0. Addresses are zero-extended to the specified width as needed.0 Table 84. 118 January 24. and truncated if the register width exceeds the state space address width for the target architecture.space}. prefetch{. and no operation occurs if the address maps to a local or shared memory location. In generic addressing.L1 [addr]. 2010 . The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. [a]. a register reg containing a byte address. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. in specified state space. . If no state space is given.space = { . Within these windows. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.global. an address maps to global memory unless it falls within the local memory window or the shared memory window. prefetchu. i. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.global. prefetch.L1.PTX ISA Version 2. .local }. an address maps to the corresponding location in local or shared memory.L2 }. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. A prefetch into the uniform cache requires a generic address.level prefetchu.L1 [a]. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. A prefetch to a shared memory location performs no operation. 32-bit). The address size may be either 32-bit or 64-bit. // prefetch to data cache // prefetch to uniform cache . 32-bit).e. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . prefetch and prefetchu require sm_20 or later.level = { .L1 [ptr].

lptr. . Take the generic address of a variable declared in global. isspacep. or vice-versa. cvta.u32. // convert to generic address // get generic address of var // convert generic address to global.u32 gptr. or shared address cvta.0. . // result is . Use cvt.u32.size = { . lptr.space. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. Introduced in PTX ISA version 2. or vice-versa. svar. .size . Description Convert a global.local isspacep.pred. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. islcl. or shared address to a generic address.local.Chapter 8. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.global isspacep. a.space.genptr. A program may use isspacep to guard against such incorrect behavior. gptr.u64 }. The source address operand must be a register of type . p.size p.global. The destination register must be of type .global. or shared address.to. local. . isshrd.0.shared isglbl.u32 to truncate or zero-extend addresses. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. . The source and destination addresses must be the same size.shared. isspacep requires sm_20 or later.u32 p.local. Instruction Set Table 85. local.u32 p. // local. p. local.space.u32 or . or shared state space.shared }.space = { . sptr. local. a. PTX ISA Notes Target ISA Notes Examples Table 86. For variables declared in global. local.space = { .u64. var.global. . cvta.local. January 24. cvta.space p.u64 or cvt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. or shared state space to generic.u64. isspacep. the generic address of the variable may be taken using cvta.size cvta. or shared state space. a. cvta requires sm_20 or later.shared }. // get generic address of svar cvta.to. 2010 119 . When converting a generic address into a global.pred .

dtype.PTX ISA Version 2.ftz.f32 float-tofloat conversions with integer rounding. a. . .rni round to nearest integer.u64. the result is clamped to the destination range by default. 120 January 24.dtype. ..e. For cvt.atype d.rpi }. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.sat limits the result to MININT. . .u16.atype cvt{. . .ftz.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. .rni.s16.rp }. . subnormal inputs are flushed to signpreserving zero.0 Table 87. Integer rounding modifiers: .dtype. d = convert(a). .sat}.f32 float-to-integer conversions and cvt. . cvt{.rm.f32. .4 and earlier.rzi round to nearest integer in the direction of zero .irnd = { .f32 float-to-integer conversions and cvt. Integer rounding is required for float-to-integer conversions.atype = { .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.ftz. a. Integer rounding is illegal in all other instances.ftz. subnormal inputs are flushed to signpreserving zero. Saturation modifier: .ftz}{.f32.sat is redundant. For float-to-integer conversions. and for same-size float-tofloat conversions where the value is rounded to an integer.e.frnd}{.f32 float-tofloat conversions with integer rounding. i.u8.dtype = . // integer rounding // fp rounding . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32.f64 }..irnd}{. . subnormal numbers are supported. The compiler will preserve this behavior for legacy PTX code.rmi round to nearest integer in direction of negative infinity . .dtype. . d.f16. .sat}. Note: In PTX ISA versions 1. 2010 .u32. the . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. Note that saturation applies to both signed and unsigned integer types.ftz modifier may be specified in these cases for clarity. i. sm_1x: For cvt. The optional . .rz. .s8.s64. .rzi.sat For integer destination types. Description Semantics Integer Notes Convert between different types and sizes.ftz}{.rn.rmi. choosing even integer if source is equidistant between two integers.s32.MAXINT for the size of the operation.frnd = { . . .

rn mantissa LSB rounds to nearest even . cvt.i.f64 types. stored in floating-point format.s32. 2010 121 .f16. Floating-point rounding is illegal in all other instances.f32. cvt. 1. The optional .y. // float-to-int saturates by default cvt.f32.f16.4 or earlier. The result is an integral value. Subnormal numbers: sm_20: By default.version is 1. result is fp cvt. The operands must be of the same size. and for integer-to-float conversions.4 and earlier.ftz behavior for sm_1x targets January 24. cvt to or from .f32 x.sat limits the result to the range [0.rm mantissa LSB rounds towards negative infinity . NaN results are flushed to positive zero. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. Floating-point rounding modifiers: .sat For floating-point destination types. Introduced in PTX ISA version 1.Chapter 8. The compiler will preserve this behavior for legacy PTX code. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32. Specifically.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.rni.0. if the PTX .f32. Modifier . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f32.0]. // note . and . . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . .y.ftz modifier may be specified in these cases for clarity.f64 requires sm_13 or later.f32 x. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.s32 f. and cvt. // round to nearest int. Saturation modifier: .r. Applies to . cvt. Note: In PTX ISA versions 1.f32.f16.f64 j. subnormal numbers are supported.f64.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).f32 instructions.0.rz mantissa LSB rounds towards zero .f32.

[tex1. and surface descriptors: • • • Static initialization of texture.f32 r1. texture and sampler information each have their own handle.r2. add. A PTX module may declare only one texturing mode. // get tex1’s txq. r5. [tex1]. r3.v4. r1.global .f32 {r1. add. sampler. r3. sampler.6.u32 r5. r1. texture and sampler information is accessed through a single . r2.entry compute_power ( . samplers. } = clamp_to_border. Ability to query fields within texture. r1. the file is assumed to use unified mode.. {f1. [tex1]. Texture and Surface Instructions This section describes PTX instructions for accessing textures. r5.param .f2}]. Module-scope and per-entry scope definitions of texture.7. 2010 . div.0 8.target texmode_independent . The texturing mode is selected using . PTX has two modes of operation.width. PTX supports the following operations on texture. and surfaces. The advantage of independent mode is that textures and samplers can be mixed and matched. mul. . // get tex1’s tex. r6.r4}. .height. sampler. . r5.b32 r6. but the number of samplers is greatly restricted to 16. allowing them to be defined separately and combined at the site of usage in the program.texref handle. 122 January 24. In the independent mode. In the unified mode. Texturing modes For working with textures and samplers.f32. If no texturing mode is declared.b32 r5.f32 r1. and surface descriptors. add.. and surface descriptors.r3.u32 r5. Example: calculate an element’s power contribution as element’s power/total number of elements. with the restriction that they correspond 1-to-1 with the 128 possible textures. = nearest width height tsamp1.2d. r4.samplerref tsamp1 = { addr_mode_0 filter_mode }. and surface descriptors. cvt.target options ‘texmode_unified’ and ‘texmode_independent’. sampler.PTX ISA Version 2.f32 r1.f32 r3. The advantage of unified mode is that it allows 128 samplers.texref tex1 ) { txq.f32.

tex txq suld sust sured suq Table 88.f4}]. the access may proceed by silently masking off low-order address bits to achieve proper rounding. //Example of unified mode texturing tex. c].f2.r2. 2010 123 .f32 {r1. A texture base address is assumed to be aligned to a 16-byte address.1d.dtype = { .. with the extra elements being ignored. If no sampler is specified.r4}. or the instruction may fault.r3. If an address is not properly aligned.btype d.v4 coordinate vectors are allowed for any geometry.v4. . d.r2. // Example of independent mode texturing tex. is a two-element vector for 2d textures. Description Texture lookup using a texture coordinate vector.s32 {r1. . The instruction always returns a four-element vector of 32-bit values. and is a four-element vector for 3d textures.geom = { . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. Instruction Set These instructions provide access to texture and surface memory.s32. . the square brackets are not required and .btype tex.v4.geom.5. b. i.3d.s32.v4. An optional texture sampler b may be specified. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. tex.s32. Unified mode texturing introduced in PTX ISA version 1.e. Supported on all target architectures. [a.0. Notes For compatibility with prior versions of PTX. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. {f1. c]. [tex_a. .Chapter 8.r4}.r3.3d }.2d.s32. the sampler behavior is a property of the named texture. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.dtype. sampler_x. // explicit sampler .v4. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.f32 }.geom. .u32. Operand c is a scalar or singleton tuple for 1d textures.1d. [a. [tex_a.f3.dtype. .btype = { .f32 }. . the resulting behavior is undefined. {f1}]. where the fourth element is ignored. PTX ISA Notes Target ISA Notes Examples January 24.

filter_mode.height . clamp_to_edge. d. txq. linear } Integer from enum { wrap. 2010 .PTX ISA Version 2. sampler attributes are also accessed via a texref argument. [smpl_B].normalized_coords . clamp_ogl. In unified mode. Operand a is a .width.depth . Query: . [a]. txq.0 Table 89.b32 %r1.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).width .b32 txq.tquery = { .texref or .addr_mode_1 .b32 %r1. addr_mode_2 }. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. mirror. . txq.depth.filter_mode .height. Supported on all target architectures. [tex_A]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .width. [a].5.normalized_coords }. txq.b32 %r1. Description Query an attribute of a texture or sampler.tquery.filter_mode.samplerref variable. . .addr_mode_0.addr_mode_0. // texture attributes // sampler attributes . Integer from enum { nearest. // unified mode // independent mode 124 January 24.squery = { .b32 d. . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.squery. [tex_A]. addr_mode_1.addr_mode_0 . and in independent mode sampler attributes are accessed via a separate samplerref argument.

dtype.vec .f2.r2}. . where the fourth element is ignored.trap. b]. . B.ca. If the destination base type is .zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.dtype. {x. and is a four-element vector for 3d surfaces.1d. then . .p requires sm_20 or later.b32.trap {r1.clamp = = = = = = { { { { { { d.geom{. and A components of the surface format. . .p.f32 }. .1d. suld.b. the surface sample elements are converted to . or the instruction may fault. and the size of the data transfer matches the size of destination operand d.p is currently unimplemented. . suld. [a.geom .y. Destination vector elements corresponding to components that do not appear in the surface format are not written. sm_1x targets support only the .v4 }.geom{. [surf_A. .b supported on all target architectures. or . Operand b is a scalar or singleton tuple for 1d surfaces. A surface base address is assumed to be aligned to a 16-byte address. suld Syntax Texture and Surface Instructions: suld Load from surface memory.2d. if the surface format contains UINT data.f3.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.trap . then . // for suld. G. b].b8 .u32.f32. suld. suld.trap clamping modifier.cg.0. .vec. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. 2010 125 .zero }. Instruction Set Table 90. .clamp field specifies how to handle out-of-bounds addresses: . {f1.v2.u32.cs. If the destination type is .f4}. and cache operations introduced in PTX ISA version 2. additional clamp modifiers. . [a.surfref variable. . size and type conversion is performed as needed to convert from the surface sample format to the destination type. {x}].u32. [surf_B. suld.v4. suld.z.cop}.s32. Target ISA Notes Examples January 24.3d. // unformatted d.cop}. .5.clamp.f32.clamp suld. . // cache operation none.p. . or FLOAT data.trap introduced in PTX ISA version 1. .clamp . .f32 is returned.v2. If an address is not properly aligned. is a two-element vector for 2d surfaces. // formatted . then . or .p .trap suld.b32. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.b. Operand a is a . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32 based on the surface format as follows: If the surface format contains UNORM.u32 is returned.b . . Description Load from surface memory using a surface coordinate vector.Chapter 8. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. suld.b performs an unformatted load of binary data.v4.clamp .b16.s32 is returned.3d requires sm_20 or later.cop .3d }. // for suld.e. the resulting behavior is undefined.b64 }.p.cv }..dtype . Coordinate elements are of type .s32.dtype .w}].b. suld. i. The . . if the surface format contains SINT data. suld. The lowest dimension coordinate represents a sample offset rather than a byte offset.b32. SNORM. Cache operations require sm_20 or later.s32.s32.b64.

[a. {f1.z.s32.0.v4.s32. c. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.f32 }.3d. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b // for sust.b32. sust.b32.p. sust. and is a four-element vector for 3d surfaces.e.{u32. B.ctype.b supported on all target architectures. Source elements that do not occur in the surface sample are ignored. Coordinate elements are of type . .s32.1d.cop .f32. .f3. {x. .geom{. // for sust. sust.0 Table 91. The . If the source type is .trap. sust. A surface base address is assumed to be aligned to a 16-byte address. These elements are written to the corresponding surface sample components.trap clamping modifier.geom . . where the fourth element is ignored.trap . Operand b is a scalar or singleton tuple for 1d surfaces. .ctype .clamp sust. .ctype . .v2.r2}. The size of the data transfer matches the size of source operand c.vec . then . . is a two-element vector for 2d surfaces.geom{. i.b16.. then . .b.clamp. 2010 . . The source data is then converted from this type to the surface sample format.1d.5. .p. Surface sample components that do not occur in the source vector will be written with an unpredictable value.cg.b32.b. sm_1x targets support only the .p.u32 is assumed. or the instruction may fault. . SNORM.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.p.zero }.cop}.vec.ctype. .trap sust.2d. The lowest dimension coordinate represents a sample offset rather than a byte offset.trap [surf_A. if the surface format contains UINT data. or . b]. If the source base type is .b64 }.b64.p Description Store to surface memory using a surface coordinate vector. b]. {x}]. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. [surf_B.clamp = = = = = = { { { { { { [a. if the surface format contains SINT data. The source vector elements are interpreted left-to-right as R. If an address is not properly aligned.f4}. and A surface components.3d }.f32 is assumed.vec.u32. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.s32. sust. c.p requires sm_20 or later. and cache operations introduced in PTX ISA version 2. .u32. sust. sust. the access may proceed by silently masking off low-order address bits to achieve proper rounding.v4 }. the resulting behavior is undefined. .wt }. or FLOAT data.trap introduced in PTX ISA version 1. Operand a is a .f32} are currently unimplemented. none. . Target ISA Notes Examples 126 January 24. .w}].f32.p performs a formatted store of a vector of 32-bit data values to a surface sample. sust. sust. . {r1.b performs an unformatted store of binary data.clamp field specifies how to handle out-of-bounds addresses: . G. Cache operations require sm_20 or later.wb.clamp . .PTX ISA Version 2.b. additional clamp modifiers.cs.b8 . // unformatted // formatted .3d requires sm_20 or later. size and type conversions are performed as needed between the surface sample format and the destination type.y.cop}.surfref variable.clamp .s32 is assumed.v2.f2. then . sust Syntax Texture and Surface Instructions: sust Store to surface memory.

min and max apply to .s32. // for sured.0. sured.3d }.and.clamp.or }. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b].ctype = { .b. .min.u64 data.p.add.trap [surf_A.b32. Instruction Set Table 92.u32 based on the surface sample format as follows: if the surface format contains UINT data. r1. 2010 127 . .s32.trap sured. {x.trap .geom. Reduction to surface memory using a surface coordinate vector.op.op. .s32 is assumed. . . . .b32.. .s32. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. sured requires sm_20 or later.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32 types. The lowest dimension coordinate represents a sample offset rather than a byte offset.ctype = { .u32. A surface base address is assumed to be aligned to a 16-byte address. is a two-element vector for 2d surfaces. then . .b32 }. . The instruction type is restricted to .geom. . if the surface format contains SINT data. .b32 type. [surf_B. {x}].2d.geom = { .u32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Operand a is a . sured.clamp [a.c. where the fourth element is ignored.trap.b].c.p performs a reduction on sample-addressed 32-bit data. . or . and .clamp .b performs an unformatted reduction on .clamp [a.y}].1d.u32.s32 or . i. January 24. Operand b is a scalar or singleton tuple for 1d surfaces. and is a four-element vector for 3d surfaces.clamp field specifies how to handle out-of-bounds addresses: . // sample addressing . Operations add applies to . r1.max.u32. or the instruction may fault.b32 }.u32 is assumed.add. .surfref variable. .e.u32 and . sured.clamp = { .u64.b32. sured.ctype. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding.min.op = { .u64. // byte addressing sured.p.s32 types. .b. // for sured. The .zero }.p .ctype. then . operations and and or apply to .Chapter 8. Coordinate elements are of type .2d. and the data is interpreted as .1d. If an address is not properly aligned.b . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.

5. . [surf_A]. [a].width. Supported on all target architectures. Operand a is a .surfref variable.height.0 Table 93. 2010 .query = { .height .query.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.b32 %r1. Query: .depth }. Description Query an attribute of a surface.width . suq. 128 January 24. . suq. .PTX ISA Version 2. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.width.b32 d.

0. } PTX ISA Notes Target ISA Notes Examples Table 95. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. ratio.Chapter 8.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.eq.7.0. {} Syntax Description Control Flow Instructions: { } Instruction grouping. mov.7. Supported on all target architectures.s32 a. 2010 129 .f32 @!p div. used primarily for defining a function body. If {!}p then instruction Introduced in PTX ISA version 1. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.y. { instructionList } The curly braces create a group of instructions.b. p.c. Instruction Set 8.s32 d. setp. @{!}p instruction.f32 @q bra L23. Execute an instruction or instruction block for threads that have the guard predicate true.x.0. Supported on all target architectures. Threads with a false guard predicate do nothing. { add. Introduced in PTX ISA version 1. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.a.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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January 24, 2010

{arrive. bar.red delays the executing threads (similar to bar. and the barrier is reinitialized so that it can be immediately reused. all-threads-true (. Barriers are executed on a per-warp basis as if all the threads in a warp are active. bar.arrive a{. b. it simply marks a thread's arrival at the barrier. a{.red should not be intermixed with bar. Thus.sync or bar. The result of .pred . All threads in the warp are stalled until the barrier completes. Thus. b}.and).op. bar.15. January 24. PTX ISA Notes Target ISA Notes Examples bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.red.popc).red are population-count (.and.or).cta. {!}c. if any thread in a warp executes a bar instruction.red also guarantee memory ordering among threads identical to membar. Register operands.sync bar. 2010 133 . The reduction operations for bar.arrive. The barrier instructions signal the arrival of the executing threads at the named barrier. Instruction Set Table 100.sync 0. execute a bar. and bar. bar.sync with an immediate barrier number is supported for sm_1x targets. bar.. Execution in this case is unpredictable. d.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. bar.sync or bar. a{.arrive using the same active barrier. and any-thread-true (. thread count. and bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).u32. all threads in the CTA participate in the barrier.sync) until the barrier count is met.0. the waiting threads are restarted without delay.red performs a reduction operation across threads.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Operand b specifies the number of threads participating in the barrier. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). b. {!}c. In addition to signaling its arrival at the barrier.red} require sm_20 or later.sync without a thread count introduced in PTX ISA 1. it is as if all the threads in the warp have executed the bar instruction. while . b}.sync and bar.op = { .red performs a predicate reduction across the threads participating in the barrier. the bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. operands p and c are predicates. In conditionally executed code. Once the barrier count is reached.red. a.arrive does not cause any waiting by the executing threads. bar. Since barriers are executed on a per-warp basis.{arrive.red} introduced in PTX .popc. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Only bar.sync and bar. and then safely read values stored by other threads prior to the barrier. threads within a CTA that wish to communicate via memory can store to memory. thread count. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. the final value is written to the destination register in all threads waiting at the barrier. p.Chapter 8. b}. When a barrier completes. If no thread count is specified. the optional thread count must be a multiple of the warp size. bar. and d have type .red instruction. Note that a non-zero thread count is required for bar.version 2. bar. Description Performs barrier synchronization and communication within a CTA. Each CTA instance has sixteen barriers numbered 0. Register operands. .u32 bar.popc is the number of threads with a true predicate.or }.and and . Operands a.0.

sys introduced in PTX .gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar. 134 January 24.gl.sys requires sm_20 or later.{cta. .{cta.cta. membar. global.sys will typically have much longer latency than membar. membar.PTX ISA Version 2.g. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar.version 1. Waits until prior memory reads have been performed with respect to other threads in the CTA.gl} supported on all target architectures. membar. membar. this is the appropriate level of membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.4. membar. membar.0 Table 101. For communication between threads in different CTAs or even different SMs.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl will typically have a longer latency than membar. or system memory level. membar. level describes the scope of other clients for which membar is an ordering event.level. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.sys. .gl.level = { .g.sys }.gl. 2010 . Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. PTX ISA Notes Target ISA Notes Examples membar. membar. and memory reads by this thread can no longer be affected by other thread writes. when the previous value can no longer be read. membar.cta. red or atom) has been performed when the value written has become visible to other clients at the specified level. that is. membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.version 2. by st.gl} introduced in PTX . A memory write (e. A memory read (e. including thoses communicating via PCI-E such as system and peer-to-peer memory.sys Waits until all prior memory requests have been performed with respect to all clients.0. .cta.

u64 . . .s32. b. [a].Chapter 8. The integer operations are add. . .or.u32 only . inc. 32-bit operations. the resulting behavior is undefined. [a].and. and stores the result of the specified operation at location a. . If no state space is given. . January 24.b]. . min. The inc and dec operations return a result in the range [0. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. b. For atom. c.e. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. overwriting the original value. min. performs a reduction operation with operand b and the value in location a.space}.global.min.dec.xor. cas (compare-and-swap). d. i. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. and max.exch. or by using atom.b64 .max }. an address maps to the corresponding location in local or shared memory.g.add. .op = { . The bit-size operations are and. . and exch (exchange). perform the memory accesses using generic addressing.s32. .. an address maps to global memory unless it falls within the local memory window or the shared memory window. . . accesses to local memory are illegal. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. Within these windows.inc. and max operations are single-precision.f32 Atomically loads the original value at location a into destination register d. or [immAddr] an immediate absolute byte address. In generic addressing. .type = { . a de-referenced register areg containing a byte address.type d. Operand a specifies a location in the specified state space. .shared }.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . or.type atom{.op. dec. The address must be naturally aligned to a multiple of the access size. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. Instruction Set Table 102. by inserting barriers between normal stores and atomic operations to a common address.space = { . Addresses are zero-extended to the specified width as needed. min.u32. . .. .exch to store to locations accessed by other atomic operations. xor. . 2010 135 . . The floating-point add. Description // // // // // . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32. atom{. A register containing an address may be declared as a bit-size type or integer type. The address size may be either 32-bit or 64-bit.b32 only .cas. .e.space}. If an address is not properly aligned. e.u32.u64. The floating-point operations are add. .b64.f32 }.op. .u32. max. .add.s32. i. and truncated if the register width exceeds the state space address width for the target architecture. or the instruction may fault. atom.b32.b32.

s32 atom.global.b32 d. : r.s. atom.{add.f32.[x+4]. Introduced in PTX ISA version 1. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.shared. *a = (operation == cas) ? : } where inc(r. s) = (r >= s) ? 0 dec(r.my_val.f32 requires sm_20 or later. atom.{min.PTX ISA Version 2. s) = (r > s) ? s exch(r. : r-1.0. 2010 . 64-bit atom.exch} requires sm_12 or later.cas. atom. b. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. atom. 64-bit atom. c) operation(*a.0.1.shared requires sm_12 or later. cas(r. d.t) = (r == s) ? t operation(*a.0 Semantics atomic { d = *a.global. d.max.[p]. b). s) = s.[a]. Use of generic addressing requires sm_20 or later.my_new_val.max} are unimplemented.cas. atom.f32 atom.add.add.shared operations require sm_20 or later.global requires sm_11 or later. Release Notes Examples @p 136 January 24. : r+1.

The floating-point operations are add. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. accesses to local memory are illegal. dec.g. min. For red. b. or by using atom. .and.b32.b32 only .f32 Performs a reduction operation with operand b and the value in location a. .add. min. The address size may be either 32-bit or 64-bit. In generic addressing.op = { .u64 . Addresses are zero-extended to the specified width as needed. and max. a de-referenced register areg containing a byte address.b64. overwriting the original value. . If no state space is given. b).f32.shared }. an address maps to global memory unless it falls within the local memory window or the shared memory window. The bit-size operations are and. . .. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32.s32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.space}.type [a].or. . 32-bit operations. or. where inc(r. The floating-point add. .exch to store to locations accessed by other reduction operations. A register containing an address may be declared as a bit-size type or integer type. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.u32 only .u32. . . Notes Operand a must reside in either the global or shared state space. January 24.dec. e. The address must be naturally aligned to a multiple of the access size.max }. . perform the memory accesses using generic addressing.inc.. max. red. and truncated if the register width exceeds the state space address width for the target architecture. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. and stores the result of the specified operation at location a. Semantics *a = operation(*a.op. The integer operations are add.Chapter 8. 2010 137 .b]. . Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.u32.u64. . or the instruction may fault. inc.f32 }. . . . an address maps to the corresponding location in local or shared memory. the resulting behavior is undefined.e. dec(r.space = { . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. . Description // // // // . by inserting barriers between normal stores and reduction operations to a common address. . Within these windows. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.add.xor. Operand a specifies a location in the specified state space. or [immAddr] an immediate absolute byte address. i. and max operations are single-precision. If an address is not properly aligned.s32. . and xor. The inc and dec operations return a result in the range [0.global.e. min. Instruction Set Table 103.u32. s) = (r > s) ? s : r-1. s) = (r >= s) ? 0 : r+1. red{. i. . .type = { .min.

64-bit red. 2010 .0. Release Notes Examples @p 138 January 24. red.and.shared operations require sm_20 or later. [x+4].2. Use of generic addressing requires sm_20 or later.global.max} are unimplemented.b32 [a].shared.f32 red. [p].f32 requires sm_20 or later.PTX ISA Version 2.s32 red.f32.1.{min.add. red.shared requires sm_12 or later. red. 64-bit red. red.global.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.global requires sm_11 or later red.add.my_val.add requires sm_12 or later.max.

Instruction Set Table 104. Negating the source predicate also computes . PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.any True if source predicate is True for some active thread in warp. 2010 139 .none. // get ‘ballot’ across warp January 24. vote. // ‘ballot’ form. .not_all. vote requires sm_12 or later. vote. where the bit position corresponds to the thread’s lane id.uni }. Negate the source predicate to compute .mode.all. . Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.Chapter 8.ballot.uni. vote.2.b32 d.all True if source predicate is True for all active threads in warp. Negate the source predicate to compute .pred vote. r1. Note that vote applies to threads in a single warp. returns bitmask .q. .b32 p. Description Performs a reduction of the source predicate across threads in a warp. vote. In the ‘ballot’ form.uni. {!}a.pred d.mode = { .ballot.pred vote.uni True if source predicate has the same value in all active threads in warp. The reduction modes are: . .p.all. {!}a. vote.b32 requires sm_20 or later.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. not across an entire CTA.q.any. p.ballot.ballot. The destination predicate value is the same across all threads in the warp.

u32.atype = .9. and btype are valid. 2.dtype. Video Instructions All video instructions operate on 32-bit register operands. .asel}.7.bsel = { .bsel}.b1.secop d.sat} d.h1 }. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.dsel. The source and destination operands are all 32-bit registers. The sign of the intermediate result depends on dtype. // 32-bit scalar operation.atype. . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. a{. a{.extended internally to . 140 January 24. a{. b{. 2010 . to produce signed 33-bit input values. with optional secondary operation vop.atype.atype. c.h0. Using the atype/btype and asel/bsel specifiers.sat} d. extract and sign.PTX ISA Version 2.b2. .s34 intermediate result.dtype. b{. . The type of each operand (. 4. The primary operation is then performed to produce an .b3.asel = .btype{. with optional data merge vop. atype.asel}.dtype. half-word. c. . 3. the input values are extracted and signor zero.or zero-extend byte.secop = { .asel}. .bsel}. or word values from its source operands.max }. taking into account the subword destination size in the case of optional data merging.add.s32) is specified in the instruction type. optionally clamp the result to the range of the destination type.btype{.s33 values. .u32 or .min.btype = { . .btype{. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.dsel = .sat}. b{. The general format of video instructions is as follows: // 32-bit scalar operation.b0.s32 }. all combinations of dtype. vop.0 8. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). . perform a scalar arithmetic operation to produce a signed 34-bit result. .bsel}.dtype = . .

c). S32_MAX. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). S8_MIN ). switch ( dsel ) { case . S16_MAX. tmp.s33 tmp. tmp. c).s33 optMerge( Modifier dsel.max return MAX(tmp. 2010 141 . U8_MIN ). c). .h0.s33 optSecOp(Modifier secop. S8_MAX. c).h1: return ((tmp & 0xffff) << 16) case .b2: return ((tmp & 0xff) << 16) case . .b3: return ((tmp & 0xff) << 24) default: return tmp. . . . U8_MAX. . c). Bool sign. U32_MAX. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. January 24. U16_MIN ). tmp. U32_MIN ). The lower 32-bits are then written to the destination operand.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.b1.b3: if ( sign ) return CLAMP( else return CLAMP( case .b1: return ((tmp & 0xff) << 8) case . default: return tmp.b0. The sign of the c operand is based on dtype. . } } .h0: return ((tmp & 0xffff) case . c). .s34 tmp.s33 optSaturate( . .b0: return ((tmp & 0xff) case .add: return tmp + c.s33 c ) switch ( dsel ) { case . Modifier dsel ) { if ( !sat ) return tmp. . S32_MIN ). tmp.min: return MIN(tmp. U16_MAX. tmp. . c).s33 tmp. Instruction Set . Bool sat. S16_MIN ). as shown in the following pseudocode.Chapter 8.b2.s33 c) { switch ( secop ) { .

bsel = { . . vadd. r1. Semantics // saturate. .sat} d. c. d = optSecondaryOp( op2. vabsdiff.s32.u32. and optional secondary arithmetic operation or subword data merge.dsel .s32.asel}.asel}. tmp = MAX( ta. vadd. asel ).s32. tb ).0 Table 105.h0.s32.h1.bsel}.b1. vmax vadd. vmin. r1. r3. Integer byte/half-word/word absolute value of difference.min. vsub. tmp = MIN( ta. . .atype.dsel.u32. . vsub vabsdiff vmin.PTX ISA Version 2.op2 d.h0. b{. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. taking into account destination type and merge operations tmp = optSaturate( tmp. tb = partSelectSignExtend( b.btype{.or zero-extend based on source operand type ta = partSelectSignExtend( a. . c.s32.atype. .sat} d. . tb ).s32. tmp = ta – tb. r1. b{.btype = { .h0.bsel}.asel = . c. Integer byte/half-word/word minimum / maximum. r2. vsub.s32. b{. isSigned(dtype). bsel ).u32. vmax Syntax Integer byte/half-word/word addition / subtraction. r2.add. // optional merge with c operand 142 January 24. 2010 .b3.asel}. // extract byte/half-word/word and sign. vabsdiff. // 32-bit scalar operation. vsub. { . .dtype .atype = .b2. btype. a{.op2 Description = = = = { vadd. vmax require sm_20 or later.max }. .add r1.s32.sat.sat vsub. with optional secondary operation vop. tmp. r3.b2.sat vabsdiff. c. r3. tmp = | ta – tb |.s32.bsel}. // 32-bit scalar operation.atype.b0.b0.btype{.s32 }.btype{.h1.h1 }. Perform scalar arithmetic operation with optional saturate. r3. a{. r2. vop.s32. // optional secondary operation d = optMerge( dsel.dtype. with optional data merge vop. r2.0.sat vmin. c ). a{.sat}. dsel ). c ).b0. vmax }. vabsdiff.vop . vmin. atype. .dtype. vmin. tmp.dtype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Video Instructions: vadd. sat.

u32 vshr. r2. // 32-bit scalar operation.sat}{. 2010 143 . Video Instructions: vshl.u32.u32. . // 32-bit scalar operation.dtype . b{.sat}{.u32. tb = partSelectSignExtend( b. c. . .h0. c. } // saturate. b{. b{. // default is .atype. .u32{.op2 Description = = = = = { vshl. sat. c ). with optional secondary operation vop.op2 d.atype.wrap r1.clamp && tb > 32 ) tb = 32.dsel. if ( mode == . Signed shift fills with the sign bit. vshl.0.wrap ) tb = tb & 0x1f.mode}. Instruction Set Table 106. vshr }. bsel ).asel = .b3.max }.u32. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. { .atype.b1.u32{. and optional secondary arithmetic operation or subword data merge. January 24. if ( mode == .s32. vshr Syntax Integer byte/half-word/word left / right shift. unsigned shift fills with zero.dsel .bsel}.dtype.u32. vshr vshl.clamp . . r3. a{. d = optSecondaryOp( op2.asel}. // optional secondary operation d = optMerge( dsel.b0. dsel ). r1.sat}{. .dtype. tmp.h1.mode} d.u32{. vshl: Shift a left by unsigned amount in b with optional saturate. switch ( vop ) { case vshl: tmp = ta << tb.asel}. atype. . vop. and optional secondary arithmetic operation or subword data merge.mode} d.bsel = { . asel ). a{. c ).dtype. vshl.vop . .s32 }.atype = { . . vshr: Shift a right by unsigned amount in b with optional saturate. r2.mode . vshr require sm_20 or later. . Semantics // extract byte/half-word/word and sign.asel}. tmp. { .bsel}. . case vshr: tmp = ta >> tb.Chapter 8.min. .clamp.b2.bsel}.u32.add.or zero-extend based on source operand type ta = partSelectSignExtend( a. isSigned(dtype). with optional data merge vop. Left shift fills with zero. r3. taking into account destination type and merge operations tmp = optSaturate( tmp.wrap }. a{.h1 }.

po{. {-}c. final unsigned -(U32 * U32) + S32 // intermediate signed. final signed (S32 * U32) + S32 // intermediate signed.0 Table 107. .sat}{. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final signed -(S32 * S32) + S32 // intermediate signed. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.h0. PTX allows negation of either (a*b) or c. and scaling. (a*b) is negated if and only if exactly one of a or b is negated. final signed -(S32 * U32) + S32 // intermediate signed.atype.S32 // intermediate signed. Source operands may not be negated in .shr7.S32 // intermediate signed. {-}b{. . The final result is unsigned if the intermediate result is unsigned and c is not negated.shr15 }.h1 }. final signed The intermediate result is optionally scaled via right-shift.U32 // intermediate unsigned. . .bsel = { .S32 // intermediate signed.PTX ISA Version 2. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. Input c has the same sign as the intermediate result. this result is sign-extended if the final result is signed. and zero-extended otherwise.scale = { . Depending on the sign of the a and b operands. which is used in computing averages. final signed (U32 * S32) + S32 // intermediate signed. final signed (S32 * U32) .dtype.po) computes (a*b) + c + 1.bsel}. 144 January 24.po mode. // 32-bit scalar operation vmad. final signed (U32 * U32) . {-}a{. final signed (U32 * S32) . vmad. .u32. Description Calculate (a*b) + c. .b3.sat}{.s32 }. “plus one” mode.b0. a{.asel}.asel}. the intermediate result is signed.btype = { .bsel}.btype.. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. internally this is represented as negation of the product (a*b). . c.atype = . Although PTX syntax allows separate negation of the a and b operands. The source operands support optional negation with some restrictions. final signed (S32 * S32) . . 2010 . b{. That is.scale} d. otherwise.asel = . final signed -(U32 * S32) + S32 // intermediate signed. final signed (S32 * S32) + S32 // intermediate signed.scale} d. with optional operand negates.dtype. .b1. . The “plus one” mode (.atype.b2.dtype = . and the operand negates.btype{.

} else if ( c. signedFinal = isSigned(atype) || isSigned(btype) || (a. U32_MAX. atype.s32.po ) { lsb = 1. vmad requires sm_20 or later.u32.h0.u32.Chapter 8. tmp[127:0] = ta * tb.sat ) { if (signedFinal) result = CLAMP(result. r2. r1. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).negate ^ b. } else if ( a. lsb = 1. bsel ). Instruction Set Semantics // extract byte/half-word/word and sign.shr7: result = (tmp >> 7) & 0xffffffffffffffff. } if ( .u32. U32_MIN). S32_MAX. r3.sat vmad. case . if ( . r0. January 24. -r3. tmp = tmp + c128 + lsb. S32_MIN).s32.shr15 r0. else result = CLAMP(result. r1. vmad. lsb = 0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.h0.negate) || c. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. btype.0. switch( scale ) { case .negate ) { tmp = ~tmp.u32. tb = partSelectSignExtend( b.negate ) { c = ~c. 2010 145 .negate. r2. lsb = 1.negate ^ b.or zero-extend based on source operand type ta = partSelectSignExtend( a. asel ).

cmp . c ).asel = .le.asel}.u32. a{. tb. tmp. .add.ge }.0. btype. vset requires sm_20 or later.cmp d.lt vset.eq. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tb = partSelectSignExtend( b. with optional secondary arithmetic operation or subword data merge.cmp d.atype.gt. c ). vset. . .dsel. . // 32-bit scalar operation.atype. r3. d = optSecondaryOp( op2. .min. tmp = compare( ta. { .b2. tmp.s32.asel}.bsel}. with optional data merge vset.bsel}.h0.h1 }.btype. b{. b{.dsel .asel}.PTX ISA Version 2. r1. .btype = { . a{. // 32-bit scalar operation. cmp ) ? 1 : 0. Semantics // extract byte/half-word/word and sign.op2 d. . asel ). b{. . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.op2 Description = = = = .max }. r2. 146 January 24.lt.h1. c.b3.u32. and therefore the c operand and final result are also unsigned.ne r1.bsel = { . Compare input values using specified comparison. . .s32 }.btype. The intermediate result of the comparison is always unsigned. .bsel}.or zero-extend based on source operand type ta = partSelectSignExtend( a. bsel ).u32. .btype. . with optional secondary operation vset.cmp.ne. a{.0 Table 108. atype. c. // optional secondary operation d = optMerge( dsel. r2. .u32.atype. r3. 2010 .atype . .b1. vset.b0. { .

brkpt. January 24.Chapter 8. Supported on all target architectures. numbered 0 through 15. Introduced in PTX ISA version 1. pmevent a. Notes PTX ISA Notes Target ISA Notes Examples Currently. Instruction Set 8. Supported on all target architectures. Table 111. pmevent 7. 2010 147 .0. @p pmevent 1. Table 110. trap. there are sixteen performance monitor events. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. brkpt requires sm_11 or later.0.10. brkpt Suspends execution Introduced in PTX ISA version 1. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. brkpt. trap Abort execution and generate an interrupt to the host CPU.7. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.4. The relationship between events and counters is programmed via API calls from the host. trap. Introduced in PTX ISA version 1. with index specified by immediate operand a. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Triggers one of a fixed number of performance monitor events. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters.

0 148 January 24.PTX ISA Version 2. 2010 .

Special Registers PTX includes a number of predefined. %lanemask_lt. …. which are visible as special registers and accessed through mov or cvt instructions. read-only variables. %lanemask_le. %lanemask_gt %clock. 2010 149 . %clock64 %pm0.Chapter 9. %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %pm3 January 24.

the fourth element is unused and always returns zero. mov.z. .z == 0 in 1D CTAs.z == 1 in 2D CTAs. CTA dimensions are non-zero. %ntid. the %tid value in unused dimensions is 0.y 0 <= %tid.u32 %h1.x. The fourth element is unused and always returns zero. // move tid. The %tid special register contains a 1D. // compute unified thread id for 2D CTA mov. cvt.y * %ntid.y == %tid.z. mov. %ntid.%r0.u32 type in PTX 2.%tid. %ntid. .x < %ntid.x.u32 type in PTX 2. Redefined as .u16 %r2. // CTA shape vector // CTA dimensions A predefined. %tid component values range from 0 through %ntid–1 in each CTA dimension.%ntid.z < %ntid.y. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.0. Every thread in the CTA has a unique %tid. The number of threads in each dimension are specified by the predefined special register %ntid.z == 1 in 1D CTAs.0 Table 112.%h1. Supported on all target architectures.z == 0 in 2D CTAs.x to %rh Target ISA Notes Examples // legacy PTX 1.y.v4 .x code Target ISA Notes Examples 150 January 24.sreg .sreg .u32 %r0. PTX ISA Notes Introduced in PTX ISA version 1. %tid.u32 %ntid.0. . The total number of threads in a CTA is (%ntid. // thread id vector // thread id components A predefined.u32 %r0.x.z to %r2 Table 113.u16 %rh.z).x * %ntid.x code accessing 16-bit component of %tid mov.x.%h2.u32 %tid. or 3D vector to match the CTA shape. It is guaranteed that: 0 <= %tid.%tid.u32. %ntid. . // zero-extend tid.x. mov.v4. mad.y < %ntid.x 0 <= %tid. 2010 . Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.%tid.sreg . %tid.0.%ntid.u32 %ntid.u32 %r1. // legacy PTX 1.sreg .z.y == %ntid.x. per-thread special register initialized with the thread identifier within the CTA. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. Supported on all target architectures. read-only special register initialized with the number of thread ids in each CTA dimension.u32 %tid. mov. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.x.%tid.y. read-only.v4.z PTX ISA Notes Introduced in PTX ISA version 1.%tid.PTX ISA Version 2.0.u32 %h2. %tid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. Redefined as .u16 %rh. 2D. %tid.v4 .

The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.sreg . %nwarpid requires sm_20 or later. read-only special register that returns the thread’s warp identifier. Introduced in PTX ISA version 2. due to rescheduling of threads following preemption. read-only special register that returns the thread’s lane within the warp. . %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.u32 %laneid.g. January 24. %warpid.u32 %r. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. A predefined. The lane identifier ranges from zero to WARP_SZ-1. mov. Special Registers Table 114. Note that %warpid is volatile and returns the location of a thread at the moment when read. 2010 151 .sreg . mov. e. Introduced in PTX ISA version 1. Supported on all target architectures. .sreg . PTX ISA Notes Target ISA Notes Examples Table 116. read-only special register that returns the maximum number of warp identifiers. mov. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.3. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Table 115.u32 %warpid.u32 %r. Introduced in PTX ISA version 1. For this reason. A predefined. but its value may change during execution. The warp identifier will be the same for all threads within a single warp. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %r.3.u32 %nwarpid. %laneid.Chapter 9.0. A predefined. . %nwarpid. Supported on all target architectures.

%rh. The %ctaid special register contains a 1D.%nctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. . %ctaid.u16 %r0. with each element having a value of at least 1.z PTX ISA Notes Introduced in PTX ISA version 1.u32 type in PTX 2. mov.x code Target ISA Notes Examples Table 118.%nctaid. depending on the shape and rank of the CTA grid. %ctaid.x. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. The fourth element is unused and always returns zero.{x.y. Redefined as .sreg .%ctaid. // Grid shape vector // Grid dimensions A predefined.sreg .y < %nctaid.z.u32 %ctaid.y 0 <= %ctaid.u32 %nctaid. The fourth element is unused and always returns zero. Supported on all target architectures.%ctaid. or 3D vector.u16 %r0. It is guaranteed that: 0 <= %ctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.x. // legacy PTX 1.y.z. The %nctaid special register contains a 3D grid shape vector. 2010 .sreg . read-only special register initialized with the number of CTAs in each grid dimension. It is guaranteed that: 1 <= %nctaid.%nctaid.z} < 65. Each vector element value is >= 0 and < 65535. // CTA id vector // CTA id components A predefined. 2D.u32 %ctaid.x < %nctaid.x.u32 %nctaid .x.536 PTX ISA Notes Introduced in PTX ISA version 1.v4 .x code Target ISA Notes Examples 152 January 24. %rh.u32 mov. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.y. .x.0 Table 117.sreg .0.v4.x 0 <= %ctaid.u32 type in PTX 2.PTX ISA Version 2.0.y.0.v4 . mov.%nctaid. Redefined as .v4. Supported on all target architectures. . read-only special register initialized with the CTA identifier within the CTA grid.u32 mov. // legacy PTX 1.z < %nctaid.0.

so %nsmid may be larger than the physical number of SMs in the device. mov.u32 %r. Introduced in PTX ISA version 2. read-only special register that returns the maximum number of SM identifiers.sreg . %nsmid. A predefined.u32 %r. e. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. %nsmid requires sm_20 or later.g. 2010 153 . mov.3. The SM identifier numbering is not guaranteed to be contiguous. %gridid. This variable provides the temporal grid launch number for this context.0. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. %smid. . During execution. Introduced in PTX ISA version 1. // initialized at grid launch A predefined. repeated launches of programs may occur.sreg .Chapter 9. where each launch starts a grid-of-CTAs.u32 %r. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. read-only special register initialized with the per-grid temporal grid identifier. Special Registers Table 119. PTX ISA Notes Target ISA Notes Examples Table 121. PTX ISA Notes Target ISA Notes Examples January 24. due to rescheduling of threads following preemption. mov.u32 %gridid. Introduced in PTX ISA version 1. The SM identifier numbering is not guaranteed to be contiguous.u32 %smid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. .u32 %nsmid.0. but its value may change during execution. The SM identifier ranges from 0 to %nsmid-1. Supported on all target architectures. Note that %smid is volatile and returns the location of a thread at the moment when read. Notes PTX ISA Notes Target ISA Notes Examples Table 120. .sreg . A predefined. Supported on all target architectures.

u32 %r.u32 %lanemask_eq. 2010 . mov. Introduced in PTX ISA version 2.0. %lanemask_eq requires sm_20 or later. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_lt.sreg . %lanemask_le. A predefined. 154 January 24. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg .PTX ISA Version 2. A predefined.sreg . %lanemask_lt requires sm_20 or later. mov. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . A predefined.0.0 Table 122.u32 %r. %lanemask_le requires sm_20 or later. .u32 %r.0. Introduced in PTX ISA version 2.u32 %lanemask_le. %lanemask_eq. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. mov. Table 123.u32 %lanemask_lt. Table 124. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. .

mov. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. %lanemask_gt requires sm_20 or later. Table 126.u32 %lanemask_gt. .0. Special Registers Table 125.u32 %r.u32 %lanemask_ge.Chapter 9. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. A predefined. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge requires sm_20 or later.0. A predefined. %lanemask_ge. 2010 155 . January 24.sreg . mov. %lanemask_gt.u32 %r. .sreg .

%pm3 %pm0. and %pm3 are unsigned 32-bit read-only performance monitor counters.u64 %clock64. The lower 32-bits of %clock64 are identical to %clock. Introduced in PTX ISA version 2. %pm2. %pm1.3. Introduced in PTX ISA version 1.0.PTX ISA Version 2. mov. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Their behavior is currently undefined. 2010 .0 Table 127.sreg . Table 128.u32 r1.u32 r1. read-only 32-bit unsigned cycle counter. Supported on all target architectures. Supported on all target architectures. …. . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm1.%pm0. Special registers %pm0.%clock64. read-only 64-bit unsigned cycle counter. .sreg .0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Introduced in PTX ISA version 1.u32 %clock. 156 January 24. Table 129.%clock.u32 %pm0. %pm1. %clock64 requires sm_20 or later.sreg . mov. %pm2. mov. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u64 r1. %pm3. . %pm2. Special Registers: %pm0.

. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directives are allowed provided they match the original .4 January 24.version 2. Directives 10.target Table 130.0 . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.minor // major. Each ptx file must begin with a . .version Syntax Description Semantics PTX version number.version 1. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.1.version directive. Increments to the major number indicate incompatible changes to PTX.0. Duplicate . minor are integers Specifies the PTX language version number.version directive.version .version .version major. 2010 157 . PTX File Directives: . and the target architecture for which the code was generated. Supported on all target architectures.Chapter 10.

map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.global. Adds {atom. The following table summarizes the features in PTX that vary according to target architecture. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.global. map_f64_to_f32 }. Therefore. immediately followed by a .target Syntax Architecture and Platform target. vote instructions. generations of SM architectures follow an “onion layer” model.5.f64 instructions used. PTX code generated for a given target can be run on later generation devices. Requires map_f64_to_f32 if any .f32.red}. texture and sampler information is referenced with independent . Adds double-precision support.red}. Description Specifies the set of features in the target architecture for which the current ptx code was generated. .texmode_unified) . PTX File Directives: .target directive specifies a single target architecture.texmode_unified . Introduced in PTX ISA version 1. Note that . sm_13.target . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. In general.texmode_independent texture and sampler information is bound together and accessed via a single .texref and . Requires map_f64_to_f32 if any . Disallows use of map_f64_to_f32. including expanded rounding modifiers. sm_12.f64 storage remains as 64-bits. 2010 .target directives can be used to change the set of target features allowed during parsing. sm_11.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. The texturing mode is specified for an entire module and cannot be changed within the module.0. Texturing mode introduced in PTX ISA version 1. 158 January 24. Texturing mode: (default is .samplerref descriptors. texmode_unified. brkpt instructions. A program with multiple . Supported on all target architectures. Requires map_f64_to_f32 if any .f64 to .version directive.f64 instructions used. Each PTX file must begin with a . with only half being used by instructions converted from . texmode_independent. but subsequent .0 Table 131. and an error is generated if an unsupported feature is used.red}.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 instructions used. PTX features are checked against the specified target architecture. Target sm_20 Description Baseline feature set for sm_20 architecture. 64-bit {atom. Adds {atom.target directive containing a target architecture and optional platform options.PTX ISA Version 2. sm_10.texref descriptor. where each generation adds new features and retains all features of previous generations.shared. A .

texmode_independent January 24.Chapter 10.target sm_20. 2010 159 . Directives Examples .target sm_10 // baseline target architecture .target sm_13 // supports double-precision .

reg .3.param. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.entry kernel-name ( param-list ) kernel-body . Supported on all target architectures.param. and .b32 y.surfref variables may be passed as parameters.b32 %r1.4.param instructions. Kernel and Function Directives: .0 through 1. In addition to normal parameters. Parameters may be referenced by name within the kernel body and loaded into registers using ld. ld.samplerref. %nctaid.param instructions. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.entry cta_fft .entry filter ( . parameter variables are declared in the kernel body.entry . Semantics Specify the entry point for a kernel program. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. For PTX ISA versions 1.func Table 132. e.PTX ISA Version 2. 2010 . .b32 %r3.entry kernel-name kernel-body Defines a kernel entry point name. .param . . opaque .param. parameter variables are declared in the kernel parameter list. store.b32 x.entry .texref. [y]. At kernel launch. .param { . … } .0 10.entry Syntax Description Kernel entry point and body. . [z]. ld.4 and later.param . These parameters can only be referenced by name within texture and surface load. and query instructions and cannot be accessed via ld. ld. 160 January 24.g.param space memory and are listed within an optional parenthesized parameter list.b32 %r2.b32 z ) Target ISA Notes Examples [x].5 and later. Parameters are passed via . the kernel dimensions and properties are established and made available via special registers. %ntid. PTX ISA Notes For PTX ISA version 1. with optional parameters. .b32 %r<99>. and body for the kernel function.0 through 1.2. parameters. The shape and size of the CTA executing the kernel are available in special registers. etc.

Supported on all target architectures. Release Notes For PTX ISA version 1. .func . dbl. and supports recursion. if any. there is no stack.func (ret-param) fname (param-list) function-body Defines a function. Parameters must be base types in either the register or parameter state space. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.0 with target sm_20 allows parameters in the .0.b32 N.reg . which may use a combination of registers and stack locations to pass parameters. mov. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. . PTX ISA 2.b32 rval) foo (.2 for a description of variadic functions. Directives Table 133. foo. Parameters in .reg .func Syntax Function definition. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Parameters in register state space may be referenced directly within instructions in the function body.x code.reg .result. implements an ABI with stack. and recursion is illegal.func definition with no body provides a function prototype.param instructions in the body. including input and return parameters and optional function body.b32 localVar.f64 dbl) { . .func fname (param-list) function-body . parameters must be in the register state space. Kernel and Function Directives: .param state space. val1).reg .func fname function-body . … use N.0 with target sm_20 supports at most one return value.func (. A .Chapter 10. Variadic functions are represented using ellipsis following the last fixed argument. (val0. } … call (fooval).param and st. … Description // return value in fooval January 24. The implementation of parameter passing is left to the optimizing translator. 2010 161 . ret. PTX 2.b32 rval. Parameter passing is call-by-value. Variadic functions are currently unimplemented.param space are accessed using ld. The parameter lists define locally-scoped variables in the function body. other code.

or as statements within a kernel or device function body.pragma directive is supported for passing information to the PTX backend.maxnctapersm (deprecated) . which pass information to the backend optimizing compiler.entry directive and its body.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. The interpretation of .maxntid.maxnreg . .maxntid directive specifies the maximum number of threads in a thread block (CTA).pragma The .0 10.g. Currently. the .minnctapersm .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. The directive passes a list of strings to the backend. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. Note that .maxntid and . at entry-scope. 162 January 24.3.PTX ISA Version 2. to throttle the resource requirements (e. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. A general . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. registers) to increase total thread count and provide a greater opportunity to hide memory latency. . and the . 2010 .maxntid .pragma directives may appear at module (file) scope.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). and . PTX supports the following directives. These can be used. and the strings have no semantics within the PTX virtual machine model. for example. the . The directives take precedence over any module-level constraints passed to the optimizing backend. The .maxnreg.minnctapersm directives may be applied per-entry and must appear between an .

ny.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. Performance-Tuning Directives: .maxnreg n Declare the maximum number of registers per thread in a CTA.entry foo . Exceeding any of these limits results in a runtime error or kernel launch failure. . Directives Table 134.maxntid and .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.3.maxntid Syntax Maximum number of threads in thread block (CTA).maxntid 16. The compiler guarantees that this limit will not be exceeded.16.maxntid nx . the backend may be able to compile to fewer registers. Performance-Tuning Directives: . The maximum number of threads is the product of the maximum extent in each dimension. . .maxntid 256 . Supported on all target architectures. The actual number of registers used may be less. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.entry bar . .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid nx.3. Introduced in PTX ISA version 1.entry foo .maxntid . or the maximum number of registers may be further constrained by . Introduced in PTX ISA version 1. or 3D CTA. 2010 163 . for example.Chapter 10. 2D.maxnreg . nz Declare the maximum number of threads in the thread block (CTA). ny .maxntid nx. Supported on all target architectures.maxctapersm.

0.maxnctapersm (deprecated) . Deprecated in PTX ISA version 2.minnctapersm 4 { … } 164 January 24.maxntid to be specified as well.maxntid and .minnctapersm generally need .maxntid 256 . Optimizations based on .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). .3. Supported on all target architectures.maxntid to be specified as well.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.PTX ISA Version 2. .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. additional CTAs may be mapped to a single multiprocessor.maxnctapersm has been renamed to .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. However.entry foo . The optimizing backend compiler uses .0. Supported on all target architectures.maxntid 256 . Optimizations based on . if the number of registers used by the backend is sufficiently lower than this bound.maxnctapersm. 2010 . . Introduced in PTX ISA version 2.minnctapersm in PTX ISA version 2.entry foo . Introduced in PTX ISA version 1.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm .maxnctapersm generally need .0 Table 136.0 as a replacement for . . . For this reason. Performance-Tuning Directives: . Performance-Tuning Directives: .

.pragma directive strings is implementation-specific and has no impact on PTX semantics. See Appendix A for descriptions of the pragma strings defined in ptxas. Supported on all target architectures. The .pragma “nounroll”. or at statementlevel.pragma list-of-strings . The interpretation of . entry-scoped.pragma Syntax Description Pass directives to PTX backend compiler. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Directives Table 138.entry foo .pragma “nounroll”.pragma . . or statement-level directives to the PTX backend compiler. at entry-scope. 2010 165 . Pass module-scoped.pragma directive may occur at module-scope.0. Introduced in PTX ISA version 2. { … } January 24.Chapter 10. Performance-Tuning Directives: .

@@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . replaced by . 0x00. 0x00000364. 0x736d6172 . @progbits . 0x6150736f.. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Table 139.quad int64-list // comma-separated hexadecimal integers in range [0.byte 0x2b. 0x02. 0x00.x code. Introduced in PTX ISA version 1.0 and replaces the @@DWARF syntax.byte byte-list // comma-separated hexadecimal byte values . The @@DWARF syntax is deprecated as of PTX version 2. 0x00 166 January 24.2. Deprecated as of PTX 2. 0x61395a5f. Supported on all target architectures.0 but is supported for legacy PTX version 1.debug_info .4.4byte int32-list // comma-separated hexadecimal integers in range [0.4byte .section directive. @@DWARF dwarf-string dwarf-string may have one of the . 0x63613031. 0x00. “”.4byte 0x6e69616d.file .PTX ISA Version 2.4byte 0x000006b5.byte 0x00.0. 0x00.section . 0x00..section .debug_pubnames. 0x00.4byte label .0 10.232-1] .loc The .section directive is new in PTX ISA verison 2.264-1] . 0x00 . 0x5f736f63 . 2010 .

0x00.0.b32 label ..b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.debug_pubnames { .b32 int32-list // comma-separated list of integers in range [0. Source file location.b8 0x2b. Supported on all target architectures. . } 0x02.Chapter 10.264-1] .b8 byte-list // comma-separated list of integers in range [0. . . replaces @@DWARF syntax. .debug_info .0. Debugging Directives: . 2010 167 . Directives Table 140. 0x00. Source file information. 0x00. Supported on all target architectures..section . Debugging Directives: . 0x5f736f63 0x6150736f. 0x00.file filename Table 142. . Debugging Directives: .section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x6e69616d.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.loc . 0x00.loc line_number January 24.file . 0x00.b32 .b64 int64-list // comma-separated list of integers in range [0. .section Syntax PTX section definition.section .b8 0x00.0. 0x00 0x61395a5f. .. 0x63613031.255] . Supported on all target architectures. 0x736d6172 0x00 Table 141.b32 0x000006b5.232-1] . 0x00000364.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Linking Directives: . Supported on all target architectures.global .visible identifier Declares identifier to be externally visible. Introduced in PTX ISA version 1.visible .global . . // foo will be externally visible 168 January 24.6.b32 foo.extern identifier Declares identifier to be defined externally.0.extern .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible .PTX ISA Version 2. Introduced in PTX ISA version 1.0. Linking Directives . // foo is defined in another module Table 144. Supported on all target architectures.0 10. 2010 .visible Table 143. Linking Directives: . . .extern . .extern .b32 foo.

and the remaining sections provide a record of changes in previous releases.1 CUDA 2.3 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 2.Chapter 11.0 driver r195 PTX ISA Version PTX ISA 1.0 CUDA 1.4 PTX ISA 1. 2010 169 .1 PTX ISA 1.2 PTX ISA 1.5 PTX ISA 2.0.2 CUDA 2.1 CUDA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2. CUDA Release CUDA 1.3 driver r190 CUDA 3. The release history is as follows.0 January 24.0 PTX ISA 1.

1. Single.ftz and . The mad.1.rm and . When code compiled for sm_1x is executed on sm_20 devices.x code and sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added. The goal is to achieve IEEE 754 compliance wherever possible.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Changes in Version 2.f32 require a rounding modifier for sm_20 targets.1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The changes from PTX ISA 1.0 for sm_20 targets. These are indicated by the use of a rounding modifier and require sm_20.ftz modifier may be used to enforce backward compatibility with sm_1x.rp rounding modifiers for sm_20 targets.1.f32 requires sm_20.and double-precision div.f32 for sm_20 targets. and mul now support .sat modifiers.rn. mad. • • • • • 170 January 24.f32 instruction also supports . 2010 . Instructions testp and copysign have been added. Both fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2.f32. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.1. fma. and sqrt with IEEE 754 compliant rounding have been added. New Features 11.0 11. sub. Single-precision add. The . The fma.1. while maximizing backward compatibility with legacy PTX 1. The mad.0 11.f32 maps to fma. rcp.PTX ISA Version 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 and mad.

A system-level membar instruction. prefetchu. isspacep. has been added.section. A “find leading non-sign bit” instruction. has been added. Surface instructions support additional . New instructions A “load uniform” instruction. popc. The bar instruction has been extended as follows: • • • A bar. Release Notes 11.le. suld. has been added. Video instructions (includes prmt) have been added. Instruction sust now supports formatted surface stores. ldu. January 24. has been added. bfind.red. and shared addresses to generic address and vice-versa has been added. membar. Cache operations have been added to instructions ld.u32 and bar.pred have been added.1. has been added.clamp and . A new directive.ge. and red now support generic addressing. st.or}. has been added.red}. %clock64. have been added. Instructions {atom.red. bfe and bfi. Instructions {atom.Chapter 11. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Instructions prefetch and prefetchu have also been added. e. ldu. prefetch. A “count leading zeros” instruction. for prefetching to specified level of memory hierarchy.minnctapersm to better match its behavior and usage.clamp modifiers. vote. A “bit reversal” instruction. Instruction cvta for converting global. . Instructions bar.gt} have been added.ballot.f32 have been implemented. and sust.add.popc. has been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. 2010 171 .1. %lanemask_{eq.arrive instruction has been added.b32. st.1.lt.2. A “population count” instruction.maxnctapersm directive was deprecated and replaced with .shared have been extended to handle 64-bit data types for sm_20 targets.3.zero. brev. Bit field extract and insert instructions. . Other new features Instructions ld.sys. local. cvta. The . clz. bar now supports optional thread count and register operands.1. atom.g. 11. A “vote ballot” instruction.{and.red}. New special registers %nsmid.

See individual instruction descriptions for details. has been fixed. 172 January 24.0 11. In PTX version 1.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.f32 type is unimplemented. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.1.ftz for PTX ISA versions 1.5.ftz (and cvt for .{u32.version is 1. To maintain compatibility with legacy PTX code. The underlying. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.p sust.f32.3.{min. Formatted surface load is unimplemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.4 or earlier.f32} atom.s32.p. call suld. Support for variadic functions and alloca are unimplemented. Formatted surface store with .red}.2. if . 2010 . where .PTX ISA Version 2. or . 11. . stack-based ABI is unimplemented. Semantic Changes and Clarifications The errata in cvt.s32.max} are not implemented. the correct number is sixteen.5 and later. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.target sm_1x. {atom.u32. Instruction bra.1. cvt. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.4 and earlier.

Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. … @p bra L1_end. Supported only for sm_20 targets. Ignored for sm_1x targets. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. disables unrolling of0 the loop for which the current block is the loop header.pragma “nounroll”. .pragma “nounroll”. including loops preceding the . and statement levels. Note that in order to have the desired effect at statement level. entry-function.entry foo (…) . L1_body: … L1_continue: bra L1_head. { … } // do not unroll any loop in this function .pragma. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Descriptions of .func bar (…) { … L1_head: .pragma “nounroll”.Appendix A.0. . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. L1_end: … } // do not unroll this loop January 24. Table 145.pragma strings defined by ptxas. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. 2010 173 . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. The “nounroll” pragma is allowed at module.pragma Strings This section describes the . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. disables unrolling for all loops in the entry function body.

PTX ISA Version 2.0 174 January 24. 2010 .

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