NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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................................... 2010 .........1. 6...4..............1.............................2.................. 29 Local State Space ...................... Texture...................6..... 42 Arrays as Operands .....3................... 47 Chapter 7..................................1.......................5........6............2............................................................................................... Operand Costs ...... State Spaces .......................... and Variables ... 32 5.............. 5........................ 5... Operand Type Information .............. 5. Instruction Operands..........1............................................................4..... Type Conversion................................................................. 39 Parameterized Variable Names ..........................................1.............................2................... 6..................................5............ 34 Variables ....................................................................2...................... 30 Shared State Space................................................................. 41 Source Operands........ 5........................................4.....................................4.....................................4.............................. Summary of Constant Expression Evaluation Rules ....................................................................................5............. 6...........8.......................................................................... 33 Restricted Use of Sub-Word Sizes .....1........................2...............0 4...................... 38 Alignment ....4............................................PTX ISA Version 2......... Types .....4....................... 42 Addresses as Operands ........... State Spaces.... 5............. 6...6..................... and Vectors ............................... 28 Special Register State Space .................3........ 33 Fundamental Types .............................................. 41 6................................ 32 Texture State Space (deprecated) .................................... Abstracting the ABI ..1........... 49 ii January 24............................................................................................. 46 6..............................2..................................... 27 Register State Space ..2.... 6........ 5.................................................................................................................3...........4...... 27 5.................... 5....................................... Function declarations and definitions .......................................... 43 Vectors as Operands ...............1................................... 49 7..........................................1...............................5....................................................... 37 Vectors . 5............................................................................................................ Arrays..........................................5...........................................................1................. 5.........1....................... 5.......................6.............................. Chapter 6............................................ 5................ 6..................................... 44 Scalar Conversions ............... 38 Initializers ......4.. 37 Array Declarations ....................... 39 5........ and Surface Types ................ Types............................................................................................................4................... 29 Parameter State Space .......4..................................................................4...........3...................................1................. 6............ 5.....2.....1.........1..........................1......... Sampler....4.................. 41 Using Addresses....................................................... 5......7...... 33 5..................... 43 6............................. 37 Variable Declarations ..........4......................................4..... 5..................... 29 Global State Space ......5..................... 41 Destination Operands . 44 Rounding Modifiers .............. 28 Constant State Space ........................2.......................... 25 Chapter 5...................1.................................................. 6...... 5..........................................................3........................ 43 Labels and Function Names as Operands .......................................... 6.. 5....

.....7................ 55 PTX Instructions .........................4................ 122 Control Flow Instructions ......10...4............3.............................. 60 8...................7........................ 8............. 162 Debugging Directives ............................................................................ Instructions ..........1......3... PTX Version and Target Directives .......................................................1........................................................................................ 11...1........... 10............................................ 100 Logic and Shift Instructions ............................ 58 8...............7.........3........................ 168 Chapter 11....1.... Special Registers ................................. 129 Parallel Synchronization and Communication Instructions .......................................................................... 170 New Features .......6..................................7........ 10.........8...................3........... 2010 iii ... 81 Comparison and Selection Instructions ... Type Information for Instructions and Operands ........................................................... 53 Alloca .................................... 8........... 157 10.................. 8. 8........1.............. 172 Unimplemented Features Remaining ..........7................................7.............................................. 7........................................ 8...........7.............................................................3............................................... 157 Specifying Kernel Entry Points and Functions ................ 55 Predicated Execution ..........7....... 54 Chapter 8..............1............................................................................................ 8.............................. 11......1.....................0 ............................5.... 8........ 147 8............. 10..................6..................................2...................................... 8...................................... 62 8..6... 62 Semantics .... 169 11....... 8............................... 149 Chapter 10.............7................ 8....... 8.... 56 Comparisons ....................... 8...................................................2..7......7........................................3.............. Changes from PTX 1......... 170 Semantic Changes and Clarifications . 8....... 104 Data Movement and Conversion Instructions .............................. 8........ 140 Miscellaneous Instructions...............1...............9...................1.......... 62 Machine-Specific Semantics of 16-bit Code .. 172 January 24..................................7.............................................................................................................................................................................. 10.............. 166 Linking Directives ........................................2........................................ 57 Manipulating Predicates ........................................7...........................1.................................................... 55 8.... 132 Video Instructions ....... 52 Variadic functions .......2................................................................ 8................................................................2..........................2................................ Release Notes ..........x ......... 63 Integer Arithmetic Instructions ................... Changes in Version 2........3..................................................................................................................................................................... Chapter 9.... Format and Semantics of Instruction Descriptions .......................................................................4........ 7......................... 160 Performance-Tuning Directives ..............................................6...........1....................4....... Instruction Set .............................1...........................5................. 8.................... 11.........................................1............... 63 Floating-Point Instructions ... 108 Texture and Surface Instructions .......... 59 Operand Size Exceeding Instruction-Type Size ............................................................................. Divergence of Threads in Control Constructs .................. Directives ....................

..........PTX ISA Version 2..........pragma Strings............... 2010 ............ Descriptions of ...0 Appendix A..... 173 iv January 24.............

................................................. 2010 v ................................................................................................................................. Table 23........................................................................................................ Table 28..... Table 8................................................................. Table 24............................. Table 10.... 57 Floating-Point Comparison Operators Accepting NaN ..................... 66 Integer Arithmetic Instructions: mul .............................................................................................................................................. 61 Integer Arithmetic Instructions: add ......................................... Table 29.................................. 60 Relaxed Type-checking Rules for Destination Operands....... 65 Integer Arithmetic Instructions: addc .......... Table 19............................cc .............................. Table 6... 71 January 24................................................................... 35 Opaque Type Fields in Independent Texture Mode .......................................................... and Bit-Size Types ............... 70 Integer Arithmetic Instructions: sad ...................................... 65 Integer Arithmetic Instructions: sub............................................................. Table 7........ Table 31... Table 22........................... 57 Floating-Point Comparison Operators ................................ 69 Integer Arithmetic Instructions: mad24 ..................................................... Table 17........ Table 20................................. Table 11........ 23 Constant Expression Evaluation Rules ................. 47 Operators for Signed Integer................ Table 13................. 58 Floating-Point Comparison Operators Testing for NaN ......... 64 Integer Arithmetic Instructions: sub .................................. 19 Predefined Identifiers ................ 46 Cost Estimates for Accessing State-Spaces .......................................................................... 67 Integer Arithmetic Instructions: mad ...................................................................................... Table 15...... Table 27.................................................. 18 Reserved Instruction Keywords ...................... 58 Type Checking Rules ......................... Unsigned Integer..................................................... 66 Integer Arithmetic Instructions: subc ........ 64 Integer Arithmetic Instructions: add........ 68 Integer Arithmetic Instructions: mul24 ............................................ Table 14................................. PTX Directives ............... 46 Integer Rounding Modifiers ............. 20 Operator Precedence ............... Table 9. 45 Floating-Point Rounding Modifiers ........ 28 Fundamental Type Specifiers ............................................... Table 18....List of Tables Table 1........... 27 Properties of State Spaces .................................................. Table 21............... Table 30............................ Table 5........................................................................................................................... Table 25...................................................... 35 Convert Instruction Precision and Format ....................................................... Table 12........... Table 32.......................... Table 4.................................................................... 59 Relaxed Type-checking Rules for Source Operands .................... Table 2...................... Table 16......cc .................. Table 26....................................................... Table 3...................... 25 State Spaces .......... 33 Opaque Type Fields in Unified Texture Mode ...

...... 85 Floating-Point Instructions: mul . 103 Comparison and Selection Instructions: slct ............. 91 Floating-Point Instructions: min ................................ Table 57..................................... 73 Integer Arithmetic Instructions: max ......................... 92 Floating-Point Instructions: max ................................................ 76 Integer Arithmetic Instructions: bfe ........................... 71 Integer Arithmetic Instructions: rem ......................... Table 64.......................... Table 49.......... 83 Floating-Point Instructions: add .............. Table 40.............................. 98 Floating-Point Instructions: ex2 .............. 2010 .......... Table 54...... Table 45.............................................. 93 Floating-Point Instructions: sqrt ............................................... 78 Integer Arithmetic Instructions: prmt ............. Table 59........ 102 Comparison and Selection Instructions: selp ........ 77 Integer Arithmetic Instructions: bfi ...................................................................................................... Table 55. 96 Floating-Point Instructions: cos ............................................................. Table 41............................. Table 44................................ 84 Floating-Point Instructions: sub ............................................ Table 35............................ Table 58................................. Table 39............................... Table 34........................................... Table 52......................................................... Table 56........................................................................................................................... Table 48........................................... Table 67............................PTX ISA Version 2....................................................................... Table 50.................................................................................................................. Table 68........................... Table 38.............................. 94 Floating-Point Instructions: rsqrt ............................... 71 Integer Arithmetic Instructions: abs ... Table 51........ 74 Integer Arithmetic Instructions: bfind .......................................................... 101 Comparison and Selection Instructions: setp .................................................. Table 61......... Table 46.... Table 65........................ 86 Floating-Point Instructions: fma ........................ 87 Floating-Point Instructions: mad ......................... Integer Arithmetic Instructions: div .......... 97 Floating-Point Instructions: lg2 ................................................................... Table 36............................................................ 72 Integer Arithmetic Instructions: min .................... Table 62.....................................................................................................................................................................................0 Table 33..................... 75 Integer Arithmetic Instructions: brev ............ 72 Integer Arithmetic Instructions: neg ..... Table 60............ Table 43.................. 103 vi January 24........................................................................... Table 69............................................. 95 Floating-Point Instructions: sin ....................................... 88 Floating-Point Instructions: div ........ Table 37.............................................. Table 63......................... 74 Integer Arithmetic Instructions: clz ..................................................................................................................... 73 Integer Arithmetic Instructions: popc .................................................................................... 79 Summary of Floating-Point Instructions ................................... 99 Comparison and Selection Instructions: set ............................. 92 Floating-Point Instructions: rcp .................. 90 Floating-Point Instructions: abs .................................................... 82 Floating-Point Instructions: testp .. Table 42...... Table 53.................................. Table 47............................................................................................................. 91 Floating-Point Instructions: neg .. 83 Floating-Point Instructions: copysign .................................................................. Table 66...................................

............................................................... 112 Data Movement and Conversion Instructions: ld ................ 126 Texture and Surface Instructions: sured............................ Table 100................... Table 77............... Table 80........ 130 Control Flow Instructions: call ..... 129 Control Flow Instructions: bra ................................................................. vabsdiff........... 105 Logic and Shift Instructions: or ....................................................................................................... 119 Data Movement and Conversion Instructions: cvta .............................................................Table 70............................................................................... 107 Logic and Shift Instructions: shr ........ Table 98......................... 127 Texture and Surface Instructions: suq ........... 123 Texture and Surface Instructions: txq . Table 87................................ Table 91.......................................................................................................... Table 92......... 134 Parallel Synchronization and Communication Instructions: atom ............................................................................ Table 71............................................................................................................. 124 Texture and Surface Instructions: suld ..... Table 84............................ 133 Parallel Synchronization and Communication Instructions: membar ........................... 131 Control Flow Instructions: exit ................. Table 97... Table 103. Table 81....................................... 105 Logic and Shift Instructions: xor ......................... Table 83..... 110 Data Movement and Conversion Instructions: mov ..... Table 79...... Table 78.................................................... Table 88. 143 January 24.............. 111 Data Movement and Conversion Instructions: mov ................. vmin.... Table 106...................... Table 93.............. Table 89............................ vsub..... Table 73..... Table 72............................................................... 131 Parallel Synchronization and Communication Instructions: bar ................................... Table 76...................................................................................................................................... vmax ...................... Table 75.................. 128 Control Flow Instructions: { } ..... Table 102............. Table 82............................. 142 Video Instructions: vshl........................................................... 139 Video Instructions: vadd.............................. 137 Parallel Synchronization and Communication Instructions: vote .................................................................................. 120 Texture and Surface Instructions: tex . Table 85... 113 Data Movement and Conversion Instructions: ldu ................. Table 95...... Table 96............................. 106 Logic and Shift Instructions: cnot ...................... 129 Control Flow Instructions: @ ................. Table 74..... Table 104................ 118 Data Movement and Conversion Instructions: isspacep ....................................... Table 105.................................................................. vshr .......................................... Table 99................. 125 Texture and Surface Instructions: sust ................................................. 135 Parallel Synchronization and Communication Instructions: red .......... Logic and Shift Instructions: and ........................... 2010 vii ...... Table 94..... 109 Cache Operators for Memory Store Instructions . Table 86.................. 119 Data Movement and Conversion Instructions: cvt .......... Table 90..... 115 Data Movement and Conversion Instructions: st .... 116 Data Movement and Conversion Instructions: prefetch..................... 106 Logic and Shift Instructions: shl ......................... 130 Control Flow Instructions: ret ................. 106 Logic and Shift Instructions: not .. prefetchu ................ Table 101..................................................................... 107 Cache Operators for Memory Load Instructions .

............... 167 Debugging Directives: ....PTX ISA Version 2................................................................ Table 127............................. 164 Performance-Tuning Directives: ..... Table 141..............................entry....target ...... 154 Special Registers: %lanemask_ge ..................section .......................... Table 139.................................................................... 156 PTX File Directives: ............... %pm1. Table 115................................................................................. 156 Special Registers: %pm0..maxnreg .......................................version.............. 147 Miscellaneous Instructions: brkpt ....................... 161 Performance-Tuning Directives: ................................. Table 130.............................................................................................................................................................................. Table 108..................................................................................... 147 Miscellaneous Instructions: pmevent................................... Table 124.. Table 114................................. 163 Performance-Tuning Directives: ............................................................... 2010 ............func .. Table 132..................................................... 154 Special Registers: %lanemask_lt .................................... Video Instructions: vmad ........................................ Table 135. %pm2................................ Table 133....... 152 Special Registers: %nctaid .. Table 116.... 153 Special Registers: %gridid ................................ Table 137................... 164 Performance-Tuning Directives: .................................................................. Table 126..........................maxntid .................................................................. Table 110..............................................................extern..... Table 136.......................................................................................... 153 Special Registers: %lanemask_eq ........ Table 134.................................. Table 131............................................ 144 Video Instructions: vset....................... 157 PTX File Directives: ... 167 Linking Directives: ................ 158 Kernel and Function Directives: ...................................... 160 Kernel and Function Directives: ....................... 146 Miscellaneous Instructions: trap ............................................................ Table 140......... Table 112.... Table 138.............. Table 143.................................................................................. 151 Special Registers: %ctaid ..................pragma ......................................... 152 Special Registers: %smid ........ 153 Special Registers: %nsmid .............minnctapersm ..... Table 120..................loc ........................................................................................................................................................................................ 147 Special Registers: %tid ... Table 125...... Table 129........................................................................ Table 121.............. Table 128...... Table 119........ 155 Special Registers: %clock ............. Table 142....... 168 viii January 24..... 167 Debugging Directives: ................... Table 123..... 166 Debugging Directives: .................................. 156 Special Registers: %clock64 ..........................maxnctapersm (deprecated) ....................................... Table 109. 150 Special Registers: %ntid ....... 150 Special Registers: %laneid ................. 155 Special Registers: %lanemask_gt .....................................................................0 Table 107..................... 163 Performance-Tuning Directives: .................... 154 Special Registers: %lanemask_le ........... %pm3 ................................................................... Table 111... Table 113......................................... Table 117............................................... 165 Debugging Directives: @@DWARF ............ Table 118.. Table 122............................................... 151 Special Registers: %nwarpid ........ 151 Special Registers: %warpid ...................................file ......

.................................Table 144................. Linking Directives: ............................... Table 145........................ 168 Pragma Strings: “nounroll” ...visible............... 173 January 24......................... 2010 ix .......................

2010 .PTX ISA Version 2.0 x January 24.

It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. there is a lower requirement for sophisticated flow control. which are optimized for and translated to native target-architecture instructions. Data-parallel processing maps data elements to parallel processing threads. and because it is executed on many data elements and has high arithmetic intensity. 1. and pattern recognition can map image blocks and pixels to parallel processing threads. PTX programs are translated at install time to the target hardware instruction set. the programmable GPU has evolved into a highly parallel. high-definition 3D graphics. 1. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. from general signal processing or physics simulation to computational finance or computational biology. image scaling. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. image and media processing applications such as post-processing of rendered images. multithreaded. In fact. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.1. stereo vision. the memory access latency can be hidden with calculations instead of big data caches. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. January 24. 2010 1 . many-core processor with tremendous computational horsepower and very high memory bandwidth. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. Similarly. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Many applications that process large data sets can use a data-parallel programming model to speed up the computations. PTX defines a virtual machine and ISA for general purpose parallel thread execution. PTX exposes the GPU as a data-parallel computing device. Because the same program is executed for each data element. video encoding and decoding.2. Introduction This document describes PTX.Chapter 1. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. In 3D rendering large sets of pixels and vertices are mapped to parallel threads.

x. Instructions marked with .rm and . Provide a machine-independent ISA for C/C++ and other compilers to target. Legacy PTX 1.rp rounding modifiers for sm_20 targets.rn. and video instructions.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.PTX ISA Version 2. and all PTX 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. The mad. 1.ftz) modifier may be used to enforce backward compatibility with sm_1x.f32 instruction also supports . extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. and mul now support . Single-precision add. The main areas of change in PTX 2. and the introduction of many new instructions. Most of the new features require a sm_20 target. performance kernels.f32 for sm_20 targets. • • • 2 January 24. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. The mad. Both fma.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.f32 require a rounding modifier for sm_20 targets. reduction. surface.f32.f32 and mad. PTX 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.x features are supported on the new sm_20 target.f32 maps to fma.f32 requires sm_20. A “flush-to-zero” (. Achieve performance in compiled applications comparable to native GPU performance. When code compiled for sm_1x is executed on sm_20 devices. including integer. fma. Facilitate hand-coding of libraries. A single-precision fused multiply-add (fma) instruction has been added. The fma.ftz and .0 is in improved support for the IEEE 754 floating-point standard.sat modifiers. Provide a code distribution ISA for application and middleware developers.1.0 are improved support for IEEE 754 floating-point operations. addition of generic addressing to facilitate the use of general-purpose pointers. 1. which map PTX to specific target machines.3. Improved Floating-Point Support A main area of change in PTX 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. and architecture tests.0 is a superset of PTX 1. 2010 . Provide a common source-level ISA for optimizing code generators and translators. The changes from PTX ISA 1. PTX ISA Version 2. sub. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. memory. barrier.3.0 PTX ISA Version 2.x code will continue to run on sm_1x targets as well. mad. atomic.

These are indicated by the use of a rounding modifier and require sm_20.2. prefetchu. Surface instructions support additional clamp modifiers.3. and sust.clamp and . and directives are introduced in PTX 2. January 24. these changes bring PTX 2. Introduction • Single. and shared state spaces. i. rcp. • Taken as a whole. for prefetching to specified level of memory hierarchy. local. 1. allowing memory instructions to access these spaces without needing to specify the state space. A new cvta instruction has been added to convert global. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.and double-precision div. and red now support generic addressing.Chapter 1.e. 1.g. and shared addresses to generic addresses. and shared addresses to generic address and vice-versa has been added. suld. an address that is the same across all threads in a warp. Instructions testp and copysign have been added. ldu.3. and sqrt with IEEE 754 compliant rounding have been added. Generic addressing unifies the global. PTX 2. 2010 3 . Generic Addressing Another major change is the addition of generic addressing. e.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. In PTX 2. instructions ld. and vice versa.0.. st.zero. local. stack layout. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. Instructions prefetch and prefetchu have been added. special registers. Instruction cvta for converting global. Cache operations have been added to instructions ld.4. st. Surface Instructions • • Instruction sust now supports formatted surface stores. prefetch.0 closer to full compliance with the IEEE 754 standard. NOTE: The current version of PTX does not implement the underlying. cvta. atom. New Instructions The following new instructions. . isspacep. so recursion is not yet supported. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. 1.3. local.3.0. Support for an Application Binary Interface Rather than expose details of a particular calling convention. stack-based ABI. and Application Binary Interface (ABI).

sys.ballot.popc.or}.red}.red.{and.pred have been added.le.u32 and bar.b32. %clock64.red}. bar now supports an optional thread count and register operands.gt} have been added. Instructions bar. New special registers %nsmid. vote. %lanemask_{eq. has been added.shared have been extended to handle 64-bit data types for sm_20 targets. has been added. Instructions {atom. A “vote ballot” instruction. 4 January 24. Barrier Instructions • • A system-level membar instruction.section. A bar.lt.add. 2010 . Reduction. and Vote Instructions • • • New atomic and reduction instructions {atom.PTX ISA Version 2. bfi bit field extract and insert popc clz Atomic.ge.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. A new directive. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. .arrive instruction has been added.f32 have been added. Other Extensions • • • Video instructions (includes prmt) have been added.red. membar.

Chapter 6 describes instruction operands. Chapter 5 describes state spaces. 2010 5 . Introduction 1. Chapter 7 describes the function and call syntax. calling convention.4. Chapter 8 describes the instruction set. types. Chapter 9 lists special registers. and PTX support for abstracting the Application Binary Interface (ABI). and variable declarations. Chapter 4 describes the basic syntax of the PTX language. January 24. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 10 lists the assembly directives supported in PTX. Chapter 11 provides release notes for PTX Version 2.0.Chapter 1.

PTX ISA Version 2.0 6 January 24. 2010 .

2D. one can specify synchronization points where threads wait until all threads in the CTA have arrived. or host: In other words. The vector ntid specifies the number of threads in each CTA dimension. 2. data-parallel. or 3D shape specified by a three-element vector ntid (with elements ntid.2. or CTA. compute-intensive portions of applications running on the host are off-loaded onto the device.2.x. It operates as a coprocessor to the main CPU. can be isolated into a kernel function that is executed on the GPU as many different threads. Cooperative thread arrays (CTAs) implement CUDA thread blocks. More precisely. Each CTA has a 1D. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. ntid.x. Each thread has a unique thread identifier within the CTA. but independently on different data.y. Programming Model 2. a portion of an application that is executed many times. January 24.y. and select work to perform. and ntid. and results across the threads of the CTA. (with elements tid.1.1. tid. work. To coordinate the communication of the threads within the CTA. Threads within a CTA can communicate with each other. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. Programs use a data parallel decomposition to partition inputs. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. A cooperative thread array.z) that specifies the thread’s position within a 1D. 2D. assign specific input and output positions. The thread identifier is a three-element vector tid. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. Each CTA thread uses its thread identifier to determine its assigned role.z). compute addresses. 2010 7 . is an array of threads that execute a kernel concurrently or in parallel. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. To that effect. or 3D CTA. and tid.Chapter 2. 2.

However.2. %nctaid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. WARP_SZ. 8 January 24. so PTX includes a run-time immediate constant. Typically. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Some applications may be able to maximize performance with knowledge of the warp size. 2D .PTX ISA Version 2. depending on the platform. Each grid of CTAs has a 1D. and %gridid. so that the total number of threads that can be launched in a single kernel invocation is very large. which may be used in any instruction where an immediate operand is allowed. or sequentially. Threads within a warp are sequentially numbered. This comes at the expense of reduced thread communication and synchronization. read-only special registers %tid. because threads in different CTAs cannot communicate and synchronize with each other. such that the threads execute the same instructions at the same time. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. %ctaid. multiple-thread) fashion in groups called warps.2. Threads may read and use these values through predefined. %ntid. 2010 . Each grid also has a unique temporal grid identifier (gridid). CTAs that execute the same kernel can be batched together into a grid of CTAs. Multiple CTAs may execute concurrently and in parallel. or 3D shape specified by the parameter nctaid. A warp is a maximal subset of threads from a single CTA. The host issues a succession of kernel invocations to the device. The warp size is a machine-dependent constant.0 Threads within a CTA execute in SIMT (single-instruction. 2. a warp has 32 threads.

1) Thread (0. 0) CTA (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Grid 2 Kernel 2 CTA (1. 2010 9 . 0) CTA (1. Thread Batching January 24. 1) Thread (0. 1) CTA (2. 1) Thread (4. 1) Thread (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) CTA (0. 2) Thread (1. 1) CTA (1. 2) Thread (4. A grid is a set of CTAs that execute independently. 2) Thread (3.Chapter 2. 0) Thread (1. 1) Thread (2. 0) Thread (2. 1) Thread (3. 0) Thread (3. 0) Thread (4. Figure 1. 0) Thread (0. 2) Thread (2.

referred to as host memory and device memory. and texture memory spaces are persistent across kernel launches by the same application. and texture memory spaces are optimized for different memory usages. Both the host and the device maintain their own local memory. as well as data filtering. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. The device memory may be mapped and read or written by the host.PTX ISA Version 2. for more efficient transfer. The global. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. for some specific data formats. or. constant. 2010 . There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.0 2. respectively. Each thread has a private local memory.3. 10 January 24. Texture memory also offers different addressing modes. Finally. all threads have access to the same global memory. constant.

1) Block (2. 1) Grid 1 Global memory Block (0. 1) Block (1. 2) Block (1. 1) Block (0. 0) Block (1. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (2. 2010 11 .Chapter 2. 0) Block (0. 2) Figure 2. 0) Block (1. Memory Hierarchy January 24. 1) Block (1.

2010 .PTX ISA Version 2.0 12 January 24.

Chapter 3. for example. and when all paths complete. The way a block is split into warps is always the same. and executes concurrent threads in hardware with zero scheduling overhead. It implements a single-instruction barrier synchronization. The threads of a thread block execute concurrently on one multiprocessor. allowing. The multiprocessor creates. 2010 13 . and each scalar thread executes independently with its own instruction address and register state. the threads converge back to the same execution path. (This term originates from weaving. the multiprocessor employs a new architecture we call SIMT (single-instruction. At every instruction issue time. The multiprocessor SIMT unit creates. disabling threads that are not on that path. a cell in a grid-based computation). multiple-thread). new blocks are launched on the vacated multiprocessors. so full efficiency is realized when all threads of a warp agree on their execution path. and executes threads in groups of parallel threads called warps. To manage hundreds of threads running several different programs. a voxel in a volume. As thread blocks terminate. January 24. Branch divergence occurs only within a warp. The multiprocessor maps each thread to one scalar processor core.1. A multiprocessor consists of multiple Scalar Processor (SP) cores.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). schedules. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. When a host program invokes a kernel grid. manages. a multithreaded instruction unit. When a multiprocessor is given one or more thread blocks to execute. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. Parallel Thread Execution Machine Model 3. it splits them into warps that get scheduled by the SIMT unit. increasing thread IDs with the first warp containing thread 0. and on-chip shared memory. A warp executes one common instruction at a time. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. each warp contains threads of consecutive. If threads of a warp diverge via a data-dependent conditional branch. manages. different warps execute independently regardless of whether they are executing common or disjointed code paths. the first parallel thread technology. the warp serially executes each branch path taken.

each read. Vector architectures. If there are not enough registers or shared memory available per multiprocessor to process at least one block. 2010 . the kernel will fail to launch. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. and writes to the same location in global memory for more than one of the threads of the warp. A key difference is that SIMD vector organizations expose the SIMD width to the software. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. but one of the writes is guaranteed to succeed. on the other hand. however. whereas SIMT instructions specify the execution and branching behavior of a single thread. For the purposes of correctness. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. • The local and global memory spaces are read-write regions of device memory and are not cached. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. scalar threads.0 SIMT architecture is akin to SIMD (Single Instruction. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. modify. require the software to coalesce loads into vectors and manage divergence manually. but the order in which they occur is undefined. If an atomic instruction executed by a warp reads.PTX ISA Version 2. A multiprocessor can execute as many as eight thread blocks concurrently. which is a read-only region of device memory. as well as data-parallel code for coordinated threads. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. 14 January 24. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. As illustrated by Figure 3. In practice. SIMT enables programmers to write thread-level parallel code for independent. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. which is a read-only region of device memory. In contrast with SIMD vector machines. modifies. the number of serialized writes that occur to that location and the order in which they occur is undefined. write to that location occurs and they are all serialized. the programmer can essentially ignore the SIMT behavior.

2010 15 . Hardware Model January 24. Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3.

PTX ISA Version 2.0 16 January 24. 2010 .

version directive specifying the PTX language version. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. followed by a . #define. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #else. #line. whitespace is ignored except for its use in separating tokens in the language. Pseudo-operations specify symbol and addressing management. and using // to begin a comment that extends to the end of the current line. #endif. 2010 17 . The following are common preprocessor directives: #include. See Section 9 for a more information on these directives. Comments Comments in PTX follow C/C++ syntax. Each PTX file must begin with a . The C preprocessor cpp may be used to process PTX source files. Syntax PTX programs are a collection of text source files. 4.1. PTX is case sensitive and uses lowercase for keywords. #ifdef. Lines beginning with # are preprocessor directives. Comments in PTX are treated as whitespace. All whitespace characters are equivalent.Chapter 4. Source Format Source files are ASCII text. 4. #if. Lines are separated by the newline character (‘\n’).target directive specifying the target architecture assumed. using non-nested /* and */ for comments that may span multiple lines. January 24.2.

3. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.pragma . r2.5. The guard predicate may be optionally negated. r2.entry .minnctapersm .b32 add. constant expressions. 18 January 24.visible 4. 2. All instruction keywords are reserved tokens in PTX. shl. 0.file PTX Directives . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.1.3. r2.maxnreg .global . r1.param . 2010 . and terminated with a semicolon.maxnctapersm .3. so no conflict is possible with user-defined identifiers.0 4. Instructions have an optional guard predicate which controls conditional execution.global start: . written as @!p.b32 r1.shared .x.sreg .extern .const .target .f32 r2.local .maxntid . where p is a predicate register. The destination operand is first. .version . .2.align .func .section .PTX ISA Version 2. Instruction keywords are listed in Table 2.loc .global.reg . followed by source operands. ld. %tid.b32 r1. The guard predicate follows the optional label and precedes the opcode. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.b32 r1. Examples: . and is written as @p. Operands may be register variables. Table 1. Directive Statements Directive keywords begin with a dot.f32 array[N].reg . array[r1]. or label names.tex . Statements begin with an optional label and end with a semicolon. Statements A PTX statement is either a directive or an instruction. address expressions. mov.

Chapter 4. Syntax Table 2. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

or percentage character followed by one or more letters. e. The percentage sign can be used to avoid name conflicts.g. Table 3. underscore. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. underscore. digits. …. between user-defined variable names and compiler-generated names. digits. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. Many high-level languages such as C and C++ follow similar rules for identifier names.4. except that the percentage sign is not allowed.PTX ISA Version 2. PTX predefines one constant and a small number of special registers that begin with the percentage sign. or dollar characters. 2010 . %pm3 WARP_SZ 20 January 24. listed in Table 3.0 4. or they start with an underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. PTX allows the percentage sign as the first character of an identifier. dollar.

Type checking rules remain the same for integer.Chapter 4.5. i. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. in which case the literal is unsigned (. the constant begins with 0f or 0F followed by 8 hex digits. literals are always represented in 64-bit double-precision format. 4. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. 4.s64) unless the value cannot be fully represented in . and bit-size types.e. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. Integer literals may be written in decimal.5..5. The syntax follows that of C. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. To specify IEEE 754 doubleprecision floating point values. These constants may be used in data initialization and as operands to instructions. Constants PTX supports integer and floating-point constants and constant expressions. octal. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. every integer constant has type . each integer constant is converted to the appropriate size based on the data or instruction type at its use. hexadecimal. integer constants are allowed and are interpreted as in C. i.u64. zero values are FALSE and non-zero values are TRUE. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. where the behavior of the operation depends on the operand types. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Syntax 4. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.u64).s64 or the unsigned suffix is specified. or binary notation. 0[fF]{hexdigit}{8} // single-precision floating point January 24. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. there is no suffix letter to specify size.s64 or . Floating-point literals may be written with an optional decimal point and an optional signed exponent. For predicate-type data and instructions. When used in an instruction or data initialization. the constant begins with 0d or 0D followed by 16 hex digits.e. Unlike C and C++.1. floating-point. 2010 21 .2.. To specify IEEE 754 single-precision floating point values.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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f64 use usual conversions .u64 .u64) (.u64 .f64 integer .s64 .s64 .u64 1st unchanged. 2010 25 .s64 .s64 .s64 .5.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .f64 integer .f64 use usual conversions .f64 use usual conversions .f64 : . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table. Table 5.u64 .f64 converted type .s64 .f64 converted type constant literal + ! ~ Cast Binary (.6.f64 integer integer integer integer integer int ?. 2nd is .u64.u64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source . Syntax 4. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .Chapter 4.s64) + .s64.f64 same as source .s64 .u64 same as 1st operand .u64 . or .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. .s64 .

0 26 January 24.PTX ISA Version 2. 2010 .

param . platform-specific. Types. Table 6. Shared. Name State Spaces Description Registers. access speed.local . and properties of state spaces are shown in Table 5. State Spaces.global . 2010 27 .tex January 24. and level of sharing between threads. and these resources are abstracted in PTX through state spaces and data types. the kinds of resources will be common across platforms. defined per-thread. access rights. and Variables While the specific resources available in a given target GPU will vary. Addressable memory shared between threads in 1 CTA. State Spaces A state space is a storage area with particular characteristics. addressability. or Function or local parameters. The list of state spaces is shown in Table 4. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. defined per-grid. Kernel parameters. 5. Local memory. .reg . The characteristics of a state space include its size. Special registers. private to each thread. fast. shared by all threads. Read-only.const .Chapter 5.sreg .shared .1. All variables reside in some state space. pre-defined. read-only memory. Global memory. Global texture memory (deprecated).

. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. register variables will be spilled to memory.global . scalar registers have a width of 8-. 64-.PTX ISA Version 2. 3 Accessible only via the tex instruction. or 128-bits.1. st. CTA. All special registers are predefined.param instruction. Special Register State Space The special register (. The most common use of 8-bit registers is with ld. 1 Accessible only via the ld. Register size is restricted. or 64-bits. 16-.e. unsigned integer. 32-.sreg . Address may be taken via mov instruction.tex Restricted Yes No3 5. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 2010 .param and st.local .sreg) state space holds predefined.0 Table 7. floating point. or as elements of vector tuples. and cvt instructions. and thread parameters. 32-. it is not possible to refer to the address of a register. predicate) or untyped. Registers may be typed (signed integer.reg . and vector registers have a width of 16-. such as grid. the parameter is then located on the stack frame and its address is in the .1. 28 January 24.1.reg state space) are fast storage locations. Register State Space Registers (. Registers differ from the other state spaces in that they are not fully addressable. platform-specific registers.param (as input to kernel) . 5. and performance monitoring registers. The number of registers is limited. When the limit is exceeded.local state space.param instructions. and will vary from platform to platform. clock counters.2. Device function input parameters may have their address taken via mov. i.param (used in functions) . causing changes in performance.shared . Registers may have alignment boundaries required by multi-word loads and stores. aside from predicate registers which are 1-bit. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 2 Accessible via ld. For each architecture.const .

the store operation updating a may still be in flight. Types. Local State Space The local state space (.1. For example. Sequential consistency is provided by the bar. 5. st.const[2] . For the current devices. bank zero is used for all statically-sized constant variables.b32 const_buffer[].1.global. Module-scoped local memory variables are stored at fixed addresses. [const_buffer+4]. Global State Space The global (. each pointing to the start address of the specified constant bank. Constant State Space The constant (.b32 const_buffer[]. as it must be allocated on a perthread basis.extern . This pointer can then be used to access the entire 64KB constant bank. where bank ranges from 0 to 10. If another thread sees the variable b change. // load second word 5.1.global) state space is memory that is accessible by all threads in a context. where the size is not known at compile time. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.global to access global variables. It is the mechanism by which different CTAs and different grids can communicate. It is typically standard memory with cache.const[2]. The size is limited. In implementations that support a stack. State Spaces. bank zero is used. initialized by the host. Consider the case where one thread executes the following two assignments: a = a + 1. Threads must be able to do their work without waiting for other threads to do theirs. By convention.sync instruction.local and st.global.const[2] . there are eleven 64KB banks.const) state space is a read-only memory. For example.const[bank] modifier. The remaining banks may be used to implement “incomplete” constant arrays (in C.local to access local variables. and Variables 5.Chapter 5. for example). Multiple incomplete array variables declared in the same bank become aliases. The constant memory is organized into fixed size banks.local) is private memory for each thread to keep its own data.3. All memory writes prior to the bar. If no bank number is given. For any thread in a context. Use ld. ld. b = b – 1. This reiterates the kind of parallelism available in machines that run PTX. the stack is in local memory. the bank number must be provided in the state space of the load instruction.b32 %r1. 2010 29 . Banks are specified using the . To access data in contant banks 1 through 10. as in lock-free and wait-free style programming.extern . Global memory is not sequentially consistent.5. Use ld.4.sync instruction are guaranteed to be visible to any reads after the barrier instruction. results in const_buffer pointing to the start of constant bank two. Threads wait at the barrier until all threads in the CTA have arrived. and atom. the declaration . all addresses are in global memory are shared. an incomplete array in bank 2 is accessed as follows: . whereas local memory variables declared January 24.

5. The use of parameter state space for device function parameters is new to PTX ISA version 2. len.param space. Similarly.reg . (2a) to declare formal input and return parameters for device functions called from within kernel execution.0 within a function or kernel body are allocated on the stack. 5.6. [%ptr]. .PTX ISA Version 2. %n.u32 %n.u32 %n. … Example: .param .x supports only kernel function parameters in .b8 buffer[64] ) { .b32 len ) { . The kernel parameter variables are shared across all CTAs within a grid. Values passed from the host to the kernel are accessed through these parameter variables using ld. all local memory variables are stored at fixed addresses and recursive function calls are not supported.param. [buffer].param. 2010 .u32 %ptr.f64 %d. These parameters are addressable.param.param) state space is used (1) to pass input arguments from the host to the kernel.u32 %n. Parameter State Space The parameter (. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. For example. device function parameters were previously restricted to the register state space. mov.f64 %d. Therefore.1. typically for passing large structures by value to a function. The resulting address is in the . per-kernel versus per-thread).align 8 .param .6. [N]. Example: .reg . … 30 January 24.u32 %ptr. read-only variables declared in the . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).0 and requires target architecture sm_20. PTX code should make no assumptions about the relative locations or ordering of . The address of a kernel parameter may be moved into a register using the mov instruction.param .param instructions. Note: The location of parameter space is implementation specific. No access protection is provided between parameter and global space in this case. ld.entry bar ( . ld.1. ld.param state space and is accessed using ld. Note that PTX ISA versions 1.entry foo ( .b32 N. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.reg .param state space.1.param space variables.param instructions. In implementations that do not support a stack. in some implementations kernel parameters reside in global memory. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. .

Example: // pass object of type struct { double d. st. . }.param .local instructions. [buffer+8].2.param. State Spaces. Device Function Parameters PTX ISA version 2.align 8 .param and function return parameters may be written using st.param space is also required whenever a formal parameter has its address taken within the called function. . int y.param. In this case.s32 %y.b8 buffer[12] ) { . Aside from passing structures by value.local and st. January 24.reg . Note that the parameter will be copied to the stack if necessary. is flattened.b8 mystruct. and so the address will be in the . ld.0 extends the use of parameter space to device function parameters.param space variable.Chapter 5.f64 %d.param .param.f64 [mystruct+0]. It is not possible to use mov to get the address of a return parameter or a locally-scoped . The most common use is for passing objects by value that do not fit within a PTX register. .func foo ( . passed to foo … .align 8 . mystruct). call foo.f64 dbl.param. [buffer]. Types. such as C structures larger than 8 bytes. the caller will declare a locally-scoped .f64 %d. . and Variables 5.s32 [mystruct+8].6. a byte array in parameter space is used. . int y. } mystruct. which declares a . … See the section on function call syntax for more details.reg .b32 N.param formal parameter having the same size and alignment as the passed argument. This will be passed by value to a callee.1. .reg . Typically. … st.reg .param byte array variable that represents a flattened C structure or union. Function input parameters may be read via ld. it is illegal to write to an input parameter or read from a return parameter.s32 %y. the address of a function input parameter may be moved into a register using the mov instruction.param. dbl. x.s32 x. … } // code snippet from the caller // struct { double d. ld. (4. In PTX.local state space and is accessed via ld.reg . 2010 31 .

tex . 32 January 24. where all threads read from the same address. The .tex variables are required to be defined in the global scope.u32 tex_a.tex state space are equivalent to module-scoped .u64. Multiple names may be bound to the same physical texture identifier.6 for its use in texture instructions.1. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex . tex_c.tex directive will bind the named texture memory variable to a hardware texture identifier. An address in shared memory can be read and written by any thread in a CTA.PTX ISA Version 2.tex) state space is global memory accessed via the texture instruction.shared and st. and programs should instead reference texture memory through variables of type .3 for the description of the . a legacy PTX definitions such as .texref type and Section 8.texref. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.tex directive is retained for backward compatibility. 5. 2010 .0 5. A texture’s base address is assumed to be aligned to a 16-byte boundary. Another is sequential access from sequential threads. and . An error is generated if the maximum number of physical resources is exceeded. tex_d.tex . Example: . is equivalent to . One example is broadcast. It is shared by all threads in a context.8. Shared State Space The shared (.texref tex_a.u32 tex_a. Physical texture resources are allocated on a per-module granularity. Texture State Space (deprecated) The texture (. where texture identifiers are allocated sequentially beginning with zero.global state space.u32 .7. See Section 5.texref variables in the .u32 .tex . tex_d. Use ld. For example.shared) state space is a per-CTA region of memory for threads in a CTA to share data. Texture memory is read-only. Shared memory typically has some optimizations to support the sharing.u32 or .global .shared to access shared variables.7. The .1.tex . The texture name must be of type . and variables declared in the . tex_f.u32 .

5. Register variables are always of a fundamental type. .f64 types. and Variables 5. The following table lists the fundamental type specifiers for each basic type: Table 8.s64 .2. January 24. and instructions operate on these types. but typed variables enhance program readability and allow for better operand type checking. and converted using regular-width registers. so their names are intentionally short.f32 and . . . and . .u32. Two fundamental types are compatible if they have the same basic type and are the same size. and cvt instructions. the fundamental types reflect the native data types supported by the target architectures. Operand types and sizes are checked against instruction types for compatibility. 2010 33 . The bitsize type is compatible with any fundamental type having the same size.f16.f32.f64 types. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.1.s8. all variables (aside from predicates) could be declared using only bit-size types. Fundamental Types In PTX. . . . stored. . and cvt instructions permit source and destination data operands to be wider than the instruction-type size.pred Most instructions have one or more type specifiers. Types.Chapter 5.s32.2. . ld.b8 instruction types are restricted to ld. so that narrow values may be loaded. or converted to other types and sizes. needed to fully specify instruction behavior.u8.s8. For example.b32.2. Types 5. The .u16.b64 .2. . Signed and unsigned integer types are compatible if they have the same size.f32 and . In principle.u8. . stored.s16.f64 . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . Restricted Use of Sub-Word Sizes The . All floating-point instructions operate only on . st. The same typesize specifiers are used for both variable definitions and for typing instructions. For convenience.f16 floating-point type is allowed only in conversions to and from . A fundamental type specifies both a basic type and a size.u64 . st. State Spaces.b8.b16. .

suq). suld. In the independent mode. store. and Surface Types PTX includes built-in “opaque” types for defining texture. Retrieving the value of a named member via query instructions (txq. samplers. opaque_var. field ordering. but the pointer cannot otherwise be treated as an address. Sampler. . and . or performing pointer arithmetic will result in undefined results. the resulting pointer may be stored to and loaded from memory. Creating pointers to opaque variables using mov.3. since these properties are defined by . sampler. The three built-in types are . and surface descriptor variables. Texture. but all information about layout. The following tables list the named members of each type for unified and independent texture modes. and overall size is hidden to a PTX program.{u32.texref.surfref. texture and sampler information each have their own handle. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. or surfaces via texture and surface load/store instructions (tex. 34 January 24.e. These types have named fields similar to structures. 2010 . accessing the pointer with ld and st instructions.texref handle.u64} reg. sust. In the unified mode. allowing them to be defined separately and combined at the site of usage in the program.0 5. hence the term “opaque”. sured).texref type that describe sampler properties are ignored. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. and de-referenced by texture and surface load. and query instructions. In independent mode the fields of the .samplerref. Referencing textures.PTX ISA Version 2.samplerref variables.. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. i. texture and sampler information is accessed through a single . PTX has two modes of operation. For working with textures and samplers. passed as a parameter to functions. base address.

clamp_to_edge. linear wrap.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. 2010 35 . mirror. Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9.samplerref values N/A N/A N/A N/A nearest. clamp_to_edge. clamp_ogl. 1 nearest. clamp_ogl. clamp_to_border N/A N/A N/A N/A N/A . linear wrap.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. mirror.texref values in elements in elements in elements 0. Member width height depth Opaque Type Fields in Unified Texture Mode .Chapter 5. clamp_to_border 0. Types.texref values . 1 ignored ignored ignored ignored . State Spaces.

samplerref tsamp1 = { addr_mode_0 = clamp_to_border. As kernel parameters.texref my_texture_name.global state space.surfref my_surface_name. these variables are declared in the . At module scope. filter_mode = nearest }.global . the types may be initialized using a list of static expressions assigning values to the named members.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. Example: . . these variables must be in the .PTX ISA Version 2. Example: .samplerref my_sampler_name. .global . 36 January 24. When declared at module scope.global . .global .texref tex1.global . 2010 .param state space.

0}.reg . a variable declaration describes both the variable’s type and its state space. State Spaces. where the fourth element provides padding. 2010 37 .v4.v2. A variable declaration names the space in which the variable resides. Variable Declarations All storage for data is specified with variable declarations. . Three-element vectors may be handled by using a . Examples: . January 24. 5. Types. 0.0}. Vectors cannot exceed 128-bits in length. 1. its type and size.f32 accel. an optional initializer. Every variable must reside in one of the state spaces enumerated in the previous section. for example. vector variables are aligned to a multiple of their overall size (vector length times base-type size). .v1.4.v4 .const .4. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v4 . Vectors Limited-length vector types are supported.u16 uv.v4 . 0.global . . . // a length-4 vector of bytes By default. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . and an optional fixed address for the variable. In addition to fundamental types.s32 i. its name. Variables In PTX.global .b8 v.v3 }.f32 bias[] = {-1.struct float4 { . Predicate variables may only be declared in the register state space. Examples: .2. This is a common case for three-dimensional grids. .Chapter 5.global . an optional array size.pred p. // typedef .v4 vector.f32 V. // a length-2 vector of unsigned ints .4.v2 .global . q.reg .struct float4 coord.global .v4.f32 v0. 5.f64 is not allowed. textures. . r. Vectors must be based on a fundamental type. and Variables 5. etc.v2 or .u32 loc. and they may reside in the register space.u8 bg[4] = {0.shared . // a length-4 vector of floats . .reg .1.0. PTX supports types for simple aggregate objects such as vectors and arrays.

or is left empty.f32 blur_kernel[][] = {{.4. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.05}. being determined by an array initializer.global .0}.b32 ptr = rgba. 19*19 (361) halfwords are reserved (722 bytes).4. ..global .0}.4.0.{... 0}. Array Declarations Array declarations are provided to allow the programmer to reserve space. Variables that hold addresses of variables or instructions should be of type . The size of the array specifies how many elements should be reserved.0.u8 rgba[3] = {{1.u64. label names appearing in initializers represent the address of the next instruction following the label.05}}.1.0 5.s32 n = 10.1. {0.u32 or .f16 and . 2010 .1. The size of the dimension is either a constant expression.pred. 5.u16 kernel[19][19]. ..1}. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. variable initialization is supported only for constant and global state spaces.global . {0. Initializers are allowed for all types except . For the kernel declaration above.{. .PTX ISA Version 2.0. // address of rgba into ptr Currently. this can be used to initialize a jump table to be used with indirect branches or calls.u8 mailbox[128].global .3. -1}. {0. A scalar takes a single value.shared . .. where the variable name is followed by an equals sign and the initial value or values for the variable.05.05. Similarly. .v4 .0.1. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). 38 January 24. this can be used to statically initialize a pointer to a variable. 0}. To declare an array.0}}.local . Variable names appearing in initializers represent the address of the variable. {0. Here are some examples: . {1.1. Examples: .s32 offset[][] = { {-1.4. 1} }.global ..

Types.align 4 . %r99. The default alignment for vector variables is to a multiple of the overall vector size. Array variables cannot be declared this way.const . and may be preceded by an alignment specifier. January 24. 2010 39 . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.4. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.b32 variables. suppose a program uses a large number.6.4. .0. not for individual elements..Chapter 5.. named %r0. it is quite common for a compiler frontend to generate a large number of register names. // declare %r0. of .0. Examples: // allocate array at 4-byte aligned address. and Variables 5. The variable will be aligned to an address which is an integer multiple of byte-count.0. say one hundred.5. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. alignment specifies the address alignment for the starting address of the entire array.2. Parameterized Variable Names Since PTX supports virtual registers.0. For arrays. %r1.align byte-count specifier immediately following the state-space specifier. Rather than require explicit declaration of every name. 5. %r1. These 100 register variables can be declared as follows: .b8 bar[8] = {0.0. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. nor are initializers permitted..reg .0}.b32 %r<100>. State Spaces. Alignment is specified using an optional . Elements are bytes. For example. …. The default alignment for scalar and array variables is to a multiple of the base-type size. .

PTX ISA Version 2.0 40 January 24. 2010 .

mov. and a few instructions have additional predicate source operands. 6. Integer types of a common size are compatible with each other. st. q. The result operand is a scalar or vector variable in the register state space.2. There is no automatic conversion between types. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Predicate operands are denoted by the names p.reg register state space. Instructions ld and st move data from/to addressable state spaces to/from registers.3. s.1. 6. PTX describes a load-store machine. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. and c. The cvt (convert) instruction takes a variety of operand types and sizes. Most instructions have an optional predicate guard that controls conditional execution. . Source Operands The source operands are denoted in the instruction descriptions by the names a. and cvt instructions copy data from one location to another. r. Instruction Operands 6. The bit-size type is compatible with every type having the same size. the sizes of the operands must be consistent. January 24. as its job is to convert from nearly any data type to any other data type (and size). The ld.Chapter 6. Each operand type must be compatible with the type determined by the instruction template and instruction type. 2010 41 . b. so operands for ALU instructions must all be in variables declared in the . Operand Type Information All operands in instructions have a known type from their declarations. For most operations. The mov instruction copies data between registers.

reg . arrays. The address is an offset in the state space in which the variable is declared. Here are a few examples: . address register plus byte offset.global . q.reg .4. [V]. Examples include pointer arithmetic and pointer comparisons. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. [tbl+12]. and vectors.v4 .v4.s32 mov. Address expressions include variable names.1.reg . tbl.shared.u32 42 January 24. The mov instruction can be used to move the address of a variable into a pointer. address registers.const. All addresses and address computations are byte-based.const .u16 r0.f32 W.reg .shared . Load and store operations move data between registers and locations in addressable state spaces. . . ld. .u16 x. W. r0. .b32 p.4.f32 ld.[x].s32 q. and Vectors Using scalar variables as operands is straightforward. . 2010 .PTX ISA Version 2.v4 .u16 ld. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.gloal.f32 V. The interesting capabilities begin with addresses. . Using Addresses. Arrays.s32 tbl[256].0 6. there is no support for C-style pointer arithmetic. The syntax is similar to that used in many assembly languages. 6. and immediate address expressions which evaluate at compile-time to a constant address. p.

ld. . // move address of a[1] into s 6. c.g V.u32 s.z V.4.y.4.y V. or a simple “register with constant offset” expression. Arrays as Operands Arrays of all types can be declared. . b. . 2010 43 . Rd}.v4. or a braceenclosed list of similarly typed scalars.w.global. .reg . it must be written as an address calculation prior to use. Vector elements can be extracted from the vector with the suffixes .2.z and .u32 s. where the offset is a constant expression that is either added or subtracted from a register variable.global.g. . a register variable.global.f32 V.d}.Chapter 6.v4.4. say {Ra. Rb.x V.b. Array elements can be accessed using an explicitly calculated byte address.f32 a. Vectors as Operands Vector operands are supported by a limited subset of instructions. January 24.u32 {a. The size of the array is a constant in the program.b. Examples are ld. a[0].v2. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.b V. which may improve memory performance. [addr+offset2].w = = = = V.f32 {a.v4 . The expression within square brackets is either a constant integer. a[N-1]. mov. mov.4. Here are examples: ld. V2.a. Vectors may also be passed as arguments to called functions. ld.reg . and in move instructions to get the address of the label or function into a register.global.b and .a 6.c. Instruction Operands 6. and the identifier becomes an address constant in the space where the array is declared. for use in an indirect branch or call.c. which include mov.r. The registers in the load/store operations can be a vector. Elements in a brace-enclosed vector.3. Rc. or by indexing into the array using square-bracket notation. If more complicated indexing is desired. d.f32 ld. V.x. a[1]. as well as the typical color fields . and tex. [addr+offset]. Vector loads and stores can be used to implement wide loads and stores.r V. st.d}. . A brace-enclosed list is used for pattern matching to pull apart vectors. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.u32 s.

Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. 6.5.000 for f16).u16 instruction is given a u16 source operand and s32 as a destination operand. Operands of different sizes or types must be converted prior to the operation.PTX ISA Version 2. 2010 . the u16 is zero-extended to s32. 44 January 24.0 6. if a cvt.5. Type Conversion All operands to all arithmetic.s32. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. except for operations where changing the size and/or type is part of the definition of the instruction. logic. and ~131. and data movement instruction must be of the same type and size.1. For example.

s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. zext = zero-extend. f2u = float-to-unsigned. f2s = float-to-signed. cvt.Chapter 6. Notes 1 If the destination register is wider than the destination format. For example. Instruction Operands Table 11. 2010 45 . the result is extended to the destination register width after chopping. s2f = signed-to-float. then sign-extend to 32-bits. chop = keep only low bits that fit.u32 targeting a 32-bit register will first chop to 16-bits. u2f = unsigned-to-float. The type of extension (sign or zero) is based on the destination format. January 24.s16. f2f = float-to-float.

The following tables summarize the rounding modifiers.rm . 2010 .rn . In PTX. Modifier .2. Modifier . Table 12. there are four integer rounding modifiers and four floating-point rounding modifiers.rni .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. Rounding Modifiers Conversion instructions may specify a rounding modifier.rzi .rpi Integer Rounding Modifiers Description round to nearest integer.rz .PTX ISA Version 2. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.5.0 6. choosing even integer if source is equidistant between two integers.rmi .

The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Operand Costs Operands from different state spaces affect the speed of an operation. Table 11 gives estimates of the costs of using different kinds of memory. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.Chapter 6. Instruction Operands 6. The register in a store operation is available much more quickly. Registers are fastest.6. Table 14. Another way to hide latency is to issue the load instructions as early as possible. Much of the delay to memory can be hidden in a number of ways. 2010 47 . while global memory is slowest. first access is high Notes January 24.

PTX ISA Version 2. 2010 .0 48 January 24.

support for variadic functions (“varargs”). or prototype. arguments may be register variables or constants.func directive. January 24. Execution of the ret instruction within foo transfers control to the instruction following the call. and memory allocated on the stack (“alloca”). NOTE: The current version of PTX does not implement the underlying. stack layout. … Here. so recursion is not yet supported. parameter passing. In this section. } … call foo.func foo { … ret. 7. and Application Binary Interface (ABI). Abstracting the ABI Rather than expose details of a particular calling convention. and is represented in PTX as follows: . stack-based ABI. Function declarations and definitions In PTX. and an optional list of input parameters. and return values may be placed directly into register variables. together these specify the function’s interface. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Scalar and vector base-type input and return parameters may be represented simply as register variables. function calls.1. The simplest function has no parameters or return values. 2010 49 . execution of the call instruction transfers control to foo. implicitly saving the return address. A function declaration specifies an optional list of return parameters. we describe the features of PTX needed to achieve this hiding of the ABI. These include syntax for function definitions. A function definition specifies both the interface and the body of the function. At the call.Chapter 7. the function name. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. functions are declared and defined using the . A function must be declared or defined prior to being called.

b8 [py+11].b8 . ret. [y+11]. (%r1.align 8 y[12]) { . st.param space memory.param.f64 field are aligned.func (.4).reg . inc_ptr. [y+8]. %inc. … st. … … // computation using x. consider the following C structure. In PTX.param .b64 [py+ 0].param. (%x.s32 x.c4.param. %rc2. … In this example. .u32 %res.b8 c1. .b8 c2. c4.param.u32 %res) inc_ptr ( .b8 [py+ 8]. st. bumpptr.reg . . note that . ld.param .b8 [py+ 9]. }.reg space. 2010 .f64 f1.b32 c1.b8 [py+10]. ld.param space call (%out). st.reg . ld.reg . py).b8 c3. [y+0]. For example.u32 %inc ) { add.0 Example: . a . %ptr.align 8 py[12]. c3.f1. [y+10].c3. a .param. st.PTX ISA Version 2.param space variables are used in two ways.c1.param. Second.reg . byte array in . 50 January 24.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.param state space is used to pass the structure by value: .param. char c[4]. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .b8 . %rc2. c2. ld. First. } … call (%r1). %rc1. } { .func (.param.reg . Since memory accesses are required to be aligned to a multiple of the access size.f64 f1. this structure will be flattened into a byte array.param variable y is used in function definition bar to represent a formal parameter. … ld.u32 %ptr.s32 out) bar (.reg . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param. [y+9].b8 c4. %rd.c2. The . // scalar args in .param. passed by value to a function: struct { double dbl. %rc1.

For .param or .Chapter 7. • The .param state space use in device functions. • • • For a callee. size.. • • Arguments may be . the argument must also be a . .param variables.reg space formal parameters. Parameters in . In the case of .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. and alignment. 4. Supporting the . the corresponding argument may be either a .reg state space in this way provides legacy support.param instructions used for argument passing must be contained in the basic block with the call instruction.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.g. size.param or .reg variables.param memory must be aligned to a multiple of 1. or a constant that can be represented in the type of the formal parameter.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.param arguments.reg variables. This enables backend optimization and ensures that the .reg space variable with matching type and size. or 16 bytes.reg or . or constants. The .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. Abstracting the ABI The following is a conceptual way to think about the . Typically. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param variables or . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. all st.param byte array is used to collect together fields of a structure being passed by value. or a constant that can be represented in the type of the formal parameter.param state space is used to receive parameter values and/or pass return values back to the caller.param space byte array with matching type. A . For a callee.reg space variable of matching type and size. In the case of . In the case of . 2010 51 .reg state space can be used to receive and return base-type scalar and vector values. and alignment of parameters. 2. the corresponding argument may be either a . • • • Input and return parameters may be .param space formal parameters that are byte arrays.param argument must be declared within the local scope of the caller. For a caller.param and ld. Note that the choice of .param space formal parameters that are base-type scalar or vector variables. January 24. For a caller. The following restrictions apply to parameter passing. • The . a . 8. The .

PTX 2. PTX 2. and a . In PTX ISA version 2.0 7.param byte array should be used to return objects that do not fit into a register. Objects such as C structures were flattened and passed or returned using multiple registers. PTX 1. and there was no support for array parameters. 2010 .0 restricts functions to a single return value. For sm_2x targets.PTX ISA Version 2. formal parameters were restricted to .1.reg or . Changes from PTX 1.0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays.param state space.0.1. 52 January 24.x In PTX ISA version 1.x supports multiple return values for this purpose. and . formal parameters may be in either .x.reg state space.

or 8 bytes. This handle is then passed to the %va_arg and %va_arg64 built-in functions. %va_arg.reg .b64 val) %va_arg64 (.reg . 2. PTX provides a high-level mechanism similar to the one provided by the stdarg. .reg . // default to MININT mov.reg . . %r1. .func baz ( . the alignment may be 1.func okay ( … ) Built-in functions are provided to initialize.u32 sz.func ( . N. call %va_end. %s2). mov.reg . .ge p.u32 align) . %va_start.b32 val) %va_arg (. Abstracting the ABI 7.reg . iteratively access. 8. 2.u32 align) . %r2.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 a. 4.pred p.func (. The function prototypes are defined as follows: .reg . 4. the size may be 1. max. (3.. … call (%max). ctr.s32 val.Chapter 7.u32 ap. . (2.reg .u32 ptr. setp.reg .reg . val. and end access to a list of variable arguments.reg .u32 ptr) %va_start .b32 result. following zero or more fixed parameters: . To support functions with a variable number of arguments.h and varargs. result.reg . variadic functions are declared with an ellipsis at the end of the input parameter list.reg . In PTX. . ctr. along with the size and alignment of the next data value to be accessed. ret. or 4 bytes. For %va_arg. 4). maxN. the size may be 1.2.u32. 2. … %va_start returns Loop: @p Done: January 24. call (val).u32 sz. call (ap)..func (.h headers in C. In both cases. } … call (%max). … ) .func (.reg . bra Loop.u32 ptr.b32 ctr. Variadic functions NOTE: The current version of PTX does not support variadic functions. . ) { .reg . %va_end is called to free the variable argument list handle. %s1. maxN. .s32 result.s32 result ) maxN ( . (ap). (ap.func %va_end (. bra Done.u32 N. for %va_arg64. 0.u32 b. 0x8000000.reg . %r3). 2010 53 . or 16 bytes. Once all arguments have been processed. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . 4.reg .

u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.0 7. a function simply calls the built-in function %alloca. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. The array is then accessed with ld. To allocate memory.3. If a particular alignment is required.PTX ISA Version 2. 54 January 24. defined as follows: .u32 ptr ) %alloca ( .local instructions.reg . Alloca NOTE: The current version of PTX does not support alloca.func ( . 2010 .local and st.reg .

A. For instructions that create a result value.1. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. Instruction Set 8. A. b. followed by some examples that attempt to show several possible instantiations of the instruction. 2010 55 .s32. q = !(a < b). plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. 8. // p = (a < b). opcode D. In addition to the name and the format of the instruction. We use a ‘|’ symbol to separate multiple destination registers. B. A.Chapter 8. while A. the semantics are described. The setp instruction writes two destination registers. setp. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. B. For some instructions the destination operand is optional. January 24. opcode A. and C are the source operands. a.lt p|q. opcode D. the D operand is the destination operand. PTX Instructions PTX instructions generally have from zero to four operands. opcode D.2. C. B.

The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. predicate registers are virtual and have . the following PTX instruction sequence might be used: @!p L1: setp.pred as the type specifier. bra L1. predicate registers can be declared as . Predicated Execution In PTX. 1. As an example.lt. Instructions without a guard predicate are executed unconditionally. i. n. use a predicate to control the execution of the branch or call instructions. So. q.s32 p. 2010 .0 8. j. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. // p = (i < n) // if i < n. branch over 56 January 24. consider the high-level code if (i < n) j = j + 1. optionally negated.reg .PTX ISA Version 2.lt. add. 1. where p is a predicate variable. add. add 1 to j To get a conditional branch or conditional function call. n. i.s32 j. To implement the above example as a true conditional branch. j. Predicates are most commonly set as the result of a comparison performed by the setp instruction. This can be written in PTX as @p setp.s32 j.pred p.3. … // compare i to n // if false.s32 p.

ne (not-equal).3. ge. le (less-than-or-equal). lt. lt (less-than). Instruction Set 8. ne. Comparisons 8.1. lo (lower). The following table shows the operators for signed integer.2. le.1.3. The bit-size comparisons are eq and ne. Unsigned Integer. If either operand is NaN. and ge (greater-than-or-equal). ordering comparisons are not defined for bit-size types. the result is false. ls (lower-or-same). and hs (higher-or-same). hi (higher). Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. ne. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. gt.3. Table 16. and bitsize types.1. 2010 57 .1. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. unsigned integer. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. gt (greater-than).Chapter 8. Table 15. The unsigned comparisons are eq.

Table 17.%p. or. and mov. and no direct way to load or store predicate register values. geu.0 To aid comparison operations in the presence of NaN values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. If either operand is NaN. ltu. If both operands are numeric values (not NaN). However. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. There is no direct conversion between predicates and integer values. not. 2010 . Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. gtu.1. for example: selp.3. then the result of these comparisons is true.PTX ISA Version 2. num returns true if both operands are numeric values (not NaN). then these comparisons have the same result as their ordered counterparts. leu. neu. // convert predicate to 32-bit value 58 January 24. two operators num (numeric) and nan (isNaN) are provided. Table 18.u32 %r1. xor. unordered versions are included: equ. and nan returns true if either operand is NaN.0. setp can be used to generate a predicate from an integer.2.

Table 19.fX ok ok ok ok January 24. Floating-point types agree only if they have the same size.sX . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.fX ok inv inv ok Instruction Type . For example. unsigned.f32. and integer operands are silently cast to the instruction type if needed. cvt.reg . and these are placed in the same order as the operands. and this information must be specified as a suffix to the opcode.bX . a. • The following table summarizes these type checking rules.reg . float.sX ok ok ok inv . different sizes). For example: . Signed and unsigned integer types agree provided they have the same size. It requires separate type-size modifiers for the result and source. . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.reg .Chapter 8. 2010 59 .u16 d. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. For example.u16 d.e.bX .u16 d. they must match exactly. a. a. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.. the add instruction requires type and size information to properly perform the addition operation (signed.u16 a. b.uX ok ok ok inv .uX . Type Checking Rules Operand Type .f32 d. most notably the data conversion instruction cvt. Example: . b. i.4. Instruction Set 8. add.

The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. When used with a floating-point instruction type. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. 1.0 8. Note that some combinations may still be invalid for a particular instruction. For example. stored. ld. “-“ = allowed. for example. the data will be truncated. 2010 . Notes 3. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 4. Floating-point source registers can only be used with bit-size or floating-point instruction types. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Table 20.bX instruction types. st. The data is truncated to the instruction-type size and interpreted according to the instruction type. parse error. the cvt instruction does not support . inv = invalid.1. Operand Size Exceeding Instruction-Type Size For convenience. no conversion needed. The following table summarizes the relaxed type-checking rules for source operands. When a source operand has a size that exceeds the instruction-type size. 60 January 24. so that narrow values may be loaded. Source register size must be of equal or greater size than the instruction-type size. floating-point instruction types still require that the operand type-size matches exactly. stored. unless the operand is of bit-size type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. the size must match exactly.PTX ISA Version 2. When used with a narrower bit-size type. or converted to other types and sizes. Bit-size source registers may be used with any appropriately-sized instruction type. so those rows are invalid for cvt.4. and converted using regular-width registers. 2.

Bit-size destination registers may be used with any appropriately-sized instruction type. When used with a narrower bit-size instruction type. When used with a floatingpoint instruction type. the data is sign-extended. Destination register size must be of equal or greater size than the instruction-type size. 2010 61 . Notes 3. If the corresponding instruction type is signed integer. “-“ = Allowed but no conversion needed. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. The data is signextended to the destination register width for signed integer instruction types. 2. January 24. the size must match exactly. 4. and is zero-extended to the destination register width otherwise. the destination data is zero. Instruction Set When a destination operand has a size that exceeds the instruction-type size.or sign-extended to the size of the destination register. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. the data will be zero-extended. inv = Invalid. the data is zeroextended. Table 21.Chapter 8. otherwise. Floating-point destination registers can only be used with bit-size or floating-point instruction types. 1. The following table summarizes the relaxed type-checking rules for destination operands. zext = zero-extend. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. The data is sign-extended to the destination register width for signed integer instruction types. parse error.

a compiler or code author targeting PTX can ignore the issue of divergent threads. and for many applications the difference in execution is preferable to limiting performance.6. Therefore. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. using the . Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. so it is important to have divergent threads re-converge as soon as possible. until they come to a conditional control construct such as a conditional branch. These extra precision bits can become visible at the application level.5. For divergent control flow. the optimizing code generator automatically determines points of re-convergence. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. or conditional return. If threads execute down different control flow paths. the semantics of 16-bit instructions in PTX is machine-specific. At the PTX language level.uni suffix. The semantics are described using C. at least in appearance. 62 January 24. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Both situations occur often in programs. 16-bit registers in PTX are mapped to 32-bit physical registers. If all of the threads act in unison and follow a single control flow path. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. Divergence of Threads in Control Constructs Threads in a CTA execute together.0 8. the threads are called divergent. the threads are called uniform.PTX ISA Version 2. until C is not expressive enough. conditional function call. and 16-bit computations are “promoted” to 32-bit computations. for example.6. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. by a right-shift instruction. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. When executing on a 32-bit data path. 8. for many performance-critical applications. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 8. A compiler or programmer may chose to enforce portable.1. 2010 . However. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. this is not desirable.

cc. Instructions All PTX instructions may be predicated.Chapter 8. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 2010 63 .7. addc sub. In the following descriptions.1. Instruction Set 8.cc. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. The Integer arithmetic instructions are: add sub add. the optional guard predicate is omitted from the syntax.7. 8.

z.1. Applies only to .u32.type add{. .a. . 2010 . Supported on all target architectures.s16. add. a.MAXINT (no overflow) for the size of the operation. // .u64.c.b. . d.s32 c.sat applies only to .0. b. // . d = a + b. .s64 }.u16.s32 . .0 Table 22. Saturation modifier: . Introduced in PTX ISA version 1.s32 type.s32 d. a.MAXINT (no overflow) for the size of the operation.s32 c.y. d.s32.sat. .u16. d = a – b.sat applies only to . Saturation modifier: .sat}.s16.0.s32 d. .sat limits result to MININT. sub.type sub{. add Syntax Integer Arithmetic Instructions: add Add two values. . b. a. Description Semantics Notes Performs addition and writes the resulting value into a destination register. Introduced in PTX ISA version 1.type = { . PTX ISA Notes Target ISA Notes Examples 64 January 24. Supported on all target architectures. . PTX ISA Notes Target ISA Notes Examples Table 23. b. sub. add.u32 x. a. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.. @p add.s32 type.s32 .s32..s64 }.u64.sat limits result to MININT. .PTX ISA Version 2. b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Applies only to .u32.sat}.type = { .

. x4. or testing the condition code. These instructions support extended-precision integer addition and subtraction. carry-out written to CC. b.cc.z3.cc.cc.b32 addc. x4.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.z3. Introduced in PTX ISA version 1.z2.CF.Chapter 8. x3.s32 }. No saturation.b32 addc. sub.type d. Instruction Set Instructions add.cc.y1. 2010 65 .b32 x1. No saturation.y4.2. addc{. d = a + b + CC. a. Supported on all target architectures. d = a + b.s32 }. Behavior is the same for unsigned and signed integers.type = { .cc Syntax Integer Arithmetic Instructions: add.cc.type d.cc Add two values with carry-out. b. @p @p @p @p add.y4. . if .u32. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. Introduced in PTX ISA version 1.type = {.b32 addc.y3.CF No integer rounding modifiers.b32 addc.cc specified. . Supported on all target architectures. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc}. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. addc.z4. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.cc.cc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. and there is no support for setting. No other instructions access the condition code. add.y1. x3.cc. @p @p @p @p add.cc.y2.b32 addc.b32 x1.z2.CF No integer rounding modifiers. Table 24.b32 addc.u32.z1.y2.z1. Behavior is the same for unsigned and signed integers. carry-out written to CC.2. add.z4. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. clearing.y3.cc. x2.CF) holding carry-in/carry-out or borrowin/borrow-out. x2. a. .

u32.cc}.b32 subc. subc{. withborrow-in and optional borrow-out. Introduced in PTX ISA version 1. @p @p @p @p sub.(b + CC.z3.b32 subc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc Syntax Integer Arithmetic Instructions: sub. d = a .z4.type d.y1. borrow-out written to CC. if . No saturation. sub.z2.z4.b32 subc. x3.CF No integer rounding modifiers. 2010 .u32.CF).y2.b32 x1.cc.cc. . . with borrow-out.cc.type d.cc Subract one value from another.b32 subc. No saturation.cc. d = a – b.b32 subc. .z3.cc.z1. Behavior is the same for unsigned and signed integers.y3. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. b.type = {.cc. x4. b.cc specified.b32 x1.s32 }. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.cc.y2.cc.y3.z1. x2. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y4. Supported on all target architectures.3. x3. sub.y4.0 Table 26. x2.cc. a. borrow-out written to CC. Supported on all target architectures. . @p @p @p @p sub.b32 subc.z2.PTX ISA Version 2.CF No integer rounding modifiers. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.type = { . Behavior is the same for unsigned and signed integers. a.3. x4.s32 }. Introduced in PTX ISA version 1.y1.

x.s32 z. then d is the same size as a and b. Supported on all target architectures.lo is specified. .wide. mul{. then d is twice as wide as a and b to receive the full result of the multiplication. .fxs. .n>. d = t.type = { .s16 fa. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.wide}.lo. If .u16. If .type d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // for . d = t<2n-1.0. . t = a * b. mul.. Instruction Set Table 28. and either the upper or lower half of the result is written to the destination register. // 16*16 bits yields 32 bits // 16*16 bits. save only the low 16 bits // 32*32 bits.s32. Description Semantics Compute the product of two values.s64 }..wide.fys. . ..hi variant // for . d = t<n-1.s16 fa.fys.wide suffix is supported only for 16.lo variant Notes The type of the operation represents the types of the a and b operands.u64. mul.lo.hi or .wide // for ..hi.wide is specified. n = bitwidth of type.u32. mul. b. The . a.s16.fxs.0>. 2010 67 .Chapter 8. creates 64 bit result January 24.and 32-bit integer types.y.

t<n-1. t + c. .s32 r. c.0 Table 29. and either the upper or lower half of the result is written to the destination register. and then writes the resulting value into a destination register. 2010 .hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi or .and 32-bit integer types.lo.u32. a. mad{.hi mode.hi.lo variant Notes The type of the operation represents the types of the a and b operands.s32 d.type = { .. Applies only to .. Saturation modifier: .s32. .p. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. // for . then d and c are twice as wide as a and b to receive the result of the multiplication.type mad. mad. Description Semantics Multiplies two values and adds a third...sat limits result to MININT.wide is specified. d. Supported on all target architectures. a.wide}.. If . @p mad. bitwidth of type.lo.wide suffix is supported only for 16.0.s64 }. .MAXINT (no overflow) for the size of the operation.r.b.s32 type in .c.u16.s16. c.lo is specified. The . b.a.0> + c.q. . t<2n-1. b.sat. .s32 d. If .wide // for .hi variant // for . t n d d d = = = = = a * b.u64.PTX ISA Version 2. 68 January 24.n> + c.lo. . then d and c are the same size as a and b.

mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. 48bits.s32 d.s32 }.hi variant // for . i.lo}. January 24. 2010 69 . d = t<31. // for . All operands are of the same type and size..u32. d = t<47.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.16>.lo. mul24{..b. mul24.e.0. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24.0>. mul24.hi. // low 32-bits of 24x24-bit signed multiply. a. t = a * b.a. Instruction Set Table 30. .lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. and return either the high or low 32-bits of the 48-bit result. mul24. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.hi may be less efficient on machines without hardware support for 24-bit multiply.type = { .type d.. b. .Chapter 8.

.lo..lo}.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. All operands are of the same type and size.s32 d. c. mad24. a.0> + c. mad24. d = t<47. Saturation modifier: .s32 d.0 Table 31. mad24.u32. t = a * b.sat. d. 32-bit value to either the high or low 32-bits of the 48-bit result. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi.0. b. c.hi mode. 2010 . 70 January 24.type mad24. b.hi may be less efficient on machines without hardware support for 24-bit multiply. 48bits.c. // for . and add a third. Supported on all target architectures.PTX ISA Version 2. Description Compute the product of two 24-bit integer values held in 32-bit source registers. d = t<31..s32 }. Return either the high or low 32-bits of the 48-bit result.s32 type in .lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.type = { . mad24{. i.sat limits result of 32-bit signed addition to MININT.hi variant // for . a. .e.MAXINT (no overflow).b..a.. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. mad24. // low 32-bits of 24x24-bit signed multiply.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. Applies only to .16> + c.hi.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b64 type. popc. } Introduced in PTX ISA version 2. a. clz. // cnt is . } while (d < max && (a&mask == 0) ) { d++. X. .b32.type d. a = a >> 1.b64 d.0. a. . inclusively.0 Table 39.b64 d. clz requires sm_20 or later. a. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. d = 0.type = { . mask = 0x80000000.b64 }. For .type == .0.type = { .b32 type. X. popc Syntax Integer Arithmetic Instructions: popc Population count. popc. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.u32 PTX ISA Notes Target ISA Notes Examples Table 40. the number of leading zeros is between 0 and 64. .b32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. popc requires sm_20 or later.b64 }.PTX ISA Version 2.u32 Semantics 74 January 24. mask = 0x8000000000000000. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. cnt. d = 0. } else { max = 64. For . cnt.b32 clz. 2010 .type d. the number of leading zeros is between 0 and 32. // cnt is . inclusively.b32 popc. a. a = a << 1. clz. .b32) { max = 32. if (. while (a != 0) { if (a&0x1) d++.

break. . Semantics msb = (. a. X.u64. For signed integers.shiftamt. a. bfind returns 0xFFFFFFFF if no non-sign bit is found.0. a. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.shiftamt is specified. for (i=msb. If .s64 cnt. Operand a has the instruction type.type d.d. bfind returns the bit position of the most significant “1”. Instruction Set Table 41. bfind requires sm_20 or later. d = -1. i>=0.type==.Chapter 8.s64 }. Description Find the bit position of the most significant non-sign bit in a and place the result in d.s32) ? 31 : 63. .u32 January 24. } } if (.u32.u32 || . bfind.u32 d. bfind. 2010 75 . . For unsigned integers. and operand d has type . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.type==.s32. // cnt is . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type bfind. .shiftamt. d. bfind. i--) { if (a & (1<<i)) { d = i.shiftamt && d != -1) { d = msb . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.type = { .

msb = (. 2010 . brev. i++) { d[i] = a[msb-i]. a.type d.0. Description Semantics Perform bitwise reversal of input.PTX ISA Version 2.b32.0 Table 42.b32) ? 31 : 63. a. for (i=0.type==.b64 }.b32 d. brev requires sm_20 or later.type = { . . brev. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i<=msb. 76 January 24. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. .

u64 || len==0) sbit = 0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.a. .u32.u32 || .u32. . d = 0. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.msb)]. i<=msb. Description Extract bit field from a and place the zero or sign-extended result in d.len. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. The destination d is padded with the sign bit of the extracted field.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.s32) ? 31 : 63.type = { . January 24.0. bfe.s64 }.u64. b.u64: . else sbit = a[min(pos+len-1.type==.b32 d. c.type==. . and source c gives the bit field length in bits. The sign bit of the extracted field is defined as: . . . Source b gives the bit field starting bit position.u32 || . a.s32.Chapter 8. and operands b and c are type . if (.s32. Semantics msb = (.start. Instruction Set Table 43. for (i=0. If the start position is beyond the msb of the input. bfe. Operands a and d have the same type as the instruction type.type==.u32. pos = b.type==.type d. len = c. the destination d is filled with the replicated sign bit of the extracted field. . 2010 77 . the result is zero. otherwise If the bit field length is zero. bfe requires sm_20 or later.

len.type = { . the result is b. and operands c and d are type . i++) { f[pos+i] = a[i]. d. If the bit field length is zero. bfi requires sm_20 or later.b64 }. for (i=0. b. i<len && pos+i<=msb. and source d gives the bit field length in bits. 78 January 24. Source c gives the starting bit position for the insertion. pos = c. bfi.b32 d.0.u32. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.type f. c. and f have the same type as the instruction type. 2010 .a. a.PTX ISA Version 2.b. len = d. Description Align and insert a bit field from a into b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 44. . If the start position is beyond the msb of the input.b32. the result is b. . and place the result in f. Operands a.type==. bfi.b32) ? 31 : 63. f = b.start. b. Semantics msb = (.

In the generic form (no mode specified).rc8. The msb defines if the byte value should be copied. b. a} = {{b7. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). . the permute control consists of four 4-bit selection values. b2. The bytes in the two source registers are numbered from 0 to 7: {b. b5. and reassemble them into a 32-bit destination register.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. Description Pick four arbitrary bytes from two 32-bit registers.ecl. b1. b4}. b6.b32{. . b0}}.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. Thus. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.Chapter 8. .rc16 }. default mode index d.ecr.b1 source select c[7:4] d.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. msb=1 means replicate the sign. .b4e.mode = { .b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.f4e. the four 4-bit values fully specify an arbitrary byte permute. Note that the sign extension is only performed as part of generic form.b2 source select c[11:8] d. msb=0 means copy the literal value. c. {b3. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. . 2010 79 . prmt.b3 source select c[15:12] d. as a 16b permute code. a.mode} d. Instruction Set Table 45. For each byte in the target register. a 4-bit selection value is defined. . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.

r4. tmp64 ). tmp[31:24] = ReadByte( mode.0 Semantics tmp64 = (b<<32) | a. tmp64 ). ctl[2]. tmp[23:16] = ReadByte( mode. tmp64 ). 80 January 24.f4e r1. r2.PTX ISA Version 2. prmt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp64 ). 2010 . ctl[1]. ctl[0].b32. ctl[3]. tmp[15:08] = ReadByte( mode. r1. ctl[1] = (c >> 4) & 0xf. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r3.0. r4.b32 prmt. prmt requires sm_20 or later. ctl[2] = (c >> 8) & 0xf. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r3. ctl[3] = (c >> 12) & 0xf. r2. } tmp[07:00] = ReadByte( mode.

Floating-Point Instructions Floating-point instructions operate on .Chapter 8.2.7. Instruction Set 8. 2010 81 .f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values.

rnd.rnd.sat Notes If no rounding modifier is specified.approx.sqrt}. Single-precision add.mul}.f32 {div. and mad support saturation of results to the range [0.rp .rn and instructions may be folded into a multiply-add.ftz . Table 46.f64 rsqrt.0. Double-precision instructions support subnormal inputs and results.f64 and fma.ex2}. .rnd.rm . 82 January 24.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. No rounding modifier.rnd.f32 rsqrt.rcp.f64 are the same.sub.rn and instructions may be folded into a multiply-add.f32 {div.f32 {add.target sm_20 .f32 .full.approx.f32 are the same.f64 {abs.max}.f64 div. default is .f32 {abs.neg.approx.rnd.sqrt}.rcp.f64 mad.approx. If no rounding modifier is specified.lg2.f64 {sin.min.min.PTX ISA Version 2.neg.0 The following table summarizes floating-point instructions in PTX. default is . The optional . Instruction Summary of Floating-Point Instructions .0]. mul.f32 {mad.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.fma}.target sm_1x No rounding modifier.sub. Note that future implementations may support NaN payloads for single-precision instructions. .max}.mul}. {add. {mad.32 and fma.rnd. sub.cos.target sm_20 mad. but single-precision instructions return an unspecified NaN. with NaNs being flushed to positive zero.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.rz . 2010 .sqrt}. so PTX programs should not rely on the specific single-precision NaNs being generated. NaN payloads are supported for double-precision instructions.rn . 1.fma}.f32 {div. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.rcp.

positive and negative zero are considered normal numbers. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.type . .f64 x. a.type = { . X.op p.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. not infinity) As a special case. f0.0. A.op. and return the result as d.infinite. testp requires sm_20 or later. .f32 copysign.notanumber. B. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. testp. C.notanumber. copysign. .0.number testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type d.infinite. . a.finite testp. p. Introduced in PTX ISA version 2.infinite testp.notanumber testp. testp.pred = { . // result is .f32.normal testp.number. b.Chapter 8.f32 testp. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.normal. Instruction Set Table 47. .subnormal }. testp Syntax Floating-Point Instructions: testp Test floating-point property. not infinity). y.f64 }. testp. z. copysign requires sm_20 or later. Table 48. January 24.f64 isnan. 2010 83 . . .f64 }.finite. copysign.f32. . true if the input is a subnormal number (not NaN. .type = { .

1.ftz.sat}.rnd}.sat. sm_1x: add. requires sm_13 for add. Rounding modifiers have the following target requirements: . add.rz. . .f64 requires sm_13 or later. Rounding modifiers (default is .rm. . 84 January 24.rz available for all targets . An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rp for add.f32 supported on all target architectures.PTX ISA Version 2.0. add.rn mantissa LSB rounds to nearest even . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rz.f32 flushes subnormal inputs and results to sign-preserving zero. b. .rp }. Description Semantics Notes Performs addition and writes the resulting value into a destination register.0 Table 49. In particular.rnd = { .f32 clamps the result to [0. add.0f. add Syntax Floating-Point Instructions: add Add two values.0. d. d = a + b. add{. NaN results are flushed to +0. Saturation modifier: .rnd}{.f2. add. b. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.f32.f32 f1.f3. requires sm_20 Examples @p add.rz mantissa LSB rounds towards zero .rm mantissa LSB rounds towards negative infinity . a.rn. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64 supports subnormal numbers.ftz.rn. add.rn): . 2010 .f64.0]. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 add{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm.ftz}{. . subnormal numbers are supported. .

rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 85 .f64 supports subnormal numbers.rz available for all targets . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.f3. Saturation modifier: sub. a.f32 sub{.ftz.rm. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . sub.0].ftz. requires sm_13 for sub.f32.0.rn): .rm mantissa LSB rounds towards negative infinity .a. Rounding modifiers (default is . 1. sub.b. .ftz}{.0. .sat}. a.rz mantissa LSB rounds towards zero . sm_1x: sub. sub{. . sub.f32 clamps the result to [0. . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 requires sm_13 or later.Chapter 8. d.f64.rn.rnd}.f64 d. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rnd = { .rnd}{.b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0f. NaN results are flushed to +0.rp for sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another.rn mantissa LSB rounds to nearest even .f32 f1.rm.rn. Instruction Set Table 50. subnormal numbers are supported.f2.f32 flushes subnormal inputs and results to sign-preserving zero. Rounding modifiers have the following target requirements: . d = a .f32 c. January 24. sub. b. requires sm_20 Examples sub.sat. . In particular. b.rz.rp }.f32 supported on all target architectures. sub.

NaN results are flushed to +0.rnd}{.f32.ftz.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. .rn mantissa LSB rounds to nearest even .ftz. mul.rz mantissa LSB rounds towards zero . a. Description Semantics Notes Compute the product of two values. a.f64 requires sm_13 or later. d. mul{.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 51. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. In particular. . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. b.rm.sat.rn.rm mantissa LSB rounds towards negative infinity . .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp }.0f.PTX ISA Version 2. 1.sat}.f32 circumf. 2010 . .rm.rn.rz.rz available for all targets . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. subnormal numbers are supported. Rounding modifiers have the following target requirements: .f32 clamps the result to [0. b. Rounding modifiers (default is . d = a * b. requires sm_13 for mul. mul.rp for mul.f32 supported on all target architectures.f32 mul{.rnd}.f64 d. mul. mul. requires sm_20 Examples mul. For floating-point multiplication. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Saturation modifier: mul. all operands must be the same size. .rnd = { .0.ftz}{.rn): .f64. mul Syntax Floating-Point Instructions: mul Multiply two values.0. .radius. sm_1x: mul.pi // a single-precision multiply 86 January 24.0].

NaN results are flushed to +0.sat.a. Instruction Set Table 52. . fma.rz mantissa LSB rounds towards zero . @p fma.y.0].rnd.rnd. d = a*b + c.f64. fma Syntax Floating-Point Instructions: fma Fused multiply-add. PTX ISA Notes Target ISA Notes Examples January 24.0.rp }.rn mantissa LSB rounds to nearest even .rn. . fma.f64 is the same as mad.0.Chapter 8. 1. The resulting value is then rounded to double precision using the rounding mode specified by .rm mantissa LSB rounds towards negative infinity .ftz}{. sm_1x: fma.c. c.f64 introduced in PTX ISA version 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. fma.ftz. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. fma.f64 supports subnormal numbers.f64 w. fma. d.f32 flushes subnormal inputs and results to sign-preserving zero. c.rnd{. fma. a.rn.f32 fma. 2010 87 .f32 computes the product of a and b to infinite precision and then adds c to this product. Rounding modifiers (no default): . . b.x.0f. fma.rnd = { . a.f32 is unimplemented in sm_1x. again in infinite precision. b. Saturation: fma.sat}.rn. subnormal numbers are supported.f64 computes the product of a and b to infinite precision and then adds c to this product. . fma.rm. fma.rz. The resulting value is then rounded to single precision using the rounding mode specified by .ftz. again in infinite precision.f32 clamps the result to [0.rnd.b.f32 introduced in PTX ISA version 2.z.f64 d.4.f64 requires sm_13 or later.f32 fma.f32 requires sm_20 or later. fma. d.

again in infinite precision. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.rnd. The exception for mad. mad{. The resulting value is then rounded to double precision using the rounding mode specified by . // . c. The resulting value is then rounded to single precision using the rounding mode specified by . a. Unlike mad. Rounding modifiers (no default): .0].0.sat}.{f32.f32 is identical to the result computed using separate mul and add instructions.f64 computes the product of a and b to infinite precision and then adds c to this product. b. Note that this is different from computing the product with mul. a.sat}. mad.. fma.f32 mad. The resulting value is then rounded to double precision using the rounding mode specified by .rnd. NaN results are flushed to +0. // . c.f64. mad. but the exponent is preserved.ftz.rn. 88 January 24.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0f.ftz. mad.0 devices.ftz}{.f32 computes the product of a and b at double precision.0. subnormal numbers are supported.sat. .rm. again in infinite precision. and then writes the resulting value into a destination register.rnd{. When JIT-compiled for SM 2.f32 clamps the result to [0. mad.f32 computes the product of a and b to infinite precision and then adds c to this product. b.rm mantissa LSB rounds towards negative infinity .f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. Saturation modifier: mad. 1.f64} is the same as fma.target sm_1x d.rn mantissa LSB rounds to nearest even .f32). b.f32 flushes subnormal inputs and results to sign-preserving zero. mad.f32 mad. again in infinite precision. For .rz. For . .target sm_20: mad.rnd = { . // .target sm_1x: mad.f32 is implemented as a fused multiply-add (i. Description Semantics Notes Multiplies two values and adds a third. and then the mantissa is truncated to 23 bits. the treatment of subnormal inputs and output follows IEEE 754 standard.f32 is when c = +/-0.f64 is the same as fma.0 Table 53.target sm_20 d. 2010 .f64 computes the product of a and b to infinite precision and then adds c to this product.rnd. c. where the mantissa can be rounded and the exponent will be clamped.rp }. mad.{f32.rn. sm_1x: mad.PTX ISA Version 2. . a.ftz}{.f64 supports subnormal numbers. In this case. mad.f64}. d = a*b + c.f32.target sm_13 and later .f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.rnd. mad.e. mad.rz mantissa LSB rounds towards zero .

a rounding modifier is required for mad.4 and later.f64. Rounding modifiers have the following target requirements: .0 and later.rm. mad.b.rz.rn. requires sm_20 Examples @p mad. requires sm_13 .rp for mad.rp for mad. Target ISA Notes mad.f64 requires sm_13 or later..rn..Chapter 8.f64.f32 for sm_20 targets.. January 24.f32 supported on all target architectures. Legacy mad.f64 instructions having no rounding modifier will map to mad.f32 d.f64.a.rn...rm.c. In PTX ISA versions 2. 2010 89 .. In PTX ISA versions 1. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.0.f32. a rounding modifier is required for mad.rz.

full-range approximation that scales operands to achieve better accuracy.ftz}. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . a. Examples 90 January 24.ftz.f32 and div. and rounding introduced in PTX ISA version 1. x.full.f32 div. // // // // fast.f64. a. .rm. div.f32 div. b. d.f64 diam. Explicit modifiers .full.rnd is required. d = a / b. Subnormal inputs and results are flushed to sign-preserving zero. d. approximate single-precision divides: div.f32.f64 introduced in PTX ISA version 1. y.rm mantissa LSB rounds towards negative infinity . For PTX ISA versions 1.0 Table 54.f64 supports subnormal numbers. div. .ftz. and div.3. Fast.4. a. but is not fully IEEE 754 compliant and does not support rounding modifiers.rnd.f64 requires sm_20 or later. div. b. zd.3. yd. z.ftz}.4 and later. or .approx.f32 implements a fast approximation to divide. div. Fast.f32 flushes subnormal inputs and results to sign-preserving zero. d.rp}. a.approx.approx.ftz. the maximum ulp error is 2. For PTX ISA version 1.f32 div.rnd.f64 d. div.rn.f32 div.ftz.rm. Target ISA Notes div. .rz mantissa LSB rounds towards zero . stores result in d.approx. Description Semantics Notes Divides a by b. b.ftz}. xd.14159.approx. b.f64 defaults to div.rn.approx. 2010 .0 through 1. PTX ISA Notes div. div.ftz.approx{. one of .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.f32 and div.0. div Syntax Floating-Point Instructions: div Divide one value by another. .f64 requires sm_13 or later.circum.PTX ISA Version 2.rnd{. The maximum ulp error is 2 across the full range of inputs. sm_1x: div. approximate division by zero creates a value of infinity (with same sign as a). div.rnd = { .rn. computed as d = a * (1/b).{rz.full.f32 requires sm_20 or later. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . div.full.f32 supported on all target architectures.full.rz.f32 implements a relatively fast. .rp }.rn. subnormal numbers are supported. . 2126].full{.f32 div.rn mantissa LSB rounds to nearest even . For b in [2-126. div.f32 defaults to div.

f64 d.f64 supports subnormal numbers. subnormal numbers are supported.ftz. neg. Table 56.f64 requires sm_13 or later. abs.f32 supported on all target architectures.Chapter 8. subnormal numbers are supported. a.f64 supports subnormal numbers. sm_1x: neg.0.ftz. a. abs{. neg{.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. Take the absolute value of a and store the result in d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg.f32 neg. NaN inputs yield an unspecified NaN. sm_1x: abs. Instruction Set Table 55.f64 d. neg. NaN inputs yield an unspecified NaN.f0. 2010 91 . abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 supported on all target architectures. Subnormal numbers: sm_20: By default.f0.f64 requires sm_13 or later. neg. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. a. abs. Negate the sign of a and store the result in d. a. Subnormal numbers: sm_20: By default. January 24. abs.f32 x.f32 abs.ftz. d = |a|. abs. d.0. d.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. abs.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero. d = -a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f32 flushes subnormal inputs and results to sign-preserving zero.

0. a. d. subnormal numbers are supported.PTX ISA Version 2.c. min. @p min.0 Table 57.x.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: max.f64 f0. Store the minimum of a and b in d.f32 max.z. max. min. b.f32 min.f1.ftz}.f32 max. Store the maximum of a and b in d.c. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a.f64 supports subnormal numbers.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. max.ftz.f64 z. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 min. b. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.0. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. sm_1x: min. a.b. d d d d = = = = NaN. a. b.f64 d. a. min{.ftz. a.f2. Table 58.ftz. b. b. max{. subnormal numbers are supported. max. (a < b) ? a : b.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures.ftz. d. 92 January 24.f32 supported on all target architectures. min.f64 requires sm_13 or later. (a > b) ? a : b. 2010 . max. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. max. min.ftz}. d d d d = = = = NaN. a.b. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 supports subnormal numbers.

d.f64.f32 implements a fast approximation to reciprocal. rcp.x.0 +subnormal +Inf NaN Result -0.rnd{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. rcp. General rounding modifiers were added in PTX ISA version 2.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. Description Semantics Notes Compute 1/a. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rz.ftz.f64 defaults to rcp. xi. d = 1 / a.f32 supported on all target architectures.0-2.0 -Inf -Inf +Inf +Inf +0.approx. For PTX ISA versions 1.f64 and explicit modifiers .f32 requires sm_20 or later.rm.approx{. PTX ISA Notes rcp.r.f32 rcp.ftz}. d. Instruction Set Table 59.rn.f64 d. one of .f32 rcp.approx and .rn.approx or . rcp.rn.rp }. rcp.rnd. For PTX ISA version 1.f64 ri.rnd is required. Target ISA Notes rcp.0 +0.f32 defaults to rcp.3. a.0. a.approx.f32 and rcp.x.ftz.rz mantissa LSB rounds towards zero . rcp. sm_1x: rcp. rcp. xi.f64 supports subnormal numbers. 2010 93 .4 and later. .f64 requires sm_13 or later. rcp.rm.Chapter 8. // fast. Input -Inf -subnormal -0.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . store result in d.rn.ftz. Examples January 24.rn. .0 over the range 1. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . subnormal numbers are supported.0. rcp.approx.f32 rcp.rn mantissa LSB rounds to nearest even .4.f32.rp}.ftz.rm mantissa LSB rounds towards negative infinity .f64 introduced in PTX ISA version 1.0 through 1. rcp.rnd = { .f64 requires sm_20 or later.f32 flushes subnormal inputs and results to sign-preserving zero.0. .ftz were introduced in PTX ISA version 1.{rz.approx.rnd.rn. and rcp. a. rcp. The maximum absolute error is 2-23.f32 rcp.

0. For PTX ISA versions 1.f32.0 +0.f64.rn. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.rn. .0 +subnormal +Inf NaN Result NaN NaN -0.f32 and sqrt.ftz were introduced in PTX ISA version 1. d = sqrt(a). For PTX ISA version 1.approx or .approx.f64 defaults to sqrt. r. sm_1x: sqrt.4.rm mantissa LSB rounds towards negative infinity .f64 d. store in d.ftz. sqrt. one of .f64 supports subnormal numbers. r. PTX ISA Notes sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. Description Semantics Notes Compute sqrt(a).ftz. a. approximate square root d.0 through 1.rnd.0. // IEEE 754 compliant rounding .x. sqrt. sqrt.rnd.rnd = { .ftz.f32 sqrt.0 -0. Target ISA Notes sqrt.PTX ISA Version 2. sqrt. // IEEE 754 compliant rounding d.x.rn.f32 implements a fast approximation to square root.rm. General rounding modifiers were added in PTX ISA version 2. Examples 94 January 24.0 Table 60.approx.x.approx{.rp }.approx.rz.f64 r. a.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rp}.3.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .rn.approx.f32 sqrt. .ftz.rn mantissa LSB rounds to nearest even .rnd is required.f64 requires sm_20 or later.{rz.rn.rz mantissa LSB rounds towards zero .approx and .f32 defaults to sqrt.4 and later. Input -Inf -normal -subnormal -0.f64 introduced in PTX ISA version 1. a.approx. sqrt.ftz}.f32 sqrt.f32 requires sm_20 or later.f32 is TBD. sqrt. sqrt. The maximum absolute error for sqrt. and sqrt.rnd{.rm. sqrt. 2010 .f64 requires sm_13 or later. sqrt. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.f32 sqrt.rn. // fast.f64 and explicit modifiers .f32 supported on all target architectures.0 +0.ftz}.0 +0.

the .0.4 and later. Input -Inf -normal -subnormal -0.ftz. 2010 95 . ISR.f64 is emulated in software and are relatively slow. and rsqrt.approx{.approx.f64 d.ftz.approx.approx modifier is required. a.f32 and rsqrt.approx. Target ISA Notes Examples rsqrt.Chapter 8. rsqrt.f32 defaults to rsqrt. store the result in d.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f32 supported on all target architectures.f64 defaults to rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers .f64.f32 rsqrt.4 over the range 1. Note that rsqrt. rsqrt.0-4.f32 is 2-22. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.approx and . Subnormal numbers: sm_20: By default. PTX ISA Notes rsqrt.ftz.f64 were introduced in PTX ISA version 1. rsqrt. January 24.f32.ftz were introduced in PTX ISA version 1.approx.0 NaN The maximum absolute error for rsqrt. a. X.0.0 +0. rsqrt.approx.f64 supports subnormal numbers.f32 rsqrt. The maximum absolute error for rsqrt.approx implements an approximation to the reciprocal square root. subnormal numbers are supported.f64 isr. For PTX ISA version 1.f64 requires sm_13 or later. rsqrt.4.0 through 1. Instruction Set Table 61. Compute 1/sqrt(a). x. d. rsqrt.ftz}.3.approx. For PTX ISA versions 1. rsqrt. sm_1x: rsqrt. d = 1/sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero.f64 is TBD.

f32. a.0 NaN NaN The maximum absolute error is 2-20.ftz}.0 through 1.approx. sin.PTX ISA Version 2. PTX ISA Notes sin.f32 flushes subnormal inputs and results to sign-preserving zero.f32 sa. 2010 .f32 introduced in PTX ISA version 1.approx{. Find the sine of the angle a (in radians). subnormal numbers are supported. 96 January 24. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to sine.ftz introduced in PTX ISA version 1. a.3.0 Table 62. sin.approx modifier is required.0.0 -0.approx. the . sin.0 +subnormal +Inf NaN Result NaN -0. Explicit modifiers .0 +0. Subnormal numbers: sm_20: By default. Input -Inf -subnormal -0.ftz.ftz. For PTX ISA version 1.4 and later.0 +0.0 +0.approx and .f32 defaults to sin.approx. For PTX ISA versions 1. sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. d = sin(a).f32 d.9 in quadrant 00.4. sin.ftz. Target ISA Notes Examples Supported on all target architectures.

approx and .approx. PTX ISA Notes cos.0 through 1. cos. Subnormal numbers: sm_20: By default. Instruction Set Table 63. cos.approx. Find the cosine of the angle a (in radians). d = cos(a). Target ISA Notes Examples Supported on all target architectures.approx. sm_1x: Subnormal inputs and results to sign-preserving zero.4 and later.f32 introduced in PTX ISA version 1. Explicit modifiers . For PTX ISA version 1. a. subnormal numbers are supported. January 24.ftz introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.f32 implements a fast approximation to cosine.0 +0.ftz.0. Input -Inf -subnormal -0.ftz.f32.f32 d.3. cos. 2010 97 .9 in quadrant 00.0 +1.f32 ca. For PTX ISA versions 1.approx{. a.4.0 +1.Chapter 8.0 NaN NaN The maximum absolute error is 2-20.0 +subnormal +Inf NaN Result NaN +1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz. the . cos.f32 defaults to cos. cos.approx modifier is required.0 +1.

The maximum absolute error is 2-22. Input -Inf -subnormal -0.approx and .ftz}.f32 la.0 Table 64.approx.f32 introduced in PTX ISA version 1. PTX ISA Notes lg2. sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.3.PTX ISA Version 2.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.f32 Determine the log2 of a.4 and later.approx{. 98 January 24.0 +0. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.f32 defaults to lg2.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. the . Subnormal numbers: sm_20: By default. lg2.approx. For PTX ISA versions 1. Explicit modifiers .6 for mantissa.0 through 1. Target ISA Notes Examples Supported on all target architectures.ftz introduced in PTX ISA version 1.f32 implements a fast approximation to log2(a).f32. lg2.approx. a.approx modifier is required. lg2. lg2. 2010 .0.ftz. a.4. d = log(a) / log(2).ftz. lg2.ftz.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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a. . le. xor.CmpOp. .CmpOp{.B) is one of: and. le.type = { . The signed and unsigned comparison operators are eq. ge. hs equ.s32 setp. c). b. setp. gtu. leu.a.f32.ftz applies only to . sm_1x: setp. higher. geu. ltu.s32. ge. {!}c. gt. lt. . leu.b16. ls. geu. neu. neu. For unsigned values. .lt.u64.type setp. and (optionally) combine this result with a predicate value by applying a Boolean operator. and can be one of: eq. hi. lt. The comparison operator is a suffix on the instruction. .b. If either operand is NaN.BoolOp{. num. loweror-same.i. gtu. p[|q]. num returns true if both operands are numeric values (not NaN). ge.f64 }.f64 supports subnormal numbers. the result is false. c). gt.u16.dtype. respectively.and.s64. le. setp. bit-size comparisons are eq and ne. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. ne. subnormal numbers are supported. setp with .s16. a.f32 flushes subnormal inputs to sign-preserving zero.b64. @q setp.0 Table 67.0.f64 source type requires sm_13 or later. setp.r. and hs for lower. b. ltu. the comparison operators lo.dtype. then the result of these comparisons is true.b32. p = BoolOp(t. lo. . or. nan The Boolean operator BoolOp(A. gt.pred variables. If both operands are numeric values (not NaN). hi. ls. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. unordered versions are included: equ.type . The untyped. . Semantics t = (a CmpOp b) ? 1 : 0. Integer Notes Floating Point Notes The ordered comparisons are eq.f32 flushes subnormal inputs to sign-preserving zero.ftz}. ge.eq. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. Applies to all numeric types. This result is written to the first destination operand. .u32. Subnormal numbers: sm_20: By default. lt. gt. then these comparisons have the same result as their ordered counterparts. Modifier . To aid comparison operations in the presence of NaN values. .n. .f32 comparisons.ftz}. p. A related value computed using the complement of the compare result is written to the second destination operand.PTX ISA Version 2. The destinations p and q must be . 2010 .u32 p|q. ne. q = BoolOp(!t. le.ftz. and higher-or-same may be used instead of lt. p[|q]. and nan returns true if either operand is NaN. If either operand is NaN.dtype. ne. 102 January 24.

Operands d. . fval.ftz applies only to .dtype. c. . otherwise b is stored in d. B. selp Syntax Comparison and Selection Instructions: selp Select between source operands. slct. If operand c is NaN.u64.s32 x. and operand a is selected.f32 flushes subnormal values of operand c to sign-preserving zero. . .ftz}. . C. .s32.b32.f64 requires sm_13 or later.s16. . . a is stored in d.g.x.b64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32. .u16. val. .s32.f32. d.b16. . If c is True. a. . based on the sign of the third operand. a.f64 }.s32 selp. negative zero equals zero.u64.f32 d. b otherwise.Chapter 8. 2010 103 . slct. . @q selp. The selected input is copied to the output without modification. z. a. .u32. . b.dtype = { .dtype.u64.u16. . . c.f32 flushes subnormal values of operand c to sign-preserving zero.b32.b16. and b are treated as a bitsize type of the same width as the first instruction type. the comparison is unordered and operand b is selected.u32.f32 comparisons.f64 requires sm_13 or later. Description Conditional selection.ftz. For . .r. If c ≥ 0. and operand a is selected.f32 r0. d = (c >= 0) ? a : b. Table 69.s32 slct{.dtype. Instruction Set Table 68.b64. b.type d. slct. .0.ftz. y. selp.s64. .f32 comparisons. Modifier . slct. slct.xp. Subnormal numbers: sm_20: By default. selp. b.0. a is stored in d. a.s16.f64 }. slct Syntax Comparison and Selection Instructions: slct Select one source operand. d = (c == 1) ? a : b. c. Operands d.f32 A.t.dtype. a. Operand c is a predicate.type = { . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.p. f0. . operand c must match the second instruction type. Semantics Floating Point Notes January 24.u32. Introduced in PTX ISA version 1. and b must be of the same type. .s64. based on the value of the predicate source operand. subnormal numbers are supported. sm_1x: slct.

provided the operands are of the same size. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4.PTX ISA Version 2. performing bit-wise operations on operands of any type. This permits bit-wise operations on floating point values without having to define a union to access the bits. Instructions and.0 8.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. 2010 . and not also operate on predicates. xor. or.

.type d. Introduced in PTX ISA version 1.type = { . . Table 71. d = a | b. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.pred. . Instruction Set Table 70.pred. but not necessarily the type.r. Allowed types include predicate registers.b32 and. and.b16.b16. d = a & b. but not necessarily the type.q. a.b32. . . January 24.b32.0. . or.q.r.pred p.b64 }. .b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b32 mask mask. and. or Syntax Logic and Shift Instructions: or Bitwise OR. Introduced in PTX ISA version 1.Chapter 8. b.0x80000000. sign. b.0x00010001 or.0. The size of the operands must match. 2010 105 . Supported on all target architectures.fpvalue.type d. The size of the operands must match. . or.b32 x. Supported on all target architectures.type = { . a. and Syntax Logic and Shift Instructions: and Bitwise AND.

b16. not. Supported on all target architectures. xor. Supported on all target architectures. . The size of the operands must match. .type d.type d. 106 January 24.type = { .b32 d.a.b64 }.x. Introduced in PTX ISA version 1. . one’s complement.type d. cnot. 2010 . The size of the operands must match.b16 d. not.0.type = { . d = a ^ b.b32.b32. .0. Table 73. .pred. a. b.0 Table 72. Introduced in PTX ISA version 1.pred p. . d = ~a.PTX ISA Version 2. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.q. not. . Allowed types include predicates. Introduced in PTX ISA version 1.b64 }. Allowed types include predicate registers. Table 74. xor. . but not necessarily the type. cnot.type = { . a. The size of the operands must match.b16. a.0x0001. .mask. but not necessarily the type.q.b32 xor.pred. . Supported on all target architectures. d = (a==0) ? 1 : 0.b32 mask. not Syntax Logic and Shift Instructions: not Bitwise negation. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). d. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b64 }. .0. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.r. but not necessarily the type.b16.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.

Introduced in PTX ISA version 1. shr.0. but not necessarily the type. .j.u64. shl Syntax Logic and Shift Instructions: shl Shift bits left.0. .s32. The b operand must be a 32-bit value. Shift amounts greater than the register width N are clamped to N. . shl.u16. Bit-size types are included for symmetry with SHL.b32. shl. d = a >> b. d = a << b.s32 shr.type d. Signed shifts fill with the sign bit. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. .type d. .a.b16. .i. zero-fill on right.2. shr Syntax Logic and Shift Instructions: shr Shift bits right. . Supported on all target architectures.b32. The b operand must be a 32-bit value. Instruction Set Table 75. regardless of the instruction type.u16 shr.s64 }. .b32 q. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. a. b.u32. unsigned and untyped shifts fill with 0.b64 }. shr. Introduced in PTX ISA version 1. . . PTX ISA Notes Target ISA Notes Examples Table 76. PTX ISA Notes Target ISA Notes Examples January 24. The sizes of the destination and first source operand must match.type = { . sign or zero fill on left. a. i. Supported on all target architectures.b16 c. b.a. k.1.type = { .i. but not necessarily the type. .b16.Chapter 8. Shift amounts greater than the register width N are clamped to N. .2.s16. 2010 107 .b64. The sizes of the destination and first source operand must match. regardless of the instruction type.

0 8. ld. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.5.7. ldu. or shared state spaces.PTX ISA Version 2. The cvta instruction converts addresses between generic and global. and from state space to state space. Instructions ld. suld. 2010 . and sust support optional cache operations. and st operate on both scalar and vector types. st. local. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. prefetchu isspacep cvta cvt 108 January 24. Data Movement and Conversion Instructions These instructions copy data from place to place. mov. possibly converting it from one format to another.

cs is applied to a Local window address. fetch again). 2010 109 . .Chapter 8. the second thread may get stale L1 cache data.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The ld. the cache operators have the following definitions and behavior. A ld. The default load instruction cache operation is ld. rather than the data stored by the first thread. Use ld. The compiler / programmer may use ld. Table 77. If one thread stores to global memory via one L1 cache. . For sm_20 and later.lu load last use operation. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. likely to be accessed again. The ld.ca. and a second thread loads that address via a second L1 cache with ld.7.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. likely to be accessed once.lu instruction performs a load cached streaming operation (ld.cv to a frame buffer DRAM address is the same as ld.cg to cache loads only globally. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cs) on global addresses. bypassing the L1 cache.lu operation. but multiple L1 caches are not coherent for global data. The ld. . As a result of this request.1. evict-first. .cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.0 introduces optional cache operators on load and store instructions. Cache Operators PTX 2. invalidates (discards) the local L1 line following the load.ca. it performs the ld.ca loads cached in L1.5. The ld. Global data is coherent at the L2 level.cs.cs Cache streaming. when applied to a local address. The cache operators require a target architecture of sm_20 or later. January 24. any existing cache lines that match the requested address in L1 will be evicted.lu Last use. if the line is fully covered. Operator . to allow the thread program to poll a SysMem location written by the CPU.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. When ld. and cache only in the L2 cache. Instruction Set 8. not L1).cv Cache as volatile (consider cached system memory lines stale.cg Cache at global level (cache in L2 and below.

and a second thread in a different SM later loads from that address via a different L1 cache with ld. Operator . regardless of the cache operation. the second thread may get a hit on stale L1 cache data. Use st. The st. bypassing the L1 cache. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. Global stores bypass L1. and marks local L1 lines evict-first.ca. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wt. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. which writes back cache lines of coherent cache levels with normal eviction policy. 2010 . likely to be accessed once.wt store write-through operation applied to a global System Memory address writes through the L2 cache. 110 January 24. Addresses not in System Memory use normal write-back. not L1).cg is the same as st. but st. In sm_20.PTX ISA Version 2.cg to local memory uses the L1 cache. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wb for global data.wt Cache write-through (to system memory). st. and discard any L1 lines that match. The st.cg to cache global store data only globally. The default store instruction cache operation is st. . in which case st. .wb. If one thread stores to global memory. .wb could write-back global store data from L1.0 Table 78. rather than get the data from L2 or memory stored by the first thread. bypassing its L1 cache. to allow a CPU program to poll a SysMem location written by the GPU with st. and cache only in the L2 cache.ca loads.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Future GPUs may have globally-coherent L1 caches.cg Cache at global level (cache in L2 and below. However.cs Cache streaming.

0.f64 requires sm_13 or later. mov. Write register d with the value of a. special register. . or function name. label.f32 mov. . local. alternately. . within the variable’s declared state space Notes Although only predicate and bit-size types are required.type mov. and .f32. addr. A[5].f64 }. the parameter will be copied onto the stack and the address will be in the local state space. Description .local.. Operand a may be a register. .e.s32. . k. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. 2010 111 . the generic address of a variable declared in global. // address is non-generic. . or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.pred.b32.u32 mov.type mov. . or shared state space. The generic address of a variable in global. immediate. d = &avar. Take the non-generic address of a variable in global. local.Chapter 8. mov. // get address of variable // get address of label or function . Instruction Set Table 79.type = { .u16.u32 mov.u32 d. A. . d = &label. .1.s16.b64. label. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. .. sreg.type mov. local. Note that if the address of a device function parameter is moved to a register.u32. d. Introduced in PTX ISA version 1. variable in an addressable memory space. i.shared state spaces. d = sreg. d. ptr. u.s64. avar.a.type d. Semantics d = a. For variables declared in . ptr.0. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. myFunc. the address of the variable in its state space) into the destination register. mov places the non-generic address of the variable (i.const. d.u64. . mov. a. . or shared state space may be taken directly using the cvta instruction.global.v.f32 mov.e.u16 mov.b16.

x.a}. mov.x | (a..b have type .u16 %x is a double.hi are .w } = { a[0. {r.%r1.b64 112 January 24..z. Supported on all target architectures. d.y << 16) | (a. d..47].b32 { d. or write vector register d with the unpacked values from scalar register a.w}.. lo.63] } // unpack 16-bit elements from .x.b.15]. a[16..z. a[16. For bit-size types.y << 8) d = a.b64 { d.31] } // unpack 8-bit elements from .g. a[16.z << 16) | (a.b64 }.hi}.b32 %r1.b64 { d. a[8..z.b64 // pack two 32-bit elements into . Description Write scalar register d with the packed value of vector register a.15]. d.b32 // pack two 16-bit elements into .x.31].7].z.type = { .u8 // unpack 32-bit elements from .u32 x.x | (a. d. . Semantics d = a.w << 48) d = a. a[8.a have type .0.15] } // unpack 8-bit elements from .y } = { a[0.b64 mov. a[24.y.b8 r.0 Table 80. d.. {lo. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector..w << 24) d = a. 2010 .y } = { a[0.b16.23].y.x..type d.z << 32) | (a.w } = { a[0.y.x.{x. %x. mov. d.y << 16) d = a.. // // // // a.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.x | (a.x | (a.y.g.b32 mov.15]. a.y << 8) | (a. a[32..b}.31].7]. . mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).31] } // unpack 16-bit elements from . d.b32 mov. a[48..b32 // pack four 16-bit elements into .y << 32) // pack two 8-bit elements into .{a. d..y } = { a[0.x | (a. .b32 { d.b16 // pack four 8-bit elements into .b32.b16 { d.. d. %r1. a[32.w have type .b. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.PTX ISA Version 2.

.volatile. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. Within these windows. In generic addressing. If an address is not properly aligned.volatile may be used with .b64.Chapter 8. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. This may be used. . d.v2.. i. or [immAddr] an immediate absolute byte address (unsigned.b16.global and . ld. . .lu.local. .param. i. *(a+immOff). and is zeroextended to the destination register width for unsigned and bit-size types. ld{.ss}{.volatile.type ld. . ld. The address size may be either 32-bit or 64-bit. an address maps to global memory unless it falls within the local memory window or the shared memory window.f32.f16 data may be loaded using ld. Semantics d d d d = = = = a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a]. d.u64.volatile introduced in PTX ISA version 1.b8.ss = { . to enforce sequential consistency between threads accessing shared memory. .v4 }. .0.ca.s16. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.type .1.s32. the resulting behavior is undefined. 32-bit). . .u32. .0.cs.const space suffix may have an optional bank number to indicate constant banks other than bank zero.cg.volatile{.global. or the instruction may fault. *(immAddr). . *a. The value loaded is sign-extended to the destination register width for signed integers.f64 using cvt. A destination register wider than the specified type may be used.ss}. and then converted to . [a].cop = { .f64 }.shared }.vec = { . for example.cv }. .b32. perform the load using generic addressing. . .cop}.u16.volatile{. Cache operations are not permitted with ld. Generic addressing may be used with ld.ss}.vec. If no state space is given.cop}. and truncated if the register width exceeds the state space address width for the target architecture.type ld{. . Instruction Set Table 81.s64. . .u8.b16.type d. . an address maps to the corresponding location in local or shared memory. .const. 32-bit). Generic addressing and cache operations introduced in PTX ISA 2. an integer or bit-size type register reg containing a byte address. .ss}{. Description Load register variable d from the location specified by the source address operand a in specified state space. . d. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. 2010 113 . ld introduced in PTX ISA version 1.reg state space. The address must be naturally aligned to a multiple of the access size. PTX ISA Notes January 24.s8. Addresses are zero-extended to the specified width as needed. . .e.e. The .vec.f32 or . .shared spaces to inhibit optimization of references to volatile memory. [a].type = { . [a].

const[4].v4. // access incomplete array x.[p]. // load .f64 requires sm_13 or later.f32. 2010 .local. ld.[a].s32 ld.const.[fs]. Q. Generic addressing requires sm_20 or later.b32 ld.0 Target ISA Notes ld.[240]. Cache operations require sm_20 or later.global.b16 cvt. d.[p+4].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.f32 ld.[p+-8]. // negative offset %r.global. x.b32 ld.%r.PTX ISA Version 2.b64 ld.[buffer+64]. // immediate address %r. %r.b32 ld.local.f16 d.shared.

. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. ldu{.s16. . *(a+immOff). i. // load from address // vec load from address . The addressable operand a is one of: [avar] the name of an addressable variable var. . Semantics d d d d = = = = a. .Chapter 8. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . The data at the specified address must be read-only.f32 or .global }.[p]. . and truncated if the register width exceeds the state space address width for the target architecture. [a].v4. [areg] a register reg containing a byte address. and then converted to .ss}. . Introduced in PTX ISA version 2.v4 }. For ldu. The address must be naturally aligned to a multiple of the access size. .b16.type = { . If no state space is given.u16. 32-bit). Addresses are zero-extended to the specified width as needed. The address size may be either 32-bit or 64-bit. .0. [a]. If an address is not properly aligned.f32 d.u64. In generic addressing.ss}.f32 Q.s32. . . ldu. ldu. .global.f32.type d. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. *a. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ldu. i.global.ss = { . ldu.b32.u32. *(immAddr). A destination register wider than the specified type may be used. Within these windows.[a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. the resulting behavior is undefined. or [immAddr] an immediate absolute byte address (unsigned.b32 d. PTX ISA Notes Target ISA Notes Examples January 24.f16 data may be loaded using ldu.u8. an address maps to the corresponding location in local or shared memory.b64.b8. 2010 115 .[p+4].e. .reg state space. where the address is guaranteed to be the same across all threads in the warp. only generic addresses that map to global memory are legal.s64.f64 requires sm_13 or later. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f64 using cvt. d.. .v2. perform the load using generic addressing.e. or the instruction may fault. . and is zeroextended to the destination register width for unsigned and bit-size types.vec.f64 }. .type ldu{. Instruction Set Table 82. 32-bit).vec = { .s8. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .b16.global. The value loaded is sign-extended to the destination register width for signed integers. A register containing an address may be declared as a bit-size type or integer type. // state space .

b.cs. the access may proceed by silently masking off low-order address bits to achieve proper rounding. This may be used. [a]. { .global.b64.0 Table 83. the resulting behavior is undefined. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. { .v4 }. an address maps to the corresponding location in local or shared memory.volatile introduced in PTX ISA version 1. [a]. A source register wider than the specified type may be used.type [a].0. an integer or bit-size type register reg containing a byte address.f16 data resulting from a cvt instruction may be stored using st. and truncated if the register width exceeds the state space address width for the target architecture. . PTX ISA Notes Target ISA Notes 116 January 24. i.reg state space.cop .b16.volatile{.. b.e.shared }. .b32. . Cache operations require sm_20 or later. i. . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.ss}.PTX ISA Version 2. .0.ss}{. to enforce sequential consistency between threads accessing shared memory. *(immAddr) = a. .cg.ss}. If no state space is given.s8. or [immAddr] an immediate absolute byte address (unsigned.type = = = = {.v2.s32.global and .type st. In generic addressing.f32.e. . st.vec . for example. [a].vec.cop}. . st. Semantics d = a. *d = a. perform the store using generic addressing.cop}.u32.vec. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.b8.wb. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . Cache operations are not permitted with st. 32-bit). or the instruction may fault.volatile.f64 }.volatile{. Addresses are zero-extended to the specified width as needed. .f64 requires sm_13 or later. . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. If an address is not properly aligned.type .wt }. The address must be naturally aligned to a multiple of the access size. st introduced in PTX ISA version 1.shared spaces to inhibit optimization of references to volatile memory. . . Within these windows.u16. . *(d+immOffset) = a.s16.s64. Generic addressing requires sm_20 or later.type st{. . . Generic addressing may be used with st. b. st{. . . an address maps to global memory unless it falls within the local memory window or the shared memory window. The lower n bits corresponding to the instruction-type width are stored to memory.volatile. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Generic addressing and cache operations introduced in PTX ISA 2. .u64. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .b16.ss}{. b. 32-bit). The address size may be either 32-bit or 64-bit.volatile may be used with .ss . { .u8.1. .local. 2010 . st.

f32 st. 2010 117 .local.s32 cvt.a. Instruction Set Examples st.local.a. // immediate address %r.local.r7. // %r is 32-bit register // store lower 16 bits January 24.%r.f32 st. [p].b.Chapter 8. [q+4].v4.Q.s32 st. // negative offset [100].global.b32 st.global. [fs]. [q+-8].f16.%r.b32 st.b16 [a].

level = { . A prefetch to a shared memory location performs no operation.0 Table 84. The address size may be either 32-bit or 64-bit. // prefetch to data cache // prefetch to uniform cache .L2 }.level prefetchu.PTX ISA Version 2.e. an address maps to global memory unless it falls within the local memory window or the shared memory window.L1.local }. and truncated if the register width exceeds the state space address width for the target architecture.0. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.space = { . prefetch. and no operation occurs if the address maps to a local or shared memory location. an address maps to the corresponding location in local or shared memory. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. Within these windows. In generic addressing.L1 [addr]. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. the prefetch uses generic addressing. i. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. in specified state space.space}.L1 [a]. [a]. Addresses are zero-extended to the specified width as needed. 118 January 24.L1 [ptr].global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. 32-bit). If no state space is given. a register reg containing a byte address. prefetch{. A prefetch into the uniform cache requires a generic address. prefetch and prefetchu require sm_20 or later. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . .global. . prefetchu. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or [immAddr] an immediate absolute byte address (unsigned. 32-bit).

local.u64. . lptr.lptr.to. Take the generic address of a variable declared in global. // get generic address of svar cvta.u32 gptr. local.size cvta. or shared address to a generic address. The source and destination addresses must be the same size. p.space p.pred .to. islcl. A program may use isspacep to guard against such incorrect behavior.u32 to truncate or zero-extend addresses. cvta. The destination register must be of type . // result is . January 24. // convert to generic address // get generic address of var // convert generic address to global.shared }. local.local isspacep. local. Instruction Set Table 85. p. isspacep. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or vice-versa. var.local. cvta. or shared state space. When converting a generic address into a global.shared. a.space.space.u64.space = { .size . gptr. Introduced in PTX ISA version 2.global. .u64 or cvt. // local. . PTX ISA Notes Target ISA Notes Examples Table 86. . Description Convert a global. . the generic address of the variable may be taken using cvta.u32 or .genptr. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.global.u32. or shared state space.size = { .global. isspacep requires sm_20 or later. or shared address cvta.u64 }. or shared state space to generic. For variables declared in global.u32 p.u32. Use cvt.global isspacep.shared }.local.0. a.u32 p. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.size p. cvta requires sm_20 or later.space. local.Chapter 8. 2010 119 . a. sptr.pred. isspacep.space = { . isshrd.shared isglbl. . svar. The source address operand must be a register of type . local.0. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. or vice-versa. cvta. or shared address.

.sat}.frnd = { . .MAXINT for the size of the operation. . subnormal inputs are flushed to signpreserving zero.f32.u16.. The optional . Note: In PTX ISA versions 1.f32 float-to-integer conversions and cvt.sat is redundant. Integer rounding is illegal in all other instances.u64.sat}. . .ftz}{. . .f64 }. a.f32 float-tofloat conversions with integer rounding.ftz. .s16.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.s64. 120 January 24. . Integer rounding modifiers: . // integer rounding // fp rounding .sat For integer destination types. i.irnd = { . subnormal numbers are supported.u32.ftz}{.. For float-to-integer conversions. . d. a. .dtype = . The compiler will preserve this behavior for legacy PTX code. the result is clamped to the destination range by default.rm.ftz.irnd}{.atype d.dtype. . sm_1x: For cvt. . subnormal inputs are flushed to signpreserving zero. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.rmi round to nearest integer in direction of negative infinity .rni.e. Note that saturation applies to both signed and unsigned integer types. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.atype cvt{.f32 float-to-integer conversions and cvt. .dtype. . . . choosing even integer if source is equidistant between two integers. the .dtype.4 and earlier. Saturation modifier: .rz. cvt{. d = convert(a). 2010 . .frnd}{.rzi. and for same-size float-tofloat conversions where the value is rounded to an integer. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. .rni round to nearest integer.sat limits the result to MININT.0 Table 87.rzi round to nearest integer in the direction of zero . For cvt. .PTX ISA Version 2.f32.ftz.atype = { .rn. .rp }.s32. Integer rounding is required for float-to-integer conversions.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. i.f16.s8.rmi.dtype.ftz modifier may be specified in these cases for clarity.f32.ftz.e.u8. Description Semantics Integer Notes Convert between different types and sizes.rpi }.f32 float-tofloat conversions with integer rounding.

4 or earlier. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. .f16. Introduced in PTX ISA version 1. The compiler will preserve this behavior for legacy PTX code.0. The operands must be of the same size.f16. and cvt.ftz modifier may be specified in these cases for clarity.i. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f32. Applies to .rz mantissa LSB rounds towards zero .ftz behavior for sm_1x targets January 24.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. cvt.y.f32.0.r.s32 f.f32. // note .y.sat limits the result to the range [0. Subnormal numbers: sm_20: By default.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).f64 types. Floating-point rounding modifiers: . // float-to-int saturates by default cvt. The result is an integral value. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64 j. cvt.f32. stored in floating-point format.f32 x. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f16. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. Note: In PTX ISA versions 1.f64 requires sm_13 or later. cvt.0].f32. NaN results are flushed to positive zero.rm mantissa LSB rounds towards negative infinity . and for integer-to-float conversions. cvt to or from .Chapter 8. if the PTX . // round to nearest int. result is fp cvt. Floating-point rounding is illegal in all other instances. Saturation modifier: . 1.s32.f64. The optional . and .f32 instructions. subnormal numbers are supported. Modifier .f32 x.f32.f32.rni. 2010 121 . Specifically.sat For floating-point destination types.version is 1.4 and earlier.rn mantissa LSB rounds to nearest even . .

In the independent mode. . Ability to query fields within texture. add.b32 r5. A PTX module may declare only one texturing mode.. Example: calculate an element’s power contribution as element’s power/total number of elements. the file is assumed to use unified mode. // get tex1’s tex.target texmode_independent .f32. r1.0 8. sampler. r6. PTX supports the following operations on texture.global .entry compute_power ( .f32. sampler. r5. and surface descriptors. r1. The advantage of unified mode is that it allows 128 samplers. sampler. with the restriction that they correspond 1-to-1 with the 128 possible textures. texture and sampler information is accessed through a single .texref tex1 ) { txq. If no texturing mode is declared. 2010 .texref handle. 122 January 24.r4}.7. add.PTX ISA Version 2. . and surface descriptors. The texturing mode is selected using . = nearest width height tsamp1.r2. r5. PTX has two modes of operation. r2.samplerref tsamp1 = { addr_mode_0 filter_mode }..r3. {f1. sampler.u32 r5. Texture and Surface Instructions This section describes PTX instructions for accessing textures. allowing them to be defined separately and combined at the site of usage in the program. [tex1].height.f32 r3.target options ‘texmode_unified’ and ‘texmode_independent’.b32 r6.width. texture and sampler information each have their own handle. and surface descriptors: • • • Static initialization of texture.v4.f2}]. r4. Module-scope and per-entry scope definitions of texture.f32 r1. cvt. mul. Texturing modes For working with textures and samplers. r5. and surface descriptors.f32 r1. In the unified mode.6. The advantage of independent mode is that textures and samplers can be mixed and matched. div. r3.2d. } = clamp_to_border. r1. samplers. [tex1].param . r3. // get tex1’s txq.f32 r1. and surfaces. [tex1. but the number of samplers is greatly restricted to 16.u32 r5.f32 {r1. . add.

//Example of unified mode texturing tex. b. Notes For compatibility with prior versions of PTX.f32 }. tex txq suld sust sured suq Table 88.1d. the access may proceed by silently masking off low-order address bits to achieve proper rounding. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.s32. {f1. Operand c is a scalar or singleton tuple for 1d textures. . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.r4}.v4. // explicit sampler . Unified mode texturing introduced in PTX ISA version 1. c].r3. [tex_a.0. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. tex.geom = { . the resulting behavior is undefined.r2. . .s32 {r1.s32.s32.f3.geom. If an address is not properly aligned. is a two-element vector for 2d textures. 2010 123 .dtype.geom. the sampler behavior is a property of the named texture. Description Texture lookup using a texture coordinate vector. or the instruction may fault. sampler_x.e.r3.r4}.5. .. If no sampler is specified. // Example of independent mode texturing tex. [a.btype = { .2d.3d. [a. . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.f32 }. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. d. . the square brackets are not required and .u32.v4 coordinate vectors are allowed for any geometry. c]. Instruction Set These instructions provide access to texture and surface memory.r2.Chapter 8. An optional texture sampler b may be specified. .f32 {r1.dtype.v4. {f1}].f4}].1d.dtype = { .v4.3d }. [tex_a. The instruction always returns a four-element vector of 32-bit values.f2. and is a four-element vector for 3d textures. with the extra elements being ignored.v4.btype tex. where the fourth element is ignored. PTX ISA Notes Target ISA Notes Examples January 24. i. Supported on all target architectures.s32. A texture base address is assumed to be aligned to a 16-byte address.btype d.

mirror. Operand a is a . Query: .tquery = { .PTX ISA Version 2. txq. // texture attributes // sampler attributes .5. txq.b32 %r1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.height . [a]. [tex_A].height. [tex_A].samplerref variable. txq. .tquery. 2010 . and in independent mode sampler attributes are accessed via a separate samplerref argument.squery = { .0 Table 89.texref or . Description Query an attribute of a texture or sampler.width.filter_mode. [a]. // unified mode // independent mode 124 January 24. Supported on all target architectures.addr_mode_0.normalized_coords }. [smpl_B].addr_mode_0. sampler attributes are also accessed via a texref argument. . clamp_ogl.filter_mode . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.b32 txq. addr_mode_2 }.b32 %r1.depth. .b32 d.width .filter_mode.b32 %r1.normalized_coords . linear } Integer from enum { wrap.addr_mode_0 .depth . . txq. In unified mode.squery.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). . d. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.width. clamp_to_edge. Integer from enum { nearest. addr_mode_1.addr_mode_1 .

The lowest dimension coordinate represents a byte offset into the surface and is not scaled. suld.trap .trap suld.dtype .Chapter 8.p. . is a two-element vector for 2d surfaces. the access may proceed by silently masking off low-order address bits to achieve proper rounding. // for suld. and cache operations introduced in PTX ISA version 2.b.p.p .p is currently unimplemented.z. [surf_A.1d. .b64 }.b .s32.clamp . B.clamp field specifies how to handle out-of-bounds addresses: .surfref variable.dtype .b supported on all target architectures.p. . . where the fourth element is ignored.v4.s32. Operand a is a .cop}. Instruction Set Table 90.cv }.b64.geom .b32. 2010 125 .clamp suld.cop}.2d.s32. suld. b]. sm_1x targets support only the . // cache operation none. suld. and is a four-element vector for 3d surfaces. // unformatted d. the surface sample elements are converted to .vec . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.trap clamping modifier. .trap. If an address is not properly aligned.1d.3d. suld Syntax Texture and Surface Instructions: suld Load from surface memory. SNORM.f32. .p requires sm_20 or later. . .3d requires sm_20 or later.u32 is returned.b32.clamp.zero }. {f1. Target ISA Notes Examples January 24. or .e. Coordinate elements are of type . .cg..trap {r1. suld.dtype.clamp .cop . [surf_B.v2. . if the surface format contains SINT data.vec.cs.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.5.y. {x. .r2}.u32. . // for suld. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. and A components of the surface format. Cache operations require sm_20 or later.dtype. . [a.geom{.v2. [a. Destination vector elements corresponding to components that do not appear in the surface format are not written. then . suld. and the size of the data transfer matches the size of destination operand d. i. .b. or the instruction may fault.s32.u32.0.v4.f32.trap introduced in PTX ISA version 1.f32 based on the surface format as follows: If the surface format contains UNORM. additional clamp modifiers. G. then . A surface base address is assumed to be aligned to a 16-byte address. If the destination base type is . if the surface format contains UINT data.b8 .clamp = = = = = = { { { { { { d. {x}]. . The .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.ca. the resulting behavior is undefined.u32.3d }.f32 is returned. size and type conversion is performed as needed to convert from the surface sample format to the destination type. Description Load from surface memory using a surface coordinate vector.geom{. // formatted . suld. Operand b is a scalar or singleton tuple for 1d surfaces.b performs an unformatted load of binary data.f4}.s32 is returned. b]. . . suld. or FLOAT data. If the destination type is .f32 }. .b32.b. or . The lowest dimension coordinate represents a sample offset rather than a byte offset.w}]. suld.f2.f3. suld. .v4 }. then .b16.

b64 }.b performs an unformatted store of binary data. or the instruction may fault. sust. . none. If the source base type is .1d.geom . . The size of the data transfer matches the size of source operand c.clamp sust. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . sust. SNORM.3d.ctype .b supported on all target architectures.v2.f32} are currently unimplemented. sust. sust.f2. If the source type is .clamp = = = = = = { { { { { { [a.wb. {r1.trap introduced in PTX ISA version 1.trap. .0 Table 91. sust.y.s32. . Operand a is a . B. These elements are written to the corresponding surface sample components. size and type conversions are performed as needed between the surface sample format and the destination type.f32.p.trap sust. and A surface components.trap . // for sust. if the surface format contains UINT data. [surf_B. Coordinate elements are of type . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. [a.cop}. and is a four-element vector for 3d surfaces. or .u32. sust. .cg. A surface base address is assumed to be aligned to a 16-byte address.b16.p Description Store to surface memory using a surface coordinate vector.ctype.0. .f32. sust Syntax Texture and Surface Instructions: sust Store to surface memory.u32.cop}. . .e.s32 is assumed.f4}.b8 . sust.b32. If an address is not properly aligned.geom{.v2. sm_1x targets support only the .vec.b. {f1.cs. .ctype .cop . .3d requires sm_20 or later. The source data is then converted from this type to the surface sample format.b64.trap [surf_A.v4 }. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.surfref variable. where the fourth element is ignored.clamp field specifies how to handle out-of-bounds addresses: .s32.z.b32.f32 }.zero }.b // for sust.2d. The lowest dimension coordinate represents a sample offset rather than a byte offset. c.PTX ISA Version 2. . Surface sample components that do not occur in the source vector will be written with an unpredictable value.u32 is assumed. The . .f3. .clamp . if the surface format contains SINT data.vec .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. c.clamp . G. then .s32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. {x}]. then .v4. // unformatted // formatted .ctype. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.p. Operand b is a scalar or singleton tuple for 1d surfaces. sust.clamp.vec. then . 2010 . Cache operations require sm_20 or later.p performs a formatted store of a vector of 32-bit data values to a surface sample. Source elements that do not occur in the surface sample are ignored. b].f32 is assumed. ..r2}.trap clamping modifier. {x.w}].p. Target ISA Notes Examples 126 January 24.geom{. additional clamp modifiers. b]. is a two-element vector for 2d surfaces. the resulting behavior is undefined. . .b32.b. i.5. or FLOAT data. The source vector elements are interpreted left-to-right as R.p requires sm_20 or later. sust. and cache operations introduced in PTX ISA version 2.{u32.3d }. .b. .1d.p.s32.wt }.

u32. .ctype.1d.b32 }.b32. Operand a is a .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The lowest dimension coordinate represents a sample offset rather than a byte offset. . or .zero }. and .max. A surface base address is assumed to be aligned to a 16-byte address.u32 based on the surface sample format as follows: if the surface format contains UINT data. operations and and or apply to .s32 types.and.geom. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.ctype. i. Operations add applies to . Instruction Set Table 92. .s32. .3d }. {x.s32.clamp = { . where the fourth element is ignored. .e. .u32. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. The . sured. . The instruction type is restricted to .u64 data. . sured requires sm_20 or later. is a two-element vector for 2d surfaces. Operand b is a scalar or singleton tuple for 1d surfaces.clamp .trap sured. or the instruction may fault. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u64.u32 and .b performs an unformatted reduction on .surfref variable.geom. Coordinate elements are of type .b32.add. {x}]. [surf_B.clamp. Reduction to surface memory using a surface coordinate vector.ctype = { . If an address is not properly aligned. // sample addressing .clamp field specifies how to handle out-of-bounds addresses: .s32 types.c.clamp [a. if the surface format contains SINT data.u64.b . sured.. // for sured.1d. sured.2d. .min.s32.ctype = { .b]. then .Chapter 8. 2010 127 .geom = { . r1.clamp [a. and is a four-element vector for 3d surfaces.b.b32.c. then .op.s32 is assumed.b32 type.b].u32 is assumed.min.op. .op = { .s32 or . and the data is interpreted as . . .add.u32. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.0. .or }. sured. January 24. // for sured.p performs a reduction on sample-addressed 32-bit data.p . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.trap [surf_A.p. min and max apply to .trap. .b32 }. . r1.p. // byte addressing sured.2d.u32.trap .y}]. .b. the resulting behavior is undefined.

128 January 24.query. [surf_A]. .b32 d. Supported on all target architectures.b32 %r1.PTX ISA Version 2. 2010 . . suq.width. suq. Description Query an attribute of a surface.width .0 Table 93.5. Operand a is a .depth }. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.query = { .surfref variable. Query: .width. [a].depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.height .height.

{ add.s32 a. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. Execute an instruction or instruction block for threads that have the guard predicate true. @{!}p instruction. If {!}p then instruction Introduced in PTX ISA version 1. Instruction Set 8.0. { instructionList } The curly braces create a group of instructions.y. Introduced in PTX ISA version 1. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.0.f32 @q bra L23.7.7.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.f32 @!p div.x. Threads with a false guard predicate do nothing.eq. setp. } PTX ISA Notes Target ISA Notes Examples Table 95.a.b. p. {} Syntax Description Control Flow Instructions: { } Instruction grouping.s32 d.c.0. used primarily for defining a function body. ratio.Chapter 8. mov. Supported on all target architectures. 2010 129 . Supported on all target architectures.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Register operands. Register operands.sync bar.arrive a{. and d have type .Chapter 8.sync) until the barrier count is met. bar.red are population-count (. When a barrier completes. bar. it simply marks a thread's arrival at the barrier. the final value is written to the destination register in all threads waiting at the barrier.u32.or). Operand b specifies the number of threads participating in the barrier. Once the barrier count is reached.u32 bar.{arrive. a{. In addition to signaling its arrival at the barrier. operands p and c are predicates. Operands a.red should not be intermixed with bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. All threads in the warp are stalled until the barrier completes.sync without a thread count introduced in PTX ISA 1.sync or bar.sync or bar. If no thread count is specified.{arrive. The reduction operations for bar. all threads in the CTA participate in the barrier.15. bar. Thus. the optional thread count must be a multiple of the warp size. it is as if all the threads in the warp have executed the bar instruction.op = { . Instruction Set Table 100. bar.sync with an immediate barrier number is supported for sm_1x targets. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.sync and bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. b}. bar. {!}c. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. a{. if any thread in a warp executes a bar instruction.popc. Barriers are executed on a per-warp basis as if all the threads in a warp are active.red. January 24.0. Each CTA instance has sixteen barriers numbered 0. b.arrive using the same active barrier. a.red instruction. Thus.red performs a reduction operation across threads.cta. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. . The result of . b. 2010 133 . a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). and bar. bar. d. and any-thread-true (.red also guarantee memory ordering among threads identical to membar. and bar.pred . Only bar. b}.red} require sm_20 or later. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). while . PTX ISA Notes Target ISA Notes Examples bar. Execution in this case is unpredictable. bar. the waiting threads are restarted without delay. all-threads-true (. thread count. bar. thread count..red performs a predicate reduction across the threads participating in the barrier.or }. and the barrier is reinitialized so that it can be immediately reused.red delays the executing threads (similar to bar. In conditionally executed code. Note that a non-zero thread count is required for bar.red} introduced in PTX . The barrier instructions signal the arrival of the executing threads at the named barrier.op. threads within a CTA that wish to communicate via memory can store to memory.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. {!}c.0.red.and.and). execute a bar. the bar.and and . b}.sync and bar.arrive does not cause any waiting by the executing threads. Description Performs barrier synchronization and communication within a CTA.popc is the number of threads with a true predicate.arrive.sync 0. and then safely read values stored by other threads prior to the barrier. p. Since barriers are executed on a per-warp basis.popc). bar.version 2.

including thoses communicating via PCI-E such as system and peer-to-peer memory.sys Waits until all prior memory requests have been performed with respect to all clients. For communication between threads in different CTAs or even different SMs.sys.4.cta. that is. this is the appropriate level of membar. . membar. membar.0. when the previous value can no longer be read. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. 2010 . membar. membar.sys }. 134 January 24. by st. PTX ISA Notes Target ISA Notes Examples membar. membar.g. membar.{cta. red or atom) has been performed when the value written has become visible to other clients at the specified level.{cta.PTX ISA Version 2.level. membar.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.version 1.g. global.sys introduced in PTX . membar. or system memory level.version 2. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.sys requires sm_20 or later.gl. membar.cta. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. . . level describes the scope of other clients for which membar is an ordering event. membar.gl will typically have a longer latency than membar.0 Table 101. and memory reads by this thread can no longer be affected by other thread writes.gl} supported on all target architectures. A memory write (e.gl. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. A memory read (e. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar.gl} introduced in PTX .cta.gl. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys will typically have much longer latency than membar.level = { .

add. or.b]. .u64. and stores the result of the specified operation at location a. . Addresses are zero-extended to the specified width as needed.inc.type atom{. The address must be naturally aligned to a multiple of the access size. a de-referenced register areg containing a byte address.op. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. and max.u64 .space = { . overwriting the original value.type = { .u32 only .Chapter 8.dec.exch. . inc. The inc and dec operations return a result in the range [0. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. . and max operations are single-precision. xor.f32.cas.u32. . [a].exch to store to locations accessed by other atomic operations. .u32. . b. performs a reduction operation with operand b and the value in location a. .. .op. the access may proceed by silently masking off low-order address bits to achieve proper rounding. an address maps to global memory unless it falls within the local memory window or the shared memory window. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. i. by inserting barriers between normal stores and atomic operations to a common address.shared }. The floating-point operations are add. dec.b32. atom{. A register containing an address may be declared as a bit-size type or integer type. In generic addressing.and. .max }. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.add.e. atom. accesses to local memory are illegal. .s32. min. The integer operations are add.op = { .type d. . and exch (exchange).s32. If no state space is given.e. . cas (compare-and-swap).. 2010 135 . c.global. . .f32 }. or [immAddr] an immediate absolute byte address. For atom. Operand a specifies a location in the specified state space.space}.xor. January 24.or. and truncated if the register width exceeds the state space address width for the target architecture. 32-bit operations. The bit-size operations are and. . . If an address is not properly aligned. .s32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.b32.g.b64.min. . or the instruction may fault. min.u32. . .f32 Atomically loads the original value at location a into destination register d. max. .b32 only . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. d. perform the memory accesses using generic addressing. or by using atom. [a]. . Within these windows. the resulting behavior is undefined. The floating-point add. b. .b64 . an address maps to the corresponding location in local or shared memory. The address size may be either 32-bit or 64-bit. Instruction Set Table 102. e. Description // // // // // .space}. min. i.

0 Semantics atomic { d = *a.f32 atom. s) = s.PTX ISA Version 2. atom.exch} requires sm_12 or later. d. Use of generic addressing requires sm_20 or later.shared operations require sm_20 or later.global requires sm_11 or later. : r.{min. c) operation(*a. Release Notes Examples @p 136 January 24.f32 requires sm_20 or later. s) = (r > s) ? s exch(r.add.[a]. atom.add. 64-bit atom.0. : r-1.shared requires sm_12 or later. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.shared.t) = (r == s) ? t operation(*a.my_new_val.1. atom.0. s) = (r >= s) ? 0 dec(r.[x+4]. atom.max.cas. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.cas. d.f32. b).my_val.global.b32 d.global.[p].max} are unimplemented.{add.s.s32 atom. cas(r. Introduced in PTX ISA version 1. atom. b. 64-bit atom. 2010 . : r+1. *a = (operation == cas) ? : } where inc(r.

f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. The inc and dec operations return a result in the range [0. Addresses are zero-extended to the specified width as needed. Operand a specifies a location in the specified state space. red{.b32.op. Notes Operand a must reside in either the global or shared state space. The floating-point add. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. s) = (r >= s) ? 0 : r+1. .f32.add.u64 . . The address must be naturally aligned to a multiple of the access size. The address size may be either 32-bit or 64-bit. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. dec(r.max }. If an address is not properly aligned.exch to store to locations accessed by other reduction operations. i. dec. . an address maps to global memory unless it falls within the local memory window or the shared memory window. .or.and.min.g.. . .e. . max.op = { . The integer operations are add. .dec. s) = (r > s) ? s : r-1.Chapter 8. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.xor. For red. b). .s32. . and truncated if the register width exceeds the state space address width for the target architecture. 32-bit operations.inc.u32 only . and max. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. or [immAddr] an immediate absolute byte address.b]. A register containing an address may be declared as a bit-size type or integer type.s32. .add. the resulting behavior is undefined.space}.s32. b. Within these windows. i. January 24.u32.global..f32 }. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or by using atom. or the instruction may fault.type [a]. Instruction Set Table 103. If no state space is given. 2010 137 . by inserting barriers between normal stores and reduction operations to a common address.b64. min. and xor. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. min.f32 Performs a reduction operation with operand b and the value in location a. perform the memory accesses using generic addressing. an address maps to the corresponding location in local or shared memory. .shared }.u64. In generic addressing. a de-referenced register areg containing a byte address. . . .e. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. e. . where inc(r. or. and stores the result of the specified operation at location a. Semantics *a = operation(*a. red. The bit-size operations are and. .b32 only . Description // // // // . . . overwriting the original value. and max operations are single-precision. accesses to local memory are illegal.type = { .u32. min. .space = { . inc. The floating-point operations are add.u32.

1. red.s32 red.shared requires sm_12 or later.b32 [a]. 2010 . [x+4].max.2.0.f32 red.shared.shared operations require sm_20 or later. 64-bit red. red. Release Notes Examples @p 138 January 24.f32.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [p].my_val.global.and.{min.max} are unimplemented. Use of generic addressing requires sm_20 or later.add.global requires sm_11 or later red.global.PTX ISA Version 2.add requires sm_12 or later.add. red. red. 64-bit red.f32 requires sm_20 or later.

. . returns bitmask . {!}a. not across an entire CTA.mode.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.none. vote.all True if source predicate is True for all active threads in warp.pred d. Instruction Set Table 104.uni.ballot.ballot. where the bit position corresponds to the thread’s lane id.pred vote. // ‘ballot’ form.all. . vote requires sm_12 or later.q.all.ballot. The destination predicate value is the same across all threads in the warp.not_all.b32 p. Description Performs a reduction of the source predicate across threads in a warp. In the ‘ballot’ form.b32 requires sm_20 or later. Negating the source predicate also computes .uni True if source predicate has the same value in all active threads in warp.Chapter 8. vote.2. Negate the source predicate to compute . Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. The reduction modes are: . . Note that vote applies to threads in a single warp.any.p.q.mode = { .b32 d.pred vote. r1.uni }. p. vote. // get ‘ballot’ across warp January 24. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.any True if source predicate is True for some active thread in warp.ballot. 2010 139 . {!}a.uni. Negate the source predicate to compute . vote. vote.

c.secop d.atype. vop. The source and destination operands are all 32-bit registers.s32) is specified in the instruction type. . .9. Using the atype/btype and asel/bsel specifiers. atype. .sat}.7.atype. 2010 .bsel}. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. The sign of the intermediate result depends on dtype. with optional data merge vop. . 3. the input values are extracted and signor zero.atype = . or word values from its source operands.dtype. The primary operation is then performed to produce an .btype = { .min.dsel = . perform a scalar arithmetic operation to produce a signed 34-bit result.b0. . all combinations of dtype.atype.s34 intermediate result.secop = { . a{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.add.bsel}.b2. . c.u32. . b{. with optional secondary operation vop. .dsel.s33 values. b{.btype{.extended internally to .bsel}. extract and sign.dtype. 140 January 24. and btype are valid. 2.asel}. optionally clamp the result to the range of the destination type. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).bsel = { .s32 }. . Video Instructions All video instructions operate on 32-bit register operands. // 32-bit scalar operation.or zero-extend byte.0 8. 4. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. b{.sat} d.b3. to produce signed 33-bit input values. The general format of video instructions is as follows: // 32-bit scalar operation.btype{.sat} d.h1 }.h0.dtype = . .dtype.u32 or .PTX ISA Version 2.asel = .btype{. The type of each operand (. a{.asel}.b1. a{. .asel}. taking into account the subword destination size in the case of optional data merging.max }. half-word.

c). Instruction Set . tmp. . S8_MAX. . The sign of the c operand is based on dtype.b1. U8_MIN ). Bool sat.b0: return ((tmp & 0xff) case . S32_MIN ). January 24.h1: return ((tmp & 0xffff) << 16) case .s33 optMerge( Modifier dsel. tmp. S8_MIN ). U16_MAX. c). U16_MIN ).b0. . .b1: return ((tmp & 0xff) << 8) case . . default: return tmp. U32_MAX.s33 tmp. c).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp. Bool sign. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).h0: return ((tmp & 0xffff) case . c). 2010 141 .s33 tmp. .b2: return ((tmp & 0xff) << 16) case . Modifier dsel ) { if ( !sat ) return tmp. . tmp. tmp.min: return MIN(tmp. S16_MAX.b3: if ( sign ) return CLAMP( else return CLAMP( case .s33 optSaturate( . c).add: return tmp + c.max return MAX(tmp. switch ( dsel ) { case . c). U8_MAX. c). . S16_MIN ).b2.b3: return ((tmp & 0xff) << 24) default: return tmp.s33 c) { switch ( secop ) { . . .s33 c ) switch ( dsel ) { case . .Chapter 8. as shown in the following pseudocode. U32_MIN ).h0. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. The lower 32-bits are then written to the destination operand.s34 tmp.s33 optSecOp(Modifier secop. S32_MAX. } } .

b3.sat}. taking into account destination type and merge operations tmp = optSaturate( tmp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tb = partSelectSignExtend( b.sat.btype = { .sat} d.max }. . vsub vabsdiff vmin. r2.dtype.bsel}.dtype. vsub.sat vsub.dtype . and optional secondary arithmetic operation or subword data merge.b1. // optional secondary operation d = optMerge( dsel. vsub.s32.s32. . with optional data merge vop. .s32. r2.h1. r3.dsel .s32. atype.sat vabsdiff. { . r3. .bsel = { .h1. Perform scalar arithmetic operation with optional saturate. vsub. vmax Syntax Integer byte/half-word/word addition / subtraction. // 32-bit scalar operation. Semantics // saturate.add r1. // optional merge with c operand 142 January 24. btype. c. d = optSecondaryOp( op2.h1 }. tmp = MIN( ta.asel = .btype{. r3.s32 }.u32.dsel. .u32. . r2. . . vmax require sm_20 or later.h0.atype = . tmp = MAX( ta.s32. Video Instructions: vadd.s32. r3. vmin. bsel ). tmp. // extract byte/half-word/word and sign. tmp = | ta – tb |. // 32-bit scalar operation.asel}. b{. with optional secondary operation vop. vadd. c. b{. Integer byte/half-word/word minimum / maximum. . Integer byte/half-word/word absolute value of difference. c ). tmp.bsel}. sat. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.b0.or zero-extend based on source operand type ta = partSelectSignExtend( a. r1. a{.bsel}.PTX ISA Version 2. vabsdiff. c.h0. r2.s32. tb ).b0. c ).op2 d. a{. .btype{.btype{.0. a{. dsel ).dtype.s32. vmax }.min.s32. vop. vmin. vabsdiff.u32.atype.s32.sat} d. r1.atype. c.sat vmin. vadd.add. 2010 .vop . tmp = ta – tb.b0.h0.b2.0 Table 105.atype.b2. asel ). . vmax vadd.asel}. tb ). isSigned(dtype).asel}. b{. r1.op2 Description = = = = { vadd. vmin. vabsdiff.

// optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.bsel = { . .s32 }. vshl.clamp && tb > 32 ) tb = 32. b{. Signed shift fills with the sign bit.h1 }.u32{. if ( mode == . and optional secondary arithmetic operation or subword data merge. b{. a{. unsigned shift fills with zero. vop. . Left shift fills with zero. // 32-bit scalar operation. vshr }.sat}{.atype.max }.min.or zero-extend based on source operand type ta = partSelectSignExtend( a. // optional secondary operation d = optMerge( dsel. and optional secondary arithmetic operation or subword data merge. case vshr: tmp = ta >> tb.h0. .wrap ) tb = tb & 0x1f. .b1.vop .u32. { . r3. Video Instructions: vshl.u32. c. // default is . . sat. tmp.b2. 2010 143 .op2 Description = = = = = { vshl.Chapter 8. with optional secondary operation vop.u32. b{. r2. tb = partSelectSignExtend( b. asel ). r2.clamp . c ).sat}{.u32.clamp.asel}. . vshl.b3.wrap }.dtype .dtype. . vshr Syntax Integer byte/half-word/word left / right shift. .asel = . atype. with optional data merge vop. { .mode} d. vshr vshl.dtype. a{.bsel}.sat}{.s32.atype = { .mode} d. isSigned(dtype). .op2 d. r1. . . if ( mode == . vshr require sm_20 or later. c ). r3.asel}. bsel ).add. switch ( vop ) { case vshl: tmp = ta << tb.mode}.u32. c. .h1.wrap r1.atype.dsel .asel}.u32. a{. vshr: Shift a right by unsigned amount in b with optional saturate. vshl: Shift a left by unsigned amount in b with optional saturate. // 32-bit scalar operation.mode .bsel}. d = optSecondaryOp( op2.dsel. Semantics // extract byte/half-word/word and sign.bsel}. taking into account destination type and merge operations tmp = optSaturate( tmp.u32{. dsel ).dtype.0. tmp. } // saturate.u32 vshr. Instruction Set Table 106. January 24.atype.u32{.b0.

The “plus one” mode (. and scaling.scale = { .s32 }. The final result is unsigned if the intermediate result is unsigned and c is not negated. which is used in computing averages. internally this is represented as negation of the product (a*b). . PTX allows negation of either (a*b) or c.btype. .h0.bsel = { . otherwise.b3.po) computes (a*b) + c + 1. (a*b) is negated if and only if exactly one of a or b is negated. // 32-bit scalar operation vmad. c. final signed -(U32 * S32) + S32 // intermediate signed. . final signed (U32 * U32) . .b2. 144 January 24. Description Calculate (a*b) + c. 2010 . .sat}{.asel = .dtype = .btype = { . final signed (S32 * U32) + S32 // intermediate signed.atype = .h1 }. this result is sign-extended if the final result is signed. {-}a{. .b1.dtype.shr7.bsel}. final signed -(S32 * U32) + S32 // intermediate signed.po{. {-}b{.atype..S32 // intermediate signed. final signed (U32 * S32) . b{. and the operand negates.u32.po mode. “plus one” mode.btype{.S32 // intermediate signed.PTX ISA Version 2. final signed -(S32 * S32) + S32 // intermediate signed.atype.scale} d.dtype. final signed The intermediate result is optionally scaled via right-shift. final signed (S32 * U32) . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.scale} d.b0. Source operands may not be negated in . That is.0 Table 107. . final signed (S32 * S32) .sat}{. final signed (U32 * S32) + S32 // intermediate signed. Although PTX syntax allows separate negation of the a and b operands. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (S32 * S32) + S32 // intermediate signed.U32 // intermediate unsigned. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. vmad.asel}.asel}. . {-}c.bsel}. the intermediate result is signed. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. Depending on the sign of the a and b operands.S32 // intermediate signed.shr15 }. final unsigned -(U32 * U32) + S32 // intermediate signed. a{. The source operands support optional negation with some restrictions. Input c has the same sign as the intermediate result. with optional operand negates. . . and zero-extended otherwise.

r3. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else if ( a. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). r1.shr7: result = (tmp >> 7) & 0xffffffffffffffff. Instruction Set Semantics // extract byte/half-word/word and sign. else result = CLAMP(result. tmp = tmp + c128 + lsb. S32_MAX. vmad. lsb = 0.po ) { lsb = 1.shr15: result = (tmp >> 15) & 0xffffffffffffffff.s32. tb = partSelectSignExtend( b.negate.h0. } else if ( c. r1.negate ^ b.u32. } if ( . case .Chapter 8. asel ).u32. r0. tmp[127:0] = ta * tb.negate ^ b.u32. signedFinal = isSigned(atype) || isSigned(btype) || (a.negate) || c.u32. vmad requires sm_20 or later.sat ) { if (signedFinal) result = CLAMP(result. r2.s32. lsb = 1.shr15 r0. btype. if ( .negate ) { c = ~c. -r3. lsb = 1. r2.h0.negate ) { tmp = ~tmp. bsel ). U32_MAX.0. 2010 145 . U32_MIN).or zero-extend based on source operand type ta = partSelectSignExtend( a. switch( scale ) { case . S32_MIN). atype.sat vmad. January 24.

b1.btype = { . 146 January 24.b0. d = optSecondaryOp( op2.0.btype. . tb. tmp.atype.h1 }. with optional secondary operation vset.b2.le.max }. // optional secondary operation d = optMerge( dsel. . The intermediate result of the comparison is always unsigned.ne.b3. c ).eq.atype.asel}. btype.lt. // 32-bit scalar operation.s32. r3.bsel}.asel}.min. 2010 .atype . .atype. r2. .cmp. . with optional data merge vset. atype.h0.dsel.or zero-extend based on source operand type ta = partSelectSignExtend( a.op2 d. vset. vset requires sm_20 or later.cmp d. a{. tb = partSelectSignExtend( b. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp = compare( ta. Semantics // extract byte/half-word/word and sign.ge }. . . vset. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.0 Table 108. // 32-bit scalar operation.btype.bsel}. . Compare input values using specified comparison.u32.s32 }. b{.asel}. bsel ).lt vset. c.ne r1.u32. . .bsel = { . . { . . r1. tmp. cmp ) ? 1 : 0. r3.cmp . and therefore the c operand and final result are also unsigned.u32. asel ). b{.u32.btype. c ).bsel}. a{. r2.dsel .gt.PTX ISA Version 2.h1. c. a{. b{.add.asel = . . with optional secondary arithmetic operation or subword data merge.cmp d. { . . .op2 Description = = = = .

numbered 0 through 15. trap. trap. brkpt. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Notes PTX ISA Notes Target ISA Notes Examples Currently. @p pmevent 1.0. pmevent a. pmevent 7.0.Chapter 8.10. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. brkpt.4. trap Abort execution and generate an interrupt to the host CPU. The relationship between events and counters is programmed via API calls from the host. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Supported on all target architectures. Introduced in PTX ISA version 1. Table 110. brkpt Suspends execution Introduced in PTX ISA version 1. there are sixteen performance monitor events. Instruction Set 8. Triggers one of a fixed number of performance monitor events. Introduced in PTX ISA version 1. brkpt requires sm_11 or later. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Table 111.7. January 24. with index specified by immediate operand a. Supported on all target architectures. 2010 147 .

0 148 January 24.PTX ISA Version 2. 2010 .

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. 2010 149 . %lanemask_ge. %clock64 %pm0. read-only variables. %pm3 January 24. %lanemask_gt %clock. Special Registers PTX includes a number of predefined.Chapter 9. %lanemask_le. %lanemask_lt. …. which are visible as special registers and accessed through mov or cvt instructions.

x. Every thread in the CTA has a unique %tid. %ntid.u32 %tid. read-only special register initialized with the number of thread ids in each CTA dimension.y. The number of threads in each dimension are specified by the predefined special register %ntid. . The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.y < %ntid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.%ntid. %tid component values range from 0 through %ntid–1 in each CTA dimension.%tid.y == %tid.u16 %rh. %ntid.u32 %ntid.sreg .y 0 <= %tid.z == 0 in 1D CTAs. . the %tid value in unused dimensions is 0.z. %ntid.0. Supported on all target architectures.u32 %h2. CTA dimensions are non-zero.y.x.z == 1 in 2D CTAs. or 3D vector to match the CTA shape. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.x code Target ISA Notes Examples 150 January 24. %tid.PTX ISA Version 2.%tid.%ntid.x to %rh Target ISA Notes Examples // legacy PTX 1. Supported on all target architectures. The %tid special register contains a 1D. // thread id vector // thread id components A predefined.%r0. 2010 . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.sreg .u32.x.%h2.v4 .x.%tid.%h1. mov. %tid.v4. 2D.u32 %ntid. mov.x.u32 %tid.u16 %r2. read-only. . It is guaranteed that: 0 <= %tid.z).y * %ntid.z == 0 in 2D CTAs.0.u32 type in PTX 2. cvt.z == 1 in 1D CTAs. mad. the fourth element is unused and always returns zero.y == %ntid.u32 %r0. mov.sreg .z < %ntid. mov.u32 %h1.z PTX ISA Notes Introduced in PTX ISA version 1.y. %tid.u32 %r0.z.x.v4 .0. %ntid.u16 %rh. PTX ISA Notes Introduced in PTX ISA version 1.u32 type in PTX 2. // move tid. The total number of threads in a CTA is (%ntid. Redefined as . // compute unified thread id for 2D CTA mov.x * %ntid.%tid.x < %ntid.sreg . per-thread special register initialized with the thread identifier within the CTA.%tid.v4. // legacy PTX 1. %tid.x. . // zero-extend tid.x code accessing 16-bit component of %tid mov. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. Redefined as .z to %r2 Table 113.0.u32 %r1.x 0 <= %tid. The fourth element is unused and always returns zero.z.0 Table 112. // CTA shape vector // CTA dimensions A predefined.

sreg . Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. A predefined. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. but its value may change during execution.3. %warpid.u32 %nwarpid. %nwarpid. read-only special register that returns the thread’s lane within the warp.3. .sreg .g. read-only special register that returns the thread’s warp identifier. Supported on all target architectures. A predefined. The lane identifier ranges from zero to WARP_SZ-1.u32 %laneid. Table 115. Introduced in PTX ISA version 1.u32 %r. For this reason. Special Registers Table 114. mov.Chapter 9. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Introduced in PTX ISA version 2. e.u32 %warpid. PTX ISA Notes Target ISA Notes Examples Table 116. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. . mov. read-only special register that returns the maximum number of warp identifiers. Supported on all target architectures.u32 %r. %laneid. The warp identifier will be the same for all threads within a single warp.sreg . due to rescheduling of threads following preemption. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. January 24. mov. A predefined.u32 %r.0. Note that %warpid is volatile and returns the location of a thread at the moment when read. . Introduced in PTX ISA version 1. 2010 151 . %nwarpid requires sm_20 or later.

y 0 <= %ctaid.z PTX ISA Notes Introduced in PTX ISA version 1.%ctaid.z. 2D.u16 %r0. // legacy PTX 1.x. The fourth element is unused and always returns zero.y.x. %ctaid.y.u32 type in PTX 2.x < %nctaid. It is guaranteed that: 1 <= %nctaid.0. %rh.x code Target ISA Notes Examples 152 January 24.y < %nctaid.x. 2010 .x. // legacy PTX 1.u32 %ctaid.PTX ISA Version 2. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. . Redefined as . read-only special register initialized with the CTA identifier within the CTA grid. The fourth element is unused and always returns zero. // Grid shape vector // Grid dimensions A predefined. mov.u32 mov.0.u32 %nctaid. Supported on all target architectures. %rh.%nctaid.sreg .{x. . // CTA id vector // CTA id components A predefined.0.sreg .x.z} < 65.x code Target ISA Notes Examples Table 118.u32 %nctaid .%nctaid.v4 .z < %nctaid. It is guaranteed that: 0 <= %ctaid.x 0 <= %ctaid.v4 .v4. depending on the shape and rank of the CTA grid. The %nctaid special register contains a 3D grid shape vector. mov. Redefined as . Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. The %ctaid special register contains a 1D.0 Table 117.u16 %r0.u32 %ctaid. %ctaid.u32 mov.536 PTX ISA Notes Introduced in PTX ISA version 1. .sreg .z. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.y. Supported on all target architectures.0. with each element having a value of at least 1.%nctaid.%ctaid.u32 type in PTX 2. or 3D vector.v4. read-only special register initialized with the number of CTAs in each grid dimension.y.%nctaid.sreg . Each vector element value is >= 0 and < 65535.

repeated launches of programs may occur. PTX ISA Notes Target ISA Notes Examples Table 121. The SM identifier ranges from 0 to %nsmid-1.u32 %r.0.sreg . but its value may change during execution. %nsmid requires sm_20 or later. 2010 153 . Introduced in PTX ISA version 2. due to rescheduling of threads following preemption.sreg . mov. The SM identifier numbering is not guaranteed to be contiguous. Introduced in PTX ISA version 1. . read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Note that %smid is volatile and returns the location of a thread at the moment when read.g. Introduced in PTX ISA version 1. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. This variable provides the temporal grid launch number for this context. Special Registers Table 119. %smid. e.u32 %r. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. read-only special register initialized with the per-grid temporal grid identifier. read-only special register that returns the maximum number of SM identifiers. Supported on all target architectures. A predefined. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Notes PTX ISA Notes Target ISA Notes Examples Table 120.sreg .u32 %r. The SM identifier numbering is not guaranteed to be contiguous. // initialized at grid launch A predefined. %gridid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. PTX ISA Notes Target ISA Notes Examples January 24. During execution. Supported on all target architectures.3.u32 %gridid.u32 %smid.Chapter 9. mov. %nsmid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. . so %nsmid may be larger than the physical number of SMs in the device. A predefined. where each launch starts a grid-of-CTAs.0.u32 %nsmid. . mov.

A predefined. 2010 . Table 123.sreg . Introduced in PTX ISA version 2.u32 %r. mov. %lanemask_lt requires sm_20 or later.u32 %lanemask_eq. %lanemask_lt.0 Table 122. . . Introduced in PTX ISA version 2. %lanemask_eq requires sm_20 or later. mov. Table 124. 154 January 24.u32 %r. %lanemask_le.u32 %lanemask_lt. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.0.0.PTX ISA Version 2. A predefined. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.sreg . %lanemask_eq. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_le. %lanemask_le requires sm_20 or later. . A predefined.u32 %r. mov. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.0.

Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. Table 126. %lanemask_gt.0. 2010 155 . mov.u32 %lanemask_ge. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge.sreg . Introduced in PTX ISA version 2. %lanemask_ge requires sm_20 or later.u32 %r. Special Registers Table 125.sreg .Chapter 9. A predefined. A predefined. .u32 %lanemask_gt. . January 24.u32 %r. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Introduced in PTX ISA version 2.0. %lanemask_gt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.

Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. %pm2.PTX ISA Version 2. %pm2. mov. Table 128. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.u32 r1. 2010 .3. Their behavior is currently undefined. The lower 32-bits of %clock64 are identical to %clock. %pm1. read-only 64-bit unsigned cycle counter. read-only 32-bit unsigned cycle counter. mov. %pm3. Supported on all target architectures. mov. %clock64 requires sm_20 or later. . . %pm2. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.sreg .0 Table 127. %pm1.%clock64.0.u32 r1. Introduced in PTX ISA version 2. Special registers %pm0. Supported on all target architectures. Table 129. 156 January 24. Special Registers: %pm0. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. . %pm1.%clock.u64 %clock64. ….u32 %clock. and %pm3 are unsigned 32-bit read-only performance monitor counters.u64 r1.sreg .0.%pm0.sreg .u32 %pm0. Introduced in PTX ISA version 1. %pm3 %pm0. Introduced in PTX ISA version 1.

version . Duplicate . .4 January 24.version directives are allowed provided they match the original . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Directives 10.0 .Chapter 10. . Each ptx file must begin with a . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version directive.version major. 2010 157 .1. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. and the target architecture for which the code was generated.0.version directive.version . PTX File Directives: . minor are integers Specifies the PTX language version number. .version Syntax Description Semantics PTX version number. Supported on all target architectures.target Table 130.minor // major. Increments to the major number indicate incompatible changes to PTX.version 2.version 1.

. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.f64 instructions used.red}.global.f64 instructions used. sm_12. and an error is generated if an unsupported feature is used. Each PTX file must begin with a .texref and .0.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.texmode_unified . A program with multiple . brkpt instructions. 64-bit {atom. Description Specifies the set of features in the target architecture for which the current ptx code was generated. texmode_independent. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. PTX File Directives: . Introduced in PTX ISA version 1.PTX ISA Version 2. Therefore.texmode_independent texture and sampler information is bound together and accessed via a single . A . texture and sampler information is referenced with independent . texmode_unified. 2010 .texref descriptor. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. PTX features are checked against the specified target architecture.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. with only half being used by instructions converted from .red}.texmode_unified) . Texturing mode introduced in PTX ISA version 1. map_f64_to_f32 }. PTX code generated for a given target can be run on later generation devices. 158 January 24. where each generation adds new features and retains all features of previous generations.shared.f64 instructions used.samplerref descriptors.red}. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Adds double-precision support.version directive.f32. immediately followed by a . Target sm_20 Description Baseline feature set for sm_20 architecture.f64 to . The texturing mode is specified for an entire module and cannot be changed within the module. sm_10.target directive specifies a single target architecture. In general. Note that .target . generations of SM architectures follow an “onion layer” model. including expanded rounding modifiers.5. Supported on all target architectures. Adds {atom. vote instructions. Adds {atom. The following table summarizes the features in PTX that vary according to target architecture. Requires map_f64_to_f32 if any . Requires map_f64_to_f32 if any . but subsequent . Texturing mode: (default is . Requires map_f64_to_f32 if any . Disallows use of map_f64_to_f32.0 Table 131.global.target directive containing a target architecture and optional platform options. sm_11.target Syntax Architecture and Platform target.target directives can be used to change the set of target features allowed during parsing.f64 storage remains as 64-bits. sm_13.

2010 159 . Directives Examples .target sm_13 // supports double-precision .Chapter 10. texmode_independent January 24.target sm_10 // baseline target architecture .target sm_20.

0 10. . and query instructions and cannot be accessed via ld. PTX ISA Notes For PTX ISA version 1. . [z].param.2.PTX ISA Version 2.param . .surfref variables may be passed as parameters. ld.reg .g. These parameters can only be referenced by name within texture and surface load. and . etc.5 and later.entry .param . In addition to normal parameters.b32 %r<99>. %nctaid.entry filter ( . the kernel dimensions and properties are established and made available via special registers.b32 %r2. Parameters are passed via . 160 January 24. store. For PTX ISA versions 1.entry kernel-name kernel-body Defines a kernel entry point name. ld. %ntid. Semantics Specify the entry point for a kernel program. and body for the kernel function. .param space memory and are listed within an optional parenthesized parameter list. . Supported on all target architectures.b32 z ) Target ISA Notes Examples [x].param. parameter variables are declared in the kernel body.b32 y.param instructions. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.4 and later. The shape and size of the CTA executing the kernel are available in special registers.0 through 1. … } . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. .b32 %r1. with optional parameters. parameters. e.entry cta_fft . Kernel and Function Directives: . ld. [y].b32 x. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.b32 %r3. At kernel launch. opaque .4.samplerref.param { . parameter variables are declared in the kernel parameter list.param.entry kernel-name ( param-list ) kernel-body .func Table 132.0 through 1. Parameters may be referenced by name within the kernel body and loaded into registers using ld.entry Syntax Description Kernel entry point and body.texref. 2010 .param instructions.3.entry .

Directives Table 133.func (ret-param) fname (param-list) function-body Defines a function. parameters must be in the register state space.param and st.x code. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.0 with target sm_20 allows parameters in the . including input and return parameters and optional function body. . which may use a combination of registers and stack locations to pass parameters.func definition with no body provides a function prototype.func (.b32 rval) foo (. Parameters must be base types in either the register or parameter state space.func fname function-body .param instructions in the body.param state space.reg .func . PTX 2. foo.result.func fname (param-list) function-body . Supported on all target architectures. Parameter passing is call-by-value.reg . and recursion is illegal. .f64 dbl) { . The implementation of parameter passing is left to the optimizing translator. 2010 161 .b32 rval. dbl.reg . … use N.reg . Parameters in register state space may be referenced directly within instructions in the function body. Variadic functions are represented using ellipsis following the last fixed argument. Kernel and Function Directives: . Parameters in . Variadic functions are currently unimplemented.b32 N.2 for a description of variadic functions. … Description // return value in fooval January 24. if any. . other code.0. The parameter lists define locally-scoped variables in the function body.0 with target sm_20 supports at most one return value. A . val1).func Syntax Function definition.param space are accessed using ld. } … call (fooval). (val0.Chapter 10.b32 localVar. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and supports recursion. ret. PTX ISA 2. Release Notes For PTX ISA version 1. implements an ABI with stack. there is no stack. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. mov.

pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. . PTX supports the following directives.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).3.maxnreg. The interpretation of .minnctapersm directives may be applied per-entry and must appear between an .entry directive and its body.g. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. A general . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. The .maxntid directive specifies the maximum number of threads in a thread block (CTA).maxnreg directive specifies the maximum number of registers to be allocated to a single thread. 2010 . Currently. The directive passes a list of strings to the backend. 162 January 24.pragma directives may appear at module (file) scope. to throttle the resource requirements (e.minnctapersm . and the . which pass information to the backend optimizing compiler. at entry-scope. The directives take precedence over any module-level constraints passed to the optimizing backend. These can be used. the .maxntid and .pragma The .pragma directive is supported for passing information to the PTX backend. Note that .maxntid.0 10. and the strings have no semantics within the PTX virtual machine model. for example.PTX ISA Version 2. or as statements within a kernel or device function body. registers) to increase total thread count and provide a greater opportunity to hide memory latency. .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.maxnctapersm (deprecated) .maxnreg .maxntid . the . and .

maxntid 256 .Chapter 10. 2D. Introduced in PTX ISA version 1.maxntid Syntax Maximum number of threads in thread block (CTA).entry bar . Directives Table 134.maxntid 16. ny . Introduced in PTX ISA version 1.maxntid and .maxntid nx. ny.maxnreg .entry foo . Performance-Tuning Directives: . the backend may be able to compile to fewer registers. 2010 163 . The maximum number of threads is the product of the maximum extent in each dimension. .maxntid nx . Exceeding any of these limits results in a runtime error or kernel launch failure. The compiler guarantees that this limit will not be exceeded. nz Declare the maximum number of threads in the thread block (CTA). . .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. Supported on all target architectures. Supported on all target architectures.maxntid nx. The actual number of registers used may be less. for example. or 3D CTA.maxntid . This maximum is specified by giving the maximum extent of each dimention of the 1D.maxnreg n Declare the maximum number of registers per thread in a CTA. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.3. Performance-Tuning Directives: .3.16.maxctapersm. or the maximum number of registers may be further constrained by . .entry foo .

entry foo . Introduced in PTX ISA version 2.maxnctapersm.maxnctapersm (deprecated) . additional CTAs may be mapped to a single multiprocessor.minnctapersm generally need . Supported on all target architectures.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. if the number of registers used by the backend is sufficiently lower than this bound.0.minnctapersm 4 { … } 164 January 24. .0 Table 136.entry foo .maxntid and .maxntid to be specified as well. . For this reason. .maxnctapersm has been renamed to .0.PTX ISA Version 2. Optimizations based on . . Deprecated in PTX ISA version 2. 2010 . Introduced in PTX ISA version 1.maxntid to be specified as well.maxntid 256 . Performance-Tuning Directives: . .3. Optimizations based on .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0 as a replacement for .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.minnctapersm in PTX ISA version 2. The optimizing backend compiler uses .maxntid 256 . Performance-Tuning Directives: . Supported on all target architectures.maxnctapersm generally need .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). However.minnctapersm .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.

pragma . or at statementlevel. Performance-Tuning Directives: . . or statement-level directives to the PTX backend compiler. Pass module-scoped.pragma list-of-strings . at entry-scope. { … } January 24. Introduced in PTX ISA version 2. Directives Table 138.entry foo .pragma “nounroll”.pragma directive may occur at module-scope. The . The interpretation of . 2010 165 .pragma Syntax Description Pass directives to PTX backend compiler. .pragma “nounroll”.Chapter 10. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma directive strings is implementation-specific and has no impact on PTX semantics. See Appendix A for descriptions of the pragma strings defined in ptxas. entry-scoped. Supported on all target architectures.0.

byte 0x2b.byte 0x00.section directive. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. replaced by .section .4.264-1] .0 10. 0x5f736f63 .x code.0 but is supported for legacy PTX version 1.quad int64-list // comma-separated hexadecimal integers in range [0.debug_pubnames. @@DWARF dwarf-string dwarf-string may have one of the .4byte .0 and replaces the @@DWARF syntax. 0x63613031.232-1] . 0x00000364. 0x61395a5f.0. Table 139.loc The . 0x736d6172 .2. 0x6150736f.section .debug_info .section directive is new in PTX ISA verison 2. 0x00 . 0x00 166 January 24. 0x00. 0x00. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . Supported on all target architectures. @progbits .. 0x02. The @@DWARF syntax is deprecated as of PTX version 2. Deprecated as of PTX 2.4byte int32-list // comma-separated hexadecimal integers in range [0.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.byte byte-list // comma-separated hexadecimal byte values . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 2010 . Introduced in PTX ISA version 1. 0x00.4byte 0x000006b5.PTX ISA Version 2..file .4byte label . “”. 0x00. 0x00.4byte 0x6e69616d.

.b32 label .file . Debugging Directives: .loc . 0x736d6172 0x00 Table 141. 0x00. Debugging Directives: . .section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x6e69616d. 2010 167 . 0x00. 0x00.0.264-1] .debug_info . Supported on all target architectures.loc line_number January 24. .0.b32 int32-list // comma-separated list of integers in range [0. .section . 0x00. 0x63613031.section .b8 byte-list // comma-separated list of integers in range [0.b8 0x2b. } 0x02.232-1] . 0x5f736f63 0x6150736f. Directives Table 140. replaces @@DWARF syntax.255] .b32 0x000006b5. 0x00. 0x00 0x61395a5f. .b64 int64-list // comma-separated list of integers in range [0. Supported on all target architectures. 0x00000364.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.Chapter 10. .file filename Table 142.debug_pubnames { . .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x00. Supported on all target architectures..b32 ..b8 0x00. Source file information. .0. Source file location.section Syntax PTX section definition. Debugging Directives: .

extern .0.extern .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Linking Directives: .b32 foo.6.0. // foo is defined in another module Table 144.visible Table 143. Supported on all target architectures. Supported on all target architectures. . Linking Directives .global .extern .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.0 10. .visible identifier Declares identifier to be externally visible.PTX ISA Version 2. .visible .b32 foo. Linking Directives: . // foo will be externally visible 168 January 24.visible . Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.global . .extern identifier Declares identifier to be defined externally. 2010 .

The release history is as follows. CUDA Release CUDA 1. and the remaining sections provide a record of changes in previous releases.0 January 24.1 PTX ISA 1. 2010 169 .0 CUDA 2.0.4 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1.0 PTX ISA 1.3 driver r190 CUDA 3.3 PTX ISA 1.2 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.1 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 1.5 PTX ISA 2.2 CUDA 2.Chapter 11.1 CUDA 2.

while maximizing backward compatibility with legacy PTX 1. When code compiled for sm_1x is executed on sm_20 devices.f32.ftz modifier may be used to enforce backward compatibility with sm_1x.rn.1.x code and sm_1x targets.f32 require a rounding modifier for sm_20 targets.1. sub.f32 maps to fma. Single.PTX ISA Version 2.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. New Features 11. Both fma. Single-precision add. fma. • • • • • 170 January 24.f32 instruction also supports . and sqrt with IEEE 754 compliant rounding have been added.1.1. These are indicated by the use of a rounding modifier and require sm_20. Floating-Point Extensions This section describes the floating-point changes in PTX 2.0 for sm_20 targets. The mad.f32 requires sm_20.ftz and . Instructions testp and copysign have been added.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The fma. mad. The .0 11. A single-precision fused multiply-add (fma) instruction has been added. and mul now support . 2010 . rcp.f32 for sm_20 targets. Changes in Version 2.rp rounding modifiers for sm_20 targets.1. The mad.sat modifiers. The changes from PTX ISA 1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 and mad.0 11. The goal is to achieve IEEE 754 compliance wherever possible.rm and .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.1.and double-precision div.

has been added. has been added.pred have been added. prefetchu.arrive instruction has been added. New special registers %nsmid. for prefetching to specified level of memory hierarchy.1. A new directive. %clock64. and shared addresses to generic address and vice-versa has been added. have been added.u32 and bar.add.sys.minnctapersm to better match its behavior and usage.1. ldu. e. st.clamp modifiers.clamp and .Chapter 11. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.red}.zero. The bar instruction has been extended as follows: • • • A bar.or}. Instructions {atom.le. suld. Bit field extract and insert instructions. cvta.maxnctapersm directive was deprecated and replaced with . brev. January 24. ldu. membar. Surface instructions support additional . Instruction sust now supports formatted surface stores. prefetch.ge.2. has been added. 11. 2010 171 . The . and sust. A “find leading non-sign bit” instruction.red. . New instructions A “load uniform” instruction.{and.g. bar now supports optional thread count and register operands.popc.f32 have been implemented.b32. st. A “population count” instruction.3. A “count leading zeros” instruction. clz. Instruction cvta for converting global.lt. has been added. atom. has been added. vote. Instructions bar. Instructions {atom. has been added. %lanemask_{eq.shared have been extended to handle 64-bit data types for sm_20 targets. bfind. A “bit reversal” instruction. isspacep.section.1. . Video instructions (includes prmt) have been added. has been added. A system-level membar instruction. local. Release Notes 11. Cache operations have been added to instructions ld. bfe and bfi.gt} have been added. A “vote ballot” instruction. Other new features Instructions ld.1. popc.red}.ballot. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. and red now support generic addressing.red. Instructions prefetch and prefetchu have also been added.

cvt.p. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.PTX ISA Version 2. Instruction bra.{u32.f32.s32. where . the correct number is sixteen.p sust. 11. 2010 .max} are not implemented.u32. Support for variadic functions and alloca are unimplemented. .4 or earlier. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.5.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. call suld.1.5 and later. Formatted surface load is unimplemented. See individual instruction descriptions for details.target sm_1x. stack-based ABI is unimplemented. or . The underlying.f32} atom.ftz (and cvt for . has been fixed.f32 type is unimplemented. Semantic Changes and Clarifications The errata in cvt.1. if . The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. 172 January 24.s32.4 and earlier.{min.red}. {atom.2.ftz for PTX ISA versions 1.3.version is 1. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. In PTX version 1. To maintain compatibility with legacy PTX code.0 11. Formatted surface store with .

func bar (…) { … L1_head: . .pragma “nounroll”. Supported only for sm_20 targets. entry-function. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. L1_body: … L1_continue: bra L1_head. The “nounroll” pragma is allowed at module.Appendix A. and statement levels. Ignored for sm_1x targets. including loops preceding the . disables unrolling for all loops in the entry function body. 2010 173 . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. . Note that in order to have the desired effect at statement level.pragma “nounroll”.pragma “nounroll”. { … } // do not unroll any loop in this function . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.0. Descriptions of . Table 145.entry foo (…) . L1_end: … } // do not unroll this loop January 24. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. … @p bra L1_end. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma. disables unrolling of0 the loop for which the current block is the loop header. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.pragma Strings This section describes the .pragma strings defined by ptxas.

PTX ISA Version 2.0 174 January 24. 2010 .

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