NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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................................................................ Chapter 6............ 49 7...... 5..................5..... 6................... 6......4. Arrays........................ Type Conversion................. 37 Variable Declarations ....... 6........................... 38 Alignment ................................. 41 Using Addresses................ 44 Rounding Modifiers .........................6. 27 5..... 42 Addresses as Operands ..................... 47 Chapter 7............................1................... 33 Restricted Use of Sub-Word Sizes ............1................................................................. 6..........2.......................1..PTX ISA Version 2............ Function declarations and definitions .............. 5.................................................. 6................................. 41 6................. Texture................................................... Abstracting the ABI ..................4... 34 Variables ...2.......................................................... 5............................4.......... 49 ii January 24......................2....................... Types ........ 39 Parameterized Variable Names .... and Variables ...1.................. Operand Type Information .............. 32 Texture State Space (deprecated) ..1.......................1...................4..... and Surface Types ...................................................... 39 5.....1................4.................................................................................1...................0 4....5...8............... 5........................................................................... 27 Register State Space .......................................... 5................. 29 Parameter State Space ............................................................................................................................................................................................................................................. State Spaces .................4.... 6.........................................2................1........1..................................................4..... 5........... 5......................... 37 Vectors ......................... and Vectors .............................................................................................................................................. 29 Global State Space ...... 5.....5........................ 5.................................................4........................................... 6................................ State Spaces......... Sampler.........................................................................................................................5............1............................... 41 Source Operands............2.4............... 5......................2.....4............................................................ 6....4.......... 5.....3.......................... 5.................................. 5...................................... 43 Vectors as Operands ................. Instruction Operands..................................................3..... Summary of Constant Expression Evaluation Rules .............................................6............. 41 Destination Operands ......................................................... 43 Labels and Function Names as Operands .................. 32 5..............3...5..................... 46 6............ 42 Arrays as Operands .......1.................... 37 Array Declarations ........... 2010 .. 29 Local State Space ...............2........................4................................. 38 Initializers ...................2.......1.......................... 30 Shared State Space............................................................... 5........... 6.............................. 43 6...... Operand Costs ................................... 5......................................................................................... 28 Special Register State Space ................................................... 5......................3..1.............................................................1.............6.......... 33 Fundamental Types ..........................4. 25 Chapter 5.......................................................... 44 Scalar Conversions ................6..............................5.................................... 33 5.......................... 28 Constant State Space .................. Types.........2...................1.............4....3......7...............................4.........

.....................1......................... 122 Control Flow Instructions ........................... 8...4................ 2010 iii ......................................................................................x ... 57 Manipulating Predicates .........................3..........................................1.....................................................6.................................2................................... 11.............7...........7....... 8............................ 8............................5..................................................................................................3......... 55 Predicated Execution .. 8..1......... 149 Chapter 10...........................6.......................... 8................................2......... PTX Version and Target Directives ........................4..........................................0 ........... 168 Chapter 11......................7.............1....10................. Changes from PTX 1................3............................... 140 Miscellaneous Instructions.. Release Notes .......... 8...7..................8............. 8............. 53 Alloca ........................... 10............ 8.....................................................1...................................................................................................................................... 62 Semantics ..................................................... 7...... Chapter 9............... Type Information for Instructions and Operands ...7.................................................................................................. 60 8...6.... Divergence of Threads in Control Constructs ................1.1............... Instruction Set ....5...................1..... 59 Operand Size Exceeding Instruction-Type Size ............................ 55 8................. 8.............................. 157 Specifying Kernel Entry Points and Functions ......... 81 Comparison and Selection Instructions .......................................................................................... 169 11..7.................7... 8..................... 7.......................................................................... 8................................................. 166 Linking Directives .............................7........................4.............. 162 Debugging Directives ..................3.. Directives ....... 108 Texture and Surface Instructions ...............................................9.....1............................. 10..1........................................1.......... 52 Variadic functions ..... 8.................... 55 PTX Instructions .....................................................................6...................... 104 Data Movement and Conversion Instructions ................... 8...... 10........ 8............................................................................... 170 Semantic Changes and Clarifications ..........................................1..................... 62 8.................................................... 129 Parallel Synchronization and Communication Instructions .................................................. 100 Logic and Shift Instructions ............................3........................................... 160 Performance-Tuning Directives ...... Special Registers ........... 54 Chapter 8..... Changes in Version 2.................7........................4....... 8.........................7.....................2............................3.... 11.. 172 January 24.................................... Format and Semantics of Instruction Descriptions ..... 56 Comparisons ................................................................................................................7........................................................................2...................... 8.............3...2............................... 170 New Features ............................... 63 Integer Arithmetic Instructions ....... 157 10........................... Instructions . 10........1.......... 147 8............................................................ 132 Video Instructions .7......................... 11. 62 Machine-Specific Semantics of 16-bit Code ........................................ 58 8.............................. 63 Floating-Point Instructions ........7.......................2...... 172 Unimplemented Features Remaining ...................................

.........0 Appendix A................ 173 iv January 24..................pragma Strings.PTX ISA Version 2.............. 2010 ......... Descriptions of .

...................... Table 27.. 2010 v .......................... 61 Integer Arithmetic Instructions: add ......................................... 46 Integer Rounding Modifiers ......... 28 Fundamental Type Specifiers ................................... and Bit-Size Types ............ Table 31....................................... Table 26................................................................. 67 Integer Arithmetic Instructions: mad ..... 33 Opaque Type Fields in Unified Texture Mode ....................................................... Table 32......................... Table 13.................. 59 Relaxed Type-checking Rules for Source Operands ......... 23 Constant Expression Evaluation Rules ...... PTX Directives ............ 65 Integer Arithmetic Instructions: addc . Table 23................................ 47 Operators for Signed Integer................ 58 Type Checking Rules ............................................. 68 Integer Arithmetic Instructions: mul24 .............. Table 4.......................................... Table 2................. Unsigned Integer................................................................................................................................................................. Table 6................ 35 Convert Instruction Precision and Format ................................................................ Table 28............................. 35 Opaque Type Fields in Independent Texture Mode .............cc .. 71 January 24......................................... Table 17.. Table 30............................................... Table 7.......... Table 20........ 69 Integer Arithmetic Instructions: mad24 .......... Table 12................................................. Table 29.......................... Table 15......... Table 9......................................................................................................cc ................... 57 Floating-Point Comparison Operators ....................................................... Table 25................................. Table 18... 70 Integer Arithmetic Instructions: sad ................................................................. Table 11................ 66 Integer Arithmetic Instructions: subc .......................................................................................................................................................................... 58 Floating-Point Comparison Operators Testing for NaN ........................................... 64 Integer Arithmetic Instructions: add................ 18 Reserved Instruction Keywords .........................................................................List of Tables Table 1..................................................................................... 66 Integer Arithmetic Instructions: mul .............................. 20 Operator Precedence . 64 Integer Arithmetic Instructions: sub ............................................................................... 25 State Spaces ...................... Table 3............................................. Table 21......................... Table 5......... Table 19.......................................... Table 16........................ 60 Relaxed Type-checking Rules for Destination Operands..... 19 Predefined Identifiers ........ 65 Integer Arithmetic Instructions: sub...................................................................................................................................................................... 46 Cost Estimates for Accessing State-Spaces .... Table 24......................... 45 Floating-Point Rounding Modifiers ........... Table 8.. 57 Floating-Point Comparison Operators Accepting NaN ............................................................................................ Table 10............. 27 Properties of State Spaces . Table 14.. Table 22.........

................ Table 38........................................................................ 101 Comparison and Selection Instructions: setp .......... 71 Integer Arithmetic Instructions: rem ................................. 96 Floating-Point Instructions: cos .................. Table 64................................ 86 Floating-Point Instructions: fma ............ 91 Floating-Point Instructions: neg ....................................................... 77 Integer Arithmetic Instructions: bfi ... 71 Integer Arithmetic Instructions: abs ................. 78 Integer Arithmetic Instructions: prmt ......................................................................................... 102 Comparison and Selection Instructions: selp .. Table 44................ Table 57...... Integer Arithmetic Instructions: div ..................... Table 39.................................................................................................. 82 Floating-Point Instructions: testp ................. Table 50.. 98 Floating-Point Instructions: ex2 ...................... 87 Floating-Point Instructions: mad ........... Table 35........................................................................................ Table 61.......................................... Table 45........ 92 Floating-Point Instructions: max ......0 Table 33........................................... Table 60.............................. Table 52................................................... 103 vi January 24.................... 97 Floating-Point Instructions: lg2 . 73 Integer Arithmetic Instructions: popc ............................................ Table 36............................................................... Table 63...................... Table 67............................................................................... Table 55.... Table 62.. Table 46..................................... 84 Floating-Point Instructions: sub .. 91 Floating-Point Instructions: min .............................. 95 Floating-Point Instructions: sin ............... 75 Integer Arithmetic Instructions: brev ..................................................................... Table 69..................................................................................................PTX ISA Version 2.. 72 Integer Arithmetic Instructions: neg ........................................ 103 Comparison and Selection Instructions: slct ................................ 83 Floating-Point Instructions: add .. 74 Integer Arithmetic Instructions: clz ....................................................................................................... 85 Floating-Point Instructions: mul ................................................................. 94 Floating-Point Instructions: rsqrt .... Table 49................................................................................... 74 Integer Arithmetic Instructions: bfind .............................. Table 47............... Table 48.......... Table 56......................................................... 92 Floating-Point Instructions: rcp .................... Table 68.................................. 88 Floating-Point Instructions: div .......... Table 34.................................. Table 59............................... 73 Integer Arithmetic Instructions: max ................................................................................................................................ Table 42.......................................................... 72 Integer Arithmetic Instructions: min ................................................. Table 41............................................................................................ Table 66........... Table 54............................... 79 Summary of Floating-Point Instructions .............. 2010 .............. Table 40......................... Table 58.. 83 Floating-Point Instructions: copysign ....................... 99 Comparison and Selection Instructions: set ................................................ Table 51..... Table 43.............................................. 93 Floating-Point Instructions: sqrt ................. Table 65................................................................................................................................................................................................. Table 53...................................................................................................................................................... 76 Integer Arithmetic Instructions: bfe .................. Table 37......... 90 Floating-Point Instructions: abs .

. Table 91....................................................................................................................................................... 112 Data Movement and Conversion Instructions: ld .............................. 109 Cache Operators for Memory Store Instructions ............ vsub........................................... vabsdiff..................................................................... 106 Logic and Shift Instructions: not ................... 2010 vii ......................................................... 131 Control Flow Instructions: exit ......... Table 98............... Table 101...................................... Table 86.. Table 80............... Table 83.................................................... Table 105..... 111 Data Movement and Conversion Instructions: mov ... vshr .......... 139 Video Instructions: vadd.......... vmin..................................................................................................................... Table 88....................................... 105 Logic and Shift Instructions: or ............... 106 Logic and Shift Instructions: shl .................................................................................. Table 89...................... 107 Logic and Shift Instructions: shr . Table 99.. 142 Video Instructions: vshl.... Table 72................................................ 107 Cache Operators for Memory Load Instructions ................................................... Table 79. Table 84............... Table 102........................................... Table 78............... 131 Parallel Synchronization and Communication Instructions: bar .......... Table 71.................. Table 104..... 133 Parallel Synchronization and Communication Instructions: membar ................................. 110 Data Movement and Conversion Instructions: mov ...... 128 Control Flow Instructions: { } .................... Table 73................... 124 Texture and Surface Instructions: suld .................................... 129 Control Flow Instructions: bra ............................................................. 119 Data Movement and Conversion Instructions: cvt ... Table 77........... Table 85............................................................................................................... 127 Texture and Surface Instructions: suq .................. 120 Texture and Surface Instructions: tex ......... prefetchu . 125 Texture and Surface Instructions: sust .................................. 118 Data Movement and Conversion Instructions: isspacep ............................................. Table 106........... Table 87.................................................................... 116 Data Movement and Conversion Instructions: prefetch.............. 143 January 24. Table 74....... 115 Data Movement and Conversion Instructions: st ........................... 135 Parallel Synchronization and Communication Instructions: red .. 130 Control Flow Instructions: ret .................. 134 Parallel Synchronization and Communication Instructions: atom .............. 123 Texture and Surface Instructions: txq ... 130 Control Flow Instructions: call ...................... Table 76. Table 95.................................................................................................. Table 81........... Table 97................................................................................................................................ 129 Control Flow Instructions: @ ... 113 Data Movement and Conversion Instructions: ldu .... Table 92.......... Logic and Shift Instructions: and .................. 126 Texture and Surface Instructions: sured.............................................................................. Table 100.......... vmax ............Table 70..................... Table 103......................................................... Table 90...... 106 Logic and Shift Instructions: cnot ....................................... Table 82....................... Table 96........................ 119 Data Movement and Conversion Instructions: cvta ............. 105 Logic and Shift Instructions: xor .... Table 94....................... Table 75............ Table 93... 137 Parallel Synchronization and Communication Instructions: vote ........

... 2010 ............................................................................ Table 135........................... Table 123. 150 Special Registers: %laneid ...................................... 168 viii January 24........................................... Table 110........................... Table 131... 152 Special Registers: %nctaid ......... 167 Linking Directives: .. 165 Debugging Directives: @@DWARF ............................................................................................... Table 118................... Video Instructions: vmad ............... 156 Special Registers: %clock64 ... 153 Special Registers: %lanemask_eq ..........loc ...........................................................target ................................................................................................................................ Table 141.... Table 112................ 157 PTX File Directives: ........................................ 160 Kernel and Function Directives: ............. 150 Special Registers: %ntid ............................... 144 Video Instructions: vset......... 164 Performance-Tuning Directives: ........................0 Table 107......................maxnreg ......... 147 Miscellaneous Instructions: pmevent......... 154 Special Registers: %lanemask_le .......... 151 Special Registers: %warpid ......maxnctapersm (deprecated) ........................ Table 119...... Table 111................................................ 167 Debugging Directives: ................................................................................................................................... 152 Special Registers: %smid ......................................................................version....................................................................................... 166 Debugging Directives: .minnctapersm ...................................... Table 122.................. Table 124..................................................... 158 Kernel and Function Directives: .............................. 156 Special Registers: %pm0.. 167 Debugging Directives: ........ Table 117..................................................................... Table 128........................... 161 Performance-Tuning Directives: .................................................................. 163 Performance-Tuning Directives: .......................................................................... Table 116................................................................................................................ Table 142........... Table 115........ %pm3 ... 146 Miscellaneous Instructions: trap ...... 154 Special Registers: %lanemask_ge .................................func ............................ %pm1...................................... 151 Special Registers: %nwarpid ....................... 156 PTX File Directives: . 147 Special Registers: %tid ................... Table 143........ Table 139......................................................................................... 163 Performance-Tuning Directives: ................................................. Table 121................... 164 Performance-Tuning Directives: ....................... Table 130................ Table 127................extern............ Table 134............... 154 Special Registers: %lanemask_lt ..... 155 Special Registers: %clock ......maxntid ..... 153 Special Registers: %nsmid ................................................................. Table 120.........PTX ISA Version 2.......... Table 129.......... Table 114................................................................. Table 125........................................pragma ...... %pm2....................... Table 113.......... Table 138...... Table 140..................................... Table 109.. Table 108................ Table 137......................................... Table 136................................... Table 133. Table 126................................................. 155 Special Registers: %lanemask_gt ....................................... 151 Special Registers: %ctaid ...............entry........................ 153 Special Registers: %gridid ........................................................ 147 Miscellaneous Instructions: brkpt ...........................................file ............... Table 132..................section .........................................................

......visible.... 168 Pragma Strings: “nounroll” ..................................Table 144. Linking Directives: . 173 January 24.. 2010 ix .................................................................... Table 145.......................................................

2010 .PTX ISA Version 2.0 x January 24.

1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). high-definition 3D graphics. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Introduction This document describes PTX. PTX defines a virtual machine and ISA for general purpose parallel thread execution. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.Chapter 1. image scaling. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. the programmable GPU has evolved into a highly parallel. stereo vision. PTX programs are translated at install time to the target hardware instruction set. and pattern recognition can map image blocks and pixels to parallel processing threads. 2010 1 . image and media processing applications such as post-processing of rendered images. the memory access latency can be hidden with calculations instead of big data caches. and because it is executed on many data elements and has high arithmetic intensity.1. PTX exposes the GPU as a data-parallel computing device. which are optimized for and translated to native target-architecture instructions. video encoding and decoding. there is a lower requirement for sophisticated flow control. from general signal processing or physics simulation to computational finance or computational biology. In fact. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Because the same program is executed for each data element. January 24. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Similarly. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. multithreaded. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. 1.2. Data-parallel processing maps data elements to parallel processing threads. many-core processor with tremendous computational horsepower and very high memory bandwidth.

1. The changes from PTX ISA 1.x features are supported on the new sm_20 target.rm and . Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. which map PTX to specific target machines.3. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. PTX ISA Version 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 for sm_20 targets.f32 and mad. including integer.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.rp rounding modifiers for sm_20 targets.0 PTX ISA Version 2.f32 instruction also supports .0 is a superset of PTX 1. • • • 2 January 24. When code compiled for sm_1x is executed on sm_20 devices.f32 requires sm_20. The main areas of change in PTX 2.ftz and . fma. and mul now support . Instructions marked with .sat modifiers.ftz) modifier may be used to enforce backward compatibility with sm_1x.x code will continue to run on sm_1x targets as well. Facilitate hand-coding of libraries. A “flush-to-zero” (.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. memory. performance kernels.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.f32 maps to fma. The mad.f32 require a rounding modifier for sm_20 targets. Provide a machine-independent ISA for C/C++ and other compilers to target. 2010 . Improved Floating-Point Support A main area of change in PTX 2.PTX ISA Version 2. addition of generic addressing to facilitate the use of general-purpose pointers. and video instructions. Most of the new features require a sm_20 target. and architecture tests. barrier. and all PTX 1.0 is in improved support for the IEEE 754 floating-point standard. surface.f32. 1. Provide a common source-level ISA for optimizing code generators and translators.0 are improved support for IEEE 754 floating-point operations.1. sub. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. The mad. Single-precision add. and the introduction of many new instructions.3. Achieve performance in compiled applications comparable to native GPU performance.x. mad. Both fma. Provide a code distribution ISA for application and middleware developers.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added. atomic. PTX 2. The fma.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Legacy PTX 1. reduction.rn.

i. these changes bring PTX 2. rcp. instructions ld. st. and sqrt with IEEE 754 compliant rounding have been added. atom. st. Introduction • Single.zero. In PTX 2.g. allowing memory instructions to access these spaces without needing to specify the state space.e. and directives are introduced in PTX 2. Surface Instructions • • Instruction sust now supports formatted surface stores. special registers. e.and double-precision div. and red now support generic addressing.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.0. Generic Addressing Another major change is the addition of generic addressing. A new cvta instruction has been added to convert global.2.clamp and . January 24. PTX 2.. and shared addresses to generic addresses.0. and shared addresses to generic address and vice-versa has been added.3. and vice versa.Chapter 1. Instruction cvta for converting global. and shared state spaces. and sust. Generic addressing unifies the global. so recursion is not yet supported. ldu.3. 1. isspacep. New Instructions The following new instructions. . for prefetching to specified level of memory hierarchy. Instructions testp and copysign have been added. prefetchu. NOTE: The current version of PTX does not implement the underlying.3. 2010 3 . local. local.0 closer to full compliance with the IEEE 754 standard. and Application Binary Interface (ABI). • Taken as a whole. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. cvta. stack layout. Support for an Application Binary Interface Rather than expose details of a particular calling convention.3.4. These are indicated by the use of a rounding modifier and require sm_20. Instructions prefetch and prefetchu have been added. 1. 1. an address that is the same across all threads in a warp. stack-based ABI. local. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. prefetch. Cache operations have been added to instructions ld. Surface instructions support additional clamp modifiers. suld.

red}. Instructions bar.lt. %lanemask_{eq. A new directive. bfi bit field extract and insert popc clz Atomic.sys. bar now supports an optional thread count and register operands.red}.ge. %clock64. A “vote ballot” instruction. has been added.le. Reduction.PTX ISA Version 2. and Vote Instructions • • • New atomic and reduction instructions {atom. New special registers %nsmid. Other Extensions • • • Video instructions (includes prmt) have been added.gt} have been added.red.popc.arrive instruction has been added.f32 have been added.b32.pred have been added.u32 and bar. has been added. membar.{and.ballot.section. . Instructions {atom. A bar. Barrier Instructions • • A system-level membar instruction.add.shared have been extended to handle 64-bit data types for sm_20 targets. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. 4 January 24. vote.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. 2010 .red.or}.

4. Chapter 4 describes the basic syntax of the PTX language. types. Chapter 7 describes the function and call syntax. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 11 provides release notes for PTX Version 2. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 9 lists special registers. Introduction 1.0. and variable declarations. Chapter 8 describes the instruction set.Chapter 1. Chapter 5 describes state spaces. Chapter 10 lists the assembly directives supported in PTX. calling convention. and PTX support for abstracting the Application Binary Interface (ABI). January 24. 2010 5 . Chapter 6 describes instruction operands.

PTX ISA Version 2. 2010 .0 6 January 24.

Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.2. To that effect. compute-intensive portions of applications running on the host are off-loaded onto the device. or 3D shape specified by a three-element vector ntid (with elements ntid. and ntid. and select work to perform. assign specific input and output positions. 2. data-parallel. The thread identifier is a three-element vector tid. and tid. can be isolated into a kernel function that is executed on the GPU as many different threads. Each thread has a unique thread identifier within the CTA. Programs use a data parallel decomposition to partition inputs. compute addresses. 2D.1. 2010 7 . 2D. tid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. (with elements tid.y.1. or CTA. or 3D CTA.y. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. Each CTA thread uses its thread identifier to determine its assigned role. 2. The vector ntid specifies the number of threads in each CTA dimension. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. is an array of threads that execute a kernel concurrently or in parallel. Threads within a CTA can communicate with each other. but independently on different data. work.x.2. Each CTA has a 1D. a portion of an application that is executed many times. January 24. ntid. Programming Model 2. To coordinate the communication of the threads within the CTA. It operates as a coprocessor to the main CPU. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. A cooperative thread array.z) that specifies the thread’s position within a 1D.x. More precisely. Cooperative thread arrays (CTAs) implement CUDA thread blocks. and results across the threads of the CTA.z).Chapter 2. or host: In other words. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.

Each grid also has a unique temporal grid identifier (gridid).2. so PTX includes a run-time immediate constant. a warp has 32 threads. CTAs that execute the same kernel can be batched together into a grid of CTAs. The warp size is a machine-dependent constant. 2D .2. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). 2010 . %ctaid.0 Threads within a CTA execute in SIMT (single-instruction. 8 January 24. Threads within a warp are sequentially numbered. such that the threads execute the same instructions at the same time. This comes at the expense of reduced thread communication and synchronization.PTX ISA Version 2. The host issues a succession of kernel invocations to the device. Each grid of CTAs has a 1D. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. WARP_SZ. Threads may read and use these values through predefined. because threads in different CTAs cannot communicate and synchronize with each other. Some applications may be able to maximize performance with knowledge of the warp size. or sequentially. 2. Typically. Multiple CTAs may execute concurrently and in parallel. depending on the platform. %ntid. read-only special registers %tid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. A warp is a maximal subset of threads from a single CTA. and %gridid. %nctaid. However. which may be used in any instruction where an immediate operand is allowed. or 3D shape specified by the parameter nctaid. so that the total number of threads that can be launched in a single kernel invocation is very large. multiple-thread) fashion in groups called warps.

0) CTA (1. Thread Batching January 24. 1) Thread (0. 0) Thread (3. 1) CTA (2. 1) Thread (4. 2) Thread (3. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2) Thread (1. 2010 9 .Chapter 2. 0) Thread (2. 1) Thread (2. 0) Thread (4. 1) Thread (3. 2) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. Figure 1. 1) Thread (0. 0) CTA (0. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (1. 0) CTA (2. 1) Thread (1. 1) CTA (1. 2) Thread (4. A grid is a set of CTAs that execute independently. 0) Thread (0.

0 2. respectively. Finally. for more efficient transfer. 2010 . constant. as well as data filtering. The device memory may be mapped and read or written by the host.3. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. all threads have access to the same global memory. Each thread has a private local memory. Both the host and the device maintain their own local memory. for some specific data formats. referred to as host memory and device memory. and texture memory spaces are optimized for different memory usages. and texture memory spaces are persistent across kernel launches by the same application. 10 January 24. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. or. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Texture memory also offers different addressing modes. constant. The global. The global. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.PTX ISA Version 2.

0) Block (1. 0) Block (0. Memory Hierarchy January 24. 2) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (0. 0) Block (2. 1) Block (1. 1) Grid 1 Global memory Block (0. 2) Figure 2. 1) Block (1. 1) Block (2. 0) Block (1.Chapter 2. 2010 11 .

PTX ISA Version 2. 2010 .0 12 January 24.

To manage hundreds of threads running several different programs. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). The multiprocessor maps each thread to one scalar processor core. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. the multiprocessor employs a new architecture we call SIMT (single-instruction. It implements a single-instruction barrier synchronization. schedules. it splits them into warps that get scheduled by the SIMT unit. The multiprocessor SIMT unit creates. disabling threads that are not on that path. and executes concurrent threads in hardware with zero scheduling overhead. January 24. allowing. a voxel in a volume.Chapter 3. When a host program invokes a kernel grid. the warp serially executes each branch path taken. and when all paths complete.1. If threads of a warp diverge via a data-dependent conditional branch. different warps execute independently regardless of whether they are executing common or disjointed code paths. increasing thread IDs with the first warp containing thread 0. A multiprocessor consists of multiple Scalar Processor (SP) cores.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. and executes threads in groups of parallel threads called warps. Branch divergence occurs only within a warp. A warp executes one common instruction at a time. At every instruction issue time. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. each warp contains threads of consecutive. a multithreaded instruction unit. a cell in a grid-based computation). and on-chip shared memory. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. As thread blocks terminate. for example. manages. multiple-thread). and each scalar thread executes independently with its own instruction address and register state. (This term originates from weaving. Parallel Thread Execution Machine Model 3. so full efficiency is realized when all threads of a warp agree on their execution path. The threads of a thread block execute concurrently on one multiprocessor. manages. The multiprocessor creates. new blocks are launched on the vacated multiprocessors. 2010 13 . the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. When a multiprocessor is given one or more thread blocks to execute. the threads converge back to the same execution path. the first parallel thread technology. The way a block is split into warps is always the same.

In practice. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A multiprocessor can execute as many as eight thread blocks concurrently.0 SIMT architecture is akin to SIMD (Single Instruction. SIMT enables programmers to write thread-level parallel code for independent. require the software to coalesce loads into vectors and manage divergence manually. on the other hand. the number of serialized writes that occur to that location and the order in which they occur is undefined. If an atomic instruction executed by a warp reads. which is a read-only region of device memory. and writes to the same location in global memory for more than one of the threads of the warp. the programmer can essentially ignore the SIMT behavior. as well as data-parallel code for coordinated threads. but one of the writes is guaranteed to succeed. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. • The local and global memory spaces are read-write regions of device memory and are not cached. modify. modifies. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. each read. the kernel will fail to launch. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. scalar threads. As illustrated by Figure 3. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. If there are not enough registers or shared memory available per multiprocessor to process at least one block. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. A key difference is that SIMD vector organizations expose the SIMD width to the software. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. however. For the purposes of correctness. In contrast with SIMD vector machines. 2010 . write to that location occurs and they are all serialized. which is a read-only region of device memory. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. but the order in which they occur is undefined. whereas SIMT instructions specify the execution and branching behavior of a single thread. 14 January 24.PTX ISA Version 2. Vector architectures.

2010 15 . Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.Chapter 3.

2010 .PTX ISA Version 2.0 16 January 24.

The following are common preprocessor directives: #include.version directive specifying the PTX language version. #else. The C preprocessor cpp may be used to process PTX source files. Pseudo-operations specify symbol and addressing management. 4. whitespace is ignored except for its use in separating tokens in the language.target directive specifying the target architecture assumed. #line. Lines beginning with # are preprocessor directives.2.Chapter 4. PTX is case sensitive and uses lowercase for keywords. followed by a . Lines are separated by the newline character (‘\n’). Source Format Source files are ASCII text. 4. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #define. #ifdef.1. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. 2010 17 . and using // to begin a comment that extends to the end of the current line. Syntax PTX programs are a collection of text source files. See Section 9 for a more information on these directives. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Comments in PTX are treated as whitespace. Comments Comments in PTX follow C/C++ syntax. #if. All whitespace characters are equivalent. January 24. #endif. using non-nested /* and */ for comments that may span multiple lines. Each PTX file must begin with a .

Statements A PTX statement is either a directive or an instruction.extern . .global. %tid.3. The guard predicate follows the optional label and precedes the opcode.b32 r1. and is written as @p.const .maxnctapersm .section .pragma . . 18 January 24.loc . where p is a predicate register. Instructions have an optional guard predicate which controls conditional execution. mov. address expressions. r1. Instruction keywords are listed in Table 2. Table 1.global start: .3.target .2. written as @!p. so no conflict is possible with user-defined identifiers.param . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. shl.sreg .maxntid . r2. All instruction keywords are reserved tokens in PTX. r2.b32 r1.minnctapersm . or label names.5. followed by source operands. 2010 .maxnreg .0 4. Statements begin with an optional label and end with a semicolon. 0.b32 r1. and terminated with a semicolon.tex .version . Examples: .align .f32 r2.reg .file PTX Directives .local .reg . 2.shared .func .3. The guard predicate may be optionally negated.x.f32 array[N]. constant expressions.global . array[r1]. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.1. Directive Statements Directive keywords begin with a dot. ld.PTX ISA Version 2.entry .b32 add. Operands may be register variables.visible 4. r2. The destination operand is first.

Syntax Table 2.Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .

…. dollar. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.g. or dollar characters. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. listed in Table 3. PTX allows the percentage sign as the first character of an identifier.PTX ISA Version 2. The percentage sign can be used to avoid name conflicts. or percentage character followed by one or more letters. Table 3. e. between user-defined variable names and compiler-generated names.4. or they start with an underscore.0 4. digits. except that the percentage sign is not allowed. Many high-level languages such as C and C++ follow similar rules for identifier names. digits. 2010 . or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. underscore. %pm3 WARP_SZ 20 January 24.

and bit-size types. integer constants are allowed and are interpreted as in C. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Floating-point literals may be written with an optional decimal point and an optional signed exponent. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons..5.u64). or binary notation. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.5. where the behavior of the operation depends on the operand types. in which case the literal is unsigned (. To specify IEEE 754 doubleprecision floating point values.s64 or the unsigned suffix is specified. Type checking rules remain the same for integer. Integer literals may be written in decimal. the sm_1x and sm_20 targets have a WARP_SZ value of 32.e. 4. i.2. 0[fF]{hexdigit}{8} // single-precision floating point January 24. octal.5. The syntax follows that of C. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.e. 4. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.. To specify IEEE 754 single-precision floating point values. i. Constants PTX supports integer and floating-point constants and constant expressions. zero values are FALSE and non-zero values are TRUE. the constant begins with 0d or 0D followed by 16 hex digits. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.s64 or .Chapter 4.u64. the constant begins with 0f or 0F followed by 8 hex digits. each integer constant is converted to the appropriate size based on the data or instruction type at its use. These constants may be used in data initialization and as operands to instructions.s64) unless the value cannot be fully represented in . literals are always represented in 64-bit double-precision format. there is no suffix letter to specify size. Syntax 4.1. hexadecimal. floating-point. every integer constant has type . Unlike C and C++. When used in an instruction or data initialization. 2010 21 . The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. For predicate-type data and instructions.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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Syntax 4.f64 same as source .f64 integer .u64 .u64 1st unchanged.s64.u64 same as 1st operand . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 use usual conversions . or . .s64 .5.u64 .u64 .u64) (.s64) + .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64.u64 .s64 .f64 use usual conversions .f64 use usual conversions .s64 .s64 .u64 .f64 : .u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 converted type constant literal + ! ~ Cast Binary (.6.Chapter 4. Table 5. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .s64 .u64 . 2010 25 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 integer integer integer integer integer int ?.s64 . 2nd is .f64 converted type .s64 .f64 integer .

2010 .PTX ISA Version 2.0 26 January 24.

reg . Table 6. Global texture memory (deprecated). shared by all threads. read-only memory.1. Read-only. and level of sharing between threads. 5. and these resources are abstracted in PTX through state spaces and data types. addressability. The list of state spaces is shown in Table 4. .tex January 24.Chapter 5.sreg .shared . pre-defined. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Local memory. defined per-grid.local . and properties of state spaces are shown in Table 5. All variables reside in some state space. platform-specific. or Function or local parameters.global . private to each thread. Types. Addressable memory shared between threads in 1 CTA. access speed. fast. Global memory. State Spaces. defined per-thread. the kinds of resources will be common across platforms. Special registers. The characteristics of a state space include its size. Kernel parameters. 2010 27 .param . State Spaces A state space is a storage area with particular characteristics. Name State Spaces Description Registers. and Variables While the specific resources available in a given target GPU will vary.const . Shared. access rights.

the parameter is then located on the stack frame and its address is in the . Register size is restricted.sreg .1. clock counters. floating point. predicate) or untyped. scalar registers have a width of 8-. All special registers are predefined. such as grid. CTA.param instructions. Register State Space Registers (.2.param (used in functions) . and performance monitoring registers. st. 5. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). and thread parameters. The number of registers is limited. causing changes in performance. 1 Accessible only via the ld. i.reg . via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 2 Accessible via ld. platform-specific registers. 28 January 24. Registers differ from the other state spaces in that they are not fully addressable.1.1. When the limit is exceeded.reg state space) are fast storage locations. 64-.sreg) state space holds predefined.e. 3 Accessible only via the tex instruction.param instruction. register variables will be spilled to memory. Registers may have alignment boundaries required by multi-word loads and stores.param and st. or 64-bits. Special Register State Space The special register (. it is not possible to refer to the address of a register. aside from predicate registers which are 1-bit.local state space. unsigned integer.param (as input to kernel) .const . The most common use of 8-bit registers is with ld. 32-.global .0 Table 7. or as elements of vector tuples. 2010 . or 128-bits. and vector registers have a width of 16-.. 32-.tex Restricted Yes No3 5.local . and will vary from platform to platform. Device function input parameters may have their address taken via mov. and cvt instructions. Registers may be typed (signed integer.PTX ISA Version 2. For each architecture.shared . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. Address may be taken via mov instruction. 16-.

1. the bank number must be provided in the state space of the load instruction.const[2]. If no bank number is given. the declaration . as it must be allocated on a perthread basis. // load second word 5. [const_buffer+4].sync instruction are guaranteed to be visible to any reads after the barrier instruction. State Spaces. To access data in contant banks 1 through 10.local to access local variables.3. Constant State Space The constant (. Module-scoped local memory variables are stored at fixed addresses. Consider the case where one thread executes the following two assignments: a = a + 1.5. Global State Space The global (.const[bank] modifier. where bank ranges from 0 to 10. and Variables 5. Types. 5. all addresses are in global memory are shared. each pointing to the start address of the specified constant bank.local and st.global) state space is memory that is accessible by all threads in a context. Threads must be able to do their work without waiting for other threads to do theirs. 2010 29 .1. for example). there are eleven 64KB banks.extern .b32 const_buffer[]. Global memory is not sequentially consistent. The size is limited. The constant memory is organized into fixed size banks. bank zero is used for all statically-sized constant variables. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. st. The remaining banks may be used to implement “incomplete” constant arrays (in C. Threads wait at the barrier until all threads in the CTA have arrived.sync instruction. the store operation updating a may still be in flight. It is typically standard memory with cache. If another thread sees the variable b change. For example. bank zero is used.Chapter 5. where the size is not known at compile time. It is the mechanism by which different CTAs and different grids can communicate.global.const[2] .const[2] .1.extern . Banks are specified using the .b32 %r1. whereas local memory variables declared January 24. Use ld.4. This pointer can then be used to access the entire 64KB constant bank.global. an incomplete array in bank 2 is accessed as follows: . For the current devices. results in const_buffer pointing to the start of constant bank two. By convention. For any thread in a context. This reiterates the kind of parallelism available in machines that run PTX. Local State Space The local state space (. Use ld. and atom. Sequential consistency is provided by the bar. initialized by the host.global to access global variables. All memory writes prior to the bar.const) state space is a read-only memory. For example. ld.b32 const_buffer[]. as in lock-free and wait-free style programming. the stack is in local memory. b = b – 1. Multiple incomplete array variables declared in the same bank become aliases. In implementations that support a stack.local) is private memory for each thread to keep its own data.

Values passed from the host to the kernel are accessed through these parameter variables using ld. len. PTX code should make no assumptions about the relative locations or ordering of . in some implementations kernel parameters reside in global memory. The kernel parameter variables are shared across all CTAs within a grid. . Parameter State Space The parameter (. For example.1.reg . These parameters are addressable.0 within a function or kernel body are allocated on the stack.param space.u32 %ptr.param . No access protection is provided between parameter and global space in this case. Example: .u32 %n. … Example: . all local memory variables are stored at fixed addresses and recursive function calls are not supported. … 30 January 24.entry foo ( .b32 len ) { .1.f64 %d.param. 5.u32 %ptr.b8 buffer[64] ) { .param instructions. [%ptr].param .6. device function parameters were previously restricted to the register state space.reg .param) state space is used (1) to pass input arguments from the host to the kernel. The resulting address is in the . read-only variables declared in the .entry bar ( .param. mov.PTX ISA Version 2. In implementations that do not support a stack. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param . Note that PTX ISA versions 1.x supports only kernel function parameters in . Similarly.6.u32 %n. Note: The location of parameter space is implementation specific. ld.f64 %d. The use of parameter state space for device function parameters is new to PTX ISA version 2.param state space and is accessed using ld. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. %n. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). ld. (2a) to declare formal input and return parameters for device functions called from within kernel execution.0 and requires target architecture sm_20. Therefore.1. ld. 5. The address of a kernel parameter may be moved into a register using the mov instruction.reg . 2010 . .param instructions. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. per-kernel versus per-thread). typically for passing large structures by value to a function. [buffer].param state space.u32 %n.align 8 .param.b32 N.param space variables. [N].

Device Function Parameters PTX ISA version 2. . This will be passed by value to a callee.param. and so the address will be in the . such as C structures larger than 8 bytes.param .func foo ( .local state space and is accessed via ld. Note that the parameter will be copied to the stack if necessary.param space is also required whenever a formal parameter has its address taken within the called function.Chapter 5. January 24. call foo.param. In PTX. the address of a function input parameter may be moved into a register using the mov instruction.param .f64 dbl.param and function return parameters may be written using st. }.b8 buffer[12] ) { . dbl. Example: // pass object of type struct { double d.align 8 . Function input parameters may be read via ld. [buffer+8]. is flattened.align 8 . Typically. It is not possible to use mov to get the address of a return parameter or a locally-scoped . .param. } mystruct. a byte array in parameter space is used.0 extends the use of parameter space to device function parameters.reg .s32 [mystruct+8].param.6.param. int y. which declares a . [buffer]. … } // code snippet from the caller // struct { double d.b8 mystruct. The most common use is for passing objects by value that do not fit within a PTX register. (4.s32 %y. .param space variable.s32 %y. and Variables 5. the caller will declare a locally-scoped . .reg . … See the section on function call syntax for more details. ld. . State Spaces.reg .local and st. st.f64 %d. it is illegal to write to an input parameter or read from a return parameter.local instructions.s32 x.param formal parameter having the same size and alignment as the passed argument.reg . int y.reg .f64 [mystruct+0]. ld. … st.f64 %d.2. mystruct).b32 N. . Types. x.param byte array variable that represents a flattened C structure or union.1. Aside from passing structures by value. In this case. 2010 31 . passed to foo … .

tex directive will bind the named texture memory variable to a hardware texture identifier. Multiple names may be bound to the same physical texture identifier.texref variables in the . 5. For example. It is shared by all threads in a context.7.7. and .6 for its use in texture instructions. The texture name must be of type . An error is generated if the maximum number of physical resources is exceeded.tex) state space is global memory accessed via the texture instruction. is equivalent to .u64. Physical texture resources are allocated on a per-module granularity.u32 .tex . Example: . Shared State Space The shared (.3 for the description of the . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. The .8.shared to access shared variables. Use ld.tex variables are required to be defined in the global scope. where all threads read from the same address. Another is sequential access from sequential threads.u32 tex_a.texref. tex_d. 2010 .shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex state space are equivalent to module-scoped . a legacy PTX definitions such as . 32 January 24.shared and st.u32 . and variables declared in the . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex .0 5.u32 . An address in shared memory can be read and written by any thread in a CTA. Texture memory is read-only.tex directive is retained for backward compatibility. The .texref type and Section 8.tex .PTX ISA Version 2.u32 tex_a.tex . tex_f.tex .global . and programs should instead reference texture memory through variables of type . See Section 5.1.texref tex_a. tex_c. Texture State Space (deprecated) The texture (. tex_d. One example is broadcast. Shared memory typically has some optimizations to support the sharing.1.global state space.u32 or . where texture identifiers are allocated sequentially beginning with zero. A texture’s base address is assumed to be aligned to a 16-byte boundary.

b32. All floating-point instructions operate only on . A fundamental type specifies both a basic type and a size.f32 and . or converted to other types and sizes.Chapter 5. Types. . State Spaces. but typed variables enhance program readability and allow for better operand type checking. and instructions operate on these types. The . For convenience.f64 . . . 5.b8 instruction types are restricted to ld. needed to fully specify instruction behavior.2.s8.1. Signed and unsigned integer types are compatible if they have the same size. . . and converted using regular-width registers. Fundamental Types In PTX. In principle. stored.u32. Operand types and sizes are checked against instruction types for compatibility.f64 types.u16.u64 .2.s8. Two fundamental types are compatible if they have the same basic type and are the same size.f16 floating-point type is allowed only in conversions to and from . For example. Types 5. so their names are intentionally short. .u8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. and . .2.s16. stored. ld. Restricted Use of Sub-Word Sizes The . January 24. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .2. so that narrow values may be loaded. and Variables 5. st.f16.pred Most instructions have one or more type specifiers. .b8. Register variables are always of a fundamental type.s64 . all variables (aside from predicates) could be declared using only bit-size types. 2010 33 .f32. the fundamental types reflect the native data types supported by the target architectures.b16. The bitsize type is compatible with any fundamental type having the same size.b64 . The following table lists the fundamental type specifiers for each basic type: Table 8. .s32. st. . . and cvt instructions.u8. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. .f64 types. The same typesize specifiers are used for both variable definitions and for typing instructions.f32 and .

e. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.u64} reg. or performing pointer arithmetic will result in undefined results. Creating pointers to opaque variables using mov.PTX ISA Version 2.3. For working with textures and samplers.samplerref variables. texture and sampler information is accessed through a single . samplers. and .samplerref. accessing the pointer with ld and st instructions.surfref.texref. but all information about layout. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. hence the term “opaque”. and surface descriptor variables. field ordering. texture and sampler information each have their own handle. the resulting pointer may be stored to and loaded from memory. PTX has two modes of operation. i. Referencing textures. Retrieving the value of a named member via query instructions (txq. but the pointer cannot otherwise be treated as an address. . suld. and de-referenced by texture and surface load. The three built-in types are . In independent mode the fields of the . and overall size is hidden to a PTX program. or surfaces via texture and surface load/store instructions (tex. sured). sampler. The following tables list the named members of each type for unified and independent texture modes. In the unified mode. base address. 34 January 24. Texture. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. passed as a parameter to functions. In the independent mode. suq). store. 2010 .0 5.texref handle. opaque_var. Sampler. These types have named fields similar to structures. and Surface Types PTX includes built-in “opaque” types for defining texture.{u32. since these properties are defined by .texref type that describe sampler properties are ignored.. sust. and query instructions. allowing them to be defined separately and combined at the site of usage in the program.

clamp_to_border 0. Types. 1 nearest. State Spaces.texref values . Member width height depth Opaque Type Fields in Independent Texture Mode . linear wrap. mirror. clamp_ogl. clamp_to_edge. 1 ignored ignored ignored ignored .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge. Member width height depth Opaque Type Fields in Unified Texture Mode .texref values in elements in elements in elements 0.Chapter 5. 2010 35 . and Variables Table 9.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. mirror. clamp_ogl.samplerref values N/A N/A N/A N/A nearest. clamp_to_border N/A N/A N/A N/A N/A . linear wrap.

global . the types may be initialized using a list of static expressions assigning values to the named members.PTX ISA Version 2.global state space.global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. filter_mode = nearest }. these variables are declared in the . 36 January 24. these variables must be in the . 2010 . As kernel parameters.texref my_texture_name. When declared at module scope. Example: . .surfref my_surface_name.global .global .global . At module scope.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. . Example: .param state space. .texref tex1.samplerref my_sampler_name.

Variable Declarations All storage for data is specified with variable declarations. q.v1.Chapter 5. . Three-element vectors may be handled by using a .v4 vector. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v2 . etc. vector variables are aligned to a multiple of their overall size (vector length times base-type size). . a variable declaration describes both the variable’s type and its state space.v3 }. // a length-2 vector of unsigned ints . 1. Types. where the fourth element provides padding. Vectors cannot exceed 128-bits in length.1.v4 . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . // typedef .4.f32 bias[] = {-1. textures.u32 loc. 5.global . and an optional fixed address for the variable. 0.v4 .global .const . an optional initializer. In addition to fundamental types.reg .f32 V. State Spaces. Examples: .v4. and Variables 5.s32 i. 0}. This is a common case for three-dimensional grids. its type and size. .u8 bg[4] = {0.reg .u16 uv. A variable declaration names the space in which the variable resides. Predicate variables may only be declared in the register state space. // a length-4 vector of bytes By default.shared . its name. Variables In PTX. 0.global . for example. // a length-4 vector of floats .v2 or .global .f32 accel. 2010 37 . Vectors Limited-length vector types are supported.0}.struct float4 { .4. 5. Every variable must reside in one of the state spaces enumerated in the previous section.v2. .struct float4 coord.v4 .global .f64 is not allowed.2. Vectors must be based on a fundamental type. . and they may reside in the register space. r.4.v4. .0.f32 v0. .b8 v. January 24.pred p. an optional array size. Examples: .reg . PTX supports types for simple aggregate objects such as vectors and arrays.

. Array Declarations Array declarations are provided to allow the programmer to reserve space.u64. Examples: . Variables that hold addresses of variables or instructions should be of type . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).b32 ptr = rgba..4. 5.local .1. 38 January 24. 0}.05}}. Similarly. .05}. where the variable name is followed by an equals sign and the initial value or values for the variable.0. . The size of the array specifies how many elements should be reserved.{.{.0}. {0.global . A scalar takes a single value. Initializers are allowed for all types except . -1}.u16 kernel[19][19]. being determined by an array initializer.PTX ISA Version 2.u8 mailbox[128].global .f16 and .0}.1}.u8 rgba[3] = {{1.3.0.4.global .0. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.v4 .1.s32 offset[][] = { {-1. // address of rgba into ptr Currently.05. ...pred.shared .s32 n = 10.4. . Here are some examples: .0}}. 0}..global .4. variable initialization is supported only for constant and global state spaces. or is left empty. 19*19 (361) halfwords are reserved (722 bytes). {1.1. Variable names appearing in initializers represent the address of the variable. For the kernel declaration above. 1} }.f32 blur_kernel[][] = {{.05. {0.u32 or .1. {0. 2010 . The size of the dimension is either a constant expression. To declare an array.1.0.0 5. .global . {0.. this can be used to initialize a jump table to be used with indirect branches or calls. label names appearing in initializers represent the address of the next instruction following the label. this can be used to statically initialize a pointer to a variable.

January 24.const .align byte-count specifier immediately following the state-space specifier.0. 5.6. . For example. and may be preceded by an alignment specifier. %r1. . %r99. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. it is quite common for a compiler frontend to generate a large number of register names.4. 2010 39 .Chapter 5. alignment specifies the address alignment for the starting address of the entire array.reg .. The default alignment for vector variables is to a multiple of the overall vector size. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.4. …. These 100 register variables can be declared as follows: . Types.0}. For arrays.. nor are initializers permitted.0.5.b32 variables. The default alignment for scalar and array variables is to a multiple of the base-type size. // declare %r0. Array variables cannot be declared this way. say one hundred. Elements are bytes. of . Examples: // allocate array at 4-byte aligned address. Parameterized Variable Names Since PTX supports virtual registers. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. The variable will be aligned to an address which is an integer multiple of byte-count.b32 %r<100>. Alignment is specified using an optional . %r1. State Spaces. not for individual elements. suppose a program uses a large number.2.align 4 .0. named %r0. and Variables 5.b8 bar[8] = {0. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.0.. Rather than require explicit declaration of every name.0.

0 40 January 24. 2010 .PTX ISA Version 2.

as its job is to convert from nearly any data type to any other data type (and size). q.reg register state space.3. The mov instruction copies data between registers. January 24. b. The bit-size type is compatible with every type having the same size. 6.1. s. Most instructions have an optional predicate guard that controls conditional execution. Each operand type must be compatible with the type determined by the instruction template and instruction type. Instructions ld and st move data from/to addressable state spaces to/from registers. 6. Operand Type Information All operands in instructions have a known type from their declarations. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.2.Chapter 6. There is no automatic conversion between types. st. The ld. r. 2010 41 . so operands for ALU instructions must all be in variables declared in the . Integer types of a common size are compatible with each other. Predicate operands are denoted by the names p. PTX describes a load-store machine. and c. For most operations. The result operand is a scalar or vector variable in the register state space. mov. . the sizes of the operands must be consistent. and a few instructions have additional predicate source operands. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. The cvt (convert) instruction takes a variety of operand types and sizes. Instruction Operands 6. and cvt instructions copy data from one location to another. Source Operands The source operands are denoted in the instruction descriptions by the names a.

global .0 6.s32 q. p. The address is an offset in the state space in which the variable is declared.u16 ld. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.reg . The interesting capabilities begin with addresses.PTX ISA Version 2. Address expressions include variable names. Load and store operations move data between registers and locations in addressable state spaces. All addresses and address computations are byte-based. there is no support for C-style pointer arithmetic. Using Addresses.reg . address registers. . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.u16 r0.const . . [tbl+12].s32 tbl[256]. W. Examples include pointer arithmetic and pointer comparisons.4. .const.1.[x]. .f32 ld.b32 p. [V]. address register plus byte offset. r0. 6. The mov instruction can be used to move the address of a variable into a pointer.4.reg .reg . The syntax is similar to that used in many assembly languages. .v4. and vectors.u32 42 January 24.u16 x. ld.v4 . arrays.shared .s32 mov. Here are a few examples: . and Vectors Using scalar variables as operands is straightforward.f32 V. q. and immediate address expressions which evaluate at compile-time to a constant address. 2010 .f32 W. . Arrays. tbl.shared.v4 .gloal.

The size of the array is a constant in the program.reg . or a braceenclosed list of similarly typed scalars.v4. . Rb. [addr+offset]. // move address of a[1] into s 6.x V. The expression within square brackets is either a constant integer.x. or by indexing into the array using square-bracket notation.y.3.v2.v4. and tex. Rc.g. . [addr+offset2]. .w.b V.b. for use in an indirect branch or call.f32 ld. mov.r V.z V. Examples are ld. Vectors may also be passed as arguments to called functions.4.4. where the offset is a constant expression that is either added or subtracted from a register variable.w = = = = V. Here are examples: ld.global. ld. ld.global.global. as well as the typical color fields .u32 s. which include mov.c. Array elements can be accessed using an explicitly calculated byte address. a[0].b. it must be written as an address calculation prior to use. . mov.u32 {a. and the identifier becomes an address constant in the space where the array is declared.a.4. a[N-1]. A brace-enclosed list is used for pattern matching to pull apart vectors. st.reg . V2.z and .c. . Vector elements can be extracted from the vector with the suffixes .v4 .d}.f32 {a. Arrays as Operands Arrays of all types can be declared.b and . Elements in a brace-enclosed vector.f32 V.g V.d}. If more complicated indexing is desired.Chapter 6. c.4. which may improve memory performance. say {Ra. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. and in move instructions to get the address of the label or function into a register.a 6.u32 s. or a simple “register with constant offset” expression. The registers in the load/store operations can be a vector.2. Vector loads and stores can be used to implement wide loads and stores. a register variable. d.r. January 24.y V.global. b. Rd}. .u32 s. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. 2010 43 . V. a[1].f32 a. Vectors as Operands Vector operands are supported by a limited subset of instructions. Instruction Operands 6.

Type Conversion All operands to all arithmetic. For example. Operands of different sizes or types must be converted prior to the operation. and data movement instruction must be of the same type and size.5.u16 instruction is given a u16 source operand and s32 as a destination operand. 44 January 24. the u16 is zero-extended to s32.0 6.PTX ISA Version 2. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.5. except for operations where changing the size and/or type is part of the definition of the instruction. 2010 . Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 6. and ~131.1.000 for f16). if a cvt.s32. logic.

zext = zero-extend.u32 targeting a 32-bit register will first chop to 16-bits. f2u = float-to-unsigned. f2s = float-to-signed. cvt.s16. Instruction Operands Table 11. then sign-extend to 32-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. s2f = signed-to-float. 2010 45 . the result is extended to the destination register width after chopping. chop = keep only low bits that fit. f2f = float-to-float. For example. u2f = unsigned-to-float. Notes 1 If the destination register is wider than the destination format. The type of extension (sign or zero) is based on the destination format. January 24.Chapter 6.

choosing even integer if source is equidistant between two integers. Table 12.rni . In PTX. The following tables summarize the rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. Rounding Modifiers Conversion instructions may specify a rounding modifier. Modifier . there are four integer rounding modifiers and four floating-point rounding modifiers.rzi .2.5.0 6. 2010 .rpi Integer Rounding Modifiers Description round to nearest integer.rn .rmi .rz . Modifier .rm .PTX ISA Version 2.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.

Much of the delay to memory can be hidden in a number of ways. first access is high Notes January 24. while global memory is slowest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Instruction Operands 6. Operand Costs Operands from different state spaces affect the speed of an operation. Registers are fastest. The register in a store operation is available much more quickly.6. Table 11 gives estimates of the costs of using different kinds of memory.Chapter 6. 2010 47 . as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Another way to hide latency is to issue the load instructions as early as possible. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Table 14.

0 48 January 24. 2010 .PTX ISA Version 2.

A function declaration specifies an optional list of return parameters. NOTE: The current version of PTX does not implement the underlying. the function name. These include syntax for function definitions. … Here. Scalar and vector base-type input and return parameters may be represented simply as register variables. At the call. Abstracting the ABI Rather than expose details of a particular calling convention. A function must be declared or defined prior to being called.func foo { … ret. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. and Application Binary Interface (ABI). January 24. and an optional list of input parameters. The simplest function has no parameters or return values. stack layout. and return values may be placed directly into register variables. together these specify the function’s interface. Function declarations and definitions In PTX. Execution of the ret instruction within foo transfers control to the instruction following the call.func directive. } … call foo. In this section. A function definition specifies both the interface and the body of the function. function calls. so recursion is not yet supported. functions are declared and defined using the . 7. arguments may be register variables or constants. we describe the features of PTX needed to achieve this hiding of the ABI. and is represented in PTX as follows: . support for variadic functions (“varargs”). implicitly saving the return address. parameter passing. and memory allocated on the stack (“alloca”).1. stack-based ABI. or prototype. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations.Chapter 7. 2010 49 . execution of the call instruction transfers control to foo.

param space memory. %inc. char c[4].param .param space variables are used in two ways.param. [y+11].4).reg space.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. [y+0]. … st.b8 c3. py).c2.u32 %inc ) { add.f64 f1.u32 %res) inc_ptr ( .param. byte array in . ld.param. st.b32 c1. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .u32 %res.reg .b8 [py+11]. … … // computation using x.func (. inc_ptr. } … call (%r1).align 8 py[12].param. %rc1. c3. st.param.param.func (.PTX ISA Version 2.reg .param space call (%out).align 8 y[12]) { . ld.b8 . In PTX. note that .s32 out) bar (.f64 f1.b8 [py+ 8]. The .param. st.reg .param variable y is used in function definition bar to represent a formal parameter. a .reg .param.s32 x. For example. c4. Second.reg . }.0 Example: . 50 January 24. First.b64 [py+ 0]. this structure will be flattened into a byte array. // scalar args in . (%x. (%r1. } { . … ld.param. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . ret.param.c1. c2.b8 c4.b8 [py+10]. bumpptr. [y+8]. ld.u32 %ptr.param . a .b8 c2. %rc1. %rc2. . [y+10]. [y+9].c3. %rd. . passed by value to a function: struct { double dbl.b8 . 2010 . st. Since memory accesses are required to be aligned to a multiple of the access size. … In this example.b8 c1.f64 field are aligned.f1.b8 [py+ 9]. .reg . consider the following C structure. %rc2. ld.param state space is used to pass the structure by value: .reg . %ptr.c4.

param space formal parameters that are base-type scalar or vector variables. Abstracting the ABI The following is a conceptual way to think about the .param memory must be aligned to a multiple of 1. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. January 24.param or . In the case of .param space formal parameters that are byte arrays. or 16 bytes.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. a .reg variables.param or . • • • For a callee. or a constant that can be represented in the type of the formal parameter. 4. In the case of . Note that the choice of . 8.param variables.reg variables.param arguments.param state space is used to receive parameter values and/or pass return values back to the caller.param argument must be declared within the local scope of the caller. and alignment of parameters. size.reg space variable of matching type and size. 2.reg or .param space byte array with matching type.param and ld. and alignment. For a callee. 2010 51 . • • • Input and return parameters may be .param instructions used for argument passing must be contained in the basic block with the call instruction.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. Typically.reg space variable with matching type and size.reg state space in this way provides legacy support. or a constant that can be represented in the type of the formal parameter.param state space use in device functions. This enables backend optimization and ensures that the . For .param byte array is used to collect together fields of a structure being passed by value.. Supporting the . Parameters in . A . • • Arguments may be .Chapter 7. For a caller.g. or constants. In the case of . The . all st. For a caller. the corresponding argument may be either a .param variables or .reg state space can be used to receive and return base-type scalar and vector values. size.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. • The . the argument must also be a . The .reg space formal parameters.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The following restrictions apply to parameter passing. • The . the corresponding argument may be either a .

0 continues to support multiple return registers for sm_1x targets. Changes from PTX 1.x In PTX ISA version 1. PTX 2.0 restricts functions to a single return value. For sm_2x targets. and a . formal parameters may be in either .param space parameters support arrays. Objects such as C structures were flattened and passed or returned using multiple registers. 2010 .0. PTX 2. 52 January 24.param byte array should be used to return objects that do not fit into a register.x.1. PTX 1.param state space.reg or .x supports multiple return values for this purpose. and there was no support for array parameters.PTX ISA Version 2.1. In PTX ISA version 2. formal parameters were restricted to .reg state space.0 7. and .

func okay ( … ) Built-in functions are provided to initialize.b32 val) %va_arg (. and end access to a list of variable arguments. . %s1. 2. PTX provides a high-level mechanism similar to the one provided by the stdarg. for %va_arg64. (2. or 4 bytes. 2. 2. 8.u32 ap. %va_end is called to free the variable argument list handle.s32 result. call (val). %r1. call (ap). (3. Variadic functions NOTE: The current version of PTX does not support variadic functions.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.b32 result. (ap. ctr.reg .reg .reg .func baz ( .reg . the size may be 1.reg .reg .u32 align) . For %va_arg. maxN. or 16 bytes.u32 sz. %s2). To support functions with a variable number of arguments. or 8 bytes.reg . Once all arguments have been processed. This handle is then passed to the %va_arg and %va_arg64 built-in functions.u32 ptr) %va_start .u32 a.reg .ge p. 2010 53 .reg ..u32 align) .reg . . ) { . the alignment may be 1. Abstracting the ABI 7. 0. ctr. maxN.reg . (ap).func %va_end (.Chapter 7.u32 ptr. .u32 ptr. // default to MININT mov. max. The function prototypes are defined as follows: .u32 sz. iteratively access.b32 ctr. 0x8000000.u32 b.s32 result ) maxN ( . . N. … %va_start returns Loop: @p Done: January 24.reg . 4. ret. . %r3). .u32.func (.h and varargs. In both cases.reg . setp. %va_start.reg . following zero or more fixed parameters: . mov.pred p.s32 val.func (. the size may be 1. 4.u32 N. .func (. bra Done.b64 val) %va_arg64 (. . result. 4).reg . call %va_end.2.func ( . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . … call (%max). … ) . along with the size and alignment of the next data value to be accessed. %r2. bra Loop.reg .h headers in C. variadic functions are declared with an ellipsis at the end of the input parameter list. } … call (%max). 4. %va_arg.reg . In PTX.. val.

local instructions.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. 54 January 24. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.3. Alloca NOTE: The current version of PTX does not support alloca. To allocate memory.u32 ptr ) %alloca ( .reg . a function simply calls the built-in function %alloca. If a particular alignment is required. defined as follows: .local and st.0 7.PTX ISA Version 2.func ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. 2010 .reg . The array is then accessed with ld. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.

Format and Semantics of Instruction Descriptions This section describes each PTX instruction. q = !(a < b).lt p|q. A. B. opcode A.2. opcode D. 2010 55 . B. PTX Instructions PTX instructions generally have from zero to four operands. A.s32. // p = (a < b). 8. The setp instruction writes two destination registers. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. For instructions that create a result value.Chapter 8. and C are the source operands. B. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. Instruction Set 8. We use a ‘|’ symbol to separate multiple destination registers. C. while A. opcode D. the semantics are described. opcode D. A. followed by some examples that attempt to show several possible instantiations of the instruction.1. January 24. In addition to the name and the format of the instruction. b. For some instructions the destination operand is optional. a. the D operand is the destination operand. setp.

pred p.pred as the type specifier. add 1 to j To get a conditional branch or conditional function call. add.s32 j. use a predicate to control the execution of the branch or call instructions. 2010 . the following PTX instruction sequence might be used: @!p L1: setp. j. This can be written in PTX as @p setp. … // compare i to n // if false.reg . 1. Predicated Execution In PTX. i.s32 p.s32 p.0 8. i. n. q. add. j. // p = (i < n) // if i < n. Predicates are most commonly set as the result of a comparison performed by the setp instruction. To implement the above example as a true conditional branch. So. As an example. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. n. Instructions without a guard predicate are executed unconditionally.lt. predicate registers are virtual and have .3.PTX ISA Version 2. consider the high-level code if (i < n) j = j + 1.s32 j. where p is a predicate variable. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. 1. predicate registers can be declared as . branch over 56 January 24. optionally negated. bra L1.lt.

2.1. lo (lower). ne. the result is false.1. Comparisons 8.1. ls (lower-or-same). Instruction Set 8.3.Chapter 8. ne (not-equal). The bit-size comparisons are eq and ne.1. gt. le. 2010 57 . If either operand is NaN. lt. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.3. le (less-than-or-equal). hi (higher).3. Table 16. Unsigned Integer. The following table shows the operators for signed integer. lt (less-than). The unsigned comparisons are eq. ne. unsigned integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). ge. and bitsize types. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and hs (higher-or-same). ordering comparisons are not defined for bit-size types. gt (greater-than). Table 15. and ge (greater-than-or-equal). and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.

PTX ISA Version 2. geu.%p. and mov. and no direct way to load or store predicate register values.0 To aid comparison operations in the presence of NaN values. neu. xor. or. for example: selp. then the result of these comparisons is true. ltu. There is no direct conversion between predicates and integer values. leu. If both operands are numeric values (not NaN). Table 17. setp can be used to generate a predicate from an integer.u32 %r1. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. 2010 . gtu.1. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. two operators num (numeric) and nan (isNaN) are provided. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. not. // convert predicate to 32-bit value 58 January 24. num returns true if both operands are numeric values (not NaN). If either operand is NaN. then these comparisons have the same result as their ordered counterparts.0. and nan returns true if either operand is NaN. Table 18. However.2.3. unordered versions are included: equ.

f32 d. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. add. a. Type Checking Rules Operand Type .uX ok ok ok inv . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. For example: .u16 d. most notably the data conversion instruction cvt. It requires separate type-size modifiers for the result and source.sX ok ok ok inv .f32.bX . unsigned. b. the add instruction requires type and size information to properly perform the addition operation (signed. i. b. cvt.reg . a. they must match exactly.fX ok inv inv ok Instruction Type .4. For example.. different sizes). Type Information for Instructions and Operands Typed instructions must have a type-size modifier. and this information must be specified as a suffix to the opcode.u16 d.reg . . • The following table summarizes these type checking rules.u16 d.bX .fX ok ok ok ok January 24. For example. 2010 59 .reg . Instruction Set 8. and integer operands are silently cast to the instruction type if needed. and these are placed in the same order as the operands.sX . Floating-point types agree only if they have the same size. float. Example: . Table 19. Signed and unsigned integer types agree provided they have the same size. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.u16 a.e.uX .Chapter 8. a.

inv = invalid. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. 2010 . ld. For example. the cvt instruction does not support . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. floating-point instruction types still require that the operand type-size matches exactly. 2.PTX ISA Version 2. parse error.4. the size must match exactly. 4. unless the operand is of bit-size type.bX instruction types. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. stored. When a source operand has a size that exceeds the instruction-type size. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. The following table summarizes the relaxed type-checking rules for source operands. 1. or converted to other types and sizes. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. the data will be truncated.0 8. “-“ = allowed. Operand Size Exceeding Instruction-Type Size For convenience. The data is truncated to the instruction-type size and interpreted according to the instruction type. When used with a narrower bit-size type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Floating-point source registers can only be used with bit-size or floating-point instruction types. When used with a floating-point instruction type.1. for example. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Table 20. Source register size must be of equal or greater size than the instruction-type size. Note that some combinations may still be invalid for a particular instruction. and converted using regular-width registers. Notes 3. so that narrow values may be loaded. no conversion needed. so those rows are invalid for cvt. st. stored. 60 January 24. Bit-size source registers may be used with any appropriately-sized instruction type.

the data is zeroextended. 2. Bit-size destination registers may be used with any appropriately-sized instruction type. When used with a narrower bit-size instruction type. 1. Table 21. Notes 3. If the corresponding instruction type is signed integer. 2010 61 . parse error. January 24.or sign-extended to the size of the destination register. the data will be zero-extended. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend.Chapter 8. The data is sign-extended to the destination register width for signed integer instruction types. The data is signextended to the destination register width for signed integer instruction types. When used with a floatingpoint instruction type. zext = zero-extend. the size must match exactly. and is zero-extended to the destination register width otherwise. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. “-“ = Allowed but no conversion needed. the data is sign-extended. Instruction Set When a destination operand has a size that exceeds the instruction-type size. otherwise. Destination register size must be of equal or greater size than the instruction-type size. The following table summarizes the relaxed type-checking rules for destination operands. 4. the destination data is zero. inv = Invalid.

Divergence of Threads in Control Constructs Threads in a CTA execute together. 2010 . However.6. If threads execute down different control flow paths. If all of the threads act in unison and follow a single control flow path. this is not desirable. and 16-bit computations are “promoted” to 32-bit computations.6. 8. until they come to a conditional control construct such as a conditional branch.5. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.1. for many performance-critical applications. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. At the PTX language level. 8. Therefore. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. at least in appearance. for example. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. 62 January 24. until C is not expressive enough. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. When executing on a 32-bit data path. These extra precision bits can become visible at the application level. a compiler or code author targeting PTX can ignore the issue of divergent threads. A compiler or programmer may chose to enforce portable. the semantics of 16-bit instructions in PTX is machine-specific. The semantics are described using C. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.PTX ISA Version 2. conditional function call. For divergent control flow.uni suffix. using the . Both situations occur often in programs. by a right-shift instruction. the optimizing code generator automatically determines points of re-convergence. the threads are called uniform. 16-bit registers in PTX are mapped to 32-bit physical registers. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. the threads are called divergent.0 8. so it is important to have divergent threads re-converge as soon as possible. or conditional return. and for many applications the difference in execution is preferable to limiting performance.

1. 8. Instruction Set 8.7. In the following descriptions. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. the optional guard predicate is omitted from the syntax. addc sub.Chapter 8.7.cc. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. The Integer arithmetic instructions are: add sub add. Instructions All PTX instructions may be predicated.cc. 2010 63 .

s64 }.sat applies only to .y.s32 d. .s16. a. // . d = a – b.sat}.s32 type.a. b. Saturation modifier: .type sub{.s16. a. PTX ISA Notes Target ISA Notes Examples Table 23.MAXINT (no overflow) for the size of the operation. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. add. Introduced in PTX ISA version 1. Applies only to .u64.u32 x.s64 }. . .u64. . PTX ISA Notes Target ISA Notes Examples 64 January 24. @p add.u32. d.u16.1. sub.s32. sub.sat applies only to . d = a + b.u16. Supported on all target architectures.type = { .MAXINT (no overflow) for the size of the operation.sat limits result to MININT.u32. a. b. Supported on all target architectures. . . .s32 type. Saturation modifier: .sat. add.PTX ISA Version 2.b.c.s32 d. Applies only to . b. Description Semantics Notes Performs addition and writes the resulting value into a destination register.s32 c.s32 .0. d.sat limits result to MININT.0.sat}.. 2010 . // .s32 . add Syntax Integer Arithmetic Instructions: add Add two values. Introduced in PTX ISA version 1.type = { .s32.type add{. b.z. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. .. .0 Table 22. . a.s32 c.

cc. Instruction Set Instructions add. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y2. d = a + b.cc.CF) holding carry-in/carry-out or borrowin/borrow-out. and there is no support for setting. .y3. .b32 x1.CF No integer rounding modifiers. a.z2. Behavior is the same for unsigned and signed integers. No saturation.y4. carry-out written to CC.CF No integer rounding modifiers.b32 addc.type d. sub. add.u32. d = a + b + CC. x4. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. @p @p @p @p add. Table 24. No other instructions access the condition code.2. @p @p @p @p add.y2. if .y1.y3.cc.z1.cc.cc.s32 }. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.z4.u32. Introduced in PTX ISA version 1. b. x3.b32 x1. x4.cc Add two values with carry-out. 2010 65 .cc.cc. or testing the condition code.b32 addc. Supported on all target architectures.b32 addc. These instructions support extended-precision integer addition and subtraction.z4.b32 addc.cc.2.type = {. clearing.CF.z2. x2.cc.Chapter 8. No saturation.cc specified. Behavior is the same for unsigned and signed integers.z1. addc{. . // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. carry-out written to CC.cc.cc Syntax Integer Arithmetic Instructions: add.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.z3. Introduced in PTX ISA version 1. x2.cc}. addc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. add. x3. a.type = { .y1.b32 addc.type d. .y4.s32 }.b32 addc. Supported on all target architectures.z3. b.

u32.PTX ISA Version 2.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. sub. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.s32 }.cc.y1.b32 subc. 2010 .type d. No saturation. @p @p @p @p sub.cc Syntax Integer Arithmetic Instructions: sub.cc.z1. . d = a – b.cc.y3.type = { . borrow-out written to CC. .y4. @p @p @p @p sub.cc Subract one value from another.z3.cc.0 Table 26.cc specified. . b.z4. x4.cc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.3.(b + CC. Supported on all target architectures. x2.b32 x1. Supported on all target architectures. Behavior is the same for unsigned and signed integers. No saturation.y2.s32 }. subc{.z2. sub.b32 subc. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers. b.z1.y2. Introduced in PTX ISA version 1.z4. x4. x2. x3.cc.b32 subc.cc.z2. a.type d.cc. withborrow-in and optional borrow-out. Introduced in PTX ISA version 1. a.y3.b32 subc. d = a . x3.CF No integer rounding modifiers. if . . borrow-out written to CC.type = {. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc}.z3.b32 x1.b32 subc.CF).3. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.y4.y1. with borrow-out.u32.cc.

fxs. .s16. If .fys.hi.wide. mul.fys. then d is twice as wide as a and b to receive the full result of the multiplication. mul. Instruction Set Table 28.0>.type d.wide}. . save only the low 16 bits // 32*32 bits.wide // for .u16. d = t. Supported on all target architectures.wide.hi or ..y..s64 }. 2010 67 .n>. d = t<n-1. mul. . a.0. Description Semantics Compute the product of two values.lo.u64.x.s32 z.s16 fa.and 32-bit integer types..wide suffix is supported only for 16.lo is specified. t = a * b.type = { . .u32. . // for . // 16*16 bits yields 32 bits // 16*16 bits. The .Chapter 8.s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. creates 64 bit result January 24. mul{.lo variant Notes The type of the operation represents the types of the a and b operands. If .s16 fa. then d is the same size as a and b. . mul Syntax Integer Arithmetic Instructions: mul Multiply two values. d = t<2n-1. n = bitwidth of type. and either the upper or lower half of the result is written to the destination register.fxs..wide is specified.hi variant // for . b.lo.

t<2n-1. Description Semantics Multiplies two values and adds a third..b. If . . and either the upper or lower half of the result is written to the destination register.lo variant Notes The type of the operation represents the types of the a and b operands.s32 d.s32 d. Supported on all target architectures. @p mad. Saturation modifier: .. c. .hi. t<n-1. b.u16. The .hi. mad.0 Table 29. If . then d and c are the same size as a and b..p.type mad.sat limits result to MININT.lo. a.sat.lo is specified. Applies only to . and then writes the resulting value into a destination register.0.s64 }.MAXINT (no overflow) for the size of the operation. mad{.s16..wide is specified.n> + c. t n d d d = = = = = a * b. .c.wide // for . // for .hi variant // for .and 32-bit integer types.lo. d.lo.a. c.0> + c.q.r. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide}.hi or . . bitwidth of type..u32.hi mode.s32 r.PTX ISA Version 2. t + c.type = { . .s32. then d and c are twice as wide as a and b to receive the result of the multiplication. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. 2010 . a. b.wide suffix is supported only for 16. 68 January 24. .s32 type in .u64.

mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24.s32 d.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. mul24.Chapter 8. mul24. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.16>. . All operands are of the same type and size.. January 24.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.. a.a. // low 32-bits of 24x24-bit signed multiply. t = a * b.b.0.type = { . mul24.e.u32. 2010 69 . and return either the high or low 32-bits of the 48-bit result.. d = t<31.s32 }. b. i.hi variant // for .hi may be less efficient on machines without hardware support for 24-bit multiply. Supported on all target architectures.lo}.lo. 48bits. mul24{.hi.0>. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // for . Instruction Set Table 30. d = t<47.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. .type d.

MAXINT (no overflow). d = t<31.s32 d. mad24. mad24.s32 }.type mad24. and add a third.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. mad24. i. Description Compute the product of two 24-bit integer values held in 32-bit source registers. 48bits.. 2010 . c.0 Table 31.0. Supported on all target architectures. .b. a.16> + c. Return either the high or low 32-bits of the 48-bit result. mad24{. // for .c. b.hi mode.lo. All operands are of the same type and size. .lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. Applies only to ..s32 d. 70 January 24. mad24. t = a * b.u32.type = { .0> + c.hi.hi.sat limits result of 32-bit signed addition to MININT. d = t<47.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. 32-bit value to either the high or low 32-bits of the 48-bit result.hi variant // for .PTX ISA Version 2.e. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.sat.lo}.s32 type in . b. // low 32-bits of 24x24-bit signed multiply.hi may be less efficient on machines without hardware support for 24-bit multiply. c. Saturation modifier: . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.a.. a. d..

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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} else { max = 64. the number of leading zeros is between 0 and 64. a = a << 1. popc. a. cnt. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b64 }. For . .type == . X.b32. 2010 . clz. a. } while (d < max && (a&mask == 0) ) { d++. clz requires sm_20 or later. . For . clz. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. while (a != 0) { if (a&0x1) d++.0 Table 39. mask = 0x80000000.type = { . d = 0.b64 d.u32 Semantics 74 January 24.PTX ISA Version 2. inclusively.type = { .b64 d. inclusively.b32 popc. a = a >> 1.0. the number of leading zeros is between 0 and 32. popc requires sm_20 or later. } Introduced in PTX ISA version 2. a. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.b32) { max = 32. if (. .b32 clz. d = 0. // cnt is . mask = 0x8000000000000000.type d.type d.b32. popc Syntax Integer Arithmetic Instructions: popc Population count. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . cnt. // cnt is .0.u32 PTX ISA Notes Target ISA Notes Examples Table 40.b32 type. X.b64 }. a.b64 type. popc.

// cnt is . and operand d has type . . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. X.type==. bfind requires sm_20 or later. bfind. bfind returns 0xFFFFFFFF if no non-sign bit is found. i--) { if (a & (1<<i)) { d = i. If .type bfind. for (i=msb. a. break.s32.s64 }.shiftamt. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind returns the bit position of the most significant “1”. Semantics msb = (. a.u32 d.u32 January 24. a.0. For unsigned integers. . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind. .shiftamt. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.u32. i>=0.type = { . bfind. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 || .shiftamt is specified.shiftamt && d != -1) { d = msb .type d. For signed integers. Instruction Set Table 41.Chapter 8.s32) ? 31 : 63. . Operand a has the instruction type.type==. 2010 75 .u32. } } if (.d.s64 cnt. d = -1.u64. d.

brev requires sm_20 or later.0 Table 42. brev.type==.PTX ISA Version 2. 2010 .b32) ? 31 : 63. a.b32 d.0. for (i=0.type d. msb = (.type = { . 76 January 24.b64 }. brev. i<=msb. a. . i++) { d[i] = a[msb-i]. Description Semantics Perform bitwise reversal of input. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. .

u64 || len==0) sbit = 0. i<=msb. b.u32 || .0. bfe.type = { .u64: . Description Extract bit field from a and place the zero or sign-extended result in d. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. January 24. Semantics msb = (. .type==.b32 d. Operands a and d have the same type as the instruction type.u32 || . c.s32. pos = b. . the destination d is filled with the replicated sign bit of the extracted field. and source c gives the bit field length in bits. . The sign bit of the extracted field is defined as: . . 2010 77 . Source b gives the bit field starting bit position.u32.s64 }. Instruction Set Table 43.Chapter 8. the result is zero.u64. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. bfe requires sm_20 or later.start. len = c.type==.len. .s32) ? 31 : 63. else sbit = a[min(pos+len-1. If the start position is beyond the msb of the input.s32. bfe.msb)]. d = 0.type==.u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. for (i=0.a. if (. The destination d is padded with the sign bit of the extracted field. and operands b and c are type .u32. otherwise If the bit field length is zero. a.type==. .type d.

2010 . If the bit field length is zero. d. len = d. . . i<len && pos+i<=msb.0. Description Align and insert a bit field from a into b. pos = c. If the start position is beyond the msb of the input.u32.b64 }. b.b32) ? 31 : 63.b32. the result is b.0 Table 44.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b.type f. 78 January 24. bfi.len. and place the result in f.type = { . a. and f have the same type as the instruction type. the result is b. Semantics msb = (.start. bfi requires sm_20 or later. bfi.PTX ISA Version 2. and source d gives the bit field length in bits. and operands c and d are type .b32 d. Source c gives the starting bit position for the insertion. c. f = b. i++) { f[pos+i] = a[i]. for (i=0. Operands a. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.a. b.

and reassemble them into a 32-bit destination register.b2 source select c[11:8] d.mode} d. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). b6. Instruction Set Table 45. b5. . 2010 79 . .b1 source select c[7:4] d. c.b3 source select c[15:12] d. Note that the sign extension is only performed as part of generic form.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. . a 4-bit selection value is defined.Chapter 8.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.ecl. In the generic form (no mode specified).b32{.rc8. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. b.ecr. msb=0 means copy the literal value.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.mode = { . b0}}.f4e. prmt. . msb=1 means replicate the sign. a. {b3. . as a 16b permute code. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. The bytes in the two source registers are numbered from 0 to 7: {b. . the four 4-bit values fully specify an arbitrary byte permute.b4e. b1. The msb defines if the byte value should be copied. b4}.rc16 }. Thus. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. the permute control consists of four 4-bit selection values. For each byte in the target register.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. b2.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. a} = {{b7. default mode index d. Description Pick four arbitrary bytes from two 32-bit registers.

ctl[3]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[3] = (c >> 12) & 0xf. tmp64 ). tmp[15:08] = ReadByte( mode.PTX ISA Version 2. tmp[23:16] = ReadByte( mode. prmt. 80 January 24. tmp[31:24] = ReadByte( mode. ctl[2] = (c >> 8) & 0xf. ctl[2]. 2010 . r3. tmp64 ). r2. tmp64 ).0 Semantics tmp64 = (b<<32) | a. r4.f4e r1. ctl[1] = (c >> 4) & 0xf. r1. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. } tmp[07:00] = ReadByte( mode. ctl[1]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r3. prmt requires sm_20 or later. tmp64 ).0.b32 prmt. ctl[0]. r4. r2.b32.

The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2. Instruction Set 8.f64 register operands and constant immediate values.Chapter 8. Floating-Point Instructions Floating-point instructions operate on . 2010 81 .7.f32 and .

f32 .f64 {abs.sqrt}. sub. and mad support saturation of results to the range [0.mul}.rm .rcp.rnd. {add.neg. with NaNs being flushed to positive zero. {mad.0.f32 {div.rn .target sm_1x No rounding modifier.approx.max}.ex2}. If no rounding modifier is specified.f32 rsqrt.PTX ISA Version 2.sat Notes If no rounding modifier is specified.target sm_20 mad.sub. Double-precision instructions support subnormal inputs and results.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.min.lg2.rcp.neg.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.f64 and fma.f64 are the same. .ftz .f32 {abs.sub.rcp. The optional .f32 {add.sqrt}.sqrt}. Note that future implementations may support NaN payloads for single-precision instructions.approx.approx. default is .rnd. Single-precision add.fma}. default is . NaN payloads are supported for double-precision instructions. 1. .cos.f64 {sin.rn and instructions may be folded into a multiply-add.rnd.max}.full. 2010 .0 The following table summarizes floating-point instructions in PTX. 82 January 24. Instruction Summary of Floating-Point Instructions .min.fma}.rnd.rz .f64 div.f64 mad.0]. Table 46.rnd.f32 {mad.32 and fma.rnd. so PTX programs should not rely on the specific single-precision NaNs being generated. but single-precision instructions return an unspecified NaN. No rounding modifier.rn and instructions may be folded into a multiply-add.f32 are the same.mul}.f32 {div. mul.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.rp .target sm_20 . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f64 rsqrt.approx.f32 {div.

f32. . z.number. Table 48. testp Syntax Floating-Point Instructions: testp Test floating-point property.f64 }.infinite testp. // result is .f32 testp.op.normal testp.type d.f64 }. . January 24.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.f64 x. Instruction Set Table 47.finite testp. copysign requires sm_20 or later.f32. y.pred = { . b.notanumber. A. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.subnormal }. a.f32 copysign. B.0. and return the result as d. p. positive and negative zero are considered normal numbers.notanumber testp. .op p. not infinity). a.normal.infinite. not infinity) As a special case.0. true if the input is a subnormal number (not NaN.type = { . f0. copysign.type . X.type = { . . copysign. .finite. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f64 isnan.notanumber. testp. C. . testp requires sm_20 or later. 2010 83 .Chapter 8. . Introduced in PTX ISA version 2. testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . .infinite. testp.number testp.

sm_1x: add.f64 d. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. d.f64 requires sm_13 or later.rz. 84 January 24.f64 supports subnormal numbers.rn): . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rn.rm.rn. . Saturation modifier: .f32.0.f32 flushes subnormal inputs and results to sign-preserving zero.rm. Rounding modifiers (default is . . .sat}.ftz.f3. In particular. add Syntax Floating-Point Instructions: add Add two values. add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. subnormal numbers are supported.rz mantissa LSB rounds towards zero .f32 supported on all target architectures.rnd = { .PTX ISA Version 2.f32 f1. d = a + b.rnd}.f32 flushes subnormal inputs and results to sign-preserving zero. 1. b.rn mantissa LSB rounds to nearest even . add.f32 add{. .0f. requires sm_20 Examples @p add. . add{. .rp for add. 2010 .rm mantissa LSB rounds towards negative infinity .ftz}{. add.rnd}{.rp }. requires sm_13 for add. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers have the following target requirements: . add.f32 clamps the result to [0. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f2.ftz. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. NaN results are flushed to +0.sat. add.0]. a. a.0 Table 49. b.rz available for all targets .f64.0.rz.

a.rz mantissa LSB rounds towards zero . .rp for sub.rm.f3. requires sm_13 for sub.rn. subnormal numbers are supported.0].rz available for all targets .f32 flushes subnormal inputs and results to sign-preserving zero.rn. d = a .f32 c. 1.f32 sub{.f32 clamps the result to [0. Instruction Set Table 50. a.f32 supported on all target architectures. sub.0f. Rounding modifiers (default is .f64 requires sm_13 or later.f64 d. sub. sm_1x: sub.f64.rz.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub.f32 f1.0.Chapter 8. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. b.ftz. . b.rm. NaN results are flushed to +0. .rm mantissa LSB rounds towards negative infinity . sub.sat}.rnd = { .rp }. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.b. .ftz}{.f32 flushes subnormal inputs and results to sign-preserving zero. a. . In particular. sub{. January 24.rnd}. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. Rounding modifiers have the following target requirements: . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.b. 2010 85 .f32.0.rn mantissa LSB rounds to nearest even .f64 supports subnormal numbers.f2. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. sub Syntax Floating-Point Instructions: sub Subtract one value from another.sat.rn. d. requires sm_20 Examples sub.rnd}{. sub. . Saturation modifier: sub.rn): .

In particular.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 2010 . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. sm_1x: mul.0. mul{.f64 supports subnormal numbers.rn): . mul. For floating-point multiplication.rn. requires sm_13 for mul.radius. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. mul. . mul. a.f64 d. a. d = a * b.ftz}{.ftz. b.f32 circumf.rnd = { . Rounding modifiers have the following target requirements: . mul Syntax Floating-Point Instructions: mul Multiply two values. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.pi // a single-precision multiply 86 January 24.rnd}.rm mantissa LSB rounds towards negative infinity .rz available for all targets .rp }. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 mul{. all operands must be the same size.0 Table 51.f32. d.f32 clamps the result to [0.rn mantissa LSB rounds to nearest even .0.sat}.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero.rm. NaN results are flushed to +0.sat.rz mantissa LSB rounds towards zero .f64.PTX ISA Version 2. requires sm_20 Examples mul. . . Saturation modifier: mul. Rounding modifiers (default is .0].rm. . mul.rp for mul.ftz. b.0f.f32 flushes subnormal inputs and results to sign-preserving zero. . . subnormal numbers are supported.f32 supported on all target architectures.rz. Description Semantics Notes Compute the product of two values.rnd}{. 1.

Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f32 computes the product of a and b to infinite precision and then adds c to this product. subnormal numbers are supported. fma.f64 computes the product of a and b to infinite precision and then adds c to this product.4. Saturation: fma.sat}. d.rnd.y.f32 requires sm_20 or later.ftz.f32 clamps the result to [0. Instruction Set Table 52.0f. 2010 87 . fma.0.0.f64 w. PTX ISA Notes Target ISA Notes Examples January 24. fma.rnd{.f64 d.x.f64 is the same as mad.f64 requires sm_13 or later.rm. d = a*b + c. a. again in infinite precision.rz. .rn. Rounding modifiers (no default): .f32 fma.rn.b.ftz}{.f32 introduced in PTX ISA version 2.a. fma. b. The resulting value is then rounded to double precision using the rounding mode specified by .f64. @p fma. d. a. NaN results are flushed to +0.f32 is unimplemented in sm_1x.f32 fma.c. sm_1x: fma.rn mantissa LSB rounds to nearest even . fma.rn. b. fma. .rp }.rnd. .ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. c.f64 supports subnormal numbers.f64 introduced in PTX ISA version 1. fma.rm mantissa LSB rounds towards negative infinity . fma.rnd.0]. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma.rz mantissa LSB rounds towards zero .sat. c.f32 flushes subnormal inputs and results to sign-preserving zero. .Chapter 8.rnd = { . 1. fma.z. again in infinite precision. The resulting value is then rounded to single precision using the rounding mode specified by .

. The exception for mad.rn. mad.rz mantissa LSB rounds towards zero . mad.0]. For .f64 computes the product of a and b to infinite precision and then adds c to this product. c.target sm_1x d. c..f64. Unlike mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 computes the product of a and b to infinite precision and then adds c to this product. . fma. . a.f64}. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. mad.rnd.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.f64 d. The resulting value is then rounded to double precision using the rounding mode specified by . mad. b. again in infinite precision. Note that this is different from computing the product with mul. mad{.f64 supports subnormal numbers.PTX ISA Version 2.f64} is the same as fma. mad.ftz}{. 1. 88 January 24.f32 clamps the result to [0.f32 mad.f32 is when c = +/-0.rp }.f32 mad.f64 is the same as fma.f32).0.target sm_13 and later . For .rnd{. but the exponent is preserved. the treatment of subnormal inputs and output follows IEEE 754 standard.{f32. // .rm mantissa LSB rounds towards negative infinity .ftz.sat}. Description Semantics Notes Multiplies two values and adds a third.e. NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero.target sm_20: mad.target sm_20 d. sm_1x: mad. Saturation modifier: mad.sat.sat}. b. a. c.{f32.0. mad.rz. mad.rnd = { . and then the mantissa is truncated to 23 bits.rnd.f32 is identical to the result computed using separate mul and add instructions.target sm_1x: mad.f32 is implemented as a fused multiply-add (i.rn mantissa LSB rounds to nearest even . In this case. Rounding modifiers (no default): .ftz}{. 2010 . again in infinite precision. and then writes the resulting value into a destination register. subnormal numbers are supported.0 Table 53.f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to single precision using the rounding mode specified by .0f.rn. When JIT-compiled for SM 2. a. again in infinite precision.ftz. d = a*b + c. mad. where the mantissa can be rounded and the exponent will be clamped. // .f32 computes the product of a and b at double precision. mad.rnd. The resulting value is then rounded to double precision using the rounding mode specified by .rnd.f64 computes the product of a and b to infinite precision and then adds c to this product.0 devices.f32. // .rm. b.

a rounding modifier is required for mad.f64 requires sm_13 or later. In PTX ISA versions 2. Legacy mad. mad. Rounding modifiers have the following target requirements: .. requires sm_13 .rm. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.4 and later.f64.c.. 2010 89 . January 24.f64.rn. In PTX ISA versions 1.f64.0 and later..rn.rp for mad..rz.f32 for sm_20 targets.b. a rounding modifier is required for mad.f64 instructions having no rounding modifier will map to mad. requires sm_20 Examples @p mad.rm.f32 supported on all target architectures.rn..rp for mad.0.f32 d. Target ISA Notes mad.Chapter 8..a.f32.rz.

rn mantissa LSB rounds to nearest even . full-range approximation that scales operands to achieve better accuracy.rp }.approx. b.f32 div.f32 flushes subnormal inputs and results to sign-preserving zero. . one of . d = a / b.0 through 1.{rz. Examples 90 January 24.f64 requires sm_13 or later. and div. 2126]. approximate division by zero creates a value of infinity (with same sign as a). d. a.14159.rn. . zd. d.full.ftz. div. PTX ISA Notes div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. subnormal numbers are supported. stores result in d.f32 div.0. For b in [2-126.PTX ISA Version 2.ftz.rz mantissa LSB rounds towards zero . Fast.f32 div. approximate single-precision divides: div.ftz}.approx. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . div. div.rnd{.approx.f64 diam.full{. and rounding introduced in PTX ISA version 1.0 Table 54. b. div.4 and later.f32 requires sm_20 or later. a. 2010 .approx. a. computed as d = a * (1/b).approx.f64 d. .full. For PTX ISA version 1.full.f64 introduced in PTX ISA version 1.rnd = { .f64.f32 flushes subnormal inputs and results to sign-preserving zero.rp}. y.rnd. Explicit modifiers . or .rn.full. div.f64 supports subnormal numbers. a. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . div. .ftz. div.f64 defaults to div.f32. z. .ftz}. the maximum ulp error is 2. div.ftz.rm.3. div Syntax Floating-Point Instructions: div Divide one value by another. Target ISA Notes div. but is not fully IEEE 754 compliant and does not support rounding modifiers. The maximum ulp error is 2 across the full range of inputs. xd.approx.full.3.approx{.4. .f32 defaults to div.rnd.rn. Description Semantics Notes Divides a by b.f32 implements a relatively fast.f32 and div. // // // // fast. d. For PTX ISA versions 1. x. yd. Fast. Subnormal inputs and results are flushed to sign-preserving zero.rnd is required.rm mantissa LSB rounds towards negative infinity . b.f32 supported on all target architectures. b.f64 requires sm_20 or later.f32 div.f32 div. sm_1x: div.ftz.rz. div.ftz}.circum.f32 and div.rn.rm.f32 implements a fast approximation to divide.

neg.f0. subnormal numbers are supported. a. neg.f32 neg. subnormal numbers are supported. a. neg. abs.ftz. Negate the sign of a and store the result in d.f64 d.f32 supported on all target architectures. abs. d = |a|.ftz}. sm_1x: neg. Instruction Set Table 55.ftz. NaN inputs yield an unspecified NaN.f32 supported on all target architectures. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f0. neg. abs. January 24. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.Chapter 8. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. d = -a. Subnormal numbers: sm_20: By default.ftz.f64 supports subnormal numbers. abs. 2010 91 .ftz.f32 abs.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 x. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.0. d. Take the absolute value of a and store the result in d.f32 flushes subnormal inputs and results to sign-preserving zero. neg.f64 requires sm_13 or later.f64 d. sm_1x: abs.f32 x. Table 56. a. Subnormal numbers: sm_20: By default. d.ftz}.f64 requires sm_13 or later. neg{. abs.0. abs{. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. NaN inputs yield an unspecified NaN.f64 supports subnormal numbers.

0.f64 d.f64 f0. min{. b.b.f32 supported on all target architectures. a. max.f32 flushes subnormal inputs and results to sign-preserving zero. d d d d = = = = NaN.ftz.f1. 2010 .ftz. b. d. b. sm_1x: max. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. Table 58.ftz. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. max.f32 flushes subnormal inputs and results to sign-preserving zero.b. Store the minimum of a and b in d.f64 supports subnormal numbers. (a > b) ? a : b.c.ftz}.f32 supported on all target architectures. b.z. sm_1x: min.f64 z. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. @p min. a.ftz. min.f32 max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. d. a. Store the maximum of a and b in d. subnormal numbers are supported.f32 min.f64 requires sm_13 or later.f32 max. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. (a < b) ? a : b. a. 92 January 24.f64 requires sm_13 or later. max.f2.f64 d.ftz}. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0 Table 57. b.0.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. a.c.x. a. max. min. min.f32 min. d d d d = = = = NaN. subnormal numbers are supported.f64 supports subnormal numbers.PTX ISA Version 2. b. min. max{.

rn.rnd. rcp.f32 rcp. rcp. Target ISA Notes rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64 defaults to rcp. General rounding modifiers were added in PTX ISA version 2. d.rz mantissa LSB rounds towards zero .ftz.f32 rcp. a.f64 d. d. one of . store result in d.rn.rm.0 over the range 1. 2010 93 .rnd{.f32.approx.ftz}.{rz. rcp.f32 rcp.rp}.rn. PTX ISA Notes rcp.f64 supports subnormal numbers.x.ftz. xi.ftz}.f32 implements a fast approximation to reciprocal.rn mantissa LSB rounds to nearest even .approx.0.f32 rcp. sm_1x: rcp.f64 ri.rz. a.approx{. Description Semantics Notes Compute 1/a. // fast. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. For PTX ISA versions 1.f32 supported on all target architectures. Input -Inf -subnormal -0.ftz were introduced in PTX ISA version 1. rcp.rnd is required. rcp. Instruction Set Table 59.0.ftz.approx.f64 introduced in PTX ISA version 1. rcp. The maximum absolute error is 2-23. rcp.3.rn. rcp.0 +0.ftz.0. subnormal numbers are supported.4.4 and later.approx.Chapter 8.rp }.0-2.0 through 1. rcp. . For PTX ISA version 1.0 +subnormal +Inf NaN Result -0. d = 1 / a. and rcp. .f64 requires sm_13 or later.f64 requires sm_20 or later. a.f32 requires sm_20 or later.rnd.r. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rn.approx or .0 -Inf -Inf +Inf +Inf +0.approx and .x.rn.f64 and explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero.f32 defaults to rcp.f64. xi. rcp.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm.f32 flushes subnormal inputs and results to sign-preserving zero. . Examples January 24.rnd = { .f32 and rcp.

rz.approx or . sqrt.0 Table 60. one of .f32.f64 r. a. store in d.f32 sqrt.rn. sqrt.rm mantissa LSB rounds towards negative infinity .{rz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx.f64 requires sm_13 or later. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. and sqrt. sqrt. subnormal numbers are supported. a.PTX ISA Version 2.f64 d.0 +subnormal +Inf NaN Result NaN NaN -0.rm.rn. Target ISA Notes sqrt. .f64 requires sm_20 or later. Input -Inf -normal -subnormal -0.ftz.0 +0. 2010 .0 -0.approx. sqrt. d = sqrt(a).4 and later. The maximum absolute error for sqrt. // IEEE 754 compliant rounding .rn.rp}.approx. sqrt.rn.f32 sqrt.rn.approx.f32 sqrt.f64.rp }.f64 supports subnormal numbers.0 +0.0 +0. sm_1x: sqrt. sqrt.ftz were introduced in PTX ISA version 1.x.rm.ftz}.f32 and sqrt. sqrt.ftz.rnd{.rn mantissa LSB rounds to nearest even .f32 implements a fast approximation to square root. .ftz. sqrt. Description Semantics Notes Compute sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero. General rounding modifiers were added in PTX ISA version 2.rn.f32 supported on all target architectures.x.rnd. Examples 94 January 24.0. r.0. PTX ISA Notes sqrt. a.f32 sqrt. // IEEE 754 compliant rounding d.f64 defaults to sqrt.approx.rnd.rz mantissa LSB rounds towards zero .0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .3.4.approx{.f64 introduced in PTX ISA version 1. approximate square root d.0 through 1. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.rnd is required.f32 defaults to sqrt. r.rnd = { . // fast.f32 is TBD.f32 requires sm_20 or later.x. .ftz}.approx and . sqrt. For PTX ISA versions 1.f64 and explicit modifiers .ftz. For PTX ISA version 1.

approx implements an approximation to the reciprocal square root. rsqrt. Explicit modifiers .0 +0. d = 1/sqrt(a).4. ISR. rsqrt. Instruction Set Table 61.f32 defaults to rsqrt.approx. subnormal numbers are supported. store the result in d.ftz. For PTX ISA version 1.f32 is 2-22. Compute 1/sqrt(a). January 24.f64 defaults to rsqrt.f32 rsqrt. and rsqrt.approx.f64 isr. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.approx.f64 is emulated in software and are relatively slow.f64 requires sm_13 or later. rsqrt.ftz were introduced in PTX ISA version 1.f32.f32 and rsqrt. Target ISA Notes Examples rsqrt.approx. d. X.f64 supports subnormal numbers. sm_1x: rsqrt.4 and later. a. the . The maximum absolute error for rsqrt.f64 is TBD.ftz.0.approx.f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA versions 1. rsqrt.f64 d.approx.3.ftz.0 through 1.0 NaN The maximum absolute error for rsqrt. PTX ISA Notes rsqrt. a. Input -Inf -normal -subnormal -0.approx modifier is required. 2010 95 .Chapter 8.4 over the range 1. rsqrt. Subnormal numbers: sm_20: By default.0-4. rsqrt.f64 were introduced in PTX ISA version 1. rsqrt.f32 rsqrt. Note that rsqrt.f64.f32 supported on all target architectures.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f32 flushes subnormal inputs and results to sign-preserving zero.0.ftz}. x.approx{.approx and .

0 +0.approx. 2010 . d = sin(a).f32 defaults to sin.approx. Input -Inf -subnormal -0.0.0 NaN NaN The maximum absolute error is 2-20.f32 d. Subnormal numbers: sm_20: By default.approx.f32 flushes subnormal inputs and results to sign-preserving zero. sin. subnormal numbers are supported.0 Table 62.0 +subnormal +Inf NaN Result NaN -0.0 through 1. Explicit modifiers . sin.ftz. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.f32 introduced in PTX ISA version 1. sin. a.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.approx{. the .PTX ISA Version 2.9 in quadrant 00.approx modifier is required.4. sin.approx and .0 +0. a. For PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures. 96 January 24.f32. For PTX ISA versions 1. PTX ISA Notes sin. sin.3.ftz.4 and later.ftz}.0 -0. Find the sine of the angle a (in radians).ftz introduced in PTX ISA version 1.f32 implements a fast approximation to sine.f32 sa.0 +0.

For PTX ISA versions 1. a. Input -Inf -subnormal -0.approx.f32 d.0 through 1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.4. Instruction Set Table 63. Explicit modifiers . d = cos(a).approx{.0 +subnormal +Inf NaN Result NaN +1.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 introduced in PTX ISA version 1.ftz}.f32 defaults to cos. Find the cosine of the angle a (in radians). 2010 97 .0 +1.ftz.4 and later. PTX ISA Notes cos. cos.approx modifier is required. the .Chapter 8. cos. For PTX ISA version 1.f32 ca. cos.0 +1.f32.approx. cos. cos. a.ftz.3.ftz introduced in PTX ISA version 1.0.approx.0 NaN NaN The maximum absolute error is 2-20. Target ISA Notes Examples Supported on all target architectures.f32 implements a fast approximation to cosine. subnormal numbers are supported. Subnormal numbers: sm_20: By default.9 in quadrant 00.approx and .0 +0. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +1. January 24.

lg2. lg2. subnormal numbers are supported. a. The maximum absolute error is 2-22. PTX ISA Notes lg2. Subnormal numbers: sm_20: By default. lg2. For PTX ISA version 1. lg2. 98 January 24.0 +0. lg2.f32.ftz introduced in PTX ISA version 1. Explicit modifiers .3. Input -Inf -subnormal -0. For PTX ISA versions 1.ftz.approx. the .ftz.f32 defaults to lg2. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. d = log(a) / log(2).approx.f32 flushes subnormal inputs and results to sign-preserving zero.PTX ISA Version 2. sm_1x: Subnormal inputs and results to sign-preserving zero.approx{.6 for mantissa.f32 implements a fast approximation to log2(a).f32 Determine the log2 of a.0 Table 64.0 through 1.4 and later.ftz. a. 2010 .approx and .4.ftz}.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Target ISA Notes Examples Supported on all target architectures.f32 introduced in PTX ISA version 1.approx.f32 la.0.approx modifier is required.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

{!}c.type = { . num. Integer Notes Floating Point Notes The ordered comparisons are eq. gt. ge. If either operand is NaN. and (optionally) combine this result with a predicate value by applying a Boolean operator.type setp. setp.dtype. @q setp.f32 comparisons.eq. .f32 flushes subnormal inputs to sign-preserving zero.BoolOp{.f64 source type requires sm_13 or later. le. . .PTX ISA Version 2. and nan returns true if either operand is NaN. Semantics t = (a CmpOp b) ? 1 : 0. ne. ltu. setp with .and. .s32.u16. and hs for lower. ltu. ne. gtu.ftz}. le.u64. The destinations p and q must be . ls. gt. gtu. lo.ftz}. q = BoolOp(!t. If both operands are numeric values (not NaN). subnormal numbers are supported.s64. This result is written to the first destination operand. and can be one of: eq.n. . setp. num returns true if both operands are numeric values (not NaN). The comparison operator is a suffix on the instruction. ge.u32 p|q. gt. . A related value computed using the complement of the compare result is written to the second destination operand.f64 }. b. gt. higher.b16. respectively.type . bit-size comparisons are eq and ne.0 Table 67. Applies to all numeric types.b32. hi. p[|q]. leu. c).r. and higher-or-same may be used instead of lt. or. Subnormal numbers: sm_20: By default. the comparison operators lo. . neu. hs equ. setp. ne.b. then these comparisons have the same result as their ordered counterparts. For unsigned values. ge. then the result of these comparisons is true. . neu. a. Modifier .pred variables. the result is false. The signed and unsigned comparison operators are eq. c). xor.a. sm_1x: setp. . b.u32. loweror-same. ge.s32 setp.CmpOp{. lt. unordered versions are included: equ. lt.f64 supports subnormal numbers.CmpOp.dtype.0. ls. le. p = BoolOp(t. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz applies only to . p[|q]. The untyped. If either operand is NaN. lt.B) is one of: and. . le. geu. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.s16. a. 2010 .lt.b64. leu.f32 flushes subnormal inputs to sign-preserving zero.ftz.i. To aid comparison operations in the presence of NaN values.f32. p.dtype. geu. 102 January 24. hi. nan The Boolean operator BoolOp(A. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.

ftz applies only to . c. subnormal numbers are supported. .s64. sm_1x: slct.ftz. C.x. .xp. b.type d.f32 comparisons. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32.u64. Introduced in PTX ISA version 1.s32 selp. .dtype.p. If c ≥ 0.f32 flushes subnormal values of operand c to sign-preserving zero. If c is True. z.s32 slct{. selp.f64 }.f32 flushes subnormal values of operand c to sign-preserving zero. slct. . .u32. Operands d.dtype = { .u32.f32. slct Syntax Comparison and Selection Instructions: slct Select one source operand. b. a.u32.s32 x. Operand c is a predicate.u64.g.f64 }. . selp. slct.f32.ftz. slct. b. a.u16. Instruction Set Table 68. the comparison is unordered and operand b is selected.b64.dtype. negative zero equals zero.0. Subnormal numbers: sm_20: By default. slct.f64 requires sm_13 or later. Semantics Floating Point Notes January 24. d. . and b are treated as a bitsize type of the same width as the first instruction type. Table 69. b otherwise.f32 A. operand c must match the second instruction type.r. Description Conditional selection. based on the sign of the third operand. a. The selected input is copied to the output without modification. otherwise b is stored in d. and operand a is selected.s16.u16. . @q selp.Chapter 8. fval. selp Syntax Comparison and Selection Instructions: selp Select between source operands. based on the value of the predicate source operand. .s32. a is stored in d. 2010 103 . .0. slct. f0.f32 comparisons. . For . and b must be of the same type.ftz}.type = { .b16.dtype. a is stored in d. If operand c is NaN. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. .s16.b32. c. a. . B. y. d = (c == 1) ? a : b. .s32. . d = (c >= 0) ? a : b. . a. . . Operands d. .b16.f32 r0. Modifier . .f32 d.b64.dtype. c. val.s64. .f64 requires sm_13 or later.t.u64. and operand a is selected. .

Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. This permits bit-wise operations on floating point values without having to define a union to access the bits. xor.0 8.PTX ISA Version 2. performing bit-wise operations on operands of any type. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. Instructions and. provided the operands are of the same size. and not also operate on predicates. or.7.4. 2010 .

Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. . The size of the operands must match. Introduced in PTX ISA version 1. sign.type = { .type d.pred.b32.fpvalue.type = { . Allowed types include predicate registers.r. January 24. but not necessarily the type.q. Table 71.b16. .b32 and. or Syntax Logic and Shift Instructions: or Bitwise OR.Chapter 8. Instruction Set Table 70. .type d. d = a | b.r. 2010 105 .b32.0x80000000. and.b16.0. . d = a & b.pred p. . but not necessarily the type.pred. or. b.b32 mask mask. Allowed types include predicate registers. and.0. Introduced in PTX ISA version 1.q. Supported on all target architectures.b64 }. a.b32 x. and Syntax Logic and Shift Instructions: and Bitwise AND. .b64 }. . a. . or. b. The size of the operands must match. Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.0x00010001 or.

Supported on all target architectures.b64 }. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.type d. The size of the operands must match. not Syntax Logic and Shift Instructions: not Bitwise negation. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.pred p.b32.0x0001.0 Table 72.b64 }. 2010 . b.b32. . one’s complement. The size of the operands must match.b16. a.q. d. . .mask.a. a. but not necessarily the type.0. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. . Table 73.b64 }. not.b32. The size of the operands must match.type = { . .0.b32 mask. a.0. . xor.pred. Supported on all target architectures.b16. but not necessarily the type. cnot. d = (a==0) ? 1 : 0.type = { .b16.q. cnot. Supported on all target architectures. d = a ^ b.type d. not.PTX ISA Version 2. Allowed types include predicates. .b32 xor. but not necessarily the type. xor.type d. . Introduced in PTX ISA version 1.b16 d.pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. . .b32 d.x.type = { . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. 106 January 24. d = ~a. Allowed types include predicate registers. not. .r. Table 74. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).

zero-fill on right. shr Syntax Logic and Shift Instructions: shr Shift bits right. a. 2010 107 .u32. The sizes of the destination and first source operand must match. but not necessarily the type. regardless of the instruction type. . .type = { . shl. . a. shr.2. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Shift amounts greater than the register width N are clamped to N. sign or zero fill on left.type d. Supported on all target architectures. .s16. d = a << b.u64.a. i.s64 }.b64 }. b. The b operand must be a 32-bit value. . Introduced in PTX ISA version 1. .s32.i. . . .type = { . Bit-size types are included for symmetry with SHL. k. shr.b16. shl Syntax Logic and Shift Instructions: shl Shift bits left. Introduced in PTX ISA version 1.u16 shr. shl. unsigned and untyped shifts fill with 0.2.a.i. regardless of the instruction type. . Signed shifts fill with the sign bit. Instruction Set Table 75. The b operand must be a 32-bit value. b.s32 shr.b32. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. . . Shift amounts greater than the register width N are clamped to N. Supported on all target architectures.j.b64. PTX ISA Notes Target ISA Notes Examples Table 76.u16. PTX ISA Notes Target ISA Notes Examples January 24.b32 q.0.b32.b16 c. but not necessarily the type.0.1.type d. The sizes of the destination and first source operand must match.Chapter 8.b16. d = a >> b.

or shared state spaces. The cvta instruction converts addresses between generic and global. ldu. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. Instructions ld.5. and sust support optional cache operations. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. ld.0 8. local. and from state space to state space. possibly converting it from one format to another. and st operate on both scalar and vector types. mov. prefetchu isspacep cvta cvt 108 January 24.PTX ISA Version 2. 2010 .7. suld. st. Data Movement and Conversion Instructions These instructions copy data from place to place.

lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. when applied to a local address. The ld.lu load last use operation.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. evict-first. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. the cache operators have the following definitions and behavior.ca. the second thread may get stale L1 cache data. . . which allocates cache lines in all levels (L1 and L2) with normal eviction policy. likely to be accessed again. and cache only in the L2 cache. Instruction Set 8. Global data is coherent at the L2 level. to allow the thread program to poll a SysMem location written by the CPU. As a result of this request. any existing cache lines that match the requested address in L1 will be evicted. .ca.lu operation. For sm_20 and later. fetch again). rather than the data stored by the first thread. and a second thread loads that address via a second L1 cache with ld.5. A ld.cg Cache at global level (cache in L2 and below.ca loads cached in L1. if the line is fully covered. The cache operators require a target architecture of sm_20 or later. The compiler / programmer may use ld.1. The ld. Operator . When ld.cv to a frame buffer DRAM address is the same as ld.Chapter 8. Use ld.7.lu instruction performs a load cached streaming operation (ld. not L1). The ld. invalidates (discards) the local L1 line following the load.cs) on global addresses. but multiple L1 caches are not coherent for global data.cs is applied to a Local window address.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. it performs the ld. . If one thread stores to global memory via one L1 cache. 2010 109 . likely to be accessed once.0 introduces optional cache operators on load and store instructions.cs Cache streaming. Cache Operators PTX 2.cs. The default load instruction cache operation is ld.lu Last use.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cg to cache loads only globally. The ld.cv Cache as volatile (consider cached system memory lines stale. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. January 24. Table 77. bypassing the L1 cache.

0 Table 78.PTX ISA Version 2. and marks local L1 lines evict-first. .cg is the same as st.cs Cache streaming. and discard any L1 lines that match. bypassing its L1 cache. and a second thread in a different SM later loads from that address via a different L1 cache with ld. rather than get the data from L2 or memory stored by the first thread. in which case st.wt Cache write-through (to system memory). The driver must invalidate global L1 cache lines between dependent grids of thread arrays. and cache only in the L2 cache. If one thread stores to global memory. to allow a CPU program to poll a SysMem location written by the GPU with st. not L1).cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. but st. the second thread may get a hit on stale L1 cache data. The default store instruction cache operation is st. The st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. which writes back cache lines of coherent cache levels with normal eviction policy.cg to cache global store data only globally. st. However. Addresses not in System Memory use normal write-back.wt.cg Cache at global level (cache in L2 and below. bypassing the L1 cache. . Use st. 2010 .wb for global data. 110 January 24.wt store write-through operation applied to a global System Memory address writes through the L2 cache. .ca loads. Global stores bypass L1. The st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. In sm_20. Operator .wb.ca. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.cg to local memory uses the L1 cache. likely to be accessed once.wb could write-back global store data from L1. Future GPUs may have globally-coherent L1 caches. regardless of the cache operation.

the generic address of a variable declared in global. d.. avar. Note that if the address of a device function parameter is moved to a register.s64. . d. the parameter will be copied onto the stack and the address will be in the local state space.b16.u32 mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.0.Chapter 8.u32 mov. // get address of variable // get address of label or function .type d. The generic address of a variable in global.const. .b64. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. label. .v. or shared state space. and . local.f64 requires sm_13 or later. A.u64. // address is non-generic. Description . mov.f32. mov. . .s16. For variables declared in . mov.0.u32 d.u32. or function name.. . the address of the variable in its state space) into the destination register. 2010 111 .e.type mov. k. d = &avar.u16 mov.type = { . local. variable in an addressable memory space. special register. Semantics d = a.f32 mov. addr.local.type mov. myFunc. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. alternately. label.pred. mov places the non-generic address of the variable (i. local.f64 }. ptr. immediate.u16. ptr. i. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. Write register d with the value of a.b32. . Operand a may be a register. Instruction Set Table 79. d = sreg. . within the variable’s declared state space Notes Although only predicate and bit-size types are required. d.s32. Introduced in PTX ISA version 1. .a. Take the non-generic address of a variable in global. sreg.e. .1. d = &label.f32 mov.shared state spaces. or shared state space may be taken directly using the cvta instruction. u. a.global. . A[5]. .type mov.

15].7]. 2010 . mov. a[8. d.x | (a.{x.b. . d. // // // // a. d.x | (a.b64 { d.b32 // pack four 16-bit elements into ..15].u16 %x is a double.b64 { d. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.. a[16.31].x | (a. d.w << 48) d = a.x. a[32.15] } // unpack 8-bit elements from .. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).y << 32) // pack two 8-bit elements into ..w } = { a[0..y.y.b16. a[16.b64 }. d.x | (a.b have type .x.w}..u8 // unpack 32-bit elements from .y << 16) d = a.u32 x. .b32 { d. %x.y } = { a[0.x. a[48.y << 16) | (a.y << 8) | (a.w << 24) d = a.type d.b8 r.%r1. {r.a}.31] } // unpack 16-bit elements from .x | (a.z. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. a[16.b32 // pack two 16-bit elements into . Description Write scalar register d with the packed value of vector register a. or write vector register d with the unpacked values from scalar register a.y << 8) d = a..x.b32 mov. .b}. a.31] } // unpack 8-bit elements from .b64 mov.z.b64 // pack two 32-bit elements into . d.63] } // unpack 16-bit elements from . a[8.31]. Semantics d = a.w } = { a[0.b32 mov.g. d. lo.b16 { d. mov.z << 16) | (a.b32 { d.b64 112 January 24.hi are .x. {lo.y.y } = { a[0. d.PTX ISA Version 2..z << 32) | (a.b16 // pack four 8-bit elements into .y } = { a[0.7]. a[24..23].g.15].b32.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.{a.0.type = { ..z.0 Table 80. a[32.b.y.b32 %r1. Supported on all target architectures. For bit-size types. %r1.a have type ..w have type .. d..z..hi}.47].

volatile.b16.volatile introduced in PTX ISA version 1.s64. .cop}. .reg state space.type = { .e.u8. [a].const space suffix may have an optional bank number to indicate constant banks other than bank zero. The value loaded is sign-extended to the destination register width for signed integers.b64.shared }. Cache operations are not permitted with ld.ss = { .v4 }.lu. for example.ss}{. . the resulting behavior is undefined. Generic addressing may be used with ld. .f16 data may be loaded using ld. *a. or the instruction may fault.ca. The address must be naturally aligned to a multiple of the access size. . Addresses are zero-extended to the specified width as needed.ss}.shared spaces to inhibit optimization of references to volatile memory. . an address maps to global memory unless it falls within the local memory window or the shared memory window. In generic addressing.global.vec.volatile may be used with .b16. Semantics d d d d = = = = a.u16. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. d.f32 or . . [a].v2.e.cop}.vec. If an address is not properly aligned. [a].cg.type d. This may be used. i.global and . . or [immAddr] an immediate absolute byte address (unsigned.cs. . an integer or bit-size type register reg containing a byte address.cop = { .local. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .type ld{. 32-bit).b8. PTX ISA Notes January 24.type ld. Generic addressing and cache operations introduced in PTX ISA 2. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f32. .ss}. A destination register wider than the specified type may be used.type .vec = { . to enforce sequential consistency between threads accessing shared memory.b32. 32-bit).volatile{. The address size may be either 32-bit or 64-bit.s16. perform the load using generic addressing. and then converted to .cv }. The . Description Load register variable d from the location specified by the source address operand a in specified state space. *(immAddr). . .f64 using cvt.s8.volatile. . . d. . Within these windows. ld. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . . .param. and is zeroextended to the destination register width for unsigned and bit-size types. 2010 113 . . . [a]. If no state space is given. and truncated if the register width exceeds the state space address width for the target architecture.1. d. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.volatile{. *(a+immOff).u32.f64 }.0. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. . ld. i.ss}{.Chapter 8. the access may proceed by silently masking off low-order address bits to achieve proper rounding. ld introduced in PTX ISA version 1.s32. Instruction Set Table 81. an address maps to the corresponding location in local or shared memory.. .u64. ld{.0. . . .const.

[p+4].b32 ld.f32.shared.const[4].0 Target ISA Notes ld. Cache operations require sm_20 or later.v4. Generic addressing requires sm_20 or later. // immediate address %r.[p+-8].f16 d.s32 ld.global. 2010 . %r.b32 ld. x.const.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.f32 ld.f64 requires sm_13 or later.b64 ld.b32 ld.PTX ISA Version 2. // load .[a].[240].global.[buffer+64].local. Q.[fs].[p].local.b16 cvt. d. // access incomplete array x. // negative offset %r. ld.%r.

perform the load using generic addressing.f32. where the address is guaranteed to be the same across all threads in the warp.e. .u64. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.type ldu{.type d. *(immAddr).Chapter 8. Instruction Set Table 82. i. The addressable operand a is one of: [avar] the name of an addressable variable var. . A destination register wider than the specified type may be used. . . . . For ldu. and then converted to . or the instruction may fault.b32.f64 using cvt.e.s8. ldu{.b8. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .ss = { .vec. *a.b16.global.v4. and truncated if the register width exceeds the state space address width for the target architecture. // state space .f32 or . Addresses are zero-extended to the specified width as needed.v2. [a].f32 d. . d. A register containing an address may be declared as a bit-size type or integer type. ldu.s16.s32. The address must be naturally aligned to a multiple of the access size.0. .type = { .u8. *(a+immOff). . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. ldu. the resulting behavior is undefined. PTX ISA Notes Target ISA Notes Examples January 24. Semantics d d d d = = = = a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .f16 data may be loaded using ldu. Introduced in PTX ISA version 2. and is zeroextended to the destination register width for unsigned and bit-size types.vec = { . .[p].f32 Q.u32.u16. an address maps to global memory unless it falls within the local memory window or the shared memory window. [areg] a register reg containing a byte address. Within these windows. 32-bit).global.global }. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. // load from address // vec load from address .reg state space.[p+4]. 32-bit). an address maps to the corresponding location in local or shared memory..b16. . . If an address is not properly aligned. The value loaded is sign-extended to the destination register width for signed integers. i. 2010 115 . or [immAddr] an immediate absolute byte address (unsigned.[a].s64.f64 requires sm_13 or later.ss}. .ss}.global.f64 }.v4 }. ldu.b64. The data at the specified address must be read-only. The address size may be either 32-bit or 64-bit. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ldu. only generic addresses that map to global memory are legal.b32 d. In generic addressing. If no state space is given. . . [a].

vec . st.cop}. . The lower n bits corresponding to the instruction-type width are stored to memory.b32.vec. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.global and . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.1.ss}{.cg.wb. 2010 .vec. the resulting behavior is undefined. In generic addressing. .b16.ss}. If an address is not properly aligned. . b.shared spaces to inhibit optimization of references to volatile memory.volatile may be used with .0 Table 83.global. { .volatile. [a]. .type st{. .s16. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.type [a]. st. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. Generic addressing may be used with st. an address maps to the corresponding location in local or shared memory. .f32.b16.ss}{. . .reg state space.f64 requires sm_13 or later.volatile{.u16. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. .type .ss . an integer or bit-size type register reg containing a byte address. .f16 data resulting from a cvt instruction may be stored using st. 32-bit).ss}.type = = = = {. The address size may be either 32-bit or 64-bit.volatile.cop}. Cache operations require sm_20 or later.b8. 32-bit).u32.local. b. st. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b64.cs. The address must be naturally aligned to a multiple of the access size.v4 }.u8. *d = a.shared }. Within these windows. to enforce sequential consistency between threads accessing shared memory.. If no state space is given. { . [a]. A source register wider than the specified type may be used.e.f64 }.wt }.volatile introduced in PTX ISA version 1. [a]. st introduced in PTX ISA version 1. and truncated if the register width exceeds the state space address width for the target architecture. PTX ISA Notes Target ISA Notes 116 January 24.e. Semantics d = a. .PTX ISA Version 2.0. .0. *(immAddr) = a. Cache operations are not permitted with st. perform the store using generic addressing. .u64.s64.cop . or the instruction may fault. i. for example. . . the access may proceed by silently masking off low-order address bits to achieve proper rounding. Generic addressing and cache operations introduced in PTX ISA 2.v2. st{. Addresses are zero-extended to the specified width as needed. This may be used. or [immAddr] an immediate absolute byte address (unsigned. i. b. . an address maps to global memory unless it falls within the local memory window or the shared memory window.s32. b. .volatile{. *(d+immOffset) = a. { .s8. . . Generic addressing requires sm_20 or later.type st.

[q+4].b. // %r is 32-bit register // store lower 16 bits January 24. [p].b32 st. // immediate address %r.a.a.global.b32 st.%r.r7. // negative offset [100].local.v4.local.%r.f32 st. 2010 117 . Instruction Set Examples st.Chapter 8.Q. [q+-8].b16 [a].f16.local.s32 cvt.f32 st.s32 st. [fs].global.

e. 118 January 24. and no operation occurs if the address maps to a local or shared memory location.L1.level = { .L1 [ptr]. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. prefetch{.local }.0 Table 84. // prefetch to data cache // prefetch to uniform cache . prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. 2010 . . If no state space is given. the prefetch uses generic addressing. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. Addresses are zero-extended to the specified width as needed. 32-bit). . or [immAddr] an immediate absolute byte address (unsigned. i.space}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.level prefetchu.global. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. A prefetch into the uniform cache requires a generic address. A prefetch to a shared memory location performs no operation.space = { .global. prefetch.L1 [addr].L1 [a]. an address maps to the corresponding location in local or shared memory. and truncated if the register width exceeds the state space address width for the target architecture. 32-bit). an address maps to global memory unless it falls within the local memory window or the shared memory window.PTX ISA Version 2. prefetch and prefetchu require sm_20 or later. Within these windows. In generic addressing.L2 }. in specified state space. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.0. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. The address size may be either 32-bit or 64-bit. . a register reg containing a byte address. prefetchu. [a].

The source and destination addresses must be the same size.space = { . . or vice-versa. var.0.u32 p.local. isspacep. The source address operand must be a register of type . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.u32 or . . svar. cvta.global.global. // get generic address of svar cvta.to.u64 }.space p. . local.to. 2010 119 .space = { .shared isglbl.pred .global. or shared address to a generic address. a. islcl. // local. or vice-versa.space.size . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. or shared address cvta. For variables declared in global. cvta. the generic address of the variable may be taken using cvta. // result is . lptr. .u32. A program may use isspacep to guard against such incorrect behavior.size cvta. local.shared }.u64. // convert to generic address // get generic address of var // convert generic address to global.local isspacep. or shared state space.local.genptr.pred. isshrd. January 24. local.Chapter 8.0. cvta. sptr. p.u32 gptr.space. a.size = { . a. or shared state space to generic.u64.u64 or cvt. Introduced in PTX ISA version 2. Instruction Set Table 85. Take the generic address of a variable declared in global. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. p. or shared state space.lptr.shared. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.global isspacep. PTX ISA Notes Target ISA Notes Examples Table 86. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. .u32 p. The destination register must be of type . cvta requires sm_20 or later. Use cvt. isspacep requires sm_20 or later.local.space. When converting a generic address into a global.size p. local. local.u32 to truncate or zero-extend addresses. Description Convert a global.shared }. or shared address. gptr. . isspacep.u32.

f32 float-tofloat conversions with integer rounding. . . . . // integer rounding // fp rounding .rzi round to nearest integer in the direction of zero .s64.0 Table 87. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.atype = { .f32 float-to-integer conversions and cvt.ftz.u16. Integer rounding is required for float-to-integer conversions. a.e.dtype. d = convert(a). Integer rounding modifiers: . sm_1x: For cvt. Description Semantics Integer Notes Convert between different types and sizes.s32. For cvt. .u8.dtype.s16. .f64 }. . .ftz}{.irnd}{.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.sat}.ftz}{.s8. subnormal inputs are flushed to signpreserving zero. For float-to-integer conversions. d..u32.u64. i. and for same-size float-tofloat conversions where the value is rounded to an integer.irnd = { .4 and earlier.sat For integer destination types. subnormal inputs are flushed to signpreserving zero.f32 float-tofloat conversions with integer rounding. The optional . cvt{.f32. . Note that saturation applies to both signed and unsigned integer types. . subnormal numbers are supported.dtype. .rm.f32. Saturation modifier: .rmi. .frnd}{.ftz. i. .PTX ISA Version 2.dtype = . . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.sat is redundant. .ftz modifier may be specified in these cases for clarity.e. .sat limits the result to MININT.f16.f32 float-to-integer conversions and cvt. The compiler will preserve this behavior for legacy PTX code.rmi round to nearest integer in direction of negative infinity .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. Note: In PTX ISA versions 1.rni.atype d.ftz.MAXINT for the size of the operation. . choosing even integer if source is equidistant between two integers.rzi. . a.ftz. .dtype.rn.rp }. 2010 .rpi }. Integer rounding is illegal in all other instances. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.sat}. .rz. the result is clamped to the destination range by default. .atype cvt{.rni round to nearest integer.frnd = { .. 120 January 24. the .f32.

0]. subnormal numbers are supported.f32.4 or earlier. Floating-point rounding modifiers: . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . NaN results are flushed to positive zero. . cvt. and cvt. // note . Floating-point rounding is illegal in all other instances.f16. Applies to . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64 types.0.f32. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16.sat limits the result to the range [0. 2010 121 . Specifically. cvt.f32.sat For floating-point destination types.y. stored in floating-point format.i.rn mantissa LSB rounds to nearest even . // round to nearest int. .f16. The operands must be of the same size. Introduced in PTX ISA version 1.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.0.f32.rz mantissa LSB rounds towards zero .y. 1.r.f32 instructions. Saturation modifier: .ftz modifier may be specified in these cases for clarity. // float-to-int saturates by default cvt.f32. cvt to or from .f32. The optional .s32 f. The result is an integral value. if the PTX .f64.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later. Modifier .Chapter 8. result is fp cvt.f64 j.f32.version is 1.4 and earlier. cvt. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. Subnormal numbers: sm_20: By default. and .f32 x.rni. Note: In PTX ISA versions 1.f32 x.ftz behavior for sm_1x targets January 24. and for integer-to-float conversions.s32. The compiler will preserve this behavior for legacy PTX code.

PTX ISA Version 2. . mul.7. The advantage of independent mode is that textures and samplers can be mixed and matched.0 8. . The advantage of unified mode is that it allows 128 samplers.texref tex1 ) { txq. = nearest width height tsamp1. } = clamp_to_border. sampler.f32 r1.u32 r5. with the restriction that they correspond 1-to-1 with the 128 possible textures. r1. but the number of samplers is greatly restricted to 16.b32 r5.f32. sampler. and surface descriptors. 2010 .r4}. allowing them to be defined separately and combined at the site of usage in the program. [tex1]. [tex1].f32 r1.width.global .param . In the independent mode. r1.f32 r1.v4. [tex1. 122 January 24. Texture and Surface Instructions This section describes PTX instructions for accessing textures. {f1.f32 {r1. A PTX module may declare only one texturing mode. // get tex1’s tex.b32 r6.f32 r3. r6. r5. add.. // get tex1’s txq. add. and surfaces.u32 r5.entry compute_power ( .height. PTX supports the following operations on texture.r3.. div.target options ‘texmode_unified’ and ‘texmode_independent’. the file is assumed to use unified mode.target texmode_independent . Module-scope and per-entry scope definitions of texture. Texturing modes For working with textures and samplers. PTX has two modes of operation. r2.2d. Example: calculate an element’s power contribution as element’s power/total number of elements. add. . If no texturing mode is declared. r5.f2}]. and surface descriptors. sampler. and surface descriptors. In the unified mode. texture and sampler information each have their own handle. samplers. texture and sampler information is accessed through a single .texref handle.r2. Ability to query fields within texture.6. The texturing mode is selected using . r4. r3.samplerref tsamp1 = { addr_mode_0 filter_mode }.f32. sampler. r3. and surface descriptors: • • • Static initialization of texture. cvt. r1. r5.

e. Operand c is a scalar or singleton tuple for 1d textures.f2.f32 }.v4.v4.s32. If an address is not properly aligned. the square brackets are not required and .s32. .s32.r3.v4.1d. Unified mode texturing introduced in PTX ISA version 1.r2. .r2. the resulting behavior is undefined. . b.btype = { .. {f1.dtype = { . If no sampler is specified. and is a four-element vector for 3d textures. {f1}].s32.2d.f4}]. tex txq suld sust sured suq Table 88.v4. An optional texture sampler b may be specified. The instruction always returns a four-element vector of 32-bit values. 2010 123 . with the extra elements being ignored. where the fourth element is ignored. // explicit sampler .3d }. i. . PTX ISA Notes Target ISA Notes Examples January 24. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.f3. tex.btype d. is a two-element vector for 2d textures. . Description Texture lookup using a texture coordinate vector.u32. the sampler behavior is a property of the named texture. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.r3.dtype. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a.geom = { .0.5. d.v4 coordinate vectors are allowed for any geometry. c].r4}. Supported on all target architectures.r4}. [tex_a. // Example of independent mode texturing tex. .f32 {r1.geom. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.dtype.3d.Chapter 8. Instruction Set These instructions provide access to texture and surface memory.s32 {r1. . or the instruction may fault. [a.btype tex. c]. A texture base address is assumed to be aligned to a 16-byte address. Notes For compatibility with prior versions of PTX.geom.1d. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. sampler_x. [tex_a. //Example of unified mode texturing tex.f32 }.

tquery = { . In unified mode.PTX ISA Version 2.addr_mode_0. Query: .filter_mode. txq. . txq. linear } Integer from enum { wrap. clamp_ogl. // unified mode // independent mode 124 January 24. .b32 txq. Integer from enum { nearest. Operand a is a . sampler attributes are also accessed via a texref argument.depth.5.b32 %r1.height. [tex_A]. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.b32 d. txq.addr_mode_0 .filter_mode . 2010 . clamp_to_edge.filter_mode. and in independent mode sampler attributes are accessed via a separate samplerref argument. mirror. addr_mode_1.addr_mode_0. .b32 %r1.tquery. addr_mode_2 }. [a]. [smpl_B]. [tex_A]. // texture attributes // sampler attributes .height . [a].width. txq.addr_mode_1 .depth . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.squery = { .b32 %r1. .samplerref variable.width . . Supported on all target architectures.texref or . d.normalized_coords .squery. Description Query an attribute of a texture or sampler.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).width. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.0 Table 89.normalized_coords }.

trap . where the fourth element is ignored. then .v2. If the destination base type is . or .cs.b supported on all target architectures.p .f32 }. b].b32.geom{.3d }. suld. Instruction Set Table 90. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b8 .cg.f32. or the instruction may fault. size and type conversion is performed as needed to convert from the surface sample format to the destination type.dtype . suld.w}].u32. {f1.geom .v4.cop}. .clamp suld. or FLOAT data. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.clamp . then .v4 }.1d. [a.ca.trap introduced in PTX ISA version 1.b16. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. and cache operations introduced in PTX ISA version 2.p. The lowest dimension coordinate represents a sample offset rather than a byte offset.u32 is returned. is a two-element vector for 2d surfaces.cv }.clamp field specifies how to handle out-of-bounds addresses: .f2.vec .y. suld. b].geom{. . SNORM. . suld. additional clamp modifiers. Cache operations require sm_20 or later. suld.s32. {x}].r2}.trap suld. . If an address is not properly aligned.f3. [a.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. .cop . .. and is a four-element vector for 3d surfaces.p requires sm_20 or later.p. .clamp = = = = = = { { { { { { d. then .v4.3d requires sm_20 or later. .b64 }. A surface base address is assumed to be aligned to a 16-byte address. .b.b64. .trap {r1. // formatted . . the resulting behavior is undefined.s32. . Description Load from surface memory using a surface coordinate vector.b32.trap clamping modifier.u32.Chapter 8. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . Coordinate elements are of type .s32 is returned. .dtype. // cache operation none. .surfref variable.f32 is returned.trap. . if the surface format contains UINT data.1d.u32.f32 based on the surface format as follows: If the surface format contains UNORM. [surf_A.5. Operand a is a .b32.cop}.b . Target ISA Notes Examples January 24.f4}. if the surface format contains SINT data.dtype.b. or . suld. and A components of the surface format. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.p.vec. Operand b is a scalar or singleton tuple for 1d surfaces.v2.dtype . G.3d. B. If the destination type is .0.b. [surf_B.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. .s32. // for suld. suld. The . 2010 125 . // unformatted d. {x.clamp.e.p is currently unimplemented.clamp . suld. suld. sm_1x targets support only the .f32. Destination vector elements corresponding to components that do not appear in the surface format are not written. and the size of the data transfer matches the size of destination operand d.z.zero }. the surface sample elements are converted to . // for suld.2d.s32.b performs an unformatted load of binary data. i. .

e.geom{. These elements are written to the corresponding surface sample components. G.ctype .cg.v4. B.p.b supported on all target architectures.cop . . . The size of the data transfer matches the size of source operand c. . b]. If an address is not properly aligned.{u32. then .b.clamp . size and type conversions are performed as needed between the surface sample format and the destination type.ctype. [surf_B. . A surface base address is assumed to be aligned to a 16-byte address.f2.p requires sm_20 or later. and A surface components.u32. Operand a is a . 2010 .clamp sust. c. .p performs a formatted store of a vector of 32-bit data values to a surface sample.f32.f32} are currently unimplemented.PTX ISA Version 2.ctype. .geom{. .f3. .vec.b. Target ISA Notes Examples 126 January 24. sust.b // for sust. [a.p Description Store to surface memory using a surface coordinate vector. . and is a four-element vector for 3d surfaces.trap sust.2d.s32 is assumed.s32. The source vector elements are interpreted left-to-right as R.w}]. The lowest dimension coordinate represents a sample offset rather than a byte offset.wt }.f32. i. sust. {x.b16.f32 }. If the source type is .b8 . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.clamp field specifies how to handle out-of-bounds addresses: . sust. or FLOAT data.cop}.cop}.surfref variable.v4 }. .cs. sust.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. if the surface format contains UINT data. or .s32. sust. .b32. .. // unformatted // formatted . if the surface format contains SINT data.trap introduced in PTX ISA version 1.s32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.trap clamping modifier. sust.trap [surf_A.z.f32 is assumed. Source elements that do not occur in the surface sample are ignored.vec .zero }.clamp .geom .u32.3d. the resulting behavior is undefined. sust. Coordinate elements are of type . SNORM. b].0 Table 91. Operand b is a scalar or singleton tuple for 1d surfaces.v2.1d.0. .trap .clamp = = = = = = { { { { { { [a. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.b64 }. . . none.b. and cache operations introduced in PTX ISA version 2. If the source base type is .b32. The source data is then converted from this type to the surface sample format.trap.b64. The . sust Syntax Texture and Surface Instructions: sust Store to surface memory.p. sust. {r1. Cache operations require sm_20 or later. then .clamp.p. is a two-element vector for 2d surfaces.5.u32 is assumed.s32.y.b32.r2}. .b performs an unformatted store of binary data. or the instruction may fault.3d }. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. additional clamp modifiers. . then .p.v2.wb. {x}]. {f1.ctype . // for sust. . Surface sample components that do not occur in the source vector will be written with an unpredictable value. sust.3d requires sm_20 or later. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.1d.vec. where the fourth element is ignored.f4}. . sm_1x targets support only the . c.

Instruction Set Table 92. . r1. The instruction type is restricted to . r1. A surface base address is assumed to be aligned to a 16-byte address.b.0.1d.u64. if the surface format contains SINT data.s32 or .b .min. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . sured.op = { . . Reduction to surface memory using a surface coordinate vector. and .min.b performs an unformatted reduction on . . .b32. Operand a is a .s32. .max. min and max apply to . {x.s32. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.u32.s32.ctype.s32 is assumed. // byte addressing sured. then .ctype = { .c.y}].clamp [a. .zero }. January 24. The lowest dimension coordinate represents a sample offset rather than a byte offset.s32 types.b32 type. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. is a two-element vector for 2d surfaces. where the fourth element is ignored.add. i. Operations add applies to . or . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.geom.trap .clamp.or }. .b. .u32 is assumed. . Operand b is a scalar or singleton tuple for 1d surfaces.geom. the access may proceed by silently masking off low-order address bits to achieve proper rounding. then . sured. or the instruction may fault.ctype = { . // for sured.b]. and is a four-element vector for 3d surfaces. If an address is not properly aligned.surfref variable.and. sured requires sm_20 or later. Coordinate elements are of type .u32 based on the surface sample format as follows: if the surface format contains UINT data. operations and and or apply to . .p performs a reduction on sample-addressed 32-bit data. {x}]. .ctype. // for sured. 2010 127 . the resulting behavior is undefined.clamp .p . [surf_B.clamp field specifies how to handle out-of-bounds addresses: .op.e.1d. sured.b32 }.Chapter 8.u32.c.b32.trap sured. .2d.p.p.trap. .u64.3d }. .add.op.u32 and .2d.u32.trap [surf_A.b].clamp = { .clamp [a.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. sured..u32.u64 data.geom = { .s32 types. and the data is interpreted as . The .b32 }. . // sample addressing .b32.

5.query.0 Table 93. . [surf_A].width. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.surfref variable. Supported on all target architectures. 2010 . 128 January 24.query = { .height. Operand a is a . suq.b32 d.b32 %r1.depth }.width . Description Query an attribute of a surface.height . [a].depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq.width.PTX ISA Version 2. Query: . .

The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. 2010 129 .c.s32 d. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. @{!}p instruction. Supported on all target architectures.0. Introduced in PTX ISA version 1.f32 @!p div.f32 @q bra L23. { add. Supported on all target architectures. Execute an instruction or instruction block for threads that have the guard predicate true.a.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Table 95.b. Instruction Set 8.x.s32 a. {} Syntax Description Control Flow Instructions: { } Instruction grouping.y. mov.eq. { instructionList } The curly braces create a group of instructions. p. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.0.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Threads with a false guard predicate do nothing. setp.7.0. used primarily for defining a function body. ratio.7. If {!}p then instruction Introduced in PTX ISA version 1.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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the waiting threads are restarted without delay. In addition to signaling its arrival at the barrier. b.red are population-count (. January 24. all-threads-true (.or }. and then safely read values stored by other threads prior to the barrier. Barriers are executed on a per-warp basis as if all the threads in a warp are active. a{. The reduction operations for bar. Description Performs barrier synchronization and communication within a CTA.op. {!}c. bar.red.arrive using the same active barrier. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). bar.popc. bar.red performs a reduction operation across threads.sync or bar.red instruction.red should not be intermixed with bar. the bar. and bar. bar.pred .red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.red. bar. threads within a CTA that wish to communicate via memory can store to memory.red also guarantee memory ordering among threads identical to membar. The barrier instructions signal the arrival of the executing threads at the named barrier.arrive does not cause any waiting by the executing threads. Thus. bar.0. When a barrier completes.op = { .sync and bar. b}. Only bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15..sync or bar. Thus. and bar. and the barrier is reinitialized so that it can be immediately reused. Once the barrier count is reached. operands p and c are predicates. and any-thread-true (. while . d.sync with an immediate barrier number is supported for sm_1x targets.red performs a predicate reduction across the threads participating in the barrier. Register operands. Register operands.red delays the executing threads (similar to bar. bar. if any thread in a warp executes a bar instruction.{arrive. Note that a non-zero thread count is required for bar.sync and bar.Chapter 8.popc is the number of threads with a true predicate.u32.cta. bar.{arrive.and). all threads in the CTA participate in the barrier. the final value is written to the destination register in all threads waiting at the barrier.15.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Operands a.sync) until the barrier count is met.sync 0. The result of .u32 bar. b}. a{. b. execute a bar.red} introduced in PTX . Execution in this case is unpredictable. Since barriers are executed on a per-warp basis.0.arrive a{. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.version 2. b}. Operand b specifies the number of threads participating in the barrier. bar. Each CTA instance has sixteen barriers numbered 0.popc). {!}c. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. If no thread count is specified. p. 2010 133 .or). PTX ISA Notes Target ISA Notes Examples bar.sync without a thread count introduced in PTX ISA 1. thread count. thread count. Instruction Set Table 100. the optional thread count must be a multiple of the warp size. it is as if all the threads in the warp have executed the bar instruction. . and d have type .red} require sm_20 or later.sync bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. All threads in the warp are stalled until the barrier completes.and and . In conditionally executed code.arrive. a.and. it simply marks a thread's arrival at the barrier.

. red or atom) has been performed when the value written has become visible to other clients at the specified level.version 2. and memory reads by this thread can no longer be affected by other thread writes.gl. membar.gl.sys requires sm_20 or later.sys.sys Waits until all prior memory requests have been performed with respect to all clients. membar.cta. membar. For communication between threads in different CTAs or even different SMs. this is the appropriate level of membar. membar. PTX ISA Notes Target ISA Notes Examples membar.cta. membar.g. or system memory level.{cta. level describes the scope of other clients for which membar is an ordering event. . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.4. membar.level. by st.0. membar.version 1.level = { .{cta.gl will typically have a longer latency than membar.gl} supported on all target architectures. membar. . that is. 134 January 24. membar. membar. A memory write (e. A memory read (e. when the previous value can no longer be read.gl. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar. including thoses communicating via PCI-E such as system and peer-to-peer memory.cta Waits until all prior memory writes are visible to other threads in the same CTA. Waits until prior memory reads have been performed with respect to other threads in the CTA. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.sys will typically have much longer latency than membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.g.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. global.sys introduced in PTX .0 Table 101. 2010 .sys }.PTX ISA Version 2.gl} introduced in PTX .cta. membar.

type d.b32. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. an address maps to global memory unless it falls within the local memory window or the shared memory window.u64 . The floating-point add. and max.add. .b32. . Description // // // // // ..cas. In generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. .max }. .s32. min. atom{. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . The inc and dec operations return a result in the range [0.inc. b.e. .min.op.type atom{.b64 . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. .space = { . The address must be naturally aligned to a multiple of the access size. overwriting the original value.type = { .f32 }.u32.global. . or [immAddr] an immediate absolute byte address. atom.u32.b32 only . .space}. an address maps to the corresponding location in local or shared memory. and exch (exchange). 2010 135 . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.s32. .u64. performs a reduction operation with operand b and the value in location a. Instruction Set Table 102. . inc. and stores the result of the specified operation at location a. min.. accesses to local memory are illegal. perform the memory accesses using generic addressing. For atom.exch. A register containing an address may be declared as a bit-size type or integer type. b.e.shared }.space}.dec. . Operand a specifies a location in the specified state space. the resulting behavior is undefined. . e. . .exch to store to locations accessed by other atomic operations.op. Addresses are zero-extended to the specified width as needed.or.u32. i. The address size may be either 32-bit or 64-bit. The bit-size operations are and. .Chapter 8.g. max.f32 Atomically loads the original value at location a into destination register d. .u32 only . January 24. c.f32.op = { . or.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.b64.s32. and max operations are single-precision. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. d.xor.add.and. [a].b]. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. i. Within these windows. . by inserting barriers between normal stores and atomic operations to a common address. If an address is not properly aligned. The integer operations are add. dec. or by using atom. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . . [a]. cas (compare-and-swap). . 32-bit operations. . If no state space is given. xor. or the instruction may fault. The floating-point operations are add. . min. a de-referenced register areg containing a byte address.

1. 64-bit atom.0.add.[a].f32 atom. : r-1.cas. Use of generic addressing requires sm_20 or later.[x+4].f32. 2010 . b. s) = s. s) = (r >= s) ? 0 dec(r.{min.b32 d. d. Release Notes Examples @p 136 January 24. : r.PTX ISA Version 2. *a = (operation == cas) ? : } where inc(r. atom.my_new_val. atom.[p].shared.f32 requires sm_20 or later. s) = (r > s) ? s exch(r.s.{add.max} are unimplemented. c) operation(*a.max.t) = (r == s) ? t operation(*a. atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.my_val.s32 atom.shared operations require sm_20 or later. d.exch} requires sm_12 or later.global requires sm_11 or later. atom. b). atom.add.global.0 Semantics atomic { d = *a. cas(r.global. Introduced in PTX ISA version 1.cas.0.shared requires sm_12 or later. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. 64-bit atom. : r+1.

b32. red{. 2010 137 .e. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. inc.u32.global.u32.or. a de-referenced register areg containing a byte address. Notes Operand a must reside in either the global or shared state space. . min.u64. The address size may be either 32-bit or 64-bit. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and xor. .xor. by inserting barriers between normal stores and reduction operations to a common address. e.s32. . . min.u64 . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Within these windows.inc. The integer operations are add. accesses to local memory are illegal. min.type [a].f32. .u32. .space = { .f32 Performs a reduction operation with operand b and the value in location a. max. The floating-point add.s32. Instruction Set Table 103..u32 only . s) = (r >= s) ? 0 : r+1.f32 }. and stores the result of the specified operation at location a. an address maps to global memory unless it falls within the local memory window or the shared memory window. where inc(r.Chapter 8. The floating-point operations are add. red. .b32 only . . b). Semantics *a = operation(*a. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. If no state space is given. . The inc and dec operations return a result in the range [0. s) = (r > s) ? s : r-1. If an address is not properly aligned. dec. dec(r. January 24. perform the memory accesses using generic addressing. .exch to store to locations accessed by other reduction operations.and. or the instruction may fault. b. and max operations are single-precision. 32-bit operations.shared }. an address maps to the corresponding location in local or shared memory.s32.add. . .max }. .space}.op. and max. . Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. overwriting the original value.e. Addresses are zero-extended to the specified width as needed. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Operand a specifies a location in the specified state space. .b]. The bit-size operations are and.add. or. . and truncated if the register width exceeds the state space address width for the target architecture.min. The address must be naturally aligned to a multiple of the access size. Description // // // // . . . the resulting behavior is undefined.type = { . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.op = { .dec. In generic addressing. i. A register containing an address may be declared as a bit-size type or integer type.. i. For red. .b64. . or [immAddr] an immediate absolute byte address.g. or by using atom.

shared. Release Notes Examples @p 138 January 24. [x+4].PTX ISA Version 2. 64-bit red.f32. Use of generic addressing requires sm_20 or later. red.and.s32 red. red. red.2.f32 red.global requires sm_11 or later red. red.f32 requires sm_20 or later.1.b32 [a].my_val.add requires sm_12 or later. 2010 .max} are unimplemented. 64-bit red.0.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.global.shared requires sm_12 or later.{min.add.add. [p].max.global.shared operations require sm_20 or later.

q. r1.q.mode. Description Performs a reduction of the source predicate across threads in a warp.Chapter 8. not across an entire CTA. Negate the source predicate to compute . vote.pred vote. Negate the source predicate to compute . vote requires sm_12 or later. Note that vote applies to threads in a single warp.any. vote.ballot. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.all True if source predicate is True for all active threads in warp.ballot.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. .all.none. Negating the source predicate also computes .pred d.any True if source predicate is True for some active thread in warp. . returns bitmask .p. . Instruction Set Table 104.2. vote. vote.b32 requires sm_20 or later. The destination predicate value is the same across all threads in the warp. vote. p.mode = { . 2010 139 .uni True if source predicate has the same value in all active threads in warp. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. In the ‘ballot’ form. where the bit position corresponds to the thread’s lane id.pred vote.uni }.all. {!}a. // ‘ballot’ form. The reduction modes are: .uni.not_all. {!}a.b32 p. . // get ‘ballot’ across warp January 24.b32 d.uni.ballot.ballot.

btype{. 4. .h0. The sign of the intermediate result depends on dtype.bsel}.sat}.bsel = { .b1.btype{.max }.btype = { . .dtype.btype{. Using the atype/btype and asel/bsel specifiers. 3. with optional data merge vop. extract and sign. b{. vop. c.9.dsel. half-word. .bsel}.asel = . .or zero-extend byte.u32. a{. b{.sat} d.add. c. // 32-bit scalar operation. 2010 . The general format of video instructions is as follows: // 32-bit scalar operation.extended internally to .dtype = .PTX ISA Version 2. b{.sat} d. perform a scalar arithmetic operation to produce a signed 34-bit result.s32) is specified in the instruction type.atype = . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). .b2. with optional secondary operation vop.b3. or word values from its source operands. to produce signed 33-bit input values.s34 intermediate result.atype. 2. The primary operation is then performed to produce an .h1 }.dsel = .secop = { .asel}. . Video Instructions All video instructions operate on 32-bit register operands. .asel}. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. a{.7. taking into account the subword destination size in the case of optional data merging. . and btype are valid.s33 values. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.dtype.u32 or .asel}. . atype.atype. the input values are extracted and signor zero. a{. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. .atype.bsel}. The type of each operand (.s32 }. optionally clamp the result to the range of the destination type.secop d.min.0 8. The source and destination operands are all 32-bit registers. 140 January 24.dtype. all combinations of dtype. .b0.

h1: return ((tmp & 0xffff) << 16) case . c). 2010 141 . S8_MAX.s33 tmp. S8_MIN ). default: return tmp. . U8_MAX.b1. U8_MIN ). c). } } . . . switch ( dsel ) { case .min: return MIN(tmp. S16_MAX.max return MAX(tmp. tmp. January 24. Modifier dsel ) { if ( !sat ) return tmp. c). c).b1: return ((tmp & 0xff) << 8) case .s34 tmp. .s33 optMerge( Modifier dsel. .Chapter 8. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. c). tmp. Bool sign. S16_MIN ). The lower 32-bits are then written to the destination operand. U32_MAX. . S32_MIN ). U16_MAX. . Instruction Set .b3: if ( sign ) return CLAMP( else return CLAMP( case .b3: return ((tmp & 0xff) << 24) default: return tmp. S32_MAX. tmp. c). c). . tmp. . Bool sat.s33 optSaturate( .b2. as shown in the following pseudocode.b2: return ((tmp & 0xff) << 16) case .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.h0. The sign of the c operand is based on dtype.add: return tmp + c.s33 c) { switch ( secop ) { . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).s33 optSecOp(Modifier secop.b0: return ((tmp & 0xff) case . tmp.s33 tmp. .s33 c ) switch ( dsel ) { case . . U32_MIN ).h0: return ((tmp & 0xffff) case . U16_MIN ).b0.

or zero-extend based on source operand type ta = partSelectSignExtend( a.dsel. . r1. r2. vabsdiff.asel}.s32. r2. bsel ).PTX ISA Version 2.s32 }. b{.s32.vop . . // optional merge with c operand 142 January 24.s32.b2. tmp = ta – tb. tmp = MAX( ta. tmp = | ta – tb |.atype. vmin.h1.s32. atype.atype. vop. vmin. // 32-bit scalar operation. r3. c ). c. b{.h1. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. a{. vsub. Semantics // saturate.btype{. r1.b0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.asel = .b2.asel}.max }. Integer byte/half-word/word minimum / maximum.u32. tmp. r3. .asel}. r3. b{. 2010 .btype{. vmax vadd. vabsdiff. . vabsdiff.add r1. r2.h0. vadd. Video Instructions: vadd. vmax Syntax Integer byte/half-word/word addition / subtraction. vmin.dsel .u32. vmax }. sat.dtype. { . c.sat}.b1. taking into account destination type and merge operations tmp = optSaturate( tmp. .s32.dtype. d = optSecondaryOp( op2.b3.btype = { . tb ). // 32-bit scalar operation.dtype.0 Table 105.op2 Description = = = = { vadd.min. .bsel}. asel ).sat.add. tmp.sat vsub. r2.dtype .bsel = { . c.b0. . r3. vadd.op2 d.h1 }. // extract byte/half-word/word and sign. .h0. Perform scalar arithmetic operation with optional saturate. a{.s32. // optional secondary operation d = optMerge( dsel. with optional data merge vop. Integer byte/half-word/word absolute value of difference. vsub. . vmax require sm_20 or later.bsel}.s32.s32. dsel ). tb = partSelectSignExtend( b.atype.u32. tb ). c ).sat vmin.sat} d.sat} d.btype{.s32. btype.h0.sat vabsdiff.b0.s32.bsel}. tmp = MIN( ta.atype = . vsub. a{. . and optional secondary arithmetic operation or subword data merge. r1. . c. vsub vabsdiff vmin. with optional secondary operation vop.0. isSigned(dtype).

Instruction Set Table 106.atype = { .u32{. vshr Syntax Integer byte/half-word/word left / right shift.s32. r2.h1 }. { .clamp. r2.mode .bsel}. isSigned(dtype). asel ). // default is . . if ( mode == . . Video Instructions: vshl. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.clamp && tb > 32 ) tb = 32.u32.wrap }.add.bsel}.b1.mode} d. .sat}{. .u32. r1. b{.op2 Description = = = = = { vshl.wrap ) tb = tb & 0x1f. // optional secondary operation d = optMerge( dsel. // 32-bit scalar operation. January 24.Chapter 8. .atype. c ).bsel = { .b0.u32. . .0. and optional secondary arithmetic operation or subword data merge.dtype . } // saturate.mode} d. tmp.wrap r1. taking into account destination type and merge operations tmp = optSaturate( tmp. vshr vshl.u32{.clamp . .dtype. . r3.mode}. c.max }.atype.min.or zero-extend based on source operand type ta = partSelectSignExtend( a. tb = partSelectSignExtend( b. vshr }. r3.asel = . . tmp. . . vshr: Shift a right by unsigned amount in b with optional saturate. d = optSecondaryOp( op2.sat}{. vop.u32{.asel}. if ( mode == .asel}.u32. sat. bsel ).asel}. a{.s32 }. a{.dtype.vop .u32. case vshr: tmp = ta >> tb. vshl.h1.u32 vshr.h0.sat}{. with optional data merge vop. vshl. vshl: Shift a left by unsigned amount in b with optional saturate. Signed shift fills with the sign bit. b{.b2. and optional secondary arithmetic operation or subword data merge.bsel}. dsel ).op2 d.b3. switch ( vop ) { case vshl: tmp = ta << tb. atype. Left shift fills with zero. 2010 143 . // 32-bit scalar operation. a{.u32. with optional secondary operation vop. vshr require sm_20 or later. Semantics // extract byte/half-word/word and sign.dtype.atype. c ). unsigned shift fills with zero. b{. c.dsel .dsel. { .

final signed (S32 * U32) . PTX allows negation of either (a*b) or c. with optional operand negates.sat}{.asel}.btype{. a{. internally this is represented as negation of the product (a*b). Description Calculate (a*b) + c.scale} d. {-}b{. Source operands may not be negated in .atype.b0.u32.dtype = . final signed The intermediate result is optionally scaled via right-shift.shr7.h1 }.dtype.scale} d.atype = . final signed -(S32 * U32) + S32 // intermediate signed. {-}a{. . “plus one” mode. final signed (U32 * S32) .U32 // intermediate unsigned.S32 // intermediate signed.S32 // intermediate signed. and the operand negates.s32 }. final signed -(U32 * S32) + S32 // intermediate signed.b1. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (S32 * U32) + S32 // intermediate signed.atype.b3. . final signed -(S32 * S32) + S32 // intermediate signed.bsel}.0 Table 107. vmad. c. 2010 . final signed (U32 * S32) + S32 // intermediate signed. the intermediate result is signed.h0. . and zero-extended otherwise. Although PTX syntax allows separate negation of the a and b operands. .bsel}.PTX ISA Version 2. and scaling. this result is sign-extended if the final result is signed. Input c has the same sign as the intermediate result. {-}c. The source operands support optional negation with some restrictions. b{. final signed (U32 * U32) . . (a*b) is negated if and only if exactly one of a or b is negated.po) computes (a*b) + c + 1. 144 January 24.asel}.scale = { .S32 // intermediate signed. final unsigned -(U32 * U32) + S32 // intermediate signed. . which is used in computing averages.asel = . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final signed (S32 * S32) . The final result is unsigned if the intermediate result is unsigned and c is not negated. // 32-bit scalar operation vmad..dtype. final signed (S32 * S32) + S32 // intermediate signed.sat}{.bsel = { .po mode. . Depending on the sign of the a and b operands. .shr15 }.po{.b2. . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. That is. The “plus one” mode (. . otherwise.btype.btype = { .

2010 145 . lsb = 1.negate. bsel ).shr15 r0. signedFinal = isSigned(atype) || isSigned(btype) || (a.sat vmad. lsb = 0.u32. switch( scale ) { case . U32_MAX. btype.u32. vmad requires sm_20 or later. tb = partSelectSignExtend( b. lsb = 1.negate ^ b. r2. S32_MIN). else result = CLAMP(result. case . } else if ( a. r1.Chapter 8. r0.po ) { lsb = 1.u32.s32. if ( . asel ). } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r3. Instruction Set Semantics // extract byte/half-word/word and sign.negate ^ b. atype.h0.negate ) { c = ~c.s32.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate ) { tmp = ~tmp.sat ) { if (signedFinal) result = CLAMP(result.shr7: result = (tmp >> 7) & 0xffffffffffffffff. } if ( . -r3. U32_MIN). vmad. January 24. tmp[127:0] = ta * tb. } else if ( c.negate) || c. tmp = tmp + c128 + lsb.0. r1. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).or zero-extend based on source operand type ta = partSelectSignExtend( a.h0. S32_MAX.u32. r2.

r2. bsel ). Semantics // extract byte/half-word/word and sign.PTX ISA Version 2. vset.btype.lt vset.eq.h1.ne.asel}. vset.le.op2 d.cmp d. b{.u32.h1 }. .cmp .btype = { . 2010 .atype.atype.u32.ne r1. Compare input values using specified comparison. . { . a{. tb. a{.b2. btype. tmp.s32. The intermediate result of the comparison is always unsigned. d = optSecondaryOp( op2. r3. tb = partSelectSignExtend( b.bsel = { .u32.max }. . . .gt. b{. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. . 146 January 24.op2 Description = = = = .dsel.lt.b1. asel ). c. { . r3. . c ). atype. b{.0. . . with optional secondary arithmetic operation or subword data merge.0 Table 108. // 32-bit scalar operation. cmp ) ? 1 : 0.or zero-extend based on source operand type ta = partSelectSignExtend( a.atype . vset requires sm_20 or later.s32 }. . .bsel}.cmp d. tmp. a{.cmp.u32.b3.asel}.min. .bsel}.asel}.ge }. r2. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. with optional secondary operation vset. .h0. .btype. with optional data merge vset.dsel . r1.add. .asel = . c ). // 32-bit scalar operation.b0. // optional secondary operation d = optMerge( dsel. and therefore the c operand and final result are also unsigned.btype. c.bsel}.atype. tmp = compare( ta.

January 24. Triggers one of a fixed number of performance monitor events. 2010 147 .7. Introduced in PTX ISA version 1. trap. pmevent 7.4. pmevent a.0. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Introduced in PTX ISA version 1. numbered 0 through 15. Table 111. with index specified by immediate operand a. there are sixteen performance monitor events. Supported on all target architectures. trap.0. brkpt Suspends execution Introduced in PTX ISA version 1. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. brkpt requires sm_11 or later. brkpt. @p pmevent 1.10. Notes PTX ISA Notes Target ISA Notes Examples Currently. Supported on all target architectures. Table 110. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.Chapter 8. Instruction Set 8. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. brkpt. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. trap Abort execution and generate an interrupt to the host CPU. The relationship between events and counters is programmed via API calls from the host.

PTX ISA Version 2.0 148 January 24. 2010 .

2010 149 . %lanemask_le. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. Special Registers PTX includes a number of predefined. %clock64 %pm0. %lanemask_lt. %pm3 January 24. read-only variables.Chapter 9. …. %lanemask_gt %clock. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_ge.

x.y. %tid. // legacy PTX 1. The %tid special register contains a 1D.x < %ntid. Redefined as . The number of threads in each dimension are specified by the predefined special register %ntid.%ntid.x code accessing 16-bit component of %tid mov.x. .u32 type in PTX 2. mov.0.u32. .z == 1 in 1D CTAs. .u32 %h2. // thread id vector // thread id components A predefined.PTX ISA Version 2.0.u32 %r0.%tid. mov. // CTA shape vector // CTA dimensions A predefined.x to %rh Target ISA Notes Examples // legacy PTX 1.x.%tid.u32 %tid.u32 type in PTX 2. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.y 0 <= %tid.u32 %r0.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %tid.sreg . .z. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.0.x.x * %ntid. %tid component values range from 0 through %ntid–1 in each CTA dimension. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. %ntid. Every thread in the CTA has a unique %tid. It is guaranteed that: 0 <= %tid.z).%tid.x code Target ISA Notes Examples 150 January 24. %tid. 2010 .v4 .u16 %r2.y == %tid.%ntid.z == 0 in 1D CTAs. Supported on all target architectures.%r0.v4 .x 0 <= %tid.u16 %rh.x.x. The fourth element is unused and always returns zero.u32 %ntid.u32 %r1.0.y * %ntid.y == %ntid.z < %ntid.v4. %tid.%h2.sreg .v4. mov.z.y. read-only. per-thread special register initialized with the thread identifier within the CTA.sreg . the %tid value in unused dimensions is 0. // move tid.0 Table 112. %ntid.y < %ntid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. mad. // zero-extend tid. %ntid. Redefined as . 2D.u32 %h1.x.%h1. cvt.sreg . the fourth element is unused and always returns zero.z == 1 in 2D CTAs.u32 %ntid. or 3D vector to match the CTA shape.u16 %rh. Supported on all target architectures.%tid. mov.z. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. The total number of threads in a CTA is (%ntid. PTX ISA Notes Introduced in PTX ISA version 1. %tid. // compute unified thread id for 2D CTA mov.z == 0 in 2D CTAs.z to %r2 Table 113.%tid. CTA dimensions are non-zero. read-only special register initialized with the number of thread ids in each CTA dimension.y. %ntid.

g. e. Table 115. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. 2010 151 . . The warp identifier will be the same for all threads within a single warp. . %laneid. mov. Special Registers Table 114. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. mov. due to rescheduling of threads following preemption. A predefined. but its value may change during execution.3. Note that %warpid is volatile and returns the location of a thread at the moment when read. A predefined. The lane identifier ranges from zero to WARP_SZ-1. mov.u32 %r. Supported on all target architectures.u32 %laneid. .sreg . A predefined. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %warpid.3.u32 %r. %nwarpid requires sm_20 or later.u32 %r.sreg . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.u32 %nwarpid.Chapter 9. For this reason. read-only special register that returns the thread’s warp identifier. read-only special register that returns the thread’s lane within the warp. Introduced in PTX ISA version 1. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Table 116.sreg . %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.0. January 24. read-only special register that returns the maximum number of warp identifiers. Introduced in PTX ISA version 2. %nwarpid. Introduced in PTX ISA version 1.u32 %warpid. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.

sreg .u32 %nctaid. read-only special register initialized with the CTA identifier within the CTA grid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.z} < 65.y.u32 type in PTX 2. // Grid shape vector // Grid dimensions A predefined. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. with each element having a value of at least 1.x.y 0 <= %ctaid.u16 %r0.x. %ctaid. The fourth element is unused and always returns zero.%nctaid.u32 mov.sreg . or 3D vector. It is guaranteed that: 0 <= %ctaid.u32 %ctaid. mov. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.v4. mov. 2010 .x code Target ISA Notes Examples Table 118.x 0 <= %ctaid.0.v4 . It is guaranteed that: 1 <= %nctaid. Redefined as .%ctaid.0. Supported on all target architectures. Redefined as .u32 %ctaid.x. // CTA id vector // CTA id components A predefined.z. depending on the shape and rank of the CTA grid.%nctaid. // legacy PTX 1. .x. The fourth element is unused and always returns zero. 2D.%ctaid. read-only special register initialized with the number of CTAs in each grid dimension.u32 %nctaid .v4 .x < %nctaid.z PTX ISA Notes Introduced in PTX ISA version 1. The %nctaid special register contains a 3D grid shape vector.u16 %r0. . Each vector element value is >= 0 and < 65535.v4. // legacy PTX 1. .PTX ISA Version 2.x code Target ISA Notes Examples 152 January 24.u32 mov.sreg .y.%nctaid.y. %rh.z.u32 type in PTX 2.y < %nctaid. Supported on all target architectures.536 PTX ISA Notes Introduced in PTX ISA version 1. The %ctaid special register contains a 1D. %rh.{x.0.0 Table 117. %ctaid.x.0.z < %nctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.y.%nctaid.sreg .

Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.0. Supported on all target architectures. mov. Notes PTX ISA Notes Target ISA Notes Examples Table 120. read-only special register that returns the maximum number of SM identifiers. The SM identifier numbering is not guaranteed to be contiguous. A predefined. .Chapter 9. Introduced in PTX ISA version 1. repeated launches of programs may occur.u32 %gridid. The SM identifier ranges from 0 to %nsmid-1. During execution. Introduced in PTX ISA version 2.g. %smid. PTX ISA Notes Target ISA Notes Examples Table 121. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Introduced in PTX ISA version 1.u32 %r. where each launch starts a grid-of-CTAs. %gridid. .3. mov. e.sreg . The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.sreg . The SM identifier numbering is not guaranteed to be contiguous.sreg .u32 %r. mov. This variable provides the temporal grid launch number for this context.0. A predefined.u32 %smid. 2010 153 . PTX ISA Notes Target ISA Notes Examples January 24. .u32 %nsmid. // initialized at grid launch A predefined. but its value may change during execution. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. %nsmid. Special Registers Table 119. %nsmid requires sm_20 or later. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Supported on all target architectures.u32 %r. due to rescheduling of threads following preemption. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. so %nsmid may be larger than the physical number of SMs in the device. Note that %smid is volatile and returns the location of a thread at the moment when read. read-only special register initialized with the per-grid temporal grid identifier.

u32 %r. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.0. mov. Introduced in PTX ISA version 2.PTX ISA Version 2. A predefined.u32 %r. 2010 . Table 123. mov. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. . %lanemask_eq requires sm_20 or later. Table 124.0.u32 %lanemask_eq. Introduced in PTX ISA version 2.u32 %lanemask_le.sreg . A predefined. %lanemask_le requires sm_20 or later.0.u32 %lanemask_lt.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. A predefined.0 Table 122.u32 %r.sreg . Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_lt. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. mov. 154 January 24. %lanemask_lt requires sm_20 or later. %lanemask_eq. . %lanemask_le.

u32 %r.u32 %lanemask_gt. %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge. Table 126.Chapter 9.u32 %lanemask_ge.0. . . read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg . A predefined. 2010 155 . A predefined. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.0. mov. Special Registers Table 125. %lanemask_gt requires sm_20 or later. %lanemask_ge requires sm_20 or later. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. Introduced in PTX ISA version 2. January 24. mov. Introduced in PTX ISA version 2.sreg .

0.u32 r1. Introduced in PTX ISA version 2. 156 January 24.3. The lower 32-bits of %clock64 are identical to %clock. %pm3.PTX ISA Version 2. Supported on all target architectures.%clock64. and %pm3 are unsigned 32-bit read-only performance monitor counters. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. .0 Table 127. %clock64 requires sm_20 or later. %pm1. Introduced in PTX ISA version 1. Supported on all target architectures. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. %pm1. %pm3 %pm0.u32 r1. read-only 32-bit unsigned cycle counter. Special Registers: %pm0. %pm1. Introduced in PTX ISA version 1. Table 129. Table 128. ….u32 %pm0.u32 %clock. mov.sreg .0. %pm2.u64 r1. Their behavior is currently undefined. mov. Special registers %pm0.sreg . . %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. .%pm0. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm2. read-only 64-bit unsigned cycle counter. 2010 .u64 %clock64. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. mov.%clock. %pm2.sreg .

Directives 10. minor are integers Specifies the PTX language version number.version directive. . PTX File Directives: .0. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.0 .version directives are allowed provided they match the original . Increments to the major number indicate incompatible changes to PTX.version major. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and the target architecture for which the code was generated. 2010 157 .target Table 130.4 January 24.version . . .minor // major. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. Each ptx file must begin with a .Chapter 10.version directive.version 2.version Syntax Description Semantics PTX version number.1.version . Duplicate . Supported on all target architectures.version 1.

PTX File Directives: . Therefore. map_f64_to_f32 }. Introduced in PTX ISA version 1. sm_11. texmode_unified.f64 instructions used. 64-bit {atom.global. but subsequent . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Target sm_20 Description Baseline feature set for sm_20 architecture. PTX features are checked against the specified target architecture. A . Adds {atom.f64 storage remains as 64-bits. and an error is generated if an unsupported feature is used. generations of SM architectures follow an “onion layer” model. The following table summarizes the features in PTX that vary according to target architecture.texref descriptor.target directives can be used to change the set of target features allowed during parsing.global.target directive containing a target architecture and optional platform options.f32. including expanded rounding modifiers.0. Each PTX file must begin with a .target Syntax Architecture and Platform target.texmode_independent texture and sampler information is bound together and accessed via a single . where each generation adds new features and retains all features of previous generations. vote instructions. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. immediately followed by a .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Adds {atom. Texturing mode: (default is .samplerref descriptors. PTX code generated for a given target can be run on later generation devices.texref and .f64 instructions used.shared. Requires map_f64_to_f32 if any . . with only half being used by instructions converted from . Adds double-precision support.5. 158 January 24. Texturing mode introduced in PTX ISA version 1. sm_13. texture and sampler information is referenced with independent .0 Table 131. The texturing mode is specified for an entire module and cannot be changed within the module.texmode_unified . brkpt instructions. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.red}. A program with multiple . sm_12.PTX ISA Version 2. Requires map_f64_to_f32 if any . Description Specifies the set of features in the target architecture for which the current ptx code was generated.red}.f64 instructions used.version directive. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Supported on all target architectures. Note that .red}. Requires map_f64_to_f32 if any . texmode_independent.target directive specifies a single target architecture. 2010 .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.texmode_unified) .target . Disallows use of map_f64_to_f32. In general.f64 to . sm_10.

2010 159 .target sm_13 // supports double-precision .Chapter 10.target sm_10 // baseline target architecture .target sm_20. texmode_independent January 24. Directives Examples .

For PTX ISA versions 1. In addition to normal parameters. parameter variables are declared in the kernel body. .param.entry .entry kernel-name ( param-list ) kernel-body . 160 January 24. the kernel dimensions and properties are established and made available via special registers. Semantics Specify the entry point for a kernel program. . Kernel and Function Directives: .surfref variables may be passed as parameters. %nctaid.4. .b32 x.param . . parameters.b32 %r3.b32 y. Parameters are passed via .entry filter ( . The shape and size of the CTA executing the kernel are available in special registers.PTX ISA Version 2.g.3.0 through 1. … } .entry kernel-name kernel-body Defines a kernel entry point name. e. . Parameters may be referenced by name within the kernel body and loaded into registers using ld.param. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. store. Supported on all target architectures.param instructions. [z].b32 %r2.2. These parameters can only be referenced by name within texture and surface load. PTX ISA Notes For PTX ISA version 1.param space memory and are listed within an optional parenthesized parameter list. and query instructions and cannot be accessed via ld. .5 and later.0 10.param.4 and later.param .texref. %ntid.func Table 132.samplerref.entry cta_fft .reg .b32 %r1.param { . ld. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. parameter variables are declared in the kernel parameter list.entry Syntax Description Kernel entry point and body. etc. [y]. and .0 through 1. ld.param instructions. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. opaque .entry . 2010 . with optional parameters.b32 %r<99>. ld. and body for the kernel function.b32 z ) Target ISA Notes Examples [x]. At kernel launch.

reg . and recursion is illegal. Variadic functions are represented using ellipsis following the last fixed argument. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.2 for a description of variadic functions.param and st.b32 rval. there is no stack.0. Parameter passing is call-by-value. val1). Parameters must be base types in either the register or parameter state space.b32 rval) foo (. (val0. . other code.reg .func definition with no body provides a function prototype.param instructions in the body. } … call (fooval).func . parameters must be in the register state space. ret.0 with target sm_20 allows parameters in the . implements an ABI with stack. The implementation of parameter passing is left to the optimizing translator. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Parameters in register state space may be referenced directly within instructions in the function body. The parameter lists define locally-scoped variables in the function body. mov. foo.Chapter 10.f64 dbl) { . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Kernel and Function Directives: .func Syntax Function definition. dbl.b32 N. .func fname (param-list) function-body .func fname function-body . . Variadic functions are currently unimplemented.param space are accessed using ld.result.reg . and supports recursion.0 with target sm_20 supports at most one return value. Release Notes For PTX ISA version 1. Parameters in . A . including input and return parameters and optional function body. which may use a combination of registers and stack locations to pass parameters. Supported on all target architectures.b32 localVar. PTX ISA 2. Directives Table 133.func (ret-param) fname (param-list) function-body Defines a function. PTX 2.x code. … use N.func (.param state space. … Description // return value in fooval January 24. 2010 161 . if any.reg .

registers) to increase total thread count and provide a greater opportunity to hide memory latency.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). to throttle the resource requirements (e.3. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. and the . at entry-scope.maxnctapersm (deprecated) . Currently.maxntid and .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxnreg . Note that .entry directive and its body.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. for example.maxntid directive specifies the maximum number of threads in a thread block (CTA). Performance-Tuning Directives To provide a mechanism for low-level performance tuning. 2010 . The interpretation of . The directive passes a list of strings to the backend. The . and .pragma directives may appear at module (file) scope.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. and the strings have no semantics within the PTX virtual machine model. .PTX ISA Version 2.maxntid . PTX supports the following directives.g. which pass information to the backend optimizing compiler. the .minnctapersm directives may be applied per-entry and must appear between an .minnctapersm . The directives take precedence over any module-level constraints passed to the optimizing backend. These can be used. . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. A general .0 10.pragma directive is supported for passing information to the PTX backend. or as statements within a kernel or device function body. the .maxnreg.pragma The . 162 January 24.maxntid.

2010 163 . Introduced in PTX ISA version 1. 2D. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Supported on all target architectures.Chapter 10. Performance-Tuning Directives: .16.maxntid nx .maxntid Syntax Maximum number of threads in thread block (CTA).4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. . The actual number of registers used may be less.entry foo .maxctapersm. ny .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. This maximum is specified by giving the maximum extent of each dimention of the 1D.entry bar .3. . Exceeding any of these limits results in a runtime error or kernel launch failure.entry foo . Directives Table 134.maxntid nx.maxnreg . . . the backend may be able to compile to fewer registers. The compiler guarantees that this limit will not be exceeded. ny.maxnreg n Declare the maximum number of registers per thread in a CTA. Supported on all target architectures. for example. Introduced in PTX ISA version 1.maxntid nx. or 3D CTA.3.maxntid 256 . nz Declare the maximum number of threads in the thread block (CTA). Performance-Tuning Directives: . or the maximum number of registers may be further constrained by .maxntid 16.maxntid .maxntid and . The maximum number of threads is the product of the maximum extent in each dimension.

Performance-Tuning Directives: . Deprecated in PTX ISA version 2.entry foo . .maxnctapersm generally need .maxntid 256 .0 Table 136. . Optimizations based on . if the number of registers used by the backend is sufficiently lower than this bound. Supported on all target architectures.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.minnctapersm . Performance-Tuning Directives: .minnctapersm in PTX ISA version 2.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). The optimizing backend compiler uses .entry foo .0. For this reason. Introduced in PTX ISA version 1.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. 2010 .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Supported on all target architectures.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. However.3.maxntid to be specified as well.0. .maxntid and .maxnctapersm (deprecated) .maxnctapersm has been renamed to .maxntid 256 .minnctapersm generally need . Introduced in PTX ISA version 2.PTX ISA Version 2.0 as a replacement for .maxnctapersm. .maxntid to be specified as well. .minnctapersm 4 { … } 164 January 24. Optimizations based on . additional CTAs may be mapped to a single multiprocessor.

entry foo . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . See Appendix A for descriptions of the pragma strings defined in ptxas. entry-scoped. 2010 165 . The interpretation of .pragma . or at statementlevel. or statement-level directives to the PTX backend compiler. .0. Introduced in PTX ISA version 2. Pass module-scoped. Supported on all target architectures.Chapter 10.pragma Syntax Description Pass directives to PTX backend compiler. Directives Table 138.pragma directive may occur at module-scope.pragma directive strings is implementation-specific and has no impact on PTX semantics. at entry-scope. The .pragma “nounroll”. { … } January 24.pragma list-of-strings . Performance-Tuning Directives: .pragma “nounroll”. .

4. 0x00. 0x6150736f. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .0 and replaces the @@DWARF syntax. 0x00000364.4byte . 0x00. replaced by .4byte label . 0x00. 0x02.4byte 0x000006b5.4byte 0x6e69616d.0 10.byte 0x2b. 2010 .0 but is supported for legacy PTX version 1. 0x736d6172 . 0x00.section .debug_pubnames. Introduced in PTX ISA version 1. 0x00..section directive is new in PTX ISA verison 2. Deprecated as of PTX 2. @@DWARF dwarf-string dwarf-string may have one of the .quad int64-list // comma-separated hexadecimal integers in range [0. The @@DWARF syntax is deprecated as of PTX version 2.section . “”.x code.section directive.2. 0x00.PTX ISA Version 2.264-1] .4byte int32-list // comma-separated hexadecimal integers in range [0. Table 139. 0x61395a5f.232-1] .0. 0x00 166 January 24.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.byte byte-list // comma-separated hexadecimal byte values . Supported on all target architectures.file .debug_info .loc The . 0x00 .byte 0x00.. @progbits . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x63613031. 0x5f736f63 .

0x00.255] .264-1] . Debugging Directives: .232-1] . .b8 0x00.section Syntax PTX section definition. . Directives Table 140.b64 int64-list // comma-separated list of integers in range [0. Debugging Directives: . 0x00 0x61395a5f.b8 byte-list // comma-separated list of integers in range [0. 0x00.debug_info .b32 0x000006b5.b32 int32-list // comma-separated list of integers in range [0. } 0x02. Debugging Directives: . Supported on all target architectures. . 2010 167 . .. replaces @@DWARF syntax. Supported on all target architectures. .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x5f736f63 0x6150736f.file .b32 0x6e69616d. 0x00.0.loc . Source file information..loc line_number January 24.b32 label .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. Supported on all target architectures.b32 . 0x00000364.Chapter 10.debug_pubnames { . 0x00. . 0x736d6172 0x00 Table 141. .section section_name { dwarf-lines } dwarf-lines have the following formats: .file filename Table 142. 0x00. 0x63613031. Source file location.b8 0x2b.0. 0x00.section ..section .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

// foo is defined in another module Table 144.0 10. .PTX ISA Version 2.extern identifier Declares identifier to be defined externally.extern . Supported on all target architectures. 2010 .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.global . . Introduced in PTX ISA version 1.global .visible .extern .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible identifier Declares identifier to be externally visible.b32 foo. Linking Directives .0. // foo will be externally visible 168 January 24. Linking Directives: .6. Introduced in PTX ISA version 1. . Linking Directives: . .extern . Supported on all target architectures.b32 foo.visible .0.visible Table 143.

0 driver r195 PTX ISA Version PTX ISA 1.1 CUDA 2.3 driver r190 CUDA 3. The first section describes ISA and implementation changes in the current release of PTX ISA 2.Chapter 11.5 PTX ISA 2.0 January 24.4 PTX ISA 1. CUDA Release CUDA 1.2 CUDA 2.0 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation. 2010 169 .0 CUDA 1.1 CUDA 2.1 PTX ISA 1.0.2 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.0 PTX ISA 1.3 PTX ISA 1. The release history is as follows.

PTX ISA Version 2. When code compiled for sm_1x is executed on sm_20 devices.1. The mad. 2010 . Changes in Version 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 11. and mul now support .f32 instruction also supports . New Features 11.ftz and .x code and sm_1x targets. Single-precision add.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.1.1. Instructions testp and copysign have been added. The goal is to achieve IEEE 754 compliance wherever possible. Both fma.f32 maps to fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2.and double-precision div. • • • • • 170 January 24.1. The changes from PTX ISA 1. The fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. and sqrt with IEEE 754 compliant rounding have been added. fma. The .sat modifiers. while maximizing backward compatibility with legacy PTX 1. mad.f32 for sm_20 targets. A single-precision fused multiply-add (fma) instruction has been added. sub.rm and .rp rounding modifiers for sm_20 targets.0 11. These are indicated by the use of a rounding modifier and require sm_20.1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. rcp.f32 and mad.f32 requires sm_20.1. The mad.f32.ftz modifier may be used to enforce backward compatibility with sm_1x.0 for sm_20 targets. Single.rn.f32 require a rounding modifier for sm_20 targets.

maxnctapersm directive was deprecated and replaced with .minnctapersm to better match its behavior and usage.1. Instructions prefetch and prefetchu have also been added.{and. st. A “vote ballot” instruction. has been added.pred have been added.f32 have been implemented. Instructions {atom. vote. 11.u32 and bar.ge. A system-level membar instruction.g.red. local.arrive instruction has been added.le. has been added.red.shared have been extended to handle 64-bit data types for sm_20 targets. prefetch. bfe and bfi. membar. popc. The .3.clamp and .lt. Other new features Instructions ld. A “find leading non-sign bit” instruction. has been added. suld. 2010 171 .popc. brev. Instructions bar. Bit field extract and insert instructions.zero.sys. . and sust. has been added. A “population count” instruction.1.clamp modifiers. Instruction sust now supports formatted surface stores.section. st. isspacep.gt} have been added. clz. January 24. cvta. %clock64. atom. bar now supports optional thread count and register operands.ballot. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. prefetchu. The bar instruction has been extended as follows: • • • A bar. Video instructions (includes prmt) have been added.red}. e. New instructions A “load uniform” instruction. Instruction cvta for converting global. for prefetching to specified level of memory hierarchy. have been added. bfind.1. Cache operations have been added to instructions ld.Chapter 11.2. ldu. .or}. Release Notes 11.1. has been added. A “count leading zeros” instruction. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added.b32. Surface instructions support additional . and red now support generic addressing. ldu. and shared addresses to generic address and vice-versa has been added.add. New special registers %nsmid. has been added. %lanemask_{eq. A new directive.red}. Instructions {atom. A “bit reversal” instruction.

4 or earlier. . 172 January 24.p sust.3.version is 1.{min.5 and later.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.f32} atom.f32 type is unimplemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.s32. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. Formatted surface load is unimplemented.1.ftz (and cvt for . stack-based ABI is unimplemented. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.PTX ISA Version 2. The underlying. if . 11.f32. or .s32.ftz for PTX ISA versions 1. 2010 .4 and earlier. Formatted surface store with .0 11. Support for variadic functions and alloca are unimplemented. has been fixed. Instruction bra. To maintain compatibility with legacy PTX code.1. cvt.p. Semantic Changes and Clarifications The errata in cvt.2. where .{u32. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.red}. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.target sm_1x. {atom. See individual instruction descriptions for details. the correct number is sixteen. call suld.max} are not implemented. In PTX version 1.u32.5.

including loops preceding the . … @p bra L1_end.0. disables unrolling of0 the loop for which the current block is the loop header.pragma “nounroll”.func bar (…) { … L1_head: . Note that in order to have the desired effect at statement level.pragma strings defined by ptxas. Table 145. Supported only for sm_20 targets. L1_end: … } // do not unroll this loop January 24. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.entry foo (…) . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. disables unrolling for all loops in the entry function body.pragma. and statement levels. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma Strings This section describes the . The “nounroll” pragma is allowed at module. entry-function. Ignored for sm_1x targets. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Descriptions of . L1_body: … L1_continue: bra L1_head. 2010 173 .pragma “nounroll”. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Appendix A. { … } // do not unroll any loop in this function .pragma “nounroll”.

2010 .PTX ISA Version 2.0 174 January 24.

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