NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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......... 5......2.. 6............2................. 41 Destination Operands .............. 34 Variables ..................................................................................4..........................................1.........................4...................................................... Arrays........................ 5......................4.............3.................. Types ................. Types........................... 29 Local State Space ............. State Spaces ... 41 Using Addresses..... Texture....2............ 6......... 5.....1.......... Function declarations and definitions ................................... 5...... 28 Special Register State Space .........................................................1............2..............4................1..... 5.........1...........4.......................... 41 Source Operands. 27 5..... 30 Shared State Space...............................................4...5..................................................................................... Chapter 6......................................... 49 7.. 6.............................................................. 5..........................................................1......7........................ 5........................... 43 Labels and Function Names as Operands ............ 43 6.................................................... 5................................... 49 ii January 24.......2.... 42 Addresses as Operands ........3...................4........................................... Summary of Constant Expression Evaluation Rules ....................................4........................ State Spaces.......... 6..........................2........ Type Conversion..........................5.............. 6..............4............. 38 Alignment ...............................5.................. 43 Vectors as Operands ........... 5...... 33 Fundamental Types ............. 32 5............4................................. 5..... 6..........8...........................6...................... 6................. 29 Global State Space ................................... 6.........................................................................................................4.PTX ISA Version 2............................... 46 6......6.. 44 Scalar Conversions ............... 29 Parameter State Space .......................... 5...5........2.........1................ 5..............................................................................6.......................................................................... 42 Arrays as Operands ..................4............... 37 Variable Declarations ............................................................1................................................. 6........................0 4......... 5.................................. Sampler..................................................................... 5...................................................................................................................... 5................................................................... 37 Array Declarations ....4........................................... 37 Vectors ................. and Variables ......................................................................................................................... 2010 ...........1.........1..................................................... and Vectors ........1. 33 Restricted Use of Sub-Word Sizes ..........4.. 5.....................2....3...........................6.......2.............. and Surface Types ........................................... Operand Costs ............. 33 5.......................... 32 Texture State Space (deprecated) .....................1.........4.......... 41 6. 28 Constant State Space ...............1...................3............ 27 Register State Space ....................1............ 38 Initializers ...............5...................................... Instruction Operands............................ 47 Chapter 7............................ 25 Chapter 5....................................................................................................... Abstracting the ABI .....1........................................................................................ Operand Type Information ...........................5.......1................................................................................. 44 Rounding Modifiers ....... 39 Parameterized Variable Names ...........................................................3....... 39 5.......................

.... 11.........7. 8............. 104 Data Movement and Conversion Instructions .................1...1........... Release Notes .........7..................4....................... Divergence of Threads in Control Constructs ..................... 7.............. Directives .... 8..................1.1....0 .....1...................................... 162 Debugging Directives ...........................................................................x ..........6.......................... 140 Miscellaneous Instructions................................................ 149 Chapter 10.. 54 Chapter 8.......................................7............................ 132 Video Instructions ..................... 57 Manipulating Predicates ................................ Instructions ..................... 11..........................................9......2................................... 56 Comparisons ................2... Instruction Set ................................................. 10............................................4.....1.....7..............7........................7.....................7............................ 63 Integer Arithmetic Instructions ..............................1........................................ 10................................. 129 Parallel Synchronization and Communication Instructions ........................... 8.......6............ 8......................................................2..........................................6...................7........5................ 55 8..................................................... Changes from PTX 1........ Changes in Version 2....1........................1........................ 8................7.......... 10................... 60 8............................... 147 8................ 170 New Features .................. 62 8.................... 169 11................................................................1............................................................. 157 10..................................................... 8..........................................2... Chapter 9.................................................... 172 January 24..................... 8................................1................................................................... 172 Unimplemented Features Remaining ..................................... 10................ 55 Predicated Execution ........................ 8...................1.......... 63 Floating-Point Instructions .................3............................................... 8........3........................... 53 Alloca ....................................10................ 55 PTX Instructions ........................................ 157 Specifying Kernel Entry Points and Functions ....7........1.................3...............4................................. 168 Chapter 11....... Format and Semantics of Instruction Descriptions .....................7............... Type Information for Instructions and Operands .............2.................. 58 8............................. 170 Semantic Changes and Clarifications ........ 8..................................... 2010 iii ... 8............................. 8................................... 52 Variadic functions .... 81 Comparison and Selection Instructions ..................................................3.......................... 59 Operand Size Exceeding Instruction-Type Size .. Special Registers ..7....................................2............................................. 166 Linking Directives .........................6........... 11.................................. 62 Semantics .................................................. 7........ 122 Control Flow Instructions ..... 100 Logic and Shift Instructions .. 8......3.. 108 Texture and Surface Instructions ................. 8.. 160 Performance-Tuning Directives ...........7.................................................... 8.8............................................................................. 8.........4................................................................................................. PTX Version and Target Directives ........................3................ 62 Machine-Specific Semantics of 16-bit Code ...........................................................................................3....................................................................5......................................................................

......... Descriptions of .........pragma Strings.......... 2010 .......0 Appendix A....... 173 iv January 24........PTX ISA Version 2..................

........................................... Table 27............................... 64 Integer Arithmetic Instructions: add........................................................................................................... 70 Integer Arithmetic Instructions: sad ...... Table 18...... 33 Opaque Type Fields in Unified Texture Mode ........................................... Table 6................................................................ 2010 v ............... 58 Type Checking Rules ... 46 Integer Rounding Modifiers ...... Table 7......... Table 9......... 25 State Spaces ................ Table 4. Table 25............................ Table 19..cc ........................................................... Table 20..............................................................cc ................................... Table 16...... Table 17.......................... Table 11........................... 45 Floating-Point Rounding Modifiers ....... Table 8....................... 65 Integer Arithmetic Instructions: sub............................... 23 Constant Expression Evaluation Rules ................................................................. 64 Integer Arithmetic Instructions: sub .. 59 Relaxed Type-checking Rules for Source Operands ...................................................... 67 Integer Arithmetic Instructions: mad ............. Table 21........ 46 Cost Estimates for Accessing State-Spaces ....... Table 24............................................................................... and Bit-Size Types ............................ 57 Floating-Point Comparison Operators ........................................................ Table 12............................. Table 22............................................................................................................................................................................................ 57 Floating-Point Comparison Operators Accepting NaN ......................................... Table 5................ Table 29....... 19 Predefined Identifiers ........................ Table 32........................ Table 26.............. Table 23..................List of Tables Table 1......... Unsigned Integer.......................................................................................................... 28 Fundamental Type Specifiers ...... 18 Reserved Instruction Keywords ...................................... 66 Integer Arithmetic Instructions: mul .................................................................................................... 61 Integer Arithmetic Instructions: add ................................ 66 Integer Arithmetic Instructions: subc ....... Table 3..... PTX Directives ........................................................................... 65 Integer Arithmetic Instructions: addc ....... Table 15........ 60 Relaxed Type-checking Rules for Destination Operands............................................ Table 13............................. 47 Operators for Signed Integer................................................................... 35 Convert Instruction Precision and Format .................................... 20 Operator Precedence ................................. 35 Opaque Type Fields in Independent Texture Mode ......... 58 Floating-Point Comparison Operators Testing for NaN ........................ Table 14... Table 31.............................. Table 2................... Table 28.... 69 Integer Arithmetic Instructions: mad24 .......... Table 10.................................. 71 January 24.............................. Table 30................................................................................................................................................... 68 Integer Arithmetic Instructions: mul24 ................................................................ 27 Properties of State Spaces ................

...... 95 Floating-Point Instructions: sin ............................................................... 92 Floating-Point Instructions: rcp ................... Table 58....... Integer Arithmetic Instructions: div ........................... Table 48....................................................... Table 45... 87 Floating-Point Instructions: mad ................. 91 Floating-Point Instructions: neg ............... 103 vi January 24................................. Table 40............................. 83 Floating-Point Instructions: add .................................................. 92 Floating-Point Instructions: max ................. 77 Integer Arithmetic Instructions: bfi ....... 73 Integer Arithmetic Instructions: max .................................................................................................... Table 49...................................... 72 Integer Arithmetic Instructions: neg ................................................................................................................................... Table 43....................... 101 Comparison and Selection Instructions: setp ............................................................. 79 Summary of Floating-Point Instructions .................... Table 41................... 90 Floating-Point Instructions: abs ........................................................................ 93 Floating-Point Instructions: sqrt ....................................... Table 44...................................... 76 Integer Arithmetic Instructions: bfe .................. 103 Comparison and Selection Instructions: slct ........................................PTX ISA Version 2..................................................................... Table 55............................................... Table 38.................................................... 73 Integer Arithmetic Instructions: popc ........................................................................................... Table 59......................................................................... 74 Integer Arithmetic Instructions: clz .............................................................................................. 71 Integer Arithmetic Instructions: abs ..................... Table 42..................................... 98 Floating-Point Instructions: ex2 ................. 74 Integer Arithmetic Instructions: bfind ...... 102 Comparison and Selection Instructions: selp ........ 94 Floating-Point Instructions: rsqrt ............................................. Table 66.................... Table 63..................................................................................... 86 Floating-Point Instructions: fma ..... 71 Integer Arithmetic Instructions: rem ............. Table 56............................... Table 36........ Table 57............................................................... Table 54................................................... 75 Integer Arithmetic Instructions: brev ....................................................................................................... Table 51........................................................................................................................... 2010 ... 83 Floating-Point Instructions: copysign ....................................................................... Table 53........................................ 78 Integer Arithmetic Instructions: prmt ............ 96 Floating-Point Instructions: cos ................................. Table 60.................0 Table 33.................................................. Table 34...... 97 Floating-Point Instructions: lg2 . 72 Integer Arithmetic Instructions: min ........................................ Table 50..... Table 69................ Table 52............. 82 Floating-Point Instructions: testp ..... 88 Floating-Point Instructions: div ....... Table 35.............................. Table 68................. Table 64............. Table 62..... Table 65................................... Table 39. 99 Comparison and Selection Instructions: set ...... Table 67................... Table 47........................................... 84 Floating-Point Instructions: sub ........................................................................................................ 85 Floating-Point Instructions: mul ................................................................ Table 46.......................................... 91 Floating-Point Instructions: min ............................................... Table 37..................................................... Table 61.....

.......................... Table 83.. Table 103..... Table 93......................... 105 Logic and Shift Instructions: xor ...... 129 Control Flow Instructions: bra ............................................................................. 124 Texture and Surface Instructions: suld ........... vmin........................................... 111 Data Movement and Conversion Instructions: mov .. 123 Texture and Surface Instructions: txq ........... vshr .................................. Table 81.................. 130 Control Flow Instructions: call .......... vsub.................... Table 96............. 119 Data Movement and Conversion Instructions: cvt ..... Table 97.................................................................................... 118 Data Movement and Conversion Instructions: isspacep ........................................................................................ Table 76............................................. 109 Cache Operators for Memory Store Instructions ................................................................................................... Table 75.................... 110 Data Movement and Conversion Instructions: mov ................................... Table 101.............................................. Table 77....... Table 73........... 128 Control Flow Instructions: { } . Table 87........ Table 80........ Table 105.................... 106 Logic and Shift Instructions: not ............................................................................................... 106 Logic and Shift Instructions: cnot .......................................................... 133 Parallel Synchronization and Communication Instructions: membar ...................................................................................................... 107 Logic and Shift Instructions: shr ... vabsdiff......... 129 Control Flow Instructions: @ ..... 116 Data Movement and Conversion Instructions: prefetch.............................................Table 70................................................. Table 106............................................... 139 Video Instructions: vadd......................................................... Table 82.................................... Table 98... 105 Logic and Shift Instructions: or .......................... 125 Texture and Surface Instructions: sust ...... Table 72................................................................ Table 78......................................... Table 84......................................................................... Table 74................ 2010 vii .......... 126 Texture and Surface Instructions: sured........... Table 91.............................................. 127 Texture and Surface Instructions: suq ............... Table 86.................................................... Table 94............. 107 Cache Operators for Memory Load Instructions ...................................................................... Logic and Shift Instructions: and .. 142 Video Instructions: vshl.... 106 Logic and Shift Instructions: shl ..... prefetchu ..... Table 88............... Table 85....................................... Table 90.... 112 Data Movement and Conversion Instructions: ld ........... 135 Parallel Synchronization and Communication Instructions: red ................... 143 January 24.................... 119 Data Movement and Conversion Instructions: cvta ................... Table 92.............. Table 104..... Table 95..................... 113 Data Movement and Conversion Instructions: ldu ... 131 Parallel Synchronization and Communication Instructions: bar .. Table 89........................ 115 Data Movement and Conversion Instructions: st ................................................... Table 79....... Table 99.............. 134 Parallel Synchronization and Communication Instructions: atom ........... Table 102......................... 120 Texture and Surface Instructions: tex ................................................ Table 100...... Table 71................................................... 137 Parallel Synchronization and Communication Instructions: vote ....... 131 Control Flow Instructions: exit ......... vmax ............................... 130 Control Flow Instructions: ret .........................

....................................... Table 127..................extern.................................................................................................................... 160 Kernel and Function Directives: ................. Table 117................................................... 161 Performance-Tuning Directives: ................................................. 155 Special Registers: %clock .............. 164 Performance-Tuning Directives: ...... 146 Miscellaneous Instructions: trap ............................ 158 Kernel and Function Directives: ...... 167 Debugging Directives: ............................ Table 125.......... Table 116........................................................................................ 156 Special Registers: %pm0............version.........................loc ........... 147 Miscellaneous Instructions: pmevent.... Table 130...................................................................PTX ISA Version 2......................... Table 142...... 154 Special Registers: %lanemask_ge .... 152 Special Registers: %smid .................func ... Table 120.................. Table 123.............................................................................................................................. Table 140........................ Table 141......... Table 132............................................................ Table 114.................................................................................................................................... Table 122.............file ....................................... 163 Performance-Tuning Directives: .................................... Table 126........................................ 151 Special Registers: %warpid ....... Table 121............ Table 112.............. 151 Special Registers: %nwarpid ............................................. %pm2.........pragma .............................. 166 Debugging Directives: ............................... 147 Special Registers: %tid ... Table 131...................... 2010 ............................................................................... Table 136.................................................................................................... 156 Special Registers: %clock64 ................................ Table 110........................ Table 124............. Table 137.... 168 viii January 24........................... 154 Special Registers: %lanemask_le ............... Table 113............................................................................................................... 163 Performance-Tuning Directives: .................... Table 135.................. Table 119......................................................................section ....... Table 108............................................. Table 115.....maxntid ......................target ........................................................ Table 128............................. Table 129................. 150 Special Registers: %laneid ....................... 147 Miscellaneous Instructions: brkpt ......................................... 153 Special Registers: %gridid .... 167 Debugging Directives: ........ Table 133.......................... Table 138.............................. 151 Special Registers: %ctaid .. Table 111............................. 165 Debugging Directives: @@DWARF ..................... 153 Special Registers: %lanemask_eq ................ 144 Video Instructions: vset.......minnctapersm .................................maxnreg ......................... 153 Special Registers: %nsmid .. 155 Special Registers: %lanemask_gt ............................................................ %pm3 .................. 150 Special Registers: %ntid ......... Table 143......................maxnctapersm (deprecated) ...................................0 Table 107............ 164 Performance-Tuning Directives: ................. Video Instructions: vmad ........................................ Table 109................. 156 PTX File Directives: .........entry................................ Table 118........................... Table 134. 167 Linking Directives: ................... 154 Special Registers: %lanemask_lt ............................................. 157 PTX File Directives: ............................................ 152 Special Registers: %nctaid .... %pm1...................... Table 139................................

.................... 173 January 24........................................................ Linking Directives: . 168 Pragma Strings: “nounroll” ........................Table 144..............................visible........ Table 145........... 2010 ix .....................

0 x January 24. 2010 .PTX ISA Version 2.

Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. multithreaded. Data-parallel processing maps data elements to parallel processing threads. PTX programs are translated at install time to the target hardware instruction set. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. the programmable GPU has evolved into a highly parallel. and pattern recognition can map image blocks and pixels to parallel processing threads. which are optimized for and translated to native target-architecture instructions. Introduction This document describes PTX. stereo vision. many-core processor with tremendous computational horsepower and very high memory bandwidth. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. 1. there is a lower requirement for sophisticated flow control. In fact. image scaling. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). from general signal processing or physics simulation to computational finance or computational biology. 1. 2010 1 . the memory access latency can be hidden with calculations instead of big data caches. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions.2. and because it is executed on many data elements and has high arithmetic intensity. image and media processing applications such as post-processing of rendered images. PTX exposes the GPU as a data-parallel computing device. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. video encoding and decoding.1. Similarly. Because the same program is executed for each data element. January 24.Chapter 1. PTX defines a virtual machine and ISA for general purpose parallel thread execution. high-definition 3D graphics. Many applications that process large data sets can use a data-parallel programming model to speed up the computations.

0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. sub. Most of the new features require a sm_20 target. and architecture tests. Provide a machine-independent ISA for C/C++ and other compilers to target. performance kernels.f32 for sm_20 targets. mad. reduction. barrier. addition of generic addressing to facilitate the use of general-purpose pointers.0 are improved support for IEEE 754 floating-point operations.3. and mul now support . PTX ISA Version 2. Facilitate hand-coding of libraries.3. surface.f32 maps to fma. 2010 . Instructions marked with .x code will continue to run on sm_1x targets as well. 1.f32 requires sm_20. When code compiled for sm_1x is executed on sm_20 devices. including integer. memory.0 is a superset of PTX 1. which map PTX to specific target machines. The main areas of change in PTX 2. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.x.ftz and . Both fma.f32 require a rounding modifier for sm_20 targets. 1. A “flush-to-zero” (. Legacy PTX 1. atomic. A single-precision fused multiply-add (fma) instruction has been added. Improved Floating-Point Support A main area of change in PTX 2. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. The fma.rn. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. • • • 2 January 24.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. PTX 2.rm and .x features are supported on the new sm_20 target.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. and video instructions. The mad.ftz) modifier may be used to enforce backward compatibility with sm_1x.f32.f32 and mad.0 PTX ISA Version 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.f32 instruction also supports .1. fma.0 is in improved support for the IEEE 754 floating-point standard.sat modifiers. and all PTX 1. Achieve performance in compiled applications comparable to native GPU performance.rp rounding modifiers for sm_20 targets. and the introduction of many new instructions. Single-precision add. The changes from PTX ISA 1. Provide a code distribution ISA for application and middleware developers. Provide a common source-level ISA for optimizing code generators and translators. The mad.PTX ISA Version 2.

and shared addresses to generic addresses.Chapter 1. and sust. These are indicated by the use of a rounding modifier and require sm_20. cvta. an address that is the same across all threads in a warp. Instruction cvta for converting global. instructions ld. Introduction • Single.clamp and . suld. . and directives are introduced in PTX 2. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. In PTX 2. allowing memory instructions to access these spaces without needing to specify the state space. Surface instructions support additional clamp modifiers. 1. Generic Addressing Another major change is the addition of generic addressing. local.4. st.0 closer to full compliance with the IEEE 754 standard.3. A new cvta instruction has been added to convert global. atom. Instructions prefetch and prefetchu have been added. and red now support generic addressing. Instructions testp and copysign have been added. st. PTX 2. isspacep.3. NOTE: The current version of PTX does not implement the underlying..and double-precision div. prefetch.0. 1. for prefetching to specified level of memory hierarchy.3.e. Support for an Application Binary Interface Rather than expose details of a particular calling convention. January 24. Generic addressing unifies the global. New Instructions The following new instructions. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. special registers. local. rcp. and sqrt with IEEE 754 compliant rounding have been added. and shared state spaces. local.0. and Application Binary Interface (ABI). stack layout. and shared addresses to generic address and vice-versa has been added. stack-based ABI. and vice versa.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.g. so recursion is not yet supported. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.2. Cache operations have been added to instructions ld. prefetchu. • Taken as a whole. ldu.zero. Surface Instructions • • Instruction sust now supports formatted surface stores. i. these changes bring PTX 2. 1. 2010 3 .3. e.

A new directive.add.red}.gt} have been added. Instructions {atom. vote.pred have been added.PTX ISA Version 2. A bar. Barrier Instructions • • A system-level membar instruction.red}.{and. has been added.or}.sys. Reduction. .b32. has been added.red. %clock64. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.le. membar.u32 and bar. %lanemask_{eq.ballot. A “vote ballot” instruction. bar now supports an optional thread count and register operands. New special registers %nsmid.popc.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.f32 have been added.ge.section.shared have been extended to handle 64-bit data types for sm_20 targets. and Vote Instructions • • • New atomic and reduction instructions {atom.arrive instruction has been added.lt. 4 January 24.red. 2010 . Other Extensions • • • Video instructions (includes prmt) have been added. Instructions bar. bfi bit field extract and insert popc clz Atomic.

Chapter 6 describes instruction operands. Chapter 11 provides release notes for PTX Version 2.4. Chapter 7 describes the function and call syntax. and variable declarations. Chapter 8 describes the instruction set. calling convention. Chapter 9 lists special registers. 2010 5 . Introduction 1. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 10 lists the assembly directives supported in PTX. Chapter 4 describes the basic syntax of the PTX language. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. January 24.Chapter 1.0. types. Chapter 5 describes state spaces. and PTX support for abstracting the Application Binary Interface (ABI).

0 6 January 24.PTX ISA Version 2. 2010 .

y. 2D. More precisely. one can specify synchronization points where threads wait until all threads in the CTA have arrived. To coordinate the communication of the threads within the CTA. January 24. is an array of threads that execute a kernel concurrently or in parallel. Programming Model 2. The vector ntid specifies the number of threads in each CTA dimension.y. but independently on different data.x. compute-intensive portions of applications running on the host are off-loaded onto the device. can be isolated into a kernel function that is executed on the GPU as many different threads.z). (with elements tid.2. or 3D CTA. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. a portion of an application that is executed many times. 2D. Each CTA has a 1D. It operates as a coprocessor to the main CPU.2. A cooperative thread array. 2010 7 .Chapter 2. To that effect. assign specific input and output positions. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. 2. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.x. compute addresses. Programs use a data parallel decomposition to partition inputs. data-parallel.1. 2. Threads within a CTA can communicate with each other. Each thread has a unique thread identifier within the CTA.z) that specifies the thread’s position within a 1D. and results across the threads of the CTA. and select work to perform. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. and tid.1. Cooperative thread arrays (CTAs) implement CUDA thread blocks. and ntid. Each CTA thread uses its thread identifier to determine its assigned role. The thread identifier is a three-element vector tid. or CTA. ntid. tid. or 3D shape specified by a three-element vector ntid (with elements ntid. or host: In other words. work.

2D . The host issues a succession of kernel invocations to the device. %nctaid. A warp is a maximal subset of threads from a single CTA.2. Multiple CTAs may execute concurrently and in parallel.2. CTAs that execute the same kernel can be batched together into a grid of CTAs. or sequentially. Some applications may be able to maximize performance with knowledge of the warp size. %ctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. 8 January 24. Each grid of CTAs has a 1D. because threads in different CTAs cannot communicate and synchronize with each other. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. WARP_SZ. and %gridid. However. read-only special registers %tid. multiple-thread) fashion in groups called warps.PTX ISA Version 2. such that the threads execute the same instructions at the same time. Threads may read and use these values through predefined. Threads within a warp are sequentially numbered.0 Threads within a CTA execute in SIMT (single-instruction. or 3D shape specified by the parameter nctaid. which may be used in any instruction where an immediate operand is allowed. depending on the platform. 2. This comes at the expense of reduced thread communication and synchronization. The warp size is a machine-dependent constant. %ntid. 2010 . Each grid also has a unique temporal grid identifier (gridid). so that the total number of threads that can be launched in a single kernel invocation is very large. so PTX includes a run-time immediate constant. Typically. a warp has 32 threads. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1).

1) Grid 2 Kernel 2 CTA (1. 0) CTA (2. 2) Thread (1. 2010 9 . Thread Batching January 24. 1) Thread (1.Chapter 2. 2) Thread (3. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (4. 2) Thread (4. 1) CTA (2. 1) Thread (3. 0) Thread (4. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (2. 1) Thread (0. 1) CTA (1. 0) CTA (1. 1) Thread (0. 0) Thread (3. 0) Thread (0. A grid is a set of CTAs that execute independently. Figure 1. 0) Thread (1. 1) Thread (2. 0) Thread (2. 0) CTA (0.

There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.PTX ISA Version 2. and texture memory spaces are persistent across kernel launches by the same application. respectively. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. or. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Each thread has a private local memory. all threads have access to the same global memory. Both the host and the device maintain their own local memory. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2.0 2. Finally. The device memory may be mapped and read or written by the host. The global. constant. 2010 . The global. 10 January 24. referred to as host memory and device memory. and texture memory spaces are optimized for different memory usages. for more efficient transfer. as well as data filtering. for some specific data formats. Texture memory also offers different addressing modes.3. constant.

0) Block (0. 1) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Figure 2. 1) Grid 1 Global memory Block (0. Memory Hierarchy January 24. 1) Block (0. 0) Block (2. 2) Block (1. 0) Block (0. 0) Block (1.Chapter 2. 0) Block (1. 2010 11 . 1) Block (1. 1) Block (2.

PTX ISA Version 2.0 12 January 24. 2010 .

The way a block is split into warps is always the same. schedules. At every instruction issue time. multiple-thread). a cell in a grid-based computation). each warp contains threads of consecutive.Chapter 3. disabling threads that are not on that path. The multiprocessor SIMT unit creates. 2010 13 . If threads of a warp diverge via a data-dependent conditional branch. the multiprocessor employs a new architecture we call SIMT (single-instruction. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. and when all paths complete. When a multiprocessor is given one or more thread blocks to execute. A multiprocessor consists of multiple Scalar Processor (SP) cores. and on-chip shared memory. a voxel in a volume. the warp serially executes each branch path taken. It implements a single-instruction barrier synchronization. the first parallel thread technology. allowing. The multiprocessor creates. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and executes threads in groups of parallel threads called warps.1. the threads converge back to the same execution path. A warp executes one common instruction at a time. so full efficiency is realized when all threads of a warp agree on their execution path. manages. new blocks are launched on the vacated multiprocessors. for example. (This term originates from weaving. When a host program invokes a kernel grid. To manage hundreds of threads running several different programs. The threads of a thread block execute concurrently on one multiprocessor. The multiprocessor maps each thread to one scalar processor core. a multithreaded instruction unit. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. and executes concurrent threads in hardware with zero scheduling overhead. and each scalar thread executes independently with its own instruction address and register state. January 24. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. Branch divergence occurs only within a warp. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). increasing thread IDs with the first warp containing thread 0. different warps execute independently regardless of whether they are executing common or disjointed code paths. Parallel Thread Execution Machine Model 3. As thread blocks terminate. it splits them into warps that get scheduled by the SIMT unit. manages.

As illustrated by Figure 3. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. the programmer can essentially ignore the SIMT behavior. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. In practice. modify. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. A key difference is that SIMD vector organizations expose the SIMD width to the software. In contrast with SIMD vector machines. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. whereas SIMT instructions specify the execution and branching behavior of a single thread. A multiprocessor can execute as many as eight thread blocks concurrently. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. require the software to coalesce loads into vectors and manage divergence manually. • The local and global memory spaces are read-write regions of device memory and are not cached. SIMT enables programmers to write thread-level parallel code for independent. as well as data-parallel code for coordinated threads. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. on the other hand. write to that location occurs and they are all serialized. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. 2010 . which is a read-only region of device memory. scalar threads. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. modifies. the number of serialized writes that occur to that location and the order in which they occur is undefined.PTX ISA Version 2. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. however. but one of the writes is guaranteed to succeed. the kernel will fail to launch. 14 January 24. but the order in which they occur is undefined. which is a read-only region of device memory. For the purposes of correctness.0 SIMT architecture is akin to SIMD (Single Instruction. Vector architectures. If an atomic instruction executed by a warp reads. each read. and writes to the same location in global memory for more than one of the threads of the warp. If there are not enough registers or shared memory available per multiprocessor to process at least one block.

Chapter 3. Hardware Model January 24. 2010 15 . Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

2010 .0 16 January 24.PTX ISA Version 2.

PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. January 24. 4. Comments in PTX are treated as whitespace. See Section 9 for a more information on these directives. All whitespace characters are equivalent.1. Source Format Source files are ASCII text. #ifdef. The following are common preprocessor directives: #include. PTX is case sensitive and uses lowercase for keywords.target directive specifying the target architecture assumed. The C preprocessor cpp may be used to process PTX source files. 4. #if. and using // to begin a comment that extends to the end of the current line.Chapter 4. #endif. Lines are separated by the newline character (‘\n’). #line.2. #else. whitespace is ignored except for its use in separating tokens in the language. Lines beginning with # are preprocessor directives. followed by a . #define. Comments Comments in PTX follow C/C++ syntax. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. Each PTX file must begin with a . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Pseudo-operations specify symbol and addressing management. 2010 17 . Syntax PTX programs are a collection of text source files.version directive specifying the PTX language version. using non-nested /* and */ for comments that may span multiple lines.

sreg . where p is a predicate register.x. %tid. so no conflict is possible with user-defined identifiers. The destination operand is first.version . 18 January 24. Table 1. The guard predicate may be optionally negated. r1.minnctapersm .maxnreg .shared .entry . 0. mov.3.target .global.align . r2. The guard predicate follows the optional label and precedes the opcode.reg . r2.global start: .2. Instructions have an optional guard predicate which controls conditional execution.const .5. Operands may be register variables. Instruction keywords are listed in Table 2. and is written as @p.f32 array[N].1.func .b32 r1.0 4.loc . Statements begin with an optional label and end with a semicolon. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. ld. Examples: . written as @!p. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. r2.b32 r1.PTX ISA Version 2.section . 2010 .tex . Statements A PTX statement is either a directive or an instruction.f32 r2.global . . followed by source operands.b32 add. Directive Statements Directive keywords begin with a dot. or label names.param .3. . All instruction keywords are reserved tokens in PTX. array[r1]. constant expressions.reg . 2. shl. and terminated with a semicolon.extern .local .visible 4.maxnctapersm .file PTX Directives . address expressions.pragma .b32 r1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.maxntid .3.

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4. 2010 19 . Syntax Table 2.

Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.PTX ISA Version 2. except that the percentage sign is not allowed. Many high-level languages such as C and C++ follow similar rules for identifier names. underscore. or they start with an underscore. The percentage sign can be used to avoid name conflicts. digits.g. PTX predefines one constant and a small number of special registers that begin with the percentage sign. %pm3 WARP_SZ 20 January 24. …. listed in Table 3. or dollar characters. digits. or percentage character followed by one or more letters. e.0 4. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. between user-defined variable names and compiler-generated names.4. 2010 . dollar. PTX allows the percentage sign as the first character of an identifier. Table 3. underscore. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.

To specify IEEE 754 doubleprecision floating point values.u64). every integer constant has type ..u64. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.1. octal. floating-point. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.5. Integer literals may be written in decimal.e. 4. Unlike C and C++. there is no suffix letter to specify size. 2010 21 .2. 4. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. The syntax follows that of C. or binary notation.s64) unless the value cannot be fully represented in .5.. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. Type checking rules remain the same for integer. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. the constant begins with 0d or 0D followed by 16 hex digits. 0[fF]{hexdigit}{8} // single-precision floating point January 24. and bit-size types. where the behavior of the operation depends on the operand types.5. To specify IEEE 754 single-precision floating point values. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.Chapter 4. Syntax 4.s64 or the unsigned suffix is specified. i. each integer constant is converted to the appropriate size based on the data or instruction type at its use. literals are always represented in 64-bit double-precision format. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. These constants may be used in data initialization and as operands to instructions. For predicate-type data and instructions.s64 or . in which case the literal is unsigned (. integer constants are allowed and are interpreted as in C. hexadecimal. the constant begins with 0f or 0F followed by 8 hex digits. Constants PTX supports integer and floating-point constants and constant expressions. zero values are FALSE and non-zero values are TRUE. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. When used in an instruction or data initialization. Floating-point literals may be written with an optional decimal point and an optional signed exponent.e. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. the sm_1x and sm_20 targets have a WARP_SZ value of 32. i.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.Chapter 4.s64 .s64 .6.f64 converted type .f64 converted type constant literal + ! ~ Cast Binary (.f64 integer integer integer integer integer int ?.u64 . Syntax 4.u64 1st unchanged.s64 .u64 same as 1st operand .u64 .5. or .s64 .f64 integer .s64) + .f64 : . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64) (.s64.s64 .f64 use usual conversions . 2nd is . .u64 .s64 . 2010 25 .f64 use usual conversions .s64 . Table 5.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .f64 use usual conversions .u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64 .f64 integer . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 same as source .u64 .u64.s64 .

PTX ISA Version 2. 2010 .0 26 January 24.

tex January 24. shared by all threads. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. and Variables While the specific resources available in a given target GPU will vary. Global texture memory (deprecated). and properties of state spaces are shown in Table 5. Global memory. Special registers. State Spaces. The list of state spaces is shown in Table 4. and these resources are abstracted in PTX through state spaces and data types. Kernel parameters. access speed. addressability.global .shared . pre-defined. defined per-thread.local . All variables reside in some state space. Read-only. and level of sharing between threads. Shared. 5. Local memory.sreg . read-only memory. private to each thread. access rights.1. defined per-grid.reg . State Spaces A state space is a storage area with particular characteristics. 2010 27 .Chapter 5. Addressable memory shared between threads in 1 CTA.param . platform-specific. fast. the kinds of resources will be common across platforms. or Function or local parameters. Table 6. Types.const . The characteristics of a state space include its size. Name State Spaces Description Registers. .

st. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. For each architecture.param instructions. 2010 . scalar registers have a width of 8-. Register size is restricted. aside from predicate registers which are 1-bit. and performance monitoring registers. 64-. Registers may have alignment boundaries required by multi-word loads and stores.0 Table 7. The most common use of 8-bit registers is with ld. or as elements of vector tuples.reg state space) are fast storage locations. Registers differ from the other state spaces in that they are not fully addressable.1. 3 Accessible only via the tex instruction.. The number of registers is limited.e. 32-. When the limit is exceeded. Register State Space Registers (. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . and thread parameters. predicate) or untyped.local .param instruction.1. CTA.param (used in functions) . clock counters.const .1. 1 Accessible only via the ld. unsigned integer. All special registers are predefined. and will vary from platform to platform. platform-specific registers.param and st.tex Restricted Yes No3 5.sreg) state space holds predefined. floating point. it is not possible to refer to the address of a register.shared .2. Registers may be typed (signed integer.global . register variables will be spilled to memory. or 128-bits. or 64-bits.param (as input to kernel) . causing changes in performance.reg . i. 5.PTX ISA Version 2. 32-. the parameter is then located on the stack frame and its address is in the . and cvt instructions. Address may be taken via mov instruction. 16-. Device function input parameters may have their address taken via mov.local state space.sreg . such as grid. 28 January 24. Special Register State Space The special register (. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 2 Accessible via ld. and vector registers have a width of 16-.

and atom. all addresses are in global memory are shared. State Spaces. the bank number must be provided in the state space of the load instruction. Banks are specified using the . Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. initialized by the host. For example.1. To access data in contant banks 1 through 10. ld. results in const_buffer pointing to the start of constant bank two. This reiterates the kind of parallelism available in machines that run PTX.const[2] . the store operation updating a may still be in flight. In implementations that support a stack. For example. The size is limited. there are eleven 64KB banks.4. the declaration .b32 const_buffer[].local and st. 2010 29 .1.const[2]. where the size is not known at compile time. Global memory is not sequentially consistent. The remaining banks may be used to implement “incomplete” constant arrays (in C. b = b – 1. Constant State Space The constant (.const[2] . as in lock-free and wait-free style programming. for example).1. bank zero is used. For any thread in a context. It is the mechanism by which different CTAs and different grids can communicate. each pointing to the start address of the specified constant bank.Chapter 5. Module-scoped local memory variables are stored at fixed addresses. If no bank number is given.global. an incomplete array in bank 2 is accessed as follows: . st.global to access global variables. the stack is in local memory. Threads must be able to do their work without waiting for other threads to do theirs. as it must be allocated on a perthread basis. It is typically standard memory with cache. This pointer can then be used to access the entire 64KB constant bank. The constant memory is organized into fixed size banks. Local State Space The local state space (. where bank ranges from 0 to 10. [const_buffer+4]. Use ld. Threads wait at the barrier until all threads in the CTA have arrived. Multiple incomplete array variables declared in the same bank become aliases. 5. All memory writes prior to the bar.sync instruction are guaranteed to be visible to any reads after the barrier instruction.extern .local to access local variables. For the current devices. Consider the case where one thread executes the following two assignments: a = a + 1.5. Use ld. If another thread sees the variable b change.3.b32 const_buffer[]. whereas local memory variables declared January 24. bank zero is used for all statically-sized constant variables. Types.b32 %r1. // load second word 5.local) is private memory for each thread to keep its own data. and Variables 5. Sequential consistency is provided by the bar.global.const[bank] modifier.extern .global) state space is memory that is accessible by all threads in a context.const) state space is a read-only memory. By convention. Global State Space The global (.sync instruction.

5. [N]. Therefore.param. in some implementations kernel parameters reside in global memory.u32 %n.b32 len ) { .align 8 .1.param) state space is used (1) to pass input arguments from the host to the kernel. 2010 . ld.param state space. In implementations that do not support a stack.0 and requires target architecture sm_20. No access protection is provided between parameter and global space in this case.param. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.entry foo ( . … Example: .param space.param .u32 %n.f64 %d. 5. The resulting address is in the . ld. len. Parameter State Space The parameter (. mov.f64 %d.param.reg . The use of parameter state space for device function parameters is new to PTX ISA version 2. These parameters are addressable.u32 %n.u32 %ptr.reg . . Example: .6.6. per-kernel versus per-thread). Note: The location of parameter space is implementation specific. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Note that PTX ISA versions 1. [%ptr]. For example. (2a) to declare formal input and return parameters for device functions called from within kernel execution.b8 buffer[64] ) { .PTX ISA Version 2. Similarly. … 30 January 24.param instructions.u32 %ptr.param state space and is accessed using ld. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. read-only variables declared in the . typically for passing large structures by value to a function.reg .param space variables.param . Kernel Function Parameters Each kernel function definition includes an optional list of parameters. The kernel parameter variables are shared across all CTAs within a grid.param . ld.1.param instructions.x supports only kernel function parameters in .0 within a function or kernel body are allocated on the stack. device function parameters were previously restricted to the register state space.entry bar ( . . %n. The address of a kernel parameter may be moved into a register using the mov instruction. [buffer].1. Values passed from the host to the kernel are accessed through these parameter variables using ld. PTX code should make no assumptions about the relative locations or ordering of . all local memory variables are stored at fixed addresses and recursive function calls are not supported.b32 N.

param.reg .f64 %d. .f64 [mystruct+0]. [buffer+8]. Aside from passing structures by value.param . int y. x.s32 x. 2010 31 . It is not possible to use mov to get the address of a return parameter or a locally-scoped .s32 %y. such as C structures larger than 8 bytes. and so the address will be in the . call foo.6.b8 mystruct.param. ld.reg . which declares a .0 extends the use of parameter space to device function parameters.reg . This will be passed by value to a callee. In this case. the address of a function input parameter may be moved into a register using the mov instruction. passed to foo … . Types. a byte array in parameter space is used.b8 buffer[12] ) { . … st. January 24.reg .param and function return parameters may be written using st. The most common use is for passing objects by value that do not fit within a PTX register.s32 [mystruct+8]. In PTX. st. Function input parameters may be read via ld.reg .param byte array variable that represents a flattened C structure or union. . State Spaces. Typically.f64 %d. Device Function Parameters PTX ISA version 2. ld. … } // code snippet from the caller // struct { double d.align 8 .func foo ( . .local state space and is accessed via ld.param space is also required whenever a formal parameter has its address taken within the called function. is flattened. int y. (4.local instructions. the caller will declare a locally-scoped . and Variables 5.param.f64 dbl. dbl. Note that the parameter will be copied to the stack if necessary.param.param formal parameter having the same size and alignment as the passed argument. .param. it is illegal to write to an input parameter or read from a return parameter. }.align 8 . } mystruct. .s32 %y.b32 N.Chapter 5.local and st.param space variable. [buffer].2.param . mystruct). . … See the section on function call syntax for more details. Example: // pass object of type struct { double d.1.

Shared State Space The shared (. Physical texture resources are allocated on a per-module granularity. 32 January 24.shared to access shared variables.texref type and Section 8. The . Texture memory is read-only. Use ld.tex variables are required to be defined in the global scope.8. Multiple names may be bound to the same physical texture identifier.u64. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.tex .u32 tex_a. The texture name must be of type .tex directive will bind the named texture memory variable to a hardware texture identifier. An error is generated if the maximum number of physical resources is exceeded.tex . A texture’s base address is assumed to be aligned to a 16-byte boundary.0 5. where texture identifiers are allocated sequentially beginning with zero.tex .1.texref tex_a.u32 .PTX ISA Version 2. tex_f. is equivalent to .tex state space are equivalent to module-scoped .3 for the description of the . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). For example.u32 or .tex directive is retained for backward compatibility. The .u32 tex_a. An address in shared memory can be read and written by any thread in a CTA. Texture State Space (deprecated) The texture (.tex . 5.shared) state space is a per-CTA region of memory for threads in a CTA to share data. and . 2010 . One example is broadcast. Another is sequential access from sequential threads.global .u32 . and programs should instead reference texture memory through variables of type .shared and st. tex_d.u32 . See Section 5. where all threads read from the same address. tex_c. and variables declared in the . Example: .global state space.1. Shared memory typically has some optimizations to support the sharing.texref variables in the .6 for its use in texture instructions.7. It is shared by all threads in a context.tex) state space is global memory accessed via the texture instruction.tex .7.texref. a legacy PTX definitions such as . tex_d.

u32. Types.f64 types.f64 . . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .2.f16 floating-point type is allowed only in conversions to and from . Restricted Use of Sub-Word Sizes The . stored.Chapter 5. State Spaces.s64 .f32 and . all variables (aside from predicates) could be declared using only bit-size types.pred Most instructions have one or more type specifiers. so their names are intentionally short.2.f64 types. January 24.f32 and . .s16. In principle. and .f16.2.2. ld. A fundamental type specifies both a basic type and a size. or converted to other types and sizes. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Two fundamental types are compatible if they have the same basic type and are the same size. . Fundamental Types In PTX. . .b64 .b32. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. and converted using regular-width registers.b8 instruction types are restricted to ld. . . .u8.1. Operand types and sizes are checked against instruction types for compatibility. The . For convenience. All floating-point instructions operate only on .b8. but typed variables enhance program readability and allow for better operand type checking. The same typesize specifiers are used for both variable definitions and for typing instructions. Signed and unsigned integer types are compatible if they have the same size.u16. The bitsize type is compatible with any fundamental type having the same size. and cvt instructions. . . 5.s8. and instructions operate on these types. Register variables are always of a fundamental type.u64 . For example. st. the fundamental types reflect the native data types supported by the target architectures. so that narrow values may be loaded.b16. The following table lists the fundamental type specifiers for each basic type: Table 8.u8. 2010 33 . st.f32.s8. and Variables 5. . Types 5.s32. stored. needed to fully specify instruction behavior. .

. or surfaces via texture and surface load/store instructions (tex. Retrieving the value of a named member via query instructions (txq. suq).PTX ISA Version 2. texture and sampler information each have their own handle. allowing them to be defined separately and combined at the site of usage in the program. In the independent mode. Creating pointers to opaque variables using mov. base address. For working with textures and samplers.{u32. hence the term “opaque”.samplerref variables. field ordering. opaque_var.e. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. Referencing textures. In the unified mode.texref handle. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. and surface descriptor variables.texref. and overall size is hidden to a PTX program. 34 January 24.surfref. PTX has two modes of operation. 2010 .0 5.texref type that describe sampler properties are ignored. store. Sampler.samplerref. In independent mode the fields of the . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. passed as a parameter to functions. suld. These types have named fields similar to structures. samplers. . i. and . or performing pointer arithmetic will result in undefined results. the resulting pointer may be stored to and loaded from memory. since these properties are defined by . and de-referenced by texture and surface load.3. and Surface Types PTX includes built-in “opaque” types for defining texture. texture and sampler information is accessed through a single . but the pointer cannot otherwise be treated as an address. sampler. sured). Texture. sust. but all information about layout. The following tables list the named members of each type for unified and independent texture modes. and query instructions.u64} reg. accessing the pointer with ld and st instructions. The three built-in types are .

samplerref values N/A N/A N/A N/A nearest. clamp_to_border 0. linear wrap. mirror.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_border N/A N/A N/A N/A N/A . Member width height depth Opaque Type Fields in Unified Texture Mode .texref values in elements in elements in elements 0.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. linear wrap. clamp_ogl. clamp_ogl. clamp_to_edge. clamp_to_edge. 1 nearest. mirror. Types.Chapter 5.texref values . 2010 35 . Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9. State Spaces. 1 ignored ignored ignored ignored .

.samplerref tsamp1 = { addr_mode_0 = clamp_to_border. .global . these variables must be in the .samplerref my_sampler_name. filter_mode = nearest }.global state space.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. Example: .global .texref tex1. As kernel parameters. the types may be initialized using a list of static expressions assigning values to the named members. . Example: .param state space. When declared at module scope. 36 January 24.texref my_texture_name.global .PTX ISA Version 2. these variables are declared in the .global .global . At module scope. 2010 .surfref my_surface_name.

s32 i. In addition to fundamental types. State Spaces.v4. Variable Declarations All storage for data is specified with variable declarations. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .f64 is not allowed.const . . .u32 loc. Examples: .reg . Types.v3 }. Vectors Limited-length vector types are supported. A variable declaration names the space in which the variable resides. 1.f32 accel. Variables In PTX. .u8 bg[4] = {0. . // a length-4 vector of floats . for example. and they may reside in the register space.4. textures.struct float4 { .global . its type and size. and Variables 5.global . .reg .v4 .reg .v4 .v2 . 0}.shared .v2 or .2.4. where the fourth element provides padding.4. This is a common case for three-dimensional grids.v2. 0.v4 vector. Every variable must reside in one of the state spaces enumerated in the previous section. // a length-2 vector of unsigned ints .f32 bias[] = {-1. an optional initializer.pred p. its name. // typedef .v4 . January 24. vector variables are aligned to a multiple of their overall size (vector length times base-type size).0. Vectors must be based on a fundamental type.v1. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. 5. PTX supports types for simple aggregate objects such as vectors and arrays.f32 v0.u16 uv.global .1. 5.Chapter 5. q. . and an optional fixed address for the variable.b8 v. Three-element vectors may be handled by using a . an optional array size. . Vectors cannot exceed 128-bits in length.f32 V. // a length-4 vector of bytes By default. Examples: . 0. r. a variable declaration describes both the variable’s type and its state space.v4.global . Predicate variables may only be declared in the register state space. 2010 37 .0}.struct float4 coord. etc.global .

0.s32 n = 10.4.{.. Examples: .{. .4. 19*19 (361) halfwords are reserved (722 bytes).u64.u8 mailbox[128].0}. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).0.global . this can be used to statically initialize a pointer to a variable. 1} }. 0}. For the kernel declaration above. this can be used to initialize a jump table to be used with indirect branches or calls.global ..05}. {0.05}}. 5.0. The size of the dimension is either a constant expression..05. . or is left empty.1}. . {0. 0}.0 5.0.4. Variables that hold addresses of variables or instructions should be of type .. .u32 or .f16 and .global .PTX ISA Version 2.global . 2010 . Variable names appearing in initializers represent the address of the variable.. -1}.4. To declare an array.shared .1. A scalar takes a single value.local .05.0}}. variable initialization is supported only for constant and global state spaces.v4 .3. Array Declarations Array declarations are provided to allow the programmer to reserve space. Similarly. .1.1.b32 ptr = rgba. {0. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.s32 offset[][] = { {-1.f32 blur_kernel[][] = {{.u16 kernel[19][19]. The size of the array specifies how many elements should be reserved.1.0}. label names appearing in initializers represent the address of the next instruction following the label.global . // address of rgba into ptr Currently.u8 rgba[3] = {{1. {1. where the variable name is followed by an equals sign and the initial value or values for the variable.pred. being determined by an array initializer. 38 January 24.1. Here are some examples: . Initializers are allowed for all types except . {0.

Elements are bytes.4.6. These 100 register variables can be declared as follows: . %r99 This shorthand syntax may be used with any of the fundamental types and with any state space..4.b32 variables.align byte-count specifier immediately following the state-space specifier. nor are initializers permitted. say one hundred. The default alignment for scalar and array variables is to a multiple of the base-type size. %r1. Alignment is specified using an optional . %r1. Types. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. . suppose a program uses a large number. it is quite common for a compiler frontend to generate a large number of register names. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. The variable will be aligned to an address which is an integer multiple of byte-count.const . and Variables 5. of .0.align 4 . State Spaces. The default alignment for vector variables is to a multiple of the overall vector size.Chapter 5.reg . named %r0. For example. . Rather than require explicit declaration of every name. %r99. Parameterized Variable Names Since PTX supports virtual registers.5. not for individual elements. // declare %r0. 2010 39 . and may be preceded by an alignment specifier...b32 %r<100>. 5. ….2.0. Array variables cannot be declared this way.0.0}.b8 bar[8] = {0. Examples: // allocate array at 4-byte aligned address. January 24.0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. For arrays.0. alignment specifies the address alignment for the starting address of the entire array.

0 40 January 24.PTX ISA Version 2. 2010 .

The cvt (convert) instruction takes a variety of operand types and sizes. The ld. Instructions ld and st move data from/to addressable state spaces to/from registers. Operands having type different from but compatible with the instruction type are silently cast to the instruction type.2.3. For most operations. The bit-size type is compatible with every type having the same size. Instruction Operands 6. b. The mov instruction copies data between registers. January 24. the sizes of the operands must be consistent. 6. PTX describes a load-store machine.reg register state space. r. Most instructions have an optional predicate guard that controls conditional execution. Integer types of a common size are compatible with each other. and c. q.1. as its job is to convert from nearly any data type to any other data type (and size). 6. The result operand is a scalar or vector variable in the register state space. There is no automatic conversion between types. . Each operand type must be compatible with the type determined by the instruction template and instruction type. Operand Type Information All operands in instructions have a known type from their declarations. Source Operands The source operands are denoted in the instruction descriptions by the names a.Chapter 6. 2010 41 . so operands for ALU instructions must all be in variables declared in the . and a few instructions have additional predicate source operands. st. mov. s. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. and cvt instructions copy data from one location to another. Predicate operands are denoted by the names p.

All addresses and address computations are byte-based. address register plus byte offset. p.shared . and immediate address expressions which evaluate at compile-time to a constant address. .s32 q.s32 tbl[256]. r0.f32 ld. Here are a few examples: .4. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. . The mov instruction can be used to move the address of a variable into a pointer.reg . .const. q. address registers.4. tbl. .f32 W.global . . 6.u16 ld.const . The address is an offset in the state space in which the variable is declared. there is no support for C-style pointer arithmetic.u16 r0. ld.u16 x.f32 V. . Address expressions include variable names.gloal.v4 . Arrays.[x]. The syntax is similar to that used in many assembly languages. Using Addresses. [V]. 2010 .shared.reg . and Vectors Using scalar variables as operands is straightforward.PTX ISA Version 2. Examples include pointer arithmetic and pointer comparisons. arrays.v4 . W.reg .u32 42 January 24.reg . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.0 6.s32 mov. The interesting capabilities begin with addresses. Load and store operations move data between registers and locations in addressable state spaces.1.b32 p.v4. and vectors. [tbl+12].

z V. The size of the array is a constant in the program. [addr+offset2]. V.u32 s. c.b. st. it must be written as an address calculation prior to use.y. Arrays as Operands Arrays of all types can be declared. . . a[N-1]. .v4 . for use in an indirect branch or call. which may improve memory performance. Vectors as Operands Vector operands are supported by a limited subset of instructions. Examples are ld. V2.v4.global. d.a 6. a[0]. Here are examples: ld.r V. // move address of a[1] into s 6.reg .global.b. Vector loads and stores can be used to implement wide loads and stores.g V. mov.x V.u32 s.x.y V. Elements in a brace-enclosed vector.b and .r. and the identifier becomes an address constant in the space where the array is declared.4. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.v2. or a simple “register with constant offset” expression. [addr+offset].u32 s.b V. If more complicated indexing is desired.v4. and in move instructions to get the address of the label or function into a register. as well as the typical color fields . ld.4. .c. or by indexing into the array using square-bracket notation. say {Ra.Chapter 6. Instruction Operands 6. The expression within square brackets is either a constant integer.reg .z and . A brace-enclosed list is used for pattern matching to pull apart vectors. Rb. . a register variable.f32 V.c. Rc.d}.4. . January 24.2.u32 {a.d}. where the offset is a constant expression that is either added or subtracted from a register variable.f32 a.w = = = = V. Vector elements can be extracted from the vector with the suffixes . b. mov.f32 ld.w.g. a[1]. The registers in the load/store operations can be a vector. and tex. Array elements can be accessed using an explicitly calculated byte address. ld.4.f32 {a. 2010 43 . Vectors may also be passed as arguments to called functions.3.a.global.global. which include mov. or a braceenclosed list of similarly typed scalars. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. Rd}.

s32. except for operations where changing the size and/or type is part of the definition of the instruction. 2010 . 44 January 24.u16 instruction is given a u16 source operand and s32 as a destination operand. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.000 for f16). Type Conversion All operands to all arithmetic. and ~131.1. and data movement instruction must be of the same type and size. the u16 is zero-extended to s32. logic. 6. Operands of different sizes or types must be converted prior to the operation. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.0 6.5. For example.5. if a cvt.PTX ISA Version 2.

s16.Chapter 6. For example. Instruction Operands Table 11. Notes 1 If the destination register is wider than the destination format. the result is extended to the destination register width after chopping. u2f = unsigned-to-float. then sign-extend to 32-bits. s2f = signed-to-float. chop = keep only low bits that fit. January 24.u32 targeting a 32-bit register will first chop to 16-bits. f2u = float-to-unsigned. zext = zero-extend. 2010 45 . f2s = float-to-signed. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2f = float-to-float. The type of extension (sign or zero) is based on the destination format. cvt.

Modifier .rn . Table 12. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rni .PTX ISA Version 2. Modifier .0 6. Rounding Modifiers Conversion instructions may specify a rounding modifier. there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 .rm .2.rzi . In PTX.rz . The following tables summarize the rounding modifiers.rmi . choosing even integer if source is equidistant between two integers.5.rpi Integer Rounding Modifiers Description round to nearest integer.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.

Operand Costs Operands from different state spaces affect the speed of an operation. Table 11 gives estimates of the costs of using different kinds of memory. 2010 47 . Much of the delay to memory can be hidden in a number of ways. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. while global memory is slowest. Another way to hide latency is to issue the load instructions as early as possible. The register in a store operation is available much more quickly. Table 14. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. as execution is not blocked until the desired result is used in a subsequent (in time) instruction.Chapter 6. Instruction Operands 6. first access is high Notes January 24. Registers are fastest.6.

PTX ISA Version 2. 2010 .0 48 January 24.

and memory allocated on the stack (“alloca”). we describe the features of PTX needed to achieve this hiding of the ABI. 2010 49 .1. } … call foo. NOTE: The current version of PTX does not implement the underlying. Execution of the ret instruction within foo transfers control to the instruction following the call.func foo { … ret. Function declarations and definitions In PTX.Chapter 7. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. together these specify the function’s interface. functions are declared and defined using the . A function definition specifies both the interface and the body of the function. or prototype. In this section. and Application Binary Interface (ABI). January 24. Scalar and vector base-type input and return parameters may be represented simply as register variables. … Here. stack layout. execution of the call instruction transfers control to foo. stack-based ABI. support for variadic functions (“varargs”). 7. At the call. These include syntax for function definitions. Abstracting the ABI Rather than expose details of a particular calling convention. A function must be declared or defined prior to being called. function calls. implicitly saving the return address. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and an optional list of input parameters. so recursion is not yet supported. and is represented in PTX as follows: . the function name. arguments may be register variables or constants.func directive. The simplest function has no parameters or return values. parameter passing. A function declaration specifies an optional list of return parameters. and return values may be placed directly into register variables.

b8 [py+ 8].c1.s32 out) bar (.reg space.b8 [py+ 9]. ret. } … call (%r1). … ld. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . byte array in .u32 %res.c3.b64 [py+ 0]. %rc1.reg .PTX ISA Version 2.4).f64 f1. For example. … st. .0 Example: .s32 x.param. (%r1. [y+9].param variable y is used in function definition bar to represent a formal parameter. %rc2.param. note that . passed by value to a function: struct { double dbl.param .func (. } { . … In this example.u32 %inc ) { add. consider the following C structure.b8 c2.reg .u32 %ptr.func (. Second. %rc2. ld.b8 c1.reg . [y+0]. }. %rd.b8 . // scalar args in . c4. char c[4]. [y+8].align 8 py[12].param. ld. a .reg . a . this structure will be flattened into a byte array. py). ld.f1.param. … … // computation using x.b8 .reg .f64 field are aligned. 50 January 24.param.b8 c3.param space memory. Since memory accesses are required to be aligned to a multiple of the access size.b8 c4. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . [y+10].c4. 2010 . The . st. (%x.param .align 8 y[12]) { .param. st. In PTX.param.b8 [py+10]. inc_ptr.c2. .param space variables are used in two ways.reg . st. c2.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.reg . %ptr.f64 f1. [y+11].param. bumpptr. %inc. %rc1.u32 %res) inc_ptr ( .param space call (%out).b8 [py+11].param state space is used to pass the structure by value: .b32 c1. st.param. First.param. ld. c3. .

param state space use in device functions. This enables backend optimization and ensures that the . Parameters in . January 24. and alignment. In the case of . the corresponding argument may be either a .param arguments.reg variables.param or . or a constant that can be represented in the type of the formal parameter.reg space formal parameters. or constants. Supporting the .param space formal parameters that are base-type scalar or vector variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. A . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.g. • The .param variables. and alignment of parameters. all st.param byte array is used to collect together fields of a structure being passed by value.reg state space can be used to receive and return base-type scalar and vector values.reg state space in this way provides legacy support. • • • Input and return parameters may be .param or . For a caller. size. 2.param space byte array with matching type. the argument must also be a . The following restrictions apply to parameter passing. 8. In the case of .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. 4. 2010 51 .reg or .param and ld. Note that the choice of .param space formal parameters that are byte arrays.reg space variable with matching type and size. the corresponding argument may be either a . For a callee. Abstracting the ABI The following is a conceptual way to think about the . • • • For a callee. • • Arguments may be . Typically. a . • The .Chapter 7. For a caller.param memory must be aligned to a multiple of 1. size. or a constant that can be represented in the type of the formal parameter.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. In the case of .reg variables.param variables or .reg space variable of matching type and size. ..param instructions used for argument passing must be contained in the basic block with the call instruction.param argument must be declared within the local scope of the caller. For . The . The .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. or 16 bytes.param state space is used to receive parameter values and/or pass return values back to the caller.

reg or . formal parameters may be in either . PTX 2.1. PTX 2.0. Objects such as C structures were flattened and passed or returned using multiple registers. Changes from PTX 1. 2010 . In PTX ISA version 2.param state space.x supports multiple return values for this purpose.reg state space.PTX ISA Version 2. and there was no support for array parameters.param byte array should be used to return objects that do not fit into a register. For sm_2x targets. 52 January 24. PTX 1.1. and .0 restricts functions to a single return value.param space parameters support arrays.x.x In PTX ISA version 1. formal parameters were restricted to .0 7. and a .0 continues to support multiple return registers for sm_1x targets.

reg .2. (ap). (3. (2.. 0. . PTX provides a high-level mechanism similar to the one provided by the stdarg. %r2. Abstracting the ABI 7. .b32 ctr. %va_end is called to free the variable argument list handle. bra Loop.u32 ptr.reg .Chapter 7.s32 result ) maxN ( . ctr. result. 4. %va_start. … %va_start returns Loop: @p Done: January 24. 4). (ap. 2.func ( . for %va_arg64.reg . For %va_arg. %r3). call (val).reg .func %va_end (. along with the size and alignment of the next data value to be accessed. the alignment may be 1. 2010 53 .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.func okay ( … ) Built-in functions are provided to initialize.reg .h headers in C.u32 align) .u32 sz. mov.u32 N. N. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg .b64 val) %va_arg64 (.func (.h and varargs. … call (%max).u32 sz. This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg .reg .b32 result.u32 ptr) %va_start . . call (ap). or 4 bytes.u32 a. ) { . setp. bra Done. … ) . To support functions with a variable number of arguments. or 16 bytes.reg . %r1.s32 result.. // default to MININT mov. 4.reg . the size may be 1.u32 align) . . ctr. .s32 val. 0x8000000. 8.b32 val) %va_arg (.reg . 2. The function prototypes are defined as follows: . %s2). . 2.reg .u32 ap. %va_arg. iteratively access.pred p. and end access to a list of variable arguments.reg .func baz ( .reg .reg . Variadic functions NOTE: The current version of PTX does not support variadic functions. or 8 bytes. variadic functions are declared with an ellipsis at the end of the input parameter list.u32.func (. call %va_end.ge p.u32 b. 4. Once all arguments have been processed. %s1. In both cases. In PTX. max.reg . following zero or more fixed parameters: . val. .reg . maxN.u32 ptr.func (. maxN. ret. the size may be 1. . } … call (%max).

u32 ptr ) %alloca ( . defined as follows: . If a particular alignment is required.local instructions.reg . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.reg .PTX ISA Version 2. To allocate memory. a function simply calls the built-in function %alloca.local and st. Alloca NOTE: The current version of PTX does not support alloca.func ( .3.0 7. 2010 . The array is then accessed with ld. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. 54 January 24.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.

a. C. opcode D. opcode D. the semantics are described. PTX Instructions PTX instructions generally have from zero to four operands. For some instructions the destination operand is optional. B. the D operand is the destination operand. opcode A. A. 8.Chapter 8. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. In addition to the name and the format of the instruction.2. The setp instruction writes two destination registers. setp. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.lt p|q. Instruction Set 8. 2010 55 . A. opcode D. q = !(a < b). b. B. B. while A. followed by some examples that attempt to show several possible instantiations of the instruction. We use a ‘|’ symbol to separate multiple destination registers. For instructions that create a result value. // p = (a < b).s32. A.1. and C are the source operands. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. January 24.

… // compare i to n // if false. // p = (i < n) // if i < n.pred p.PTX ISA Version 2. i.s32 p. i. where p is a predicate variable. n. Instructions without a guard predicate are executed unconditionally. j. optionally negated.3. So. To implement the above example as a true conditional branch. As an example. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.lt. 2010 .pred as the type specifier. 1. q. predicate registers can be declared as . consider the high-level code if (i < n) j = j + 1. 1.0 8.s32 p. j. bra L1. This can be written in PTX as @p setp. the following PTX instruction sequence might be used: @!p L1: setp. Predicated Execution In PTX. branch over 56 January 24. add. Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 j. n. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. add 1 to j To get a conditional branch or conditional function call.s32 j.reg . predicate registers are virtual and have . add.lt. use a predicate to control the execution of the branch or call instructions.

lt (less-than). ordering comparisons are not defined for bit-size types. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. le.3.1. le (less-than-or-equal). Table 16. Table 15. ne. gt (greater-than). ne (not-equal).1. and ge (greater-than-or-equal).3. gt. ne. Unsigned Integer. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. 2010 57 . the result is false. and hs (higher-or-same).1.2. and bitsize types.3. The following table shows the operators for signed integer. The unsigned comparisons are eq. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ls (lower-or-same).1. ge. Comparisons 8. unsigned integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Instruction Set 8. If either operand is NaN. The bit-size comparisons are eq and ne. hi (higher). lt. lo (lower).Chapter 8.

leu. and mov. neu. However. Table 18.u32 %r1. geu. and no direct way to load or store predicate register values.1. then these comparisons have the same result as their ordered counterparts. Table 17. There is no direct conversion between predicates and integer values. If either operand is NaN.PTX ISA Version 2.3.2. 2010 . Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. xor. ltu. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. two operators num (numeric) and nan (isNaN) are provided. not. unordered versions are included: equ. gtu.0 To aid comparison operations in the presence of NaN values. // convert predicate to 32-bit value 58 January 24. or.%p. then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN). and nan returns true if either operand is NaN. setp can be used to generate a predicate from an integer. If both operands are numeric values (not NaN). for example: selp.0.

reg . Type Checking Rules Operand Type . they must match exactly. Instruction Set 8. different sizes). b.Chapter 8.4. and this information must be specified as a suffix to the opcode.u16 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.. b. and integer operands are silently cast to the instruction type if needed.reg .fX ok inv inv ok Instruction Type . • The following table summarizes these type checking rules. add. and these are placed in the same order as the operands.uX ok ok ok inv .uX .sX ok ok ok inv . i.u16 d. a. Floating-point types agree only if they have the same size. . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.sX . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.u16 a. For example. unsigned.bX .reg . float.f32. most notably the data conversion instruction cvt.u16 d. For example: . Signed and unsigned integer types agree provided they have the same size.fX ok ok ok ok January 24. 2010 59 . For example. cvt.e.f32 d. a. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. It requires separate type-size modifiers for the result and source. Table 19. the add instruction requires type and size information to properly perform the addition operation (signed.bX . Example: . a.

2. so that narrow values may be loaded. When used with a floating-point instruction type. Table 20. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. the size must match exactly. 2010 .4.PTX ISA Version 2. inv = invalid. “-“ = allowed. Notes 3. When used with a narrower bit-size type. so those rows are invalid for cvt. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. stored.bX instruction types. st. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. for example. no conversion needed. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Floating-point source registers can only be used with bit-size or floating-point instruction types. 1.1. Bit-size source registers may be used with any appropriately-sized instruction type. the data will be truncated. ld. For example. or converted to other types and sizes. unless the operand is of bit-size type. 4. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. The following table summarizes the relaxed type-checking rules for source operands. 60 January 24. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. The data is truncated to the instruction-type size and interpreted according to the instruction type. the cvt instruction does not support . stored. parse error. floating-point instruction types still require that the operand type-size matches exactly. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. When a source operand has a size that exceeds the instruction-type size.0 8. Operand Size Exceeding Instruction-Type Size For convenience. Note that some combinations may still be invalid for a particular instruction. and converted using regular-width registers. Source register size must be of equal or greater size than the instruction-type size.

the data is sign-extended. If the corresponding instruction type is signed integer. Destination register size must be of equal or greater size than the instruction-type size. Notes 3. the data will be zero-extended. Bit-size destination registers may be used with any appropriately-sized instruction type. and is zero-extended to the destination register width otherwise. otherwise. The following table summarizes the relaxed type-checking rules for destination operands. January 24.or sign-extended to the size of the destination register. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. 4.Chapter 8. zext = zero-extend. parse error. the size must match exactly. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Instruction Set When a destination operand has a size that exceeds the instruction-type size. 2. inv = Invalid. The data is signextended to the destination register width for signed integer instruction types. 2010 61 . the destination data is zero. When used with a narrower bit-size instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. Table 21. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. 1. “-“ = Allowed but no conversion needed. The data is sign-extended to the destination register width for signed integer instruction types. When used with a floatingpoint instruction type. the data is zeroextended.

Therefore. this is not desirable.5. a compiler or code author targeting PTX can ignore the issue of divergent threads. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. These extra precision bits can become visible at the application level.1.0 8. Both situations occur often in programs. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 8. the optimizing code generator automatically determines points of re-convergence. the threads are called divergent.6. The semantics are described using C. the threads are called uniform. at least in appearance. so it is important to have divergent threads re-converge as soon as possible. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. Divergence of Threads in Control Constructs Threads in a CTA execute together. and for many applications the difference in execution is preferable to limiting performance. 62 January 24.PTX ISA Version 2. If all of the threads act in unison and follow a single control flow path. the semantics of 16-bit instructions in PTX is machine-specific.uni suffix. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. However. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. by a right-shift instruction. and 16-bit computations are “promoted” to 32-bit computations. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. for many performance-critical applications. or conditional return. until they come to a conditional control construct such as a conditional branch.6. A compiler or programmer may chose to enforce portable. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. If threads execute down different control flow paths. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. When executing on a 32-bit data path. until C is not expressive enough. 2010 . conditional function call. For divergent control flow. 16-bit registers in PTX are mapped to 32-bit physical registers. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. At the PTX language level. for example. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. 8. using the .

2010 63 .Chapter 8. 8.7.cc.1. Instructions All PTX instructions may be predicated.cc. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. addc sub. The Integer arithmetic instructions are: add sub add. In the following descriptions. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8. the optional guard predicate is omitted from the syntax.7.

a.s64 }.u32.s16. Supported on all target architectures. a. b. d = a – b.u64. PTX ISA Notes Target ISA Notes Examples Table 23.s32 d. Supported on all target architectures. a.s32 type.s32 d. @p add.type = { . Saturation modifier: .type add{. b. Description Semantics Notes Performs addition and writes the resulting value into a destination register. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.s32 type. . b.s32 c. . . add. b. d.sat limits result to MININT. d = a + b.a.c. .sat limits result to MININT.s32. . // .type sub{. Applies only to . d. sub.b. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.0 Table 22.0.sat.PTX ISA Version 2. Introduced in PTX ISA version 1. . . . . add.0.u32. Introduced in PTX ISA version 1.s16.. 2010 .1.u64.u32 x.MAXINT (no overflow) for the size of the operation.u16. . Applies only to .sat applies only to .s32 c. Saturation modifier: .sat}. // .u16. a.y.s32 . sub.s32.type = { .sat applies only to ..MAXINT (no overflow) for the size of the operation.s64 }.sat}. add Syntax Integer Arithmetic Instructions: add Add two values.z. PTX ISA Notes Target ISA Notes Examples 64 January 24.s32 .

CF. a. carry-out written to CC. a. b. Introduced in PTX ISA version 1. Behavior is the same for unsigned and signed integers. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. add.y2.CF No integer rounding modifiers.cc.y1. b.y3.y4. x4.CF No integer rounding modifiers. Table 24. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.b32 x1. Supported on all target architectures. Behavior is the same for unsigned and signed integers.Chapter 8.cc Add two values with carry-out.cc.type d. d = a + b.cc.b32 addc.type = { . addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. No saturation. d = a + b + CC.b32 addc.z3.z4.s32 }. or testing the condition code.type = {.cc specified.s32 }.b32 addc. .cc.u32. Supported on all target architectures. x3. No other instructions access the condition code.cc. clearing.cc. .b32 addc.CF) holding carry-in/carry-out or borrowin/borrow-out. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.type d. @p @p @p @p add. x4. .2. carry-out written to CC.cc Syntax Integer Arithmetic Instructions: add.z1. sub. No saturation. x2. These instructions support extended-precision integer addition and subtraction. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.y1. x3. Introduced in PTX ISA version 1.z2. add.cc.y2.cc.b32 addc. @p @p @p @p add.z3.u32. x2. Instruction Set Instructions add.y4.z2.2.b32 x1.z4. 2010 65 .cc.y3. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. if .cc.b32 addc. addc. and there is no support for setting. addc{.z1. .cc}.

type d. with borrow-out.cc. x4.b32 subc. x4. x3. sub.type = { .(b + CC.s32 }. d = a – b.cc Subract one value from another. 2010 .PTX ISA Version 2. b. x2.cc.z1.cc.b32 subc.z3.z3. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. Introduced in PTX ISA version 1.y2.cc. subc{.z2.CF No integer rounding modifiers. .b32 subc.b32 x1.3. No saturation. Behavior is the same for unsigned and signed integers.y3.CF No integer rounding modifiers. borrow-out written to CC.cc.u32.y2.b32 subc. withborrow-in and optional borrow-out.cc Syntax Integer Arithmetic Instructions: sub. if .z1.cc.3.z4.0 Table 26.z2.b32 subc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. a. @p @p @p @p sub. Supported on all target architectures. . .type = {. borrow-out written to CC. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.CF). Supported on all target architectures.y4. d = a . No saturation.z4.cc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. x3.cc specified.type d.y3.b32 subc.s32 }.u32. Behavior is the same for unsigned and signed integers. a.y4.cc.cc}.cc. b. x2.y1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. . Introduced in PTX ISA version 1. sub.y1. @p @p @p @p sub.b32 x1.

If .s64 }. Supported on all target architectures. .hi variant // for .and 32-bit integer types. // for .fys.lo. .u32. n = bitwidth of type.type = { .hi or . d = t.u64. creates 64 bit result January 24.0.fxs. . mul{.s32. and either the upper or lower half of the result is written to the destination register.wide}. .lo variant Notes The type of the operation represents the types of the a and b operands. then d is twice as wide as a and b to receive the full result of the multiplication. then d is the same size as a and b. . a.s32 z.n>. The .wide.y.. d = t<2n-1. save only the low 16 bits // 32*32 bits.x.s16 fa. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b. Description Semantics Compute the product of two values. mul.lo is specified. mul. d = t<n-1. 2010 67 .0>. Instruction Set Table 28.wide // for .s16. .u16..hi.lo. If .Chapter 8.type d. mul.wide suffix is supported only for 16.wide is specified. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. t = a * b.fxs.s16 fa..fys. // 16*16 bits yields 32 bits // 16*16 bits.wide..

type = { . t<n-1.. .a.wide}. Description Semantics Multiplies two values and adds a third. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.q. c. . . c. a. The .n> + c.MAXINT (no overflow) for the size of the operation. then d and c are twice as wide as a and b to receive the result of the multiplication.p.wide is specified. t<2n-1.s32 d. then d and c are the same size as a and b.0. @p mad.s32 type in .wide // for .s64 }...lo is specified. // for .c.hi variant // for .s32 d.sat.lo variant Notes The type of the operation represents the types of the a and b operands. and either the upper or lower half of the result is written to the destination register.wide suffix is supported only for 16.. . and then writes the resulting value into a destination register.type mad. If .s32. mad.r.lo. a. bitwidth of type.0> + c. Supported on all target architectures. mad{. If . t n d d d = = = = = a * b.lo.hi or .u64. 68 January 24. d.. 2010 .sat limits result to MININT.hi mode.and 32-bit integer types. .u16.hi. Applies only to . b.s32 r. b. Saturation modifier: .s16. t + c.0 Table 29. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .u32.lo.b.PTX ISA Version 2.hi.

a.a. Instruction Set Table 30.s32 }.Chapter 8.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.lo}..16>.lo.type d.0>. mul24.e.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24.type = { . 2010 69 .. mul24{. 48bits.hi.hi may be less efficient on machines without hardware support for 24-bit multiply. b. d = t<47. mul24. // for . All operands are of the same type and size. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d = t<31.0. i.hi variant // for . mul24. . Supported on all target architectures.s32 d. and return either the high or low 32-bits of the 48-bit result.b.u32. .hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.. January 24. t = a * b. // low 32-bits of 24x24-bit signed multiply.

lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.lo}.type mad24. mad24{.hi mode.e. t = a * b.c.hi variant // for . d. Description Compute the product of two 24-bit integer values held in 32-bit source registers. mad24.s32 d. 2010 .u32. a. d = t<47. mad24.0.type = { . 32-bit value to either the high or low 32-bits of the 48-bit result.a.0 Table 31.s32 d. a. Applies only to . c.sat. 70 January 24. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.lo.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value..b.. b. mad24. 48bits.hi may be less efficient on machines without hardware support for 24-bit multiply.s32 }. . d = t<31.0> + c. . and add a third.hi.hi..16> + c. Saturation modifier: .PTX ISA Version 2. Return either the high or low 32-bits of the 48-bit result. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. c.. b. // for . i. Supported on all target architectures.MAXINT (no overflow).s32 type in . mad24.sat limits result of 32-bit signed addition to MININT. // low 32-bits of 24x24-bit signed multiply. All operands are of the same type and size.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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popc requires sm_20 or later.0. cnt. the number of leading zeros is between 0 and 32. d = 0. popc Syntax Integer Arithmetic Instructions: popc Population count. clz. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. popc. d = 0. // cnt is . } else { max = 64. cnt.b32) { max = 32. a.b32. the number of leading zeros is between 0 and 64.u32 Semantics 74 January 24. X. if (. inclusively. a. inclusively.type d.b64 }. while (a != 0) { if (a&0x1) d++. .b32.b64 type. mask = 0x80000000.b64 }.b32 clz. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. popc. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. mask = 0x8000000000000000.type d.b32 popc. } Introduced in PTX ISA version 2. a. X. a = a >> 1.type = { . . . a.b64 d. // cnt is . For .0.type = { .0 Table 39. 2010 . clz. For .PTX ISA Version 2. . clz requires sm_20 or later.type == .b64 d. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.b32 type. a = a << 1. } while (d < max && (a&mask == 0) ) { d++.u32 PTX ISA Notes Target ISA Notes Examples Table 40.

s64 cnt.shiftamt. Instruction Set Table 41.s32. If . for (i=msb. bfind. For signed integers. 2010 75 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i--) { if (a & (1<<i)) { d = i.type==. bfind requires sm_20 or later.s32) ? 31 : 63. . Operand a has the instruction type.type==.0. For unsigned integers.s64 }. a.u32. bfind. X. a.Chapter 8. bfind.u32 || . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. break.d. a. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. d.shiftamt. Semantics msb = (. bfind returns the bit position of the most significant “1”.type = { .u32 January 24. .type d.shiftamt && d != -1) { d = msb . bfind returns 0xFFFFFFFF if no non-sign bit is found.u64. Description Find the bit position of the most significant non-sign bit in a and place the result in d. } } if (. .u32 d. // cnt is . and operand d has type . . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.shiftamt is specified. i>=0.type bfind.u32. d = -1.

.type==. brev.0.b64 }. .PTX ISA Version 2. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i++) { d[i] = a[msb-i].0 Table 42.type d. Description Semantics Perform bitwise reversal of input. for (i=0. a.b32. a. i<=msb. 76 January 24. brev.b32 d. msb = (.type = { . brev requires sm_20 or later. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. 2010 .b32) ? 31 : 63.

s64 }. bfe.a. . bfe. .s32. and source c gives the bit field length in bits. Instruction Set Table 43. . Description Extract bit field from a and place the zero or sign-extended result in d.start. Semantics msb = (. and operands b and c are type .type==. b. Source b gives the bit field starting bit position.u64 || len==0) sbit = 0. otherwise If the bit field length is zero. . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. i<=msb. The sign bit of the extracted field is defined as: . 2010 77 .u64: .type==.b32 d.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. bfe requires sm_20 or later. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.u32 || .u32.u64. d = 0. the result is zero. for (i=0. . len = c.type d.s32. If the start position is beyond the msb of the input.type==. the destination d is filled with the replicated sign bit of the extracted field.type = { . .u32. The destination d is padded with the sign bit of the extracted field.u32 || .u32.msb)]. January 24. pos = b.Chapter 8. a. c.len. else sbit = a[min(pos+len-1.0. Operands a and d have the same type as the instruction type. if (.s32) ? 31 : 63.

f = b. Semantics msb = (. Description Align and insert a bit field from a into b. a.start. for (i=0. i++) { f[pos+i] = a[i].b32) ? 31 : 63. and place the result in f. bfi.PTX ISA Version 2. c. b.len. d. 78 January 24.b64 }. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. i<len && pos+i<=msb.0.type = { . len = d. Operands a.a. the result is b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b.b32 d. pos = c. Source c gives the starting bit position for the insertion. bfi. If the start position is beyond the msb of the input. If the bit field length is zero.type==. 2010 .b32. . and source d gives the bit field length in bits. b. and operands c and d are type . .type f. bfi requires sm_20 or later.u32. and f have the same type as the instruction type.0 Table 44. the result is b.

For each byte in the target register. Thus. 2010 79 .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. msb=1 means replicate the sign. msb=0 means copy the literal value.b1 source select c[7:4] d. b2. prmt. default mode index d.mode} d.rc8.Chapter 8.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. . a} = {{b7. In the generic form (no mode specified). b6. . as a 16b permute code. b5. {b3. a 4-bit selection value is defined. and reassemble them into a 32-bit destination register. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.ecl. b0}}. Note that the sign extension is only performed as part of generic form. . The bytes in the two source registers are numbered from 0 to 7: {b. .b2 source select c[11:8] d. . Instruction Set Table 45.f4e. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.rc16 }.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. Description Pick four arbitrary bytes from two 32-bit registers.b4e.b3 source select c[15:12] d. b.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. the permute control consists of four 4-bit selection values. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). a.b32{.ecr. b1.mode = { . b4}. .b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. c. The msb defines if the byte value should be copied. the four 4-bit values fully specify an arbitrary byte permute.

b32 prmt. ctl[2] = (c >> 8) & 0xf. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r1. ctl[3] = (c >> 12) & 0xf.PTX ISA Version 2. tmp[15:08] = ReadByte( mode. ctl[0]. r4. r2. ctl[1].f4e r1. tmp64 ). prmt. tmp[23:16] = ReadByte( mode. tmp[31:24] = ReadByte( mode. 80 January 24. r4. r3. prmt requires sm_20 or later. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ). tmp64 ). ctl[2]. r2. r3.0.b32. } tmp[07:00] = ReadByte( mode. 2010 . ctl[3]. ctl[1] = (c >> 4) & 0xf.0 Semantics tmp64 = (b<<32) | a.

f32 and .Chapter 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2.7. Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on . 2010 81 .f64 register operands and constant immediate values.

f32 rsqrt.32 and fma.approx.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.rnd.PTX ISA Version 2.sub.min.sqrt}.f64 div.cos. but single-precision instructions return an unspecified NaN. mul.rn .mul}.f32 {div.full. default is .f32 {mad.rcp.f64 mad.0 The following table summarizes floating-point instructions in PTX. sub.f64 {abs.rn and instructions may be folded into a multiply-add.rnd.rcp. and mad support saturation of results to the range [0. The optional .mul}.approx.min.target sm_20 mad. 82 January 24.approx. 1. .f32 {abs.sqrt}. so PTX programs should not rely on the specific single-precision NaNs being generated.target sm_1x No rounding modifier.rnd. with NaNs being flushed to positive zero.sqrt}. default is . {mad.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f64 and fma.neg.neg.f32 {add.max}. If no rounding modifier is specified.rcp. Instruction Summary of Floating-Point Instructions . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f64 {sin.rz .approx.f32 are the same.fma}. 2010 .ftz .lg2. {add.0].max}.rnd.rn and instructions may be folded into a multiply-add.target sm_20 .sub. Table 46. No rounding modifier.f64 are the same.rp . Double-precision instructions support subnormal inputs and results.f64 rsqrt. Note that future implementations may support NaN payloads for single-precision instructions.f32 {div.f32 {div. NaN payloads are supported for double-precision instructions.rm .ex2}.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. Single-precision add. .rnd.f32 .0.rnd.sat Notes If no rounding modifier is specified.fma}.

. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. p. .f32.0.f32 copysign. not infinity). copysign. Instruction Set Table 47. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.pred = { . true if the input is a subnormal number (not NaN. C. . 2010 83 .finite. testp.f32 testp. a. testp Syntax Floating-Point Instructions: testp Test floating-point property.type .f64 }. positive and negative zero are considered normal numbers. January 24. .normal.f32.op p. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. .notanumber.subnormal }. .infinite testp. y. b. z. A.finite testp. . testp. Introduced in PTX ISA version 2.0.normal testp. f0. copysign requires sm_20 or later. // result is .op. testp.notanumber testp. Table 48. copysign. not infinity) As a special case. B. testp requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type d.infinite.f64 isnan. a.notanumber.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.infinite.f64 }. and return the result as d.number.Chapter 8.type = { .type = { . . . X.f64 x.number testp.

add Syntax Floating-Point Instructions: add Add two values. sm_1x: add.ftz. . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. .ftz}{. . Rounding modifiers have the following target requirements: .rnd}{.rp }.rn): . 2010 .rp for add.0. NaN results are flushed to +0. add. Saturation modifier: . 84 January 24.f32 add{.f64 requires sm_13 or later.0f. subnormal numbers are supported. requires sm_13 for add.rz. a.rm mantissa LSB rounds towards negative infinity . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 f1. In particular.rm.rnd = { . b. d. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32.ftz. add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat. b. .f64. .f2. add. 1.f3.rn.0].PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.rz.rn mantissa LSB rounds to nearest even . add{.rnd}.rn.f64 supports subnormal numbers. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. add.rz available for all targets .0.rz mantissa LSB rounds towards zero . add. .f32 clamps the result to [0. requires sm_20 Examples @p add. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 49. Rounding modifiers (default is . a.rm.f32 supported on all target architectures. d = a + b.sat}.

rm.f32. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. requires sm_20 Examples sub.ftz.f3.a.0]. sub{.f64 supports subnormal numbers.f64 requires sm_13 or later. .b.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat.sat}.rn. Rounding modifiers (default is . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. 2010 85 . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.b.rz mantissa LSB rounds towards zero . sub. d.f32 clamps the result to [0. a. sub.0.rn. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rn): .f32 sub{.f32 supported on all target architectures.rn mantissa LSB rounds to nearest even . sub Syntax Floating-Point Instructions: sub Subtract one value from another. a. sub. In particular. NaN results are flushed to +0.0f. subnormal numbers are supported.rm. 1. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. b. Rounding modifiers have the following target requirements: . sm_1x: sub. . .f2.rz.0. sub. . .f32 flushes subnormal inputs and results to sign-preserving zero. sub.f32 c.rnd}{. January 24.rn.rp for sub.Chapter 8.f64.f32 f1.rnd}.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 50.rnd = { .f64 d.ftz.ftz}{. Saturation modifier: sub.rz available for all targets . d = a . requires sm_13 for sub. b.rp }.

PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rm mantissa LSB rounds towards negative infinity . Rounding modifiers have the following target requirements: .0.f32 mul{. a. NaN results are flushed to +0.rnd}{. mul Syntax Floating-Point Instructions: mul Multiply two values.rn. .rp for mul. . requires sm_20 Examples mul.rn): . b.f32.PTX ISA Version 2.sat}. mul. Rounding modifiers (default is . .f32 flushes subnormal inputs and results to sign-preserving zero. 2010 .f64. Saturation modifier: mul.0].ftz. For floating-point multiplication.f64 requires sm_13 or later.0f. mul{. mul. . In particular.rp }. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_13 for mul.rn. 1.0 Table 51.radius. . b. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn mantissa LSB rounds to nearest even .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. mul. mul.rm. Description Semantics Notes Compute the product of two values.f32 supported on all target architectures.rm. subnormal numbers are supported.sat.pi // a single-precision multiply 86 January 24.rnd}.f32 circumf. all operands must be the same size.rz. .0.f64 d. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.f64 supports subnormal numbers. d.rz available for all targets .ftz}{. sm_1x: mul.f32 flushes subnormal inputs and results to sign-preserving zero. d = a * b.rz mantissa LSB rounds towards zero . a.f32 clamps the result to [0.rnd = { .

rnd. a. d.Chapter 8.f64 d.sat}.x.rnd.rn mantissa LSB rounds to nearest even . d = a*b + c. The resulting value is then rounded to single precision using the rounding mode specified by . fma. c. Saturation: fma. . .ftz. PTX ISA Notes Target ISA Notes Examples January 24. b.rnd.rp }. d.c.f32 computes the product of a and b to infinite precision and then adds c to this product.0. Rounding modifiers (no default): .f64. c.f64 introduced in PTX ISA version 1.rn.b.f64 is the same as mad. fma.0f. fma. fma. subnormal numbers are supported. again in infinite precision.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0. a.a. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rnd{.rnd = { .rm mantissa LSB rounds towards negative infinity .4.f64 computes the product of a and b to infinite precision and then adds c to this product. . fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add.f32 fma. sm_1x: fma.f32 requires sm_20 or later.f64 w. fma. NaN results are flushed to +0.z.rz.rn. fma. 1.y. again in infinite precision. fma. The resulting value is then rounded to double precision using the rounding mode specified by .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.sat. .0.f32 is unimplemented in sm_1x. fma.f64 requires sm_13 or later. @p fma. b.rm.f32 introduced in PTX ISA version 2.rz mantissa LSB rounds towards zero . 2010 87 .f32 fma. fma.0].rn. Instruction Set Table 52.ftz}{.ftz.

fma.rnd. where the mantissa can be rounded and the exponent will be clamped. For .target sm_13 and later .{f32. In this case. c.f64 is the same as fma. mad.f32 computes the product of a and b at double precision.f32. When JIT-compiled for SM 2.f64} is the same as fma.target sm_1x d.f64 computes the product of a and b to infinite precision and then adds c to this product.rnd. 88 January 24.sat.0.f32 mad.ftz}{.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz}{.rnd{. b. mad. and then writes the resulting value into a destination register. NaN results are flushed to +0. subnormal numbers are supported.ftz.0 devices. The exception for mad. The resulting value is then rounded to double precision using the rounding mode specified by . again in infinite precision.f64 supports subnormal numbers.rp }. // .0f. sm_1x: mad.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0. The resulting value is then rounded to double precision using the rounding mode specified by .f64}.rnd. a.rm. .e.sat}. 1.f32 is identical to the result computed using separate mul and add instructions.{f32.rn mantissa LSB rounds to nearest even . // . 2010 .f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.target sm_1x: mad. a.f32 is implemented as a fused multiply-add (i.ftz..f64 d. b. again in infinite precision.PTX ISA Version 2.0 Table 53.f32 flushes subnormal inputs and results to sign-preserving zero. mad. mad{.f32 mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. mad.0]. and then the mantissa is truncated to 23 bits. mad. c. c.rz mantissa LSB rounds towards zero . mad. mad.rn.sat}. Note that this is different from computing the product with mul. . Unlike mad. Description Semantics Notes Multiplies two values and adds a third.rnd = { . d = a*b + c.rm mantissa LSB rounds towards negative infinity . a. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. For . The resulting value is then rounded to single precision using the rounding mode specified by . again in infinite precision.f32).target sm_20 d. .target sm_20: mad.rn.rz. Rounding modifiers (no default): . mad. // .rnd.0. Saturation modifier: mad.f64.f32 is when c = +/-0. the treatment of subnormal inputs and output follows IEEE 754 standard. mad. b. but the exponent is preserved.f32 computes the product of a and b to infinite precision and then adds c to this product.

f64 instructions having no rounding modifier will map to mad..0.rp for mad. Rounding modifiers have the following target requirements: .f32 supported on all target architectures.f64. a rounding modifier is required for mad. a rounding modifier is required for mad.rp for mad.. In PTX ISA versions 1.f64. In PTX ISA versions 2.c.rn. requires sm_20 Examples @p mad.b..Chapter 8.0 and later.rn. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f64.f32.rm.4 and later. 2010 89 . mad... requires sm_13 .. Target ISA Notes mad.rz. Legacy mad.rm. January 24.f64 requires sm_13 or later.a.rz.f32 d.f32 for sm_20 targets.rn.

div.rp}.rnd = { .f64 defaults to div. computed as d = a * (1/b). yd. b.full. 2010 .3.rp }.full{.3.f32 and div. stores result in d.f32 div. d = a / b.full. div. and div. d. one of . a.f32 div. d. . Explicit modifiers .f64 requires sm_20 or later. a. approximate division by zero creates a value of infinity (with same sign as a).approx. but is not fully IEEE 754 compliant and does not support rounding modifiers. . For PTX ISA version 1.rz mantissa LSB rounds towards zero .4.rn.circum. b. The maximum ulp error is 2 across the full range of inputs. . or . Examples 90 January 24.approx{. .PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero. div.rnd.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. PTX ISA Notes div.ftz. div. .ftz}. div. Subnormal inputs and results are flushed to sign-preserving zero. subnormal numbers are supported. zd. y. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 div.f32 implements a relatively fast.f64 introduced in PTX ISA version 1.f32 div.rm.approx. Description Semantics Notes Divides a by b.ftz.ftz. a. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . xd.rz. div.f64 requires sm_13 or later.ftz.full.approx.rn. div.full.approx.f64 diam. and rounding introduced in PTX ISA version 1.f64 d.f32 requires sm_20 or later. the maximum ulp error is 2. 2126].14159. full-range approximation that scales operands to achieve better accuracy.ftz}.ftz}. div. a.rnd is required. div Syntax Floating-Point Instructions: div Divide one value by another.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 54. Target ISA Notes div.f32.4 and later.f32 defaults to div. For PTX ISA versions 1. // // // // fast.rn.rnd{.0 through 1. .{rz.0.rn mantissa LSB rounds to nearest even . approximate single-precision divides: div. b. For b in [2-126.f32 implements a fast approximation to divide.f32 div.rnd.rn.rm.f32 supported on all target architectures.f64 supports subnormal numbers. Fast.rm mantissa LSB rounds towards negative infinity . Fast. x. b.ftz.approx. z. d. sm_1x: div.approx. div.full.f64.f32 and div.

f32 x. neg.0. d = -a.ftz}. NaN inputs yield an unspecified NaN.f32 supported on all target architectures. NaN inputs yield an unspecified NaN. abs{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f0.ftz}. abs. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz. Take the absolute value of a and store the result in d. sm_1x: neg. neg.f64 requires sm_13 or later.ftz. sm_1x: abs.Chapter 8. a.ftz. neg. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. subnormal numbers are supported. Subnormal numbers: sm_20: By default. neg. Negate the sign of a and store the result in d. d = |a|.f64 supports subnormal numbers. abs. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. neg. 2010 91 .f64 supports subnormal numbers. a.f32 neg.f32 x.f32 supported on all target architectures.0. abs. neg{.f32 flushes subnormal inputs and results to sign-preserving zero. d. Table 56. d.f64 requires sm_13 or later.f0. January 24.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. abs. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. abs.f32 abs. a. subnormal numbers are supported.f64 d. Instruction Set Table 55.

b.f1. 92 January 24. @p min.x.f2. b.b.z. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b. sm_1x: max.f64 supports subnormal numbers. min. a.0. min{. a. Table 58.c.PTX ISA Version 2. subnormal numbers are supported. sm_1x: min.f64 d.f32 supported on all target architectures. d d d d = = = = NaN. b.ftz. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.f64 d. (a < b) ? a : b. b. 2010 . b.f64 supports subnormal numbers. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. max. a.f32 flushes subnormal inputs and results to sign-preserving zero.c.ftz}. Store the maximum of a and b in d. max. d d d d = = = = NaN. min.ftz. a. max. b.f64 z.f32 min.f64 f0.f32 supported on all target architectures. d. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. min. a. a.f32 min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. subnormal numbers are supported.0 Table 57.f64 requires sm_13 or later. (a > b) ? a : b. max.ftz}.f32 max. Store the minimum of a and b in d. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. d.0. max{. min.f32 max.ftz.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. a.

approx and .{rz.f32 requires sm_20 or later. Instruction Set Table 59. Target ISA Notes rcp.rnd{.0.r.rm.rm mantissa LSB rounds towards negative infinity . .f32 defaults to rcp.0-2.0. xi.f32 rcp.f64 defaults to rcp.approx{.x.f32. subnormal numbers are supported. d.rn.0 +subnormal +Inf NaN Result -0.f32 rcp. // fast.rn.0 +0. sm_1x: rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . Input -Inf -subnormal -0.ftz}.f32 implements a fast approximation to reciprocal. .f32 flushes subnormal inputs and results to sign-preserving zero.ftz.0 over the range 1. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. store result in d. PTX ISA Notes rcp.rnd. The maximum absolute error is 2-23.f64.f64 introduced in PTX ISA version 1.approx.0. xi. rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.x. d = 1 / a. a. a.rn.ftz.f64 requires sm_20 or later.rp}.rz mantissa LSB rounds towards zero .0 through 1.rp }.f64 supports subnormal numbers.f64 requires sm_13 or later.approx or .4 and later. rcp. rcp.approx.ftz were introduced in PTX ISA version 1.3. General rounding modifiers were added in PTX ISA version 2.f64 ri. rcp.f32 flushes subnormal inputs and results to sign-preserving zero. and rcp.rnd is required.f32 and rcp. one of .0 -Inf -Inf +Inf +Inf +0.f64 d. rcp. rcp.f32 rcp. rcp.rn. For PTX ISA version 1. .f32 rcp. For PTX ISA versions 1.rn. Description Semantics Notes Compute 1/a.rm. rcp.4.ftz}. 2010 93 .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .approx.f64 and explicit modifiers . rcp.rz.rn mantissa LSB rounds to nearest even . Examples January 24. rcp.Chapter 8.rnd.rn.ftz.f32 supported on all target architectures.ftz.rnd = { .approx. a. d.

x.f32 sqrt.rp }. sqrt.rnd.4. sqrt.ftz.4 and later.f32 and sqrt.f64 supports subnormal numbers.f64 defaults to sqrt.x.3.f64 requires sm_13 or later.f32 supported on all target architectures.f64 introduced in PTX ISA version 1. sqrt.f32 implements a fast approximation to square root.rm.approx. sqrt.rp}.approx. a. r. store in d.f32 defaults to sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f32 requires sm_20 or later.0 Table 60.rn. . // fast. d = sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero.f64 and explicit modifiers .f64 d.rz mantissa LSB rounds towards zero .rz. sqrt.0 +0.rm. r. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.0 +0.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . // IEEE 754 compliant rounding d.0 +subnormal +Inf NaN Result NaN NaN -0.ftz}.PTX ISA Version 2.rn.rnd is required. and sqrt. // IEEE 754 compliant rounding .approx or . sqrt.ftz}.approx.0. PTX ISA Notes sqrt. approximate square root d.approx and . . . The maximum absolute error for sqrt.rn.approx{.0 through 1.ftz. Description Semantics Notes Compute sqrt(a).f32 is TBD.rnd.0 -0.0.rn. sqrt.x. General rounding modifiers were added in PTX ISA version 2.rm mantissa LSB rounds towards negative infinity . sqrt.ftz were introduced in PTX ISA version 1.f64.rn mantissa LSB rounds to nearest even .f64 requires sm_20 or later. one of .f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Examples 94 January 24. 2010 . subnormal numbers are supported.approx. For PTX ISA versions 1.ftz.rnd{. For PTX ISA version 1.rn.ftz. sqrt. a. Target ISA Notes sqrt.approx.rnd = { . sm_1x: sqrt. sqrt. Input -Inf -normal -subnormal -0.0 +0.f32 sqrt. a.f32 sqrt.rn.{rz.f64 r.f32 sqrt.

and rsqrt.f32 is 2-22.ftz}. The maximum absolute error for rsqrt. Compute 1/sqrt(a). a.ftz.f32. d. rsqrt.0 NaN The maximum absolute error for rsqrt. Note that rsqrt.f32 defaults to rsqrt.approx. subnormal numbers are supported.ftz. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f32 rsqrt. rsqrt. January 24. rsqrt. X.approx. PTX ISA Notes rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 95 . For PTX ISA versions 1. rsqrt.f64 isr.approx.f32 supported on all target architectures.0.ftz.f64 is emulated in software and are relatively slow.approx.f32 and rsqrt.Chapter 8.4 over the range 1.4 and later.f64 defaults to rsqrt.f64 supports subnormal numbers.0-4.approx.0 +0. rsqrt. a.0 through 1. rsqrt. ISR. x.f64 were introduced in PTX ISA version 1.f64 requires sm_13 or later.0.approx modifier is required.4. Input -Inf -normal -subnormal -0.approx and .3.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers . the . Instruction Set Table 61. Target ISA Notes Examples rsqrt.approx{. store the result in d.ftz were introduced in PTX ISA version 1.approx implements an approximation to the reciprocal square root. For PTX ISA version 1. sm_1x: rsqrt. d = 1/sqrt(a).0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt.f64 d.approx.f64. Subnormal numbers: sm_20: By default.f64 is TBD.f32 rsqrt.

For PTX ISA versions 1. sm_1x: Subnormal inputs and results to sign-preserving zero. sin.4 and later.approx.approx{.0. 2010 .ftz.PTX ISA Version 2.approx modifier is required.0 +0.ftz. Explicit modifiers .9 in quadrant 00. sin.3. For PTX ISA version 1.0 Table 62. d = sin(a).f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1.0 +subnormal +Inf NaN Result NaN -0. subnormal numbers are supported.0 -0.ftz.approx and .f32 implements a fast approximation to sine.0 +0.0 +0. sin.0 NaN NaN The maximum absolute error is 2-20.f32.f32 sa. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. 96 January 24.ftz}. the . sin.f32 d. Input -Inf -subnormal -0. a.4.f32 introduced in PTX ISA version 1.ftz introduced in PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures.approx. a. PTX ISA Notes sin. sin.approx. Subnormal numbers: sm_20: By default. Find the sine of the angle a (in radians).f32 defaults to sin.

sm_1x: Subnormal inputs and results to sign-preserving zero. cos.0 +1. subnormal numbers are supported.ftz introduced in PTX ISA version 1.f32 defaults to cos. Find the cosine of the angle a (in radians).0 +1.approx. cos. Instruction Set Table 63.0.9 in quadrant 00.ftz}.f32 introduced in PTX ISA version 1.approx. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.3.approx modifier is required.Chapter 8. cos. For PTX ISA version 1.0 +0. the . 2010 97 . a. January 24. For PTX ISA versions 1.ftz. Target ISA Notes Examples Supported on all target architectures.0 through 1.0 +subnormal +Inf NaN Result NaN +1.0 NaN NaN The maximum absolute error is 2-20.approx{. Subnormal numbers: sm_20: By default.0 +1.f32 implements a fast approximation to cosine.f32 d. cos.4 and later. Input -Inf -subnormal -0.f32.f32 ca.approx. d = cos(a). a.4. cos. Explicit modifiers . PTX ISA Notes cos.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.ftz.approx and .

The maximum absolute error is 2-22.f32. sm_1x: Subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.ftz.approx.4.0 through 1. lg2.approx{.ftz.f32 defaults to lg2.ftz introduced in PTX ISA version 1.4 and later.0. lg2.f32 la.f32 Determine the log2 of a. lg2. Subnormal numbers: sm_20: By default.f32 introduced in PTX ISA version 1. a.PTX ISA Version 2.3. For PTX ISA version 1. 2010 .approx modifier is required. lg2. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.0 Table 64.approx and .ftz}.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.approx. Target ISA Notes Examples Supported on all target architectures.f32 implements a fast approximation to log2(a).approx.ftz. Input -Inf -subnormal -0. Explicit modifiers . PTX ISA Notes lg2. 98 January 24.f32 flushes subnormal inputs and results to sign-preserving zero. d = log(a) / log(2).6 for mantissa. the . a. lg2. For PTX ISA versions 1.0 +0.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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and nan returns true if either operand is NaN.BoolOp{. c). ne. To aid comparison operations in the presence of NaN values. Modifier . unordered versions are included: equ.a. ge.u32. the comparison operators lo.ftz.CmpOp{.type .CmpOp.dtype. num. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. .f64 }.0 Table 67. ge. If both operands are numeric values (not NaN). 2010 . respectively.u16. Subnormal numbers: sm_20: By default. leu. p[|q].dtype. gt.f32 comparisons. gt. lt. gtu. setp. neu. then these comparisons have the same result as their ordered counterparts.n.f32.s32.dtype. This result is written to the first destination operand. p. or. ltu.u32 p|q. p[|q]. geu.b64. c). q = BoolOp(!t. loweror-same. and can be one of: eq. setp with . Integer Notes Floating Point Notes The ordered comparisons are eq.s32 setp. a. setp. subnormal numbers are supported.B) is one of: and. Semantics t = (a CmpOp b) ? 1 : 0. The untyped. and hs for lower. gt. the result is false.r. The destinations p and q must be . nan The Boolean operator BoolOp(A.s64.type = { . .0. ls. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. b. higher. b. hi. . A related value computed using the complement of the compare result is written to the second destination operand.u64. If either operand is NaN. {!}c. For unsigned values. @q setp. a.b16. . le.eq. le. . ne.ftz applies only to . xor. lt. and higher-or-same may be used instead of lt. and (optionally) combine this result with a predicate value by applying a Boolean operator. le. If either operand is NaN. ltu.f64 source type requires sm_13 or later. le. 102 January 24. ge.s16. setp.pred variables. .b.f64 supports subnormal numbers.f32 flushes subnormal inputs to sign-preserving zero. gt. The comparison operator is a suffix on the instruction. ne. .ftz}. . leu. then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN). p = BoolOp(t. neu.type setp. lo. ls. . hi. bit-size comparisons are eq and ne.i. gtu. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . The signed and unsigned comparison operators are eq.ftz}. geu.PTX ISA Version 2.f32 flushes subnormal inputs to sign-preserving zero.and. ge.b32. Applies to all numeric types.lt. lt. hs equ. sm_1x: setp.

f64 }.0. d. . Introduced in PTX ISA version 1.f32.s32 x.ftz. .s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . If c ≥ 0. a. . .t. Operand c is a predicate. and operand a is selected. d = (c >= 0) ? a : b. 2010 103 . a is stored in d. . slct. and b are treated as a bitsize type of the same width as the first instruction type.b32. a is stored in d. and operand a is selected.f64 requires sm_13 or later. d = (c == 1) ? a : b. val. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.x. sm_1x: slct. b. slct. based on the sign of the third operand.Chapter 8. f0. subnormal numbers are supported.u32. . . .ftz applies only to . . and b must be of the same type.u16.u16. .s64.r. slct. slct. . c. . For .f32 comparisons. If c is True.p.ftz.g. Description Conditional selection. a. b otherwise. Instruction Set Table 68. c. .s64. selp Syntax Comparison and Selection Instructions: selp Select between source operands. fval.f32 d.b16.u32. b.b64.s32.s32 selp. a. operand c must match the second instruction type.f32 flushes subnormal values of operand c to sign-preserving zero. z. selp.f32. Table 69. based on the value of the predicate source operand. y. . If operand c is NaN.u32. Semantics Floating Point Notes January 24.f64 requires sm_13 or later.dtype = { . Modifier . b. c. .dtype.s32 slct{. selp. . B. slct.b64.dtype. @q selp. a.xp. Operands d. otherwise b is stored in d.b32.0. slct Syntax Comparison and Selection Instructions: slct Select one source operand. .type d.ftz}. .s16. Subnormal numbers: sm_20: By default.u64.dtype.u64. C.f32 A.u64.f32 r0.type = { .f64 }. negative zero equals zero. . .dtype. a. Operands d.s16. The selected input is copied to the output without modification.f32 comparisons. the comparison is unordered and operand b is selected.b16. .f32 flushes subnormal values of operand c to sign-preserving zero.

4. provided the operands are of the same size. Instructions and.PTX ISA Version 2.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. This permits bit-wise operations on floating point values without having to define a union to access the bits. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.0 8. xor. 2010 . performing bit-wise operations on operands of any type. or. and not also operate on predicates.

b32.type = { . The size of the operands must match. 2010 105 . .b16. b. . . b. Allowed types include predicate registers.type d. d = a & b.0. Supported on all target architectures. Introduced in PTX ISA version 1.type d.b16.pred p. Introduced in PTX ISA version 1.0x80000000. or. but not necessarily the type.fpvalue. or. January 24. .0. . sign. d = a | b. The size of the operands must match.pred.pred.b64 }.q.b32. Table 71.q. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. Instruction Set Table 70.b32 and. and Syntax Logic and Shift Instructions: and Bitwise AND. a. Supported on all target architectures.b64 }. . a.Chapter 8. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.r. or Syntax Logic and Shift Instructions: or Bitwise OR.b32 x. . and.type = { .r.b32 mask mask.0x00010001 or. Allowed types include predicate registers. and.

not. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.type d. .b64 }. Allowed types include predicate registers. xor.PTX ISA Version 2. .b32. cnot.b16. cnot. Supported on all target architectures. . The size of the operands must match. xor.0. Supported on all target architectures.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. a.0 Table 72. Introduced in PTX ISA version 1.0. The size of the operands must match. not. d. one’s complement. .r. not.type d.x. 2010 . not Syntax Logic and Shift Instructions: not Bitwise negation.type = { . but not necessarily the type.b16.pred.type = { . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b32 mask. .type = { .pred. but not necessarily the type.q. . 106 January 24.b32. d = ~a.b64 }. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). The size of the operands must match. . . Allowed types include predicates. Supported on all target architectures. Introduced in PTX ISA version 1.0x0001. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.0.a. a.q. . Table 73. . Table 74. .b32 xor.b16. Introduced in PTX ISA version 1.pred p. but not necessarily the type. a.mask. d = (a==0) ? 1 : 0.b16 d. b.type d.b64 }.b32 d. d = a ^ b.

regardless of the instruction type.s32 shr. . i.i. .1. Bit-size types are included for symmetry with SHL. . .type d. shr. . Signed shifts fill with the sign bit. regardless of the instruction type. k.u16 shr. .2. . a. but not necessarily the type.i. sign or zero fill on left. a. but not necessarily the type.a.0.u64.type d.j.b32. Instruction Set Table 75.a. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.type = { . .0. shl.2. The b operand must be a 32-bit value. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. . Supported on all target architectures. 2010 107 .type = { .s64 }.u32.b32 q.b64. PTX ISA Notes Target ISA Notes Examples January 24.u16. . d = a << b.b16. Supported on all target architectures. unsigned and untyped shifts fill with 0.b32. d = a >> b. b. shr.s32. . shl Syntax Logic and Shift Instructions: shl Shift bits left. b. PTX ISA Notes Target ISA Notes Examples Table 76.b16 c. shl.b16. The sizes of the destination and first source operand must match. zero-fill on right.b64 }. Introduced in PTX ISA version 1. Shift amounts greater than the register width N are clamped to N. Introduced in PTX ISA version 1. . The sizes of the destination and first source operand must match. The b operand must be a 32-bit value. shr Syntax Logic and Shift Instructions: shr Shift bits right. Shift amounts greater than the register width N are clamped to N.s16.Chapter 8.

The cvta instruction converts addresses between generic and global. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. or shared state spaces.0 8. prefetchu isspacep cvta cvt 108 January 24. Instructions ld. st.PTX ISA Version 2. and st operate on both scalar and vector types. 2010 . mov. and from state space to state space. ldu. local. suld.7. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. possibly converting it from one format to another.5. Data Movement and Conversion Instructions These instructions copy data from place to place. ld. and sust support optional cache operations.

invalidates (discards) the local L1 line following the load. The compiler / programmer may use ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. likely to be accessed again.ca.cg Cache at global level (cache in L2 and below.lu load last use operation. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.lu Last use. Use ld. The default load instruction cache operation is ld. when applied to a local address. A ld. and cache only in the L2 cache. bypassing the L1 cache.cg to cache loads only globally.Chapter 8. any existing cache lines that match the requested address in L1 will be evicted. rather than the data stored by the first thread.7. not L1). The ld. to allow the thread program to poll a SysMem location written by the CPU.cs. For sm_20 and later. 2010 109 .5. Global data is coherent at the L2 level. . . January 24. Instruction Set 8.cs) on global addresses.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Operator . . likely to be accessed once. If one thread stores to global memory via one L1 cache. fetch again). Cache Operators PTX 2.lu operation.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. Table 77. and a second thread loads that address via a second L1 cache with ld. it performs the ld. .lu instruction performs a load cached streaming operation (ld. As a result of this request.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cv to a frame buffer DRAM address is the same as ld.cv Cache as volatile (consider cached system memory lines stale.ca. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.0 introduces optional cache operators on load and store instructions. but multiple L1 caches are not coherent for global data. evict-first. The cache operators require a target architecture of sm_20 or later. The ld. if the line is fully covered.1. The ld.cs is applied to a Local window address. the cache operators have the following definitions and behavior. The ld. When ld. the second thread may get stale L1 cache data.cs Cache streaming.ca loads cached in L1.

If one thread stores to global memory.wb for global data. Future GPUs may have globally-coherent L1 caches. rather than get the data from L2 or memory stored by the first thread. The default store instruction cache operation is st.ca loads.wb. 110 January 24. However. likely to be accessed once.cg Cache at global level (cache in L2 and below. bypassing the L1 cache. st.wt store write-through operation applied to a global System Memory address writes through the L2 cache. to allow a CPU program to poll a SysMem location written by the GPU with st. not L1).wb could write-back global store data from L1.cs Cache streaming. Addresses not in System Memory use normal write-back. . and discard any L1 lines that match. Operator . in which case st.cg is the same as st.wt.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. . The driver must invalidate global L1 cache lines between dependent grids of thread arrays.cg to cache global store data only globally. The st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.cg to local memory uses the L1 cache.PTX ISA Version 2.wt Cache write-through (to system memory). bypassing its L1 cache. Use st. The st. 2010 . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. regardless of the cache operation. which writes back cache lines of coherent cache levels with normal eviction policy.ca. and marks local L1 lines evict-first. . and a second thread in a different SM later loads from that address via a different L1 cache with ld. the second thread may get a hit on stale L1 cache data. and cache only in the L2 cache. Global stores bypass L1. but st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. In sm_20.0 Table 78.

mov. mov. d.e. For variables declared in . // get address of variable // get address of label or function . . immediate.type mov.pred. or function name. ptr. The generic address of a variable in global. a. Note that if the address of a device function parameter is moved to a register. mov. special register. .u32 mov.s16. local. A.s32.u16. Take the non-generic address of a variable in global. . or shared state space.f64 requires sm_13 or later. .u16 mov.b64.type = { . Write register d with the value of a. local. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.a. .b32. Description . sreg. 2010 111 . the parameter will be copied onto the stack and the address will be in the local state space. // address is non-generic. label.u32.e.type mov.shared state spaces. A[5]. variable in an addressable memory space.u64. Operand a may be a register. d = &avar.. addr.b16. myFunc. label. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. ..type d.0. i. . the address of the variable in its state space) into the destination register.const. . . d.type mov. and . u. within the variable’s declared state space Notes Although only predicate and bit-size types are required. ptr.1. alternately. d = sreg.v.Chapter 8. local. Instruction Set Table 79. Semantics d = a. mov places the non-generic address of the variable (i. .0.u32 d. the generic address of a variable declared in global.local.global. Introduced in PTX ISA version 1. or shared state space may be taken directly using the cvta instruction. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. d. d = &label.f32 mov. k.u32 mov. .f32.s64. avar.f32 mov. .f64 }.

15]. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. Semantics d = a.47].31]. lo. For bit-size types.x. d. 2010 .x | (a.z.x.u32 x.b. a[48.b32 mov.b}. %r1.z << 32) | (a.g. a[8. Description Write scalar register d with the packed value of vector register a.. d.y << 32) // pack two 8-bit elements into .b32 // pack four 16-bit elements into .b64 mov.b16.7]. // // // // a.{x.u16 %x is a double.y } = { a[0. a[32.31].y. {r. d.x | (a. d.15] } // unpack 8-bit elements from .z...w << 24) d = a. {lo.y.15].w } = { a[0.b64 }.x.w << 48) d = a. ..{a.b16 { d. ....a}.b32 mov.y. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).w have type . a[16.b32 // pack two 16-bit elements into ..w } = { a[0.b64 112 January 24.z << 16) | (a. d.z.0 Table 80.15]. d.23].b64 { d.b32.. Supported on all target architectures.z.x | (a.u8 // unpack 32-bit elements from .7]. .y } = { a[0.y << 8) d = a. mov.b8 r. d. or write vector register d with the unpacked values from scalar register a.a have type .w}.y << 16) | (a.0.b32 { d. %x.b.b32 { d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mov. a[24... a[16.hi are ..y << 16) d = a.y.PTX ISA Version 2.x. d.y << 8) | (a.b16 // pack four 8-bit elements into .x | (a.31] } // unpack 8-bit elements from . d.hi}.x | (a. a[32.31] } // unpack 16-bit elements from .63] } // unpack 16-bit elements from .x.type d..y } = { a[0. a.b64 // pack two 32-bit elements into .%r1.b have type ..g.b64 { d.type = { . a[16. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b32 %r1. a[8.

Chapter 8. the resulting behavior is undefined.vec = { .cop}. 32-bit). . d. to enforce sequential consistency between threads accessing shared memory.type . . 32-bit). or the instruction may fault. . .volatile{.ca. Cache operations are not permitted with ld. The address size may be either 32-bit or 64-bit. This may be used.local. .v2. .e.f32. ld{. The value loaded is sign-extended to the destination register width for signed integers. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. . . .0. ld. . Generic addressing and cache operations introduced in PTX ISA 2.u32. *(immAddr).global and .shared }.global. ld.vec.b32.vec.u8. ld introduced in PTX ISA version 1. [a]. PTX ISA Notes January 24.reg state space.f64 using cvt.cop}. .f32 or . an address maps to global memory unless it falls within the local memory window or the shared memory window.volatile may be used with .0. .type d. and truncated if the register width exceeds the state space address width for the target architecture. and then converted to .b16.u64.param.1. *(a+immOff). A destination register wider than the specified type may be used. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.s64. . .f64 }.const..ss}. [a]. . an integer or bit-size type register reg containing a byte address. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. and is zeroextended to the destination register width for unsigned and bit-size types. .volatile introduced in PTX ISA version 1. or [immAddr] an immediate absolute byte address (unsigned.const space suffix may have an optional bank number to indicate constant banks other than bank zero. for example.u16.f16 data may be loaded using ld. i.b64. If no state space is given. [a]. d. . 2010 113 . an address maps to the corresponding location in local or shared memory.b8. The . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . Generic addressing may be used with ld.cv }. . . [a].volatile.shared spaces to inhibit optimization of references to volatile memory. *a. Description Load register variable d from the location specified by the source address operand a in specified state space.volatile{. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.ss}{. Semantics d d d d = = = = a.v4 }.volatile.ss}.ss = { . . . perform the load using generic addressing. The address must be naturally aligned to a multiple of the access size. Within these windows. In generic addressing. If an address is not properly aligned.type = { .s16.cg. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b16. Instruction Set Table 81.s8. i. .cop = { . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .type ld{.ss}{.lu.cs.type ld. Addresses are zero-extended to the specified width as needed.e. .s32. d.

local.b32 ld. Cache operations require sm_20 or later.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.f64 requires sm_13 or later.%r.0 Target ISA Notes ld.[buffer+64].b32 ld.[p+-8].[a]. %r. Q.[p].PTX ISA Version 2. // negative offset %r.const. Generic addressing requires sm_20 or later.[p+4].f32 ld.local.shared.[240].s32 ld.b16 cvt. // access incomplete array x. d.const[4].[fs].f16 d.b64 ld.global.global.b32 ld. ld.v4. 2010 . // load . // immediate address %r.f32. x.

b16. 32-bit).f32. . an address maps to global memory unless it falls within the local memory window or the shared memory window. 32-bit). .vec = { .f64 using cvt. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.u64. ldu. Within these windows. only generic addresses that map to global memory are legal.f32 or .v4. .s64. ldu. . If no state space is given. and truncated if the register width exceeds the state space address width for the target architecture.e.f64 requires sm_13 or later.s16.u8. If an address is not properly aligned. perform the load using generic addressing. A register containing an address may be declared as a bit-size type or integer type.type d. ldu{. *a. *(a+immOff).[p].f32 d.s8.. ldu. . [a]. Semantics d d d d = = = = a.b64.Chapter 8.b8. *(immAddr). . or the instruction may fault. . . 2010 115 . . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. For ldu. A destination register wider than the specified type may be used.reg state space.ss = { .b32. or [immAddr] an immediate absolute byte address (unsigned.ss}.vec.b16.f32 Q. .[a]. The address must be naturally aligned to a multiple of the access size. i.f16 data may be loaded using ldu. // load from address // vec load from address .f64 }. The data at the specified address must be read-only. In generic addressing.s32.0. the resulting behavior is undefined.global.b32 d. // state space . The value loaded is sign-extended to the destination register width for signed integers. i.v4 }. Introduced in PTX ISA version 2. Instruction Set Table 82. The address size may be either 32-bit or 64-bit. where the address is guaranteed to be the same across all threads in the warp. . The addressable operand a is one of: [avar] the name of an addressable variable var. the access may proceed by silently masking off low-order address bits to achieve proper rounding.[p+4]. ldu. an address maps to the corresponding location in local or shared memory. [areg] a register reg containing a byte address. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . and then converted to .ss}.type = { . Addresses are zero-extended to the specified width as needed.v2. . . . PTX ISA Notes Target ISA Notes Examples January 24. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.u16.type ldu{. and is zeroextended to the destination register width for unsigned and bit-size types.global.e.global }.u32. .global. d.

global and . .type st. st introduced in PTX ISA version 1. .wb.v4 }. an address maps to global memory unless it falls within the local memory window or the shared memory window.cg. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.volatile. st{. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. perform the store using generic addressing.cs.cop}. . i. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. for example. or the instruction may fault. Generic addressing may be used with st.f64 requires sm_13 or later. [a].f16 data resulting from a cvt instruction may be stored using st. { .v2. The address size may be either 32-bit or 64-bit.e.vec. and truncated if the register width exceeds the state space address width for the target architecture. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. The lower n bits corresponding to the instruction-type width are stored to memory. st.b8.u64. . b. or [immAddr] an immediate absolute byte address (unsigned. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . .type [a]. 32-bit).ss}{. . .type st{. *(immAddr) = a. 2010 . 32-bit). st. Semantics d = a. Addresses are zero-extended to the specified width as needed.s64. { . an integer or bit-size type register reg containing a byte address.global.0.u8. b.local.ss}{.e. This may be used. .s16. . . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st..vec. *(d+immOffset) = a. *d = a.wt }. If an address is not properly aligned.type . { . Generic addressing and cache operations introduced in PTX ISA 2.volatile{. [a]. Generic addressing requires sm_20 or later. In generic addressing. . an address maps to the corresponding location in local or shared memory. . Cache operations are not permitted with st. . .vec . Cache operations require sm_20 or later. .type = = = = {.s32. . [a]. .0.f32.b16.ss}. st.b32. .ss}.volatile may be used with . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.u32.reg state space. A source register wider than the specified type may be used. b. .shared }.volatile introduced in PTX ISA version 1.volatile. If no state space is given. to enforce sequential consistency between threads accessing shared memory.s8.b16. PTX ISA Notes Target ISA Notes 116 January 24.f64 }.ss .shared spaces to inhibit optimization of references to volatile memory. b. The address must be naturally aligned to a multiple of the access size.0 Table 83.b64.volatile{. the resulting behavior is undefined. i.PTX ISA Version 2. Within these windows.cop}.cop .u16.1. .

local. [fs].b32 st.s32 cvt.f32 st. [p]. // negative offset [100].v4.r7.local.f16.global.b32 st.b. // %r is 32-bit register // store lower 16 bits January 24. Instruction Set Examples st. 2010 117 . // immediate address %r.Chapter 8.%r. [q+4].global.local.a.a. [q+-8].s32 st.b16 [a].f32 st.%r.Q.

L1 [addr].0 Table 84.space = { . prefetchu Prefetch line containing generic address at specified level of memory hierarchy.L1 [ptr]. the prefetch uses generic addressing. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.global.L2 }. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. prefetchu.local }. an address maps to global memory unless it falls within the local memory window or the shared memory window. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. A prefetch to a shared memory location performs no operation. 118 January 24.e. A prefetch into the uniform cache requires a generic address. The address size may be either 32-bit or 64-bit. Within these windows.L1.L1 [a]. and truncated if the register width exceeds the state space address width for the target architecture. [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetch and prefetchu require sm_20 or later. If no state space is given. 2010 . prefetch{.PTX ISA Version 2. In generic addressing. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.level = { . a register reg containing a byte address. prefetch. . an address maps to the corresponding location in local or shared memory. // prefetch to data cache // prefetch to uniform cache . Addresses are zero-extended to the specified width as needed.space}. .global. i. 32-bit). 32-bit).0.level prefetchu. or [immAddr] an immediate absolute byte address (unsigned. in specified state space. . and no operation occurs if the address maps to a local or shared memory location.

cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. or shared state space. p.pred . sptr. local.size = { . isspacep. For variables declared in global. isshrd.pred. or vice-versa.0.u32 gptr.u32 p. // convert to generic address // get generic address of var // convert generic address to global. . . cvta requires sm_20 or later. var.size .u32. .space p. a. the generic address of the variable may be taken using cvta. Use cvt.u32. The source address operand must be a register of type .local. Instruction Set Table 85.global.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Chapter 8. a. Description Convert a global.shared }. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.genptr.local. p. The source and destination addresses must be the same size. or vice-versa.global. 2010 119 .global isspacep.u64.space. local. January 24. or shared address to a generic address. or shared address.shared.u64. // local.u32 or .global. cvta.u64 }.u32 p.size p. isspacep requires sm_20 or later. . or shared state space. // result is . When converting a generic address into a global. local.local.shared isglbl. Introduced in PTX ISA version 2. svar.space = { . islcl. cvta.u64 or cvt. PTX ISA Notes Target ISA Notes Examples Table 86. local. a.lptr.to. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. or shared state space to generic.space. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.size cvta. . A program may use isspacep to guard against such incorrect behavior. The destination register must be of type . Take the generic address of a variable declared in global. isspacep. gptr. // get generic address of svar cvta.space = { .space.u32 to truncate or zero-extend addresses. local.local isspacep.to. . lptr. cvta.shared }. or shared address cvta.

s64. .f32 float-to-integer conversions and cvt.u64.u32.rmi round to nearest integer in direction of negative infinity .rp }.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.dtype.frnd = { . .u8. a. . .PTX ISA Version 2.s8.atype = { .f32. and for same-size float-tofloat conversions where the value is rounded to an integer.ftz.ftz.ftz. d = convert(a). subnormal inputs are flushed to signpreserving zero. .rm.sat}. 120 January 24.sat}.sat is redundant. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. the result is clamped to the destination range by default..f32. d.f32.rni round to nearest integer.rzi.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. .rz.0 Table 87.f32 float-tofloat conversions with integer rounding. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. Note that saturation applies to both signed and unsigned integer types. .ftz modifier may be specified in these cases for clarity.rni. Integer rounding is illegal in all other instances.s16. subnormal numbers are supported.f64 }. cvt{. // integer rounding // fp rounding .sat For integer destination types.atype cvt{.e. .4 and earlier. the . 2010 .dtype = . sm_1x: For cvt. For float-to-integer conversions.ftz}{.f32 float-to-integer conversions and cvt. .atype d. . .u16.rn. .rpi }.rzi round to nearest integer in the direction of zero .s32. . i. . .f16. i. Description Semantics Integer Notes Convert between different types and sizes. Integer rounding is required for float-to-integer conversions. a. choosing even integer if source is equidistant between two integers. subnormal inputs are flushed to signpreserving zero. The compiler will preserve this behavior for legacy PTX code.dtype. .dtype.irnd}{.dtype. .frnd}{. Integer rounding modifiers: . . For cvt. Note: In PTX ISA versions 1.rmi.e. Saturation modifier: . .f32 float-tofloat conversions with integer rounding. .ftz}{.ftz.MAXINT for the size of the operation.sat limits the result to MININT. The optional .. .irnd = { .

cvt. if the PTX . The operands must be of the same size. 2010 121 . Modifier . // float-to-int saturates by default cvt.s32. // note .f32. Subnormal numbers: sm_20: By default.f32. Floating-point rounding modifiers: . .4 or earlier. 1. cvt.rn mantissa LSB rounds to nearest even .y.0. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16.f16.f16.f32 x.f64 j.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.ftz behavior for sm_1x targets January 24. // round to nearest int. and .0.f32. Note: In PTX ISA versions 1.f32.f32.s32 f.0]. cvt.sat limits the result to the range [0. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32 x.r. and cvt.y.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).rni.sat For floating-point destination types.ftz modifier may be specified in these cases for clarity. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.rm mantissa LSB rounds towards negative infinity .4 and earlier. stored in floating-point format. .Chapter 8. and for integer-to-float conversions. cvt to or from .version is 1.f64. NaN results are flushed to positive zero. result is fp cvt. The result is an integral value. Specifically.f32.f32. Applies to . Floating-point rounding is illegal in all other instances. subnormal numbers are supported.rz mantissa LSB rounds towards zero .i. The compiler will preserve this behavior for legacy PTX code.f64 requires sm_13 or later. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . Introduced in PTX ISA version 1. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.f64 types.f32 instructions. The optional . Saturation modifier: .

PTX supports the following operations on texture.b32 r5. the file is assumed to use unified mode. 2010 .param . [tex1]. If no texturing mode is declared.target options ‘texmode_unified’ and ‘texmode_independent’. texture and sampler information is accessed through a single . mul. .f2}].v4. allowing them to be defined separately and combined at the site of usage in the program. // get tex1’s txq.f32 r1.PTX ISA Version 2.texref handle. } = clamp_to_border. sampler. In the independent mode. with the restriction that they correspond 1-to-1 with the 128 possible textures. 122 January 24. sampler. and surface descriptors. but the number of samplers is greatly restricted to 16.r4}.texref tex1 ) { txq. sampler. r3.u32 r5. PTX has two modes of operation. Example: calculate an element’s power contribution as element’s power/total number of elements. sampler. In the unified mode.f32 r3.f32. r4.global . The texturing mode is selected using .f32 r1.f32 {r1.7. texture and sampler information each have their own handle.. r1. r6. r5. div.f32 r1.r3. add. [tex1]. r1.6. r3. r1.width.entry compute_power ( . and surfaces. r5. add. cvt. Texturing modes For working with textures and samplers.0 8. . . add.f32. The advantage of unified mode is that it allows 128 samplers. = nearest width height tsamp1. Module-scope and per-entry scope definitions of texture. The advantage of independent mode is that textures and samplers can be mixed and matched. {f1. Ability to query fields within texture. and surface descriptors.r2. Texture and Surface Instructions This section describes PTX instructions for accessing textures. A PTX module may declare only one texturing mode. r5. and surface descriptors.. samplers.samplerref tsamp1 = { addr_mode_0 filter_mode }.b32 r6. r2. // get tex1’s tex.u32 r5.target texmode_independent . and surface descriptors: • • • Static initialization of texture. [tex1.2d.height.

[tex_a.s32. //Example of unified mode texturing tex. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . [tex_a.s32. . .v4. . b.geom.geom. Instruction Set These instructions provide access to texture and surface memory. A texture base address is assumed to be aligned to a 16-byte address.r2. d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. . 2010 123 . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.btype = { . If an address is not properly aligned. is a two-element vector for 2d textures. or the instruction may fault. . If no sampler is specified.r4}.f32 {r1.u32.r4}. with the extra elements being ignored. // Example of independent mode texturing tex. Description Texture lookup using a texture coordinate vector. the sampler behavior is a property of the named texture..1d.Chapter 8.btype d. the square brackets are not required and .5.r3. An optional texture sampler b may be specified. // explicit sampler . the resulting behavior is undefined. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. Supported on all target architectures.r2. {f1. PTX ISA Notes Target ISA Notes Examples January 24.s32.f3. where the fourth element is ignored.3d. .2d. sampler_x.dtype.s32.v4. tex txq suld sust sured suq Table 88.3d }.0.s32 {r1. i. Notes For compatibility with prior versions of PTX. {f1}].e.v4. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.f32 }.btype tex.dtype.geom = { . c]. c]. [a. and is a four-element vector for 3d textures. Unified mode texturing introduced in PTX ISA version 1. Operand c is a scalar or singleton tuple for 1d textures. The instruction always returns a four-element vector of 32-bit values.dtype = { .1d. tex.v4.f32 }.f2.v4 coordinate vectors are allowed for any geometry. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.r3. [a.f4}].

// texture attributes // sampler attributes .tquery = { . [smpl_B]. clamp_ogl. linear } Integer from enum { wrap.height . clamp_to_edge.0 Table 89. . d. . [tex_A]. [tex_A].addr_mode_1 .b32 %r1. addr_mode_2 }.tquery.normalized_coords }.filter_mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Operand a is a .addr_mode_0. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.b32 d. In unified mode.samplerref variable.addr_mode_0. Query: . and in independent mode sampler attributes are accessed via a separate samplerref argument.width. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.5. [a].width . txq. txq. mirror.texref or . txq.PTX ISA Version 2.depth. sampler attributes are also accessed via a texref argument.filter_mode. addr_mode_1.b32 %r1.filter_mode .normalized_coords .squery = { . Description Query an attribute of a texture or sampler. .addr_mode_0 .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). // unified mode // independent mode 124 January 24. .b32 %r1. 2010 . Integer from enum { nearest. [a]. . Supported on all target architectures.height.width.depth . txq.b32 txq.squery.

[surf_B.p. . // unformatted d. If the destination type is .b16. suld. and cache operations introduced in PTX ISA version 2.vec .clamp field specifies how to handle out-of-bounds addresses: . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .u32.b.s32.3d requires sm_20 or later.5. Coordinate elements are of type . If the destination base type is . .b.trap . A surface base address is assumed to be aligned to a 16-byte address.b supported on all target architectures. Cache operations require sm_20 or later.z. .b . size and type conversion is performed as needed to convert from the surface sample format to the destination type.cop}. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [surf_A.3d }. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. G. [a. sm_1x targets support only the .vec. suld.f32 }.p.f3. Target ISA Notes Examples January 24.b32. {x. . // cache operation none. Operand a is a .clamp suld.s32.dtype.u32.p is currently unimplemented. The lowest dimension coordinate represents a sample offset rather than a byte offset.2d.1d. suld.. // for suld. . .y.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.cs. b].clamp . and A components of the surface format. SNORM.dtype . . Destination vector elements corresponding to components that do not appear in the surface format are not written.clamp . .trap {r1. suld.b64.v4.b performs an unformatted load of binary data. Operand b is a scalar or singleton tuple for 1d surfaces. or FLOAT data.trap suld.r2}.s32. {x}]. // for suld.cop}. .geom{. the resulting behavior is undefined. suld. then . . i. suld. or . suld.v4. where the fourth element is ignored.cv }.cop .1d.e.dtype.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. b].s32. . If an address is not properly aligned.geom . or . .f32 based on the surface format as follows: If the surface format contains UNORM.b64 }. . Instruction Set Table 90.v4 }.0.f32 is returned. 2010 125 . [a.b. The .clamp = = = = = = { { { { { { d.trap clamping modifier. .Chapter 8. if the surface format contains UINT data.f2.p .dtype .surfref variable.w}]. is a two-element vector for 2d surfaces.v2.zero }.trap. additional clamp modifiers. Description Load from surface memory using a surface coordinate vector.b32.u32. then . . or the instruction may fault. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. B.3d. and is a four-element vector for 3d surfaces. suld.b32.u32 is returned. suld.clamp. {f1.f4}.p requires sm_20 or later. . if the surface format contains SINT data.f32.ca.cg.geom{.f32. then . and the size of the data transfer matches the size of destination operand d. the surface sample elements are converted to .b8 . .p. // formatted . suld Syntax Texture and Surface Instructions: suld Load from surface memory.trap introduced in PTX ISA version 1. .s32 is returned.v2.

v2. {f1.geom{.cg.f32 is assumed.y. If the source base type is .clamp = = = = = = { { { { { { [a. sust.p requires sm_20 or later. is a two-element vector for 2d surfaces. . .vec. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.1d. Coordinate elements are of type . sust. sm_1x targets support only the . .ctype.0. A surface base address is assumed to be aligned to a 16-byte address.p. These elements are written to the corresponding surface sample components.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. 2010 . i. c. b].trap introduced in PTX ISA version 1.cop}. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. and is a four-element vector for 3d surfaces.p. and A surface components.s32. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.clamp. sust. .s32.clamp .u32 is assumed.vec.cs. then . .cop .f4}.b32.v4 }.zero }.3d. . If the source type is .v2.w}]. size and type conversions are performed as needed between the surface sample format and the destination type. sust. then . .f3.b64 }.f32. then .PTX ISA Version 2.r2}. .b. .f2.trap clamping modifier.trap .z.b32.s32.b16. {x.2d. . none. G. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.0 Table 91. .p.b // for sust.clamp . The lowest dimension coordinate represents a sample offset rather than a byte offset.surfref variable. [a. sust. . SNORM.b supported on all target architectures. additional clamp modifiers. or the instruction may fault.e. c. {x}].5. or .vec . The source vector elements are interpreted left-to-right as R. and cache operations introduced in PTX ISA version 2.p performs a formatted store of a vector of 32-bit data values to a surface sample.3d requires sm_20 or later.p. Operand b is a scalar or singleton tuple for 1d surfaces. sust.trap sust. where the fourth element is ignored. if the surface format contains UINT data.ctype .f32} are currently unimplemented. the resulting behavior is undefined.f32 }. sust. B. .u32.wb. sust Syntax Texture and Surface Instructions: sust Store to surface memory.f32. [surf_B. Cache operations require sm_20 or later.b8 .trap [surf_A. // unformatted // formatted . Operand a is a . . The source data is then converted from this type to the surface sample format.b32.cop}. if the surface format contains SINT data. . {r1.1d.clamp sust.ctype ..u32.3d }.b. Target ISA Notes Examples 126 January 24.geom{.s32 is assumed. sust.ctype. Source elements that do not occur in the surface sample are ignored. If an address is not properly aligned. The . b]. // for sust.v4. .b64.{u32. .trap.b performs an unformatted store of binary data. . The size of the data transfer matches the size of source operand c. sust.b.wt }. .clamp field specifies how to handle out-of-bounds addresses: . or FLOAT data. Surface sample components that do not occur in the source vector will be written with an unpredictable value. .geom .s32.p Description Store to surface memory using a surface coordinate vector. the access may proceed by silently masking off low-order address bits to achieve proper rounding.

.and.u32 based on the surface sample format as follows: if the surface format contains UINT data. Coordinate elements are of type . // byte addressing sured. Operations add applies to . Instruction Set Table 92.add. is a two-element vector for 2d surfaces.p.b32.b.op = { . If an address is not properly aligned.s32 types. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.ctype.b].u32.u64 data.s32 types.b32.u32.u32.op. January 24.b]. 2010 127 . sured.op.b32 type. . . sured. then . sured. . .Chapter 8.surfref variable.p.clamp. The . .1d.p performs a reduction on sample-addressed 32-bit data.u64.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.2d.clamp field specifies how to handle out-of-bounds addresses: . . . {x}].b32 }.s32 or .0.c.2d.ctype = { .s32. operations and and or apply to . // for sured.trap [surf_A.u32 is assumed.p . sured requires sm_20 or later. where the fourth element is ignored.u32 and . or . min and max apply to . .s32.c. and .trap . . then .min..geom = { .geom.ctype. . // sample addressing . r1.clamp [a. [surf_B. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.or }. The lowest dimension coordinate represents a sample offset rather than a byte offset.s32 is assumed.max.s32. sured. . r1.e.geom. .b performs an unformatted reduction on . Operand b is a scalar or singleton tuple for 1d surfaces.trap sured.ctype = { . .u32.1d.zero }.y}]. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. and is a four-element vector for 3d surfaces. The instruction type is restricted to . . and the data is interpreted as . Reduction to surface memory using a surface coordinate vector.b . A surface base address is assumed to be aligned to a 16-byte address.b32 }. {x.b. the resulting behavior is undefined. .3d }.clamp [a.u64.trap. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp = { .clamp .min.b32. Operand a is a .add. if the surface format contains SINT data. or the instruction may fault. // for sured. i.

Query: . Supported on all target architectures.query = { .depth }.5. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. [surf_A].width.query. . suq.PTX ISA Version 2.0 Table 93.width . 2010 . .b32 d.surfref variable.height . Operand a is a . [a]. Description Query an attribute of a surface.height.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq. .b32 %r1. 128 January 24.width.

b. Introduced in PTX ISA version 1.s32 a.0. used primarily for defining a function body.x. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.Chapter 8.c.s32 d.7. Instruction Set 8.a. } PTX ISA Notes Target ISA Notes Examples Table 95.f32 @!p div.0.7. { instructionList } The curly braces create a group of instructions.eq. {} Syntax Description Control Flow Instructions: { } Instruction grouping.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. 2010 129 . Supported on all target architectures.0. mov. { add. p. Supported on all target architectures.y. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Threads with a false guard predicate do nothing.f32 @q bra L23. @{!}p instruction. ratio. Execute an instruction or instruction block for threads that have the guard predicate true. If {!}p then instruction Introduced in PTX ISA version 1. setp. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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or }. When a barrier completes.red are population-count (. Instruction Set Table 100.u32 bar.and and . d. In conditionally executed code.sync and bar. the bar. b}. The reduction operations for bar. and bar.arrive.. Operands a. operands p and c are predicates. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.red delays the executing threads (similar to bar. the final value is written to the destination register in all threads waiting at the barrier. bar. b.sync with an immediate barrier number is supported for sm_1x targets.0.red. b}. all threads in the CTA participate in the barrier. PTX ISA Notes Target ISA Notes Examples bar.red} introduced in PTX .red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. and the barrier is reinitialized so that it can be immediately reused. Thus. Barriers are executed on a per-warp basis as if all the threads in a warp are active.{arrive.pred . bar. a. Operand b specifies the number of threads participating in the barrier.popc.and).cta.op = { . If no thread count is specified. all-threads-true (. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).Chapter 8. execute a bar. a{. bar. b}. . thread count. it simply marks a thread's arrival at the barrier. bar. bar.red} require sm_20 or later.red.red instruction.popc). Thus.15. and d have type .and. All threads in the warp are stalled until the barrier completes.arrive a{.op. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. the optional thread count must be a multiple of the warp size.sync 0. it is as if all the threads in the warp have executed the bar instruction.version 2.red should not be intermixed with bar.red also guarantee memory ordering among threads identical to membar. bar.popc is the number of threads with a true predicate.sync) until the barrier count is met.arrive does not cause any waiting by the executing threads.arrive using the same active barrier. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.{arrive.sync or bar. the waiting threads are restarted without delay. Only bar. while . a{.0. January 24. and any-thread-true (.red performs a reduction operation across threads. Note that a non-zero thread count is required for bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.red performs a predicate reduction across the threads participating in the barrier. In addition to signaling its arrival at the barrier. threads within a CTA that wish to communicate via memory can store to memory.or). bar. {!}c. {!}c. Register operands.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.sync or bar.u32.sync and bar. The barrier instructions signal the arrival of the executing threads at the named barrier.sync bar. bar. Since barriers are executed on a per-warp basis.sync without a thread count introduced in PTX ISA 1. and then safely read values stored by other threads prior to the barrier. bar. Execution in this case is unpredictable. p. Description Performs barrier synchronization and communication within a CTA. b. Once the barrier count is reached. 2010 133 . The result of . Register operands. thread count. if any thread in a warp executes a bar instruction. and bar. Each CTA instance has sixteen barriers numbered 0.

membar. and memory reads by this thread can no longer be affected by other thread writes.gl} supported on all target architectures. For communication between threads in different CTAs or even different SMs.sys Waits until all prior memory requests have been performed with respect to all clients. 134 January 24.g.4. . membar. membar. membar.sys requires sm_20 or later.gl.gl. . including thoses communicating via PCI-E such as system and peer-to-peer memory. 2010 . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. red or atom) has been performed when the value written has become visible to other clients at the specified level. PTX ISA Notes Target ISA Notes Examples membar. A memory read (e.version 2.level = { .cta. membar. membar.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.sys will typically have much longer latency than membar. or system memory level. membar. membar.gl} introduced in PTX .gl will typically have a longer latency than membar.sys }.level. membar.{cta.sys introduced in PTX .cta. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. Waits until prior memory reads have been performed with respect to other threads in the CTA. level describes the scope of other clients for which membar is an ordering event.cta. that is.{cta. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.version 1.0 Table 101. when the previous value can no longer be read.g. membar. . Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar.gl.PTX ISA Version 2.0. by st.sys. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. global. membar. this is the appropriate level of membar. A memory write (e.

and. . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. b. Instruction Set Table 102.f32 Atomically loads the original value at location a into destination register d. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Within these windows.e. perform the memory accesses using generic addressing.inc.s32. 32-bit operations. max. . The floating-point operations are add.u32.global. In generic addressing. and stores the result of the specified operation at location a. . performs a reduction operation with operand b and the value in location a.b32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. atom. . . January 24. min. overwriting the original value. an address maps to global memory unless it falls within the local memory window or the shared memory window. i. c. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32 }. min. accesses to local memory are illegal. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. For atom. e.shared }.add. or.f32.op = { .cas. . [a].op. The address must be naturally aligned to a multiple of the access size.s32. .u64. . The bit-size operations are and.b64 .Chapter 8. inc. . The floating-point add. cas (compare-and-swap). and max. Addresses are zero-extended to the specified width as needed. 2010 135 . i.b64. xor.u32.xor. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.e. The inc and dec operations return a result in the range [0. a de-referenced register areg containing a byte address. .b32 only .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. min. or [immAddr] an immediate absolute byte address. [a].u32 only . .or. b.s32. . by inserting barriers between normal stores and atomic operations to a common address. an address maps to the corresponding location in local or shared memory.u32.space = { . or the instruction may fault. Description // // // // // . The address size may be either 32-bit or 64-bit.dec. .b].type atom{. A register containing an address may be declared as a bit-size type or integer type. ..b32.type = { . .exch.min.max }. the resulting behavior is undefined.u64 . .exch to store to locations accessed by other atomic operations. Operand a specifies a location in the specified state space.. or by using atom. dec. and truncated if the register width exceeds the state space address width for the target architecture.g.add. . d. . . and max operations are single-precision. If no state space is given. . . . . and exch (exchange). The integer operations are add. .type d. If an address is not properly aligned.op. atom{.space}.space}.

s) = (r > s) ? s exch(r. Use of generic addressing requires sm_20 or later. 64-bit atom.global. cas(r.1.{min.b32 d. b).f32 atom.add.t) = (r == s) ? t operation(*a.global. s) = s. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.0.0.cas.exch} requires sm_12 or later. atom. atom.shared requires sm_12 or later. 2010 .s. b.shared.cas.max} are unimplemented.f32 requires sm_20 or later. d.[p].f32. : r.{add. 64-bit atom. atom. atom.my_val.[a].PTX ISA Version 2. : r+1. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. d.max.[x+4]. atom.my_new_val. Release Notes Examples @p 136 January 24.add.s32 atom. : r-1. s) = (r >= s) ? 0 dec(r.shared operations require sm_20 or later. *a = (operation == cas) ? : } where inc(r.0 Semantics atomic { d = *a. c) operation(*a.global requires sm_11 or later.

s) = (r > s) ? s : r-1. dec(r. dec. Semantics *a = operation(*a.type = { .u32. a de-referenced register areg containing a byte address.e. The floating-point add.u32. .Chapter 8. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.b32 only . min. . and max. b). . perform the memory accesses using generic addressing. . Notes Operand a must reside in either the global or shared state space.b64. red. If no state space is given.u32 only . max. .f32 }. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.min.or.global. the access may proceed by silently masking off low-order address bits to achieve proper rounding.dec. and stores the result of the specified operation at location a. Addresses are zero-extended to the specified width as needed. or.op = { . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.space}. overwriting the original value. i. . i. and max operations are single-precision. .inc. an address maps to the corresponding location in local or shared memory. Instruction Set Table 103. b.b32.f32 Performs a reduction operation with operand b and the value in location a.s32.exch to store to locations accessed by other reduction operations. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.max }.and.e. The integer operations are add. .type [a]. by inserting barriers between normal stores and reduction operations to a common address. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s32. . Description // // // // . . . . and xor. e.shared }. January 24. where inc(r.op.add. . or the instruction may fault.add. A register containing an address may be declared as a bit-size type or integer type. .u64 . If an address is not properly aligned. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. For red. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. red{. In generic addressing.u32. The floating-point operations are add.g. accesses to local memory are illegal.f32. The address must be naturally aligned to a multiple of the access size. and truncated if the register width exceeds the state space address width for the target architecture. Operand a specifies a location in the specified state space.b]. min. .xor.. s) = (r >= s) ? 0 : r+1. 32-bit operations. 2010 137 . The inc and dec operations return a result in the range [0. the resulting behavior is undefined. .. . . The bit-size operations are and. or by using atom. or [immAddr] an immediate absolute byte address.u64. an address maps to global memory unless it falls within the local memory window or the shared memory window. inc. . Within these windows.space = { . The address size may be either 32-bit or 64-bit.s32. min.

64-bit red.global.my_val.shared requires sm_12 or later.f32 requires sm_20 or later.max} are unimplemented. 2010 .b32 [a].2.f32. red. red.{min.global. Release Notes Examples @p 138 January 24.1.add.add.add requires sm_12 or later.shared operations require sm_20 or later.f32 red. [p]. 64-bit red.0.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.max.PTX ISA Version 2. [x+4]. red.global requires sm_11 or later red. Use of generic addressing requires sm_20 or later. red.shared.s32 red.and.

Negate the source predicate to compute .q.any True if source predicate is True for some active thread in warp. vote. Note that vote applies to threads in a single warp.q.mode = { .all True if source predicate is True for all active threads in warp. returns bitmask .Chapter 8. // ‘ballot’ form. Description Performs a reduction of the source predicate across threads in a warp. .pred vote.pred d.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.p.uni }. p.ballot.mode. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.2.all. Negate the source predicate to compute . 2010 139 . Instruction Set Table 104.uni.ballot. . vote. not across an entire CTA.b32 p. . vote.all.ballot. // get ‘ballot’ across warp January 24. In the ‘ballot’ form.pred vote.any. vote requires sm_12 or later. The destination predicate value is the same across all threads in the warp.ballot.uni True if source predicate has the same value in all active threads in warp. vote.b32 requires sm_20 or later. r1. . The reduction modes are: .uni. {!}a.not_all.none.b32 d. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. where the bit position corresponds to the thread’s lane id. {!}a. Negating the source predicate also computes . vote.

Using the atype/btype and asel/bsel specifiers. .add. a{.max }. with optional data merge vop.dtype. The source and destination operands are all 32-bit registers. atype. // 32-bit scalar operation.b1.b3. extract and sign.btype{.s34 intermediate result.h1 }.atype.asel}. . with optional secondary operation vop.sat} d.atype.asel}. The sign of the intermediate result depends on dtype. . vop. . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). half-word.PTX ISA Version 2.btype{. optionally clamp the result to the range of the destination type. 4. The primary operation is then performed to produce an . .u32.s33 values.sat}.7.btype = { .asel}. the input values are extracted and signor zero.u32 or . .btype{.h0.b0. b{. perform a scalar arithmetic operation to produce a signed 34-bit result.s32) is specified in the instruction type. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.atype = .s32 }.0 8. c.dtype.atype.min. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. .9. to produce signed 33-bit input values.bsel}. a{.dsel. .b2. and btype are valid. 140 January 24. . . a{.or zero-extend byte.sat} d. .secop d. Video Instructions All video instructions operate on 32-bit register operands.dtype.bsel}.dsel = .extended internally to . The type of each operand (. 2. b{. c.secop = { .asel = . taking into account the subword destination size in the case of optional data merging. b{.bsel = { . 2010 .dtype = . 3.bsel}. The general format of video instructions is as follows: // 32-bit scalar operation. all combinations of dtype. or word values from its source operands.

2010 141 .s33 tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. The sign of the c operand is based on dtype.b3: if ( sign ) return CLAMP( else return CLAMP( case . tmp. S16_MAX. Instruction Set . S16_MIN ). . .max return MAX(tmp.h0. U16_MIN ). U32_MAX. The lower 32-bits are then written to the destination operand. c).b2: return ((tmp & 0xff) << 16) case . U8_MIN ). c).s33 optMerge( Modifier dsel. Bool sat. . c).Chapter 8. switch ( dsel ) { case .s33 c) { switch ( secop ) { . January 24.h0: return ((tmp & 0xffff) case . S8_MIN ). U8_MAX.s33 tmp.s34 tmp. . U32_MIN ). . tmp.add: return tmp + c.b0. c). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.b1: return ((tmp & 0xff) << 8) case . Modifier dsel ) { if ( !sat ) return tmp.s33 optSecOp(Modifier secop.min: return MIN(tmp. S8_MAX.s33 optSaturate( . S32_MIN ).b2. . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). .b0: return ((tmp & 0xff) case . .s33 c ) switch ( dsel ) { case . default: return tmp. as shown in the following pseudocode. .h1: return ((tmp & 0xffff) << 16) case . tmp. . tmp. c). Bool sign. c). .b3: return ((tmp & 0xff) << 24) default: return tmp. S32_MAX. tmp. U16_MAX. } } .b1. c).

asel}.sat} d.sat.bsel}.b0. r3. tmp = MAX( ta. vmax require sm_20 or later. // 32-bit scalar operation. vmax Syntax Integer byte/half-word/word addition / subtraction.s32.bsel = { . .s32. tmp.btype{. . r1. vsub. .max }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . r3.atype. vmax vadd.bsel}.btype = { .atype = .dsel .s32 }. with optional secondary operation vop.b2.b1. vmin. Video Instructions: vadd. vsub.dtype. .s32. tmp. with optional data merge vop. Semantics // saturate. // optional merge with c operand 142 January 24. tmp = | ta – tb |. vabsdiff. r2. vsub. . c. . r1. .s32.h1.h1. Perform scalar arithmetic operation with optional saturate.asel = . c.s32. . Integer byte/half-word/word minimum / maximum.op2 d. r2. vmax }.sat vsub. tb = partSelectSignExtend( b. tb ).u32. taking into account destination type and merge operations tmp = optSaturate( tmp. // extract byte/half-word/word and sign.s32. r2.atype. b{.s32.op2 Description = = = = { vadd. { . vadd.b3. 2010 .b0. r3. vmin.b0. asel ). c ). vmin. . c ).btype{.dsel. r3.add r1.dtype . a{. a{.min.h0. and optional secondary arithmetic operation or subword data merge.vop .bsel}. isSigned(dtype).or zero-extend based on source operand type ta = partSelectSignExtend( a. tmp = ta – tb. c.sat vabsdiff. vsub vabsdiff vmin. tb ). vabsdiff. bsel ). btype.h0. r2.s32. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.btype{.add. r1. atype.asel}.h0. dsel ).asel}.dtype. b{.s32.sat vmin. a{. tmp = MIN( ta.h1 }.s32.dtype. . vadd.u32.atype. // 32-bit scalar operation. Integer byte/half-word/word absolute value of difference.PTX ISA Version 2.u32.sat}. // optional secondary operation d = optMerge( dsel.0.sat} d. sat. vop. vabsdiff. b{. c.b2.0 Table 105. d = optSecondaryOp( op2.

u32{. . Semantics // extract byte/half-word/word and sign. atype. { .clamp && tb > 32 ) tb = 32. January 24. . . dsel ). b{.asel}.u32.b2.vop . sat. if ( mode == . vshr Syntax Integer byte/half-word/word left / right shift. vshr vshl.bsel}. b{. a{.bsel = { .or zero-extend based on source operand type ta = partSelectSignExtend( a.mode} d.atype. // optional secondary operation d = optMerge( dsel.atype = { . r1.h0.dsel.u32. and optional secondary arithmetic operation or subword data merge.dtype.b3. with optional secondary operation vop.asel}. vop. .u32 vshr.wrap ) tb = tb & 0x1f.wrap }.asel = .mode . // 32-bit scalar operation.wrap r1.u32. a{. with optional data merge vop.sat}{.add.b1.dsel . r3.bsel}.s32 }. .min. { .u32.op2 d. . . c ).h1 }.s32.mode}. isSigned(dtype).u32. tb = partSelectSignExtend( b.Chapter 8.sat}{. tmp. Signed shift fills with the sign bit. c. Instruction Set Table 106. vshl: Shift a left by unsigned amount in b with optional saturate. Left shift fills with zero.atype. bsel ).u32{. // 32-bit scalar operation. vshl. vshr }. b{.dtype.sat}{.clamp . vshl. . Video Instructions: vshl. switch ( vop ) { case vshl: tmp = ta << tb. asel ).b0. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. } // saturate.u32. and optional secondary arithmetic operation or subword data merge.h1.atype. .bsel}. d = optSecondaryOp( op2. 2010 143 . unsigned shift fills with zero.dtype . . if ( mode == .u32{. . c ). taking into account destination type and merge operations tmp = optSaturate( tmp. r3. c. r2.asel}.dtype. .mode} d. vshr: Shift a right by unsigned amount in b with optional saturate.max }. vshr require sm_20 or later.clamp. tmp. r2. a{. case vshr: tmp = ta >> tb.op2 Description = = = = = { vshl. // default is .

S32 // intermediate signed. 2010 .po) computes (a*b) + c + 1. . final signed (U32 * S32) + S32 // intermediate signed.u32.scale} d.s32 }. this result is sign-extended if the final result is signed. which is used in computing averages.S32 // intermediate signed. the intermediate result is signed. Input c has the same sign as the intermediate result. The final result is unsigned if the intermediate result is unsigned and c is not negated.shr7. final signed (U32 * S32) .S32 // intermediate signed.po{. internally this is represented as negation of the product (a*b).scale = { .shr15 }. That is.PTX ISA Version 2.btype{. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. final signed The intermediate result is optionally scaled via right-shift. {-}c. final signed -(U32 * S32) + S32 // intermediate signed.dtype.dtype = . vmad. // 32-bit scalar operation vmad.atype = . and the operand negates. Source operands may not be negated in .po mode. Description Calculate (a*b) + c. final signed -(S32 * S32) + S32 // intermediate signed. final signed -(S32 * U32) + S32 // intermediate signed.0 Table 107. (a*b) is negated if and only if exactly one of a or b is negated. . final signed (S32 * U32) + S32 // intermediate signed. final unsigned -(U32 * U32) + S32 // intermediate signed.sat}{. Although PTX syntax allows separate negation of the a and b operands.btype = { .btype.scale} d. . otherwise.bsel}. .b3. . {-}a{. . . final signed (U32 * U32) .bsel = { .asel = . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. a{. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.atype. and zero-extended otherwise. {-}b{. final signed (S32 * S32) . final signed (S32 * S32) + S32 // intermediate signed.asel}. The source operands support optional negation with some restrictions. final signed (S32 * U32) . c.asel}.atype.sat}{.h1 }. The “plus one” mode (..b0.h0. .b2. with optional operand negates. Depending on the sign of the a and b operands.bsel}. and scaling.U32 // intermediate unsigned. 144 January 24. “plus one” mode.dtype.b1. PTX allows negation of either (a*b) or c. b{. . . The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.

negate) || c.shr7: result = (tmp >> 7) & 0xffffffffffffffff.sat ) { if (signedFinal) result = CLAMP(result. U32_MIN).u32. Instruction Set Semantics // extract byte/half-word/word and sign. } if ( . lsb = 1. if ( . asel ). r0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.sat vmad.negate ^ b. atype. lsb = 1. } else if ( c. case . } else if ( a. 2010 145 . January 24. else result = CLAMP(result. U32_MAX.or zero-extend based on source operand type ta = partSelectSignExtend( a. r3.h0. r2. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). switch( scale ) { case .negate ) { c = ~c. vmad requires sm_20 or later. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. btype. lsb = 0. r2.u32. S32_MIN). tmp[127:0] = ta * tb. r1.u32. vmad. -r3.0.shr15 r0.negate ^ b. r1.s32. tmp = tmp + c128 + lsb.po ) { lsb = 1. bsel ).h0.negate ) { tmp = ~tmp.negate. S32_MAX.s32. signedFinal = isSigned(atype) || isSigned(btype) || (a.Chapter 8. tb = partSelectSignExtend( b.u32.

a{.PTX ISA Version 2. atype.h1.le. . vset. c ).u32.bsel}.atype . r2. vset.b3.dsel .bsel}.b1. tmp. . r2.s32 }.eq.or zero-extend based on source operand type ta = partSelectSignExtend( a. .min.bsel = { .btype. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.max }. r3.asel}.add. .btype = { . . b{. with optional secondary arithmetic operation or subword data merge.dsel. a{. a{.asel = . . tb.h1 }. c. vset requires sm_20 or later.b2.cmp. tmp = compare( ta. // 32-bit scalar operation. 2010 .0. // 32-bit scalar operation. tb = partSelectSignExtend( b. { .ne r1. bsel ). . Compare input values using specified comparison.cmp .h0.btype.cmp d. c.asel}. .op2 d.u32. b{.asel}.op2 Description = = = = . . . r1. tmp.lt. . 146 January 24.atype. r3. with optional data merge vset.0 Table 108. The intermediate result of the comparison is always unsigned. d = optSecondaryOp( op2.btype. .bsel}. asel ). b{. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.atype. Semantics // extract byte/half-word/word and sign.lt vset.s32.u32.ge }.b0.ne.cmp d. with optional secondary operation vset. // optional secondary operation d = optMerge( dsel.gt. { . . and therefore the c operand and final result are also unsigned.atype. cmp ) ? 1 : 0. . btype. . c ).

trap.Chapter 8. Introduced in PTX ISA version 1. brkpt. pmevent 7. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters.7. January 24. Supported on all target architectures. @p pmevent 1. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. with index specified by immediate operand a. The relationship between events and counters is programmed via API calls from the host. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. brkpt requires sm_11 or later.0. Notes PTX ISA Notes Target ISA Notes Examples Currently. pmevent a.4. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. trap. 2010 147 . Table 111. Table 110. brkpt Suspends execution Introduced in PTX ISA version 1. numbered 0 through 15. Instruction Set 8. Supported on all target architectures. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.10. Triggers one of a fixed number of performance monitor events.0. trap Abort execution and generate an interrupt to the host CPU. Introduced in PTX ISA version 1. there are sixteen performance monitor events. brkpt.

PTX ISA Version 2. 2010 .0 148 January 24.

read-only variables.Chapter 9. …. %lanemask_gt %clock. which are visible as special registers and accessed through mov or cvt instructions. %clock64 %pm0. Special Registers PTX includes a number of predefined. 2010 149 . %lanemask_le. %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %pm3 January 24. %lanemask_lt.

// CTA shape vector // CTA dimensions A predefined.z.sreg . mov.u32 type in PTX 2.y * %ntid.%tid.v4. .z to %r2 Table 113.0.x code accessing 16-bit component of %tid mov. or 3D vector to match the CTA shape.0.x. cvt.z == 0 in 1D CTAs. // compute unified thread id for 2D CTA mov. %tid.y 0 <= %tid.v4 . the %tid value in unused dimensions is 0. 2010 .y == %tid. Supported on all target architectures.%h1.z == 0 in 2D CTAs.%tid.x * %ntid.0.x.z).x.u32 type in PTX 2. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. %ntid.z < %ntid.y.0 Table 112. The %tid special register contains a 1D. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.%r0. .x.x code Target ISA Notes Examples 150 January 24.u32 %tid. per-thread special register initialized with the thread identifier within the CTA.z. mov. The fourth element is unused and always returns zero. %tid component values range from 0 through %ntid–1 in each CTA dimension. CTA dimensions are non-zero.%tid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.v4.%ntid.y. read-only.PTX ISA Version 2. PTX ISA Notes Introduced in PTX ISA version 1.x < %ntid. // thread id vector // thread id components A predefined.x.sreg . mov. It is guaranteed that: 0 <= %tid. %tid.%tid.0.x 0 <= %tid.y == %ntid.u32.z == 1 in 2D CTAs.y.u16 %rh. 2D. // zero-extend tid.%ntid.u32 %tid. . // legacy PTX 1.x. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.y < %ntid. %tid. mad. mov.u32 %ntid.u16 %rh.x.%h2. %ntid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.u32 %r1. %ntid.%tid.u32 %r0. The total number of threads in a CTA is (%ntid.x to %rh Target ISA Notes Examples // legacy PTX 1.z. The number of threads in each dimension are specified by the predefined special register %ntid. // move tid.v4 .u32 %r0.sreg . Redefined as .u16 %r2.sreg . %tid.u32 %h2.z == 1 in 1D CTAs. .z PTX ISA Notes Introduced in PTX ISA version 1. Every thread in the CTA has a unique %tid. the fourth element is unused and always returns zero. %ntid.u32 %h1.u32 %ntid. Supported on all target architectures. read-only special register initialized with the number of thread ids in each CTA dimension. Redefined as .

3. Special Registers Table 114. read-only special register that returns the maximum number of warp identifiers. Introduced in PTX ISA version 1. . The lane identifier ranges from zero to WARP_SZ-1. mov. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.sreg . mov. read-only special register that returns the thread’s lane within the warp. .3. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.sreg .g. For this reason. but its value may change during execution.u32 %laneid.u32 %warpid. Supported on all target architectures. %nwarpid.sreg .Chapter 9. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.u32 %r. %laneid. mov. e. 2010 151 .u32 %r. January 24. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. . Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Table 116. A predefined.0. Introduced in PTX ISA version 1. A predefined. due to rescheduling of threads following preemption. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. A predefined.u32 %nwarpid. Table 115. Introduced in PTX ISA version 2. read-only special register that returns the thread’s warp identifier. The warp identifier will be the same for all threads within a single warp. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.u32 %r. %warpid. Note that %warpid is volatile and returns the location of a thread at the moment when read. %nwarpid requires sm_20 or later.

sreg . mov. mov.%nctaid. It is guaranteed that: 1 <= %nctaid.0. The fourth element is unused and always returns zero.z < %nctaid. // legacy PTX 1.sreg .x. depending on the shape and rank of the CTA grid.v4 .%nctaid. %rh. // CTA id vector // CTA id components A predefined. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.x.u32 %ctaid.u32 mov.x code Target ISA Notes Examples Table 118. %ctaid. Supported on all target architectures.x code Target ISA Notes Examples 152 January 24.0 Table 117. It is guaranteed that: 0 <= %ctaid. The %ctaid special register contains a 1D.u32 %nctaid . .z.v4.z} < 65. // Grid shape vector // Grid dimensions A predefined. The fourth element is unused and always returns zero. or 3D vector.z PTX ISA Notes Introduced in PTX ISA version 1.y < %nctaid.0.x.%ctaid. read-only special register initialized with the CTA identifier within the CTA grid.x 0 <= %ctaid.PTX ISA Version 2.y. read-only special register initialized with the number of CTAs in each grid dimension. .%ctaid. with each element having a value of at least 1.%nctaid. . Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.u32 mov.u32 %nctaid. Redefined as .u16 %r0.0.y.x < %nctaid. // legacy PTX 1. 2D.y.sreg .0.y.z. 2010 . %rh.536 PTX ISA Notes Introduced in PTX ISA version 1.u16 %r0.y 0 <= %ctaid.u32 type in PTX 2.u32 %ctaid.{x.x.x. The %nctaid special register contains a 3D grid shape vector. Supported on all target architectures.v4.u32 type in PTX 2. Redefined as .sreg . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.v4 . %ctaid. Each vector element value is >= 0 and < 65535.%nctaid.

During execution.u32 %r.3.u32 %gridid.g.sreg .u32 %smid.u32 %r. read-only special register that returns the maximum number of SM identifiers.0.0. A predefined. but its value may change during execution. PTX ISA Notes Target ISA Notes Examples Table 121. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. The SM identifier numbering is not guaranteed to be contiguous. %nsmid. mov. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Examples Table 120. // initialized at grid launch A predefined. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Supported on all target architectures. . due to rescheduling of threads following preemption. where each launch starts a grid-of-CTAs. Special Registers Table 119. so %nsmid may be larger than the physical number of SMs in the device. . Note that %smid is volatile and returns the location of a thread at the moment when read.u32 %nsmid. read-only special register initialized with the per-grid temporal grid identifier. PTX ISA Notes Target ISA Notes Examples January 24. %nsmid requires sm_20 or later. Introduced in PTX ISA version 1.Chapter 9. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. %smid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Introduced in PTX ISA version 2. Supported on all target architectures. . repeated launches of programs may occur.u32 %r. %gridid. mov. 2010 153 . This variable provides the temporal grid launch number for this context. The SM identifier numbering is not guaranteed to be contiguous. The SM identifier ranges from 0 to %nsmid-1.sreg . %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. e.sreg . mov. A predefined.

Introduced in PTX ISA version 2. . %lanemask_eq requires sm_20 or later.u32 %lanemask_le. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Table 123. . Introduced in PTX ISA version 2. . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.0. %lanemask_le.u32 %lanemask_lt. A predefined. mov.sreg .PTX ISA Version 2. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_lt.u32 %lanemask_eq. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later.u32 %r. 154 January 24. 2010 . %lanemask_le requires sm_20 or later.u32 %r. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. mov. A predefined. Table 124. %lanemask_eq. Introduced in PTX ISA version 2.u32 %r.sreg .0. A predefined.sreg .0. mov.0 Table 122.

sreg .0. 2010 155 . Special Registers Table 125.Chapter 9. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_gt.u32 %lanemask_gt.sreg . A predefined. A predefined. %lanemask_gt requires sm_20 or later. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge.u32 %lanemask_ge. . read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %r. January 24. . mov. Table 126. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. mov. %lanemask_ge requires sm_20 or later.0.u32 %r.

. %pm2.u32 %clock.sreg . Introduced in PTX ISA version 1.PTX ISA Version 2. %pm1.u32 %pm0. read-only 32-bit unsigned cycle counter. Special registers %pm0. The lower 32-bits of %clock64 are identical to %clock.0. Table 128. Supported on all target architectures. mov. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.u64 r1.0. mov.u32 r1. Their behavior is currently undefined. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. …. . . Special Registers: %pm0.%clock. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm3. mov.u64 %clock64. Supported on all target architectures. %pm1. %pm2.3.u32 r1. read-only 64-bit unsigned cycle counter.sreg . Introduced in PTX ISA version 1. %pm3 %pm0.sreg . %pm1.%pm0. and %pm3 are unsigned 32-bit read-only performance monitor counters. %clock64 requires sm_20 or later. 2010 . Introduced in PTX ISA version 2. Table 129.%clock64. 156 January 24. %pm2.0 Table 127. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.

Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directive.0 .0.version directives are allowed provided they match the original .4 January 24. Supported on all target architectures.version major. . Increments to the major number indicate incompatible changes to PTX. Each ptx file must begin with a .version 2.version directive. .version Syntax Description Semantics PTX version number. minor are integers Specifies the PTX language version number.version 1.minor // major.Chapter 10.version .1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. and the target architecture for which the code was generated. Duplicate . . PTX File Directives: .version . 2010 157 .target Table 130. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Directives 10.

Note that . brkpt instructions. Each PTX file must begin with a . vote instructions.target directives can be used to change the set of target features allowed during parsing. Adds double-precision support.red}. Supported on all target architectures.texmode_unified . Requires map_f64_to_f32 if any . including expanded rounding modifiers. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. sm_12. Therefore.0 Table 131.texref descriptor. texture and sampler information is referenced with independent . texmode_independent.target directive containing a target architecture and optional platform options.red}.target .f32. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. 2010 . generations of SM architectures follow an “onion layer” model.0.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. and an error is generated if an unsupported feature is used. with only half being used by instructions converted from .target directive specifies a single target architecture.f64 instructions used.f64 instructions used. Introduced in PTX ISA version 1.f64 instructions used. Texturing mode: (default is . Requires map_f64_to_f32 if any . 64-bit {atom.shared. . immediately followed by a . Adds {atom.texmode_independent texture and sampler information is bound together and accessed via a single . where each generation adds new features and retains all features of previous generations. PTX features are checked against the specified target architecture.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. 158 January 24.samplerref descriptors.texref and . Requires map_f64_to_f32 if any . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Texturing mode introduced in PTX ISA version 1. Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_10. sm_13. but subsequent .f64 storage remains as 64-bits.5. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Target sm_20 Description Baseline feature set for sm_20 architecture. The texturing mode is specified for an entire module and cannot be changed within the module. Adds {atom. A .version directive. PTX File Directives: . PTX code generated for a given target can be run on later generation devices.red}.global. texmode_unified.target Syntax Architecture and Platform target. The following table summarizes the features in PTX that vary according to target architecture. In general. Disallows use of map_f64_to_f32. A program with multiple . map_f64_to_f32 }.PTX ISA Version 2.texmode_unified) . sm_11.global.f64 to .

2010 159 .Chapter 10.target sm_20. Directives Examples . texmode_independent January 24.target sm_13 // supports double-precision .target sm_10 // baseline target architecture .

… } . parameter variables are declared in the kernel body. %nctaid.param.5 and later. Kernel and Function Directives: .entry filter ( .entry Syntax Description Kernel entry point and body. Supported on all target architectures.entry . parameter variables are declared in the kernel parameter list.g. and query instructions and cannot be accessed via ld.4.b32 %r2. Semantics Specify the entry point for a kernel program. parameters.param. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. [z].entry cta_fft .texref.PTX ISA Version 2. opaque . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. 160 January 24. the kernel dimensions and properties are established and made available via special registers. . . For PTX ISA versions 1. ld. At kernel launch.param instructions. and . .param . ld. . e.func Table 132.param instructions. In addition to normal parameters.3.entry kernel-name kernel-body Defines a kernel entry point name.0 through 1. .4 and later.b32 %r<99>.entry kernel-name ( param-list ) kernel-body . ld. %ntid.b32 %r1. with optional parameters. 2010 .b32 x. and body for the kernel function. PTX ISA Notes For PTX ISA version 1.0 10. [y].param .b32 %r3.surfref variables may be passed as parameters. The shape and size of the CTA executing the kernel are available in special registers.2.samplerref. Parameters may be referenced by name within the kernel body and loaded into registers using ld. etc. . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Parameters are passed via . These parameters can only be referenced by name within texture and surface load.reg .param { . store.b32 z ) Target ISA Notes Examples [x].entry .b32 y.param space memory and are listed within an optional parenthesized parameter list.0 through 1.param.

The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.b32 rval) foo (. A . mov. parameters must be in the register state space.reg . Parameters must be base types in either the register or parameter state space.func definition with no body provides a function prototype. foo.b32 N. .0. 2010 161 . dbl. PTX ISA 2.func fname function-body . .result.func (ret-param) fname (param-list) function-body Defines a function. Parameters in . other code. Variadic functions are currently unimplemented. Supported on all target architectures. Kernel and Function Directives: .2 for a description of variadic functions. if any. The parameter lists define locally-scoped variables in the function body.x code. Directives Table 133. PTX 2.param space are accessed using ld.b32 localVar.param instructions in the body. including input and return parameters and optional function body. Parameter passing is call-by-value.reg . there is no stack. and recursion is illegal.b32 rval. Variadic functions are represented using ellipsis following the last fixed argument.0 with target sm_20 supports at most one return value. .func fname (param-list) function-body . Parameters in register state space may be referenced directly within instructions in the function body. which may use a combination of registers and stack locations to pass parameters. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.func .param state space. The implementation of parameter passing is left to the optimizing translator. … use N. Release Notes For PTX ISA version 1. implements an ABI with stack.reg .f64 dbl) { .Chapter 10.func Syntax Function definition. (val0.func (. val1).0 with target sm_20 allows parameters in the . … Description // return value in fooval January 24. and supports recursion. } … call (fooval).param and st. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. ret.reg .

minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). the .pragma directive is supported for passing information to the PTX backend.maxntid directive specifies the maximum number of threads in a thread block (CTA). 2010 . and . The . 162 January 24. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. Currently.maxntid.g.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. for example. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. A general .pragma directives may appear at module (file) scope. and the .maxnreg. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.PTX ISA Version 2. PTX supports the following directives. Note that . The directives take precedence over any module-level constraints passed to the optimizing backend. and the strings have no semantics within the PTX virtual machine model. These can be used.maxntid and . The directive passes a list of strings to the backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. .minnctapersm directives may be applied per-entry and must appear between an . registers) to increase total thread count and provide a greater opportunity to hide memory latency.maxnreg . the . The interpretation of . which pass information to the backend optimizing compiler. or as statements within a kernel or device function body.minnctapersm .entry directive and its body. at entry-scope. to throttle the resource requirements (e.3.pragma The .0 10.maxnctapersm (deprecated) .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. .maxntid .

maxntid nx. Performance-Tuning Directives: .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.entry foo . or 3D CTA. .maxctapersm. Introduced in PTX ISA version 1. .maxnreg .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid and . ny .3. 2D. Exceeding any of these limits results in a runtime error or kernel launch failure.maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid Syntax Maximum number of threads in thread block (CTA). nz Declare the maximum number of threads in the thread block (CTA). . 2010 163 . Performance-Tuning Directives: .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. Directives Table 134. The actual number of registers used may be less. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid 16.Chapter 10. Introduced in PTX ISA version 1. Supported on all target architectures.maxntid 256 . The maximum number of threads is the product of the maximum extent in each dimension.entry foo . for example. The compiler guarantees that this limit will not be exceeded.maxntid .entry bar . the backend may be able to compile to fewer registers.maxntid nx . ny. or the maximum number of registers may be further constrained by . Supported on all target architectures.maxntid nx. .16.3.

additional CTAs may be mapped to a single multiprocessor.PTX ISA Version 2. .maxnctapersm generally need .maxnctapersm (deprecated) . The optimizing backend compiler uses . Optimizations based on .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.entry foo . Performance-Tuning Directives: .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid and .0 Table 136.minnctapersm .maxntid to be specified as well.0.maxnctapersm has been renamed to . For this reason.0.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.minnctapersm 4 { … } 164 January 24.maxntid to be specified as well.minnctapersm in PTX ISA version 2.maxntid 256 . Performance-Tuning Directives: .entry foo . 2010 .maxntid 256 . Optimizations based on .minnctapersm generally need .maxnctapersm.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. . Supported on all target architectures. Introduced in PTX ISA version 2.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). . .0 as a replacement for . Supported on all target architectures. Deprecated in PTX ISA version 2. However. if the number of registers used by the backend is sufficiently lower than this bound.3. Introduced in PTX ISA version 1. .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).

pragma Syntax Description Pass directives to PTX backend compiler. Directives Table 138. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Performance-Tuning Directives: .pragma list-of-strings . The interpretation of . or statement-level directives to the PTX backend compiler. at entry-scope. { … } January 24. The . or at statementlevel.pragma directive may occur at module-scope.pragma directive strings is implementation-specific and has no impact on PTX semantics. Introduced in PTX ISA version 2. Pass module-scoped.entry foo . Supported on all target architectures. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma “nounroll”.pragma . entry-scoped. .Chapter 10.0. 2010 165 . .pragma “nounroll”.

0 10.0. 0x00.4. replaced by . 0x02.264-1] . 0x00 . 0x5f736f63 . Deprecated as of PTX 2.2.quad int64-list // comma-separated hexadecimal integers in range [0. 0x00.byte 0x00. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .byte byte-list // comma-separated hexadecimal byte values .4byte int32-list // comma-separated hexadecimal integers in range [0.debug_info . Introduced in PTX ISA version 1.x code.232-1] . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .4byte 0x6e69616d.4byte . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x736d6172 .debug_pubnames.section . Supported on all target architectures.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. @@DWARF dwarf-string dwarf-string may have one of the . @progbits .4byte label . Table 139. 0x00.. 0x61395a5f.4byte 0x000006b5. 0x00. 0x00 166 January 24.file . 0x6150736f.byte 0x2b.. 0x00. “”.section .0 and replaces the @@DWARF syntax.PTX ISA Version 2.0 but is supported for legacy PTX version 1. 0x00. The @@DWARF syntax is deprecated as of PTX version 2.section directive. 2010 . 0x63613031.section directive is new in PTX ISA verison 2. 0x00000364.loc The .

.file . . 0x00. 0x63613031. 0x5f736f63 0x6150736f. .b32 int32-list // comma-separated list of integers in range [0. Supported on all target architectures.section Syntax PTX section definition. 0x00000364.b32 label .b64 int64-list // comma-separated list of integers in range [0.0.b32 .0.b32 0x000006b5.255] .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.232-1] .debug_pubnames { .b8 byte-list // comma-separated list of integers in range [0.264-1] . replaces @@DWARF syntax.. 0x00. . Debugging Directives: .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Debugging Directives: .section .file filename Table 142. 2010 167 .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.debug_info . 0x736d6172 0x00 Table 141.Chapter 10.b8 0x00. . 0x00. Supported on all target architectures. } 0x02.loc line_number January 24. 0x00. Directives Table 140. 0x00.0. Source file location. .b8 0x2b.. 0x00 0x61395a5f. Supported on all target architectures. Debugging Directives: . Source file information.section .loc .b32 0x6e69616d.section section_name { dwarf-lines } dwarf-lines have the following formats: . . . 0x00.

Linking Directives .b32 foo. Supported on all target architectures. Supported on all target architectures. // foo is defined in another module Table 144.PTX ISA Version 2.extern .visible . .extern identifier Declares identifier to be defined externally. .visible identifier Declares identifier to be externally visible. Introduced in PTX ISA version 1. . // foo will be externally visible 168 January 24.visible Table 143.0.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.visible . Linking Directives: .0.6. Introduced in PTX ISA version 1. .extern . Linking Directives: .0 10.global .b32 foo. 2010 .global .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern .

2 PTX ISA 1.3 PTX ISA 1.4 PTX ISA 1.0 CUDA 1. and the remaining sections provide a record of changes in previous releases.0 January 24.0 driver r195 PTX ISA Version PTX ISA 1.1 CUDA 2.5 PTX ISA 2. 2010 169 .0 PTX ISA 1. CUDA Release CUDA 1.1 PTX ISA 1.3 driver r190 CUDA 3. The release history is as follows.0 CUDA 2.Chapter 11.1 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.2 CUDA 2.0. The first section describes ISA and implementation changes in the current release of PTX ISA 2.

ftz modifier may be used to enforce backward compatibility with sm_1x. and sqrt with IEEE 754 compliant rounding have been added.1.0 11.rn. When code compiled for sm_1x is executed on sm_20 devices. mad.f32 maps to fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.sat modifiers. rcp.PTX ISA Version 2. Single.0 for sm_20 targets.0 11. Floating-Point Extensions This section describes the floating-point changes in PTX 2. The mad. The goal is to achieve IEEE 754 compliance wherever possible. and mul now support .f32. while maximizing backward compatibility with legacy PTX 1. Changes in Version 2.1.1.1. The .f32 instruction also supports . A single-precision fused multiply-add (fma) instruction has been added.f32 requires sm_20. The fma. • • • • • 170 January 24.rm and .rp rounding modifiers for sm_20 targets.1.f32 for sm_20 targets.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Instructions testp and copysign have been added.x code and sm_1x targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. The changes from PTX ISA 1. New Features 11.f32 require a rounding modifier for sm_20 targets. The mad.and double-precision div.ftz and . Single-precision add.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. sub.f32 and mad. These are indicated by the use of a rounding modifier and require sm_20. fma.1. Both fma. 2010 .

%clock64. A “population count” instruction.clamp modifiers. local. A system-level membar instruction. Bit field extract and insert instructions.1. Video instructions (includes prmt) have been added.zero. and sust.arrive instruction has been added.minnctapersm to better match its behavior and usage. vote. January 24. New special registers %nsmid. Instruction sust now supports formatted surface stores.gt} have been added.or}.g.red}. Instructions {atom. Instructions prefetch and prefetchu have also been added.1.ge. Instructions bar. 2010 171 .red. A “bit reversal” instruction.add.Chapter 11.le. New instructions A “load uniform” instruction. e.clamp and . ldu.red}. clz. has been added.sys. atom.maxnctapersm directive was deprecated and replaced with . and red now support generic addressing. has been added. A “vote ballot” instruction. st. cvta.f32 have been implemented. prefetchu.pred have been added. prefetch.red.1.lt. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. popc. Instruction cvta for converting global. st.2. has been added. for prefetching to specified level of memory hierarchy.section. isspacep. bfind.1. A “find leading non-sign bit” instruction. has been added. membar.3.shared have been extended to handle 64-bit data types for sm_20 targets. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. %lanemask_{eq. suld. Release Notes 11. have been added.b32. Other new features Instructions ld. ldu. has been added. 11. Instructions {atom.ballot. . bar now supports optional thread count and register operands. The . A “count leading zeros” instruction. has been added.popc.u32 and bar. .{and. Cache operations have been added to instructions ld. brev. A new directive. has been added. and shared addresses to generic address and vice-versa has been added. Surface instructions support additional . The bar instruction has been extended as follows: • • • A bar. bfe and bfi.

max} are not implemented. where . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. or .ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.0 11.4 and earlier. In PTX version 1. 11. has been fixed. {atom.{min. Formatted surface load is unimplemented. See individual instruction descriptions for details.PTX ISA Version 2. stack-based ABI is unimplemented. The underlying.red}. .u32. 2010 .1. if . Support for variadic functions and alloca are unimplemented. the correct number is sixteen.3.s32. Formatted surface store with .5 and later.5.1. cvt. 172 January 24.{u32.2.f32} atom.target sm_1x. Instruction bra.p. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. To maintain compatibility with legacy PTX code. call suld. Semantic Changes and Clarifications The errata in cvt.s32.ftz for PTX ISA versions 1.p sust.f32 type is unimplemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.ftz (and cvt for .version is 1. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.4 or earlier.f32.

The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.pragma “nounroll”. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. { … } // do not unroll any loop in this function .pragma. Ignored for sm_1x targets. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.func bar (…) { … L1_head: . and statement levels. Supported only for sm_20 targets.pragma strings defined by ptxas.entry foo (…) . disables unrolling for all loops in the entry function body.pragma “nounroll”. L1_end: … } // do not unroll this loop January 24. including loops preceding the .0. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. L1_body: … L1_continue: bra L1_head. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.Appendix A. . 2010 173 . . The “nounroll” pragma is allowed at module. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Descriptions of . entry-function. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. disables unrolling of0 the loop for which the current block is the loop header. Note that in order to have the desired effect at statement level. … @p bra L1_end. Table 145.pragma “nounroll”.pragma Strings This section describes the .

2010 .PTX ISA Version 2.0 174 January 24.

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