NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

.... Operand Type Information .........................4............ Abstracting the ABI .... 43 Vectors as Operands ..... 49 ii January 24......4....................................... Summary of Constant Expression Evaluation Rules ..............................1..................................................................................................... and Variables ...................................4.....3...............................1....3.................................... 39 5.....2..............4..................................................................................................................................................................... 42 Addresses as Operands ............................... 6.............4.........................1................................................................3......2...... 39 Parameterized Variable Names .3........................... 32 5...... 29 Parameter State Space .........4.....2..... 5................................6............ 44 Rounding Modifiers ............................8................... 6......... 5.......4..................... 25 Chapter 5.................................................4............ Texture.. 6........................ 5............. 33 5.........................5...............1........................................5....................................................................... Types ........................................ 5.............1............... Arrays...................................................4...............0 4.... 5........................5....................................1...1.................. 5.........................PTX ISA Version 2............1....... 37 Vectors ............ 27 5.................................................................................................................. 6..................................... 28 Constant State Space . 5.... 37 Array Declarations ............................................................. 5.4...... 5...... 43 Labels and Function Names as Operands ...................... Chapter 6............................................................2...............................4...................... 2010 ................. State Spaces................................. 30 Shared State Space....................................................................................... 46 6...1................................................1..................... 6............ 6............................ and Surface Types ..................... 5.................................. 33 Restricted Use of Sub-Word Sizes ...........1..............................................5..............................2............................................. 41 Using Addresses............................... Operand Costs ...............6............ 41 Source Operands.................................................. Sampler............ 38 Alignment ...7....................... State Spaces .......... 29 Local State Space ....... 34 Variables ......................5...........4..........3................... 5.............................6.... 5................ and Vectors .................................. 29 Global State Space ......... 5............... 43 6..................................................... 41 6..................... Function declarations and definitions ............................................................ 5............................... 32 Texture State Space (deprecated) ..........1................2................................ 44 Scalar Conversions .... 6...............1........................................ 6..................4.............................................5...2...........................................................2............................................................. 6.......... 49 7..........4............................ Type Conversion....................4................................ 47 Chapter 7...... 33 Fundamental Types ...................................................... 5..................... 5............. 37 Variable Declarations ...................... Instruction Operands...6............... 38 Initializers ..1...............................................1... 28 Special Register State Space ...................................................... Types.... 42 Arrays as Operands .......................2....................................................................... 27 Register State Space ..............................1...... 41 Destination Operands ..............................................

...................... 10...................................... 8................................ 10.....................................7............................................................ Changes from PTX 1....................6................4............................... 8....1............................................ Instructions .......... 104 Data Movement and Conversion Instructions ........7..................................................................................................... 162 Debugging Directives ....................................................... 52 Variadic functions ...................9...... 8....1...................... 100 Logic and Shift Instructions . 168 Chapter 11........... 166 Linking Directives ..........1. 8......................... 157 10...6..............1..1..... 8............0 .. 157 Specifying Kernel Entry Points and Functions ........................................ 172 January 24..........................................................................4................7......... 8.................................................................... 2010 iii ....... 63 Floating-Point Instructions ..........................x .................................................................... 170 Semantic Changes and Clarifications ....... 62 Machine-Specific Semantics of 16-bit Code .....7........5....3..... 60 8.............................2..1....................................... 55 PTX Instructions ............................1......... 8.................................................6..............................3.. 8..............................7...............................................1........1.... 56 Comparisons . Release Notes .......................... Type Information for Instructions and Operands ..............................................7........................................3..................................... Format and Semantics of Instruction Descriptions ............. 59 Operand Size Exceeding Instruction-Type Size ...............................................2........ 122 Control Flow Instructions ....... 8.........2.................................................................2.... 58 8..............................................7...................................... 160 Performance-Tuning Directives .................................10.................. PTX Version and Target Directives ...........................................3.......................................................... Divergence of Threads in Control Constructs ........................ Directives ............................................................7..................7............................. 81 Comparison and Selection Instructions .................................... 55 8...................... 10..................... 7.......... Chapter 9................. 149 Chapter 10.. 108 Texture and Surface Instructions ....................................................... 170 New Features ........................................3...................................................... 172 Unimplemented Features Remaining .. 63 Integer Arithmetic Instructions ...... 8.......................... 8............. 140 Miscellaneous Instructions.................... 11.............. 7............ 129 Parallel Synchronization and Communication Instructions ...............3........................1....7.................. 55 Predicated Execution ........................... 147 8....................... 8........................................ 10.................................1....................2...................... 54 Chapter 8.................4..................................................................................6... 8.......................................................................................................................... Instruction Set ..... 57 Manipulating Predicates ................................................... Changes in Version 2........................5........ 8.. 169 11........... 62 Semantics .............................. 132 Video Instructions . 62 8............................................7..... Special Registers .......................................................... 11.....................1.7.............................3..1. 11...........................2........................................8......... 8........................... 53 Alloca ..... 8...................7.............................4.................

............... 173 iv January 24...........0 Appendix A... Descriptions of ................... 2010 .............pragma Strings.....PTX ISA Version 2..

.. Table 21.................... Table 31........................................... 58 Floating-Point Comparison Operators Testing for NaN .................. Unsigned Integer.............................................................................................................................. 19 Predefined Identifiers ... Table 25..... 25 State Spaces .. Table 6... Table 27...................................... Table 2.. 57 Floating-Point Comparison Operators .......................... Table 23....................................................... 61 Integer Arithmetic Instructions: add ............ 57 Floating-Point Comparison Operators Accepting NaN ........................... Table 22.............................. Table 12................... 69 Integer Arithmetic Instructions: mad24 ............... Table 9.......................................................................................................... 46 Cost Estimates for Accessing State-Spaces ............. Table 17............................................................................................................................. 67 Integer Arithmetic Instructions: mad ............................. Table 13........... 65 Integer Arithmetic Instructions: addc ........ 65 Integer Arithmetic Instructions: sub. PTX Directives ....................................... 66 Integer Arithmetic Instructions: subc ........................................................................ 35 Opaque Type Fields in Independent Texture Mode .............. Table 28......................... Table 14............................... and Bit-Size Types ................................................................... 28 Fundamental Type Specifiers ............. 59 Relaxed Type-checking Rules for Source Operands ................... Table 3.................................................. 47 Operators for Signed Integer............ Table 5...................................................................... 20 Operator Precedence .................................................... Table 10.............. 71 January 24.... 60 Relaxed Type-checking Rules for Destination Operands.......................................................... Table 7...................... 27 Properties of State Spaces ...... Table 8. Table 15................................................ 64 Integer Arithmetic Instructions: add................................................................................................................................................................. 70 Integer Arithmetic Instructions: sad ..................... Table 32................ 46 Integer Rounding Modifiers .......................cc ................................................. 2010 v ................................... Table 18............................................... 45 Floating-Point Rounding Modifiers .......................... 18 Reserved Instruction Keywords ..................... 58 Type Checking Rules ....................................................List of Tables Table 1................................... 35 Convert Instruction Precision and Format ...................................... 64 Integer Arithmetic Instructions: sub .................................................................... Table 30..................................... 23 Constant Expression Evaluation Rules ....... 33 Opaque Type Fields in Unified Texture Mode .............. 66 Integer Arithmetic Instructions: mul ...................................... Table 4........... Table 20.............. Table 29............................................................. Table 19..................... Table 26........................ Table 16... Table 24......... Table 11.................cc ............................................. 68 Integer Arithmetic Instructions: mul24 .................................................................................

..................................... 78 Integer Arithmetic Instructions: prmt ................................................ 74 Integer Arithmetic Instructions: bfind . 90 Floating-Point Instructions: abs ....................................................................................................................................... Integer Arithmetic Instructions: div ........ 2010 ..................................... Table 38...................................... 76 Integer Arithmetic Instructions: bfe ........................................................... 87 Floating-Point Instructions: mad .................................. Table 47............................ Table 46............................................... Table 64..... Table 69.. Table 36....... 102 Comparison and Selection Instructions: selp ............ 84 Floating-Point Instructions: sub ........... Table 37...................................................... 96 Floating-Point Instructions: cos ................................................................ 74 Integer Arithmetic Instructions: clz ...................... 83 Floating-Point Instructions: copysign .... 99 Comparison and Selection Instructions: set ............................... 92 Floating-Point Instructions: max .............................................................................................................................................................. Table 45........... 83 Floating-Point Instructions: add ............................................ 79 Summary of Floating-Point Instructions ........................... Table 44... Table 54................ Table 62............... 86 Floating-Point Instructions: fma ................................................................................. Table 49.................................. Table 58..................................................................................................... Table 65................... Table 63.................. 85 Floating-Point Instructions: mul ...................................................................................................... Table 60.................................... Table 42................................................................... 71 Integer Arithmetic Instructions: rem .......... 91 Floating-Point Instructions: neg ............ Table 59............................................................................................................... Table 50................ Table 40............................................. 82 Floating-Point Instructions: testp .......... 101 Comparison and Selection Instructions: setp .. 72 Integer Arithmetic Instructions: min ..................0 Table 33................................................ Table 68........... 95 Floating-Point Instructions: sin ........... 75 Integer Arithmetic Instructions: brev ...................... 71 Integer Arithmetic Instructions: abs .......................................................................................... 72 Integer Arithmetic Instructions: neg ........ Table 55............................................................ 103 vi January 24..................................................PTX ISA Version 2...................................... 77 Integer Arithmetic Instructions: bfi ............ 98 Floating-Point Instructions: ex2 ........ Table 48......... Table 41.......... Table 34..................... 92 Floating-Point Instructions: rcp ....................... Table 43................. Table 39................................................ 97 Floating-Point Instructions: lg2 ............................................. Table 53....................................................... 88 Floating-Point Instructions: div .. 93 Floating-Point Instructions: sqrt .... Table 61........................................................................... 94 Floating-Point Instructions: rsqrt ....................... Table 35.. Table 52................................................................................................... Table 56.............................................. 103 Comparison and Selection Instructions: slct .............................................................. Table 51... 91 Floating-Point Instructions: min ................................ 73 Integer Arithmetic Instructions: popc ....................................................... Table 57............ Table 67......... Table 66............................. 73 Integer Arithmetic Instructions: max .....................................................................................................................................

.... Table 79......... Table 89........ Table 91............................................ 115 Data Movement and Conversion Instructions: st .............. Table 94................. 131 Control Flow Instructions: exit ...... 118 Data Movement and Conversion Instructions: isspacep ......... 143 January 24.......................... Table 106.....................Table 70.......................................................................... Table 98............. 106 Logic and Shift Instructions: not ................. Table 86....................................................................................................................... 131 Parallel Synchronization and Communication Instructions: bar ...................................... 126 Texture and Surface Instructions: sured...... 127 Texture and Surface Instructions: suq ............................................................................... Table 90............................... Table 83........................ 105 Logic and Shift Instructions: or ................ 107 Logic and Shift Instructions: shr . Table 97.................................................... Table 82.................................................... Logic and Shift Instructions: and ............................. 119 Data Movement and Conversion Instructions: cvta ........................ vmin.......... 130 Control Flow Instructions: ret .......................................................... Table 104................. 113 Data Movement and Conversion Instructions: ldu ............................................ Table 87.......... Table 103.. 2010 vii ...................... 129 Control Flow Instructions: @ ......................... vmax .......... Table 84....................... 139 Video Instructions: vadd........... Table 76............. 105 Logic and Shift Instructions: xor .................... Table 72. 133 Parallel Synchronization and Communication Instructions: membar ............ 110 Data Movement and Conversion Instructions: mov ............................................... Table 95.................................. Table 88............... vabsdiff... Table 81. 119 Data Movement and Conversion Instructions: cvt ....... prefetchu .............................. 128 Control Flow Instructions: { } .......... 106 Logic and Shift Instructions: cnot ...................................... 134 Parallel Synchronization and Communication Instructions: atom ............... Table 78........................ 137 Parallel Synchronization and Communication Instructions: vote ..... 107 Cache Operators for Memory Load Instructions ................................................................. 130 Control Flow Instructions: call .......................................... Table 96......... 106 Logic and Shift Instructions: shl ............ 135 Parallel Synchronization and Communication Instructions: red ....... Table 105............................. vsub............. Table 102........................... Table 75....................................... Table 100... Table 92...... 111 Data Movement and Conversion Instructions: mov ............................................. 124 Texture and Surface Instructions: suld .................................................... Table 73.......... Table 101.................. 109 Cache Operators for Memory Store Instructions .................................... Table 74..................................................... Table 99................ 116 Data Movement and Conversion Instructions: prefetch...................................... 142 Video Instructions: vshl............................................................................................................................................................................................................................. 125 Texture and Surface Instructions: sust ..... 112 Data Movement and Conversion Instructions: ld .............................. vshr ...................... Table 80................... Table 85... 129 Control Flow Instructions: bra ... 123 Texture and Surface Instructions: txq ...... Table 93.................................... Table 77............................................................. 120 Texture and Surface Instructions: tex .................................. Table 71.............................

............................. %pm2................................................................................................ Table 111........... 153 Special Registers: %nsmid ................................................................................................................................ Table 127..... 147 Miscellaneous Instructions: pmevent............................................................................................................................................................................................................................................... 154 Special Registers: %lanemask_lt ...................... 158 Kernel and Function Directives: ........................................................... Table 122...pragma ............ 156 Special Registers: %clock64 ................................................ 155 Special Registers: %clock .......... Table 117........... Table 126..................................................................................entry... Table 128................................. 150 Special Registers: %laneid .................. 163 Performance-Tuning Directives: ..0 Table 107.................................. Table 133.......file ....... Table 134................................minnctapersm ........................................................................................... Table 136....................... Table 125....... 156 PTX File Directives: .................................................... 156 Special Registers: %pm0............................target ........... Table 140.......................... Table 109...... Table 121...................loc ................................................................................. 144 Video Instructions: vset............................................ 152 Special Registers: %smid ..................................................................... 168 viii January 24..... Table 108................................... 153 Special Registers: %lanemask_eq ...... Table 119............... 151 Special Registers: %ctaid ... 151 Special Registers: %nwarpid ....... 167 Debugging Directives: .........extern.............. Table 116......................................... Table 113............................................version................... Table 115............... Table 142.................................................................... Video Instructions: vmad ..................... 150 Special Registers: %ntid ........................... 163 Performance-Tuning Directives: ..................................... 146 Miscellaneous Instructions: trap ............... Table 139........ 153 Special Registers: %gridid ......... 151 Special Registers: %warpid ..................................................... %pm3 ............................ 154 Special Registers: %lanemask_le ..........maxntid ... 154 Special Registers: %lanemask_ge . Table 120.................... %pm1........................................................ 157 PTX File Directives: ..... 166 Debugging Directives: ............................................. Table 110........................ Table 138...........maxnreg ..................................... 152 Special Registers: %nctaid ...................................................................... Table 143...... Table 123... Table 132............................................... 161 Performance-Tuning Directives: . 2010 ........................ Table 118............................................ 147 Special Registers: %tid .... 167 Linking Directives: ... Table 135......... 160 Kernel and Function Directives: ............................ Table 130........maxnctapersm (deprecated) .............. Table 131... 164 Performance-Tuning Directives: ..PTX ISA Version 2.................. 147 Miscellaneous Instructions: brkpt ............................................section ... Table 141.................................................... 155 Special Registers: %lanemask_gt ....................................... 167 Debugging Directives: ......................... Table 112......... Table 129. Table 114....................................................................................... Table 137.................func ........ 165 Debugging Directives: @@DWARF ...................................................................................... 164 Performance-Tuning Directives: .................................... Table 124..........

.................... 2010 ix ...... Linking Directives: ......................... 168 Pragma Strings: “nounroll” .........................Table 144.............. Table 145.......visible................................................................... 173 January 24.......

PTX ISA Version 2.0 x January 24. 2010 .

1. January 24. image and media processing applications such as post-processing of rendered images.Chapter 1. PTX defines a virtual machine and ISA for general purpose parallel thread execution. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations.2. Data-parallel processing maps data elements to parallel processing threads. Because the same program is executed for each data element. the programmable GPU has evolved into a highly parallel. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. stereo vision. PTX exposes the GPU as a data-parallel computing device. and pattern recognition can map image blocks and pixels to parallel processing threads. there is a lower requirement for sophisticated flow control. 1. PTX programs are translated at install time to the target hardware instruction set. many-core processor with tremendous computational horsepower and very high memory bandwidth. which are optimized for and translated to native target-architecture instructions. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. multithreaded. and because it is executed on many data elements and has high arithmetic intensity. 2010 1 . video encoding and decoding. image scaling. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time.1. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. the memory access latency can be hidden with calculations instead of big data caches. Similarly. In fact. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. from general signal processing or physics simulation to computational finance or computational biology. high-definition 3D graphics. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Introduction This document describes PTX.

Most of the new features require a sm_20 target.rm and . When code compiled for sm_1x is executed on sm_20 devices.x.f32 require a rounding modifier for sm_20 targets. reduction.0 is in improved support for the IEEE 754 floating-point standard. addition of generic addressing to facilitate the use of general-purpose pointers.rp rounding modifiers for sm_20 targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. memory.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Provide a machine-independent ISA for C/C++ and other compilers to target.f32 for sm_20 targets. A “flush-to-zero” (.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. PTX 2.ftz) modifier may be used to enforce backward compatibility with sm_1x. and all PTX 1. Provide a code distribution ISA for application and middleware developers.3. The changes from PTX ISA 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. Improved Floating-Point Support A main area of change in PTX 2. 1.f32 and mad. performance kernels. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. The mad.f32 requires sm_20. The main areas of change in PTX 2.0 PTX ISA Version 2. PTX ISA Version 2.f32 instruction also supports . Achieve performance in compiled applications comparable to native GPU performance. Facilitate hand-coding of libraries. The fma. mad. and video instructions.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32. and mul now support .ftz and . A single-precision fused multiply-add (fma) instruction has been added.3.PTX ISA Version 2.x code will continue to run on sm_1x targets as well. and the introduction of many new instructions.0 is a superset of PTX 1. including integer. atomic.1. Provide a common source-level ISA for optimizing code generators and translators.sat modifiers. fma. Single-precision add. sub. 2010 .x features are supported on the new sm_20 target.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Both fma.0 are improved support for IEEE 754 floating-point operations.rn. Instructions marked with . The mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. which map PTX to specific target machines. surface. • • • 2 January 24. barrier. 1. Legacy PTX 1. and architecture tests. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.f32 maps to fma.

local. e. allowing memory instructions to access these spaces without needing to specify the state space. an address that is the same across all threads in a warp. . 1.zero. and red now support generic addressing. 1. special registers.4.3. and directives are introduced in PTX 2. Generic Addressing Another major change is the addition of generic addressing. Instruction cvta for converting global. Surface Instructions • • Instruction sust now supports formatted surface stores. stack-based ABI. rcp.0. and sqrt with IEEE 754 compliant rounding have been added. st. New Instructions The following new instructions. i. Cache operations have been added to instructions ld.clamp and .g. January 24. These are indicated by the use of a rounding modifier and require sm_20. Instructions prefetch and prefetchu have been added.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Support for an Application Binary Interface Rather than expose details of a particular calling convention. instructions ld.Chapter 1.3. atom. so recursion is not yet supported. • Taken as a whole. st. Introduction • Single.and double-precision div. local. and shared addresses to generic addresses. for prefetching to specified level of memory hierarchy. and Application Binary Interface (ABI). Surface instructions support additional clamp modifiers. ldu.e.3. 2010 3 . cvta. PTX 2. A new cvta instruction has been added to convert global. In PTX 2. and shared state spaces. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.. NOTE: The current version of PTX does not implement the underlying.0. prefetch. local. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. stack layout. and shared addresses to generic address and vice-versa has been added. Generic addressing unifies the global. these changes bring PTX 2. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.3. prefetchu. suld.2. isspacep. Instructions testp and copysign have been added. 1. and sust.0 closer to full compliance with the IEEE 754 standard. and vice versa.

red}.ballot. 4 January 24.red}. Instructions bar. and Vote Instructions • • • New atomic and reduction instructions {atom. New special registers %nsmid. bar now supports an optional thread count and register operands.{and.PTX ISA Version 2.add. has been added.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. Barrier Instructions • • A system-level membar instruction. Reduction.pred have been added.u32 and bar. %lanemask_{eq. has been added. %clock64.arrive instruction has been added. A bar.sys.lt. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.red.shared have been extended to handle 64-bit data types for sm_20 targets. 2010 . A “vote ballot” instruction. bfi bit field extract and insert popc clz Atomic. Other Extensions • • • Video instructions (includes prmt) have been added.f32 have been added.or}. .section.red. A new directive. vote.gt} have been added.b32.ge. Instructions {atom.popc.le. membar.

4. Chapter 9 lists special registers. types. Chapter 4 describes the basic syntax of the PTX language. Introduction 1. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 11 provides release notes for PTX Version 2. Chapter 7 describes the function and call syntax. 2010 5 . January 24. Chapter 8 describes the instruction set. and PTX support for abstracting the Application Binary Interface (ABI).Chapter 1. Chapter 10 lists the assembly directives supported in PTX.0. calling convention. Chapter 6 describes instruction operands. Chapter 5 describes state spaces. Chapter 3 gives an overview of the PTX virtual machine model. and variable declarations.

2010 .0 6 January 24.PTX ISA Version 2.

1. Programming Model 2. ntid. can be isolated into a kernel function that is executed on the GPU as many different threads. compute-intensive portions of applications running on the host are off-loaded onto the device. Programs use a data parallel decomposition to partition inputs. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. compute addresses. The vector ntid specifies the number of threads in each CTA dimension. (with elements tid.z) that specifies the thread’s position within a 1D.y. or host: In other words. data-parallel.1. 2. A cooperative thread array. The thread identifier is a three-element vector tid. It operates as a coprocessor to the main CPU. is an array of threads that execute a kernel concurrently or in parallel.x. Each thread has a unique thread identifier within the CTA. More precisely. Each CTA thread uses its thread identifier to determine its assigned role. or CTA. 2D. a portion of an application that is executed many times.2. To coordinate the communication of the threads within the CTA. but independently on different data. Each CTA has a 1D. January 24. 2.2. and tid.y. Threads within a CTA can communicate with each other. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Cooperative thread arrays (CTAs) implement CUDA thread blocks. or 3D shape specified by a three-element vector ntid (with elements ntid.z). and results across the threads of the CTA. assign specific input and output positions.x.Chapter 2. tid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. work. 2D. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. or 3D CTA. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. To that effect. and ntid. 2010 7 . such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. and select work to perform.

Each grid also has a unique temporal grid identifier (gridid). Threads may read and use these values through predefined. such that the threads execute the same instructions at the same time.2.0 Threads within a CTA execute in SIMT (single-instruction. However. Threads within a warp are sequentially numbered. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). or sequentially. %ntid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. This comes at the expense of reduced thread communication and synchronization. which may be used in any instruction where an immediate operand is allowed.2.PTX ISA Version 2. or 3D shape specified by the parameter nctaid. %nctaid. 8 January 24. The warp size is a machine-dependent constant. 2. Each grid of CTAs has a 1D. CTAs that execute the same kernel can be batched together into a grid of CTAs. Typically. Some applications may be able to maximize performance with knowledge of the warp size. 2D . so that the total number of threads that can be launched in a single kernel invocation is very large. depending on the platform. Multiple CTAs may execute concurrently and in parallel. because threads in different CTAs cannot communicate and synchronize with each other. WARP_SZ. A warp is a maximal subset of threads from a single CTA. multiple-thread) fashion in groups called warps. The host issues a succession of kernel invocations to the device. so PTX includes a run-time immediate constant. a warp has 32 threads. 2010 . and %gridid. %ctaid. read-only special registers %tid.

0) Thread (0. 1) Thread (4. Programming Model Host GPU Grid 1 Kernel 1 CTA (0.Chapter 2. Figure 1. 2) Thread (2. 1) CTA (1. 1) Thread (0. 0) Thread (1. 2) Thread (4. 0) CTA (2. 1) Thread (0. 2) Thread (3. 2) Thread (1. 0) Thread (4. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (2. 1) Thread (1. 1) CTA (2. 0) Thread (3. 0) CTA (1. 2010 9 . Thread Batching January 24. 0) Thread (2. 0) CTA (0. 1) Grid 2 Kernel 2 CTA (1. A grid is a set of CTAs that execute independently. 1) Thread (3.

Each thread has a private local memory. or. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. constant. for some specific data formats. 2010 . constant. The global. Finally.0 2. referred to as host memory and device memory. The device memory may be mapped and read or written by the host. and texture memory spaces are persistent across kernel launches by the same application. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Texture memory also offers different addressing modes. for more efficient transfer.PTX ISA Version 2. Both the host and the device maintain their own local memory. as well as data filtering. and texture memory spaces are optimized for different memory usages. all threads have access to the same global memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. respectively. The global.3. 10 January 24.

Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (1. 1) Block (1. 1) Block (0. 0) Block (0. 0) Block (2.Chapter 2. 2010 11 . 2) Figure 2. 0) Block (0. 0) Block (1. 1) Grid 1 Global memory Block (0. 0) Block (1. 2) Block (1. 1) Block (2. Memory Hierarchy January 24.

2010 .0 12 January 24.PTX ISA Version 2.

different warps execute independently regardless of whether they are executing common or disjointed code paths. manages. the threads converge back to the same execution path. each warp contains threads of consecutive.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. manages. The way a block is split into warps is always the same. the warp serially executes each branch path taken. disabling threads that are not on that path. and on-chip shared memory. it splits them into warps that get scheduled by the SIMT unit. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). January 24.1. so full efficiency is realized when all threads of a warp agree on their execution path. a multithreaded instruction unit. A multiprocessor consists of multiple Scalar Processor (SP) cores. At every instruction issue time. The multiprocessor maps each thread to one scalar processor core. a cell in a grid-based computation). a voxel in a volume. and when all paths complete. new blocks are launched on the vacated multiprocessors. schedules. To manage hundreds of threads running several different programs. increasing thread IDs with the first warp containing thread 0. multiple-thread). The multiprocessor creates. When a multiprocessor is given one or more thread blocks to execute. The multiprocessor SIMT unit creates. the multiprocessor employs a new architecture we call SIMT (single-instruction. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. As thread blocks terminate. Parallel Thread Execution Machine Model 3. the first parallel thread technology. It implements a single-instruction barrier synchronization. A warp executes one common instruction at a time. (This term originates from weaving. Branch divergence occurs only within a warp. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. The threads of a thread block execute concurrently on one multiprocessor. and executes concurrent threads in hardware with zero scheduling overhead.Chapter 3. 2010 13 . Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. If threads of a warp diverge via a data-dependent conditional branch. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. allowing. and executes threads in groups of parallel threads called warps. and each scalar thread executes independently with its own instruction address and register state. When a host program invokes a kernel grid. for example.

each read. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. In contrast with SIMD vector machines. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. write to that location occurs and they are all serialized. If an atomic instruction executed by a warp reads.0 SIMT architecture is akin to SIMD (Single Instruction. modify. the number of serialized writes that occur to that location and the order in which they occur is undefined. require the software to coalesce loads into vectors and manage divergence manually. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. A key difference is that SIMD vector organizations expose the SIMD width to the software. which is a read-only region of device memory. • The local and global memory spaces are read-write regions of device memory and are not cached. but one of the writes is guaranteed to succeed. on the other hand. the programmer can essentially ignore the SIMT behavior. but the order in which they occur is undefined. scalar threads. which is a read-only region of device memory. whereas SIMT instructions specify the execution and branching behavior of a single thread. In practice. A multiprocessor can execute as many as eight thread blocks concurrently. Vector architectures. SIMT enables programmers to write thread-level parallel code for independent. If there are not enough registers or shared memory available per multiprocessor to process at least one block. modifies. As illustrated by Figure 3. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp.PTX ISA Version 2. however. the kernel will fail to launch. and writes to the same location in global memory for more than one of the threads of the warp. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. 14 January 24. as well as data-parallel code for coordinated threads. 2010 . this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. For the purposes of correctness.

2010 15 . Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.Chapter 3. Figure 3.

0 16 January 24. 2010 .PTX ISA Version 2.

#else. and using // to begin a comment that extends to the end of the current line. 4. Each PTX file must begin with a . 4. See Section 9 for a more information on these directives. Source Format Source files are ASCII text. January 24.1. Comments Comments in PTX follow C/C++ syntax. #endif. The C preprocessor cpp may be used to process PTX source files. Syntax PTX programs are a collection of text source files.Chapter 4.2. PTX is case sensitive and uses lowercase for keywords. followed by a . whitespace is ignored except for its use in separating tokens in the language. All whitespace characters are equivalent. Lines are separated by the newline character (‘\n’). Comments in PTX are treated as whitespace.target directive specifying the target architecture assumed. Lines beginning with # are preprocessor directives. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #if. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. The following are common preprocessor directives: #include.version directive specifying the PTX language version. #ifdef. using non-nested /* and */ for comments that may span multiple lines. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #line. #define. Pseudo-operations specify symbol and addressing management. 2010 17 .

Instructions have an optional guard predicate which controls conditional execution. Examples: . 2.b32 add. The destination operand is first. r2.x. Table 1.global . ld.5.extern .pragma .PTX ISA Version 2. Directive Statements Directive keywords begin with a dot.target .maxntid . Operands may be register variables.0 4.3.1. and is written as @p.tex .2.maxnreg . %tid. and terminated with a semicolon.b32 r1. so no conflict is possible with user-defined identifiers.visible 4. The guard predicate follows the optional label and precedes the opcode. .f32 array[N].loc .3. The guard predicate may be optionally negated. written as @!p. shl. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.reg .b32 r1. followed by source operands. 2010 . or label names. 18 January 24. address expressions.3.section . Statements A PTX statement is either a directive or an instruction. r2. r2.f32 r2.func .minnctapersm . .file PTX Directives .global start: . Instruction keywords are listed in Table 2. All instruction keywords are reserved tokens in PTX. r1.const .local .maxnctapersm . where p is a predicate register.param .shared . Statements begin with an optional label and end with a semicolon.version . array[r1].global. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.b32 r1. constant expressions.entry .sreg .reg .align . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. 0. mov.

Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 . Syntax Table 2.

PTX allows the percentage sign as the first character of an identifier. underscore.4.PTX ISA Version 2. except that the percentage sign is not allowed. e. digits. Table 3. PTX predefines one constant and a small number of special registers that begin with the percentage sign. or dollar characters. underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. %pm3 WARP_SZ 20 January 24. 2010 . listed in Table 3. The percentage sign can be used to avoid name conflicts. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. between user-defined variable names and compiler-generated names. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. digits.0 4. Many high-level languages such as C and C++ follow similar rules for identifier names. …. dollar. or they start with an underscore.g. or percentage character followed by one or more letters.

in which case the literal is unsigned (. To specify IEEE 754 doubleprecision floating point values. floating-point. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Syntax 4. or binary notation.e. These constants may be used in data initialization and as operands to instructions. The syntax follows that of C. the constant begins with 0d or 0D followed by 16 hex digits. 0[fF]{hexdigit}{8} // single-precision floating point January 24.s64) unless the value cannot be fully represented in . 4. hexadecimal.e.s64 or . i.5. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. When used in an instruction or data initialization. where the behavior of the operation depends on the operand types.u64. every integer constant has type . Integer literals may be written in decimal.. 2010 21 . each integer constant is converted to the appropriate size based on the data or instruction type at its use. Constants PTX supports integer and floating-point constants and constant expressions.s64 or the unsigned suffix is specified. and bit-size types.u64). Floating-point literals may be written with an optional decimal point and an optional signed exponent. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. i. For predicate-type data and instructions. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. octal. 4. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.5.2. literals are always represented in 64-bit double-precision format. Type checking rules remain the same for integer. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.. the constant begins with 0f or 0F followed by 8 hex digits.5.1. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Unlike C and C++. zero values are FALSE and non-zero values are TRUE. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.Chapter 4. integer constants are allowed and are interpreted as in C. To specify IEEE 754 single-precision floating point values. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. there is no suffix letter to specify size. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

f64 converted type .s64 .f64 integer integer integer integer integer int ?.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 use usual conversions . .u64 .f64 integer .f64 converted type constant literal + ! ~ Cast Binary (.f64 use usual conversions .s64 .f64 use usual conversions .u64 .u64 .u64 .5.s64.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .u64 .s64 .f64 integer .s64 . Table 5.u64) (.u64 same as 1st operand .s64 . 2010 25 . Syntax 4. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .u64 .u64 1st unchanged.Chapter 4. 2nd is .u64.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 : . or .6.s64) + .f64 same as source .s64 .s64 .

0 26 January 24. 2010 .PTX ISA Version 2.

defined per-thread. Global texture memory (deprecated). 5.tex January 24. Types.1. Kernel parameters. private to each thread. State Spaces A state space is a storage area with particular characteristics.const .sreg . pre-defined. the kinds of resources will be common across platforms.local . Special registers. Global memory.Chapter 5. access speed. Shared. platform-specific. shared by all threads. . and level of sharing between threads. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Local memory.shared . The list of state spaces is shown in Table 4. 2010 27 . Addressable memory shared between threads in 1 CTA. Name State Spaces Description Registers. and these resources are abstracted in PTX through state spaces and data types. Read-only.global . All variables reside in some state space. access rights. and Variables While the specific resources available in a given target GPU will vary. State Spaces.param . fast.reg . addressability. The characteristics of a state space include its size. read-only memory. Table 6. defined per-grid. or Function or local parameters. and properties of state spaces are shown in Table 5.

it is not possible to refer to the address of a register. floating point. 32-. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Device function input parameters may have their address taken via mov. causing changes in performance.sreg . 64-. predicate) or untyped.. Address may be taken via mov instruction. 2010 . and will vary from platform to platform. 2 Accessible via ld.reg . aside from predicate registers which are 1-bit. and performance monitoring registers. CTA.shared .reg state space) are fast storage locations.PTX ISA Version 2. Register State Space Registers (.0 Table 7. Registers may be typed (signed integer. i.const .param (used in functions) . register variables will be spilled to memory.tex Restricted Yes No3 5.global . 5. and cvt instructions. or as elements of vector tuples.sreg) state space holds predefined. and thread parameters. 28 January 24.1. the parameter is then located on the stack frame and its address is in the . All special registers are predefined. and vector registers have a width of 16-. Registers differ from the other state spaces in that they are not fully addressable. The number of registers is limited.1. For each architecture.local state space. 1 Accessible only via the ld.param (as input to kernel) . or 128-bits.param instructions. st.local . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 32-.1. clock counters. scalar registers have a width of 8-. such as grid. The most common use of 8-bit registers is with ld.e. 3 Accessible only via the tex instruction. Register size is restricted. or 64-bits. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. When the limit is exceeded. 16-. unsigned integer.param and st. platform-specific registers. Special Register State Space The special register (. Registers may have alignment boundaries required by multi-word loads and stores.param instruction.2.

Local State Space The local state space (.const[bank] modifier.sync instruction. If another thread sees the variable b change.1. results in const_buffer pointing to the start of constant bank two. the store operation updating a may still be in flight. initialized by the host. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.4.global to access global variables. Threads wait at the barrier until all threads in the CTA have arrived. State Spaces. This reiterates the kind of parallelism available in machines that run PTX. as it must be allocated on a perthread basis. Use ld. Constant State Space The constant (. Global State Space The global (.extern . This pointer can then be used to access the entire 64KB constant bank. [const_buffer+4]. Use ld. and Variables 5.const) state space is a read-only memory. The size is limited. as in lock-free and wait-free style programming. ld. In implementations that support a stack. b = b – 1.b32 const_buffer[]. all addresses are in global memory are shared. Threads must be able to do their work without waiting for other threads to do theirs.const[2] . 5. whereas local memory variables declared January 24. The constant memory is organized into fixed size banks.b32 %r1. // load second word 5. To access data in contant banks 1 through 10.global. where bank ranges from 0 to 10. and atom. Types.5. Sequential consistency is provided by the bar.global. For the current devices. Global memory is not sequentially consistent. For example. Banks are specified using the .global) state space is memory that is accessible by all threads in a context.local to access local variables. It is the mechanism by which different CTAs and different grids can communicate. st. there are eleven 64KB banks. The remaining banks may be used to implement “incomplete” constant arrays (in C.local) is private memory for each thread to keep its own data. If no bank number is given. where the size is not known at compile time.b32 const_buffer[].const[2]. the bank number must be provided in the state space of the load instruction. each pointing to the start address of the specified constant bank.3.extern . bank zero is used. the stack is in local memory. 2010 29 .1.sync instruction are guaranteed to be visible to any reads after the barrier instruction.1.local and st. bank zero is used for all statically-sized constant variables. the declaration . For example. It is typically standard memory with cache. Multiple incomplete array variables declared in the same bank become aliases. For any thread in a context. By convention.Chapter 5. an incomplete array in bank 2 is accessed as follows: . for example). Consider the case where one thread executes the following two assignments: a = a + 1. All memory writes prior to the bar.const[2] . Module-scoped local memory variables are stored at fixed addresses.

ld.b32 N.f64 %d.PTX ISA Version 2.x supports only kernel function parameters in .param space variables.param instructions.b8 buffer[64] ) { . Example: .u32 %ptr. The use of parameter state space for device function parameters is new to PTX ISA version 2. Similarly. These parameters are addressable. … Example: .1.reg . Values passed from the host to the kernel are accessed through these parameter variables using ld. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).1.u32 %n. [%ptr].param . per-kernel versus per-thread). In implementations that do not support a stack. No access protection is provided between parameter and global space in this case.param instructions. PTX code should make no assumptions about the relative locations or ordering of .param space.param) state space is used (1) to pass input arguments from the host to the kernel.entry foo ( .1.param state space and is accessed using ld.0 and requires target architecture sm_20. [N].6. typically for passing large structures by value to a function. %n. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. all local memory variables are stored at fixed addresses and recursive function calls are not supported. len. ld.reg . Parameter State Space The parameter (. mov.u32 %n.param state space. The kernel parameter variables are shared across all CTAs within a grid. For example.entry bar ( .f64 %d. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. 2010 . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.u32 %ptr. [buffer].param .6. Note: The location of parameter space is implementation specific.param . . ld. Therefore. The address of a kernel parameter may be moved into a register using the mov instruction. … 30 January 24. device function parameters were previously restricted to the register state space.param.param.param.b32 len ) { . read-only variables declared in the .u32 %n. 5. (2a) to declare formal input and return parameters for device functions called from within kernel execution.align 8 .0 within a function or kernel body are allocated on the stack. 5. .reg . The resulting address is in the . Note that PTX ISA versions 1. in some implementations kernel parameters reside in global memory.

b8 mystruct.param. [buffer+8]. Function input parameters may be read via ld. mystruct).align 8 . Device Function Parameters PTX ISA version 2. … st.s32 [mystruct+8]. In PTX.reg .b32 N. passed to foo … . January 24.f64 [mystruct+0].param.local and st. } mystruct. and Variables 5. Aside from passing structures by value. a byte array in parameter space is used. the address of a function input parameter may be moved into a register using the mov instruction.Chapter 5. . int y.align 8 .2.param. ld. is flattened. … } // code snippet from the caller // struct { double d. 2010 31 . . It is not possible to use mov to get the address of a return parameter or a locally-scoped . ld. In this case. call foo.param space is also required whenever a formal parameter has its address taken within the called function.f64 dbl. State Spaces. .param formal parameter having the same size and alignment as the passed argument. it is illegal to write to an input parameter or read from a return parameter.reg .f64 %d.param space variable. [buffer].param . .1.b8 buffer[12] ) { .param.param byte array variable that represents a flattened C structure or union. Types. Example: // pass object of type struct { double d. .param . int y.0 extends the use of parameter space to device function parameters.f64 %d. The most common use is for passing objects by value that do not fit within a PTX register.s32 %y. (4. Typically. and so the address will be in the .param.reg . x. Note that the parameter will be copied to the stack if necessary.param and function return parameters may be written using st. st. which declares a . dbl. This will be passed by value to a callee.6.reg .func foo ( . the caller will declare a locally-scoped . }.reg .local state space and is accessed via ld.local instructions. … See the section on function call syntax for more details.s32 %y.s32 x. such as C structures larger than 8 bytes. .

5. Texture memory is read-only.tex . A texture’s base address is assumed to be aligned to a 16-byte boundary. and variables declared in the .tex state space are equivalent to module-scoped . See Section 5.tex .texref.7.texref variables in the . It is shared by all threads in a context.u32 .1. An error is generated if the maximum number of physical resources is exceeded.shared to access shared variables.6 for its use in texture instructions.texref type and Section 8.u32 or . Use ld. Shared State Space The shared (.7. One example is broadcast.u32 . The . Texture State Space (deprecated) The texture (.1. Example: . where texture identifiers are allocated sequentially beginning with zero.tex .texref tex_a.0 5. The . Another is sequential access from sequential threads. An address in shared memory can be read and written by any thread in a CTA. tex_c. tex_d. and programs should instead reference texture memory through variables of type .tex) state space is global memory accessed via the texture instruction. Shared memory typically has some optimizations to support the sharing.tex . tex_f. tex_d. and . 2010 . 32 January 24. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. The texture name must be of type .u64. Multiple names may be bound to the same physical texture identifier. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).global .global state space.u32 tex_a.3 for the description of the .u32 tex_a.shared and st.tex directive will bind the named texture memory variable to a hardware texture identifier. For example.8. a legacy PTX definitions such as . Physical texture resources are allocated on a per-module granularity.shared) state space is a per-CTA region of memory for threads in a CTA to share data. is equivalent to .tex variables are required to be defined in the global scope.u32 .tex directive is retained for backward compatibility.tex . where all threads read from the same address.PTX ISA Version 2.

The following table lists the fundamental type specifiers for each basic type: Table 8. the fundamental types reflect the native data types supported by the target architectures. The same typesize specifiers are used for both variable definitions and for typing instructions. Two fundamental types are compatible if they have the same basic type and are the same size. and converted using regular-width registers. . st. January 24. st.f64 types.2. State Spaces. needed to fully specify instruction behavior. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .s8. or converted to other types and sizes. A fundamental type specifies both a basic type and a size. stored.f32. Types 5. All floating-point instructions operate only on .2.Chapter 5. Operand types and sizes are checked against instruction types for compatibility. so that narrow values may be loaded. stored.2. .s8.f64 .2. and cvt instructions.b64 . .u16. In principle. and .f32 and . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Fundamental Types In PTX.b8. 5. Signed and unsigned integer types are compatible if they have the same size. For convenience. The . .s16.f16 floating-point type is allowed only in conversions to and from .b16. . and Variables 5. and instructions operate on these types.pred Most instructions have one or more type specifiers.b32.f32 and . ld.u32. 2010 33 . .u8.s64 . Register variables are always of a fundamental type.u64 . but typed variables enhance program readability and allow for better operand type checking.b8 instruction types are restricted to ld. so their names are intentionally short. For example. .f64 types.s32. Restricted Use of Sub-Word Sizes The . all variables (aside from predicates) could be declared using only bit-size types.1. . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Types.f16. The bitsize type is compatible with any fundamental type having the same size. . . . .u8.

texture and sampler information is accessed through a single .e. i. accessing the pointer with ld and st instructions. and de-referenced by texture and surface load. and overall size is hidden to a PTX program.3. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. sampler. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. In the independent mode.samplerref.texref handle. PTX has two modes of operation. but all information about layout. Texture. In independent mode the fields of the . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. the resulting pointer may be stored to and loaded from memory.texref.. Sampler. field ordering. store. In the unified mode. and surface descriptor variables.0 5. samplers.PTX ISA Version 2. passed as a parameter to functions.{u32. allowing them to be defined separately and combined at the site of usage in the program. The following tables list the named members of each type for unified and independent texture modes. suld. or performing pointer arithmetic will result in undefined results. sured).samplerref variables. but the pointer cannot otherwise be treated as an address. and query instructions. Referencing textures.surfref. sust. . and Surface Types PTX includes built-in “opaque” types for defining texture. or surfaces via texture and surface load/store instructions (tex. and . suq). These types have named fields similar to structures. base address. 34 January 24. 2010 .u64} reg. since these properties are defined by . Creating pointers to opaque variables using mov. Retrieving the value of a named member via query instructions (txq. For working with textures and samplers.texref type that describe sampler properties are ignored. opaque_var. hence the term “opaque”. The three built-in types are . texture and sampler information each have their own handle.

Chapter 5. clamp_to_border 0. Types. clamp_to_border N/A N/A N/A N/A N/A .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. 1 ignored ignored ignored ignored . 1 nearest.texref values .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.texref values in elements in elements in elements 0. mirror. 2010 35 .samplerref values N/A N/A N/A N/A nearest. clamp_to_edge. clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9. linear wrap. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_ogl. mirror. clamp_to_edge. linear wrap. State Spaces.

.texref tex1. the types may be initialized using a list of static expressions assigning values to the named members. At module scope. filter_mode = nearest }. When declared at module scope.samplerref my_sampler_name. these variables must be in the .texref my_texture_name.global .global . Example: . these variables are declared in the .global . Example: . . 36 January 24.param state space.global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. As kernel parameters.global state space. .global .PTX ISA Version 2.samplerref tsamp1 = { addr_mode_0 = clamp_to_border. 2010 .surfref my_surface_name.

etc. Examples: .s32 i. q. Predicate variables may only be declared in the register state space. . an optional array size.u8 bg[4] = {0.f32 V.f64 is not allowed. r.f32 bias[] = {-1.reg . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . . where the fourth element provides padding.v4 vector. .v4 .f32 accel.shared .global .v4 .global . // a length-4 vector of floats . 0}. and an optional fixed address for the variable. and they may reside in the register space. // a length-4 vector of bytes By default. its name.0}.reg .v2 or . Variables In PTX.1.struct float4 { . . State Spaces. . for example. 0.b8 v. Vectors must be based on a fundamental type. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.global .global . vector variables are aligned to a multiple of their overall size (vector length times base-type size). Examples: . .pred p. PTX supports types for simple aggregate objects such as vectors and arrays. 2010 37 .v2 .2. // typedef .v4. A variable declaration names the space in which the variable resides. a variable declaration describes both the variable’s type and its state space. 0.Chapter 5.const . its type and size. and Variables 5.0. In addition to fundamental types.v3 }. 5.4. Three-element vectors may be handled by using a .u32 loc.4. Variable Declarations All storage for data is specified with variable declarations.struct float4 coord.reg . Types. 1. Vectors Limited-length vector types are supported.global . Vectors cannot exceed 128-bits in length.4. textures.v4 . Every variable must reside in one of the state spaces enumerated in the previous section. January 24.f32 v0. // a length-2 vector of unsigned ints . This is a common case for three-dimensional grids.v2. .v1. an optional initializer. 5.v4.u16 uv.

.u16 kernel[19][19]. The size of the array specifies how many elements should be reserved. this can be used to initialize a jump table to be used with indirect branches or calls.4.05. .05}}. 2010 . label names appearing in initializers represent the address of the next instruction following the label. Array Declarations Array declarations are provided to allow the programmer to reserve space.global . being determined by an array initializer. {0.{.global .0}}. // address of rgba into ptr Currently.05}.v4 . 0}.0}.s32 n = 10.4..pred. {0.. Variable names appearing in initializers represent the address of the variable. Examples: . {0. To declare an array.1. . 1} }. Similarly.0. where the variable name is followed by an equals sign and the initial value or values for the variable.s32 offset[][] = { {-1.1. {1. -1}.global .u8 mailbox[128].05.PTX ISA Version 2. 0}. . For the kernel declaration above..global .4.u8 rgba[3] = {{1.4. Here are some examples: . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.1.global .f16 and .0 5.. 5. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.0.1}. variable initialization is supported only for constant and global state spaces. or is left empty.u32 or . Initializers are allowed for all types except ..3. 19*19 (361) halfwords are reserved (722 bytes).f32 blur_kernel[][] = {{. .shared .local .0. A scalar takes a single value.1.b32 ptr = rgba. this can be used to statically initialize a pointer to a variable. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).0}. . The size of the dimension is either a constant expression. {0. Variables that hold addresses of variables or instructions should be of type .0.1. 38 January 24.{.u64.

b32 %r<100>.. The default alignment for vector variables is to a multiple of the overall vector size. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. . suppose a program uses a large number.0. Rather than require explicit declaration of every name. 2010 39 . Elements are bytes. Examples: // allocate array at 4-byte aligned address. it is quite common for a compiler frontend to generate a large number of register names. For arrays. Parameterized Variable Names Since PTX supports virtual registers.2. State Spaces. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. named %r0. Types. …. The variable will be aligned to an address which is an integer multiple of byte-count.0. and may be preceded by an alignment specifier. of . %r1.b32 variables.0. For example. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.0}. January 24. .const . These 100 register variables can be declared as follows: . not for individual elements. alignment specifies the address alignment for the starting address of the entire array.reg . %r99. nor are initializers permitted.5.0.4. // declare %r0.0. Alignment is specified using an optional .. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. 5. and Variables 5.. Array variables cannot be declared this way. say one hundred.4.6. %r1.Chapter 5.align 4 .b8 bar[8] = {0.align byte-count specifier immediately following the state-space specifier. The default alignment for scalar and array variables is to a multiple of the base-type size.

PTX ISA Version 2.0 40 January 24. 2010 .

Predicate operands are denoted by the names p. . q. 6. as its job is to convert from nearly any data type to any other data type (and size). so operands for ALU instructions must all be in variables declared in the . st. the sizes of the operands must be consistent. The result operand is a scalar or vector variable in the register state space. Most instructions have an optional predicate guard that controls conditional execution. PTX describes a load-store machine. Operand Type Information All operands in instructions have a known type from their declarations.2. 6. and cvt instructions copy data from one location to another. b. and a few instructions have additional predicate source operands. Instruction Operands 6. Each operand type must be compatible with the type determined by the instruction template and instruction type. The cvt (convert) instruction takes a variety of operand types and sizes. January 24. The mov instruction copies data between registers. Source Operands The source operands are denoted in the instruction descriptions by the names a. The ld.3.Chapter 6. 2010 41 . The bit-size type is compatible with every type having the same size. Instructions ld and st move data from/to addressable state spaces to/from registers. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Integer types of a common size are compatible with each other. There is no automatic conversion between types. and c. For most operations. mov. r. s.1.reg register state space. Operands having type different from but compatible with the instruction type are silently cast to the instruction type.

f32 V. arrays. q. W. Using Addresses. [V].u16 ld. [tbl+12]. The address is an offset in the state space in which the variable is declared. .v4 .reg .1. and Vectors Using scalar variables as operands is straightforward. Arrays.0 6. 6. ld.PTX ISA Version 2.4. tbl. Load and store operations move data between registers and locations in addressable state spaces.shared .s32 tbl[256]. The interesting capabilities begin with addresses.4. Examples include pointer arithmetic and pointer comparisons.reg . and vectors. . All addresses and address computations are byte-based.[x]. The mov instruction can be used to move the address of a variable into a pointer.b32 p. r0. and immediate address expressions which evaluate at compile-time to a constant address.global .u16 x. Address expressions include variable names. . there is no support for C-style pointer arithmetic. 2010 . .v4 . .reg .gloal. p. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.reg . Here are a few examples: . .f32 W. The syntax is similar to that used in many assembly languages.s32 q. address registers.s32 mov.u16 r0.const.shared.u32 42 January 24. address register plus byte offset.f32 ld.const .v4.

Vectors may also be passed as arguments to called functions. The size of the array is a constant in the program.v4.global. Rb.g. mov.reg .u32 s. Vectors as Operands Vector operands are supported by a limited subset of instructions. a[N-1].4. for use in an indirect branch or call.b. Array elements can be accessed using an explicitly calculated byte address. and in move instructions to get the address of the label or function into a register.a. . which include mov. Examples are ld. If more complicated indexing is desired.x V. Vector elements can be extracted from the vector with the suffixes . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. or a simple “register with constant offset” expression.z and .r V. V. January 24. The expression within square brackets is either a constant integer.f32 V.w.g V.c. Elements in a brace-enclosed vector.z V. 2010 43 . and the identifier becomes an address constant in the space where the array is declared. // move address of a[1] into s 6. b.y V. ld.w = = = = V.c. [addr+offset].global.a 6.2. .d}.4.u32 {a.y. . The registers in the load/store operations can be a vector. c. . Instruction Operands 6.x.f32 {a.4. Here are examples: ld.v4 . [addr+offset2]. Rc.3. . V2.f32 ld.f32 a. which may improve memory performance. . it must be written as an address calculation prior to use.b V.b. or by indexing into the array using square-bracket notation.reg . a[1].u32 s. Rd}. say {Ra.b and . as well as the typical color fields . st. mov.v2. or a braceenclosed list of similarly typed scalars.v4.4.global. Vector loads and stores can be used to implement wide loads and stores. Arrays as Operands Arrays of all types can be declared. a register variable. a[0]. and tex. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. d.global.u32 s. where the offset is a constant expression that is either added or subtracted from a register variable. A brace-enclosed list is used for pattern matching to pull apart vectors.r. ld.d}.Chapter 6.

5. 2010 . Operands of different sizes or types must be converted prior to the operation. if a cvt. For example.1. except for operations where changing the size and/or type is part of the definition of the instruction. 44 January 24.PTX ISA Version 2. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. and ~131. 6. and data movement instruction must be of the same type and size.s32. Type Conversion All operands to all arithmetic.u16 instruction is given a u16 source operand and s32 as a destination operand. logic. the u16 is zero-extended to s32.0 6.000 for f16).5.

f2u = float-to-unsigned.u32 targeting a 32-bit register will first chop to 16-bits.Chapter 6. January 24. u2f = unsigned-to-float. the result is extended to the destination register width after chopping. 2010 45 . cvt.s16. zext = zero-extend. then sign-extend to 32-bits. chop = keep only low bits that fit. For example. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. The type of extension (sign or zero) is based on the destination format. f2s = float-to-signed. f2f = float-to-float. Notes 1 If the destination register is wider than the destination format. Instruction Operands Table 11. s2f = signed-to-float.

The following tables summarize the rounding modifiers.rpi Integer Rounding Modifiers Description round to nearest integer.PTX ISA Version 2.rz .2.rmi .rn .rm . Modifier . Table 12. Rounding Modifiers Conversion instructions may specify a rounding modifier. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rni . Modifier .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.0 6. there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 .5.rzi . choosing even integer if source is equidistant between two integers. In PTX.

Chapter 6. Another way to hide latency is to issue the load instructions as early as possible. Table 14. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. first access is high Notes January 24. Operand Costs Operands from different state spaces affect the speed of an operation. while global memory is slowest. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Much of the delay to memory can be hidden in a number of ways. 2010 47 . Registers are fastest. Table 11 gives estimates of the costs of using different kinds of memory. The register in a store operation is available much more quickly. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Instruction Operands 6.6.

0 48 January 24.PTX ISA Version 2. 2010 .

and Application Binary Interface (ABI). 2010 49 . At the call. A function declaration specifies an optional list of return parameters. A function must be declared or defined prior to being called. Scalar and vector base-type input and return parameters may be represented simply as register variables. and return values may be placed directly into register variables. Execution of the ret instruction within foo transfers control to the instruction following the call. stack layout. we describe the features of PTX needed to achieve this hiding of the ABI. Function declarations and definitions In PTX. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. The simplest function has no parameters or return values. implicitly saving the return address. so recursion is not yet supported. parameter passing. together these specify the function’s interface. These include syntax for function definitions.func directive. arguments may be register variables or constants. 7. functions are declared and defined using the . NOTE: The current version of PTX does not implement the underlying. January 24. and memory allocated on the stack (“alloca”). A function definition specifies both the interface and the body of the function. execution of the call instruction transfers control to foo. Abstracting the ABI Rather than expose details of a particular calling convention. In this section. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. stack-based ABI.Chapter 7. … Here.func foo { … ret. or prototype. support for variadic functions (“varargs”). function calls.1. the function name. and is represented in PTX as follows: . and an optional list of input parameters. } … call foo.

[y+9].param state space is used to pass the structure by value: . .param. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . The .reg .b8 [py+11]. ld. %rc2.u32 %inc ) { add.reg .b8 [py+ 8].func (.b8 [py+10].f64 f1. st.param space memory.reg . Second.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.reg . note that .c4. 2010 . c4.4).b8 .reg space. %rc2.reg .param.param . … st.b8 . a . [y+0]. a . (%x.b8 c1.c1. For example.align 8 y[12]) { .param. 50 January 24.reg . st.f64 field are aligned. bumpptr. ret.b64 [py+ 0]. [y+11]. py). }.b32 c1. st. (%r1. inc_ptr.param variable y is used in function definition bar to represent a formal parameter. . c3. [y+8].param space call (%out). %inc.reg . consider the following C structure.u32 %res. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .s32 x. // scalar args in . ld.align 8 py[12].b8 [py+ 9].b8 c3. } { . %rc1.f64 f1.c3.s32 out) bar (. In PTX. ld. Since memory accesses are required to be aligned to a multiple of the access size. } … call (%r1).u32 %res) inc_ptr ( . c2.param. this structure will be flattened into a byte array. passed by value to a function: struct { double dbl.param. %ptr. … ld.PTX ISA Version 2.u32 %ptr.param.param.func (.param space variables are used in two ways.c2. st.b8 c4.0 Example: .b8 c2. byte array in .param. … In this example. … … // computation using x. %rd. [y+10].param.f1. First. char c[4].param.param . ld. %rc1. .

reg or . 2.param memory must be aligned to a multiple of 1. • The . 4. . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. In the case of . 8.param variables. January 24. In the case of .param or .reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. the corresponding argument may be either a . or constants. For a caller.param and ld. Abstracting the ABI The following is a conceptual way to think about the .reg space variable with matching type and size. • • • Input and return parameters may be . Typically. or a constant that can be represented in the type of the formal parameter. For a callee. size.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.. Supporting the .g.param space formal parameters that are byte arrays.reg state space in this way provides legacy support. and alignment. size. 2010 51 .param byte array is used to collect together fields of a structure being passed by value. A . • The . For a caller. • • Arguments may be . • • • For a callee.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg space formal parameters. Parameters in . or a constant that can be represented in the type of the formal parameter. or 16 bytes. The .reg space variable of matching type and size.reg variables.reg state space can be used to receive and return base-type scalar and vector values.param instructions used for argument passing must be contained in the basic block with the call instruction. the corresponding argument may be either a . and alignment of parameters. the argument must also be a .param state space use in device functions.param state space is used to receive parameter values and/or pass return values back to the caller.Chapter 7. This enables backend optimization and ensures that the .param space formal parameters that are base-type scalar or vector variables.param arguments. Note that the choice of .param variables or . The following restrictions apply to parameter passing.param space byte array with matching type. The . all st.param or . In the case of . a .param argument must be declared within the local scope of the caller. For .

param space parameters support arrays. formal parameters may be in either .0 continues to support multiple return registers for sm_1x targets. 2010 . In PTX ISA version 2.param state space. and .0 restricts functions to a single return value. formal parameters were restricted to . PTX 2. and there was no support for array parameters. For sm_2x targets. PTX 2.0.reg or . Objects such as C structures were flattened and passed or returned using multiple registers.reg state space.x supports multiple return values for this purpose.x In PTX ISA version 1. and a .param byte array should be used to return objects that do not fit into a register. 52 January 24.1.1. Changes from PTX 1.0 7.x.PTX ISA Version 2. PTX 1.

or 8 bytes. Once all arguments have been processed.Chapter 7.reg . .func baz ( .func (. (3. maxN.u32 ptr. along with the size and alignment of the next data value to be accessed. . call (ap).reg . 4.u32 sz.s32 val. ctr.func okay ( … ) Built-in functions are provided to initialize.u32 sz. (ap. %r1. following zero or more fixed parameters: .reg .func (.u32 ap. val.b32 val) %va_arg (.reg . iteratively access.u32 align) . … %va_start returns Loop: @p Done: January 24. . 4.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 ptr) %va_start .h headers in C. 8. %va_start.u32 align) . Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . %s2).u32 b. setp. the alignment may be 1.u32 ptr. For %va_arg. mov. In PTX. 0. %r3). The function prototypes are defined as follows: . (2. and end access to a list of variable arguments. 2.reg .ge p.b32 result. or 16 bytes. 4. .reg . maxN. 2. 2010 53 .b64 val) %va_arg64 (. (ap). Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg .reg . . … call (%max). In both cases. ) { .u32 a.reg .reg .reg . This handle is then passed to the %va_arg and %va_arg64 built-in functions. 0x8000000. .s32 result ) maxN ( . variadic functions are declared with an ellipsis at the end of the input parameter list. .. for %va_arg64. Abstracting the ABI 7. %r2. PTX provides a high-level mechanism similar to the one provided by the stdarg.reg .reg . … ) . max. %s1. .pred p. // default to MININT mov. %va_arg. the size may be 1. } … call (%max). ret.reg . To support functions with a variable number of arguments. result. bra Done.2.reg . 2. %va_end is called to free the variable argument list handle.func (.u32 N.h and varargs.s32 result. bra Loop.. the size may be 1.func %va_end (. call (val). 4). ctr. or 4 bytes. call %va_end.b32 ctr.u32. N.func ( .reg .

0 7. If a particular alignment is required.PTX ISA Version 2. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.local and st. The array is then accessed with ld.reg . 54 January 24. Alloca NOTE: The current version of PTX does not support alloca.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.reg . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.3.func ( .local instructions. defined as follows: . 2010 .u32 ptr ) %alloca ( . To allocate memory. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. a function simply calls the built-in function %alloca.

Chapter 8. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. Instruction Set 8. In addition to the name and the format of the instruction.lt p|q. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. q = !(a < b). For some instructions the destination operand is optional. A. a. b. The setp instruction writes two destination registers. B. C. opcode D. B. January 24. opcode D. setp. 2010 55 . the D operand is the destination operand. 8. followed by some examples that attempt to show several possible instantiations of the instruction.2. opcode D. For instructions that create a result value. We use a ‘|’ symbol to separate multiple destination registers. // p = (a < b). A. opcode A. and C are the source operands. A.s32. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. B. the semantics are described.1. PTX Instructions PTX instructions generally have from zero to four operands. while A.

lt.0 8.s32 p. 2010 .pred as the type specifier. q. j. i. add.s32 j. optionally negated. // p = (i < n) // if i < n. To implement the above example as a true conditional branch. predicate registers are virtual and have . bra L1. This can be written in PTX as @p setp.reg . add. consider the high-level code if (i < n) j = j + 1. n.pred p. Predicated Execution In PTX.s32 j.PTX ISA Version 2. Instructions without a guard predicate are executed unconditionally. predicate registers can be declared as . Predicates are most commonly set as the result of a comparison performed by the setp instruction. n. where p is a predicate variable. 1.3. 1. So. j. add 1 to j To get a conditional branch or conditional function call. As an example. branch over 56 January 24. i. use a predicate to control the execution of the branch or call instructions.lt. … // compare i to n // if false.s32 p. the following PTX instruction sequence might be used: @!p L1: setp. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.

Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.Chapter 8. hi (higher). ne (not-equal). le (less-than-or-equal). and hs (higher-or-same). ne.1. ne. 2010 57 .1.3. ls (lower-or-same). Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. gt (greater-than). Comparisons 8. le. Table 15. and bitsize types. If either operand is NaN. The unsigned comparisons are eq.1. Unsigned Integer. ordering comparisons are not defined for bit-size types. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). unsigned integer. gt. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.3.1. The following table shows the operators for signed integer. lo (lower). The bit-size comparisons are eq and ne. lt.2. lt (less-than). ge. the result is false. and ge (greater-than-or-equal). Instruction Set 8. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. Table 16.3.

gtu.2. Table 17. then the result of these comparisons is true. 2010 . Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. num returns true if both operands are numeric values (not NaN). and no direct way to load or store predicate register values. Table 18. then these comparisons have the same result as their ordered counterparts. There is no direct conversion between predicates and integer values. not. for example: selp.3.PTX ISA Version 2. and mov.%p. However.0. ltu. setp can be used to generate a predicate from an integer. two operators num (numeric) and nan (isNaN) are provided. or.0 To aid comparison operations in the presence of NaN values. neu.1. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. If both operands are numeric values (not NaN). // convert predicate to 32-bit value 58 January 24. xor. unordered versions are included: equ. leu. geu. If either operand is NaN.u32 %r1. and nan returns true if either operand is NaN. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.

reg . Instruction Set 8. and integer operands are silently cast to the instruction type if needed. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.bX . For example.fX ok ok ok ok January 24.fX ok inv inv ok Instruction Type . different sizes).. i. and these are placed in the same order as the operands. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 a.sX . For example.4. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. Signed and unsigned integer types agree provided they have the same size. and this information must be specified as a suffix to the opcode.f32 d.u16 d. b.Chapter 8.reg . Example: . Floating-point types agree only if they have the same size. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.f32. Type Checking Rules Operand Type . It requires separate type-size modifiers for the result and source. cvt. a.reg .u16 d.uX . add. 2010 59 . unsigned. they must match exactly. a. For example: . b. float. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Table 19.e. • The following table summarizes these type checking rules.uX ok ok ok inv . the add instruction requires type and size information to properly perform the addition operation (signed. .sX ok ok ok inv .bX .u16 d. most notably the data conversion instruction cvt. a.

Floating-point source registers can only be used with bit-size or floating-point instruction types. the size must match exactly. When used with a narrower bit-size type. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. stored. and converted using regular-width registers. 4. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. inv = invalid.1.PTX ISA Version 2. Source register size must be of equal or greater size than the instruction-type size. so those rows are invalid for cvt. stored. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. floating-point instruction types still require that the operand type-size matches exactly. When a source operand has a size that exceeds the instruction-type size. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Table 20.bX instruction types. Note that some combinations may still be invalid for a particular instruction. or converted to other types and sizes. parse error. the data will be truncated. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. the cvt instruction does not support . For example. so that narrow values may be loaded. When used with a floating-point instruction type. “-“ = allowed. Notes 3. for example. Bit-size source registers may be used with any appropriately-sized instruction type.0 8. unless the operand is of bit-size type. Operand Size Exceeding Instruction-Type Size For convenience. ld. The following table summarizes the relaxed type-checking rules for source operands. 2. 2010 . Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. The data is truncated to the instruction-type size and interpreted according to the instruction type. st. no conversion needed. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.4. 60 January 24. 1.

and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. otherwise. inv = Invalid. Notes 3. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the data is sign-extended. and is zero-extended to the destination register width otherwise. Instruction Set When a destination operand has a size that exceeds the instruction-type size. 2010 61 . parse error. Table 21.Chapter 8.or sign-extended to the size of the destination register. zext = zero-extend. The data is sign-extended to the destination register width for signed integer instruction types. 1. If the corresponding instruction type is signed integer. January 24. Destination register size must be of equal or greater size than the instruction-type size. 2. the data will be zero-extended. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. “-“ = Allowed but no conversion needed. the size must match exactly. the destination data is zero. the data is zeroextended. Bit-size destination registers may be used with any appropriately-sized instruction type. The following table summarizes the relaxed type-checking rules for destination operands. The data is signextended to the destination register width for signed integer instruction types. 4. When used with a narrower bit-size instruction type. When used with a floatingpoint instruction type.

the semantics of 16-bit instructions in PTX is machine-specific. the threads are called uniform. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. When executing on a 32-bit data path.PTX ISA Version 2.uni suffix. Both situations occur often in programs.6. a compiler or code author targeting PTX can ignore the issue of divergent threads. the optimizing code generator automatically determines points of re-convergence. until C is not expressive enough. Therefore. at least in appearance. At the PTX language level. by a right-shift instruction. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. using the . so it is important to have divergent threads re-converge as soon as possible. 8. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 62 January 24.5. 8. If threads execute down different control flow paths. conditional function call. and for many applications the difference in execution is preferable to limiting performance. A compiler or programmer may chose to enforce portable. 2010 . The semantics are described using C. until they come to a conditional control construct such as a conditional branch. These extra precision bits can become visible at the application level. However. this is not desirable. Divergence of Threads in Control Constructs Threads in a CTA execute together. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. or conditional return. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers.0 8.6. For divergent control flow. for example. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. for many performance-critical applications. and 16-bit computations are “promoted” to 32-bit computations. 16-bit registers in PTX are mapped to 32-bit physical registers.1. If all of the threads act in unison and follow a single control flow path. the threads are called divergent. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent.

Instructions All PTX instructions may be predicated. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.1.7. In the following descriptions.cc.Chapter 8. Instruction Set 8. The Integer arithmetic instructions are: add sub add. 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.7. addc sub. 2010 63 .cc. the optional guard predicate is omitted from the syntax.

s32 d.sat}. a. 2010 .1. Applies only to .s32 type. .u32 x.u16. a. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. Supported on all target architectures.sat}.s32 c.s16. d = a + b.b. @p add.y.sat applies only to . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.s32 . add Syntax Integer Arithmetic Instructions: add Add two values. . Supported on all target architectures.s16. . d. sub.s32 d. d = a – b. add. // .PTX ISA Version 2.MAXINT (no overflow) for the size of the operation.z.s32 c. d.. . add.u32.s64 }.a. . Saturation modifier: .s64 }.c. Description Semantics Notes Performs addition and writes the resulting value into a destination register..type add{.type sub{.0.sat. Introduced in PTX ISA version 1. Saturation modifier: .MAXINT (no overflow) for the size of the operation.sat applies only to . a. sub. b. .0 Table 22.type = { .s32 type.s32.u32.u64.0.sat limits result to MININT.u16. b. .sat limits result to MININT. . Applies only to .s32 .s32. . b. b.u64. // . Introduced in PTX ISA version 1. . PTX ISA Notes Target ISA Notes Examples Table 23. a. PTX ISA Notes Target ISA Notes Examples 64 January 24.type = { .

type d.y3.CF No integer rounding modifiers.y1. x3. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. x4. or testing the condition code.cc. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc Add two values with carry-out. clearing.cc. Introduced in PTX ISA version 1.b32 addc.z2. a. Table 24.type = {.cc}. No saturation. x3. d = a + b. Supported on all target architectures.cc.cc specified.CF. . No other instructions access the condition code. b. Instruction Set Instructions add. .type d.y2. Supported on all target architectures.CF) holding carry-in/carry-out or borrowin/borrow-out. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.cc.cc. add.cc.u32.y1. These instructions support extended-precision integer addition and subtraction.z3. sub. and there is no support for setting. a. Behavior is the same for unsigned and signed integers.2. . addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. b.z4. x2.b32 addc.cc.u32. carry-out written to CC.cc.b32 x1. d = a + b + CC.b32 addc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. carry-out written to CC. Introduced in PTX ISA version 1.y4.2. if .z4.cc. @p @p @p @p add.z2.z3. x4.cc. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers. .cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. x2.y3.type = { . addc. @p @p @p @p add. add.b32 addc.s32 }. 2010 65 .z1.s32 }.y4.b32 addc.cc Syntax Integer Arithmetic Instructions: add. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. No saturation.z1.Chapter 8.b32 addc.b32 x1. addc{.y2.

y2.z1.y4. sub.PTX ISA Version 2.b32 subc. x3.type d. borrow-out written to CC.3.s32 }. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y2.z4.type = {. b.cc. borrow-out written to CC.CF No integer rounding modifiers.cc Syntax Integer Arithmetic Instructions: sub. a. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.u32.type d. .s32 }.cc.b32 subc.(b + CC.cc Subract one value from another.cc.y1. Introduced in PTX ISA version 1.CF No integer rounding modifiers.z3. with borrow-out.0 Table 26.cc. 2010 . @p @p @p @p sub. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.CF).cc.z1. x4.y3.b32 subc. a. No saturation.b32 x1.y4. Supported on all target architectures.cc}. No saturation. x2.b32 subc.cc specified.3. @p @p @p @p sub.cc. . x2. sub. d = a . x3.type = { . Supported on all target architectures.b32 x1.y3.y1.z3.b32 subc. .z2. Behavior is the same for unsigned and signed integers.z4. Behavior is the same for unsigned and signed integers. withborrow-in and optional borrow-out. subc{.b32 subc. x4. Introduced in PTX ISA version 1.cc. if . b. .cc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. d = a – b.u32.z2.cc.

mul..wide.0>. mul. and either the upper or lower half of the result is written to the destination register. .u64. . d = t<n-1. save only the low 16 bits // 32*32 bits.fxs.wide is specified.. . 2010 67 . // for . mul. d = t<2n-1.s16.s16 fa.hi or .and 32-bit integer types. . The .. a. d = t. Instruction Set Table 28.type = { .s32 z.u32. .wide suffix is supported only for 16. mul{.y.s16 fa. // 16*16 bits yields 32 bits // 16*16 bits. b. then d is the same size as a and b. creates 64 bit result January 24.hi variant // for .lo is specified.type d. n = bitwidth of type.n>.x.0.u16. If .fys. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s64 }. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.lo. Description Semantics Compute the product of two values.wide // for . t = a * b. then d is twice as wide as a and b to receive the full result of the multiplication.lo.lo variant Notes The type of the operation represents the types of the a and b operands.hi. Supported on all target architectures..wide}.Chapter 8.wide.fys. . If .fxs.s32.

wide}.u16. then d and c are twice as wide as a and b to receive the result of the multiplication. c. and then writes the resulting value into a destination register.0 Table 29.b. The .0.n> + c.lo variant Notes The type of the operation represents the types of the a and b operands.hi variant // for . Supported on all target architectures.s32 d. // for . Saturation modifier: .type = { .sat limits result to MININT. d. a.lo.and 32-bit integer types.p.PTX ISA Version 2.s16.hi.s32. mad{. .0> + c. bitwidth of type.wide is specified.MAXINT (no overflow) for the size of the operation. . mad.type mad. b.hi or . then d and c are the same size as a and b. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.wide suffix is supported only for 16. t<2n-1. t + c.. t<n-1..lo. Applies only to ..u64. c..s64 }.hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Description Semantics Multiplies two values and adds a third.a. 2010 . and either the upper or lower half of the result is written to the destination register. . @p mad. t n d d d = = = = = a * b. b.s32 r.s32 type in .lo is specified. 68 January 24. a.s32 d. . .wide // for .. .lo.q.r.u32. If . If .hi mode.sat.c.

s32 }. // for .lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.u32. d = t<31. Supported on all target architectures.b.. a. b.hi may be less efficient on machines without hardware support for 24-bit multiply. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24. 48bits.e. Instruction Set Table 30. mul24{.. All operands are of the same type and size.0>.hi variant // for . .type = { . . i. mul24.type d. mul24. 2010 69 .0..hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. // low 32-bits of 24x24-bit signed multiply. mul24. and return either the high or low 32-bits of the 48-bit result.s32 d. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.lo.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.a.16>. t = a * b.lo}. January 24. d = t<47.Chapter 8.hi.

48bits..s32 type in .type mad24. 32-bit value to either the high or low 32-bits of the 48-bit result.a. mad24. a. Description Compute the product of two 24-bit integer values held in 32-bit source registers.u32.hi may be less efficient on machines without hardware support for 24-bit multiply.sat. a.b.hi mode.MAXINT (no overflow).lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. mad24.. t = a * b.0> + c.hi. b. Saturation modifier: . Supported on all target architectures. mad24{.lo}.0. All operands are of the same type and size. b..s32 d. c. d = t<47. d. .sat limits result of 32-bit signed addition to MININT. Return either the high or low 32-bits of the 48-bit result. // low 32-bits of 24x24-bit signed multiply. mad24.PTX ISA Version 2.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. c.lo. 2010 .s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.c. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. 70 January 24. d = t<31.hi variant // for .s32 }. . i. Applies only to . and add a third.0 Table 31. // for .. mad24.type = { .16> + c.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.hi.e.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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type = { .u32 PTX ISA Notes Target ISA Notes Examples Table 40. // cnt is . Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. a. } Introduced in PTX ISA version 2. For .u32 Semantics 74 January 24. . a. a = a >> 1. cnt. clz.type d. a.b64 d. mask = 0x8000000000000000. X. clz.b32.type d.b32 type.PTX ISA Version 2.b32 popc. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. inclusively. // cnt is .0 Table 39.0. mask = 0x80000000. a = a << 1. } while (d < max && (a&mask == 0) ) { d++. d = 0. d = 0. while (a != 0) { if (a&0x1) d++.0. popc requires sm_20 or later.b64 d.b32) { max = 32.b64 }. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. } else { max = 64. cnt. a. 2010 . clz requires sm_20 or later. inclusively. popc. the number of leading zeros is between 0 and 64.b64 type. if (.type == .b32 clz. For . the number of leading zeros is between 0 and 32. . popc Syntax Integer Arithmetic Instructions: popc Population count. X. .b64 }.b32. popc. .type = { .

d. Description Find the bit position of the most significant non-sign bit in a and place the result in d.u32 January 24. Instruction Set Table 41.type d. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.shiftamt.0.shiftamt. i>=0.d. 2010 75 . i--) { if (a & (1<<i)) { d = i.s32) ? 31 : 63. Operand a has the instruction type. // cnt is . Semantics msb = (.shiftamt is specified. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.shiftamt && d != -1) { d = msb .s64 }.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. d = -1. X. a. . for (i=msb. For signed integers.u32 || . bfind returns 0xFFFFFFFF if no non-sign bit is found.s32. If . For unsigned integers.u64.type==.u32 d. . break. bfind returns the bit position of the most significant “1”.type bfind.u32.type = { . bfind. . and operand d has type . } } if (. a. bfind. a. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. bfind.type==. bfind requires sm_20 or later.s64 cnt.u32. .

brev requires sm_20 or later. for (i=0.b32.type d. 76 January 24. i<=msb. .type==. i++) { d[i] = a[msb-i].type = { .PTX ISA Version 2. 2010 .b32) ? 31 : 63. msb = (. a.0 Table 42. brev. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. Description Semantics Perform bitwise reversal of input. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. brev. .b64 }. a.b32 d.0.

. i<=msb.len. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.start. for (i=0. The sign bit of the extracted field is defined as: . Description Extract bit field from a and place the zero or sign-extended result in d.u32. 2010 77 . d = 0.type==.s32) ? 31 : 63.s64 }. Source b gives the bit field starting bit position.u32 || .a. bfe requires sm_20 or later.type==.u32 || . else sbit = a[min(pos+len-1. .b32 d.type = { . pos = b. the result is zero. . the destination d is filled with the replicated sign bit of the extracted field.u32. January 24. . and operands b and c are type . Instruction Set Table 43.u64: .type==.s32. otherwise If the bit field length is zero.u64. bfe. len = c. Semantics msb = (. Operands a and d have the same type as the instruction type. bfe. b. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. and source c gives the bit field length in bits.u32.type d. If the start position is beyond the msb of the input. .u64 || len==0) sbit = 0.type==.s32. The destination d is padded with the sign bit of the extracted field. if (.Chapter 8. c.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.msb)]. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. .0. a.

2010 . b. the result is b.b32) ? 31 : 63.0 Table 44. . c. and f have the same type as the instruction type. Semantics msb = (. for (i=0. and place the result in f. a. d. If the bit field length is zero.b64 }.type = { . pos = c. i++) { f[pos+i] = a[i]. Operands a.a.start.u32.b. the result is b. . bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.b32 d. bfi. bfi. 78 January 24. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. i<len && pos+i<=msb. b. Source c gives the starting bit position for the insertion. bfi requires sm_20 or later.0.len. If the start position is beyond the msb of the input. f = b.PTX ISA Version 2. Description Align and insert a bit field from a into b. len = d. and source d gives the bit field length in bits.type==. and operands c and d are type .type f.

b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. b1. the permute control consists of four 4-bit selection values. c.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. For each byte in the target register. b2. msb=0 means copy the literal value. {b3. prmt. .b1 source select c[7:4] d.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. as a 16b permute code. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.mode} d.ecl.Chapter 8.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. b6. Thus. 2010 79 . The msb defines if the byte value should be copied. . b4}.rc8. . and reassemble them into a 32-bit destination register. msb=1 means replicate the sign. . the four 4-bit values fully specify an arbitrary byte permute. a.b32{. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).mode = { .b4e.b2 source select c[11:8] d.b3 source select c[15:12] d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.rc16 }. Note that the sign extension is only performed as part of generic form. a 4-bit selection value is defined. The bytes in the two source registers are numbered from 0 to 7: {b. default mode index d. Instruction Set Table 45. b0}}. b. . In the generic form (no mode specified). . The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b5. Description Pick four arbitrary bytes from two 32-bit registers.ecr.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. a} = {{b7.f4e.

tmp64 ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[2]. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ). tmp64 ).b32 prmt. tmp[23:16] = ReadByte( mode. r3.f4e r1.b32.0 Semantics tmp64 = (b<<32) | a. r3. prmt requires sm_20 or later. ctl[0]. tmp[31:24] = ReadByte( mode. r4. r2. ctl[2] = (c >> 8) & 0xf. r4. ctl[3] = (c >> 12) & 0xf. ctl[1]. 80 January 24. } tmp[07:00] = ReadByte( mode. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.PTX ISA Version 2. ctl[3]. r1.0. ctl[1] = (c >> 4) & 0xf. 2010 . r2. tmp[15:08] = ReadByte( mode. tmp64 ). prmt.

7. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2.f32 and .f64 register operands and constant immediate values. Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on .Chapter 8. 2010 81 .

so PTX programs should not rely on the specific single-precision NaNs being generated.0 The following table summarizes floating-point instructions in PTX.fma}.rm .f32 {add.approx.full.min. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. Double-precision instructions support subnormal inputs and results.f64 {abs.ex2}.rn .f64 mad. mul.target sm_20 mad.rcp. {mad.f32 {div.rcp.32 and fma.f32 {div. {add.sqrt}.mul}. but single-precision instructions return an unspecified NaN. .rn and instructions may be folded into a multiply-add.rnd.sub. Instruction Summary of Floating-Point Instructions .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.target sm_1x No rounding modifier.cos.max}.sub. default is . sub. Table 46.f32 .f64 are the same. default is .max}.neg.min.f32 {mad.f32 rsqrt.approx.0].rn and instructions may be folded into a multiply-add.f32 are the same.rnd.f64 {sin.approx. with NaNs being flushed to positive zero.rp .rnd.mul}.0. The optional . .neg.rz . 2010 .sqrt}.sqrt}. 1.PTX ISA Version 2.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. NaN payloads are supported for double-precision instructions.f64 and fma.lg2.rnd.approx. 82 January 24.fma}.f32 {div.f32 {abs.f64 rsqrt. Note that future implementations may support NaN payloads for single-precision instructions.ftz . If no rounding modifier is specified. No rounding modifier. and mad support saturation of results to the range [0. Single-precision add.sat Notes If no rounding modifier is specified.rnd.rcp.f64 div.rnd.target sm_20 .

X.infinite testp. testp. B.f64 }.type d. . true if the input is a subnormal number (not NaN.op. January 24.notanumber.f32. 2010 83 . Introduced in PTX ISA version 2.pred = { . Table 48. z.notanumber.f32 testp.type = { . C. copysign requires sm_20 or later. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. not infinity) As a special case. not infinity). copysign. positive and negative zero are considered normal numbers.infinite.number. a.type . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. A.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. . y. . .type = { .subnormal }. b. .f32 copysign.Chapter 8.op p.notanumber testp.finite testp.number testp. testp Syntax Floating-Point Instructions: testp Test floating-point property.f64 isnan. f0.normal. testp.f64 x.0. . a. testp.normal testp.f32.0. p. and return the result as d.infinite.finite. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. . . testp requires sm_20 or later. // result is . copysign. Instruction Set Table 47. .f64 }. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.

b. 1.rn.f32. Rounding modifiers (default is .f32 add{. d = a + b. .f2. subnormal numbers are supported. add{. a.f32 f1. add. 84 January 24. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64.rz.ftz}{. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. . Rounding modifiers have the following target requirements: .rnd}.rn. requires sm_13 for add.0]. 2010 .rz available for all targets . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64 supports subnormal numbers.f32 clamps the result to [0. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. Saturation modifier: .0.f64 d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. add.0f. requires sm_20 Examples @p add.0 Table 49. add Syntax Floating-Point Instructions: add Add two values.rz.rm mantissa LSB rounds towards negative infinity .ftz.rnd}{.f32 supported on all target architectures. b.sat.rn): .rm. In particular.f32 flushes subnormal inputs and results to sign-preserving zero.sat}.rz mantissa LSB rounds towards zero .rm. d. add. . . NaN results are flushed to +0.rnd = { .rn mantissa LSB rounds to nearest even .PTX ISA Version 2. add. sm_1x: add.rp }. . add. a.rp for add. .f64 requires sm_13 or later. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 flushes subnormal inputs and results to sign-preserving zero.0.f3.

a.f32.rnd}{.rm.f32 f1.rn mantissa LSB rounds to nearest even .Chapter 8. a. January 24.rn): . Saturation modifier: sub.f32 supported on all target architectures.f32 sub{. b.rn. d = a .rz.0.rn.f64 d. requires sm_13 for sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub.f32 clamps the result to [0. 2010 85 . .sat}.f64 supports subnormal numbers.f64 requires sm_13 or later. subnormal numbers are supported. sub.rm.0].0f. NaN results are flushed to +0.rnd = { . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.a.f32 c. sub{. requires sm_20 Examples sub. sub.0. . .rm mantissa LSB rounds towards negative infinity .b.f2.rp for sub. Rounding modifiers have the following target requirements: .ftz.ftz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.sat.rp }. .f64. 1.rn. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f3. d.ftz}{. sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another. . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. sub.rz available for all targets .rnd}. sm_1x: sub. Rounding modifiers (default is . Instruction Set Table 50.rz mantissa LSB rounds towards zero .b.f32 flushes subnormal inputs and results to sign-preserving zero. In particular. b. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. .

rm mantissa LSB rounds towards negative infinity . Saturation modifier: mul. mul. d = a * b.rn.rp for mul. 2010 .rnd}.rz mantissa LSB rounds towards zero . mul. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rz available for all targets . .ftz. . mul. sm_1x: mul.0f. 1.rz. b. b.f64 d. Rounding modifiers (default is . For floating-point multiplication. .f64 requires sm_13 or later. mul{. mul Syntax Floating-Point Instructions: mul Multiply two values. mul.rn.rm.rp }. Rounding modifiers have the following target requirements: . a.ftz}{.0 Table 51. requires sm_13 for mul. all operands must be the same size.radius.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.PTX ISA Version 2. In particular.sat}. requires sm_20 Examples mul.f32 clamps the result to [0. a.pi // a single-precision multiply 86 January 24.f32.rn): . .0]. d.0.rnd}{.f32 circumf. .f32 supported on all target architectures.f64.ftz. Description Semantics Notes Compute the product of two values.0.rn mantissa LSB rounds to nearest even .f32 mul{. .f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero.sat. NaN results are flushed to +0. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. subnormal numbers are supported.rm.

rp }.c.sat. fma.ftz.0. .f64 introduced in PTX ISA version 1.0. fma.rnd.rm.rn.rz mantissa LSB rounds towards zero . Saturation: fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add.f64 d. .f32 is unimplemented in sm_1x. . sm_1x: fma. a.0f. fma. a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. @p fma.f32 requires sm_20 or later. again in infinite precision. d = a*b + c.f32 computes the product of a and b to infinite precision and then adds c to this product.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 clamps the result to [0.f64.f64 requires sm_13 or later. again in infinite precision.rnd = { . The resulting value is then rounded to double precision using the rounding mode specified by . c. b.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.x. subnormal numbers are supported.f32 fma.f32 introduced in PTX ISA version 2. d. fma.sat}. c. fma.b.f64 is the same as mad. NaN results are flushed to +0.0]. .f32 fma.f64 w.rn.rn mantissa LSB rounds to nearest even .Chapter 8.rnd{.rnd.rn. fma. fma.rm mantissa LSB rounds towards negative infinity . fma.z. b.a.4. 1.ftz}{. fma. Instruction Set Table 52.rnd.rz. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. 2010 87 . The resulting value is then rounded to single precision using the rounding mode specified by .y.f64 supports subnormal numbers. fma. d. PTX ISA Notes Target ISA Notes Examples January 24. Rounding modifiers (no default): .

ftz}{. The resulting value is then rounded to double precision using the rounding mode specified by .{f32.f64}. again in infinite precision.ftz. For .rnd.rnd = { . c.f32 is when c = +/-0. NaN results are flushed to +0.target sm_1x: mad. d = a*b + c.ftz}{. 88 January 24. For . The exception for mad.rm mantissa LSB rounds towards negative infinity . mad. mad. b.rnd.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.rn.0 Table 53. When JIT-compiled for SM 2.rp }. c.target sm_1x d. Description Semantics Notes Multiplies two values and adds a third.target sm_20: mad. and then writes the resulting value into a destination register. Note that this is different from computing the product with mul.f32 is implemented as a fused multiply-add (i.rnd. again in infinite precision.f32 flushes subnormal inputs and results to sign-preserving zero. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. Rounding modifiers (no default): .f64. // . The resulting value is then rounded to single precision using the rounding mode specified by . subnormal numbers are supported.f64 computes the product of a and b to infinite precision and then adds c to this product.f32).0].rn mantissa LSB rounds to nearest even . 2010 .f64} is the same as fma. // .f64 is the same as fma. a. . mad. The resulting value is then rounded to double precision using the rounding mode specified by .rz.f32 computes the product of a and b at double precision. sm_1x: mad. but the exponent is preserved.f32 mad. mad.rnd. again in infinite precision. .f32. a.0f. c.f64 computes the product of a and b to infinite precision and then adds c to this product.rm.f32 flushes subnormal inputs and results to sign-preserving zero. and then the mantissa is truncated to 23 bits.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 clamps the result to [0.rz mantissa LSB rounds towards zero . where the mantissa can be rounded and the exponent will be clamped. mad. the treatment of subnormal inputs and output follows IEEE 754 standard. mad. a. b.sat}. Saturation modifier: mad. b.f64 supports subnormal numbers.0 devices. In this case.target sm_20 d. 1. mad.PTX ISA Version 2.f64 d. mad{.rnd{. mad. Unlike mad.{f32.f32 mad. .target sm_13 and later . fma. // .rn.e.sat}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz.0.0. mad.f32 is identical to the result computed using separate mul and add instructions..sat.

rp for mad.f32..rp for mad. In PTX ISA versions 2. a rounding modifier is required for mad.a..c.rz. 2010 89 .4 and later.. In PTX ISA versions 1. requires sm_20 Examples @p mad.rm. Legacy mad.f32 for sm_20 targets..f64.0.f64.rn.rz..f32 supported on all target architectures. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. Target ISA Notes mad.f32 d.rm.rn. requires sm_13 .b.. mad. January 24.Chapter 8.f64 requires sm_13 or later.0 and later. a rounding modifier is required for mad.f64 instructions having no rounding modifier will map to mad.f64.rn. Rounding modifiers have the following target requirements: .

ftz}. b.f64 supports subnormal numbers.rm mantissa LSB rounds towards negative infinity . d = a / b. div.f32 implements a relatively fast. PTX ISA Notes div.f32 and div. .f32 and div.rm.approx.f32 div.approx.f32 div. computed as d = a * (1/b).rm. Examples 90 January 24.{rz. d.rn mantissa LSB rounds to nearest even .f64 defaults to div.approx{. a.full.rn.ftz. x.full.rnd.ftz}. y.3. yd. a. For b in [2-126.f32. b.approx.approx.approx. .0 through 1.rp}.f64 requires sm_13 or later. The maximum ulp error is 2 across the full range of inputs. d. sm_1x: div. b. xd. Fast. div Syntax Floating-Point Instructions: div Divide one value by another.full.full.f32 div. Explicit modifiers . .rp }.approx. full-range approximation that scales operands to achieve better accuracy. and rounding introduced in PTX ISA version 1.rn. Target ISA Notes div.4 and later.f32 defaults to div. Subnormal inputs and results are flushed to sign-preserving zero.ftz. .ftz. one of . and div.4. div. div. or .f64 diam. div. z.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.ftz}. the maximum ulp error is 2.f32 implements a fast approximation to divide. Fast.rnd = { . d. div. Description Semantics Notes Divides a by b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 2126].f32 div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64 introduced in PTX ISA version 1. . 2010 .rnd{. For PTX ISA version 1.f32 div.rnd is required.f64 d.f32 requires sm_20 or later.ftz.rnd.rn.rn. a.f32 flushes subnormal inputs and results to sign-preserving zero. b. approximate single-precision divides: div. zd.full{. // // // // fast. a. subnormal numbers are supported.0 Table 54. .full.rz mantissa LSB rounds towards zero .f64 requires sm_20 or later. div. but is not fully IEEE 754 compliant and does not support rounding modifiers. div.14159. div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . For PTX ISA versions 1. div. stores result in d.0.f32 supported on all target architectures. approximate division by zero creates a value of infinity (with same sign as a).f64.rz.3.circum.PTX ISA Version 2.

neg. Take the absolute value of a and store the result in d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs.f64 requires sm_13 or later. d = |a|. neg. subnormal numbers are supported. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.ftz. abs. subnormal numbers are supported. abs.ftz}. a.f64 d.f64 supports subnormal numbers. sm_1x: abs. a.f32 x.ftz. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. neg.ftz. sm_1x: neg. abs.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. d = -a. neg. Negate the sign of a and store the result in d. NaN inputs yield an unspecified NaN.f32 x.f32 supported on all target architectures. a.f64 supports subnormal numbers.Chapter 8. abs{. neg.ftz. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 neg. abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later. neg{. d. Table 56.f32 abs.f0. a.0.f32 supported on all target architectures. 2010 91 .f32 flushes subnormal inputs and results to sign-preserving zero. NaN inputs yield an unspecified NaN.0.f64 d. Instruction Set Table 55. d.f0. January 24.

d.0. a. max. d d d d = = = = NaN. a. 92 January 24. max. Table 58. max{. b.f64 supports subnormal numbers.f32 supported on all target architectures. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 requires sm_13 or later. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. Store the minimum of a and b in d. sm_1x: max. b. min{. min. b.f64 requires sm_13 or later. max.z. min.x. d d d d = = = = NaN.b.f32 min.f32 min.b.f2. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.f32 max.ftz. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. a.ftz}.c. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.ftz.f1. sm_1x: min. Store the maximum of a and b in d. a.f64 d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 supported on all target architectures.f64 f0. (a < b) ? a : b. d. a. min.ftz}. subnormal numbers are supported. b. @p min.f32 flushes subnormal inputs and results to sign-preserving zero. a. (a > b) ? a : b.ftz. max. b. max.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 57.f32 max. 2010 .f64 z.f32 flushes subnormal inputs and results to sign-preserving zero.c.PTX ISA Version 2.f64 d. min. subnormal numbers are supported. a. a.

d.f32 defaults to rcp.rm. one of . rcp.approx.f64 requires sm_20 or later. Instruction Set Table 59.rp}.rn.approx.ftz. a.ftz.0. Description Semantics Notes Compute 1/a.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 93 .rn mantissa LSB rounds to nearest even .rnd = { .0 through 1. rcp. a.0 +subnormal +Inf NaN Result -0.rm mantissa LSB rounds towards negative infinity . rcp. For PTX ISA versions 1.0.x. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. xi.0 -Inf -Inf +Inf +Inf +0.rn.rn.{rz. and rcp.rm. store result in d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . d = 1 / a.3.approx. rcp. Target ISA Notes rcp. sm_1x: rcp. rcp.f64 defaults to rcp. rcp.f64 ri. . rcp.rnd.rn.approx and .r. Examples January 24. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .4. . xi.f64 d. General rounding modifiers were added in PTX ISA version 2.f64 and explicit modifiers . rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rn.f32 and rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . rcp.ftz were introduced in PTX ISA version 1. // fast.rnd. a.ftz.0. Input -Inf -subnormal -0.approx{. rcp.f64 introduced in PTX ISA version 1. PTX ISA Notes rcp.f32 rcp.approx. rcp.rz.rp }.x.rz mantissa LSB rounds towards zero .f32 implements a fast approximation to reciprocal.rnd{.0-2.f32 requires sm_20 or later.0 +0.ftz.f64.f64 supports subnormal numbers.f32.f64 requires sm_13 or later.approx or .f32 rcp.f32 supported on all target architectures.0 over the range 1.rn.ftz}. d.f32 rcp. For PTX ISA version 1.rnd is required. The maximum absolute error is 2-23.f32 rcp.4 and later.

rn.approx.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .3. sqrt. . sqrt.0.f64 requires sm_20 or later.0 +0.f32 defaults to sqrt.0 +0.rm. a.rn. one of . subnormal numbers are supported.rn.0 through 1. Examples 94 January 24.rnd is required.rz. sqrt.f64 and explicit modifiers . sm_1x: sqrt. 2010 .rn.rz mantissa LSB rounds towards zero .f32 requires sm_20 or later.f32 flushes subnormal inputs and results to sign-preserving zero.approx{. and sqrt.f32 sqrt.rnd{. d = sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero. .approx. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. sqrt.ftz were introduced in PTX ISA version 1.f32 and sqrt. sqrt.f32 supported on all target architectures. . // IEEE 754 compliant rounding . For PTX ISA version 1.f32 is TBD.f64 introduced in PTX ISA version 1.f64. r. General rounding modifiers were added in PTX ISA version 2. // fast.4.0.ftz}.rm.x. Description Semantics Notes Compute sqrt(a). a. approximate square root d.{rz.approx and .rnd.ftz.PTX ISA Version 2.approx.4 and later.0 +0.f64 supports subnormal numbers. PTX ISA Notes sqrt.f64 requires sm_13 or later.rn.rnd = { .approx or . For PTX ISA versions 1.rn. // IEEE 754 compliant rounding d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32. a.x.rnd.f32 sqrt.0 +subnormal +Inf NaN Result NaN NaN -0.approx.ftz}.f64 defaults to sqrt.f32 sqrt.rn mantissa LSB rounds to nearest even . Input -Inf -normal -subnormal -0.f32 sqrt. sqrt.ftz. sqrt.f64 r.f32 implements a fast approximation to square root. sqrt. r.approx.rm mantissa LSB rounds towards negative infinity .ftz. store in d. sqrt.rp }.0 -0.0 Table 60.ftz. sqrt. Target ISA Notes sqrt.rp}. The maximum absolute error for sqrt.f64 d.x.

4 and later.f32 is 2-22. x. Explicit modifiers . Note that rsqrt.f64 is TBD.0 +0.approx. PTX ISA Notes rsqrt.f32 rsqrt.0 through 1. sm_1x: rsqrt. rsqrt.approx implements an approximation to the reciprocal square root. Target ISA Notes Examples rsqrt.f64 supports subnormal numbers. d.approx.ftz were introduced in PTX ISA version 1. For PTX ISA version 1. Instruction Set Table 61. The maximum absolute error for rsqrt.f32 defaults to rsqrt. rsqrt.0. Compute 1/sqrt(a). rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f32 and rsqrt.f32. ISR. rsqrt.f64 is emulated in software and are relatively slow.0.f64.4.ftz}.approx. a. rsqrt. rsqrt.f64 d.3.f64 isr.approx{.f32 supported on all target architectures. 2010 95 .f64 requires sm_13 or later.f64 defaults to rsqrt.approx and .0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.0-4.ftz.0 NaN The maximum absolute error for rsqrt.approx.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. the . rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. a.approx modifier is required. Subnormal numbers: sm_20: By default. store the result in d.approx. Input -Inf -normal -subnormal -0. subnormal numbers are supported. For PTX ISA versions 1. and rsqrt.Chapter 8.approx. January 24.f64 were introduced in PTX ISA version 1.4 over the range 1. d = 1/sqrt(a). rsqrt.ftz.f32 rsqrt. X.

approx{. sin. Target ISA Notes Examples Supported on all target architectures. Subnormal numbers: sm_20: By default. sin.0 through 1.4. Input -Inf -subnormal -0.4 and later.ftz}.0 +0. sin. sin.f32 sa. the .f32 flushes subnormal inputs and results to sign-preserving zero.0 -0.ftz.ftz introduced in PTX ISA version 1.approx and .approx. 96 January 24.9 in quadrant 00. PTX ISA Notes sin.0 Table 62.f32 introduced in PTX ISA version 1. Explicit modifiers .approx modifier is required.0 +0.approx.ftz.f32.f32 implements a fast approximation to sine.0. Find the sine of the angle a (in radians). a.PTX ISA Version 2.0 +0.approx.f32 defaults to sin.0 NaN NaN The maximum absolute error is 2-20. d = sin(a). For PTX ISA versions 1. sm_1x: Subnormal inputs and results to sign-preserving zero. a. subnormal numbers are supported. sin.0 +subnormal +Inf NaN Result NaN -0. 2010 . For PTX ISA version 1.3.f32 d.ftz. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.

f32 flushes subnormal inputs and results to sign-preserving zero.approx modifier is required. 2010 97 . Find the cosine of the angle a (in radians). Input -Inf -subnormal -0. a. a.approx. Explicit modifiers .f32 ca. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. January 24. the .f32 defaults to cos. cos.ftz}. cos.9 in quadrant 00.3.f32 implements a fast approximation to cosine.4. sm_1x: Subnormal inputs and results to sign-preserving zero. cos. cos. For PTX ISA versions 1. d = cos(a).0 +1.Chapter 8. subnormal numbers are supported. Target ISA Notes Examples Supported on all target architectures.0 +1.ftz.0 +subnormal +Inf NaN Result NaN +1. Instruction Set Table 63. Subnormal numbers: sm_20: By default.0 through 1.0.4 and later.approx.0 +0. cos.ftz.f32 introduced in PTX ISA version 1.ftz introduced in PTX ISA version 1. PTX ISA Notes cos.f32 d.0 +1.f32.0 NaN NaN The maximum absolute error is 2-20.ftz.approx.approx and . For PTX ISA version 1.approx{.

4.approx{.0. Target ISA Notes Examples Supported on all target architectures. lg2. lg2. Explicit modifiers . 98 January 24.ftz}. 2010 .0 +0. a. d = log(a) / log(2).ftz.f32 defaults to lg2.4 and later.f32 Determine the log2 of a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Input -Inf -subnormal -0.PTX ISA Version 2.6 for mantissa.f32 la.approx and .ftz. For PTX ISA versions 1. PTX ISA Notes lg2.approx.f32.0 Table 64.f32 implements a fast approximation to log2(a). the .f32 flushes subnormal inputs and results to sign-preserving zero.f32 introduced in PTX ISA version 1.approx. a. lg2.0 through 1. For PTX ISA version 1.ftz introduced in PTX ISA version 1.approx modifier is required. Subnormal numbers: sm_20: By default. subnormal numbers are supported. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. sm_1x: Subnormal inputs and results to sign-preserving zero. lg2.approx.3.ftz. lg2. The maximum absolute error is 2-22.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

u16. setp. le.u32 p|q. gt. b. respectively. leu. hs equ. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. If either operand is NaN. gt. loweror-same. Subnormal numbers: sm_20: By default. lt. p = BoolOp(t. neu. nan The Boolean operator BoolOp(A.u32. .f32 flushes subnormal inputs to sign-preserving zero.f32. or.type . sm_1x: setp. neu. p.0 Table 67. le. then these comparisons have the same result as their ordered counterparts. gtu. c). p[|q]. xor. ne. the result is false. ls. q = BoolOp(!t. lt. This result is written to the first destination operand.b.ftz. ge. lt. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.PTX ISA Version 2. b. ls.s16. num returns true if both operands are numeric values (not NaN). .r.pred variables.s32. {!}c.i.u64. hi. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. num.ftz}. le.CmpOp{. ge. To aid comparison operations in the presence of NaN values. The comparison operator is a suffix on the instruction.ftz}. bit-size comparisons are eq and ne. geu. If both operands are numeric values (not NaN). For unsigned values.CmpOp. and nan returns true if either operand is NaN. ltu. geu.and.type setp. If either operand is NaN. . .dtype. c). and (optionally) combine this result with a predicate value by applying a Boolean operator.a. 2010 .s32 setp. subnormal numbers are supported. gt. 102 January 24. leu. Integer Notes Floating Point Notes The ordered comparisons are eq. gtu. setp.lt. .B) is one of: and. Modifier .f64 supports subnormal numbers. and higher-or-same may be used instead of lt. the comparison operators lo. p[|q]. A related value computed using the complement of the compare result is written to the second destination operand. ge. The destinations p and q must be .ftz applies only to . then the result of these comparisons is true. gt.b16.type = { . ne. higher. a.BoolOp{.b32. ge. hi. . unordered versions are included: equ. Semantics t = (a CmpOp b) ? 1 : 0. ltu.n.b64. Applies to all numeric types. setp with . le. The untyped.dtype.f64 source type requires sm_13 or later. @q setp. . and hs for lower.f64 }. and can be one of: eq.0. ne. a. setp.f32 flushes subnormal inputs to sign-preserving zero. . The signed and unsigned comparison operators are eq. .eq.f32 comparisons. lo.dtype. .s64.

slct.s16. b. y. . a is stored in d.ftz.r.f32. a.s32.s16. Table 69. negative zero equals zero. slct Syntax Comparison and Selection Instructions: slct Select one source operand.Chapter 8. . .b32. slct. based on the sign of the third operand.f32 comparisons. . b otherwise. . fval.ftz applies only to . Modifier .s32 x. . @q selp. d = (c == 1) ? a : b. .f32 flushes subnormal values of operand c to sign-preserving zero.f32.b32.u16. selp Syntax Comparison and Selection Instructions: selp Select between source operands.xp. Instruction Set Table 68.dtype. subnormal numbers are supported. If c is True. val.u64. 2010 103 . slct.f32 flushes subnormal values of operand c to sign-preserving zero. otherwise b is stored in d.f32 comparisons.f64 requires sm_13 or later. .b64. slct. .b64. c. . f0.f64 }. . If operand c is NaN.f32 r0. Subnormal numbers: sm_20: By default.u64.s64.dtype. and operand a is selected. z.s32 selp.t.dtype. For . . a. d = (c >= 0) ? a : b.u32.u16. Operands d.p. .s32 slct{. operand c must match the second instruction type.x. . .b16. The selected input is copied to the output without modification.dtype. C. . the comparison is unordered and operand b is selected.ftz}. selp. . based on the value of the predicate source operand.f64 requires sm_13 or later. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d. c. .type = { .0. Description Conditional selection.ftz. . b. Introduced in PTX ISA version 1. a. a is stored in d.f64 }. and b must be of the same type. Operand c is a predicate.type d.u64. . a.s32. . Semantics Floating Point Notes January 24.f32 d.g.s64. selp. and b are treated as a bitsize type of the same width as the first instruction type. c.f32 A. Operands d.u32.b16. a. sm_1x: slct.dtype = { . B. . and operand a is selected. b.0. slct.u32. If c ≥ 0.

Instructions and.PTX ISA Version 2. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.0 8. 2010 .7. and not also operate on predicates. This permits bit-wise operations on floating point values without having to define a union to access the bits. or. provided the operands are of the same size.4. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. xor. performing bit-wise operations on operands of any type.

January 24. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.q. and. d = a & b.pred. or.0x00010001 or.b64 }. Introduced in PTX ISA version 1.fpvalue.0. and. Supported on all target architectures.pred. Allowed types include predicate registers. 2010 105 . but not necessarily the type. a. Introduced in PTX ISA version 1. The size of the operands must match. .b16.b64 }. d = a | b. . .r.0.b32 mask mask. .0x80000000.pred p.type d. or.b16. b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. and Syntax Logic and Shift Instructions: and Bitwise AND. . Instruction Set Table 70.type d.b32 x.Chapter 8.b32. . b.b32.type = { . sign. Table 71. Supported on all target architectures.r.b32 and.type = { . or Syntax Logic and Shift Instructions: or Bitwise OR. The size of the operands must match.q. a. Allowed types include predicate registers. . but not necessarily the type. .

.q.b16.b16.type d. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.pred p. 106 January 24. but not necessarily the type. but not necessarily the type. a.0 Table 72. . a. .type = { . The size of the operands must match. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).0.type d. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. d = (a==0) ? 1 : 0. .mask.0x0001. xor. The size of the operands must match. but not necessarily the type.PTX ISA Version 2. Introduced in PTX ISA version 1. d. . Supported on all target architectures. . cnot. xor. The size of the operands must match.b64 }.pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. .x.b64 }. Introduced in PTX ISA version 1. cnot.type d. not Syntax Logic and Shift Instructions: not Bitwise negation. a.type = { . d = ~a.b32.0. . Table 73. not. Allowed types include predicates. one’s complement.b32 xor.b32. Table 74. not.b64 }. not.pred. .b32 d. . Supported on all target architectures.b16 d.b32 mask. Supported on all target architectures. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.q.type = { . .b16.0. 2010 .b32.r. b.a. d = a ^ b.

d = a >> b.j. Supported on all target architectures.type d. shl.b64 }.Chapter 8.1. zero-fill on right. . shr. Signed shifts fill with the sign bit. shl. .s16. shl Syntax Logic and Shift Instructions: shl Shift bits left. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.b16 c. shr. .b16. The b operand must be a 32-bit value. PTX ISA Notes Target ISA Notes Examples January 24.s64 }. regardless of the instruction type.u32. .a. The sizes of the destination and first source operand must match. . but not necessarily the type. but not necessarily the type. The sizes of the destination and first source operand must match. . shr Syntax Logic and Shift Instructions: shr Shift bits right.b32 q. Shift amounts greater than the register width N are clamped to N.u16. a. k. sign or zero fill on left.s32. d = a << b.b32.type d. Introduced in PTX ISA version 1. b. unsigned and untyped shifts fill with 0. .b64.0. Shift amounts greater than the register width N are clamped to N. . . regardless of the instruction type.a.type = { . . . Instruction Set Table 75.u16 shr.u64. Supported on all target architectures. a. b.2.b32. i. Bit-size types are included for symmetry with SHL.s32 shr. .type = { .i.i.2. Introduced in PTX ISA version 1. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. PTX ISA Notes Target ISA Notes Examples Table 76.b16. The b operand must be a 32-bit value. 2010 107 .0.

Data Movement and Conversion Instructions These instructions copy data from place to place. or shared state spaces. The cvta instruction converts addresses between generic and global. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and from state space to state space.PTX ISA Version 2. and sust support optional cache operations. ldu.7. ld. 2010 . Instructions ld. prefetchu isspacep cvta cvt 108 January 24. mov. st. and st operate on both scalar and vector types. suld. local.0 8.5. possibly converting it from one format to another. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.

Use ld. likely to be accessed once. Cache Operators PTX 2. The ld. and a second thread loads that address via a second L1 cache with ld. rather than the data stored by the first thread.cv to a frame buffer DRAM address is the same as ld. the second thread may get stale L1 cache data.cs) on global addresses. if the line is fully covered. evict-first. but multiple L1 caches are not coherent for global data.5. not L1). bypassing the L1 cache. As a result of this request. 2010 109 . A ld.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The compiler / programmer may use ld. when applied to a local address. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.lu load last use operation. When ld. . . The ld.lu instruction performs a load cached streaming operation (ld. If one thread stores to global memory via one L1 cache. The cache operators require a target architecture of sm_20 or later. to allow the thread program to poll a SysMem location written by the CPU. . likely to be accessed again.1. Table 77.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.lu operation.0 introduces optional cache operators on load and store instructions.cs. the cache operators have the following definitions and behavior. .cs is applied to a Local window address. any existing cache lines that match the requested address in L1 will be evicted. January 24. The ld. The ld.cg to cache loads only globally. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Operator . Global data is coherent at the L2 level. and cache only in the L2 cache. it performs the ld. invalidates (discards) the local L1 line following the load.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.ca loads cached in L1. fetch again).cg Cache at global level (cache in L2 and below.cv Cache as volatile (consider cached system memory lines stale.ca.Chapter 8. Instruction Set 8.lu Last use.ca. For sm_20 and later. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. The default load instruction cache operation is ld.cs Cache streaming.7.

2010 . bypassing its L1 cache. .cg is the same as st.wb. and a second thread in a different SM later loads from that address via a different L1 cache with ld.wt store write-through operation applied to a global System Memory address writes through the L2 cache. 110 January 24. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wb could write-back global store data from L1. In sm_20. The st.wt Cache write-through (to system memory). but st. Operator . in which case st. not L1). The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wt.cg to local memory uses the L1 cache. which writes back cache lines of coherent cache levels with normal eviction policy. .cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. .wb for global data.ca loads. The st. If one thread stores to global memory. regardless of the cache operation. Addresses not in System Memory use normal write-back. rather than get the data from L2 or memory stored by the first thread. Global stores bypass L1. and cache only in the L2 cache.PTX ISA Version 2. However. bypassing the L1 cache. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. and discard any L1 lines that match.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. to allow a CPU program to poll a SysMem location written by the GPU with st. st.0 Table 78.cg to cache global store data only globally.cg Cache at global level (cache in L2 and below.ca. Use st. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. and marks local L1 lines evict-first. The default store instruction cache operation is st. likely to be accessed once.cs Cache streaming. the second thread may get a hit on stale L1 cache data. Future GPUs may have globally-coherent L1 caches.

u32 d. local.u64.type mov.f64 }. label. mov places the non-generic address of the variable (i. or shared state space.u16 mov. Write register d with the value of a.local. addr. or shared state space may be taken directly using the cvta instruction. d. u.Chapter 8. label. d. .e. Operand a may be a register.b64. .b32.0. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. ptr.const. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.s32. .f32 mov. the generic address of a variable declared in global.type mov. sreg. or function name.1. Introduced in PTX ISA version 1.shared state spaces. local.u32 mov. // get address of variable // get address of label or function . ptr. .s64..global.e. . myFunc. avar. . A[5]. d = &avar. 2010 111 . mov. d. d = &label.v.type d. within the variable’s declared state space Notes Although only predicate and bit-size types are required.type mov.f32.b16. local.pred. Description . a. .0. mov.u32 mov. the parameter will be copied onto the stack and the address will be in the local state space. Note that if the address of a device function parameter is moved to a register.f32 mov. . i. mov.u32.f64 requires sm_13 or later.type = { . // address is non-generic. Instruction Set Table 79. The generic address of a variable in global. For variables declared in . or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. . alternately. variable in an addressable memory space. . Semantics d = a. d = sreg.a. and . k.u16. Take the non-generic address of a variable in global. special register. A. immediate..s16. . the address of the variable in its state space) into the destination register.

.y } = { a[0.x | (a.z.w << 24) d = a.0 Table 80.y << 8) d = a.b64 }.b32. a.15].63] } // unpack 16-bit elements from . mov. a[32. d.{a.x.y << 8) | (a.b16 // pack four 8-bit elements into . d.hi are .z. a[16.u32 x.15].y << 16) d = a.z.y. .w << 48) d = a.. a[48..b64 { d.23]. a[16.15].u16 %x is a double.y. a[24.type d.b64 { d.w } = { a[0. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.y.hi}. .b32 mov.x | (a. mov.y << 16) | (a. 2010 ...x.b64 // pack two 32-bit elements into . d.z << 32) | (a.b32 // pack two 16-bit elements into .type = { .g. Semantics d = a.b64 mov. %x.y << 32) // pack two 8-bit elements into .7].b16.z. a[16.. Description Write scalar register d with the packed value of vector register a..31].63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b have type .b32 // pack four 16-bit elements into . or write vector register d with the unpacked values from scalar register a.w}.x.y } = { a[0.b32 { d. a[8.z << 16) | (a.PTX ISA Version 2.. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. lo. {lo. d. ..b32 { d. d.31] } // unpack 16-bit elements from .x | (a. {r. d. For bit-size types..0.a}. d.15] } // unpack 8-bit elements from .x..b16 { d.b32 mov.31]..x. d.y } = { a[0. a[32.a have type .47]. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).x | (a.x | (a.7]. d.b}.w have type . // // // // a.b32 %r1.b.b.w } = { a[0.{x.y.%r1.b8 r.b64 112 January 24.31] } // unpack 8-bit elements from . Supported on all target architectures.g. a[8.. %r1.u8 // unpack 32-bit elements from ..

ld introduced in PTX ISA version 1. Instruction Set Table 81. an integer or bit-size type register reg containing a byte address. . to enforce sequential consistency between threads accessing shared memory.ss}{.cop}. . In generic addressing.u64. . .vec. Description Load register variable d from the location specified by the source address operand a in specified state space. . . [a].e. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .volatile. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .const space suffix may have an optional bank number to indicate constant banks other than bank zero.type . an address maps to the corresponding location in local or shared memory.s32. *(a+immOff). The address must be naturally aligned to a multiple of the access size. .volatile{. an address maps to global memory unless it falls within the local memory window or the shared memory window. The .e. Cache operations are not permitted with ld. i. . .vec = { .0.u8.f16 data may be loaded using ld. *(immAddr).volatile. If no state space is given. 32-bit).0.v4 }.b16. Generic addressing may be used with ld.volatile may be used with . Within these windows. i. 2010 113 .ss = { .f32. .ca.type ld. .s16.u16. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. A destination register wider than the specified type may be used. . . Generic addressing and cache operations introduced in PTX ISA 2.type d. or [immAddr] an immediate absolute byte address (unsigned. and is zeroextended to the destination register width for unsigned and bit-size types. d.global and .Chapter 8. PTX ISA Notes January 24.cop}.ss}{. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.f64 using cvt. [a].cg. . and truncated if the register width exceeds the state space address width for the target architecture. and then converted to . d..b64.1.b16.reg state space. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.local.global. perform the load using generic addressing. 32-bit).b8. the access may proceed by silently masking off low-order address bits to achieve proper rounding.shared spaces to inhibit optimization of references to volatile memory. d. *a. or the instruction may fault. .type ld{.lu. . . Addresses are zero-extended to the specified width as needed. The value loaded is sign-extended to the destination register width for signed integers. . . [a].s8.cop = { . Semantics d d d d = = = = a.volatile{.type = { .ss}. .b32.ss}.cv }.param.shared }. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. This may be used.u32. The address size may be either 32-bit or 64-bit.cs.vec. . .f32 or . If an address is not properly aligned.f64 }. . for example.v2. ld{. ld.const. ld. [a]. the resulting behavior is undefined.s64.volatile introduced in PTX ISA version 1.

const.[fs].[p+-8].f32.PTX ISA Version 2.b32 ld.[buffer+64]. // negative offset %r.s32 ld.f32 ld. x.b32 ld.[a].shared. // access incomplete array x. Q.b16 cvt.v4. Generic addressing requires sm_20 or later.f64 requires sm_13 or later.b32 ld. Cache operations require sm_20 or later. d.b64 ld. // load .%r.[p+4].0 Target ISA Notes ld.const[4].local.global. %r.[240].f16 d. // immediate address %r. 2010 .f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[p].global. ld.local.

b16. A register containing an address may be declared as a bit-size type or integer type. . ldu{. For ldu.f32 Q.s32. *a. 32-bit). or the instruction may fault.u64. Within these windows.b16.s8.type d. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. where the address is guaranteed to be the same across all threads in the warp.0. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . an address maps to the corresponding location in local or shared memory. The data at the specified address must be read-only.b64. *(a+immOff). to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f16 data may be loaded using ldu.b32 d.v4 }.[a]. 32-bit). .f32 or .Chapter 8.s16. The value loaded is sign-extended to the destination register width for signed integers. The addressable operand a is one of: [avar] the name of an addressable variable var. ldu. PTX ISA Notes Target ISA Notes Examples January 24. Semantics d d d d = = = = a. i. 2010 115 . an address maps to global memory unless it falls within the local memory window or the shared memory window. and truncated if the register width exceeds the state space address width for the target architecture. .global.f32 d. . ldu. and is zeroextended to the destination register width for unsigned and bit-size types.e.type = { . .ss}. If no state space is given. i.b8. A destination register wider than the specified type may be used. .[p]. .global }.ss = { . // load from address // vec load from address .f64 requires sm_13 or later.type ldu{. and then converted to .f64 using cvt. or [immAddr] an immediate absolute byte address (unsigned.u16. . The address must be naturally aligned to a multiple of the access size.v4. [areg] a register reg containing a byte address.reg state space. . In generic addressing.vec = { . ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.global. [a]. The address size may be either 32-bit or 64-bit. *(immAddr).s64.b32. Introduced in PTX ISA version 2.u8. ldu.f32.. only generic addresses that map to global memory are legal. [a].[p+4]. perform the load using generic addressing. Addresses are zero-extended to the specified width as needed. d.f64 }. If an address is not properly aligned. the resulting behavior is undefined. .ss}. Instruction Set Table 82. the access may proceed by silently masking off low-order address bits to achieve proper rounding.vec. . . ldu.u32.global. . .v2. // state space .e. . .

type [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. { . st. Generic addressing requires sm_20 or later.b16.cop}.shared }.type = = = = {.wb. Cache operations are not permitted with st.type st{. i. If an address is not properly aligned.v2.volatile may be used with .. .ss}. Cache operations require sm_20 or later.volatile. If no state space is given.0.ss . This may be used. . b. .vec.s32. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.e. .f16 data resulting from a cvt instruction may be stored using st. b.local.u8. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. st. .shared spaces to inhibit optimization of references to volatile memory. 32-bit). for example. *d = a.b8. perform the store using generic addressing. *(immAddr) = a. The lower n bits corresponding to the instruction-type width are stored to memory.volatile{.cs. *(d+immOffset) = a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. . i. . or [immAddr] an immediate absolute byte address (unsigned.s16. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. b. The address size may be either 32-bit or 64-bit. b. [a].b32.cg. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .cop}.1.global and . [a]. The address must be naturally aligned to a multiple of the access size.vec.global. .b16.ss}. and truncated if the register width exceeds the state space address width for the target architecture. . Addresses are zero-extended to the specified width as needed. the resulting behavior is undefined. .volatile{.u32. . Generic addressing may be used with st.f32.volatile.ss}{.f64 }.e.b64.vec .u16. .PTX ISA Version 2. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.u64. 32-bit).s64.cop .ss}{. .0 Table 83. 2010 . an integer or bit-size type register reg containing a byte address. an address maps to the corresponding location in local or shared memory. Within these windows. In generic addressing. . Semantics d = a. or the instruction may fault. to enforce sequential consistency between threads accessing shared memory. st{. .0. . . st introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes 116 January 24. .v4 }. { .type . . st. Generic addressing and cache operations introduced in PTX ISA 2.reg state space. { .type st.s8. A source register wider than the specified type may be used.volatile introduced in PTX ISA version 1.wt }. .f64 requires sm_13 or later. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.

s32 cvt.f32 st.local.global.f32 st. Instruction Set Examples st. 2010 117 . [p].local.b32 st.v4. // negative offset [100].s32 st.b.b16 [a].global. [q+4].a. // immediate address %r.b32 st.%r.local.Chapter 8. [fs].a.f16.Q. // %r is 32-bit register // store lower 16 bits January 24.%r. [q+-8].r7.

. the prefetch uses generic addressing. 118 January 24.space = { . prefetchu.global.L1 [addr]. A prefetch to a shared memory location performs no operation. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. The address size may be either 32-bit or 64-bit. and truncated if the register width exceeds the state space address width for the target architecture. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Addresses are zero-extended to the specified width as needed. an address maps to global memory unless it falls within the local memory window or the shared memory window.space}. or [immAddr] an immediate absolute byte address (unsigned. [a].L1 [a]. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L1. . a register reg containing a byte address.e.level = { .local }. prefetch. Within these windows. 2010 . 32-bit). prefetch and prefetchu require sm_20 or later.0 Table 84. // prefetch to data cache // prefetch to uniform cache . A prefetch into the uniform cache requires a generic address.L2 }. In generic addressing.L1 [ptr].PTX ISA Version 2. an address maps to the corresponding location in local or shared memory. i. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.0.level prefetchu. and no operation occurs if the address maps to a local or shared memory location. If no state space is given.global. in specified state space. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. . prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. 32-bit). prefetch{.

// get generic address of svar cvta. local. cvta requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.local.size = { .u32 p. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. For variables declared in global. Introduced in PTX ISA version 2. .u32 p.global.global isspacep.u64 or cvt.u64.pred .shared. cvta.space = { . p. local. or shared address.size . // result is . a. var. or vice-versa.shared }.u32. // convert to generic address // get generic address of var // convert generic address to global. svar.genptr. The source address operand must be a register of type . or shared state space. PTX ISA Notes Target ISA Notes Examples Table 86.0. p. or shared address to a generic address. sptr. When converting a generic address into a global.local. . A program may use isspacep to guard against such incorrect behavior. . Description Convert a global.to. or shared state space to generic. cvta.pred. a. . The source and destination addresses must be the same size. or shared address cvta.size p. // local.0. January 24. Instruction Set Table 85. gptr.global.u32.u32 or .to.shared }. local.u64 }. local. islcl. isshrd.space.u32 to truncate or zero-extend addresses. or vice-versa. a. . the generic address of the variable may be taken using cvta. isspacep.shared isglbl.Chapter 8.size cvta. or shared state space. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.lptr.local isspacep. isspacep requires sm_20 or later.global. cvta. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. Use cvt. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.u32 gptr. lptr. The destination register must be of type .local. isspacep.space.space p. . local. Take the generic address of a variable declared in global.space.u64. 2010 119 .space = { .

.rzi round to nearest integer in the direction of zero .f32 float-tofloat conversions with integer rounding. Integer rounding modifiers: . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. Integer rounding is required for float-to-integer conversions. and for same-size float-tofloat conversions where the value is rounded to an integer.. d = convert(a). Description Semantics Integer Notes Convert between different types and sizes.f32.f32 float-tofloat conversions with integer rounding.f16. .dtype.ftz.e. . . .0 Table 87.s64. the . a. .atype = { . subnormal numbers are supported.dtype.rp }.ftz}{.f64 }.u64.PTX ISA Version 2. cvt{. . choosing even integer if source is equidistant between two integers. .sat limits the result to MININT. For cvt.rz. Note that saturation applies to both signed and unsigned integer types. . i.e.irnd}{. Saturation modifier: .f32 float-to-integer conversions and cvt. // integer rounding // fp rounding .rni. .sat}.rm. d. .u32.rmi round to nearest integer in direction of negative infinity .sat is redundant.s8. . the result is clamped to the destination range by default.dtype = . . . Note: In PTX ISA versions 1.f32 float-to-integer conversions and cvt.ftz.sat}.ftz.rni round to nearest integer. For float-to-integer conversions.atype d. subnormal inputs are flushed to signpreserving zero.dtype.dtype.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.rpi }. Integer rounding is illegal in all other instances.ftz modifier may be specified in these cases for clarity.frnd = { .sat For integer destination types.4 and earlier. . i. .rzi. .u8.u16. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.f32. 2010 . .rn.frnd}{. The compiler will preserve this behavior for legacy PTX code. a. The optional .atype cvt{. 120 January 24. subnormal inputs are flushed to signpreserving zero. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.MAXINT for the size of the operation. .ftz}{..ftz.s32.irnd = { . .s16. sm_1x: For cvt.rmi.f32.

1.ftz behavior for sm_1x targets January 24. .s32 f.rn mantissa LSB rounds to nearest even .y.f32 x.4 and earlier.rm mantissa LSB rounds towards negative infinity .f32. . and . cvt. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32. Specifically. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.s32.0]. The optional . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . 2010 121 . and cvt. Floating-point rounding modifiers: .f32.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. Floating-point rounding is illegal in all other instances.rni.y. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16. The compiler will preserve this behavior for legacy PTX code.f32.f32.f64 types.f64 j. The result is an integral value.f64 requires sm_13 or later.f64.sat limits the result to the range [0.f16. subnormal numbers are supported.rz mantissa LSB rounds towards zero . Subnormal numbers: sm_20: By default.f32. cvt to or from .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). cvt. and for integer-to-float conversions. The operands must be of the same size. Applies to . // note . stored in floating-point format. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.i.version is 1. cvt.f32. Modifier .0.f32 instructions.r. Introduced in PTX ISA version 1.ftz modifier may be specified in these cases for clarity.4 or earlier. Note: In PTX ISA versions 1. // float-to-int saturates by default cvt.sat For floating-point destination types.Chapter 8.f16.f32 x. result is fp cvt. // round to nearest int. if the PTX . NaN results are flushed to positive zero. Saturation modifier: .0.

entry compute_power ( . and surface descriptors. r5.f32 {r1. Example: calculate an element’s power contribution as element’s power/total number of elements. r5. Module-scope and per-entry scope definitions of texture. 122 January 24. } = clamp_to_border. with the restriction that they correspond 1-to-1 with the 128 possible textures.texref tex1 ) { txq. {f1. add.height.r4}. If no texturing mode is declared.u32 r5. Texturing modes For working with textures and samplers.v4. [tex1. and surface descriptors.2d.width.param .f2}]. PTX has two modes of operation. Ability to query fields within texture. 2010 . sampler. div.b32 r6.f32 r1.f32. . sampler. but the number of samplers is greatly restricted to 16. r4. add. sampler. .. In the unified mode. = nearest width height tsamp1.6. and surfaces.u32 r5.b32 r5. r1. r1. r3. and surface descriptors: • • • Static initialization of texture. In the independent mode.7.f32 r1. sampler. . samplers. mul.0 8. r2.f32. texture and sampler information each have their own handle.r3. r1. The advantage of independent mode is that textures and samplers can be mixed and matched. the file is assumed to use unified mode. texture and sampler information is accessed through a single . PTX supports the following operations on texture.r2.samplerref tsamp1 = { addr_mode_0 filter_mode }.f32 r1. add.PTX ISA Version 2. The advantage of unified mode is that it allows 128 samplers. The texturing mode is selected using . allowing them to be defined separately and combined at the site of usage in the program.f32 r3. [tex1]. cvt. A PTX module may declare only one texturing mode. r5.global . r6. // get tex1’s tex. r3.texref handle. [tex1]. and surface descriptors. // get tex1’s txq..target texmode_independent .target options ‘texmode_unified’ and ‘texmode_independent’. Texture and Surface Instructions This section describes PTX instructions for accessing textures.

3d }. PTX ISA Notes Target ISA Notes Examples January 24. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. .geom.r3.v4 coordinate vectors are allowed for any geometry. If no sampler is specified.v4. [a.1d. Unified mode texturing introduced in PTX ISA version 1.r4}. .f32 }. An optional texture sampler b may be specified. with the extra elements being ignored. // Example of independent mode texturing tex.f2. //Example of unified mode texturing tex.geom = { . is a two-element vector for 2d textures.s32. . [a.dtype. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.btype tex. tex txq suld sust sured suq Table 88. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. Instruction Set These instructions provide access to texture and surface memory. where the fourth element is ignored.geom. .f4}].r2.s32.f3. or the instruction may fault. and is a four-element vector for 3d textures. A texture base address is assumed to be aligned to a 16-byte address.f32 }.dtype = { .3d. Supported on all target architectures. 2010 123 . Description Texture lookup using a texture coordinate vector. {f1. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. the square brackets are not required and .e. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.0. Notes For compatibility with prior versions of PTX.r4}. tex.Chapter 8. sampler_x.r3. {f1}].1d. [tex_a.f32 {r1. If an address is not properly aligned. [tex_a.s32 {r1.5.v4.dtype. c]. i. the sampler behavior is a property of the named texture.. the resulting behavior is undefined. b.r2. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. Operand c is a scalar or singleton tuple for 1d textures.u32.btype = { .v4.s32. d. c].btype d.v4. The instruction always returns a four-element vector of 32-bit values. .2d. . // explicit sampler .s32.

b32 txq.0 Table 89.addr_mode_0. [tex_A]. txq. [a].tquery. addr_mode_1.addr_mode_0. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.squery = { .depth .tquery = { . Integer from enum { nearest. 2010 .width.depth.filter_mode.addr_mode_1 . . . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. addr_mode_2 }.addr_mode_0 . d. linear } Integer from enum { wrap. clamp_ogl.width.texref or .b32 %r1. sampler attributes are also accessed via a texref argument.samplerref variable. txq. . Query: .normalized_coords }.filter_mode .filter_mode. // unified mode // independent mode 124 January 24.squery.height . [tex_A].5.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [a].height. Description Query an attribute of a texture or sampler. txq.PTX ISA Version 2. .width . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. clamp_to_edge.normalized_coords . // texture attributes // sampler attributes . . Operand a is a . and in independent mode sampler attributes are accessed via a separate samplerref argument. Supported on all target architectures. mirror.b32 d. In unified mode.b32 %r1.b32 %r1. txq. [smpl_B].

B.s32.cop}.cs. then . sm_1x targets support only the .b . suld. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.f32 is returned. Cache operations require sm_20 or later.1d.f32 }. Operand b is a scalar or singleton tuple for 1d surfaces. . . // for suld. . suld. .p.b.u32.v4.clamp. suld. . . and A components of the surface format.y.trap.v2.ca. . .trap suld. .b64.dtype.trap .r2}. the surface sample elements are converted to . suld. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The . b]. Destination vector elements corresponding to components that do not appear in the surface format are not written.s32.1d.p requires sm_20 or later. if the surface format contains UINT data.z. [a. and is a four-element vector for 3d surfaces.f32.b. [surf_A.2d. suld. If an address is not properly aligned. If the destination base type is .b performs an unformatted load of binary data.trap introduced in PTX ISA version 1. 2010 125 . if the surface format contains SINT data.u32.clamp = = = = = = { { { { { { d.dtype .Chapter 8. . or FLOAT data. . . Target ISA Notes Examples January 24. then .5.w}].cop}.geom{.v2.3d }.surfref variable. the resulting behavior is undefined. Instruction Set Table 90.clamp .vec .b64 }.clamp . . // cache operation none. suld. the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom{. and the size of the data transfer matches the size of destination operand d.3d requires sm_20 or later. [a.p is currently unimplemented. .cg.s32. .0.b8 . . SNORM.clamp suld.b. size and type conversion is performed as needed to convert from the surface sample format to the destination type. A surface base address is assumed to be aligned to a 16-byte address. b]. Operand a is a . [surf_B. // unformatted d. {x}]. i. // for suld.f3. {f1.p.p .b32. G. or .b32.e.b32.u32 is returned. or . {x.vec.b16.zero }.b supported on all target architectures. Coordinate elements are of type .clamp field specifies how to handle out-of-bounds addresses: . then .v4 }. is a two-element vector for 2d surfaces.dtype.f32.u32. .cv }. .trap clamping modifier.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.dtype .s32 is returned. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap {r1.f2.p. and cache operations introduced in PTX ISA version 2. or the instruction may fault. Description Load from surface memory using a surface coordinate vector. The lowest dimension coordinate represents a sample offset rather than a byte offset.f32 based on the surface format as follows: If the surface format contains UNORM.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. suld.3d.. suld Syntax Texture and Surface Instructions: suld Load from surface memory. suld. where the fourth element is ignored.f4}. additional clamp modifiers.s32.v4.cop . .geom . If the destination type is . suld. // formatted .

if the surface format contains SINT data. If the source base type is .v4.ctype .f32} are currently unimplemented. . {x.cop}. Surface sample components that do not occur in the source vector will be written with an unpredictable value.f32 is assumed.b performs an unformatted store of binary data. then . then .v2. sust. {x}].geom .p requires sm_20 or later.1d. B. sust.cop .3d }. {f1. sust. if the surface format contains UINT data. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. .u32 is assumed.0 Table 91.b32.trap [surf_A.f2. If an address is not properly aligned. The source data is then converted from this type to the surface sample format.p. sust. // for sust. sust. is a two-element vector for 2d surfaces. . .u32. A surface base address is assumed to be aligned to a 16-byte address.clamp = = = = = = { { { { { { [a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The source vector elements are interpreted left-to-right as R. .clamp field specifies how to handle out-of-bounds addresses: .b.clamp sust.v2.b32. . Coordinate elements are of type . .vec . and is a four-element vector for 3d surfaces. // unformatted // formatted .f4}.s32.geom{.p. .3d. . c.s32.cg.clamp . then .w}]. i. sust. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.5. where the fourth element is ignored. size and type conversions are performed as needed between the surface sample format and the destination type.p.f32.ctype . sust.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.PTX ISA Version 2. .f32 }.{u32.p performs a formatted store of a vector of 32-bit data values to a surface sample. . sust Syntax Texture and Surface Instructions: sust Store to surface memory.b. none. and cache operations introduced in PTX ISA version 2.b // for sust.trap.trap sust. Operand a is a .f3.geom{.u32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. or FLOAT data.b supported on all target architectures.trap clamping modifier. b]. and A surface components. .y.p.ctype. additional clamp modifiers. G. These elements are written to the corresponding surface sample components.1d.b.b16. SNORM.wt }.b32.cop}. . .r2}.clamp . the resulting behavior is undefined. c. .b64. {r1.0. Cache operations require sm_20 or later.zero }.vec. or .cs. The size of the data transfer matches the size of source operand c.b64 }.trap introduced in PTX ISA version 1. . sust. . [surf_B.. Target ISA Notes Examples 126 January 24. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. .p Description Store to surface memory using a surface coordinate vector.f32.ctype. Operand b is a scalar or singleton tuple for 1d surfaces.e.vec. The . b]. The lowest dimension coordinate represents a sample offset rather than a byte offset.b8 . .v4 }.z. or the instruction may fault.surfref variable. sust. If the source type is . .2d. 2010 .s32 is assumed. [a.s32. Source elements that do not occur in the surface sample are ignored.s32.3d requires sm_20 or later.wb.clamp. sm_1x targets support only the .trap .

1d. // for sured.2d. Operations add applies to .u32. .b.clamp = { . and the data is interpreted as .u32 based on the surface sample format as follows: if the surface format contains UINT data. // sample addressing .clamp. sured.b]. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. the resulting behavior is undefined. Operand a is a . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.2d.1d.surfref variable.s32.b]. .u32. .trap . .p .s32. or the instruction may fault.add.c. [surf_B. . 2010 127 .or }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. {x}].ctype = { . .trap.e. // for sured.u64.trap [surf_A. sured.geom.b32 }. Instruction Set Table 92.s32 types. sured. .geom. . . . sured.clamp . i.min. then . and is a four-element vector for 3d surfaces.s32 or . then .u64. The instruction type is restricted to . .s32 types. The lowest dimension coordinate represents a sample offset rather than a byte offset.y}].b32.add. or .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Coordinate elements are of type .clamp [a.Chapter 8.p.op. . .u64 data.b32. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.u32. January 24. min and max apply to .s32. Operand b is a scalar or singleton tuple for 1d surfaces.b performs an unformatted reduction on . . r1. // byte addressing sured.0.s32 is assumed.p performs a reduction on sample-addressed 32-bit data.b32 type.b. {x. operations and and or apply to . is a two-element vector for 2d surfaces.b32 }.min. . The . If an address is not properly aligned.u32 and .op = { . Reduction to surface memory using a surface coordinate vector. where the fourth element is ignored.c. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.zero }. .p.ctype.ctype = { .b32.and..3d }.ctype. A surface base address is assumed to be aligned to a 16-byte address.trap sured.u32.max.clamp field specifies how to handle out-of-bounds addresses: .b . sured requires sm_20 or later. if the surface format contains SINT data.clamp [a. and .geom = { . r1.op.u32 is assumed.

2010 .PTX ISA Version 2.surfref variable. suq.depth }.width .query. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. .width. .b32 %r1.height. 128 January 24. Query: .b32 d.0 Table 93.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. [a]. Supported on all target architectures. . suq.width. [surf_A].5. Description Query an attribute of a surface.query = { . Operand a is a .height .

Chapter 8. Introduced in PTX ISA version 1. Threads with a false guard predicate do nothing. Supported on all target architectures. @{!}p instruction.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.f32 @!p div.eq.7.c. ratio. } PTX ISA Notes Target ISA Notes Examples Table 95. 2010 129 . The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.y. setp. { add. p.s32 d. {} Syntax Description Control Flow Instructions: { } Instruction grouping. mov.7.0.0. Execute an instruction or instruction block for threads that have the guard predicate true. If {!}p then instruction Introduced in PTX ISA version 1. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.0.b. { instructionList } The curly braces create a group of instructions.x.f32 @q bra L23. Instruction Set 8.a. Supported on all target architectures.s32 a. used primarily for defining a function body.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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and any-thread-true (.or }.op. it simply marks a thread's arrival at the barrier. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. If no thread count is specified. b}. it is as if all the threads in the warp have executed the bar instruction. the bar.Chapter 8. and bar.u32.op = { . and d have type . Operands a.popc is the number of threads with a true predicate.sync and bar. Thus.cta.sync and bar. The reduction operations for bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active.u32 bar. thread count.arrive does not cause any waiting by the executing threads. thread count. all threads in the CTA participate in the barrier. the waiting threads are restarted without delay.. January 24.sync or bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. All threads in the warp are stalled until the barrier completes. In addition to signaling its arrival at the barrier. a.15.0.sync or bar. b. Once the barrier count is reached. bar.red performs a predicate reduction across the threads participating in the barrier.red also guarantee memory ordering among threads identical to membar.red} introduced in PTX . Each CTA instance has sixteen barriers numbered 0.arrive using the same active barrier. if any thread in a warp executes a bar instruction.and and .0. while . bar. bar. bar. Description Performs barrier synchronization and communication within a CTA. bar. the final value is written to the destination register in all threads waiting at the barrier. Execution in this case is unpredictable.sync with an immediate barrier number is supported for sm_1x targets.arrive. Only bar. PTX ISA Notes Target ISA Notes Examples bar. .red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. The barrier instructions signal the arrival of the executing threads at the named barrier.red instruction.popc.red. all-threads-true (. and bar. bar. the optional thread count must be a multiple of the warp size.sync 0.and.version 2.or). a{.and). b. Since barriers are executed on a per-warp basis. Register operands. and then safely read values stored by other threads prior to the barrier. threads within a CTA that wish to communicate via memory can store to memory. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Operand b specifies the number of threads participating in the barrier. The result of .red. Thus. a{. In conditionally executed code. Note that a non-zero thread count is required for bar.sync) until the barrier count is met. b}.pred . Register operands. operands p and c are predicates. {!}c.popc). bar. bar.red} require sm_20 or later. and the barrier is reinitialized so that it can be immediately reused. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).red delays the executing threads (similar to bar. execute a bar.red performs a reduction operation across threads. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).{arrive.sync bar. Instruction Set Table 100. p. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.{arrive. b}.red should not be intermixed with bar.red are population-count (. d.sync without a thread count introduced in PTX ISA 1. bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. 2010 133 .arrive a{. {!}c. When a barrier completes.

level = { .sys Waits until all prior memory requests have been performed with respect to all clients. level describes the scope of other clients for which membar is an ordering event.cta. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. and memory reads by this thread can no longer be affected by other thread writes. membar. membar.sys.sys }.{cta. membar.sys introduced in PTX . membar.gl. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar.cta Waits until all prior memory writes are visible to other threads in the same CTA.4. . by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.sys requires sm_20 or later.version 2. membar.{cta. red or atom) has been performed when the value written has become visible to other clients at the specified level.gl will typically have a longer latency than membar.cta.g.0.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.level. A memory write (e. global.PTX ISA Version 2. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. including thoses communicating via PCI-E such as system and peer-to-peer memory.0 Table 101. membar.sys will typically have much longer latency than membar.version 1.gl} introduced in PTX . Waits until prior memory reads have been performed with respect to other threads in the CTA. this is the appropriate level of membar. PTX ISA Notes Target ISA Notes Examples membar. that is. membar. or system memory level. For communication between threads in different CTAs or even different SMs. A memory read (e. when the previous value can no longer be read.gl. membar. 134 January 24.gl} supported on all target architectures. by st. membar. . membar.cta. 2010 .g.gl. membar. . Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.

max }.exch to store to locations accessed by other atomic operations.f32. min.type d. and exch (exchange).s32. Within these windows. 32-bit operations.type atom{. .b64 . . . The address must be naturally aligned to a multiple of the access size. 2010 135 .add. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.space = { . or by using atom.type = { . an address maps to the corresponding location in local or shared memory. perform the memory accesses using generic addressing.s32. . January 24. dec.u32. max. The floating-point operations are add.g. cas (compare-and-swap). i. Instruction Set Table 102. The integer operations are add. inc. .op.inc. min.. . . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Operand a specifies a location in the specified state space. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . Addresses are zero-extended to the specified width as needed. min.exch. In generic addressing. b. or [immAddr] an immediate absolute byte address.op.global. atom. performs a reduction operation with operand b and the value in location a.xor..e. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and stores the result of the specified operation at location a.u32. i. . The address size may be either 32-bit or 64-bit. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and truncated if the register width exceeds the state space address width for the target architecture. Description // // // // // . . .space}. accesses to local memory are illegal.u32 only . .space}. and max operations are single-precision.f32 }. d. a de-referenced register areg containing a byte address. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.op = { .and.u64.b]. .b32.f32 Atomically loads the original value at location a into destination register d. overwriting the original value. b.min.b64. If no state space is given. . . by inserting barriers between normal stores and atomic operations to a common address.s32. or.b32.Chapter 8.dec.u32. the resulting behavior is undefined.cas. and max.shared }.b32 only . e. . [a]. c.e. or the instruction may fault. an address maps to global memory unless it falls within the local memory window or the shared memory window. The floating-point add. . [a]. atom{. .or.add.u64 . . For atom. A register containing an address may be declared as a bit-size type or integer type. xor. The bit-size operations are and. If an address is not properly aligned. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. The inc and dec operations return a result in the range [0.

atom. d.0. : r-1.global. b. *a = (operation == cas) ? : } where inc(r.s32 atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.b32 d. Release Notes Examples @p 136 January 24.{add.0. atom. s) = (r > s) ? s exch(r. 2010 .max. cas(r. c) operation(*a.PTX ISA Version 2.max} are unimplemented. atom.global.0 Semantics atomic { d = *a. Introduced in PTX ISA version 1.f32 atom.cas.t) = (r == s) ? t operation(*a.exch} requires sm_12 or later.[x+4]. atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. : r.add.shared requires sm_12 or later.my_new_val.s.cas. s) = s. s) = (r >= s) ? 0 dec(r.[p].global requires sm_11 or later. atom. 64-bit atom.[a]. d.my_val. : r+1.f32.f32 requires sm_20 or later.1. 64-bit atom.{min. b).shared. Use of generic addressing requires sm_20 or later.shared operations require sm_20 or later.add.

2010 137 .b32 only . and xor. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.min. e.s32. The floating-point add.u32. i.b32. .u32.u64. max. The integer operations are add. Operand a specifies a location in the specified state space. dec(r. If an address is not properly aligned.. b).e.or. The inc and dec operations return a result in the range [0.shared }. The address must be naturally aligned to a multiple of the access size. Description // // // // . .u32. min.f32 }. . .u64 .s32. s) = (r >= s) ? 0 : r+1. In generic addressing.b64. The bit-size operations are and. by inserting barriers between normal stores and reduction operations to a common address.type [a].exch to store to locations accessed by other reduction operations. .add. inc. . A register containing an address may be declared as a bit-size type or integer type.g. .space}.max }.. . . perform the memory accesses using generic addressing.type = { . the resulting behavior is undefined.inc. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.op = { . 32-bit operations.s32. Notes Operand a must reside in either the global or shared state space. accesses to local memory are illegal. . . .xor. min. . and stores the result of the specified operation at location a.b].dec.space = { . or by using atom. or the instruction may fault. red{. Within these windows. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Semantics *a = operation(*a.u32 only . . and max operations are single-precision. and max. Addresses are zero-extended to the specified width as needed. i. and truncated if the register width exceeds the state space address width for the target architecture. the access may proceed by silently masking off low-order address bits to achieve proper rounding.op.global. or [immAddr] an immediate absolute byte address. Instruction Set Table 103. .add. .Chapter 8. a de-referenced register areg containing a byte address.f32. overwriting the original value. January 24. The address size may be either 32-bit or 64-bit. b.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. where inc(r. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. s) = (r > s) ? s : r-1. . . .e. min.and. dec. or. red. . . an address maps to global memory unless it falls within the local memory window or the shared memory window. If no state space is given. For red. an address maps to the corresponding location in local or shared memory.f32 Performs a reduction operation with operand b and the value in location a. The floating-point operations are add. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.

my_val.{min. red.and. [p].0.PTX ISA Version 2. red.global. red. Release Notes Examples @p 138 January 24.f32 red.b32 [a].add requires sm_12 or later.2.shared operations require sm_20 or later.max} are unimplemented.max.f32. 64-bit red.f32 requires sm_20 or later.add.global. [x+4].shared requires sm_12 or later.global requires sm_11 or later red. 64-bit red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.1. red.s32 red. 2010 . Use of generic addressing requires sm_20 or later.shared.add.

uni. Negating the source predicate also computes . vote.pred d.none. not across an entire CTA.b32 requires sm_20 or later. vote requires sm_12 or later. {!}a.mode. // get ‘ballot’ across warp January 24.p.ballot.2. The destination predicate value is the same across all threads in the warp. The reduction modes are: .any True if source predicate is True for some active thread in warp. .mode = { . vote. Description Performs a reduction of the source predicate across threads in a warp. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.q. 2010 139 . vote.q. In the ‘ballot’ form.all. vote.ballot. // ‘ballot’ form. p.b32 p.pred vote.not_all. . Negate the source predicate to compute . returns bitmask .uni }. Instruction Set Table 104. . Negate the source predicate to compute . r1. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Note that vote applies to threads in a single warp.uni.all.Chapter 8.all True if source predicate is True for all active threads in warp. where the bit position corresponds to the thread’s lane id.ballot.uni True if source predicate has the same value in all active threads in warp.ballot. .pred vote.b32 d. {!}a.any. vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.

taking into account the subword destination size in the case of optional data merging. or word values from its source operands. and btype are valid. .7.asel = .sat} d. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. .add. The type of each operand (.s32 }. . The primary operation is then performed to produce an .btype{. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).s32) is specified in the instruction type. atype.btype{.PTX ISA Version 2.bsel = { . 3.btype = { .u32.h0. .b1.s34 intermediate result.dsel = . a{.asel}.extended internally to .bsel}. Video Instructions All video instructions operate on 32-bit register operands. optionally clamp the result to the range of the destination type. .dtype.atype. 140 January 24.sat}.btype{. half-word. vop.h1 }. . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. . all combinations of dtype. extract and sign. 2. b{.dtype = .dsel.b3. .b2.secop = { . The source and destination operands are all 32-bit registers.min.atype. 4. Using the atype/btype and asel/bsel specifiers. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.secop d.atype. .atype = . c.bsel}. The sign of the intermediate result depends on dtype. with optional data merge vop. .b0. // 32-bit scalar operation.max }. . The general format of video instructions is as follows: // 32-bit scalar operation. with optional secondary operation vop.u32 or . perform a scalar arithmetic operation to produce a signed 34-bit result. a{. the input values are extracted and signor zero.sat} d.or zero-extend byte. b{. c. a{.dtype. 2010 .asel}.dtype. to produce signed 33-bit input values. b{.bsel}.asel}.s33 values.0 8.9.

b0. tmp. c). . The sign of the c operand is based on dtype. . January 24. default: return tmp. The lower 32-bits are then written to the destination operand. S8_MIN ).s33 optSaturate( . Bool sat. U16_MAX. tmp.b3: return ((tmp & 0xff) << 24) default: return tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. . tmp. c). . Modifier dsel ) { if ( !sat ) return tmp. c).add: return tmp + c.h1: return ((tmp & 0xffff) << 16) case . . c).b1: return ((tmp & 0xff) << 8) case .s33 optSecOp(Modifier secop. as shown in the following pseudocode.s34 tmp.Chapter 8. Instruction Set . switch ( dsel ) { case .min: return MIN(tmp.h0. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). . S16_MIN ). } } . U8_MAX. .h0: return ((tmp & 0xffff) case . S8_MAX. 2010 141 . S32_MIN ).b2.max return MAX(tmp. . .b2: return ((tmp & 0xff) << 16) case .s33 tmp.b0: return ((tmp & 0xff) case .s33 c ) switch ( dsel ) { case . U8_MIN ). c).b3: if ( sign ) return CLAMP( else return CLAMP( case . tmp. c). Bool sign.s33 c) { switch ( secop ) { . tmp.b1. S32_MAX.s33 optMerge( Modifier dsel. U16_MIN ). U32_MIN ). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 tmp. c). . . U32_MAX. S16_MAX.

Integer byte/half-word/word absolute value of difference. c. vmin.h0. c. a{.max }. { . r1. . r2. vadd. . with optional data merge vop.h1.atype.h1 }. . atype.s32.dtype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. with optional secondary operation vop. tmp = MAX( ta.b3.h0. tmp = | ta – tb |. vop.dtype .s32.min.asel = .add r1.op2 Description = = = = { vadd. // optional merge with c operand 142 January 24.dtype.h0. Integer byte/half-word/word minimum / maximum. c. isSigned(dtype). r3.u32. vabsdiff.s32. Perform scalar arithmetic operation with optional saturate. b{. c ).0 Table 105. // 32-bit scalar operation. . a{.asel}.bsel}. .or zero-extend based on source operand type ta = partSelectSignExtend( a.vop . r2. b{. tmp = MIN( ta.s32. . 2010 .btype = { . tb = partSelectSignExtend( b. asel ). // 32-bit scalar operation.bsel = { . .s32.bsel}.sat.sat}.b0.h1.b2. c ).atype. r2. tmp = ta – tb. vadd.PTX ISA Version 2. // optional secondary operation d = optMerge( dsel. sat.dtype. bsel ).sat vsub.b1.s32. r1. tb ).asel}. r3. vabsdiff. tmp. vmax }.atype = .btype{. d = optSecondaryOp( op2.s32 }. . vsub.u32. c.sat} d. . btype. and optional secondary arithmetic operation or subword data merge. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.s32. r2. tmp. vmax require sm_20 or later.b0.0. r3.atype.op2 d.dsel .bsel}.s32. vmin. tb ). vmax Syntax Integer byte/half-word/word addition / subtraction.sat vabsdiff.sat vmin. r1. r3. vsub vabsdiff vmin. vabsdiff.u32.s32.dsel. . a{.b0. dsel ). Video Instructions: vadd.btype{. vmax vadd. b{.b2. vmin. taking into account destination type and merge operations tmp = optSaturate( tmp. .btype{. // extract byte/half-word/word and sign.sat} d. vsub. Semantics // saturate. vsub.add.s32.asel}.

h1 }. if ( mode == . r3. a{. taking into account destination type and merge operations tmp = optSaturate( tmp.max }. tmp. Signed shift fills with the sign bit. a{.Chapter 8.add.dsel .clamp .wrap }.op2 d. .u32{.vop . case vshr: tmp = ta >> tb. { . Semantics // extract byte/half-word/word and sign. .u32. // default is .clamp.asel}.atype. isSigned(dtype).u32. vshr: Shift a right by unsigned amount in b with optional saturate.u32.atype. a{.min. .or zero-extend based on source operand type ta = partSelectSignExtend( a. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. { .u32{.asel = . bsel ). with optional data merge vop. .u32.u32. .b3. r2. asel ). atype. unsigned shift fills with zero. January 24.mode .bsel}. . vshr vshl.atype = { . 2010 143 . // optional secondary operation d = optMerge( dsel.asel}.clamp && tb > 32 ) tb = 32. vshr }. .b1. b{. vshr Syntax Integer byte/half-word/word left / right shift.b0. vshl.h0. Left shift fills with zero.dtype.sat}{. vshl: Shift a left by unsigned amount in b with optional saturate.u32 vshr. tmp. and optional secondary arithmetic operation or subword data merge. if ( mode == .s32. switch ( vop ) { case vshl: tmp = ta << tb. d = optSecondaryOp( op2.asel}.u32{.mode}.mode} d. // 32-bit scalar operation. vshl.wrap ) tb = tb & 0x1f.wrap r1. Instruction Set Table 106. .0. Video Instructions: vshl. dsel ). c ). r1.atype.mode} d. c ). vshr require sm_20 or later. b{.dtype. .dtype. tb = partSelectSignExtend( b. c. with optional secondary operation vop. r2.dtype . .h1. .op2 Description = = = = = { vshl. sat.bsel}. } // saturate.dsel. and optional secondary arithmetic operation or subword data merge.sat}{. c.u32.sat}{. r3.b2. // 32-bit scalar operation. vop. b{.bsel}. .s32 }.bsel = { .

.scale} d. a{. . 2010 . and scaling. . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.atype = . vmad. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final signed -(S32 * U32) + S32 // intermediate signed. and the operand negates.u32.atype.po) computes (a*b) + c + 1.sat}{.po mode. internally this is represented as negation of the product (a*b).0 Table 107. final signed (S32 * U32) .sat}{.shr15 }. . final signed -(U32 * S32) + S32 // intermediate signed.b2. PTX allows negation of either (a*b) or c.dtype = . That is. otherwise.b1.S32 // intermediate signed.dtype.bsel}. Source operands may not be negated in . final signed (S32 * U32) + S32 // intermediate signed.btype.asel = . “plus one” mode.asel}. // 32-bit scalar operation vmad. {-}c.po{. final signed -(S32 * S32) + S32 // intermediate signed. 144 January 24.dtype. this result is sign-extended if the final result is signed. final signed (U32 * S32) . . with optional operand negates. Description Calculate (a*b) + c.btype = { . The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. (a*b) is negated if and only if exactly one of a or b is negated.b3.U32 // intermediate unsigned.bsel = { . final signed The intermediate result is optionally scaled via right-shift. The final result is unsigned if the intermediate result is unsigned and c is not negated.shr7. final unsigned -(U32 * U32) + S32 // intermediate signed.atype. final signed (S32 * S32) + S32 // intermediate signed. . c.S32 // intermediate signed. the intermediate result is signed. .b0.PTX ISA Version 2. Input c has the same sign as the intermediate result. final signed (U32 * U32) .scale} d. and zero-extended otherwise. .asel}. The “plus one” mode (. final signed (S32 * S32) . {-}a{. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.s32 }. Although PTX syntax allows separate negation of the a and b operands.scale = { . b{. The source operands support optional negation with some restrictions.S32 // intermediate signed. . Depending on the sign of the a and b operands. . . which is used in computing averages. final signed (U32 * S32) + S32 // intermediate signed.bsel}.btype{.h1 }. {-}b{.h0.

U32_MAX. 2010 145 . signedFinal = isSigned(atype) || isSigned(btype) || (a. lsb = 1.negate ) { tmp = ~tmp.u32. } else if ( c. r2. btype. } else if ( a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.h0. r2.u32. tb = partSelectSignExtend( b.negate ^ b.or zero-extend based on source operand type ta = partSelectSignExtend( a. if ( . case .negate.s32. S32_MIN). tmp = tmp + c128 + lsb.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate ) { c = ~c.shr7: result = (tmp >> 7) & 0xffffffffffffffff. vmad. S32_MAX. atype.po ) { lsb = 1. U32_MIN). Instruction Set Semantics // extract byte/half-word/word and sign. vmad requires sm_20 or later. bsel ). lsb = 1. } if ( .shr15 r0. lsb = 0. r1. r0.Chapter 8.u32. r1.sat vmad.sat ) { if (signedFinal) result = CLAMP(result. r3.u32. -r3. tmp[127:0] = ta * tb. switch( scale ) { case .s32.0. January 24.negate) || c. else result = CLAMP(result.negate ^ b. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). asel ).h0.

. a{.atype .h1 }.u32. c. .asel}.lt.b1. { .btype. tb. tmp.min.PTX ISA Version 2. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. Semantics // extract byte/half-word/word and sign. 2010 .dsel . // 32-bit scalar operation. r2. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tb = partSelectSignExtend( b. with optional secondary arithmetic operation or subword data merge. . asel ).bsel}.0.s32 }. tmp.b2. c. . . r2.asel = . a{. b{. b{. c ). btype. // optional secondary operation d = optMerge( dsel.add.op2 d.dsel. a{. .eq.btype.b3. with optional secondary operation vset. { . vset requires sm_20 or later. with optional data merge vset.0 Table 108.atype.ge }.ne. . .cmp d.atype. tmp = compare( ta.h1. .asel}. . b{. 146 January 24.u32. bsel ). atype. . and therefore the c operand and final result are also unsigned.bsel}.u32.lt vset.ne r1. The intermediate result of the comparison is always unsigned. // 32-bit scalar operation.cmp d.atype.cmp . .or zero-extend based on source operand type ta = partSelectSignExtend( a.gt. . d = optSecondaryOp( op2. Compare input values using specified comparison.u32. r3. vset. vset.asel}. r1.op2 Description = = = = . cmp ) ? 1 : 0.bsel = { .cmp. .bsel}. .btype = { .s32.b0. c ).h0. r3.le.max }.btype.

Notes PTX ISA Notes Target ISA Notes Examples Currently. trap. numbered 0 through 15. brkpt Suspends execution Introduced in PTX ISA version 1. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Table 111. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. there are sixteen performance monitor events.4. brkpt. with index specified by immediate operand a. trap. January 24. trap Abort execution and generate an interrupt to the host CPU. brkpt. Supported on all target architectures.10. 2010 147 . Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.Chapter 8. The relationship between events and counters is programmed via API calls from the host.7. Triggers one of a fixed number of performance monitor events. Table 110. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Introduced in PTX ISA version 1.0. brkpt requires sm_11 or later. Supported on all target architectures. Introduced in PTX ISA version 1. Instruction Set 8. @p pmevent 1.0. pmevent 7. pmevent a.

0 148 January 24. 2010 .PTX ISA Version 2.

%lanemask_le.Chapter 9. %lanemask_ge. %lanemask_lt. %lanemask_gt %clock. read-only variables. 2010 149 . which are visible as special registers and accessed through mov or cvt instructions. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %clock64 %pm0. …. Special Registers PTX includes a number of predefined. %pm3 January 24.

The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.y == %ntid.0.%tid.x < %ntid.x * %ntid. The %tid special register contains a 1D. 2D.y.u32 %ntid.x.x to %rh Target ISA Notes Examples // legacy PTX 1. mov. The number of threads in each dimension are specified by the predefined special register %ntid.%h2.z == 0 in 1D CTAs.%ntid.u32 %r1. // legacy PTX 1. .v4 .u32 %tid.z).sreg . %tid component values range from 0 through %ntid–1 in each CTA dimension.y 0 <= %tid.sreg .x. 2010 . mov.z to %r2 Table 113.0 Table 112. .u32 %h1.z. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. .x. %tid.u32.u32 %r0.y.x code accessing 16-bit component of %tid mov.y * %ntid.z == 1 in 1D CTAs. // move tid.x code Target ISA Notes Examples 150 January 24.v4 .z == 0 in 2D CTAs.z.z PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures. read-only special register initialized with the number of thread ids in each CTA dimension.%h1. mov.0. PTX ISA Notes Introduced in PTX ISA version 1. It is guaranteed that: 0 <= %tid.u32 %h2. the fourth element is unused and always returns zero.u32 type in PTX 2.%tid. read-only.x. %tid.PTX ISA Version 2.y < %ntid.y. %ntid. mad. Redefined as .y == %tid. . per-thread special register initialized with the thread identifier within the CTA.u32 %tid.u16 %r2.u32 %ntid.v4.u16 %rh. Supported on all target architectures. or 3D vector to match the CTA shape.sreg . Redefined as .v4. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.u32 %r0. The total number of threads in a CTA is (%ntid.%ntid. %ntid. The fourth element is unused and always returns zero. cvt.0. the %tid value in unused dimensions is 0.z.x. %tid.x 0 <= %tid.%tid. %ntid.u16 %rh.%tid.u32 type in PTX 2. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. // thread id vector // thread id components A predefined. mov.z < %ntid.x.z == 1 in 2D CTAs. %ntid. CTA dimensions are non-zero. Every thread in the CTA has a unique %tid. // zero-extend tid. %tid. // CTA shape vector // CTA dimensions A predefined.%tid.0.%r0.x.sreg . // compute unified thread id for 2D CTA mov.

Introduced in PTX ISA version 1. %nwarpid requires sm_20 or later. mov.g. A predefined. %warpid. Supported on all target architectures.u32 %warpid. mov. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. January 24.sreg . . Introduced in PTX ISA version 2. The lane identifier ranges from zero to WARP_SZ-1. Introduced in PTX ISA version 1. For this reason. %laneid. %nwarpid.u32 %r. read-only special register that returns the thread’s warp identifier. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.sreg . Note that %warpid is volatile and returns the location of a thread at the moment when read. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. A predefined.u32 %nwarpid.3. e.u32 %r. read-only special register that returns the maximum number of warp identifiers.0. PTX ISA Notes Target ISA Notes Examples Table 116.u32 %r. The warp identifier will be the same for all threads within a single warp. due to rescheduling of threads following preemption.sreg . . The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. read-only special register that returns the thread’s lane within the warp. Table 115.Chapter 9. Supported on all target architectures. 2010 151 . .3.u32 %laneid. mov. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. A predefined. but its value may change during execution. Special Registers Table 114.

Redefined as .z} < 65.u16 %r0.536 PTX ISA Notes Introduced in PTX ISA version 1.%nctaid. mov. %rh. .u32 mov. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. The fourth element is unused and always returns zero.y.y < %nctaid.0. . The %nctaid special register contains a 3D grid shape vector.y.z.x.x. // legacy PTX 1.sreg .0. // legacy PTX 1. Redefined as . %ctaid.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %nctaid.u32 type in PTX 2.v4.x code Target ISA Notes Examples 152 January 24.x. // Grid shape vector // Grid dimensions A predefined.sreg .%nctaid.x code Target ISA Notes Examples Table 118.PTX ISA Version 2. It is guaranteed that: 0 <= %ctaid.u32 %nctaid .z.z < %nctaid. // CTA id vector // CTA id components A predefined.0 Table 117. 2D. The %ctaid special register contains a 1D.v4 .y.y 0 <= %ctaid. 2010 .u16 %r0. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.y.%ctaid.x 0 <= %ctaid. Supported on all target architectures.%nctaid.x < %nctaid.0.u32 %ctaid.x. mov. It is guaranteed that: 1 <= %nctaid.v4.%nctaid. read-only special register initialized with the CTA identifier within the CTA grid. read-only special register initialized with the number of CTAs in each grid dimension. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u32 %ctaid. or 3D vector. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. with each element having a value of at least 1. . depending on the shape and rank of the CTA grid. %rh.0.{x.%ctaid.u32 mov. Supported on all target architectures.sreg .u32 type in PTX 2. Each vector element value is >= 0 and < 65535.v4 .x. The fourth element is unused and always returns zero. %ctaid.sreg .

mov. The SM identifier numbering is not guaranteed to be contiguous. PTX ISA Notes Target ISA Notes Examples January 24. . 2010 153 . Introduced in PTX ISA version 1. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. %gridid.u32 %nsmid. Introduced in PTX ISA version 1. Supported on all target architectures. Special Registers Table 119.0. Supported on all target architectures.sreg . . A predefined. mov. During execution. %nsmid requires sm_20 or later. The SM identifier ranges from 0 to %nsmid-1. %smid. . A predefined.u32 %gridid. repeated launches of programs may occur. Notes PTX ISA Notes Target ISA Notes Examples Table 120.u32 %smid. so %nsmid may be larger than the physical number of SMs in the device.3. %nsmid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. but its value may change during execution.0.u32 %r.sreg . The SM identifier numbering is not guaranteed to be contiguous. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.g.u32 %r. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. PTX ISA Notes Target ISA Notes Examples Table 121. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Note that %smid is volatile and returns the location of a thread at the moment when read.u32 %r. Introduced in PTX ISA version 2. mov. where each launch starts a grid-of-CTAs. due to rescheduling of threads following preemption. // initialized at grid launch A predefined. read-only special register that returns the maximum number of SM identifiers. This variable provides the temporal grid launch number for this context.sreg . read-only special register initialized with the per-grid temporal grid identifier. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. e.Chapter 9.

0. . mov.sreg .0. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined. %lanemask_le.sreg . 154 January 24. %lanemask_lt requires sm_20 or later. Table 123.u32 %lanemask_le.0 Table 122. Introduced in PTX ISA version 2.u32 %r. A predefined.u32 %lanemask_lt. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. 2010 . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later. %lanemask_lt.PTX ISA Version 2. mov. %lanemask_eq. Table 124.u32 %r.0.u32 %r. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.u32 %lanemask_eq. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2.sreg . . . mov. A predefined. %lanemask_le requires sm_20 or later.

Chapter 9. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge requires sm_20 or later.u32 %lanemask_gt. Introduced in PTX ISA version 2. mov.u32 %r. Introduced in PTX ISA version 2. %lanemask_ge. . %lanemask_gt requires sm_20 or later. A predefined. 2010 155 . %lanemask_gt. Table 126.u32 %lanemask_ge. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. .u32 %r. mov.sreg .0.0. Special Registers Table 125. A predefined. January 24. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg .

Special registers %pm0.sreg . . Supported on all target architectures.3. .%clock. %clock64 requires sm_20 or later.0 Table 127. . Introduced in PTX ISA version 1. %pm1. %pm1. and %pm3 are unsigned 32-bit read-only performance monitor counters. read-only 32-bit unsigned cycle counter. %pm2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.sreg .u32 %clock.sreg .%pm0.u64 r1. %pm3.PTX ISA Version 2. Introduced in PTX ISA version 1. 2010 . mov.u64 %clock64.0. Supported on all target architectures. Their behavior is currently undefined. ….u32 %pm0. Table 128.u32 r1. Special Registers: %pm0. %pm2.0. read-only 64-bit unsigned cycle counter. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. %pm2. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Table 129. Introduced in PTX ISA version 2. %pm3 %pm0. The lower 32-bits of %clock64 are identical to %clock. 156 January 24. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. mov.u32 r1.%clock64. %pm1. mov.

Supported on all target architectures. . minor are integers Specifies the PTX language version number.4 January 24.Chapter 10.version Syntax Description Semantics PTX version number.1. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. PTX File Directives: .0. Increments to the major number indicate incompatible changes to PTX. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.version major.version 1.version 2. 2010 157 .version directives are allowed provided they match the original . .target Table 130.0 .minor // major. Duplicate .version directive. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version .version . Each ptx file must begin with a . and the target architecture for which the code was generated. Directives 10.version directive. .

texmode_unified. The texturing mode is specified for an entire module and cannot be changed within the module.target directive specifies a single target architecture.samplerref descriptors. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.f64 instructions used. Therefore.texmode_unified) . 2010 .red}.texref descriptor. In general.5.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Requires map_f64_to_f32 if any . PTX File Directives: .target . sm_12.global. vote instructions. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.f64 to . Supported on all target architectures. 158 January 24. Introduced in PTX ISA version 1.texref and .f64 storage remains as 64-bits. with only half being used by instructions converted from . Adds double-precision support.0 Table 131.texmode_unified .global. PTX features are checked against the specified target architecture. map_f64_to_f32 }. 64-bit {atom. where each generation adds new features and retains all features of previous generations. texture and sampler information is referenced with independent . and an error is generated if an unsupported feature is used.target Syntax Architecture and Platform target. PTX code generated for a given target can be run on later generation devices. immediately followed by a . Disallows use of map_f64_to_f32. sm_13. sm_11. Target sm_20 Description Baseline feature set for sm_20 architecture.f32. Requires map_f64_to_f32 if any .red}. The following table summarizes the features in PTX that vary according to target architecture. Each PTX file must begin with a .target directives can be used to change the set of target features allowed during parsing. Description Specifies the set of features in the target architecture for which the current ptx code was generated.shared. Adds {atom. brkpt instructions. including expanded rounding modifiers. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. A . Texturing mode introduced in PTX ISA version 1. but subsequent . Note that . sm_10.0.texmode_independent texture and sampler information is bound together and accessed via a single . texmode_independent.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.PTX ISA Version 2. Texturing mode: (default is .f64 instructions used. . Requires map_f64_to_f32 if any .red}. A program with multiple .version directive.target directive containing a target architecture and optional platform options. generations of SM architectures follow an “onion layer” model. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Adds {atom.f64 instructions used.

target sm_13 // supports double-precision .Chapter 10.target sm_10 // baseline target architecture .target sm_20. Directives Examples . texmode_independent January 24. 2010 159 .

param.entry kernel-name kernel-body Defines a kernel entry point name.surfref variables may be passed as parameters. 2010 . PTX ISA Notes For PTX ISA version 1. etc. parameter variables are declared in the kernel parameter list.entry kernel-name ( param-list ) kernel-body .5 and later. ld.texref. .param .param { . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. parameters. 160 January 24.g. [y]. For PTX ISA versions 1. . Supported on all target architectures. opaque . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.b32 %r2. … } . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.param .0 through 1. Semantics Specify the entry point for a kernel program.param space memory and are listed within an optional parenthesized parameter list.b32 z ) Target ISA Notes Examples [x].samplerref. ld. and query instructions and cannot be accessed via ld.entry filter ( . .reg .func Table 132.param instructions. store. %nctaid. %ntid.entry . At kernel launch. Parameters may be referenced by name within the kernel body and loaded into registers using ld. The shape and size of the CTA executing the kernel are available in special registers.0 through 1. Kernel and Function Directives: .PTX ISA Version 2.2.b32 y.b32 %r1.param. and body for the kernel function.entry . In addition to normal parameters.entry cta_fft .4.entry Syntax Description Kernel entry point and body. . the kernel dimensions and properties are established and made available via special registers. parameter variables are declared in the kernel body.b32 x.0 10. with optional parameters.b32 %r<99>. e.b32 %r3.3. Parameters are passed via .param instructions. These parameters can only be referenced by name within texture and surface load. .4 and later. [z]. .param. and . ld.

and recursion is illegal.b32 rval.f64 dbl) { .param state space. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. and supports recursion. parameters must be in the register state space. PTX ISA 2.func fname function-body . } … call (fooval).func . Variadic functions are represented using ellipsis following the last fixed argument. Parameters must be base types in either the register or parameter state space. Parameter passing is call-by-value.func fname (param-list) function-body .0 with target sm_20 allows parameters in the . Kernel and Function Directives: . which may use a combination of registers and stack locations to pass parameters. Parameters in register state space may be referenced directly within instructions in the function body.param space are accessed using ld.b32 localVar. .2 for a description of variadic functions.param and st. (val0.func Syntax Function definition. there is no stack.x code. … Description // return value in fooval January 24. foo.func (ret-param) fname (param-list) function-body Defines a function. Variadic functions are currently unimplemented.Chapter 10. ret. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.reg . Release Notes For PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0 with target sm_20 supports at most one return value.b32 rval) foo (. if any. .func definition with no body provides a function prototype. val1). The parameter lists define locally-scoped variables in the function body. … use N.func (. implements an ABI with stack.reg . including input and return parameters and optional function body. dbl. . Directives Table 133. PTX 2.b32 N. A .result.param instructions in the body. 2010 161 . other code. Parameters in .reg . The implementation of parameter passing is left to the optimizing translator. mov. Supported on all target architectures.0.reg .

A general . Currently. The directives take precedence over any module-level constraints passed to the optimizing backend.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). The interpretation of .minnctapersm directives may be applied per-entry and must appear between an . 2010 . The directive passes a list of strings to the backend. and the strings have no semantics within the PTX virtual machine model. . 162 January 24. for example. to throttle the resource requirements (e. These can be used.maxntid .maxnreg. and .maxntid directive specifies the maximum number of threads in a thread block (CTA).maxnreg . .maxnctapersm (deprecated) .3.maxntid.pragma directive is supported for passing information to the PTX backend. and the .entry directive and its body.pragma The . or as statements within a kernel or device function body.pragma directives may appear at module (file) scope. PTX supports the following directives. the . The .g.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. at entry-scope. the . which pass information to the backend optimizing compiler.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxntid and .PTX ISA Version 2.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. Note that .0 10.minnctapersm . registers) to increase total thread count and provide a greater opportunity to hide memory latency.

maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid 256 .maxntid nx.maxntid nx.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. .maxntid and . Performance-Tuning Directives: .entry bar .maxctapersm. Supported on all target architectures. the backend may be able to compile to fewer registers.maxnreg .3.3.entry foo . The compiler guarantees that this limit will not be exceeded. nz Declare the maximum number of threads in the thread block (CTA). or 3D CTA.maxntid 16. Performance-Tuning Directives: . .Chapter 10.entry foo .16. Exceeding any of these limits results in a runtime error or kernel launch failure. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. This maximum is specified by giving the maximum extent of each dimention of the 1D. Introduced in PTX ISA version 1. 2010 163 .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid Syntax Maximum number of threads in thread block (CTA). The actual number of registers used may be less. ny. . 2D. for example. Supported on all target architectures. . The maximum number of threads is the product of the maximum extent in each dimension. Introduced in PTX ISA version 1.maxntid . ny . or the maximum number of registers may be further constrained by .maxntid nx . Directives Table 134.

minnctapersm generally need .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid 256 .maxnctapersm generally need .minnctapersm in PTX ISA version 2.maxntid 256 .maxntid to be specified as well. . For this reason. . additional CTAs may be mapped to a single multiprocessor.minnctapersm . Optimizations based on .maxntid and . The optimizing backend compiler uses . .0 as a replacement for . Introduced in PTX ISA version 2.entry foo .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). However. Supported on all target architectures. Performance-Tuning Directives: .maxnctapersm (deprecated) . 2010 .maxntid to be specified as well. if the number of registers used by the backend is sufficiently lower than this bound.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. Introduced in PTX ISA version 1. Optimizations based on .0.PTX ISA Version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.entry foo . Deprecated in PTX ISA version 2.maxnctapersm has been renamed to . .maxnctapersm. .3.minnctapersm 4 { … } 164 January 24. Supported on all target architectures.0.0 Table 136. Performance-Tuning Directives: .

// disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . { … } January 24.pragma .pragma list-of-strings .entry foo .Chapter 10. The interpretation of . or statement-level directives to the PTX backend compiler.pragma directive may occur at module-scope. . or at statementlevel.pragma directive strings is implementation-specific and has no impact on PTX semantics.0. Pass module-scoped. See Appendix A for descriptions of the pragma strings defined in ptxas. at entry-scope.pragma Syntax Description Pass directives to PTX backend compiler.pragma “nounroll”. Supported on all target architectures. Performance-Tuning Directives: . Directives Table 138. entry-scoped. The . 2010 165 . Introduced in PTX ISA version 2.pragma “nounroll”. .

quad int64-list // comma-separated hexadecimal integers in range [0.0 10. 0x00. Introduced in PTX ISA version 1. 0x00. 0x736d6172 . 0x00. 0x00 .. 0x00. 2010 .4byte int32-list // comma-separated hexadecimal integers in range [0..section .debug_info .byte 0x2b. Supported on all target architectures.232-1] .loc The . 0x61395a5f.0.2. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x63613031. Table 139.4byte 0x000006b5. 0x00000364.4.0 and replaces the @@DWARF syntax. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.file . @@DWARF dwarf-string dwarf-string may have one of the .section directive is new in PTX ISA verison 2.x code.section .PTX ISA Version 2. “”. 0x5f736f63 . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .byte byte-list // comma-separated hexadecimal byte values .264-1] .4byte label . @progbits .debug_pubnames. 0x00 166 January 24.4byte 0x6e69616d.section directive.0 but is supported for legacy PTX version 1. 0x00. 0x00. 0x6150736f. Deprecated as of PTX 2. replaced by . 0x02. The @@DWARF syntax is deprecated as of PTX version 2.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.4byte .byte 0x00.

0x5f736f63 0x6150736f.b32 int32-list // comma-separated list of integers in range [0. 0x00.0. Source file location.b32 .264-1] . 0x00.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .loc line_number January 24.file filename Table 142..b8 byte-list // comma-separated list of integers in range [0.debug_pubnames { .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.255] .file . . . 0x00. . 0x00..0.b8 0x2b.b32 0x6e69616d. . 0x63613031.section Syntax PTX section definition. Debugging Directives: .0. 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00 0x61395a5f. . Supported on all target architectures.section . 0x00000364.section section_name { dwarf-lines } dwarf-lines have the following formats: . } 0x02. . Supported on all target architectures..232-1] . Source file information. Supported on all target architectures.b32 label . Directives Table 140.b64 int64-list // comma-separated list of integers in range [0.b32 0x000006b5.debug_info . Debugging Directives: . Debugging Directives: .b8 0x00.loc . 0x00.section . 0x736d6172 0x00 Table 141. replaces @@DWARF syntax.Chapter 10. 2010 167 .

extern .visible .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. .PTX ISA Version 2. Linking Directives: . .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.b32 foo.0.0.extern .visible identifier Declares identifier to be externally visible. Supported on all target architectures.extern .visible Table 143. Supported on all target architectures.6.0 10.global .visible .b32 foo. . .extern identifier Declares identifier to be defined externally. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Linking Directives . // foo will be externally visible 168 January 24.global . // foo is defined in another module Table 144. Linking Directives: . 2010 .

2 CUDA 2.0 January 24. and the remaining sections provide a record of changes in previous releases. The release history is as follows.1 CUDA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.4 PTX ISA 1.3 PTX ISA 1.1 CUDA 2.0 CUDA 2.5 PTX ISA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 1. 2010 169 .0 PTX ISA 1.Chapter 11.3 driver r190 CUDA 3.0.0 driver r195 PTX ISA Version PTX ISA 1. CUDA Release CUDA 1.1 PTX ISA 1.2 PTX ISA 1.

• • • • • 170 January 24. rcp.rn.1.ftz and .ftz modifier may be used to enforce backward compatibility with sm_1x. fma.f32 and mad. New Features 11. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 requires sm_20.x code and sm_1x targets. mad. Instructions testp and copysign have been added.0 for sm_20 targets. Single. The mad.f32 instruction also supports . Floating-Point Extensions This section describes the floating-point changes in PTX 2.sat modifiers. Single-precision add.rp rounding modifiers for sm_20 targets. and mul now support . Both fma.1. sub. The . Changes in Version 2. These are indicated by the use of a rounding modifier and require sm_20.1.1.f32 maps to fma.f32 require a rounding modifier for sm_20 targets. The fma.1.rm and .PTX ISA Version 2.1.0 11. and sqrt with IEEE 754 compliant rounding have been added. 2010 . A single-precision fused multiply-add (fma) instruction has been added.f32.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 11. The mad.f32 for sm_20 targets. The goal is to achieve IEEE 754 compliance wherever possible. When code compiled for sm_1x is executed on sm_20 devices.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. while maximizing backward compatibility with legacy PTX 1.and double-precision div.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The changes from PTX ISA 1.

zero. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.add. popc. . New special registers %nsmid. has been added. A “find leading non-sign bit” instruction.gt} have been added. st.popc.b32. A new directive. and sust. and red now support generic addressing.sys. The bar instruction has been extended as follows: • • • A bar.1. Video instructions (includes prmt) have been added. . Instructions prefetch and prefetchu have also been added.1. and shared addresses to generic address and vice-versa has been added. membar. prefetchu. New instructions A “load uniform” instruction. has been added.g. atom. Other new features Instructions ld. prefetch.f32 have been implemented.{and. January 24. st. clz. vote.red. bar now supports optional thread count and register operands.shared have been extended to handle 64-bit data types for sm_20 targets.ge. local.clamp modifiers.red. ldu. bfind. bfe and bfi. has been added. %clock64.2. Instruction cvta for converting global. Release Notes 11. 2010 171 .or}. A “count leading zeros” instruction.3.u32 and bar. The . isspacep. Instructions {atom.red}.maxnctapersm directive was deprecated and replaced with .lt. 11. Instructions bar. Surface instructions support additional . Instruction sust now supports formatted surface stores. cvta. Bit field extract and insert instructions.arrive instruction has been added. A “bit reversal” instruction.Chapter 11. A “vote ballot” instruction. A “population count” instruction.ballot. e.pred have been added.le. has been added.minnctapersm to better match its behavior and usage. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added. have been added.clamp and .1.red}. has been added. A system-level membar instruction. %lanemask_{eq. Cache operations have been added to instructions ld. Instructions {atom. suld.section. ldu. brev. has been added. for prefetching to specified level of memory hierarchy.1.

PTX ISA Version 2.ftz (and cvt for .3.f32} atom.2.version is 1.5 and later.{min. if .p sust. .5.f32 type is unimplemented.1. 172 January 24. call suld. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.u32. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.f32. See individual instruction descriptions for details. where . 2010 . or .max} are not implemented. Formatted surface load is unimplemented. the correct number is sixteen. Semantic Changes and Clarifications The errata in cvt.red}.4 or earlier. 11.{u32.4 and earlier. In PTX version 1. cvt. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.p. stack-based ABI is unimplemented.s32. To maintain compatibility with legacy PTX code. has been fixed.0 11.ftz for PTX ISA versions 1. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.s32.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. Formatted surface store with . Support for variadic functions and alloca are unimplemented. {atom. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. The underlying. Instruction bra.1.target sm_1x.

Descriptions of . and statement levels. Ignored for sm_1x targets.pragma “nounroll”. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.pragma.entry foo (…) . … @p bra L1_end. 2010 173 . .pragma Strings This section describes the . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. including loops preceding the . The “nounroll” pragma is allowed at module. Table 145.0. L1_body: … L1_continue: bra L1_head. disables unrolling of0 the loop for which the current block is the loop header. entry-function. L1_end: … } // do not unroll this loop January 24. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. . { … } // do not unroll any loop in this function .pragma “nounroll”. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma strings defined by ptxas. Supported only for sm_20 targets.func bar (…) { … L1_head: . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. disables unrolling for all loops in the entry function body.pragma “nounroll”. Note that in order to have the desired effect at statement level.Appendix A.

0 174 January 24. 2010 .PTX ISA Version 2.

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