NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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........................................................................ Types........................................................ Sampler................................................................. 34 Variables .....2...................................................1.... 5............................4.........4. 42 Addresses as Operands ............................................................. State Spaces .1.............................................1............. 49 ii January 24............ 32 Texture State Space (deprecated) .... 5.................. 5........... 6.......6.1.................................4......................................2..... 5............................... 6.......... 5...... 6....6.......................... 27 5................5...................................... 25 Chapter 5............. 5...................................... 46 6.. 41 Using Addresses.............................5............. 32 5... 5.........................................PTX ISA Version 2.........1............ and Surface Types ................ 33 Restricted Use of Sub-Word Sizes ................................. 6...................4.......4............................... State Spaces............................. 2010 ...........................1................. Type Conversion.................... 38 Initializers ..........5.......................... Abstracting the ABI ...................4........2..........8... 42 Arrays as Operands ................1.............................................5.................2......... 43 6...............1.. 6...................................................................................................0 4.............................. 49 7................ Function declarations and definitions .....................1......... and Vectors .... 6.. 39 Parameterized Variable Names .........4.....2......................5...................... 39 5....................................3............1.........4....................................................................... 44 Rounding Modifiers ..............2......................3............................ Types ...........................1.......2.............................................................................................................................................. Operand Costs ................. 37 Array Declarations ...... 5..............................6............................................................. Arrays..................... 28 Special Register State Space ..................................................................................................................... 5.................................. 5.. 41 Destination Operands ............ 27 Register State Space ...... 29 Parameter State Space .................................... 41 Source Operands...................5.................................................. 5....1.................................................................2.......................1....... 37 Variable Declarations .... 44 Scalar Conversions .................................. 5......4.6............................................................. 6.......... 5........................... 41 6.................................................. 33 5..........1..................................................................... 37 Vectors . and Variables ..... 47 Chapter 7.................. 5........................................................ Instruction Operands.......................4....... Summary of Constant Expression Evaluation Rules ........................................... 6......................................3.................................................................................................7....................1......................................................................................3................................................1............4................. 43 Vectors as Operands .....2.. Texture...........................4......................... 5.............. 30 Shared State Space........................... 43 Labels and Function Names as Operands .3............................................... 29 Global State Space ................................ 6........... 28 Constant State Space ................... 33 Fundamental Types ...........4...... Chapter 6..4.................................... 5....................................................................... Operand Type Information . 38 Alignment ..............................................4.... 29 Local State Space .....................................

................................................................. 104 Data Movement and Conversion Instructions ..... 157 10............................................. 170 New Features ....................7..........................2.......................................................... 11..................... 10.............. 147 8............ Changes from PTX 1.............1...................1........7..................................... Release Notes ....1.........................7....2.... 157 Specifying Kernel Entry Points and Functions ................................... 10................................................6.................................................................................................... 8................................................... 59 Operand Size Exceeding Instruction-Type Size ............................................. 63 Integer Arithmetic Instructions ...... 100 Logic and Shift Instructions ...............1............................ 63 Floating-Point Instructions ................2................ PTX Version and Target Directives .2...........................6................... Special Registers ........................................................1.3..........7..........x .............1................................... 10.......................2.......................... 8... 52 Variadic functions ........ 53 Alloca ...................6.......... 8........................................................................................................... 55 8.....................................7..................7.............................5.... 7.....7............ 62 Machine-Specific Semantics of 16-bit Code ...................... 81 Comparison and Selection Instructions ..... 8.. Changes in Version 2.................. 162 Debugging Directives .............3............................................................................................6....... 7............ 129 Parallel Synchronization and Communication Instructions ...... 122 Control Flow Instructions .................................2...............................................8........................................3....3..... 8.. 108 Texture and Surface Instructions ......... 8........................................................................ 11.3............. 8............... 8...... Instructions ............................................... 2010 iii ....................................................................7...... 60 8.......... 10.......................................... Type Information for Instructions and Operands ........... 8......................................... Divergence of Threads in Control Constructs .......9................................................................................1..........3.........................................4...............1........................... 56 Comparisons ............................................. 170 Semantic Changes and Clarifications ..1...................................1...............4.. 172 January 24.1..............................................7...........................7... 57 Manipulating Predicates ........ Instruction Set . 172 Unimplemented Features Remaining ......................4................................. 58 8......... 8.......................... 55 Predicated Execution .......... 62 Semantics .......7...... 8....... 169 11. 8....... 55 PTX Instructions .....................7... Format and Semantics of Instruction Descriptions ..3........................... Directives ................ 8................ 8..... 168 Chapter 11............................. 149 Chapter 10....................5............ 166 Linking Directives .......10............ Chapter 9.......................................................................................................................................................0 ....................... 8.......................................... 8.........................7....................................... 62 8................4............... 11......1.................................................................................... 160 Performance-Tuning Directives ................................................... 132 Video Instructions ..........1............................................................................................ 140 Miscellaneous Instructions....................................... 54 Chapter 8...............................................

................. 2010 .0 Appendix A..................................pragma Strings...... Descriptions of ..PTX ISA Version 2... 173 iv January 24.....

......... Table 18.................cc ................ Table 5... 46 Cost Estimates for Accessing State-Spaces ............. 58 Type Checking Rules .........List of Tables Table 1................... 57 Floating-Point Comparison Operators ................................... and Bit-Size Types .................................................................................................... Table 22... 35 Opaque Type Fields in Independent Texture Mode ....................... Table 17............................. Table 21...... 25 State Spaces ....................................... 57 Floating-Point Comparison Operators Accepting NaN .................................................... Table 4................................................... Table 12............................................................................................ 64 Integer Arithmetic Instructions: add............ Table 6............. 66 Integer Arithmetic Instructions: mul ................................. 71 January 24................................................................... 45 Floating-Point Rounding Modifiers ......................................... 19 Predefined Identifiers ............. Unsigned Integer......................... Table 8.......... Table 15............................................................. Table 28........................................................... Table 31................................. Table 3..................................................................................................... Table 26............................... Table 25............................................... Table 16............. 66 Integer Arithmetic Instructions: subc ............. 68 Integer Arithmetic Instructions: mul24 ... Table 14................................ 20 Operator Precedence .... 61 Integer Arithmetic Instructions: add ..................... Table 23.......................... PTX Directives .. 59 Relaxed Type-checking Rules for Source Operands ...................................................................................................... 60 Relaxed Type-checking Rules for Destination Operands................................. 69 Integer Arithmetic Instructions: mad24 ................ Table 19................................................. 33 Opaque Type Fields in Unified Texture Mode ..... 47 Operators for Signed Integer.......................... Table 30.................. 27 Properties of State Spaces .......... 46 Integer Rounding Modifiers ............................. Table 7............................ 2010 v ..................................................................................... Table 9........ Table 11.... 65 Integer Arithmetic Instructions: addc ................................... 58 Floating-Point Comparison Operators Testing for NaN ............... 70 Integer Arithmetic Instructions: sad .......................................... 35 Convert Instruction Precision and Format ................................................. Table 10......................................... 64 Integer Arithmetic Instructions: sub ............................................. 28 Fundamental Type Specifiers ................................ Table 13.................................... 67 Integer Arithmetic Instructions: mad ............. 23 Constant Expression Evaluation Rules ....................... Table 29...................................... 18 Reserved Instruction Keywords ....................... Table 20...cc ........................ Table 32................................ Table 27............................................... 65 Integer Arithmetic Instructions: sub.................................... Table 2........................................................ Table 24.......................................................................................................................................................

................ Table 44..................... Table 69........ Table 55........................... Table 36............. 72 Integer Arithmetic Instructions: min ...... Table 47.......................................... Table 67.................................................. 96 Floating-Point Instructions: cos ................................ Table 52.......................................................................................... 86 Floating-Point Instructions: fma .................... 71 Integer Arithmetic Instructions: rem ..................................................... 73 Integer Arithmetic Instructions: popc ................................................................................................. 83 Floating-Point Instructions: copysign .................................................................................... Table 48.................. 87 Floating-Point Instructions: mad .................... Table 54............ 71 Integer Arithmetic Instructions: abs ................................................................. 103 vi January 24.... 77 Integer Arithmetic Instructions: bfi ................ 98 Floating-Point Instructions: ex2 ..................................................................................................................... Integer Arithmetic Instructions: div .............................PTX ISA Version 2... 88 Floating-Point Instructions: div ........................... 76 Integer Arithmetic Instructions: bfe ......................... 90 Floating-Point Instructions: abs ...........................................................0 Table 33....................................... Table 50.................................. Table 49. 101 Comparison and Selection Instructions: setp ....................................... 102 Comparison and Selection Instructions: selp ............................................................................................................................. Table 51......................... Table 60............................................................ 78 Integer Arithmetic Instructions: prmt ................................................................ 75 Integer Arithmetic Instructions: brev ..... 97 Floating-Point Instructions: lg2 ......................... Table 53........... 74 Integer Arithmetic Instructions: clz ............................................................................... Table 37.......... Table 61.. Table 42......................... 72 Integer Arithmetic Instructions: neg ............ Table 59................................................... 103 Comparison and Selection Instructions: slct ... Table 38........ 83 Floating-Point Instructions: add ......................................................................................................................... Table 56.. Table 41... Table 57.................................................................... Table 66. 92 Floating-Point Instructions: rcp ................................ Table 40..... 99 Comparison and Selection Instructions: set ..................................................................................................... 93 Floating-Point Instructions: sqrt ....... 91 Floating-Point Instructions: neg .................................. Table 65...................................................... 94 Floating-Point Instructions: rsqrt ............................. 73 Integer Arithmetic Instructions: max .................. Table 43.................. 74 Integer Arithmetic Instructions: bfind ..................... 79 Summary of Floating-Point Instructions ............................................................... Table 45...................... Table 68....................................................................................................................................................................... Table 39.................................. 92 Floating-Point Instructions: max ..... 95 Floating-Point Instructions: sin .......... 82 Floating-Point Instructions: testp .................................. 2010 ............ Table 63.............................................. 84 Floating-Point Instructions: sub ................................................................. Table 64........................................ Table 34........... Table 46............................................................ 85 Floating-Point Instructions: mul ..................................... Table 62........... Table 58............................. 91 Floating-Point Instructions: min ............................ Table 35....................................................

................... 131 Parallel Synchronization and Communication Instructions: bar ..... Table 86.................. Table 99................................... 107 Logic and Shift Instructions: shr ................................................................. Table 74............................................................................................. 105 Logic and Shift Instructions: xor .................................................. 119 Data Movement and Conversion Instructions: cvta ............. Table 71............................. 130 Control Flow Instructions: ret .................... 126 Texture and Surface Instructions: sured............................ Table 100...... Table 98........................... Table 88.................................................. Table 105......................... Logic and Shift Instructions: and ....................... 113 Data Movement and Conversion Instructions: ldu ........................................ 142 Video Instructions: vshl........................ 109 Cache Operators for Memory Store Instructions ......... Table 87......... Table 102...................................................... Table 103................. vmin.................................................................................... Table 85..... 2010 vii .. Table 73.................... Table 81...... Table 106............. 135 Parallel Synchronization and Communication Instructions: red .. Table 79.................................. Table 91............................ 106 Logic and Shift Instructions: shl ............................... Table 82............................................ Table 78................... 130 Control Flow Instructions: call .................. Table 83........................................ Table 90........................................................ 131 Control Flow Instructions: exit .............................................. 129 Control Flow Instructions: @ .............. Table 75........... Table 95....................... 119 Data Movement and Conversion Instructions: cvt ....................................................... Table 84...... 129 Control Flow Instructions: bra ............................................................................ 116 Data Movement and Conversion Instructions: prefetch.......... 137 Parallel Synchronization and Communication Instructions: vote .................................. vshr ............................ Table 104.................... 123 Texture and Surface Instructions: txq ................................... prefetchu .......... Table 77............... 107 Cache Operators for Memory Load Instructions ........................................ 133 Parallel Synchronization and Communication Instructions: membar ............................ Table 72... 111 Data Movement and Conversion Instructions: mov ....................... 143 January 24........................................................... vsub............... Table 80.................................. vmax ... Table 94.........................Table 70.................................................................. Table 101............. 106 Logic and Shift Instructions: cnot ............................ 118 Data Movement and Conversion Instructions: isspacep ............... 127 Texture and Surface Instructions: suq ... 115 Data Movement and Conversion Instructions: st .... Table 97........ 139 Video Instructions: vadd.................. 110 Data Movement and Conversion Instructions: mov ...... 106 Logic and Shift Instructions: not .......................... 112 Data Movement and Conversion Instructions: ld ......... Table 92... 124 Texture and Surface Instructions: suld ..................... 105 Logic and Shift Instructions: or ... 128 Control Flow Instructions: { } ...... 120 Texture and Surface Instructions: tex .................................................................................................. Table 89................................................ vabsdiff.............. 125 Texture and Surface Instructions: sust ............................ Table 76..................... Table 93.................. 134 Parallel Synchronization and Communication Instructions: atom ......... Table 96..........................................................................................

... 150 Special Registers: %laneid .......... 147 Miscellaneous Instructions: brkpt ....... Table 124.................................................................................. 167 Debugging Directives: .................... Table 138................... Table 111.... Table 127.... 164 Performance-Tuning Directives: ........... 153 Special Registers: %lanemask_eq ............................ Table 140....PTX ISA Version 2......................func .................. 158 Kernel and Function Directives: .......................... 164 Performance-Tuning Directives: ............................ Table 143.............................................................. 166 Debugging Directives: ....................... Table 121....... 147 Miscellaneous Instructions: pmevent.......................................... Table 120....... 155 Special Registers: %clock ........................................................................................ 163 Performance-Tuning Directives: ............target .................. Table 137......................................... Table 114......................................................................................................... 154 Special Registers: %lanemask_ge ....... Table 116....................... Table 113.......... 156 PTX File Directives: ...................................................................................maxnreg ............................... %pm2........... Table 129..................... 152 Special Registers: %smid ................................................... 157 PTX File Directives: ........................................ 154 Special Registers: %lanemask_le .... 144 Video Instructions: vset...............................................loc ...................................... Table 108................ %pm1..................................... Table 139.....minnctapersm .............................. 155 Special Registers: %lanemask_gt .......................................................................................................... Table 119.............. Table 128................................................. Table 133.................................... 146 Miscellaneous Instructions: trap ............ Table 134....................................... Video Instructions: vmad ......... Table 135...extern........................................................................................... 154 Special Registers: %lanemask_lt ............................................... 147 Special Registers: %tid .......... 165 Debugging Directives: @@DWARF ........................ Table 130.......................................................................................................................... Table 141.............................. 150 Special Registers: %ntid . Table 132.......... 153 Special Registers: %nsmid ................................................. Table 118............................................... Table 115... 167 Debugging Directives: ............................ 151 Special Registers: %warpid .......section .......................................................pragma ............................... 160 Kernel and Function Directives: ...... 167 Linking Directives: .......................................................... %pm3 ...maxnctapersm (deprecated) ................ 163 Performance-Tuning Directives: ............................................. Table 112..........maxntid ............... 161 Performance-Tuning Directives: ............................................ 2010 .......................... Table 123........................ Table 125......file .......................... Table 126................entry............... 153 Special Registers: %gridid ...............................................0 Table 107.. Table 122... Table 131......... Table 142.............................. 156 Special Registers: %pm0.............................. Table 109................................................ 156 Special Registers: %clock64 ............................ 168 viii January 24...................................... 151 Special Registers: %ctaid ............................ 152 Special Registers: %nctaid ..................... Table 136........ Table 117................................................................................... Table 110.................. 151 Special Registers: %nwarpid ............................................................version.........

...................... 173 January 24..........................................visible................................ Linking Directives: .................Table 144.......................... 168 Pragma Strings: “nounroll” .... Table 145.. 2010 ix ..........................

0 x January 24. 2010 .PTX ISA Version 2.

multithreaded. which are optimized for and translated to native target-architecture instructions. 2010 1 . Similarly. high-definition 3D graphics. In fact. Data-parallel processing maps data elements to parallel processing threads. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. January 24. PTX programs are translated at install time to the target hardware instruction set. there is a lower requirement for sophisticated flow control. 1. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. from general signal processing or physics simulation to computational finance or computational biology. image and media processing applications such as post-processing of rendered images. and because it is executed on many data elements and has high arithmetic intensity. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. stereo vision. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.Chapter 1. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. video encoding and decoding. the programmable GPU has evolved into a highly parallel. 1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). PTX defines a virtual machine and ISA for general purpose parallel thread execution. Because the same program is executed for each data element. and pattern recognition can map image blocks and pixels to parallel processing threads.2. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. the memory access latency can be hidden with calculations instead of big data caches. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth. PTX exposes the GPU as a data-parallel computing device.1. image scaling. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Introduction This document describes PTX.

3.x. Provide a code distribution ISA for application and middleware developers. A single-precision fused multiply-add (fma) instruction has been added.ftz and . When code compiled for sm_1x is executed on sm_20 devices. Facilitate hand-coding of libraries.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. reduction.0 are improved support for IEEE 754 floating-point operations.f32 instruction also supports . and mul now support . surface.sat modifiers. addition of generic addressing to facilitate the use of general-purpose pointers. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. Most of the new features require a sm_20 target. performance kernels. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.f32. fma. Provide a machine-independent ISA for C/C++ and other compilers to target.x code will continue to run on sm_1x targets as well. and all PTX 1. PTX ISA Version 2.f32 require a rounding modifier for sm_20 targets. memory.PTX ISA Version 2. The fma.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. Instructions marked with .f32 requires sm_20. and the introduction of many new instructions. including integer. Both fma. A “flush-to-zero” (. atomic.x features are supported on the new sm_20 target.f32 maps to fma.rn. and architecture tests. Improved Floating-Point Support A main area of change in PTX 2.ftz) modifier may be used to enforce backward compatibility with sm_1x. Legacy PTX 1. Single-precision add. The mad. barrier.0 is a superset of PTX 1.0 is in improved support for the IEEE 754 floating-point standard. sub.0 PTX ISA Version 2.f32 and mad.3. 1. The mad. The main areas of change in PTX 2. 1. Achieve performance in compiled applications comparable to native GPU performance. The changes from PTX ISA 1. 2010 . with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. PTX 2.rm and .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. which map PTX to specific target machines. Provide a common source-level ISA for optimizing code generators and translators.1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 for sm_20 targets. mad. and video instructions.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. • • • 2 January 24.rp rounding modifiers for sm_20 targets.

e. and red now support generic addressing. prefetch. instructions ld.3.clamp and . suld. isspacep.and double-precision div. and shared state spaces. st. and directives are introduced in PTX 2. so recursion is not yet supported. cvta. local. special registers. rcp. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.3. In PTX 2. e. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Support for an Application Binary Interface Rather than expose details of a particular calling convention. stack layout. Instructions testp and copysign have been added. and sust. for prefetching to specified level of memory hierarchy. January 24. 1.0.. local. atom. and shared addresses to generic address and vice-versa has been added. 1.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. st.0.Chapter 1. i. an address that is the same across all threads in a warp. allowing memory instructions to access these spaces without needing to specify the state space. A new cvta instruction has been added to convert global. 1. Generic addressing unifies the global.g. PTX 2.3.0 closer to full compliance with the IEEE 754 standard. and vice versa. Surface instructions support additional clamp modifiers. Instruction cvta for converting global. and Application Binary Interface (ABI). New Instructions The following new instructions. Generic Addressing Another major change is the addition of generic addressing. stack-based ABI. • Taken as a whole.zero. and sqrt with IEEE 754 compliant rounding have been added. Introduction • Single. Surface Instructions • • Instruction sust now supports formatted surface stores. These are indicated by the use of a rounding modifier and require sm_20. 2010 3 . Cache operations have been added to instructions ld. and shared addresses to generic addresses. Instructions prefetch and prefetchu have been added. ldu.3. NOTE: The current version of PTX does not implement the underlying. these changes bring PTX 2.4. local. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. prefetchu.2. .

le.gt} have been added.or}.PTX ISA Version 2. A new directive. Instructions {atom. %lanemask_{eq. 4 January 24.{and. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.arrive instruction has been added. has been added.popc.shared have been extended to handle 64-bit data types for sm_20 targets. .red}. Instructions bar. membar.sys.section. Reduction. 2010 .f32 have been added.u32 and bar. bfi bit field extract and insert popc clz Atomic. New special registers %nsmid. has been added. %clock64.lt.ballot. and Vote Instructions • • • New atomic and reduction instructions {atom.red}.red.add. Other Extensions • • • Video instructions (includes prmt) have been added. vote.red. A bar.ge. Barrier Instructions • • A system-level membar instruction.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. A “vote ballot” instruction.pred have been added. bar now supports an optional thread count and register operands.b32.

Chapter 1. Chapter 9 lists special registers. calling convention. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 5 describes state spaces. Introduction 1.0. and variable declarations. Chapter 3 gives an overview of the PTX virtual machine model. 2010 5 . Chapter 4 describes the basic syntax of the PTX language.4. Chapter 6 describes instruction operands. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 8 describes the instruction set. types. Chapter 10 lists the assembly directives supported in PTX. January 24. Chapter 11 provides release notes for PTX Version 2. Chapter 7 describes the function and call syntax.

2010 .PTX ISA Version 2.0 6 January 24.

compute-intensive portions of applications running on the host are off-loaded onto the device. a portion of an application that is executed many times. and select work to perform.y. A cooperative thread array. ntid. but independently on different data.z). 2. and ntid.1.2. data-parallel.y.x. or CTA. Each CTA has a 1D. Cooperative thread arrays (CTAs) implement CUDA thread blocks. or 3D CTA. The vector ntid specifies the number of threads in each CTA dimension.Chapter 2. The thread identifier is a three-element vector tid. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. To coordinate the communication of the threads within the CTA. (with elements tid. is an array of threads that execute a kernel concurrently or in parallel. January 24.z) that specifies the thread’s position within a 1D. 2D. Threads within a CTA can communicate with each other.x. 2. or host: In other words.1. Each thread has a unique thread identifier within the CTA. 2D. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. one can specify synchronization points where threads wait until all threads in the CTA have arrived. Programming Model 2. tid. and results across the threads of the CTA. can be isolated into a kernel function that is executed on the GPU as many different threads. Programs use a data parallel decomposition to partition inputs. 2010 7 . and tid. More precisely. or 3D shape specified by a three-element vector ntid (with elements ntid. assign specific input and output positions. To that effect. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.2. compute addresses. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. It operates as a coprocessor to the main CPU. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Each CTA thread uses its thread identifier to determine its assigned role. work.

or sequentially. Typically. %nctaid. or 3D shape specified by the parameter nctaid. because threads in different CTAs cannot communicate and synchronize with each other. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. This comes at the expense of reduced thread communication and synchronization. Some applications may be able to maximize performance with knowledge of the warp size. depending on the platform. Each grid of CTAs has a 1D. so PTX includes a run-time immediate constant.PTX ISA Version 2.0 Threads within a CTA execute in SIMT (single-instruction. such that the threads execute the same instructions at the same time. a warp has 32 threads. so that the total number of threads that can be launched in a single kernel invocation is very large. %ctaid. 2D . WARP_SZ. However.2. CTAs that execute the same kernel can be batched together into a grid of CTAs. The host issues a succession of kernel invocations to the device. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. The warp size is a machine-dependent constant. 2. which may be used in any instruction where an immediate operand is allowed. A warp is a maximal subset of threads from a single CTA.2. 2010 . Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). %ntid. Each grid also has a unique temporal grid identifier (gridid). and %gridid. multiple-thread) fashion in groups called warps. Multiple CTAs may execute concurrently and in parallel. read-only special registers %tid. 8 January 24. Threads within a warp are sequentially numbered. Threads may read and use these values through predefined.

1) Thread (3. 1) CTA (2. 0) Thread (3. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (1.Chapter 2. 2) Thread (2. 0) CTA (0. 2) Thread (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (0. 1) Thread (1. 0) CTA (1. 0) CTA (2. 1) Thread (4. 1) CTA (1. Thread Batching January 24. 1) Thread (0. 1) Grid 2 Kernel 2 CTA (1. 1) Thread (2. 2010 9 . Figure 1. 0) Thread (0. 0) Thread (2. 2) Thread (3. 2) Thread (4. A grid is a set of CTAs that execute independently. 0) Thread (4.

for some specific data formats. and texture memory spaces are persistent across kernel launches by the same application. all threads have access to the same global memory. Each thread has a private local memory. 2010 . The device memory may be mapped and read or written by the host. Finally. constant. referred to as host memory and device memory. 10 January 24. Both the host and the device maintain their own local memory. and texture memory spaces are optimized for different memory usages. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global.3. or. constant. respectively. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. for more efficient transfer.0 2. The global.PTX ISA Version 2. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Texture memory also offers different addressing modes. as well as data filtering. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.

2) Block (1. 0) Block (0. 0) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (1. 1) Grid 1 Global memory Block (0. 0) Block (1. 2) Figure 2. 0) Block (2. 2010 11 . 1) Block (2. 1) Block (1. 0) Block (0. Memory Hierarchy January 24.Chapter 2. 1) Block (0.

2010 .PTX ISA Version 2.0 12 January 24.

increasing thread IDs with the first warp containing thread 0. and on-chip shared memory. Branch divergence occurs only within a warp. To manage hundreds of threads running several different programs. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). January 24. a multithreaded instruction unit. The way a block is split into warps is always the same. the warp serially executes each branch path taken. It implements a single-instruction barrier synchronization. for example. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. disabling threads that are not on that path. a cell in a grid-based computation). multiple-thread). When a multiprocessor is given one or more thread blocks to execute. the first parallel thread technology. the threads converge back to the same execution path. and each scalar thread executes independently with its own instruction address and register state.1. (This term originates from weaving. a voxel in a volume. If threads of a warp diverge via a data-dependent conditional branch. When a host program invokes a kernel grid.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. new blocks are launched on the vacated multiprocessors. manages. and executes concurrent threads in hardware with zero scheduling overhead. and when all paths complete. each warp contains threads of consecutive. so full efficiency is realized when all threads of a warp agree on their execution path. The multiprocessor creates. As thread blocks terminate. different warps execute independently regardless of whether they are executing common or disjointed code paths. Parallel Thread Execution Machine Model 3. At every instruction issue time. and executes threads in groups of parallel threads called warps. A multiprocessor consists of multiple Scalar Processor (SP) cores. A warp executes one common instruction at a time. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp.Chapter 3. The multiprocessor maps each thread to one scalar processor core. The threads of a thread block execute concurrently on one multiprocessor. 2010 13 . The multiprocessor SIMT unit creates. schedules. it splits them into warps that get scheduled by the SIMT unit. manages. the multiprocessor employs a new architecture we call SIMT (single-instruction. allowing.

How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each read. the kernel will fail to launch. 2010 . however. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. • The local and global memory spaces are read-write regions of device memory and are not cached. which is a read-only region of device memory. whereas SIMT instructions specify the execution and branching behavior of a single thread. 14 January 24. Vector architectures. the number of serialized writes that occur to that location and the order in which they occur is undefined. A multiprocessor can execute as many as eight thread blocks concurrently.PTX ISA Version 2. For the purposes of correctness. As illustrated by Figure 3. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. which is a read-only region of device memory. If there are not enough registers or shared memory available per multiprocessor to process at least one block. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. on the other hand. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. as well as data-parallel code for coordinated threads. but the order in which they occur is undefined. the programmer can essentially ignore the SIMT behavior. but one of the writes is guaranteed to succeed. In contrast with SIMD vector machines. modifies. A key difference is that SIMD vector organizations expose the SIMD width to the software. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. and writes to the same location in global memory for more than one of the threads of the warp. require the software to coalesce loads into vectors and manage divergence manually. modify. SIMT enables programmers to write thread-level parallel code for independent. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. write to that location occurs and they are all serialized. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. If an atomic instruction executed by a warp reads.0 SIMT architecture is akin to SIMD (Single Instruction. In practice. scalar threads.

Hardware Model January 24. 2010 15 .Chapter 3. Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

0 16 January 24. 2010 .PTX ISA Version 2.

#else. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Lines beginning with # are preprocessor directives. January 24. and using // to begin a comment that extends to the end of the current line. #define. followed by a . The following are common preprocessor directives: #include. Comments Comments in PTX follow C/C++ syntax. Comments in PTX are treated as whitespace. #if. All whitespace characters are equivalent. 4. Syntax PTX programs are a collection of text source files. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.version directive specifying the PTX language version. whitespace is ignored except for its use in separating tokens in the language. #endif. Each PTX file must begin with a . PTX is case sensitive and uses lowercase for keywords. Source Format Source files are ASCII text. using non-nested /* and */ for comments that may span multiple lines.target directive specifying the target architecture assumed. 4. Pseudo-operations specify symbol and addressing management. The C preprocessor cpp may be used to process PTX source files.Chapter 4.2. #line. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. See Section 9 for a more information on these directives. 2010 17 . #ifdef.1. Lines are separated by the newline character (‘\n’).

b32 add.visible 4.maxnreg . All instruction keywords are reserved tokens in PTX. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. 0.5. followed by source operands.reg . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.version .0 4.3. Table 1. . and is written as @p. constant expressions. 2010 . r2. The destination operand is first. Statements A PTX statement is either a directive or an instruction. The guard predicate may be optionally negated. r1. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.local .b32 r1.3.shared .x.PTX ISA Version 2.extern . Examples: . so no conflict is possible with user-defined identifiers.f32 array[N].const .target . The guard predicate follows the optional label and precedes the opcode. 2. r2. Instructions have an optional guard predicate which controls conditional execution.global .entry . array[r1].maxnctapersm .func . address expressions.section .param . or label names.file PTX Directives .global start: . Statements begin with an optional label and end with a semicolon. . where p is a predicate register.3.loc . Directive Statements Directive keywords begin with a dot. Instruction keywords are listed in Table 2.align .pragma . and terminated with a semicolon.2.tex . written as @!p. %tid. r2.minnctapersm .b32 r1.maxntid .b32 r1.global.reg . Operands may be register variables. shl. mov.1. 18 January 24. ld.sreg .f32 r2.

Syntax Table 2.Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

PTX ISA Version 2. PTX predefines one constant and a small number of special registers that begin with the percentage sign. Many high-level languages such as C and C++ follow similar rules for identifier names. digits. or they start with an underscore. or dollar characters.g. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. %pm3 WARP_SZ 20 January 24. between user-defined variable names and compiler-generated names. digits. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. underscore. PTX allows the percentage sign as the first character of an identifier. listed in Table 3. or percentage character followed by one or more letters. underscore. except that the percentage sign is not allowed. e.4. The percentage sign can be used to avoid name conflicts. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. dollar.0 4. Table 3. …. 2010 .

Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. in which case the literal is unsigned (.5. To specify IEEE 754 doubleprecision floating point values. the sm_1x and sm_20 targets have a WARP_SZ value of 32. the constant begins with 0f or 0F followed by 8 hex digits. i. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. octal.2. there is no suffix letter to specify size. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. 4. Integer literals may be written in decimal. every integer constant has type . such values retain their exact 32-bit single-precision value and may not be used in constant expressions. 4.s64) unless the value cannot be fully represented in . i.5.. Syntax 4. literals are always represented in 64-bit double-precision format. When used in an instruction or data initialization.Chapter 4. each integer constant is converted to the appropriate size based on the data or instruction type at its use.s64 or . Floating-point literals may be written with an optional decimal point and an optional signed exponent. To specify IEEE 754 single-precision floating point values. zero values are FALSE and non-zero values are TRUE.e. the constant begins with 0d or 0D followed by 16 hex digits. integer constants are allowed and are interpreted as in C.1. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. 2010 21 . Constants PTX supports integer and floating-point constants and constant expressions. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. These constants may be used in data initialization and as operands to instructions. hexadecimal.e.s64 or the unsigned suffix is specified.. where the behavior of the operation depends on the operand types. or binary notation. The syntax follows that of C. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. floating-point.u64.u64). Unlike C and C++. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Type checking rules remain the same for integer. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. and bit-size types.5. For predicate-type data and instructions.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

s64 . Table 5.s64 .u64 .s64) + . 2010 25 . Syntax 4.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 .f64 : .u64. . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64 .s64 .u64 1st unchanged.s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 use usual conversions .s64 .s64 .u64 same as 1st operand .6.f64 converted type constant literal + ! ~ Cast Binary (.s64 .u64 .f64 integer integer integer integer integer int ?.5.f64 integer .s64 .u64 .u64 . or . 2nd is .s64.f64 same as source .f64 use usual conversions .Chapter 4.f64 converted type .f64 use usual conversions .f64 integer . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .u64) (.

PTX ISA Version 2. 2010 .0 26 January 24.

the kinds of resources will be common across platforms. All variables reside in some state space. Read-only. platform-specific. The list of state spaces is shown in Table 4. and level of sharing between threads. The characteristics of a state space include its size.1.tex January 24. Local memory. Global memory.sreg .const . Name State Spaces Description Registers.Chapter 5. pre-defined. Table 6. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Special registers. . private to each thread. fast. addressability. 5. Global texture memory (deprecated). or Function or local parameters.local . 2010 27 . State Spaces. defined per-grid. Types.reg . defined per-thread. read-only memory. Shared.shared . access rights.global .param . Kernel parameters. and Variables While the specific resources available in a given target GPU will vary. Addressable memory shared between threads in 1 CTA. shared by all threads. and properties of state spaces are shown in Table 5. State Spaces A state space is a storage area with particular characteristics. access speed. and these resources are abstracted in PTX through state spaces and data types.

16-. The most common use of 8-bit registers is with ld. 1 Accessible only via the ld.1..local state space. floating point.tex Restricted Yes No3 5.e. Address may be taken via mov instruction. CTA.global . or 128-bits.param instruction. 5. Register State Space Registers (. and performance monitoring registers. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .0 Table 7. it is not possible to refer to the address of a register. When the limit is exceeded. 2 Accessible via ld. 2010 .shared . and cvt instructions. predicate) or untyped. Registers may be typed (signed integer.sreg) state space holds predefined. unsigned integer.PTX ISA Version 2.param instructions. The number of registers is limited. st. or 64-bits. All special registers are predefined. Registers may have alignment boundaries required by multi-word loads and stores.local . or as elements of vector tuples.param and st. 3 Accessible only via the tex instruction.param (as input to kernel) .const . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). and will vary from platform to platform.1. and thread parameters. such as grid. 32-. Device function input parameters may have their address taken via mov. 32-. the parameter is then located on the stack frame and its address is in the . scalar registers have a width of 8-. Register size is restricted. causing changes in performance.reg . 64-. register variables will be spilled to memory. For each architecture.sreg . aside from predicate registers which are 1-bit. Registers differ from the other state spaces in that they are not fully addressable. clock counters. platform-specific registers. 28 January 24.2. and vector registers have a width of 16-.1. i.param (used in functions) . Special Register State Space The special register (.reg state space) are fast storage locations.

By convention. and Variables 5. bank zero is used for all statically-sized constant variables.global. as in lock-free and wait-free style programming. whereas local memory variables declared January 24. This reiterates the kind of parallelism available in machines that run PTX.local) is private memory for each thread to keep its own data. It is typically standard memory with cache.global. The size is limited. 2010 29 . Global State Space The global (. For example. The remaining banks may be used to implement “incomplete” constant arrays (in C. If another thread sees the variable b change. Local State Space The local state space (.local to access local variables. an incomplete array in bank 2 is accessed as follows: . Sequential consistency is provided by the bar. the bank number must be provided in the state space of the load instruction. For example. where bank ranges from 0 to 10. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. It is the mechanism by which different CTAs and different grids can communicate. In implementations that support a stack. Types. all addresses are in global memory are shared. as it must be allocated on a perthread basis.1. For any thread in a context. If no bank number is given. where the size is not known at compile time. ld. st.const[2]. bank zero is used. Threads wait at the barrier until all threads in the CTA have arrived.5.b32 const_buffer[]. there are eleven 64KB banks. the declaration . [const_buffer+4].4.3.local and st. The constant memory is organized into fixed size banks.sync instruction.b32 %r1.const) state space is a read-only memory.1. To access data in contant banks 1 through 10.global) state space is memory that is accessible by all threads in a context. Banks are specified using the .b32 const_buffer[].Chapter 5. results in const_buffer pointing to the start of constant bank two.extern .const[bank] modifier.const[2] . initialized by the host. // load second word 5.sync instruction are guaranteed to be visible to any reads after the barrier instruction. 5. Consider the case where one thread executes the following two assignments: a = a + 1. All memory writes prior to the bar. For the current devices. b = b – 1. Global memory is not sequentially consistent.const[2] .global to access global variables. State Spaces. for example).1. Use ld. Threads must be able to do their work without waiting for other threads to do theirs. Module-scoped local memory variables are stored at fixed addresses.extern . Constant State Space The constant (. and atom. the store operation updating a may still be in flight. This pointer can then be used to access the entire 64KB constant bank. the stack is in local memory. Use ld. each pointing to the start address of the specified constant bank. Multiple incomplete array variables declared in the same bank become aliases.

b32 N.param . typically for passing large structures by value to a function.reg .param state space and is accessed using ld. Therefore.param state space. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. … Example: .param instructions. len. Parameter State Space The parameter (. device function parameters were previously restricted to the register state space. ld. 2010 .0 and requires target architecture sm_20. The kernel parameter variables are shared across all CTAs within a grid.param) state space is used (1) to pass input arguments from the host to the kernel. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.1. The address of a kernel parameter may be moved into a register using the mov instruction.param space. These parameters are addressable.param .f64 %d.1. 5. (2a) to declare formal input and return parameters for device functions called from within kernel execution.entry bar ( . Note that PTX ISA versions 1.u32 %n. For example.PTX ISA Version 2. The use of parameter state space for device function parameters is new to PTX ISA version 2. PTX code should make no assumptions about the relative locations or ordering of .reg . 5.entry foo ( .param. Similarly.0 within a function or kernel body are allocated on the stack. read-only variables declared in the .f64 %d. [N].reg .6. The resulting address is in the . all local memory variables are stored at fixed addresses and recursive function calls are not supported.param .b32 len ) { .param instructions. .param.u32 %ptr. [buffer]. .param.u32 %n.u32 %ptr.param space variables. No access protection is provided between parameter and global space in this case. ld. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.align 8 . Note: The location of parameter space is implementation specific.x supports only kernel function parameters in . ld. … 30 January 24.b8 buffer[64] ) { . per-kernel versus per-thread). In implementations that do not support a stack. Example: .u32 %n. [%ptr].1. Values passed from the host to the kernel are accessed through these parameter variables using ld. in some implementations kernel parameters reside in global memory. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).6. mov. %n.

0 extends the use of parameter space to device function parameters. 2010 31 . ld.param formal parameter having the same size and alignment as the passed argument. dbl.param space variable.param .s32 %y.reg . In this case.reg .param.align 8 .6.s32 x.reg .s32 %y. the address of a function input parameter may be moved into a register using the mov instruction. This will be passed by value to a callee.func foo ( .param.b32 N. Device Function Parameters PTX ISA version 2.local state space and is accessed via ld.param byte array variable that represents a flattened C structure or union. .reg . [buffer+8]. .b8 mystruct. Note that the parameter will be copied to the stack if necessary. It is not possible to use mov to get the address of a return parameter or a locally-scoped .f64 %d.align 8 . State Spaces.param. } mystruct. … st.param space is also required whenever a formal parameter has its address taken within the called function.param and function return parameters may be written using st. and Variables 5. ld. Typically. .Chapter 5. st.param. Function input parameters may be read via ld. Example: // pass object of type struct { double d. which declares a .s32 [mystruct+8].local and st. … } // code snippet from the caller // struct { double d.1.param .f64 %d. the caller will declare a locally-scoped . int y.f64 dbl. . such as C structures larger than 8 bytes.b8 buffer[12] ) { . passed to foo … . and so the address will be in the .reg . int y. it is illegal to write to an input parameter or read from a return parameter.2. The most common use is for passing objects by value that do not fit within a PTX register. In PTX. x. }.local instructions. (4. . Types. Aside from passing structures by value. mystruct). [buffer]. is flattened. … See the section on function call syntax for more details.f64 [mystruct+0]. a byte array in parameter space is used. January 24. call foo.param. .

The texture name must be of type .global .1.shared) state space is a per-CTA region of memory for threads in a CTA to share data. The . An address in shared memory can be read and written by any thread in a CTA.0 5.7.tex directive is retained for backward compatibility.u32 . and variables declared in the . Shared memory typically has some optimizations to support the sharing.texref tex_a.shared and st. For example. Example: . Physical texture resources are allocated on a per-module granularity. A texture’s base address is assumed to be aligned to a 16-byte boundary.shared to access shared variables. Multiple names may be bound to the same physical texture identifier.tex state space are equivalent to module-scoped . tex_c.tex .1.u32 tex_a.texref type and Section 8. tex_d. a legacy PTX definitions such as . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Shared State Space The shared (. One example is broadcast. where all threads read from the same address.6 for its use in texture instructions.tex variables are required to be defined in the global scope. where texture identifiers are allocated sequentially beginning with zero.u32 .tex directive will bind the named texture memory variable to a hardware texture identifier. Use ld. tex_d. 2010 .u32 tex_a.u64.u32 .tex .tex . tex_f.texref variables in the . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).global state space.u32 or . See Section 5. and . The . Texture State Space (deprecated) The texture (.texref.tex) state space is global memory accessed via the texture instruction. 5. An error is generated if the maximum number of physical resources is exceeded.PTX ISA Version 2. It is shared by all threads in a context. and programs should instead reference texture memory through variables of type . 32 January 24.tex .tex . is equivalent to .3 for the description of the .8. Another is sequential access from sequential threads. Texture memory is read-only.7.

ld. .pred Most instructions have one or more type specifiers.f16.u16. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . . The following table lists the fundamental type specifiers for each basic type: Table 8.u64 . In principle. so that narrow values may be loaded. . For convenience.b32.f32 and .s32. Signed and unsigned integer types are compatible if they have the same size. all variables (aside from predicates) could be declared using only bit-size types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Operand types and sizes are checked against instruction types for compatibility. .s8. the fundamental types reflect the native data types supported by the target architectures. For example.u8. needed to fully specify instruction behavior. . or converted to other types and sizes. stored. 2010 33 . Types.2. and cvt instructions. January 24. . State Spaces.b8 instruction types are restricted to ld.1. .2. stored.s64 .u32.f64 types.f32 and . . st. All floating-point instructions operate only on . st. Fundamental Types In PTX. 5. . Register variables are always of a fundamental type.f64 types. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.f16 floating-point type is allowed only in conversions to and from .Chapter 5. Two fundamental types are compatible if they have the same basic type and are the same size. and converted using regular-width registers.s16.f32. Restricted Use of Sub-Word Sizes The . so their names are intentionally short.b16. but typed variables enhance program readability and allow for better operand type checking. The bitsize type is compatible with any fundamental type having the same size. The . .b64 .2. and . and instructions operate on these types.f64 .u8. The same typesize specifiers are used for both variable definitions and for typing instructions. A fundamental type specifies both a basic type and a size. .b8.2.s8. and Variables 5. Types 5.

PTX ISA Version 2. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. the resulting pointer may be stored to and loaded from memory. hence the term “opaque”. i.0 5. . allowing them to be defined separately and combined at the site of usage in the program.. suq). accessing the pointer with ld and st instructions. The three built-in types are . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. passed as a parameter to functions. field ordering. Creating pointers to opaque variables using mov. Retrieving the value of a named member via query instructions (txq. store. since these properties are defined by . and Surface Types PTX includes built-in “opaque” types for defining texture. but all information about layout. and de-referenced by texture and surface load. texture and sampler information is accessed through a single . PTX has two modes of operation. base address. or performing pointer arithmetic will result in undefined results.{u32. 2010 . suld. opaque_var. Texture.texref handle. Referencing textures. For working with textures and samplers. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. In the independent mode. sust. and surface descriptor variables. or surfaces via texture and surface load/store instructions (tex. and query instructions.e. samplers. sured). Sampler.samplerref variables.texref. In the unified mode.texref type that describe sampler properties are ignored.samplerref.surfref.u64} reg.3. 34 January 24. In independent mode the fields of the . The following tables list the named members of each type for unified and independent texture modes. These types have named fields similar to structures. but the pointer cannot otherwise be treated as an address. and overall size is hidden to a PTX program. and . sampler. texture and sampler information each have their own handle.

2010 35 . Types. and Variables Table 9.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. mirror. State Spaces. clamp_ogl. clamp_to_edge.samplerref values N/A N/A N/A N/A nearest.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_to_edge. 1 ignored ignored ignored ignored . linear wrap. mirror.Chapter 5. clamp_to_border 0. Member width height depth Opaque Type Fields in Independent Texture Mode .texref values .texref values in elements in elements in elements 0. clamp_ogl. clamp_to_border N/A N/A N/A N/A N/A . linear wrap. 1 nearest.

param state space. .global . these variables must be in the .surfref my_surface_name.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global state space. Example: .texref tex1.global . these variables are declared in the .global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. As kernel parameters. 36 January 24. At module scope. filter_mode = nearest }. Example: . When declared at module scope. .global . the types may be initialized using a list of static expressions assigning values to the named members.texref my_texture_name.samplerref my_sampler_name.PTX ISA Version 2. 2010 . .global .

and Variables 5.reg . r.v4 . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .v2 .struct float4 coord. an optional array size. . for example.v3 }.v4 . textures.f32 bias[] = {-1. Every variable must reside in one of the state spaces enumerated in the previous section.f32 V.b8 v.global . an optional initializer.global . 0}. 5.global . .shared .global . A variable declaration names the space in which the variable resides. 1. January 24.Chapter 5. State Spaces. vector variables are aligned to a multiple of their overall size (vector length times base-type size).1. 2010 37 . etc.v4 vector. // a length-2 vector of unsigned ints .u8 bg[4] = {0.global .v2 or . and they may reside in the register space. Examples: . q. Examples: .4. // typedef . Vectors Limited-length vector types are supported.u16 uv.4.struct float4 { . This is a common case for three-dimensional grids.reg . . Variable Declarations All storage for data is specified with variable declarations. . PTX supports types for simple aggregate objects such as vectors and arrays. 5. . Variables In PTX. Three-element vectors may be handled by using a .f32 v0.0. // a length-4 vector of bytes By default. 0.s32 i.f64 is not allowed.u32 loc. and an optional fixed address for the variable. its name. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v2.0}. .4.2. .reg .v4 .const . a variable declaration describes both the variable’s type and its state space. // a length-4 vector of floats . 0. Types.f32 accel. Predicate variables may only be declared in the register state space.v4.v1. In addition to fundamental types.v4. Vectors cannot exceed 128-bits in length. its type and size. Vectors must be based on a fundamental type.pred p. where the fourth element provides padding.

5. . {0. Array Declarations Array declarations are provided to allow the programmer to reserve space. this can be used to statically initialize a pointer to a variable.global .4. Initializers are allowed for all types except . Here are some examples: . Initializers Declared variables may specify an initial value using a syntax similar to C/C++. Variables that hold addresses of variables or instructions should be of type . {0.global . 38 January 24.1. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. // address of rgba into ptr Currently.1. 2010 .0.global .f32 blur_kernel[][] = {{.4.f16 and ...1.. .pred. where the variable name is followed by an equals sign and the initial value or values for the variable.{.{.1}.4.0}}.4. {1. variable initialization is supported only for constant and global state spaces. Variable names appearing in initializers represent the address of the variable.u64.v4 .. For the kernel declaration above. label names appearing in initializers represent the address of the next instruction following the label. 1} }.3.global .shared . or is left empty. Similarly. 0}.u8 rgba[3] = {{1.0. . {0. The size of the array specifies how many elements should be reserved.05. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).PTX ISA Version 2.0 5.0.b32 ptr = rgba.. 0}.05}}.0}.05. . To declare an array. . A scalar takes a single value.u8 mailbox[128].1. The size of the dimension is either a constant expression..s32 offset[][] = { {-1.s32 n = 10.05}. -1}.global . being determined by an array initializer.0}. this can be used to initialize a jump table to be used with indirect branches or calls.1. Examples: .local .0. {0.u16 kernel[19][19].u32 or . 19*19 (361) halfwords are reserved (722 bytes).

. For arrays. nor are initializers permitted.0.5.4. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. . These 100 register variables can be declared as follows: .b8 bar[8] = {0. The variable will be aligned to an address which is an integer multiple of byte-count. Examples: // allocate array at 4-byte aligned address.0.b32 variables. 5. %r1. January 24. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Rather than require explicit declaration of every name. of .. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. Elements are bytes. Types.align 4 .4. say one hundred.2. Array variables cannot be declared this way. not for individual elements. // declare %r0.align byte-count specifier immediately following the state-space specifier. it is quite common for a compiler frontend to generate a large number of register names. State Spaces. %r1. Alignment is specified using an optional .0.Chapter 5. and may be preceded by an alignment specifier. The default alignment for vector variables is to a multiple of the overall vector size. 2010 39 . named %r0. ….0. %r99.6. Parameterized Variable Names Since PTX supports virtual registers.reg . suppose a program uses a large number.b32 %r<100>. alignment specifies the address alignment for the starting address of the entire array.0}. For example.. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. .0.const . The default alignment for scalar and array variables is to a multiple of the base-type size. and Variables 5.

2010 .PTX ISA Version 2.0 40 January 24.

The cvt (convert) instruction takes a variety of operand types and sizes. Instructions ld and st move data from/to addressable state spaces to/from registers. The mov instruction copies data between registers. There is no automatic conversion between types. Source Operands The source operands are denoted in the instruction descriptions by the names a. For most operations. The result operand is a scalar or vector variable in the register state space. mov. st. the sizes of the operands must be consistent. Predicate operands are denoted by the names p.2. Integer types of a common size are compatible with each other.3. . and c. Instruction Operands 6. s. 6. The ld. q. and cvt instructions copy data from one location to another. Operand Type Information All operands in instructions have a known type from their declarations. Each operand type must be compatible with the type determined by the instruction template and instruction type.Chapter 6. The bit-size type is compatible with every type having the same size. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. r.reg register state space. January 24. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. 6.1. Most instructions have an optional predicate guard that controls conditional execution. so operands for ALU instructions must all be in variables declared in the . as its job is to convert from nearly any data type to any other data type (and size). PTX describes a load-store machine. and a few instructions have additional predicate source operands. b. 2010 41 .

.s32 q. .4. Address expressions include variable names.v4 . arrays. Examples include pointer arithmetic and pointer comparisons. The mov instruction can be used to move the address of a variable into a pointer.gloal. there is no support for C-style pointer arithmetic. q. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.v4 .shared. 2010 .f32 W. p.reg .4.reg . The syntax is similar to that used in many assembly languages. and Vectors Using scalar variables as operands is straightforward. . All addresses and address computations are byte-based. address registers.f32 V. address register plus byte offset.u16 r0. Load and store operations move data between registers and locations in addressable state spaces. [tbl+12].v4.const. r0. ld. Here are a few examples: . 6.const .PTX ISA Version 2. .s32 mov. Arrays.b32 p.s32 tbl[256].u16 ld.reg . [V].0 6. tbl. Using Addresses. .shared .global .u16 x. and vectors. The interesting capabilities begin with addresses. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. W.[x]. The address is an offset in the state space in which the variable is declared. .u32 42 January 24.f32 ld. and immediate address expressions which evaluate at compile-time to a constant address.1.reg .

ld. a[1]. Vector loads and stores can be used to implement wide loads and stores. which may improve memory performance.z and .3. and tex. or by indexing into the array using square-bracket notation. a register variable.f32 ld. which include mov.2. .v4.global. ld.b.4. st.g. V.4. mov. Here are examples: ld.a.global.y. Vector elements can be extracted from the vector with the suffixes . If more complicated indexing is desired.d}.u32 s. Elements in a brace-enclosed vector. a[N-1]. . [addr+offset].b V. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.global.reg . 2010 43 . January 24.Chapter 6. Vectors may also be passed as arguments to called functions. mov. b. Array elements can be accessed using an explicitly calculated byte address. it must be written as an address calculation prior to use. . d. or a simple “register with constant offset” expression. where the offset is a constant expression that is either added or subtracted from a register variable.4. Instruction Operands 6.f32 V.y V. as well as the typical color fields . Rd}.4.f32 a. a[0].f32 {a.r.r V. Vectors as Operands Vector operands are supported by a limited subset of instructions.v2.v4.d}.b. for use in an indirect branch or call.reg . Arrays as Operands Arrays of all types can be declared.b and . and the identifier becomes an address constant in the space where the array is declared.u32 {a. // move address of a[1] into s 6.g V.x V. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. . A brace-enclosed list is used for pattern matching to pull apart vectors.w. say {Ra.u32 s.c. . or a braceenclosed list of similarly typed scalars.v4 .a 6. [addr+offset2].global. The expression within square brackets is either a constant integer. The registers in the load/store operations can be a vector.z V. The size of the array is a constant in the program. . V2.x.u32 s. c.w = = = = V. Examples are ld. Rb. Rc.c. and in move instructions to get the address of the label or function into a register.

000 for f16). 2010 .5. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. and ~131. Type Conversion All operands to all arithmetic. if a cvt. and data movement instruction must be of the same type and size.0 6.u16 instruction is given a u16 source operand and s32 as a destination operand. For example. 44 January 24. logic. 6.PTX ISA Version 2. the u16 is zero-extended to s32.1.s32. Operands of different sizes or types must be converted prior to the operation. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.5. except for operations where changing the size and/or type is part of the definition of the instruction.

zext = zero-extend.s16. cvt. The type of extension (sign or zero) is based on the destination format. the result is extended to the destination register width after chopping. u2f = unsigned-to-float. chop = keep only low bits that fit. f2u = float-to-unsigned.u32 targeting a 32-bit register will first chop to 16-bits. Notes 1 If the destination register is wider than the destination format. For example.Chapter 6. f2s = float-to-signed. 2010 45 . s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. s2f = signed-to-float. Instruction Operands Table 11. f2f = float-to-float. then sign-extend to 32-bits. January 24.

rmi . In PTX.PTX ISA Version 2.rm .rzi .rz .0 6. Modifier .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rn . there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 . The following tables summarize the rounding modifiers. Modifier .rpi Integer Rounding Modifiers Description round to nearest integer. choosing even integer if source is equidistant between two integers.rni .5. Rounding Modifiers Conversion instructions may specify a rounding modifier. Table 12. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.2.

Table 14. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Much of the delay to memory can be hidden in a number of ways.Chapter 6. Operand Costs Operands from different state spaces affect the speed of an operation. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. first access is high Notes January 24. Registers are fastest. 2010 47 . The register in a store operation is available much more quickly. Table 11 gives estimates of the costs of using different kinds of memory. Another way to hide latency is to issue the load instructions as early as possible. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. while global memory is slowest. Instruction Operands 6.6.

0 48 January 24.PTX ISA Version 2. 2010 .

and is represented in PTX as follows: . January 24. stack-based ABI. NOTE: The current version of PTX does not implement the underlying. functions are declared and defined using the . function calls. A function must be declared or defined prior to being called. and return values may be placed directly into register variables. we describe the features of PTX needed to achieve this hiding of the ABI. A function definition specifies both the interface and the body of the function.func foo { … ret. These include syntax for function definitions.func directive. so recursion is not yet supported. and Application Binary Interface (ABI). 2010 49 . In this section.1. 7. At the call. parameter passing. implicitly saving the return address. support for variadic functions (“varargs”). PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. the function name. The simplest function has no parameters or return values.Chapter 7. Scalar and vector base-type input and return parameters may be represented simply as register variables. and an optional list of input parameters. … Here. Abstracting the ABI Rather than expose details of a particular calling convention. } … call foo. arguments may be register variables or constants. Execution of the ret instruction within foo transfers control to the instruction following the call. A function declaration specifies an optional list of return parameters. execution of the call instruction transfers control to foo. or prototype. together these specify the function’s interface. and memory allocated on the stack (“alloca”). The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Function declarations and definitions In PTX. stack layout.

First. For example.c2. a .align 8 y[12]) { . py).b8 .reg . ld. .param.param state space is used to pass the structure by value: . Since memory accesses are required to be aligned to a multiple of the access size.c4.4). char c[4].c1. c2.0 Example: . … … // computation using x. st.u32 %res) inc_ptr ( . ld.reg .f64 field are aligned. st.param space memory. %rd.b64 [py+ 0]. ld. inc_ptr.b8 c4. %rc1. In PTX.reg . a . Second.param. %rc2.b8 [py+ 8]. … In this example. 2010 . this structure will be flattened into a byte array. st. byte array in . [y+8]. The . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . (%x. st.f1.b8 .b8 [py+ 9]. // scalar args in .param.PTX ISA Version 2. %inc. c3. } … call (%r1). (%r1.param space variables are used in two ways. [y+0].param. [y+10].param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 [py+11].b32 c1.param .u32 %ptr.reg . passed by value to a function: struct { double dbl. consider the following C structure. bumpptr. %rc1. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . %rc2.reg . ld. … st.b8 [py+10].reg .reg .u32 %inc ) { add. [y+9].align 8 py[12].param.func (.b8 c3.param.param. … ld.u32 %res.f64 f1.b8 c1.s32 x. 50 January 24.param.param.c3. [y+11]. }. ret. .param.f64 f1.param .param space call (%out).reg space. %ptr. .b8 c2.s32 out) bar (.func (.param variable y is used in function definition bar to represent a formal parameter. note that . } { . c4.

. the corresponding argument may be either a .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. The following restrictions apply to parameter passing.g.reg space formal parameters. This enables backend optimization and ensures that the . Supporting the . • The . • • • Input and return parameters may be . and alignment of parameters.Chapter 7.param arguments. size. The . 4. and alignment. In the case of . Note that the choice of . or 16 bytes.param argument must be declared within the local scope of the caller.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. • • • For a callee.param state space is used to receive parameter values and/or pass return values back to the caller. size.param state space use in device functions. 2010 51 .param or .reg variables.param or .reg state space can be used to receive and return base-type scalar and vector values. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param space formal parameters that are base-type scalar or vector variables.param space formal parameters that are byte arrays. For a caller.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. For a callee. the argument must also be a .reg space variable of matching type and size. or a constant that can be represented in the type of the formal parameter.param instructions used for argument passing must be contained in the basic block with the call instruction. January 24.param variables.reg space variable with matching type and size. all st. The . In the case of .param space byte array with matching type.reg state space in this way provides legacy support. Abstracting the ABI The following is a conceptual way to think about the . • The . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. 8. or a constant that can be represented in the type of the formal parameter.param variables or .param byte array is used to collect together fields of a structure being passed by value.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. For a caller. 2. A .param memory must be aligned to a multiple of 1.param and ld.reg variables. For . or constants. • • Arguments may be . Parameters in . Typically.. the corresponding argument may be either a . In the case of .reg or . a .

0 continues to support multiple return registers for sm_1x targets. PTX 2.param space parameters support arrays.PTX ISA Version 2. formal parameters may be in either .1.0 restricts functions to a single return value.reg state space.param state space. and a .x. and . Objects such as C structures were flattened and passed or returned using multiple registers. For sm_2x targets.x supports multiple return values for this purpose.reg or . formal parameters were restricted to .x In PTX ISA version 1.1. In PTX ISA version 2.0. and there was no support for array parameters. Changes from PTX 1. 52 January 24.0 7. PTX 1.param byte array should be used to return objects that do not fit into a register. 2010 . PTX 2.

u32 align) .reg .pred p.reg . In PTX.s32 val. . %s2). 2.h and varargs. bra Done.b32 ctr.2.ge p.u32 ap. This handle is then passed to the %va_arg and %va_arg64 built-in functions.u32. ctr.reg . val. .func ( . %va_arg. // default to MININT mov. 4). … call (%max). Once all arguments have been processed. or 4 bytes. along with the size and alignment of the next data value to be accessed.u32 ptr) %va_start . ctr. (ap). maxN.u32 align) . 2. The function prototypes are defined as follows: .u32 sz. and end access to a list of variable arguments.b32 result. Variadic functions NOTE: The current version of PTX does not support variadic functions.s32 result ) maxN ( .reg . . iteratively access.b64 val) %va_arg64 (.reg .reg .func (. In both cases. (3.func (. setp. call %va_end.reg .reg . the alignment may be 1. To support functions with a variable number of arguments.u32 sz.reg .s32 result.u32 ptr. maxN. %r3).reg . .reg . variadic functions are declared with an ellipsis at the end of the input parameter list. } … call (%max).u32 ptr. (ap.u32 b. result. . %va_end is called to free the variable argument list handle. 0x8000000. For %va_arg.reg . call (ap).u32 N. the size may be 1. 8. … ) . call (val). 4. bra Loop. mov. PTX provides a high-level mechanism similar to the one provided by the stdarg.reg .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. . %va_start. or 8 bytes.Chapter 7. 4.func %va_end (. 0. 2010 53 . N.func baz ( . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . . for %va_arg64. ) { .. %r1.. 2. %r2. following zero or more fixed parameters: . %s1. the size may be 1.reg .reg . 4.b32 val) %va_arg (. Abstracting the ABI 7.func (.func okay ( … ) Built-in functions are provided to initialize. max. (2. … %va_start returns Loop: @p Done: January 24. .reg .reg .h headers in C. ret. or 16 bytes.u32 a.

func ( . a function simply calls the built-in function %alloca. If a particular alignment is required. Alloca NOTE: The current version of PTX does not support alloca.u32 ptr ) %alloca ( . To allocate memory.local instructions. defined as follows: .reg . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.local and st.PTX ISA Version 2. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. 2010 .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. The array is then accessed with ld. 54 January 24.0 7.reg .3.

q = !(a < b). plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode.Chapter 8. opcode D. // p = (a < b). B. the semantics are described. while A. opcode A.lt p|q. A. followed by some examples that attempt to show several possible instantiations of the instruction. opcode D. b. Instruction Set 8. A. January 24. For instructions that create a result value. 2010 55 . B. and C are the source operands. opcode D.s32. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. PTX Instructions PTX instructions generally have from zero to four operands. The setp instruction writes two destination registers. the D operand is the destination operand. C. 8. a. In addition to the name and the format of the instruction. setp. B.1. A. For some instructions the destination operand is optional.2. We use a ‘|’ symbol to separate multiple destination registers. Format and Semantics of Instruction Descriptions This section describes each PTX instruction.

Predicated Execution In PTX.lt.s32 p. add.s32 p. 1. j.s32 j. // p = (i < n) // if i < n.PTX ISA Version 2. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. Predicates are most commonly set as the result of a comparison performed by the setp instruction. j. n. add.3. i. predicate registers are virtual and have . optionally negated. So. … // compare i to n // if false.pred p. predicate registers can be declared as . use a predicate to control the execution of the branch or call instructions.lt. the following PTX instruction sequence might be used: @!p L1: setp.reg . consider the high-level code if (i < n) j = j + 1.0 8. This can be written in PTX as @p setp. 2010 . q. bra L1. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. branch over 56 January 24.s32 j. To implement the above example as a true conditional branch.pred as the type specifier. 1. n. add 1 to j To get a conditional branch or conditional function call. i. Instructions without a guard predicate are executed unconditionally. where p is a predicate variable. As an example.

The following table shows the operators for signed integer. Unsigned Integer.3. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. gt. lo (lower). Table 16. le (less-than-or-equal). Instruction Set 8. unsigned integer. ge. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.3. ne (not-equal). Table 15. The bit-size comparisons are eq and ne. ordering comparisons are not defined for bit-size types. le.1. ne.1. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. and hs (higher-or-same).1.Chapter 8.2. 2010 57 .3. hi (higher). lt (less-than). ls (lower-or-same). The unsigned comparisons are eq. lt. and ge (greater-than-or-equal). If either operand is NaN.1. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. and bitsize types. ne. the result is false. Comparisons 8. gt (greater-than).

xor. and no direct way to load or store predicate register values. 2010 . Table 18. num returns true if both operands are numeric values (not NaN). and nan returns true if either operand is NaN. unordered versions are included: equ. There is no direct conversion between predicates and integer values.0 To aid comparison operations in the presence of NaN values. neu. gtu. not.2. for example: selp. two operators num (numeric) and nan (isNaN) are provided. // convert predicate to 32-bit value 58 January 24. geu. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. leu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. then the result of these comparisons is true. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. However. If both operands are numeric values (not NaN). If either operand is NaN. Table 17. or.%p.u32 %r1.3. ltu.0. and mov. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.1.PTX ISA Version 2. setp can be used to generate a predicate from an integer. then these comparisons have the same result as their ordered counterparts.

float.bX .fX ok ok ok ok January 24. Type Checking Rules Operand Type . Table 19. .sX . Instruction Set 8.f32.sX ok ok ok inv .reg . most notably the data conversion instruction cvt.uX ok ok ok inv .4. unsigned. For example.u16 d. cvt. b. Signed and unsigned integer types agree provided they have the same size. add.bX . a. and these are placed in the same order as the operands. Floating-point types agree only if they have the same size. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. and integer operands are silently cast to the instruction type if needed.uX .reg . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. For example. For example: . the add instruction requires type and size information to properly perform the addition operation (signed. different sizes). 2010 59 . and this information must be specified as a suffix to the opcode. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. It requires separate type-size modifiers for the result and source.fX ok inv inv ok Instruction Type .f32 d.reg .u16 a. they must match exactly.e.u16 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. b. a.u16 d. a.Chapter 8. i. Example: .. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. • The following table summarizes these type checking rules.

Note that some combinations may still be invalid for a particular instruction.0 8. stored. “-“ = allowed. Source register size must be of equal or greater size than the instruction-type size. unless the operand is of bit-size type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.bX instruction types. Table 20. so those rows are invalid for cvt. ld. the size must match exactly. When used with a narrower bit-size type. The following table summarizes the relaxed type-checking rules for source operands. the cvt instruction does not support . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Notes 3. no conversion needed.PTX ISA Version 2. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. When used with a floating-point instruction type. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.4. st. inv = invalid. When a source operand has a size that exceeds the instruction-type size. 1. The data is truncated to the instruction-type size and interpreted according to the instruction type. or converted to other types and sizes. 4. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. For example. stored. Floating-point source registers can only be used with bit-size or floating-point instruction types. 2010 . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. for example. 2. floating-point instruction types still require that the operand type-size matches exactly. so that narrow values may be loaded. the data will be truncated.1. 60 January 24. parse error. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. and converted using regular-width registers. Operand Size Exceeding Instruction-Type Size For convenience. Bit-size source registers may be used with any appropriately-sized instruction type.

zext = zero-extend. parse error. When used with a narrower bit-size instruction type. The data is sign-extended to the destination register width for signed integer instruction types. Destination register size must be of equal or greater size than the instruction-type size. The following table summarizes the relaxed type-checking rules for destination operands. the data is sign-extended.Chapter 8. Table 21. “-“ = Allowed but no conversion needed.or sign-extended to the size of the destination register. the size must match exactly. If the corresponding instruction type is signed integer. the destination data is zero. and is zero-extended to the destination register width otherwise. 2010 61 . and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. The data is signextended to the destination register width for signed integer instruction types. inv = Invalid. the data will be zero-extended. January 24. Floating-point destination registers can only be used with bit-size or floating-point instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. the data is zeroextended. otherwise. Notes 3. 4. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. When used with a floatingpoint instruction type. 1. 2. Bit-size destination registers may be used with any appropriately-sized instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size.

All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. conditional function call. the semantics of 16-bit instructions in PTX is machine-specific. the optimizing code generator automatically determines points of re-convergence. for example. a compiler or code author targeting PTX can ignore the issue of divergent threads. However. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. The semantics are described using C. this is not desirable. until they come to a conditional control construct such as a conditional branch. until C is not expressive enough. When executing on a 32-bit data path. 8. the threads are called uniform. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs.6. or conditional return. and 16-bit computations are “promoted” to 32-bit computations. and for many applications the difference in execution is preferable to limiting performance. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code.5. At the PTX language level. for many performance-critical applications. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. so it is important to have divergent threads re-converge as soon as possible.6. A compiler or programmer may chose to enforce portable. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.0 8. 16-bit registers in PTX are mapped to 32-bit physical registers. by a right-shift instruction. For divergent control flow. Both situations occur often in programs. at least in appearance. 8. If threads execute down different control flow paths. Therefore. 2010 . Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. 62 January 24. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. These extra precision bits can become visible at the application level. the threads are called divergent.uni suffix.PTX ISA Version 2. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. using the . Divergence of Threads in Control Constructs Threads in a CTA execute together. If all of the threads act in unison and follow a single control flow path.1.

7.7. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.1. the optional guard predicate is omitted from the syntax. Instruction Set 8. 8. The Integer arithmetic instructions are: add sub add. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.cc. In the following descriptions.Chapter 8. 2010 63 .cc. addc sub. Instructions All PTX instructions may be predicated.

@p add.sat limits result to MININT.s16.u32.0.sat limits result to MININT. d = a + b. .type = { . . Saturation modifier: .a.. .s32 type.s32 c. d.s16. b. a. PTX ISA Notes Target ISA Notes Examples 64 January 24. Supported on all target architectures. b.PTX ISA Version 2.. a. b. // . .sat applies only to .b.s32.s64 }. d = a – b.type add{. . add. . // . d.0 Table 22.s64 }.u64. add. Saturation modifier: .0. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. .s32 d.sat applies only to . Description Semantics Notes Performs addition and writes the resulting value into a destination register. b. .z.u16.s32 c. sub.c.1.s32 . Applies only to .sat}.s32 d. . a. a.u64.s32 . Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Supported on all target architectures.sat}.MAXINT (no overflow) for the size of the operation. .s32.type = { . add Syntax Integer Arithmetic Instructions: add Add two values. 2010 .sat. Applies only to .u32.y. PTX ISA Notes Target ISA Notes Examples Table 23.u32 x.s32 type.u16.MAXINT (no overflow) for the size of the operation.type sub{. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sub.

b.b32 addc.z4. add.cc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.type = {.CF No integer rounding modifiers.2. carry-out written to CC. addc{.y3. . @p @p @p @p add. if . . .type = { .type d. . x4. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc. d = a + b + CC.u32.b32 x1.z3.CF.cc}.y2. d = a + b.z1.b32 addc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. @p @p @p @p add. No saturation. carry-out written to CC.z3. Introduced in PTX ISA version 1.s32 }. x2.cc Syntax Integer Arithmetic Instructions: add.CF) holding carry-in/carry-out or borrowin/borrow-out. a.y4.type d.cc. x4.y1.cc.2. and there is no support for setting.b32 addc.cc Add two values with carry-out.b32 addc. Introduced in PTX ISA version 1.b32 addc.s32 }. Behavior is the same for unsigned and signed integers.y2. Supported on all target architectures.cc. Supported on all target architectures. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.b32 x1.y4. or testing the condition code.cc. clearing.y1.z2. Table 24. x3. addc. add.cc. x2.z2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.y3. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc. No other instructions access the condition code. 2010 65 .z4.cc.cc specified.CF No integer rounding modifiers.u32.cc. Behavior is the same for unsigned and signed integers. a.z1.Chapter 8. No saturation. x3. sub. These instructions support extended-precision integer addition and subtraction. b.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.b32 addc. Instruction Set Instructions add.

cc. borrow-out written to CC.u32.y1.b32 subc.b32 x1.b32 subc. No saturation.y2.PTX ISA Version 2.cc}.cc. Supported on all target architectures.s32 }. Behavior is the same for unsigned and signed integers.z3. . .type = { . with borrow-out.CF No integer rounding modifiers.cc Subract one value from another.z4.z4. x2.3.cc.z1.cc.y2.CF No integer rounding modifiers. 2010 . x2. .u32. borrow-out written to CC.b32 subc. Behavior is the same for unsigned and signed integers. x3. No saturation. .z2. subc{. x4. Introduced in PTX ISA version 1. Supported on all target architectures. x3.cc.b32 subc.cc. d = a . b.y1.z2.cc.cc. sub.cc Syntax Integer Arithmetic Instructions: sub.y3.z3. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. sub.cc specified.type = {. @p @p @p @p sub.y4. withborrow-in and optional borrow-out. b. @p @p @p @p sub.b32 x1.cc. d = a – b. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.type d.y4.3.CF). // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.type d.z1.0 Table 26. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. x4.b32 subc. a. a.b32 subc.s32 }.(b + CC. Introduced in PTX ISA version 1. if .y3.

then d is twice as wide as a and b to receive the full result of the multiplication.hi or .y. . then d is the same size as a and b.wide suffix is supported only for 16. If . The . 2010 67 .u64.and 32-bit integer types. // for . . mul. . .type = { .lo.hi. Instruction Set Table 28.s32 z. t = a * b.Chapter 8. mul.u16.type d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.s16. .s64 }. a. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.. mul{.n>. and either the upper or lower half of the result is written to the destination register.x.. creates 64 bit result January 24.fys. Supported on all target architectures.wide. . mul.lo variant Notes The type of the operation represents the types of the a and b operands. If .s32.wide // for .lo is specified.fxs. // 16*16 bits yields 32 bits // 16*16 bits.fxs. Description Semantics Compute the product of two values.s16 fa..0>. d = t.fys. d = t<n-1. d = t<2n-1. b.wide}.u32. save only the low 16 bits // 32*32 bits..lo. n = bitwidth of type.wide.hi variant // for .s16 fa.wide is specified.

b.s32 r.n> + c.lo. Saturation modifier: . The . t<2n-1.a. then d and c are twice as wide as a and b to receive the result of the multiplication. . 2010 .s16. c.. // for .hi.hi.s32.u64.PTX ISA Version 2. .sat.s32 type in . mad{.wide // for .lo.lo is specified.r.. Supported on all target architectures.type mad.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .s64 }.wide is specified. c. and then writes the resulting value into a destination register.q.c.u32. bitwidth of type.lo variant Notes The type of the operation represents the types of the a and b operands.s32 d. If . Description Semantics Multiplies two values and adds a third.wide suffix is supported only for 16.s32 d.hi variant // for . t n d d d = = = = = a * b. 68 January 24. b.. . t + c.0> + c.wide}. Applies only to .type = { . If .u16. then d and c are the same size as a and b.lo. b.0.MAXINT (no overflow) for the size of the operation.hi or .. a.and 32-bit integer types. .sat limits result to MININT.hi mode. . @p mad. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.p.0 Table 29. a. mad. and either the upper or lower half of the result is written to the destination register. t<n-1. d.

0>. // low 32-bits of 24x24-bit signed multiply.hi. All operands are of the same type and size.type = { .lo}.a. January 24. Instruction Set Table 30.s32 }. a. 48bits.b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.hi may be less efficient on machines without hardware support for 24-bit multiply.u32.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. . mul24. d = t<47.type d.hi variant // for . i. mul24{.e.. mul24. d = t<31.Chapter 8.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. 2010 69 . mul24.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. t = a * b. . and return either the high or low 32-bits of the 48-bit result.. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.16>. mul24.lo.s32 d.. Supported on all target architectures. b. // for .

b.PTX ISA Version 2. Saturation modifier: . Return either the high or low 32-bits of the 48-bit result. and add a third.sat. a. .u32.. i. mad24.hi may be less efficient on machines without hardware support for 24-bit multiply. // for ..hi.type mad24. 70 January 24.e. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. Description Compute the product of two 24-bit integer values held in 32-bit source registers.0 Table 31. d = t<31. d = t<47. t = a * b. b.a.s32 d.c. Applies only to .16> + c.s32 d. 2010 ..hi mode. 32-bit value to either the high or low 32-bits of the 48-bit result.s32 }.lo}. mad24. .b. mad24{. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.0> + c. c.sat limits result of 32-bit signed addition to MININT. mad24.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.hi variant // for .type = { . 48bits.hi.MAXINT (no overflow). mad24. // low 32-bits of 24x24-bit signed multiply.s32 type in . c. Supported on all target architectures. a.lo.. d. All operands are of the same type and size.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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inclusively.b64 d.b32 type. popc. . . mask = 0x8000000000000000.b64 d. if (. clz requires sm_20 or later.PTX ISA Version 2.type d. a. d = 0. } else { max = 64.b64 }. } while (d < max && (a&mask == 0) ) { d++. .b32. . while (a != 0) { if (a&0x1) d++. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.type d. popc Syntax Integer Arithmetic Instructions: popc Population count. inclusively. X.b64 type. clz. mask = 0x80000000. cnt. // cnt is .0 Table 39.b32 clz. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 popc. a = a << 1.0. a. the number of leading zeros is between 0 and 32. the number of leading zeros is between 0 and 64. For .u32 PTX ISA Notes Target ISA Notes Examples Table 40. a. a. // cnt is .type = { . clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. popc. a = a >> 1.0. For . popc requires sm_20 or later. d = 0.b64 }.type == .b32) { max = 32. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.u32 Semantics 74 January 24.type = { .b32. X. } Introduced in PTX ISA version 2. cnt. clz. 2010 .

2010 75 . a. . a. bfind requires sm_20 or later. .u32.type==. X. bfind. For unsigned integers.s32) ? 31 : 63. If . For signed integers. Description Find the bit position of the most significant non-sign bit in a and place the result in d. i>=0.type = { .s64 cnt. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.shiftamt is specified. for (i=msb. i--) { if (a & (1<<i)) { d = i. bfind returns 0xFFFFFFFF if no non-sign bit is found.shiftamt && d != -1) { d = msb . bfind returns the bit position of the most significant “1”. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. . .u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. d. bfind.u32 d. Semantics msb = (.type d.u64. Operand a has the instruction type.shiftamt.type bfind. d = -1.s32. } } if (.d. break.type==.u32 January 24.0.Chapter 8. a.u32 || . bfind.shiftamt. // cnt is . Instruction Set Table 41. and operand d has type .s64 }.

for (i=0.b32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { . i<=msb.b32) ? 31 : 63.0. . brev requires sm_20 or later.type d. 2010 . a. a.PTX ISA Version 2. Description Semantics Perform bitwise reversal of input.b64 }. msb = (.0 Table 42. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.type==.b32 d. brev. i++) { d[i] = a[msb-i]. . 76 January 24. brev.

. . c.s32) ? 31 : 63.u32.u64.type d. Instruction Set Table 43. for (i=0. d = 0. if (. .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. The destination d is padded with the sign bit of the extracted field.s64 }. bfe requires sm_20 or later.0.u64: . If the start position is beyond the msb of the input. . a.s32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The sign bit of the extracted field is defined as: .type==.u64 || len==0) sbit = 0.u32.start. and operands b and c are type .a.type==.len. pos = b.s32. otherwise If the bit field length is zero. .msb)].type==.type = { . the destination d is filled with the replicated sign bit of the extracted field. else sbit = a[min(pos+len-1.u32. .Chapter 8. 2010 77 .u32 || .type==.b32 d. January 24. Semantics msb = (. i<=msb. bfe. len = c. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. Description Extract bit field from a and place the zero or sign-extended result in d. b.u32 || . the result is zero. Operands a and d have the same type as the instruction type. bfe. and source c gives the bit field length in bits. Source b gives the bit field starting bit position. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.

.b32.len. 78 January 24.PTX ISA Version 2. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. f = b. the result is b. Source c gives the starting bit position for the insertion.b32) ? 31 : 63.b32 d. d. b. Description Align and insert a bit field from a into b.type = { .b64 }. Operands a. If the bit field length is zero. and f have the same type as the instruction type. i<len && pos+i<=msb. and place the result in f. pos = c. and source d gives the bit field length in bits.0 Table 44.0. and operands c and d are type . i++) { f[pos+i] = a[i]. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. 2010 . a. len = d. for (i=0.u32. bfi requires sm_20 or later.a. If the start position is beyond the msb of the input.type f.start. c. bfi.type==. bfi. b. . Semantics msb = (.b. the result is b.

.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. a 4-bit selection value is defined. default mode index d. In the generic form (no mode specified). b4}. b2. the four 4-bit values fully specify an arbitrary byte permute.b4e. prmt.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. b0}}. a. .b2 source select c[11:8] d. . . b1.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. . Thus. a} = {{b7. The msb defines if the byte value should be copied. The bytes in the two source registers are numbered from 0 to 7: {b. 2010 79 .ecl. c. msb=0 means copy the literal value. Instruction Set Table 45.f4e.b32{.mode} d. b6.rc8. and reassemble them into a 32-bit destination register. {b3.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. b.Chapter 8. . Note that the sign extension is only performed as part of generic form. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). b5.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.ecr. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. msb=1 means replicate the sign. as a 16b permute code. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.b1 source select c[7:4] d.b3 source select c[15:12] d. the permute control consists of four 4-bit selection values.mode = { . For each byte in the target register. Description Pick four arbitrary bytes from two 32-bit registers.rc16 }.

r1. tmp64 ). r4. ctl[1]. 2010 . } tmp[07:00] = ReadByte( mode. r3. r2. r4.PTX ISA Version 2.0 Semantics tmp64 = (b<<32) | a. tmp64 ). ctl[1] = (c >> 4) & 0xf. prmt. prmt requires sm_20 or later. 80 January 24. ctl[3]. ctl[3] = (c >> 12) & 0xf.0. tmp[23:16] = ReadByte( mode.f4e r1.b32 prmt. tmp64 ). tmp[15:08] = ReadByte( mode.b32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[2] = (c >> 8) & 0xf. tmp64 ). r3. ctl[2]. tmp[31:24] = ReadByte( mode. ctl[0]. r2. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.

Chapter 8. Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2.f64 register operands and constant immediate values.f32 and . 2010 81 . Floating-Point Instructions Floating-point instructions operate on .7.

f64 mad. 2010 .PTX ISA Version 2.neg.rnd.f32 {mad.sqrt}.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.sub.f32 rsqrt.target sm_20 .fma}.max}. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. {mad.f32 {div.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.mul}.min.ftz .rp . Double-precision instructions support subnormal inputs and results.sub. 82 January 24.rz .target sm_20 mad.rn and instructions may be folded into a multiply-add.rn and instructions may be folded into a multiply-add. Table 46. mul.f64 div. .neg.32 and fma.f32 {div.f32 {abs.max}. NaN payloads are supported for double-precision instructions.f32 {div. with NaNs being flushed to positive zero.rnd.fma}.rm .rcp.approx. default is .rcp.rn .rnd.f32 {add.rcp. so PTX programs should not rely on the specific single-precision NaNs being generated.target sm_1x No rounding modifier.f32 are the same. Instruction Summary of Floating-Point Instructions .0].f32 .f64 and fma.f64 rsqrt. 1.rnd.sqrt}.approx. The optional .f64 {abs.cos. No rounding modifier. {add.rnd. sub.lg2. If no rounding modifier is specified. but single-precision instructions return an unspecified NaN. Single-precision add.sqrt}.approx. .rnd. and mad support saturation of results to the range [0.f64 {sin.f64 are the same.0 The following table summarizes floating-point instructions in PTX.min.0.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.approx.mul}.sat Notes If no rounding modifier is specified.ex2}. default is . Note that future implementations may support NaN payloads for single-precision instructions.full.

Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. . Introduced in PTX ISA version 2.f32 copysign.type . . f0. p. . .f64 }. copysign. . copysign requires sm_20 or later. copysign. . true if the input is a subnormal number (not NaN. positive and negative zero are considered normal numbers.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. testp requires sm_20 or later.finite. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. 2010 83 . B. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. A.op. C.f64 }.normal testp. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Table 48.f64 x.f64 isnan. .op p. not infinity).f32 testp. testp.f32. .number testp.subnormal }.infinite. // result is .normal. a. b.type = { . z. X.Chapter 8. testp.0.infinite.pred = { .0. testp.infinite testp. testp Syntax Floating-Point Instructions: testp Test floating-point property. Instruction Set Table 47.f32. January 24. .type d.notanumber.type = { .notanumber testp. not infinity) As a special case.notanumber. y.number.finite testp. and return the result as d.

Rounding modifiers (default is . a.f64 supports subnormal numbers.ftz}{. .f2. add.rp }.rnd = { .sat}.sat. b. In particular. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_20 Examples @p add.f32 f1.rz.rm. requires sm_13 for add.rz available for all targets .f32 clamps the result to [0.rp for add.f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. .f32 flushes subnormal inputs and results to sign-preserving zero. Rounding modifiers have the following target requirements: . NaN results are flushed to +0. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Saturation modifier: . add.rnd}{.f3. sm_1x: add.f32 flushes subnormal inputs and results to sign-preserving zero. add{.rn): . . 2010 .rn mantissa LSB rounds to nearest even . b. a.rm. .rn.0. .rz mantissa LSB rounds towards zero . add. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add. d.rz. 1.ftz.PTX ISA Version 2.0.rnd}. subnormal numbers are supported.f64 d.0f. d = a + b. add Syntax Floating-Point Instructions: add Add two values.rm mantissa LSB rounds towards negative infinity . .0 Table 49.f64 requires sm_13 or later.rn.f64. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 add{.f32 supported on all target architectures. add. 84 January 24.0].

Saturation modifier: sub.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. d.f32. subnormal numbers are supported. sub.f32 clamps the result to [0. b.f32 flushes subnormal inputs and results to sign-preserving zero.rn): .ftz}{. 2010 85 . . 1.ftz.0. b. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sm_1x: sub.rn.f32 supported on all target architectures.f32 c. Instruction Set Table 50.rp }.sat.f32 f1. In particular.rn. a.rnd}{.sat}.rp for sub.f3.0f. Rounding modifiers (default is .a.rm.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f2.rz mantissa LSB rounds towards zero . requires sm_13 for sub.rnd = { . . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. Rounding modifiers have the following target requirements: . .rz available for all targets .f64.rm mantissa LSB rounds towards negative infinity . .0.rn. sub.f64 requires sm_13 or later. a. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. sub Syntax Floating-Point Instructions: sub Subtract one value from another.0].b. sub{. NaN results are flushed to +0.b.rnd}. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm.rn mantissa LSB rounds to nearest even . sub.f32 sub{.Chapter 8. requires sm_20 Examples sub.rz. January 24. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sub.f64 supports subnormal numbers. sub. d = a .f64 d. .

0f. . requires sm_13 for mul. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. d. . .rn): . all operands must be the same size. Description Semantics Notes Compute the product of two values.rz available for all targets . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.pi // a single-precision multiply 86 January 24. mul.f64 supports subnormal numbers.rm. Rounding modifiers have the following target requirements: .f64 d.rm mantissa LSB rounds towards negative infinity . 1.ftz.0].rz mantissa LSB rounds towards zero . In particular.rn.rn mantissa LSB rounds to nearest even . NaN results are flushed to +0.f32. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. b.f32 flushes subnormal inputs and results to sign-preserving zero.rp }. mul.rm. 2010 .radius.0.rp for mul. . subnormal numbers are supported.rz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { .ftz.f32 mul{.ftz}{.f64.f32 supported on all target architectures.rnd}. For floating-point multiplication.f32 clamps the result to [0.f32 circumf.rn.rnd}{. a. requires sm_20 Examples mul. a. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. mul{.sat}. d = a * b. mul Syntax Floating-Point Instructions: mul Multiply two values.PTX ISA Version 2. .0. Saturation modifier: mul. Rounding modifiers (default is .sat. sm_1x: mul.f64 requires sm_13 or later. mul.0 Table 51. mul. . b.

.rz.sat}. a.rn. subnormal numbers are supported. fma.f64 introduced in PTX ISA version 1. again in infinite precision. fma. fma.f32 fma.f64 supports subnormal numbers. fma Syntax Floating-Point Instructions: fma Fused multiply-add.f32 flushes subnormal inputs and results to sign-preserving zero.z.c. b. a.ftz. fma. fma.rz mantissa LSB rounds towards zero . d.f64 w.rnd = { . 1.f64 is the same as mad. c.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 clamps the result to [0.ftz}{. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0. Instruction Set Table 52.f64. Rounding modifiers (no default): .rp }. again in infinite precision. c.f32 computes the product of a and b to infinite precision and then adds c to this product. d.f32 fma. Saturation: fma. .a.f32 requires sm_20 or later.sat. The resulting value is then rounded to single precision using the rounding mode specified by . b.f32 introduced in PTX ISA version 2.b. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rnd{. fma. 2010 87 .Chapter 8. NaN results are flushed to +0. fma.rnd.y.rn mantissa LSB rounds to nearest even . PTX ISA Notes Target ISA Notes Examples January 24. The resulting value is then rounded to double precision using the rounding mode specified by .rn.rnd.rm. .rn.4.ftz. fma.rm mantissa LSB rounds towards negative infinity .f32 is unimplemented in sm_1x.0]. @p fma.0f. fma.f64 requires sm_13 or later. fma. d = a*b + c.0.rnd.x. sm_1x: fma.f64 d.

0 Table 53.target sm_1x: mad.sat}.f32 flushes subnormal inputs and results to sign-preserving zero.f32.f64 computes the product of a and b to infinite precision and then adds c to this product. In this case.target sm_20: mad. // .0. .rn mantissa LSB rounds to nearest even . sm_1x: mad. mad.target sm_20 d.0 devices.ftz}{. Description Semantics Notes Multiplies two values and adds a third. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. NaN results are flushed to +0.{f32. again in infinite precision.0].f64. Note that this is different from computing the product with mul.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz.f32 mad. When JIT-compiled for SM 2.f32). c. mad. // .f32 is when c = +/-0.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. // .0. The resulting value is then rounded to double precision using the rounding mode specified by .rn.f32 mad.. mad.PTX ISA Version 2. The resulting value is then rounded to single precision using the rounding mode specified by .rm.rm mantissa LSB rounds towards negative infinity .f64 is the same as fma.e. d = a*b + c. mad.f32 computes the product of a and b to infinite precision and then adds c to this product. b. Unlike mad. mad. Rounding modifiers (no default): . a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.rnd.sat}. 1. again in infinite precision. the treatment of subnormal inputs and output follows IEEE 754 standard.f64} is the same as fma. where the mantissa can be rounded and the exponent will be clamped.rnd.rn.rnd = { . and then writes the resulting value into a destination register. mad. mad. mad. subnormal numbers are supported.f64}. . and then the mantissa is truncated to 23 bits.sat.f32 is identical to the result computed using separate mul and add instructions.rnd{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. c. For . For . 88 January 24.rnd.rnd. a.rz mantissa LSB rounds towards zero . The exception for mad. Saturation modifier: mad.ftz}{. 2010 . mad{. .f32 is implemented as a fused multiply-add (i.rz. b. mad.f32 clamps the result to [0. The resulting value is then rounded to double precision using the rounding mode specified by . b. fma. c.ftz.f64 supports subnormal numbers. but the exponent is preserved.0f. a.target sm_1x d.f32 computes the product of a and b at double precision. again in infinite precision.{f32.target sm_13 and later .rp }.

f64. Legacy mad.. requires sm_13 .f64.f32 for sm_20 targets. requires sm_20 Examples @p mad.f32 supported on all target architectures..rn..0 and later. Target ISA Notes mad.rp for mad.c.f32.rz. In PTX ISA versions 2.a.rp for mad.b. Rounding modifiers have the following target requirements: .rn.. a rounding modifier is required for mad. a rounding modifier is required for mad. January 24. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.Chapter 8.f64 instructions having no rounding modifier will map to mad.rz. In PTX ISA versions 1.f64 requires sm_13 or later.rm..4 and later.rn. mad.rm. 2010 89 .0.f32 d..f64.

full. Fast. . div. 2126].ftz.0 Table 54. . . a. div Syntax Floating-Point Instructions: div Divide one value by another.rz. d.approx.3.ftz.approx. b.f32 div.0 through 1.f64 diam.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. div. or .f32 and div.rn mantissa LSB rounds to nearest even .rnd{. z. y.3. Subnormal inputs and results are flushed to sign-preserving zero.PTX ISA Version 2.f32 requires sm_20 or later. computed as d = a * (1/b). div. div.rnd = { .4.{rz.f32 div. PTX ISA Notes div.f64.rn. div. yd. The maximum ulp error is 2 across the full range of inputs. Target ISA Notes div.f64 supports subnormal numbers. For PTX ISA version 1.circum. d. x. b. .f64 introduced in PTX ISA version 1.rm. a.ftz. 2010 . and rounding introduced in PTX ISA version 1.rn.approx. approximate single-precision divides: div. For b in [2-126.rz mantissa LSB rounds towards zero .approx.f32 defaults to div.ftz}. and div. Fast. b. div.14159.4 and later.full. Description Semantics Notes Divides a by b.rm mantissa LSB rounds towards negative infinity .f32 div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . one of .0.f32 div.f32 and div. full-range approximation that scales operands to achieve better accuracy.rnd is required.ftz.full{. . a. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . For PTX ISA versions 1. but is not fully IEEE 754 compliant and does not support rounding modifiers.ftz}.f64 defaults to div.f32 implements a relatively fast. stores result in d. d.f64 d. xd.f64 requires sm_13 or later. . div.approx{. subnormal numbers are supported.full. b. div. // // // // fast.rn. a.rm.full.f32 div. d = a / b.approx.f32 flushes subnormal inputs and results to sign-preserving zero. Examples 90 January 24.rnd.f64 requires sm_20 or later.f32.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. div.full.rnd.rn.f32 supported on all target architectures. Explicit modifiers .approx.rp }. approximate division by zero creates a value of infinity (with same sign as a).f32 implements a fast approximation to divide.rp}. zd. the maximum ulp error is 2. sm_1x: div.

f32 abs. a.f64 requires sm_13 or later. 2010 91 . abs{. January 24.0. abs. Table 56.f32 supported on all target architectures.ftz. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs.0.f32 x.f0. neg. neg{.f32 supported on all target architectures. neg.f64 requires sm_13 or later. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. Instruction Set Table 55. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.f32 x.f64 supports subnormal numbers. NaN inputs yield an unspecified NaN.f32 neg. NaN inputs yield an unspecified NaN. d = |a|.ftz. Negate the sign of a and store the result in d. a.ftz.ftz}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs. d. Take the absolute value of a and store the result in d. sm_1x: abs. a.ftz}.f64 d. d = -a. d. Subnormal numbers: sm_20: By default.ftz. subnormal numbers are supported. neg.Chapter 8.f64 supports subnormal numbers. a. sm_1x: neg.f64 d. abs. neg.f32 flushes subnormal inputs and results to sign-preserving zero. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs.f32 flushes subnormal inputs and results to sign-preserving zero.f0.f32 flushes subnormal inputs and results to sign-preserving zero.

b.f32 max.f32 max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b. min{. sm_1x: min. a.ftz. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. Store the maximum of a and b in d.f64 supports subnormal numbers. Table 58. b. max.f64 requires sm_13 or later. b.f2.f32 supported on all target architectures.b.c.ftz. sm_1x: max.f32 supported on all target architectures. a. d. 2010 .f64 f0.ftz}.b. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.0.0. 92 January 24.ftz. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f1. d d d d = = = = NaN. @p min.c. subnormal numbers are supported.z. b. min. Store the minimum of a and b in d.f64 d. (a > b) ? a : b.f32 flushes subnormal inputs and results to sign-preserving zero.x. a. min. min. (a < b) ? a : b.f32 flushes subnormal inputs and results to sign-preserving zero. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 min.0 Table 57.f64 z.f64 d. d. a. subnormal numbers are supported.f32 min.ftz. max.f64 supports subnormal numbers.PTX ISA Version 2.ftz}. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. a.f64 requires sm_13 or later. d d d d = = = = NaN.f32 flushes subnormal inputs and results to sign-preserving zero. a. b.f32 flushes subnormal inputs and results to sign-preserving zero. max{. min. a. max. max. max.

rcp. 2010 93 . rcp.rnd is required.0.f64 supports subnormal numbers. one of .ftz}.f32 defaults to rcp. rcp.0 +subnormal +Inf NaN Result -0.r.{rz.4 and later.f32 flushes subnormal inputs and results to sign-preserving zero.approx and .ftz.f32 rcp.f32 rcp.approx. d.f64 defaults to rcp. d. .rn.ftz.0 over the range 1.ftz.ftz. The maximum absolute error is 2-23.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. For PTX ISA versions 1.approx.f64 d. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 ri.approx.0.approx or .f32 requires sm_20 or later.Chapter 8. rcp. PTX ISA Notes rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.ftz were introduced in PTX ISA version 1.rp }.f32 rcp. Examples January 24.f32.rn mantissa LSB rounds to nearest even .3.0 through 1.f64. sm_1x: rcp.rn.f64 requires sm_20 or later.f64 introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f32 rcp.0 +0.0 -Inf -Inf +Inf +Inf +0.f64 and explicit modifiers . // fast. General rounding modifiers were added in PTX ISA version 2. Instruction Set Table 59. rcp. rcp. rcp.rn.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64 requires sm_13 or later. store result in d.0. Input -Inf -subnormal -0.f32 supported on all target architectures. d = 1 / a. and rcp. rcp. xi. subnormal numbers are supported.rz. rcp.4.rn.rnd{.f32 implements a fast approximation to reciprocal.rp}. xi.rm mantissa LSB rounds towards negative infinity .0-2.rnd.approx{.rm. Target ISA Notes rcp. a.rnd.x. a.f32 and rcp.rm. For PTX ISA version 1. Description Semantics Notes Compute 1/a.ftz}.approx. a.rn. .rz mantissa LSB rounds towards zero .rn. rcp.rnd = { .x. .

f32 sqrt.rnd = { . sqrt. subnormal numbers are supported.rm mantissa LSB rounds towards negative infinity . // IEEE 754 compliant rounding d.rp }.rn.0 +0.f32 sqrt. For PTX ISA versions 1.f64 d.approx.f32 and sqrt.approx.approx.rn mantissa LSB rounds to nearest even .rn.0 +0. sqrt.f64 introduced in PTX ISA version 1.rn. sqrt. PTX ISA Notes sqrt. d = sqrt(a). store in d.ftz.f64 r.rn.0 -0.0 +0. sm_1x: sqrt. sqrt.f64 requires sm_20 or later. r. Input -Inf -normal -subnormal -0.ftz.0 +subnormal +Inf NaN Result NaN NaN -0.rnd{. // fast.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . approximate square root d.f64 and explicit modifiers .rn. Description Semantics Notes Compute sqrt(a).f32.ftz}. The maximum absolute error for sqrt.ftz}.rn. sqrt. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.4 and later.f32 flushes subnormal inputs and results to sign-preserving zero.f64.ftz were introduced in PTX ISA version 1.f64 defaults to sqrt.x.{rz.rnd. a. .approx. sqrt.f32 implements a fast approximation to square root.0 through 1. r. Examples 94 January 24.f32 is TBD.rz mantissa LSB rounds towards zero . // IEEE 754 compliant rounding . sqrt.0 Table 60.PTX ISA Version 2.f32 sqrt.approx or .0.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.rz.rnd is required.approx{. . one of .rm.4.rnd. sqrt. Target ISA Notes sqrt.x.f32 requires sm_20 or later. sqrt.f64 supports subnormal numbers. 2010 .ftz.3. For PTX ISA version 1.rm.f64 requires sm_13 or later. a. sqrt. and sqrt.f32 sqrt. General rounding modifiers were added in PTX ISA version 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp}.0.f32 defaults to sqrt.approx and .approx. .f32 supported on all target architectures.x. a.

Instruction Set Table 61.f64 defaults to rsqrt.approx{. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt.f64 isr.0.ftz. sm_1x: rsqrt.f64 were introduced in PTX ISA version 1.approx.approx. ISR.f32 rsqrt. For PTX ISA version 1. rsqrt.f64 is TBD.f32 flushes subnormal inputs and results to sign-preserving zero. X.4. The maximum absolute error for rsqrt.0 through 1.approx and .Chapter 8.f32 rsqrt. store the result in d. x.f64 requires sm_13 or later.ftz. rsqrt. rsqrt.f32 supported on all target architectures. Compute 1/sqrt(a). d = 1/sqrt(a). a. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. and rsqrt. For PTX ISA versions 1. rsqrt.f64 d.f32 is 2-22.4 over the range 1.ftz. rsqrt. PTX ISA Notes rsqrt.f32 and rsqrt.f64.ftz were introduced in PTX ISA version 1. d. Input -Inf -normal -subnormal -0.approx.approx. the . Explicit modifiers .f32 defaults to rsqrt. Target ISA Notes Examples rsqrt. a.f64 is emulated in software and are relatively slow.approx modifier is required. 2010 95 .approx.approx. Subnormal numbers: sm_20: By default.3. subnormal numbers are supported.0-4. Note that rsqrt.0 NaN The maximum absolute error for rsqrt.approx implements an approximation to the reciprocal square root. January 24.0 +0.f64 supports subnormal numbers.f32.4 and later.ftz}.0.

3. a.0 +subnormal +Inf NaN Result NaN -0. sin.0 NaN NaN The maximum absolute error is 2-20.0 Table 62.ftz.approx modifier is required. For PTX ISA versions 1. Find the sine of the angle a (in radians). sin.approx.ftz introduced in PTX ISA version 1.approx.PTX ISA Version 2.f32 d. sin. a. sin.f32 defaults to sin.0 -0. Target ISA Notes Examples Supported on all target architectures.ftz.0 +0.approx{.0 +0. d = sin(a). sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx and .4 and later. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers . the .0 through 1. Input -Inf -subnormal -0.f32.9 in quadrant 00.ftz}. 96 January 24. sin. For PTX ISA version 1.f32 sa.0 +0.f32 implements a fast approximation to sine.0. 2010 .4. PTX ISA Notes sin. subnormal numbers are supported.f32 introduced in PTX ISA version 1.approx.

Explicit modifiers .ftz. subnormal numbers are supported. cos. Find the cosine of the angle a (in radians).approx.0.4 and later. d = cos(a). Target ISA Notes Examples Supported on all target architectures.approx and . cos.Chapter 8.ftz. cos. the . Subnormal numbers: sm_20: By default.approx.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1. For PTX ISA versions 1. 2010 97 .approx{.f32 ca.9 in quadrant 00.0 +subnormal +Inf NaN Result NaN +1.f32 introduced in PTX ISA version 1. a.ftz}. January 24. For PTX ISA version 1. Instruction Set Table 63. a.f32.f32 implements a fast approximation to cosine.0 +1.ftz introduced in PTX ISA version 1.f32 defaults to cos. PTX ISA Notes cos. cos.4.0 NaN NaN The maximum absolute error is 2-20.0 +1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. Input -Inf -subnormal -0.0 +0.ftz.approx.f32 d.0 +1. sm_1x: Subnormal inputs and results to sign-preserving zero.3.approx modifier is required. cos.

approx modifier is required. lg2.f32 defaults to lg2.approx. d = log(a) / log(2). 2010 .0.approx.ftz}.approx and . sm_1x: Subnormal inputs and results to sign-preserving zero.f32.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers . lg2. lg2.ftz.approx.f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default.ftz. For PTX ISA versions 1.f32 Determine the log2 of a. PTX ISA Notes lg2. The maximum absolute error is 2-22. a. For PTX ISA version 1. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.0 Table 64.4 and later.0 +0.0 through 1.3. a. lg2.PTX ISA Version 2. subnormal numbers are supported. lg2. the . Target ISA Notes Examples Supported on all target architectures. 98 January 24.ftz.6 for mantissa.4.approx{.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Input -Inf -subnormal -0.f32 la.ftz introduced in PTX ISA version 1.f32 implements a fast approximation to log2(a).

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

u16. gt. gt.type = { .type setp. setp. ge. and hs for lower. unordered versions are included: equ.s16. p[|q]. subnormal numbers are supported. This result is written to the first destination operand. gt.BoolOp{. . setp with . The signed and unsigned comparison operators are eq.pred variables.f32. gtu. neu.dtype. le. num. The destinations p and q must be .dtype. ge. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. . gt.f64 supports subnormal numbers. . setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. and higher-or-same may be used instead of lt. Modifier . le. q = BoolOp(!t. . lt. lt.ftz}. le.i.ftz applies only to . nan The Boolean operator BoolOp(A. respectively. ls. leu.type .lt. hs equ.b16.s32 setp. and can be one of: eq.and.r.0.u32 p|q. {!}c. ltu. lt. sm_1x: setp.eq.CmpOp{.u32. Semantics t = (a CmpOp b) ? 1 : 0. ne. .u64.b. leu.s32. b.ftz}. higher.f64 source type requires sm_13 or later.f32 flushes subnormal inputs to sign-preserving zero.PTX ISA Version 2. . setp.0 Table 67. p[|q].a. ne. or.f64 }. then the result of these comparisons is true. Applies to all numeric types. The untyped.f32 comparisons.s64. Integer Notes Floating Point Notes The ordered comparisons are eq. the comparison operators lo. and nan returns true if either operand is NaN. c). . gtu.B) is one of: and. If both operands are numeric values (not NaN). p. For unsigned values. the result is false. a. A related value computed using the complement of the compare result is written to the second destination operand. hi. Subnormal numbers: sm_20: By default.b64. ge. ltu. ls. xor. To aid comparison operations in the presence of NaN values. b. If either operand is NaN. p = BoolOp(t. c). . bit-size comparisons are eq and ne. num returns true if both operands are numeric values (not NaN).b32. ne. le. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz.n.dtype. a. 2010 .CmpOp. then these comparisons have the same result as their ordered counterparts.f32 flushes subnormal inputs to sign-preserving zero. hi. ge. geu. geu. 102 January 24. neu. The comparison operator is a suffix on the instruction. loweror-same. lo. setp. . If either operand is NaN. and (optionally) combine this result with a predicate value by applying a Boolean operator. @q setp. .

b. f0. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. If c is True. C.f32 flushes subnormal values of operand c to sign-preserving zero. Table 69. a.type = { . .b32. d = (c == 1) ? a : b. . .s32 slct{.s16.s32.f32. Operand c is a predicate.f32. . .f32 A. Introduced in PTX ISA version 1. If c ≥ 0.p.u16. selp.s16.f64 }. c.u32. slct. .dtype. . If operand c is NaN.u64. based on the sign of the third operand. y. b.f64 }. Description Conditional selection. and b must be of the same type.u64. slct. and b are treated as a bitsize type of the same width as the first instruction type. c. selp. slct.dtype. . . negative zero equals zero. . .u16. Semantics Floating Point Notes January 24. val. . .u32. @q selp.f32 d. d.f64 requires sm_13 or later.xp. a. .dtype = { .t. a is stored in d.s64. .b16.f32 flushes subnormal values of operand c to sign-preserving zero. operand c must match the second instruction type.b32. a is stored in d. slct.ftz.f32 r0.g. B. . subnormal numbers are supported. fval. 2010 103 . a.Chapter 8. . . based on the value of the predicate source operand.f64 requires sm_13 or later.f32 comparisons.0.x. . selp Syntax Comparison and Selection Instructions: selp Select between source operands. and operand a is selected. b.ftz.dtype. Instruction Set Table 68.s64. sm_1x: slct. and operand a is selected. d = (c >= 0) ? a : b. Subnormal numbers: sm_20: By default.dtype. slct. Operands d.s32 x.r. b otherwise. c. . The selected input is copied to the output without modification.b64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b16.u64.ftz}.type d.0. Modifier . a. z.f32 comparisons.s32. a.ftz applies only to . otherwise b is stored in d. .u32. For . slct Syntax Comparison and Selection Instructions: slct Select one source operand. the comparison is unordered and operand b is selected. . Operands d.b64.s32 selp.

2010 . or. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. provided the operands are of the same size. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.7.0 8. Instructions and. xor. and not also operate on predicates. performing bit-wise operations on operands of any type.4. This permits bit-wise operations on floating point values without having to define a union to access the bits.PTX ISA Version 2.

pred p. a.b32. . Allowed types include predicate registers.Chapter 8. .0x00010001 or. and Syntax Logic and Shift Instructions: and Bitwise AND.type d.pred. but not necessarily the type. .b32 x. Supported on all target architectures. a.0x80000000. .b32 and. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. .q. Allowed types include predicate registers. sign. but not necessarily the type.0. or. and. Instruction Set Table 70. . Table 71.type d. Supported on all target architectures.type = { .b32. .b16. and.pred.q. b. The size of the operands must match. 2010 105 .b32 mask mask. d = a & b.fpvalue.b16. b. Introduced in PTX ISA version 1.b64 }.r. January 24. .0. d = a | b. or Syntax Logic and Shift Instructions: or Bitwise OR.type = { . Introduced in PTX ISA version 1. or.r. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. The size of the operands must match.b64 }.

type = { .q. xor. The size of the operands must match.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.type d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. d.0. .mask.0 Table 72. Allowed types include predicate registers. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.x. but not necessarily the type. d = (a==0) ? 1 : 0. . Introduced in PTX ISA version 1.b64 }.b32 xor.b32 d. . .0x0001. but not necessarily the type. The size of the operands must match.a.pred. Supported on all target architectures.type = { . . . Supported on all target architectures. one’s complement. . 106 January 24.b16 d.PTX ISA Version 2. a. cnot.b32. not. Allowed types include predicates.0.type = { . Supported on all target architectures. The size of the operands must match. b. a. d = a ^ b. . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). 2010 . Introduced in PTX ISA version 1.0. not. . but not necessarily the type.type d.pred p. Introduced in PTX ISA version 1. xor.b16. not Syntax Logic and Shift Instructions: not Bitwise negation. . Table 74.r. a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. cnot. .pred.b16. d = ~a.b32.b32 mask. not.b16.q.b64 }. Table 73.type d.b64 }.

u32.s32. .j. PTX ISA Notes Target ISA Notes Examples Table 76.b16.type d. The sizes of the destination and first source operand must match. . b.i. zero-fill on right.b16 c. The b operand must be a 32-bit value. . . a. shl.0.type d. .2. Instruction Set Table 75.b32.b64.b16. .u16 shr.2.i. b.a. Introduced in PTX ISA version 1. 2010 107 . Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. PTX ISA Notes Target ISA Notes Examples January 24. k. . unsigned and untyped shifts fill with 0. regardless of the instruction type. shr Syntax Logic and Shift Instructions: shr Shift bits right. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Supported on all target architectures. a. d = a >> b. The sizes of the destination and first source operand must match. Shift amounts greater than the register width N are clamped to N.b32. Supported on all target architectures. . .0. shr.s32 shr. Bit-size types are included for symmetry with SHL.b64 }. Signed shifts fill with the sign bit. .type = { . regardless of the instruction type.a.b32 q. but not necessarily the type. .u64.Chapter 8. d = a << b.type = { . Shift amounts greater than the register width N are clamped to N.u16. Introduced in PTX ISA version 1.s64 }.s16. i. shl. . The b operand must be a 32-bit value. sign or zero fill on left. shl Syntax Logic and Shift Instructions: shl Shift bits left.1. shr. but not necessarily the type.

The cvta instruction converts addresses between generic and global. Instructions ld. local.5. or shared state spaces. st.7.0 8.PTX ISA Version 2. prefetchu isspacep cvta cvt 108 January 24. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. mov. suld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. Data Movement and Conversion Instructions These instructions copy data from place to place. 2010 . and from state space to state space. and sust support optional cache operations. ld. and st operate on both scalar and vector types. possibly converting it from one format to another. ldu.

7. The ld. A ld. Instruction Set 8.cv Cache as volatile (consider cached system memory lines stale. Use ld. to allow the thread program to poll a SysMem location written by the CPU.cg Cache at global level (cache in L2 and below.cv to a frame buffer DRAM address is the same as ld. The ld.5. likely to be accessed once. For sm_20 and later.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Cache Operators PTX 2. the cache operators have the following definitions and behavior. when applied to a local address. As a result of this request. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Table 77. Operator .lu Last use. .lu load last use operation. 2010 109 . .cs is applied to a Local window address. not L1). and cache only in the L2 cache.cs. The default load instruction cache operation is ld. The ld.lu instruction performs a load cached streaming operation (ld. If one thread stores to global memory via one L1 cache.1.ca loads cached in L1. fetch again).ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. it performs the ld.ca. if the line is fully covered. When ld. invalidates (discards) the local L1 line following the load. and a second thread loads that address via a second L1 cache with ld.0 introduces optional cache operators on load and store instructions. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. January 24.cs) on global addresses. The cache operators require a target architecture of sm_20 or later. evict-first. . The ld. The compiler / programmer may use ld. any existing cache lines that match the requested address in L1 will be evicted.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.lu operation. likely to be accessed again. Global data is coherent at the L2 level.ca.Chapter 8.cg to cache loads only globally. bypassing the L1 cache. rather than the data stored by the first thread. . the second thread may get stale L1 cache data.cs Cache streaming. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. but multiple L1 caches are not coherent for global data.

and a second thread in a different SM later loads from that address via a different L1 cache with ld. the second thread may get a hit on stale L1 cache data. and discard any L1 lines that match. bypassing the L1 cache.cs Cache streaming. rather than get the data from L2 or memory stored by the first thread. Addresses not in System Memory use normal write-back.wb for global data. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. not L1).cg to local memory uses the L1 cache. and marks local L1 lines evict-first. in which case st. but st. st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.wb could write-back global store data from L1.ca loads. The default store instruction cache operation is st.wt Cache write-through (to system memory). If one thread stores to global memory.cg to cache global store data only globally. and cache only in the L2 cache. Global stores bypass L1. 110 January 24.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Operator .wb. bypassing its L1 cache.0 Table 78.wt. to allow a CPU program to poll a SysMem location written by the GPU with st. However. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. regardless of the cache operation. Use st. Future GPUs may have globally-coherent L1 caches. .cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. .PTX ISA Version 2. The st. likely to be accessed once. which writes back cache lines of coherent cache levels with normal eviction policy.ca.cg Cache at global level (cache in L2 and below. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. The st. In sm_20. 2010 . .cg is the same as st. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.

shared state spaces. . sreg.1. Introduced in PTX ISA version 1. and . d. A[5].f64 requires sm_13 or later.Chapter 8. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. alternately. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. .u32.b64.b16.type d.u32 d.type = { . The generic address of a variable in global. // get address of variable // get address of label or function . Write register d with the value of a.type mov. Operand a may be a register. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.f32 mov. mov. d. local. .u32 mov. . immediate.a.f32.e. avar. mov. variable in an addressable memory space.0..type mov. i. ptr. within the variable’s declared state space Notes Although only predicate and bit-size types are required. Note that if the address of a device function parameter is moved to a register. mov places the non-generic address of the variable (i. or shared state space.s64.const. a. the parameter will be copied onto the stack and the address will be in the local state space. special register.u32 mov. Instruction Set Table 79. d. or shared state space may be taken directly using the cvta instruction. d = &label. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. . k. For variables declared in . Take the non-generic address of a variable in global.u16..f32 mov.global.v. .u16 mov. mov. myFunc. label. addr. A. 2010 111 . // address is non-generic.b32. local. the generic address of a variable declared in global. . .s16.local. Description .pred. ptr. the address of the variable in its state space) into the destination register.u64. local.e. . d = &avar.s32. Semantics d = a. u.0. .type mov. label. . or function name. d = sreg.f64 }. .

hi}.b32 // pack two 16-bit elements into .type = { .47]. a[16.b32 mov. d. a[8. {lo..b32..0 Table 80.a}.x | (a.g.x.y << 32) // pack two 8-bit elements into ... a[8.b64 mov.z << 32) | (a.{a.31]. Supported on all target architectures.x | (a.b32 mov.15].b32 { d.31] } // unpack 16-bit elements from .z.y.y } = { a[0.15]. a[32.. mov.y << 16) d = a.y.w } = { a[0. d.15] } // unpack 8-bit elements from . For bit-size types.63] } // unpack 16-bit elements from .x | (a.y. %x. lo.b32 { d. a[32..y } = { a[0..w have type .7]. a..31] } // unpack 8-bit elements from . Description Write scalar register d with the packed value of vector register a..z. a[16. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b16. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.%r1.z << 16) | (a.x.z.x | (a..b16 // pack four 8-bit elements into .b8 r.w } = { a[0. Semantics d = a.y.b16 { d.b32 %r1. .y << 8) d = a.y << 16) | (a.b}. 2010 .z.b64 { d. d.a have type .15].y } = { a[0.b64 112 January 24.31]. mov. a[48..w}.type d.w << 24) d = a.x.u32 x.7]. {r.x. .hi are .b.23].{x. d. d.0. %r1.b64 }. d.b64 { d. // // // // a. d.u8 // unpack 32-bit elements from .b have type .b64 // pack two 32-bit elements into .w << 48) d = a.x | (a. a[16.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 // pack four 16-bit elements into . a[24. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). . d.y << 8) | (a.PTX ISA Version 2.u16 %x is a double.. d..x.. or write vector register d with the unpacked values from scalar register a.b.g.

.u16. 32-bit).const space suffix may have an optional bank number to indicate constant banks other than bank zero.s32. or the instruction may fault. . . The . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. [a]. Generic addressing may be used with ld. The value loaded is sign-extended to the destination register width for signed integers.cs. ld introduced in PTX ISA version 1.cg. Cache operations are not permitted with ld.vec = { . . Semantics d d d d = = = = a. an address maps to the corresponding location in local or shared memory. for example.Chapter 8. .ss}{.local.global and .volatile may be used with .0. . or [immAddr] an immediate absolute byte address (unsigned. [a]. *(immAddr). . i. .volatile{.shared }. to enforce sequential consistency between threads accessing shared memory. . ld{. .f32 or .volatile introduced in PTX ISA version 1. .b16.cv }. [a]. If an address is not properly aligned.cop = { .u8..ca. . Addresses are zero-extended to the specified width as needed. . perform the load using generic addressing.lu.type d. . In generic addressing.vec.type ld. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. d. Within these windows. . . .e. ld.ss = { . 32-bit).b32.f64 using cvt.volatile{. and then converted to .0. The address size may be either 32-bit or 64-bit.1. The address must be naturally aligned to a multiple of the access size.s16.u64. *a. If no state space is given.ss}{.b8. This may be used. Generic addressing and cache operations introduced in PTX ISA 2. . .cop}. . d.type = { . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . A destination register wider than the specified type may be used.f64 }. 2010 113 .s8.param. and truncated if the register width exceeds the state space address width for the target architecture.v4 }. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.f32.shared spaces to inhibit optimization of references to volatile memory.volatile. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s64. ld.b64.vec.ss}.u32. and is zeroextended to the destination register width for unsigned and bit-size types. *(a+immOff). .volatile.cop}.type ld{.global.b16.e. an integer or bit-size type register reg containing a byte address. an address maps to global memory unless it falls within the local memory window or the shared memory window.v2. . [a]. d. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. PTX ISA Notes January 24. i.reg state space.const. Description Load register variable d from the location specified by the source address operand a in specified state space.ss}. Instruction Set Table 81.f16 data may be loaded using ld. the resulting behavior is undefined.type .

local. // access incomplete array x. Q.b32 ld.[p+-8].[p+4].const.PTX ISA Version 2.global.b32 ld. // negative offset %r.[p].f16 d. Cache operations require sm_20 or later. Generic addressing requires sm_20 or later.b32 ld.f64 requires sm_13 or later.const[4]. x. 2010 . %r.[240]. ld.%r.[fs].[buffer+64].global.b64 ld.0 Target ISA Notes ld.f32.local.v4.shared. // immediate address %r.f32 ld.b16 cvt.s32 ld.[a].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. // load . d.

.b32 d.f32 or . ldu. perform the load using generic addressing. ldu{.vec = { . where the address is guaranteed to be the same across all threads in the warp.f64 }. For ldu.global.global }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. an address maps to the corresponding location in local or shared memory.global.u64. Introduced in PTX ISA version 2.type ldu{. ldu. .s64. The address must be naturally aligned to a multiple of the access size.s16. Instruction Set Table 82.u16.f32 Q. The data at the specified address must be read-only. 32-bit). .s8.reg state space.ss}.global.f32 d. 32-bit).ss}.f16 data may be loaded using ldu.v2. and truncated if the register width exceeds the state space address width for the target architecture.b32. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. ldu. *(a+immOff). [areg] a register reg containing a byte address. . ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. In generic addressing. .b16.[p]. Semantics d d d d = = = = a. i. The value loaded is sign-extended to the destination register width for signed integers.vec. or [immAddr] an immediate absolute byte address (unsigned. an address maps to global memory unless it falls within the local memory window or the shared memory window.[a]. or the instruction may fault.f64 using cvt. . d. 2010 115 . the resulting behavior is undefined. The address size may be either 32-bit or 64-bit.ss = { . Within these windows. [a]. . .f64 requires sm_13 or later. i. . // state space . . Addresses are zero-extended to the specified width as needed. *(immAddr). . A destination register wider than the specified type may be used.e. and then converted to .b8.b16. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type d.s32. // load from address // vec load from address .b64. The addressable operand a is one of: [avar] the name of an addressable variable var. PTX ISA Notes Target ISA Notes Examples January 24. only generic addresses that map to global memory are legal.f32.0. . A register containing an address may be declared as a bit-size type or integer type. . *a. If no state space is given.v4 }. .Chapter 8.v4. . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. and is zeroextended to the destination register width for unsigned and bit-size types. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .[p+4].u8. . .type = { . [a].u32.e. ldu. If an address is not properly aligned.

. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .cop . 32-bit).local. 32-bit).vec.f32. . Semantics d = a. The address size may be either 32-bit or 64-bit. b.0.. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. . the resulting behavior is undefined. A source register wider than the specified type may be used.s64.type = = = = {.b16. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.e. *(immAddr) = a.s8. for example. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or the instruction may fault. The address must be naturally aligned to a multiple of the access size.wb.b16. [a].ss}{.cs.ss}{. st. st. { .ss . the access may proceed by silently masking off low-order address bits to achieve proper rounding. PTX ISA Notes Target ISA Notes 116 January 24. If no state space is given.s16.volatile. .PTX ISA Version 2. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. b.b8. { .ss}. an address maps to the corresponding location in local or shared memory.vec . .volatile{. Generic addressing and cache operations introduced in PTX ISA 2.type st. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.s32. *d = a. . . Within these windows.v2. { . 2010 . or [immAddr] an immediate absolute byte address (unsigned. If an address is not properly aligned.shared spaces to inhibit optimization of references to volatile memory. [a]. . Generic addressing requires sm_20 or later.vec. The lower n bits corresponding to the instruction-type width are stored to memory.cg.b32. b. .cop}. i.type . to enforce sequential consistency between threads accessing shared memory.wt }.reg state space. b. [a]. .1. and truncated if the register width exceeds the state space address width for the target architecture.0 Table 83.shared }.f16 data resulting from a cvt instruction may be stored using st.u32. . Generic addressing may be used with st.v4 }. i. an integer or bit-size type register reg containing a byte address. . st introduced in PTX ISA version 1. This may be used.global.volatile introduced in PTX ISA version 1.e. *(d+immOffset) = a.u64. .volatile. Cache operations require sm_20 or later. Cache operations are not permitted with st. st{. .volatile may be used with . In generic addressing.u16.f64 }. Addresses are zero-extended to the specified width as needed. .f64 requires sm_13 or later. an address maps to global memory unless it falls within the local memory window or the shared memory window. .type [a]. .volatile{.0.type st{. .ss}. perform the store using generic addressing.global and .b64. .u8. .cop}. st. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.

Q.Chapter 8.v4.%r. [q+-8].f16.b32 st. // negative offset [100]. [q+4]. // immediate address %r.local.f32 st.%r.local.s32 cvt.a.b32 st.global.local. [p]. // %r is 32-bit register // store lower 16 bits January 24. 2010 117 .global.b16 [a].r7.a. Instruction Set Examples st.b. [fs].s32 st.f32 st.

[reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. // prefetch to data cache // prefetch to uniform cache . the prefetch uses generic addressing. 32-bit).space = { . prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. The address size may be either 32-bit or 64-bit. and truncated if the register width exceeds the state space address width for the target architecture.local }. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.L1 [ptr]. A prefetch to a shared memory location performs no operation.L1 [a]. If no state space is given. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. Within these windows. in specified state space. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.L1. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.0 Table 84.level = { . or [immAddr] an immediate absolute byte address (unsigned.e. 118 January 24.level prefetchu.space}. Addresses are zero-extended to the specified width as needed. a register reg containing a byte address.L1 [addr]. 32-bit). an address maps to global memory unless it falls within the local memory window or the shared memory window. A prefetch into the uniform cache requires a generic address. and no operation occurs if the address maps to a local or shared memory location. prefetch and prefetchu require sm_20 or later. i.PTX ISA Version 2. prefetch{. prefetchu. prefetch.0. an address maps to the corresponding location in local or shared memory. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.global. In generic addressing. [a]. 2010 . . .L2 }. .global.

isshrd. local. islcl. a.pred.shared. svar.u32 p.global. 2010 119 . . // convert to generic address // get generic address of var // convert generic address to global. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. isspacep.u32 gptr.Chapter 8. or vice-versa.space. p. . The source address operand must be a register of type . cvta. .shared }. var. January 24.lptr.size cvta. gptr. .size p. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.to.global. local.global.space = { . A program may use isspacep to guard against such incorrect behavior. // local. Description Convert a global.u64 or cvt. Instruction Set Table 85. a. p. or shared address.to. isspacep requires sm_20 or later.local.u32 p. . When converting a generic address into a global. or shared state space. or shared state space.space. The destination register must be of type .space = { . or shared address cvta.pred .local. .0.space. For variables declared in global. local. local.shared isglbl.u32 or .0. Introduced in PTX ISA version 2. or shared address to a generic address. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32. a.global isspacep.shared }.size = { . or vice-versa. cvta.u64. cvta requires sm_20 or later. cvta. Use cvt. lptr.u32. // result is .local isspacep. // get generic address of svar cvta. isspacep. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. The source and destination addresses must be the same size.u64. the generic address of the variable may be taken using cvta. local. PTX ISA Notes Target ISA Notes Examples Table 86.u64 }.u32 to truncate or zero-extend addresses. Take the generic address of a variable declared in global. or shared state space to generic. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.genptr.local.space p.size . sptr.

and for same-size float-tofloat conversions where the value is rounded to an integer.PTX ISA Version 2. Integer rounding is illegal in all other instances.s16. ..f64 }.dtype. . . cvt{. . . . i.ftz.ftz.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.rni round to nearest integer. The optional .ftz.sat}.f32 float-to-integer conversions and cvt.ftz. For float-to-integer conversions.f32 float-to-integer conversions and cvt. 120 January 24. . . d = convert(a). d.frnd = { . Note that saturation applies to both signed and unsigned integer types.ftz modifier may be specified in these cases for clarity.s32.rz.frnd}{. a.s64.rzi round to nearest integer in the direction of zero .f32 float-tofloat conversions with integer rounding. . . choosing even integer if source is equidistant between two integers. .sat is redundant. .dtype. Saturation modifier: . i.e.f32.atype cvt{.sat}.dtype = .s8.ftz}{. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. Integer rounding is required for float-to-integer conversions.atype = { .rmi round to nearest integer in direction of negative infinity .rmi. .dtype. 2010 . .4 and earlier. . sm_1x: For cvt.f32. . subnormal numbers are supported.rp }. // integer rounding // fp rounding .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. Description Semantics Integer Notes Convert between different types and sizes.atype d.ftz}{.MAXINT for the size of the operation.irnd = { . . the . For cvt. Note: In PTX ISA versions 1.sat limits the result to MININT.dtype.e. the result is clamped to the destination range by default. .rm.u16. .u32. a.rzi.rn.0 Table 87.irnd}{. Integer rounding modifiers: .u8. . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. subnormal inputs are flushed to signpreserving zero.rpi }. subnormal inputs are flushed to signpreserving zero.rni. .sat For integer destination types.f32. The compiler will preserve this behavior for legacy PTX code.. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.u64.f32 float-tofloat conversions with integer rounding.f16.

and .f16.0.ftz modifier may be specified in these cases for clarity.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.ftz behavior for sm_1x targets January 24. The optional . NaN results are flushed to positive zero. if the PTX .s32 f. .Chapter 8. // note . The result is an integral value.f32. Saturation modifier: .f32. Specifically.f32.f32 x. // float-to-int saturates by default cvt. result is fp cvt.f32. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. cvt.i. cvt.f32 instructions.f32. Subnormal numbers: sm_20: By default. .rn mantissa LSB rounds to nearest even .4 and earlier. cvt to or from .f64 types. 2010 121 .4 or earlier.sat For floating-point destination types. 1.y. The operands must be of the same size. Applies to . and cvt. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16.r.s32.rm mantissa LSB rounds towards negative infinity .f64 j. Modifier . Floating-point rounding is illegal in all other instances.sat limits the result to the range [0.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Floating-point rounding modifiers: .f64. cvt. The compiler will preserve this behavior for legacy PTX code.version is 1.f64 requires sm_13 or later.f16. Note: In PTX ISA versions 1.0].0.rni.f32. subnormal numbers are supported.y. and for integer-to-float conversions.f32. Introduced in PTX ISA version 1. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32 x. stored in floating-point format.rz mantissa LSB rounds towards zero . // round to nearest int.

Module-scope and per-entry scope definitions of texture. r3. The advantage of independent mode is that textures and samplers can be mixed and matched. r6. // get tex1’s txq. {f1. r3. sampler.f32 r3. and surface descriptors.texref handle.f32. r5. add. The advantage of unified mode is that it allows 128 samplers.6. with the restriction that they correspond 1-to-1 with the 128 possible textures. r5.b32 r6.2d.PTX ISA Version 2.u32 r5. .7. .param . PTX supports the following operations on texture.r2. add. r4. and surfaces. [tex1]. sampler.samplerref tsamp1 = { addr_mode_0 filter_mode }. Texture and Surface Instructions This section describes PTX instructions for accessing textures.0 8.height. Ability to query fields within texture. and surface descriptors. [tex1].u32 r5. and surface descriptors: • • • Static initialization of texture. r1. 122 January 24. but the number of samplers is greatly restricted to 16. = nearest width height tsamp1.f32 {r1. In the independent mode. In the unified mode. sampler.b32 r5.r3. 2010 . add.r4}. . sampler. mul. samplers. If no texturing mode is declared.f32 r1. texture and sampler information each have their own handle. cvt. PTX has two modes of operation..f2}].f32. texture and sampler information is accessed through a single . [tex1.entry compute_power ( .f32 r1.target texmode_independent .. The texturing mode is selected using .v4. allowing them to be defined separately and combined at the site of usage in the program.target options ‘texmode_unified’ and ‘texmode_independent’. r2. A PTX module may declare only one texturing mode. r5.texref tex1 ) { txq.width. r1. // get tex1’s tex. } = clamp_to_border. div. and surface descriptors.global .f32 r1. Example: calculate an element’s power contribution as element’s power/total number of elements. Texturing modes For working with textures and samplers. the file is assumed to use unified mode. r1.

e.1d.Chapter 8. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. . //Example of unified mode texturing tex. A texture base address is assumed to be aligned to a 16-byte address. where the fourth element is ignored. . tex.s32 {r1. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.f32 {r1. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. . [a. the square brackets are not required and . If an address is not properly aligned. .r2.r4}.2d. b. the sampler behavior is a property of the named texture.s32.v4.f2.v4. Notes For compatibility with prior versions of PTX. d.3d }.dtype. // explicit sampler . sampler_x. .5. and is a four-element vector for 3d textures. [tex_a.r3. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. is a two-element vector for 2d textures. {f1}]. Unified mode texturing introduced in PTX ISA version 1.s32.btype = { .dtype. c].f4}].btype tex. // Example of independent mode texturing tex.3d. . Description Texture lookup using a texture coordinate vector. [a.f3.r2.0. or the instruction may fault.dtype = { .v4 coordinate vectors are allowed for any geometry. with the extra elements being ignored.s32.r3.v4.geom. If no sampler is specified. Supported on all target architectures. i. {f1.geom = { . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.. Operand c is a scalar or singleton tuple for 1d textures.btype d.v4. [tex_a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. An optional texture sampler b may be specified. 2010 123 .f32 }. c]. The instruction always returns a four-element vector of 32-bit values. . PTX ISA Notes Target ISA Notes Examples January 24.f32 }. the resulting behavior is undefined.s32.u32.geom. Instruction Set These instructions provide access to texture and surface memory.r4}. tex txq suld sust sured suq Table 88.1d.

Integer from enum { nearest.5. clamp_ogl. [tex_A]. d.squery. [tex_A].squery = { .b32 d. txq. . [smpl_B]. .tquery = { . clamp_to_edge.filter_mode. and in independent mode sampler attributes are accessed via a separate samplerref argument. sampler attributes are also accessed via a texref argument.b32 %r1.normalized_coords . In unified mode.width. // texture attributes // sampler attributes . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. linear } Integer from enum { wrap. 2010 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.samplerref variable. // unified mode // independent mode 124 January 24.depth.addr_mode_0.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).filter_mode .normalized_coords }. mirror.depth . txq.addr_mode_0.texref or . Query: . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.0 Table 89. Operand a is a . [a].filter_mode.addr_mode_1 .width . Supported on all target architectures.tquery. Description Query an attribute of a texture or sampler.addr_mode_0 .width. txq. . addr_mode_2 }. [a].height .b32 %r1.PTX ISA Version 2.height. addr_mode_1. .b32 %r1.b32 txq. . txq.

b performs an unformatted load of binary data. If an address is not properly aligned. the surface sample elements are converted to . .clamp field specifies how to handle out-of-bounds addresses: .dtype . 2010 125 .b supported on all target architectures. suld. suld. where the fourth element is ignored. suld.b. or . suld. or . Destination vector elements corresponding to components that do not appear in the surface format are not written.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.v2.geom{.trap {r1. .b8 .trap.trap clamping modifier. . .v4 }. {x.p .b64 }. b]. B.cg. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.u32. if the surface format contains SINT data.e.w}].v4. // for suld.p requires sm_20 or later. .f32.p. b].trap introduced in PTX ISA version 1. Description Load from surface memory using a surface coordinate vector. If the destination base type is .s32.b . suld.trap .f32 based on the surface format as follows: If the surface format contains UNORM. additional clamp modifiers.u32. suld.cop}.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. .cv }.b32.b32.f4}.geom . .0.f2.b32. suld.b64.p is currently unimplemented.u32 is returned. or the instruction may fault. SNORM. sm_1x targets support only the . {x}]. size and type conversion is performed as needed to convert from the surface sample format to the destination type. [a.s32.s32 is returned.1d. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp suld. Operand a is a . The lowest dimension coordinate represents a sample offset rather than a byte offset.b16. Instruction Set Table 90. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.p. . .b. If the destination type is . .zero }. // unformatted d.vec .f32 }.clamp.v2. [surf_B. Operand b is a scalar or singleton tuple for 1d surfaces. . // cache operation none. suld Syntax Texture and Surface Instructions: suld Load from surface memory. or FLOAT data.r2}.f3. then .3d }. suld.b.s32. .ca.dtype.1d. then . and the size of the data transfer matches the size of destination operand d.3d.f32 is returned. then . and A components of the surface format. [surf_A.5. if the surface format contains UINT data.y.cop}.3d requires sm_20 or later. suld. . [a. // formatted . {f1.z. . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. // for suld.clamp . . and is a four-element vector for 3d surfaces.vec.dtype .2d. The .clamp .u32.trap suld. is a two-element vector for 2d surfaces.geom{.p. Coordinate elements are of type . G. .cop . i. Target ISA Notes Examples January 24.clamp = = = = = = { { { { { { d.Chapter 8.surfref variable. .cs.v4. Cache operations require sm_20 or later.f32. the resulting behavior is undefined. . A surface base address is assumed to be aligned to a 16-byte address. and cache operations introduced in PTX ISA version 2.dtype..s32.

vec.geom{.r2}. sust.ctype .s32. is a two-element vector for 2d surfaces.cg. sm_1x targets support only the .b performs an unformatted store of binary data. sust.ctype .3d requires sm_20 or later. . .wb. b].p Description Store to surface memory using a surface coordinate vector.zero }. {r1. sust.f32 is assumed. sust Syntax Texture and Surface Instructions: sust Store to surface memory.f32.p. where the fourth element is ignored. SNORM.5. . .f32} are currently unimplemented. The .f32 }.b16. Coordinate elements are of type . Operand a is a . . .PTX ISA Version 2.cop}.b. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. [a.f4}. . or .v4 }. Operand b is a scalar or singleton tuple for 1d surfaces. {x}]. G. .b32.u32.cop . sust. and is a four-element vector for 3d surfaces. or the instruction may fault.p.b.1d. .b32.clamp.2d.vec. additional clamp modifiers.0.ctype.trap.ctype.e.s32.v2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. sust. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. // for sust.v4. Surface sample components that do not occur in the source vector will be written with an unpredictable value. if the surface format contains UINT data.trap sust. the access may proceed by silently masking off low-order address bits to achieve proper rounding.0 Table 91.u32 is assumed. none. 2010 . If the source base type is .y.p performs a formatted store of a vector of 32-bit data values to a surface sample. . then .z.p requires sm_20 or later.p. .b8 .s32. Source elements that do not occur in the surface sample are ignored.{u32. .f32. . . . The lowest dimension coordinate represents a sample offset rather than a byte offset.cs.1d.trap .3d }. If the source type is . A surface base address is assumed to be aligned to a 16-byte address. if the surface format contains SINT data.b // for sust.p. These elements are written to the corresponding surface sample components.surfref variable. If an address is not properly aligned.b32.u32. [surf_B. {x. then . {f1.s32 is assumed. c. The size of the data transfer matches the size of source operand c.vec . sust.3d. b].b64 }. The source data is then converted from this type to the surface sample format.v2.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.clamp . B.geom . // unformatted // formatted . sust. and A surface components.clamp sust.s32. then .clamp = = = = = = { { { { { { [a.trap clamping modifier. sust.b supported on all target architectures. .w}]. Target ISA Notes Examples 126 January 24. or FLOAT data.trap [surf_A.cop}. Cache operations require sm_20 or later. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. .clamp . size and type conversions are performed as needed between the surface sample format and the destination type. .wt }.clamp field specifies how to handle out-of-bounds addresses: .geom{. and cache operations introduced in PTX ISA version 2. c.. i. .trap introduced in PTX ISA version 1.b. sust.b64.f2. The source vector elements are interpreted left-to-right as R.f3. the resulting behavior is undefined.

trap . or .b performs an unformatted reduction on .u64.p.s32 types. and .trap. the access may proceed by silently masking off low-order address bits to achieve proper rounding.ctype = { .y}]. Operand a is a . sured requires sm_20 or later.op. // sample addressing .c.1d.2d. operations and and or apply to .add.b32 }.u32 and .zero }.geom = { . [surf_B.b32.u32.1d.b].Chapter 8. . Reduction to surface memory using a surface coordinate vector. .trap [surf_A. .min. . A surface base address is assumed to be aligned to a 16-byte address. .surfref variable.. {x}].u32.s32 or . . .geom. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. Instruction Set Table 92. sured.max.ctype.s32 types. .u32.s32. . sured. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b32 type.e.and. . // byte addressing sured. .clamp [a. // for sured. .trap sured. 2010 127 . sured. and the data is interpreted as . The lowest dimension coordinate represents a sample offset rather than a byte offset.clamp [a.s32.ctype.min.b32 }.u32 is assumed. . where the fourth element is ignored.s32 is assumed.2d. sured.u32 based on the surface sample format as follows: if the surface format contains UINT data.p. is a two-element vector for 2d surfaces.c.b32. and is a four-element vector for 3d surfaces.op. If an address is not properly aligned. r1.op = { .b.3d }.clamp. The instruction type is restricted to . the resulting behavior is undefined. Operations add applies to . i. if the surface format contains SINT data. {x.b]. min and max apply to . Operand b is a scalar or singleton tuple for 1d surfaces.clamp field specifies how to handle out-of-bounds addresses: .p . The .or }.clamp .add.u64 data. then .b .s32.u64. . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.b. January 24. Coordinate elements are of type .p performs a reduction on sample-addressed 32-bit data. . . or the instruction may fault. r1.0.geom.clamp = { . then . // for sured. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32.ctype = { .u32.

b32 d.height.b32 %r1. Query: .width . Supported on all target architectures.width. . Operand a is a . [a]. suq.surfref variable. .depth }.query = { . Description Query an attribute of a surface. [surf_A]. suq.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. 2010 . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.5.height .query. .PTX ISA Version 2. 128 January 24.0 Table 93.width.

Instruction Set 8.a. used primarily for defining a function body. @{!}p instruction.7. {} Syntax Description Control Flow Instructions: { } Instruction grouping. { add.Chapter 8. Supported on all target architectures. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.0.f32 @!p div. Threads with a false guard predicate do nothing.0.f32 @q bra L23.s32 d. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. Introduced in PTX ISA version 1.x.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Supported on all target architectures. ratio.c. If {!}p then instruction Introduced in PTX ISA version 1. Execute an instruction or instruction block for threads that have the guard predicate true. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. { instructionList } The curly braces create a group of instructions.0.y.s32 a. setp.b. p. 2010 129 .eq. mov. } PTX ISA Notes Target ISA Notes Examples Table 95.7.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

January 24, 2010

131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Thus.or). and the barrier is reinitialized so that it can be immediately reused.op = { . In conditionally executed code. Register operands.popc. Each CTA instance has sixteen barriers numbered 0.red.u32. and bar. 2010 133 . d.red} require sm_20 or later. bar. bar. Register operands.sync or bar..red. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. and any-thread-true (. The result of . the bar.15. Description Performs barrier synchronization and communication within a CTA. . bar. a. p. Execution in this case is unpredictable.sync 0.and). If no thread count is specified.sync and bar.Chapter 8.red} introduced in PTX .u32 bar. all-threads-true (. b}. bar.and. execute a bar. All threads in the warp are stalled until the barrier completes. b. Operand b specifies the number of threads participating in the barrier.red are population-count (. thread count. Note that a non-zero thread count is required for bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.sync with an immediate barrier number is supported for sm_1x targets.{arrive. operands p and c are predicates. b}. the final value is written to the destination register in all threads waiting at the barrier. and then safely read values stored by other threads prior to the barrier. Thus. Instruction Set Table 100. Once the barrier count is reached.red should not be intermixed with bar. thread count.red delays the executing threads (similar to bar. a{. Operands a.pred . it simply marks a thread's arrival at the barrier. The reduction operations for bar. The barrier instructions signal the arrival of the executing threads at the named barrier. all threads in the CTA participate in the barrier.{arrive. January 24.arrive using the same active barrier.popc is the number of threads with a true predicate.red also guarantee memory ordering among threads identical to membar.version 2. Only bar.red performs a reduction operation across threads.arrive does not cause any waiting by the executing threads.red performs a predicate reduction across the threads participating in the barrier.sync bar.sync or bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). bar. Since barriers are executed on a per-warp basis. bar. and bar.0.red instruction. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.or }. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.cta. bar. it is as if all the threads in the warp have executed the bar instruction. PTX ISA Notes Target ISA Notes Examples bar.arrive. b. {!}c.popc). When a barrier completes.sync without a thread count introduced in PTX ISA 1. In addition to signaling its arrival at the barrier.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. while . if any thread in a warp executes a bar instruction. and d have type .sync and bar.0.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. Barriers are executed on a per-warp basis as if all the threads in a warp are active.arrive a{. the optional thread count must be a multiple of the warp size. the waiting threads are restarted without delay. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).op. threads within a CTA that wish to communicate via memory can store to memory. a{. {!}c. bar.and and . bar. b}.sync) until the barrier count is met.

gl will typically have a longer latency than membar.sys introduced in PTX . membar. 134 January 24.cta. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys will typically have much longer latency than membar. global.PTX ISA Version 2.level.sys. this is the appropriate level of membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. when the previous value can no longer be read. membar. membar.cta.sys Waits until all prior memory requests have been performed with respect to all clients. membar. membar.gl} introduced in PTX . 2010 . membar. by st. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.version 2.{cta. membar. membar.gl} supported on all target architectures. A memory write (e.version 1. .g. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. For communication between threads in different CTAs or even different SMs.4. .{cta. . PTX ISA Notes Target ISA Notes Examples membar.gl. membar.gl.sys }. membar.0.cta. membar.sys requires sm_20 or later. and memory reads by this thread can no longer be affected by other thread writes. A memory read (e. including thoses communicating via PCI-E such as system and peer-to-peer memory. or system memory level.g. that is. level describes the scope of other clients for which membar is an ordering event.gl. red or atom) has been performed when the value written has become visible to other clients at the specified level.level = { .cta Waits until all prior memory writes are visible to other threads in the same CTA.0 Table 101.

or.op.u32. January 24. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. . b. The address must be naturally aligned to a multiple of the access size.u64. Description // // // // // . i. . . . min. and stores the result of the specified operation at location a. .u32. and exch (exchange).inc. min.u32. .b32 only .space}.s32. . . The address size may be either 32-bit or 64-bit. . . Addresses are zero-extended to the specified width as needed. Operand a specifies a location in the specified state space. .space = { . accesses to local memory are illegal. . . . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.max }.exch to store to locations accessed by other atomic operations. e.e..g. an address maps to global memory unless it falls within the local memory window or the shared memory window. For atom. The integer operations are add. performs a reduction operation with operand b and the value in location a.min. If no state space is given. c. atom. The bit-size operations are and. dec. and max operations are single-precision.b64 .type atom{. or [immAddr] an immediate absolute byte address. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . The floating-point operations are add.b32. [a]. overwriting the original value.shared }. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. In generic addressing.s32.u64 . 2010 135 . Instruction Set Table 102..s32.add.b]. min. max. perform the memory accesses using generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. b.Chapter 8. by inserting barriers between normal stores and atomic operations to a common address.and. or. inc. or the instruction may fault.dec.op. . d.f32. xor. .u32 only . . the resulting behavior is undefined.global.e. 32-bit operations. atom{.op = { . an address maps to the corresponding location in local or shared memory.b64. . . If an address is not properly aligned. i. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . . a de-referenced register areg containing a byte address.space}. The inc and dec operations return a result in the range [0. cas (compare-and-swap). to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.cas.type = { . A register containing an address may be declared as a bit-size type or integer type. and max.f32 Atomically loads the original value at location a into destination register d. The floating-point add.b32. .f32 }.xor. or by using atom.add. .exch. Within these windows.type d. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. [a].

atom.PTX ISA Version 2.add. 64-bit atom. c) operation(*a. : r-1.0 Semantics atomic { d = *a. b. s) = (r >= s) ? 0 dec(r.f32 requires sm_20 or later.0.f32 atom.{min.1.exch} requires sm_12 or later.my_new_val. 64-bit atom.[x+4].add. b). Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.f32.global. Use of generic addressing requires sm_20 or later.shared operations require sm_20 or later. : r+1.max} are unimplemented.cas.max.0. s) = (r > s) ? s exch(r.shared requires sm_12 or later.s. atom.[a]. 2010 .s32 atom.global requires sm_11 or later.global.t) = (r == s) ? t operation(*a. atom.my_val. atom. s) = s. atom. *a = (operation == cas) ? : } where inc(r. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.cas. Introduced in PTX ISA version 1.b32 d. d.{add.[p]. : r. Release Notes Examples @p 136 January 24. d. cas(r.shared.

op.f32. The address must be naturally aligned to a multiple of the access size.exch to store to locations accessed by other reduction operations. an address maps to global memory unless it falls within the local memory window or the shared memory window. Addresses are zero-extended to the specified width as needed. b. . or. Within these windows.b]. . .b64.u32. The bit-size operations are and. The integer operations are add.add.f32 }. red{. For red. .and. s) = (r >= s) ? 0 : r+1. . . overwriting the original value. e. In generic addressing. or by using atom. .u64 . . .min. inc.u64. i. b). and max operations are single-precision. .or. If no state space is given.g. .b32 only .type = { .space}. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. . and stores the result of the specified operation at location a. min.s32. 32-bit operations. . max.global. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. .. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.max }. dec.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and max. a de-referenced register areg containing a byte address. by inserting barriers between normal stores and reduction operations to a common address. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. . The address size may be either 32-bit or 64-bit. min. If an address is not properly aligned. Instruction Set Table 103. and xor. January 24. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.op = { . or the instruction may fault. Description // // // // . and truncated if the register width exceeds the state space address width for the target architecture.type [a].inc.u32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. dec(r. . .e. where inc(r. an address maps to the corresponding location in local or shared memory. Operand a specifies a location in the specified state space.u32 only . A register containing an address may be declared as a bit-size type or integer type. .s32. Semantics *a = operation(*a.e. perform the memory accesses using generic addressing.space = { . the resulting behavior is undefined. i.shared }. . The floating-point operations are add. The inc and dec operations return a result in the range [0.add. min. red.f32 Performs a reduction operation with operand b and the value in location a. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. The floating-point add. Notes Operand a must reside in either the global or shared state space.b32. 2010 137 .dec.s32.xor. or [immAddr] an immediate absolute byte address. ..Chapter 8. s) = (r > s) ? s : r-1.u32. accesses to local memory are illegal.

b32 [a].1.shared operations require sm_20 or later. red.and.0.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Use of generic addressing requires sm_20 or later.f32 red.add.f32 requires sm_20 or later.global.shared. [p].global. [x+4]. red.max} are unimplemented.s32 red. Release Notes Examples @p 138 January 24.shared requires sm_12 or later.add. red.my_val.2.add requires sm_12 or later.max.PTX ISA Version 2.f32. red. 64-bit red.{min. 2010 .global requires sm_11 or later red. 64-bit red.

. 2010 139 . Negate the source predicate to compute . In the ‘ballot’ form.uni True if source predicate has the same value in all active threads in warp.2.uni. Negate the source predicate to compute .uni. Description Performs a reduction of the source predicate across threads in a warp.ballot.pred vote.mode. vote requires sm_12 or later. // ‘ballot’ form. vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.all. vote.pred d.all. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. vote. . The destination predicate value is the same across all threads in the warp.not_all.ballot.Chapter 8.q.any True if source predicate is True for some active thread in warp.b32 d. r1.any.q. Instruction Set Table 104.mode = { . Negating the source predicate also computes . .none.p. {!}a.pred vote. p. . Note that vote applies to threads in a single warp. returns bitmask .all True if source predicate is True for all active threads in warp. vote. where the bit position corresponds to the thread’s lane id.ballot. not across an entire CTA. {!}a. The reduction modes are: . PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. // get ‘ballot’ across warp January 24.ballot.b32 requires sm_20 or later.uni }. vote.b32 p.

.u32. with optional secondary operation vop.add. atype.0 8.h0. 140 January 24. a{. 4. . b{. . 3.asel = . or word values from its source operands.9.btype{. the input values are extracted and signor zero.bsel = { . .sat} d. .u32 or .b3.s34 intermediate result. The type of each operand (. The source and destination operands are all 32-bit registers.dsel = . // 32-bit scalar operation.btype = { .bsel}. The general format of video instructions is as follows: // 32-bit scalar operation. .dtype. 2.extended internally to .atype = . Video Instructions All video instructions operate on 32-bit register operands.asel}. The primary operation is then performed to produce an .dtype.atype. and btype are valid.b1.b2.s32) is specified in the instruction type. to produce signed 33-bit input values.s33 values. vop.PTX ISA Version 2.min. . 2010 .bsel}. half-word. perform a scalar arithmetic operation to produce a signed 34-bit result.sat} d. a{.secop d.sat}.asel}. .h1 }.btype{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.secop = { .or zero-extend byte. c.atype. b{.max }. c. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. taking into account the subword destination size in the case of optional data merging.asel}.b0.s32 }.bsel}.btype{.7. b{. extract and sign. . .atype. all combinations of dtype.dsel.dtype. .dtype = . The sign of the intermediate result depends on dtype. with optional data merge vop. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. optionally clamp the result to the range of the destination type. a{. Using the atype/btype and asel/bsel specifiers.

} } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).b2: return ((tmp & 0xff) << 16) case . c).max return MAX(tmp.b0. The sign of the c operand is based on dtype. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. U32_MIN ). . . } } . c). c).h0. U32_MAX.s33 optSecOp(Modifier secop. U8_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. U16_MAX.s33 c) { switch ( secop ) { .add: return tmp + c. switch ( dsel ) { case . c).Chapter 8. 2010 141 . . S16_MIN ).min: return MIN(tmp. tmp.s34 tmp. S16_MAX.h1: return ((tmp & 0xffff) << 16) case . c). Bool sign. S32_MIN ). default: return tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case . Modifier dsel ) { if ( !sat ) return tmp. S8_MIN ).s33 c ) switch ( dsel ) { case . c). January 24. . .b1. . U16_MIN ). tmp. . Instruction Set .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. S32_MAX. c).b2. as shown in the following pseudocode.h0: return ((tmp & 0xffff) case .s33 optSaturate( . The lower 32-bits are then written to the destination operand. tmp. . .s33 tmp.s33 tmp.s33 optMerge( Modifier dsel. tmp. Bool sat. U8_MAX.b0: return ((tmp & 0xff) case . . S8_MAX. . tmp.b1: return ((tmp & 0xff) << 8) case .

b{. tb ). asel ). . . atype.h0.sat vmin. b{.s32. a{. c. vmin. vmin. . taking into account destination type and merge operations tmp = optSaturate( tmp.s32.0. bsel ).atype. r1. .h1.s32. vmax }. Integer byte/half-word/word minimum / maximum. vsub.dtype . tmp = ta – tb. // 32-bit scalar operation. r3. . vadd. .h1 }.min.dtype. vmax require sm_20 or later.s32. vmin. vmax vadd.dsel . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.dsel. a{. c.s32.atype. tb = partSelectSignExtend( b. tmp = MIN( ta.0 Table 105. // optional merge with c operand 142 January 24.max }. d = optSecondaryOp( op2.s32.btype{.or zero-extend based on source operand type ta = partSelectSignExtend( a. .s32.b2.vop . tb ).atype.s32. r2. r1. a{. Semantics // saturate. vabsdiff.h1. r1.PTX ISA Version 2.btype = { . r2.add r1. vabsdiff.s32. // optional secondary operation d = optMerge( dsel. vop. with optional secondary operation vop. c ). { . btype. vsub.sat vabsdiff. dsel ). r3. vabsdiff.bsel}.asel}. vsub vabsdiff vmin. with optional data merge vop.sat} d.bsel}. b{.sat} d. Integer byte/half-word/word absolute value of difference. r3.sat.b0. tmp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c.sat}.asel = . c.b0.dtype.sat vsub.b1. // extract byte/half-word/word and sign. // 32-bit scalar operation. r2.op2 Description = = = = { vadd. Perform scalar arithmetic operation with optional saturate. 2010 .asel}. tmp = | ta – tb |. tmp. r2.atype = .u32.asel}. isSigned(dtype).h0. c ). vsub.s32.u32.dtype. r3.add. Video Instructions: vadd.btype{. sat. and optional secondary arithmetic operation or subword data merge.u32. vadd.btype{.b3.h0.s32 }.b0.b2. vmax Syntax Integer byte/half-word/word addition / subtraction.bsel = { .bsel}. . . .op2 d. . tmp = MAX( ta.

dsel. a{. vshr Syntax Integer byte/half-word/word left / right shift.dtype. if ( mode == . vshr vshl.sat}{.u32{.sat}{.b2.op2 d. and optional secondary arithmetic operation or subword data merge. .wrap ) tb = tb & 0x1f. . January 24. unsigned shift fills with zero.min. asel ).atype. bsel ). vshl. .s32.u32. } // saturate. c ). Instruction Set Table 106.u32{.Chapter 8. if ( mode == . r3.bsel}.u32. r2. . and optional secondary arithmetic operation or subword data merge. tmp. a{. vshr: Shift a right by unsigned amount in b with optional saturate. r3. . b{. b{. c. isSigned(dtype).u32. . r2.add. { . .bsel}.u32 vshr.wrap r1.asel = .b0. Semantics // extract byte/half-word/word and sign. Video Instructions: vshl. // 32-bit scalar operation.dtype.wrap }.mode .bsel}. with optional data merge vop.h1.asel}. taking into account destination type and merge operations tmp = optSaturate( tmp. { . vshl. c. sat.b1.clamp. a{.dsel .dtype. .h1 }.asel}. // 32-bit scalar operation.u32. .op2 Description = = = = = { vshl.sat}{.atype = { . Left shift fills with zero. Signed shift fills with the sign bit.clamp . tmp. d = optSecondaryOp( op2. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b3. with optional secondary operation vop. b{.atype.0.u32. case vshr: tmp = ta >> tb.max }.clamp && tb > 32 ) tb = 32.u32{. // optional secondary operation d = optMerge( dsel.mode} d.vop . tb = partSelectSignExtend( b. vshl: Shift a left by unsigned amount in b with optional saturate. // default is .or zero-extend based on source operand type ta = partSelectSignExtend( a.dtype .mode} d. vshr }. vshr require sm_20 or later. . . atype. switch ( vop ) { case vshl: tmp = ta << tb. c ). 2010 143 .u32. dsel ).asel}.mode}.h0.atype.s32 }. vop. r1.bsel = { .

asel}. final signed (U32 * S32) + S32 // intermediate signed.S32 // intermediate signed. (a*b) is negated if and only if exactly one of a or b is negated.btype{. final signed (U32 * S32) . .dtype.atype.bsel = { .h0.0 Table 107. a{. final signed (S32 * S32) + S32 // intermediate signed.S32 // intermediate signed. and scaling. final signed (S32 * U32) . which is used in computing averages. and the operand negates. . final signed (S32 * S32) .scale} d. the intermediate result is signed. . “plus one” mode. . final signed -(U32 * S32) + S32 // intermediate signed.scale} d. final signed (S32 * U32) + S32 // intermediate signed. .shr15 }.bsel}.u32. 2010 .b1.b0. {-}b{. final signed -(S32 * U32) + S32 // intermediate signed.. Input c has the same sign as the intermediate result. // 32-bit scalar operation vmad. .s32 }. this result is sign-extended if the final result is signed.PTX ISA Version 2. 144 January 24. . The “plus one” mode (. final signed The intermediate result is optionally scaled via right-shift. otherwise.b2. Depending on the sign of the a and b operands. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.atype.dtype = . . vmad.po{. {-}c. The source operands support optional negation with some restrictions. The final result is unsigned if the intermediate result is unsigned and c is not negated.asel}.dtype.S32 // intermediate signed. . . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.asel = .po mode. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. Description Calculate (a*b) + c. That is. Although PTX syntax allows separate negation of the a and b operands. internally this is represented as negation of the product (a*b).bsel}. Source operands may not be negated in .shr7. {-}a{. final signed -(S32 * S32) + S32 // intermediate signed. final signed (U32 * U32) . with optional operand negates.po) computes (a*b) + c + 1. and zero-extended otherwise.U32 // intermediate unsigned.btype.h1 }.b3.btype = { . c.sat}{.atype = . b{.scale = { . PTX allows negation of either (a*b) or c.sat}{. final unsigned -(U32 * U32) + S32 // intermediate signed.

u32.shr15: result = (tmp >> 15) & 0xffffffffffffffff. S32_MIN). lsb = 1. S32_MAX.h0. r1. U32_MAX. else result = CLAMP(result.negate ) { tmp = ~tmp. tmp[127:0] = ta * tb. January 24. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. case . Instruction Set Semantics // extract byte/half-word/word and sign. -r3. atype.u32.po ) { lsb = 1. } else if ( c. 2010 145 . signedFinal = isSigned(atype) || isSigned(btype) || (a.sat ) { if (signedFinal) result = CLAMP(result.negate.s32. lsb = 1. r3. lsb = 0.shr15 r0. if ( . btype. vmad. r2. r2. asel ).negate ) { c = ~c. } if ( .s32.h0. bsel ). } else if ( a. r1.0.negate) || c.negate ^ b. switch( scale ) { case . r0.Chapter 8. tmp = tmp + c128 + lsb.u32. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). vmad requires sm_20 or later.u32.shr7: result = (tmp >> 7) & 0xffffffffffffffff. U32_MIN).sat vmad. tb = partSelectSignExtend( b.negate ^ b.or zero-extend based on source operand type ta = partSelectSignExtend( a.

d = optSecondaryOp( op2.0 Table 108.PTX ISA Version 2.min. c. atype. asel ). r2. 146 January 24.lt vset. a{. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.asel}.cmp.s32.gt. r3. .bsel}.h1. bsel ). .bsel}.atype. { .b3. tb.h0. with optional secondary arithmetic operation or subword data merge. c.ge }. tmp = compare( ta.asel}. r2.btype.add. . b{.bsel = { .u32. . .cmp . a{. a{. tmp. b{. .btype. btype.op2 Description = = = = .h1 }. . r3. b{. Compare input values using specified comparison. . Semantics // extract byte/half-word/word and sign.or zero-extend based on source operand type ta = partSelectSignExtend( a. // 32-bit scalar operation. tmp. // 32-bit scalar operation.u32.u32. . The intermediate result of the comparison is always unsigned. .asel}.btype.asel = .ne.atype.op2 d. 2010 . . and therefore the c operand and final result are also unsigned. // optional secondary operation d = optMerge( dsel. .atype .b1.lt. cmp ) ? 1 : 0. c ). // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.0. with optional secondary operation vset.atype. r1.max }.ne r1. c ). .cmp d.bsel}. vset.dsel .dsel. vset requires sm_20 or later.s32 }.b2.eq. . vset.btype = { . { .cmp d.b0. with optional data merge vset. tb = partSelectSignExtend( b. .le.

trap. trap. with index specified by immediate operand a.0. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Triggers one of a fixed number of performance monitor events. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Notes PTX ISA Notes Target ISA Notes Examples Currently. numbered 0 through 15.10. January 24. Introduced in PTX ISA version 1. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.Chapter 8. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. brkpt requires sm_11 or later. there are sixteen performance monitor events. Table 110.0. brkpt. trap Abort execution and generate an interrupt to the host CPU. Supported on all target architectures. 2010 147 . Table 111. Introduced in PTX ISA version 1. Supported on all target architectures. The relationship between events and counters is programmed via API calls from the host.7.4. @p pmevent 1. pmevent a. brkpt Suspends execution Introduced in PTX ISA version 1. pmevent 7. Instruction Set 8. brkpt.

0 148 January 24. 2010 .PTX ISA Version 2.

Chapter 9. 2010 149 . …. %lanemask_gt %clock. %lanemask_le. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_lt. which are visible as special registers and accessed through mov or cvt instructions. %clock64 %pm0. %lanemask_ge. %pm3 January 24. read-only variables. Special Registers PTX includes a number of predefined.

y == %ntid.y. per-thread special register initialized with the thread identifier within the CTA. mov.0.%r0. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. .y. Redefined as . The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. %tid.u32 %ntid. 2010 .u32. %ntid. The total number of threads in a CTA is (%ntid. mad. 2D. Supported on all target architectures.z.u32 %h2. the %tid value in unused dimensions is 0.%tid.x.0.x code accessing 16-bit component of %tid mov.0.z.z < %ntid.x to %rh Target ISA Notes Examples // legacy PTX 1.%tid. // CTA shape vector // CTA dimensions A predefined. . // thread id vector // thread id components A predefined. mov.u16 %rh.v4.v4 . It is guaranteed that: 0 <= %tid.sreg . mov.x code Target ISA Notes Examples 150 January 24.%h2.x.x * %ntid. . read-only special register initialized with the number of thread ids in each CTA dimension.z. Every thread in the CTA has a unique %tid.y < %ntid.PTX ISA Version 2.x 0 <= %tid.sreg .sreg . %tid component values range from 0 through %ntid–1 in each CTA dimension.y 0 <= %tid.u32 %r1.u16 %r2.z == 1 in 2D CTAs. The number of threads in each dimension are specified by the predefined special register %ntid. %ntid.x. cvt. mov. The %tid special register contains a 1D. CTA dimensions are non-zero. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. or 3D vector to match the CTA shape.0. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. // move tid. read-only. Supported on all target architectures.y * %ntid.%ntid.z == 0 in 1D CTAs.%tid.u32 %r0. // legacy PTX 1.z).z PTX ISA Notes Introduced in PTX ISA version 1.u32 type in PTX 2.u32 type in PTX 2.u32 %r0.u32 %ntid.u16 %rh. . %tid. %tid. // zero-extend tid. The fourth element is unused and always returns zero.%h1.z == 1 in 1D CTAs.x < %ntid. %tid.x.z to %r2 Table 113.u32 %tid.%tid. PTX ISA Notes Introduced in PTX ISA version 1.v4.0 Table 112.y == %tid.x. %ntid.z == 0 in 2D CTAs. Redefined as .x.%tid.y. the fourth element is unused and always returns zero.%ntid.u32 %tid. %ntid. // compute unified thread id for 2D CTA mov.u32 %h1.x.sreg .v4 .

.Chapter 9. . Introduced in PTX ISA version 1. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %laneid. PTX ISA Notes Target ISA Notes Examples Table 116. mov. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Table 115. but its value may change during execution. %warpid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Introduced in PTX ISA version 2. A predefined. The lane identifier ranges from zero to WARP_SZ-1.u32 %warpid. January 24.3.3. 2010 151 .sreg . read-only special register that returns the maximum number of warp identifiers. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. %nwarpid requires sm_20 or later. read-only special register that returns the thread’s lane within the warp. mov. A predefined.g.u32 %r.sreg . . due to rescheduling of threads following preemption. Supported on all target architectures. %nwarpid. Supported on all target architectures.0. read-only special register that returns the thread’s warp identifier. mov. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.u32 %r. Special Registers Table 114.u32 %nwarpid. Note that %warpid is volatile and returns the location of a thread at the moment when read. A predefined.sreg . %laneid. e. The warp identifier will be the same for all threads within a single warp. Introduced in PTX ISA version 1. For this reason. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %r.

{x.u32 %ctaid.u32 mov.0.v4.x.sreg . It is guaranteed that: 1 <= %nctaid. Supported on all target architectures. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. Redefined as .%nctaid. mov.y.u32 %nctaid.u16 %r0.y. The fourth element is unused and always returns zero.%ctaid. The fourth element is unused and always returns zero. It is guaranteed that: 0 <= %ctaid. Each vector element value is >= 0 and < 65535.y.536 PTX ISA Notes Introduced in PTX ISA version 1. %rh. .z.x.x code Target ISA Notes Examples 152 January 24. // legacy PTX 1.z.u32 %nctaid .x < %nctaid.u32 mov.sreg . %rh. The %ctaid special register contains a 1D. or 3D vector.x.z PTX ISA Notes Introduced in PTX ISA version 1.x code Target ISA Notes Examples Table 118.u16 %r0. // legacy PTX 1. .y 0 <= %ctaid.0 Table 117.v4. // CTA id vector // CTA id components A predefined. Redefined as . %ctaid.%ctaid. .z < %nctaid.0.PTX ISA Version 2.x 0 <= %ctaid.sreg . Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.%nctaid. 2D. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.v4 . // Grid shape vector // Grid dimensions A predefined. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.%nctaid. The %nctaid special register contains a 3D grid shape vector.0.z} < 65. with each element having a value of at least 1. depending on the shape and rank of the CTA grid. 2010 . read-only special register initialized with the CTA identifier within the CTA grid.x.u32 %ctaid. mov.v4 . %ctaid.0.sreg .u32 type in PTX 2.y < %nctaid.u32 type in PTX 2.x.y. Supported on all target architectures. read-only special register initialized with the number of CTAs in each grid dimension.%nctaid.

u32 %r. mov. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov.sreg .u32 %r. Introduced in PTX ISA version 2. e. PTX ISA Notes Target ISA Notes Examples January 24. . The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.Chapter 9. read-only special register that returns the maximum number of SM identifiers. Note that %smid is volatile and returns the location of a thread at the moment when read. so %nsmid may be larger than the physical number of SMs in the device. .sreg . Supported on all target architectures. repeated launches of programs may occur. The SM identifier ranges from 0 to %nsmid-1. // initialized at grid launch A predefined. due to rescheduling of threads following preemption. PTX ISA Notes Target ISA Notes Examples Table 121. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. where each launch starts a grid-of-CTAs. Special Registers Table 119. mov.g. Supported on all target architectures.sreg .u32 %smid.u32 %nsmid. A predefined. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.u32 %gridid. During execution. read-only special register initialized with the per-grid temporal grid identifier. This variable provides the temporal grid launch number for this context. . A predefined.0. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. but its value may change during execution. Notes PTX ISA Notes Target ISA Notes Examples Table 120.3. The SM identifier numbering is not guaranteed to be contiguous. %gridid. %nsmid requires sm_20 or later. %smid. 2010 153 . Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.u32 %r.0. %nsmid. The SM identifier numbering is not guaranteed to be contiguous. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.

read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. A predefined.PTX ISA Version 2. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. %lanemask_lt.u32 %r. . A predefined.u32 %r. mov. %lanemask_le requires sm_20 or later.u32 %lanemask_le. %lanemask_lt requires sm_20 or later.sreg . %lanemask_eq. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.0 Table 122.0.0. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . 154 January 24.sreg .0. Table 124. %lanemask_eq requires sm_20 or later. %lanemask_le. Table 123. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. mov.sreg . A predefined. . Introduced in PTX ISA version 2.u32 %lanemask_eq. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.u32 %lanemask_lt. mov.u32 %r. 2010 .

January 24. %lanemask_ge requires sm_20 or later.u32 %r. %lanemask_gt requires sm_20 or later.0.u32 %lanemask_gt.Chapter 9.0. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_gt. %lanemask_ge. A predefined. . A predefined. Introduced in PTX ISA version 2. 2010 155 .sreg . Special Registers Table 125. Introduced in PTX ISA version 2. mov. Table 126.sreg .u32 %lanemask_ge. .u32 %r. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.

Their behavior is currently undefined. …. Table 128.PTX ISA Version 2. %pm1. . mov.u64 r1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Special Registers: %pm0.u32 %clock. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.0 Table 127. %pm1. %pm3. %pm1. Table 129. Introduced in PTX ISA version 1. %pm2. %pm2. . %clock64 requires sm_20 or later.%pm0.0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. The lower 32-bits of %clock64 are identical to %clock.u32 r1.u32 r1.sreg . read-only 32-bit unsigned cycle counter. Introduced in PTX ISA version 2.u32 %pm0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. read-only 64-bit unsigned cycle counter. and %pm3 are unsigned 32-bit read-only performance monitor counters.%clock. mov. . 2010 .3. %pm3 %pm0. Introduced in PTX ISA version 1.0.u64 %clock64.%clock64. Special registers %pm0. 156 January 24. Supported on all target architectures. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Supported on all target architectures. mov. %pm2.sreg .sreg .

version 2.1.version Syntax Description Semantics PTX version number.version 1.version .version major. and the target architecture for which the code was generated. . PTX File Directives: . .4 January 24. .target Table 130. minor are integers Specifies the PTX language version number. Increments to the major number indicate incompatible changes to PTX.version directive. Duplicate .version . Directives 10. Each ptx file must begin with a .version directives are allowed provided they match the original .0 . 2010 157 . Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version directive.0. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.Chapter 10. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.minor // major.

Requires map_f64_to_f32 if any . 64-bit {atom.f64 instructions used. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. 2010 .5. 158 January 24. Introduced in PTX ISA version 1. Description Specifies the set of features in the target architecture for which the current ptx code was generated. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.target directive containing a target architecture and optional platform options.samplerref descriptors. PTX features are checked against the specified target architecture. but subsequent . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. texmode_unified.global. generations of SM architectures follow an “onion layer” model.texmode_unified . A . Texturing mode: (default is . Each PTX file must begin with a .0. brkpt instructions. Target sm_20 Description Baseline feature set for sm_20 architecture. A program with multiple . Adds {atom. Therefore.PTX ISA Version 2.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 instructions used.target directive specifies a single target architecture. PTX File Directives: . sm_13. The following table summarizes the features in PTX that vary according to target architecture. with only half being used by instructions converted from . Adds {atom.red}. sm_11. Requires map_f64_to_f32 if any . vote instructions. Supported on all target architectures. immediately followed by a .0 Table 131. Disallows use of map_f64_to_f32.texmode_unified) . texmode_independent. sm_12.target Syntax Architecture and Platform target. Requires map_f64_to_f32 if any . including expanded rounding modifiers. texture and sampler information is referenced with independent . The texturing mode is specified for an entire module and cannot be changed within the module. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.texref descriptor.red}.target . . map_f64_to_f32 }.f32.texref and . and an error is generated if an unsupported feature is used.f64 storage remains as 64-bits. where each generation adds new features and retains all features of previous generations. In general. PTX code generated for a given target can be run on later generation devices.f64 to . Note that . sm_10.texmode_independent texture and sampler information is bound together and accessed via a single .f64 instructions used.target directives can be used to change the set of target features allowed during parsing.shared. Texturing mode introduced in PTX ISA version 1.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.red}.version directive. Adds double-precision support.global.

texmode_independent January 24.target sm_20. Directives Examples .target sm_10 // baseline target architecture . 2010 159 .Chapter 10.target sm_13 // supports double-precision .

b32 z ) Target ISA Notes Examples [x].func Table 132. . Parameters may be referenced by name within the kernel body and loaded into registers using ld. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. parameters.param { . The shape and size of the CTA executing the kernel are available in special registers.surfref variables may be passed as parameters. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. . store. with optional parameters. At kernel launch. and query instructions and cannot be accessed via ld. and body for the kernel function.param instructions. In addition to normal parameters.g. … } .param. etc.entry filter ( . ld.3. e.param . . Parameters are passed via .entry cta_fft . . Semantics Specify the entry point for a kernel program. .samplerref.b32 %r<99>.0 through 1. Kernel and Function Directives: .entry . [y]. 2010 .param space memory and are listed within an optional parenthesized parameter list.b32 %r1.entry kernel-name kernel-body Defines a kernel entry point name.2. %nctaid.reg . the kernel dimensions and properties are established and made available via special registers. parameter variables are declared in the kernel parameter list. ld.entry Syntax Description Kernel entry point and body. opaque . 160 January 24.0 through 1.param.entry kernel-name ( param-list ) kernel-body .4. .4 and later. ld.PTX ISA Version 2.b32 %r3.entry . parameter variables are declared in the kernel body. PTX ISA Notes For PTX ISA version 1.0 10.texref.b32 %r2.param instructions.param. %ntid.b32 x. Supported on all target architectures. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. [z]. For PTX ISA versions 1. These parameters can only be referenced by name within texture and surface load.b32 y.5 and later. and .param .

The implementation of parameter passing is left to the optimizing translator. Variadic functions are currently unimplemented.param and st. and supports recursion. foo.func Syntax Function definition. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. if any.param instructions in the body. Parameters in register state space may be referenced directly within instructions in the function body. Directives Table 133. Parameter passing is call-by-value. implements an ABI with stack.func definition with no body provides a function prototype.func fname function-body . . .reg .b32 localVar. Supported on all target architectures.reg . PTX 2. } … call (fooval).0 with target sm_20 allows parameters in the .param state space. Kernel and Function Directives: . dbl.reg .0 with target sm_20 supports at most one return value.param space are accessed using ld. which may use a combination of registers and stack locations to pass parameters.2 for a description of variadic functions.func (ret-param) fname (param-list) function-body Defines a function. … Description // return value in fooval January 24. .f64 dbl) { . Parameters in . … use N.b32 rval) foo (.reg .b32 N. A .0. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. PTX ISA 2.x code. Release Notes For PTX ISA version 1.result.func (. there is no stack. 2010 161 .Chapter 10. mov. including input and return parameters and optional function body. other code. The parameter lists define locally-scoped variables in the function body. parameters must be in the register state space. val1). Parameters must be base types in either the register or parameter state space.b32 rval. Variadic functions are represented using ellipsis following the last fixed argument. (val0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.func fname (param-list) function-body . ret. and recursion is illegal.func .

minnctapersm . for example. and the . The directives take precedence over any module-level constraints passed to the optimizing backend.0 10. The . and .minnctapersm directives may be applied per-entry and must appear between an . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. The directive passes a list of strings to the backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. or as statements within a kernel or device function body. The interpretation of . 162 January 24. 2010 .pragma The . the . Currently.g.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. These can be used.maxntid and . the . .pragma directives may appear at module (file) scope.maxntid . Note that .3.entry directive and its body.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. . PTX supports the following directives.PTX ISA Version 2. which pass information to the backend optimizing compiler.maxnreg . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. at entry-scope.pragma directive is supported for passing information to the PTX backend. A general .maxntid directive specifies the maximum number of threads in a thread block (CTA).minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). to throttle the resource requirements (e.maxnreg. and the strings have no semantics within the PTX virtual machine model. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxntid.maxnctapersm (deprecated) . registers) to increase total thread count and provide a greater opportunity to hide memory latency.

This maximum is specified by giving the maximum extent of each dimention of the 1D. .maxntid . 2010 163 . Performance-Tuning Directives: .maxnreg .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. 2D. for example. Exceeding any of these limits results in a runtime error or kernel launch failure. the backend may be able to compile to fewer registers.maxntid nx. nz Declare the maximum number of threads in the thread block (CTA).3. .maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid nx.maxntid 256 . Supported on all target architectures. The actual number of registers used may be less. Introduced in PTX ISA version 1. . Supported on all target architectures. or the maximum number of registers may be further constrained by .entry foo . Directives Table 134.maxntid nx .maxntid 16.maxntid Syntax Maximum number of threads in thread block (CTA). The maximum number of threads is the product of the maximum extent in each dimension.maxntid and . ny . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.entry bar .Chapter 10. The compiler guarantees that this limit will not be exceeded. Introduced in PTX ISA version 1. ny.3. Performance-Tuning Directives: .maxctapersm. or 3D CTA.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.16.entry foo . .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.

0.minnctapersm .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Introduced in PTX ISA version 1.minnctapersm in PTX ISA version 2.maxntid and . .minnctapersm generally need . additional CTAs may be mapped to a single multiprocessor. Optimizations based on .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm (deprecated) .entry foo . Introduced in PTX ISA version 2. if the number of registers used by the backend is sufficiently lower than this bound.maxntid to be specified as well. Optimizations based on . 2010 . Performance-Tuning Directives: .maxntid 256 . The optimizing backend compiler uses .0 Table 136.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Deprecated in PTX ISA version 2.3.maxnctapersm generally need . .maxntid 256 .0. .minnctapersm 4 { … } 164 January 24. Performance-Tuning Directives: .maxnctapersm has been renamed to .entry foo . . For this reason. Supported on all target architectures.maxntid to be specified as well.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Supported on all target architectures. However.0 as a replacement for .PTX ISA Version 2.maxnctapersm. .

2010 165 . or statement-level directives to the PTX backend compiler. Performance-Tuning Directives: .pragma Syntax Description Pass directives to PTX backend compiler.pragma list-of-strings . Supported on all target architectures.entry foo . entry-scoped. Introduced in PTX ISA version 2.0. The .pragma directive may occur at module-scope. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .Chapter 10. { … } January 24.pragma “nounroll”. at entry-scope. . The interpretation of . . Pass module-scoped.pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma .pragma directive strings is implementation-specific and has no impact on PTX semantics. Directives Table 138. or at statementlevel.

4byte . 0x00. The @@DWARF syntax is deprecated as of PTX version 2.byte 0x00. Deprecated as of PTX 2.4byte int32-list // comma-separated hexadecimal integers in range [0.byte 0x2b. “”.4byte label .x code.. Table 139. 0x00 166 January 24. 0x61395a5f. Introduced in PTX ISA version 1. Supported on all target architectures.4byte 0x6e69616d. 0x00.4byte 0x000006b5. 0x00. 0x6150736f. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .byte byte-list // comma-separated hexadecimal byte values .loc The . 0x736d6172 . @@DWARF dwarf-string dwarf-string may have one of the .0 but is supported for legacy PTX version 1.2.debug_info . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. @progbits .section .section .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x02. 0x00. replaced by . 0x00000364.0.section directive is new in PTX ISA verison 2.264-1] . 2010 .section directive. 0x5f736f63 .4.0 10. 0x63613031. 0x00..PTX ISA Version 2. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .232-1] .0 and replaces the @@DWARF syntax.file . 0x00 . 0x00.quad int64-list // comma-separated hexadecimal integers in range [0.debug_pubnames.

section .b32 label . .0. Debugging Directives: .b8 0x2b. 0x00. 0x00.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x00000364.section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00.b64 int64-list // comma-separated list of integers in range [0. . 0x63613031. .file .255] . .. Debugging Directives: .0..b8 byte-list // comma-separated list of integers in range [0.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x736d6172 0x00 Table 141.232-1] . Debugging Directives: .Chapter 10.section Syntax PTX section definition..file filename Table 142. 0x00.b32 int32-list // comma-separated list of integers in range [0.264-1] . replaces @@DWARF syntax.b8 0x00. Source file location. Supported on all target architectures.0. 0x00.debug_pubnames { . . } 0x02.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Source file information.b32 . 0x00 0x61395a5f.debug_info .loc .loc line_number January 24. .section . Supported on all target architectures. Directives Table 140. Supported on all target architectures. . 0x5f736f63 0x6150736f. 0x00. 2010 167 .b32 0x6e69616d.b32 0x000006b5.

Introduced in PTX ISA version 1.b32 foo.visible identifier Declares identifier to be externally visible.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. . Linking Directives .visible Table 143. Supported on all target architectures. .extern .extern identifier Declares identifier to be defined externally.0.extern . Introduced in PTX ISA version 1. Linking Directives: . Supported on all target architectures.b32 foo.extern .0 10.PTX ISA Version 2. Linking Directives: . . .0.visible .6. // foo is defined in another module Table 144.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.global .global . // foo will be externally visible 168 January 24. 2010 .visible .

Chapter 11. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 2.4 PTX ISA 1.0.3 driver r190 CUDA 3.5 PTX ISA 2.2 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 January 24.1 PTX ISA 1. The release history is as follows.3 PTX ISA 1.0 CUDA 1.1 CUDA 2. 2010 169 .0 driver r195 PTX ISA Version PTX ISA 1. CUDA Release CUDA 1.2 CUDA 2.0 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.1 CUDA 2.

The goal is to achieve IEEE 754 compliance wherever possible. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 instruction also supports .1. Floating-Point Extensions This section describes the floating-point changes in PTX 2. Single. Both fma.f32 maps to fma. These are indicated by the use of a rounding modifier and require sm_20.0 11.PTX ISA Version 2. Single-precision add.rn.f32 and mad.ftz and .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.and double-precision div. New Features 11.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.rp rounding modifiers for sm_20 targets. fma. and mul now support .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.ftz modifier may be used to enforce backward compatibility with sm_1x. 2010 . The mad. Instructions testp and copysign have been added. The . When code compiled for sm_1x is executed on sm_20 devices.1.x code and sm_1x targets. and sqrt with IEEE 754 compliant rounding have been added.1.1.1.0 11.f32.f32 require a rounding modifier for sm_20 targets.sat modifiers.rm and . mad.1. • • • • • 170 January 24. while maximizing backward compatibility with legacy PTX 1.f32 for sm_20 targets. The mad.0 for sm_20 targets. The fma. rcp. sub. A single-precision fused multiply-add (fma) instruction has been added. The changes from PTX ISA 1. Changes in Version 2.f32 requires sm_20.

The .red}.gt} have been added.or}. A “vote ballot” instruction. has been added.red. st. Bit field extract and insert instructions. cvta. prefetch.lt.section.minnctapersm to better match its behavior and usage.g.add. atom. ldu. The bar instruction has been extended as follows: • • • A bar.le.clamp and . has been added. Other new features Instructions ld. isspacep. clz. A “find leading non-sign bit” instruction. . A “count leading zeros” instruction. vote. has been added.ballot.u32 and bar.arrive instruction has been added. Release Notes 11. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. %lanemask_{eq.1.f32 have been implemented. and shared addresses to generic address and vice-versa has been added. membar. 2010 171 . Surface instructions support additional .popc. have been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. for prefetching to specified level of memory hierarchy. Instruction sust now supports formatted surface stores. Instructions bar. New instructions A “load uniform” instruction.sys.clamp modifiers. prefetchu. New special registers %nsmid. Instruction cvta for converting global. Cache operations have been added to instructions ld.1. Video instructions (includes prmt) have been added.1. . popc. local.zero. A new directive.red. bfe and bfi.maxnctapersm directive was deprecated and replaced with . January 24. and red now support generic addressing.2. Instructions {atom.1. has been added. suld. brev. bar now supports optional thread count and register operands.Chapter 11. %clock64. A “population count” instruction. Instructions prefetch and prefetchu have also been added. A system-level membar instruction. A “bit reversal” instruction. Instructions {atom. and sust.ge. has been added.pred have been added.red}.{and. bfind. has been added. has been added.shared have been extended to handle 64-bit data types for sm_20 targets. st. e. ldu.b32.3. 11.

u32.2. or .{u32. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.s32. Formatted surface store with .p sust. To maintain compatibility with legacy PTX code.{min.PTX ISA Version 2. Instruction bra.f32. stack-based ABI is unimplemented. has been fixed. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.1.3. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.ftz (and cvt for . 11. {atom. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. the correct number is sixteen.5 and later.version is 1. 172 January 24. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. Support for variadic functions and alloca are unimplemented.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. In PTX version 1.f32} atom.4 or earlier.4 and earlier.ftz for PTX ISA versions 1.p.red}. See individual instruction descriptions for details.1. .f32 type is unimplemented. Formatted surface load is unimplemented.target sm_1x. if . Semantic Changes and Clarifications The errata in cvt. 2010 . call suld.0 11. The underlying.s32.5. where . cvt.max} are not implemented.

the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma “nounroll”. L1_body: … L1_continue: bra L1_head.0. disables unrolling for all loops in the entry function body. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. disables unrolling of0 the loop for which the current block is the loop header. Descriptions of . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.pragma. Note that in order to have the desired effect at statement level.pragma “nounroll”. entry-function. 2010 173 .pragma strings defined by ptxas. .Appendix A. including loops preceding the . Supported only for sm_20 targets. Table 145. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma “nounroll”. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and statement levels. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.entry foo (…) . . L1_end: … } // do not unroll this loop January 24. { … } // do not unroll any loop in this function .pragma Strings This section describes the . The “nounroll” pragma is allowed at module. Ignored for sm_1x targets. … @p bra L1_end.func bar (…) { … L1_head: .

0 174 January 24. 2010 .PTX ISA Version 2.

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