NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

............. 25 Chapter 5.......................................................................... 42 Addresses as Operands .................4. 5.......................4............................................................................................... 6.. State Spaces ................1....................................................................................4...1.........................................................4......................................................................................................................................................................... 6.............................. 29 Parameter State Space .......... 5................................. Arrays...1.......................................................................1......................................4.............................................6...............1... 43 Vectors as Operands .................................. 39 Parameterized Variable Names ............1........................................................................ 44 Scalar Conversions ..........2... 43 6............................PTX ISA Version 2.............0 4.......... 6..2........................................................... 33 Restricted Use of Sub-Word Sizes ..............................1........................................1.......4...................................................................... Summary of Constant Expression Evaluation Rules ....................6............................................. 37 Vectors ..6........................................... Types ..... 30 Shared State Space...............................................................................5.........................7.................... 32 5... 6........ 33 Fundamental Types ........................................................2........................6....................................1.3....................................................... Operand Costs ...... 5.............................................................................. 39 5........................... 5.............4............... 5.............. 32 Texture State Space (deprecated) ...................4... Function declarations and definitions ...........1................................................................4..2.......3.. Instruction Operands................2.................................................3.............................................. 38 Initializers ........... 41 6................................................. and Surface Types .......................................... 5................4.......................................... 37 Array Declarations .............. 43 Labels and Function Names as Operands .... 5......................... Texture......... 5.............5........ and Vectors ........................................3..............1.....3...5................................. Types.....................4........... Sampler...........4................................................. 2010 .............. 34 Variables .. 49 7....................2...1.................... 5.................. and Variables ......... 5....4............................................................... 5.... 29 Local State Space ........................................................................ 6... 29 Global State Space .................... 27 5....... 28 Constant State Space ................... Abstracting the ABI ....................................................2......................1.............................. 6. 5...............5.... Type Conversion... 27 Register State Space ........ 5.................................................1.................... 6...... 49 ii January 24...............2.......................... 37 Variable Declarations . 46 6........... 5... 41 Source Operands...........4......... 47 Chapter 7.................... 33 5................................1........................................ 5................ State Spaces.... 6...................5...... 44 Rounding Modifiers .............................1......4... 41 Destination Operands ....................................................................................................................... Chapter 6....... 28 Special Register State Space .2................................... 6....8.................................. 41 Using Addresses.......5... 5................................ Operand Type Information ............................................................... 38 Alignment .................. 42 Arrays as Operands ..........................

....5......2........... 170 Semantic Changes and Clarifications ........................... 55 Predicated Execution ... 62 Semantics .......3..................................... 11...6........................................... PTX Version and Target Directives ................ 62 Machine-Specific Semantics of 16-bit Code ...................... 58 8......................................................7................... 54 Chapter 8....................................1..............7............ 100 Logic and Shift Instructions ................................................. 157 10....................................................................... 8...3...................................2.............. Changes from PTX 1.......5............................... 81 Comparison and Selection Instructions ....................................................... Special Registers ............7........ 7................................... 53 Alloca .................. 8.................................................................................6...1..... 56 Comparisons ................1..................... 170 New Features ................................. 8................................................................................ 10............. 8.................................... 132 Video Instructions ............................................... Changes in Version 2................................................................................2........................................7..... 10........ Instruction Set .............................................................3.............................. 60 8......... 149 Chapter 10.............4.......................................................1....................................1............. 122 Control Flow Instructions ............. 147 8........... 8....................................................7......... 172 January 24.............3...........................7....................7......7.......... Instructions ...........1.......... 7.................8..................10..................................................6........ 8....................................................2..................................... 162 Debugging Directives ............................. 10..........1.......... 52 Variadic functions .3.........1..... 2010 iii .................................................. Chapter 9................................................................................................ 8............2......................... 8........ 8..................3......................1...............................4..... 8.......................... 55 8........................ 10.......... 160 Performance-Tuning Directives ......7.....3........................................... Type Information for Instructions and Operands ........... 140 Miscellaneous Instructions....................................1................... 63 Integer Arithmetic Instructions ................. Divergence of Threads in Control Constructs ............0 ......... 168 Chapter 11...............1...... 62 8....................................... 8.............................................................................7.. 55 PTX Instructions ....................................... 8................................. 59 Operand Size Exceeding Instruction-Type Size .......................... 157 Specifying Kernel Entry Points and Functions .........6..............................7.......................... 8.................. 166 Linking Directives .......... 11.......x .............. 63 Floating-Point Instructions ......................................................................... Directives ..............................7...... 8................................. 57 Manipulating Predicates .................................................. 104 Data Movement and Conversion Instructions ...............................7.................................................. 108 Texture and Surface Instructions .2........................................................... 172 Unimplemented Features Remaining .............................1..... 11.............................4....................4................................. Format and Semantics of Instruction Descriptions ...... 129 Parallel Synchronization and Communication Instructions ..............................9............... 8..................... 8........... Release Notes ........................1.. 169 11......

.pragma Strings............0 Appendix A........... Descriptions of .......PTX ISA Version 2. 173 iv January 24................... 2010 .................

.......... Table 31......................................................... Table 3.......................................... 23 Constant Expression Evaluation Rules ........ Table 30.......................................... 58 Floating-Point Comparison Operators Testing for NaN ............... Table 28...................... 33 Opaque Type Fields in Unified Texture Mode ................................... 47 Operators for Signed Integer........................................ Table 21.......... 65 Integer Arithmetic Instructions: sub....................................................... Table 24......................... Table 12........................ Table 11................................ Table 23...................................... Table 18.................. 46 Cost Estimates for Accessing State-Spaces ..... Table 22............ 28 Fundamental Type Specifiers ......................................................................... 69 Integer Arithmetic Instructions: mad24 .............. 70 Integer Arithmetic Instructions: sad ............................................... Table 29..................................................... Table 20.. 64 Integer Arithmetic Instructions: sub .............................................. 57 Floating-Point Comparison Operators .............................................................................. Table 19.................... Table 17..... and Bit-Size Types ....................................................................... 45 Floating-Point Rounding Modifiers ..List of Tables Table 1....................................................................................... Table 16....... 66 Integer Arithmetic Instructions: subc .................................................. 19 Predefined Identifiers ........................ Table 5....................................... Table 26.... 18 Reserved Instruction Keywords ............................................... 25 State Spaces ............ 61 Integer Arithmetic Instructions: add ..................... 46 Integer Rounding Modifiers ........ Table 9...................................................................................................................... 35 Opaque Type Fields in Independent Texture Mode .......................................................... 65 Integer Arithmetic Instructions: addc ........................ Table 10............... 64 Integer Arithmetic Instructions: add.......................................... Table 14....................................................... 20 Operator Precedence ........ Table 25................. 66 Integer Arithmetic Instructions: mul ............................................................... PTX Directives ........ Table 13............................................ Table 4. Unsigned Integer.............................................................. Table 2.... Table 27........cc .............. 2010 v ............................................................... 60 Relaxed Type-checking Rules for Destination Operands.................................... Table 32....................................... 68 Integer Arithmetic Instructions: mul24 .................................................................. Table 6....... 58 Type Checking Rules .. 35 Convert Instruction Precision and Format .... 59 Relaxed Type-checking Rules for Source Operands .................................................................................................................................................................cc .................................... Table 7...................... Table 8...................... Table 15............................................... 27 Properties of State Spaces ........... 57 Floating-Point Comparison Operators Accepting NaN ............................................ 71 January 24........................ 67 Integer Arithmetic Instructions: mad .....

......................... Table 63.............................................................. 74 Integer Arithmetic Instructions: clz ....... 86 Floating-Point Instructions: fma ..................................................... 101 Comparison and Selection Instructions: setp ..................................... 77 Integer Arithmetic Instructions: bfi ............................... 94 Floating-Point Instructions: rsqrt ........................................................... 72 Integer Arithmetic Instructions: min ......... Table 42.............. Table 52.. Table 62..................................................... Table 46.............................................................................. Table 69......................................................................... 83 Floating-Point Instructions: copysign ..................................... 73 Integer Arithmetic Instructions: max ..................................... Table 47...... 103 vi January 24............................................... 103 Comparison and Selection Instructions: slct ......................................... Table 61................................... Table 40...................... Table 56.. 87 Floating-Point Instructions: mad ........................................ Table 58...................................................... 99 Comparison and Selection Instructions: set ........................................... Table 35............... Integer Arithmetic Instructions: div ................................................................................................... Table 50... 2010 .............. Table 57.................................................... 91 Floating-Point Instructions: neg ................................................................... 76 Integer Arithmetic Instructions: bfe ...... Table 53............................................................................................................................................... Table 48..................... 73 Integer Arithmetic Instructions: popc ............................................... 71 Integer Arithmetic Instructions: abs ..................................................................0 Table 33.............................................. Table 36............. 75 Integer Arithmetic Instructions: brev .. Table 43. Table 65..................... 92 Floating-Point Instructions: rcp .................................................................................. 74 Integer Arithmetic Instructions: bfind .... 102 Comparison and Selection Instructions: selp .... Table 37........................... 85 Floating-Point Instructions: mul ..................... 98 Floating-Point Instructions: ex2 .... 84 Floating-Point Instructions: sub ............................................................................................................................................ 92 Floating-Point Instructions: max ....................................... Table 34...................................... Table 59.. 93 Floating-Point Instructions: sqrt ....................................................... Table 41................ 95 Floating-Point Instructions: sin ......................................... 71 Integer Arithmetic Instructions: rem ..... 72 Integer Arithmetic Instructions: neg .................................................................................................. 88 Floating-Point Instructions: div ................... Table 60..................................................... Table 66.. Table 44..................................... Table 49......................................... Table 64....... 78 Integer Arithmetic Instructions: prmt ....... Table 54......... 82 Floating-Point Instructions: testp ....... Table 39....................................................................................... 97 Floating-Point Instructions: lg2 ........PTX ISA Version 2........... Table 55............................... 90 Floating-Point Instructions: abs ................ Table 45............... 91 Floating-Point Instructions: min ...... Table 67............. Table 51.... 83 Floating-Point Instructions: add ..... 96 Floating-Point Instructions: cos ......................................................................................................................................................... 79 Summary of Floating-Point Instructions ................................................ Table 38...................................................................................................................................................... Table 68........................

.... 137 Parallel Synchronization and Communication Instructions: vote ........... Table 80.................................... 125 Texture and Surface Instructions: sust .................. 109 Cache Operators for Memory Store Instructions .................................................... Table 105................. 116 Data Movement and Conversion Instructions: prefetch............. 130 Control Flow Instructions: call ............................... 127 Texture and Surface Instructions: suq ......................... Table 102... Table 72.................................................................................. Table 98............................ Table 91........................ 113 Data Movement and Conversion Instructions: ldu .................................................................................................. Table 77................ Table 78. prefetchu ............................... Table 89.................. Table 99....................... 2010 vii ...................................................................... Table 94................ 106 Logic and Shift Instructions: shl ....... 107 Logic and Shift Instructions: shr ................................. 135 Parallel Synchronization and Communication Instructions: red . 129 Control Flow Instructions: bra ......... 115 Data Movement and Conversion Instructions: st ... Table 92. 118 Data Movement and Conversion Instructions: isspacep ........ Table 71................................ Logic and Shift Instructions: and .... Table 88..... Table 84............................... Table 81................................................. 143 January 24........................ Table 101.........................................................................................Table 70.................................. 123 Texture and Surface Instructions: txq .................. 124 Texture and Surface Instructions: suld ................... Table 86......................................................................... 131 Control Flow Instructions: exit ................. 112 Data Movement and Conversion Instructions: ld ................................................................................... Table 93................................ 111 Data Movement and Conversion Instructions: mov ............. 139 Video Instructions: vadd... Table 106............................ 126 Texture and Surface Instructions: sured.. 130 Control Flow Instructions: ret ................ 128 Control Flow Instructions: { } ................... vshr ................................................ 119 Data Movement and Conversion Instructions: cvta ..... Table 85........................ vabsdiff. 134 Parallel Synchronization and Communication Instructions: atom ................................................ Table 76... 106 Logic and Shift Instructions: not ..................................................... 106 Logic and Shift Instructions: cnot .................... vsub........................................................................ Table 74.......... Table 90........... Table 79......................... Table 96.......... 105 Logic and Shift Instructions: xor .......................................................... Table 100.................................................................. 131 Parallel Synchronization and Communication Instructions: bar ....................................................... 133 Parallel Synchronization and Communication Instructions: membar ......... Table 104....... vmin.............................................................................. vmax ..................................... 107 Cache Operators for Memory Load Instructions ........................ Table 87.................. 105 Logic and Shift Instructions: or ..... Table 83.............. Table 103.................... 129 Control Flow Instructions: @ ........................ Table 97... 119 Data Movement and Conversion Instructions: cvt ............. 142 Video Instructions: vshl......... 120 Texture and Surface Instructions: tex ....................................................................................................................... Table 95....... Table 73.. Table 82.............................. Table 75........ 110 Data Movement and Conversion Instructions: mov .......................

160 Kernel and Function Directives: . Table 128................... Table 116....... 167 Debugging Directives: ...................... Table 138.........................minnctapersm ..... Table 127............. 163 Performance-Tuning Directives: ......................... 150 Special Registers: %ntid .......................... 164 Performance-Tuning Directives: ..............................target ................................... Table 108........................................................ 150 Special Registers: %laneid .....................................func ................................. Video Instructions: vmad ... 155 Special Registers: %clock ........................ %pm1.................. 153 Special Registers: %nsmid .................................................................... Table 121......... Table 139......... Table 124... 154 Special Registers: %lanemask_ge ............. 153 Special Registers: %lanemask_eq .............................. Table 118...............pragma .......................maxnctapersm (deprecated) ...... Table 143.................................. Table 115................................................................................................. Table 123... 165 Debugging Directives: @@DWARF ......................................... 151 Special Registers: %warpid ..................... 153 Special Registers: %gridid ........................................ Table 125.extern............................................................ 2010 ............ 168 viii January 24....file .................. Table 111................................. 158 Kernel and Function Directives: ....... 151 Special Registers: %nwarpid ....................................................................................................................................................................................... Table 126............... Table 142............. Table 134........................................PTX ISA Version 2.... Table 114............................... 146 Miscellaneous Instructions: trap ......................... Table 130............. 154 Special Registers: %lanemask_le ................................................................................................................maxntid .................. 166 Debugging Directives: ................................................... Table 141.. 167 Debugging Directives: ................................................................................................................................................. 167 Linking Directives: ..................... Table 112......................................................................................................................................... Table 132....... 147 Miscellaneous Instructions: pmevent............ 154 Special Registers: %lanemask_lt .............................. Table 110... Table 113.......... 156 PTX File Directives: ......................... 151 Special Registers: %ctaid . Table 136.... 152 Special Registers: %nctaid .................................... 156 Special Registers: %pm0.... Table 135.......................................................................loc ....... Table 131...... Table 137................ %pm3 .................................. Table 117............................................................................................................. Table 122.................................... Table 140.......................entry..................................... Table 129................ 163 Performance-Tuning Directives: .......... Table 119............................................ 164 Performance-Tuning Directives: .............................................. Table 133.................................... 156 Special Registers: %clock64 .................................. 161 Performance-Tuning Directives: ...................... Table 120..................section ................maxnreg ................... 144 Video Instructions: vset............................. 147 Special Registers: %tid ................. Table 109........................................... 157 PTX File Directives: ............................. 155 Special Registers: %lanemask_gt .........................version.................0 Table 107....................................................... %pm2.. 147 Miscellaneous Instructions: brkpt ..................... 152 Special Registers: %smid ..................................

....... 2010 ix ..........visible............................................ Linking Directives: ................Table 144........................................................... 173 January 24............. Table 145..................... 168 Pragma Strings: “nounroll” .

0 x January 24. 2010 .PTX ISA Version 2.

1. which are optimized for and translated to native target-architecture instructions. there is a lower requirement for sophisticated flow control. In fact. many-core processor with tremendous computational horsepower and very high memory bandwidth. PTX defines a virtual machine and ISA for general purpose parallel thread execution. Data-parallel processing maps data elements to parallel processing threads. stereo vision. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. 1. Similarly. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Because the same program is executed for each data element. the programmable GPU has evolved into a highly parallel. image scaling. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. January 24. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). PTX exposes the GPU as a data-parallel computing device.Chapter 1. Introduction This document describes PTX.2. the memory access latency can be hidden with calculations instead of big data caches. and pattern recognition can map image blocks and pixels to parallel processing threads. high-definition 3D graphics. and because it is executed on many data elements and has high arithmetic intensity. multithreaded. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. video encoding and decoding. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. PTX programs are translated at install time to the target hardware instruction set. image and media processing applications such as post-processing of rendered images.1. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. from general signal processing or physics simulation to computational finance or computational biology. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. 2010 1 .

x features are supported on the new sm_20 target. memory.ftz) modifier may be used to enforce backward compatibility with sm_1x.f32 instruction also supports .rn. fma.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. The mad. addition of generic addressing to facilitate the use of general-purpose pointers. reduction.f32 require a rounding modifier for sm_20 targets. PTX 2. Single-precision add.f32 maps to fma.1. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. 1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. 1. Achieve performance in compiled applications comparable to native GPU performance.sat modifiers. Provide a machine-independent ISA for C/C++ and other compilers to target. The main areas of change in PTX 2.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.x.rm and . which map PTX to specific target machines. barrier. Improved Floating-Point Support A main area of change in PTX 2. A single-precision fused multiply-add (fma) instruction has been added.x code will continue to run on sm_1x targets as well.0 is in improved support for the IEEE 754 floating-point standard.3. Facilitate hand-coding of libraries.0 PTX ISA Version 2.f32 requires sm_20.3. A “flush-to-zero” (. surface.f32. and mul now support .0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. PTX ISA Version 2.ftz and . • • • 2 January 24. atomic. including integer.0 are improved support for IEEE 754 floating-point operations. and video instructions.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 and mad. performance kernels. The mad.f32 for sm_20 targets. The fma. Legacy PTX 1. The changes from PTX ISA 1. and the introduction of many new instructions. Both fma.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Instructions marked with . When code compiled for sm_1x is executed on sm_20 devices. Provide a code distribution ISA for application and middleware developers. and architecture tests. sub. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.0 is a superset of PTX 1.PTX ISA Version 2. 2010 . and all PTX 1.rp rounding modifiers for sm_20 targets. Provide a common source-level ISA for optimizing code generators and translators. Most of the new features require a sm_20 target. mad.

Introduction • Single. st. and directives are introduced in PTX 2.2. suld. allowing memory instructions to access these spaces without needing to specify the state space. A new cvta instruction has been added to convert global.e.and double-precision div. Instructions prefetch and prefetchu have been added. and shared addresses to generic address and vice-versa has been added. so recursion is not yet supported. Generic addressing unifies the global. st. special registers. stack layout. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. and shared state spaces. 1. isspacep. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. and Application Binary Interface (ABI). PTX 2. prefetchu. cvta. Support for an Application Binary Interface Rather than expose details of a particular calling convention.clamp and . stack-based ABI.0 closer to full compliance with the IEEE 754 standard. ldu. and sqrt with IEEE 754 compliant rounding have been added.Chapter 1. and sust. • Taken as a whole. Surface Instructions • • Instruction sust now supports formatted surface stores. and shared addresses to generic addresses. and red now support generic addressing. Generic Addressing Another major change is the addition of generic addressing. and vice versa.3.g. instructions ld. 2010 3 . New Instructions The following new instructions. In PTX 2. Surface instructions support additional clamp modifiers.3. . See Section 7 for details of the function definition and call syntax needed to abstract the ABI.. local. i.3.3. Cache operations have been added to instructions ld. NOTE: The current version of PTX does not implement the underlying. an address that is the same across all threads in a warp.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. January 24. local. prefetch.zero. These are indicated by the use of a rounding modifier and require sm_20.0. Instructions testp and copysign have been added.0. 1. rcp. atom. local.4. for prefetching to specified level of memory hierarchy. e. 1. these changes bring PTX 2. Instruction cvta for converting global.

arrive instruction has been added. vote.or}.le. Other Extensions • • • Video instructions (includes prmt) have been added. bar now supports an optional thread count and register operands. and Vote Instructions • • • New atomic and reduction instructions {atom. Instructions bar.pred have been added.u32 and bar. Barrier Instructions • • A system-level membar instruction. %clock64.red}. 2010 .PTX ISA Version 2.shared have been extended to handle 64-bit data types for sm_20 targets. has been added. has been added. .red.ge.section. membar. A new directive. A bar.popc.lt. %lanemask_{eq. A “vote ballot” instruction.gt} have been added. New special registers %nsmid.add. Reduction. Instructions {atom.{and. bfi bit field extract and insert popc clz Atomic.ballot.sys.red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.f32 have been added.red}. 4 January 24.b32.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.

Chapter 9 lists special registers. Chapter 8 describes the instruction set. Chapter 10 lists the assembly directives supported in PTX. Introduction 1. types. Chapter 3 gives an overview of the PTX virtual machine model. and variable declarations.4.0.Chapter 1. 2010 5 . and PTX support for abstracting the Application Binary Interface (ABI). Chapter 5 describes state spaces. calling convention. Chapter 11 provides release notes for PTX Version 2. January 24. Chapter 4 describes the basic syntax of the PTX language. Chapter 7 describes the function and call syntax. Chapter 6 describes instruction operands. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.

PTX ISA Version 2.0 6 January 24. 2010 .

Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.2. To coordinate the communication of the threads within the CTA. 2. and tid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. data-parallel. a portion of an application that is executed many times. January 24. Threads within a CTA can communicate with each other. work. 2010 7 .Chapter 2. or 3D shape specified by a three-element vector ntid (with elements ntid. Programming Model 2. Each CTA thread uses its thread identifier to determine its assigned role.y. compute-intensive portions of applications running on the host are off-loaded onto the device. assign specific input and output positions.1. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. is an array of threads that execute a kernel concurrently or in parallel.y. or 3D CTA. but independently on different data. More precisely. Programs use a data parallel decomposition to partition inputs. 2D. or CTA. 2D.z) that specifies the thread’s position within a 1D. To that effect. The vector ntid specifies the number of threads in each CTA dimension. Each thread has a unique thread identifier within the CTA. Each CTA has a 1D.x. and ntid. Cooperative thread arrays (CTAs) implement CUDA thread blocks. and select work to perform. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.x. and results across the threads of the CTA. (with elements tid. It operates as a coprocessor to the main CPU.2. 2. can be isolated into a kernel function that is executed on the GPU as many different threads.1. or host: In other words. A cooperative thread array. compute addresses. ntid. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. The thread identifier is a three-element vector tid. tid.z).

or sequentially. However. A warp is a maximal subset of threads from a single CTA. which may be used in any instruction where an immediate operand is allowed.2. a warp has 32 threads.0 Threads within a CTA execute in SIMT (single-instruction. %nctaid. Each grid of CTAs has a 1D. such that the threads execute the same instructions at the same time. Threads may read and use these values through predefined. multiple-thread) fashion in groups called warps. Each grid also has a unique temporal grid identifier (gridid). or 3D shape specified by the parameter nctaid. Typically. This comes at the expense of reduced thread communication and synchronization. 2. WARP_SZ. The warp size is a machine-dependent constant. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. CTAs that execute the same kernel can be batched together into a grid of CTAs. %ctaid.2. Threads within a warp are sequentially numbered. read-only special registers %tid. 2D . and %gridid. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Some applications may be able to maximize performance with knowledge of the warp size. 2010 . so that the total number of threads that can be launched in a single kernel invocation is very large. 8 January 24.PTX ISA Version 2. because threads in different CTAs cannot communicate and synchronize with each other. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. depending on the platform. Multiple CTAs may execute concurrently and in parallel. so PTX includes a run-time immediate constant. The host issues a succession of kernel invocations to the device. %ntid.

0) Thread (1. 0) Thread (0.Chapter 2. Figure 1. 1) CTA (1. 2) Thread (4. 1) Thread (4. 1) Thread (3. 0) CTA (2. 2010 9 . 1) Thread (1. 2) Thread (3. 2) Thread (2. 0) CTA (0. 0) Thread (3. Thread Batching January 24. 1) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) CTA (1. 2) Thread (1. 1) Thread (0. 0) Thread (4. 1) Grid 2 Kernel 2 CTA (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. A grid is a set of CTAs that execute independently. 1) CTA (2. 1) Thread (0. 0) Thread (2.

Both the host and the device maintain their own local memory. and texture memory spaces are persistent across kernel launches by the same application. The device memory may be mapped and read or written by the host. constant. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. 10 January 24. for more efficient transfer.0 2. or. and texture memory spaces are optimized for different memory usages.3. The global.PTX ISA Version 2. Finally. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Each thread has a private local memory. 2010 . as well as data filtering. respectively. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. for some specific data formats. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. all threads have access to the same global memory. constant. referred to as host memory and device memory. The global. Texture memory also offers different addressing modes.

1) Block (1.Chapter 2. 0) Block (1. 1) Block (1. 0) Block (2. Memory Hierarchy January 24. 1) Block (0. 1) Block (2. 0) Block (1. 2010 11 . 1) Grid 1 Global memory Block (0. 2) Figure 2. 0) Block (0. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Block (1.

0 12 January 24. 2010 .PTX ISA Version 2.

As thread blocks terminate. The multiprocessor SIMT unit creates.1. The threads of a thread block execute concurrently on one multiprocessor. the first parallel thread technology. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. A multiprocessor consists of multiple Scalar Processor (SP) cores. The way a block is split into warps is always the same. A warp executes one common instruction at a time. for example. disabling threads that are not on that path. so full efficiency is realized when all threads of a warp agree on their execution path. and executes concurrent threads in hardware with zero scheduling overhead. schedules. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. it splits them into warps that get scheduled by the SIMT unit. and executes threads in groups of parallel threads called warps. If threads of a warp diverge via a data-dependent conditional branch. the threads converge back to the same execution path.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. each warp contains threads of consecutive. new blocks are launched on the vacated multiprocessors. and on-chip shared memory. manages. (This term originates from weaving. To manage hundreds of threads running several different programs. a multithreaded instruction unit. the warp serially executes each branch path taken. increasing thread IDs with the first warp containing thread 0. Branch divergence occurs only within a warp. Parallel Thread Execution Machine Model 3. a voxel in a volume. When a multiprocessor is given one or more thread blocks to execute. The multiprocessor maps each thread to one scalar processor core. When a host program invokes a kernel grid. 2010 13 . different warps execute independently regardless of whether they are executing common or disjointed code paths. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. a cell in a grid-based computation). the multiprocessor employs a new architecture we call SIMT (single-instruction. At every instruction issue time. manages. multiple-thread). A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). and each scalar thread executes independently with its own instruction address and register state. It implements a single-instruction barrier synchronization. allowing.Chapter 3. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. January 24. and when all paths complete. The multiprocessor creates.

As illustrated by Figure 3. require the software to coalesce loads into vectors and manage divergence manually. and writes to the same location in global memory for more than one of the threads of the warp. modify. modifies. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. the kernel will fail to launch.PTX ISA Version 2. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. each read. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. which is a read-only region of device memory. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. as well as data-parallel code for coordinated threads. If an atomic instruction executed by a warp reads.0 SIMT architecture is akin to SIMD (Single Instruction. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. 2010 . however. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. Vector architectures. SIMT enables programmers to write thread-level parallel code for independent. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. 14 January 24. which is a read-only region of device memory. scalar threads. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. but one of the writes is guaranteed to succeed. the number of serialized writes that occur to that location and the order in which they occur is undefined. on the other hand. A key difference is that SIMD vector organizations expose the SIMD width to the software. whereas SIMT instructions specify the execution and branching behavior of a single thread. For the purposes of correctness. but the order in which they occur is undefined. If there are not enough registers or shared memory available per multiprocessor to process at least one block. A multiprocessor can execute as many as eight thread blocks concurrently. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. In practice. write to that location occurs and they are all serialized. the programmer can essentially ignore the SIMT behavior. In contrast with SIMD vector machines. • The local and global memory spaces are read-write regions of device memory and are not cached.

Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3. 2010 15 . Figure 3. Hardware Model January 24.

0 16 January 24. 2010 .PTX ISA Version 2.

version directive specifying the PTX language version. The following are common preprocessor directives: #include. PTX is case sensitive and uses lowercase for keywords.target directive specifying the target architecture assumed. Comments Comments in PTX follow C/C++ syntax.Chapter 4. The C preprocessor cpp may be used to process PTX source files. #else. 2010 17 . whitespace is ignored except for its use in separating tokens in the language. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #line. January 24. Each PTX file must begin with a . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. and using // to begin a comment that extends to the end of the current line. #ifdef. using non-nested /* and */ for comments that may span multiple lines. #endif. Lines beginning with # are preprocessor directives. See Section 9 for a more information on these directives.1. #define. #if. Source Format Source files are ASCII text. Lines are separated by the newline character (‘\n’). Syntax PTX programs are a collection of text source files. 4. followed by a .2. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 4. All whitespace characters are equivalent. Pseudo-operations specify symbol and addressing management. Comments in PTX are treated as whitespace.

18 January 24. Instruction keywords are listed in Table 2.maxnreg .global . Examples: . Statements A PTX statement is either a directive or an instruction. address expressions. written as @!p.loc . Table 1. followed by source operands. Directive Statements Directive keywords begin with a dot. shl. array[r1].minnctapersm . Instructions have an optional guard predicate which controls conditional execution. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.b32 r1. r2.5.target .x. .maxntid . r1. 2.global start: .reg . The guard predicate may be optionally negated. so no conflict is possible with user-defined identifiers.1. . 0. mov.3.version .3.pragma .f32 array[N].maxnctapersm .tex . and is written as @p.func . r2.section . Statements begin with an optional label and end with a semicolon.0 4. constant expressions. %tid.local .entry .param .align . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. Operands may be register variables. All instruction keywords are reserved tokens in PTX.sreg . r2.2.b32 r1.global. or label names.const .extern . and terminated with a semicolon.3. 2010 .shared . where p is a predicate register. The destination operand is first. ld.PTX ISA Version 2.f32 r2.b32 add.visible 4.reg . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. The guard predicate follows the optional label and precedes the opcode.b32 r1.file PTX Directives .

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4. Syntax Table 2. 2010 19 .

e. …. %pm3 WARP_SZ 20 January 24.PTX ISA Version 2. The percentage sign can be used to avoid name conflicts. Table 3. Many high-level languages such as C and C++ follow similar rules for identifier names. dollar. digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign. listed in Table 3.4. underscore. underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or percentage character followed by one or more letters. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.0 4. digits. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. PTX allows the percentage sign as the first character of an identifier. between user-defined variable names and compiler-generated names. 2010 . or they start with an underscore. except that the percentage sign is not allowed.g. or dollar characters.

Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. Type checking rules remain the same for integer. For predicate-type data and instructions. octal. where the behavior of the operation depends on the operand types. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.u64. Unlike C and C++.e. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.1.s64) unless the value cannot be fully represented in . Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. 0[fF]{hexdigit}{8} // single-precision floating point January 24. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. hexadecimal.2. integer constants are allowed and are interpreted as in C. 2010 21 . and bit-size types. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.. To specify IEEE 754 doubleprecision floating point values. i. 4.Chapter 4. Integer literals may be written in decimal. When used in an instruction or data initialization. there is no suffix letter to specify size. i. the sm_1x and sm_20 targets have a WARP_SZ value of 32. or binary notation. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. Constants PTX supports integer and floating-point constants and constant expressions. 4.5.s64 or . Floating-point literals may be written with an optional decimal point and an optional signed exponent. These constants may be used in data initialization and as operands to instructions.s64 or the unsigned suffix is specified. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. To specify IEEE 754 single-precision floating point values. zero values are FALSE and non-zero values are TRUE. Syntax 4.5. floating-point.e. the constant begins with 0d or 0D followed by 16 hex digits. literals are always represented in 64-bit double-precision format. every integer constant has type .. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. the constant begins with 0f or 0F followed by 8 hex digits.5. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. The syntax follows that of C.u64). in which case the literal is unsigned (. each integer constant is converted to the appropriate size based on the data or instruction type at its use.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

January 24, 2010

Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

January 24, 2010

23

PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

24

January 24, 2010

2nd is .u64 .f64 use usual conversions .f64 integer . 2010 25 .s64) + .u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64.Chapter 4.f64 integer .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 integer integer integer integer integer int ?.s64 .s64 . Syntax 4.f64 use usual conversions .6.f64 converted type constant literal + ! ~ Cast Binary (.s64 .f64 : . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .s64 .f64 converted type .u64.5.u64 .s64 .u64 same as 1st operand .s64 .u64 .s64 .f64 same as source .f64 use usual conversions .u64) (. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . Table 5.u64 . or .u64 1st unchanged.u64 . .

2010 .0 26 January 24.PTX ISA Version 2.

the kinds of resources will be common across platforms. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.sreg . addressability.tex January 24. and level of sharing between threads. access speed. Global texture memory (deprecated). The list of state spaces is shown in Table 4. Special registers. 2010 27 . read-only memory. defined per-thread.param . and properties of state spaces are shown in Table 5. shared by all threads. defined per-grid.Chapter 5. fast.shared . and Variables While the specific resources available in a given target GPU will vary. Local memory.const . Addressable memory shared between threads in 1 CTA. access rights. Kernel parameters. Read-only. . pre-defined.local . State Spaces.reg . private to each thread.global . All variables reside in some state space. Global memory. State Spaces A state space is a storage area with particular characteristics. 5. Table 6. or Function or local parameters. Types.1. Name State Spaces Description Registers. and these resources are abstracted in PTX through state spaces and data types. The characteristics of a state space include its size. Shared. platform-specific.

local state space.param (as input to kernel) .shared . aside from predicate registers which are 1-bit. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).e. or 64-bits. 32-. 32-. unsigned integer.param and st. 1 Accessible only via the ld. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 64-. register variables will be spilled to memory. Registers differ from the other state spaces in that they are not fully addressable.sreg) state space holds predefined.1.1. Register size is restricted. or as elements of vector tuples. 3 Accessible only via the tex instruction.local . 16-. 28 January 24. Special Register State Space The special register (. Registers may have alignment boundaries required by multi-word loads and stores.param instructions. clock counters.param instruction.reg state space) are fast storage locations. Address may be taken via mov instruction. scalar registers have a width of 8-. Register State Space Registers (. For each architecture. The number of registers is limited. The most common use of 8-bit registers is with ld. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. and performance monitoring registers.tex Restricted Yes No3 5. CTA. the parameter is then located on the stack frame and its address is in the . it is not possible to refer to the address of a register. causing changes in performance. platform-specific registers. Device function input parameters may have their address taken via mov. st.global .0 Table 7. 2 Accessible via ld. such as grid.. All special registers are predefined. i. or 128-bits. When the limit is exceeded. 2010 .param (used in functions) .reg . and will vary from platform to platform. and cvt instructions.2. 5.sreg .const . and vector registers have a width of 16-.1. floating point. and thread parameters. predicate) or untyped.PTX ISA Version 2. Registers may be typed (signed integer.

Multiple incomplete array variables declared in the same bank become aliases.global. 5. ld. each pointing to the start address of the specified constant bank. 2010 29 . For the current devices.const[2] . In implementations that support a stack.const) state space is a read-only memory. the store operation updating a may still be in flight.b32 const_buffer[]. Local State Space The local state space (. the bank number must be provided in the state space of the load instruction.local to access local variables. whereas local memory variables declared January 24.5. This reiterates the kind of parallelism available in machines that run PTX. Constant State Space The constant (. For any thread in a context. Threads must be able to do their work without waiting for other threads to do theirs.local and st.b32 const_buffer[]. All memory writes prior to the bar. For example.Chapter 5. initialized by the host.extern . Sequential consistency is provided by the bar. there are eleven 64KB banks.global to access global variables. where bank ranges from 0 to 10. // load second word 5.b32 %r1. It is the mechanism by which different CTAs and different grids can communicate. Global memory is not sequentially consistent.3.global. This pointer can then be used to access the entire 64KB constant bank. as in lock-free and wait-free style programming. st. The constant memory is organized into fixed size banks. all addresses are in global memory are shared.local) is private memory for each thread to keep its own data.const[bank] modifier. where the size is not known at compile time.sync instruction are guaranteed to be visible to any reads after the barrier instruction. the stack is in local memory. To access data in contant banks 1 through 10.const[2].const[2] . State Spaces. [const_buffer+4]. It is typically standard memory with cache. an incomplete array in bank 2 is accessed as follows: . Banks are specified using the .4. Use ld. Types. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. bank zero is used for all statically-sized constant variables. Threads wait at the barrier until all threads in the CTA have arrived. and Variables 5. For example.global) state space is memory that is accessible by all threads in a context. The size is limited.1. Module-scoped local memory variables are stored at fixed addresses. Use ld. results in const_buffer pointing to the start of constant bank two. as it must be allocated on a perthread basis.sync instruction.1. Consider the case where one thread executes the following two assignments: a = a + 1. If another thread sees the variable b change.extern . If no bank number is given.1. Global State Space The global (. By convention. and atom. bank zero is used. for example). b = b – 1. The remaining banks may be used to implement “incomplete” constant arrays (in C. the declaration .

param instructions. read-only variables declared in the . mov. [buffer].0 within a function or kernel body are allocated on the stack.u32 %n.PTX ISA Version 2. ld.param state space.param instructions. per-kernel versus per-thread).1.param) state space is used (1) to pass input arguments from the host to the kernel.reg . device function parameters were previously restricted to the register state space. Similarly. ld.1.param. all local memory variables are stored at fixed addresses and recursive function calls are not supported. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. typically for passing large structures by value to a function. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param state space and is accessed using ld. Note that PTX ISA versions 1.param . (2a) to declare formal input and return parameters for device functions called from within kernel execution. 5.param space variables.f64 %d. [N]. For example. 5.f64 %d. Example: .x supports only kernel function parameters in .entry foo ( . PTX code should make no assumptions about the relative locations or ordering of . These parameters are addressable. … 30 January 24. The address of a kernel parameter may be moved into a register using the mov instruction.param .entry bar ( . .6. .u32 %n.u32 %ptr.6. Values passed from the host to the kernel are accessed through these parameter variables using ld.param.0 and requires target architecture sm_20.param. The kernel parameter variables are shared across all CTAs within a grid. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).reg .1. in some implementations kernel parameters reside in global memory. Therefore.b32 N.param space. 2010 .reg . Note: The location of parameter space is implementation specific. Parameter State Space The parameter (. The use of parameter state space for device function parameters is new to PTX ISA version 2. len. %n.u32 %n.b32 len ) { . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.align 8 . No access protection is provided between parameter and global space in this case. In implementations that do not support a stack. … Example: .b8 buffer[64] ) { .param .u32 %ptr. [%ptr]. ld. The resulting address is in the .

ld. the address of a function input parameter may be moved into a register using the mov instruction. the caller will declare a locally-scoped .param formal parameter having the same size and alignment as the passed argument. It is not possible to use mov to get the address of a return parameter or a locally-scoped . In PTX. The most common use is for passing objects by value that do not fit within a PTX register. (4. a byte array in parameter space is used.f64 %d. In this case.local and st.param . }. State Spaces. and Variables 5. call foo.param. and so the address will be in the . Note that the parameter will be copied to the stack if necessary. . } mystruct. mystruct). 2010 31 .align 8 . … st. x.param. int y.align 8 .b32 N. st.s32 %y.reg . This will be passed by value to a callee.func foo ( .param space is also required whenever a formal parameter has its address taken within the called function. ld.param .param and function return parameters may be written using st. . January 24.reg .param space variable.f64 [mystruct+0]. which declares a . .param. such as C structures larger than 8 bytes.b8 buffer[12] ) { .Chapter 5.local instructions. passed to foo … . Function input parameters may be read via ld.reg .0 extends the use of parameter space to device function parameters. [buffer].2.param. … } // code snippet from the caller // struct { double d. dbl.s32 [mystruct+8]. it is illegal to write to an input parameter or read from a return parameter.f64 %d.6. Example: // pass object of type struct { double d. … See the section on function call syntax for more details. Typically.local state space and is accessed via ld. . is flattened. Types.f64 dbl.s32 x.s32 %y. .reg . Device Function Parameters PTX ISA version 2.reg .b8 mystruct.1. [buffer+8]. .param. Aside from passing structures by value.param byte array variable that represents a flattened C structure or union. int y.

7.tex directive will bind the named texture memory variable to a hardware texture identifier.8.tex state space are equivalent to module-scoped .u32 tex_a.u32 .1. An error is generated if the maximum number of physical resources is exceeded.u32 . A texture’s base address is assumed to be aligned to a 16-byte boundary.u32 .shared and st. Another is sequential access from sequential threads. 32 January 24. The texture name must be of type . Shared memory typically has some optimizations to support the sharing.tex . a legacy PTX definitions such as . tex_d.u32 tex_a.6 for its use in texture instructions.texref variables in the . Multiple names may be bound to the same physical texture identifier.global state space.tex directive is retained for backward compatibility. tex_d. where texture identifiers are allocated sequentially beginning with zero. It is shared by all threads in a context. where all threads read from the same address.3 for the description of the . The .1.tex variables are required to be defined in the global scope.tex) state space is global memory accessed via the texture instruction. and programs should instead reference texture memory through variables of type .tex . tex_c.0 5. 5.7.texref tex_a. One example is broadcast. Texture State Space (deprecated) The texture (. An address in shared memory can be read and written by any thread in a CTA. tex_f.shared to access shared variables. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. The . Example: .texref type and Section 8. is equivalent to .tex . Use ld. Shared State Space The shared (.tex .tex .global . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 or .PTX ISA Version 2. and variables declared in the . Texture memory is read-only. For example.shared) state space is a per-CTA region of memory for threads in a CTA to share data. See Section 5. Physical texture resources are allocated on a per-module granularity.u64. 2010 .texref. and .

. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . and . .2.s32. . Signed and unsigned integer types are compatible if they have the same size. 2010 33 .f32.pred Most instructions have one or more type specifiers.b8 instruction types are restricted to ld. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. st. For convenience. st. all variables (aside from predicates) could be declared using only bit-size types. and Variables 5. State Spaces.f64 . Types 5. January 24. Types.2.b8.2.f64 types. . Two fundamental types are compatible if they have the same basic type and are the same size. Fundamental Types In PTX.f16. so their names are intentionally short.u16. The same typesize specifiers are used for both variable definitions and for typing instructions. Restricted Use of Sub-Word Sizes The .Chapter 5. . stored.f32 and . .u8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. or converted to other types and sizes.s8. . ld. so that narrow values may be loaded. and converted using regular-width registers.2. A fundamental type specifies both a basic type and a size. . and cvt instructions. the fundamental types reflect the native data types supported by the target architectures.u8. and instructions operate on these types. 5.u64 .b16.1. needed to fully specify instruction behavior. but typed variables enhance program readability and allow for better operand type checking.f64 types. The .f32 and . For example.b64 . The bitsize type is compatible with any fundamental type having the same size.b32. .s16.s64 . . . The following table lists the fundamental type specifiers for each basic type: Table 8. . Register variables are always of a fundamental type. All floating-point instructions operate only on .f16 floating-point type is allowed only in conversions to and from .u32. stored.s8. In principle. Operand types and sizes are checked against instruction types for compatibility.

and overall size is hidden to a PTX program.{u32.e.3. allowing them to be defined separately and combined at the site of usage in the program. In independent mode the fields of the . suq). hence the term “opaque”. and surface descriptor variables. PTX has two modes of operation. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. suld. since these properties are defined by . sampler.u64} reg. Texture. field ordering. sured). Sampler. In the unified mode. opaque_var. store. but all information about layout. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. In the independent mode.0 5. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. These types have named fields similar to structures. For working with textures and samplers.texref. Creating pointers to opaque variables using mov. sust. texture and sampler information each have their own handle. i. accessing the pointer with ld and st instructions. and query instructions.samplerref.surfref. The three built-in types are . or surfaces via texture and surface load/store instructions (tex. 34 January 24. Retrieving the value of a named member via query instructions (txq. and Surface Types PTX includes built-in “opaque” types for defining texture. . but the pointer cannot otherwise be treated as an address. and . passed as a parameter to functions. and de-referenced by texture and surface load. 2010 . samplers. texture and sampler information is accessed through a single . or performing pointer arithmetic will result in undefined results. base address.samplerref variables.texref type that describe sampler properties are ignored. The following tables list the named members of each type for unified and independent texture modes.texref handle.PTX ISA Version 2. Referencing textures. the resulting pointer may be stored to and loaded from memory..

clamp_ogl. clamp_to_border N/A N/A N/A N/A N/A . linear wrap. 2010 35 . Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_to_edge. mirror. mirror.samplerref values N/A N/A N/A N/A nearest. and Variables Table 9.texref values .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. 1 nearest. clamp_to_border 0.Chapter 5.texref values in elements in elements in elements 0. linear wrap. clamp_to_edge. clamp_ogl. Types. Member width height depth Opaque Type Fields in Independent Texture Mode .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. State Spaces. 1 ignored ignored ignored ignored .

.PTX ISA Version 2.samplerref my_sampler_name. Example: . When declared at module scope. Example: .texref my_texture_name.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.texref tex1.global .global . these variables must be in the . . filter_mode = nearest }.global .surfref my_surface_name.global . the types may be initialized using a list of static expressions assigning values to the named members. 36 January 24.global state space.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. At module scope.param state space. these variables are declared in the . . As kernel parameters.global . 2010 .

b8 v.struct float4 { . and an optional fixed address for the variable. . a variable declaration describes both the variable’s type and its state space. This is a common case for three-dimensional grids. its name. Examples: . and Variables 5. r.v3 }.v2 . Variable Declarations All storage for data is specified with variable declarations. A variable declaration names the space in which the variable resides. // a length-4 vector of bytes By default. and they may reside in the register space.4. 5.1. an optional initializer.f32 bias[] = {-1. etc.global .u16 uv. q. an optional array size. 0. Vectors cannot exceed 128-bits in length. Vectors Limited-length vector types are supported. .pred p.reg .v2 or .u32 loc.v2.4.f32 v0.Chapter 5. // typedef .0}. .f64 is not allowed. for example. State Spaces.v4.s32 i. vector variables are aligned to a multiple of their overall size (vector length times base-type size). Examples: . // a length-2 vector of unsigned ints .reg .v4 vector. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . January 24. PTX supports types for simple aggregate objects such as vectors and arrays.u8 bg[4] = {0. 0}. // a length-4 vector of floats . its type and size. . to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v1. Types.struct float4 coord. 1.v4. where the fourth element provides padding. Variables In PTX. .2.global .4.v4 . 2010 37 . Three-element vectors may be handled by using a .f32 V. 5. Predicate variables may only be declared in the register state space.f32 accel. Vectors must be based on a fundamental type.shared .const . .0. .global . textures. In addition to fundamental types.reg .v4 . 0.v4 . Every variable must reside in one of the state spaces enumerated in the previous section.global .global .

Similarly. where the variable name is followed by an equals sign and the initial value or values for the variable.1}.0 5. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. Initializers are allowed for all types except . .05.u32 or .local . -1}. 19*19 (361) halfwords are reserved (722 bytes).u8 rgba[3] = {{1.. Here are some examples: . or is left empty.{. 5.v4 .1.f32 blur_kernel[][] = {{. The size of the array specifies how many elements should be reserved.1.4. Variable names appearing in initializers represent the address of the variable. For the kernel declaration above. // address of rgba into ptr Currently. .0}}. Variables that hold addresses of variables or instructions should be of type .1.0.PTX ISA Version 2. The size of the dimension is either a constant expression. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).4. this can be used to initialize a jump table to be used with indirect branches or calls. {0.u64.0. 38 January 24.pred.. Array Declarations Array declarations are provided to allow the programmer to reserve space.. {0.0}. . {0.global .u16 kernel[19][19].0. 2010 .05}..1.global .4.4.global . 1} }. A scalar takes a single value.shared .3. being determined by an array initializer.. {1. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. {0. variable initialization is supported only for constant and global state spaces. Examples: .0}.0.05.s32 offset[][] = { {-1.{. 0}.. label names appearing in initializers represent the address of the next instruction following the label. .global . To declare an array.f16 and . 0}.1.s32 n = 10.05}}.u8 mailbox[128]. .global . this can be used to statically initialize a pointer to a variable.b32 ptr = rgba.

reg . . %r1. suppose a program uses a large number.const . %r99.. and Variables 5.0}. say one hundred. The variable will be aligned to an address which is an integer multiple of byte-count. The default alignment for vector variables is to a multiple of the overall vector size. For arrays. State Spaces. %r1. Parameterized Variable Names Since PTX supports virtual registers. Elements are bytes. named %r0.b32 %r<100>.. …. 5.0. Array variables cannot be declared this way.b8 bar[8] = {0..0.align 4 . it is quite common for a compiler frontend to generate a large number of register names. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.2. January 24.4. .5. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. The default alignment for scalar and array variables is to a multiple of the base-type size. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Examples: // allocate array at 4-byte aligned address. These 100 register variables can be declared as follows: . For example. Rather than require explicit declaration of every name.b32 variables.0. Types. 2010 39 . Alignment is specified using an optional .4. not for individual elements.0.6. nor are initializers permitted. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.0.align byte-count specifier immediately following the state-space specifier. // declare %r0. of . and may be preceded by an alignment specifier.Chapter 5. alignment specifies the address alignment for the starting address of the entire array.

PTX ISA Version 2.0 40 January 24. 2010 .

b. . Predicate operands are denoted by the names p. Instructions ld and st move data from/to addressable state spaces to/from registers. 2010 41 . the sizes of the operands must be consistent.3. r. Source Operands The source operands are denoted in the instruction descriptions by the names a. 6. Integer types of a common size are compatible with each other. The ld. The mov instruction copies data between registers.2. and c. The result operand is a scalar or vector variable in the register state space. q. There is no automatic conversion between types. PTX describes a load-store machine. as its job is to convert from nearly any data type to any other data type (and size). For most operations. s.reg register state space.1. Instruction Operands 6. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. so operands for ALU instructions must all be in variables declared in the . and a few instructions have additional predicate source operands. and cvt instructions copy data from one location to another. Operand Type Information All operands in instructions have a known type from their declarations. Most instructions have an optional predicate guard that controls conditional execution. The cvt (convert) instruction takes a variety of operand types and sizes. Each operand type must be compatible with the type determined by the instruction template and instruction type. 6. mov. The bit-size type is compatible with every type having the same size. January 24. st.Chapter 6. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.

W. . Here are a few examples: .reg .4.s32 mov. q. 6. . r0. [V].const. . tbl. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.reg .f32 V. All addresses and address computations are byte-based. . The mov instruction can be used to move the address of a variable into a pointer.u16 x.s32 tbl[256].gloal. p. .u32 42 January 24. [tbl+12].const .u16 ld. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. address registers. . and immediate address expressions which evaluate at compile-time to a constant address.[x]. and Vectors Using scalar variables as operands is straightforward.reg . there is no support for C-style pointer arithmetic.4.s32 q. 2010 . and vectors.0 6. arrays.reg .f32 ld. Using Addresses.global .v4 .1. Load and store operations move data between registers and locations in addressable state spaces. The address is an offset in the state space in which the variable is declared.PTX ISA Version 2.b32 p.f32 W.v4 . Examples include pointer arithmetic and pointer comparisons. ld. address register plus byte offset. Arrays.shared.v4. The interesting capabilities begin with addresses. Address expressions include variable names.shared . The syntax is similar to that used in many assembly languages.u16 r0.

Instruction Operands 6. Array elements can be accessed using an explicitly calculated byte address.r.c. January 24. or a simple “register with constant offset” expression. [addr+offset]. [addr+offset2]. . as well as the typical color fields . . a[N-1].reg .global.f32 {a.global. or by indexing into the array using square-bracket notation.y.reg . . .u32 s.z V.4. A brace-enclosed list is used for pattern matching to pull apart vectors.u32 s. where the offset is a constant expression that is either added or subtracted from a register variable.u32 {a.x.f32 ld. Rd}. Arrays as Operands Arrays of all types can be declared. V. Vector elements can be extracted from the vector with the suffixes . and in move instructions to get the address of the label or function into a register. a register variable. c.f32 a.3. V2.r V. The expression within square brackets is either a constant integer. mov.2. say {Ra. The size of the array is a constant in the program. Vector loads and stores can be used to implement wide loads and stores. . The registers in the load/store operations can be a vector.4. it must be written as an address calculation prior to use. // move address of a[1] into s 6.b and . 2010 43 . and tex.v4 .d}. ld.v2.g.f32 V. ld.b.global.b V. d. Rb. Vectors as Operands Vector operands are supported by a limited subset of instructions.x V.4.4.w. or a braceenclosed list of similarly typed scalars.u32 s. . a[0]. Here are examples: ld. which may improve memory performance. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.global. If more complicated indexing is desired. Vectors may also be passed as arguments to called functions. and the identifier becomes an address constant in the space where the array is declared. b.v4.c.g V.z and .y V. Examples are ld.w = = = = V. st. which include mov. Elements in a brace-enclosed vector.b. Rc.v4.d}. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.Chapter 6. for use in an indirect branch or call. a[1].a.a 6. mov.

Operands of different sizes or types must be converted prior to the operation.0 6. Type Conversion All operands to all arithmetic. 6. the u16 is zero-extended to s32.PTX ISA Version 2.s32.5. For example. except for operations where changing the size and/or type is part of the definition of the instruction. 44 January 24. and data movement instruction must be of the same type and size.5.u16 instruction is given a u16 source operand and s32 as a destination operand.000 for f16). Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. and ~131. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. logic. if a cvt.1. 2010 .

cvt. The type of extension (sign or zero) is based on the destination format. zext = zero-extend. f2u = float-to-unsigned.s16. Instruction Operands Table 11. s2f = signed-to-float.u32 targeting a 32-bit register will first chop to 16-bits. 2010 45 . For example. f2f = float-to-float. the result is extended to the destination register width after chopping.Chapter 6. u2f = unsigned-to-float. f2s = float-to-signed. Notes 1 If the destination register is wider than the destination format. chop = keep only low bits that fit. January 24. then sign-extend to 32-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.

choosing even integer if source is equidistant between two integers. 2010 .2. Table 12.0 6. Modifier . Rounding Modifiers Conversion instructions may specify a rounding modifier.rn .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. there are four integer rounding modifiers and four floating-point rounding modifiers.rz .PTX ISA Version 2. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. In PTX.rzi .rm .rni .5. The following tables summarize the rounding modifiers.rmi . Modifier .rpi Integer Rounding Modifiers Description round to nearest integer.

while global memory is slowest. The register in a store operation is available much more quickly.6. Instruction Operands 6. Operand Costs Operands from different state spaces affect the speed of an operation. Much of the delay to memory can be hidden in a number of ways. Registers are fastest.Chapter 6. Table 11 gives estimates of the costs of using different kinds of memory. Another way to hide latency is to issue the load instructions as early as possible. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. first access is high Notes January 24. Table 14. 2010 47 . The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution.

PTX ISA Version 2. 2010 .0 48 January 24.

we describe the features of PTX needed to achieve this hiding of the ABI. so recursion is not yet supported. 7. The simplest function has no parameters or return values. NOTE: The current version of PTX does not implement the underlying.func directive. stack-based ABI. These include syntax for function definitions. function calls. Function declarations and definitions In PTX. Abstracting the ABI Rather than expose details of a particular calling convention. together these specify the function’s interface. A function must be declared or defined prior to being called. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Execution of the ret instruction within foo transfers control to the instruction following the call.Chapter 7. and return values may be placed directly into register variables. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. the function name. … Here. and is represented in PTX as follows: .1. parameter passing. 2010 49 . arguments may be register variables or constants. and an optional list of input parameters. or prototype. stack layout. At the call. A function definition specifies both the interface and the body of the function. and memory allocated on the stack (“alloca”). implicitly saving the return address. In this section. and Application Binary Interface (ABI). January 24. Scalar and vector base-type input and return parameters may be represented simply as register variables. execution of the call instruction transfers control to foo. A function declaration specifies an optional list of return parameters. } … call foo. functions are declared and defined using the . support for variadic functions (“varargs”).func foo { … ret.

f64 f1.reg . (%x.func (.b8 c2. %rc2.func (. %ptr. … … // computation using x.param. (%r1.param.param. st. [y+11].b8 .param. %rc2.b8 .param. c3.reg .s32 x.PTX ISA Version 2.c4.0 Example: . [y+8].param.align 8 y[12]) { .param variable y is used in function definition bar to represent a formal parameter. inc_ptr. Second. For example.param space memory. ld. %rc1. ld. } … call (%r1).reg .f1. a . bumpptr. char c[4]. [y+9].b8 [py+ 8].param. a . note that . [y+0]. consider the following C structure.f64 f1.b64 [py+ 0]. Since memory accesses are required to be aligned to a multiple of the access size. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .4).c2. The .align 8 py[12].b8 [py+10]. st.b8 [py+ 9].reg .param . } { . %rd. c2.reg space.b8 c1. … In this example. In PTX.b8 [py+11].b32 c1. . 50 January 24.u32 %res) inc_ptr ( .c3. // scalar args in . py).param space variables are used in two ways. %rc1. [y+10].b8 c3. 2010 .param. st. ld.param. … ld.reg .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.u32 %inc ) { add. st. %inc. First. passed by value to a function: struct { double dbl. . this structure will be flattened into a byte array.param . c4. ret.f64 field are aligned.c1.reg .u32 %ptr.s32 out) bar (. ld.u32 %res.param. … st. }.param space call (%out).b8 c4. .reg . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .param state space is used to pass the structure by value: . byte array in .

For . 8. Parameters in .param state space is used to receive parameter values and/or pass return values back to the caller. Typically. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param and ld.param instructions used for argument passing must be contained in the basic block with the call instruction.reg state space can be used to receive and return base-type scalar and vector values. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. size.param space byte array with matching type.reg space variable with matching type and size. In the case of .param space formal parameters that are byte arrays. The .reg space formal parameters. In the case of .reg variables.param byte array is used to collect together fields of a structure being passed by value. • The . the corresponding argument may be either a . or a constant that can be represented in the type of the formal parameter.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. In the case of .param state space use in device functions. and alignment of parameters.Chapter 7. 4.reg variables.param variables.param variables or . January 24. Abstracting the ABI The following is a conceptual way to think about the . the corresponding argument may be either a .reg state space in this way provides legacy support. Note that the choice of . a .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.. The .param arguments. size. For a caller. • • • For a callee. Supporting the .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. the argument must also be a .param or . For a callee. or 16 bytes. • • Arguments may be .param memory must be aligned to a multiple of 1. A .g. all st. and alignment. or constants. 2010 51 .param space formal parameters that are base-type scalar or vector variables. . or a constant that can be represented in the type of the formal parameter.param argument must be declared within the local scope of the caller. This enables backend optimization and ensures that the . For a caller.reg space variable of matching type and size.reg or .param or . The following restrictions apply to parameter passing. • The . • • • Input and return parameters may be . 2.

0.param byte array should be used to return objects that do not fit into a register.1.0 restricts functions to a single return value. For sm_2x targets.x In PTX ISA version 1.reg or .x.param state space. PTX 2.1. formal parameters may be in either . PTX 2. 52 January 24. formal parameters were restricted to . 2010 .reg state space.param space parameters support arrays. PTX 1. Changes from PTX 1. and a .0 7.x supports multiple return values for this purpose. Objects such as C structures were flattened and passed or returned using multiple registers.PTX ISA Version 2. In PTX ISA version 2.0 continues to support multiple return registers for sm_1x targets. and . and there was no support for array parameters.

func (. 4. %s1.u32 ptr) %va_start . (3.reg . call %va_end. the alignment may be 1.reg . %r3).reg .. In PTX.func baz ( . %va_arg.reg . ctr.Chapter 7. … ) . max. Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . .func okay ( … ) Built-in functions are provided to initialize.u32 a.h and varargs.reg . This handle is then passed to the %va_arg and %va_arg64 built-in functions. . the size may be 1.func ( . PTX provides a high-level mechanism similar to the one provided by the stdarg. or 8 bytes. 0x8000000. %va_start.u32 align) .s32 result ) maxN ( .reg .reg . iteratively access. maxN. variadic functions are declared with an ellipsis at the end of the input parameter list.. N. 8. . . and end access to a list of variable arguments.s32 val.u32 ap. result. val. .reg . 4). following zero or more fixed parameters: . Once all arguments have been processed.reg . . } … call (%max). Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . (2.reg .u32 align) .b32 val) %va_arg (.u32 sz. Abstracting the ABI 7. or 4 bytes. … call (%max). . 2010 53 .2.u32 N. maxN. %s2).reg .func (.b32 ctr.b32 result. (ap).reg . 2. The function prototypes are defined as follows: . ret. along with the size and alignment of the next data value to be accessed. call (ap).reg .reg .u32 b. or 16 bytes.reg .u32.func (. bra Done. … %va_start returns Loop: @p Done: January 24.func %va_end (. ctr. (ap.pred p.ge p. the size may be 1. 4.u32 sz. %r2. bra Loop. 4. // default to MININT mov. call (val).b64 val) %va_arg64 (.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. %r1. 0. ) { .h headers in C. 2. setp. In both cases.u32 ptr.u32 ptr. . 2.reg .s32 result. mov. %va_end is called to free the variable argument list handle. For %va_arg. To support functions with a variable number of arguments. for %va_arg64.

If a particular alignment is required.local instructions. defined as follows: . The array is then accessed with ld.3.0 7. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. a function simply calls the built-in function %alloca.PTX ISA Version 2. To allocate memory. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.local and st.u32 ptr ) %alloca ( .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. Alloca NOTE: The current version of PTX does not support alloca. 54 January 24.reg .reg . 2010 .

2. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. and C are the source operands. b.s32. followed by some examples that attempt to show several possible instantiations of the instruction. q = !(a < b). A. opcode D.Chapter 8.lt p|q. B. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. while A. The setp instruction writes two destination registers. B. PTX Instructions PTX instructions generally have from zero to four operands. Instruction Set 8. 2010 55 .1. opcode D. C. In addition to the name and the format of the instruction. For some instructions the destination operand is optional. B. the D operand is the destination operand. We use a ‘|’ symbol to separate multiple destination registers. opcode A. 8. // p = (a < b). the semantics are described. For instructions that create a result value. a. setp. January 24. A.

2010 . // p = (i < n) // if i < n. … // compare i to n // if false. add. As an example. predicate registers can be declared as . r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. 1. the following PTX instruction sequence might be used: @!p L1: setp.0 8. 1. branch over 56 January 24.reg .pred as the type specifier. To implement the above example as a true conditional branch. q. This can be written in PTX as @p setp. add 1 to j To get a conditional branch or conditional function call. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.lt. Instructions without a guard predicate are executed unconditionally.pred p. where p is a predicate variable. i. add. bra L1. Predicated Execution In PTX.3. consider the high-level code if (i < n) j = j + 1.s32 p. j. n. So. n. i. j. use a predicate to control the execution of the branch or call instructions. optionally negated. predicate registers are virtual and have . Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 j.s32 p.s32 j.lt.PTX ISA Version 2.

2. ne. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. ne (not-equal). le. ordering comparisons are not defined for bit-size types. hi (higher).1.1. ls (lower-or-same). Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). the result is false. Comparisons 8. lt (less-than). The following table shows the operators for signed integer.3. unsigned integer.1. ge. Unsigned Integer. le (less-than-or-equal).Chapter 8. The unsigned comparisons are eq. and hs (higher-or-same). gt. ne. Instruction Set 8. Table 15. Table 16. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.3.1.3. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. If either operand is NaN. The bit-size comparisons are eq and ne. 2010 57 . gt (greater-than). and bitsize types. and ge (greater-than-or-equal). lt. lo (lower).

%p. and no direct way to load or store predicate register values. and mov. If either operand is NaN. 2010 . Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. If both operands are numeric values (not NaN). Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.1.0. geu. gtu. However.2. then these comparisons have the same result as their ordered counterparts. neu. two operators num (numeric) and nan (isNaN) are provided. unordered versions are included: equ. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. leu. xor. then the result of these comparisons is true. or.0 To aid comparison operations in the presence of NaN values. num returns true if both operands are numeric values (not NaN). and nan returns true if either operand is NaN.PTX ISA Version 2. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. setp can be used to generate a predicate from an integer. // convert predicate to 32-bit value 58 January 24. for example: selp. Table 17.u32 %r1. Table 18. There is no direct conversion between predicates and integer values. ltu. not.3.

bX . Signed and unsigned integer types agree provided they have the same size. and these are placed in the same order as the operands. i. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. • The following table summarizes these type checking rules.bX . most notably the data conversion instruction cvt.sX .fX ok ok ok ok January 24.reg . 2010 59 . and this information must be specified as a suffix to the opcode. For example. Floating-point types agree only if they have the same size..f32. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. cvt.reg . different sizes). the add instruction requires type and size information to properly perform the addition operation (signed.uX .f32 d. For example.4. a.sX ok ok ok inv . . they must match exactly.fX ok inv inv ok Instruction Type . Type Checking Rules Operand Type .Chapter 8. Table 19. a. For example: . and integer operands are silently cast to the instruction type if needed. It requires separate type-size modifiers for the result and source. b. b.u16 d. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.u16 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. float. Instruction Set 8. Example: . add. unsigned.e. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.uX ok ok ok inv .u16 d. a.u16 a.reg .

Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. When used with a narrower bit-size type. Source register size must be of equal or greater size than the instruction-type size. 1.1. the size must match exactly. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. inv = invalid. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.0 8. Bit-size source registers may be used with any appropriately-sized instruction type. The data is truncated to the instruction-type size and interpreted according to the instruction type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize.bX instruction types. ld. st. so those rows are invalid for cvt. stored. Operand Size Exceeding Instruction-Type Size For convenience. floating-point instruction types still require that the operand type-size matches exactly. The following table summarizes the relaxed type-checking rules for source operands. Table 20. the data will be truncated. Note that some combinations may still be invalid for a particular instruction.4. or converted to other types and sizes. Floating-point source registers can only be used with bit-size or floating-point instruction types. Notes 3. for example. the cvt instruction does not support . “-“ = allowed. 2010 . 60 January 24. For example. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. parse error. When used with a floating-point instruction type. so that narrow values may be loaded. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. no conversion needed. When a source operand has a size that exceeds the instruction-type size. unless the operand is of bit-size type. 4. stored. 2. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. and converted using regular-width registers.PTX ISA Version 2.

inv = Invalid. 1. 2010 61 . If the corresponding instruction type is signed integer. The following table summarizes the relaxed type-checking rules for destination operands.Chapter 8. When used with a narrower bit-size instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. Bit-size destination registers may be used with any appropriately-sized instruction type. the data is sign-extended. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. January 24. The data is signextended to the destination register width for signed integer instruction types. Destination register size must be of equal or greater size than the instruction-type size. When used with a floatingpoint instruction type.or sign-extended to the size of the destination register. the size must match exactly. Table 21. the data is zeroextended. and is zero-extended to the destination register width otherwise. 4. otherwise. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. the destination data is zero. Instruction Set When a destination operand has a size that exceeds the instruction-type size. 2. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. parse error. Notes 3. zext = zero-extend. “-“ = Allowed but no conversion needed. The data is sign-extended to the destination register width for signed integer instruction types. the data will be zero-extended.

When executing on a 32-bit data path. These extra precision bits can become visible at the application level. a compiler or code author targeting PTX can ignore the issue of divergent threads. until C is not expressive enough. Divergence of Threads in Control Constructs Threads in a CTA execute together. conditional function call. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.uni suffix. the threads are called uniform. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. the semantics of 16-bit instructions in PTX is machine-specific. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 8. Both situations occur often in programs. the threads are called divergent. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. at least in appearance.1.0 8. or conditional return. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. using the . If threads execute down different control flow paths. for many performance-critical applications. and for many applications the difference in execution is preferable to limiting performance. At the PTX language level. the optimizing code generator automatically determines points of re-convergence. until they come to a conditional control construct such as a conditional branch. 2010 . this is not desirable. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. 16-bit registers in PTX are mapped to 32-bit physical registers.PTX ISA Version 2. for example. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. For divergent control flow. by a right-shift instruction.6. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path.5. 8. 62 January 24. However.6. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. so it is important to have divergent threads re-converge as soon as possible. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. A compiler or programmer may chose to enforce portable. and 16-bit computations are “promoted” to 32-bit computations. The semantics are described using C. If all of the threads act in unison and follow a single control flow path. Therefore.

The Integer arithmetic instructions are: add sub add. 2010 63 . Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7.cc.7. the optional guard predicate is omitted from the syntax. In the following descriptions. Instructions All PTX instructions may be predicated.cc. Instruction Set 8.Chapter 8. addc sub. 8.1.

0.u16. sub. . a.PTX ISA Version 2. .s32 d. Introduced in PTX ISA version 1. Supported on all target architectures. 2010 .type sub{.s32. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.b. b.sat limits result to MININT. @p add..s32 c.u32. b.s64 }. sub.z.s32 type. Applies only to . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Applies only to . . PTX ISA Notes Target ISA Notes Examples Table 23. Description Semantics Notes Performs addition and writes the resulting value into a destination register.s32 c. .a.s32 .s32 type. . b.s32.type = { . add. Saturation modifier: .MAXINT (no overflow) for the size of the operation.sat limits result to MININT.. .c.sat.sat applies only to . Introduced in PTX ISA version 1.u32. d = a + b.sat}.1. d.s32 . add. .s32 d. a. b.u32 x. // . .type = { . d.sat}. PTX ISA Notes Target ISA Notes Examples 64 January 24.s64 }.sat applies only to .type add{. Supported on all target architectures. .s16. Saturation modifier: .0. // .s16. a. .0 Table 22.MAXINT (no overflow) for the size of the operation.u16. a. d = a – b. add Syntax Integer Arithmetic Instructions: add Add two values.u64.y.u64.

y2.b32 x1. carry-out written to CC.b32 x1.z2. @p @p @p @p add. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.z2.y1. x4. . a. x3.cc Syntax Integer Arithmetic Instructions: add. .cc.type = { .2.z4. . Supported on all target architectures.CF No integer rounding modifiers. No saturation. sub.z4.cc Add two values with carry-out. Supported on all target architectures.CF No integer rounding modifiers.y4.CF) holding carry-in/carry-out or borrowin/borrow-out. x3.y2. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.z1.cc.cc. add. Instruction Set Instructions add. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. @p @p @p @p add.z3.y4. x2. a. Behavior is the same for unsigned and signed integers.s32 }. Table 24.cc.type = {. addc{.cc. addc.cc}. x4.Chapter 8.b32 addc.CF. 2010 65 .u32.y1.b32 addc.y3. and there is no support for setting.cc.2.cc.u32.cc.z1. Introduced in PTX ISA version 1.s32 }. carry-out written to CC.b32 addc. b. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.type d.cc. x2. d = a + b + CC.b32 addc. d = a + b.cc specified. Introduced in PTX ISA version 1.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.b32 addc.type d. if .cc. These instructions support extended-precision integer addition and subtraction. Behavior is the same for unsigned and signed integers. clearing. or testing the condition code. . add.z3. No saturation. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.b32 addc. b.y3. No other instructions access the condition code.

with borrow-out.cc}. borrow-out written to CC.type d. Introduced in PTX ISA version 1.z4. @p @p @p @p sub. x4.cc. 2010 .y1.cc Syntax Integer Arithmetic Instructions: sub.cc. a. x3. x2.cc Subract one value from another.3.(b + CC.type = { . d = a – b.b32 subc. Behavior is the same for unsigned and signed integers. .z3.cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc. No saturation.cc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y2.s32 }. . x3.z3.b32 subc.y4. x4.z2. if .b32 x1.type = {. . a.y3. No saturation.cc specified.CF No integer rounding modifiers.z1.z2.b32 subc.0 Table 26. sub.s32 }. x2.CF). borrow-out written to CC.type d.y1. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.z1.y4. Behavior is the same for unsigned and signed integers.cc. .u32.z4.b32 x1. b.PTX ISA Version 2. Introduced in PTX ISA version 1.3. d = a .cc.cc.u32.b32 subc.cc. Supported on all target architectures. sub. b. subc{. @p @p @p @p sub.b32 subc.y2.CF No integer rounding modifiers.b32 subc. withborrow-in and optional borrow-out.y3. Supported on all target architectures. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.n>.wide}.Chapter 8.and 32-bit integer types.u16. mul{. . If .. then d is the same size as a and b.fys. The . then d is twice as wide as a and b to receive the full result of the multiplication.fys.y.0.fxs.type d.lo is specified.wide // for . mul.x. .hi variant // for .0>. t = a * b.hi or .s32. n = bitwidth of type. save only the low 16 bits // 32*32 bits. creates 64 bit result January 24. a.. d = t.lo variant Notes The type of the operation represents the types of the a and b operands.lo. d = t<2n-1. If .fxs. . b.type = { .wide.u64. Instruction Set Table 28.s16..wide.s32 z.. . 2010 67 . mul.hi. .s16 fa. Description Semantics Compute the product of two values. and either the upper or lower half of the result is written to the destination register. // for . // 16*16 bits yields 32 bits // 16*16 bits. Supported on all target architectures. .wide suffix is supported only for 16.wide is specified. d = t<n-1. mul.u32.lo.s64 }.s16 fa.

b.s32. t<2n-1.0 Table 29. mad{. If .0> + c.lo is specified. b.p. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.wide}.s32 r.wide is specified.lo.and 32-bit integer types. a.q.s64 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type mad.lo.sat. mad. . . t n d d d = = = = = a * b. and then writes the resulting value into a destination register.u16.hi. and either the upper or lower half of the result is written to the destination register.. d. then d and c are the same size as a and b.c. The .hi. a.lo variant Notes The type of the operation represents the types of the a and b operands. @p mad. Saturation modifier: . If .r.. b.s32 d. then d and c are twice as wide as a and b to receive the result of the multiplication. .s32 d. .hi mode.sat limits result to MININT. Description Semantics Multiplies two values and adds a third.MAXINT (no overflow) for the size of the operation..u64. Supported on all target architectures.hi variant // for .wide // for .wide suffix is supported only for 16.hi or .u32. 68 January 24.PTX ISA Version 2. bitwidth of type.s16..type = { .a. . // for . Applies only to .n> + c.s32 type in . 2010 . c. c.lo. . t<n-1.. t + c.0.

Instruction Set Table 30. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. 2010 69 .s32 d. and return either the high or low 32-bits of the 48-bit result. Supported on all target architectures. All operands are of the same type and size.Chapter 8.s32 }.16>. mul24.type = { . // for ... // low 32-bits of 24x24-bit signed multiply.type d.hi variant // for .lo}.b.. i. January 24. mul24{.hi may be less efficient on machines without hardware support for 24-bit multiply. mul24.a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.0. mul24. .hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.0>. d = t<47. . mul24.hi. b.u32. d = t<31. 48bits. a.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. t = a * b.e.

a.hi variant // for . 2010 .sat limits result of 32-bit signed addition to MININT.hi. t = a * b.. // for . 32-bit value to either the high or low 32-bits of the 48-bit result. b.type mad24.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. b. All operands are of the same type and size. i. c. .u32.c. c. a. // low 32-bits of 24x24-bit signed multiply. 70 January 24.sat.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. d.s32 d. d = t<31.type = { .s32 type in . mad24. a. mad24.e...hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mad24. Description Compute the product of two 24-bit integer values held in 32-bit source registers.16> + c. and add a third. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. Supported on all target architectures.lo. mad24{. d = t<47. Return either the high or low 32-bits of the 48-bit result.0..lo}.s32 }. .s32 d.hi may be less efficient on machines without hardware support for 24-bit multiply.b.0 Table 31.hi mode.PTX ISA Version 2.0> + c. Saturation modifier: . Applies only to . 48bits.MAXINT (no overflow). mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

January 24, 2010

71

PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

72

January 24, 2010

Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

January 24, 2010

73

Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. .b32 clz. a = a << 1. mask = 0x80000000. popc.0. } while (d < max && (a&mask == 0) ) { d++.b64 d. a.u32 Semantics 74 January 24. .b32. For . if (. 2010 . d = 0.b32 popc.type = { .b32 type. // cnt is . a. clz. clz requires sm_20 or later. For . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. X. popc requires sm_20 or later.PTX ISA Version 2. a. .type d. while (a != 0) { if (a&0x1) d++. } Introduced in PTX ISA version 2.type == .b64 type. X.b64 }. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. inclusively. mask = 0x8000000000000000. a = a >> 1.b64 }. popc Syntax Integer Arithmetic Instructions: popc Population count. a. } else { max = 64. clz. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. the number of leading zeros is between 0 and 32. d = 0. cnt.u32 PTX ISA Notes Target ISA Notes Examples Table 40. cnt. popc. // cnt is .0 Table 39. inclusively.type d.0.type = { .b64 d.b32) { max = 32.b32. the number of leading zeros is between 0 and 64. .

Operand a has the instruction type.u64. bfind requires sm_20 or later. and operand d has type . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. X. d = -1. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.type d.d.shiftamt && d != -1) { d = msb .u32 d. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.type==. // cnt is . i>=0. a. } } if (. For unsigned integers. .s32. bfind. d. break. bfind returns 0xFFFFFFFF if no non-sign bit is found. .s32) ? 31 : 63.type bfind.s64 cnt.u32 || .u32. If . For signed integers. 2010 75 .u32.shiftamt. a.type = { .shiftamt. a. Instruction Set Table 41. Semantics msb = (.0. .u32 January 24. i--) { if (a & (1<<i)) { d = i.Chapter 8.type==. bfind. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind.s64 }.shiftamt is specified. bfind returns the bit position of the most significant “1”. . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. for (i=msb.

a. i<=msb. for (i=0.0. brev requires sm_20 or later. 2010 .0 Table 42. brev. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. brev.b32 d. 76 January 24. a.b32) ? 31 : 63.b32.type d. msb = (. .PTX ISA Version 2. Description Semantics Perform bitwise reversal of input.type = { .b64 }. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. .type==. i++) { d[i] = a[msb-i].

type==.a. else sbit = a[min(pos+len-1.b32 d. if (.s32. bfe.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. otherwise If the bit field length is zero.len.u64 || len==0) sbit = 0.start. bfe requires sm_20 or later.u32.u32. January 24. pos = b.s32. and operands b and c are type . d = 0.u32 || . Semantics msb = (.type==. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. the destination d is filled with the replicated sign bit of the extracted field.u32 || .type==. bfe. The destination d is padded with the sign bit of the extracted field. 2010 77 . . Description Extract bit field from a and place the zero or sign-extended result in d.s32) ? 31 : 63. .type==. . for (i=0. . i<=msb.u64: .msb)]. If the start position is beyond the msb of the input.type = { . Source b gives the bit field starting bit position.Chapter 8. a. c.0. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Operands a and d have the same type as the instruction type. The sign bit of the extracted field is defined as: .u32. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u64. the result is zero.type d. .s64 }. Instruction Set Table 43. len = c. and source c gives the bit field length in bits. b.

78 January 24. d. 2010 . the result is b.b32.type = { . and place the result in f.0 Table 44. for (i=0. and f have the same type as the instruction type. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. .b64 }. Description Align and insert a bit field from a into b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0.b32 d.PTX ISA Version 2.a. a.type==. bfi. f = b. c. Source c gives the starting bit position for the insertion.b32) ? 31 : 63. and source d gives the bit field length in bits. bfi requires sm_20 or later. . i<len && pos+i<=msb.start. i++) { f[pos+i] = a[i].len. bfi. If the start position is beyond the msb of the input.type f. Semantics msb = (.b. pos = c. b. b. Operands a. and operands c and d are type . the result is b. len = d.u32. If the bit field length is zero.

b2 source select c[11:8] d. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). . the permute control consists of four 4-bit selection values. msb=1 means replicate the sign. The bytes in the two source registers are numbered from 0 to 7: {b.rc8. a. Note that the sign extension is only performed as part of generic form. In the generic form (no mode specified). c. b0}}. as a 16b permute code.mode = { . The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b2. b5. b4}. and reassemble them into a 32-bit destination register. a 4-bit selection value is defined. default mode index d. Thus. The msb defines if the byte value should be copied.f4e. the four 4-bit values fully specify an arbitrary byte permute. {b3. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.b1 source select c[7:4] d. . 2010 79 . Description Pick four arbitrary bytes from two 32-bit registers. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. b6.b3 source select c[15:12] d.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. .rc16 }. msb=0 means copy the literal value.b4e. Instruction Set Table 45. For each byte in the target register. b. b1.Chapter 8.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.ecl.b32{.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. .mode} d.ecr. prmt. . . a} = {{b7.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp[15:08] = ReadByte( mode. tmp[23:16] = ReadByte( mode. r1.0 Semantics tmp64 = (b<<32) | a.PTX ISA Version 2.f4e r1. tmp64 ).0. } tmp[07:00] = ReadByte( mode. ctl[1] = (c >> 4) & 0xf. prmt. ctl[0]. tmp64 ). r2. prmt requires sm_20 or later. 2010 . ctl[2] = (c >> 8) & 0xf. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ). r4. 80 January 24. r4. ctl[3] = (c >> 12) & 0xf. ctl[2]. ctl[3]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r2.b32 prmt. r3.b32. r3. tmp64 ). ctl[1]. tmp[31:24] = ReadByte( mode.

Chapter 8.f64 register operands and constant immediate values.2. Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on . 2010 81 .f32 and .7. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.

1.mul}. 2010 .min.sqrt}.rnd. NaN payloads are supported for double-precision instructions.sub.f32 {div.approx.f32 {div.max}.f64 div.fma}.rnd.target sm_20 .f64 are the same.approx.rn and instructions may be folded into a multiply-add.f64 and fma.rcp. Table 46. Double-precision instructions support subnormal inputs and results.ex2}. but single-precision instructions return an unspecified NaN. Single-precision add.rcp.full.f64 rsqrt.rm .approx.0].32 and fma.approx.mul}.neg.f32 {abs.sqrt}.f32 {add.rnd.rp .rnd. with NaNs being flushed to positive zero.lg2.rcp. The optional .f64 {sin.cos.rn and instructions may be folded into a multiply-add. mul.sat Notes If no rounding modifier is specified.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {mad.0 The following table summarizes floating-point instructions in PTX.rnd. {mad.f64 {abs. .target sm_20 mad.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 rsqrt. 82 January 24. default is .fma}.neg. Instruction Summary of Floating-Point Instructions .ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. so PTX programs should not rely on the specific single-precision NaNs being generated.f32 {div. . If no rounding modifier is specified.target sm_1x No rounding modifier.PTX ISA Version 2.rz . default is .rnd.f32 . {add. and mad support saturation of results to the range [0.f32 are the same.sqrt}. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.max}.ftz .min.rn . No rounding modifier. Note that future implementations may support NaN payloads for single-precision instructions.sub.0.f64 mad. sub.

op p. b.infinite. Introduced in PTX ISA version 2. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.infinite testp. copysign requires sm_20 or later. C.type .f32. . . 2010 83 . .0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. testp. January 24.normal testp. true if the input is a subnormal number (not NaN.finite.subnormal }. . p. a.finite testp. . . f0. testp requires sm_20 or later. A. Instruction Set Table 47. z. not infinity).f64 x. // result is .number. copysign. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. a. testp.f64 }.type = { . testp.type = { . y.notanumber. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. positive and negative zero are considered normal numbers. and return the result as d.f64 isnan.f32. .infinite. testp Syntax Floating-Point Instructions: testp Test floating-point property. B. .notanumber testp.0.type d.normal.f32 testp.Chapter 8.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.op. .pred = { . Table 48.number testp.f32 copysign. copysign.notanumber. not infinity) As a special case. X.f64 }.

subnormal numbers are supported. . add.f32.sat. requires sm_20 Examples @p add.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_13 for add.rn. .0.ftz}{.f2. add{. . d = a + b. NaN results are flushed to +0.rnd}{.f64 requires sm_13 or later.sat}. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rz.f3. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 add{. 84 January 24.rn): . b. . d.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0.f32 f1. b. Description Semantics Notes Performs addition and writes the resulting value into a destination register. sm_1x: add.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64. add.0 Table 49. 1.rz.f32 supported on all target architectures.rm mantissa LSB rounds towards negative infinity . Rounding modifiers (default is .rnd = { .0f.rm.rp }. . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. Rounding modifiers have the following target requirements: . add Syntax Floating-Point Instructions: add Add two values. add. Saturation modifier: .ftz. a.rp for add.rz available for all targets .rnd}.f64 d.rm. a.0. add. .rn.f64 supports subnormal numbers. 2010 .rn mantissa LSB rounds to nearest even .rz mantissa LSB rounds towards zero . In particular.0]. add.

rnd = { .0. sub. Saturation modifier: sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another.rnd}. Instruction Set Table 50. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rn. 2010 85 .rn.f3.f64 supports subnormal numbers.rm. subnormal numbers are supported.f64. .ftz.a.f32 clamps the result to [0.rz available for all targets . 1.f64 requires sm_13 or later.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub. . In particular.rn): .sat. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.b. requires sm_20 Examples sub.f2.0.f32 supported on all target architectures.ftz}{.Chapter 8. sub.f32 flushes subnormal inputs and results to sign-preserving zero.rz mantissa LSB rounds towards zero .rn. .rm mantissa LSB rounds towards negative infinity . sub.rz.ftz. d = a .rp for sub.f32. d. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. Rounding modifiers have the following target requirements: .f32 flushes subnormal inputs and results to sign-preserving zero. January 24. a. sub.f64 d.sat}. b.b. .f32 sub{. NaN results are flushed to +0.0f.rnd}{.rm. Rounding modifiers (default is .rp }. sm_1x: sub. a.0].rn mantissa LSB rounds to nearest even . b. sub{.f32 c. . . requires sm_13 for sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 f1.

f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. . b.ftz}{.rz available for all targets .pi // a single-precision multiply 86 January 24.f32 circumf.ftz. d = a * b.radius.rm. a. .rn. mul. subnormal numbers are supported.0]. .f64 d.0. mul{. . requires sm_13 for mul.f64.rnd = { .0f.rm mantissa LSB rounds towards negative infinity . Rounding modifiers have the following target requirements: . In particular.sat}. NaN results are flushed to +0. mul. sm_1x: mul.rm. d.f32 clamps the result to [0. .PTX ISA Version 2.0 Table 51. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. mul. Rounding modifiers (default is .f32 mul{.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later. Description Semantics Notes Compute the product of two values.rz mantissa LSB rounds towards zero . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rp for mul.f32.0.rn): .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz. b.rnd}{. mul.ftz. For floating-point multiplication.rn mantissa LSB rounds to nearest even .sat. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Saturation modifier: mul. a. . 1. all operands must be the same size.rnd}.rn. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 supported on all target architectures. requires sm_20 Examples mul. 2010 . mul Syntax Floating-Point Instructions: mul Multiply two values.rp }.

ftz}{. a. fma.f32 clamps the result to [0. c.c. 1. . again in infinite precision.f64 d.rnd.f32 is unimplemented in sm_1x.0.rn. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. fma.sat}. fma. @p fma. again in infinite precision.0. .ftz.4. fma.f64 w.rnd{.f32 fma.rp }.rz. fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 2010 87 . b.rnd = { .f32 computes the product of a and b to infinite precision and then adds c to this product.ftz.b. fma. a. d. Instruction Set Table 52. b. Rounding modifiers (no default): .f64 computes the product of a and b to infinite precision and then adds c to this product.f64 requires sm_13 or later.rn.f64 is the same as mad. . fma Syntax Floating-Point Instructions: fma Fused multiply-add.rnd. fma.f64 supports subnormal numbers.rm mantissa LSB rounds towards negative infinity . PTX ISA Notes Target ISA Notes Examples January 24.x. Saturation: fma.z.f64.a. fma. fma.y.rn.f32 introduced in PTX ISA version 2. subnormal numbers are supported. d = a*b + c.rnd. sm_1x: fma. d.f32 requires sm_20 or later.rn mantissa LSB rounds to nearest even .0].Chapter 8.0f. The resulting value is then rounded to single precision using the rounding mode specified by . .rm.f32 fma.f32 flushes subnormal inputs and results to sign-preserving zero. fma. c. NaN results are flushed to +0.sat.f64 introduced in PTX ISA version 1. The resulting value is then rounded to double precision using the rounding mode specified by .rz mantissa LSB rounds towards zero .

again in infinite precision.target sm_1x d..e. c. The exception for mad.f32 flushes subnormal inputs and results to sign-preserving zero. mad. the treatment of subnormal inputs and output follows IEEE 754 standard.{f32. mad{.f32 computes the product of a and b at double precision. a. mad.sat. .0].rnd{. a. b. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.rm. // .target sm_13 and later . 1.f64.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.rn.rn.target sm_20 d.f32 mad.rz.rnd.ftz.f32 is identical to the result computed using separate mul and add instructions. Description Semantics Notes Multiplies two values and adds a third. subnormal numbers are supported.0. Note that this is different from computing the product with mul. For . The resulting value is then rounded to single precision using the rounding mode specified by . mad.0 devices. 2010 .sat}. When JIT-compiled for SM 2.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 mad. NaN results are flushed to +0. c. b. mad. In this case.rz mantissa LSB rounds towards zero .ftz}{. fma.f32 clamps the result to [0. The resulting value is then rounded to double precision using the rounding mode specified by .target sm_20: mad. mad.f64}. // . // .f32 is when c = +/-0. mad. Saturation modifier: mad.rnd = { .ftz}{.sat}. sm_1x: mad.0.rp }. .f32.{f32.0f. a.rnd.f64 supports subnormal numbers.rnd. . and then the mantissa is truncated to 23 bits.f64 is the same as fma.rm mantissa LSB rounds towards negative infinity .f64 computes the product of a and b to infinite precision and then adds c to this product.ftz. where the mantissa can be rounded and the exponent will be clamped.0 Table 53. again in infinite precision. but the exponent is preserved. c. mad. and then writes the resulting value into a destination register.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 is implemented as a fused multiply-add (i. For . mad. Unlike mad.f32 flushes subnormal inputs and results to sign-preserving zero.rn mantissa LSB rounds to nearest even .rnd.f32).PTX ISA Version 2. d = a*b + c. The resulting value is then rounded to double precision using the rounding mode specified by .f64 computes the product of a and b to infinite precision and then adds c to this product. again in infinite precision. 88 January 24. Rounding modifiers (no default): . mad. b.f64} is the same as fma.f64 d.target sm_1x: mad.

f64. requires sm_13 .4 and later.rn.0.rm.. a rounding modifier is required for mad.rm. January 24.0 and later.f64 instructions having no rounding modifier will map to mad. Rounding modifiers have the following target requirements: .rn.b..rp for mad.a.f32 supported on all target architectures.rz...f64.rn.c.f32 for sm_20 targets. requires sm_20 Examples @p mad.f64.rz. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. mad.f64 requires sm_13 or later. Legacy mad..rp for mad. In PTX ISA versions 1.Chapter 8. Target ISA Notes mad. 2010 89 . a rounding modifier is required for mad.. In PTX ISA versions 2.f32.f32 d.

f32 div.3. .f32 and div.ftz.f64 defaults to div. div.full.f32 div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. xd.f64 introduced in PTX ISA version 1.f32 requires sm_20 or later.ftz.approx. a. y. d.rp}. Explicit modifiers .f32 implements a relatively fast. div. // // // // fast. approximate single-precision divides: div.f32 flushes subnormal inputs and results to sign-preserving zero.f32 div. b. yd.full{. PTX ISA Notes div. or . b.rm. The maximum ulp error is 2 across the full range of inputs. .f32 implements a fast approximation to divide. d.approx{.ftz}. Target ISA Notes div. a. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . div. Subnormal inputs and results are flushed to sign-preserving zero.PTX ISA Version 2.f64 diam.ftz.approx.rn mantissa LSB rounds to nearest even .f32 supported on all target architectures. but is not fully IEEE 754 compliant and does not support rounding modifiers.ftz}.0 Table 54. 2010 . the maximum ulp error is 2.rz mantissa LSB rounds towards zero .approx.rz. and rounding introduced in PTX ISA version 1.3. d.approx.f32 defaults to div. b.f64.ftz}. a.circum. div. For b in [2-126.f64 supports subnormal numbers. x. zd. and div.rn.f32 div. computed as d = a * (1/b).rn.rn. approximate division by zero creates a value of infinity (with same sign as a). sm_1x: div.full. b.f32 flushes subnormal inputs and results to sign-preserving zero.f32 and div. one of .rn.4 and later. div. . . full-range approximation that scales operands to achieve better accuracy. d = a / b.f64 d. . . subnormal numbers are supported.0. Description Semantics Notes Divides a by b. stores result in d.0 through 1. div Syntax Floating-Point Instructions: div Divide one value by another.rnd. Fast.approx.f64 requires sm_13 or later. 2126].rnd is required.full. div.4.{rz. div. Fast.ftz. div.rp }. div. For PTX ISA version 1. a.rnd.f64 requires sm_20 or later.full.full.rm mantissa LSB rounds towards negative infinity .f32 div.f32.14159.approx.rnd = { . Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .rm.rnd{. Examples 90 January 24. For PTX ISA versions 1.ftz. z.

f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. d = |a|. sm_1x: abs. a. abs. a.f0. NaN inputs yield an unspecified NaN.0.ftz.f32 x. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Negate the sign of a and store the result in d. neg{. NaN inputs yield an unspecified NaN.ftz. neg.f32 abs. subnormal numbers are supported. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. abs{. d = -a.Chapter 8.f32 supported on all target architectures. a. a.f32 supported on all target architectures.ftz}. abs. subnormal numbers are supported. d. neg. abs. Subnormal numbers: sm_20: By default.f64 d. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f0. Subnormal numbers: sm_20: By default.ftz. neg. January 24. Instruction Set Table 55.f32 flushes subnormal inputs and results to sign-preserving zero. Take the absolute value of a and store the result in d. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.ftz. neg. sm_1x: neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later.0.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. Table 56. abs.f32 x. abs.f32 neg. 2010 91 . d.f64 requires sm_13 or later.

max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. d. a.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 .ftz.b. Store the maximum of a and b in d. subnormal numbers are supported. subnormal numbers are supported.b. min.ftz}.f2.c. Store the minimum of a and b in d.0. a. b. max{. b. (a > b) ? a : b.c. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. max. a.f1.f32 max.ftz. sm_1x: max. min. sm_1x: min. d.f32 flushes subnormal inputs and results to sign-preserving zero. Table 58.f64 supports subnormal numbers.f64 supports subnormal numbers.f64 d.f32 min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. min{.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. 92 January 24. max.f32 max. a.f64 requires sm_13 or later.0.f32 min. min.ftz}. (a < b) ? a : b. d d d d = = = = NaN.f64 f0.f64 d. @p min.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later. max.ftz. a. d d d d = = = = NaN.PTX ISA Version 2. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.z.x. b.0 Table 57. max. min.f32 supported on all target architectures. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b.ftz. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. a. b.f64 z. b.

rn.f32 rcp. For PTX ISA versions 1.rz. rcp.f32 and rcp.0. rcp.f64 requires sm_13 or later. Target ISA Notes rcp.approx.f64 and explicit modifiers .approx.0 -Inf -Inf +Inf +Inf +0. PTX ISA Notes rcp.rn. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.approx or .ftz.r.0 through 1.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rnd. rcp. General rounding modifiers were added in PTX ISA version 2. 2010 93 .ftz}.f64.f64 d.rnd{.Chapter 8. Instruction Set Table 59.3.rp }.rn. Input -Inf -subnormal -0. The maximum absolute error is 2-23.0.ftz.rm. sm_1x: rcp.rnd.f32.approx and .0 over the range 1.f32 defaults to rcp. rcp. . rcp.0-2.f32 requires sm_20 or later.4.f64 defaults to rcp.rm mantissa LSB rounds towards negative infinity . d. rcp. For PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f64 introduced in PTX ISA version 1.ftz.rnd = { .f64 ri. Description Semantics Notes Compute 1/a.f32 supported on all target architectures.rn mantissa LSB rounds to nearest even . a. rcp.rz mantissa LSB rounds towards zero . xi. a. rcp.f32 rcp.ftz}.f64 requires sm_20 or later. rcp.f32 implements a fast approximation to reciprocal. Examples January 24.approx.f32 rcp.rn. one of . d.rn. a.4 and later.x.rm. .0. store result in d.ftz.approx.0 +subnormal +Inf NaN Result -0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. rcp.ftz were introduced in PTX ISA version 1.{rz.0 +0. .f64 supports subnormal numbers.approx{. and rcp. subnormal numbers are supported.f32 rcp.f32 flushes subnormal inputs and results to sign-preserving zero. d = 1 / a. // fast.rp}.rnd is required. xi.rn.x.

0 +subnormal +Inf NaN Result NaN NaN -0.rn.x. sqrt.rp}.approx.f64 r.f32 flushes subnormal inputs and results to sign-preserving zero. and sqrt. a.x.0 +0. Target ISA Notes sqrt.rn.rnd{.rm.ftz}. sqrt. The maximum absolute error for sqrt. For PTX ISA version 1.0 +0.rz. a. r.rp }. 2010 .f32 sqrt. sm_1x: sqrt.rnd = { .f64. // IEEE 754 compliant rounding d.rz mantissa LSB rounds towards zero .f64 defaults to sqrt.f64 and explicit modifiers .f64 d.approx.f32.0. sqrt. sqrt.4.rnd. sqrt. Input -Inf -normal -subnormal -0.rn mantissa LSB rounds to nearest even .0. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f32 flushes subnormal inputs and results to sign-preserving zero. d = sqrt(a).0 through 1.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .{rz.f32 is TBD.4 and later.ftz were introduced in PTX ISA version 1.ftz}.approx.x. r. PTX ISA Notes sqrt.f64 supports subnormal numbers.ftz. approximate square root d.3. General rounding modifiers were added in PTX ISA version 2.rnd is required.approx.rm mantissa LSB rounds towards negative infinity . subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm.f32 sqrt. .rnd. // fast.ftz.approx or .approx and .f32 sqrt.ftz. sqrt. For PTX ISA versions 1.ftz. . sqrt.PTX ISA Version 2. // IEEE 754 compliant rounding . store in d.approx.0 -0.f32 defaults to sqrt. Examples 94 January 24.0 +0. Description Semantics Notes Compute sqrt(a).0 Table 60.f64 requires sm_20 or later.approx{. sqrt.rn.rn.f64 requires sm_13 or later.rn. sqrt.f32 and sqrt. one of .rn.f32 requires sm_20 or later.f32 sqrt.f32 implements a fast approximation to square root. sqrt. a.f64 introduced in PTX ISA version 1.f32 supported on all target architectures. .

Instruction Set Table 61. January 24. rsqrt. a.4 and later. Explicit modifiers . x. 2010 95 . sm_1x: rsqrt. rsqrt.f64 supports subnormal numbers.ftz.approx implements an approximation to the reciprocal square root. Compute 1/sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero.approx and .0 +0.approx. the . For PTX ISA versions 1.ftz}.0-4.approx. PTX ISA Notes rsqrt. subnormal numbers are supported.approx. X. For PTX ISA version 1.ftz.0.f32 supported on all target architectures. Target ISA Notes Examples rsqrt.f32 rsqrt. ISR. a. store the result in d.f32 flushes subnormal inputs and results to sign-preserving zero.0. The maximum absolute error for rsqrt. d = 1/sqrt(a).f64 were introduced in PTX ISA version 1.4 over the range 1.0 NaN The maximum absolute error for rsqrt.f32.approx.f64 is emulated in software and are relatively slow.f64 d.approx. Subnormal numbers: sm_20: By default.f32 and rsqrt.f32 rsqrt. d.approx.approx{.3. and rsqrt. rsqrt. Input -Inf -normal -subnormal -0.f32 is 2-22.ftz were introduced in PTX ISA version 1. rsqrt.0 through 1.4.f64.f64 requires sm_13 or later.f64 defaults to rsqrt.approx modifier is required.f64 is TBD.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt.Chapter 8. rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f64 isr. rsqrt. Note that rsqrt.f32 defaults to rsqrt.ftz.

0 +0. subnormal numbers are supported.f32 d. sin.ftz introduced in PTX ISA version 1.4 and later.approx{. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx.0 Table 62. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz.0 NaN NaN The maximum absolute error is 2-20.0 +0. For PTX ISA version 1. sin. sin.0.approx modifier is required.PTX ISA Version 2. 2010 .f32 sa. Explicit modifiers . For PTX ISA versions 1. a.0 -0. PTX ISA Notes sin.approx.9 in quadrant 00. sin. 96 January 24.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.0 +0. the .0 +subnormal +Inf NaN Result NaN -0. sin.ftz. a. Find the sine of the angle a (in radians).ftz.0 through 1.3. Input -Inf -subnormal -0.4.f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default.f32 defaults to sin. d = sin(a).approx and . Target ISA Notes Examples Supported on all target architectures.f32 implements a fast approximation to sine.approx.f32.

ftz. 2010 97 . d = cos(a).0 +1.Chapter 8.9 in quadrant 00.approx. For PTX ISA versions 1. January 24.f32 implements a fast approximation to cosine.ftz introduced in PTX ISA version 1.f32 d.4 and later.0.approx modifier is required.approx and . Subnormal numbers: sm_20: By default.f32 introduced in PTX ISA version 1. cos. Instruction Set Table 63. cos. Explicit modifiers .f32 ca. cos. cos.0 NaN NaN The maximum absolute error is 2-20.approx{.0 +1. the . cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.4.0 +1.approx.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1. a. PTX ISA Notes cos.ftz. For PTX ISA version 1.f32.0 +subnormal +Inf NaN Result NaN +1.f32 defaults to cos.3. cos. Find the cosine of the angle a (in radians).approx. a. Target ISA Notes Examples Supported on all target architectures.ftz}. Input -Inf -subnormal -0. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +0. subnormal numbers are supported.

d = log(a) / log(2).0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. lg2. lg2. The maximum absolute error is 2-22.approx. 98 January 24.ftz introduced in PTX ISA version 1.0 Table 64. For PTX ISA versions 1.f32.f32 la. the .f32 Determine the log2 of a.0 through 1.approx.approx and . subnormal numbers are supported. For PTX ISA version 1.4.PTX ISA Version 2. Input -Inf -subnormal -0. lg2.f32 implements a fast approximation to log2(a). PTX ISA Notes lg2. lg2. 2010 .6 for mantissa.f32 defaults to lg2. lg2.f32 introduced in PTX ISA version 1.approx modifier is required.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers . sm_1x: Subnormal inputs and results to sign-preserving zero.ftz}. Target ISA Notes Examples Supported on all target architectures.0 +0. a.0.ftz. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. Subnormal numbers: sm_20: By default.ftz.approx{.4 and later.approx. a.3.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

January 24, 2010

99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

January 24, 2010

Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

January 24, 2010

101

ftz}. {!}c. lo.s16.u32 p|q.CmpOp{. For unsigned values. and (optionally) combine this result with a predicate value by applying a Boolean operator. ltu. A related value computed using the complement of the compare result is written to the second destination operand.f32. . gtu. lt.b16.ftz applies only to . lt. then these comparisons have the same result as their ordered counterparts. .f64 }. lt. setp. p = BoolOp(t. . Semantics t = (a CmpOp b) ? 1 : 0. p[|q]. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.pred variables.lt. ge. p[|q]. respectively. and hs for lower.u16. Subnormal numbers: sm_20: By default. p. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. bit-size comparisons are eq and ne. nan The Boolean operator BoolOp(A.type .u32. hs equ. ge.f64 supports subnormal numbers.ftz}.i. geu.a.type setp.f32 comparisons. The destinations p and q must be . Modifier . ls. or.dtype.s32 setp. subnormal numbers are supported.f32 flushes subnormal inputs to sign-preserving zero. le. . higher. 102 January 24. neu.type = { . gt. gt.0. setp.CmpOp.ftz. q = BoolOp(!t. . c). leu. hi. hi. ge. geu. setp. . c). and can be one of: eq. . The comparison operator is a suffix on the instruction.b32. the result is false.and.b. b. ls. num returns true if both operands are numeric values (not NaN). setp with . Integer Notes Floating Point Notes The ordered comparisons are eq. then the result of these comparisons is true. le. @q setp. le.f64 source type requires sm_13 or later.s32. gtu. . gt.u64. ne. the comparison operators lo. neu.r. Applies to all numeric types.eq. gt. and nan returns true if either operand is NaN. and higher-or-same may be used instead of lt.0 Table 67. To aid comparison operations in the presence of NaN values. unordered versions are included: equ. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. le.BoolOp{.dtype. If either operand is NaN. sm_1x: setp.f32 flushes subnormal inputs to sign-preserving zero. The signed and unsigned comparison operators are eq. ltu. This result is written to the first destination operand.n. a. If both operands are numeric values (not NaN). loweror-same. num. The untyped.b64. leu. a. ne. b. ge. 2010 .PTX ISA Version 2.dtype. If either operand is NaN.s64.B) is one of: and. xor. ne. .

u64. Modifier .f64 requires sm_13 or later. slct. slct. b. .dtype = { . .dtype. Introduced in PTX ISA version 1. and operand a is selected.dtype. Description Conditional selection. C. . . .u32. Semantics Floating Point Notes January 24. If c is True.b64.xp.dtype.f32 comparisons. .s32 x.f32. c. the comparison is unordered and operand b is selected. Operands d. Operands d. d. a is stored in d. and b must be of the same type.b16. slct. . fval.u16. For .g. Table 69. @q selp. c. 2010 103 . c.f32 A. .ftz. selp Syntax Comparison and Selection Instructions: selp Select between source operands. a.u16.x. .s64. otherwise b is stored in d.0. Operand c is a predicate. selp.f32.s16. . .u64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.f32 d.b32. y. B. . . based on the sign of the third operand. d = (c >= 0) ? a : b. operand c must match the second instruction type.ftz}.f32 flushes subnormal values of operand c to sign-preserving zero.s32 slct{. . Instruction Set Table 68. a. selp. val.dtype. .t.0. Subnormal numbers: sm_20: By default.s16. negative zero equals zero. .f32 r0.s32.f64 requires sm_13 or later. subnormal numbers are supported. and b are treated as a bitsize type of the same width as the first instruction type.s32 selp. f0.f32 flushes subnormal values of operand c to sign-preserving zero.b16.Chapter 8.s32. slct.ftz applies only to . The selected input is copied to the output without modification.b32. .u64. slct Syntax Comparison and Selection Instructions: slct Select one source operand. b.type = { . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. b otherwise.f64 }.r.type d.u32. .f64 }. z.ftz. d = (c == 1) ? a : b.b64. . based on the value of the predicate source operand.f32 comparisons.p. b. a.s64. sm_1x: slct. If operand c is NaN.u32. If c ≥ 0. slct. a is stored in d. and operand a is selected. . . a. .

7. or.PTX ISA Version 2. Instructions and.0 8. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. This permits bit-wise operations on floating point values without having to define a union to access the bits. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. and not also operate on predicates.4. provided the operands are of the same size. xor. performing bit-wise operations on operands of any type.

and. Supported on all target architectures.pred. Introduced in PTX ISA version 1.r.type = { .b64 }.b32.type d.b32 x. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b16.q. a.b32 mask mask. d = a | b.q. and Syntax Logic and Shift Instructions: and Bitwise AND. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. b.0x80000000.Chapter 8. . The size of the operands must match. . Instruction Set Table 70.b16. or Syntax Logic and Shift Instructions: or Bitwise OR. but not necessarily the type.pred p.type d.b32. Supported on all target architectures.0. and. The size of the operands must match. or.r. . 2010 105 .0. . .fpvalue.b32 and.type = { . sign. or. . . Allowed types include predicate registers. . January 24.b64 }. a. Introduced in PTX ISA version 1.0x00010001 or. but not necessarily the type. Table 71. b.pred. d = a & b.

Supported on all target architectures.b16.mask. . not.PTX ISA Version 2.type d.0x0001. Introduced in PTX ISA version 1. Table 73. a.b32. Table 74. .b32 mask. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. d = a ^ b.b32 d. but not necessarily the type.pred.b32. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b64 }. . xor.type = { .a.0 Table 72. d. a. . cnot.r. but not necessarily the type. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Supported on all target architectures. one’s complement.0. . d = ~a.0. 106 January 24. . but not necessarily the type.type d. Introduced in PTX ISA version 1.pred p. d = (a==0) ? 1 : 0. . Introduced in PTX ISA version 1.b16.b32 xor.type = { .q.b32. b. The size of the operands must match.b64 }. cnot. The size of the operands must match. a.pred. .b16.b64 }. not. .0. Allowed types include predicates. not.q.x. xor. Supported on all target architectures. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.type d.b16 d. 2010 . not Syntax Logic and Shift Instructions: not Bitwise negation. The size of the operands must match.type = { . .

Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.j.b32.type = { . but not necessarily the type. regardless of the instruction type. a.u32. unsigned and untyped shifts fill with 0. Shift amounts greater than the register width N are clamped to N.s64 }.s16. Instruction Set Table 75.b64 }. .Chapter 8. shr. .i.a. PTX ISA Notes Target ISA Notes Examples Table 76. shl Syntax Logic and Shift Instructions: shl Shift bits left. The sizes of the destination and first source operand must match. . zero-fill on right.2. b.u16. .b32 q.type d. regardless of the instruction type.0.s32 shr. Signed shifts fill with the sign bit. d = a << b. d = a >> b. PTX ISA Notes Target ISA Notes Examples January 24. b. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. . shr Syntax Logic and Shift Instructions: shr Shift bits right. .2. .type = { . .s32.b64.u64. shl. i.u16 shr.b16. The b operand must be a 32-bit value. Shift amounts greater than the register width N are clamped to N.i. a. sign or zero fill on left.type d. 2010 107 . but not necessarily the type.a.b32. The b operand must be a 32-bit value. shr. Bit-size types are included for symmetry with SHL. shl.b16 c. . Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. . .b16.0. Supported on all target architectures. Supported on all target architectures. k.1. . The sizes of the destination and first source operand must match.

PTX ISA Version 2. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. local. st. The cvta instruction converts addresses between generic and global. mov. Data Movement and Conversion Instructions These instructions copy data from place to place.5. or shared state spaces. ldu. and sust support optional cache operations. possibly converting it from one format to another. prefetchu isspacep cvta cvt 108 January 24. and st operate on both scalar and vector types. 2010 .0 8.7. suld. Instructions ld. ld. and from state space to state space. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.

7. fetch again).cg to cache loads only globally. to allow the thread program to poll a SysMem location written by the CPU. The default load instruction cache operation is ld. evict-first. it performs the ld. If one thread stores to global memory via one L1 cache. The ld. any existing cache lines that match the requested address in L1 will be evicted. bypassing the L1 cache.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.5. Table 77. When ld. when applied to a local address. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Cache Operators PTX 2. but multiple L1 caches are not coherent for global data.cs.ca. January 24.1. the second thread may get stale L1 cache data. The cache operators require a target architecture of sm_20 or later.ca loads cached in L1. A ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.0 introduces optional cache operators on load and store instructions.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. if the line is fully covered. For sm_20 and later. Operator . . The ld.Chapter 8.cv to a frame buffer DRAM address is the same as ld.cg Cache at global level (cache in L2 and below.cv Cache as volatile (consider cached system memory lines stale. likely to be accessed again.ca. Use ld.lu Last use.lu instruction performs a load cached streaming operation (ld. . invalidates (discards) the local L1 line following the load. As a result of this request. rather than the data stored by the first thread. . Global data is coherent at the L2 level. and cache only in the L2 cache. 2010 109 .lu operation. . the cache operators have the following definitions and behavior.cs is applied to a Local window address.cs) on global addresses.lu load last use operation. Instruction Set 8. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. likely to be accessed once. not L1). The ld. and a second thread loads that address via a second L1 cache with ld. The ld. The compiler / programmer may use ld.cs Cache streaming.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.

bypassing the L1 cache. st. . Operator .cg is the same as st.0 Table 78.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. likely to be accessed once.wt Cache write-through (to system memory).wb. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wb could write-back global store data from L1.cg to local memory uses the L1 cache.ca loads. 110 January 24. The st. . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wt. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. and marks local L1 lines evict-first. and cache only in the L2 cache. 2010 . .wb for global data. not L1).wt store write-through operation applied to a global System Memory address writes through the L2 cache.cs Cache streaming. and a second thread in a different SM later loads from that address via a different L1 cache with ld. regardless of the cache operation.ca. The default store instruction cache operation is st.cg to cache global store data only globally. the second thread may get a hit on stale L1 cache data. Global stores bypass L1. which writes back cache lines of coherent cache levels with normal eviction policy. Future GPUs may have globally-coherent L1 caches.PTX ISA Version 2. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. Use st. and discard any L1 lines that match.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. If one thread stores to global memory. to allow a CPU program to poll a SysMem location written by the GPU with st. but st. bypassing its L1 cache.cg Cache at global level (cache in L2 and below. The st. In sm_20. in which case st. rather than get the data from L2 or memory stored by the first thread. Addresses not in System Memory use normal write-back. However.

Description .type mov. Note that if the address of a device function parameter is moved to a register. the address of the variable in its state space) into the destination register.global. d = &label. u. mov. .type mov. A.s32. special register. . the generic address of a variable declared in global. . label.0.u16. sreg..type d. local. .pred.0. or function name.1. alternately. ptr. the parameter will be copied onto the stack and the address will be in the local state space. .f32 mov. a. or shared state space.u64. .s64. Take the non-generic address of a variable in global. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. mov. or shared state space may be taken directly using the cvta instruction. . immediate. label.type mov.v. k. // address is non-generic. myFunc. variable in an addressable memory space. d = &avar. mov places the non-generic address of the variable (i.b32. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. .b16..const. Semantics d = a. For variables declared in . avar. Write register d with the value of a. . 2010 111 .f32.u32 mov.u32 mov. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. . d. Instruction Set Table 79.u16 mov. d. .a.e. A[5]. // get address of variable // get address of label or function .f64 }. The generic address of a variable in global. d = sreg. i.e.shared state spaces. mov.type = { . Operand a may be a register. addr.local. within the variable’s declared state space Notes Although only predicate and bit-size types are required. ptr.f32 mov. local. Introduced in PTX ISA version 1. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.b64. local. d.s16. and . .Chapter 8.f64 requires sm_13 or later.u32.u32 d.

d.x | (a...23].x.31] } // unpack 16-bit elements from . // // // // a. mov.15]..y.u32 x.x.b64 { d. d..z.31].w << 48) d = a. d.y << 8) | (a. {lo.{x. a[16.a}.%r1.w } = { a[0. a[24.y << 8) d = a.. a[16.g. a[48.b32 // pack four 16-bit elements into .x | (a.b64 // pack two 32-bit elements into .b16 { d.b64 mov.PTX ISA Version 2.x.y << 16) | (a. a[16.z << 16) | (a... Both the overall size of the vector and the size of the scalar must match the size of the instruction type. Supported on all target architectures.x | (a.. a[32.0.b32 mov.b. d. 2010 .y } = { a[0.x.b64 }.b64 112 January 24. Semantics d = a. a[32.. d.y. For bit-size types. lo. a[8.15].b16 // pack four 8-bit elements into . Description Write scalar register d with the packed value of vector register a.x | (a..w } = { a[0.b}.b.b have type .b32 %r1.z.z.b32. . d.7].type d. %r1.31] } // unpack 8-bit elements from .y.{a.. d.b32 { d.x. mov.hi}..63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.15] } // unpack 8-bit elements from .0 Table 80. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.u16 %x is a double. {r.15].z. a.w have type .w << 24) d = a. d.b16. . %x.a have type ..31]. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b32 mov.type = { .b32 // pack two 16-bit elements into .x | (a.z << 32) | (a.u8 // unpack 32-bit elements from .47].b8 r.y } = { a[0.w}.y } = { a[0.7].b32 { d..g. a[8.b64 { d.y. or write vector register d with the unpacked values from scalar register a. .y << 16) d = a.hi are .y << 32) // pack two 8-bit elements into . d.63] } // unpack 16-bit elements from .

cop = { . Description Load register variable d from the location specified by the source address operand a in specified state space. . i. . .volatile. The address size may be either 32-bit or 64-bit. Semantics d d d d = = = = a.vec.cg. and truncated if the register width exceeds the state space address width for the target architecture. Instruction Set Table 81.ca. [a]. The value loaded is sign-extended to the destination register width for signed integers.global.param.lu. an integer or bit-size type register reg containing a byte address.volatile introduced in PTX ISA version 1.type ld{.1. .cs.const space suffix may have an optional bank number to indicate constant banks other than bank zero. If no state space is given. PTX ISA Notes January 24.u64.Chapter 8. [a].s64.shared spaces to inhibit optimization of references to volatile memory. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. and is zeroextended to the destination register width for unsigned and bit-size types.f16 data may be loaded using ld.ss = { . ld. . . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. . ld. 2010 113 . ld{. d.cv }.b8.global and . The address must be naturally aligned to a multiple of the access size. . .volatile{.e. . . ld introduced in PTX ISA version 1. an address maps to the corresponding location in local or shared memory. 32-bit). The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .type .type d.ss}{.e.f64 using cvt.volatile. This may be used. . Addresses are zero-extended to the specified width as needed. If an address is not properly aligned.f64 }.ss}{. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . The . and then converted to . d. . A destination register wider than the specified type may be used.b16.f32 or . .vec.u8. an address maps to global memory unless it falls within the local memory window or the shared memory window. .shared }.cop}. . .v2. . or [immAddr] an immediate absolute byte address (unsigned.u32. . Generic addressing and cache operations introduced in PTX ISA 2. In generic addressing.volatile may be used with . to enforce sequential consistency between threads accessing shared memory.b64. perform the load using generic addressing. .cop}. .ss}. i. *(a+immOff).f32.type ld. .u16.local.v4 }. .b16. 32-bit). ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. the access may proceed by silently masking off low-order address bits to achieve proper rounding. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . for example.type = { . Within these windows. d.volatile{.s8.0. .b32. [a].const. Cache operations are not permitted with ld. [a]. the resulting behavior is undefined. Generic addressing may be used with ld.. or the instruction may fault.s32.reg state space.vec = { . *(immAddr).ss}.0. *a.s16.

// negative offset %r.s32 ld.global.b16 cvt.[240].[buffer+64].global.shared.[a].[p+4].const[4].b64 ld.%r.f64 requires sm_13 or later. Q.b32 ld.local. ld.b32 ld. // load . d.[p].f32 ld.[p+-8].PTX ISA Version 2.b32 ld. // access incomplete array x.f16 d. Cache operations require sm_20 or later.v4. x. %r.local.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.f32.const.[fs].0 Target ISA Notes ld. Generic addressing requires sm_20 or later. 2010 . // immediate address %r.

to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . *(a+immOff). Addresses are zero-extended to the specified width as needed. .e. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . or the instruction may fault. . The value loaded is sign-extended to the destination register width for signed integers.b8.f64 requires sm_13 or later. If an address is not properly aligned.global.u16.vec = { . // load from address // vec load from address . If no state space is given. The addressable operand a is one of: [avar] the name of an addressable variable var. In generic addressing. ldu{. . d.b16.f64 }. and truncated if the register width exceeds the state space address width for the target architecture. .[a]. ldu. A destination register wider than the specified type may be used.f16 data may be loaded using ldu. Instruction Set Table 82. PTX ISA Notes Target ISA Notes Examples January 24. 32-bit). Within these windows.. A register containing an address may be declared as a bit-size type or integer type. .reg state space. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.global. ldu.type = { . i.b32. .vec. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . For ldu. or [immAddr] an immediate absolute byte address (unsigned.type d.f64 using cvt.s64. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. // state space .b16.u64.Chapter 8.ss}. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.v4. . and is zeroextended to the destination register width for unsigned and bit-size types. only generic addresses that map to global memory are legal.ss = { . *(immAddr). ldu. . .0.s32.[p+4]. The address must be naturally aligned to a multiple of the access size.f32 Q. where the address is guaranteed to be the same across all threads in the warp.b64. *a. [a]. The address size may be either 32-bit or 64-bit. ldu. . 32-bit). [areg] a register reg containing a byte address. Semantics d d d d = = = = a. [a]. . and then converted to . Introduced in PTX ISA version 2.f32.global }.[p].v4 }.type ldu{.global.s16.ss}. the resulting behavior is undefined. an address maps to global memory unless it falls within the local memory window or the shared memory window.v2. i.u32. 2010 115 .s8. The data at the specified address must be read-only. perform the load using generic addressing.b32 d. .f32 or .f32 d. an address maps to the corresponding location in local or shared memory.u8.e.

.cg. st introduced in PTX ISA version 1. If no state space is given.wt }. Generic addressing and cache operations introduced in PTX ISA 2. *d = a. .ss}.ss}{.volatile{.vec .shared spaces to inhibit optimization of references to volatile memory. .f32. or the instruction may fault. .u32. A source register wider than the specified type may be used.b32. 2010 . st. b.s64.global. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . st. .volatile may be used with . .b8.e. { . [a]. This may be used. b. Generic addressing may be used with st.type st.volatile.b16. for example.PTX ISA Version 2.s32.v2. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.0.type . . b. . st{. or [immAddr] an immediate absolute byte address (unsigned. Semantics d = a.volatile.cs. { . *(immAddr) = a. PTX ISA Notes Target ISA Notes 116 January 24.u64. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. .ss}{.s16.global and . . .ss . 32-bit).f64 }. st.volatile introduced in PTX ISA version 1.vec.0 Table 83. i.cop .vec. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.0. Within these windows. [a]. . an address maps to the corresponding location in local or shared memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding.shared }.local.volatile{. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.type [a]. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. to enforce sequential consistency between threads accessing shared memory. *(d+immOffset) = a.b16. .e.1.type st{. . The address size may be either 32-bit or 64-bit. perform the store using generic addressing.b64. Cache operations are not permitted with st. The address must be naturally aligned to a multiple of the access size. Addresses are zero-extended to the specified width as needed.cop}. the resulting behavior is undefined. i. 32-bit).. b.type = = = = {.u16.u8.v4 }. and truncated if the register width exceeds the state space address width for the target architecture. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . . Cache operations require sm_20 or later. { . an address maps to global memory unless it falls within the local memory window or the shared memory window.s8.ss}. .reg state space. . The lower n bits corresponding to the instruction-type width are stored to memory. Generic addressing requires sm_20 or later.wb.cop}. .f16 data resulting from a cvt instruction may be stored using st. [a].f64 requires sm_13 or later. . an integer or bit-size type register reg containing a byte address. If an address is not properly aligned. In generic addressing.

[q+-8].%r.f16.r7.b16 [a]. // %r is 32-bit register // store lower 16 bits January 24.Q.a. 2010 117 .%r.f32 st.b32 st.global. [q+4].b.local.b32 st.v4. // negative offset [100].Chapter 8. // immediate address %r.local.s32 cvt.global. [fs].local.s32 st.f32 st. Instruction Set Examples st. [p].a.

local }.L2 }.L1 [addr]. a register reg containing a byte address. . // prefetch to data cache // prefetch to uniform cache . .level = { .0.space}.global. in specified state space. [a]. 32-bit). In generic addressing.global. or [immAddr] an immediate absolute byte address (unsigned. 32-bit).0 Table 84.PTX ISA Version 2. A prefetch into the uniform cache requires a generic address. an address maps to the corresponding location in local or shared memory.L1 [ptr]. A prefetch to a shared memory location performs no operation. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e. Addresses are zero-extended to the specified width as needed. 2010 . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. an address maps to global memory unless it falls within the local memory window or the shared memory window. i. 118 January 24. The address size may be either 32-bit or 64-bit. prefetchu. . and truncated if the register width exceeds the state space address width for the target architecture. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. prefetch{. prefetch.level prefetchu. Within these windows. the prefetch uses generic addressing. If no state space is given. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L1 [a]. and no operation occurs if the address maps to a local or shared memory location. prefetch and prefetchu require sm_20 or later.space = { .L1.

// convert to generic address // get generic address of var // convert generic address to global. isspacep. local.to. The source and destination addresses must be the same size.pred.0. or vice-versa.u32 gptr. or shared state space to generic.space.global. gptr. // result is . local. cvta requires sm_20 or later. a. isspacep requires sm_20 or later. January 24. local. The source address operand must be a register of type . isshrd.size .local. the generic address of the variable may be taken using cvta.space = { . sptr. // local. a. PTX ISA Notes Target ISA Notes Examples Table 86.u32. . islcl. .space. or vice-versa.shared. A program may use isspacep to guard against such incorrect behavior.shared isglbl.u32 p. or shared state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. lptr. p.global. or shared address to a generic address. For variables declared in global. // get generic address of svar cvta.u32 to truncate or zero-extend addresses. a.genptr.u32 p.u32.Chapter 8.local. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. 2010 119 . or shared address cvta.u64 }.size p.u32 or . var. Use cvt. local. cvta.global isspacep. or shared address. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.shared }. p. svar.space = { . isspacep. .local.local isspacep. The destination register must be of type . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.pred . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u64 or cvt.size = { . Take the generic address of a variable declared in global.u64.size cvta. Description Convert a global.to. . local.space p.shared }. When converting a generic address into a global. Introduced in PTX ISA version 2. cvta.u64. Instruction Set Table 85.space.lptr.0. cvta. .global. or shared state space. .

rpi }. . a. Integer rounding is illegal in all other instances.sat For integer destination types. Description Semantics Integer Notes Convert between different types and sizes.. subnormal numbers are supported.u64.PTX ISA Version 2. sm_1x: For cvt.sat limits the result to MININT.rmi. choosing even integer if source is equidistant between two integers. and for same-size float-tofloat conversions where the value is rounded to an integer.. For float-to-integer conversions. . a.sat is redundant.rni.4 and earlier. Note: In PTX ISA versions 1.u8.rni round to nearest integer.f32 float-to-integer conversions and cvt.0 Table 87.u32.ftz.s8. d.dtype.f32 float-to-integer conversions and cvt. d = convert(a).ftz. .e. .f32. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.s16.ftz modifier may be specified in these cases for clarity. Integer rounding modifiers: .f64 }.atype d. 120 January 24. .u16.rzi round to nearest integer in the direction of zero .f32.sat}. . The optional . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. .rm.rn. .ftz. Integer rounding is required for float-to-integer conversions.rzi.sat}. . subnormal inputs are flushed to signpreserving zero.dtype.atype cvt{.f32 float-tofloat conversions with integer rounding.frnd = { .sat modifier is illegal in cases where saturation is not possible based on the source and destination types. . Saturation modifier: .ftz}{.ftz}{. .irnd = { .rz.e.dtype = . . cvt{.s32.dtype. i. // integer rounding // fp rounding . . . .rmi round to nearest integer in direction of negative infinity .atype = { . Note that saturation applies to both signed and unsigned integer types.f32.rp }. . the result is clamped to the destination range by default.MAXINT for the size of the operation. subnormal inputs are flushed to signpreserving zero. the . .irnd}{.f32 float-tofloat conversions with integer rounding. i. 2010 .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.f16. . .frnd}{.dtype. .ftz.s64. . The compiler will preserve this behavior for legacy PTX code. For cvt.

f32.rn mantissa LSB rounds to nearest even .Chapter 8. if the PTX . Introduced in PTX ISA version 1.f32.ftz behavior for sm_1x targets January 24. Note: In PTX ISA versions 1.f32.i. cvt.y. cvt.f32.0. result is fp cvt. and for integer-to-float conversions.f32.4 and earlier. Subnormal numbers: sm_20: By default. // round to nearest int. Floating-point rounding is illegal in all other instances. // note .0].sat limits the result to the range [0.f32. and .f32 instructions. subnormal numbers are supported. Specifically.s32 f.f16. 1.sat For floating-point destination types.f64 requires sm_13 or later. The optional .f16. 2010 121 .f64 types.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f64 j. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. and cvt. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f16. Saturation modifier: . stored in floating-point format. The operands must be of the same size.f32. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.0.r.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).rz mantissa LSB rounds towards zero . The result is an integral value.4 or earlier.s32.y.ftz modifier may be specified in these cases for clarity. The compiler will preserve this behavior for legacy PTX code. NaN results are flushed to positive zero.f32 x.f32 x. Applies to . Modifier .version is 1.rni.rm mantissa LSB rounds towards negative infinity . Floating-point rounding modifiers: . cvt to or from . // float-to-int saturates by default cvt. cvt.f64. . .

[tex1]. r5. r1. add. .target options ‘texmode_unified’ and ‘texmode_independent’.height. A PTX module may declare only one texturing mode.f32 {r1. r3. // get tex1’s txq.u32 r5.global . // get tex1’s tex. sampler.2d.f32. texture and sampler information is accessed through a single .u32 r5. the file is assumed to use unified mode.f32 r3. r2. PTX supports the following operations on texture. r5.texref handle.b32 r6. and surface descriptors.7. Example: calculate an element’s power contribution as element’s power/total number of elements.texref tex1 ) { txq. mul. add. with the restriction that they correspond 1-to-1 with the 128 possible textures.entry compute_power ( . If no texturing mode is declared. sampler. Texture and Surface Instructions This section describes PTX instructions for accessing textures.param . {f1. div.v4. sampler. 2010 . and surface descriptors. and surface descriptors: • • • Static initialization of texture. r4. sampler.r2. r5. but the number of samplers is greatly restricted to 16.6.r4}.PTX ISA Version 2. 122 January 24. The texturing mode is selected using . r1.b32 r5.f32.. [tex1.samplerref tsamp1 = { addr_mode_0 filter_mode }. Module-scope and per-entry scope definitions of texture. = nearest width height tsamp1.f32 r1. The advantage of unified mode is that it allows 128 samplers. PTX has two modes of operation. Texturing modes For working with textures and samplers.f32 r1.f32 r1.r3. The advantage of independent mode is that textures and samplers can be mixed and matched. cvt. and surfaces. Ability to query fields within texture. . and surface descriptors. texture and sampler information each have their own handle. r6. In the independent mode. } = clamp_to_border. samplers. In the unified mode. . r3.width. [tex1].f2}].target texmode_independent . allowing them to be defined separately and combined at the site of usage in the program. add. r1..0 8.

.r4}. . and is a four-element vector for 3d textures. Operand c is a scalar or singleton tuple for 1d textures. PTX ISA Notes Target ISA Notes Examples January 24. b. Unified mode texturing introduced in PTX ISA version 1. [a.geom. the square brackets are not required and . d.geom = { .f4}]. the resulting behavior is undefined. A texture base address is assumed to be aligned to a 16-byte address. where the fourth element is ignored. tex txq suld sust sured suq Table 88. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. // Example of independent mode texturing tex.dtype.s32. Description Texture lookup using a texture coordinate vector. . Notes For compatibility with prior versions of PTX.u32.1d. is a two-element vector for 2d textures.0. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. .f32 }. {f1}].f3. tex. c].Chapter 8.f32 }.3d }. the sampler behavior is a property of the named texture. sampler_x..s32 {r1. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.v4 coordinate vectors are allowed for any geometry. .v4.s32.f32 {r1.r2.2d. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.btype tex.v4.btype = { .3d. or the instruction may fault. [tex_a.dtype. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.dtype = { . {f1. An optional texture sampler b may be specified. The instruction always returns a four-element vector of 32-bit values. If no sampler is specified. the access may proceed by silently masking off low-order address bits to achieve proper rounding.r3. Instruction Set These instructions provide access to texture and surface memory. // explicit sampler . i. If an address is not properly aligned. . with the extra elements being ignored.5. //Example of unified mode texturing tex.r3. Supported on all target architectures.1d.f2.v4. c]. 2010 123 .btype d.r2. [a. [tex_a.r4}.v4.s32.s32.e.geom. .

b32 %r1.width . Query: . [a]. txq. // unified mode // independent mode 124 January 24. .squery = { .depth. . [a].filter_mode.height.b32 txq.5.tquery = { . Description Query an attribute of a texture or sampler.addr_mode_0 .height .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [tex_A].addr_mode_0. Supported on all target architectures. txq.normalized_coords . In unified mode. . addr_mode_2 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. clamp_ogl. addr_mode_1. [tex_A].b32 d. 2010 .b32 %r1.b32 %r1. Integer from enum { nearest.texref or . sampler attributes are also accessed via a texref argument.squery. . txq. . txq. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.width. Operand a is a .depth .samplerref variable.PTX ISA Version 2.addr_mode_0.0 Table 89. d. [smpl_B].addr_mode_1 .normalized_coords }. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.filter_mode . mirror.width. linear } Integer from enum { wrap.tquery. // texture attributes // sampler attributes . and in independent mode sampler attributes are accessed via a separate samplerref argument. clamp_to_edge.filter_mode.

size and type conversion is performed as needed to convert from the surface sample format to the destination type. . the surface sample elements are converted to .geom{.f32. .clamp field specifies how to handle out-of-bounds addresses: .surfref variable. . If an address is not properly aligned. is a two-element vector for 2d surfaces. Cache operations require sm_20 or later.dtype . The lowest dimension coordinate represents a sample offset rather than a byte offset.trap {r1. .trap introduced in PTX ISA version 1. or the instruction may fault. {x. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. If the destination base type is . {x}].cop}.p.f3. or FLOAT data.cop .Chapter 8. suld. then .b32. the resulting behavior is undefined. Operand a is a .b. . suld.b16.b performs an unformatted load of binary data.0.b32.clamp .trap . and cache operations introduced in PTX ISA version 2.clamp = = = = = = { { { { { { d. or . .p.u32. suld.b. The . where the fourth element is ignored.u32. suld Syntax Texture and Surface Instructions: suld Load from surface memory.trap suld.clamp suld.s32 is returned. 2010 125 . . Instruction Set Table 90. b].v2. B. .b64 }.p is currently unimplemented.r2}. .z. or .e.b8 .2d.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. [a. . .p requires sm_20 or later. Target ISA Notes Examples January 24. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. suld.f32 }.dtype .cop}.v4.vec.geom . // for suld.f32 based on the surface format as follows: If the surface format contains UNORM. b].f4}. Coordinate elements are of type . .s32. .3d }. suld.1d.5. If the destination type is . Destination vector elements corresponding to components that do not appear in the surface format are not written.w}]. // formatted . suld. A surface base address is assumed to be aligned to a 16-byte address.vec . suld. suld.f2.v2.v4. [surf_B.geom{.cg. additional clamp modifiers.clamp . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. Description Load from surface memory using a surface coordinate vector. // cache operation none.trap. .b64.dtype. // for suld.s32. if the surface format contains UINT data.trap clamping modifier.f32 is returned.3d requires sm_20 or later.p .b32. . and A components of the surface format.u32. and the size of the data transfer matches the size of destination operand d. i. . Operand b is a scalar or singleton tuple for 1d surfaces.s32.zero }. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f32.cs.u32 is returned.b . [surf_A. .b.3d.y.dtype.v4 }. {f1. SNORM. sm_1x targets support only the . G.ca. and is a four-element vector for 3d surfaces. // unformatted d.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.clamp. .b supported on all target architectures.s32. suld..1d.p. [a.cv }. if the surface format contains SINT data. then . then .

v4 }. .s32.b performs an unformatted store of binary data. .geom{.z.p requires sm_20 or later. sust.b32.b // for sust. 2010 . sust Syntax Texture and Surface Instructions: sust Store to surface memory. Operand b is a scalar or singleton tuple for 1d surfaces.0 Table 91.s32. the resulting behavior is undefined.trap [surf_A.p. if the surface format contains SINT data. or FLOAT data.clamp .p performs a formatted store of a vector of 32-bit data values to a surface sample.f32} are currently unimplemented.ctype .3d requires sm_20 or later.cop . . {x}]. sust.surfref variable. SNORM.e.2d.ctype. A surface base address is assumed to be aligned to a 16-byte address. and cache operations introduced in PTX ISA version 2.trap. .p.f4}.ctype.clamp field specifies how to handle out-of-bounds addresses: . These elements are written to the corresponding surface sample components.trap clamping modifier.clamp = = = = = = { { { { { { [a. // for sust.cop}. where the fourth element is ignored.b. b]. c. The source data is then converted from this type to the surface sample format.clamp sust. . Source elements that do not occur in the surface sample are ignored. if the surface format contains UINT data. sust. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.clamp.f32 is assumed.{u32.geom .vec. If the source type is .5.u32 is assumed.v2. [surf_B. The . G. .3d }. Operand a is a . or . none.. then .b. sust. . .s32.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.trap introduced in PTX ISA version 1. c.b32. i.1d. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.vec . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. // unformatted // formatted . sust. Cache operations require sm_20 or later.f32.1d.u32.b16. Coordinate elements are of type .b supported on all target architectures. additional clamp modifiers. sust.v4.trap . {f1. . sust. . then .f2.y. .zero }. is a two-element vector for 2d surfaces. sust. . . B. The lowest dimension coordinate represents a sample offset rather than a byte offset.f32.p. and A surface components.f32 }.s32. b].geom{. {x. .3d. or the instruction may fault.b.b32.p. Surface sample components that do not occur in the source vector will be written with an unpredictable value. .f3. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The source vector elements are interpreted left-to-right as R. sm_1x targets support only the .trap sust.ctype . {r1. size and type conversions are performed as needed between the surface sample format and the destination type. [a. sust.b8 .PTX ISA Version 2. . If an address is not properly aligned.clamp .cg.wt }. .w}].0.vec.cs. . The size of the data transfer matches the size of source operand c.r2}.wb.p Description Store to surface memory using a surface coordinate vector.cop}.b64 }.u32.b64. and is a four-element vector for 3d surfaces. . then .s32 is assumed. If the source base type is .v2. Target ISA Notes Examples 126 January 24.

Instruction Set Table 92.ctype = { . sured. . or the instruction may fault. [surf_B. // byte addressing sured. {x}].u64. r1.ctype.clamp [a.c.min.b . ..op. .clamp .u32.1d.s32.op. January 24. Coordinate elements are of type .geom.zero }.geom.clamp field specifies how to handle out-of-bounds addresses: .clamp = { . . the resulting behavior is undefined.b32 }.max.b]. 2010 127 .p. r1. where the fourth element is ignored.b performs an unformatted reduction on . .s32.Chapter 8.p . sured. operations and and or apply to . .op = { .clamp.add.s32 is assumed.or }.u32 based on the surface sample format as follows: if the surface format contains UINT data. or .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and the data is interpreted as . Operand a is a . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.s32 types.1d.trap [surf_A. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. // for sured.u32. .u32 and .add.trap sured.ctype. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b].b32 type. . . Operand b is a scalar or singleton tuple for 1d surfaces.min.u32. The . and is a four-element vector for 3d surfaces. . // sample addressing .u64. sured.2d. Reduction to surface memory using a surface coordinate vector. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b32.geom = { .e. sured requires sm_20 or later. The instruction type is restricted to .surfref variable.y}].u32 is assumed.b32.b32 }. . min and max apply to . .ctype = { .trap .3d }.p. Operations add applies to . . sured. . if the surface format contains SINT data. A surface base address is assumed to be aligned to a 16-byte address. {x. .0.clamp [a. is a two-element vector for 2d surfaces. .s32.trap.s32 or .c. then .2d.s32 types. i.u64 data.u32. and .b.b32.p performs a reduction on sample-addressed 32-bit data.and. If an address is not properly aligned. then . The lowest dimension coordinate represents a sample offset rather than a byte offset. // for sured.b. the access may proceed by silently masking off low-order address bits to achieve proper rounding.

[a]. [surf_A].b32 %r1. .surfref variable.query = { . Query: .PTX ISA Version 2.5.width.query. 128 January 24.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.width. suq.b32 d. .depth }. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.height. Supported on all target architectures. Description Query an attribute of a surface. .0 Table 93.width . 2010 .height . suq. Operand a is a .

x. {} Syntax Description Control Flow Instructions: { } Instruction grouping.7. 2010 129 .y.0. Instruction Set 8. { instructionList } The curly braces create a group of instructions.s32 a.Chapter 8. { add. used primarily for defining a function body. mov. setp. p.s32 d. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.f32 @q bra L23. @{!}p instruction. If {!}p then instruction Introduced in PTX ISA version 1. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.c.f32 @!p div.0.eq.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.7.0. Supported on all target architectures. ratio. Introduced in PTX ISA version 1. } PTX ISA Notes Target ISA Notes Examples Table 95. Supported on all target architectures. Threads with a false guard predicate do nothing.b. Execute an instruction or instruction block for threads that have the guard predicate true.a.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

130

January 24, 2010

Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

January 24, 2010

131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

132

January 24, 2010

sync 0. In conditionally executed code. operands p and c are predicates. 2010 133 . and then safely read values stored by other threads prior to the barrier.red performs a reduction operation across threads.sync bar.version 2.sync) until the barrier count is met.cta. b}.or }. If no thread count is specified. .popc is the number of threads with a true predicate. bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.and and . d.. bar.sync without a thread count introduced in PTX ISA 1. Note that a non-zero thread count is required for bar.red delays the executing threads (similar to bar. bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Since barriers are executed on a per-warp basis. and any-thread-true (. thread count. and bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.red instruction. b}.red} require sm_20 or later. Execution in this case is unpredictable.red} introduced in PTX .sync or bar.red. {!}c. In addition to signaling its arrival at the barrier. all threads in the CTA participate in the barrier.0.red should not be intermixed with bar. the waiting threads are restarted without delay. Thus. if any thread in a warp executes a bar instruction.op.op = { . bar. all-threads-true (. Each CTA instance has sixteen barriers numbered 0.popc. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. it is as if all the threads in the warp have executed the bar instruction. The result of . January 24.sync or bar. b. bar. the final value is written to the destination register in all threads waiting at the barrier.15. All threads in the warp are stalled until the barrier completes. Register operands. b}. and the barrier is reinitialized so that it can be immediately reused. the bar. Operand b specifies the number of threads participating in the barrier. {!}c. thread count.red. a{.u32 bar.0. while . p. the optional thread count must be a multiple of the warp size. threads within a CTA that wish to communicate via memory can store to memory. The reduction operations for bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).pred . a. bar.red are population-count (.popc).{arrive.arrive does not cause any waiting by the executing threads. bar. bar. Register operands.red also guarantee memory ordering among threads identical to membar. and bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active.sync and bar.red performs a predicate reduction across the threads participating in the barrier.Chapter 8.or). b. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. Only bar. Instruction Set Table 100. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. PTX ISA Notes Target ISA Notes Examples bar.sync and bar.and.arrive using the same active barrier.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. Description Performs barrier synchronization and communication within a CTA. it simply marks a thread's arrival at the barrier.and). When a barrier completes. The barrier instructions signal the arrival of the executing threads at the named barrier.arrive.sync with an immediate barrier number is supported for sm_1x targets. execute a bar. Operands a. Thus.{arrive. bar. a{.arrive a{. Once the barrier count is reached. and d have type .u32.

cta Waits until all prior memory writes are visible to other threads in the same CTA. membar.g.sys requires sm_20 or later.sys.sys introduced in PTX .sys }.sys Waits until all prior memory requests have been performed with respect to all clients. membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar. 2010 . membar.cta.version 2. or system memory level. membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.cta.version 1.0 Table 101. when the previous value can no longer be read.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.level. 134 January 24. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar. membar.gl} introduced in PTX . level describes the scope of other clients for which membar is an ordering event. membar. PTX ISA Notes Target ISA Notes Examples membar. by st.{cta.gl will typically have a longer latency than membar. .4.{cta.level = { . A memory write (e.sys will typically have much longer latency than membar.0. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl.gl.gl} supported on all target architectures. membar. For communication between threads in different CTAs or even different SMs. membar. including thoses communicating via PCI-E such as system and peer-to-peer memory. A memory read (e.PTX ISA Version 2. membar.gl. . global. that is. red or atom) has been performed when the value written has become visible to other clients at the specified level. this is the appropriate level of membar.g.cta. . and memory reads by this thread can no longer be affected by other thread writes. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.

.b32.op = { . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.type d. . Description // // // // // . c. .add. the access may proceed by silently masking off low-order address bits to achieve proper rounding. 32-bit operations. . i. 2010 135 .add.u32.b]. and stores the result of the specified operation at location a. or. . If no state space is given. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The address size may be either 32-bit or 64-bit.Chapter 8. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. min.space}.e. The floating-point operations are add. inc.b32 only .exch. The integer operations are add.b32. or the instruction may fault. .or. . performs a reduction operation with operand b and the value in location a.dec. and exch (exchange).global. atom.u64 .type = { .exch to store to locations accessed by other atomic operations. an address maps to the corresponding location in local or shared memory. and max. a de-referenced register areg containing a byte address.b64.op.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. overwriting the original value.shared }. The bit-size operations are and. e. The address must be naturally aligned to a multiple of the access size.f32 Atomically loads the original value at location a into destination register d.b64 . Within these windows. the resulting behavior is undefined. i. . For atom.u32 only . . accesses to local memory are illegal. max. . .min. If an address is not properly aligned.cas. b. [a].g. A register containing an address may be declared as a bit-size type or integer type. .max }. Addresses are zero-extended to the specified width as needed. and truncated if the register width exceeds the state space address width for the target architecture.. [a]. . b. perform the memory accesses using generic addressing. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. min. atom{. Operand a specifies a location in the specified state space. an address maps to global memory unless it falls within the local memory window or the shared memory window.u64.e. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. .space = { . or [immAddr] an immediate absolute byte address.space}. dec. Instruction Set Table 102. . . min.f32. .type atom{.u32.f32 }.s32. .and. by inserting barriers between normal stores and atomic operations to a common address.. xor. The floating-point add. cas (compare-and-swap). In generic addressing. . or by using atom.s32. and max operations are single-precision. . The inc and dec operations return a result in the range [0.xor. d.inc.s32. . January 24.u32.op.

: r.[a]. c) operation(*a.global. atom.global. d.0. atom. b. b). Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.add.f32 atom. d. atom.s32 atom.f32.my_val.my_new_val. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.[p].f32 requires sm_20 or later.0. Introduced in PTX ISA version 1.shared. s) = (r >= s) ? 0 dec(r.PTX ISA Version 2.exch} requires sm_12 or later. : r-1.max. Use of generic addressing requires sm_20 or later.max} are unimplemented.s. 64-bit atom. atom. s) = (r > s) ? s exch(r.{min.cas.b32 d. 2010 . atom.{add.shared requires sm_12 or later.[x+4]. Release Notes Examples @p 136 January 24. 64-bit atom.add. *a = (operation == cas) ? : } where inc(r.1. cas(r. s) = s.cas.global requires sm_11 or later. : r+1.shared operations require sm_20 or later.t) = (r == s) ? t operation(*a.0 Semantics atomic { d = *a.

The bit-size operations are and. The floating-point operations are add. or [immAddr] an immediate absolute byte address. . The inc and dec operations return a result in the range [0. If an address is not properly aligned. or the instruction may fault. .shared }.b64. If no state space is given.u32. The address size may be either 32-bit or 64-bit.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. 2010 137 . . .f32. and max operations are single-precision. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . Description // // // // . For red. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. by inserting barriers between normal stores and reduction operations to a common address.s32.add.xor.. . dec. i. The address must be naturally aligned to a multiple of the access size. and xor. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. accesses to local memory are illegal. . an address maps to the corresponding location in local or shared memory. .and.. or.type [a]. i. . overwriting the original value. red{. b. or by using atom.space}. inc. and truncated if the register width exceeds the state space address width for the target architecture.Chapter 8.s32.e.f32 Performs a reduction operation with operand b and the value in location a.op = { .dec. 32-bit operations.global. min. . where inc(r. Within these windows. . A register containing an address may be declared as a bit-size type or integer type.s32. b). [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Semantics *a = operation(*a. min.g.min. .space = { . January 24. .inc. Addresses are zero-extended to the specified width as needed.u32. The integer operations are add.u64 . the access may proceed by silently masking off low-order address bits to achieve proper rounding. Operand a specifies a location in the specified state space.or.f32 }. . In generic addressing.e. and stores the result of the specified operation at location a.exch to store to locations accessed by other reduction operations.add. an address maps to global memory unless it falls within the local memory window or the shared memory window. red.b32. e. and max. Notes Operand a must reside in either the global or shared state space. Instruction Set Table 103. a de-referenced register areg containing a byte address. the resulting behavior is undefined. min. .u32 only . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.b]. s) = (r >= s) ? 0 : r+1. s) = (r > s) ? s : r-1. max. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.b32 only . . . The floating-point add.u64. . dec(r.max }.op.u32. .type = { . . perform the memory accesses using generic addressing.

my_val.shared.shared requires sm_12 or later.f32 red.max.add.global requires sm_11 or later red. 64-bit red. [x+4].add.and. red.2.f32 requires sm_20 or later. red.0.PTX ISA Version 2.s32 red.{min.add requires sm_12 or later.global.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 64-bit red.shared operations require sm_20 or later.f32. Release Notes Examples @p 138 January 24.global. 2010 . red.b32 [a].1.max} are unimplemented. red. Use of generic addressing requires sm_20 or later. [p].

.uni }. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.uni. vote. Instruction Set Table 104. r1. returns bitmask . Negating the source predicate also computes .uni True if source predicate has the same value in all active threads in warp. .all. {!}a. {!}a.mode. vote requires sm_12 or later.ballot.b32 p. // get ‘ballot’ across warp January 24. Description Performs a reduction of the source predicate across threads in a warp.uni. Negate the source predicate to compute . p.any True if source predicate is True for some active thread in warp.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.b32 requires sm_20 or later. 2010 139 . Note that vote applies to threads in a single warp.none.2.all. The destination predicate value is the same across all threads in the warp. not across an entire CTA. vote. vote. vote.any.pred d.ballot. .pred vote. // ‘ballot’ form.p.ballot.q.Chapter 8.not_all.mode = { . .q.b32 d.ballot.pred vote. where the bit position corresponds to the thread’s lane id. The reduction modes are: . vote.all True if source predicate is True for all active threads in warp. Negate the source predicate to compute . In the ‘ballot’ form.

secop d.dtype = . b{.btype = { . .sat}.secop = { . . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). with optional data merge vop. .7.s34 intermediate result. with optional secondary operation vop.dtype.9.u32 or . The general format of video instructions is as follows: // 32-bit scalar operation.b0. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. c. half-word.atype = . The primary operation is then performed to produce an . 2.sat} d.bsel}.s33 values.sat} d. optionally clamp the result to the range of the destination type.add.h1 }.dtype. a{. Using the atype/btype and asel/bsel specifiers. .bsel}.0 8.s32) is specified in the instruction type. . 3. extract and sign. .min. . perform a scalar arithmetic operation to produce a signed 34-bit result. . a{. 2010 .asel}. to produce signed 33-bit input values. vop. taking into account the subword destination size in the case of optional data merging.atype. the input values are extracted and signor zero.atype.h0. b{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. The type of each operand (. The source and destination operands are all 32-bit registers. The sign of the intermediate result depends on dtype. atype.b3.btype{. Video Instructions All video instructions operate on 32-bit register operands.btype{. c. 4.atype.dsel = . all combinations of dtype.bsel = { . . and btype are valid.PTX ISA Version 2. .u32.extended internally to .asel}. // 32-bit scalar operation.b1.bsel}.b2. . a{.max }. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.or zero-extend byte.asel = .asel}. or word values from its source operands. b{.dtype. 140 January 24.dsel.s32 }.btype{.

min: return MIN(tmp. U8_MAX. . . c).b0: return ((tmp & 0xff) case . The lower 32-bits are then written to the destination operand. tmp. c). } } . c). 2010 141 . tmp.h1: return ((tmp & 0xffff) << 16) case . S8_MAX. Bool sat. January 24. as shown in the following pseudocode. . U16_MAX.max return MAX(tmp.b2: return ((tmp & 0xff) << 16) case . . U16_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. S32_MIN ).Chapter 8.b1: return ((tmp & 0xff) << 8) case .s33 optSaturate( .s33 tmp. The sign of the c operand is based on dtype. tmp. .s33 c) { switch ( secop ) { .b2.b3: if ( sign ) return CLAMP( else return CLAMP( case .s33 c ) switch ( dsel ) { case . c). } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). .s34 tmp.h0: return ((tmp & 0xffff) case . S16_MIN ).b0.s33 optSecOp(Modifier secop. . Instruction Set . U8_MIN ).b1. switch ( dsel ) { case .h0. .s33 tmp. c). c). U32_MAX. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 optMerge( Modifier dsel. . . c). Modifier dsel ) { if ( !sat ) return tmp. Bool sign. default: return tmp. S16_MAX.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp.add: return tmp + c. S8_MIN ). S32_MAX. tmp. . U32_MIN ).

bsel = { .h1. r3.vop . .bsel}. vsub.dsel .s32 }.s32.bsel}.s32. with optional data merge vop. r1. r3.bsel}. vmin. // optional secondary operation d = optMerge( dsel. vsub vabsdiff vmin. vmax }. vabsdiff.btype{.btype = { . r3. 2010 . isSigned(dtype).add.s32.sat}. tb ).dtype. tmp = MAX( ta. and optional secondary arithmetic operation or subword data merge. dsel ).asel}.b0. a{. vabsdiff. . c ). .s32. vmin. r2.min.0. tmp = MIN( ta.s32. // extract byte/half-word/word and sign.PTX ISA Version 2. tmp = ta – tb.atype. b{. vabsdiff. vadd.sat} d. .atype.btype{.atype = .dtype. tmp. vsub. { .b0.h0.atype.asel = . // 32-bit scalar operation.sat} d.op2 d. c.max }. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.s32.b1. c. . Perform scalar arithmetic operation with optional saturate. tmp = | ta – tb |.add r1. // 32-bit scalar operation. vmin. Semantics // saturate.b0. btype.sat vsub. Video Instructions: vadd. Integer byte/half-word/word absolute value of difference. vadd. r2.h1. vsub. r2.dtype .dsel. .b2.sat. c.h0. a{. bsel ). r2. vmax require sm_20 or later. r1.op2 Description = = = = { vadd. c.u32.sat vabsdiff. . vmax vadd.or zero-extend based on source operand type ta = partSelectSignExtend( a.asel}.s32.b2. with optional secondary operation vop.s32. b{. vop.sat vmin. // optional merge with c operand 142 January 24.dtype.u32.s32. . Integer byte/half-word/word minimum / maximum. d = optSecondaryOp( op2.0 Table 105.btype{. .h1 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .h0.b3. taking into account destination type and merge operations tmp = optSaturate( tmp. . tb ).s32.asel}. sat. tmp. r1. r3. asel ).u32. vmax Syntax Integer byte/half-word/word addition / subtraction. a{. atype. b{. tb = partSelectSignExtend( b. c ).

dtype. // default is . . r2. tmp.mode} d. vshl. Video Instructions: vshl.u32{.clamp.b0.u32 vshr. January 24.dsel . atype. . a{. and optional secondary arithmetic operation or subword data merge.u32. vop. vshr }. with optional secondary operation vop.asel}. { .u32{.atype.h0. tb = partSelectSignExtend( b.s32. // 32-bit scalar operation.atype. and optional secondary arithmetic operation or subword data merge.b3. r3. . with optional data merge vop.atype = { .sat}{.u32{.dtype. c. d = optSecondaryOp( op2. // 32-bit scalar operation.asel}.wrap ) tb = tb & 0x1f. Left shift fills with zero. vshr: Shift a right by unsigned amount in b with optional saturate.op2 Description = = = = = { vshl.atype. { . 2010 143 .bsel = { . Instruction Set Table 106. if ( mode == .op2 d.clamp .u32.sat}{.asel = . Semantics // extract byte/half-word/word and sign.vop . } // saturate. dsel ).0.u32. taking into account destination type and merge operations tmp = optSaturate( tmp.add.mode} d. // optional secondary operation d = optMerge( dsel. unsigned shift fills with zero. bsel ). vshl. .h1.mode . vshl: Shift a left by unsigned amount in b with optional saturate. . r3. tmp. b{.b2. switch ( vop ) { case vshl: tmp = ta << tb.b1. . a{.u32.max }. .min.or zero-extend based on source operand type ta = partSelectSignExtend( a.mode}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . . sat. b{. .clamp && tb > 32 ) tb = 32. if ( mode == .dtype. .h1 }. isSigned(dtype).u32.bsel}. vshr require sm_20 or later.bsel}. c ). a{. b{.dtype . case vshr: tmp = ta >> tb.u32. vshr vshl.wrap r1.dsel. . c ). r2. r1. asel ). c.Chapter 8.bsel}. vshr Syntax Integer byte/half-word/word left / right shift.sat}{. Signed shift fills with the sign bit.wrap }.asel}.s32 }.

final signed -(S32 * U32) + S32 // intermediate signed.0 Table 107. Depending on the sign of the a and b operands.b3.sat}{. 2010 .shr15 }. (a*b) is negated if and only if exactly one of a or b is negated. otherwise. b{. final signed The intermediate result is optionally scaled via right-shift.u32. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. . final signed (S32 * U32) . . 144 January 24. with optional operand negates. The source operands support optional negation with some restrictions. “plus one” mode. and scaling. final signed (U32 * U32) . the intermediate result is signed.atype. . {-}a{. Source operands may not be negated in .scale = { .asel = . // 32-bit scalar operation vmad. .asel}. . and zero-extended otherwise. final signed -(U32 * S32) + S32 // intermediate signed.S32 // intermediate signed.dtype..btype{. and the operand negates. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.s32 }. final signed (S32 * S32) + S32 // intermediate signed. a{.S32 // intermediate signed.btype.b0.atype. internally this is represented as negation of the product (a*b). this result is sign-extended if the final result is signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final signed (S32 * U32) + S32 // intermediate signed. final signed (U32 * S32) + S32 // intermediate signed.btype = { . The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.scale} d. Although PTX syntax allows separate negation of the a and b operands.bsel}. . The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed (S32 * S32) . . The “plus one” mode (. . Input c has the same sign as the intermediate result. c.shr7.asel}. Description Calculate (a*b) + c.po mode. That is.U32 // intermediate unsigned. which is used in computing averages.bsel}. vmad.S32 // intermediate signed.dtype. .b1. PTX allows negation of either (a*b) or c. final signed -(S32 * S32) + S32 // intermediate signed. {-}b{. final signed (U32 * S32) .scale} d.b2. .h0. final unsigned -(U32 * U32) + S32 // intermediate signed.atype = .dtype = .h1 }. {-}c.sat}{.po) computes (a*b) + c + 1.bsel = { .po{.PTX ISA Version 2.

r0.u32. r3.Chapter 8. r2. vmad.0. } else if ( c. } if ( . if ( .po ) { lsb = 1.or zero-extend based on source operand type ta = partSelectSignExtend( a. asel ). tmp[127:0] = ta * tb.s32. r1. } else if ( a. Instruction Set Semantics // extract byte/half-word/word and sign.u32. lsb = 0. lsb = 1.negate ) { tmp = ~tmp.s32. atype. January 24.negate ) { c = ~c.h0. r2.negate) || c.u32. vmad requires sm_20 or later. signedFinal = isSigned(atype) || isSigned(btype) || (a. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). case .negate ^ b. U32_MIN). lsb = 1. switch( scale ) { case . U32_MAX. -r3.sat vmad. 2010 145 .u32.shr15: result = (tmp >> 15) & 0xffffffffffffffff. r1.negate. S32_MAX. bsel ). btype. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tb = partSelectSignExtend( b.shr7: result = (tmp >> 7) & 0xffffffffffffffff. tmp = tmp + c128 + lsb. else result = CLAMP(result.shr15 r0.negate ^ b. S32_MIN).sat ) { if (signedFinal) result = CLAMP(result.h0.

The intermediate result of the comparison is always unsigned. { .h1.s32.lt. c. and therefore the c operand and final result are also unsigned.le. // optional secondary operation d = optMerge( dsel.b0.asel}. vset requires sm_20 or later. . with optional secondary arithmetic operation or subword data merge.bsel}.bsel = { .op2 d. r1. tmp = compare( ta.u32.gt. // 32-bit scalar operation. cmp ) ? 1 : 0.b1.asel = . r2.asel}.btype = { .op2 Description = = = = . . . . .asel}.lt vset.atype. Semantics // extract byte/half-word/word and sign. r3.bsel}.ne.dsel. vset.add. r3.b2.btype.b3. c ).cmp d. 146 January 24. a{. { . d = optSecondaryOp( op2.btype. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. b{. . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. . bsel ). . asel ). 2010 .or zero-extend based on source operand type ta = partSelectSignExtend( a. Compare input values using specified comparison.u32.min. c.bsel}. tmp.max }. with optional data merge vset.btype.u32.dsel . tb = partSelectSignExtend( b. c ).0 Table 108. a{.ne r1. tb.atype . . .s32 }. . atype.u32. a{. . with optional secondary operation vset. vset. btype. b{.atype. .cmp d.cmp. // 32-bit scalar operation.cmp .PTX ISA Version 2.h1 }. .atype. . b{.ge }.eq.0.h0. r2. tmp.

Table 110. @p pmevent 1. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Introduced in PTX ISA version 1. Supported on all target architectures. numbered 0 through 15.0. brkpt. pmevent 7. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. The relationship between events and counters is programmed via API calls from the host. Notes PTX ISA Notes Target ISA Notes Examples Currently. with index specified by immediate operand a. trap. brkpt Suspends execution Introduced in PTX ISA version 1. January 24. Triggers one of a fixed number of performance monitor events. trap Abort execution and generate an interrupt to the host CPU. trap.10. pmevent a. brkpt requires sm_11 or later.Chapter 8. there are sixteen performance monitor events.0. Instruction Set 8. brkpt. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.4. Introduced in PTX ISA version 1. Supported on all target architectures.7. 2010 147 . Table 111.

0 148 January 24. 2010 .PTX ISA Version 2.

which are visible as special registers and accessed through mov or cvt instructions. 2010 149 . %clock64 %pm0.Chapter 9. %lanemask_ge. %lanemask_lt. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. Special Registers PTX includes a number of predefined. …. %pm3 January 24. %lanemask_gt %clock. read-only variables. %lanemask_le.

%ntid.sreg .y 0 <= %tid.%h1.sreg . cvt. // compute unified thread id for 2D CTA mov. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.v4.x.z < %ntid.x code accessing 16-bit component of %tid mov.z.x 0 <= %tid. %tid.u32 %r0. read-only special register initialized with the number of thread ids in each CTA dimension. per-thread special register initialized with the thread identifier within the CTA. 2D.x code Target ISA Notes Examples 150 January 24. %tid. %ntid. .x to %rh Target ISA Notes Examples // legacy PTX 1.z == 0 in 2D CTAs. . PTX ISA Notes Introduced in PTX ISA version 1. // legacy PTX 1.%tid. mov.y * %ntid. The number of threads in each dimension are specified by the predefined special register %ntid. read-only.%tid.z. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.z to %r2 Table 113. mad.v4 . // thread id vector // thread id components A predefined. 2010 .u32 type in PTX 2. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. The total number of threads in a CTA is (%ntid.0 Table 112.u16 %rh.x * %ntid.x.v4. The %tid special register contains a 1D. CTA dimensions are non-zero. // move tid.y == %tid. the %tid value in unused dimensions is 0. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u32 %h2. Every thread in the CTA has a unique %tid.%tid. Redefined as . %tid.y.x < %ntid. Supported on all target architectures. or 3D vector to match the CTA shape.x.sreg .y. the fourth element is unused and always returns zero.u16 %r2.0. %tid component values range from 0 through %ntid–1 in each CTA dimension.0. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.sreg .PTX ISA Version 2.0.z. The fourth element is unused and always returns zero. mov. Supported on all target architectures. .z == 1 in 1D CTAs.u32 type in PTX 2.z == 1 in 2D CTAs.u32 %r1.v4 .x. Redefined as .x. // zero-extend tid.y == %ntid.u32 %r0.x. mov.u16 %rh.y.x.%ntid.z == 0 in 1D CTAs.u32 %tid.u32 %ntid. It is guaranteed that: 0 <= %tid. %ntid.%tid.%ntid.0.y < %ntid.%tid.u32 %tid.u32 %ntid.u32. . // CTA shape vector // CTA dimensions A predefined.u32 %h1. mov. %ntid. %tid.z PTX ISA Notes Introduced in PTX ISA version 1.z).%r0.%h2.

Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Table 116. The warp identifier will be the same for all threads within a single warp. .0. read-only special register that returns the thread’s warp identifier. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. A predefined. . January 24. but its value may change during execution.u32 %nwarpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.u32 %laneid.3. mov. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Table 115. read-only special register that returns the thread’s lane within the warp.u32 %r.g.u32 %r.sreg . Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. %nwarpid requires sm_20 or later. Supported on all target architectures.sreg . . Note that %warpid is volatile and returns the location of a thread at the moment when read. A predefined. Introduced in PTX ISA version 1. e. For this reason. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. A predefined. Special Registers Table 114. %nwarpid. Supported on all target architectures.3.Chapter 9. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. 2010 151 . mov. %laneid. Introduced in PTX ISA version 2. %warpid.sreg . The lane identifier ranges from zero to WARP_SZ-1.u32 %warpid. due to rescheduling of threads following preemption. read-only special register that returns the maximum number of warp identifiers.u32 %r. mov.

// CTA id vector // CTA id components A predefined. or 3D vector. The %ctaid special register contains a 1D.v4 .x.sreg . 2D.z < %nctaid.x 0 <= %ctaid. %ctaid. // legacy PTX 1.PTX ISA Version 2.0. // Grid shape vector // Grid dimensions A predefined. The fourth element is unused and always returns zero.u32 %ctaid.0. %rh.x.y 0 <= %ctaid.{x.%nctaid.u32 %ctaid.x code Target ISA Notes Examples Table 118. Supported on all target architectures.v4.u32 %nctaid.y. %ctaid. The fourth element is unused and always returns zero.v4 .%ctaid.x code Target ISA Notes Examples 152 January 24. // legacy PTX 1. It is guaranteed that: 0 <= %ctaid.y.y. with each element having a value of at least 1. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. Each vector element value is >= 0 and < 65535.sreg .x. mov. 2010 . %rh.z.u32 mov. .sreg .%nctaid.z} < 65.sreg . . Redefined as .%ctaid. mov.z. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u32 %nctaid .x. read-only special register initialized with the CTA identifier within the CTA grid.%nctaid.u32 mov.u32 type in PTX 2. It is guaranteed that: 1 <= %nctaid.%nctaid.z PTX ISA Notes Introduced in PTX ISA version 1. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.u16 %r0.y.u32 type in PTX 2. depending on the shape and rank of the CTA grid.u16 %r0. read-only special register initialized with the number of CTAs in each grid dimension.v4. Supported on all target architectures.0.y < %nctaid.536 PTX ISA Notes Introduced in PTX ISA version 1. Redefined as .0.x < %nctaid.0 Table 117.x. . Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. The %nctaid special register contains a 3D grid shape vector.

Supported on all target architectures. A predefined. Supported on all target architectures.3. mov. Introduced in PTX ISA version 2. // initialized at grid launch A predefined.u32 %r.0. so %nsmid may be larger than the physical number of SMs in the device.g. The SM identifier numbering is not guaranteed to be contiguous. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. e.sreg . Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Note that %smid is volatile and returns the location of a thread at the moment when read. Special Registers Table 119. read-only special register that returns the maximum number of SM identifiers. but its value may change during execution. mov. where each launch starts a grid-of-CTAs. %gridid. . Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Introduced in PTX ISA version 1.u32 %gridid. %smid.Chapter 9. Introduced in PTX ISA version 1. repeated launches of programs may occur.u32 %smid. . read-only special register initialized with the per-grid temporal grid identifier. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. mov. %nsmid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.u32 %r. PTX ISA Notes Target ISA Notes Examples January 24. due to rescheduling of threads following preemption.u32 %r. This variable provides the temporal grid launch number for this context. . Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. During execution. A predefined.sreg .0. The SM identifier numbering is not guaranteed to be contiguous. PTX ISA Notes Target ISA Notes Examples Table 121. The SM identifier ranges from 0 to %nsmid-1. 2010 153 . %nsmid requires sm_20 or later.sreg .u32 %nsmid.

Table 124.0.u32 %lanemask_eq. %lanemask_lt. mov. Table 123. mov.0.sreg . %lanemask_lt requires sm_20 or later.sreg . Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_le. 154 January 24. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined.0 Table 122.u32 %lanemask_le.sreg .0. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later.u32 %r.u32 %lanemask_lt. A predefined.u32 %r. Introduced in PTX ISA version 2.PTX ISA Version 2. . %lanemask_eq. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. 2010 . . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.u32 %r. mov. %lanemask_le requires sm_20 or later.

.Chapter 9. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. A predefined. Special Registers Table 125.sreg . 2010 155 .u32 %r. Introduced in PTX ISA version 2.0. %lanemask_gt requires sm_20 or later. %lanemask_ge. . %lanemask_ge requires sm_20 or later. Table 126. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %r. Introduced in PTX ISA version 2. mov. January 24.u32 %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_gt. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %lanemask_ge.sreg . mov.0.

Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. read-only 32-bit unsigned cycle counter.%clock. %pm3 %pm0.u32 %clock. %pm3. Table 129. The lower 32-bits of %clock64 are identical to %clock. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm2. read-only 64-bit unsigned cycle counter. %pm1. Supported on all target architectures. mov. Introduced in PTX ISA version 1. mov. . %pm2. mov.u64 %clock64.0 Table 127.sreg . and %pm3 are unsigned 32-bit read-only performance monitor counters. …. Introduced in PTX ISA version 1. %pm2.PTX ISA Version 2. Introduced in PTX ISA version 2. Special registers %pm0. Supported on all target architectures.0.u64 r1.3. %pm1. 156 January 24. Special Registers: %pm0. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm1. .%pm0.0.sreg . Table 128.u32 r1.u32 r1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. . Their behavior is currently undefined.%clock64. %clock64 requires sm_20 or later. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.sreg .u32 %pm0. 2010 .

4 January 24. .version directives are allowed provided they match the original . .version directive.version Syntax Description Semantics PTX version number. Supported on all target architectures. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.minor // major. Duplicate . . minor are integers Specifies the PTX language version number.Chapter 10.version .target Table 130. Each ptx file must begin with a . 2010 157 . PTX File Directives: .0.version 1. Increments to the major number indicate incompatible changes to PTX.version .version directive. Directives 10.version 2.1.0 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. and the target architecture for which the code was generated.version major.

5.shared.target Syntax Architecture and Platform target. Texturing mode: (default is . sm_13.f64 instructions used. sm_12.texref and . 64-bit {atom. where each generation adds new features and retains all features of previous generations.0. Each PTX file must begin with a . with only half being used by instructions converted from .red}.target . sm_11.target directive containing a target architecture and optional platform options. texture and sampler information is referenced with independent .red}.samplerref descriptors. Note that . Supported on all target architectures. Adds {atom.f64 instructions used. PTX features are checked against the specified target architecture. Target sm_20 Description Baseline feature set for sm_20 architecture. map_f64_to_f32 }. Requires map_f64_to_f32 if any . A . texmode_unified. The texturing mode is specified for an entire module and cannot be changed within the module. In general. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.version directive. 2010 .f64 storage remains as 64-bits. The following table summarizes the features in PTX that vary according to target architecture. Description Specifies the set of features in the target architecture for which the current ptx code was generated. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. PTX code generated for a given target can be run on later generation devices.texmode_independent texture and sampler information is bound together and accessed via a single . immediately followed by a .f64 to .target directive specifies a single target architecture. and an error is generated if an unsupported feature is used. Requires map_f64_to_f32 if any . sm_10. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.f64 instructions used.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. brkpt instructions.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. but subsequent .red}.PTX ISA Version 2. Texturing mode introduced in PTX ISA version 1.texref descriptor.texmode_unified) . 158 January 24. Disallows use of map_f64_to_f32.texmode_unified . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. texmode_independent. vote instructions. generations of SM architectures follow an “onion layer” model. Adds {atom. PTX File Directives: . Introduced in PTX ISA version 1. A program with multiple .f32. Therefore.target directives can be used to change the set of target features allowed during parsing.0 Table 131. including expanded rounding modifiers. Adds double-precision support. . Requires map_f64_to_f32 if any .global.global.

2010 159 .target sm_20.Chapter 10.target sm_13 // supports double-precision . Directives Examples . texmode_independent January 24.target sm_10 // baseline target architecture .

param space memory and are listed within an optional parenthesized parameter list. . Kernel and Function Directives: . [z].texref.g. At kernel launch. ld.entry cta_fft . store.5 and later. %nctaid.2.entry .surfref variables may be passed as parameters.param . PTX ISA Notes For PTX ISA version 1. and query instructions and cannot be accessed via ld. parameters.0 through 1. .samplerref. The shape and size of the CTA executing the kernel are available in special registers. . … } .PTX ISA Version 2.4. ld.b32 %r3. and body for the kernel function. 2010 . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. parameter variables are declared in the kernel body.3.param. Supported on all target architectures.b32 x. and . ld.b32 %r1.b32 %r2. Semantics Specify the entry point for a kernel program. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. opaque .b32 y.entry .b32 %r<99>.param. [y].entry kernel-name ( param-list ) kernel-body . parameter variables are declared in the kernel parameter list. In addition to normal parameters.param instructions. etc.param { .b32 z ) Target ISA Notes Examples [x]. with optional parameters.0 through 1. e. For PTX ISA versions 1. .4 and later. Parameters may be referenced by name within the kernel body and loaded into registers using ld. These parameters can only be referenced by name within texture and surface load.param instructions. 160 January 24.param.entry filter ( .func Table 132. Parameters are passed via .reg .param .entry Syntax Description Kernel entry point and body. . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.0 10.entry kernel-name kernel-body Defines a kernel entry point name. the kernel dimensions and properties are established and made available via special registers. %ntid. .

x code.param space are accessed using ld. and recursion is illegal.func (.func definition with no body provides a function prototype. . ret. … Description // return value in fooval January 24. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.b32 localVar. } … call (fooval). Kernel and Function Directives: .reg .result.func fname function-body .Chapter 10.b32 rval. 2010 161 .0 with target sm_20 allows parameters in the . val1). other code. Parameters must be base types in either the register or parameter state space. Directives Table 133. A . Parameters in . Variadic functions are currently unimplemented.0. foo. Supported on all target architectures. PTX ISA 2. . Variadic functions are represented using ellipsis following the last fixed argument. which may use a combination of registers and stack locations to pass parameters. The implementation of parameter passing is left to the optimizing translator. parameters must be in the register state space.2 for a description of variadic functions. implements an ABI with stack. and supports recursion.param and st. dbl.param state space. … use N.0 with target sm_20 supports at most one return value. including input and return parameters and optional function body. The parameter lists define locally-scoped variables in the function body. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.reg . PTX 2. Release Notes For PTX ISA version 1.func (ret-param) fname (param-list) function-body Defines a function.reg .b32 rval) foo (.reg . Parameter passing is call-by-value.param instructions in the body.b32 N.func Syntax Function definition.func . mov.func fname (param-list) function-body . Parameters in register state space may be referenced directly within instructions in the function body.f64 dbl) { . if any. there is no stack. (val0. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

registers) to increase total thread count and provide a greater opportunity to hide memory latency. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).pragma The . Note that . . The directive passes a list of strings to the backend.pragma directive is supported for passing information to the PTX backend.maxntid directive specifies the maximum number of threads in a thread block (CTA).maxntid . Currently. which pass information to the backend optimizing compiler. These can be used. The directives take precedence over any module-level constraints passed to the optimizing backend. at entry-scope.maxnctapersm (deprecated) .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.minnctapersm directives may be applied per-entry and must appear between an . The interpretation of . PTX supports the following directives.pragma directives may appear at module (file) scope. 162 January 24.0 10. .maxntid and . and the .3.PTX ISA Version 2. for example.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. 2010 . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. or as statements within a kernel or device function body. to throttle the resource requirements (e.maxnreg. and the strings have no semantics within the PTX virtual machine model.g.minnctapersm . the . The . A general .entry directive and its body.maxntid.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. and . the .maxnreg .

for example. Supported on all target architectures.3. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid 256 . .3. ny. 2D.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.entry foo .maxctapersm. Introduced in PTX ISA version 1. nz Declare the maximum number of threads in the thread block (CTA). ny .16. . or the maximum number of registers may be further constrained by . Directives Table 134.maxntid 16. Supported on all target architectures.maxntid and .maxnreg .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid Syntax Maximum number of threads in thread block (CTA).Chapter 10. or 3D CTA. .maxntid nx.maxntid nx .entry bar . Introduced in PTX ISA version 1. The maximum number of threads is the product of the maximum extent in each dimension. the backend may be able to compile to fewer registers.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. The actual number of registers used may be less. Performance-Tuning Directives: . 2010 163 . Exceeding any of these limits results in a runtime error or kernel launch failure.maxnreg n Declare the maximum number of registers per thread in a CTA. Performance-Tuning Directives: . .maxntid nx.maxntid .entry foo . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. The compiler guarantees that this limit will not be exceeded.

maxntid to be specified as well. For this reason. . . Deprecated in PTX ISA version 2.minnctapersm . additional CTAs may be mapped to a single multiprocessor. Performance-Tuning Directives: . Supported on all target architectures. 2010 . Performance-Tuning Directives: .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. .entry foo .maxnctapersm generally need . Introduced in PTX ISA version 1.0.0. The optimizing backend compiler uses .entry foo .maxntid and . .0 as a replacement for . if the number of registers used by the backend is sufficiently lower than this bound.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. However.PTX ISA Version 2. Optimizations based on .minnctapersm 4 { … } 164 January 24.maxntid 256 .minnctapersm generally need . Introduced in PTX ISA version 2. Optimizations based on .3.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid to be specified as well.maxnctapersm has been renamed to .maxnctapersm.maxnctapersm (deprecated) .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Supported on all target architectures. .0 Table 136.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid 256 .minnctapersm in PTX ISA version 2.

or at statementlevel.entry foo . at entry-scope. 2010 165 .pragma list-of-strings . entry-scoped. or statement-level directives to the PTX backend compiler. { … } January 24.0. .pragma Syntax Description Pass directives to PTX backend compiler. The .pragma . Performance-Tuning Directives: .Chapter 10. . Directives Table 138. The interpretation of . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma directive may occur at module-scope. Pass module-scoped. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Introduced in PTX ISA version 2.pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma “nounroll”.pragma “nounroll”. Supported on all target architectures.

0 and replaces the @@DWARF syntax.section . 0x6150736f. 2010 .232-1] .PTX ISA Version 2.. Supported on all target architectures. 0x61395a5f.debug_info . 0x5f736f63 . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .0.4byte label .2.section directive.quad int64-list // comma-separated hexadecimal integers in range [0.4. 0x736d6172 . 0x02.loc The .byte byte-list // comma-separated hexadecimal byte values . 0x00 166 January 24. 0x00.section directive is new in PTX ISA verison 2.4byte int32-list // comma-separated hexadecimal integers in range [0.4byte 0x6e69616d. 0x00.section . 0x00. The @@DWARF syntax is deprecated as of PTX version 2.4byte . 0x00.4byte 0x000006b5.. 0x00. 0x00 .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.0 but is supported for legacy PTX version 1. @@DWARF dwarf-string dwarf-string may have one of the . 0x63613031.byte 0x00. 0x00000364. “”. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .264-1] . Table 139. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. @progbits . Deprecated as of PTX 2. 0x00.0 10.byte 0x2b.x code. Introduced in PTX ISA version 1.debug_pubnames.file . replaced by .

b8 byte-list // comma-separated list of integers in range [0. replaces @@DWARF syntax. 0x63613031.b32 label .. Supported on all target architectures.b32 0x000006b5.section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00.loc line_number January 24. Debugging Directives: .b32 0x6e69616d. 0x00. .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.264-1] . Supported on all target architectures.b32 .file filename Table 142. 0x00.0.. 0x5f736f63 0x6150736f. Supported on all target architectures. .0. 0x00.section Syntax PTX section definition.0.debug_info . . Source file information. . Debugging Directives: .b8 0x00. Directives Table 140.Chapter 10.232-1] . 2010 167 ..file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.section .section . 0x00. 0x00 0x61395a5f.b8 0x2b. . 0x736d6172 0x00 Table 141.debug_pubnames { . 0x00000364.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } 0x02. Debugging Directives: . Source file location.file .b64 int64-list // comma-separated list of integers in range [0. .loc .b32 int32-list // comma-separated list of integers in range [0. . 0x00.255] .

.global .visible .extern .visible identifier Declares identifier to be externally visible.extern .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures.visible . Linking Directives: . Linking Directives: . // foo will be externally visible 168 January 24. .0. .0 10.global .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. .b32 foo. // foo is defined in another module Table 144.extern . Supported on all target architectures. Introduced in PTX ISA version 1.0. Linking Directives .6.PTX ISA Version 2. Introduced in PTX ISA version 1.extern identifier Declares identifier to be defined externally.visible Table 143.b32 foo. 2010 .

Chapter 11.0 driver r195 PTX ISA Version PTX ISA 1.3 PTX ISA 1.2 CUDA 2. CUDA Release CUDA 1. and the remaining sections provide a record of changes in previous releases.0. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 January 24. 2010 169 .3 driver r190 CUDA 3.2 PTX ISA 1. The release history is as follows.1 PTX ISA 1.5 PTX ISA 2.1 CUDA 2.0 PTX ISA 1.4 PTX ISA 1.1 CUDA 2.0 CUDA 2.

f32 requires sm_20. mad. When code compiled for sm_1x is executed on sm_20 devices. rcp. fma. • • • • • 170 January 24.ftz modifier may be used to enforce backward compatibility with sm_1x.1.0 11.1.0 11. and mul now support . The goal is to achieve IEEE 754 compliance wherever possible.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 and mad.1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. These are indicated by the use of a rounding modifier and require sm_20.1. Both fma.1. Single-precision add.f32 for sm_20 targets. Single.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. A single-precision fused multiply-add (fma) instruction has been added.and double-precision div.0 for sm_20 targets.PTX ISA Version 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32.rm and .f32 maps to fma. The mad.1.rp rounding modifiers for sm_20 targets. 2010 . The . The fma.x code and sm_1x targets. New Features 11. and sqrt with IEEE 754 compliant rounding have been added. The mad. The changes from PTX ISA 1.f32 require a rounding modifier for sm_20 targets. while maximizing backward compatibility with legacy PTX 1.rn.f32 instruction also supports . Floating-Point Extensions This section describes the floating-point changes in PTX 2.ftz and . sub. Changes in Version 2. Instructions testp and copysign have been added.sat modifiers.

bar now supports optional thread count and register operands. and sust.popc. A “population count” instruction. A “bit reversal” instruction.add. A new directive. has been added.3. and red now support generic addressing. .red. popc. A “count leading zeros” instruction.pred have been added.or}.red. for prefetching to specified level of memory hierarchy.section. %clock64.lt. bfe and bfi. Instructions {atom. st. A system-level membar instruction.1. Bit field extract and insert instructions.arrive instruction has been added. ldu. prefetch. and shared addresses to generic address and vice-versa has been added. has been added.1. atom. st.1.shared have been extended to handle 64-bit data types for sm_20 targets. membar.clamp and . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.ballot. Instruction cvta for converting global. isspacep. suld. 11.f32 have been implemented.ge. New special registers %nsmid. Instructions prefetch and prefetchu have also been added. Surface instructions support additional .1.gt} have been added. Instructions {atom.minnctapersm to better match its behavior and usage. has been added. Cache operations have been added to instructions ld. prefetchu.zero. A “find leading non-sign bit” instruction.maxnctapersm directive was deprecated and replaced with . vote. local.Chapter 11.2. Instructions bar. cvta. e. has been added.b32.g. New instructions A “load uniform” instruction. %lanemask_{eq. January 24. has been added. The bar instruction has been extended as follows: • • • A bar. 2010 171 . has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. bfind.u32 and bar.red}.red}. Release Notes 11.le. Other new features Instructions ld.sys. has been added.clamp modifiers. The . . A “vote ballot” instruction. have been added. Video instructions (includes prmt) have been added. has been added. clz. Instruction sust now supports formatted surface stores. brev. ldu.{and.

has been fixed.p sust.target sm_1x. cvt. 172 January 24. the correct number is sixteen.f32.s32. See individual instruction descriptions for details. Formatted surface store with .{min. Formatted surface load is unimplemented.5.ftz for PTX ISA versions 1. 11.f32 type is unimplemented. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. if . The underlying.p.5 and later.u32. Support for variadic functions and alloca are unimplemented.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.1. where . The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.3.f32} atom.ftz (and cvt for . {atom.4 and earlier.PTX ISA Version 2. stack-based ABI is unimplemented.{u32.s32.1. 2010 . Semantic Changes and Clarifications The errata in cvt. call suld. Instruction bra. .max} are not implemented. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.4 or earlier. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.red}. In PTX version 1. or . To maintain compatibility with legacy PTX code.2.0 11.version is 1.

the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Descriptions of . including loops preceding the . { … } // do not unroll any loop in this function . L1_body: … L1_continue: bra L1_head.pragma strings defined by ptxas. Table 145.pragma “nounroll”.func bar (…) { … L1_head: .Appendix A.pragma “nounroll”. and statement levels. 2010 173 . disables unrolling for all loops in the entry function body. disables unrolling of0 the loop for which the current block is the loop header. The “nounroll” pragma is allowed at module. . . … @p bra L1_end.pragma “nounroll”. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.0. L1_end: … } // do not unroll this loop January 24. entry-function. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Supported only for sm_20 targets.pragma. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.entry foo (…) . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. Note that in order to have the desired effect at statement level. Ignored for sm_1x targets.pragma Strings This section describes the .

2010 .0 174 January 24.PTX ISA Version 2.

Information furnished is believed to be accurate and reliable. DRAWINGS. No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation. Specifications mentioned in this publication are subject to change without notice. OR OTHERWISE WITH RESPECT TO THE MATERIALS. EXPRESSED. “MATERIALS”) ARE BEING PROVIDED “AS IS. REFERENCE BOARDS. STATUTORY. Copyright © 2010 NVIDIA Corporation. This publication supersedes and replaces all information previously supplied. . Trademarks NVIDIA. AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY. the NVIDIA logo. NVIDIA Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation. CUDA. DIAGNOSTICS. AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT.” NVIDIA MAKES NO WARRANTIES. MERCHANTABILITY. IMPLIED. All rights reserved. However. LISTS. NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use. FILES. and Tesla are trademarks or registered trademarks of NVIDIA Corporation in the United States and other countries. Other company and product names may be trademarks of the respective companies with which they are associated. AND FITNESS FOR A PARTICULAR PURPOSE.Notice ALL NVIDIA DESIGN SPECIFICATIONS.