NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

..........4.................................4..... State Spaces .......................................................5.............1.............................................. and Vectors ....... 5..........................6. 5....... Abstracting the ABI .......................................... 34 Variables ........4........................................... 38 Alignment .......................4............................................ 5............... Arrays..... 2010 .............................................................................................................. Summary of Constant Expression Evaluation Rules ................................................1........4.........4.................1.................................................................. Types .......................................4............................... 5.....1............................... 5................................................ 39 Parameterized Variable Names .... 5..................................4.......................................1...... 46 6...........................................8...........................3.. 6...............................................................4........................................2....................... 43 6...................1......................................................................5...................................................................... 44 Scalar Conversions ..............3..............5.......2.......................................................................................................... 6........ 25 Chapter 5............................ Operand Costs ...................................................2... 32 5......... 28 Special Register State Space ................PTX ISA Version 2... 42 Arrays as Operands ............................... 29 Global State Space .......................1............................................................ 29 Parameter State Space .....................................................2.......................................... 5.........2. 5.......... 5........0 4......1..............2. 28 Constant State Space .... 5. 5.............. 32 Texture State Space (deprecated) ......................7...........................1............................1............................. 30 Shared State Space....................................... and Surface Types ....3..............................................4.... 42 Addresses as Operands .................. 37 Array Declarations ..........................................................................................................................................................4............................... Function declarations and definitions .........1....................... 27 Register State Space .....1.............................. 43 Vectors as Operands ............................ and Variables .... 41 Source Operands.....................6.......... 29 Local State Space ...... 33 Fundamental Types ....... 6.. Texture....... 39 5.................. 6.................5.. 47 Chapter 7................................. Type Conversion.................3............................... 5............ 37 Vectors ............. 38 Initializers ................. 49 ii January 24...................... Operand Type Information ........................... 6.......................................1.........................................................................4......4.2.................... 44 Rounding Modifiers ......4..................4................3........................................1................... 6................. 41 Destination Operands ................................................ 41 Using Addresses............ 5................. 5........................2........ Chapter 6...2.......................................... 33 5................................. 49 7............................................................. 43 Labels and Function Names as Operands ......... 27 5................. Types............... 6............................ 37 Variable Declarations .....5.........................................................................................................6............................. 5...........................1........................... 41 6.... State Spaces............................................... 5....... 33 Restricted Use of Sub-Word Sizes ....1................ 6... Sampler......................................................................6.......5...... Instruction Operands.................. 6.............

................................... 8......................7.......7...7................4.............. 2010 iii ...................................... 132 Video Instructions .......................... 104 Data Movement and Conversion Instructions ...................................... 10..................................1.....................1.............. 149 Chapter 10....................2.... 162 Debugging Directives .......... 11..............................................1....................3.............................5..........................3............................ Changes from PTX 1...... 81 Comparison and Selection Instructions ..... 147 8..........................0 .... Release Notes ......... Chapter 9......... 172 January 24.10....................... Directives .................................................... 170 New Features ...9........................... 8.........................................................................................7.............5... 8.................... Format and Semantics of Instruction Descriptions ................. 108 Texture and Surface Instructions .................6....... 160 Performance-Tuning Directives ......................2.................................................. 63 Integer Arithmetic Instructions ....1..2.................. 62 Machine-Specific Semantics of 16-bit Code ..................... 172 Unimplemented Features Remaining ......................... 10...................................... Instruction Set ............................ 8....................7........ 100 Logic and Shift Instructions ........................... 59 Operand Size Exceeding Instruction-Type Size .................. 11....... PTX Version and Target Directives ......... Changes in Version 2........... 52 Variadic functions ................... 11......... 60 8.............................. Type Information for Instructions and Operands .......x ................................1.......................... 8............ 8.............1. 8............................................................................................................................................................... 55 8....................... 57 Manipulating Predicates ......... 168 Chapter 11........................... 157 10......7.......................7... 8... Divergence of Threads in Control Constructs ........ 62 Semantics . 63 Floating-Point Instructions .................. 8...................... 10......7.........7.1.................................... 7...........................1................................... 62 8.................................... 8............7......7......................1.......................................................................1.....................3......................................................................7..... 170 Semantic Changes and Clarifications ................................ 56 Comparisons ................................3........... 58 8............ 169 11..................... 140 Miscellaneous Instructions............................................3...3.......................7............1........... 8........ 8............................. 55 PTX Instructions ..................................6.3...................2.......2............................................................... 122 Control Flow Instructions .............................................................................. Instructions ......... 7.............. 53 Alloca .................... 55 Predicated Execution . 10.....................1................... 54 Chapter 8......................................................................................4......................... 8..................................................................... 8.... 8.........................4...........................................................................................................................................................................6.................................6..........................................................8........................ 129 Parallel Synchronization and Communication Instructions ................... 166 Linking Directives ..........................2...............................1........................................................... 157 Specifying Kernel Entry Points and Functions ...4........................................................... Special Registers .......................................... 8.........

173 iv January 24....0 Appendix A................. Descriptions of .......... 2010 ...............pragma Strings.....PTX ISA Version 2.................

................................................................ Table 20.List of Tables Table 1... 18 Reserved Instruction Keywords .............................................................................. 71 January 24... Table 31................ Table 26............. Table 2............................................cc ........................................... 65 Integer Arithmetic Instructions: sub.......................................................................................................................... 47 Operators for Signed Integer. Table 8........................................................................ Table 12............................ 58 Type Checking Rules ............................................................ 25 State Spaces ......................................................................................................................................................................................................... Table 28................................................................... and Bit-Size Types ............ 66 Integer Arithmetic Instructions: subc ...... 35 Opaque Type Fields in Independent Texture Mode ................ 58 Floating-Point Comparison Operators Testing for NaN ...................... Table 30............................................................................................. Table 24..... Table 7................... Unsigned Integer................................... Table 10.............. 57 Floating-Point Comparison Operators Accepting NaN .......... 20 Operator Precedence . Table 18............. Table 9............. 23 Constant Expression Evaluation Rules ............................... Table 5.................................. Table 6............... 60 Relaxed Type-checking Rules for Destination Operands.............. 35 Convert Instruction Precision and Format . Table 13........................................ Table 11.......................... 65 Integer Arithmetic Instructions: addc .. Table 4........................................................................ 46 Cost Estimates for Accessing State-Spaces .... Table 16...... PTX Directives ... 69 Integer Arithmetic Instructions: mad24 .................................................... 68 Integer Arithmetic Instructions: mul24 ................................................ 2010 v ................................ 57 Floating-Point Comparison Operators ......................................................................................... Table 25............................................................................................................................................................ 27 Properties of State Spaces ........ 64 Integer Arithmetic Instructions: sub .......................cc ................ 61 Integer Arithmetic Instructions: add ............................... 59 Relaxed Type-checking Rules for Source Operands ............................................................ Table 21........................ 64 Integer Arithmetic Instructions: add............................................................ Table 19............................. Table 27........ Table 22................................................. Table 14.. 67 Integer Arithmetic Instructions: mad .... Table 3.......................... 46 Integer Rounding Modifiers .. 66 Integer Arithmetic Instructions: mul ................................... 28 Fundamental Type Specifiers ...................... Table 15........................ 33 Opaque Type Fields in Unified Texture Mode ............................................................... Table 29............ Table 17............. Table 32........ 19 Predefined Identifiers ................................................... 70 Integer Arithmetic Instructions: sad .............................................. Table 23........... 45 Floating-Point Rounding Modifiers ...

........................................ Table 59................................................................................. 99 Comparison and Selection Instructions: set ................................. 85 Floating-Point Instructions: mul ............... Table 40................ 2010 ......................... 96 Floating-Point Instructions: cos ..................... 94 Floating-Point Instructions: rsqrt ............................................................................... Table 69........................... 72 Integer Arithmetic Instructions: neg ........ Table 62................ 103 Comparison and Selection Instructions: slct .................................. Table 57................. Table 65........................................................................... 97 Floating-Point Instructions: lg2 ........................................ Table 50............................................................. 88 Floating-Point Instructions: div ..................................................................................................... Table 39..................................... 92 Floating-Point Instructions: max ............................... Table 61................................................................ Table 67......................................................................... Table 42......... Table 51............................................... Table 37...... 91 Floating-Point Instructions: neg . Integer Arithmetic Instructions: div ............................................ Table 68............ Table 41............ Table 36........................................ 74 Integer Arithmetic Instructions: bfind .............................................. Table 45.............................................. Table 46................. Table 44................................................ 84 Floating-Point Instructions: sub .................... 73 Integer Arithmetic Instructions: popc ............................ Table 47........... 79 Summary of Floating-Point Instructions .............. Table 43...................................................................... 101 Comparison and Selection Instructions: setp ............. 98 Floating-Point Instructions: ex2 ........................................ Table 53.................................................. 86 Floating-Point Instructions: fma ........................0 Table 33................................PTX ISA Version 2.............. Table 66........................... 77 Integer Arithmetic Instructions: bfi ..................... Table 64....................... 74 Integer Arithmetic Instructions: clz ........ 71 Integer Arithmetic Instructions: rem ...... 78 Integer Arithmetic Instructions: prmt ...................................... 91 Floating-Point Instructions: min .................................................. 76 Integer Arithmetic Instructions: bfe .......................................................... 75 Integer Arithmetic Instructions: brev . Table 35.......................................................... Table 58..................................................... Table 63................................................................................................... 82 Floating-Point Instructions: testp ...................................................................... 73 Integer Arithmetic Instructions: max ................................................................................ Table 52........................................................................................................ Table 38..... 93 Floating-Point Instructions: sqrt ........... 90 Floating-Point Instructions: abs ..... 83 Floating-Point Instructions: add ...................... 103 vi January 24............................. 71 Integer Arithmetic Instructions: abs ......................... 83 Floating-Point Instructions: copysign ............. 92 Floating-Point Instructions: rcp .............................. Table 54......................................... Table 60.... Table 34............................................... Table 56.......................................................... Table 49.............................. 95 Floating-Point Instructions: sin ......................................... Table 48...................... 87 Floating-Point Instructions: mad ................. 102 Comparison and Selection Instructions: selp ............................. Table 55.............................................................. 72 Integer Arithmetic Instructions: min .......................................................................................

. 135 Parallel Synchronization and Communication Instructions: red ................................ Table 106................................................................ 111 Data Movement and Conversion Instructions: mov ..... Table 84........................................ 107 Cache Operators for Memory Load Instructions ................................. 106 Logic and Shift Instructions: not ............... 105 Logic and Shift Instructions: or .......................................... 119 Data Movement and Conversion Instructions: cvta ........ 134 Parallel Synchronization and Communication Instructions: atom ........... Table 100...... Table 83................ Table 76............. 106 Logic and Shift Instructions: shl ............ vsub... 133 Parallel Synchronization and Communication Instructions: membar .. Table 77................................. vmax .................................................................................................... Table 78...................... Table 81............................................. 125 Texture and Surface Instructions: sust ........................................................................ Table 86......... 120 Texture and Surface Instructions: tex .... vmin.................................... 107 Logic and Shift Instructions: shr ....... Table 95.................................... Table 75................. Table 96................................... Table 88................. 131 Control Flow Instructions: exit ................ 127 Texture and Surface Instructions: suq ............ Table 90......... 139 Video Instructions: vadd. Table 87................................................................................ Table 71.......... Table 102... Table 80.............................................. 2010 vii ............. 112 Data Movement and Conversion Instructions: ld .......... 129 Control Flow Instructions: bra .............................. Table 99... Logic and Shift Instructions: and ................. 129 Control Flow Instructions: @ .................................... Table 74................... 115 Data Movement and Conversion Instructions: st . prefetchu ...................................................................................................................................... 113 Data Movement and Conversion Instructions: ldu ............................... vshr ........................ 143 January 24................ Table 104....................... 123 Texture and Surface Instructions: txq ............................................ Table 93............. 118 Data Movement and Conversion Instructions: isspacep .................................................................. Table 85....... Table 98................ Table 97........................................... Table 82.. 128 Control Flow Instructions: { } .................................. 137 Parallel Synchronization and Communication Instructions: vote ................................ Table 94........................... 110 Data Movement and Conversion Instructions: mov ........................................................... Table 105. Table 92.............. Table 73.......................................... 105 Logic and Shift Instructions: xor ........ Table 101........... Table 79................................ 131 Parallel Synchronization and Communication Instructions: bar ......................................... Table 103...... 126 Texture and Surface Instructions: sured........... 130 Control Flow Instructions: ret ......................... Table 91.............................. Table 72. 109 Cache Operators for Memory Store Instructions ............................................................. 124 Texture and Surface Instructions: suld ............................................................................ 116 Data Movement and Conversion Instructions: prefetch.... 130 Control Flow Instructions: call .............................. 142 Video Instructions: vshl..............Table 70........................... 119 Data Movement and Conversion Instructions: cvt ........... vabsdiff........................................................ 106 Logic and Shift Instructions: cnot ..... Table 89..............................................................................................................

........ 154 Special Registers: %lanemask_lt .....................maxntid ..... Table 121....... Table 112....... 152 Special Registers: %nctaid ............... 147 Miscellaneous Instructions: brkpt .................................................................... Table 129......................................................................................... Table 128............................................. 150 Special Registers: %laneid .......................................... 156 Special Registers: %pm0..... 147 Miscellaneous Instructions: pmevent.................... Table 122..................section ................... Table 137.......... Table 114.....................................version.................. Table 126.............................................................................................................. Table 138........................................... 168 viii January 24........ Table 113.................. Table 111..........................................................................0 Table 107..................... 153 Special Registers: %nsmid ........PTX ISA Version 2........................... Table 134................. %pm2............................................................................................extern.... 165 Debugging Directives: @@DWARF .........func ............pragma .......................... 154 Special Registers: %lanemask_ge .. Table 132.................................................. Table 118.............entry............................ 161 Performance-Tuning Directives: ............................................. Table 124........ 155 Special Registers: %lanemask_gt .......................................................... 158 Kernel and Function Directives: ............................. Table 139............................................................................................... 164 Performance-Tuning Directives: ... Table 142.................. Table 120.......................... %pm1.. Table 143..................................................... 151 Special Registers: %nwarpid .............................................................. 147 Special Registers: %tid .......................... Table 115............................................................................................. Table 116.............. 151 Special Registers: %ctaid .................................. 163 Performance-Tuning Directives: ................. 154 Special Registers: %lanemask_le .............. 146 Miscellaneous Instructions: trap ....... 152 Special Registers: %smid ....... 153 Special Registers: %lanemask_eq ................................................................ %pm3 .................................................. Table 136....................... 160 Kernel and Function Directives: ................................................. 157 PTX File Directives: ......loc ...............................................maxnreg ........................... Table 141.... Table 108...file ........... Table 123................................................................................................... 167 Linking Directives: ................. Table 125.................. 156 PTX File Directives: ............ 163 Performance-Tuning Directives: ............................. Video Instructions: vmad ....................... 150 Special Registers: %ntid ........ 155 Special Registers: %clock ................................. 167 Debugging Directives: ... 151 Special Registers: %warpid ...............maxnctapersm (deprecated) ... 144 Video Instructions: vset.................. 167 Debugging Directives: ............... Table 130................................................................................................................. 164 Performance-Tuning Directives: ................................................................................................... 2010 .................. Table 110............................................ Table 117...... Table 133....................................target ......... 153 Special Registers: %gridid ...................................................................... Table 140......minnctapersm . 166 Debugging Directives: ............................................................... Table 109.......................... 156 Special Registers: %clock64 . Table 131..... Table 127......... Table 119................................. Table 135.................

. 168 Pragma Strings: “nounroll” ................ Linking Directives: ....................................... 2010 ix .... 173 January 24......visible..................................Table 144................................................... Table 145....................

2010 .PTX ISA Version 2.0 x January 24.

1. the programmable GPU has evolved into a highly parallel. image scaling. Because the same program is executed for each data element.Chapter 1. 1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). which are optimized for and translated to native target-architecture instructions.2. In fact. Introduction This document describes PTX. the memory access latency can be hidden with calculations instead of big data caches. PTX defines a virtual machine and ISA for general purpose parallel thread execution. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. high-definition 3D graphics. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Data-parallel processing maps data elements to parallel processing threads. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. Similarly. from general signal processing or physics simulation to computational finance or computational biology. 2010 1 . and because it is executed on many data elements and has high arithmetic intensity. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. and pattern recognition can map image blocks and pixels to parallel processing threads. stereo vision. 1. multithreaded. many-core processor with tremendous computational horsepower and very high memory bandwidth. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. PTX programs are translated at install time to the target hardware instruction set. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. there is a lower requirement for sophisticated flow control. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. video encoding and decoding. PTX exposes the GPU as a data-parallel computing device. January 24. image and media processing applications such as post-processing of rendered images. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time.

PTX ISA Version 2.rn.ftz and . and architecture tests. Most of the new features require a sm_20 target.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. A “flush-to-zero” (. Instructions marked with . surface. Achieve performance in compiled applications comparable to native GPU performance.0 is in improved support for the IEEE 754 floating-point standard. addition of generic addressing to facilitate the use of general-purpose pointers. The fma. The main areas of change in PTX 2. 1.rp rounding modifiers for sm_20 targets.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. and video instructions. The mad.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Legacy PTX 1. • • • 2 January 24. fma.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.x code will continue to run on sm_1x targets as well. 2010 . Provide a common source-level ISA for optimizing code generators and translators. and the introduction of many new instructions.f32 and mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 for sm_20 targets. PTX ISA Version 2. When code compiled for sm_1x is executed on sm_20 devices. The changes from PTX ISA 1. sub. Facilitate hand-coding of libraries. barrier. Provide a machine-independent ISA for C/C++ and other compilers to target.x features are supported on the new sm_20 target.f32 requires sm_20. PTX 2.rm and . extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Single-precision add. and mul now support .0 are improved support for IEEE 754 floating-point operations.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. performance kernels. which map PTX to specific target machines. A single-precision fused multiply-add (fma) instruction has been added.f32 require a rounding modifier for sm_20 targets. mad.1.ftz) modifier may be used to enforce backward compatibility with sm_1x.f32 instruction also supports . The mad. Improved Floating-Point Support A main area of change in PTX 2.f32 maps to fma. and all PTX 1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.3.0 is a superset of PTX 1. Provide a code distribution ISA for application and middleware developers. reduction.sat modifiers.0 PTX ISA Version 2. atomic. memory. 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.x.f32. Both fma.3. including integer.

3.Chapter 1. instructions ld. and Application Binary Interface (ABI). • Taken as a whole. Surface Instructions • • Instruction sust now supports formatted surface stores.e. Instructions testp and copysign have been added. Cache operations have been added to instructions ld.3. .g. 1. e. local. Support for an Application Binary Interface Rather than expose details of a particular calling convention. and shared addresses to generic addresses. Generic Addressing Another major change is the addition of generic addressing. st. These are indicated by the use of a rounding modifier and require sm_20. stack-based ABI.0. stack layout. January 24.3. Surface instructions support additional clamp modifiers. allowing memory instructions to access these spaces without needing to specify the state space. st. New Instructions The following new instructions. and sust. Introduction • Single. 2010 3 . local. local. A new cvta instruction has been added to convert global.. In PTX 2. and shared addresses to generic address and vice-versa has been added. and directives are introduced in PTX 2. cvta. prefetchu. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. and red now support generic addressing. 1. ldu. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. prefetch. 1. NOTE: The current version of PTX does not implement the underlying.clamp and . Instructions prefetch and prefetchu have been added.0. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.and double-precision div. for prefetching to specified level of memory hierarchy. special registers.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.3. atom. and shared state spaces. these changes bring PTX 2. isspacep. so recursion is not yet supported. Generic addressing unifies the global. rcp.4. i. an address that is the same across all threads in a warp.zero. PTX 2. and vice versa.0 closer to full compliance with the IEEE 754 standard. suld.2. Instruction cvta for converting global. and sqrt with IEEE 754 compliant rounding have been added.

section. has been added. %lanemask_{eq.pred have been added. membar. Reduction. . vote.le.f32 have been added. Barrier Instructions • • A system-level membar instruction.add.ballot.red. Other Extensions • • • Video instructions (includes prmt) have been added.ge. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.{and.or}.arrive instruction has been added.sys. 2010 . Instructions bar.u32 and bar.b32. A “vote ballot” instruction. A new directive.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. Instructions {atom. New special registers %nsmid. has been added.popc.lt.shared have been extended to handle 64-bit data types for sm_20 targets. 4 January 24. %clock64.gt} have been added.red. A bar. bar now supports an optional thread count and register operands.PTX ISA Version 2. bfi bit field extract and insert popc clz Atomic.red}. and Vote Instructions • • • New atomic and reduction instructions {atom.red}.

Chapter 5 describes state spaces. Chapter 9 lists special registers. types.0. Chapter 8 describes the instruction set. Chapter 6 describes instruction operands. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and variable declarations. Chapter 7 describes the function and call syntax. 2010 5 .Chapter 1. Chapter 11 provides release notes for PTX Version 2. Introduction 1. calling convention. Chapter 3 gives an overview of the PTX virtual machine model. January 24. Chapter 4 describes the basic syntax of the PTX language.4. Chapter 10 lists the assembly directives supported in PTX. and PTX support for abstracting the Application Binary Interface (ABI).

2010 .PTX ISA Version 2.0 6 January 24.

The vector ntid specifies the number of threads in each CTA dimension. More precisely. Threads within a CTA can communicate with each other.x. one can specify synchronization points where threads wait until all threads in the CTA have arrived.z) that specifies the thread’s position within a 1D.Chapter 2. The thread identifier is a three-element vector tid. To that effect. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. and tid. work. It operates as a coprocessor to the main CPU. compute addresses.2. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. (with elements tid. 2D. A cooperative thread array.z). Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.y. assign specific input and output positions. To coordinate the communication of the threads within the CTA. Each thread has a unique thread identifier within the CTA. or 3D CTA.2.y. a portion of an application that is executed many times. 2D. can be isolated into a kernel function that is executed on the GPU as many different threads. or 3D shape specified by a three-element vector ntid (with elements ntid.1. 2. and select work to perform. tid. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. Programs use a data parallel decomposition to partition inputs. ntid. compute-intensive portions of applications running on the host are off-loaded onto the device. and results across the threads of the CTA. 2. Each CTA thread uses its thread identifier to determine its assigned role. 2010 7 .1. Programming Model 2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. or CTA. and ntid. but independently on different data. or host: In other words. Each CTA has a 1D. data-parallel. January 24.x. Cooperative thread arrays (CTAs) implement CUDA thread blocks. is an array of threads that execute a kernel concurrently or in parallel.

The warp size is a machine-dependent constant. CTAs that execute the same kernel can be batched together into a grid of CTAs. so that the total number of threads that can be launched in a single kernel invocation is very large. Multiple CTAs may execute concurrently and in parallel. Threads may read and use these values through predefined. Threads within a warp are sequentially numbered. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1).PTX ISA Version 2. %ntid.2. and %gridid. because threads in different CTAs cannot communicate and synchronize with each other. The host issues a succession of kernel invocations to the device. depending on the platform. or 3D shape specified by the parameter nctaid. 8 January 24. 2D . However. a warp has 32 threads. 2. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. This comes at the expense of reduced thread communication and synchronization.0 Threads within a CTA execute in SIMT (single-instruction. multiple-thread) fashion in groups called warps. Typically. Each grid also has a unique temporal grid identifier (gridid). %nctaid. %ctaid. WARP_SZ. A warp is a maximal subset of threads from a single CTA. or sequentially. such that the threads execute the same instructions at the same time.2. read-only special registers %tid. which may be used in any instruction where an immediate operand is allowed. Each grid of CTAs has a 1D. so PTX includes a run-time immediate constant. Some applications may be able to maximize performance with knowledge of the warp size. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 2010 .

2) Thread (2. 0) Thread (2. 1) Thread (0. 0) Thread (4. 0) CTA (1. 1) CTA (2. 2) Thread (3. 1) Thread (4. 1) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program.Chapter 2. 1) Thread (2. 1) Thread (0. Figure 1. 2) Thread (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (4. 0) Thread (1. 0) Thread (3. 0) CTA (2. 2010 9 . 0) CTA (0. Thread Batching January 24. 1) Thread (1. A grid is a set of CTAs that execute independently. 1) CTA (1. 0) Thread (0.

copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. or. 2010 . and texture memory spaces are optimized for different memory usages. for more efficient transfer.PTX ISA Version 2. as well as data filtering. constant.3.0 2. The device memory may be mapped and read or written by the host. Both the host and the device maintain their own local memory. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. referred to as host memory and device memory. The global. all threads have access to the same global memory. Texture memory also offers different addressing modes. respectively. for some specific data formats. Finally. Each thread has a private local memory. and texture memory spaces are persistent across kernel launches by the same application. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. 10 January 24. constant.

Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (0.Chapter 2. 0) Block (1. 0) Block (0. Memory Hierarchy January 24. 0) Block (2. 1) Block (0. 2) Block (1. 2010 11 . 1) Block (1. 1) Block (2. 2) Figure 2. 1) Block (1. 0) Block (1. 1) Grid 1 Global memory Block (0.

PTX ISA Version 2.0 12 January 24. 2010 .

new blocks are launched on the vacated multiprocessors. Branch divergence occurs only within a warp. multiple-thread). so full efficiency is realized when all threads of a warp agree on their execution path.Chapter 3. When a host program invokes a kernel grid. it splits them into warps that get scheduled by the SIMT unit. The multiprocessor SIMT unit creates. 2010 13 . the warp serially executes each branch path taken. As thread blocks terminate. At every instruction issue time. If threads of a warp diverge via a data-dependent conditional branch. (This term originates from weaving. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. The threads of a thread block execute concurrently on one multiprocessor. and on-chip shared memory. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. manages. different warps execute independently regardless of whether they are executing common or disjointed code paths. disabling threads that are not on that path. Parallel Thread Execution Machine Model 3. increasing thread IDs with the first warp containing thread 0. and each scalar thread executes independently with its own instruction address and register state. manages. the threads converge back to the same execution path. A warp executes one common instruction at a time. a voxel in a volume. The multiprocessor maps each thread to one scalar processor core. The multiprocessor creates. It implements a single-instruction barrier synchronization. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. the first parallel thread technology. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). a cell in a grid-based computation). and executes threads in groups of parallel threads called warps. each warp contains threads of consecutive. and executes concurrent threads in hardware with zero scheduling overhead. for example. the multiprocessor employs a new architecture we call SIMT (single-instruction. allowing. The way a block is split into warps is always the same. When a multiprocessor is given one or more thread blocks to execute. A multiprocessor consists of multiple Scalar Processor (SP) cores. To manage hundreds of threads running several different programs. schedules. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. and when all paths complete.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. a multithreaded instruction unit.1. January 24.

Vector architectures. modifies. SIMT enables programmers to write thread-level parallel code for independent. 2010 . A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. As illustrated by Figure 3. modify. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. In practice. however. on the other hand. scalar threads. require the software to coalesce loads into vectors and manage divergence manually. and writes to the same location in global memory for more than one of the threads of the warp. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. each read. but one of the writes is guaranteed to succeed. the kernel will fail to launch. • The local and global memory spaces are read-write regions of device memory and are not cached. as well as data-parallel code for coordinated threads. 14 January 24. write to that location occurs and they are all serialized. whereas SIMT instructions specify the execution and branching behavior of a single thread. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. the programmer can essentially ignore the SIMT behavior. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. which is a read-only region of device memory. the number of serialized writes that occur to that location and the order in which they occur is undefined. which is a read-only region of device memory. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks.0 SIMT architecture is akin to SIMD (Single Instruction. If an atomic instruction executed by a warp reads. If there are not enough registers or shared memory available per multiprocessor to process at least one block. A multiprocessor can execute as many as eight thread blocks concurrently.PTX ISA Version 2. A key difference is that SIMD vector organizations expose the SIMD width to the software. For the purposes of correctness. In contrast with SIMD vector machines. but the order in which they occur is undefined. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. Multiple Data) vector organizations in that a single instruction controls multiple processing elements.

2010 15 . Figure 3.Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.

0 16 January 24.PTX ISA Version 2. 2010 .

#file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor.1. See Section 9 for a more information on these directives.Chapter 4. 4. and using // to begin a comment that extends to the end of the current line. followed by a . Pseudo-operations specify symbol and addressing management. Syntax PTX programs are a collection of text source files. Lines are separated by the newline character (‘\n’). #define. PTX is case sensitive and uses lowercase for keywords.2. using non-nested /* and */ for comments that may span multiple lines. January 24. The following are common preprocessor directives: #include. The C preprocessor cpp may be used to process PTX source files. #else. Lines beginning with # are preprocessor directives.version directive specifying the PTX language version. Comments in PTX are treated as whitespace. #line. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 4. #ifdef. Comments Comments in PTX follow C/C++ syntax. All whitespace characters are equivalent. #endif. whitespace is ignored except for its use in separating tokens in the language. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. 2010 17 . #if. Each PTX file must begin with a .target directive specifying the target architecture assumed. Source Format Source files are ASCII text.

3. and terminated with a semicolon. ld.local . 2. r1. The guard predicate follows the optional label and precedes the opcode. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.entry . 2010 .f32 r2.b32 add.0 4. 18 January 24. constant expressions. . r2.minnctapersm .x.loc . %tid. Instructions have an optional guard predicate which controls conditional execution.maxnreg . Instruction keywords are listed in Table 2. Operands may be register variables. or label names.func .PTX ISA Version 2.b32 r1.visible 4.3.align .global start: .b32 r1.file PTX Directives . All instruction keywords are reserved tokens in PTX.version . shl. r2.2.param . address expressions. The destination operand is first. r2.extern .3.shared . Examples: .maxnctapersm . so no conflict is possible with user-defined identifiers.global. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.1.f32 array[N]. written as @!p.section . Statements begin with an optional label and end with a semicolon.maxntid .sreg . where p is a predicate register. Table 1. The guard predicate may be optionally negated. and is written as @p. array[r1].5.reg .tex . followed by source operands.pragma .const . Directive Statements Directive keywords begin with a dot. 0. Statements A PTX statement is either a directive or an instruction.target . . mov.reg . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.global .b32 r1.

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4. Syntax Table 2. 2010 19 .

digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign. The percentage sign can be used to avoid name conflicts. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.0 4. PTX allows the percentage sign as the first character of an identifier. or percentage character followed by one or more letters. 2010 . except that the percentage sign is not allowed.4.g. dollar. or dollar characters. %pm3 WARP_SZ 20 January 24. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. digits. between user-defined variable names and compiler-generated names. or they start with an underscore. underscore.PTX ISA Version 2. …. listed in Table 3. underscore. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. e. Many high-level languages such as C and C++ follow similar rules for identifier names. Table 3.

Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use..s64 or . The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. floating-point. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Floating-point literals may be written with an optional decimal point and an optional signed exponent. there is no suffix letter to specify size. where the behavior of the operation depends on the operand types. Syntax 4.5.2. integer constants are allowed and are interpreted as in C. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. Unlike C and C++. To specify IEEE 754 doubleprecision floating point values. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. and bit-size types.u64). Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. or binary notation. The syntax follows that of C.5.. These constants may be used in data initialization and as operands to instructions.e. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. When used in an instruction or data initialization. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. Constants PTX supports integer and floating-point constants and constant expressions. the constant begins with 0f or 0F followed by 8 hex digits.u64. in which case the literal is unsigned (. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Type checking rules remain the same for integer. i. the constant begins with 0d or 0D followed by 16 hex digits. octal. 2010 21 . hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.5. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. literals are always represented in 64-bit double-precision format. Integer literals may be written in decimal. zero values are FALSE and non-zero values are TRUE. every integer constant has type . To specify IEEE 754 single-precision floating point values. 0[fF]{hexdigit}{8} // single-precision floating point January 24.Chapter 4.1.s64) unless the value cannot be fully represented in . For predicate-type data and instructions. i. hexadecimal. each integer constant is converted to the appropriate size based on the data or instruction type at its use.e. 4. 4.s64 or the unsigned suffix is specified.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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f64 use usual conversions .s64. or . Syntax 4.f64 use usual conversions .u64.6.s64 . . 2nd is .f64 use usual conversions . 2010 25 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .f64 same as source .f64 integer .f64 : .5.f64 integer .u64 .u64 same as 1st operand .s64 .s64 .s64) + . Table 5.u64 .u64 .s64 .u64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 integer integer integer integer integer int ?.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .u64) (.u64 .Chapter 4.f64 converted type .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 1st unchanged.s64 .s64 .s64 .f64 converted type constant literal + ! ~ Cast Binary (. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .

PTX ISA Version 2.0 26 January 24. 2010 .

Types. defined per-grid. addressability. and these resources are abstracted in PTX through state spaces and data types. The characteristics of a state space include its size.reg .global .1. 2010 27 .Chapter 5. Table 6. fast. platform-specific. Global memory. 5. read-only memory. and level of sharing between threads. Name State Spaces Description Registers. and properties of state spaces are shown in Table 5. Shared. The list of state spaces is shown in Table 4. access rights.sreg .shared . access speed.tex January 24. pre-defined. State Spaces. Read-only. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. shared by all threads. private to each thread. defined per-thread.param . . Global texture memory (deprecated).const . Special registers. Addressable memory shared between threads in 1 CTA. Local memory.local . and Variables While the specific resources available in a given target GPU will vary. the kinds of resources will be common across platforms. Kernel parameters. All variables reside in some state space. State Spaces A state space is a storage area with particular characteristics. or Function or local parameters.

or 128-bits. The most common use of 8-bit registers is with ld. 64-.e. 2010 .param instructions. or 64-bits. The number of registers is limited. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Registers may be typed (signed integer.1. 32-.1. For each architecture. and cvt instructions. 32-..const . floating point.local state space.1. it is not possible to refer to the address of a register. unsigned integer. such as grid. 2 Accessible via ld.2. i. and performance monitoring registers. scalar registers have a width of 8-.tex Restricted Yes No3 5. and vector registers have a width of 16-. aside from predicate registers which are 1-bit. 16-. Register State Space Registers (. register variables will be spilled to memory. the parameter is then located on the stack frame and its address is in the . Registers may have alignment boundaries required by multi-word loads and stores. Registers differ from the other state spaces in that they are not fully addressable. platform-specific registers. Special Register State Space The special register (.sreg . clock counters. predicate) or untyped. or as elements of vector tuples. 1 Accessible only via the ld.param and st. Device function input parameters may have their address taken via mov. 28 January 24.sreg) state space holds predefined. and will vary from platform to platform.param (as input to kernel) . st. 5. When the limit is exceeded. and thread parameters. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.param (used in functions) . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). Register size is restricted. Address may be taken via mov instruction. 3 Accessible only via the tex instruction. causing changes in performance. All special registers are predefined. CTA.shared .0 Table 7.reg state space) are fast storage locations.reg .global .param instruction.PTX ISA Version 2.local .

local to access local variables. All memory writes prior to the bar. for example). Use ld. results in const_buffer pointing to the start of constant bank two. If no bank number is given. For example. Consider the case where one thread executes the following two assignments: a = a + 1.global) state space is memory that is accessible by all threads in a context. the stack is in local memory. the store operation updating a may still be in flight. where bank ranges from 0 to 10.global.extern . and Variables 5. Sequential consistency is provided by the bar.b32 const_buffer[]. Global State Space The global (. the declaration . 5. [const_buffer+4]. // load second word 5. In implementations that support a stack. as it must be allocated on a perthread basis.sync instruction.const) state space is a read-only memory. This reiterates the kind of parallelism available in machines that run PTX. where the size is not known at compile time. Constant State Space The constant (. the bank number must be provided in the state space of the load instruction. initialized by the host. bank zero is used. State Spaces. Types. It is the mechanism by which different CTAs and different grids can communicate. Banks are specified using the . each pointing to the start address of the specified constant bank. Multiple incomplete array variables declared in the same bank become aliases. Global memory is not sequentially consistent. as in lock-free and wait-free style programming. By convention. To access data in contant banks 1 through 10. bank zero is used for all statically-sized constant variables.b32 const_buffer[].const[2] .1.3. Threads must be able to do their work without waiting for other threads to do theirs.b32 %r1. b = b – 1. ld. If another thread sees the variable b change.const[2].4.1. Use ld. It is typically standard memory with cache. an incomplete array in bank 2 is accessed as follows: . The remaining banks may be used to implement “incomplete” constant arrays (in C.const[2] . there are eleven 64KB banks. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.sync instruction are guaranteed to be visible to any reads after the barrier instruction.5. st.const[bank] modifier. This pointer can then be used to access the entire 64KB constant bank. all addresses are in global memory are shared. For example.global to access global variables. Local State Space The local state space (.1.Chapter 5. Threads wait at the barrier until all threads in the CTA have arrived. For the current devices. The size is limited. 2010 29 .local and st. and atom.local) is private memory for each thread to keep its own data. For any thread in a context. Module-scoped local memory variables are stored at fixed addresses.global. whereas local memory variables declared January 24. The constant memory is organized into fixed size banks.extern .

reg .param .param instructions. Therefore.u32 %n. [%ptr]. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.param space.param . read-only variables declared in the .PTX ISA Version 2.f64 %d. 5. Note: The location of parameter space is implementation specific. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param state space and is accessed using ld.param. Parameter State Space The parameter (. [N]. [buffer]. typically for passing large structures by value to a function.x supports only kernel function parameters in . all local memory variables are stored at fixed addresses and recursive function calls are not supported. mov.u32 %n. Note that PTX ISA versions 1.align 8 . No access protection is provided between parameter and global space in this case. … 30 January 24.reg . ld.1.param.param.u32 %n.entry bar ( .0 within a function or kernel body are allocated on the stack.b32 len ) { . .6. The use of parameter state space for device function parameters is new to PTX ISA version 2. These parameters are addressable. %n.1. The kernel parameter variables are shared across all CTAs within a grid. Values passed from the host to the kernel are accessed through these parameter variables using ld.1.param) state space is used (1) to pass input arguments from the host to the kernel.u32 %ptr.b32 N. 5. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param state space. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. . The resulting address is in the . For example. 2010 . … Example: .0 and requires target architecture sm_20.param instructions.6. device function parameters were previously restricted to the register state space. len.param . in some implementations kernel parameters reside in global memory. ld.param space variables. PTX code should make no assumptions about the relative locations or ordering of .entry foo ( .b8 buffer[64] ) { . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Example: .reg .f64 %d. ld. per-kernel versus per-thread). Similarly. In implementations that do not support a stack. The address of a kernel parameter may be moved into a register using the mov instruction.u32 %ptr.

Function input parameters may be read via ld. 2010 31 .param.param and function return parameters may be written using st.reg . Aside from passing structures by value. Example: // pass object of type struct { double d.reg .f64 [mystruct+0].reg . The most common use is for passing objects by value that do not fit within a PTX register. it is illegal to write to an input parameter or read from a return parameter. passed to foo … . which declares a .s32 %y. }.param. and so the address will be in the .b8 mystruct. . .func foo ( .param .param byte array variable that represents a flattened C structure or union.local state space and is accessed via ld. [buffer+8].s32 x. . a byte array in parameter space is used. … st. x. int y. is flattened.align 8 .f64 dbl.f64 %d. Device Function Parameters PTX ISA version 2. [buffer]. mystruct).1. … See the section on function call syntax for more details.s32 [mystruct+8]. Note that the parameter will be copied to the stack if necessary. dbl. .param. call foo.f64 %d.param space variable. the caller will declare a locally-scoped . State Spaces. such as C structures larger than 8 bytes.b8 buffer[12] ) { . January 24. Typically.local and st. and Variables 5.param .6. In PTX. In this case.reg . the address of a function input parameter may be moved into a register using the mov instruction. This will be passed by value to a callee. . st. .local instructions.param.reg .param.param space is also required whenever a formal parameter has its address taken within the called function. (4. ld.0 extends the use of parameter space to device function parameters.2.b32 N.s32 %y. int y.align 8 . ld. … } // code snippet from the caller // struct { double d. } mystruct. It is not possible to use mov to get the address of a return parameter or a locally-scoped .Chapter 5.param formal parameter having the same size and alignment as the passed argument. Types.

tex_c.shared to access shared variables.global . and programs should instead reference texture memory through variables of type . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Another is sequential access from sequential threads. Texture memory is read-only. See Section 5.tex directive is retained for backward compatibility.7. The .PTX ISA Version 2.shared and st.texref variables in the . tex_d. where all threads read from the same address.6 for its use in texture instructions.shared) state space is a per-CTA region of memory for threads in a CTA to share data. The texture name must be of type .3 for the description of the . tex_d.8.tex . tex_f.tex . 2010 . a legacy PTX definitions such as .u32 .u32 tex_a.tex directive will bind the named texture memory variable to a hardware texture identifier.texref. Example: . One example is broadcast.u32 . For example.u32 . and .7. Use ld.global state space. Shared memory typically has some optimizations to support the sharing. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 tex_a.tex variables are required to be defined in the global scope. An error is generated if the maximum number of physical resources is exceeded.tex state space are equivalent to module-scoped .tex .tex) state space is global memory accessed via the texture instruction. Multiple names may be bound to the same physical texture identifier. Texture State Space (deprecated) The texture (.1.texref tex_a.u64. A texture’s base address is assumed to be aligned to a 16-byte boundary. is equivalent to . 32 January 24. Shared State Space The shared (. It is shared by all threads in a context.texref type and Section 8.0 5. Physical texture resources are allocated on a per-module granularity.tex . and variables declared in the .1. An address in shared memory can be read and written by any thread in a CTA. The . 5.tex .u32 or . where texture identifiers are allocated sequentially beginning with zero.

The following table lists the fundamental type specifiers for each basic type: Table 8. In principle. so their names are intentionally short. .Chapter 5. . Two fundamental types are compatible if they have the same basic type and are the same size.s16. 2010 33 . so that narrow values may be loaded.2.s32. and converted using regular-width registers.b32. The same typesize specifiers are used for both variable definitions and for typing instructions.b8 instruction types are restricted to ld. and cvt instructions. .u32. but typed variables enhance program readability and allow for better operand type checking.s8. Types 5. A fundamental type specifies both a basic type and a size. January 24. stored. . and . all variables (aside from predicates) could be declared using only bit-size types. Signed and unsigned integer types are compatible if they have the same size.f32 and . The .pred Most instructions have one or more type specifiers.1. For example.2. and instructions operate on these types.s64 . .f64 types.f16. Restricted Use of Sub-Word Sizes The . . State Spaces. Fundamental Types In PTX.f32 and . st. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Register variables are always of a fundamental type. .b8. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. stored.u8.f64 .u16. The bitsize type is compatible with any fundamental type having the same size.f64 types.b16.s8. 5. All floating-point instructions operate only on . and Variables 5.b64 . .2. . or converted to other types and sizes. . . the fundamental types reflect the native data types supported by the target architectures.u64 . For convenience.f16 floating-point type is allowed only in conversions to and from . st. Operand types and sizes are checked against instruction types for compatibility.2. needed to fully specify instruction behavior.u8. Types. .f32. ld.

texref. Retrieving the value of a named member via query instructions (txq. accessing the pointer with ld and st instructions. PTX has two modes of operation. Referencing textures. allowing them to be defined separately and combined at the site of usage in the program.texref type that describe sampler properties are ignored. field ordering. In independent mode the fields of the .u64} reg. but all information about layout. The following tables list the named members of each type for unified and independent texture modes. or performing pointer arithmetic will result in undefined results.surfref. but the pointer cannot otherwise be treated as an address. and overall size is hidden to a PTX program. hence the term “opaque”. and Surface Types PTX includes built-in “opaque” types for defining texture.PTX ISA Version 2. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. passed as a parameter to functions. texture and sampler information is accessed through a single . or surfaces via texture and surface load/store instructions (tex. In the independent mode. The three built-in types are . For working with textures and samplers. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. Sampler..{u32. sampler. opaque_var.3. sured). and de-referenced by texture and surface load. These types have named fields similar to structures. 2010 . i. and query instructions. suq).0 5. and surface descriptor variables. sust. base address. samplers.samplerref variables.texref handle. since these properties are defined by . Creating pointers to opaque variables using mov.samplerref. .e. 34 January 24. store. texture and sampler information each have their own handle. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. In the unified mode. suld. the resulting pointer may be stored to and loaded from memory. Texture. and .

surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_to_border 0. linear wrap. clamp_to_edge. mirror. clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode . State Spaces. clamp_ogl. 1 ignored ignored ignored ignored . linear wrap.texref values . clamp_to_border N/A N/A N/A N/A N/A . 1 nearest.texref values in elements in elements in elements 0. clamp_to_edge. mirror. and Variables Table 9. Types. 2010 35 .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.Chapter 5.samplerref values N/A N/A N/A N/A nearest.

At module scope.texref tex1.global . . 36 January 24.texref my_texture_name. As kernel parameters.global .param state space. . these variables are declared in the .global . When declared at module scope.global state space. Example: .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. these variables must be in the .global . . the types may be initialized using a list of static expressions assigning values to the named members.global . 2010 . filter_mode = nearest }.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.surfref my_surface_name. Example: .PTX ISA Version 2.samplerref my_sampler_name.

reg . .s32 i.2.v4.v4 .global .0}.f32 accel. and Variables 5. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.1. . r.f32 V. 0. . 5. . Vectors Limited-length vector types are supported.global .struct float4 { . a variable declaration describes both the variable’s type and its state space. . q.u8 bg[4] = {0. and an optional fixed address for the variable. Examples: .const .v2. A variable declaration names the space in which the variable resides. In addition to fundamental types. Predicate variables may only be declared in the register state space. an optional array size.shared . 2010 37 . 1. // a length-4 vector of floats . . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .reg .global .v2 .v4 .v2 or . and they may reside in the register space.4.u16 uv.v4 .Chapter 5.global . // a length-4 vector of bytes By default.v1. // a length-2 vector of unsigned ints .4. etc.f32 bias[] = {-1.f32 v0. PTX supports types for simple aggregate objects such as vectors and arrays. Variables In PTX. for example.v4 vector. State Spaces. This is a common case for three-dimensional grids.pred p. Types. Vectors cannot exceed 128-bits in length. Vectors must be based on a fundamental type.u32 loc. 0. Every variable must reside in one of the state spaces enumerated in the previous section.f64 is not allowed.v4. where the fourth element provides padding. vector variables are aligned to a multiple of their overall size (vector length times base-type size).4.struct float4 coord. 5.global . an optional initializer.v3 }.0. its name. textures. 0}. January 24. Examples: . Three-element vectors may be handled by using a . // typedef . .reg .b8 v. its type and size. Variable Declarations All storage for data is specified with variable declarations.

global .f32 blur_kernel[][] = {{.1. 1} }. {0.PTX ISA Version 2.0. To declare an array. being determined by an array initializer.1.global .v4 .0. {1.1. .0. The size of the array specifies how many elements should be reserved. this can be used to statically initialize a pointer to a variable.s32 n = 10.3. {0. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. Examples: .0.1.u32 or .05}..0 5.1}.. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).local .{. 2010 . {0. 0}. Similarly. 0}. . Array Declarations Array declarations are provided to allow the programmer to reserve space.. where the variable name is followed by an equals sign and the initial value or values for the variable. A scalar takes a single value. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.0}}. {0.b32 ptr = rgba.05.global ..u8 rgba[3] = {{1.u8 mailbox[128]. 38 January 24. Here are some examples: . -1}.4. . The size of the dimension is either a constant expression. For the kernel declaration above.global .0}.1.u16 kernel[19][19]. 5.4. 19*19 (361) halfwords are reserved (722 bytes).0}.s32 offset[][] = { {-1.global .05. this can be used to initialize a jump table to be used with indirect branches or calls. Variables that hold addresses of variables or instructions should be of type . Initializers are allowed for all types except . // address of rgba into ptr Currently.{. label names appearing in initializers represent the address of the next instruction following the label.. or is left empty.pred.05}}. .4. . variable initialization is supported only for constant and global state spaces.u64.shared . Variable names appearing in initializers represent the address of the variable.f16 and ..4.

. // declare %r0. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Alignment is specified using an optional . The variable will be aligned to an address which is an integer multiple of byte-count. …. %r99. The default alignment for vector variables is to a multiple of the overall vector size. say one hundred. %r1.const . alignment specifies the address alignment for the starting address of the entire array. . For arrays.5. and may be preceded by an alignment specifier.4. %r1.0. The default alignment for scalar and array variables is to a multiple of the base-type size. These 100 register variables can be declared as follows: . and Variables 5.0}.reg .4.0. Array variables cannot be declared this way. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Parameterized Variable Names Since PTX supports virtual registers. Examples: // allocate array at 4-byte aligned address.0. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. it is quite common for a compiler frontend to generate a large number of register names. Rather than require explicit declaration of every name.2. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. Types. 2010 39 . 5. January 24..b32 variables.b8 bar[8] = {0. nor are initializers permitted.b32 %r<100>. Elements are bytes.align 4 .0.6. named %r0. suppose a program uses a large number.Chapter 5.align byte-count specifier immediately following the state-space specifier. not for individual elements. State Spaces. For example.0.. . of .

0 40 January 24. 2010 .PTX ISA Version 2.

the sizes of the operands must be consistent.reg register state space. For most operations. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. s. 6.3. and a few instructions have additional predicate source operands. as its job is to convert from nearly any data type to any other data type (and size). The bit-size type is compatible with every type having the same size. The mov instruction copies data between registers.2. The cvt (convert) instruction takes a variety of operand types and sizes. The result operand is a scalar or vector variable in the register state space. Integer types of a common size are compatible with each other. st. PTX describes a load-store machine. Most instructions have an optional predicate guard that controls conditional execution. Source Operands The source operands are denoted in the instruction descriptions by the names a. so operands for ALU instructions must all be in variables declared in the . 6. q. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. and c. The ld. b. Each operand type must be compatible with the type determined by the instruction template and instruction type. There is no automatic conversion between types. January 24. 2010 41 . r. Instruction Operands 6. Instructions ld and st move data from/to addressable state spaces to/from registers. and cvt instructions copy data from one location to another.Chapter 6.1. mov. Predicate operands are denoted by the names p. . Operand Type Information All operands in instructions have a known type from their declarations.

r0. The syntax is similar to that used in many assembly languages. Here are a few examples: .gloal. Using Addresses. . Load and store operations move data between registers and locations in addressable state spaces. . .0 6.b32 p.f32 ld. tbl. address registers. All addresses and address computations are byte-based. . 6. Arrays.shared .1. and immediate address expressions which evaluate at compile-time to a constant address.f32 V. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.f32 W.reg . and Vectors Using scalar variables as operands is straightforward.PTX ISA Version 2. The address is an offset in the state space in which the variable is declared. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.reg .v4.s32 mov.v4 .s32 tbl[256]. there is no support for C-style pointer arithmetic.[x].u16 x. 2010 . q. [V]. and vectors. [tbl+12]. .const .u32 42 January 24. ld. p.reg .u16 ld. The interesting capabilities begin with addresses.4.global .const. W.u16 r0. arrays. Examples include pointer arithmetic and pointer comparisons. .4.shared.v4 . The mov instruction can be used to move the address of a variable into a pointer.reg . address register plus byte offset.s32 q. Address expressions include variable names.

a[1]. d.w = = = = V. . V.f32 ld. a[0].b and . and in move instructions to get the address of the label or function into a register.global.y V.z V. Vector loads and stores can be used to implement wide loads and stores.u32 {a. 2010 43 . Here are examples: ld. mov. The size of the array is a constant in the program.b V.4.w.g V.r V. and tex. a register variable.c.r.v4. c.u32 s. . which may improve memory performance.v4. Vectors may also be passed as arguments to called functions. Instruction Operands 6.v2.x.x V. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Rb.g. as well as the typical color fields . Elements in a brace-enclosed vector. mov.f32 {a.2. // move address of a[1] into s 6. Vector elements can be extracted from the vector with the suffixes . Examples are ld. or a braceenclosed list of similarly typed scalars.Chapter 6.d}.b.global.u32 s. The expression within square brackets is either a constant integer. or by indexing into the array using square-bracket notation.a. Array elements can be accessed using an explicitly calculated byte address.y. st. Vectors as Operands Vector operands are supported by a limited subset of instructions. it must be written as an address calculation prior to use. a[N-1].4. If more complicated indexing is desired. which include mov. [addr+offset]. Rd}. A brace-enclosed list is used for pattern matching to pull apart vectors. January 24.reg . The registers in the load/store operations can be a vector.z and . .4. b.c.u32 s. .reg . say {Ra. and the identifier becomes an address constant in the space where the array is declared. ld. [addr+offset2]. Rc. .f32 a. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. ld.4. .a 6. for use in an indirect branch or call.global.f32 V.d}.b. or a simple “register with constant offset” expression.v4 . where the offset is a constant expression that is either added or subtracted from a register variable.global.3. Arrays as Operands Arrays of all types can be declared. V2.

Type Conversion All operands to all arithmetic. Operands of different sizes or types must be converted prior to the operation.1. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. except for operations where changing the size and/or type is part of the definition of the instruction.PTX ISA Version 2.s32. the u16 is zero-extended to s32. 44 January 24. For example. logic. and ~131. if a cvt. 6.u16 instruction is given a u16 source operand and s32 as a destination operand. 2010 . Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.5.5. and data movement instruction must be of the same type and size.0 6.000 for f16).

u32 targeting a 32-bit register will first chop to 16-bits. zext = zero-extend. The type of extension (sign or zero) is based on the destination format.s16. then sign-extend to 32-bits. chop = keep only low bits that fit. u2f = unsigned-to-float. Instruction Operands Table 11. f2f = float-to-float. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. Notes 1 If the destination register is wider than the destination format. f2u = float-to-unsigned.Chapter 6. cvt. January 24. f2s = float-to-signed. the result is extended to the destination register width after chopping. 2010 45 . For example. s2f = signed-to-float.

PTX ISA Version 2. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rmi .5. In PTX.rm .rpi Integer Rounding Modifiers Description round to nearest integer.rn .0 6. Modifier .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. choosing even integer if source is equidistant between two integers.rni . Table 12. there are four integer rounding modifiers and four floating-point rounding modifiers.2. Rounding Modifiers Conversion instructions may specify a rounding modifier. The following tables summarize the rounding modifiers.rz .rzi . Modifier . 2010 .

2010 47 . as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Instruction Operands 6. Another way to hide latency is to issue the load instructions as early as possible. Table 11 gives estimates of the costs of using different kinds of memory. Table 14. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.Chapter 6. The register in a store operation is available much more quickly. while global memory is slowest.6. first access is high Notes January 24. Operand Costs Operands from different state spaces affect the speed of an operation. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Registers are fastest. Much of the delay to memory can be hidden in a number of ways.

PTX ISA Version 2. 2010 .0 48 January 24.

These include syntax for function definitions. 2010 49 . and is represented in PTX as follows: . In this section. stack-based ABI. The simplest function has no parameters or return values.func foo { … ret. and an optional list of input parameters. functions are declared and defined using the . stack layout. At the call. and memory allocated on the stack (“alloca”). … Here. we describe the features of PTX needed to achieve this hiding of the ABI.Chapter 7. and Application Binary Interface (ABI). together these specify the function’s interface. A function must be declared or defined prior to being called. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Abstracting the ABI Rather than expose details of a particular calling convention. arguments may be register variables or constants. function calls. and return values may be placed directly into register variables. Execution of the ret instruction within foo transfers control to the instruction following the call. the function name. execution of the call instruction transfers control to foo. A function definition specifies both the interface and the body of the function. 7. implicitly saving the return address. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. Scalar and vector base-type input and return parameters may be represented simply as register variables. Function declarations and definitions In PTX.func directive. or prototype. January 24. NOTE: The current version of PTX does not implement the underlying. support for variadic functions (“varargs”). parameter passing. } … call foo. A function declaration specifies an optional list of return parameters.1. so recursion is not yet supported.

reg .u32 %res) inc_ptr ( .f64 f1.b8 c4.b8 c3.b8 [py+11].b64 [py+ 0].param. } { . c4.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. st. In PTX.param. %rd. %rc2.u32 %ptr.param space memory. // scalar args in . .param. ld.b8 c1.reg . %ptr.b8 [py+ 8].param.reg . a . .4). [y+9]. c3.align 8 py[12].reg space. bumpptr. [y+8].PTX ISA Version 2. ld. this structure will be flattened into a byte array. %rc2.u32 %inc ) { add.b8 . The . passed by value to a function: struct { double dbl. a .b8 [py+ 9]. … In this example.c4. %inc. ret. st.reg .c3. st. consider the following C structure.param.b32 c1.f64 f1. byte array in .b8 c2.reg .func (. … st.param .u32 %res. [y+11].param space variables are used in two ways. [y+0].c2.func (.param.reg .param state space is used to pass the structure by value: .f1. Second. %rc1.b8 [py+10]. }.param. . (%x.param space call (%out). } … call (%r1). … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . [y+10]. note that .param . … ld.param.param.f64 field are aligned. inc_ptr.param. st.b8 . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . c2.s32 x.reg .param variable y is used in function definition bar to represent a formal parameter. … … // computation using x. 50 January 24. char c[4].s32 out) bar (. py).align 8 y[12]) { . For example.0 Example: . %rc1.c1. First. (%r1. Since memory accesses are required to be aligned to a multiple of the access size. 2010 . ld. ld.

• • • For a callee. Typically. A .param space formal parameters that are byte arrays.param arguments. The .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. size.reg or .param variables.g.. Abstracting the ABI The following is a conceptual way to think about the . • The .reg space variable of matching type and size. a .param variables or .reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. The following restrictions apply to parameter passing.reg state space in this way provides legacy support. . the corresponding argument may be either a .param memory must be aligned to a multiple of 1. • • • Input and return parameters may be .param or . In the case of . January 24. 4. The .param state space is used to receive parameter values and/or pass return values back to the caller.reg space variable with matching type and size.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.param byte array is used to collect together fields of a structure being passed by value. the corresponding argument may be either a .param instructions used for argument passing must be contained in the basic block with the call instruction. Parameters in .Chapter 7. Note that the choice of .reg space formal parameters. or a constant that can be represented in the type of the formal parameter. the argument must also be a . and alignment of parameters.param space byte array with matching type.param state space use in device functions. For a caller. For a caller. 2. • • Arguments may be . In the case of . all st. • The .param and ld.reg state space can be used to receive and return base-type scalar and vector values. or constants.param argument must be declared within the local scope of the caller. or 16 bytes. For a callee. For . Supporting the . size. or a constant that can be represented in the type of the formal parameter. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. 8. This enables backend optimization and ensures that the . and alignment. 2010 51 .reg variables.param or .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. In the case of .param space formal parameters that are base-type scalar or vector variables.

param state space.x In PTX ISA version 1.x supports multiple return values for this purpose. Changes from PTX 1.1. In PTX ISA version 2. and a .0.param byte array should be used to return objects that do not fit into a register.1. and there was no support for array parameters. Objects such as C structures were flattened and passed or returned using multiple registers. 2010 .0 continues to support multiple return registers for sm_1x targets. 52 January 24.x.reg state space.0 7. PTX 2.0 restricts functions to a single return value. For sm_2x targets. and . formal parameters may be in either . PTX 1. PTX 2. formal parameters were restricted to .param space parameters support arrays.PTX ISA Version 2.reg or .

. For %va_arg. %r3). .. To support functions with a variable number of arguments. %va_arg. bra Loop. 4.reg .reg .u32 sz. call (ap). bra Done. (ap). the size may be 1. } … call (%max). The function prototypes are defined as follows: .u32 ptr.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .func ( . … ) . %s2). call (val).func (.s32 result ) maxN ( . the alignment may be 1. Abstracting the ABI 7. following zero or more fixed parameters: . and end access to a list of variable arguments.reg .h headers in C.b64 val) %va_arg64 (. or 4 bytes. … %va_start returns Loop: @p Done: January 24. maxN. 2.b32 ctr. 2. setp. %r1. . 2.func baz ( ..reg .s32 result.u32 N.reg .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg .reg .pred p.reg . max. %va_start.u32 b. This handle is then passed to the %va_arg and %va_arg64 built-in functions.func %va_end (. 4. (3. N. 2010 53 . . the size may be 1. maxN. . 4). In PTX. In both cases. ) { . Once all arguments have been processed.func okay ( … ) Built-in functions are provided to initialize.h and varargs. 0x8000000.u32.reg .2.reg . result.reg . ctr. 0.u32 ptr) %va_start . . PTX provides a high-level mechanism similar to the one provided by the stdarg. %s1. … call (%max).func (. (2.reg .u32 ptr. Variadic functions NOTE: The current version of PTX does not support variadic functions. val.Chapter 7. 8. // default to MININT mov.reg . or 16 bytes.u32 sz.b32 val) %va_arg (. along with the size and alignment of the next data value to be accessed.u32 ap.u32 align) . %r2. call %va_end.u32 align) .reg . ctr. (ap.ge p. iteratively access. for %va_arg64.b32 result. %va_end is called to free the variable argument list handle.s32 val. or 8 bytes. . 4.reg .func (. mov. variadic functions are declared with an ellipsis at the end of the input parameter list.reg . ret. .u32 a.

3. a function simply calls the built-in function %alloca.reg .local instructions.reg .func ( . The array is then accessed with ld. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. Alloca NOTE: The current version of PTX does not support alloca. 54 January 24. 2010 . defined as follows: . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.local and st. To allocate memory.u32 ptr ) %alloca ( .0 7. If a particular alignment is required.PTX ISA Version 2.

opcode D. q = !(a < b). For some instructions the destination operand is optional. In addition to the name and the format of the instruction. PTX Instructions PTX instructions generally have from zero to four operands. setp. and C are the source operands. C. opcode D. Format and Semantics of Instruction Descriptions This section describes each PTX instruction.s32.Chapter 8. followed by some examples that attempt to show several possible instantiations of the instruction. opcode A. the semantics are described. b. A. 8.2. We use a ‘|’ symbol to separate multiple destination registers.lt p|q. opcode D. while A. January 24. Instruction Set 8.1. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. A. the D operand is the destination operand. // p = (a < b). The setp instruction writes two destination registers. 2010 55 . For instructions that create a result value. a. B. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. B. B. A.

1. branch over 56 January 24. i. q. So.s32 j.3. add 1 to j To get a conditional branch or conditional function call.lt. … // compare i to n // if false. // p = (i < n) // if i < n.pred as the type specifier.s32 p. optionally negated. As an example. use a predicate to control the execution of the branch or call instructions. Predicated Execution In PTX. add. bra L1. j. Predicates are most commonly set as the result of a comparison performed by the setp instruction.PTX ISA Version 2. j. n. the following PTX instruction sequence might be used: @!p L1: setp. This can be written in PTX as @p setp. consider the high-level code if (i < n) j = j + 1. Instructions without a guard predicate are executed unconditionally. n. add. i.s32 j.pred p. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. predicate registers can be declared as . 2010 . To implement the above example as a true conditional branch. where p is a predicate variable.lt.reg . The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. 1.s32 p. predicate registers are virtual and have .0 8.

1. ls (lower-or-same). ordering comparisons are not defined for bit-size types. ge. lt.3. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Table 16. ne. Instruction Set 8. 2010 57 . The following table shows the operators for signed integer. and hs (higher-or-same). hi (higher). le. gt (greater-than).1. Unsigned Integer. ne. the result is false. and ge (greater-than-or-equal). ne (not-equal).1. lo (lower). lt (less-than).3.2.1. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.3. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. le (less-than-or-equal).Chapter 8. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. The bit-size comparisons are eq and ne. If either operand is NaN. and bitsize types. The unsigned comparisons are eq. Table 15. Comparisons 8. unsigned integer. gt.

geu. Table 17.2. then the result of these comparisons is true. unordered versions are included: equ. There is no direct conversion between predicates and integer values. num returns true if both operands are numeric values (not NaN). or. gtu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.%p.PTX ISA Version 2. leu. Table 18.u32 %r1. neu. then these comparisons have the same result as their ordered counterparts.0 To aid comparison operations in the presence of NaN values.1. xor. // convert predicate to 32-bit value 58 January 24. setp can be used to generate a predicate from an integer. and no direct way to load or store predicate register values.3. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. and mov. ltu. If both operands are numeric values (not NaN). 2010 . Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. and nan returns true if either operand is NaN. for example: selp. not. If either operand is NaN.0. However. two operators num (numeric) and nan (isNaN) are provided. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.

For example: .reg .uX ok ok ok inv .f32.sX . the add instruction requires type and size information to properly perform the addition operation (signed. a.reg . b.f32 d.. and these are placed in the same order as the operands.uX . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. cvt. a.e.Chapter 8. i. most notably the data conversion instruction cvt. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. Example: . For example.fX ok inv inv ok Instruction Type .bX . different sizes). . and integer operands are silently cast to the instruction type if needed.bX . add. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Instruction Set 8.reg .sX ok ok ok inv .u16 d. It requires separate type-size modifiers for the result and source. Signed and unsigned integer types agree provided they have the same size. Floating-point types agree only if they have the same size. unsigned. 2010 59 . they must match exactly. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. Type Checking Rules Operand Type .fX ok ok ok ok January 24.u16 d. Table 19. a. float.4.u16 d. and this information must be specified as a suffix to the opcode. • The following table summarizes these type checking rules. For example.u16 a. b.

When used with a floating-point instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.0 8. Bit-size source registers may be used with any appropriately-sized instruction type. parse error. ld. the cvt instruction does not support . the size must match exactly.bX instruction types. For example. and converted using regular-width registers. so that narrow values may be loaded. The data is truncated to the instruction-type size and interpreted according to the instruction type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. no conversion needed. stored. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. for example. 2010 . “-“ = allowed. floating-point instruction types still require that the operand type-size matches exactly. inv = invalid. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. Source register size must be of equal or greater size than the instruction-type size.PTX ISA Version 2. Table 20. Notes 3.4. unless the operand is of bit-size type.1. so those rows are invalid for cvt. When a source operand has a size that exceeds the instruction-type size. stored. 2. 60 January 24. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. 4. When used with a narrower bit-size type. or converted to other types and sizes. 1. the data will be truncated. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. The following table summarizes the relaxed type-checking rules for source operands. st. Operand Size Exceeding Instruction-Type Size For convenience. Floating-point source registers can only be used with bit-size or floating-point instruction types. Note that some combinations may still be invalid for a particular instruction.

“-“ = Allowed but no conversion needed. parse error. 1. January 24. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Notes 3. Destination register size must be of equal or greater size than the instruction-type size. 2010 61 .or sign-extended to the size of the destination register. the destination data is zero. 2. Bit-size destination registers may be used with any appropriately-sized instruction type. the data is zeroextended.Chapter 8. otherwise. When used with a floatingpoint instruction type. The data is signextended to the destination register width for signed integer instruction types. the data will be zero-extended. When used with a narrower bit-size instruction type. the data is sign-extended. the size must match exactly. Table 21. Floating-point destination registers can only be used with bit-size or floating-point instruction types. 4. Instruction Set When a destination operand has a size that exceeds the instruction-type size. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. The data is sign-extended to the destination register width for signed integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. and is zero-extended to the destination register width otherwise. zext = zero-extend. The following table summarizes the relaxed type-checking rules for destination operands. inv = Invalid. If the corresponding instruction type is signed integer.

uni suffix. 8. When executing on a 32-bit data path. by a right-shift instruction. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. and 16-bit computations are “promoted” to 32-bit computations. 2010 . Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. A compiler or programmer may chose to enforce portable. Both situations occur often in programs. the threads are called divergent. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. However. 8. conditional function call. The semantics are described using C. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. or conditional return.0 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. For divergent control flow.5. for example. until C is not expressive enough. for many performance-critical applications. 62 January 24. If threads execute down different control flow paths. These extra precision bits can become visible at the application level.PTX ISA Version 2. until they come to a conditional control construct such as a conditional branch. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. this is not desirable. a compiler or code author targeting PTX can ignore the issue of divergent threads. If all of the threads act in unison and follow a single control flow path. Divergence of Threads in Control Constructs Threads in a CTA execute together. 16-bit registers in PTX are mapped to 32-bit physical registers. using the . At the PTX language level. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. the semantics of 16-bit instructions in PTX is machine-specific. so it is important to have divergent threads re-converge as soon as possible. at least in appearance.6. the optimizing code generator automatically determines points of re-convergence. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.1. Therefore. the threads are called uniform. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. and for many applications the difference in execution is preferable to limiting performance.6.

7. Instruction Set 8.Chapter 8.cc.1. 8.cc. Instructions All PTX instructions may be predicated. In the following descriptions. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. 2010 63 . addc sub.7. the optional guard predicate is omitted from the syntax. The Integer arithmetic instructions are: add sub add. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.

.PTX ISA Version 2.sat applies only to . . d. . . sub. d. Introduced in PTX ISA version 1.s32.s32 d.0 Table 22. add Syntax Integer Arithmetic Instructions: add Add two values. Saturation modifier: . .y.u32.u64.z. Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples 64 January 24. .sat limits result to MININT.sat. d = a – b. Applies only to . PTX ISA Notes Target ISA Notes Examples Table 23. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.s64 }. Description Semantics Notes Performs addition and writes the resulting value into a destination register. a. a. b.0. sub.u16.sat limits result to MININT. @p add. a. b..MAXINT (no overflow) for the size of the operation. Applies only to . add.s32 c.u32.sat}. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. // .s32 c.s32.u32 x.u64.MAXINT (no overflow) for the size of the operation.type = { .s32 . a.1.s32 d.s16. Supported on all target architectures. 2010 . Supported on all target architectures. add.type add{.type sub{.0.s16. . . . b. d = a + b.c. . Saturation modifier: .b. // .u16.s64 }. .type = { .s32 type.s32 . b.a.s32 type.sat}.sat applies only to .

cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.cc. @p @p @p @p add.b32 x1. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc. addc{. clearing.b32 addc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.cc.cc Add two values with carry-out. x3.z1. @p @p @p @p add.cc.b32 addc. a. b. addc.cc}.b32 addc. Instruction Set Instructions add.z2. x2. carry-out written to CC.cc.z3. add.type = { . Table 24.cc.type d. Introduced in PTX ISA version 1.b32 addc.y1.CF) holding carry-in/carry-out or borrowin/borrow-out. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.b32 addc. or testing the condition code. and there is no support for setting. No saturation.type = {.y4.y3.type d.u32. d = a + b. b. No saturation.2. Supported on all target architectures. carry-out written to CC.y2. a. Behavior is the same for unsigned and signed integers.y1. No other instructions access the condition code. .Chapter 8.s32 }. Supported on all target architectures. d = a + b + CC.z2.b32 x1. sub.CF No integer rounding modifiers.cc specified.y3.2. Introduced in PTX ISA version 1. . . x4.b32 addc.cc.z4. x2. These instructions support extended-precision integer addition and subtraction.s32 }.CF No integer rounding modifiers. .u32. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. x3.y4.CF.cc. add. if .z3.cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc Syntax Integer Arithmetic Instructions: add.z1.y2.z4. Behavior is the same for unsigned and signed integers. 2010 65 . x4. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc.

y1.s32 }.cc}.cc Syntax Integer Arithmetic Instructions: sub. @p @p @p @p sub.z3. sub. subc{.u32.y4.b32 subc.0 Table 26.b32 subc. Supported on all target architectures.cc.cc.u32.cc. sub. Supported on all target architectures.z1. .z2.cc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. Introduced in PTX ISA version 1. @p @p @p @p sub.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.cc. No saturation.type = { .z4. . a.(b + CC. . a. Behavior is the same for unsigned and signed integers. withborrow-in and optional borrow-out.z4.y3. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. if .type = {.type d. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.b32 subc. Behavior is the same for unsigned and signed integers.cc.z3.y4.y2. x3.b32 x1.CF). with borrow-out. d = a . Introduced in PTX ISA version 1. b.type d.b32 subc.b32 x1. x4.CF No integer rounding modifiers.z1. borrow-out written to CC. d = a – b. .y1. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.3.cc. No saturation. x3. x4.y2.y3. x2.cc Subract one value from another. borrow-out written to CC.b32 subc.CF No integer rounding modifiers.z2.cc. b.cc specified.PTX ISA Version 2.cc.s32 }. x2. 2010 .3.

hi or .x.s16. d = t<2n-1.hi variant // for . then d is the same size as a and b. .lo.0>. mul. . .s64 }.fxs.n>.s16 fa. If .lo.0. a. // for .lo variant Notes The type of the operation represents the types of the a and b operands.fxs. save only the low 16 bits // 32*32 bits. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.wide // for . creates 64 bit result January 24. Instruction Set Table 28.u32.fys.wide.type d.u64.lo is specified.wide}.wide suffix is supported only for 16.fys.u16.hi. 2010 67 . mul.. If .Chapter 8. mul.s32. d = t<n-1.s32 z. and either the upper or lower half of the result is written to the destination register. b.type = { .and 32-bit integer types.. mul{. d = t.. . Description Semantics Compute the product of two values. The .s16 fa..wide. . Supported on all target architectures. . then d is twice as wide as a and b to receive the full result of the multiplication. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // 16*16 bits yields 32 bits // 16*16 bits.wide is specified. n = bitwidth of type. t = a * b.y.

then d and c are twice as wide as a and b to receive the result of the multiplication.and 32-bit integer types. . a.s64 }.PTX ISA Version 2.s32 d. If . Applies only to .s32 type in . Supported on all target architectures.sat.lo. t n d d d = = = = = a * b.s16.c. // for . mad{.. b. b. .q.n> + c.u16. a.. Description Semantics Multiplies two values and adds a third..MAXINT (no overflow) for the size of the operation. .u32. and either the upper or lower half of the result is written to the destination register. The . @p mad. . c.lo. 68 January 24. Saturation modifier: . .lo variant Notes The type of the operation represents the types of the a and b operands. t<n-1. t<2n-1.b.0 Table 29.r.. t + c.wide}.hi mode. c. bitwidth of type.sat limits result to MININT. mad.s32.lo is specified.0> + c.lo.u64.0. .hi or .wide is specified.s32 d.type mad. and then writes the resulting value into a destination register..hi variant // for . If .hi.s32 r.a. then d and c are the same size as a and b. 2010 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide // for .p.type = { .hi. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. d.wide suffix is supported only for 16.

hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. b. mul24. Supported on all target architectures.hi may be less efficient on machines without hardware support for 24-bit multiply. and return either the high or low 32-bits of the 48-bit result.hi variant // for .0>.type d. mul24. // for .a.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.type = { . All operands are of the same type and size.. d = t<47.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.e. mul24. .s32 }. mul24.lo. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. // low 32-bits of 24x24-bit signed multiply. 48bits. d = t<31.b. 2010 69 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.lo}. . t = a * b.. Instruction Set Table 30. mul24{..s32 d.0.u32. i.16>.Chapter 8.hi. January 24.

lo}. d. mad24. mad24.u32. and add a third. 2010 . b.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.s32 }.b. c.hi may be less efficient on machines without hardware support for 24-bit multiply.0 Table 31.0.type = { .e. // for . mad24.s32 d.lo. // low 32-bits of 24x24-bit signed multiply.c. d = t<47.sat. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. a. 32-bit value to either the high or low 32-bits of the 48-bit result. a..type mad24. 48bits. Saturation modifier: . t = a * b.s32 type in .PTX ISA Version 2. c.hi variant // for . mad24. b. i.s32 d. mad24{. . Description Compute the product of two 24-bit integer values held in 32-bit source registers.0> + c. d = t<31. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. All operands are of the same type and size..16> + c. Supported on all target architectures. Applies only to .hi. 70 January 24. ..hi.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.a. Return either the high or low 32-bits of the 48-bit result.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.MAXINT (no overflow).sat limits result of 32-bit signed addition to MININT..hi mode.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b64 d. clz.u32 Semantics 74 January 24. clz requires sm_20 or later.type = { . Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.b32) { max = 32. a. X.b32. . } while (d < max && (a&mask == 0) ) { d++. popc requires sm_20 or later. .b64 }.0.b32 type. the number of leading zeros is between 0 and 32. // cnt is . X. 2010 . mask = 0x80000000. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. . popc. inclusively. cnt. // cnt is . d = 0. For .type d.u32 PTX ISA Notes Target ISA Notes Examples Table 40. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b64 d.b64 }.type d. mask = 0x8000000000000000. cnt. popc. popc Syntax Integer Arithmetic Instructions: popc Population count. the number of leading zeros is between 0 and 64. inclusively.PTX ISA Version 2. a. } Introduced in PTX ISA version 2. while (a != 0) { if (a&0x1) d++. } else { max = 64. a = a << 1. clz.b64 type. a. d = 0.0. if (.b32 popc. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a = a >> 1.type = { .0 Table 39.type == . For . a.b32.b32 clz.

type bfind.s32) ? 31 : 63.Chapter 8. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind returns 0xFFFFFFFF if no non-sign bit is found. a.shiftamt. Operand a has the instruction type.shiftamt is specified. i--) { if (a & (1<<i)) { d = i. For unsigned integers. break. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.shiftamt && d != -1) { d = msb .0. bfind. for (i=msb. .type==.u32 January 24. For signed integers.u32. d. bfind returns the bit position of the most significant “1”. X. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Instruction Set Table 41.s64 cnt. // cnt is . } } if (. d = -1. i>=0. bfind. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.s32. .u32 || . If .u64. . 2010 75 . a. bfind requires sm_20 or later. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. .type d. and operand d has type .shiftamt. Semantics msb = (.type==. bfind.s64 }.u32.u32 d.d.type = { . a.

.b32) ? 31 : 63.b32 d.b32.0. .type d.0 Table 42. a. i<=msb. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. msb = (. a.type = { . Description Semantics Perform bitwise reversal of input. i++) { d[i] = a[msb-i].b64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. brev. 2010 .type==. brev.PTX ISA Version 2. brev requires sm_20 or later. 76 January 24. for (i=0.

Instruction Set Table 43. . Description Extract bit field from a and place the zero or sign-extended result in d. Source b gives the bit field starting bit position.u32. the destination d is filled with the replicated sign bit of the extracted field.u64 || len==0) sbit = 0. . for (i=0. d = 0.b32 d.len.u32 || .type==.u64. len = c. . If the start position is beyond the msb of the input. bfe requires sm_20 or later. The destination d is padded with the sign bit of the extracted field. Semantics msb = (. 2010 77 . January 24.start. the result is zero. and operands b and c are type .u32 || . and source c gives the bit field length in bits. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. Operands a and d have the same type as the instruction type. else sbit = a[min(pos+len-1. bfe. .s64 }. . a.Chapter 8. if (. c.msb)]. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.a.u64: .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. otherwise If the bit field length is zero.type==. pos = b.s32. The sign bit of the extracted field is defined as: .type==.u32.type==.s32) ? 31 : 63. b.s32.type = { . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. bfe.type d.u32. .0. i<=msb.

a. 78 January 24.b32. d.len.start. bfi. Operands a.u32.0 Table 44. . Description Align and insert a bit field from a into b.b64 }.PTX ISA Version 2. If the bit field length is zero. b.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. and operands c and d are type .b32 d.a. i<len && pos+i<=msb.b. bfi requires sm_20 or later. the result is b.type = { . b. and source d gives the bit field length in bits.type f. for (i=0. len = d. and f have the same type as the instruction type.b32) ? 31 : 63. . f = b. Source c gives the starting bit position for the insertion. If the start position is beyond the msb of the input. bfi. 2010 . c.0. pos = c. i++) { f[pos+i] = a[i]. the result is b. Semantics msb = (. and place the result in f.

the four 4-bit values fully specify an arbitrary byte permute. default mode index d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.mode} d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.ecl. a 4-bit selection value is defined.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. b5. Description Pick four arbitrary bytes from two 32-bit registers. The bytes in the two source registers are numbered from 0 to 7: {b.rc16 }. 2010 79 .b2 source select c[11:8] d. msb=0 means copy the literal value.b32{. a} = {{b7. c. In the generic form (no mode specified).rc8. a. .b4e.mode = { . . .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. For each byte in the target register. and reassemble them into a 32-bit destination register.f4e. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). . b0}}.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. {b3. prmt. . b. Instruction Set Table 45. b1. Note that the sign extension is only performed as part of generic form. b4}. Thus. b6. .b1 source select c[7:4] d. the permute control consists of four 4-bit selection values. b2. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.Chapter 8. The msb defines if the byte value should be copied.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. as a 16b permute code.ecr. msb=1 means replicate the sign.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.b3 source select c[15:12] d.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Semantics tmp64 = (b<<32) | a. ctl[0]. r4. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[1] = (c >> 4) & 0xf. r4. r1. prmt. ctl[2]. tmp64 ). // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[1].f4e r1. tmp64 ). tmp[15:08] = ReadByte( mode. ctl[3].0. tmp[23:16] = ReadByte( mode.b32. } tmp[07:00] = ReadByte( mode. tmp[31:24] = ReadByte( mode. r2. tmp64 ).b32 prmt. r2. ctl[2] = (c >> 8) & 0xf. 2010 . ctl[3] = (c >> 12) & 0xf. r3. prmt requires sm_20 or later. r3. tmp64 ).PTX ISA Version 2. 80 January 24.

f32 and .Chapter 8.7. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Floating-Point Instructions Floating-point instructions operate on .2. Instruction Set 8.f64 register operands and constant immediate values. 2010 81 .

f64 div.32 and fma.rn and instructions may be folded into a multiply-add.rp .rm .target sm_1x No rounding modifier.rnd.f32 {abs. .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 {div. The optional .target sm_20 .sat Notes If no rounding modifier is specified.fma}.sqrt}.lg2.f32 are the same.mul}. with NaNs being flushed to positive zero. Instruction Summary of Floating-Point Instructions .f32 .PTX ISA Version 2.approx.0].f64 {sin. NaN payloads are supported for double-precision instructions.max}.f32 {add.rn .sqrt}.max}.approx.0 The following table summarizes floating-point instructions in PTX.f32 {mad. 1.fma}. default is . 2010 .approx. No rounding modifier.f64 {abs.0. and mad support saturation of results to the range [0.f64 are the same.rnd.neg.rcp. Single-precision add. {add. If no rounding modifier is specified. Table 46.rz .sub.rnd.rcp.sqrt}.f32 rsqrt. {mad.min.ex2}.rnd. default is .sub.mul}.neg.cos. Double-precision instructions support subnormal inputs and results.f32 {div.target sm_20 mad.full.approx.f64 mad.f32 {div.f64 and fma. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.rnd. mul. 82 January 24.min. Note that future implementations may support NaN payloads for single-precision instructions.rcp.f64 rsqrt.ftz . sub.rn and instructions may be folded into a multiply-add. . so PTX programs should not rely on the specific single-precision NaNs being generated. but single-precision instructions return an unspecified NaN.rnd.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

p. B. .f64 isnan. f0.normal testp. Table 48.number testp.infinite.number. Introduced in PTX ISA version 2.f32.f64 x. . true if the input is a subnormal number (not NaN.0. testp.f32 testp.type d.f64 }. positive and negative zero are considered normal numbers.notanumber testp. . January 24. a.type .infinite. a. .type = { .f32 copysign. testp requires sm_20 or later.type = { .finite testp. .pred = { .notanumber. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.infinite testp. // result is . copysign. testp. testp Syntax Floating-Point Instructions: testp Test floating-point property. A. not infinity).f32. copysign requires sm_20 or later. . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. C.op. Instruction Set Table 47. and return the result as d.0.f64 }. testp. .subnormal }.finite.op p. b. not infinity) As a special case.normal. z.Chapter 8. . X. . copysign. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.notanumber. 2010 83 . y.

add. .rz.f32 flushes subnormal inputs and results to sign-preserving zero.rm. b.f64 requires sm_13 or later. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. . add Syntax Floating-Point Instructions: add Add two values.f64.0.sat}.f32 add{. In particular. Saturation modifier: . sm_1x: add.f64 d. requires sm_13 for add. 84 January 24.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . NaN results are flushed to +0. add. add.0 Table 49.f2. .rn mantissa LSB rounds to nearest even . 2010 .f32 supported on all target architectures. Rounding modifiers have the following target requirements: .0]. add{.rnd}{. .rn): .f32. requires sm_20 Examples @p add. a.rnd}. d.rm mantissa LSB rounds towards negative infinity . subnormal numbers are supported.0.rm.f32 flushes subnormal inputs and results to sign-preserving zero.rz mantissa LSB rounds towards zero . Description Semantics Notes Performs addition and writes the resulting value into a destination register.rz available for all targets . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 1. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.0f. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz}{.PTX ISA Version 2. .f32 f1.f64 supports subnormal numbers.rn.rp }. Rounding modifiers (default is . d = a + b.rz.rn.f3. b. a.ftz.rp for add.f32 clamps the result to [0. add.rnd = { .sat.ftz. add.

a. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. subnormal numbers are supported.rnd}.0].b.rz available for all targets .rnd = { . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. Saturation modifier: sub.f32 supported on all target architectures.rm mantissa LSB rounds towards negative infinity .f2. NaN results are flushed to +0.f32.f64 requires sm_13 or later. Rounding modifiers have the following target requirements: .f3.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.f64.rm.rn. . January 24. b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f32 c. a.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0. In particular. sub. d. sub{. requires sm_13 for sub.f32 f1. requires sm_20 Examples sub. Instruction Set Table 50. .rz mantissa LSB rounds towards zero .rn mantissa LSB rounds to nearest even . d = a . sm_1x: sub.Chapter 8.rp }. b.ftz}{.rnd}{.a. Rounding modifiers (default is .b. sub.rn.rz. sub. 1.f64 supports subnormal numbers.sat}.f32 sub{.rn): . .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp for sub.rm.rn. .0f. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.ftz.sat.0. sub. 2010 85 . .0. . sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another.

rn mantissa LSB rounds to nearest even . mul.rnd}.f32 supported on all target architectures. d = a * b. 1. a.0]. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. Rounding modifiers have the following target requirements: .rp }. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 circumf.0.ftz}{. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz.rm. b. 2010 .f64 supports subnormal numbers.rm. . In particular. d.f64 d.f32 mul{. For floating-point multiplication. .sat}.rp for mul.rnd}{. a. . sm_1x: mul. mul. Rounding modifiers (default is .rm mantissa LSB rounds towards negative infinity .0 Table 51. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0. requires sm_13 for mul.pi // a single-precision multiply 86 January 24.sat. mul{.f32 flushes subnormal inputs and results to sign-preserving zero. b.rn. Description Semantics Notes Compute the product of two values.f64. mul.rz mantissa LSB rounds towards zero .rn): .rn. .rnd = { .0. mul. requires sm_20 Examples mul. subnormal numbers are supported. mul Syntax Floating-Point Instructions: mul Multiply two values.PTX ISA Version 2.radius.ftz. Saturation modifier: mul. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 requires sm_13 or later. . all operands must be the same size.f32.rz available for all targets .rz.0f.

f64 requires sm_13 or later. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. d. b.y. again in infinite precision.f32 computes the product of a and b to infinite precision and then adds c to this product. fma.rnd.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Instruction Set Table 52.f64 supports subnormal numbers.Chapter 8.c.0. c. fma. fma. Saturation: fma. The resulting value is then rounded to single precision using the rounding mode specified by . 1.rz mantissa LSB rounds towards zero .b.f64 is the same as mad.rz.x.f64 computes the product of a and b to infinite precision and then adds c to this product.rm.rn mantissa LSB rounds to nearest even .f64. .f64 d. NaN results are flushed to +0. subnormal numbers are supported.ftz.ftz.0.f64 introduced in PTX ISA version 1.sat. .a.rn.0].0f. d = a*b + c.rnd.sat}.rnd.rnd{. fma. 2010 87 .z. fma.rp }.f32 fma. PTX ISA Notes Target ISA Notes Examples January 24.rn.f32 fma. fma.rn. a.ftz}{.f32 requires sm_20 or later. Rounding modifiers (no default): .f64 w. sm_1x: fma. again in infinite precision. b.f32 flushes subnormal inputs and results to sign-preserving zero.4. fma. fma. fma.rnd = { . a. . . @p fma. d. fma.f32 introduced in PTX ISA version 2. The resulting value is then rounded to double precision using the rounding mode specified by . c.rm mantissa LSB rounds towards negative infinity . fma Syntax Floating-Point Instructions: fma Fused multiply-add.f32 is unimplemented in sm_1x.f32 clamps the result to [0.

f64}. Unlike mad.f64 computes the product of a and b to infinite precision and then adds c to this product.rnd = { . d = a*b + c.f32).f64 is the same as fma. again in infinite precision.f64 supports subnormal numbers. and then the mantissa is truncated to 23 bits.{f32. Note that this is different from computing the product with mul. b.f64 computes the product of a and b to infinite precision and then adds c to this product. 1.target sm_1x: mad. mad. but the exponent is preserved. // .PTX ISA Version 2.. fma.target sm_20 d.rnd{. 88 January 24.sat. mad{.target sm_13 and later .f64.{f32. the treatment of subnormal inputs and output follows IEEE 754 standard.rnd. where the mantissa can be rounded and the exponent will be clamped.f64} is the same as fma. The resulting value is then rounded to single precision using the rounding mode specified by . c.f32 clamps the result to [0. c. a.sat}.rm.sat}.0.f32 is identical to the result computed using separate mul and add instructions. Rounding modifiers (no default): . sm_1x: mad. The exception for mad.ftz. b. c.rn mantissa LSB rounds to nearest even . For .f32 mad.rnd. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. For .rn. In this case. The resulting value is then rounded to double precision using the rounding mode specified by .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}{. Description Semantics Notes Multiplies two values and adds a third. mad.rp }. again in infinite precision. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero. // . . mad. mad. subnormal numbers are supported.rm mantissa LSB rounds towards negative infinity . NaN results are flushed to +0.0f.0 devices. a.0 Table 53.e.f32.f32 is implemented as a fused multiply-add (i. again in infinite precision.rnd. . mad.rz. mad.f64 d. .ftz.rnd. The resulting value is then rounded to double precision using the rounding mode specified by . When JIT-compiled for SM 2.target sm_1x d.rn.f32 flushes subnormal inputs and results to sign-preserving zero. and then writes the resulting value into a destination register.ftz}{. mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. b. Saturation modifier: mad.0].f32 mad. mad. // .0.f32 computes the product of a and b to infinite precision and then adds c to this product.target sm_20: mad.rz mantissa LSB rounds towards zero .f32 computes the product of a and b at double precision.f32 is when c = +/-0. mad. a.

Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.Chapter 8...0 and later. a rounding modifier is required for mad. Target ISA Notes mad. a rounding modifier is required for mad.0.f64 instructions having no rounding modifier will map to mad.f64. requires sm_13 ..a.rz.f32 supported on all target architectures.rn.b. Rounding modifiers have the following target requirements: . mad..f32 d. In PTX ISA versions 2.rp for mad. January 24.rm.f64.4 and later. 2010 89 .rm. In PTX ISA versions 1..rn. Legacy mad.f32.c.rn.rz.f32 for sm_20 targets. requires sm_20 Examples @p mad..f64 requires sm_13 or later.rp for mad.f64.

div. approximate single-precision divides: div. z.f32 div. . stores result in d.f32 supported on all target architectures. and div. div.ftz}. b.rm.rn.approx. zd. .PTX ISA Version 2.f32 div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . div.f32 flushes subnormal inputs and results to sign-preserving zero. a. The maximum ulp error is 2 across the full range of inputs.rm.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 d. a. a. div. y.0 through 1.f32 and div. sm_1x: div.approx. d. d.ftz}.f64 requires sm_20 or later.f32.ftz.ftz.full.3.approx. Description Semantics Notes Divides a by b. div.f64 defaults to div. div.f32 defaults to div. .ftz. div. xd. div. 2010 .rp}. Fast. b.full.f64 supports subnormal numbers. but is not fully IEEE 754 compliant and does not support rounding modifiers.approx{. Target ISA Notes div.f32 implements a relatively fast. For PTX ISA version 1.rz mantissa LSB rounds towards zero .rn.ftz. subnormal numbers are supported. Examples 90 January 24. b.0 Table 54.approx.rn.f32 requires sm_20 or later.f64 diam.ftz}.approx.f64 requires sm_13 or later.f32 implements a fast approximation to divide.f64. Subnormal inputs and results are flushed to sign-preserving zero.14159.rnd. div Syntax Floating-Point Instructions: div Divide one value by another. PTX ISA Notes div.f32 div.rn.full{. . // // // // fast.rnd = { .rz. and rounding introduced in PTX ISA version 1.0. For PTX ISA versions 1. Fast.rp }.rnd is required.f32 div. a.4. 2126]. computed as d = a * (1/b). x. approximate division by zero creates a value of infinity (with same sign as a). For b in [2-126.full.3.full. d.circum. one of .f32 flushes subnormal inputs and results to sign-preserving zero.full.rn mantissa LSB rounds to nearest even . . . yd.f32 and div. d = a / b. b. div.{rz.rm mantissa LSB rounds towards negative infinity . Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . Explicit modifiers .rnd{.approx. or .rnd. full-range approximation that scales operands to achieve better accuracy.f64 introduced in PTX ISA version 1. the maximum ulp error is 2.ftz.f32 div.4 and later.

neg.f32 supported on all target architectures. abs.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs. d = -a. d = |a|. NaN inputs yield an unspecified NaN.ftz. d. neg.f32 flushes subnormal inputs and results to sign-preserving zero. abs.f0. Negate the sign of a and store the result in d. neg.f64 supports subnormal numbers. Subnormal numbers: sm_20: By default.f64 requires sm_13 or later.Chapter 8. sm_1x: abs. Take the absolute value of a and store the result in d. a.ftz}. January 24. Table 56.ftz.f64 d.ftz}. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. sm_1x: neg. subnormal numbers are supported. NaN inputs yield an unspecified NaN. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 x.f32 supported on all target architectures.f64 supports subnormal numbers. a. neg{. Subnormal numbers: sm_20: By default.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 91 . a.f0.0.f32 x.f32 neg.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. neg. neg. d. Instruction Set Table 55.ftz. a. abs.f32 abs. abs{. subnormal numbers are supported. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.

f64 f0. a. @p min. a.f32 supported on all target architectures. b. a. subnormal numbers are supported. max. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. min. b. (a < b) ? a : b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f1.f2.f32 max. max. Store the maximum of a and b in d.f64 requires sm_13 or later. b.0.x.ftz}.f32 max.f32 min. Store the minimum of a and b in d. max{.0 Table 57. min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 z. sm_1x: max. max.c.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. max.f32 min. 2010 .ftz. min{. d d d d = = = = NaN. subnormal numbers are supported. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d. Table 58.f32 supported on all target architectures.f64 supports subnormal numbers. min. a. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.c.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. a.b.ftz. a. min. sm_1x: min.z. d. b. a.b.f32 flushes subnormal inputs and results to sign-preserving zero.PTX ISA Version 2.f64 d.ftz.0.ftz. a. 92 January 24. d d d d = = = = NaN. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 supports subnormal numbers.f64 requires sm_13 or later. b. (a > b) ? a : b.

rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f32 implements a fast approximation to reciprocal. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . sm_1x: rcp.ftz.rz mantissa LSB rounds towards zero .f32 supported on all target architectures. rcp. rcp. PTX ISA Notes rcp. .0 +subnormal +Inf NaN Result -0.rn. a.approx.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 rcp.rnd{. a.approx or .f32 flushes subnormal inputs and results to sign-preserving zero.0 +0. Description Semantics Notes Compute 1/a.f64 and explicit modifiers .f64. and rcp.ftz}. Examples January 24.rn. d = 1 / a.approx.approx.rz. rcp. For PTX ISA version 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero.ftz were introduced in PTX ISA version 1. a.ftz.f32 rcp. General rounding modifiers were added in PTX ISA version 2.0 through 1. 2010 93 .rn mantissa LSB rounds to nearest even . xi. rcp.approx{.ftz}.r.0.rn.f64 requires sm_13 or later. rcp.f32 defaults to rcp.rnd.0 -Inf -Inf +Inf +Inf +0. d.4.f64 ri.approx. subnormal numbers are supported. . .f64 defaults to rcp.f32 and rcp.0. store result in d.approx and .f64 requires sm_20 or later. Input -Inf -subnormal -0.f64 d.rm.rm.rm mantissa LSB rounds towards negative infinity .f64 supports subnormal numbers. rcp.0. rcp.x. // fast.ftz.rn. Target ISA Notes rcp.ftz.Chapter 8. Instruction Set Table 59.f32 requires sm_20 or later. xi. The maximum absolute error is 2-23.f64 introduced in PTX ISA version 1.rnd.x.0 over the range 1. one of . For PTX ISA versions 1. rcp.rn.4 and later.rnd is required.rp}.f32 rcp.f32 rcp. rcp. rcp.0-2.f32.3. d.rp }.{rz.

rnd.rz.f64 requires sm_13 or later. 2010 . .f32 implements a fast approximation to square root.rp}.0 +0. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. a. // IEEE 754 compliant rounding d. sqrt.rm.ftz}.approx and .4 and later.0 +subnormal +Inf NaN Result NaN NaN -0. sqrt. sqrt. a.f32 defaults to sqrt. sqrt.rm.ftz.x.ftz were introduced in PTX ISA version 1.f32.f32 sqrt.rm mantissa LSB rounds towards negative infinity .f32 flushes subnormal inputs and results to sign-preserving zero. approximate square root d.rn.{rz. Examples 94 January 24. For PTX ISA version 1. a.f64 r.f32 sqrt.rnd.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. The maximum absolute error for sqrt.0 -0.f64 defaults to sqrt.approx.rnd is required.f64 and explicit modifiers .f64 introduced in PTX ISA version 1. sqrt. one of . Description Semantics Notes Compute sqrt(a). store in d.x.rn. Input -Inf -normal -subnormal -0.0 Table 60.rn.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0 +0.f32 requires sm_20 or later.approx.f32 supported on all target architectures.f64 requires sm_20 or later. sqrt.4.rn.f64 supports subnormal numbers. For PTX ISA versions 1. // fast. sqrt.f32 sqrt.approx or . . General rounding modifiers were added in PTX ISA version 2.3. r.f64 d.0. Target ISA Notes sqrt.rz mantissa LSB rounds towards zero . sqrt.approx{.f32 is TBD. .rn mantissa LSB rounds to nearest even . and sqrt.x.f32 and sqrt. // IEEE 754 compliant rounding .rnd{.rn.rp }.0. sqrt. d = sqrt(a).f32 sqrt.PTX ISA Version 2.ftz}.rnd = { .approx.ftz. sqrt.0 +0.approx.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .0 through 1. PTX ISA Notes sqrt. r. subnormal numbers are supported.approx. sm_1x: sqrt.f64.rn.

approx. For PTX ISA version 1.f32 defaults to rsqrt. d. d = 1/sqrt(a). subnormal numbers are supported.approx.approx{.ftz.approx. rsqrt.f64. 2010 95 .0 through 1.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. store the result in d. Note that rsqrt. x.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt.f64 isr. rsqrt.approx modifier is required. rsqrt.f32 and rsqrt.Chapter 8.f64 is emulated in software and are relatively slow. ISR.0-4. For PTX ISA versions 1. sm_1x: rsqrt. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.approx.f64 defaults to rsqrt. The maximum absolute error for rsqrt.approx. Explicit modifiers . rsqrt.0. Input -Inf -normal -subnormal -0.f64 d.f32 rsqrt.approx. and rsqrt.f32 is 2-22.0 +0.3. the .f64 were introduced in PTX ISA version 1.0.f32. a.f32 supported on all target architectures. PTX ISA Notes rsqrt. rsqrt. a.4 over the range 1. Compute 1/sqrt(a).ftz.f32 rsqrt.f64 supports subnormal numbers. Instruction Set Table 61.4 and later. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 NaN The maximum absolute error for rsqrt.f64 requires sm_13 or later.ftz were introduced in PTX ISA version 1.4.approx implements an approximation to the reciprocal square root.f64 is TBD.ftz.approx and . January 24. Target ISA Notes Examples rsqrt. X.

sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.ftz introduced in PTX ISA version 1.approx.0 through 1.f32 introduced in PTX ISA version 1.0 NaN NaN The maximum absolute error is 2-20. For PTX ISA versions 1.0.4 and later. sin.f32. sin. a.0 -0.approx and .0 +0. subnormal numbers are supported. Subnormal numbers: sm_20: By default. Explicit modifiers .ftz. Input -Inf -subnormal -0.f32 implements a fast approximation to sine. d = sin(a).ftz. 96 January 24.f32 defaults to sin.4. Target ISA Notes Examples Supported on all target architectures.approx. sin.ftz. sin. Find the sine of the angle a (in radians).PTX ISA Version 2.3.approx{.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.0 Table 62.approx modifier is required. For PTX ISA version 1.0 +subnormal +Inf NaN Result NaN -0.0 +0. PTX ISA Notes sin.f32 sa.f32 d. sin. a.0 +0. 2010 . the .9 in quadrant 00.approx. sm_1x: Subnormal inputs and results to sign-preserving zero.

f32 flushes subnormal inputs and results to sign-preserving zero.approx{.3.4.f32 d. For PTX ISA versions 1. Input -Inf -subnormal -0. cos.f32 introduced in PTX ISA version 1. cos.0 +0.approx and .approx modifier is required.ftz.ftz}.Chapter 8.ftz introduced in PTX ISA version 1. Explicit modifiers . Find the cosine of the angle a (in radians). 2010 97 . sm_1x: Subnormal inputs and results to sign-preserving zero.approx. Instruction Set Table 63. d = cos(a). a. January 24.0 +1. subnormal numbers are supported.f32 implements a fast approximation to cosine.0 +1.approx.ftz. PTX ISA Notes cos. cos.ftz.0 +1.approx. cos.0 through 1.0. the . a.9 in quadrant 00.f32. cos.f32 ca.f32 defaults to cos. Subnormal numbers: sm_20: By default. Target ISA Notes Examples Supported on all target architectures.4 and later. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 NaN NaN The maximum absolute error is 2-20.0 +subnormal +Inf NaN Result NaN +1. For PTX ISA version 1.

Subnormal numbers: sm_20: By default. The maximum absolute error is 2-22. lg2. lg2. d = log(a) / log(2). Explicit modifiers . Input -Inf -subnormal -0.0.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. subnormal numbers are supported. lg2.f32 defaults to lg2.f32 Determine the log2 of a.4. a.0 Table 64.approx modifier is required.f32. a. 98 January 24.f32 la.6 for mantissa.ftz}.0 +0. 2010 . For PTX ISA versions 1.approx and .approx.approx{.f32 introduced in PTX ISA version 1.ftz introduced in PTX ISA version 1. lg2. sm_1x: Subnormal inputs and results to sign-preserving zero.3. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. the . PTX ISA Notes lg2.f32 implements a fast approximation to log2(a).PTX ISA Version 2.0 through 1. lg2.approx.ftz.4 and later.ftz. Target ISA Notes Examples Supported on all target architectures.ftz.approx.f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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. ne. a. Applies to all numeric types.lt. b. loweror-same. xor. gtu.ftz applies only to . .b16. and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default. geu.s64.u32. To aid comparison operations in the presence of NaN values. p = BoolOp(t. setp with . le.b64. ge. gt. and higher-or-same may be used instead of lt. the result is false. le. . ls. or.dtype. c). Modifier . unordered versions are included: equ. This result is written to the first destination operand. and hs for lower. Integer Notes Floating Point Notes The ordered comparisons are eq. ne.u32 p|q. ge.pred variables. neu. . hi.f32 flushes subnormal inputs to sign-preserving zero. If both operands are numeric values (not NaN).n. a. le. leu. If either operand is NaN. .ftz}. setp. . p.s32.type = { .s16. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. and (optionally) combine this result with a predicate value by applying a Boolean operator. respectively. lo. The signed and unsigned comparison operators are eq. For unsigned values. lt.BoolOp{. .type .u16. If either operand is NaN.s32 setp. ge.b. sm_1x: setp. num returns true if both operands are numeric values (not NaN). leu. @q setp. 2010 . lt. and can be one of: eq. . ltu. Semantics t = (a CmpOp b) ? 1 : 0. neu.f64 source type requires sm_13 or later.PTX ISA Version 2.ftz. 102 January 24. geu. setp. setp. num.u64.r. b. gt. The destinations p and q must be . then these comparisons have the same result as their ordered counterparts. gt. higher. ge. hs equ. hi. nan The Boolean operator BoolOp(A. q = BoolOp(!t.a. bit-size comparisons are eq and ne. gt. {!}c. The comparison operator is a suffix on the instruction. c).f32 flushes subnormal inputs to sign-preserving zero.and.f64 supports subnormal numbers. subnormal numbers are supported.b32. lt.0 Table 67.dtype.ftz}. p[|q]. ls. le.B) is one of: and. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.CmpOp{. gtu. The untyped.0.eq. ne. then the result of these comparisons is true. A related value computed using the complement of the compare result is written to the second destination operand.f32.f64 }.f32 comparisons. .CmpOp.i.type setp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. the comparison operators lo. . ltu.dtype. p[|q].

s32.u64.dtype. B. 2010 103 . b. . Operands d. . b. sm_1x: slct.dtype = { . otherwise b is stored in d. slct. .b32.u64.0.f64 }. z. .f32 A. Instruction Set Table 68. If c is True.u32. Semantics Floating Point Notes January 24.dtype.type = { .0. .p. . subnormal numbers are supported.b16. d = (c >= 0) ? a : b.s16.s32.u16.f32 d.dtype. . a. The selected input is copied to the output without modification. a.Chapter 8. d = (c == 1) ? a : b.u32. Operand c is a predicate. fval. and b are treated as a bitsize type of the same width as the first instruction type. Table 69.f32 flushes subnormal values of operand c to sign-preserving zero.f64 }. slct. c. based on the value of the predicate source operand. slct. slct. . selp. . . . selp Syntax Comparison and Selection Instructions: selp Select between source operands.xp.dtype.ftz. Introduced in PTX ISA version 1. b otherwise. d. and b must be of the same type. negative zero equals zero.f32 comparisons. slct Syntax Comparison and Selection Instructions: slct Select one source operand. . f0. C.u64. y. For .s64. .s32 selp. . .u32. the comparison is unordered and operand b is selected. val. Subnormal numbers: sm_20: By default.f32.t. c. and operand a is selected. a. .x.f32 r0.f32. operand c must match the second instruction type. slct.f64 requires sm_13 or later. . . based on the sign of the third operand.f32 comparisons.f32 flushes subnormal values of operand c to sign-preserving zero.b32. If operand c is NaN.ftz.s32 x. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. c. Modifier .f64 requires sm_13 or later.u16. b. If c ≥ 0.type d. a. a is stored in d.ftz}. a is stored in d. selp.ftz applies only to .b16. . and operand a is selected. .s64.s16.g. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . .b64.s32 slct{. a.b64.r. Operands d. @q selp. Description Conditional selection.

provided the operands are of the same size. and not also operate on predicates. Instructions and. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.0 8.4. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. This permits bit-wise operations on floating point values without having to define a union to access the bits.7. xor. or. performing bit-wise operations on operands of any type.PTX ISA Version 2.

Supported on all target architectures.Chapter 8. sign. d = a | b. Allowed types include predicate registers. but not necessarily the type.0. Introduced in PTX ISA version 1. Supported on all target architectures. . or. The size of the operands must match.b64 }.type d.type = { . . .type = { . but not necessarily the type. and. a.pred p.b64 }. and Syntax Logic and Shift Instructions: and Bitwise AND.b32 x.fpvalue. .0x00010001 or.b32. 2010 105 .0. Table 71.b16. . .pred. .b32 mask mask. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. b.b32.pred. The size of the operands must match. January 24. a.b16. d = a & b. Allowed types include predicate registers.r. and.q.type d. or.b32 and.q. Instruction Set Table 70.0x80000000. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. b.r. Introduced in PTX ISA version 1. . or Syntax Logic and Shift Instructions: or Bitwise OR.

b.q.type = { . not Syntax Logic and Shift Instructions: not Bitwise negation.type = { . Supported on all target architectures.b64 }. . d.0 Table 72.b16.b32.b16.0.q.type d.0.pred p.b32 mask. The size of the operands must match. xor. The size of the operands must match. not. not. not. cnot. Introduced in PTX ISA version 1. Supported on all target architectures. . cnot.x.type = { . a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.r. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b16 d.pred.b32.b64 }. a.a.0. xor. 2010 . . . Table 73.mask.b32 d. Table 74. a. Introduced in PTX ISA version 1. 106 January 24. .PTX ISA Version 2. Supported on all target architectures. d = ~a. Introduced in PTX ISA version 1. but not necessarily the type. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. but not necessarily the type.0x0001. . The size of the operands must match. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b32.b16.pred. one’s complement.b64 }.b32 xor. d = a ^ b. . cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. .type d. . but not necessarily the type. d = (a==0) ? 1 : 0. .type d. Allowed types include predicates. .

The sizes of the destination and first source operand must match. Shift amounts greater than the register width N are clamped to N. 2010 107 . . Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. shl Syntax Logic and Shift Instructions: shl Shift bits left. shl.u32. Signed shifts fill with the sign bit.s16.2. . shr. but not necessarily the type. d = a << b. The b operand must be a 32-bit value. PTX ISA Notes Target ISA Notes Examples Table 76. Shift amounts greater than the register width N are clamped to N.s64 }. b. .type d.b16 c. The sizes of the destination and first source operand must match.0. sign or zero fill on left. shl. Bit-size types are included for symmetry with SHL. regardless of the instruction type.u16 shr.a.b16. .2.i.Chapter 8. k. Supported on all target architectures. but not necessarily the type.0. zero-fill on right. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. shr Syntax Logic and Shift Instructions: shr Shift bits right. . a.b32.b64 }. . d = a >> b. a.1.s32 shr. b. The b operand must be a 32-bit value. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples January 24. .b32 q. .u64. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Instruction Set Table 75.type d.u16.b16. unsigned and untyped shifts fill with 0. shr. i.a. .j. .type = { .type = { .i.s32.b32.b64. regardless of the instruction type. . .

possibly converting it from one format to another. Instructions ld. suld. ld. Data Movement and Conversion Instructions These instructions copy data from place to place.0 8. local. mov. st. and st operate on both scalar and vector types. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and from state space to state space.7. The cvta instruction converts addresses between generic and global. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. ldu. or shared state spaces.5.PTX ISA Version 2. and sust support optional cache operations. 2010 . prefetchu isspacep cvta cvt 108 January 24.

the cache operators have the following definitions and behavior. Cache Operators PTX 2. Global data is coherent at the L2 level. it performs the ld. to allow the thread program to poll a SysMem location written by the CPU. The ld. when applied to a local address. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cs Cache streaming. The ld. rather than the data stored by the first thread. but multiple L1 caches are not coherent for global data.ca. and a second thread loads that address via a second L1 cache with ld. As a result of this request. The ld.cs.Chapter 8. A ld. not L1).cs is applied to a Local window address. Table 77. likely to be accessed again.lu instruction performs a load cached streaming operation (ld. the second thread may get stale L1 cache data.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cg to cache loads only globally. The cache operators require a target architecture of sm_20 or later.0 introduces optional cache operators on load and store instructions.cg Cache at global level (cache in L2 and below. Instruction Set 8. The compiler / programmer may use ld.cv Cache as volatile (consider cached system memory lines stale.lu operation.ca. When ld. if the line is fully covered. 2010 109 .1. The ld.7. For sm_20 and later.5. .lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. If one thread stores to global memory via one L1 cache.cs) on global addresses.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. January 24. invalidates (discards) the local L1 line following the load.lu load last use operation. . . Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. The default load instruction cache operation is ld. Operator .lu Last use.cv to a frame buffer DRAM address is the same as ld. bypassing the L1 cache. Use ld. likely to be accessed once. fetch again). . and cache only in the L2 cache.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. evict-first.ca loads cached in L1. any existing cache lines that match the requested address in L1 will be evicted. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.

the second thread may get a hit on stale L1 cache data. Future GPUs may have globally-coherent L1 caches.wt. . regardless of the cache operation. In sm_20.cs Cache streaming. If one thread stores to global memory.cg is the same as st. However. and discard any L1 lines that match. The default store instruction cache operation is st. . Use st. Addresses not in System Memory use normal write-back. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wt Cache write-through (to system memory). 2010 . bypassing its L1 cache.cg to cache global store data only globally. 110 January 24.wb.cg to local memory uses the L1 cache. Global stores bypass L1.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. and a second thread in a different SM later loads from that address via a different L1 cache with ld. in which case st. to allow a CPU program to poll a SysMem location written by the GPU with st. and marks local L1 lines evict-first.wt store write-through operation applied to a global System Memory address writes through the L2 cache. .PTX ISA Version 2.ca loads. and cache only in the L2 cache. st. bypassing the L1 cache. rather than get the data from L2 or memory stored by the first thread.ca.cg Cache at global level (cache in L2 and below. but st. not L1).wb could write-back global store data from L1. which writes back cache lines of coherent cache levels with normal eviction policy. likely to be accessed once.0 Table 78.wb for global data. Operator . The st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. The st.

or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. the generic address of a variable declared in global. label.f32 mov. . .s16. variable in an addressable memory space.type mov. local.. // get address of variable // get address of label or function .const. mov. myFunc.u16. immediate. .1.0.type = { . . mov.Chapter 8. .e. Operand a may be a register.b32. . local.b16. 2010 111 . special register.type mov. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. or function name. the parameter will be copied onto the stack and the address will be in the local state space. d. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.b64.f64 }. a.v. d = sreg.shared state spaces. A[5]. .type d. label. . Instruction Set Table 79.type mov. or shared state space. i. ptr. Note that if the address of a device function parameter is moved to a register. Write register d with the value of a.a.s32. local. . sreg. mov. Introduced in PTX ISA version 1. u.u64.global. and . Semantics d = a. alternately. Take the non-generic address of a variable in global.0. For variables declared in . avar.f32. the address of the variable in its state space) into the destination register. The generic address of a variable in global. ptr.u32 mov.s64. k. d = &avar.u16 mov.u32. . Description . // address is non-generic. d = &label. mov places the non-generic address of the variable (i.local.f32 mov.u32 d. d. d. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. or shared state space may be taken directly using the cvta instruction.. .u32 mov.e. A. within the variable’s declared state space Notes Although only predicate and bit-size types are required.f64 requires sm_13 or later. addr. .pred.

mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.b32.y.y. a[48.b32 { d.w << 24) d = a.type = { . mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). mov. Semantics d = a..b have type . Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b64 { d.47]. Supported on all target architectures. d.hi are . a[24..u16 %x is a double. d.x | (a.63] } // unpack 16-bit elements from .y.x. a[16.u8 // unpack 32-bit elements from . .15].{a.hi}. . 2010 .b.w } = { a[0. a[8.x.31] } // unpack 16-bit elements from .b16.w have type .b.b}.w}.x | (a. lo. or write vector register d with the unpacked values from scalar register a.15] } // unpack 8-bit elements from ..x.u32 x.z << 16) | (a.z. d.type d.b32 mov.y << 16) | (a.b64 // pack two 32-bit elements into .z.x.w << 48) d = a. .y } = { a[0..b64 112 January 24.g.y << 16) d = a.31]..z << 32) | (a.%r1..23].a}.7].w } = { a[0..g.31] } // unpack 8-bit elements from .y << 32) // pack two 8-bit elements into . a[16.b64 { d. a[32.b32 // pack two 16-bit elements into .b32 { d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b16 { d.. %x.. d.x | (a. a[16.x.y << 8) | (a. d..z. {lo.z.b32 mov. %r1.b8 r. mov.15].PTX ISA Version 2. a[8.b32 %r1.y.7].y } = { a[0. // // // // a.y } = { a[0.x | (a.x | (a.0.a have type .b32 // pack four 16-bit elements into . a.{x.b64 }. {r. a[32.y << 8) d = a.b16 // pack four 8-bit elements into . d.b64 mov.31].15]. For bit-size types.0 Table 80. d... Description Write scalar register d with the packed value of vector register a.. d. d..

ca.volatile introduced in PTX ISA version 1.local.s32. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. ld. and then converted to . .const.shared spaces to inhibit optimization of references to volatile memory. If an address is not properly aligned.u32.e. i.b32. .type ld. Semantics d d d d = = = = a.b16. Generic addressing and cache operations introduced in PTX ISA 2. or [immAddr] an immediate absolute byte address (unsigned.s8. an address maps to the corresponding location in local or shared memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding. to enforce sequential consistency between threads accessing shared memory.shared }. .param. ld introduced in PTX ISA version 1. . or the instruction may fault.u16. ld{. 32-bit). .u8.v2.global and .type . . .volatile may be used with .cv }.f32.s64. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .s16. Addresses are zero-extended to the specified width as needed. The . perform the load using generic addressing. d.e. Description Load register variable d from the location specified by the source address operand a in specified state space.f64 }. Within these windows.volatile.type d.b16.u64. .0.volatile. Generic addressing may be used with ld. .reg state space. . .0. the resulting behavior is undefined. 2010 113 .type ld{. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.cop}.cg.ss}.v4 }.. The address size may be either 32-bit or 64-bit. [a]. [a].ss = { .lu. If no state space is given. d. i.b8. *a. . .1. .Chapter 8. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. This may be used. .vec.cop = { . . *(a+immOff).vec = { . an integer or bit-size type register reg containing a byte address. and is zeroextended to the destination register width for unsigned and bit-size types. A destination register wider than the specified type may be used.volatile{.ss}. for example. and truncated if the register width exceeds the state space address width for the target architecture.type = { .ss}{. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. *(immAddr). .ss}{. The value loaded is sign-extended to the destination register width for signed integers. 32-bit). [a].const space suffix may have an optional bank number to indicate constant banks other than bank zero.volatile{. .vec. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . . The address must be naturally aligned to a multiple of the access size. . .cop}. PTX ISA Notes January 24. [a].f32 or . Instruction Set Table 81.f64 using cvt. d. . ld.cs.f16 data may be loaded using ld. Cache operations are not permitted with ld. In generic addressing. an address maps to global memory unless it falls within the local memory window or the shared memory window.global.b64.

const. Generic addressing requires sm_20 or later.%r.[p+-8]. %r.global.s32 ld.b32 ld.PTX ISA Version 2.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[buffer+64]. // load .b32 ld.b16 cvt. d.b64 ld. // access incomplete array x.const[4].local.b32 ld.f16 d.[a]. Q. x.local.[240].f64 requires sm_13 or later.[p+4].[p]. 2010 .global. Cache operations require sm_20 or later. // immediate address %r. // negative offset %r.f32 ld.f32. ld.shared.[fs].0 Target ISA Notes ld.v4.

reg state space.e.v4 }.ss = { .type ldu{.0. . Instruction Set Table 82. .u8.u64. // load from address // vec load from address .f16 data may be loaded using ldu. an address maps to global memory unless it falls within the local memory window or the shared memory window.global. i.global }. ldu.b8. 32-bit). to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ldu.v2.v4.ss}. i. .f32.. and then converted to . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The value loaded is sign-extended to the destination register width for signed integers. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. For ldu.e.b32 d. Semantics d d d d = = = = a. .s32. A destination register wider than the specified type may be used.vec = { . If no state space is given. . where the address is guaranteed to be the same across all threads in the warp.global. . perform the load using generic addressing. . an address maps to the corresponding location in local or shared memory.b32.f32 d. [a]. A register containing an address may be declared as a bit-size type or integer type. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. the resulting behavior is undefined.global. Introduced in PTX ISA version 2. *(immAddr).Chapter 8.s64. . [a].s16. *(a+immOff). only generic addresses that map to global memory are legal. The address size may be either 32-bit or 64-bit. . The addressable operand a is one of: [avar] the name of an addressable variable var. d. or the instruction may fault. 2010 115 . [areg] a register reg containing a byte address.u16. or [immAddr] an immediate absolute byte address (unsigned. Addresses are zero-extended to the specified width as needed. . .[a]. The address must be naturally aligned to a multiple of the access size.vec.f64 requires sm_13 or later.s8. and is zeroextended to the destination register width for unsigned and bit-size types. ldu. // state space .b64. The data at the specified address must be read-only. Within these windows.f64 using cvt. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.u32.f32 or . In generic addressing.f32 Q. .b16. *a.b16.f64 }. .[p+4].type = { .ss}. 32-bit). the access may proceed by silently masking off low-order address bits to achieve proper rounding.[p]. ldu{. If an address is not properly aligned. . . . PTX ISA Notes Target ISA Notes Examples January 24. ldu. and truncated if the register width exceeds the state space address width for the target architecture.type d.

// store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.f16 data resulting from a cvt instruction may be stored using st. . st.v2.type st{.b32.0.s8.volatile introduced in PTX ISA version 1.s32. .PTX ISA Version 2.b64.volatile. an integer or bit-size type register reg containing a byte address.vec.wb. b. [a]. { . The address size may be either 32-bit or 64-bit. . . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Cache operations require sm_20 or later.u32.v4 }.volatile may be used with . If an address is not properly aligned. .0. b. Cache operations are not permitted with st.vec .ss}. Generic addressing may be used with st. .u64.ss}{. . i. st{. b. . . .u16. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. b. perform the store using generic addressing. [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window.local.cop}.0 Table 83. i.b16. This may be used. . . and truncated if the register width exceeds the state space address width for the target architecture.ss}. { . [a]. 32-bit). PTX ISA Notes Target ISA Notes 116 January 24.e. *(immAddr) = a. . *d = a.ss . . . The address must be naturally aligned to a multiple of the access size. Within these windows.global and . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. or the instruction may fault.volatile. st.volatile{. A source register wider than the specified type may be used. Generic addressing requires sm_20 or later. . In generic addressing. 32-bit).vec. to enforce sequential consistency between threads accessing shared memory. an address maps to the corresponding location in local or shared memory.type st. The lower n bits corresponding to the instruction-type width are stored to memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Addresses are zero-extended to the specified width as needed.s16.global. st.cs. . { . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .type .b8.. for example. . or [immAddr] an immediate absolute byte address (unsigned. Semantics d = a. If no state space is given.f64 requires sm_13 or later. .e.shared }.f32. *(d+immOffset) = a.reg state space.f64 }.cg. 2010 .1.b16.s64. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.shared spaces to inhibit optimization of references to volatile memory.type = = = = {.wt }. Generic addressing and cache operations introduced in PTX ISA 2. the resulting behavior is undefined. st introduced in PTX ISA version 1.cop}. .ss}{.type [a].cop .u8.volatile{.

b.local. [q+4]. // negative offset [100].a. 2010 117 . // immediate address %r.global.s32 st.f32 st.r7.b16 [a].local. [q+-8].%r. // %r is 32-bit register // store lower 16 bits January 24.Q.b32 st.f16. [fs].local. Instruction Set Examples st. [p].f32 st.b32 st.a.v4.%r.s32 cvt.global.Chapter 8.

level = { . 32-bit). The addressable operand a is one of: [var] [reg] the name of an addressable variable var.level prefetchu. . or [immAddr] an immediate absolute byte address (unsigned. and truncated if the register width exceeds the state space address width for the target architecture.L1 [addr]. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. 118 January 24.L1 [ptr]. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. In generic addressing. the prefetch uses generic addressing. 32-bit).global. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. The address size may be either 32-bit or 64-bit. prefetch and prefetchu require sm_20 or later. . A prefetch into the uniform cache requires a generic address.e. 2010 . in specified state space. prefetch{.local }.global. i.0 Table 84. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . Addresses are zero-extended to the specified width as needed. an address maps to global memory unless it falls within the local memory window or the shared memory window. [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and no operation occurs if the address maps to a local or shared memory location.L1 [a]. a register reg containing a byte address.L1.space = { .0.PTX ISA Version 2.L2 }. prefetch. prefetchu. Within these windows. an address maps to the corresponding location in local or shared memory. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. If no state space is given.space}. A prefetch to a shared memory location performs no operation. // prefetch to data cache // prefetch to uniform cache .

local isspacep. lptr.space.global. Introduced in PTX ISA version 2. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.u32 or .global.space p. isspacep requires sm_20 or later.pred .0. PTX ISA Notes Target ISA Notes Examples Table 86.to.shared }. local. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or shared state space. isspacep. When converting a generic address into a global. or vice-versa. A program may use isspacep to guard against such incorrect behavior.space = { . // result is .0. isspacep. isshrd. svar. . local.u64 }.u32. The source address operand must be a register of type . or shared state space. p.global. Instruction Set Table 85. or shared address.u32 p. Take the generic address of a variable declared in global.local. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.lptr. . cvta requires sm_20 or later.shared }. // local. a.pred. The source and destination addresses must be the same size.genptr. local. or shared address cvta.u32 to truncate or zero-extend addresses.u64 or cvt. Use cvt. local. For variables declared in global. gptr. // convert to generic address // get generic address of var // convert generic address to global.global isspacep.local. cvta.size = { . .size .to. a.space = { . the generic address of the variable may be taken using cvta. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shared. or vice-versa. .space. // get generic address of svar cvta.size p.u32 gptr.u32.u64.Chapter 8. .shared isglbl. or shared state space to generic. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. 2010 119 .space.size cvta. a. cvta.u32 p. local. . p. cvta. sptr. or shared address to a generic address. islcl.u64.local. The destination register must be of type . January 24. var. Description Convert a global.

Description Semantics Integer Notes Convert between different types and sizes. Note that saturation applies to both signed and unsigned integer types.f32 float-to-integer conversions and cvt.f32. .s16. d.irnd = { .PTX ISA Version 2. // integer rounding // fp rounding . Note: In PTX ISA versions 1. . Saturation modifier: .ftz modifier may be specified in these cases for clarity. sm_1x: For cvt. . choosing even integer if source is equidistant between two integers. i.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.rp }.f32 float-tofloat conversions with integer rounding.irnd}{.frnd}{. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. .frnd = { .dtype. i.sat}. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. . .rz.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. .s32.rpi }. .dtype = . For cvt. .rm. The optional .MAXINT for the size of the operation. . .ftz}{.dtype.0 Table 87. .ftz}{. .atype = { . subnormal numbers are supported. subnormal inputs are flushed to signpreserving zero. .rzi round to nearest integer in the direction of zero .e.u16. a.ftz. . . d = convert(a).f64 }. the .s64. .rmi round to nearest integer in direction of negative infinity .s8. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.dtype.rzi. Integer rounding is illegal in all other instances. For float-to-integer conversions.rn.atype d.ftz.. 120 January 24.atype cvt{. .sat limits the result to MININT.sat For integer destination types. Integer rounding is required for float-to-integer conversions.u32.rni.f32 float-to-integer conversions and cvt.sat}.rni round to nearest integer.rmi.dtype. cvt{.f32 float-tofloat conversions with integer rounding..f32.ftz. and for same-size float-tofloat conversions where the value is rounded to an integer. .4 and earlier.e.u8. . 2010 .ftz. the result is clamped to the destination range by default. . Integer rounding modifiers: .f32.f16.sat is redundant.u64. subnormal inputs are flushed to signpreserving zero. The compiler will preserve this behavior for legacy PTX code. a.

0]. . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32. // note . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.Chapter 8.rz mantissa LSB rounds towards zero . Specifically.ftz modifier may be specified in these cases for clarity. Subnormal numbers: sm_20: By default.y.sat limits the result to the range [0.f32.version is 1.s32 f.f32. if the PTX .rni.f16. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.0.f32 instructions.i.f16. stored in floating-point format.ftz behavior for sm_1x targets January 24. subnormal numbers are supported.f16.4 or earlier.f32. Note: In PTX ISA versions 1. cvt. The optional .f32 x.f32 x.f64 types. 1.y.s32.f32. Applies to . . and .f64 j.sat For floating-point destination types.f64. The compiler will preserve this behavior for legacy PTX code. and for integer-to-float conversions. 2010 121 .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). cvt. Floating-point rounding is illegal in all other instances.r. Floating-point rounding modifiers: . result is fp cvt. The operands must be of the same size.f32. // float-to-int saturates by default cvt.f64 requires sm_13 or later. The result is an integral value. Introduced in PTX ISA version 1. NaN results are flushed to positive zero.0.rm mantissa LSB rounds towards negative infinity . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.4 and earlier. cvt. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . Saturation modifier: . and cvt. // round to nearest int.f32.rn mantissa LSB rounds to nearest even . cvt to or from . Modifier .

cvt. and surface descriptors. 2010 . PTX has two modes of operation. If no texturing mode is declared. add. In the independent mode.target texmode_independent . PTX supports the following operations on texture. and surface descriptors. texture and sampler information each have their own handle.6.v4. r2. mul. r5.. r1.param .f32 r1. and surface descriptors.r3. r3.global . [tex1. {f1. Module-scope and per-entry scope definitions of texture.f2}].f32 {r1. with the restriction that they correspond 1-to-1 with the 128 possible textures. . r5. 122 January 24. and surfaces. r1. . [tex1].0 8. samplers. Ability to query fields within texture.target options ‘texmode_unified’ and ‘texmode_independent’.u32 r5.entry compute_power ( . A PTX module may declare only one texturing mode.height. r1.r2. sampler. add.b32 r6.2d. sampler. div. allowing them to be defined separately and combined at the site of usage in the program. the file is assumed to use unified mode.width.r4}.PTX ISA Version 2. = nearest width height tsamp1. The advantage of independent mode is that textures and samplers can be mixed and matched. add. r6.texref tex1 ) { txq. } = clamp_to_border. Texture and Surface Instructions This section describes PTX instructions for accessing textures. Example: calculate an element’s power contribution as element’s power/total number of elements. but the number of samplers is greatly restricted to 16. The advantage of unified mode is that it allows 128 samplers. texture and sampler information is accessed through a single . . Texturing modes For working with textures and samplers.f32 r3.f32 r1. sampler..f32 r1. The texturing mode is selected using . // get tex1’s tex. and surface descriptors: • • • Static initialization of texture. // get tex1’s txq.samplerref tsamp1 = { addr_mode_0 filter_mode }. r5.f32.u32 r5.f32. r3.texref handle. [tex1].b32 r5. r4. sampler.7. In the unified mode.

v4. tex txq suld sust sured suq Table 88. [tex_a. PTX ISA Notes Target ISA Notes Examples January 24.geom. or the instruction may fault. Supported on all target architectures.s32..3d }.geom = { .s32 {r1. Operand c is a scalar or singleton tuple for 1d textures. . // Example of independent mode texturing tex. sampler_x. 2010 123 . [a.s32. is a two-element vector for 2d textures.Chapter 8.1d. . An optional texture sampler b may be specified. Instruction Set These instructions provide access to texture and surface memory.r3. . c].v4. .f32 }. Unified mode texturing introduced in PTX ISA version 1. [tex_a.f32 }.f32 {r1. {f1}]. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.r4}.s32. If no sampler is specified.0.u32. . and is a four-element vector for 3d textures.s32.r2. d. the resulting behavior is undefined. [a. i.1d. the access may proceed by silently masking off low-order address bits to achieve proper rounding. b.btype d.f3. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.v4. A texture base address is assumed to be aligned to a 16-byte address.r4}.f2.v4 coordinate vectors are allowed for any geometry. Description Texture lookup using a texture coordinate vector. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.geom. c]. tex.3d.dtype.dtype. //Example of unified mode texturing tex. Notes For compatibility with prior versions of PTX. the square brackets are not required and .dtype = { . If an address is not properly aligned. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.btype = { .r3. {f1. the sampler behavior is a property of the named texture. // explicit sampler .r2. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.2d. where the fourth element is ignored. .e.btype tex.f4}].5. The instruction always returns a four-element vector of 32-bit values. with the extra elements being ignored.v4.

height.b32 %r1. Description Query an attribute of a texture or sampler. [a]. Operand a is a . txq.tquery. d.squery = { .addr_mode_0. sampler attributes are also accessed via a texref argument.depth.width .b32 %r1. . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. Integer from enum { nearest.width.b32 %r1.filter_mode. .height .normalized_coords . Supported on all target architectures.filter_mode .0 Table 89. linear } Integer from enum { wrap. [tex_A].squery. txq. and in independent mode sampler attributes are accessed via a separate samplerref argument.texref or .depth . // unified mode // independent mode 124 January 24. Query: . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. [tex_A].addr_mode_0. // texture attributes // sampler attributes .samplerref variable.b32 d. clamp_ogl. txq. In unified mode. 2010 .filter_mode. addr_mode_1. .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [smpl_B].5.b32 txq. . [a].addr_mode_1 .addr_mode_0 .width.normalized_coords }. txq. clamp_to_edge.PTX ISA Version 2. .tquery = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. addr_mode_2 }. mirror.

3d. . .b64.1d.dtype . or FLOAT data. . [surf_B. . then . . and A components of the surface format.r2}.trap. {f1.z.surfref variable. Description Load from surface memory using a surface coordinate vector.geom . the surface sample elements are converted to . G. suld. if the surface format contains UINT data. the access may proceed by silently masking off low-order address bits to achieve proper rounding.y. suld.trap suld.u32. suld.dtype.clamp = = = = = = { { { { { { d.b. . where the fourth element is ignored. and is a four-element vector for 3d surfaces. {x}].dtype . [surf_A. // cache operation none. the resulting behavior is undefined.Chapter 8. .1d.clamp suld. then . suld.w}].trap .u32.trap introduced in PTX ISA version 1. B. sm_1x targets support only the .f32.dtype. suld.clamp. additional clamp modifiers.e.v4 }.s32. suld.v4. Cache operations require sm_20 or later.p. [a.geom{. b]. . .v4.s32 is returned. . Instruction Set Table 90.b8 .clamp field specifies how to handle out-of-bounds addresses: . .v2. i.u32 is returned.cop}. b].p.vec.s32.p is currently unimplemented.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. // unformatted d. The .cop}. . suld.f32 based on the surface format as follows: If the surface format contains UNORM.b32.geom{.2d.b32.b supported on all target architectures.s32.f32 }. suld. and cache operations introduced in PTX ISA version 2.cv }. or . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.ca. .b.f32. Target ISA Notes Examples January 24. Operand b is a scalar or singleton tuple for 1d surfaces.f3.0.b32.cs. .f2. {x. [a.p .trap {r1. Coordinate elements are of type . size and type conversion is performed as needed to convert from the surface sample format to the destination type.cop .5.. if the surface format contains SINT data. If the destination type is .trap clamping modifier. If an address is not properly aligned. Operand a is a . .s32.zero }.b performs an unformatted load of binary data. The lowest dimension coordinate represents a sample offset rather than a byte offset. SNORM.f4}. is a two-element vector for 2d surfaces. .clamp . suld.3d requires sm_20 or later. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b . and the size of the data transfer matches the size of destination operand d. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. or the instruction may fault.p.b. // for suld.b16.f32 is returned.cg. // for suld.u32. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b64 }. or .vec .p requires sm_20 or later. If the destination base type is .clamp . . . then .v2.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.3d }. Destination vector elements corresponding to components that do not appear in the surface format are not written. 2010 125 . // formatted . A surface base address is assumed to be aligned to a 16-byte address. .

The size of the data transfer matches the size of source operand c.clamp .cop}.b16. . if the surface format contains UINT data.b supported on all target architectures. . none.clamp sust.vec.b performs an unformatted store of binary data.f32. sust. and is a four-element vector for 3d surfaces. {x}].ctype.z. . Operand b is a scalar or singleton tuple for 1d surfaces. . // for sust.f32} are currently unimplemented. . The source data is then converted from this type to the surface sample format. Operand a is a . SNORM.ctype.trap introduced in PTX ISA version 1. . Surface sample components that do not occur in the source vector will be written with an unpredictable value. If an address is not properly aligned. Cache operations require sm_20 or later.b64 }.3d }.clamp. G.cs. and A surface components. {r1. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. . [surf_B.vec.0. // unformatted // formatted .f32.b32. is a two-element vector for 2d surfaces. If the source type is . .s32 is assumed. the access may proceed by silently masking off low-order address bits to achieve proper rounding. {f1. .wb.geom{.geom .trap .p requires sm_20 or later.b32. .b.ctype .3d requires sm_20 or later.v4 }.b // for sust.{u32.v2.surfref variable. Source elements that do not occur in the surface sample are ignored.s32.p. Target ISA Notes Examples 126 January 24.geom{. the resulting behavior is undefined.ctype . [a.5. then .f2. . .v2.3d.f3. or . sust. A surface base address is assumed to be aligned to a 16-byte address.PTX ISA Version 2. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.f32 }. The source vector elements are interpreted left-to-right as R. b]. sust.s32.b32.cg.f32 is assumed. or the instruction may fault.zero }. c. . and cache operations introduced in PTX ISA version 2. sust. i.clamp . .vec . .b.clamp = = = = = = { { { { { { [a.p performs a formatted store of a vector of 32-bit data values to a surface sample.e.f4}.trap sust. then .. {x.r2}. where the fourth element is ignored. .p. sust. The . . sust.w}].p.u32 is assumed.0 Table 91. sust. . then . sust Syntax Texture and Surface Instructions: sust Store to surface memory. sust. .v4.p Description Store to surface memory using a surface coordinate vector.clamp field specifies how to handle out-of-bounds addresses: . b].s32.b.1d. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . These elements are written to the corresponding surface sample components.u32.cop . sust. B. If the source base type is . or FLOAT data. 2010 .y.wt }.1d.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.trap [surf_A.b64. sm_1x targets support only the .2d.b8 . size and type conversions are performed as needed between the surface sample format and the destination type.cop}. The lowest dimension coordinate represents a sample offset rather than a byte offset. c. additional clamp modifiers.trap clamping modifier.trap. Coordinate elements are of type .s32. if the surface format contains SINT data. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.p.u32.

clamp = { ..u32 and . if the surface format contains SINT data.u32 is assumed.clamp. where the fourth element is ignored.c. Reduction to surface memory using a surface coordinate vector.0.u32. Coordinate elements are of type .Chapter 8.or }. January 24. . and the data is interpreted as .geom.b]. operations and and or apply to .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.c.b32 type.ctype.b32 }.b32.s32 types. If an address is not properly aligned.min.u64 data. 2010 127 . the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp field specifies how to handle out-of-bounds addresses: .s32.clamp [a. {x}]. . r1. Instruction Set Table 92. [surf_B.max.op. sured.geom. {x.s32. sured. . .trap sured. .s32 types.b. // for sured. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.trap. Operand b is a scalar or singleton tuple for 1d surfaces. The instruction type is restricted to . and is a four-element vector for 3d surfaces.b performs an unformatted reduction on . and .u32.p . The lowest dimension coordinate represents a sample offset rather than a byte offset. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.geom = { . sured requires sm_20 or later. min and max apply to . is a two-element vector for 2d surfaces.clamp .clamp [a.surfref variable. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. the resulting behavior is undefined.b . A surface base address is assumed to be aligned to a 16-byte address. r1.trap [surf_A.b32. .3d }. or .b32.p. sured. then . .min. Operand a is a .ctype.y}].2d. // sample addressing .1d. // for sured.p performs a reduction on sample-addressed 32-bit data. // byte addressing sured.u32.zero }. .trap .s32. The .b32 }.e.op = { .ctype = { .b].p. .s32 or .u64. or the instruction may fault.op.add. Operations add applies to . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.and. .u32.add. .1d. .ctype = { . .s32 is assumed. .u64. sured. then . .2d.u32 based on the surface sample format as follows: if the surface format contains UINT data.b. i.

[surf_A].depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Supported on all target architectures. . 2010 .b32 %r1.width .PTX ISA Version 2.width. Operand a is a . Query: . Description Query an attribute of a surface.height .depth }.surfref variable.0 Table 93.query = { .width. suq.5. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. .height.b32 d. .query. suq. 128 January 24. [a].

Execute an instruction or instruction block for threads that have the guard predicate true.0.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.Chapter 8.s32 d.7. If {!}p then instruction Introduced in PTX ISA version 1.s32 a.y. Supported on all target architectures. 2010 129 .7. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. Instruction Set 8.0.c. { add. setp.f32 @!p div.0. mov.a.b. Supported on all target architectures. Threads with a false guard predicate do nothing. } PTX ISA Notes Target ISA Notes Examples Table 95. {} Syntax Description Control Flow Instructions: { } Instruction grouping. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. @{!}p instruction.f32 @q bra L23. { instructionList } The curly braces create a group of instructions. used primarily for defining a function body. p.eq. Introduced in PTX ISA version 1.x. ratio.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. d. and then safely read values stored by other threads prior to the barrier. . The reduction operations for bar.red performs a predicate reduction across the threads participating in the barrier.0. {!}c. and any-thread-true (. January 24. execute a bar. p.red.popc. the waiting threads are restarted without delay. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).red} require sm_20 or later. Thus. When a barrier completes. PTX ISA Notes Target ISA Notes Examples bar. Note that a non-zero thread count is required for bar..popc is the number of threads with a true predicate. The barrier instructions signal the arrival of the executing threads at the named barrier. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).arrive using the same active barrier.arrive a{.arrive. it is as if all the threads in the warp have executed the bar instruction. Barriers are executed on a per-warp basis as if all the threads in a warp are active. In conditionally executed code. and the barrier is reinitialized so that it can be immediately reused.pred .red should not be intermixed with bar.and.sync) until the barrier count is met. a. and bar. a{.popc). b. If no thread count is specified. Each CTA instance has sixteen barriers numbered 0. thread count.sync and bar. Since barriers are executed on a per-warp basis. the final value is written to the destination register in all threads waiting at the barrier. 2010 133 . bar.op. bar. threads within a CTA that wish to communicate via memory can store to memory. Operands a.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.and and .red delays the executing threads (similar to bar.sync and bar.and).or). Thus. Instruction Set Table 100. Description Performs barrier synchronization and communication within a CTA. bar.u32 bar. Once the barrier count is reached.or }. Operand b specifies the number of threads participating in the barrier. b. b}.{arrive.red instruction.u32. b}. Register operands. all-threads-true (.cta. operands p and c are predicates.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.sync with an immediate barrier number is supported for sm_1x targets.sync bar. The result of .version 2.0. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. and bar. thread count. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.15.arrive does not cause any waiting by the executing threads. Register operands. Execution in this case is unpredictable. bar. All threads in the warp are stalled until the barrier completes. it simply marks a thread's arrival at the barrier.red are population-count (. b}. if any thread in a warp executes a bar instruction. the bar. bar.sync without a thread count introduced in PTX ISA 1. a{. bar. bar.sync or bar.red performs a reduction operation across threads. while .red} introduced in PTX .op = { .Chapter 8.{arrive. In addition to signaling its arrival at the barrier. the optional thread count must be a multiple of the warp size. bar.red. bar.sync 0. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. and d have type .sync or bar. Only bar. all threads in the CTA participate in the barrier. {!}c.red also guarantee memory ordering among threads identical to membar.

membar. level describes the scope of other clients for which membar is an ordering event.sys introduced in PTX .level = { . membar. membar. 134 January 24. membar. membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl will typically have a longer latency than membar. or system memory level. . membar.level.cta.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.gl} supported on all target architectures.sys will typically have much longer latency than membar. membar.PTX ISA Version 2.version 1.cta.g.0. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. global. 2010 .{cta. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.gl.sys Waits until all prior memory requests have been performed with respect to all clients.{cta.0 Table 101. membar. membar. membar. For communication between threads in different CTAs or even different SMs. this is the appropriate level of membar. . red or atom) has been performed when the value written has become visible to other clients at the specified level.4.cta. by st.sys }.sys. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar.version 2.gl.gl} introduced in PTX . Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. A memory read (e. membar. when the previous value can no longer be read. including thoses communicating via PCI-E such as system and peer-to-peer memory. .cta Waits until all prior memory writes are visible to other threads in the same CTA.sys requires sm_20 or later.g. A memory write (e. that is. Waits until prior memory reads have been performed with respect to other threads in the CTA.gl. PTX ISA Notes Target ISA Notes Examples membar. and memory reads by this thread can no longer be affected by other thread writes.

. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.and.b64.g.xor. accesses to local memory are illegal. The integer operations are add. The floating-point add. and max operations are single-precision. 32-bit operations.s32. . c.dec.op. . Description // // // // // . . If an address is not properly aligned. . 2010 135 .s32. and stores the result of the specified operation at location a. .b64 . the resulting behavior is undefined. . i. or [immAddr] an immediate absolute byte address. atom{. January 24. .. A register containing an address may be declared as a bit-size type or integer type. min.op. . .op = { .exch. .type atom{.add. .u32. xor. . inc. dec. and exch (exchange).b].u64 .space = { . an address maps to the corresponding location in local or shared memory.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32 only . .exch to store to locations accessed by other atomic operations. . . b.global. b.min. an address maps to global memory unless it falls within the local memory window or the shared memory window.. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Instruction Set Table 102.u32.space}.f32 }. or the instruction may fault. atom. d.or. .add.e.s32.b32. . The address size may be either 32-bit or 64-bit.type = { . [a]. i.e. or by using atom. If no state space is given. The inc and dec operations return a result in the range [0. and max. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u64.inc. max. The address must be naturally aligned to a multiple of the access size.f32 Atomically loads the original value at location a into destination register d. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. For atom. by inserting barriers between normal stores and atomic operations to a common address.max }.Chapter 8. . overwriting the original value.shared }. . [a]. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.type d.f32. Within these windows. or. and truncated if the register width exceeds the state space address width for the target architecture. The bit-size operations are and. In generic addressing.cas. perform the memory accesses using generic addressing. Operand a specifies a location in the specified state space. The floating-point operations are add. a de-referenced register areg containing a byte address. Addresses are zero-extended to the specified width as needed. . min.u32 only . . . min.u32. cas (compare-and-swap).b32. .space}. e. performs a reduction operation with operand b and the value in location a.

s32 atom.global.0. cas(r. atom.[a].shared requires sm_12 or later.shared. atom.f32 atom.max. s) = (r > s) ? s exch(r.shared operations require sm_20 or later.global.{min.f32 requires sm_20 or later.b32 d.cas.global requires sm_11 or later. Use of generic addressing requires sm_20 or later.0. atom. atom. 2010 . s) = (r >= s) ? 0 dec(r.[p]. s) = s.0 Semantics atomic { d = *a. : r. *a = (operation == cas) ? : } where inc(r. b. : r-1. b).max} are unimplemented. Release Notes Examples @p 136 January 24.my_val.f32. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.{add.1. 64-bit atom. Introduced in PTX ISA version 1. c) operation(*a.PTX ISA Version 2. d.my_new_val.exch} requires sm_12 or later. atom. : r+1.s. d.[x+4].add. 64-bit atom.add.cas.t) = (r == s) ? t operation(*a.

. an address maps to the corresponding location in local or shared memory. red. perform the memory accesses using generic addressing.add. the resulting behavior is undefined. s) = (r > s) ? s : r-1. dec(r. In generic addressing. .f32 }. dec.space}.type = { . If an address is not properly aligned. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Addresses are zero-extended to the specified width as needed.b]. or the instruction may fault. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. and max operations are single-precision. b). . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.and. The address size may be either 32-bit or 64-bit. . red{.u32. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. min. . Instruction Set Table 103. . The integer operations are add.op. A register containing an address may be declared as a bit-size type or integer type. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.Chapter 8. b. . . . min.inc.. max.s32.s32. and max. and xor. . The floating-point operations are add. and truncated if the register width exceeds the state space address width for the target architecture.s32.b32 only . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.dec. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u64.b32. or by using atom.u32 only .min. i. Within these windows. .xor. The address must be naturally aligned to a multiple of the access size. e.f32. January 24.b64.shared }. . i.e. overwriting the original value. or. or [immAddr] an immediate absolute byte address. Notes Operand a must reside in either the global or shared state space. . s) = (r >= s) ? 0 : r+1. . 2010 137 . If no state space is given. Semantics *a = operation(*a.max }. a de-referenced register areg containing a byte address.space = { .op = { . by inserting barriers between normal stores and reduction operations to a common address. . .global. The bit-size operations are and. where inc(r. inc..type [a]. accesses to local memory are illegal. Operand a specifies a location in the specified state space.u32. . . .g. an address maps to global memory unless it falls within the local memory window or the shared memory window.e. .f32 Performs a reduction operation with operand b and the value in location a. The floating-point add. and stores the result of the specified operation at location a.or.exch to store to locations accessed by other reduction operations.u32.u64 . Description // // // // . 32-bit operations. . The inc and dec operations return a result in the range [0.add. For red. min.

64-bit red. red. red. red.b32 [a].max} are unimplemented.shared operations require sm_20 or later.add requires sm_12 or later.global. Release Notes Examples @p 138 January 24.{min.and.f32. 64-bit red.shared requires sm_12 or later.2.add.global requires sm_11 or later red.PTX ISA Version 2.f32 requires sm_20 or later.f32 red.add.max. 2010 .0.s32 red. Use of generic addressing requires sm_20 or later. [x+4]. red. [p].0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.shared.global.1.my_val.

Negate the source predicate to compute . Negate the source predicate to compute . returns bitmask .uni. 2010 139 . r1.uni True if source predicate has the same value in all active threads in warp. Instruction Set Table 104.ballot.not_all.q.any True if source predicate is True for some active thread in warp.q.2. where the bit position corresponds to the thread’s lane id.p. vote.Chapter 8. {!}a. vote requires sm_12 or later.pred vote. .b32 d. Description Performs a reduction of the source predicate across threads in a warp. . PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. . Note that vote applies to threads in a single warp. Negating the source predicate also computes . .all. vote. vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. p.ballot. // get ‘ballot’ across warp January 24.uni }. // ‘ballot’ form.uni. The destination predicate value is the same across all threads in the warp. vote. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.mode = { .all True if source predicate is True for all active threads in warp.b32 p. vote.pred vote.any. not across an entire CTA.b32 requires sm_20 or later.none.ballot.ballot.pred d. In the ‘ballot’ form.mode. The reduction modes are: .all. {!}a.

The sign of the intermediate result depends on dtype. optionally clamp the result to the range of the destination type. c.atype = .sat}. // 32-bit scalar operation.PTX ISA Version 2.secop = { . and btype are valid. atype.btype = { .h1 }.0 8. . 3. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. .bsel = { .extended internally to . b{. b{.dtype.9. b{. .btype{.bsel}. 140 January 24.atype. to produce signed 33-bit input values. The source and destination operands are all 32-bit registers.dtype.u32.s32) is specified in the instruction type. perform a scalar arithmetic operation to produce a signed 34-bit result. Using the atype/btype and asel/bsel specifiers.b0.bsel}. or word values from its source operands. The type of each operand (.secop d.sat} d. a{.b1.asel}. vop. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.asel}. extract and sign. 4. .add.max }.7.btype{. with optional secondary operation vop. Video Instructions All video instructions operate on 32-bit register operands. taking into account the subword destination size in the case of optional data merging.b3. all combinations of dtype. . The general format of video instructions is as follows: // 32-bit scalar operation.atype.dsel = .min.s32 }. 2.or zero-extend byte.bsel}. . . . 2010 .s33 values. the input values are extracted and signor zero.btype{.atype. .dtype = . a{.s34 intermediate result. c. The primary operation is then performed to produce an .asel = .dtype.b2. .u32 or . half-word. . with optional data merge vop.asel}. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.h0.sat} d.dsel. a{. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).

c). 2010 141 .h1: return ((tmp & 0xffff) << 16) case .s33 optMerge( Modifier dsel. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. } } . January 24. c). S16_MIN ).s33 c) { switch ( secop ) { . .min: return MIN(tmp.s34 tmp. tmp. tmp. . The lower 32-bits are then written to the destination operand. U8_MAX. tmp.s33 optSaturate( .b3: return ((tmp & 0xff) << 24) default: return tmp. Instruction Set . . U16_MAX. S8_MAX.h0. S16_MAX. U16_MIN ). default: return tmp. Modifier dsel ) { if ( !sat ) return tmp.b1.b0: return ((tmp & 0xff) case .b1: return ((tmp & 0xff) << 8) case . The sign of the c operand is based on dtype.s33 tmp.max return MAX(tmp. tmp. . . . . Bool sign.b0. U32_MAX. switch ( dsel ) { case .s33 c ) switch ( dsel ) { case .b3: if ( sign ) return CLAMP( else return CLAMP( case . c). S8_MIN ). .b2: return ((tmp & 0xff) << 16) case .h0: return ((tmp & 0xffff) case . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).s33 optSecOp(Modifier secop. Bool sat. S32_MAX.b2.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. as shown in the following pseudocode. S32_MIN ).s33 tmp. c). . U8_MIN ).add: return tmp + c. tmp. . .Chapter 8. c). c). c). U32_MIN ).

s32.PTX ISA Version 2.btype{. vadd.min.btype{. bsel ). taking into account destination type and merge operations tmp = optSaturate( tmp. sat. a{. tmp = MIN( ta.btype{. dsel ).bsel = { . // 32-bit scalar operation. Perform scalar arithmetic operation with optional saturate. asel ). . c.dtype.asel}. tb = partSelectSignExtend( b.sat vabsdiff.b0. btype. tmp = MAX( ta. r2.b3. d = optSecondaryOp( op2.s32.u32.s32 }.atype.s32. vmin. r2. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.h0.op2 Description = = = = { vadd.bsel}.b2.u32.s32. r2.u32. r2.s32. c ).0 Table 105.b2. // 32-bit scalar operation.s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat vsub.asel}. vmin. // optional secondary operation d = optMerge( dsel.sat. tmp = | ta – tb |.atype.b0. tmp. with optional data merge vop. c. .dtype. b{. a{.add.btype = { .max }.0. and optional secondary arithmetic operation or subword data merge. Integer byte/half-word/word minimum / maximum. vmax require sm_20 or later.h1.dtype. vop.dsel .asel = .s32. Integer byte/half-word/word absolute value of difference.s32. a{.h1 }.or zero-extend based on source operand type ta = partSelectSignExtend( a. Semantics // saturate. b{.sat}. 2010 . vmin. .asel}.sat} d. r1.op2 d.atype = .add r1. . Video Instructions: vadd. atype. with optional secondary operation vop. r3.s32. vabsdiff.b0. vsub.dtype .sat} d. { . .atype. r1. // extract byte/half-word/word and sign. b{. r1. . vsub. // optional merge with c operand 142 January 24. . vmax vadd. vmax }. vabsdiff. r3.bsel}. tmp.s32. c ). c.sat vmin. . c.h0.h1. . vsub.bsel}. vadd.b1. r3. r3. tmp = ta – tb. . isSigned(dtype).h0.dsel. vabsdiff. tb ). .vop . vmax Syntax Integer byte/half-word/word addition / subtraction. tb ). vsub vabsdiff vmin.

b3.b0. atype. Semantics // extract byte/half-word/word and sign.u32{.u32.dtype.mode .b1.asel}.u32.dtype.bsel = { . if ( mode == .0. tb = partSelectSignExtend( b.s32. unsigned shift fills with zero. vshl. a{. if ( mode == . tmp. c ). 2010 143 .dsel. } // saturate. c.u32.asel}.wrap }. tmp.or zero-extend based on source operand type ta = partSelectSignExtend( a. . r3.atype.b2.asel = .add. . vshl: Shift a left by unsigned amount in b with optional saturate. Instruction Set Table 106.mode}.wrap ) tb = tb & 0x1f.min. dsel ). vop. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 vshr.clamp && tb > 32 ) tb = 32. // default is . with optional secondary operation vop.u32. .sat}{.atype.max }.op2 Description = = = = = { vshl. { . . . switch ( vop ) { case vshl: tmp = ta << tb. . vshr vshl. c. taking into account destination type and merge operations tmp = optSaturate( tmp.dtype. .s32 }. a{.op2 d. Video Instructions: vshl.wrap r1. vshl.bsel}. .h1. .sat}{. vshr }. vshr Syntax Integer byte/half-word/word left / right shift.dsel .h1 }. sat. with optional data merge vop.u32{. { . January 24. . bsel ). d = optSecondaryOp( op2.sat}{.mode} d. vshr require sm_20 or later.bsel}.Chapter 8.u32. Left shift fills with zero.bsel}. vshr: Shift a right by unsigned amount in b with optional saturate. isSigned(dtype).u32. // optional secondary operation d = optMerge( dsel.dtype . // 32-bit scalar operation. .h0.vop . a{. asel ). and optional secondary arithmetic operation or subword data merge.clamp. r2. b{.u32{. r2. // 32-bit scalar operation. b{. b{. r1.mode} d. r3.atype. c ). and optional secondary arithmetic operation or subword data merge. . Signed shift fills with the sign bit.clamp .asel}.atype = { . case vshr: tmp = ta >> tb.

otherwise. and zero-extended otherwise.po{. final signed (S32 * U32) + S32 // intermediate signed. .sat}{. The source operands support optional negation with some restrictions. “plus one” mode. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. 144 January 24. final unsigned -(U32 * U32) + S32 // intermediate signed.bsel}.scale} d.atype. . final signed -(S32 * U32) + S32 // intermediate signed.btype = { . vmad. PTX allows negation of either (a*b) or c. {-}b{.b2. Although PTX syntax allows separate negation of the a and b operands.h1 }.s32 }. Input c has the same sign as the intermediate result. The final result is unsigned if the intermediate result is unsigned and c is not negated. . final signed (U32 * U32) . with optional operand negates. b{. final signed (S32 * S32) . {-}a{.scale = { . the intermediate result is signed. c.btype. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.u32. final signed (S32 * S32) + S32 // intermediate signed.scale} d. .b3.PTX ISA Version 2. Source operands may not be negated in .bsel}. internally this is represented as negation of the product (a*b).atype = . 2010 . .po mode.shr15 }. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.asel}.dtype. .h0. final signed The intermediate result is optionally scaled via right-shift. // 32-bit scalar operation vmad.U32 // intermediate unsigned. final signed (S32 * U32) ..0 Table 107.S32 // intermediate signed. Description Calculate (a*b) + c.sat}{.asel = . final signed -(S32 * S32) + S32 // intermediate signed.dtype.b0. {-}c. The “plus one” mode (.S32 // intermediate signed. a{. .S32 // intermediate signed. final signed -(U32 * S32) + S32 // intermediate signed. . That is.bsel = { . and scaling.btype{. .dtype = .atype.po) computes (a*b) + c + 1. which is used in computing averages.shr7. final signed (U32 * S32) + S32 // intermediate signed.b1. this result is sign-extended if the final result is signed.asel}. (a*b) is negated if and only if exactly one of a or b is negated. . final signed (U32 * S32) . and the operand negates. Depending on the sign of the a and b operands.

lsb = 0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate.shr15 r0. r1. vmad.h0.0. } else if ( c. r2. tmp = tmp + c128 + lsb. -r3.shr7: result = (tmp >> 7) & 0xffffffffffffffff.sat vmad. vmad requires sm_20 or later. r0.sat ) { if (signedFinal) result = CLAMP(result. atype.u32. tb = partSelectSignExtend( b. signedFinal = isSigned(atype) || isSigned(btype) || (a. else result = CLAMP(result.u32.h0.po ) { lsb = 1. r1. Instruction Set Semantics // extract byte/half-word/word and sign. lsb = 1.s32. 2010 145 . } if ( .negate ) { tmp = ~tmp. r2. tmp[127:0] = ta * tb.s32. r3.or zero-extend based on source operand type ta = partSelectSignExtend( a. bsel ). switch( scale ) { case . btype. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. U32_MAX. January 24.negate ^ b. U32_MIN).negate ^ b.Chapter 8. lsb = 1. asel ).u32.u32. S32_MIN).negate ) { c = ~c. if ( . } else if ( a. case . S32_MAX. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).negate) || c.

a{.cmp d. 146 January 24. Semantics // extract byte/half-word/word and sign. c ).cmp .btype.lt. c.or zero-extend based on source operand type ta = partSelectSignExtend( a. . .btype = { .atype. { . 2010 .add.ge }. . // optional secondary operation d = optMerge( dsel. a{. . . b{.atype.atype . atype. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. c.asel}.lt vset.b1.asel}. and therefore the c operand and final result are also unsigned. .min.gt.u32. The intermediate result of the comparison is always unsigned.u32.s32. bsel ). tmp = compare( ta.u32.h1 }. b{.btype.b3.u32.b0.PTX ISA Version 2. with optional data merge vset. . vset.cmp d.bsel}.bsel}. btype.0 Table 108. . vset. .h1.bsel = { .bsel}. { . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // 32-bit scalar operation. r3. tmp. r2.ne.h0. // 32-bit scalar operation. r1. .le. .eq. asel ). .ne r1. .0.asel}.op2 Description = = = = . tb = partSelectSignExtend( b. Compare input values using specified comparison. vset requires sm_20 or later.dsel . tb.cmp.dsel. tmp. cmp ) ? 1 : 0. c ).asel = . r2. b{. a{.op2 d.atype. d = optSecondaryOp( op2. r3. .b2.btype. with optional secondary operation vset. . with optional secondary arithmetic operation or subword data merge.s32 }.max }.

trap Abort execution and generate an interrupt to the host CPU. pmevent 7.10. Introduced in PTX ISA version 1. numbered 0 through 15. brkpt requires sm_11 or later. with index specified by immediate operand a. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. The relationship between events and counters is programmed via API calls from the host. Supported on all target architectures. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.Chapter 8. @p pmevent 1. Introduced in PTX ISA version 1.4.0.0. January 24. Triggers one of a fixed number of performance monitor events. Supported on all target architectures. brkpt. trap.7. brkpt. Table 110. Instruction Set 8. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. pmevent a. 2010 147 . there are sixteen performance monitor events. brkpt Suspends execution Introduced in PTX ISA version 1. trap. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Table 111. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.

0 148 January 24. 2010 .PTX ISA Version 2.

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. …. %lanemask_ge. read-only variables. Special Registers PTX includes a number of predefined. 2010 149 . %lanemask_gt %clock. %lanemask_lt. %pm3 January 24. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_le.Chapter 9. %clock64 %pm0.

read-only special register initialized with the number of thread ids in each CTA dimension.y == %tid. mov. %ntid. 2010 .z.x code accessing 16-bit component of %tid mov. // compute unified thread id for 2D CTA mov.x. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.u32 %r1. // zero-extend tid.sreg .y < %ntid. The number of threads in each dimension are specified by the predefined special register %ntid. or 3D vector to match the CTA shape.u32 %r0. Supported on all target architectures.u32 %r0. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.u32 %tid. mad. . the fourth element is unused and always returns zero. %ntid.%tid.v4. // thread id vector // thread id components A predefined.v4 .%tid.y == %ntid.u32. %tid.z.%ntid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. It is guaranteed that: 0 <= %tid.x.x * %ntid.0 Table 112.v4 .y.z). Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x.PTX ISA Version 2.x < %ntid.z == 1 in 2D CTAs. per-thread special register initialized with the thread identifier within the CTA. // legacy PTX 1. %tid. %ntid.u32 %ntid. %tid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.y.u32 %ntid.z to %r2 Table 113.y. read-only.sreg . %ntid.y 0 <= %tid.%tid. Supported on all target architectures.%h1. %tid component values range from 0 through %ntid–1 in each CTA dimension.x code Target ISA Notes Examples 150 January 24.v4. .z < %ntid. .x 0 <= %tid. Redefined as . The total number of threads in a CTA is (%ntid. the %tid value in unused dimensions is 0.u32 %h1.0. // move tid.u32 type in PTX 2. CTA dimensions are non-zero.0.x.x to %rh Target ISA Notes Examples // legacy PTX 1. mov.u32 %tid.u16 %rh.u16 %rh.y * %ntid.%tid.x. .u32 %h2.0.x.z == 0 in 1D CTAs. 2D.sreg .x. The fourth element is unused and always returns zero. Every thread in the CTA has a unique %tid.z PTX ISA Notes Introduced in PTX ISA version 1. // CTA shape vector // CTA dimensions A predefined. mov.sreg . %tid.%h2. cvt.%ntid.0. Redefined as .u16 %r2. mov. The %tid special register contains a 1D.%tid. PTX ISA Notes Introduced in PTX ISA version 1.z.z == 1 in 1D CTAs.z == 0 in 2D CTAs.%r0.u32 type in PTX 2.

read-only special register that returns the thread’s lane within the warp.sreg .sreg . 2010 151 . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Introduced in PTX ISA version 1.u32 %r. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. Introduced in PTX ISA version 2. due to rescheduling of threads following preemption.3. The warp identifier will be the same for all threads within a single warp. Supported on all target architectures.3. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %nwarpid. A predefined. .sreg . A predefined. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. e.u32 %warpid. %nwarpid requires sm_20 or later. Note that %warpid is volatile and returns the location of a thread at the moment when read. PTX ISA Notes Target ISA Notes Examples Table 116. read-only special register that returns the maximum number of warp identifiers. The lane identifier ranges from zero to WARP_SZ-1.0.g. read-only special register that returns the thread’s warp identifier. %nwarpid. . January 24. A predefined. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. mov. mov. For this reason.u32 %r. but its value may change during execution. mov. Introduced in PTX ISA version 1. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.u32 %laneid. %warpid. Special Registers Table 114. . Supported on all target architectures.Chapter 9.u32 %r. Table 115. %laneid.

%nctaid. read-only special register initialized with the CTA identifier within the CTA grid.u32 mov. mov.x. depending on the shape and rank of the CTA grid. mov. .u32 %ctaid.u32 %nctaid.y 0 <= %ctaid.u32 mov.z.u32 %nctaid . %ctaid.sreg . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.z. The fourth element is unused and always returns zero.y < %nctaid. The %nctaid special register contains a 3D grid shape vector.sreg .0.{x. with each element having a value of at least 1.sreg . Redefined as . %ctaid.y.y. // Grid shape vector // Grid dimensions A predefined.sreg .PTX ISA Version 2. The %ctaid special register contains a 1D.%nctaid. // CTA id vector // CTA id components A predefined.%ctaid. Supported on all target architectures.v4 .x code Target ISA Notes Examples Table 118. . It is guaranteed that: 1 <= %nctaid.0. Redefined as .x. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. read-only special register initialized with the number of CTAs in each grid dimension.%nctaid.y.z} < 65. . 2010 .%ctaid.u16 %r0.x.x. The fourth element is unused and always returns zero. %rh.536 PTX ISA Notes Introduced in PTX ISA version 1.0 Table 117.u32 %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.0. It is guaranteed that: 0 <= %ctaid.v4 . 2D.x. %rh.x < %nctaid.v4.%nctaid.x 0 <= %ctaid.x code Target ISA Notes Examples 152 January 24. // legacy PTX 1.u32 type in PTX 2.z < %nctaid.z PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures. // legacy PTX 1.v4.0.y. Each vector element value is >= 0 and < 65535. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.u32 type in PTX 2.u16 %r0. or 3D vector.

. PTX ISA Notes Target ISA Notes Examples Table 121. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Supported on all target architectures. read-only special register that returns the maximum number of SM identifiers. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Special Registers Table 119. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.sreg . The SM identifier numbering is not guaranteed to be contiguous. so %nsmid may be larger than the physical number of SMs in the device. %gridid. The SM identifier numbering is not guaranteed to be contiguous.Chapter 9. . This variable provides the temporal grid launch number for this context. Supported on all target architectures. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %gridid. but its value may change during execution. Introduced in PTX ISA version 2.3. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Introduced in PTX ISA version 1. %smid.u32 %r.u32 %r. mov. mov.u32 %nsmid. where each launch starts a grid-of-CTAs. %nsmid.0. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. A predefined. Introduced in PTX ISA version 1. A predefined. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. // initialized at grid launch A predefined.u32 %r. due to rescheduling of threads following preemption.sreg . e.u32 %smid. mov. PTX ISA Notes Target ISA Notes Examples January 24. Note that %smid is volatile and returns the location of a thread at the moment when read. %nsmid requires sm_20 or later. . repeated launches of programs may occur.sreg . The SM identifier ranges from 0 to %nsmid-1. During execution.g. 2010 153 .0. read-only special register initialized with the per-grid temporal grid identifier.

%lanemask_lt. Introduced in PTX ISA version 2. 2010 . 154 January 24.0. . Introduced in PTX ISA version 2.u32 %lanemask_eq. %lanemask_eq. mov. Table 123.sreg . A predefined. A predefined.u32 %lanemask_le.u32 %r.0. mov. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.u32 %r.PTX ISA Version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. .sreg .sreg . A predefined. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_le.0.u32 %lanemask_lt. mov. %lanemask_lt requires sm_20 or later. %lanemask_le requires sm_20 or later. . %lanemask_eq requires sm_20 or later.0 Table 122. Table 124. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.u32 %r.

Special Registers Table 125. . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. 2010 155 . A predefined.u32 %lanemask_gt. A predefined. .Chapter 9.u32 %lanemask_ge.sreg . mov. mov. %lanemask_gt requires sm_20 or later. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.0.sreg . %lanemask_gt. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. January 24. %lanemask_ge requires sm_20 or later.u32 %r.0. %lanemask_ge.u32 %r. Table 126.

u32 %clock. 156 January 24. Supported on all target architectures.%pm0. Introduced in PTX ISA version 1. Supported on all target architectures.0.PTX ISA Version 2. %pm2. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. . %pm3 %pm0. read-only 32-bit unsigned cycle counter. Introduced in PTX ISA version 2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.sreg . Table 128. Their behavior is currently undefined.u64 r1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm1.u32 r1. mov. %pm2. .0. %clock64 requires sm_20 or later. %pm1.u32 %pm0. Introduced in PTX ISA version 1. %pm2.0 Table 127. mov. read-only 64-bit unsigned cycle counter. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.sreg .3. %pm3. %pm1. …. Special registers %pm0.u32 r1. Table 129.sreg . The lower 32-bits of %clock64 are identical to %clock. Special Registers: %pm0. .%clock64.%clock. 2010 . mov. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.u64 %clock64. and %pm3 are unsigned 32-bit read-only performance monitor counters.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.4 January 24. Directives 10.version directive.version .0 .target Table 130. Increments to the major number indicate incompatible changes to PTX.version 2.version .0. Each ptx file must begin with a . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Duplicate .version Syntax Description Semantics PTX version number.minor // major. Supported on all target architectures.version major. minor are integers Specifies the PTX language version number.Chapter 10. PTX File Directives: . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. . .version directives are allowed provided they match the original . . and the target architecture for which the code was generated.1.version directive.version 1. 2010 157 .

texmode_unified . with only half being used by instructions converted from . PTX features are checked against the specified target architecture.texmode_independent texture and sampler information is bound together and accessed via a single . The following table summarizes the features in PTX that vary according to target architecture. Requires map_f64_to_f32 if any .red}. map_f64_to_f32 }.PTX ISA Version 2. but subsequent . A . Requires map_f64_to_f32 if any .5.target directive specifies a single target architecture. where each generation adds new features and retains all features of previous generations.target directive containing a target architecture and optional platform options. In general.target directives can be used to change the set of target features allowed during parsing. Each PTX file must begin with a .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.shared. PTX File Directives: .target . and an error is generated if an unsupported feature is used. Texturing mode: (default is . Adds {atom. Supported on all target architectures.samplerref descriptors. texmode_independent.f64 storage remains as 64-bits. Adds double-precision support. Therefore. Disallows use of map_f64_to_f32.global. sm_13. Note that . Description Specifies the set of features in the target architecture for which the current ptx code was generated. 64-bit {atom.f64 instructions used. A program with multiple . The texturing mode is specified for an entire module and cannot be changed within the module.texref and .red}.texmode_unified) . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.f64 instructions used.f64 instructions used. vote instructions. Texturing mode introduced in PTX ISA version 1. . texture and sampler information is referenced with independent . Adds {atom. Target sm_20 Description Baseline feature set for sm_20 architecture. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.0 Table 131. brkpt instructions.target Syntax Architecture and Platform target.texref descriptor. immediately followed by a . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.f32. Introduced in PTX ISA version 1. 158 January 24. including expanded rounding modifiers. Requires map_f64_to_f32 if any . 2010 .0. sm_10.f64 to . sm_11.global. PTX code generated for a given target can be run on later generation devices. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.red}. texmode_unified. generations of SM architectures follow an “onion layer” model.version directive. sm_12.

Directives Examples . texmode_independent January 24. 2010 159 .Chapter 10.target sm_10 // baseline target architecture .target sm_20.target sm_13 // supports double-precision .

and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.2.param. .entry Syntax Description Kernel entry point and body.entry .surfref variables may be passed as parameters. and . ld.b32 %r<99>. store. .texref. parameter variables are declared in the kernel parameter list. 2010 .0 10.param space memory and are listed within an optional parenthesized parameter list. with optional parameters.b32 %r2.b32 %r3. the kernel dimensions and properties are established and made available via special registers. ld.0 through 1.samplerref. In addition to normal parameters. [y].param. . parameter variables are declared in the kernel body. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. e. For PTX ISA versions 1.b32 z ) Target ISA Notes Examples [x]. %nctaid. . PTX ISA Notes For PTX ISA version 1. and query instructions and cannot be accessed via ld. opaque .g. parameters.b32 x. and body for the kernel function. %ntid. Kernel and Function Directives: . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. These parameters can only be referenced by name within texture and surface load. . Semantics Specify the entry point for a kernel program.param instructions. … } .param. Parameters are passed via .entry kernel-name ( param-list ) kernel-body .param .b32 y.0 through 1. [z].func Table 132.4 and later.entry .entry kernel-name kernel-body Defines a kernel entry point name. At kernel launch. ld.5 and later. Supported on all target architectures. .PTX ISA Version 2.3.param .param { .reg . The shape and size of the CTA executing the kernel are available in special registers. 160 January 24.param instructions.b32 %r1.entry filter ( . etc.4.entry cta_fft . Parameters may be referenced by name within the kernel body and loaded into registers using ld.

PTX ISA 2. Parameters must be base types in either the register or parameter state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.param state space.2 for a description of variadic functions. and recursion is illegal.Chapter 10. Directives Table 133.0 with target sm_20 supports at most one return value. there is no stack.b32 localVar. } … call (fooval).0. implements an ABI with stack. The implementation of parameter passing is left to the optimizing translator.func Syntax Function definition. … Description // return value in fooval January 24.func . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Release Notes For PTX ISA version 1.f64 dbl) { .func fname function-body . Parameter passing is call-by-value. . mov.func (. if any. . other code.reg .0 with target sm_20 allows parameters in the .b32 rval) foo (. ret. parameters must be in the register state space. Parameters in .param space are accessed using ld. .b32 rval.param and st. and supports recursion.reg .reg . Supported on all target architectures. val1). Variadic functions are currently unimplemented. … use N. A . dbl.param instructions in the body. Variadic functions are represented using ellipsis following the last fixed argument.reg . foo. PTX 2. 2010 161 .func (ret-param) fname (param-list) function-body Defines a function.func definition with no body provides a function prototype. The parameter lists define locally-scoped variables in the function body. including input and return parameters and optional function body.func fname (param-list) function-body .result. Parameters in register state space may be referenced directly within instructions in the function body.x code. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Kernel and Function Directives: .b32 N. which may use a combination of registers and stack locations to pass parameters. (val0.

pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. registers) to increase total thread count and provide a greater opportunity to hide memory latency. and the . which pass information to the backend optimizing compiler. at entry-scope. the .0 10.maxntid.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. to throttle the resource requirements (e. 2010 . or as statements within a kernel or device function body. the .pragma The .maxntid .maxntid directive specifies the maximum number of threads in a thread block (CTA). and .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.3.minnctapersm .maxnctapersm (deprecated) .pragma directive is supported for passing information to the PTX backend. PTX supports the following directives. The interpretation of . A general .g. and the strings have no semantics within the PTX virtual machine model.entry directive and its body. The directives take precedence over any module-level constraints passed to the optimizing backend. 162 January 24.maxnreg.PTX ISA Version 2. Note that .minnctapersm directives may be applied per-entry and must appear between an .maxnreg . for example. . These can be used. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxntid and . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. Currently.pragma directives may appear at module (file) scope. The . The directive passes a list of strings to the backend.

The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.3.entry foo . The actual number of registers used may be less. the backend may be able to compile to fewer registers. Introduced in PTX ISA version 1.maxntid 256 . The maximum number of threads is the product of the maximum extent in each dimension. or the maximum number of registers may be further constrained by .maxctapersm. This maximum is specified by giving the maximum extent of each dimention of the 1D. Performance-Tuning Directives: . nz Declare the maximum number of threads in the thread block (CTA).maxnreg n Declare the maximum number of registers per thread in a CTA. . ny . 2010 163 . for example. Performance-Tuning Directives: . .16.maxntid 16.maxntid nx.entry bar . 2D. Supported on all target architectures. Exceeding any of these limits results in a runtime error or kernel launch failure. .maxntid nx.maxntid and . .maxntid Syntax Maximum number of threads in thread block (CTA).entry foo . Directives Table 134. ny. Supported on all target architectures.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.3.maxntid .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxntid nx .Chapter 10.maxnreg . The compiler guarantees that this limit will not be exceeded. Introduced in PTX ISA version 1.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. or 3D CTA.

The optimizing backend compiler uses . . Introduced in PTX ISA version 2. Optimizations based on . Supported on all target architectures.maxntid and .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm .0.entry foo .minnctapersm generally need .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxntid to be specified as well. However. Performance-Tuning Directives: .entry foo . For this reason.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid 256 .maxntid to be specified as well. . Performance-Tuning Directives: . 2010 .maxnctapersm.0. Introduced in PTX ISA version 1.0 Table 136. additional CTAs may be mapped to a single multiprocessor.0 as a replacement for . Supported on all target architectures.minnctapersm in PTX ISA version 2.PTX ISA Version 2. .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxntid 256 .3.maxnctapersm generally need .maxnctapersm has been renamed to .minnctapersm 4 { … } 164 January 24. . Optimizations based on .maxnctapersm (deprecated) . . Deprecated in PTX ISA version 2.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).

0.entry foo .pragma Syntax Description Pass directives to PTX backend compiler. .pragma list-of-strings . { … } January 24. Directives Table 138. 2010 165 . . or at statementlevel.pragma “nounroll”. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Performance-Tuning Directives: .pragma directive may occur at module-scope. The interpretation of . or statement-level directives to the PTX backend compiler.pragma . at entry-scope. entry-scoped. The . Introduced in PTX ISA version 2.pragma directive strings is implementation-specific and has no impact on PTX semantics. See Appendix A for descriptions of the pragma strings defined in ptxas. Pass module-scoped.pragma “nounroll”. Supported on all target architectures.Chapter 10.

.0 and replaces the @@DWARF syntax. 0x00.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.byte 0x2b. The @@DWARF syntax is deprecated as of PTX version 2. 0x61395a5f. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.PTX ISA Version 2.debug_info .2.section directive is new in PTX ISA verison 2.4byte 0x6e69616d. 0x736d6172 .232-1] . Table 139. 0x00000364.0 10.x code.section . 0x6150736f.4byte 0x000006b5.4byte label . 0x00. 0x02.byte byte-list // comma-separated hexadecimal byte values . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x63613031.4byte . Deprecated as of PTX 2.loc The .file . Supported on all target architectures. Introduced in PTX ISA version 1.byte 0x00.section .0 but is supported for legacy PTX version 1. 0x00.debug_pubnames. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x00.264-1] . 2010 . 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0.0.quad int64-list // comma-separated hexadecimal integers in range [0.4.. @progbits . 0x00 . 0x5f736f63 . replaced by . @@DWARF dwarf-string dwarf-string may have one of the . 0x00. 0x00 166 January 24.section directive. “”.

Directives Table 140.b64 int64-list // comma-separated list of integers in range [0.255] .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00.b8 byte-list // comma-separated list of integers in range [0.b32 int32-list // comma-separated list of integers in range [0. Supported on all target architectures. . 0x5f736f63 0x6150736f. 0x00.b8 0x00.loc line_number January 24.section . Supported on all target architectures. Supported on all target architectures.0.b32 0x6e69616d. .section Syntax PTX section definition.b32 . Source file information. 0x00.debug_info .. .. . Debugging Directives: .264-1] .232-1] .file .file filename Table 142. Debugging Directives: .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x736d6172 0x00 Table 141. Source file location.b32 label .Chapter 10.section . . 0x00. 0x00000364. . 0x00 0x61395a5f. 2010 167 . } 0x02. 0x00.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x000006b5. Debugging Directives: .b8 0x2b.debug_pubnames { .. 0x00. replaces @@DWARF syntax. .0. 0x63613031.loc .0.

PTX ISA Version 2. Introduced in PTX ISA version 1.0 10.global . 2010 .visible Table 143. . Linking Directives: .0.b32 foo.extern .0.visible . .global .extern .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Introduced in PTX ISA version 1. . Linking Directives .extern identifier Declares identifier to be defined externally.visible identifier Declares identifier to be externally visible.6.b32 foo. Supported on all target architectures. Supported on all target architectures. // foo is defined in another module Table 144. // foo will be externally visible 168 January 24.visible .extern . . Linking Directives: .

0 CUDA 1.1 PTX ISA 1.Chapter 11.0 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.0.3 PTX ISA 1. The release history is as follows. CUDA Release CUDA 1.0 CUDA 2.2 CUDA 2. 2010 169 .4 PTX ISA 1.1 CUDA 2.2 PTX ISA 1.5 PTX ISA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 driver r195 PTX ISA Version PTX ISA 1.1 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.0 January 24.3 driver r190 CUDA 3.

The goal is to achieve IEEE 754 compliance wherever possible. A single-precision fused multiply-add (fma) instruction has been added. while maximizing backward compatibility with legacy PTX 1.0 for sm_20 targets.1. When code compiled for sm_1x is executed on sm_20 devices.ftz modifier may be used to enforce backward compatibility with sm_1x.f32 maps to fma. Single-precision add.ftz and .1.rm and . Both fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.1. rcp. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The mad.PTX ISA Version 2.0 11. The fma. and mul now support . The mad. fma. Single.1.x code and sm_1x targets. Changes in Version 2.1. The changes from PTX ISA 1. 2010 .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 instruction also supports . and sqrt with IEEE 754 compliant rounding have been added. Instructions testp and copysign have been added.f32 for sm_20 targets.0 11. • • • • • 170 January 24. New Features 11.f32 requires sm_20.rp rounding modifiers for sm_20 targets.rn.f32 and mad. sub.1.and double-precision div. These are indicated by the use of a rounding modifier and require sm_20.sat modifiers.f32 require a rounding modifier for sm_20 targets.f32. The . mad.

A “vote ballot” instruction.Chapter 11. e. bar now supports optional thread count and register operands. bfe and bfi. atom.2. The .le. has been added. A “find leading non-sign bit” instruction. Bit field extract and insert instructions. prefetchu.arrive instruction has been added.red. clz. for prefetching to specified level of memory hierarchy.sys. have been added.minnctapersm to better match its behavior and usage. has been added. Other new features Instructions ld. has been added.1.g. isspacep. Instruction cvta for converting global. Release Notes 11.{and.lt. has been added. has been added. 11. suld. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. st. A “count leading zeros” instruction. ldu.1. Surface instructions support additional . Instructions {atom. has been added. local.3. %clock64.maxnctapersm directive was deprecated and replaced with .1.zero. st. Instructions {atom.f32 have been implemented.clamp and .b32. The bar instruction has been extended as follows: • • • A bar. and sust. Instructions prefetch and prefetchu have also been added. A “population count” instruction. vote.shared have been extended to handle 64-bit data types for sm_20 targets. Instruction sust now supports formatted surface stores. has been added. 2010 171 . brev.clamp modifiers.add. A new directive.red. Video instructions (includes prmt) have been added.u32 and bar.gt} have been added. and shared addresses to generic address and vice-versa has been added. ldu.section. %lanemask_{eq.ge.red}. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.pred have been added. cvta. popc. and red now support generic addressing.or}. A “bit reversal” instruction. Cache operations have been added to instructions ld. A system-level membar instruction.1. bfind.popc.ballot. Instructions bar. January 24. prefetch. New instructions A “load uniform” instruction. membar.red}. New special registers %nsmid. . .

stack-based ABI is unimplemented.u32.s32.3.4 and earlier. Support for variadic functions and alloca are unimplemented.PTX ISA Version 2.red}.ftz (and cvt for .1.5. The underlying. Semantic Changes and Clarifications The errata in cvt.f32.1. the correct number is sixteen. has been fixed. To maintain compatibility with legacy PTX code. Formatted surface load is unimplemented.{u32. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. 2010 .s32. cvt. {atom.4 or earlier. In PTX version 1. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.{min. 11. Instruction bra.ftz for PTX ISA versions 1. See individual instruction descriptions for details.5 and later.f32} atom.0 11.p. if . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.p sust. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. where .2.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. . call suld. Formatted surface store with . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. 172 January 24.max} are not implemented.target sm_1x.version is 1.f32 type is unimplemented. or .

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.pragma “nounroll”. .pragma “nounroll”. Table 145. Ignored for sm_1x targets. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.Appendix A. … @p bra L1_end. L1_end: … } // do not unroll this loop January 24. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. disables unrolling of0 the loop for which the current block is the loop header. Descriptions of . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. 2010 173 .entry foo (…) . and statement levels.pragma strings defined by ptxas. . { … } // do not unroll any loop in this function .func bar (…) { … L1_head: .pragma Strings This section describes the . The “nounroll” pragma is allowed at module. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. disables unrolling for all loops in the entry function body. including loops preceding the .pragma “nounroll”.0.pragma. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. L1_body: … L1_continue: bra L1_head. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. entry-function. Supported only for sm_20 targets. Note that in order to have the desired effect at statement level.

2010 .0 174 January 24.PTX ISA Version 2.

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