ptx_isa_2.0 | Thread (Computing) | Parallel Computing

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PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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......................... 6.............. Sampler.............. State Spaces........................................................................... 32 Texture State Space (deprecated) ...............4............................5...8......... 43 6............... 5.....1......................................... 34 Variables ...... 5.......................2.............................. Function declarations and definitions ...................... Arrays............................................4...... 5..................................... 44 Scalar Conversions ..........................................1.......................................................................2................................ 43 Vectors as Operands ............................................................................... 41 Destination Operands ....... 33 Restricted Use of Sub-Word Sizes .1.................................................. 38 Initializers ....... 6............................................... 47 Chapter 7............ 27 Register State Space ............................................................................................................................................................................................................. Operand Type Information ........................................................... 5..... 28 Special Register State Space .................................................... 2010 ..4....................... Type Conversion............ and Vectors .....................2........ 49 ii January 24.......1.............................. and Variables .....................................6......4........................................................1........ 5............ and Surface Types ..................... 5.............................................1.............................................3..................... Summary of Constant Expression Evaluation Rules ........2........4....4......................................... 29 Local State Space ................4................ Types............................ Abstracting the ABI ........................ Instruction Operands........ 38 Alignment ..........................................................................4....................3..1.......... 6..................4.................................. Types ............ 6................5... 33 Fundamental Types .1........1............4.........................................1.5..........4....... 44 Rounding Modifiers ................................ 29 Parameter State Space ..... 5.............................................................6.......... 5.... 6............................................................................ 5.......3......................... 41 Source Operands............ 37 Variable Declarations ....................................................................1..................................................... Texture............................. 46 6......6..................................................... 28 Constant State Space ..................... 42 Addresses as Operands .......................6..5....PTX ISA Version 2.........................................................................................................3....................... 30 Shared State Space................................... State Spaces ................................. 37 Vectors .................2....... 43 Labels and Function Names as Operands ....3.................. 39 5................ 5. 5.............1.. Chapter 6.................................1............5............................................1........................................................................5.........2.......................2...........4............. 6....0 4. 41 Using Addresses....................... 42 Arrays as Operands ... 6.........................................................................................................7................. 25 Chapter 5..... 6...............4........ 6.....4................. 27 5..............................................................2............................................2......................................... 41 6..........1... 5..................... 29 Global State Space .........1......................... 5...... 5.......................................... 5.................................................................. 49 7....... 5.......................................................... Operand Costs ................ 32 5.......... 39 Parameterized Variable Names ............... 33 5.... 37 Array Declarations ............4.

.............................4............................................................. Format and Semantics of Instruction Descriptions ...................2........................ 132 Video Instructions ... 63 Integer Arithmetic Instructions .....................................................................3................................................... 10................................ Directives ...................0 ......................8......2.................................... Special Registers .......10.................................................. Changes from PTX 1..................1.......................................... 81 Comparison and Selection Instructions .................................................................................... 8...................1............................................... 8.....................................3........... 56 Comparisons ... 7............ Chapter 9................ 8.......................................... 8.............................6...................1....................... 172 January 24............x ........1..........................1........................... Instructions .....................................................................3.............................7.......................................................................... 147 8.............................7........ Changes in Version 2................................ 166 Linking Directives ....................................1......... 149 Chapter 10.....7...... 8................................7........................................................................ 11.............................................. 170 New Features ................. 10............ 8.................... 172 Unimplemented Features Remaining ......................................................... PTX Version and Target Directives ....... 60 8.. 58 8................... 62 Machine-Specific Semantics of 16-bit Code ............1.............................. 8..... 140 Miscellaneous Instructions........................... 122 Control Flow Instructions ............7....................... 8.................. 8............................. 7............................................................................................................................................................................ 55 Predicated Execution ...................................................... Divergence of Threads in Control Constructs ............ 157 10..................... 8............................................................. Release Notes . 55 8............................. 11...........................1........................ 63 Floating-Point Instructions .2........ 57 Manipulating Predicates .....................1........1.........3.4..7......................2... 8........6....................1..........9...................... 10.......................................................... 157 Specifying Kernel Entry Points and Functions ......2.................6.. 8.................... 8.............4........ 169 11............3.............. 168 Chapter 11.............7................................................. 8..................................................................................... Type Information for Instructions and Operands ............................................................... 52 Variadic functions ..................1...................................... 160 Performance-Tuning Directives ......................4................................................ 2010 iii ................................ 10............7.. 8........................5.. Instruction Set .................... 100 Logic and Shift Instructions ..................................... 129 Parallel Synchronization and Communication Instructions .7............................... 8.......... 53 Alloca . 170 Semantic Changes and Clarifications . 162 Debugging Directives ................................................ 55 PTX Instructions ..6. 62 Semantics .......................... 108 Texture and Surface Instructions .... 54 Chapter 8...................... 104 Data Movement and Conversion Instructions .........................2..............7........ 62 8....................................................5................................................. 11......... 59 Operand Size Exceeding Instruction-Type Size .............7...........3.............7.................7..3...1...........

............ Descriptions of ......... 173 iv January 24..0 Appendix A.....................pragma Strings............ 2010 ..PTX ISA Version 2..........

............................................................................................................................... 27 Properties of State Spaces ..................................................... Table 29....................... Table 23..................................................................................... 45 Floating-Point Rounding Modifiers ..................................................................................... 67 Integer Arithmetic Instructions: mad ........ 33 Opaque Type Fields in Unified Texture Mode ............................................................................................................................................................. 28 Fundamental Type Specifiers .............................. Table 31.......... 70 Integer Arithmetic Instructions: sad ................................................. 57 Floating-Point Comparison Operators ................................. Table 15....................... 2010 v .......... 69 Integer Arithmetic Instructions: mad24 ....................................... Table 13... Table 17...... Table 12.......................................................... 66 Integer Arithmetic Instructions: mul ........................................ 60 Relaxed Type-checking Rules for Destination Operands..........................................................cc ........... Table 8....... Table 3.................................................... 23 Constant Expression Evaluation Rules ..................................... Table 4................................ 58 Floating-Point Comparison Operators Testing for NaN ....................................... Table 27............. Table 7................................................... Table 11................................ Unsigned Integer............................................................................. Table 9.................... 58 Type Checking Rules ............ Table 19..... 19 Predefined Identifiers ............................................. Table 20............................................................. 64 Integer Arithmetic Instructions: sub ............ 25 State Spaces ................................................................................ 65 Integer Arithmetic Instructions: sub......... Table 28........................................... Table 22. Table 26...... 68 Integer Arithmetic Instructions: mul24 ............. Table 25.......List of Tables Table 1.................................................................................................... 61 Integer Arithmetic Instructions: add .......... Table 32................... Table 18............................. 35 Opaque Type Fields in Independent Texture Mode ...... 64 Integer Arithmetic Instructions: add......... 46 Cost Estimates for Accessing State-Spaces ........................... Table 6........................... PTX Directives ........ 35 Convert Instruction Precision and Format ......................... 46 Integer Rounding Modifiers .. Table 14................................ 59 Relaxed Type-checking Rules for Source Operands ........... 20 Operator Precedence ............................................... and Bit-Size Types .................. Table 24................ Table 21....... 71 January 24.......................................... Table 16....................... 66 Integer Arithmetic Instructions: subc ................................... 65 Integer Arithmetic Instructions: addc ........................ Table 10............................................................................... Table 2......................................cc .......................................... 47 Operators for Signed Integer..... Table 5........................................................... 18 Reserved Instruction Keywords ................ Table 30........... 57 Floating-Point Comparison Operators Accepting NaN .

.................... Table 65. Table 55.................................................................................. Table 62................................. 75 Integer Arithmetic Instructions: brev ............. Table 35................................................. 101 Comparison and Selection Instructions: setp ....... Table 59.........................................PTX ISA Version 2.......................................................... 87 Floating-Point Instructions: mad .................................................................. Table 34...... 103 Comparison and Selection Instructions: slct .................................... Table 49............................................ Table 44... 72 Integer Arithmetic Instructions: neg ..................................................... 96 Floating-Point Instructions: cos ................. Table 63............. 90 Floating-Point Instructions: abs ...................................... Table 50............................ 73 Integer Arithmetic Instructions: max .................. Table 39................................ Table 68... Table 38................................................. Table 36.......................................................... Table 53................................................................................................................................. 92 Floating-Point Instructions: max ............................................................. Table 61.................................................................................................................................................... 85 Floating-Point Instructions: mul ....... 79 Summary of Floating-Point Instructions ................................................................... Table 40....... Table 52......... 91 Floating-Point Instructions: min ..................................................................... Table 57.............................................................. 76 Integer Arithmetic Instructions: bfe ................. 88 Floating-Point Instructions: div ........................................................................................................ 2010 ........ 102 Comparison and Selection Instructions: selp ......................................................... 84 Floating-Point Instructions: sub ................................................. 94 Floating-Point Instructions: rsqrt ...................................................................... 83 Floating-Point Instructions: add .................................................................... Table 69........... 97 Floating-Point Instructions: lg2 ................. Table 47........ Table 54........................................ Table 60..........................................................0 Table 33............................................. 73 Integer Arithmetic Instructions: popc ............................................. 71 Integer Arithmetic Instructions: abs ........... 72 Integer Arithmetic Instructions: min ..... Table 37.. 91 Floating-Point Instructions: neg ....................................................................................................................................... Table 48........... Table 56.......................................................... Table 51....... Table 43........... Integer Arithmetic Instructions: div . 74 Integer Arithmetic Instructions: bfind ........... 86 Floating-Point Instructions: fma ...... 95 Floating-Point Instructions: sin ........................................... 103 vi January 24... 77 Integer Arithmetic Instructions: bfi .............. Table 64........... Table 41............ 92 Floating-Point Instructions: rcp ................................................ 82 Floating-Point Instructions: testp ............................................ Table 67.................................................................................... 98 Floating-Point Instructions: ex2 ........................................... Table 45.............................................................. 78 Integer Arithmetic Instructions: prmt ......... 83 Floating-Point Instructions: copysign ... Table 46........................................... Table 58................................... 74 Integer Arithmetic Instructions: clz .................................... 71 Integer Arithmetic Instructions: rem ..................................................................... Table 42................... Table 66.... 93 Floating-Point Instructions: sqrt ................. 99 Comparison and Selection Instructions: set ...............................

.......... Table 71.................................................. Table 77............... Table 102..................................................................................... Table 98..... Table 97.............................................................. Table 93......... 127 Texture and Surface Instructions: suq .......................... 116 Data Movement and Conversion Instructions: prefetch................................................................ Table 96.............. Table 92...... 123 Texture and Surface Instructions: txq ...................... Table 87....................... 113 Data Movement and Conversion Instructions: ldu .......................... 111 Data Movement and Conversion Instructions: mov ....................... Table 105.. vmin.... Table 103................................................. 133 Parallel Synchronization and Communication Instructions: membar ....................... 112 Data Movement and Conversion Instructions: ld ......................... Table 75.............. Table 90.................................................................... Table 79..... vabsdiff... Table 81...................................................... vsub....................................................................................................................... 142 Video Instructions: vshl......................... 120 Texture and Surface Instructions: tex ............................................................................. Table 91......................................................................... 131 Control Flow Instructions: exit ............................ 119 Data Movement and Conversion Instructions: cvta .......................... Table 94. 137 Parallel Synchronization and Communication Instructions: vote ............ Table 106..... 130 Control Flow Instructions: call .. 115 Data Movement and Conversion Instructions: st ................... 134 Parallel Synchronization and Communication Instructions: atom .......... 125 Texture and Surface Instructions: sust ........ Table 100........................ 129 Control Flow Instructions: bra ..................... Table 95.................................. Table 84........... Table 85............. 105 Logic and Shift Instructions: or .................... Table 74........................ Table 80................................. 106 Logic and Shift Instructions: cnot . 131 Parallel Synchronization and Communication Instructions: bar ...................................................................... 118 Data Movement and Conversion Instructions: isspacep ........ 143 January 24.. 126 Texture and Surface Instructions: sured..................... vshr ......................................................................................................................................................................... Table 73.................... 107 Cache Operators for Memory Load Instructions ............ 135 Parallel Synchronization and Communication Instructions: red ...... 105 Logic and Shift Instructions: xor ...... Table 78............ Table 82............................................................................................ 119 Data Movement and Conversion Instructions: cvt ....... 139 Video Instructions: vadd..................... 130 Control Flow Instructions: ret .................................................................. 107 Logic and Shift Instructions: shr ................ Table 76....... 109 Cache Operators for Memory Store Instructions ........................................................................... Table 99................. Table 101.......... prefetchu ..................... Table 83.....Table 70................... Table 72............................. 124 Texture and Surface Instructions: suld .... 106 Logic and Shift Instructions: shl ..... vmax ...................................... 2010 vii .. 106 Logic and Shift Instructions: not ................. Table 86................................................................. Logic and Shift Instructions: and ....................... Table 104......... 110 Data Movement and Conversion Instructions: mov ....................... 129 Control Flow Instructions: @ ............ 128 Control Flow Instructions: { } ............ Table 89.......... Table 88.........................

.......................... Table 132........................................................................................................................................................................................... 150 Special Registers: %laneid ...... Table 115....................................... Table 111...... 163 Performance-Tuning Directives: ................................. Table 120.... %pm1......................................... 151 Special Registers: %warpid ................... 150 Special Registers: %ntid ........... 147 Miscellaneous Instructions: pmevent........................................ 147 Miscellaneous Instructions: brkpt .......................................................................... Table 126.... 153 Special Registers: %gridid . Table 121................... Table 139..............................................................................................................................entry............................. 163 Performance-Tuning Directives: .... 160 Kernel and Function Directives: ... 2010 ......................................................................................................... 167 Linking Directives: ....................extern.................................................................. Table 117... %pm2........................................................................................................ Table 124................................................. Table 125................... 167 Debugging Directives: ... Table 119.......... Table 122...............................maxnreg ....... Table 131.......................... 146 Miscellaneous Instructions: trap . 164 Performance-Tuning Directives: ......target .................... 151 Special Registers: %nwarpid ... 152 Special Registers: %nctaid ..version................................................................... Table 129..... Table 116............................... Table 143..................................................................... 153 Special Registers: %lanemask_eq ................................................ Table 109........ Table 138...........maxnctapersm (deprecated) ....... Table 135.................................................... Table 128................minnctapersm ................................ 151 Special Registers: %ctaid ...... Table 134................................... Table 108............. 152 Special Registers: %smid .............................................. Table 137........................................... 158 Kernel and Function Directives: .. Table 113............................................................................. 153 Special Registers: %nsmid .......................... %pm3 ...........maxntid .....file ............. 168 viii January 24.......pragma ...section ............................................................ Table 110............................................................................. Table 130............PTX ISA Version 2.... Table 112.. Table 114....... Table 141........................................ 164 Performance-Tuning Directives: ....................................................................... 161 Performance-Tuning Directives: ........................ 155 Special Registers: %lanemask_gt ................................................................................... 166 Debugging Directives: ............ 154 Special Registers: %lanemask_ge .... Table 123......................func . Table 136............................. 167 Debugging Directives: ............................... 157 PTX File Directives: ........ 144 Video Instructions: vset................................................................. Table 133......................................................................0 Table 107............................................................. 155 Special Registers: %clock . 147 Special Registers: %tid ................ 154 Special Registers: %lanemask_le ................................................. 156 Special Registers: %clock64 ........................................................ 156 Special Registers: %pm0..loc ....... Table 118........................ 165 Debugging Directives: @@DWARF ........................................ Table 142........................ 154 Special Registers: %lanemask_lt ............................ 156 PTX File Directives: .... Video Instructions: vmad . Table 127.................... Table 140.....

Table 145................... 173 January 24........................................................................visible......................... 2010 ix ......Table 144...... Linking Directives: ..... 168 Pragma Strings: “nounroll” ......................................

PTX ISA Version 2. 2010 .0 x January 24.

The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. which are optimized for and translated to native target-architecture instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth.1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). PTX exposes the GPU as a data-parallel computing device. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. and because it is executed on many data elements and has high arithmetic intensity. 1. 1. the memory access latency can be hidden with calculations instead of big data caches. there is a lower requirement for sophisticated flow control. high-definition 3D graphics. from general signal processing or physics simulation to computational finance or computational biology. video encoding and decoding. image scaling. Because the same program is executed for each data element. 2010 1 . multithreaded. Introduction This document describes PTX. and pattern recognition can map image blocks and pixels to parallel processing threads. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. In fact. PTX programs are translated at install time to the target hardware instruction set. Similarly. January 24. Data-parallel processing maps data elements to parallel processing threads. PTX defines a virtual machine and ISA for general purpose parallel thread execution. stereo vision. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions.Chapter 1. image and media processing applications such as post-processing of rendered images. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. the programmable GPU has evolved into a highly parallel. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing.2.

1.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. The mad. which map PTX to specific target machines. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. mad. Achieve performance in compiled applications comparable to native GPU performance. and architecture tests.0 is a superset of PTX 1. and mul now support . Both fma. surface.0 is in improved support for the IEEE 754 floating-point standard. memory. Provide a code distribution ISA for application and middleware developers.f32 for sm_20 targets. PTX 2.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.ftz) modifier may be used to enforce backward compatibility with sm_1x.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Facilitate hand-coding of libraries. performance kernels. PTX ISA Version 2. The main areas of change in PTX 2.1.rp rounding modifiers for sm_20 targets.rn. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The changes from PTX ISA 1. The mad.f32 and mad.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. 2010 . and the introduction of many new instructions. A single-precision fused multiply-add (fma) instruction has been added. Most of the new features require a sm_20 target.PTX ISA Version 2. When code compiled for sm_1x is executed on sm_20 devices.0 are improved support for IEEE 754 floating-point operations. fma. and all PTX 1. 1.f32 require a rounding modifier for sm_20 targets. • • • 2 January 24. Legacy PTX 1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.ftz and . Improved Floating-Point Support A main area of change in PTX 2. sub. The fma. barrier. addition of generic addressing to facilitate the use of general-purpose pointers.x features are supported on the new sm_20 target.rm and . Single-precision add.x code will continue to run on sm_1x targets as well.f32. atomic.x.sat modifiers. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.f32 requires sm_20.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.f32 instruction also supports . Provide a machine-independent ISA for C/C++ and other compilers to target. including integer.3.0 PTX ISA Version 2. Instructions marked with .f32 maps to fma. Provide a common source-level ISA for optimizing code generators and translators. and video instructions. A “flush-to-zero” (.3. reduction.

clamp and . and Application Binary Interface (ABI). an address that is the same across all threads in a warp. e. These are indicated by the use of a rounding modifier and require sm_20. for prefetching to specified level of memory hierarchy. so recursion is not yet supported. stack-based ABI. Instructions testp and copysign have been added. atom. • Taken as a whole. 2010 3 . Instructions prefetch and prefetchu have been added. and shared addresses to generic address and vice-versa has been added. and shared addresses to generic addresses. Surface Instructions • • Instruction sust now supports formatted surface stores. January 24. Introduction • Single. cvta. and directives are introduced in PTX 2.Chapter 1. suld.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Generic addressing unifies the global. and sust.0.2. prefetch.4. local.0. 1. and shared state spaces.3. and sqrt with IEEE 754 compliant rounding have been added. and red now support generic addressing. New Instructions The following new instructions. local. isspacep. PTX 2.e. local.and double-precision div.3. ldu. Support for an Application Binary Interface Rather than expose details of a particular calling convention. Surface instructions support additional clamp modifiers. stack layout. and vice versa. Cache operations have been added to instructions ld. st. allowing memory instructions to access these spaces without needing to specify the state space. In PTX 2. NOTE: The current version of PTX does not implement the underlying. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.3. A new cvta instruction has been added to convert global. 1. 1. these changes bring PTX 2. prefetchu. i. Instruction cvta for converting global.g. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.3. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. instructions ld.0 closer to full compliance with the IEEE 754 standard. special registers.zero. Generic Addressing Another major change is the addition of generic addressing. st. rcp.. .

A bar. bar now supports an optional thread count and register operands.gt} have been added. Other Extensions • • • Video instructions (includes prmt) have been added. membar.red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. bfi bit field extract and insert popc clz Atomic. New special registers %nsmid.red}.section.ballot.b32.pred have been added. Reduction. Instructions {atom. %lanemask_{eq.u32 and bar. Barrier Instructions • • A system-level membar instruction.f32 have been added. .lt. has been added.add.PTX ISA Version 2.{and. has been added. and Vote Instructions • • • New atomic and reduction instructions {atom.le. 2010 .0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.popc. vote. Instructions bar.sys.arrive instruction has been added.red.red}. A new directive. 4 January 24.ge.shared have been extended to handle 64-bit data types for sm_20 targets.or}. %clock64. A “vote ballot” instruction.

calling convention. Chapter 4 describes the basic syntax of the PTX language. 2010 5 . types. January 24. Chapter 5 describes state spaces. Chapter 7 describes the function and call syntax.4. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 6 describes instruction operands.Chapter 1. Chapter 8 describes the instruction set. Chapter 9 lists special registers. Chapter 10 lists the assembly directives supported in PTX. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and variable declarations.0. Introduction 1. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 11 provides release notes for PTX Version 2.

PTX ISA Version 2. 2010 .0 6 January 24.

Each thread has a unique thread identifier within the CTA. work. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. compute addresses.x. Programming Model 2. 2D. More precisely. Programs use a data parallel decomposition to partition inputs. or 3D shape specified by a three-element vector ntid (with elements ntid.1. 2. Each CTA thread uses its thread identifier to determine its assigned role.1. is an array of threads that execute a kernel concurrently or in parallel.z) that specifies the thread’s position within a 1D.y. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. A cooperative thread array. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. but independently on different data. January 24. tid. (with elements tid. To that effect. and select work to perform. and tid. assign specific input and output positions. a portion of an application that is executed many times. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2. Cooperative thread arrays (CTAs) implement CUDA thread blocks. or CTA. Threads within a CTA can communicate with each other. 2010 7 . and ntid.2.2. or host: In other words.x. The thread identifier is a three-element vector tid. ntid. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. or 3D CTA. and results across the threads of the CTA. can be isolated into a kernel function that is executed on the GPU as many different threads. Each CTA has a 1D.y.Chapter 2. data-parallel. To coordinate the communication of the threads within the CTA. The vector ntid specifies the number of threads in each CTA dimension. It operates as a coprocessor to the main CPU. 2D. compute-intensive portions of applications running on the host are off-loaded onto the device.z). Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.

%nctaid. such that the threads execute the same instructions at the same time. Each grid also has a unique temporal grid identifier (gridid). or sequentially.PTX ISA Version 2. or 3D shape specified by the parameter nctaid. 2010 . Typically. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. This comes at the expense of reduced thread communication and synchronization. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Each grid of CTAs has a 1D. CTAs that execute the same kernel can be batched together into a grid of CTAs. The host issues a succession of kernel invocations to the device. 2. Threads within a warp are sequentially numbered. Multiple CTAs may execute concurrently and in parallel. Some applications may be able to maximize performance with knowledge of the warp size. which may be used in any instruction where an immediate operand is allowed. %ctaid. A warp is a maximal subset of threads from a single CTA. The warp size is a machine-dependent constant.2. and %gridid.2. read-only special registers %tid. multiple-thread) fashion in groups called warps.0 Threads within a CTA execute in SIMT (single-instruction. However. 2D . because threads in different CTAs cannot communicate and synchronize with each other. a warp has 32 threads. so that the total number of threads that can be launched in a single kernel invocation is very large. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). WARP_SZ. so PTX includes a run-time immediate constant. 8 January 24. Threads may read and use these values through predefined. depending on the platform. %ntid.

Chapter 2. 0) Thread (2. 2) Thread (1. 1) Grid 2 Kernel 2 CTA (1. 0) CTA (2. 0) CTA (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. A grid is a set of CTAs that execute independently. Thread Batching January 24. 1) Thread (4. Figure 1. 1) CTA (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) Thread (1. 2010 9 . 0) Thread (3. 0) Thread (0. 1) Thread (2. 1) Thread (0. 2) Thread (3. 2) Thread (2. 1) Thread (0. 0) CTA (0. 2) Thread (4. 1) Thread (3. 1) Thread (1. 1) CTA (1. 0) Thread (4.

Each thread has a private local memory. 10 January 24. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. for more efficient transfer. constant. The global. respectively. Both the host and the device maintain their own local memory. constant. or. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. and texture memory spaces are persistent across kernel launches by the same application.0 2. for some specific data formats. The global. all threads have access to the same global memory.3. 2010 . Finally. and texture memory spaces are optimized for different memory usages. referred to as host memory and device memory.PTX ISA Version 2. Texture memory also offers different addressing modes. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. as well as data filtering. The device memory may be mapped and read or written by the host. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.

1) Grid 1 Global memory Block (0. 2010 11 . 1) Block (1. 0) Block (0. 0) Block (1. 2) Block (1. 0) Block (0. 1) Block (2. 1) Block (1. 0) Block (2. Memory Hierarchy January 24. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (0. 2) Figure 2.Chapter 2. 0) Block (1.

PTX ISA Version 2.0 12 January 24. 2010 .

1. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. each warp contains threads of consecutive. schedules. As thread blocks terminate. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). When a host program invokes a kernel grid. new blocks are launched on the vacated multiprocessors. and executes concurrent threads in hardware with zero scheduling overhead. a cell in a grid-based computation). (This term originates from weaving. a multithreaded instruction unit. a voxel in a volume. different warps execute independently regardless of whether they are executing common or disjointed code paths. The multiprocessor maps each thread to one scalar processor core. disabling threads that are not on that path. Branch divergence occurs only within a warp. and when all paths complete.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. manages. multiple-thread).Chapter 3. The multiprocessor creates. the multiprocessor employs a new architecture we call SIMT (single-instruction. January 24. To manage hundreds of threads running several different programs. so full efficiency is realized when all threads of a warp agree on their execution path. allowing. 2010 13 . The way a block is split into warps is always the same. A warp executes one common instruction at a time. Parallel Thread Execution Machine Model 3. and each scalar thread executes independently with its own instruction address and register state. If threads of a warp diverge via a data-dependent conditional branch. and on-chip shared memory. When a multiprocessor is given one or more thread blocks to execute. The multiprocessor SIMT unit creates. for example. manages. increasing thread IDs with the first warp containing thread 0. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. it splits them into warps that get scheduled by the SIMT unit. the warp serially executes each branch path taken. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. At every instruction issue time. the threads converge back to the same execution path. and executes threads in groups of parallel threads called warps. The threads of a thread block execute concurrently on one multiprocessor. the first parallel thread technology. It implements a single-instruction barrier synchronization. A multiprocessor consists of multiple Scalar Processor (SP) cores.

If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. SIMT enables programmers to write thread-level parallel code for independent. whereas SIMT instructions specify the execution and branching behavior of a single thread. the kernel will fail to launch. As illustrated by Figure 3. on the other hand. Vector architectures. and writes to the same location in global memory for more than one of the threads of the warp. modifies. If there are not enough registers or shared memory available per multiprocessor to process at least one block. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. which is a read-only region of device memory. but one of the writes is guaranteed to succeed. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space.0 SIMT architecture is akin to SIMD (Single Instruction. For the purposes of correctness. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. • The local and global memory spaces are read-write regions of device memory and are not cached. 14 January 24. In contrast with SIMD vector machines. In practice. require the software to coalesce loads into vectors and manage divergence manually. however. but the order in which they occur is undefined. write to that location occurs and they are all serialized. modify. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. 2010 . the number of serialized writes that occur to that location and the order in which they occur is undefined. If an atomic instruction executed by a warp reads. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance.PTX ISA Version 2. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. scalar threads. as well as data-parallel code for coordinated threads. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. each read. which is a read-only region of device memory. A multiprocessor can execute as many as eight thread blocks concurrently. A key difference is that SIMD vector organizations expose the SIMD width to the software. the programmer can essentially ignore the SIMT behavior. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks.

Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24. 2010 15 . Figure 3.

2010 .0 16 January 24.PTX ISA Version 2.

Source Format Source files are ASCII text. Pseudo-operations specify symbol and addressing management. All whitespace characters are equivalent. PTX is case sensitive and uses lowercase for keywords. Comments in PTX are treated as whitespace. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. whitespace is ignored except for its use in separating tokens in the language. and using // to begin a comment that extends to the end of the current line. The C preprocessor cpp may be used to process PTX source files. Syntax PTX programs are a collection of text source files. Comments Comments in PTX follow C/C++ syntax. 2010 17 . The following are common preprocessor directives: #include. #if.version directive specifying the PTX language version. January 24. Lines beginning with # are preprocessor directives. using non-nested /* and */ for comments that may span multiple lines. 4. #endif. Each PTX file must begin with a . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #define. 4.1. Lines are separated by the newline character (‘\n’). The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #line.Chapter 4. See Section 9 for a more information on these directives.2.target directive specifying the target architecture assumed. #ifdef. #else. followed by a .

const .b32 r1.x. Operands may be register variables. and terminated with a semicolon.0 4.minnctapersm .b32 r1.entry . Examples: .5. address expressions. shl. or label names. where p is a predicate register. r2.global . and is written as @p. Statements begin with an optional label and end with a semicolon. 18 January 24.align .1. .3.loc .shared . followed by source operands. Statements A PTX statement is either a directive or an instruction.file PTX Directives . %tid. Table 1. .version .func . Directive Statements Directive keywords begin with a dot. so no conflict is possible with user-defined identifiers.b32 add. All instruction keywords are reserved tokens in PTX. 2010 . constant expressions.global start: . 2.global.sreg .maxntid .local . Instruction keywords are listed in Table 2.2.target .b32 r1.pragma .3.visible 4. Instructions have an optional guard predicate which controls conditional execution.PTX ISA Version 2. r2. written as @!p.maxnctapersm . The guard predicate may be optionally negated. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. r2.param . r1.tex . ld.reg .section . array[r1].f32 r2.f32 array[N].maxnreg . mov.reg . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.extern . The guard predicate follows the optional label and precedes the opcode. 0. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. The destination operand is first.3.

Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.

listed in Table 3. or percentage character followed by one or more letters. …. or they start with an underscore. between user-defined variable names and compiler-generated names.0 4.g.PTX ISA Version 2. Many high-level languages such as C and C++ follow similar rules for identifier names. underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Table 3. The percentage sign can be used to avoid name conflicts. digits. PTX allows the percentage sign as the first character of an identifier. dollar. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or dollar characters. underscore. %pm3 WARP_SZ 20 January 24. digits. except that the percentage sign is not allowed. PTX predefines one constant and a small number of special registers that begin with the percentage sign.4. e. 2010 .

u64). 2010 21 .5. zero values are FALSE and non-zero values are TRUE. To specify IEEE 754 doubleprecision floating point values. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. and bit-size types. or binary notation. 4. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. i. The syntax follows that of C. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. hexadecimal.s64 or the unsigned suffix is specified. the constant begins with 0f or 0F followed by 8 hex digits. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.u64. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.. octal.Chapter 4. there is no suffix letter to specify size.s64) unless the value cannot be fully represented in .. in which case the literal is unsigned (. When used in an instruction or data initialization. 0[fF]{hexdigit}{8} // single-precision floating point January 24.e. For predicate-type data and instructions.5.e. every integer constant has type . Type checking rules remain the same for integer. integer constants are allowed and are interpreted as in C. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. Floating-point literals may be written with an optional decimal point and an optional signed exponent. These constants may be used in data initialization and as operands to instructions. Syntax 4. To specify IEEE 754 single-precision floating point values. Integer literals may be written in decimal. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. where the behavior of the operation depends on the operand types. Unlike C and C++. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. floating-point. Constants PTX supports integer and floating-point constants and constant expressions. 4.1.2. i. the constant begins with 0d or 0D followed by 16 hex digits.5. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. each integer constant is converted to the appropriate size based on the data or instruction type at its use.s64 or . The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. literals are always represented in 64-bit double-precision format. the sm_1x and sm_20 targets have a WARP_SZ value of 32.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 use usual conversions .f64 converted type constant literal + ! ~ Cast Binary (.u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64) (.s64 .f64 integer .s64 .f64 converted type .u64 1st unchanged. Syntax 4.s64 .s64 .u64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. .s64 .u64 .f64 integer integer integer integer integer int ?.6.s64 .s64 .f64 integer .u64 .5.u64 .f64 : .s64 .u64 same as 1st operand . or .f64 same as source . Table 5.Chapter 4.u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 use usual conversions .s64.u64 .f64 use usual conversions . 2nd is . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64) + .u64. 2010 25 .

0 26 January 24. 2010 .PTX ISA Version 2.

or Function or local parameters. platform-specific. and these resources are abstracted in PTX through state spaces and data types. 2010 27 .shared . defined per-grid. the kinds of resources will be common across platforms.param .Chapter 5. addressability. private to each thread. and Variables While the specific resources available in a given target GPU will vary. The characteristics of a state space include its size.sreg . . Global texture memory (deprecated). access rights. shared by all threads.local . Global memory. defined per-thread. Name State Spaces Description Registers. and level of sharing between threads. Special registers. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.const . access speed. fast.reg . Read-only.global . pre-defined. and properties of state spaces are shown in Table 5. State Spaces. Types. 5. Kernel parameters.1. Local memory. Shared. All variables reside in some state space. Table 6. The list of state spaces is shown in Table 4. read-only memory.tex January 24. Addressable memory shared between threads in 1 CTA. State Spaces A state space is a storage area with particular characteristics.

Registers may be typed (signed integer. i. Special Register State Space The special register (. such as grid. 1 Accessible only via the ld.param and st.. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.1.param instructions.sreg . Registers differ from the other state spaces in that they are not fully addressable.2. and vector registers have a width of 16-. When the limit is exceeded. and cvt instructions. 28 January 24.reg .1.shared . The number of registers is limited.global . or 64-bits. clock counters. CTA. 3 Accessible only via the tex instruction.param instruction. register variables will be spilled to memory. and performance monitoring registers. and thread parameters. platform-specific registers.param (used in functions) . Registers may have alignment boundaries required by multi-word loads and stores. Register State Space Registers (. floating point.local state space.param (as input to kernel) . scalar registers have a width of 8-. causing changes in performance. All special registers are predefined. or as elements of vector tuples. st.e. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). the parameter is then located on the stack frame and its address is in the .tex Restricted Yes No3 5. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Address may be taken via mov instruction.const .PTX ISA Version 2. For each architecture.local .reg state space) are fast storage locations.sreg) state space holds predefined. Device function input parameters may have their address taken via mov. 32-. 5. unsigned integer. predicate) or untyped. Register size is restricted. 2 Accessible via ld. 32-. aside from predicate registers which are 1-bit. or 128-bits.0 Table 7. and will vary from platform to platform. 2010 . it is not possible to refer to the address of a register.1. 64-. The most common use of 8-bit registers is with ld. 16-.

This pointer can then be used to access the entire 64KB constant bank. This reiterates the kind of parallelism available in machines that run PTX. // load second word 5. the bank number must be provided in the state space of the load instruction.4.const) state space is a read-only memory. All memory writes prior to the bar. For any thread in a context.1. bank zero is used for all statically-sized constant variables. State Spaces.3. Module-scoped local memory variables are stored at fixed addresses. st.const[2] . the stack is in local memory. Global State Space The global (.const[2].sync instruction. and Variables 5. each pointing to the start address of the specified constant bank. and atom. for example). initialized by the host. there are eleven 64KB banks. where bank ranges from 0 to 10. Global memory is not sequentially consistent. For example.extern . Local State Space The local state space (. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. as it must be allocated on a perthread basis. 2010 29 .global.1.extern . an incomplete array in bank 2 is accessed as follows: .Chapter 5. In implementations that support a stack. If another thread sees the variable b change. [const_buffer+4].sync instruction are guaranteed to be visible to any reads after the barrier instruction. whereas local memory variables declared January 24. the declaration . Threads must be able to do their work without waiting for other threads to do theirs. For the current devices. Banks are specified using the . the store operation updating a may still be in flight. It is typically standard memory with cache. By convention. If no bank number is given.global) state space is memory that is accessible by all threads in a context. Constant State Space The constant (. Sequential consistency is provided by the bar. Multiple incomplete array variables declared in the same bank become aliases. as in lock-free and wait-free style programming.b32 const_buffer[]. 5. ld.local) is private memory for each thread to keep its own data. For example.const[2] . b = b – 1.b32 %r1.global to access global variables. Use ld.local to access local variables. To access data in contant banks 1 through 10. where the size is not known at compile time. The constant memory is organized into fixed size banks.5.local and st.global. It is the mechanism by which different CTAs and different grids can communicate.1. The size is limited. Use ld. The remaining banks may be used to implement “incomplete” constant arrays (in C. bank zero is used. all addresses are in global memory are shared. results in const_buffer pointing to the start of constant bank two.b32 const_buffer[]. Consider the case where one thread executes the following two assignments: a = a + 1. Types.const[bank] modifier. Threads wait at the barrier until all threads in the CTA have arrived.

… 30 January 24.param space variables.reg . per-kernel versus per-thread). Similarly. These parameters are addressable.param.param state space and is accessed using ld. .6.u32 %ptr.u32 %n. ld. %n.param .param instructions. mov.param instructions.b32 len ) { . … Example: . PTX code should make no assumptions about the relative locations or ordering of . The address of a kernel parameter may be moved into a register using the mov instruction.6. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). 5. Note that PTX ISA versions 1. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.1. read-only variables declared in the .u32 %ptr.reg . [N].f64 %d.1. Example: .param .x supports only kernel function parameters in .b8 buffer[64] ) { .param. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. len.0 within a function or kernel body are allocated on the stack. Parameter State Space The parameter (.param) state space is used (1) to pass input arguments from the host to the kernel. in some implementations kernel parameters reside in global memory.u32 %n.entry bar ( . ld. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. device function parameters were previously restricted to the register state space. ld.entry foo ( . The resulting address is in the .0 and requires target architecture sm_20.param state space. Therefore. all local memory variables are stored at fixed addresses and recursive function calls are not supported.f64 %d. The kernel parameter variables are shared across all CTAs within a grid.reg . [%ptr]. 2010 . Note: The location of parameter space is implementation specific.align 8 .param .u32 %n. In implementations that do not support a stack. (2a) to declare formal input and return parameters for device functions called from within kernel execution. [buffer].param space. . typically for passing large structures by value to a function.param. For example. The use of parameter state space for device function parameters is new to PTX ISA version 2.PTX ISA Version 2. No access protection is provided between parameter and global space in this case.b32 N.1. 5. Values passed from the host to the kernel are accessed through these parameter variables using ld.

x. ld. int y. st. State Spaces. Example: // pass object of type struct { double d. 2010 31 . the caller will declare a locally-scoped .s32 %y. January 24.param . … st. [buffer]. … } // code snippet from the caller // struct { double d.local state space and is accessed via ld. . Aside from passing structures by value. [buffer+8]. .param . int y.func foo ( .1.align 8 . which declares a .f64 dbl. and so the address will be in the . } mystruct. and Variables 5. ld. The most common use is for passing objects by value that do not fit within a PTX register. dbl. . (4.reg . a byte array in parameter space is used.f64 %d. is flattened. … See the section on function call syntax for more details.b8 mystruct. It is not possible to use mov to get the address of a return parameter or a locally-scoped .reg . Typically. the address of a function input parameter may be moved into a register using the mov instruction.param.param.local and st. In this case.b8 buffer[12] ) { . . }.2.s32 x.Chapter 5.reg . .param and function return parameters may be written using st.param byte array variable that represents a flattened C structure or union.f64 %d.param.s32 [mystruct+8]. This will be passed by value to a callee.param formal parameter having the same size and alignment as the passed argument. Note that the parameter will be copied to the stack if necessary.param space variable. In PTX. Device Function Parameters PTX ISA version 2.s32 %y.param.local instructions. mystruct).param.f64 [mystruct+0].b32 N. call foo. Types.reg .0 extends the use of parameter space to device function parameters. it is illegal to write to an input parameter or read from a return parameter. .param space is also required whenever a formal parameter has its address taken within the called function.6.align 8 . passed to foo … . Function input parameters may be read via ld. such as C structures larger than 8 bytes.reg .

1. where all threads read from the same address.u32 or .shared to access shared variables.u64. One example is broadcast.7. and . Another is sequential access from sequential threads. 2010 . is equivalent to . Texture State Space (deprecated) The texture (. It is shared by all threads in a context.8. An address in shared memory can be read and written by any thread in a CTA. a legacy PTX definitions such as .tex directive is retained for backward compatibility. Example: .tex . The texture name must be of type . Texture memory is read-only. The .u32 tex_a. tex_d.3 for the description of the . A texture’s base address is assumed to be aligned to a 16-byte boundary.texref tex_a. Use ld.6 for its use in texture instructions. and programs should instead reference texture memory through variables of type .texref.texref type and Section 8.shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex state space are equivalent to module-scoped . The . 32 January 24.tex variables are required to be defined in the global scope.tex) state space is global memory accessed via the texture instruction.PTX ISA Version 2. An error is generated if the maximum number of physical resources is exceeded.global . 5. Shared State Space The shared (. See Section 5.tex .shared and st.u32 .global state space. For example.tex .0 5. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex .7.u32 .u32 . where texture identifiers are allocated sequentially beginning with zero. Shared memory typically has some optimizations to support the sharing. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.u32 tex_a. Multiple names may be bound to the same physical texture identifier. tex_d. Physical texture resources are allocated on a per-module granularity. tex_c. and variables declared in the .1. tex_f.tex directive will bind the named texture memory variable to a hardware texture identifier.tex .texref variables in the .

. so their names are intentionally short. and cvt instructions. but typed variables enhance program readability and allow for better operand type checking. The . For example.f32.u8. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . or converted to other types and sizes.s8. Fundamental Types In PTX. .f16.f64 .f64 types.2. st.b8.u16. . Operand types and sizes are checked against instruction types for compatibility. Signed and unsigned integer types are compatible if they have the same size. Register variables are always of a fundamental type. . and Variables 5. st. 5.b32. Restricted Use of Sub-Word Sizes The . all variables (aside from predicates) could be declared using only bit-size types. The following table lists the fundamental type specifiers for each basic type: Table 8. so that narrow values may be loaded. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.Chapter 5. stored. .f32 and . The same typesize specifiers are used for both variable definitions and for typing instructions. .f64 types. 2010 33 .u8.b64 . .s8.1. . The bitsize type is compatible with any fundamental type having the same size. .s32. .s16. In principle. January 24.pred Most instructions have one or more type specifiers. State Spaces.2.2. All floating-point instructions operate only on . and instructions operate on these types.f16 floating-point type is allowed only in conversions to and from . needed to fully specify instruction behavior. the fundamental types reflect the native data types supported by the target architectures. Types.u64 .b8 instruction types are restricted to ld. A fundamental type specifies both a basic type and a size. stored.f32 and . ld. . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.s64 . For convenience. Types 5. and converted using regular-width registers.2. and . Two fundamental types are compatible if they have the same basic type and are the same size.b16.u32. .

since these properties are defined by . and .samplerref. In the independent mode. Referencing textures. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.texref.. base address. For working with textures and samplers. Texture. passed as a parameter to functions. or surfaces via texture and surface load/store instructions (tex. and Surface Types PTX includes built-in “opaque” types for defining texture. or performing pointer arithmetic will result in undefined results. allowing them to be defined separately and combined at the site of usage in the program.PTX ISA Version 2. These types have named fields similar to structures.e. In the unified mode. opaque_var. sust. but all information about layout.texref handle. i.0 5. texture and sampler information each have their own handle. suld. and de-referenced by texture and surface load. PTX has two modes of operation. and surface descriptor variables. and overall size is hidden to a PTX program. accessing the pointer with ld and st instructions. 34 January 24. sampler. texture and sampler information is accessed through a single . field ordering. sured). suq). The three built-in types are .{u32.surfref. 2010 . store.samplerref variables.texref type that describe sampler properties are ignored. . Creating pointers to opaque variables using mov. In independent mode the fields of the . and query instructions. but the pointer cannot otherwise be treated as an address. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. Retrieving the value of a named member via query instructions (txq.3. the resulting pointer may be stored to and loaded from memory. hence the term “opaque”.u64} reg. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. samplers. Sampler. The following tables list the named members of each type for unified and independent texture modes.

texref values in elements in elements in elements 0. 1 nearest. linear wrap. 2010 35 . State Spaces.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge. Types.Chapter 5. Member width height depth Opaque Type Fields in Unified Texture Mode . linear wrap. clamp_to_edge. clamp_ogl.texref values . clamp_to_border N/A N/A N/A N/A N/A . 1 ignored ignored ignored ignored . clamp_ogl. and Variables Table 9. mirror. mirror.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Member width height depth Opaque Type Fields in Independent Texture Mode .samplerref values N/A N/A N/A N/A nearest. clamp_to_border 0.

. these variables are declared in the .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. 2010 . 36 January 24.global .global .param state space. .global . these variables must be in the . As kernel parameters.surfref my_surface_name.samplerref my_sampler_name. Example: . At module scope.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.PTX ISA Version 2. filter_mode = nearest }.global state space.global . Example: . When declared at module scope.global .texref tex1. the types may be initialized using a list of static expressions assigning values to the named members. .texref my_texture_name.

const .reg . its name. etc. an optional initializer. .v1. 1.v3 }. This is a common case for three-dimensional grids.v4 vector. Vectors Limited-length vector types are supported. vector variables are aligned to a multiple of their overall size (vector length times base-type size). . 0.s32 i. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . for example. 5. State Spaces.v4 . // a length-2 vector of unsigned ints .v4.reg . Vectors must be based on a fundamental type. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.struct float4 { .global . .v2 . Examples: .Chapter 5. PTX supports types for simple aggregate objects such as vectors and arrays.1. 0.global . Variables In PTX. // a length-4 vector of floats .v4 .f32 bias[] = {-1. q. textures.global . . Vectors cannot exceed 128-bits in length.v4 . its type and size. January 24. .0.u32 loc.f32 accel.4.f64 is not allowed. Three-element vectors may be handled by using a .b8 v. and an optional fixed address for the variable.global . Types.u16 uv.v2. A variable declaration names the space in which the variable resides. Predicate variables may only be declared in the register state space. and Variables 5.2. an optional array size. and they may reside in the register space.v2 or . 0}. r.f32 V.struct float4 coord.global . a variable declaration describes both the variable’s type and its state space. . . where the fourth element provides padding.f32 v0. 2010 37 .u8 bg[4] = {0.pred p.shared . 5.4. Variable Declarations All storage for data is specified with variable declarations. // a length-4 vector of bytes By default. In addition to fundamental types. // typedef . Examples: .4. Every variable must reside in one of the state spaces enumerated in the previous section.v4.0}.reg .

Initializers Declared variables may specify an initial value using a syntax similar to C/C++.0. or is left empty.shared . this can be used to initialize a jump table to be used with indirect branches or calls.u8 mailbox[128].s32 n = 10. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration)..0.05}}.05}.3..u8 rgba[3] = {{1. Initializers are allowed for all types except .4.u64.local .pred. 19*19 (361) halfwords are reserved (722 bytes).PTX ISA Version 2.0}}. . 1} }.4. {0.1. being determined by an array initializer.0}. // address of rgba into ptr Currently. 0}. this can be used to statically initialize a pointer to a variable. For the kernel declaration above.u16 kernel[19][19].global .05.{. .s32 offset[][] = { {-1.b32 ptr = rgba. Here are some examples: . . To declare an array. . Similarly. {0. variable initialization is supported only for constant and global state spaces. {1. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. Variable names appearing in initializers represent the address of the variable. {0. 2010 .global ..u32 or . Array Declarations Array declarations are provided to allow the programmer to reserve space.v4 . 0}. A scalar takes a single value.05.4. Examples: .f32 blur_kernel[][] = {{. {0.0 5. The size of the array specifies how many elements should be reserved.0.0}.4. -1}. 38 January 24.. Variables that hold addresses of variables or instructions should be of type . .global .f16 and .{.1}.1.. The size of the dimension is either a constant expression.1. where the variable name is followed by an equals sign and the initial value or values for the variable. 5..1.1.global .0.global . label names appearing in initializers represent the address of the next instruction following the label.

0. 2010 39 . and may be preceded by an alignment specifier. Rather than require explicit declaration of every name. For example.0}. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.b32 %r<100>.b8 bar[8] = {0.0. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.. Elements are bytes.align 4 .0. The default alignment for vector variables is to a multiple of the overall vector size.2. Types.5. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.4. The variable will be aligned to an address which is an integer multiple of byte-count.const . and Variables 5.. Parameterized Variable Names Since PTX supports virtual registers.Chapter 5. nor are initializers permitted. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.4. The default alignment for scalar and array variables is to a multiple of the base-type size. %r1. .align byte-count specifier immediately following the state-space specifier. Alignment is specified using an optional . %r99. …. not for individual elements. These 100 register variables can be declared as follows: . %r1. 5. January 24. alignment specifies the address alignment for the starting address of the entire array. State Spaces.. Examples: // allocate array at 4-byte aligned address.b32 variables. // declare %r0.6. it is quite common for a compiler frontend to generate a large number of register names. . say one hundred. For arrays. Array variables cannot be declared this way. of .0. suppose a program uses a large number.0. named %r0.reg .

0 40 January 24. 2010 .PTX ISA Version 2.

The ld. s. b. Most instructions have an optional predicate guard that controls conditional execution. Instruction Operands 6.3. and c. 2010 41 . st. and a few instructions have additional predicate source operands.Chapter 6. Integer types of a common size are compatible with each other. mov.1. the sizes of the operands must be consistent.reg register state space. Operand Type Information All operands in instructions have a known type from their declarations. so operands for ALU instructions must all be in variables declared in the . . PTX describes a load-store machine. The bit-size type is compatible with every type having the same size. Each operand type must be compatible with the type determined by the instruction template and instruction type. Predicate operands are denoted by the names p. r. 6. 6. and cvt instructions copy data from one location to another. There is no automatic conversion between types. Source Operands The source operands are denoted in the instruction descriptions by the names a. The cvt (convert) instruction takes a variety of operand types and sizes. For most operations. as its job is to convert from nearly any data type to any other data type (and size).2. The result operand is a scalar or vector variable in the register state space. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The mov instruction copies data between registers. Instructions ld and st move data from/to addressable state spaces to/from registers. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. January 24. q.

. ld.reg . Load and store operations move data between registers and locations in addressable state spaces. W.0 6.b32 p. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. The address is an offset in the state space in which the variable is declared. The syntax is similar to that used in many assembly languages. Here are a few examples: .reg .v4.reg . 2010 . All addresses and address computations are byte-based.u16 r0.gloal.const .shared .f32 ld.1.reg .u16 ld. The interesting capabilities begin with addresses.[x].s32 tbl[256]. and vectors. Arrays. . [V]. there is no support for C-style pointer arithmetic.PTX ISA Version 2. Using Addresses.shared.s32 mov. and Vectors Using scalar variables as operands is straightforward. . r0. Address expressions include variable names. 6. arrays. and immediate address expressions which evaluate at compile-time to a constant address.f32 V. .v4 . tbl. q. p. Examples include pointer arithmetic and pointer comparisons. address register plus byte offset. [tbl+12]. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.u16 x.global .const.4.u32 42 January 24.f32 W. address registers.v4 . The mov instruction can be used to move the address of a variable into a pointer.4.s32 q. . .

. Arrays as Operands Arrays of all types can be declared.4.w = = = = V.y. where the offset is a constant expression that is either added or subtracted from a register variable. say {Ra.r V. c. .f32 {a.b V. Vector elements can be extracted from the vector with the suffixes .c.w. ld. V.2. and the identifier becomes an address constant in the space where the array is declared.u32 s. a register variable.g. ld.u32 s. . correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Rd}. January 24.3. [addr+offset].4. mov. Array elements can be accessed using an explicitly calculated byte address. .Chapter 6.b.g V. Here are examples: ld. . a[1]. Rb. or a simple “register with constant offset” expression.u32 {a. Vector loads and stores can be used to implement wide loads and stores. [addr+offset2].f32 a.v2.c.reg . Vectors as Operands Vector operands are supported by a limited subset of instructions.global.global.x V. The registers in the load/store operations can be a vector. st. a[0]. which may improve memory performance.global. // move address of a[1] into s 6.4. Examples are ld.a 6. or a braceenclosed list of similarly typed scalars.u32 s. Elements in a brace-enclosed vector.v4 . mov. for use in an indirect branch or call.b.z and .x. or by indexing into the array using square-bracket notation. The size of the array is a constant in the program. b.d}. Vectors may also be passed as arguments to called functions. as well as the typical color fields .b and . a[N-1]. A brace-enclosed list is used for pattern matching to pull apart vectors.global. If more complicated indexing is desired.4.y V. d.d}. and tex. 2010 43 . Instruction Operands 6.f32 V.v4. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.f32 ld. and in move instructions to get the address of the label or function into a register. V2.reg . Rc. The expression within square brackets is either a constant integer.r. it must be written as an address calculation prior to use. .z V. which include mov.v4.a.

Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. Type Conversion All operands to all arithmetic.5. 6.u16 instruction is given a u16 source operand and s32 as a destination operand.PTX ISA Version 2. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. For example. 44 January 24.0 6.000 for f16). except for operations where changing the size and/or type is part of the definition of the instruction.5. logic. 2010 . and ~131.1. the u16 is zero-extended to s32.s32. Operands of different sizes or types must be converted prior to the operation. and data movement instruction must be of the same type and size. if a cvt.

January 24. Notes 1 If the destination register is wider than the destination format. The type of extension (sign or zero) is based on the destination format. f2u = float-to-unsigned. For example. 2010 45 . s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.Chapter 6. cvt. f2s = float-to-signed. f2f = float-to-float. the result is extended to the destination register width after chopping. chop = keep only low bits that fit. zext = zero-extend. then sign-extend to 32-bits.s16. u2f = unsigned-to-float. Instruction Operands Table 11. s2f = signed-to-float.u32 targeting a 32-bit register will first chop to 16-bits.

0 6. The following tables summarize the rounding modifiers.rm . Modifier .rpi Integer Rounding Modifiers Description round to nearest integer.rni .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rmi . In PTX. Modifier . there are four integer rounding modifiers and four floating-point rounding modifiers.5. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rz .2. Rounding Modifiers Conversion instructions may specify a rounding modifier. choosing even integer if source is equidistant between two integers. 2010 .rn .rzi .PTX ISA Version 2. Table 12.

Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Registers are fastest. first access is high Notes January 24.Chapter 6. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Table 14. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Instruction Operands 6. The register in a store operation is available much more quickly. Operand Costs Operands from different state spaces affect the speed of an operation. Table 11 gives estimates of the costs of using different kinds of memory. while global memory is slowest. Another way to hide latency is to issue the load instructions as early as possible.6. Much of the delay to memory can be hidden in a number of ways. 2010 47 .

0 48 January 24. 2010 .PTX ISA Version 2.

the function name. These include syntax for function definitions. and return values may be placed directly into register variables. At the call. } … call foo. NOTE: The current version of PTX does not implement the underlying. implicitly saving the return address. 7. Abstracting the ABI Rather than expose details of a particular calling convention. parameter passing. The simplest function has no parameters or return values. arguments may be register variables or constants. Execution of the ret instruction within foo transfers control to the instruction following the call. A function definition specifies both the interface and the body of the function.func directive. Function declarations and definitions In PTX. January 24. and an optional list of input parameters. 2010 49 . functions are declared and defined using the . … Here. together these specify the function’s interface. stack layout. A function declaration specifies an optional list of return parameters. In this section. execution of the call instruction transfers control to foo. function calls. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and memory allocated on the stack (“alloca”).func foo { … ret.Chapter 7. or prototype. support for variadic functions (“varargs”). A function must be declared or defined prior to being called. so recursion is not yet supported. we describe the features of PTX needed to achieve this hiding of the ABI. and is represented in PTX as follows: .1. and Application Binary Interface (ABI). stack-based ABI. Scalar and vector base-type input and return parameters may be represented simply as register variables. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters.

0 Example: .b8 [py+11]. %rd. this structure will be flattened into a byte array.reg .align 8 y[12]) { .u32 %res.param. The . [y+10]. … In this example. inc_ptr.align 8 py[12]. c3.b8 [py+ 9].4).b8 .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. [y+11]. %ptr.reg . %rc1.f64 f1.b8 c3.param.c3. } … call (%r1). bumpptr. .param . byte array in .b8 . %rc1. a .f1. ld.reg . c2. st.param.param space call (%out). (%r1.f64 field are aligned.b8 c2. ld.param variable y is used in function definition bar to represent a formal parameter. First.u32 %ptr. char c[4].func (. } { .b32 c1. st. 50 January 24.param.s32 out) bar (. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . 2010 .c1. … st. %inc.c2.param state space is used to pass the structure by value: .param.param.reg . ld.reg space.b8 c4.param space memory. For example. [y+0]. In PTX. }. … ld. %rc2.b64 [py+ 0].b8 c1.func (. // scalar args in . c4.c4.reg . [y+8].u32 %inc ) { add. consider the following C structure. . py).param.f64 f1. Second. ret.PTX ISA Version 2.b8 [py+10]. … … // computation using x. passed by value to a function: struct { double dbl. %rc2. st. note that .param .reg . . Since memory accesses are required to be aligned to a multiple of the access size. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .reg . (%x.param.param.param space variables are used in two ways. a .param. ld.s32 x.b8 [py+ 8]. [y+9]. st.u32 %res) inc_ptr ( .

8. • The . Supporting the .param variables or . In the case of . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param space formal parameters that are byte arrays. For a callee. Note that the choice of . or 16 bytes.param and ld. For .param instructions used for argument passing must be contained in the basic block with the call instruction. and alignment of parameters.param space byte array with matching type. size. • • • Input and return parameters may be .reg variables. For a caller.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. the corresponding argument may be either a . all st. The .reg state space in this way provides legacy support.param or .reg state space can be used to receive and return base-type scalar and vector values.. and alignment. 4. This enables backend optimization and ensures that the . or a constant that can be represented in the type of the formal parameter.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. The .reg space variable of matching type and size. Typically.g.param byte array is used to collect together fields of a structure being passed by value. The following restrictions apply to parameter passing. For a caller.Chapter 7. • • • For a callee.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. a . 2. .param state space use in device functions. Abstracting the ABI The following is a conceptual way to think about the . the corresponding argument may be either a .reg or .param argument must be declared within the local scope of the caller. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.param space formal parameters that are base-type scalar or vector variables.reg space formal parameters. In the case of . January 24. size.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. • The . or constants.param state space is used to receive parameter values and/or pass return values back to the caller.param arguments.reg variables.reg space variable with matching type and size. In the case of .param or . or a constant that can be represented in the type of the formal parameter. the argument must also be a .param variables. Parameters in . A .param memory must be aligned to a multiple of 1. 2010 51 . • • Arguments may be .

formal parameters may be in either .0. 52 January 24. Changes from PTX 1.x supports multiple return values for this purpose. 2010 .0 continues to support multiple return registers for sm_1x targets.PTX ISA Version 2. formal parameters were restricted to . PTX 2. In PTX ISA version 2. and . Objects such as C structures were flattened and passed or returned using multiple registers.reg state space.1.0 7. and a . PTX 2.param space parameters support arrays.param state space.reg or .x In PTX ISA version 1. For sm_2x targets. and there was no support for array parameters.param byte array should be used to return objects that do not fit into a register.x.1. PTX 1.0 restricts functions to a single return value.

// default to MININT mov. (ap). … %va_start returns Loop: @p Done: January 24. or 16 bytes.pred p.reg . In both cases. along with the size and alignment of the next data value to be accessed. 8.reg . N. (3.reg . Abstracting the ABI 7.Chapter 7. } … call (%max). In PTX.func okay ( … ) Built-in functions are provided to initialize. the size may be 1.func baz ( . %r3). . and end access to a list of variable arguments.b32 ctr. .func (.b32 result. %s2). ctr. ret. . %va_end is called to free the variable argument list handle.u32 a. This handle is then passed to the %va_arg and %va_arg64 built-in functions.. %r1. Variadic functions NOTE: The current version of PTX does not support variadic functions. Once all arguments have been processed. (ap. . ) { .reg . 4. To support functions with a variable number of arguments. call %va_end.u32 ptr) %va_start . For %va_arg.h and varargs. or 4 bytes. .reg . or 8 bytes. 0x8000000. mov. The function prototypes are defined as follows: . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .u32 align) .ge p.2. … call (%max).u32 b.u32 sz. 2.b32 val) %va_arg (. max. 4. .reg . call (val).reg . the alignment may be 1. 4.func (.b64 val) %va_arg64 (. result. variadic functions are declared with an ellipsis at the end of the input parameter list.u32 align) .reg .u32 ptr. %va_start.reg .func ( . 0. the size may be 1. . %s1.u32 ptr.s32 val. bra Done. 2. val. (2.u32 N. . … ) . %va_arg. 4). maxN. maxN. 2. call (ap).u32 sz.u32 ap.func (.h headers in C.reg .reg .. for %va_arg64.reg . bra Loop. setp.s32 result.reg .reg . PTX provides a high-level mechanism similar to the one provided by the stdarg. ctr. following zero or more fixed parameters: . %r2.s32 result ) maxN ( .func %va_end (.reg . 2010 53 .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg .reg . iteratively access.u32.

The array is then accessed with ld. 54 January 24.func ( .reg . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.local instructions. a function simply calls the built-in function %alloca.reg .u32 ptr ) %alloca ( .PTX ISA Version 2.3. If a particular alignment is required. defined as follows: . To allocate memory.0 7. Alloca NOTE: The current version of PTX does not support alloca. 2010 . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.local and st.

opcode A. A. and C are the source operands. opcode D. // p = (a < b).Chapter 8. the D operand is the destination operand. January 24.2. A. Instruction Set 8. opcode D.1. C. followed by some examples that attempt to show several possible instantiations of the instruction. B. 8.s32. B. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. 2010 55 . A. setp. b. while A. B. q = !(a < b). opcode D.lt p|q. In addition to the name and the format of the instruction. The setp instruction writes two destination registers. the semantics are described. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. For some instructions the destination operand is optional. We use a ‘|’ symbol to separate multiple destination registers. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. For instructions that create a result value. a. PTX Instructions PTX instructions generally have from zero to four operands.

1. This can be written in PTX as @p setp. 2010 . To implement the above example as a true conditional branch. // p = (i < n) // if i < n. branch over 56 January 24. consider the high-level code if (i < n) j = j + 1.pred as the type specifier.PTX ISA Version 2. add. bra L1. predicate registers can be declared as . predicate registers are virtual and have . the following PTX instruction sequence might be used: @!p L1: setp.s32 j. Instructions without a guard predicate are executed unconditionally. where p is a predicate variable.lt.pred p. i. i. 1.3. n.s32 p. q.0 8. Predicated Execution In PTX. add.reg . j. use a predicate to control the execution of the branch or call instructions. … // compare i to n // if false. So.s32 p. add 1 to j To get a conditional branch or conditional function call.s32 j. j. n. As an example. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.lt. Predicates are most commonly set as the result of a comparison performed by the setp instruction. optionally negated.

and ge (greater-than-or-equal). le (less-than-or-equal). gt.1. ls (lower-or-same). unsigned integer. the result is false. and bitsize types. le.3. The unsigned comparisons are eq. Instruction Set 8. The following table shows the operators for signed integer. ordering comparisons are not defined for bit-size types. ne. ne (not-equal). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. lo (lower). gt (greater-than). Table 16. ge. lt. ne. hi (higher). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and hs (higher-or-same). 2010 57 . lt (less-than).3. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).1. Comparisons 8. Unsigned Integer.1. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. The bit-size comparisons are eq and ne. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.2. Table 15.Chapter 8.3. If either operand is NaN.1.

Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.u32 %r1. for example: selp. geu.0. and mov.0 To aid comparison operations in the presence of NaN values. two operators num (numeric) and nan (isNaN) are provided. then these comparisons have the same result as their ordered counterparts.2. not. If both operands are numeric values (not NaN). or. // convert predicate to 32-bit value 58 January 24. gtu. Table 18.PTX ISA Version 2. and no direct way to load or store predicate register values.3. setp can be used to generate a predicate from an integer. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. and nan returns true if either operand is NaN. leu. unordered versions are included: equ. If either operand is NaN. neu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. Table 17.%p. 2010 . Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. ltu. There is no direct conversion between predicates and integer values. xor. then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN).1. However.

2010 59 . unsigned. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Type Checking Rules Operand Type .reg . they must match exactly. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. It requires separate type-size modifiers for the result and source..bX . i.u16 d.Chapter 8.sX ok ok ok inv . b. For example: . add. Example: . different sizes). and integer operands are silently cast to the instruction type if needed.sX .reg . Signed and unsigned integer types agree provided they have the same size.fX ok inv inv ok Instruction Type . Instruction Set 8.e. the add instruction requires type and size information to properly perform the addition operation (signed. and this information must be specified as a suffix to the opcode. float. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.reg .bX .fX ok ok ok ok January 24. and these are placed in the same order as the operands.f32 d.uX .uX ok ok ok inv . a. most notably the data conversion instruction cvt. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. Table 19. Floating-point types agree only if they have the same size. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.u16 a.4. • The following table summarizes these type checking rules. b.u16 d. For example. a. .f32. a. cvt. For example.u16 d.

the cvt instruction does not support . The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. unless the operand is of bit-size type. floating-point instruction types still require that the operand type-size matches exactly. The following table summarizes the relaxed type-checking rules for source operands. so those rows are invalid for cvt. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. or converted to other types and sizes. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type.bX instruction types. for example. When a source operand has a size that exceeds the instruction-type size. 1.PTX ISA Version 2.0 8. When used with a floating-point instruction type. Source register size must be of equal or greater size than the instruction-type size. and converted using regular-width registers. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. “-“ = allowed. stored. so that narrow values may be loaded. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.1. Floating-point source registers can only be used with bit-size or floating-point instruction types. 60 January 24. Bit-size source registers may be used with any appropriately-sized instruction type. 2. st. Table 20. When used with a narrower bit-size type. inv = invalid. Operand Size Exceeding Instruction-Type Size For convenience. 4. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. The data is truncated to the instruction-type size and interpreted according to the instruction type. parse error. Note that some combinations may still be invalid for a particular instruction. 2010 . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. ld. For example. the data will be truncated.4. the size must match exactly. stored. no conversion needed. Notes 3.

The following table summarizes the relaxed type-checking rules for destination operands. the size must match exactly. The data is sign-extended to the destination register width for signed integer instruction types. January 24. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend.Chapter 8. the data will be zero-extended. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. the data is sign-extended. If the corresponding instruction type is signed integer. otherwise. inv = Invalid. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Notes 3. 1. 2. When used with a narrower bit-size instruction type. The data is signextended to the destination register width for signed integer instruction types.or sign-extended to the size of the destination register. Bit-size destination registers may be used with any appropriately-sized instruction type. Destination register size must be of equal or greater size than the instruction-type size. and is zero-extended to the destination register width otherwise. When used with a floatingpoint instruction type. the data is zeroextended. 4. the destination data is zero. “-“ = Allowed but no conversion needed. Floating-point destination registers can only be used with bit-size or floating-point instruction types. zext = zero-extend. parse error. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Table 21. 2010 61 .

At the PTX language level. the threads are called uniform. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent.0 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. until C is not expressive enough. 62 January 24. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 8.5. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. 8. For divergent control flow. at least in appearance. this is not desirable.6. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. If all of the threads act in unison and follow a single control flow path. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. and 16-bit computations are “promoted” to 32-bit computations. the semantics of 16-bit instructions in PTX is machine-specific. using the . This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. a compiler or code author targeting PTX can ignore the issue of divergent threads. by a right-shift instruction. Divergence of Threads in Control Constructs Threads in a CTA execute together. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.PTX ISA Version 2. so it is important to have divergent threads re-converge as soon as possible. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path.6. the optimizing code generator automatically determines points of re-convergence. Both situations occur often in programs. The semantics are described using C. 16-bit registers in PTX are mapped to 32-bit physical registers. the threads are called divergent.uni suffix. If threads execute down different control flow paths. for example. or conditional return. for many performance-critical applications. and for many applications the difference in execution is preferable to limiting performance. until they come to a conditional control construct such as a conditional branch. When executing on a 32-bit data path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 2010 . These extra precision bits can become visible at the application level. However. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform.1. conditional function call. A compiler or programmer may chose to enforce portable. Therefore.

1. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. addc sub. 2010 63 .cc.Chapter 8. The Integer arithmetic instructions are: add sub add. 8. Instructions All PTX instructions may be predicated.7. Instruction Set 8.cc. In the following descriptions.7. the optional guard predicate is omitted from the syntax.

u64.s32.s32 . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add Syntax Integer Arithmetic Instructions: add Add two values. Saturation modifier: .u32... a. PTX ISA Notes Target ISA Notes Examples Table 23. . a. 2010 . @p add. b.c. .s64 }.u64. Supported on all target architectures.type = { .s32 d. Introduced in PTX ISA version 1. Supported on all target architectures.sat}. // . .s32 type.s32 c.1. a.PTX ISA Version 2.u16.b.u16.sat. .MAXINT (no overflow) for the size of the operation. Applies only to . sub. b. . d. .type sub{. d.sat}.s16. b.MAXINT (no overflow) for the size of the operation.0.s32 c.s32 type.y.u32. . add. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. Applies only to .s32 d. PTX ISA Notes Target ISA Notes Examples 64 January 24.z. . d = a – b. d = a + b. .sat applies only to .type add{.sat limits result to MININT. Saturation modifier: . // . a. Introduced in PTX ISA version 1.s32.0 Table 22.u32 x.sat limits result to MININT. . sub.s16. add.a.type = { .0.s32 . b.sat applies only to .s64 }.

z4. No saturation. These instructions support extended-precision integer addition and subtraction.cc.CF No integer rounding modifiers. . Behavior is the same for unsigned and signed integers.z2. x3.cc.Chapter 8.u32.z3.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.2.cc.b32 addc. .u32.type d. No saturation. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1.cc.2.z2. or testing the condition code. x3. b.z3. add.b32 addc.type = {.CF. a. x4.s32 }. if .cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.y1. addc. carry-out written to CC.z1. d = a + b + CC.y1. x2.cc.cc Add two values with carry-out.y3. @p @p @p @p add.cc specified.y4. a. add.z4.cc Syntax Integer Arithmetic Instructions: add. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc. 2010 65 . Table 24.z1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.s32 }. @p @p @p @p add. clearing.cc. Behavior is the same for unsigned and signed integers. d = a + b.y2. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.y4. x2.b32 addc.cc. No other instructions access the condition code. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.b32 x1.y3. . sub.cc}.b32 addc.b32 x1.CF) holding carry-in/carry-out or borrowin/borrow-out. Supported on all target architectures. Introduced in PTX ISA version 1. .b32 addc. Instruction Set Instructions add. addc{. b. carry-out written to CC. x4.y2. Supported on all target architectures. and there is no support for setting.type d.cc.type = { .b32 addc.CF No integer rounding modifiers.

z3. b.b32 x1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Introduced in PTX ISA version 1. x3.type = {. .type d.cc. Behavior is the same for unsigned and signed integers.b32 x1. d = a .cc.cc Syntax Integer Arithmetic Instructions: sub.z1.cc specified. x3.b32 subc.cc.b32 subc.y1.cc.cc. borrow-out written to CC.s32 }.y4. x2.z4.cc.cc. if .y2.cc. borrow-out written to CC. sub.(b + CC. No saturation. a. a.cc.CF No integer rounding modifiers. No saturation.3. x4.y4.u32. x2. Supported on all target architectures.z1. withborrow-in and optional borrow-out.y1. . Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.b32 subc.s32 }.z2.b32 subc. .cc Subract one value from another.y3.z2.3.CF No integer rounding modifiers. Behavior is the same for unsigned and signed integers. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.b32 subc. 2010 .type = { . b.y2.y3. @p @p @p @p sub.CF).0 Table 26.z3. @p @p @p @p sub. sub. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.type d. Introduced in PTX ISA version 1.z4.PTX ISA Version 2. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. . Supported on all target architectures.cc}.u32. with borrow-out. d = a – b.b32 subc. subc{. x4.

Chapter 8.u32.n>. // for . .fys..fxs.wide. // 16*16 bits yields 32 bits // 16*16 bits. d = t.s64 }.hi. . Description Semantics Compute the product of two values.u64.type = { .type d. Instruction Set Table 28. a.wide // for . mul. d = t<n-1. If .u16.hi or . If . The .and 32-bit integer types. mul. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. then d is the same size as a and b.lo. . mul{.lo is specified.. t = a * b. creates 64 bit result January 24. .s32 z.fys. b.wide}.0>. Supported on all target architectures. save only the low 16 bits // 32*32 bits. mul. n = bitwidth of type.s16.s32.wide..y.lo. d = t<2n-1. then d is twice as wide as a and b to receive the full result of the multiplication..s16 fa. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo variant Notes The type of the operation represents the types of the a and b operands. 2010 67 .s16 fa. .0.x.hi variant // for .wide is specified.fxs.wide suffix is supported only for 16. and either the upper or lower half of the result is written to the destination register. .

Applies only to . .s32 d.lo is specified. // for . c.wide}..lo.wide // for .hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.and 32-bit integer types.u16. and then writes the resulting value into a destination register.0> + c. If .PTX ISA Version 2.0. Supported on all target architectures.a.b. bitwidth of type.MAXINT (no overflow) for the size of the operation. t<n-1.type mad.r.lo.. then d and c are twice as wide as a and b to receive the result of the multiplication.hi or .sat limits result to MININT.u64. If .type = { .wide suffix is supported only for 16.lo variant Notes The type of the operation represents the types of the a and b operands. c.wide is specified.s32 r. 2010 . @p mad. b. and either the upper or lower half of the result is written to the destination register. ..n> + c.0 Table 29.s32 type in ..hi variant // for . d. t<2n-1. 68 January 24. . mad. Saturation modifier: . .p. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.q. The . t + c. mad{.lo.s32.s16. Description Semantics Multiplies two values and adds a third.u32.c. b. .sat.s32 d.hi.. then d and c are the same size as a and b. t n d d d = = = = = a * b. a. a.hi mode. .s64 }.

b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures. d = t<31. All operands are of the same type and size. January 24.Chapter 8.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. a.b..hi.hi variant // for ..0>. // low 32-bits of 24x24-bit signed multiply. Instruction Set Table 30.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24.16>.s32 }. mul24.type d.. .0.a.lo}. and return either the high or low 32-bits of the 48-bit result. 2010 69 .lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.hi may be less efficient on machines without hardware support for 24-bit multiply. mul24. d = t<47. // for .type = { . .s32 d.lo.u32. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24{. i.e. t = a * b. 48bits. mul24.

s32 }.a. mad24. c.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. a. 32-bit value to either the high or low 32-bits of the 48-bit result. mad24. c.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.hi.sat limits result of 32-bit signed addition to MININT. // for .hi. .s32 type in .hi may be less efficient on machines without hardware support for 24-bit multiply. 2010 .sat.MAXINT (no overflow). Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi variant // for .c. // low 32-bits of 24x24-bit signed multiply. Description Compute the product of two 24-bit integer values held in 32-bit source registers.e.lo}. d = t<31.lo. Return either the high or low 32-bits of the 48-bit result.16> + c..hi mode.0> + c.s32 d. 48bits.0 Table 31. t = a * b. .b.type = { . a.. All operands are of the same type and size. b. b. mad24.s32 d. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. mad24.PTX ISA Version 2.. Applies only to . i. mad24{. Saturation modifier: .0.u32. and add a third. 70 January 24. d = t<47..type mad24. d.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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d = 0.type = { . . a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type d. inclusively. mask = 0x8000000000000000. cnt. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b32. inclusively.0. popc. a.type == . a.b32 clz. 2010 . while (a != 0) { if (a&0x1) d++.u32 Semantics 74 January 24. clz.b64 type. popc requires sm_20 or later.u32 PTX ISA Notes Target ISA Notes Examples Table 40.b64 }. the number of leading zeros is between 0 and 64. For . For . a = a << 1.b32 type. clz. d = 0. // cnt is . clz requires sm_20 or later.b64 d. } else { max = 64. . Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. . a = a >> 1.0. the number of leading zeros is between 0 and 32. . X. cnt.b64 }.type d. a.0 Table 39. } Introduced in PTX ISA version 2. // cnt is . popc. X.type = { .b64 d. if (.b32) { max = 32. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. popc Syntax Integer Arithmetic Instructions: popc Population count.b32 popc.b32. mask = 0x80000000. } while (d < max && (a&mask == 0) ) { d++.PTX ISA Version 2.

. a. 2010 75 .shiftamt is specified.u32.type = { . .shiftamt && d != -1) { d = msb .u64. Operand a has the instruction type.Chapter 8. For signed integers.type d. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind. } } if (. X.s32. d. for (i=msb.type==. a. i--) { if (a & (1<<i)) { d = i. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.s64 }.type bfind. If .u32 || . . bfind.u32 January 24. bfind requires sm_20 or later. break.s32) ? 31 : 63. a. i>=0.type==. and operand d has type . Instruction Set Table 41.0. Semantics msb = (. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Description Find the bit position of the most significant non-sign bit in a and place the result in d. . d = -1.shiftamt. // cnt is . For unsigned integers.s64 cnt. bfind returns the bit position of the most significant “1”.d.shiftamt. bfind returns 0xFFFFFFFF if no non-sign bit is found.u32. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. bfind.u32 d.

. . i<=msb. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.PTX ISA Version 2.b64 }. Description Semantics Perform bitwise reversal of input. brev requires sm_20 or later. msb = (.0. brev. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 42.b32.type==.type = { . 2010 . 76 January 24. a.type d.b32 d. a. i++) { d[i] = a[msb-i]. for (i=0.b32) ? 31 : 63. brev.

i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. Semantics msb = (.u32 || .s32. pos = b.len. if (.0.type d. and operands b and c are type . January 24.a. 2010 77 .b32 d. otherwise If the bit field length is zero.s32.type = { . Instruction Set Table 43. The destination d is padded with the sign bit of the extracted field.type==. Operands a and d have the same type as the instruction type.u32.u32. len = c. the destination d is filled with the replicated sign bit of the extracted field.u64: . The sign bit of the extracted field is defined as: . bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. d = 0. bfe. b. .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.s64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .u64 || len==0) sbit = 0. bfe. Source b gives the bit field starting bit position. .Chapter 8. . .msb)].s32) ? 31 : 63.u64.u32 || . and source c gives the bit field length in bits.start.type==. . else sbit = a[min(pos+len-1. for (i=0. i<=msb.type==. Description Extract bit field from a and place the zero or sign-extended result in d.type==. a. bfe requires sm_20 or later. the result is zero.u32. If the start position is beyond the msb of the input. c.

} PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.a. 2010 .0 Table 44. .start. 78 January 24. and operands c and d are type . a.b32 d. bfi. i<len && pos+i<=msb. and f have the same type as the instruction type. b. and source d gives the bit field length in bits.b64 }. len = d. d. . If the bit field length is zero. bfi.type==. the result is b. Operands a. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. Description Align and insert a bit field from a into b. for (i=0. the result is b. i++) { f[pos+i] = a[i]. bfi requires sm_20 or later. f = b.b32. pos = c.type f. Source c gives the starting bit position for the insertion.len.b32) ? 31 : 63.u32. and place the result in f.type = { .0. If the start position is beyond the msb of the input. b. c.b. Semantics msb = (.PTX ISA Version 2.

rc8. The msb defines if the byte value should be copied.b1 source select c[7:4] d. b4}. b6. b1.b3 source select c[15:12] d.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. msb=0 means copy the literal value.b32{.b2 source select c[11:8] d. b2. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. msb=1 means replicate the sign. the permute control consists of four 4-bit selection values. The bytes in the two source registers are numbered from 0 to 7: {b. Instruction Set Table 45. c. Thus. . a} = {{b7. Description Pick four arbitrary bytes from two 32-bit registers. and reassemble them into a 32-bit destination register. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. . For each byte in the target register. b5.f4e.mode = { . a. 2010 79 . Note that the sign extension is only performed as part of generic form. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. b0}}.mode} d. default mode index d. In the generic form (no mode specified).Chapter 8.b4e. prmt. a 4-bit selection value is defined.rc16 }.ecl. the four 4-bit values fully specify an arbitrary byte permute.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). b. {b3. . .ecr. as a 16b permute code.

ctl[1] = (c >> 4) & 0xf. tmp[23:16] = ReadByte( mode. r2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r1. prmt. ctl[1]. ctl[3] = (c >> 12) & 0xf. tmp64 ). ctl[2]. r3. tmp64 ). r4. r3.0 Semantics tmp64 = (b<<32) | a. } tmp[07:00] = ReadByte( mode.0. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.b32.f4e r1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 prmt. tmp64 ). prmt requires sm_20 or later. tmp64 ). 80 January 24. r2. r4. ctl[2] = (c >> 8) & 0xf. 2010 . tmp[15:08] = ReadByte( mode. ctl[0]. tmp[31:24] = ReadByte( mode.PTX ISA Version 2. ctl[3].

The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.Chapter 8.f32 and .f64 register operands and constant immediate values. Instruction Set 8. 2010 81 . Floating-Point Instructions Floating-point instructions operate on .2.7.

Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. default is .rcp.f64 and fma. 1. {mad.min. sub.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.rnd.min.sat Notes If no rounding modifier is specified.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.rp . {add.rnd.target sm_20 mad.f32 {div.approx. Single-precision add.rn and instructions may be folded into a multiply-add.f32 are the same. 2010 .rcp.0].rm . so PTX programs should not rely on the specific single-precision NaNs being generated.f32 {div.f32 {abs.neg.f32 . . mul. No rounding modifier.f64 are the same.f64 {sin. Note that future implementations may support NaN payloads for single-precision instructions.approx.sub.sqrt}.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. Double-precision instructions support subnormal inputs and results.cos.f64 {abs.ex2}.approx.f64 mad. Table 46.f32 {div.target sm_1x No rounding modifier.sqrt}. with NaNs being flushed to positive zero.0.fma}.f32 rsqrt.mul}.f64 rsqrt. but single-precision instructions return an unspecified NaN.mul}.max}. Instruction Summary of Floating-Point Instructions .rn and instructions may be folded into a multiply-add.full.rnd.f32 {mad. The optional .PTX ISA Version 2.rcp.ftz . default is .rz .rnd.neg.rnd.max}.lg2.0 The following table summarizes floating-point instructions in PTX. 82 January 24.sqrt}.approx.f64 div. and mad support saturation of results to the range [0.fma}.rn . .target sm_20 . NaN payloads are supported for double-precision instructions.rnd.f32 {add.32 and fma. If no rounding modifier is specified.sub.

infinite. a. testp.op. f0.f32 copysign.f32 testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.infinite. p. testp. z.number testp. testp. Instruction Set Table 47.notanumber. . . and return the result as d.f64 }. X.Chapter 8.subnormal }.f64 isnan.type = { . . A.normal.type d.notanumber testp. . copysign.op p. 2010 83 . . true if the input is a subnormal number (not NaN.notanumber. .f32. positive and negative zero are considered normal numbers. b.finite.infinite testp. a.0.finite testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. not infinity). // result is . copysign.0. . Introduced in PTX ISA version 2.type . testp requires sm_20 or later.type = { .pred = { .f64 x. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.normal testp.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.f64 }. copysign requires sm_20 or later. not infinity) As a special case. B.number.f32. . . Table 48. January 24. testp Syntax Floating-Point Instructions: testp Test floating-point property. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. C. y.

2010 .ftz. add Syntax Floating-Point Instructions: add Add two values. add{.rz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .f2.f32.rn.f64.rz mantissa LSB rounds towards zero .PTX ISA Version 2.f32 supported on all target architectures.rm. d = a + b. requires sm_20 Examples @p add. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. 1.f32 f1.f32 add{.ftz.sat. Description Semantics Notes Performs addition and writes the resulting value into a destination register. In particular.rm.f32 flushes subnormal inputs and results to sign-preserving zero. a.rz.f32 clamps the result to [0.rnd}{. Saturation modifier: .rz available for all targets .rn): . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f3.f64 requires sm_13 or later.rm mantissa LSB rounds towards negative infinity . .rn mantissa LSB rounds to nearest even .f64 d. 84 January 24. . add. .rp }. sm_1x: add. NaN results are flushed to +0. a. Rounding modifiers have the following target requirements: . b. .0 Table 49. Rounding modifiers (default is .ftz}{.rnd = { .0. d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . requires sm_13 for add.f64 supports subnormal numbers. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.0].rn.rp for add. b.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.0.0f. add. add.sat}. add. add.rnd}.

rnd = { .0f.rn. subnormal numbers are supported. sub. b.rn.a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 flushes subnormal inputs and results to sign-preserving zero.rm. d = a . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rn mantissa LSB rounds to nearest even .rz.Chapter 8.rn): . Rounding modifiers (default is .sat}. .rp }.f64 requires sm_13 or later. .f64 supports subnormal numbers. January 24.f32 supported on all target architectures.0.0. sub. In particular.rm mantissa LSB rounds towards negative infinity .ftz. sub.rnd}{.rz available for all targets .sat. sm_1x: sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. sub. Saturation modifier: sub. Instruction Set Table 50.f32 sub{.ftz. a.f3. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rp for sub.f32. . sub Syntax Floating-Point Instructions: sub Subtract one value from another.f32 c.f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples sub.b.f32 clamps the result to [0. a.f2.ftz}{. 2010 85 .rn.rnd}.rz mantissa LSB rounds towards zero . .rm. sub{. NaN results are flushed to +0. b. Rounding modifiers have the following target requirements: . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64. .0]. .f32 f1.b. d. sub. requires sm_13 for sub.f64 d.

all operands must be the same size.sat}. Rounding modifiers have the following target requirements: .0]. sm_1x: mul.f64. b. Saturation modifier: mul. .f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples mul. 2010 .f32 circumf.pi // a single-precision multiply 86 January 24.rz mantissa LSB rounds towards zero . a.rn): . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.0 Table 51. mul.ftz. .rm.rp for mul.rm mantissa LSB rounds towards negative infinity .rnd}{. d.rn.rp }. mul.f32 mul{.f64 d. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.ftz. d = a * b.radius.rnd = { . mul.f32 flushes subnormal inputs and results to sign-preserving zero.rn. b.rn mantissa LSB rounds to nearest even . Description Semantics Notes Compute the product of two values. .0.f32.f64 requires sm_13 or later. For floating-point multiplication.0f.rm. 1.0.rnd}.rz available for all targets .f32 clamps the result to [0.f32 supported on all target architectures. a. . . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_13 for mul.sat. In particular. mul{.PTX ISA Version 2.ftz}{.f64 supports subnormal numbers. subnormal numbers are supported. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. NaN results are flushed to +0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz. Rounding modifiers (default is . . mul. mul Syntax Floating-Point Instructions: mul Multiply two values.

f64 requires sm_13 or later. fma. The resulting value is then rounded to double precision using the rounding mode specified by .f32 fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn mantissa LSB rounds to nearest even .ftz.rz.f64 introduced in PTX ISA version 1.b.rnd.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is unimplemented in sm_1x.y.rp }. Saturation: fma. b. Instruction Set Table 52. fma. a.4. c.f64 is the same as mad. 2010 87 . NaN results are flushed to +0. The resulting value is then rounded to single precision using the rounding mode specified by . fma. again in infinite precision.f64 computes the product of a and b to infinite precision and then adds c to this product. @p fma.f64 d. b.ftz.rm mantissa LSB rounds towards negative infinity .rnd{.f64 supports subnormal numbers.f32 computes the product of a and b to infinite precision and then adds c to this product.c. .Chapter 8. PTX ISA Notes Target ISA Notes Examples January 24.f32 fma.f32 introduced in PTX ISA version 2.rnd. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma.0.rnd = { . Rounding modifiers (no default): . d.f64 w.rn.sat}. again in infinite precision.a.z. fma.0f.f32 requires sm_20 or later. c. .x.sat. .rnd.ftz}{. d = a*b + c.rn. fma. fma.rz mantissa LSB rounds towards zero . 1. .rn.0]. fma. d.f32 clamps the result to [0. fma.rm.0. sm_1x: fma. subnormal numbers are supported. fma. a. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f64.

mad. b.ftz}{. the treatment of subnormal inputs and output follows IEEE 754 standard. 2010 .rn. fma.f32).rnd. . The resulting value is then rounded to double precision using the rounding mode specified by .target sm_1x d. and then the mantissa is truncated to 23 bits. Note that this is different from computing the product with mul. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. mad{. again in infinite precision. d = a*b + c. subnormal numbers are supported. mad. b.PTX ISA Version 2.e. and then writes the resulting value into a destination register. mad.rz.f64 d. // .0. c.f32 flushes subnormal inputs and results to sign-preserving zero.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. mad.f32 computes the product of a and b at double precision. Rounding modifiers (no default): . The exception for mad.target sm_1x: mad.rm mantissa LSB rounds towards negative infinity .rnd.f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to single precision using the rounding mode specified by .f32.rnd = { . a.f32 mad. Description Semantics Notes Multiplies two values and adds a third. again in infinite precision.sat}. b. Unlike mad.target sm_20: mad.f64.0f. where the mantissa can be rounded and the exponent will be clamped.ftz}{. For .rnd{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . 88 January 24.rm..{f32.target sm_13 and later . 1. c. but the exponent is preserved.rn mantissa LSB rounds to nearest even .f64 computes the product of a and b to infinite precision and then adds c to this product.f64 is the same as fma.f32 is when c = +/-0.target sm_20 d.rn.0 devices. mad. a.rnd.rz mantissa LSB rounds towards zero . // .f32 is implemented as a fused multiply-add (i. In this case.ftz.f32 is identical to the result computed using separate mul and add instructions.{f32.f64}.0. When JIT-compiled for SM 2. For .f32 computes the product of a and b to infinite precision and then adds c to this product.rp }. mad. // .0 Table 53. again in infinite precision.f64 computes the product of a and b to infinite precision and then adds c to this product. mad. . NaN results are flushed to +0.f64 supports subnormal numbers.sat.ftz.f32 clamps the result to [0. a.sat}. The resulting value is then rounded to double precision using the rounding mode specified by . mad. c.0].f64} is the same as fma.f32 mad. mad. sm_1x: mad. Saturation modifier: mad.rnd.

mad.rz.4 and later.f64. In PTX ISA versions 1. Target ISA Notes mad.f64.f32 d..rz.rm. 2010 89 .c. requires sm_20 Examples @p mad.Chapter 8...f32 for sm_20 targets. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f64 requires sm_13 or later.f32.0.rp for mad.rn..rn. In PTX ISA versions 2.rp for mad.. Rounding modifiers have the following target requirements: .f64 instructions having no rounding modifier will map to mad.a.0 and later.. a rounding modifier is required for mad.f64. Legacy mad.f32 supported on all target architectures. January 24.b. requires sm_13 .rn. a rounding modifier is required for mad.rm.

div.full. b.approx. div. z.approx. a.0 Table 54. zd. .rnd is required. a.f64 requires sm_20 or later. computed as d = a * (1/b). a.rn mantissa LSB rounds to nearest even .f32. y. Examples 90 January 24.rp }. . sm_1x: div.rm.0 through 1.f32 div. d. Fast.rp}.f32 flushes subnormal inputs and results to sign-preserving zero. div. Subnormal inputs and results are flushed to sign-preserving zero. 2010 .approx. For PTX ISA version 1.ftz}.f64 introduced in PTX ISA version 1. b. The maximum ulp error is 2 across the full range of inputs.f32 flushes subnormal inputs and results to sign-preserving zero. Description Semantics Notes Divides a by b.ftz.rz.f32 and div.approx{.f32 defaults to div.{rz.full.f64 requires sm_13 or later.rnd = { . Explicit modifiers .rn. div. Fast. and div.rnd. . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 supported on all target architectures. but is not fully IEEE 754 compliant and does not support rounding modifiers.f64.full.f64 defaults to div. For PTX ISA versions 1.3.ftz}.f64 diam. d.ftz.ftz. xd.rn. div. div.rnd. stores result in d.full.circum. PTX ISA Notes div.f32 div.rz mantissa LSB rounds towards zero .f64 d. b. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 requires sm_20 or later. For b in [2-126. 2126]. and rounding introduced in PTX ISA version 1. or .full{. div Syntax Floating-Point Instructions: div Divide one value by another. b. one of .4.4 and later. Target ISA Notes div.approx.f64 supports subnormal numbers. yd. .ftz. d. a.PTX ISA Version 2.f32 div.ftz. subnormal numbers are supported.approx.full.rnd{.approx.f32 div.3. div. . // // // // fast.rn.0. div.rm mantissa LSB rounds towards negative infinity . div. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.f32 implements a fast approximation to divide. the maximum ulp error is 2. x.ftz}. approximate single-precision divides: div.14159.rm.f32 implements a relatively fast.f32 and div. full-range approximation that scales operands to achieve better accuracy. d = a / b. approximate division by zero creates a value of infinity (with same sign as a).f32 div.

ftz.ftz.ftz.f0. a. a. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. neg. a. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs. d = |a|. a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. d.f32 supported on all target architectures. abs. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Take the absolute value of a and store the result in d.f32 x. d = -a.ftz}. NaN inputs yield an unspecified NaN. Table 56. Subnormal numbers: sm_20: By default.f64 d. NaN inputs yield an unspecified NaN.0.f32 neg. Subnormal numbers: sm_20: By default. sm_1x: abs. neg. d.0.f64 requires sm_13 or later.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures.ftz}. neg.f0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. neg{.f32 flushes subnormal inputs and results to sign-preserving zero. January 24. Negate the sign of a and store the result in d. 2010 91 .f32 x. abs. abs. subnormal numbers are supported.ftz. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. subnormal numbers are supported. abs{.f64 requires sm_13 or later.f32 abs.f64 d.f64 supports subnormal numbers. neg. sm_1x: neg.f64 supports subnormal numbers. abs. Instruction Set Table 55.f32 flushes subnormal inputs and results to sign-preserving zero.

a.f64 supports subnormal numbers.c.z.ftz.f32 min. d. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.ftz.0.PTX ISA Version 2.x. 92 January 24.ftz}. max{.f32 flushes subnormal inputs and results to sign-preserving zero. Table 58. subnormal numbers are supported.f32 supported on all target architectures. min.b.b.f64 f0.f1.f64 supports subnormal numbers. b. max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.0 Table 57. Store the minimum of a and b in d. (a < b) ? a : b.ftz. a. a. (a > b) ? a : b. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. a.f32 max. d d d d = = = = NaN. d.f32 max. b.f2. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. min.f64 d. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. max.c. b. max. max.f64 requires sm_13 or later.f64 z. b.f64 requires sm_13 or later. 2010 . max.f32 flushes subnormal inputs and results to sign-preserving zero. b. a. a. subnormal numbers are supported. sm_1x: min. min.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. d d d d = = = = NaN. min.f32 supported on all target architectures. a.f32 min. min{. sm_1x: max.f64 d. b. Store the maximum of a and b in d. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.ftz}. @p min.

2010 93 .ftz.f32 rcp.x.f32 defaults to rcp.rnd{. PTX ISA Notes rcp. rcp.rp}.f32 implements a fast approximation to reciprocal. // fast.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero.f64 ri.Chapter 8.rnd. d. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. Input -Inf -subnormal -0. xi. a.3.approx. Examples January 24.rm.approx or .f64 supports subnormal numbers.rnd = { .0 +0.f64 d.0 -Inf -Inf +Inf +Inf +0. rcp.0 +subnormal +Inf NaN Result -0.approx. sm_1x: rcp.approx{.ftz.f32 rcp. . Instruction Set Table 59. a. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rn. rcp.ftz}.0 over the range 1. store result in d. and rcp.f64 requires sm_20 or later.rn. xi.f64 and explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .{rz.rm. The maximum absolute error is 2-23. General rounding modifiers were added in PTX ISA version 2.0.r.f64 requires sm_13 or later. subnormal numbers are supported.rnd is required.0-2.rn.ftz}.f64.rp }.rn. .f32 supported on all target architectures.f64 defaults to rcp.rz mantissa LSB rounds towards zero .0. rcp.rz.rnd.4.0. rcp. d.4 and later.rn mantissa LSB rounds to nearest even .f32 rcp.approx.ftz were introduced in PTX ISA version 1.f32.approx. For PTX ISA versions 1. rcp.f32 rcp.ftz. For PTX ISA version 1.rn. .f32 requires sm_20 or later.f32 and rcp. rcp.x. one of . d = 1 / a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx and . a. rcp.rn.ftz. rcp. Target ISA Notes rcp. Description Semantics Notes Compute 1/a.f64 introduced in PTX ISA version 1.rm mantissa LSB rounds towards negative infinity .

rnd is required.rz mantissa LSB rounds towards zero . Description Semantics Notes Compute sqrt(a).x.rm.rp}.f64 defaults to sqrt.ftz.ftz were introduced in PTX ISA version 1.f32. a. .3.f64 requires sm_13 or later.f32 is TBD.0.approx. sqrt.x.rn. one of .4.f64 d.0 +subnormal +Inf NaN Result NaN NaN -0. // IEEE 754 compliant rounding d.rn.rnd.0 +0.PTX ISA Version 2. For PTX ISA versions 1. sqrt.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.rz. subnormal numbers are supported.f32 sqrt.f64. sqrt.approx. . For PTX ISA version 1. The maximum absolute error for sqrt. sqrt.ftz.0 Table 60.0 -0.ftz}.f32 sqrt. r. and sqrt. a.x. d = sqrt(a). 2010 .rn. PTX ISA Notes sqrt.approx.rm.f32 defaults to sqrt.approx. General rounding modifiers were added in PTX ISA version 2.ftz. sm_1x: sqrt. sqrt. sqrt.{rz.rn.rn mantissa LSB rounds to nearest even .approx or . sqrt.f64 supports subnormal numbers.approx.0 +0.f32 sqrt.f64 introduced in PTX ISA version 1.rm mantissa LSB rounds towards negative infinity . approximate square root d. a.rn. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.ftz}.rnd = { .f32 sqrt.approx and .f32 requires sm_20 or later. store in d.0 through 1.f64 requires sm_20 or later.rn.0. // fast.f32 supported on all target architectures.4 and later.f32 implements a fast approximation to square root. sqrt. Input -Inf -normal -subnormal -0. . r. Examples 94 January 24. Target ISA Notes sqrt.f64 r.approx{.rnd{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sqrt.0 +0.f32 and sqrt.rp }. sqrt. // IEEE 754 compliant rounding .rnd.f64 and explicit modifiers .

The maximum absolute error for rsqrt. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.approx and .4 and later.f32 and rsqrt.0 NaN The maximum absolute error for rsqrt. Target ISA Notes Examples rsqrt.Chapter 8. rsqrt. 2010 95 . sm_1x: rsqrt. subnormal numbers are supported.f64 defaults to rsqrt.4.ftz.f64 requires sm_13 or later.f64 were introduced in PTX ISA version 1.approx.f32 defaults to rsqrt. For PTX ISA version 1. Subnormal numbers: sm_20: By default. rsqrt.ftz}.approx.0. PTX ISA Notes rsqrt.f64 isr.f64 is emulated in software and are relatively slow. Explicit modifiers . January 24. a. rsqrt.f32 is 2-22.f32 rsqrt.approx implements an approximation to the reciprocal square root.approx.f64 is TBD. rsqrt.4 over the range 1. Input -Inf -normal -subnormal -0.approx{.approx. and rsqrt. Compute 1/sqrt(a).f64.0-4.approx. a. d.0 +0.0 through 1.f64 supports subnormal numbers. Note that rsqrt.approx modifier is required. x. rsqrt. store the result in d. Instruction Set Table 61.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f32.ftz were introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. the .ftz. rsqrt. For PTX ISA versions 1.approx.f32 supported on all target architectures.f64 d. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. X.3. d = 1/sqrt(a).ftz. ISR.0.f32 rsqrt.

f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default. the .f32. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz.approx and . a.f32 implements a fast approximation to sine.ftz introduced in PTX ISA version 1.4 and later.f32 flushes subnormal inputs and results to sign-preserving zero.0 +0. PTX ISA Notes sin. Target ISA Notes Examples Supported on all target architectures. sin.3. Find the sine of the angle a (in radians).0.ftz.0 +subnormal +Inf NaN Result NaN -0.0 -0.f32 d.0 +0. sin. d = sin(a).approx. For PTX ISA versions 1. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.ftz.f32 defaults to sin. a.PTX ISA Version 2.approx. subnormal numbers are supported. Input -Inf -subnormal -0. 96 January 24. sin. sin. For PTX ISA version 1. 2010 .0 +0.approx.0 Table 62.f32 sa.ftz}.approx modifier is required.0 NaN NaN The maximum absolute error is 2-20.9 in quadrant 00. sin.0 through 1.approx{. Explicit modifiers .4.

d = cos(a). 2010 97 .0 +1.ftz.f32 implements a fast approximation to cosine.ftz.approx modifier is required.f32.f32 introduced in PTX ISA version 1.approx.0 +0. sm_1x: Subnormal inputs and results to sign-preserving zero.0. cos.4 and later.ftz}. Subnormal numbers: sm_20: By default.Chapter 8. January 24.ftz introduced in PTX ISA version 1. a. Target ISA Notes Examples Supported on all target architectures.f32 defaults to cos.f32 flushes subnormal inputs and results to sign-preserving zero. Input -Inf -subnormal -0.0 +1.0 +1. a.approx. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.approx.approx{.f32 ca. cos. Find the cosine of the angle a (in radians). PTX ISA Notes cos.4.f32 d. cos.ftz. cos. the . For PTX ISA version 1. Instruction Set Table 63.0 NaN NaN The maximum absolute error is 2-20.0 +subnormal +Inf NaN Result NaN +1.approx and . cos. Explicit modifiers .9 in quadrant 00.3. For PTX ISA versions 1.0 through 1. subnormal numbers are supported.

f32 la.f32 implements a fast approximation to log2(a).ftz}.6 for mantissa. subnormal numbers are supported.ftz. PTX ISA Notes lg2. a. For PTX ISA versions 1.approx and .0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.ftz introduced in PTX ISA version 1.0.f32 Determine the log2 of a. Target ISA Notes Examples Supported on all target architectures. For PTX ISA version 1.approx{. Subnormal numbers: sm_20: By default.approx.PTX ISA Version 2. sm_1x: Subnormal inputs and results to sign-preserving zero. The maximum absolute error is 2-22. lg2. lg2.f32 introduced in PTX ISA version 1.4 and later.4.f32 defaults to lg2. 2010 . d = log(a) / log(2). 98 January 24.0 Table 64. lg2. lg2. the .3.f32.ftz. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz. Explicit modifiers . a.0 through 1. Input -Inf -subnormal -0. lg2.approx.f32 flushes subnormal inputs and results to sign-preserving zero.0 +0.approx modifier is required.approx.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

type . 2010 .dtype. gt. loweror-same. and nan returns true if either operand is NaN. geu. b. bit-size comparisons are eq and ne. If either operand is NaN. le. . . gt.dtype. . @q setp.ftz}. b.n. and hs for lower.type setp. ls. If either operand is NaN. the comparison operators lo. To aid comparison operations in the presence of NaN values. gtu.b32.u16.ftz}.f32. lt. lt. A related value computed using the complement of the compare result is written to the second destination operand.and. hi. {!}c. ne. ltu. If both operands are numeric values (not NaN).B) is one of: and. gtu.b64. ge. The comparison operator is a suffix on the instruction.s16. leu. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. lt. .eq. .CmpOp{.f32 flushes subnormal inputs to sign-preserving zero. respectively.s64. nan The Boolean operator BoolOp(A. ne.u32 p|q.ftz applies only to . neu. ls. le. ne.0.f64 source type requires sm_13 or later. num returns true if both operands are numeric values (not NaN). then these comparisons have the same result as their ordered counterparts. The signed and unsigned comparison operators are eq. leu. Modifier .r.f64 }.pred variables.b. a.f32 comparisons. setp. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. sm_1x: setp. xor. c). gt. p. ge.a. . ge.PTX ISA Version 2. This result is written to the first destination operand. unordered versions are included: equ. gt. .f32 flushes subnormal inputs to sign-preserving zero.0 Table 67. le. geu. and higher-or-same may be used instead of lt. For unsigned values. hs equ. setp with .s32. c). Subnormal numbers: sm_20: By default.b16. Applies to all numeric types.dtype. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. Semantics t = (a CmpOp b) ? 1 : 0. ltu. neu. and (optionally) combine this result with a predicate value by applying a Boolean operator.lt. q = BoolOp(!t. . setp.i.ftz. the result is false. . then the result of these comparisons is true. . The destinations p and q must be . p[|q]. higher. The untyped.CmpOp. or. 102 January 24.s32 setp. hi. p = BoolOp(t. Integer Notes Floating Point Notes The ordered comparisons are eq. and can be one of: eq. lo.u32. setp. a.type = { .f64 supports subnormal numbers. p[|q]. ge.u64. num. subnormal numbers are supported.BoolOp{. le.

. negative zero equals zero. @q selp. Operands d.f32.dtype. .f32 flushes subnormal values of operand c to sign-preserving zero. .f32 flushes subnormal values of operand c to sign-preserving zero. .xp.f32.f64 requires sm_13 or later.b32. If c ≥ 0. . Semantics Floating Point Notes January 24.Chapter 8.dtype = { .s16.0. otherwise b is stored in d. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s64.dtype. subnormal numbers are supported. . a. Table 69.u32. y. b.s32 selp. . . c.type = { .b64. operand c must match the second instruction type. b. selp. .b16.type d. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.s32.u32. . selp. and b must be of the same type. the comparison is unordered and operand b is selected. a is stored in d.u64.u32. slct.u64.dtype. Description Conditional selection. Subnormal numbers: sm_20: By default. slct. Operands d. a.f64 }.t.s64.f32 d. b.r. The selected input is copied to the output without modification. based on the sign of the third operand. slct. and operand a is selected.u16. . Modifier . . based on the value of the predicate source operand. 2010 103 . b otherwise.u64. selp Syntax Comparison and Selection Instructions: selp Select between source operands. d = (c >= 0) ? a : b. Instruction Set Table 68. a. z. slct.0.u16.f32 comparisons.f32 A. slct Syntax Comparison and Selection Instructions: slct Select one source operand. B. val. a. If c is True. c.s16. .ftz.f64 requires sm_13 or later. If operand c is NaN.x.ftz}.s32 x. .s32 slct{. a. .dtype. d.f32 comparisons. fval.b16.ftz. . C. sm_1x: slct. . . For .s32.b32. . c.p.f64 }.g. . and b are treated as a bitsize type of the same width as the first instruction type. f0.b64. and operand a is selected. Introduced in PTX ISA version 1. Operand c is a predicate.ftz applies only to .f32 r0. a is stored in d. d = (c == 1) ? a : b. . slct.

or. provided the operands are of the same size.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.4. performing bit-wise operations on operands of any type. This permits bit-wise operations on floating point values without having to define a union to access the bits.PTX ISA Version 2.0 8. Instructions and. 2010 . xor. and not also operate on predicates. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.

.0. Allowed types include predicate registers. d = a & b. .type = { .type d. but not necessarily the type.b16.b16. but not necessarily the type. .b32 x. sign.Chapter 8. Instruction Set Table 70.b64 }. b. and. and.type = { .0x80000000.r. January 24. . . . The size of the operands must match.pred.pred p. a. or Syntax Logic and Shift Instructions: or Bitwise OR.b32 mask mask.b64 }. Introduced in PTX ISA version 1.0x00010001 or.fpvalue. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. Supported on all target architectures. a.b32 and. b. The size of the operands must match. Allowed types include predicate registers.r.q.q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. . or. Supported on all target architectures.0. Introduced in PTX ISA version 1.b32. d = a | b.b32. .type d. 2010 105 . or.pred. and Syntax Logic and Shift Instructions: and Bitwise AND. Table 71.

not. . a.type = { .b32.b16 d. d = ~a. b.r.pred. cnot. . Table 74. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. The size of the operands must match.b32 mask. but not necessarily the type. Allowed types include predicates. Supported on all target architectures.0.type d. d. a. The size of the operands must match. not. but not necessarily the type.q. . 106 January 24. xor. d = (a==0) ? 1 : 0.b16.mask.0.b16.0.b32. .b64 }. one’s complement. . 2010 . Supported on all target architectures. . xor. The size of the operands must match. cnot.type = { .b64 }.b32 d. not. a.x.b64 }.type = { .type d. Table 73. . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). .0 Table 72.b32 xor. Introduced in PTX ISA version 1. .a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b16. d = a ^ b. not Syntax Logic and Shift Instructions: not Bitwise negation. Introduced in PTX ISA version 1.q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Introduced in PTX ISA version 1.pred.pred p. but not necessarily the type.type d. Allowed types include predicate registers. .0x0001. Supported on all target architectures.PTX ISA Version 2. .b32.

Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. a.u16 shr.type = { .type d. The b operand must be a 32-bit value.b32. PTX ISA Notes Target ISA Notes Examples January 24. i. sign or zero fill on left.a. . a. Signed shifts fill with the sign bit.b32 q.b64 }. Introduced in PTX ISA version 1.b16. . .b32.u16.2. b.2. Supported on all target architectures.0.u32. d = a >> b. . The b operand must be a 32-bit value.i. Shift amounts greater than the register width N are clamped to N. . b. d = a << b.a.u64. . shr. unsigned and untyped shifts fill with 0. k.1. regardless of the instruction type.j. shr Syntax Logic and Shift Instructions: shr Shift bits right. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. zero-fill on right. .b64.s32.0. shl. 2010 107 . shl. Shift amounts greater than the register width N are clamped to N. but not necessarily the type. The sizes of the destination and first source operand must match. regardless of the instruction type. The sizes of the destination and first source operand must match. Instruction Set Table 75.b16.type = { .i. Supported on all target architectures. .Chapter 8. but not necessarily the type. shr.b16 c.s16. .s32 shr. Introduced in PTX ISA version 1.s64 }. PTX ISA Notes Target ISA Notes Examples Table 76.type d. shl Syntax Logic and Shift Instructions: shl Shift bits left. . . Bit-size types are included for symmetry with SHL. .

local. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and sust support optional cache operations. Instructions ld. ld. possibly converting it from one format to another. The cvta instruction converts addresses between generic and global. and st operate on both scalar and vector types. or shared state spaces. 2010 . Data Movement and Conversion Instructions These instructions copy data from place to place.5. mov. and from state space to state space.7. ldu. st. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. prefetchu isspacep cvta cvt 108 January 24.PTX ISA Version 2. suld.0 8.

. A ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The default load instruction cache operation is ld. when applied to a local address.lu Last use. . invalidates (discards) the local L1 line following the load.cv Cache as volatile (consider cached system memory lines stale. but multiple L1 caches are not coherent for global data.cg Cache at global level (cache in L2 and below.lu load last use operation. Instruction Set 8. The ld.cs) on global addresses.cg to cache loads only globally. not L1).cs Cache streaming. Operator . For sm_20 and later. and a second thread loads that address via a second L1 cache with ld. . Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. If one thread stores to global memory via one L1 cache. to allow the thread program to poll a SysMem location written by the CPU.0 introduces optional cache operators on load and store instructions. The ld. The ld.lu operation.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.Chapter 8.cs. likely to be accessed again. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cs is applied to a Local window address.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. When ld. if the line is fully covered. evict-first. Cache Operators PTX 2.ca loads cached in L1. and cache only in the L2 cache. January 24.lu instruction performs a load cached streaming operation (ld. likely to be accessed once. the second thread may get stale L1 cache data. The cache operators require a target architecture of sm_20 or later. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. Global data is coherent at the L2 level. .cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. fetch again). Use ld. As a result of this request.ca. 2010 109 . The compiler / programmer may use ld.5. The ld. the cache operators have the following definitions and behavior. bypassing the L1 cache.cv to a frame buffer DRAM address is the same as ld.ca. it performs the ld.7. any existing cache lines that match the requested address in L1 will be evicted.1. rather than the data stored by the first thread. Table 77.

bypassing its L1 cache.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. bypassing the L1 cache.ca loads. and discard any L1 lines that match. but st. st.wt. likely to be accessed once. and a second thread in a different SM later loads from that address via a different L1 cache with ld. and cache only in the L2 cache. .0 Table 78. not L1). Operator . and marks local L1 lines evict-first.wt store write-through operation applied to a global System Memory address writes through the L2 cache. .cg is the same as st. If one thread stores to global memory. In sm_20. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wb for global data.wt Cache write-through (to system memory). The st. the second thread may get a hit on stale L1 cache data. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. in which case st.wb. Global stores bypass L1. 2010 . Use st. . Addresses not in System Memory use normal write-back.PTX ISA Version 2. The st.cs Cache streaming.cg to cache global store data only globally. which writes back cache lines of coherent cache levels with normal eviction policy.cg Cache at global level (cache in L2 and below. rather than get the data from L2 or memory stored by the first thread. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. to allow a CPU program to poll a SysMem location written by the GPU with st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. 110 January 24.cg to local memory uses the L1 cache. Future GPUs may have globally-coherent L1 caches.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.wb could write-back global store data from L1. regardless of the cache operation.ca. However. The default store instruction cache operation is st.

type mov. the parameter will be copied onto the stack and the address will be in the local state space. d = sreg.pred. the address of the variable in its state space) into the destination register. k.u32 mov.e. d = &avar. d. . local.1. immediate. myFunc. ptr.u16. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.0.type d.type = { ..u16 mov. // address is non-generic.a. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. Description .s16. or shared state space. local. Write register d with the value of a.f32 mov. a. Instruction Set Table 79. . within the variable’s declared state space Notes Although only predicate and bit-size types are required. . avar. variable in an addressable memory space.f32 mov. or shared state space may be taken directly using the cvta instruction. addr. d. the generic address of a variable declared in global. Introduced in PTX ISA version 1.shared state spaces.Chapter 8. mov places the non-generic address of the variable (i.b64. alternately. // get address of variable // get address of label or function . mov. mov. The generic address of a variable in global.f64 }. . label. . For variables declared in . . .v.const. Note that if the address of a device function parameter is moved to a register. local.u32 d. Take the non-generic address of a variable in global. d. .. .b32. . and . A[5]. Semantics d = a. Operand a may be a register. special register.f64 requires sm_13 or later.s32.type mov. A.u64.u32. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.type mov.e.0. label.u32 mov.local. mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. d = &label. u. . i. or function name.global. 2010 111 . sreg.s64.f32. . ptr.b16.

63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .. d.%r1. %r1. d. .x | (a.b16 { d. Description Write scalar register d with the packed value of vector register a.15].b32 { d.z.b}. a[32. {r. mov.a}.x.y.w } = { a[0.b. {lo.31].w}.15] } // unpack 8-bit elements from .b64 mov.63] } // unpack 16-bit elements from . lo.y << 16) d = a.b64 // pack two 32-bit elements into .. d. or write vector register d with the unpacked values from scalar register a..b8 r.y.b32 %r1.z << 32) | (a.w } = { a[0. mov. Supported on all target architectures.y << 16) | (a..w have type . a[16.b32 // pack two 16-bit elements into .31] } // unpack 16-bit elements from .y. a[32.z << 16) | (a. a.b64 { d.x | (a.x.y } = { a[0.b32 { d.x.7]..47]. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.a have type . a[16.31].u16 %x is a double.b32 mov.0 Table 80.. a[16.b16 // pack four 8-bit elements into .y << 8) | (a.x..w << 48) d = a.type = { .{a..7].y << 32) // pack two 8-bit elements into .z. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.{x.y } = { a[0. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). a[8. 2010 . d.x | (a.y. // // // // a.b64 { d.0.b..z. a[48.x | (a.b32.b have type . d.w << 24) d = a..b32 // pack four 16-bit elements into . For bit-size types. a[8. %x.z.u32 x.PTX ISA Version 2. d.b32 mov. .. d.y } = { a[0.u8 // unpack 32-bit elements from .hi}.. Semantics d = a.b64 112 January 24.hi are .15].b16.g.x | (a.y << 8) d = a. d...23]. d.31] } // unpack 8-bit elements from .type d.15].x. a[24.g.b64 }.

. .volatile{. . The . . .b64. [a]. .ss}{. . ld. 32-bit).cop = { .u32.type d. Semantics d d d d = = = = a. the access may proceed by silently masking off low-order address bits to achieve proper rounding.cop}.ss}{. an address maps to global memory unless it falls within the local memory window or the shared memory window.cs. i.global and .type = { .ca. ld introduced in PTX ISA version 1.v4 }. This may be used.f64 using cvt. . .shared spaces to inhibit optimization of references to volatile memory. or the instruction may fault. .f16 data may be loaded using ld.f32 or . Addresses are zero-extended to the specified width as needed. The address size may be either 32-bit or 64-bit. Within these windows.e. [a].volatile..local. i.vec = { . . Cache operations are not permitted with ld. Generic addressing and cache operations introduced in PTX ISA 2.0.shared }. .0. The value loaded is sign-extended to the destination register width for signed integers. or [immAddr] an immediate absolute byte address (unsigned.const. . A destination register wider than the specified type may be used.param. d.f64 }.1.v2. Generic addressing may be used with ld. . Description Load register variable d from the location specified by the source address operand a in specified state space.s32. If no state space is given.lu. . .vec. *(a+immOff).u16. . to enforce sequential consistency between threads accessing shared memory. In generic addressing. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.ss}. *a. 2010 113 .u64. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.volatile may be used with .cop}.global. the resulting behavior is undefined. Instruction Set Table 81.volatile introduced in PTX ISA version 1.const space suffix may have an optional bank number to indicate constant banks other than bank zero.cg. d. an address maps to the corresponding location in local or shared memory. . and is zeroextended to the destination register width for unsigned and bit-size types.f32.reg state space.ss}. ld.Chapter 8. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . The address must be naturally aligned to a multiple of the access size.ss = { . .b8.s64.volatile{. [a]. and then converted to .s16.e. . ld{.type ld{. 32-bit). The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. PTX ISA Notes January 24. *(immAddr). for example.u8. . d. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. .cv }. . .type ld. and truncated if the register width exceeds the state space address width for the target architecture.b16. perform the load using generic addressing. .s8. an integer or bit-size type register reg containing a byte address.type . [a].vec.b16.volatile. If an address is not properly aligned.b32.

b16 cvt.global. %r. d.[p+-8].[p+4]. // load . Cache operations require sm_20 or later.f32 ld. // immediate address %r.const. // access incomplete array x.b32 ld.f32.shared.[buffer+64].[240].[fs]. ld.%r.local.local.b64 ld.f16 d.0 Target ISA Notes ld. x.b32 ld.[a]. 2010 . Q. Generic addressing requires sm_20 or later.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.const[4].s32 ld.v4.global.b32 ld.[p].PTX ISA Version 2.f64 requires sm_13 or later. // negative offset %r.

32-bit). an address maps to the corresponding location in local or shared memory. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e.[p]. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.f64 using cvt. . or [immAddr] an immediate absolute byte address (unsigned. i.s64. // state space .[a]. perform the load using generic addressing. A register containing an address may be declared as a bit-size type or integer type. the access may proceed by silently masking off low-order address bits to achieve proper rounding.global }.u8. .s16. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. .vec. . the resulting behavior is undefined. .s32. *(immAddr). ldu{. *(a+immOff).f32. .type ldu{. Introduced in PTX ISA version 2. [a]. A destination register wider than the specified type may be used. In generic addressing. Instruction Set Table 82. [a]. and then converted to .f32 d. .f64 }.global. ldu. Within these windows.v4 }.0. For ldu.vec = { .b16.reg state space.global. or the instruction may fault.f32 or . The address must be naturally aligned to a multiple of the access size. . i.b32 d.f32 Q.Chapter 8. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.ss}. 2010 115 .e.b64. and truncated if the register width exceeds the state space address width for the target architecture. where the address is guaranteed to be the same across all threads in the warp. . 32-bit).global.b32.type = { .u16. only generic addresses that map to global memory are legal. ldu. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . Addresses are zero-extended to the specified width as needed.b8.b16. // load from address // vec load from address . The value loaded is sign-extended to the destination register width for signed integers. . ldu. The addressable operand a is one of: [avar] the name of an addressable variable var. and is zeroextended to the destination register width for unsigned and bit-size types. PTX ISA Notes Target ISA Notes Examples January 24.ss = { . [areg] a register reg containing a byte address.s8. . .ss}. The address size may be either 32-bit or 64-bit. ldu. d.type d. .f64 requires sm_13 or later. If an address is not properly aligned..[p+4]. The data at the specified address must be read-only.v2.u64. .v4. an address maps to global memory unless it falls within the local memory window or the shared memory window.f16 data may be loaded using ldu. . Semantics d d d d = = = = a. *a.u32. If no state space is given. .

f64 requires sm_13 or later.v2.wt }.reg state space. .ss}. the resulting behavior is undefined.0. The lower n bits corresponding to the instruction-type width are stored to memory. . st. PTX ISA Notes Target ISA Notes 116 January 24. This may be used.u32. Addresses are zero-extended to the specified width as needed.f64 }. A source register wider than the specified type may be used.b8. *(d+immOffset) = a. Semantics d = a.global. b. Generic addressing may be used with st. [a]. *d = a. If no state space is given.s16.f32. The address size may be either 32-bit or 64-bit. Cache operations require sm_20 or later.shared }.global and . . If an address is not properly aligned. and truncated if the register width exceeds the state space address width for the target architecture. b.type [a]. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. . Generic addressing requires sm_20 or later. .cs.b16.volatile. Generic addressing and cache operations introduced in PTX ISA 2.u8.PTX ISA Version 2.v4 }. i.s32. for example.b32. [a]. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .cop .cg.vec.ss}.s64.cop}. an integer or bit-size type register reg containing a byte address. .. .shared spaces to inhibit optimization of references to volatile memory.vec .type st{. The address must be naturally aligned to a multiple of the access size. 32-bit). [a]. st. Within these windows.volatile introduced in PTX ISA version 1. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. .ss . . { . i. { . an address maps to the corresponding location in local or shared memory.volatile may be used with . b. . perform the store using generic addressing. st. Cache operations are not permitted with st.type .s8.0 Table 83.b16. or [immAddr] an immediate absolute byte address (unsigned. 2010 . . .f16 data resulting from a cvt instruction may be stored using st.u16. an address maps to global memory unless it falls within the local memory window or the shared memory window. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e. b. *(immAddr) = a.ss}{.volatile. .cop}. st{. to enforce sequential consistency between threads accessing shared memory.vec. 32-bit).e. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. or the instruction may fault.local. .0. In generic addressing.type = = = = {. . st introduced in PTX ISA version 1. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.type st.1. .b64. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. .u64.wb. .ss}{.volatile{. { .volatile{.

%r. 2010 117 .b.b16 [a]. // negative offset [100].%r.a.f32 st.global.v4.f32 st.global.Q. [q+-8].f16.a.s32 st.local.b32 st. // immediate address %r. // %r is 32-bit register // store lower 16 bits January 24.s32 cvt.Chapter 8.local. [p]. [fs]. Instruction Set Examples st.local.r7.b32 st. [q+4].

prefetch{. The address size may be either 32-bit or 64-bit. and truncated if the register width exceeds the state space address width for the target architecture. 32-bit).0 Table 84.L2 }. In generic addressing. in specified state space. prefetch. or [immAddr] an immediate absolute byte address (unsigned. an address maps to the corresponding location in local or shared memory.0. . The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. prefetchu. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.level prefetchu. Addresses are zero-extended to the specified width as needed.global. If no state space is given.L1 [addr]. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. i.L1 [ptr]. .space = { .PTX ISA Version 2. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. [a]. 32-bit). 2010 . A prefetch to a shared memory location performs no operation.level = { . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. the prefetch uses generic addressing. // prefetch to data cache // prefetch to uniform cache . an address maps to global memory unless it falls within the local memory window or the shared memory window. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.e. Within these windows.space}.L1. a register reg containing a byte address. prefetch and prefetchu require sm_20 or later. A prefetch into the uniform cache requires a generic address. . The addressable operand a is one of: [var] [reg] the name of an addressable variable var. 118 January 24.L1 [a].local }. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. and no operation occurs if the address maps to a local or shared memory location.global.

shared. Introduced in PTX ISA version 2.global.space. isspacep.to. or shared address cvta. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shared isglbl. Use cvt. The destination register must be of type . a. or vice-versa.u32.size cvta. isspacep. or shared address.genptr.u64 }. svar.pred .local isspacep.lptr. . sptr.local.u32 p.u32 p. cvta requires sm_20 or later. . // result is .size p. var. cvta. January 24.shared }. The source address operand must be a register of type . cvta.space = { . isspacep requires sm_20 or later. or shared state space.local.space.u32. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. the generic address of the variable may be taken using cvta. When converting a generic address into a global. Instruction Set Table 85. A program may use isspacep to guard against such incorrect behavior. local. lptr. or shared state space to generic. . or shared address to a generic address. . a. 2010 119 .global.0. Description Convert a global.u32 to truncate or zero-extend addresses.local. isshrd. a. // get generic address of svar cvta. or vice-versa. local.space p.u64. // convert to generic address // get generic address of var // convert generic address to global. local. gptr. .u64.to. p.size = { . the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. cvta. islcl. PTX ISA Notes Target ISA Notes Examples Table 86. For variables declared in global. The source and destination addresses must be the same size. local.u32 gptr.u32 or . local. Take the generic address of a variable declared in global.space = { .shared }. .space. or shared state space. // local. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.global.0. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.size .Chapter 8.u64 or cvt. p.pred.global isspacep.

Integer rounding is required for float-to-integer conversions. . .irnd}{.f16. The optional . 120 January 24. a. 2010 . subnormal inputs are flushed to signpreserving zero.f32.rn.dtype.ftz.u16.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.ftz. Integer rounding modifiers: . .s64.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. a. The compiler will preserve this behavior for legacy PTX code. .ftz}{.sat}. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32. subnormal numbers are supported.frnd}{.rpi }. .u8.rzi round to nearest integer in the direction of zero .dtype. // integer rounding // fp rounding . .ftz.dtype = .atype d. subnormal inputs are flushed to signpreserving zero. .e. choosing even integer if source is equidistant between two integers.ftz}{.s8. . . .MAXINT for the size of the operation.sat}. . cvt{.PTX ISA Version 2.0 Table 87.4 and earlier.sat is redundant.atype = { . For float-to-integer conversions. Saturation modifier: . i. d. . . .rni round to nearest integer.dtype.f32 float-to-integer conversions and cvt. i.f32.f32 float-to-integer conversions and cvt. Description Semantics Integer Notes Convert between different types and sizes.u32.frnd = { .ftz modifier may be specified in these cases for clarity.s32. and for same-size float-tofloat conversions where the value is rounded to an integer. sm_1x: For cvt.f64 }. Integer rounding is illegal in all other instances.rmi. . the result is clamped to the destination range by default.rm. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. .rz.atype cvt{.rzi.sat limits the result to MININT. Note: In PTX ISA versions 1. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.rp }. . Note that saturation applies to both signed and unsigned integer types. For cvt. the .f32 float-tofloat conversions with integer rounding.dtype.e.rmi round to nearest integer in direction of negative infinity .. .s16.ftz.u64.rni.irnd = { . . . ..sat For integer destination types. d = convert(a).f32 float-tofloat conversions with integer rounding.

f64.f32 x. NaN results are flushed to positive zero. cvt.y.s32 f. Applies to . stored in floating-point format.f32. Saturation modifier: .version is 1. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f32 instructions.0.f16.f32 x. Specifically. and . // round to nearest int.f64 requires sm_13 or later.f32.r. cvt. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.rni.4 and earlier. // note . result is fp cvt. Floating-point rounding modifiers: .Chapter 8. The operands must be of the same size. subnormal numbers are supported.i. The result is an integral value. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f32. 2010 121 . Modifier .f16. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f16. Note: In PTX ISA versions 1. // float-to-int saturates by default cvt.f64 types.sat For floating-point destination types.rm mantissa LSB rounds towards negative infinity . cvt to or from . if the PTX . Subnormal numbers: sm_20: By default.rn mantissa LSB rounds to nearest even .f32.y. .f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64 j.0]. and for integer-to-float conversions. The compiler will preserve this behavior for legacy PTX code.f32. Floating-point rounding is illegal in all other instances.ftz behavior for sm_1x targets January 24.rz mantissa LSB rounds towards zero . 1.ftz modifier may be specified in these cases for clarity.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Introduced in PTX ISA version 1.s32.0.f32.4 or earlier. . and cvt. The optional . cvt.sat limits the result to the range [0.

. r4.v4. r1. [tex1]. and surface descriptors. sampler. sampler. add. r1.f32 r1.b32 r6.texref tex1 ) { txq. The advantage of independent mode is that textures and samplers can be mixed and matched.0 8. 2010 .global . add. add. 122 January 24. with the restriction that they correspond 1-to-1 with the 128 possible textures. = nearest width height tsamp1. In the independent mode. texture and sampler information each have their own handle. and surface descriptors.6. } = clamp_to_border.target options ‘texmode_unified’ and ‘texmode_independent’. div. r6. [tex1. PTX has two modes of operation. cvt.PTX ISA Version 2.texref handle. samplers.f2}]. the file is assumed to use unified mode.f32.b32 r5. r5. and surface descriptors. // get tex1’s txq. Module-scope and per-entry scope definitions of texture.f32 r3.samplerref tsamp1 = { addr_mode_0 filter_mode }.f32. r1. r5.f32 r1. r2.. sampler. and surfaces.width.height. If no texturing mode is declared.u32 r5. mul. r5. r3. .r3.entry compute_power ( . PTX supports the following operations on texture. .. Texture and Surface Instructions This section describes PTX instructions for accessing textures.r4}.u32 r5. The texturing mode is selected using . Example: calculate an element’s power contribution as element’s power/total number of elements. allowing them to be defined separately and combined at the site of usage in the program. but the number of samplers is greatly restricted to 16. sampler.f32 r1. Ability to query fields within texture. r3.2d. [tex1].target texmode_independent . and surface descriptors: • • • Static initialization of texture. {f1. In the unified mode. texture and sampler information is accessed through a single .f32 {r1. A PTX module may declare only one texturing mode.7. The advantage of unified mode is that it allows 128 samplers.r2. // get tex1’s tex. Texturing modes For working with textures and samplers.param .

s32. 2010 123 .3d }. tex txq suld sust sured suq Table 88. . Notes For compatibility with prior versions of PTX. [tex_a. the access may proceed by silently masking off low-order address bits to achieve proper rounding.r4}.v4. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.geom. with the extra elements being ignored. //Example of unified mode texturing tex.v4.r3. is a two-element vector for 2d textures. . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. and is a four-element vector for 3d textures.Chapter 8. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.geom. If no sampler is specified. Operand c is a scalar or singleton tuple for 1d textures.dtype. . the sampler behavior is a property of the named texture.f32 }.1d. [tex_a. where the fourth element is ignored.v4. d.f3.s32.v4. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.btype tex. {f1. PTX ISA Notes Target ISA Notes Examples January 24. .f4}]. {f1}].3d.1d. c].geom = { .2d. If an address is not properly aligned.r4}. tex.e.r2.0. // Example of independent mode texturing tex.5. The instruction always returns a four-element vector of 32-bit values. .f32 }. A texture base address is assumed to be aligned to a 16-byte address.f32 {r1. [a.dtype. or the instruction may fault. [a. An optional texture sampler b may be specified.f2. the resulting behavior is undefined. Unified mode texturing introduced in PTX ISA version 1. b.btype = { . sampler_x.s32. // explicit sampler .r3.dtype = { . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. c]. i.s32.v4 coordinate vectors are allowed for any geometry.u32..btype d.s32 {r1.r2. . . the square brackets are not required and . Description Texture lookup using a texture coordinate vector. Supported on all target architectures. Instruction Set These instructions provide access to texture and surface memory.

Description Query an attribute of a texture or sampler.PTX ISA Version 2. . Operand a is a .depth . Query: . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. addr_mode_1. mirror.5. sampler attributes are also accessed via a texref argument. [a]. . .normalized_coords .filter_mode.tquery = { .addr_mode_2 Returns: value in elements 1 (true) or 0 (false).tquery. [a].addr_mode_0.height . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.squery.squery = { . txq. clamp_to_edge. // texture attributes // sampler attributes . addr_mode_2 }. [tex_A].b32 txq.texref or .filter_mode .depth. .b32 %r1.addr_mode_0 .width. In unified mode. txq. linear } Integer from enum { wrap.b32 d. txq. 2010 . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. [tex_A].addr_mode_1 . d.b32 %r1.width . .b32 %r1.height. txq. // unified mode // independent mode 124 January 24.addr_mode_0.0 Table 89. clamp_ogl.width. [smpl_B].filter_mode. Supported on all target architectures. and in independent mode sampler attributes are accessed via a separate samplerref argument.samplerref variable.normalized_coords }. Integer from enum { nearest.

The lowest dimension coordinate represents a sample offset rather than a byte offset. Cache operations require sm_20 or later. [a.u32. . . then .clamp. {x.p.v2.s32.2d.3d.trap . suld.trap suld.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.clamp . {x}]. or the instruction may fault. .s32. suld.b.r2}.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.dtype.trap introduced in PTX ISA version 1.cop .f4}. .p is currently unimplemented. {f1. suld. [surf_B.b32.zero }.p.b32. where the fourth element is ignored. suld Syntax Texture and Surface Instructions: suld Load from surface memory.Chapter 8. // formatted .p requires sm_20 or later.trap {r1. the access may proceed by silently masking off low-order address bits to achieve proper rounding. size and type conversion is performed as needed to convert from the surface sample format to the destination type.3d requires sm_20 or later. . if the surface format contains UINT data.w}].b64 }.b8 . G. .v2.s32.dtype . if the surface format contains SINT data. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.clamp suld. If an address is not properly aligned.clamp = = = = = = { { { { { { d. .geom{. . If the destination base type is . sm_1x targets support only the . and cache operations introduced in PTX ISA version 2. The . and is a four-element vector for 3d surfaces. .surfref variable. // cache operation none.cop}. additional clamp modifiers.z. or FLOAT data.s32. suld.u32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. . // unformatted d.f32 is returned.b.e.v4 }.p. Instruction Set Table 90. .b .v4.b16.v4. Description Load from surface memory using a surface coordinate vector. // for suld. suld.cs.dtype . [surf_A. .trap. . Operand b is a scalar or singleton tuple for 1d surfaces.s32 is returned.b64. i. then .f32 based on the surface format as follows: If the surface format contains UNORM. If the destination type is .y.u32 is returned. is a two-element vector for 2d surfaces.p . suld.0.cg. Target ISA Notes Examples January 24.dtype. suld. .clamp field specifies how to handle out-of-bounds addresses: .cop}.1d.geom{.f32.cv }.5. .b32. [a. . the surface sample elements are converted to .trap clamping modifier. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Operand a is a .f2.u32.ca. A surface base address is assumed to be aligned to a 16-byte address. Destination vector elements corresponding to components that do not appear in the surface format are not written. or . the resulting behavior is undefined. or . b]. . then . and A components of the surface format.f3.geom . Coordinate elements are of type . B. suld. 2010 125 .clamp .b supported on all target architectures. SNORM. b]. ..f32 }.vec.3d }. // for suld. suld. .b.f32. and the size of the data transfer matches the size of destination operand d.1d.vec .b performs an unformatted load of binary data.

vec.clamp = = = = = = { { { { { { [a.b.z.r2}.b.b32.ctype .v2.p requires sm_20 or later. sust.p performs a formatted store of a vector of 32-bit data values to a surface sample.ctype . . c.trap sust.cop}. or FLOAT data. sust. If an address is not properly aligned.clamp field specifies how to handle out-of-bounds addresses: . {f1.f32} are currently unimplemented. .ctype.3d requires sm_20 or later. then . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. and is a four-element vector for 3d surfaces. sust. b]. Operand b is a scalar or singleton tuple for 1d surfaces.f32.v4 }.vec . . .p.s32.y. and A surface components. {x}]. The size of the data transfer matches the size of source operand c.s32. {r1.v2. then . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.wb. b]. and cache operations introduced in PTX ISA version 2. {x. SNORM.geom{.p.0. .b8 .vec. These elements are written to the corresponding surface sample components.e. . Surface sample components that do not occur in the source vector will be written with an unpredictable value. size and type conversions are performed as needed between the surface sample format and the destination type.b // for sust.wt }. If the source type is . if the surface format contains UINT data.f2.cop .f4}.0 Table 91.cs. Operand a is a . sust.b supported on all target architectures. .f32 is assumed. additional clamp modifiers. sust. .trap [surf_A. // for sust.p. B..v4.b. . The lowest dimension coordinate represents a sample offset rather than a byte offset. sust. sust Syntax Texture and Surface Instructions: sust Store to surface memory. A surface base address is assumed to be aligned to a 16-byte address.f3.trap clamping modifier. the resulting behavior is undefined. . 2010 . [a.f32.3d }.clamp. then . . Source elements that do not occur in the surface sample are ignored. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .surfref variable.ctype. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b32.b16.p Description Store to surface memory using a surface coordinate vector. where the fourth element is ignored.trap .5. . . c. none. // unformatted // formatted .3d.b64. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.cg.zero }.cop}. Coordinate elements are of type . The .s32. .s32 is assumed. i.w}].u32. sust. sm_1x targets support only the .geom{. .trap. . G. .s32.u32. or the instruction may fault. is a two-element vector for 2d surfaces.u32 is assumed.clamp sust. sust.b performs an unformatted store of binary data. if the surface format contains SINT data.b32. If the source base type is .{u32. Target ISA Notes Examples 126 January 24.1d.1d.f32 }. or .b64 }. [surf_B. .p. The source data is then converted from this type to the surface sample format.geom .PTX ISA Version 2.clamp .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. sust. .trap introduced in PTX ISA version 1.2d.clamp . Cache operations require sm_20 or later. The source vector elements are interpreted left-to-right as R.

sured requires sm_20 or later. or the instruction may fault.trap [surf_A. then .p.b . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.surfref variable.add. January 24.clamp.b32 type.u32. is a two-element vector for 2d surfaces. if the surface format contains SINT data.add. . .0.u32 is assumed.y}]. or . // for sured.b. min and max apply to . .geom. Operand b is a scalar or singleton tuple for 1d surfaces.u32 based on the surface sample format as follows: if the surface format contains UINT data. .3d }. sured.op. the resulting behavior is undefined.min. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.b. .ctype = { .u32 and . .clamp . If an address is not properly aligned.2d.ctype = { .u64.p performs a reduction on sample-addressed 32-bit data.p .b32.op. A surface base address is assumed to be aligned to a 16-byte address.u32.op = { .s32.c.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r1. . sured.. . The instruction type is restricted to .c.b].clamp [a.clamp = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. i. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.geom = { .geom. .p.trap . .or }. where the fourth element is ignored.max.u64. operations and and or apply to .clamp field specifies how to handle out-of-bounds addresses: .min. {x. sured. r1. {x}]. and . Operand a is a . . Reduction to surface memory using a surface coordinate vector.1d. Instruction Set Table 92.ctype.e.u32.2d.trap. The lowest dimension coordinate represents a sample offset rather than a byte offset.s32.1d.s32 types.b performs an unformatted reduction on . .and.b].ctype. [surf_B.s32 or .Chapter 8. .s32 types.s32. . // byte addressing sured.zero }.b32. then . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. // for sured. Operations add applies to .u64 data.clamp [a. and the data is interpreted as . // sample addressing .s32 is assumed.b32 }. .b32. Coordinate elements are of type .u32. 2010 127 . The . sured.b32 }. and is a four-element vector for 3d surfaces. .trap sured.

.depth }. [surf_A].width . Description Query an attribute of a surface. Operand a is a . [a].0 Table 93.query.b32 d.height.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.b32 %r1. 2010 . Supported on all target architectures. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.5.surfref variable. .width.width.query = { . Query: .height . suq. 128 January 24.PTX ISA Version 2. suq.

2010 129 . Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. Supported on all target architectures. used primarily for defining a function body.0. If {!}p then instruction Introduced in PTX ISA version 1. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. { add.0.y.s32 a. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.f32 @q bra L23. ratio. } PTX ISA Notes Target ISA Notes Examples Table 95.7.f32 @!p div. setp. Instruction Set 8.eq. mov. @{!}p instruction.0. Supported on all target architectures.s32 d.a. { instructionList } The curly braces create a group of instructions. Execute an instruction or instruction block for threads that have the guard predicate true. {} Syntax Description Control Flow Instructions: { } Instruction grouping.c. Introduced in PTX ISA version 1. p.b.7.Chapter 8. Threads with a false guard predicate do nothing.x.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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and the barrier is reinitialized so that it can be immediately reused. the waiting threads are restarted without delay.arrive does not cause any waiting by the executing threads.or }. January 24.sync with an immediate barrier number is supported for sm_1x targets.sync and bar. b. p. bar. and d have type . If no thread count is specified.0. Note that a non-zero thread count is required for bar. b}. Instruction Set Table 100.sync 0.red are population-count (. .or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Once the barrier count is reached. 2010 133 . threads within a CTA that wish to communicate via memory can store to memory.sync bar. bar.popc).op.popc is the number of threads with a true predicate.red} introduced in PTX . b}. When a barrier completes.0. and bar. Operand b specifies the number of threads participating in the barrier. thread count.sync or bar. Only bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.arrive.popc. the optional thread count must be a multiple of the warp size. and any-thread-true (. it is as if all the threads in the warp have executed the bar instruction.sync without a thread count introduced in PTX ISA 1.{arrive. a{.u32 bar.u32. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.and. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. Description Performs barrier synchronization and communication within a CTA.red should not be intermixed with bar. d. b}. {!}c. Thus.15.arrive a{. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). bar.red also guarantee memory ordering among threads identical to membar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. a{. bar. The barrier instructions signal the arrival of the executing threads at the named barrier. a.red instruction.cta. In addition to signaling its arrival at the barrier. The reduction operations for bar.and and .red} require sm_20 or later. and bar. PTX ISA Notes Target ISA Notes Examples bar.arrive using the same active barrier.red. Operands a. operands p and c are predicates. In conditionally executed code. bar. and then safely read values stored by other threads prior to the barrier. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. if any thread in a warp executes a bar instruction. Each CTA instance has sixteen barriers numbered 0..pred .red. b. Register operands.red performs a predicate reduction across the threads participating in the barrier. Execution in this case is unpredictable. Since barriers are executed on a per-warp basis. bar.sync and bar.and). {!}c.sync or bar. bar. the final value is written to the destination register in all threads waiting at the barrier.version 2. it simply marks a thread's arrival at the barrier. the bar. Register operands. The result of .op = { . thread count. All threads in the warp are stalled until the barrier completes. all threads in the CTA participate in the barrier.red delays the executing threads (similar to bar. bar. all-threads-true (. bar. execute a bar.or). Barriers are executed on a per-warp basis as if all the threads in a warp are active.sync) until the barrier count is met.red performs a reduction operation across threads. while . a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).{arrive. Thus.Chapter 8.

membar. PTX ISA Notes Target ISA Notes Examples membar. this is the appropriate level of membar. A memory read (e.sys introduced in PTX . membar. and memory reads by this thread can no longer be affected by other thread writes. membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.sys requires sm_20 or later. membar. level describes the scope of other clients for which membar is an ordering event.sys will typically have much longer latency than membar.sys Waits until all prior memory requests have been performed with respect to all clients.sys. membar. membar. that is.gl.cta.gl will typically have a longer latency than membar. membar. global. 134 January 24.gl.version 1. . Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. A memory write (e.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.g.0.g.version 2.level = { .gl} introduced in PTX . membar.gl} supported on all target architectures. 2010 . or system memory level.gl.cta. Waits until prior memory reads have been performed with respect to other threads in the CTA. including thoses communicating via PCI-E such as system and peer-to-peer memory.sys }.cta Waits until all prior memory writes are visible to other threads in the same CTA.{cta. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. For communication between threads in different CTAs or even different SMs. membar. when the previous value can no longer be read. red or atom) has been performed when the value written has become visible to other clients at the specified level. . membar. membar.4.level.cta.{cta. . Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.0 Table 101. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. by st.PTX ISA Version 2.

b. If no state space is given. atom. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. d.max }. The integer operations are add. . [a]. .u64 . the resulting behavior is undefined. 2010 135 . perform the memory accesses using generic addressing. atom{. The address must be naturally aligned to a multiple of the access size.cas.b]. 32-bit operations.space}.u32.e. dec.type atom{.. The floating-point operations are add. . . Description // // // // // .g.add.s32. A register containing an address may be declared as a bit-size type or integer type.e.b32. For atom. inc. c.Chapter 8. ..f32 Atomically loads the original value at location a into destination register d.xor. xor. .global.u32. The bit-size operations are and. [a].f32. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.b64. .s32. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. Instruction Set Table 102.op = { . min. an address maps to the corresponding location in local or shared memory. max. Operand a specifies a location in the specified state space. .exch.space = { .dec. . .min. min. or the instruction may fault. and max. min. performs a reduction operation with operand b and the value in location a.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.add. Within these windows. i. If an address is not properly aligned.b32. The address size may be either 32-bit or 64-bit. . . or by using atom.u64. .u32 only . an address maps to global memory unless it falls within the local memory window or the shared memory window. or. . .s32.u32.f32 }.type d. b.b32 only . .shared }. In generic addressing.b64 . . by inserting barriers between normal stores and atomic operations to a common address.or. Addresses are zero-extended to the specified width as needed. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. e. overwriting the original value. cas (compare-and-swap). or [immAddr] an immediate absolute byte address. and exch (exchange). and stores the result of the specified operation at location a. .op. .space}.inc. and truncated if the register width exceeds the state space address width for the target architecture. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.op. . . The floating-point add. . a de-referenced register areg containing a byte address. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. January 24. accesses to local memory are illegal. .and. and max operations are single-precision. i.exch to store to locations accessed by other atomic operations. The inc and dec operations return a result in the range [0. the access may proceed by silently masking off low-order address bits to achieve proper rounding.type = { .

s) = (r > s) ? s exch(r.global requires sm_11 or later.t) = (r == s) ? t operation(*a. c) operation(*a. : r+1.f32 requires sm_20 or later. Release Notes Examples @p 136 January 24.0.{add.global. atom. 64-bit atom.s.[a].1.[x+4].f32.max} are unimplemented.0 Semantics atomic { d = *a. atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. d. 2010 .max.global.add.shared. atom. Use of generic addressing requires sm_20 or later. atom.{min.cas. d. s) = s.PTX ISA Version 2.cas.0. 64-bit atom.shared requires sm_12 or later.add.exch} requires sm_12 or later.my_val.f32 atom.[p]. atom.b32 d. s) = (r >= s) ? 0 dec(r. : r-1. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. b). : r. *a = (operation == cas) ? : } where inc(r. b.shared operations require sm_20 or later. cas(r. Introduced in PTX ISA version 1.my_new_val.s32 atom.

The floating-point operations are add.op = { . accesses to local memory are illegal. the access may proceed by silently masking off low-order address bits to achieve proper rounding.global.add. or. Instruction Set Table 103. inc. . .b].b64. overwriting the original value. by inserting barriers between normal stores and reduction operations to a common address.op.b32. Semantics *a = operation(*a. .and.u32. red{.u64 . . where inc(r.. . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. . . Operand a specifies a location in the specified state space.space}.u32.Chapter 8.type [a].b32 only . Within these windows.min.. max.s32. . or [immAddr] an immediate absolute byte address.g.xor. an address maps to the corresponding location in local or shared memory. January 24. The inc and dec operations return a result in the range [0.u32 only .space = { . Description // // // // . The address must be naturally aligned to a multiple of the access size. . . min. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.e. .inc. 2010 137 . red.exch to store to locations accessed by other reduction operations. .e.f32. The floating-point add. b.s32.max }. . . an address maps to global memory unless it falls within the local memory window or the shared memory window.u64. . e. The address size may be either 32-bit or 64-bit. min. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.s32. or the instruction may fault.add.u32. s) = (r > s) ? s : r-1. b). If an address is not properly aligned. . dec(r. . or by using atom. Notes Operand a must reside in either the global or shared state space. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. A register containing an address may be declared as a bit-size type or integer type. the resulting behavior is undefined. Addresses are zero-extended to the specified width as needed. . The integer operations are add.or.f32 }. . The bit-size operations are and. and stores the result of the specified operation at location a.shared }.dec. . For red. 32-bit operations. min. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. and max.type = { .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. s) = (r >= s) ? 0 : r+1. and truncated if the register width exceeds the state space address width for the target architecture. If no state space is given. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. perform the memory accesses using generic addressing.f32 Performs a reduction operation with operand b and the value in location a. dec. i. and xor. i. a de-referenced register areg containing a byte address. and max operations are single-precision. In generic addressing.

PTX ISA Version 2.global.f32 red. 64-bit red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.s32 red. 64-bit red. red.add.global requires sm_11 or later red.b32 [a]. [x+4].shared operations require sm_20 or later.and.f32.my_val. red.f32 requires sm_20 or later. Release Notes Examples @p 138 January 24. Use of generic addressing requires sm_20 or later. red.add requires sm_12 or later.shared requires sm_12 or later.max} are unimplemented.0.1. [p]. 2010 . red.add.2.{min.shared.global.max.

where the bit position corresponds to the thread’s lane id. The reduction modes are: .none. .all True if source predicate is True for all active threads in warp. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.uni True if source predicate has the same value in all active threads in warp.ballot.Chapter 8. vote. . vote. .uni.p.ballot.any True if source predicate is True for some active thread in warp.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. vote. r1.all. p.not_all.uni.pred vote.pred vote. The destination predicate value is the same across all threads in the warp. not across an entire CTA.2.any. Negating the source predicate also computes . returns bitmask . // ‘ballot’ form. vote requires sm_12 or later.mode = { .pred d.ballot.ballot. Negate the source predicate to compute . 2010 139 .b32 requires sm_20 or later.q.b32 d. . Instruction Set Table 104. {!}a. Description Performs a reduction of the source predicate across threads in a warp.uni }.all. {!}a.mode. In the ‘ballot’ form. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.b32 p. // get ‘ballot’ across warp January 24. Negate the source predicate to compute .q. vote. Note that vote applies to threads in a single warp. vote.

to produce signed 33-bit input values.max }. extract and sign. 2010 . vop. The type of each operand (.b2. b{.b1. b{. c.u32.9.bsel}. half-word. .btype{. a{.asel}.u32 or . . 140 January 24.atype. . b{. the input values are extracted and signor zero. .atype.h0.0 8. 3. . a{.bsel}. 4. Using the atype/btype and asel/bsel specifiers.dtype = . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. c.bsel}. optionally clamp the result to the range of the destination type.asel}.dsel = .s32) is specified in the instruction type. // 32-bit scalar operation. a{. with optional data merge vop.secop = { .h1 }.s32 }.btype{. The general format of video instructions is as follows: // 32-bit scalar operation. Video Instructions All video instructions operate on 32-bit register operands. with optional secondary operation vop. taking into account the subword destination size in the case of optional data merging. 2. .dtype.min.sat} d.or zero-extend byte. The source and destination operands are all 32-bit registers.btype = { . or word values from its source operands. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).asel}. .sat} d.atype = .secop d.atype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. .b3.bsel = { . The primary operation is then performed to produce an .extended internally to .sat}.dsel.s34 intermediate result. all combinations of dtype.btype{. .add. .s33 values.7.asel = .dtype.PTX ISA Version 2. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.dtype. The sign of the intermediate result depends on dtype. atype. and btype are valid. .b0. perform a scalar arithmetic operation to produce a signed 34-bit result.

c). U32_MIN ). c). The lower 32-bits are then written to the destination operand. . U16_MIN ).h0. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). January 24. . S16_MAX. . .b3: return ((tmp & 0xff) << 24) default: return tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. as shown in the following pseudocode. S32_MIN ).b0. Instruction Set . The sign of the c operand is based on dtype. .s33 optSecOp(Modifier secop. Modifier dsel ) { if ( !sat ) return tmp. switch ( dsel ) { case . tmp. .h0: return ((tmp & 0xffff) case . S32_MAX.add: return tmp + c.b1. U16_MAX. S8_MIN ). c). S8_MAX. c). tmp.min: return MIN(tmp. U8_MIN ).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp. .s33 optSaturate( .max return MAX(tmp. c).b0: return ((tmp & 0xff) case . c). Bool sign. tmp.s33 tmp. .Chapter 8.h1: return ((tmp & 0xffff) << 16) case . Bool sat. tmp. . .b2. 2010 141 . default: return tmp.s33 optMerge( Modifier dsel.b3: if ( sign ) return CLAMP( else return CLAMP( case . U32_MAX.b1: return ((tmp & 0xff) << 8) case .s34 tmp. c). S16_MIN ). .b2: return ((tmp & 0xff) << 16) case . } } . U8_MAX.s33 c ) switch ( dsel ) { case .s33 tmp.s33 c) { switch ( secop ) { .

or zero-extend based on source operand type ta = partSelectSignExtend( a.max }. atype.op2 d.0 Table 105.btype{. r3.s32. tb = partSelectSignExtend( b. . d = optSecondaryOp( op2.add r1. .b2. . tb ). r2.s32.s32.op2 Description = = = = { vadd. { .min. dsel ).bsel}. b{. c ).bsel = { .dtype . vmax Syntax Integer byte/half-word/word addition / subtraction. vabsdiff. c ). Integer byte/half-word/word minimum / maximum. vadd. c. // extract byte/half-word/word and sign. // 32-bit scalar operation.dsel.s32. . Integer byte/half-word/word absolute value of difference. tmp = MIN( ta.dtype. vmin. .s32.sat}. bsel ).atype = . a{. tb ). c. r3.asel}. with optional secondary operation vop. tmp.btype{.dtype.asel}. a{. . r2. .sat vsub. c. r3.h1 }. . .sat vabsdiff. vsub. 2010 .atype. Perform scalar arithmetic operation with optional saturate. vsub vabsdiff vmin.h0.s32. sat. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vmin.atype.bsel}. with optional data merge vop.s32.b1.h0.atype. Video Instructions: vadd.sat vmin. and optional secondary arithmetic operation or subword data merge. tmp = | ta – tb |. c. b{.s32 }. isSigned(dtype). vsub. vabsdiff.b0. r3. tmp = MAX( ta. // optional secondary operation d = optMerge( dsel.sat} d. r2. vmax vadd. vmin.dsel .btype = { .u32. btype. // optional merge with c operand 142 January 24. Semantics // saturate. asel ). tmp.0.b0.b2. vadd. r1.add.h1. b{. . r2.s32.dtype.h0. a{. vmax }.btype{. r1.u32. vop.s32.b3. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.PTX ISA Version 2. r1. taking into account destination type and merge operations tmp = optSaturate( tmp.asel = .sat. tmp = ta – tb. vsub.s32. vmax require sm_20 or later. // 32-bit scalar operation. vabsdiff.h1.u32.bsel}.asel}. .b0.sat} d.vop .

c ).0.dtype.atype. with optional secondary operation vop. . a{. taking into account destination type and merge operations tmp = optSaturate( tmp.b0. with optional data merge vop. r3. . // optional secondary operation d = optMerge( dsel.u32{.s32. .dtype .u32{. tmp.b2.h0. switch ( vop ) { case vshl: tmp = ta << tb.min. d = optSecondaryOp( op2. . January 24.h1 }. .atype.wrap r1. if ( mode == . r1.dsel . vshl.mode .wrap }. isSigned(dtype). { . 2010 143 . vshr Syntax Integer byte/half-word/word left / right shift.mode} d.b1.u32{. a{. vop. asel ). r2.s32 }. c ).dsel. sat. Left shift fills with zero.u32. . c. . vshr vshl. b{. Signed shift fills with the sign bit.or zero-extend based on source operand type ta = partSelectSignExtend( a.atype. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .wrap ) tb = tb & 0x1f. c.sat}{.max }. // 32-bit scalar operation. .bsel}.mode} d. .bsel = { . bsel ). r2.asel}.clamp.bsel}.u32 vshr.h1. vshr: Shift a right by unsigned amount in b with optional saturate. dsel ). { . unsigned shift fills with zero.vop .dtype. and optional secondary arithmetic operation or subword data merge.Chapter 8.bsel}. r3.asel = .u32. vshl. b{. Video Instructions: vshl.b3.u32. if ( mode == .add. .op2 Description = = = = = { vshl. b{. Semantics // extract byte/half-word/word and sign. vshr }.op2 d.mode}.u32.dtype.u32. a{.atype = { .clamp . . atype. } // saturate.u32.asel}.sat}{.clamp && tb > 32 ) tb = 32. and optional secondary arithmetic operation or subword data merge. case vshr: tmp = ta >> tb. tmp. vshl: Shift a left by unsigned amount in b with optional saturate. // default is .sat}{. vshr require sm_20 or later. tb = partSelectSignExtend( b.asel}. // 32-bit scalar operation. Instruction Set Table 106.

. 2010 . Description Calculate (a*b) + c.btype = { .S32 // intermediate signed. and the operand negates. Source operands may not be negated in .scale = { . That is. 144 January 24. otherwise. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.s32 }. .dtype. “plus one” mode.sat}{. the intermediate result is signed. {-}c. .. Depending on the sign of the a and b operands. final signed (S32 * U32) . and scaling. final signed (S32 * S32) + S32 // intermediate signed.PTX ISA Version 2. final signed (S32 * S32) . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. The “plus one” mode (. with optional operand negates.shr7. final signed -(S32 * U32) + S32 // intermediate signed. Although PTX syntax allows separate negation of the a and b operands.btype{.b2.b1. . vmad. internally this is represented as negation of the product (a*b).S32 // intermediate signed.po{.h1 }. c. b{.bsel = { .po) computes (a*b) + c + 1.0 Table 107.asel = .h0. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. final signed (U32 * S32) + S32 // intermediate signed. // 32-bit scalar operation vmad. {-}a{. final signed -(S32 * S32) + S32 // intermediate signed. and zero-extended otherwise. Input c has the same sign as the intermediate result. .atype.atype = . final signed (U32 * U32) . .atype. . {-}b{.asel}.u32. final signed The intermediate result is optionally scaled via right-shift. The source operands support optional negation with some restrictions. this result is sign-extended if the final result is signed. final unsigned -(U32 * U32) + S32 // intermediate signed.dtype = . final signed (S32 * U32) + S32 // intermediate signed. . a{. The final result is unsigned if the intermediate result is unsigned and c is not negated.btype. which is used in computing averages.S32 // intermediate signed.scale} d. PTX allows negation of either (a*b) or c.po mode. final signed (U32 * S32) .asel}. .scale} d. final signed -(U32 * S32) + S32 // intermediate signed.bsel}. (a*b) is negated if and only if exactly one of a or b is negated. .bsel}.sat}{.b3.dtype.shr15 }.U32 // intermediate unsigned.b0.

shr15 r0.negate ) { c = ~c. r0.negate ^ b. S32_MAX.shr15: result = (tmp >> 15) & 0xffffffffffffffff.sat vmad. r2.0. r1. vmad. r2.u32. case .u32.negate ^ b.u32.u32.sat ) { if (signedFinal) result = CLAMP(result.h0. signedFinal = isSigned(atype) || isSigned(btype) || (a. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).negate ) { tmp = ~tmp. if ( .shr7: result = (tmp >> 7) & 0xffffffffffffffff.po ) { lsb = 1. S32_MIN). vmad requires sm_20 or later. tmp = tmp + c128 + lsb. switch( scale ) { case . U32_MIN). } if ( .Chapter 8. -r3. btype. else result = CLAMP(result. lsb = 0. January 24. Instruction Set Semantics // extract byte/half-word/word and sign. 2010 145 . atype.h0. U32_MAX. } else if ( c. asel ). r3.negate. tb = partSelectSignExtend( b. lsb = 1.negate) || c.s32.or zero-extend based on source operand type ta = partSelectSignExtend( a. tmp[127:0] = ta * tb. } else if ( a. r1. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32. bsel ). lsb = 1.

asel = . atype. // 32-bit scalar operation.atype.b1. . // optional secondary operation d = optMerge( dsel.le. with optional secondary operation vset. cmp ) ? 1 : 0.ne.u32.op2 Description = = = = .op2 d. { . . vset requires sm_20 or later. tmp = compare( ta. vset. b{.b0. asel ). . a{. .cmp d. .bsel}. tmp. with optional data merge vset. Semantics // extract byte/half-word/word and sign.u32. b{.h0.bsel}. { . 2010 . r3. tmp.dsel . a{.eq.0. tb.ge }. r3.atype .or zero-extend based on source operand type ta = partSelectSignExtend( a.h1 }.u32. bsel ). Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. c.0 Table 108. r2. . . b{. .h1. and therefore the c operand and final result are also unsigned.b2. . vset.asel}. d = optSecondaryOp( op2.lt vset.s32. . 146 January 24.bsel}.gt.atype. c ). r2. r1.cmp. . The intermediate result of the comparison is always unsigned. .cmp .lt.btype.b3.asel}.bsel = { .asel}.atype.btype = { . Compare input values using specified comparison.dsel. btype. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c.min.btype.PTX ISA Version 2.add. c ). a{. with optional secondary arithmetic operation or subword data merge. .cmp d. // 32-bit scalar operation. . .s32 }.max }.btype.ne r1. tb = partSelectSignExtend( b.u32.

Table 111. @p pmevent 1.Chapter 8. pmevent 7. trap Abort execution and generate an interrupt to the host CPU. trap. The relationship between events and counters is programmed via API calls from the host. Supported on all target architectures.4. 2010 147 . Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.0. brkpt Suspends execution Introduced in PTX ISA version 1. numbered 0 through 15. pmevent a. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Introduced in PTX ISA version 1. brkpt. Instruction Set 8.7. there are sixteen performance monitor events. Supported on all target architectures. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. brkpt. Notes PTX ISA Notes Target ISA Notes Examples Currently. trap. with index specified by immediate operand a. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.10. brkpt requires sm_11 or later. Table 110. Triggers one of a fixed number of performance monitor events. Introduced in PTX ISA version 1. January 24.0.

0 148 January 24. 2010 .PTX ISA Version 2.

…. %lanemask_lt. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_gt %clock. %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_le. %pm3 January 24.Chapter 9. Special Registers PTX includes a number of predefined. %clock64 %pm0. 2010 149 . read-only variables.

u32 %tid. mov.y * %ntid.x 0 <= %tid. the fourth element is unused and always returns zero.u32 %tid.sreg .0. per-thread special register initialized with the thread identifier within the CTA.z PTX ISA Notes Introduced in PTX ISA version 1.y == %tid.z < %ntid.u32 %r1. %tid.z == 1 in 2D CTAs.0 Table 112.x * %ntid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.%tid. Redefined as . It is guaranteed that: 0 <= %tid. The total number of threads in a CTA is (%ntid.%ntid.x.%tid.x.u16 %r2. mad.u32.%tid.x code Target ISA Notes Examples 150 January 24.u32 %r0.%h2.z to %r2 Table 113. Redefined as .x.x. 2010 . cvt.u16 %rh. CTA dimensions are non-zero. .0. // move tid. %ntid. mov.z == 0 in 1D CTAs.v4. Supported on all target architectures. The fourth element is unused and always returns zero. read-only. // compute unified thread id for 2D CTA mov.%tid.x.z. .u16 %rh. The number of threads in each dimension are specified by the predefined special register %ntid. // thread id vector // thread id components A predefined.v4.x code accessing 16-bit component of %tid mov. The %tid special register contains a 1D. %tid.0.u32 %ntid. // legacy PTX 1. the %tid value in unused dimensions is 0. %tid.z == 1 in 1D CTAs. . %tid component values range from 0 through %ntid–1 in each CTA dimension.y.%tid.u32 type in PTX 2.y < %ntid.y == %ntid.sreg .y 0 <= %tid.PTX ISA Version 2.0. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.sreg .%ntid. PTX ISA Notes Introduced in PTX ISA version 1.x. mov.%r0. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. %ntid.%h1.z == 0 in 2D CTAs.x to %rh Target ISA Notes Examples // legacy PTX 1. // zero-extend tid.y. 2D.v4 .u32 type in PTX 2.z. mov. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. Every thread in the CTA has a unique %tid. %ntid. or 3D vector to match the CTA shape.x. Supported on all target architectures.x < %ntid.u32 %ntid. read-only special register initialized with the number of thread ids in each CTA dimension.u32 %r0.u32 %h2. // CTA shape vector // CTA dimensions A predefined. .u32 %h1.y.sreg .z). %tid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.v4 . %ntid.z.

Table 115. due to rescheduling of threads following preemption. read-only special register that returns the thread’s warp identifier.Chapter 9. read-only special register that returns the maximum number of warp identifiers. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. but its value may change during execution. %nwarpid. Supported on all target architectures. A predefined. PTX ISA Notes Target ISA Notes Examples Table 116.3. Introduced in PTX ISA version 1.u32 %r. A predefined. mov. %nwarpid requires sm_20 or later. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. mov. The lane identifier ranges from zero to WARP_SZ-1. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Introduced in PTX ISA version 1.u32 %warpid. read-only special register that returns the thread’s lane within the warp. mov. Supported on all target architectures. e. Special Registers Table 114. %warpid. A predefined.u32 %r.sreg .u32 %laneid. . . Note that %warpid is volatile and returns the location of a thread at the moment when read.0. 2010 151 .3. . January 24. %laneid.u32 %nwarpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. The warp identifier will be the same for all threads within a single warp. Introduced in PTX ISA version 2.u32 %r. For this reason.g.sreg . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.sreg .

u32 %ctaid.%nctaid. // legacy PTX 1. The fourth element is unused and always returns zero. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.y.u16 %r0. The %ctaid special register contains a 1D.%ctaid. %ctaid. 2D.0.z < %nctaid. // CTA id vector // CTA id components A predefined. mov.0. mov. %rh.y. // legacy PTX 1.u32 mov.y < %nctaid.u32 %nctaid.x.y. read-only special register initialized with the number of CTAs in each grid dimension. It is guaranteed that: 1 <= %nctaid. with each element having a value of at least 1.sreg . Supported on all target architectures.536 PTX ISA Notes Introduced in PTX ISA version 1.x code Target ISA Notes Examples 152 January 24. Supported on all target architectures.x.z} < 65. read-only special register initialized with the CTA identifier within the CTA grid. depending on the shape and rank of the CTA grid. %ctaid.{x. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u32 %nctaid .u32 %ctaid.u32 mov. %rh.x.v4 . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.PTX ISA Version 2.sreg .z PTX ISA Notes Introduced in PTX ISA version 1. .v4.%nctaid. or 3D vector.z.sreg . // Grid shape vector // Grid dimensions A predefined.sreg . The fourth element is unused and always returns zero.y. Each vector element value is >= 0 and < 65535. Redefined as .z. .%nctaid.x.v4 . Redefined as .%ctaid. The %nctaid special register contains a 3D grid shape vector.%nctaid.u16 %r0. It is guaranteed that: 0 <= %ctaid.y 0 <= %ctaid.0.0 Table 117. 2010 . .u32 type in PTX 2. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.u32 type in PTX 2.x.v4.x code Target ISA Notes Examples Table 118.0.x 0 <= %ctaid.x < %nctaid.

Introduced in PTX ISA version 2. A predefined. A predefined. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.0. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.0.sreg .u32 %r. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Special Registers Table 119. 2010 153 . During execution. mov. The SM identifier numbering is not guaranteed to be contiguous. %nsmid requires sm_20 or later.u32 %nsmid. Notes PTX ISA Notes Target ISA Notes Examples Table 120. The SM identifier numbering is not guaranteed to be contiguous. %gridid. . PTX ISA Notes Target ISA Notes Examples January 24.3. so %nsmid may be larger than the physical number of SMs in the device. Introduced in PTX ISA version 1. %nsmid. Note that %smid is volatile and returns the location of a thread at the moment when read.u32 %r. The SM identifier ranges from 0 to %nsmid-1. read-only special register that returns the maximum number of SM identifiers. This variable provides the temporal grid launch number for this context. // initialized at grid launch A predefined. but its value may change during execution. where each launch starts a grid-of-CTAs. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.sreg .u32 %gridid. mov. e. %smid. Supported on all target architectures. due to rescheduling of threads following preemption. Introduced in PTX ISA version 1. . . mov.sreg .Chapter 9. PTX ISA Notes Target ISA Notes Examples Table 121. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. repeated launches of programs may occur.u32 %r.g. Supported on all target architectures. read-only special register initialized with the per-grid temporal grid identifier.u32 %smid.

sreg . A predefined.u32 %r.0.0 Table 122. %lanemask_eq. 2010 . 154 January 24. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_le. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later.0. A predefined.0. Introduced in PTX ISA version 2. mov.PTX ISA Version 2.u32 %r. Table 123. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_le. . A predefined. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. %lanemask_lt. %lanemask_eq requires sm_20 or later.sreg . mov. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. . %lanemask_le requires sm_20 or later. . mov.u32 %lanemask_lt.sreg .u32 %lanemask_eq.u32 %r. Table 124.

A predefined.u32 %lanemask_gt. Introduced in PTX ISA version 2.u32 %lanemask_ge.u32 %r. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. Table 126. January 24. %lanemask_gt. %lanemask_ge.sreg . . . mov. %lanemask_ge requires sm_20 or later. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. 2010 155 .Chapter 9. Introduced in PTX ISA version 2. mov. Special Registers Table 125.sreg . A predefined. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.0. %lanemask_gt requires sm_20 or later.0.

Table 129. %pm2.0. read-only 64-bit unsigned cycle counter. Introduced in PTX ISA version 1. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Special registers %pm0. mov. Supported on all target architectures. %clock64 requires sm_20 or later. %pm2. 2010 . Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.3.sreg . . read-only 32-bit unsigned cycle counter. . . Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Their behavior is currently undefined. %pm1. Introduced in PTX ISA version 2.%clock64. %pm3 %pm0.u32 %clock.u64 r1.PTX ISA Version 2.%pm0.u32 %pm0. %pm1. %pm1. %pm3.0. mov. Special Registers: %pm0.u64 %clock64.%clock. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.u32 r1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.sreg . %pm2. 156 January 24. …. and %pm3 are unsigned 32-bit read-only performance monitor counters. mov.0 Table 127.sreg . Supported on all target architectures. The lower 32-bits of %clock64 are identical to %clock. Introduced in PTX ISA version 1.u32 r1. Table 128.

version 2. and the target architecture for which the code was generated. 2010 157 . minor are integers Specifies the PTX language version number. .Chapter 10.4 January 24.version major. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directive.version .1.minor // major.version directives are allowed provided they match the original .version Syntax Description Semantics PTX version number. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. . . Supported on all target architectures. Each ptx file must begin with a .version directive.0 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version 1.0. Duplicate . PTX File Directives: .target Table 130. Directives 10. Increments to the major number indicate incompatible changes to PTX.version .

f64 instructions used. Requires map_f64_to_f32 if any . sm_13. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. PTX code generated for a given target can be run on later generation devices. In general.5.red}.f64 to .target . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.texref and . sm_10. The texturing mode is specified for an entire module and cannot be changed within the module. Each PTX file must begin with a . Target sm_20 Description Baseline feature set for sm_20 architecture. with only half being used by instructions converted from . sm_12. vote instructions.0 Table 131. Adds double-precision support.global. map_f64_to_f32 }.f64 instructions used. sm_11. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. brkpt instructions. including expanded rounding modifiers. A program with multiple .texref descriptor.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Therefore.f32. where each generation adds new features and retains all features of previous generations.target directive containing a target architecture and optional platform options. but subsequent . PTX File Directives: . Texturing mode: (default is . .target directive specifies a single target architecture.f64 instructions used.target Syntax Architecture and Platform target.version directive. A . and an error is generated if an unsupported feature is used.global. Note that .red}. 158 January 24.f64 storage remains as 64-bits.PTX ISA Version 2. texmode_independent. The following table summarizes the features in PTX that vary according to target architecture. Texturing mode introduced in PTX ISA version 1. Description Specifies the set of features in the target architecture for which the current ptx code was generated.texmode_unified) .shared. texmode_unified. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.red}. immediately followed by a .target directives can be used to change the set of target features allowed during parsing. Adds {atom. Introduced in PTX ISA version 1. PTX features are checked against the specified target architecture. Adds {atom.texmode_independent texture and sampler information is bound together and accessed via a single . Disallows use of map_f64_to_f32. Requires map_f64_to_f32 if any . Supported on all target architectures. generations of SM architectures follow an “onion layer” model.0.texmode_unified . 64-bit {atom. 2010 . texture and sampler information is referenced with independent .samplerref descriptors. Requires map_f64_to_f32 if any .

texmode_independent January 24.target sm_10 // baseline target architecture . 2010 159 .Chapter 10.target sm_20. Directives Examples .target sm_13 // supports double-precision .

entry kernel-name kernel-body Defines a kernel entry point name. store.param instructions. PTX ISA Notes For PTX ISA version 1. Kernel and Function Directives: . For PTX ISA versions 1.param. .entry . 2010 .texref.param .0 through 1. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.2.samplerref.3. and .b32 %r1. … } .b32 z ) Target ISA Notes Examples [x].b32 y.param. .entry cta_fft .param space memory and are listed within an optional parenthesized parameter list.param . Parameters may be referenced by name within the kernel body and loaded into registers using ld. Supported on all target architectures.b32 x.4 and later.0 10.g. . and query instructions and cannot be accessed via ld. At kernel launch. [y].param. %nctaid. %ntid.entry kernel-name ( param-list ) kernel-body . .entry Syntax Description Kernel entry point and body. and body for the kernel function.surfref variables may be passed as parameters.reg . parameter variables are declared in the kernel parameter list.b32 %r2. Parameters are passed via . ld. the kernel dimensions and properties are established and made available via special registers. parameter variables are declared in the kernel body. The shape and size of the CTA executing the kernel are available in special registers. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.b32 %r<99>. .param { . e.4. opaque .b32 %r3.param instructions. ld.0 through 1.5 and later. parameters. Semantics Specify the entry point for a kernel program.PTX ISA Version 2. These parameters can only be referenced by name within texture and surface load. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.func Table 132.entry . 160 January 24. with optional parameters. etc.entry filter ( . In addition to normal parameters. ld. . [z].

param state space. there is no stack.param space are accessed using ld. A . val1).result.func fname (param-list) function-body . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Variadic functions are represented using ellipsis following the last fixed argument. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. The parameter lists define locally-scoped variables in the function body. if any. other code.reg . The implementation of parameter passing is left to the optimizing translator. Parameter passing is call-by-value. foo.x code.reg . (val0.2 for a description of variadic functions.func (.f64 dbl) { . PTX ISA 2. implements an ABI with stack. Parameters in . parameters must be in the register state space. .func (ret-param) fname (param-list) function-body Defines a function. Parameters in register state space may be referenced directly within instructions in the function body.0 with target sm_20 allows parameters in the .param instructions in the body.reg .func definition with no body provides a function prototype.0. 2010 161 .func . . and supports recursion. dbl.b32 N. } … call (fooval). including input and return parameters and optional function body.b32 localVar.param and st.func fname function-body .0 with target sm_20 supports at most one return value. mov. which may use a combination of registers and stack locations to pass parameters.b32 rval) foo (. … Description // return value in fooval January 24. Variadic functions are currently unimplemented.Chapter 10. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 rval. Directives Table 133. . Kernel and Function Directives: . … use N. and recursion is illegal. ret. Supported on all target architectures. Parameters must be base types in either the register or parameter state space.func Syntax Function definition. Release Notes For PTX ISA version 1.reg . PTX 2.

for example.pragma directives may appear at module (file) scope. at entry-scope.PTX ISA Version 2. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.maxntid and .maxntid . to throttle the resource requirements (e. Note that . the .maxntid directive specifies the maximum number of threads in a thread block (CTA). Performance-Tuning Directives To provide a mechanism for low-level performance tuning. the . or as statements within a kernel or device function body. 2010 .minnctapersm .entry directive and its body. A general . and the . The . The directive passes a list of strings to the backend.maxnreg.3. These can be used. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.pragma The .maxnctapersm (deprecated) . .0 10. The directives take precedence over any module-level constraints passed to the optimizing backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. which pass information to the backend optimizing compiler. 162 January 24.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. The interpretation of . PTX supports the following directives.maxnreg .minnctapersm directives may be applied per-entry and must appear between an . Currently.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). . and the strings have no semantics within the PTX virtual machine model. registers) to increase total thread count and provide a greater opportunity to hide memory latency.g.pragma directive is supported for passing information to the PTX backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. and .maxntid.

maxntid and .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.16.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.3. . 2010 163 . The actual number of registers used may be less. Performance-Tuning Directives: .maxntid nx. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. This maximum is specified by giving the maximum extent of each dimention of the 1D. Supported on all target architectures.maxntid nx.maxntid nx .entry foo .maxntid .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. . The compiler guarantees that this limit will not be exceeded. ny.maxnreg . or the maximum number of registers may be further constrained by .3.maxntid 256 . for example. . .maxctapersm. Exceeding any of these limits results in a runtime error or kernel launch failure. Performance-Tuning Directives: . or 3D CTA.entry bar . Directives Table 134. The maximum number of threads is the product of the maximum extent in each dimension.maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg n Declare the maximum number of registers per thread in a CTA. ny .entry foo . Supported on all target architectures. nz Declare the maximum number of threads in the thread block (CTA). Introduced in PTX ISA version 1. 2D.Chapter 10. the backend may be able to compile to fewer registers.maxntid 16. Introduced in PTX ISA version 1.

maxnctapersm generally need . if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxntid to be specified as well.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid 256 . For this reason. Optimizations based on . Supported on all target architectures. . .3. .minnctapersm in PTX ISA version 2. Performance-Tuning Directives: .minnctapersm generally need . Introduced in PTX ISA version 1.maxnctapersm (deprecated) .maxnctapersm has been renamed to .maxntid 256 .maxnctapersm.entry foo . Performance-Tuning Directives: .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Optimizations based on . Introduced in PTX ISA version 2. additional CTAs may be mapped to a single multiprocessor.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. .entry foo . Deprecated in PTX ISA version 2. However.0 Table 136. Supported on all target architectures.minnctapersm 4 { … } 164 January 24.maxntid and .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. 2010 .0 as a replacement for .0.maxntid to be specified as well. .PTX ISA Version 2.0. The optimizing backend compiler uses .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.

pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas.Chapter 10. at entry-scope. 2010 165 .pragma list-of-strings . Directives Table 138. or at statementlevel. entry-scoped. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma . The . Introduced in PTX ISA version 2.pragma Syntax Description Pass directives to PTX backend compiler. Supported on all target architectures. Performance-Tuning Directives: . The interpretation of . { … } January 24. or statement-level directives to the PTX backend compiler.0.pragma “nounroll”.entry foo .pragma directive may occur at module-scope. . . Pass module-scoped.pragma directive strings is implementation-specific and has no impact on PTX semantics.

debug_pubnames. 0x00 .4byte 0x000006b5. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.4.0. 0x00.0 10.file .section directive is new in PTX ISA verison 2. 0x00000364.4byte . 0x6150736f. The @@DWARF syntax is deprecated as of PTX version 2. Introduced in PTX ISA version 1. 0x61395a5f.2.232-1] . “”. 2010 . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .debug_info .loc The . 0x00 166 January 24. @progbits .0 but is supported for legacy PTX version 1. 0x00.byte 0x2b. 0x5f736f63 .byte 0x00. 0x00..0 and replaces the @@DWARF syntax.x code. 0x00.byte byte-list // comma-separated hexadecimal byte values ..section . Supported on all target architectures.section directive.quad int64-list // comma-separated hexadecimal integers in range [0. 0x02.section .PTX ISA Version 2.264-1] .4byte 0x6e69616d. Deprecated as of PTX 2. 0x00. @@DWARF dwarf-string dwarf-string may have one of the .4byte label . replaced by . 0x63613031. 0x736d6172 . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Table 139.4byte int32-list // comma-separated hexadecimal integers in range [0.

. . 0x00.264-1] .b64 int64-list // comma-separated list of integers in range [0.section .loc .b32 label .232-1] . Supported on all target architectures.b8 0x2b. .0. 0x00.Chapter 10. Source file information.b32 0x6e69616d. } 0x02. .b32 int32-list // comma-separated list of integers in range [0. 0x00. 2010 167 . Supported on all target architectures. . 0x00 0x61395a5f.b32 0x000006b5.255] .debug_info .file . replaces @@DWARF syntax.b8 byte-list // comma-separated list of integers in range [0. .b32 .0. 0x00. Source file location.0. Directives Table 140. 0x5f736f63 0x6150736f. 0x00.. Debugging Directives: . Debugging Directives: .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.section Syntax PTX section definition. Supported on all target architectures..b8 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. ..section .file filename Table 142. 0x736d6172 0x00 Table 141. 0x63613031. 0x00.section section_name { dwarf-lines } dwarf-lines have the following formats: . Debugging Directives: .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00000364.debug_pubnames { .loc line_number January 24.

.0 10.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures. // foo is defined in another module Table 144. Supported on all target architectures.b32 foo.extern .global . // foo will be externally visible 168 January 24.0. .6.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern identifier Declares identifier to be defined externally. Linking Directives: .extern .visible . . .global .visible identifier Declares identifier to be externally visible.b32 foo.PTX ISA Version 2.visible .visible Table 143. Linking Directives: . Linking Directives . 2010 .extern .0. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.

CUDA Release CUDA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2. The release history is as follows.3 PTX ISA 1.0 CUDA 2.3 driver r190 CUDA 3.0 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.0 driver r195 PTX ISA Version PTX ISA 1. 2010 169 .5 PTX ISA 2.0 CUDA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.4 PTX ISA 1.1 PTX ISA 1.1 CUDA 2.1 CUDA 2.Chapter 11.0.0 January 24.2 PTX ISA 1.2 CUDA 2.

A single-precision fused multiply-add (fma) instruction has been added.1. New Features 11.0 11. The changes from PTX ISA 1.rm and . mad.f32 for sm_20 targets.f32 require a rounding modifier for sm_20 targets. 2010 .x code and sm_1x targets. Changes in Version 2. while maximizing backward compatibility with legacy PTX 1.rp rounding modifiers for sm_20 targets.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2. and sqrt with IEEE 754 compliant rounding have been added.1.and double-precision div. The goal is to achieve IEEE 754 compliance wherever possible.1.ftz and .f32.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices. and mul now support .1.rn. Single-precision add. The mad.1. fma.sat modifiers.PTX ISA Version 2. Both fma.f32 and mad.f32 requires sm_20. sub. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Single. These are indicated by the use of a rounding modifier and require sm_20.f32 instruction also supports .0 for sm_20 targets. The mad. • • • • • 170 January 24.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. The .ftz modifier may be used to enforce backward compatibility with sm_1x.1. rcp. The fma. Instructions testp and copysign have been added.0 11.f32 maps to fma.

membar. A system-level membar instruction. atom.3.sys.ballot. suld. Instructions {atom. Instruction sust now supports formatted surface stores. prefetch.minnctapersm to better match its behavior and usage. cvta. st. The . A new directive.f32 have been implemented.lt. has been added. has been added. st. Video instructions (includes prmt) have been added.le. clz. . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. brev. ldu. A “count leading zeros” instruction. .1. A “find leading non-sign bit” instruction. bfind. %clock64. and shared addresses to generic address and vice-versa has been added. 2010 171 . Bit field extract and insert instructions. January 24.add. bfe and bfi. Cache operations have been added to instructions ld. Instructions prefetch and prefetchu have also been added.b32. has been added.2.g.1. local. has been added.gt} have been added.section. 11.1.pred have been added.u32 and bar. ldu. for prefetching to specified level of memory hierarchy.ge. Surface instructions support additional .maxnctapersm directive was deprecated and replaced with . Other new features Instructions ld.popc. The bar instruction has been extended as follows: • • • A bar. %lanemask_{eq.arrive instruction has been added. prefetchu.zero. isspacep. has been added. A “vote ballot” instruction. A “population count” instruction. has been added. Instruction cvta for converting global. popc. Instructions {atom. A “bit reversal” instruction.clamp and .1.red. e. Instructions bar. bar now supports optional thread count and register operands. New instructions A “load uniform” instruction. and red now support generic addressing.red. New special registers %nsmid.{and.shared have been extended to handle 64-bit data types for sm_20 targets. has been added. have been added.red}. vote.or}. Release Notes 11. and sust.red}.Chapter 11.clamp modifiers.

max} are not implemented. To maintain compatibility with legacy PTX code. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. . 172 January 24. if .5 and later. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.f32. See individual instruction descriptions for details.1.{min. Support for variadic functions and alloca are unimplemented.2.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.p.version is 1. 2010 .ftz (and cvt for . {atom.PTX ISA Version 2. the correct number is sixteen.{u32.0 11.ftz for PTX ISA versions 1. has been fixed. where . The underlying.f32} atom. In PTX version 1.5. stack-based ABI is unimplemented. Formatted surface store with . or .u32. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.red}. cvt.3.1. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. Formatted surface load is unimplemented. Instruction bra.4 or earlier.s32.4 and earlier.s32.p sust.f32 type is unimplemented. call suld. 11.target sm_1x. Semantic Changes and Clarifications The errata in cvt.

entry foo (…) . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. disables unrolling of0 the loop for which the current block is the loop header.0. … @p bra L1_end.pragma. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma “nounroll”. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. including loops preceding the . { … } // do not unroll any loop in this function . and statement levels. Supported only for sm_20 targets. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. L1_end: … } // do not unroll this loop January 24. .func bar (…) { … L1_head: .pragma strings defined by ptxas.pragma “nounroll”. entry-function. . Table 145. Descriptions of . L1_body: … L1_continue: bra L1_head. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Note that in order to have the desired effect at statement level. 2010 173 . disables unrolling for all loops in the entry function body. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Ignored for sm_1x targets. The “nounroll” pragma is allowed at module.pragma “nounroll”.Appendix A.pragma Strings This section describes the .

2010 .PTX ISA Version 2.0 174 January 24.

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