NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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........................................................... 30 Shared State Space..................................................... 6............... 2010 ....4.........3.......................2....................... Sampler................ 27 5...4............................ 5..................................1..................... 6...................7........ Arrays................................................................................................ 41 Destination Operands ...........................5....2... 5.... Types .................................................................................................... Summary of Constant Expression Evaluation Rules . Operand Type Information ..................1..................................................... Texture....................1.......................................................2..... 5.............1.............. and Surface Types ........3............................................ 6......... State Spaces. 5.......... 5.................................. 25 Chapter 5.................1............. 47 Chapter 7.2..................2............................2..................................4...................................... 29 Local State Space ............................ Type Conversion..................................................... 42 Arrays as Operands .................1............................1........................................ 33 Restricted Use of Sub-Word Sizes ................................................................4... 28 Constant State Space .......1........................................................................................................4......................... 6...... 6.................2...................... 44 Rounding Modifiers ......5..... 29 Parameter State Space . 44 Scalar Conversions ...................... 42 Addresses as Operands ..................... 32 Texture State Space (deprecated) ............................8.......... 43 Vectors as Operands ...................2....................................PTX ISA Version 2.............6....4....1........................... 5..........1....1........... 46 6.......................... 38 Alignment ..........4..................4..................................................................................6....................................... 37 Array Declarations ............. 6................................................................ 41 Source Operands...... and Vectors ...................................... 5......... 43 Labels and Function Names as Operands ............... 5..................1.......................... State Spaces .................................................1.. 6........4......... 43 6......... 29 Global State Space ........ 6......1............................................... 34 Variables ......................... Function declarations and definitions ................... 37 Vectors ...........................................................................................5............... 32 5..... 49 ii January 24............3................ 49 7... 5................................................4............. 5................................ 41 6...........................4................5.... 5..................................................... 41 Using Addresses............................................................................................. 39 5............................................................................. Types... Operand Costs ......................... 5............4...........1.. Instruction Operands.........0 4....... 27 Register State Space . 39 Parameterized Variable Names .............................................. 5...........5.....3....... Chapter 6.........3............ 38 Initializers ............................ 5......................................................................................................... and Variables ...............................4..........................................................4..................................................................................6................................ 5...................4.....................6.......... 28 Special Register State Space . 5.. 37 Variable Declarations ......................................................2..................... Abstracting the ABI ....................................................... 6.......................................................1................................. 33 5..............................5............. 33 Fundamental Types ...............

........................ 62 Machine-Specific Semantics of 16-bit Code ........................................................ 8.....................1..................................................................1....................................................................................................................................... 10............... 8... 57 Manipulating Predicates ........ Release Notes ................. 8.2.................................................................................... 81 Comparison and Selection Instructions ....................................................................... 132 Video Instructions .................1............................. 157 10........................................................................................1............... 10......................................... 172 Unimplemented Features Remaining ......... 62 Semantics ........................ 11.. 55 PTX Instructions ..3............................ 7.................0 ......... 162 Debugging Directives ..........7....6.................... 62 8..........................................8........................3......... 157 Specifying Kernel Entry Points and Functions .................................................................2........4. 160 Performance-Tuning Directives ................ 55 Predicated Execution .........7......... 147 8............................................ 129 Parallel Synchronization and Communication Instructions ................. 11........ 52 Variadic functions ......................7..........................................7...................................... 8................ Divergence of Threads in Control Constructs .. Chapter 9. 8....1.......1................7. Changes from PTX 1......3............7....................................... Instructions ............. 8.............................. 10.......7............................. 63 Floating-Point Instructions ................. 10...1..................................... 166 Linking Directives ...........................................................................................................................................7...3................................................................................................ 8..... 8... 8.......... PTX Version and Target Directives ........2................... 59 Operand Size Exceeding Instruction-Type Size ................................4.................3......................................... Format and Semantics of Instruction Descriptions ..... 63 Integer Arithmetic Instructions ..7............................................................x ...........................4....1.............. 54 Chapter 8......................2. Directives ..................... 8............. 149 Chapter 10.................. 8...... Instruction Set .. 8..... Changes in Version 2. Type Information for Instructions and Operands . 168 Chapter 11.................... Special Registers .............................. 122 Control Flow Instructions ....... 104 Data Movement and Conversion Instructions ................3.......................................1................ 53 Alloca ... 60 8.... 8....................................................1.........................................................................................................10......................... 100 Logic and Shift Instructions ........................... 170 Semantic Changes and Clarifications ...................................... 108 Texture and Surface Instructions .................................................4... 7...... 56 Comparisons ...............9....................... 8....................5.....3.. 172 January 24.......... 58 8.......................6.........7................................................................................2...................................5........................................2................................1..................................1.......................................................................................6.......1............................... 170 New Features ..............6....................................................... 140 Miscellaneous Instructions............................................. 11............................. 8...............7..........7...... 169 11...................... 2010 iii .............. 55 8..............7..................................................... 8..........

0 Appendix A....................pragma Strings..................... 2010 .PTX ISA Version 2.................. Descriptions of ..... 173 iv January 24...

................... Table 16........................... 57 Floating-Point Comparison Operators Accepting NaN ............................. Table 26..................... 33 Opaque Type Fields in Unified Texture Mode ........................................................................ 46 Integer Rounding Modifiers ............................................................ 58 Type Checking Rules .............................. 67 Integer Arithmetic Instructions: mad ........... Table 4.... 66 Integer Arithmetic Instructions: mul .......................................... 66 Integer Arithmetic Instructions: subc ................................ Table 29...................................................... Table 7.......... 35 Opaque Type Fields in Independent Texture Mode ......................... 68 Integer Arithmetic Instructions: mul24 ..... 46 Cost Estimates for Accessing State-Spaces .................... 64 Integer Arithmetic Instructions: add.......... 65 Integer Arithmetic Instructions: addc ..................... 61 Integer Arithmetic Instructions: add ....... Table 8.......................................................................................................................... 25 State Spaces ...................... 19 Predefined Identifiers ................. 58 Floating-Point Comparison Operators Testing for NaN ........................................................... Table 19.................... Table 21..................... Table 9................................................................ 70 Integer Arithmetic Instructions: sad .................................................................................. Table 2............................ 65 Integer Arithmetic Instructions: sub... 20 Operator Precedence ............. Table 23........... 64 Integer Arithmetic Instructions: sub .............................. 57 Floating-Point Comparison Operators ................ 35 Convert Instruction Precision and Format ............................................................................................................... 60 Relaxed Type-checking Rules for Destination Operands..................................... 69 Integer Arithmetic Instructions: mad24 .................................. Table 10.............cc .......... 47 Operators for Signed Integer.................cc ......... Table 25........... Table 30.................................................. Table 12..................... Table 13.. 23 Constant Expression Evaluation Rules ............................................... Table 27............................ Table 14................................................... 59 Relaxed Type-checking Rules for Source Operands .......................................... 27 Properties of State Spaces .................................................... and Bit-Size Types ................................................ Table 6... 18 Reserved Instruction Keywords ...... Table 20..................... Table 32........................................................................................................................... Table 17............................................................................... 28 Fundamental Type Specifiers ........ Table 18................................................. 71 January 24..................................... 2010 v . Table 15.... Table 3................... PTX Directives ....................................................................................................... 45 Floating-Point Rounding Modifiers ............................ Unsigned Integer......................................................... Table 22.... Table 31..................List of Tables Table 1........................................... Table 24................................. Table 5.......................... Table 28................................................ Table 11..............................

................................................................ Table 55............................ Table 61................................... 72 Integer Arithmetic Instructions: neg ............................ Table 62........... Integer Arithmetic Instructions: div ....... Table 38........................................................................................................... Table 58......... Table 46...................................................................................................................................... 102 Comparison and Selection Instructions: selp .. 83 Floating-Point Instructions: add ....................................................................... Table 60....... Table 39........................................... 74 Integer Arithmetic Instructions: bfind ................................................................. Table 69......................... Table 66...................................................................................................................................................................... Table 35............................................ 74 Integer Arithmetic Instructions: clz .................................... Table 53.......... 73 Integer Arithmetic Instructions: max .......................................................................... Table 45................ 95 Floating-Point Instructions: sin ............................................. Table 57............... Table 63........................................................................................................... 87 Floating-Point Instructions: mad .......... 103 Comparison and Selection Instructions: slct ................ Table 59........................................................................ 71 Integer Arithmetic Instructions: abs ......................................... Table 47...................... Table 41............... Table 52.........PTX ISA Version 2........ 76 Integer Arithmetic Instructions: bfe ....................................... 75 Integer Arithmetic Instructions: brev .......................................... 84 Floating-Point Instructions: sub ..................... 91 Floating-Point Instructions: neg ............................................................................ Table 54.................................................................................................................................. Table 65........ 91 Floating-Point Instructions: min .... 92 Floating-Point Instructions: rcp .......... Table 50....................................................... 78 Integer Arithmetic Instructions: prmt ........... Table 48. Table 51............... Table 42................. Table 40..... 83 Floating-Point Instructions: copysign ........................ Table 64...................... 94 Floating-Point Instructions: rsqrt ... 90 Floating-Point Instructions: abs ......................................................................................... 73 Integer Arithmetic Instructions: popc ....................... 85 Floating-Point Instructions: mul ..0 Table 33....................................... 92 Floating-Point Instructions: max ............. Table 37............. 103 vi January 24.......................... 101 Comparison and Selection Instructions: setp ........................... Table 43.............. 96 Floating-Point Instructions: cos ....................................................................................................... 77 Integer Arithmetic Instructions: bfi ................. 82 Floating-Point Instructions: testp ........ 93 Floating-Point Instructions: sqrt ............. Table 34............. Table 36............................................. Table 67..... 97 Floating-Point Instructions: lg2 ....................... 99 Comparison and Selection Instructions: set ..................................................................... Table 68.................................. 88 Floating-Point Instructions: div .............................................................................................................................................. 72 Integer Arithmetic Instructions: min .... 71 Integer Arithmetic Instructions: rem ............ 2010 ........................................ Table 49..... Table 44............................................... 86 Floating-Point Instructions: fma .............................................. Table 56............................................. 98 Floating-Point Instructions: ex2 ..................................................................... 79 Summary of Floating-Point Instructions .

........................ Table 101... Table 82........ Table 93.... 118 Data Movement and Conversion Instructions: isspacep .................................................. Table 90.......... Table 71.... Table 83........................... vmin...... Table 76............................ vshr ....................... Table 88.................................. Table 79......................................................... Table 99.................................. 115 Data Movement and Conversion Instructions: st ........... 116 Data Movement and Conversion Instructions: prefetch.. 109 Cache Operators for Memory Store Instructions ...................................... 142 Video Instructions: vshl.................... 120 Texture and Surface Instructions: tex ............ 105 Logic and Shift Instructions: xor .................................. 107 Cache Operators for Memory Load Instructions ............................................ Table 77........................................ 111 Data Movement and Conversion Instructions: mov .................................... 129 Control Flow Instructions: @ .............. 128 Control Flow Instructions: { } ................................................ Table 103........................... 137 Parallel Synchronization and Communication Instructions: vote ....... 110 Data Movement and Conversion Instructions: mov ............................................ Table 75.......................................................... Table 80.................................. 105 Logic and Shift Instructions: or ....................... 112 Data Movement and Conversion Instructions: ld ...................................................................................... Table 78......... Table 104... Table 72............................................. 129 Control Flow Instructions: bra .... 139 Video Instructions: vadd... 126 Texture and Surface Instructions: sured.. Table 102.......................... 119 Data Movement and Conversion Instructions: cvt .. Table 100.................. 130 Control Flow Instructions: ret . vabsdiff. 2010 vii ........ 133 Parallel Synchronization and Communication Instructions: membar ............................... 131 Parallel Synchronization and Communication Instructions: bar ......................................... 106 Logic and Shift Instructions: shl ................ Table 73.. Table 87...Table 70.. Table 95...................... Table 105................ Table 96.......................................... 123 Texture and Surface Instructions: txq ................................................ prefetchu ...... 135 Parallel Synchronization and Communication Instructions: red ...................................................................................... Table 86................................................................................. Table 85............................................ Table 98......................................................... Table 94.................................. Table 84....................................................................................................................................................... 113 Data Movement and Conversion Instructions: ldu ... Table 91.......................................................... 143 January 24...... 127 Texture and Surface Instructions: suq ......................................... 125 Texture and Surface Instructions: sust ................................... Table 74...... 134 Parallel Synchronization and Communication Instructions: atom ..................... Table 89......... 131 Control Flow Instructions: exit ........................ 124 Texture and Surface Instructions: suld ....... Logic and Shift Instructions: and ................................ 107 Logic and Shift Instructions: shr ........................................................... 106 Logic and Shift Instructions: cnot ...................... 119 Data Movement and Conversion Instructions: cvta ................................ Table 106.............. Table 97........................ Table 92.... vmax .......................................... Table 81.............................................. 106 Logic and Shift Instructions: not .... 130 Control Flow Instructions: call ........................................... vsub...

....... Table 140........... 147 Miscellaneous Instructions: pmevent. Table 116.............. Table 128....................... Table 121......................................................................................................................................... Table 129.maxnreg ........ 152 Special Registers: %smid ............... 164 Performance-Tuning Directives: ..................... 147 Miscellaneous Instructions: brkpt ....... Table 119.................................................................................... 166 Debugging Directives: .......... Table 127. 147 Special Registers: %tid ..........................................................pragma .................................................... Table 117...................................................... Table 115........................................................................... Table 109....... Table 136......... Table 135............. 152 Special Registers: %nctaid .................................................................. 157 PTX File Directives: ........................................ %pm3 ..................................minnctapersm . Table 113................ 164 Performance-Tuning Directives: ................................ 154 Special Registers: %lanemask_le ............................. 156 Special Registers: %clock64 ................................................................................... 153 Special Registers: %lanemask_eq ......... 154 Special Registers: %lanemask_lt ..................... Table 108............. 165 Debugging Directives: @@DWARF ......................................................... %pm2................................................... Table 118......... 153 Special Registers: %gridid ................................ 161 Performance-Tuning Directives: ........ 167 Debugging Directives: ....................................................................................... Table 123.................................. 156 PTX File Directives: ................ Table 138...................................... Table 120..................................................................... 158 Kernel and Function Directives: ............................................................................................ Table 133...... 156 Special Registers: %pm0............ Table 139.................. 167 Debugging Directives: .. 163 Performance-Tuning Directives: ........................................................ Table 122......................................................................... %pm1........................ 150 Special Registers: %ntid ............... 163 Performance-Tuning Directives: .............. 155 Special Registers: %lanemask_gt . Table 141....... Table 131................... 155 Special Registers: %clock .. 154 Special Registers: %lanemask_ge ........... Table 112....................... 151 Special Registers: %warpid ....................................... Table 124. Table 132...... 144 Video Instructions: vset.................... Table 125.......................section ................................func ............................... Table 114......... 160 Kernel and Function Directives: ............... Table 137...................................... Table 134................................................. 2010 ................PTX ISA Version 2........................... 151 Special Registers: %ctaid ......................................................... 146 Miscellaneous Instructions: trap .extern..................... 150 Special Registers: %laneid ..........loc ............................................................................................ 167 Linking Directives: ...... Table 142......................version........................entry................................................................. Table 110........................target .. Table 126....................................................... Table 130...........................................................maxntid .................................... 153 Special Registers: %nsmid ...file ........... 151 Special Registers: %nwarpid ...................................................................... 168 viii January 24............................................................................................................... Table 143....0 Table 107.... Table 111..... Video Instructions: vmad .......maxnctapersm (deprecated) .................

.visible............................................................. 173 January 24.............................. Linking Directives: ................ 168 Pragma Strings: “nounroll” ........................ 2010 ix ... Table 145...Table 144.................................

2010 .PTX ISA Version 2.0 x January 24.

many-core processor with tremendous computational horsepower and very high memory bandwidth.2. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. and pattern recognition can map image blocks and pixels to parallel processing threads. and because it is executed on many data elements and has high arithmetic intensity. 1. Similarly. PTX exposes the GPU as a data-parallel computing device. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. the memory access latency can be hidden with calculations instead of big data caches. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Introduction This document describes PTX. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. PTX programs are translated at install time to the target hardware instruction set. stereo vision. which are optimized for and translated to native target-architecture instructions. video encoding and decoding. Data-parallel processing maps data elements to parallel processing threads. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations.1. PTX defines a virtual machine and ISA for general purpose parallel thread execution. there is a lower requirement for sophisticated flow control. 1. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. 2010 1 . image and media processing applications such as post-processing of rendered images. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. high-definition 3D graphics.Chapter 1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). image scaling. multithreaded. from general signal processing or physics simulation to computational finance or computational biology. In fact. January 24. Because the same program is executed for each data element. the programmable GPU has evolved into a highly parallel.

1. 2010 . When code compiled for sm_1x is executed on sm_20 devices.ftz and .3. A single-precision fused multiply-add (fma) instruction has been added. The main areas of change in PTX 2.0 PTX ISA Version 2.x.ftz) modifier may be used to enforce backward compatibility with sm_1x.f32 require a rounding modifier for sm_20 targets. Single-precision add.f32 maps to fma. memory. fma. • • • 2 January 24. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.f32 instruction also supports . sub.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32. addition of generic addressing to facilitate the use of general-purpose pointers.f32 requires sm_20.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.rp rounding modifiers for sm_20 targets. 1. reduction. Improved Floating-Point Support A main area of change in PTX 2. and video instructions. Legacy PTX 1. Provide a common source-level ISA for optimizing code generators and translators. The mad.rm and .PTX ISA Version 2.x features are supported on the new sm_20 target. performance kernels. Both fma. Provide a code distribution ISA for application and middleware developers. The fma. Facilitate hand-coding of libraries.0 is a superset of PTX 1. including integer. barrier.0 is in improved support for the IEEE 754 floating-point standard.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Instructions marked with .sat modifiers. atomic. The changes from PTX ISA 1. Provide a machine-independent ISA for C/C++ and other compilers to target.1. PTX ISA Version 2. and all PTX 1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. and the introduction of many new instructions. mad.f32 for sm_20 targets.0 are improved support for IEEE 754 floating-point operations.x code will continue to run on sm_1x targets as well. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Most of the new features require a sm_20 target.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. A “flush-to-zero” (.rn. The mad. PTX 2. surface. and architecture tests. and mul now support .f32 and mad. Achieve performance in compiled applications comparable to native GPU performance.3. which map PTX to specific target machines.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.

e.Chapter 1. atom. an address that is the same across all threads in a warp. Surface Instructions • • Instruction sust now supports formatted surface stores.and double-precision div. and Application Binary Interface (ABI). e. PTX 2.0. • Taken as a whole. . See Section 7 for details of the function definition and call syntax needed to abstract the ABI. 1. these changes bring PTX 2. Surface instructions support additional clamp modifiers. allowing memory instructions to access these spaces without needing to specify the state space. Instruction cvta for converting global. instructions ld. stack-based ABI. and directives are introduced in PTX 2. st. so recursion is not yet supported.g.0 closer to full compliance with the IEEE 754 standard. 1. prefetch. A new cvta instruction has been added to convert global.clamp and . i. isspacep. suld.3.2. and red now support generic addressing. prefetchu. and shared addresses to generic address and vice-versa has been added. In PTX 2.3. st. stack layout. and vice versa. 2010 3 .zero. Generic Addressing Another major change is the addition of generic addressing.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.0. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. ldu. Generic addressing unifies the global. Instructions prefetch and prefetchu have been added. 1. rcp. Support for an Application Binary Interface Rather than expose details of a particular calling convention.3. cvta. January 24. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Instructions testp and copysign have been added. Introduction • Single. and sust. local. These are indicated by the use of a rounding modifier and require sm_20.3.4. and shared addresses to generic addresses. special registers. and shared state spaces.. NOTE: The current version of PTX does not implement the underlying. local. local. for prefetching to specified level of memory hierarchy. Cache operations have been added to instructions ld. New Instructions The following new instructions. and sqrt with IEEE 754 compliant rounding have been added.

pred have been added.red. 4 January 24.section. has been added.popc. has been added.f32 have been added.u32 and bar. Instructions {atom. A “vote ballot” instruction.arrive instruction has been added. Reduction.red. .0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. A new directive. 2010 . vote.red}.red}. bfi bit field extract and insert popc clz Atomic. membar. Other Extensions • • • Video instructions (includes prmt) have been added.b32. and Vote Instructions • • • New atomic and reduction instructions {atom.or}. %lanemask_{eq.sys.PTX ISA Version 2. Instructions bar.shared have been extended to handle 64-bit data types for sm_20 targets.ballot. %clock64. Barrier Instructions • • A system-level membar instruction.{and. New special registers %nsmid. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.lt.gt} have been added.le.add. bar now supports an optional thread count and register operands. A bar.ge.

Chapter 6 describes instruction operands.Chapter 1. and variable declarations. Chapter 10 lists the assembly directives supported in PTX. Chapter 3 gives an overview of the PTX virtual machine model. types. Chapter 4 describes the basic syntax of the PTX language. Chapter 5 describes state spaces.4.0. 2010 5 . Chapter 7 describes the function and call syntax. and PTX support for abstracting the Application Binary Interface (ABI). The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. January 24. Chapter 9 lists special registers. Introduction 1. Chapter 8 describes the instruction set. calling convention. Chapter 11 provides release notes for PTX Version 2.

0 6 January 24. 2010 .PTX ISA Version 2.

2. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. A cooperative thread array. is an array of threads that execute a kernel concurrently or in parallel.1. tid. Threads within a CTA can communicate with each other. or host: In other words. The vector ntid specifies the number of threads in each CTA dimension. 2D. Programming Model 2. and results across the threads of the CTA. January 24. ntid. or 3D CTA. Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2010 7 .x. compute-intensive portions of applications running on the host are off-loaded onto the device. assign specific input and output positions. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. but independently on different data.z). and tid.y. To that effect. a portion of an application that is executed many times. can be isolated into a kernel function that is executed on the GPU as many different threads. It operates as a coprocessor to the main CPU. The thread identifier is a three-element vector tid. Programs use a data parallel decomposition to partition inputs. one can specify synchronization points where threads wait until all threads in the CTA have arrived. work. Each CTA thread uses its thread identifier to determine its assigned role.2.1. 2. (with elements tid. or CTA. 2.z) that specifies the thread’s position within a 1D. To coordinate the communication of the threads within the CTA.x. 2D. and ntid.y. compute addresses. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. and select work to perform. or 3D shape specified by a three-element vector ntid (with elements ntid. data-parallel. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.Chapter 2. Each thread has a unique thread identifier within the CTA. More precisely. Each CTA has a 1D.

CTAs that execute the same kernel can be batched together into a grid of CTAs.0 Threads within a CTA execute in SIMT (single-instruction. 2010 . or sequentially. Multiple CTAs may execute concurrently and in parallel. read-only special registers %tid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. The warp size is a machine-dependent constant. or 3D shape specified by the parameter nctaid. Each grid of CTAs has a 1D. %ctaid. 2D . However. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Each grid also has a unique temporal grid identifier (gridid). 2. Some applications may be able to maximize performance with knowledge of the warp size. WARP_SZ. depending on the platform. 8 January 24. Threads may read and use these values through predefined. a warp has 32 threads. so PTX includes a run-time immediate constant. and %gridid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Threads within a warp are sequentially numbered. Typically. The host issues a succession of kernel invocations to the device. %ntid. multiple-thread) fashion in groups called warps. %nctaid. so that the total number of threads that can be launched in a single kernel invocation is very large.2.2. This comes at the expense of reduced thread communication and synchronization.PTX ISA Version 2. A warp is a maximal subset of threads from a single CTA. because threads in different CTAs cannot communicate and synchronize with each other. which may be used in any instruction where an immediate operand is allowed. such that the threads execute the same instructions at the same time.

0) Thread (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (0. 1) Thread (1. 2) Thread (4. 1) CTA (2. A grid is a set of CTAs that execute independently. 1) Thread (0.Chapter 2. 1) CTA (1. 2) Thread (3. Thread Batching January 24. Figure 1. 0) Thread (4. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (2. 0) Thread (3. 2) Thread (2. 0) CTA (2. 0) CTA (0. 1) Thread (3. 2) Thread (1. 0) CTA (1. 1) Thread (4. 0) Thread (0. 0) Thread (1. 2010 9 . 1) Grid 2 Kernel 2 CTA (1.

Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. The global.3. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. 10 January 24. all threads have access to the same global memory. The global. for more efficient transfer. Each thread has a private local memory.PTX ISA Version 2. as well as data filtering. referred to as host memory and device memory. Both the host and the device maintain their own local memory.0 2. The device memory may be mapped and read or written by the host. for some specific data formats. Texture memory also offers different addressing modes. or. 2010 . and texture memory spaces are optimized for different memory usages. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Finally. constant. constant. and texture memory spaces are persistent across kernel launches by the same application. respectively.

Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Figure 2. 0) Block (1. 1) Block (1. 0) Block (0. 1) Block (1. 1) Block (2. 0) Block (2.Chapter 2. 2010 11 . 1) Block (0. 2) Block (1. 0) Block (1. Memory Hierarchy January 24. 0) Block (0. 1) Grid 1 Global memory Block (0.

0 12 January 24.PTX ISA Version 2. 2010 .

disabling threads that are not on that path.1. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. so full efficiency is realized when all threads of a warp agree on their execution path. The multiprocessor SIMT unit creates. each warp contains threads of consecutive. the first parallel thread technology. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. manages. When a host program invokes a kernel grid. a multithreaded instruction unit.Chapter 3. A warp executes one common instruction at a time. and each scalar thread executes independently with its own instruction address and register state. January 24. To manage hundreds of threads running several different programs. it splits them into warps that get scheduled by the SIMT unit. the multiprocessor employs a new architecture we call SIMT (single-instruction. and on-chip shared memory. Parallel Thread Execution Machine Model 3. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs).) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. The multiprocessor creates. It implements a single-instruction barrier synchronization. the threads converge back to the same execution path. The multiprocessor maps each thread to one scalar processor core. A multiprocessor consists of multiple Scalar Processor (SP) cores. for example. multiple-thread). and executes threads in groups of parallel threads called warps. a cell in a grid-based computation). manages. 2010 13 . (This term originates from weaving. The way a block is split into warps is always the same. new blocks are launched on the vacated multiprocessors. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. Branch divergence occurs only within a warp. a voxel in a volume. As thread blocks terminate. If threads of a warp diverge via a data-dependent conditional branch. and when all paths complete. schedules. increasing thread IDs with the first warp containing thread 0. the warp serially executes each branch path taken. The threads of a thread block execute concurrently on one multiprocessor. and executes concurrent threads in hardware with zero scheduling overhead. allowing. When a multiprocessor is given one or more thread blocks to execute. different warps execute independently regardless of whether they are executing common or disjointed code paths. At every instruction issue time.

scalar threads.PTX ISA Version 2. 2010 . If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. the programmer can essentially ignore the SIMT behavior. If there are not enough registers or shared memory available per multiprocessor to process at least one block. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. For the purposes of correctness. 14 January 24. whereas SIMT instructions specify the execution and branching behavior of a single thread. Vector architectures. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides.0 SIMT architecture is akin to SIMD (Single Instruction. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. SIMT enables programmers to write thread-level parallel code for independent. modifies. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. write to that location occurs and they are all serialized. If an atomic instruction executed by a warp reads. but one of the writes is guaranteed to succeed. on the other hand. the number of serialized writes that occur to that location and the order in which they occur is undefined. and writes to the same location in global memory for more than one of the threads of the warp. • The local and global memory spaces are read-write regions of device memory and are not cached. modify. the kernel will fail to launch. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. In practice. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. In contrast with SIMD vector machines. A key difference is that SIMD vector organizations expose the SIMD width to the software. A multiprocessor can execute as many as eight thread blocks concurrently. which is a read-only region of device memory. As illustrated by Figure 3. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. as well as data-parallel code for coordinated threads. however. which is a read-only region of device memory. but the order in which they occur is undefined. each read. require the software to coalesce loads into vectors and manage divergence manually. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space.

Hardware Model January 24. 2010 15 .Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Figure 3.

2010 .PTX ISA Version 2.0 16 January 24.

#line. whitespace is ignored except for its use in separating tokens in the language. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #define. Source Format Source files are ASCII text. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.Chapter 4. The following are common preprocessor directives: #include. January 24. Pseudo-operations specify symbol and addressing management. Comments Comments in PTX follow C/C++ syntax. Syntax PTX programs are a collection of text source files. #endif. #if. Each PTX file must begin with a .target directive specifying the target architecture assumed. 4. 2010 17 .2.version directive specifying the PTX language version. 4. #ifdef. Lines beginning with # are preprocessor directives. All whitespace characters are equivalent. Comments in PTX are treated as whitespace. See Section 9 for a more information on these directives. PTX is case sensitive and uses lowercase for keywords. followed by a . #else. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.1. Lines are separated by the newline character (‘\n’). using non-nested /* and */ for comments that may span multiple lines. The C preprocessor cpp may be used to process PTX source files. and using // to begin a comment that extends to the end of the current line.

entry .5. or label names. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.sreg . r2.visible 4. .section . and terminated with a semicolon.b32 add.pragma .1. The guard predicate follows the optional label and precedes the opcode.tex .version . followed by source operands.reg . Table 1.0 4.3. %tid.global .b32 r1. where p is a predicate register. .PTX ISA Version 2.x.func .param .maxnreg . so no conflict is possible with user-defined identifiers. array[r1].local . Statements begin with an optional label and end with a semicolon. Instruction keywords are listed in Table 2.const . 2.file PTX Directives .maxnctapersm . 18 January 24.minnctapersm . Operands may be register variables.shared . address expressions. written as @!p. Directive Statements Directive keywords begin with a dot.3.maxntid . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. and is written as @p. r2. shl.extern . ld. r2.b32 r1. The destination operand is first. 0.target . mov. Instructions have an optional guard predicate which controls conditional execution. All instruction keywords are reserved tokens in PTX. Examples: .f32 array[N].global start: .b32 r1.f32 r2.reg . 2010 . The guard predicate may be optionally negated.3.align .2. r1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. Statements A PTX statement is either a directive or an instruction.loc .global. constant expressions.

Syntax Table 2. 2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

between user-defined variable names and compiler-generated names. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.4.PTX ISA Version 2. digits. The percentage sign can be used to avoid name conflicts. dollar. listed in Table 3. PTX predefines one constant and a small number of special registers that begin with the percentage sign. digits. 2010 . underscore. e. underscore. or they start with an underscore. or dollar characters. %pm3 WARP_SZ 20 January 24. Table 3. PTX allows the percentage sign as the first character of an identifier.0 4. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or percentage character followed by one or more letters.g. Many high-level languages such as C and C++ follow similar rules for identifier names. except that the percentage sign is not allowed. ….

1. the constant begins with 0d or 0D followed by 16 hex digits.5.. hexadecimal. and bit-size types. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. i.2.5. 4. i. or binary notation. literals are always represented in 64-bit double-precision format. floating-point.5. Integer literals may be written in decimal.u64). zero values are FALSE and non-zero values are TRUE. 0[fF]{hexdigit}{8} // single-precision floating point January 24. 2010 21 .e. every integer constant has type . Constants PTX supports integer and floating-point constants and constant expressions. in which case the literal is unsigned (. These constants may be used in data initialization and as operands to instructions. Floating-point literals may be written with an optional decimal point and an optional signed exponent.s64) unless the value cannot be fully represented in . To specify IEEE 754 single-precision floating point values. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Type checking rules remain the same for integer. 4. For predicate-type data and instructions.Chapter 4. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.e. To specify IEEE 754 doubleprecision floating point values.s64 or . where the behavior of the operation depends on the operand types. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Unlike C and C++. octal. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. each integer constant is converted to the appropriate size based on the data or instruction type at its use. The syntax follows that of C. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. When used in an instruction or data initialization. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. the constant begins with 0f or 0F followed by 8 hex digits.s64 or the unsigned suffix is specified. integer constants are allowed and are interpreted as in C.. there is no suffix letter to specify size. Syntax 4.u64.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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f64 use usual conversions .s64 .s64 .u64 .5. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . .f64 use usual conversions .f64 use usual conversions . Table 5.f64 converted type .s64 .f64 integer integer integer integer integer int ?. 2010 25 .s64 .u64 same as 1st operand . or .f64 : .f64 same as source .u64 .s64.s64 . Syntax 4.f64 converted type constant literal + ! ~ Cast Binary (.Chapter 4.u64 .u64.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 1st unchanged.u64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .f64 integer .6.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 . 2nd is .u64 .s64) + .f64 integer .u64) (.u64 .s64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.

PTX ISA Version 2. 2010 .0 26 January 24.

All variables reside in some state space. access rights. Kernel parameters. State Spaces A state space is a storage area with particular characteristics.param .shared . The characteristics of a state space include its size.local . Types. platform-specific. Global memory. Read-only. Special registers. Shared. the kinds of resources will be common across platforms. shared by all threads. . 5. 2010 27 .const .1. Table 6.Chapter 5. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. access speed. read-only memory. State Spaces. and level of sharing between threads.tex January 24. and Variables While the specific resources available in a given target GPU will vary. pre-defined. private to each thread.reg . or Function or local parameters. Name State Spaces Description Registers. Local memory.sreg . Addressable memory shared between threads in 1 CTA. and properties of state spaces are shown in Table 5. defined per-grid. fast. addressability.global . and these resources are abstracted in PTX through state spaces and data types. The list of state spaces is shown in Table 4. defined per-thread. Global texture memory (deprecated).

st. 2010 . causing changes in performance. 1 Accessible only via the ld. platform-specific registers. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Device function input parameters may have their address taken via mov.tex Restricted Yes No3 5. 5.param instruction. and performance monitoring registers. and vector registers have a width of 16-. Register State Space Registers (.reg . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).global .. scalar registers have a width of 8-. 32-.const . and cvt instructions. Registers may be typed (signed integer. The number of registers is limited.param instructions. All special registers are predefined. 32-.1. When the limit is exceeded.2. or 128-bits.e.local state space. 28 January 24. such as grid. Registers differ from the other state spaces in that they are not fully addressable. 16-. or 64-bits.1. i.reg state space) are fast storage locations. CTA.param and st.sreg) state space holds predefined. the parameter is then located on the stack frame and its address is in the . Address may be taken via mov instruction. register variables will be spilled to memory.1. 64-.shared . For each architecture. floating point.0 Table 7. Special Register State Space The special register (. or as elements of vector tuples. and thread parameters. Registers may have alignment boundaries required by multi-word loads and stores.param (as input to kernel) . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. clock counters. unsigned integer. 2 Accessible via ld. 3 Accessible only via the tex instruction.param (used in functions) .local . The most common use of 8-bit registers is with ld. aside from predicate registers which are 1-bit. and will vary from platform to platform.sreg . Register size is restricted. predicate) or untyped.PTX ISA Version 2. it is not possible to refer to the address of a register.

5.1. In implementations that support a stack. Global State Space The global (. Threads wait at the barrier until all threads in the CTA have arrived.extern . The remaining banks may be used to implement “incomplete” constant arrays (in C. 2010 29 .global) state space is memory that is accessible by all threads in a context. results in const_buffer pointing to the start of constant bank two. Consider the case where one thread executes the following two assignments: a = a + 1. Global memory is not sequentially consistent.Chapter 5.const) state space is a read-only memory. whereas local memory variables declared January 24.local and st. an incomplete array in bank 2 is accessed as follows: . This pointer can then be used to access the entire 64KB constant bank. and Variables 5.const[2] . It is typically standard memory with cache. the declaration .4. b = b – 1.b32 %r1. as it must be allocated on a perthread basis.const[2] . where the size is not known at compile time. as in lock-free and wait-free style programming.b32 const_buffer[]. there are eleven 64KB banks. Sequential consistency is provided by the bar. If another thread sees the variable b change.5.1. Use ld.3. To access data in contant banks 1 through 10.global.sync instruction are guaranteed to be visible to any reads after the barrier instruction. where bank ranges from 0 to 10. ld. [const_buffer+4]. The constant memory is organized into fixed size banks. Threads must be able to do their work without waiting for other threads to do theirs. For example.b32 const_buffer[].global to access global variables.global.local to access local variables. Local State Space The local state space (.const[2]. the bank number must be provided in the state space of the load instruction. This reiterates the kind of parallelism available in machines that run PTX. For any thread in a context. For the current devices. It is the mechanism by which different CTAs and different grids can communicate. State Spaces. for example). Types. bank zero is used. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. Constant State Space The constant (.const[bank] modifier. // load second word 5. Banks are specified using the . the store operation updating a may still be in flight. For example.local) is private memory for each thread to keep its own data. all addresses are in global memory are shared. The size is limited.1. bank zero is used for all statically-sized constant variables. st. Use ld. each pointing to the start address of the specified constant bank. By convention. If no bank number is given. initialized by the host. and atom. All memory writes prior to the bar. Multiple incomplete array variables declared in the same bank become aliases.extern . Module-scoped local memory variables are stored at fixed addresses. the stack is in local memory.sync instruction.

These parameters are addressable. In implementations that do not support a stack. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. [%ptr]. 2010 .param) state space is used (1) to pass input arguments from the host to the kernel.reg .param .u32 %ptr. Note that PTX ISA versions 1. mov.b32 len ) { . The use of parameter state space for device function parameters is new to PTX ISA version 2. (2a) to declare formal input and return parameters for device functions called from within kernel execution. … 30 January 24. The kernel parameter variables are shared across all CTAs within a grid. [N].u32 %n. device function parameters were previously restricted to the register state space. Similarly.param state space.f64 %d.param instructions.b32 N.param space variables.u32 %n.param .param. all local memory variables are stored at fixed addresses and recursive function calls are not supported.param instructions. %n. ld.6.reg . typically for passing large structures by value to a function.6.1. The resulting address is in the . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Example: .param.param space.u32 %n. Therefore. ld.1. in some implementations kernel parameters reside in global memory. Parameter State Space The parameter (. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.x supports only kernel function parameters in . For example.f64 %d.b8 buffer[64] ) { . PTX code should make no assumptions about the relative locations or ordering of . No access protection is provided between parameter and global space in this case. Note: The location of parameter space is implementation specific. 5. 5.param state space and is accessed using ld. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. [buffer].reg .PTX ISA Version 2. Values passed from the host to the kernel are accessed through these parameter variables using ld.0 within a function or kernel body are allocated on the stack.0 and requires target architecture sm_20. … Example: . read-only variables declared in the . ld. len.param .u32 %ptr. .align 8 . The address of a kernel parameter may be moved into a register using the mov instruction. per-kernel versus per-thread).1.entry foo ( .entry bar ( . .param.

Types.b32 N. . In PTX. The most common use is for passing objects by value that do not fit within a PTX register.b8 buffer[12] ) { . the address of a function input parameter may be moved into a register using the mov instruction. Function input parameters may be read via ld. … See the section on function call syntax for more details. (4. It is not possible to use mov to get the address of a return parameter or a locally-scoped .Chapter 5.align 8 .f64 [mystruct+0].reg . int y.param formal parameter having the same size and alignment as the passed argument. such as C structures larger than 8 bytes.param.s32 x. . } mystruct.param and function return parameters may be written using st. . passed to foo … . and so the address will be in the . Note that the parameter will be copied to the stack if necessary.s32 %y.param . st. Example: // pass object of type struct { double d. ld. mystruct).f64 %d. is flattened.reg . Device Function Parameters PTX ISA version 2. a byte array in parameter space is used. which declares a . State Spaces.param.param.s32 [mystruct+8]. .param space variable.param byte array variable that represents a flattened C structure or union.b8 mystruct.reg . call foo. [buffer].align 8 .param.2. dbl. x. In this case.param space is also required whenever a formal parameter has its address taken within the called function.s32 %y. … st. 2010 31 . the caller will declare a locally-scoped .func foo ( . January 24. int y.6.param.f64 %d.1.0 extends the use of parameter space to device function parameters. Typically. … } // code snippet from the caller // struct { double d. and Variables 5.local state space and is accessed via ld. [buffer+8]. .f64 dbl. it is illegal to write to an input parameter or read from a return parameter. This will be passed by value to a callee.reg .reg .local and st.param . }. .local instructions. Aside from passing structures by value. ld.

u32 .6 for its use in texture instructions. One example is broadcast.8. A texture’s base address is assumed to be aligned to a 16-byte boundary.u64. tex_d. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.u32 tex_a.global .texref variables in the .3 for the description of the .shared and st.tex) state space is global memory accessed via the texture instruction.u32 tex_a.1. Texture State Space (deprecated) The texture (. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).7. tex_f. where texture identifiers are allocated sequentially beginning with zero. and .tex directive is retained for backward compatibility. The .7. where all threads read from the same address. Use ld. 32 January 24. An error is generated if the maximum number of physical resources is exceeded.tex . 2010 . Another is sequential access from sequential threads. 5.tex state space are equivalent to module-scoped . An address in shared memory can be read and written by any thread in a CTA. Texture memory is read-only. and programs should instead reference texture memory through variables of type .tex .texref tex_a.0 5. Physical texture resources are allocated on a per-module granularity.shared to access shared variables. Shared State Space The shared (. The texture name must be of type .1.u32 or .shared) state space is a per-CTA region of memory for threads in a CTA to share data.u32 . and variables declared in the . Example: .tex .global state space. See Section 5. tex_c. It is shared by all threads in a context.u32 .tex directive will bind the named texture memory variable to a hardware texture identifier.texref.tex variables are required to be defined in the global scope. tex_d.tex . a legacy PTX definitions such as . The .texref type and Section 8. Multiple names may be bound to the same physical texture identifier. For example. is equivalent to .tex . Shared memory typically has some optimizations to support the sharing.PTX ISA Version 2.

.f16.f32 and . The bitsize type is compatible with any fundamental type having the same size. . In principle. and instructions operate on these types.s8. needed to fully specify instruction behavior. and . Signed and unsigned integer types are compatible if they have the same size.f64 types. so that narrow values may be loaded. all variables (aside from predicates) could be declared using only bit-size types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.f32 and .2. . For example.s32.u32. st. Operand types and sizes are checked against instruction types for compatibility. A fundamental type specifies both a basic type and a size.b8 instruction types are restricted to ld. State Spaces. Fundamental Types In PTX. .f16 floating-point type is allowed only in conversions to and from .2.s64 .s16. Types 5.f64 . January 24.2.u64 . and converted using regular-width registers. and Variables 5.Chapter 5. ld.1. Register variables are always of a fundamental type. .b16.pred Most instructions have one or more type specifiers. Two fundamental types are compatible if they have the same basic type and are the same size. but typed variables enhance program readability and allow for better operand type checking. . All floating-point instructions operate only on . so their names are intentionally short.f64 types. .f32. Types. the fundamental types reflect the native data types supported by the target architectures. .b8. 2010 33 . .s8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. stored.u8. and cvt instructions. . The following table lists the fundamental type specifiers for each basic type: Table 8. . 5. stored. Restricted Use of Sub-Word Sizes The .u8. .2. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .u16.b64 . The same typesize specifiers are used for both variable definitions and for typing instructions. For convenience. st. or converted to other types and sizes.b32. The .

In the unified mode. Referencing textures. Creating pointers to opaque variables using mov.samplerref. but all information about layout. store. accessing the pointer with ld and st instructions. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. In the independent mode. and query instructions.samplerref variables. 34 January 24.surfref. allowing them to be defined separately and combined at the site of usage in the program.texref. and surface descriptor variables. sured). Retrieving the value of a named member via query instructions (txq. the resulting pointer may be stored to and loaded from memory. PTX has two modes of operation. and Surface Types PTX includes built-in “opaque” types for defining texture. samplers. Sampler. or surfaces via texture and surface load/store instructions (tex. These types have named fields similar to structures.e. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.{u32. texture and sampler information each have their own handle. passed as a parameter to functions. but the pointer cannot otherwise be treated as an address. suld. suq).0 5. and overall size is hidden to a PTX program. i. field ordering.PTX ISA Version 2. sampler. Texture. and . . The following tables list the named members of each type for unified and independent texture modes. opaque_var..3. since these properties are defined by . sust. base address. In independent mode the fields of the . and de-referenced by texture and surface load. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. 2010 . For working with textures and samplers.texref type that describe sampler properties are ignored.texref handle. hence the term “opaque”. or performing pointer arithmetic will result in undefined results. texture and sampler information is accessed through a single . The three built-in types are .u64} reg.

2010 35 . Types. linear wrap. clamp_to_border 0. clamp_to_border N/A N/A N/A N/A N/A . clamp_to_edge. clamp_ogl.samplerref values N/A N/A N/A N/A nearest.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. 1 nearest.texref values .texref values in elements in elements in elements 0. mirror. and Variables Table 9. linear wrap. clamp_to_edge. mirror. 1 ignored ignored ignored ignored . Member width height depth Opaque Type Fields in Independent Texture Mode . State Spaces. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_ogl.Chapter 5.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.

36 January 24. . Example: .global .global .texref tex1.texref my_texture_name. these variables are declared in the .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. When declared at module scope.global . Example: . .global .surfref my_surface_name.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.PTX ISA Version 2. As kernel parameters. filter_mode = nearest }. these variables must be in the . 2010 .global . At module scope.global state space. .samplerref my_sampler_name. the types may be initialized using a list of static expressions assigning values to the named members.param state space.

f32 bias[] = {-1. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. A variable declaration names the space in which the variable resides. and an optional fixed address for the variable. . a variable declaration describes both the variable’s type and its state space.2.v4 . PTX supports types for simple aggregate objects such as vectors and arrays.u16 uv.pred p. Examples: . vector variables are aligned to a multiple of their overall size (vector length times base-type size). q. // a length-4 vector of bytes By default. its type and size.0.v4 .reg . Three-element vectors may be handled by using a .f32 accel.global .v4 . Vectors Limited-length vector types are supported. 0}. // a length-2 vector of unsigned ints . In addition to fundamental types.1. .0}. .Chapter 5.b8 v. its name. Variables In PTX.v1.4.u8 bg[4] = {0.f32 V.shared .f32 v0.const . Types. and they may reside in the register space. Predicate variables may only be declared in the register state space. Variable Declarations All storage for data is specified with variable declarations. textures. for example.global .global . r. January 24. and Variables 5. 5. an optional initializer. etc. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . Vectors must be based on a fundamental type.struct float4 { . Every variable must reside in one of the state spaces enumerated in the previous section. Examples: . Vectors cannot exceed 128-bits in length. 5.u32 loc.v2 or .4.global . an optional array size.global . where the fourth element provides padding. // a length-4 vector of floats .4.v4. This is a common case for three-dimensional grids. 0.reg .struct float4 coord.v2 . . 0. . 1.s32 i.f64 is not allowed. . // typedef . 2010 37 .reg .v3 }.v2.v4.v4 vector. . State Spaces.

Array Declarations Array declarations are provided to allow the programmer to reserve space.1. -1}. {0. The size of the array specifies how many elements should be reserved. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. 0}.0 5.. .f32 blur_kernel[][] = {{.{.global . where the variable name is followed by an equals sign and the initial value or values for the variable. variable initialization is supported only for constant and global state spaces.u8 mailbox[128].u32 or . // address of rgba into ptr Currently. . Variables that hold addresses of variables or instructions should be of type . 19*19 (361) halfwords are reserved (722 bytes).4. Initializers are allowed for all types except .s32 offset[][] = { {-1.global .. this can be used to statically initialize a pointer to a variable.4.u16 kernel[19][19]. .05}}.0}. {0. 0}. 2010 . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). this can be used to initialize a jump table to be used with indirect branches or calls.b32 ptr = rgba. For the kernel declaration above.3..PTX ISA Version 2.0. The size of the dimension is either a constant expression. Here are some examples: . {1.0.1.05}.1.05. To declare an array.. 5. Initializers Declared variables may specify an initial value using a syntax similar to C/C++..v4 . {0.4. Variable names appearing in initializers represent the address of the variable. 1} }.1.{. Similarly.u64. . or is left empty.shared .pred.1}. {0. .0}}.1.u8 rgba[3] = {{1. 38 January 24.global .05. label names appearing in initializers represent the address of the next instruction following the label.0.0. being determined by an array initializer. A scalar takes a single value.0}.global .local ..global .4.s32 n = 10.f16 and . Examples: .

of . // declare %r0. Examples: // allocate array at 4-byte aligned address.reg .5. it is quite common for a compiler frontend to generate a large number of register names.2.Chapter 5. %r99.const . Elements are bytes. 2010 39 . . Types. For arrays.0. The default alignment for scalar and array variables is to a multiple of the base-type size.0. not for individual elements. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. For example.6. State Spaces.. suppose a program uses a large number. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. nor are initializers permitted.4. 5. January 24. Parameterized Variable Names Since PTX supports virtual registers.align byte-count specifier immediately following the state-space specifier. These 100 register variables can be declared as follows: . The default alignment for vector variables is to a multiple of the overall vector size. named %r0.0.align 4 . and Variables 5. %r1. The variable will be aligned to an address which is an integer multiple of byte-count.b32 variables.0}. Rather than require explicit declaration of every name. Array variables cannot be declared this way. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.0. %r1. alignment specifies the address alignment for the starting address of the entire array.4. . Alignment is specified using an optional ...b8 bar[8] = {0. …. and may be preceded by an alignment specifier.0. say one hundred.b32 %r<100>.

2010 .0 40 January 24.PTX ISA Version 2.

Predicate operands are denoted by the names p. and cvt instructions copy data from one location to another. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The result operand is a scalar or vector variable in the register state space. as its job is to convert from nearly any data type to any other data type (and size). . Integer types of a common size are compatible with each other. mov. Instruction Operands 6. Source Operands The source operands are denoted in the instruction descriptions by the names a. 6. The ld. 2010 41 . There is no automatic conversion between types. and c. The bit-size type is compatible with every type having the same size. Operand Type Information All operands in instructions have a known type from their declarations. Most instructions have an optional predicate guard that controls conditional execution. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. r. January 24. and a few instructions have additional predicate source operands.3. s. The mov instruction copies data between registers.Chapter 6.reg register state space. The cvt (convert) instruction takes a variety of operand types and sizes. 6. b. PTX describes a load-store machine. Instructions ld and st move data from/to addressable state spaces to/from registers. Each operand type must be compatible with the type determined by the instruction template and instruction type.2. For most operations.1. the sizes of the operands must be consistent. st. so operands for ALU instructions must all be in variables declared in the . q.

. address registers.[x].reg . .reg . ld. 6.1.reg . W.v4. Arrays. The syntax is similar to that used in many assembly languages.global . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.u16 x. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. Load and store operations move data between registers and locations in addressable state spaces.PTX ISA Version 2.v4 .s32 mov. . [V]. q. Using Addresses.u32 42 January 24. The interesting capabilities begin with addresses. r0. Here are a few examples: .f32 W. and Vectors Using scalar variables as operands is straightforward.const . address register plus byte offset.u16 ld. p.b32 p.f32 V.gloal.reg . The address is an offset in the state space in which the variable is declared.shared. .f32 ld.s32 q. Address expressions include variable names.4. there is no support for C-style pointer arithmetic. All addresses and address computations are byte-based.shared .0 6. arrays. 2010 .u16 r0. Examples include pointer arithmetic and pointer comparisons. .const. The mov instruction can be used to move the address of a variable into a pointer. tbl.s32 tbl[256]. and immediate address expressions which evaluate at compile-time to a constant address. [tbl+12].4. .v4 . and vectors.

f32 {a.b.global. Examples are ld. or by indexing into the array using square-bracket notation.r. Rc. .Chapter 6.v2. or a simple “register with constant offset” expression.v4 . Instruction Operands 6.b. // move address of a[1] into s 6. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.y. The registers in the load/store operations can be a vector. ld.u32 s.w = = = = V. If more complicated indexing is desired.2.c. and the identifier becomes an address constant in the space where the array is declared. a[1]. .b and . and in move instructions to get the address of the label or function into a register. V. The size of the array is a constant in the program.f32 ld. d. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.u32 s. which may improve memory performance.r V. mov.reg . Arrays as Operands Arrays of all types can be declared. a[N-1]. which include mov.a 6. .global. .4. V2.4. Rd}.d}. Rb. where the offset is a constant expression that is either added or subtracted from a register variable.d}.z and . and tex. or a braceenclosed list of similarly typed scalars. a[0].u32 s. Here are examples: ld. a register variable.a. st.y V. . Elements in a brace-enclosed vector. say {Ra.w.z V.x.3. ld.reg .4.f32 V.c. A brace-enclosed list is used for pattern matching to pull apart vectors. 2010 43 .u32 {a. .g. Vector loads and stores can be used to implement wide loads and stores.g V. Vectors as Operands Vector operands are supported by a limited subset of instructions. b.f32 a. Array elements can be accessed using an explicitly calculated byte address. for use in an indirect branch or call.global.b V. The expression within square brackets is either a constant integer. [addr+offset2].x V.v4. Vectors may also be passed as arguments to called functions. January 24.v4. [addr+offset]. it must be written as an address calculation prior to use. mov. Vector elements can be extracted from the vector with the suffixes . as well as the typical color fields . c.4.global.

6. and data movement instruction must be of the same type and size. For example. if a cvt.5.u16 instruction is given a u16 source operand and s32 as a destination operand.0 6. Operands of different sizes or types must be converted prior to the operation. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. 2010 . Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. except for operations where changing the size and/or type is part of the definition of the instruction.s32. and ~131.000 for f16). the u16 is zero-extended to s32.1. logic.5.PTX ISA Version 2. 44 January 24. Type Conversion All operands to all arithmetic.

u2f = unsigned-to-float. chop = keep only low bits that fit. January 24. For example. f2s = float-to-signed. zext = zero-extend. the result is extended to the destination register width after chopping. s2f = signed-to-float. 2010 45 . The type of extension (sign or zero) is based on the destination format. Notes 1 If the destination register is wider than the destination format. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.Chapter 6. f2u = float-to-unsigned. Instruction Operands Table 11. f2f = float-to-float.u32 targeting a 32-bit register will first chop to 16-bits. cvt.s16. then sign-extend to 32-bits.

Modifier . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. there are four integer rounding modifiers and four floating-point rounding modifiers.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rpi Integer Rounding Modifiers Description round to nearest integer. 2010 .2.0 6.rni .PTX ISA Version 2.rn . In PTX. Table 12.rm . choosing even integer if source is equidistant between two integers. The following tables summarize the rounding modifiers.rzi . Modifier . Rounding Modifiers Conversion instructions may specify a rounding modifier.rmi .rz .5.

as execution is not blocked until the desired result is used in a subsequent (in time) instruction.6. The register in a store operation is available much more quickly. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Operand Costs Operands from different state spaces affect the speed of an operation. Table 11 gives estimates of the costs of using different kinds of memory.Chapter 6. Table 14. Another way to hide latency is to issue the load instructions as early as possible. Instruction Operands 6. 2010 47 . while global memory is slowest. first access is high Notes January 24. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Much of the delay to memory can be hidden in a number of ways. Registers are fastest.

2010 .PTX ISA Version 2.0 48 January 24.

parameter passing. These include syntax for function definitions. stack layout. and an optional list of input parameters. or prototype. Function declarations and definitions In PTX. A function definition specifies both the interface and the body of the function. and is represented in PTX as follows: . Abstracting the ABI Rather than expose details of a particular calling convention. arguments may be register variables or constants. we describe the features of PTX needed to achieve this hiding of the ABI. January 24. and return values may be placed directly into register variables. execution of the call instruction transfers control to foo. functions are declared and defined using the . 7. together these specify the function’s interface. In this section. A function must be declared or defined prior to being called. implicitly saving the return address. At the call.Chapter 7. support for variadic functions (“varargs”). and memory allocated on the stack (“alloca”). NOTE: The current version of PTX does not implement the underlying. Execution of the ret instruction within foo transfers control to the instruction following the call. the function name. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. } … call foo.func foo { … ret. A function declaration specifies an optional list of return parameters. stack-based ABI. Scalar and vector base-type input and return parameters may be represented simply as register variables. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. function calls. so recursion is not yet supported.1. The simplest function has no parameters or return values. 2010 49 . and Application Binary Interface (ABI).func directive. … Here.

The .param.u32 %ptr.reg . [y+10]. a . %rc1.param space variables are used in two ways. 2010 . st. [y+11]. a .c3.s32 out) bar (.param . passed by value to a function: struct { double dbl. Since memory accesses are required to be aligned to a multiple of the access size.b8 c4.u32 %res.c1.reg .0 Example: .func (.reg .reg .b8 . For example. [y+0]. py). … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . note that . [y+8].func (.param . ld. c4.param.param variable y is used in function definition bar to represent a formal parameter.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.f64 f1. … In this example. Second. … … // computation using x.f1. 50 January 24.b8 . byte array in .b8 [py+10]. c3. … ld.param state space is used to pass the structure by value: .reg .b8 [py+ 8].u32 %inc ) { add. First. %inc.param. %rc2.param space memory. char c[4].param.param. }. %ptr.s32 x.param space call (%out).b8 c2.4). consider the following C structure. // scalar args in . st.b8 c1.u32 %res) inc_ptr ( . ret.param.align 8 py[12]. st.b8 [py+ 9].b8 c3.param.param. (%r1.b64 [py+ 0].param. %rc2.c2. . (%x.c4.f64 f1. } { . %rc1.reg space.b8 [py+11]. %rd.PTX ISA Version 2. } … call (%r1). c2.f64 field are aligned. ld. st. bumpptr. . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .align 8 y[12]) { . .param.reg . this structure will be flattened into a byte array. ld. ld. … st.reg . In PTX. inc_ptr. [y+9].b32 c1.

reg variables.param space formal parameters that are base-type scalar or vector variables. Typically. or constants.param or .Chapter 7. 2010 51 . The .param arguments. For . Supporting the .param byte array is used to collect together fields of a structure being passed by value. • The . This enables backend optimization and ensures that the . • • • Input and return parameters may be . January 24. or 16 bytes.reg variables.reg space formal parameters.param variables. and alignment of parameters. • The .param variables or .param space byte array with matching type. The following restrictions apply to parameter passing. In the case of . size. In the case of . 2. Note that the choice of .reg state space in this way provides legacy support. the corresponding argument may be either a .param or . • • • For a callee.param state space use in device functions.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. A .param space formal parameters that are byte arrays. Abstracting the ABI The following is a conceptual way to think about the . the argument must also be a . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. For a callee. 8.param argument must be declared within the local scope of the caller. • • Arguments may be ..reg space variable with matching type and size.param instructions used for argument passing must be contained in the basic block with the call instruction. In the case of . or a constant that can be represented in the type of the formal parameter.param state space is used to receive parameter values and/or pass return values back to the caller.g.reg or . .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. a . the corresponding argument may be either a . size. Parameters in . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.reg space variable of matching type and size. The . or a constant that can be represented in the type of the formal parameter.reg state space can be used to receive and return base-type scalar and vector values. For a caller.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param memory must be aligned to a multiple of 1. and alignment.param and ld. For a caller. 4. all st.

Changes from PTX 1.x.0 restricts functions to a single return value.x supports multiple return values for this purpose.reg state space. and a . formal parameters were restricted to .0 continues to support multiple return registers for sm_1x targets.PTX ISA Version 2. 52 January 24.reg or . Objects such as C structures were flattened and passed or returned using multiple registers.1. 2010 . formal parameters may be in either . PTX 1. In PTX ISA version 2. For sm_2x targets.0. and . PTX 2. and there was no support for array parameters.param space parameters support arrays.x In PTX ISA version 1.1.0 7.param byte array should be used to return objects that do not fit into a register. PTX 2.param state space.

4. Variadic functions NOTE: The current version of PTX does not support variadic functions. and end access to a list of variable arguments. the size may be 1. .reg . call %va_end.u32 ap. the alignment may be 1.. call (ap). maxN. call (val). Once all arguments have been processed.reg . PTX provides a high-level mechanism similar to the one provided by the stdarg.reg .b64 val) %va_arg64 (. For %va_arg. %r1.b32 result. %s1. %s2). 2010 53 . max.Chapter 7.reg . setp. … %va_start returns Loop: @p Done: January 24. (3. %va_start.reg .s32 result. . To support functions with a variable number of arguments.ge p. mov. } … call (%max). 2.b32 val) %va_arg (. In PTX.reg . or 8 bytes.u32. ctr. (2. 8. for %va_arg64. (ap.u32 b.func baz ( . 4).func %va_end (. 2.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. 4..reg . bra Loop. variadic functions are declared with an ellipsis at the end of the input parameter list. (ap).u32 ptr.2.u32 a.u32 sz.reg . maxN.u32 align) . … call (%max). // default to MININT mov. or 4 bytes. the size may be 1.h and varargs. iteratively access.h headers in C. N.func ( .reg . bra Done. . %va_end is called to free the variable argument list handle.reg . Abstracting the ABI 7.s32 result ) maxN ( . .reg .reg . … ) .u32 ptr. %r3). %r2.reg . This handle is then passed to the %va_arg and %va_arg64 built-in functions. . The function prototypes are defined as follows: . or 16 bytes. 0x8000000. val. result.reg . 2. along with the size and alignment of the next data value to be accessed.func (.u32 align) .func (. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .u32 N. ctr.reg .u32 sz.pred p. 0.reg . ) { . following zero or more fixed parameters: .reg . 4.b32 ctr.s32 val. .func okay ( … ) Built-in functions are provided to initialize. In both cases.u32 ptr) %va_start .func (. ret. . %va_arg. .

Alloca NOTE: The current version of PTX does not support alloca. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. The array is then accessed with ld.u32 ptr ) %alloca ( .0 7.reg . 2010 .local instructions. a function simply calls the built-in function %alloca. defined as follows: .reg .PTX ISA Version 2.3.local and st. 54 January 24. If a particular alignment is required. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.func ( . To allocate memory.

A.1. opcode D. opcode D. setp. Instruction Set 8. a. For some instructions the destination operand is optional. PTX Instructions PTX instructions generally have from zero to four operands. // p = (a < b).s32. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. We use a ‘|’ symbol to separate multiple destination registers. January 24. b. opcode A. The setp instruction writes two destination registers. B. C. while A. A. and C are the source operands. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. B. B. For instructions that create a result value. the semantics are described.lt p|q. the D operand is the destination operand. opcode D.Chapter 8. q = !(a < b). In addition to the name and the format of the instruction. followed by some examples that attempt to show several possible instantiations of the instruction. A.2. 2010 55 . 8.

branch over 56 January 24. This can be written in PTX as @p setp. Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 j. add.0 8. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. 2010 .lt.pred as the type specifier. add. n.PTX ISA Version 2. Predicated Execution In PTX. j. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.3. optionally negated. predicate registers are virtual and have . i. Instructions without a guard predicate are executed unconditionally. i.s32 p. predicate registers can be declared as .s32 p. consider the high-level code if (i < n) j = j + 1. the following PTX instruction sequence might be used: @!p L1: setp. 1.lt. use a predicate to control the execution of the branch or call instructions. n.s32 j. // p = (i < n) // if i < n. j. So.reg . 1. add 1 to j To get a conditional branch or conditional function call. To implement the above example as a true conditional branch.pred p. As an example. where p is a predicate variable. q. … // compare i to n // if false. bra L1.

Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and ge (greater-than-or-equal). le.3. lt (less-than).1.1. ne. The following table shows the operators for signed integer. gt (greater-than). unsigned integer. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.Chapter 8. and bitsize types.1. le (less-than-or-equal). Table 16. Instruction Set 8. Comparisons 8. 2010 57 .3. lo (lower).1. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). the result is false. hi (higher).3. lt. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Unsigned Integer. ne. gt. ls (lower-or-same). ge. If either operand is NaN. and hs (higher-or-same). Table 15. The unsigned comparisons are eq. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.2. ne (not-equal). The bit-size comparisons are eq and ne. ordering comparisons are not defined for bit-size types.

gtu. Table 17. There is no direct conversion between predicates and integer values. for example: selp. However.1. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. geu. not. and no direct way to load or store predicate register values. If both operands are numeric values (not NaN). or. setp can be used to generate a predicate from an integer. two operators num (numeric) and nan (isNaN) are provided.PTX ISA Version 2. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.0.0 To aid comparison operations in the presence of NaN values. ltu.2.3. and mov.u32 %r1. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. If either operand is NaN. Table 18. num returns true if both operands are numeric values (not NaN). leu. neu. then these comparisons have the same result as their ordered counterparts. // convert predicate to 32-bit value 58 January 24. then the result of these comparisons is true. unordered versions are included: equ.%p. xor. 2010 . and nan returns true if either operand is NaN.

reg .u16 a.uX . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. b. Instruction Set 8.Chapter 8.bX . the add instruction requires type and size information to properly perform the addition operation (signed. For example: . different sizes). // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. most notably the data conversion instruction cvt. and integer operands are silently cast to the instruction type if needed.fX ok inv inv ok Instruction Type . Table 19.f32 d.u16 d. b.sX . they must match exactly. For example.uX ok ok ok inv . Floating-point types agree only if they have the same size.bX .f32. a.reg . Signed and unsigned integer types agree provided they have the same size. float. Type Checking Rules Operand Type .u16 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. add..e.fX ok ok ok ok January 24. It requires separate type-size modifiers for the result and source. and this information must be specified as a suffix to the opcode. and these are placed in the same order as the operands. i. Example: . For example. cvt.u16 d. a.4. a.sX ok ok ok inv . unsigned. 2010 59 . . • The following table summarizes these type checking rules. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.reg .

The following table summarizes the relaxed type-checking rules for source operands. or converted to other types and sizes.0 8. for example. and converted using regular-width registers. unless the operand is of bit-size type. “-“ = allowed. ld. parse error. 60 January 24. 2. When a source operand has a size that exceeds the instruction-type size.1.bX instruction types. stored. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. When used with a narrower bit-size type. 1. Notes 3. Table 20. Floating-point source registers can only be used with bit-size or floating-point instruction types. Source register size must be of equal or greater size than the instruction-type size. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. no conversion needed. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.PTX ISA Version 2. so that narrow values may be loaded. 4. When used with a floating-point instruction type. 2010 .4. the cvt instruction does not support . Bit-size source registers may be used with any appropriately-sized instruction type. so those rows are invalid for cvt. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. For example. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. stored. Note that some combinations may still be invalid for a particular instruction. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. st. the size must match exactly. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Operand Size Exceeding Instruction-Type Size For convenience. The data is truncated to the instruction-type size and interpreted according to the instruction type. inv = invalid. the data will be truncated. floating-point instruction types still require that the operand type-size matches exactly.

Bit-size destination registers may be used with any appropriately-sized instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. When used with a floatingpoint instruction type. parse error. Table 21. The data is signextended to the destination register width for signed integer instruction types. otherwise. inv = Invalid. “-“ = Allowed but no conversion needed. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size. the data will be zero-extended. 4. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend.or sign-extended to the size of the destination register. the data is sign-extended. 2010 61 . 1. the data is zeroextended. the size must match exactly. The data is sign-extended to the destination register width for signed integer instruction types. Destination register size must be of equal or greater size than the instruction-type size.Chapter 8. The following table summarizes the relaxed type-checking rules for destination operands. zext = zero-extend. the destination data is zero. If the corresponding instruction type is signed integer. 2. and is zero-extended to the destination register width otherwise. January 24. Notes 3. When used with a narrower bit-size instruction type.

the threads are called uniform. at least in appearance. so it is important to have divergent threads re-converge as soon as possible. Both situations occur often in programs. and for many applications the difference in execution is preferable to limiting performance. or conditional return.uni suffix. and 16-bit computations are “promoted” to 32-bit computations. the threads are called divergent. If threads execute down different control flow paths. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. for many performance-critical applications. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. 8. For divergent control flow. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. a compiler or code author targeting PTX can ignore the issue of divergent threads. conditional function call. Divergence of Threads in Control Constructs Threads in a CTA execute together.PTX ISA Version 2. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. by a right-shift instruction. The semantics are described using C. until they come to a conditional control construct such as a conditional branch. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. When executing on a 32-bit data path. Therefore. the semantics of 16-bit instructions in PTX is machine-specific.0 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. If all of the threads act in unison and follow a single control flow path. the optimizing code generator automatically determines points of re-convergence. 8.1. this is not desirable. 62 January 24. 16-bit registers in PTX are mapped to 32-bit physical registers. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. A compiler or programmer may chose to enforce portable. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. At the PTX language level.6. until C is not expressive enough.5.6. These extra precision bits can become visible at the application level. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. 2010 . However. using the . Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. for example.

Chapter 8.1. 8. Instructions All PTX instructions may be predicated. the optional guard predicate is omitted from the syntax. The Integer arithmetic instructions are: add sub add.7. Instruction Set 8. In the following descriptions.cc.cc. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 2010 63 .7. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. addc sub.

u64.s32 c. // .s64 }.s64 }. Description Semantics Notes Performs addition and writes the resulting value into a destination register. d = a + b. .c.0 Table 22.u32.u16. add. b. a. Introduced in PTX ISA version 1. . d = a – b. sub.. add. sub.. Saturation modifier: .u64. @p add.s32 c.s32 . . .0.s32.s16.y. . d. b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. // . Supported on all target architectures. .sat applies only to . PTX ISA Notes Target ISA Notes Examples Table 23.s32 type. .sat}.sat.PTX ISA Version 2.s32. Applies only to .sat applies only to . b. PTX ISA Notes Target ISA Notes Examples 64 January 24.sat}.type sub{.s32 type.0. d.type = { .u32. a.s32 d. a.s16.1.sat limits result to MININT.b. . Introduced in PTX ISA version 1. Applies only to .u32 x. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.MAXINT (no overflow) for the size of the operation. . 2010 .a. add Syntax Integer Arithmetic Instructions: add Add two values. .z.s32 d.u16. b. Saturation modifier: .s32 . Supported on all target architectures. a.type add{.sat limits result to MININT.MAXINT (no overflow) for the size of the operation.type = { .

b32 addc. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.b32 addc. and there is no support for setting. @p @p @p @p add.z2. x2. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. carry-out written to CC.y3. addc.cc Add two values with carry-out.z3.cc. . x3. a. Supported on all target architectures. or testing the condition code. d = a + b + CC.b32 addc. No saturation. carry-out written to CC. x4. sub.y1.y3.cc. Introduced in PTX ISA version 1. 2010 65 .type d.cc. . .u32. add.cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.y4.y4.CF No integer rounding modifiers.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. b.z2. No saturation.type = { . Introduced in PTX ISA version 1.cc}. x2.z1.b32 x1.2. These instructions support extended-precision integer addition and subtraction.CF) holding carry-in/carry-out or borrowin/borrow-out. a.CF No integer rounding modifiers.z3.cc.type = {.cc specified.y2.s32 }.2. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. b.y1.cc Syntax Integer Arithmetic Instructions: add.CF. if . Instruction Set Instructions add.z1. No other instructions access the condition code.cc.cc. Behavior is the same for unsigned and signed integers. x4.Chapter 8. addc{.b32 addc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.z4.b32 addc.y2. Behavior is the same for unsigned and signed integers.type d.u32. x3.b32 x1. @p @p @p @p add. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.cc.cc. d = a + b. .z4. add. Supported on all target architectures. Table 24.cc.s32 }.b32 addc. clearing.

type d.3. . b. x3.b32 subc.z4. borrow-out written to CC.cc. No saturation. x2. a. x2. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. 2010 .(b + CC.type d.b32 subc.y2.3.y1. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.z1. sub. .z1.cc Syntax Integer Arithmetic Instructions: sub.b32 subc.z2. x3.y4.y2.cc.cc Subract one value from another.cc.u32.cc}.y1. a. d = a – b. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.cc specified. with borrow-out.u32. No saturation.z4.y3.PTX ISA Version 2. subc{. withborrow-in and optional borrow-out.cc.b32 subc.type = {. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Supported on all target architectures.s32 }.b32 x1. Supported on all target architectures. Introduced in PTX ISA version 1. @p @p @p @p sub. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. @p @p @p @p sub. if .CF).z3.b32 subc. d = a .cc.cc. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers. Behavior is the same for unsigned and signed integers. . .b32 x1. sub. x4.s32 }.CF No integer rounding modifiers. x4. Introduced in PTX ISA version 1.y3.cc.cc.z2.y4.b32 subc.type = { .0 Table 26. b.cc.z3. borrow-out written to CC.

Description Semantics Compute the product of two values.s16.wide suffix is supported only for 16. then d is the same size as a and b. mul. then d is twice as wide as a and b to receive the full result of the multiplication. d = t.wide.n>.s32.s64 }. .. b.lo variant Notes The type of the operation represents the types of the a and b operands. creates 64 bit result January 24. If . The .y.. .fxs.0>.u16.type d.Chapter 8. // 16*16 bits yields 32 bits // 16*16 bits. a..s32 z. n = bitwidth of type. . and either the upper or lower half of the result is written to the destination register.lo is specified.s16 fa. d = t<2n-1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.hi variant // for .fys.wide}.and 32-bit integer types.hi. . d = t<n-1. . // for .fys.lo.0.type = { .fxs.hi or ..wide // for . mul.wide is specified. mul{. t = a * b. 2010 67 .s16 fa.u64. Instruction Set Table 28. mul. If . save only the low 16 bits // 32*32 bits. .x. Supported on all target architectures.u32.lo.

.lo. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and then writes the resulting value into a destination register. @p mad. Description Semantics Multiplies two values and adds a third. . a.s64 }.MAXINT (no overflow) for the size of the operation.. Saturation modifier: ..s32 type in .u16. Applies only to .0> + c.PTX ISA Version 2.c.wide suffix is supported only for 16. c.type mad. and either the upper or lower half of the result is written to the destination register.sat limits result to MININT.0 Table 29. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. 68 January 24. .hi. If . mad. If .s32 r.and 32-bit integer types. // for .u32.hi variant // for . then d and c are the same size as a and b. c. d. The . Supported on all target architectures.s32.lo. .n> + c..s16.s32 d.u64.p.wide}. t n d d d = = = = = a * b. t + c.lo is specified.. t<2n-1.wide is specified.hi or . 2010 . then d and c are twice as wide as a and b to receive the result of the multiplication.wide // for .q.a. bitwidth of type. b.lo variant Notes The type of the operation represents the types of the a and b operands.lo.. .r.s32 d. t<n-1.b. .0.type = { . mad{.hi.sat.hi mode. b.

Instruction Set Table 30.type = { . a.16>.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. d = t<31..s32 d.lo.e. All operands are of the same type and size. mul24.type d. .s32 }.lo}. t = a * b. i.0..b. 48bits. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24. and return either the high or low 32-bits of the 48-bit result. January 24.hi.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.Chapter 8.hi may be less efficient on machines without hardware support for 24-bit multiply.0>. d = t<47.. Supported on all target architectures. 2010 69 . mul24.hi variant // for .u32. // low 32-bits of 24x24-bit signed multiply. mul24. .a. b. // for . mul24{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.

b. i. Description Compute the product of two 24-bit integer values held in 32-bit source registers. Applies only to . // low 32-bits of 24x24-bit signed multiply.sat limits result of 32-bit signed addition to MININT.sat.. mad24.a. a. Supported on all target architectures.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.0> + c.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands..lo. 32-bit value to either the high or low 32-bits of the 48-bit result. All operands are of the same type and size. mad24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.e. 48bits.. t = a * b. .PTX ISA Version 2.s32 d. mad24.s32 d.type mad24. c. ..0 Table 31. d.hi mode. Return either the high or low 32-bits of the 48-bit result.0.16> + c. 2010 . // for . a. Saturation modifier: . and add a third. b.MAXINT (no overflow).hi variant // for .hi may be less efficient on machines without hardware support for 24-bit multiply. d = t<47. 70 January 24.b.hi. mad24{.lo}.type = { .s32 }.hi. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. c.s32 type in . mad24. d = t<31.u32.c.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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// cnt is . For .b32 popc.b32. cnt.u32 PTX ISA Notes Target ISA Notes Examples Table 40. clz requires sm_20 or later.b32 type.0. 2010 .b64 type.u32 Semantics 74 January 24. inclusively. // cnt is . d = 0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. a.type = { . } Introduced in PTX ISA version 2. .b32.PTX ISA Version 2.b64 d.b64 }. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. cnt. . while (a != 0) { if (a&0x1) d++.b64 d. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. } else { max = 64.0 Table 39. d = 0. the number of leading zeros is between 0 and 32.type d. popc.type d. a. the number of leading zeros is between 0 and 64. For . clz.type = { . . a. X. inclusively. mask = 0x80000000. popc Syntax Integer Arithmetic Instructions: popc Population count.0. a. a = a >> 1. X.b64 }. .type == . } while (d < max && (a&mask == 0) ) { d++. popc requires sm_20 or later.b32) { max = 32.b32 clz. if (. mask = 0x8000000000000000. popc. a = a << 1.

d = -1. a.u32 d. a.type = { . and operand d has type .u32 January 24. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. bfind returns the bit position of the most significant “1”.0. bfind returns 0xFFFFFFFF if no non-sign bit is found. 2010 75 .s64 cnt. If .shiftamt && d != -1) { d = msb .s32. i--) { if (a & (1<<i)) { d = i. X.u32. } } if (.Chapter 8. break.shiftamt is specified. i>=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfind. a. Semantics msb = (.shiftamt. . For unsigned integers.type d. for (i=msb. For signed integers. bfind requires sm_20 or later. .u32 || . .s64 }. d.s32) ? 31 : 63. .type==.u32. bfind. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.shiftamt. Operand a has the instruction type. // cnt is . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type bfind. Instruction Set Table 41.d. Description Find the bit position of the most significant non-sign bit in a and place the result in d.u64.type==. bfind.

a. brev. brev requires sm_20 or later.b32) ? 31 : 63.type = { . .0 Table 42. i++) { d[i] = a[msb-i].0. i<=msb.b64 }.type d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a.PTX ISA Version 2. .b32 d. brev. 2010 . Description Semantics Perform bitwise reversal of input. 76 January 24. for (i=0.b32. msb = (. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.type==.

. . the result is zero. The destination d is padded with the sign bit of the extracted field.a. c.u32 || .u32. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. if (.type==. The sign bit of the extracted field is defined as: .u32 || . bfe.type==.start. pos = b. bfe. Semantics msb = (.0.u32.s64 }. .s32.u64.len.b32 d.u64 || len==0) sbit = 0.type d. 2010 77 .type==. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. . b. Instruction Set Table 43. . Operands a and d have the same type as the instruction type.u32. else sbit = a[min(pos+len-1. for (i=0.msb)].s32. Description Extract bit field from a and place the zero or sign-extended result in d. i<=msb.s32) ? 31 : 63.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.type==. d = 0. a. If the start position is beyond the msb of the input. Source b gives the bit field starting bit position. .u64: . bfe requires sm_20 or later. and operands b and c are type . January 24. and source c gives the bit field length in bits.Chapter 8. the destination d is filled with the replicated sign bit of the extracted field. otherwise If the bit field length is zero.type = { . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. len = c.

and place the result in f. If the bit field length is zero. the result is b.a. Description Align and insert a bit field from a into b. the result is b. b. 2010 . Source c gives the starting bit position for the insertion. and source d gives the bit field length in bits. and f have the same type as the instruction type. and operands c and d are type . bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.b32. If the start position is beyond the msb of the input. Semantics msb = (.0 Table 44. i<len && pos+i<=msb.0. i++) { f[pos+i] = a[i]. .type = { .b64 }.b32) ? 31 : 63. bfi. .b.type f. pos = c. f = b.b32 d.PTX ISA Version 2. b. a. d. Operands a.type==. bfi. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c. 78 January 24.u32. for (i=0.start. bfi requires sm_20 or later.len. len = d.

b2 source select c[11:8] d. prmt. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). .b4e. c. b0}}.b1 source select c[7:4] d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. b5.f4e. . prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. msb=1 means replicate the sign. the four 4-bit values fully specify an arbitrary byte permute. msb=0 means copy the literal value. . For each byte in the target register. Description Pick four arbitrary bytes from two 32-bit registers. a 4-bit selection value is defined.ecl. as a 16b permute code. The bytes in the two source registers are numbered from 0 to 7: {b. and reassemble them into a 32-bit destination register.Chapter 8. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b1. b2. Note that the sign extension is only performed as part of generic form. default mode index d.ecr.rc8. The msb defines if the byte value should be copied. b. .mode = { .mode} d.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. 2010 79 . the permute control consists of four 4-bit selection values.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b32{. Instruction Set Table 45. a.b3 source select c[15:12] d. {b3. In the generic form (no mode specified). b6.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. .rc16 }. a} = {{b7. b4}. Thus.

2010 . r1. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. 80 January 24. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3.b32 prmt.f4e r1. r2. ctl[0]. r2. ctl[2] = (c >> 8) & 0xf.PTX ISA Version 2. tmp[23:16] = ReadByte( mode. tmp[15:08] = ReadByte( mode.b32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } tmp[07:00] = ReadByte( mode. tmp64 ). ctl[2]. ctl[3].0. r4. ctl[3] = (c >> 12) & 0xf. tmp64 ).0 Semantics tmp64 = (b<<32) | a. r3. tmp64 ). prmt. ctl[1] = (c >> 4) & 0xf. ctl[1]. tmp64 ). prmt requires sm_20 or later. tmp[31:24] = ReadByte( mode. r4. r3.

f64 register operands and constant immediate values.f32 and .2.Chapter 8. Floating-Point Instructions Floating-point instructions operate on .7. Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .

rp .cos.min.f64 {abs. sub. . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f32 are the same.f32 rsqrt.sub.f32 {add.sat Notes If no rounding modifier is specified.ex2}.PTX ISA Version 2.f64 {sin.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 .approx.0 The following table summarizes floating-point instructions in PTX.rnd. Double-precision instructions support subnormal inputs and results.rnd. Table 46.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.rnd. mul.f32 {div.lg2.rcp. .rnd.neg.f64 mad.f64 div. {add.target sm_20 mad.rnd. and mad support saturation of results to the range [0.sqrt}.target sm_20 .rm . 2010 .neg.f64 are the same.rnd.f64 and fma.mul}.sqrt}.approx.f32 {div. Single-precision add.rz . default is .max}. Instruction Summary of Floating-Point Instructions .ftz . default is .f64 rsqrt.0].f32 {div.target sm_1x No rounding modifier.rcp. The optional . 82 January 24. No rounding modifier. {mad.full. 1.sqrt}. If no rounding modifier is specified.fma}. NaN payloads are supported for double-precision instructions.f32 {abs. Note that future implementations may support NaN payloads for single-precision instructions.approx. with NaNs being flushed to positive zero.rn and instructions may be folded into a multiply-add.rn and instructions may be folded into a multiply-add.mul}.rcp.fma}. but single-precision instructions return an unspecified NaN.approx.f32 {mad. so PTX programs should not rely on the specific single-precision NaNs being generated.0.min.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.sub.max}.32 and fma.rn .

. testp. Introduced in PTX ISA version 2. copysign.f64 isnan.op.f32 copysign. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. C. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Table 48. .f32 testp. . testp requires sm_20 or later.notanumber. true if the input is a subnormal number (not NaN.number.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.type d. z.type . copysign. . B.f64 x.Chapter 8.notanumber. . .subnormal }. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.f32.finite testp. not infinity). testp. 2010 83 . copysign requires sm_20 or later.0. not infinity) As a special case.normal. Instruction Set Table 47.f32.number testp. // result is . testp Syntax Floating-Point Instructions: testp Test floating-point property. and return the result as d.f64 }. b. . a.notanumber testp.normal testp. positive and negative zero are considered normal numbers.type = { .infinite testp. A. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. y. January 24. .infinite.op p.pred = { . X.infinite. . f0.finite. testp.type = { .0.f64 }. p. a.

f64 requires sm_13 or later.rn mantissa LSB rounds to nearest even .rz available for all targets . add{.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. a. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f2.f32 f1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. requires sm_13 for add. b. Rounding modifiers have the following target requirements: . add.ftz}{.ftz.rz mantissa LSB rounds towards zero . Description Semantics Notes Performs addition and writes the resulting value into a destination register. Rounding modifiers (default is . . add. sm_1x: add. In particular.f32.rz.0.PTX ISA Version 2. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64. .rm mantissa LSB rounds towards negative infinity .sat. 1.rnd = { .ftz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. a. add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. add Syntax Floating-Point Instructions: add Add two values.f32 clamps the result to [0.f64 supports subnormal numbers.rp }.0].rm. 84 January 24. . Saturation modifier: . . .f32 add{. b.rnd}.rp for add. add.0 Table 49.rnd}{.0. 2010 .rn): . d = a + b.f32 supported on all target architectures. . NaN results are flushed to +0. d.0f.f64 d.f3. add.rm.sat}.rn. subnormal numbers are supported.rz. requires sm_20 Examples @p add.rn.

January 24.f32 sub{. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rz available for all targets .f32 supported on all target architectures.rp }. b.f2.rm.rnd = { . . requires sm_20 Examples sub. NaN results are flushed to +0.sat}. .rn.f32 flushes subnormal inputs and results to sign-preserving zero. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Rounding modifiers (default is . sub. Rounding modifiers have the following target requirements: .rn): . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.0. sub Syntax Floating-Point Instructions: sub Subtract one value from another.f64.f32. .f32 c.rz.ftz.rm mantissa LSB rounds towards negative infinity . .rz mantissa LSB rounds towards zero .0f. sub.Chapter 8. sub.sat.rn mantissa LSB rounds to nearest even . . Saturation modifier: sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd}. d.b. Instruction Set Table 50.rnd}{. .f32 clamps the result to [0.f32 f1. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 1. a.f64 requires sm_13 or later.rn.f64 supports subnormal numbers. b. requires sm_13 for sub. sub{. In particular.a. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.b.0]. sm_1x: sub. sub.ftz.rn. subnormal numbers are supported.ftz}{. 2010 85 .rp for sub.f32 flushes subnormal inputs and results to sign-preserving zero.rm. d = a .f64 d.0.f3. sub. a.

all operands must be the same size.rz.f32 clamps the result to [0.0 Table 51. mul.0f. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .f64.f32 circumf.PTX ISA Version 2. d = a * b.rp }.f32 supported on all target architectures.rp for mul.rn mantissa LSB rounds to nearest even .rnd = { . subnormal numbers are supported.sat}.rnd}. 1.rn.ftz. . . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.ftz.rn. . In particular.rm mantissa LSB rounds towards negative infinity .rm. mul Syntax Floating-Point Instructions: mul Multiply two values. a. Rounding modifiers have the following target requirements: . For floating-point multiplication. mul.f32 flushes subnormal inputs and results to sign-preserving zero.radius.f64 supports subnormal numbers. Saturation modifier: mul. mul. sm_1x: mul. Rounding modifiers (default is . . b. mul. Description Semantics Notes Compute the product of two values. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. a. b.rz mantissa LSB rounds towards zero . mul{. .f64 d. requires sm_20 Examples mul.rm.f32 mul{.f64 requires sm_13 or later.sat.rz available for all targets . 2010 . d.f32 flushes subnormal inputs and results to sign-preserving zero.0].pi // a single-precision multiply 86 January 24.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. requires sm_13 for mul.rnd}{.f32. NaN results are flushed to +0.ftz}{. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.0.rn): .0.

1. fma. Saturation: fma. c.rp }. The resulting value is then rounded to double precision using the rounding mode specified by .rz mantissa LSB rounds towards zero .ftz.Chapter 8. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. .0]. subnormal numbers are supported. fma. sm_1x: fma.rnd. PTX ISA Notes Target ISA Notes Examples January 24. d.rnd.f32 clamps the result to [0.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. d = a*b + c. c.f32 introduced in PTX ISA version 2.b.rm.f64 w.f64. fma. @p fma.rn mantissa LSB rounds to nearest even .f64 requires sm_13 or later.rn. fma.a.0.f32 requires sm_20 or later. b.sat. again in infinite precision.y.c. Instruction Set Table 52. b. NaN results are flushed to +0.f64 is the same as mad.rn. fma.f64 d.0f.f64 supports subnormal numbers.rnd. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add. .sat}. . fma.x.rnd{.rz. .f32 fma.f32 fma.rn.4. fma. again in infinite precision. The resulting value is then rounded to single precision using the rounding mode specified by .f32 computes the product of a and b to infinite precision and then adds c to this product. a. a.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz. fma.f32 is unimplemented in sm_1x.0. 2010 87 .f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { . Rounding modifiers (no default): .z.ftz}{. d.f64 introduced in PTX ISA version 1. fma.

The resulting value is then rounded to double precision using the rounding mode specified by . and then writes the resulting value into a destination register.f32 flushes subnormal inputs and results to sign-preserving zero.0 devices. b. For . fma. In this case. The exception for mad. subnormal numbers are supported.rn. where the mantissa can be rounded and the exponent will be clamped. For . Saturation modifier: mad.0. a.f64 computes the product of a and b to infinite precision and then adds c to this product. mad. .f32 mad. mad{.ftz.sat}.0f. c. a.ftz. mad. 1.rnd = { . Note that this is different from computing the product with mul. a.f32. mad.f32 mad.sat.rnd{. . 88 January 24.e. the treatment of subnormal inputs and output follows IEEE 754 standard.target sm_13 and later . // . again in infinite precision. again in infinite precision.rm mantissa LSB rounds towards negative infinity .rn. mad.f64 computes the product of a and b to infinite precision and then adds c to this product. The resulting value is then rounded to double precision using the rounding mode specified by . Description Semantics Notes Multiplies two values and adds a third.rnd.f64 is the same as fma.f32).f32 clamps the result to [0.rz mantissa LSB rounds towards zero . c.f32 is when c = +/-0. mad. mad. When JIT-compiled for SM 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. d = a*b + c.rz. but the exponent is preserved. mad.f32 is identical to the result computed using separate mul and add instructions.0 Table 53.. mad. Unlike mad. b.sat}. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. The resulting value is then rounded to single precision using the rounding mode specified by . // . mad.target sm_1x: mad.rm.PTX ISA Version 2. sm_1x: mad. // .f64 d.f64 supports subnormal numbers.f32 is implemented as a fused multiply-add (i.ftz}{.rnd.f64}.rp }. .{f32.target sm_1x d.target sm_20: mad.rnd.target sm_20 d.f32 flushes subnormal inputs and results to sign-preserving zero.0].f64.f32 computes the product of a and b at double precision. NaN results are flushed to +0. again in infinite precision. and then the mantissa is truncated to 23 bits.f32 computes the product of a and b to infinite precision and then adds c to this product.rn mantissa LSB rounds to nearest even .0.f64} is the same as fma.rnd. c.ftz}{.{f32. Rounding modifiers (no default): . 2010 . b.

rp for mad.. requires sm_20 Examples @p mad. Target ISA Notes mad. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rn. 2010 89 .f64. a rounding modifier is required for mad.a. Legacy mad.rp for mad.rn.rz. In PTX ISA versions 1.0.f64.f32 for sm_20 targets.Chapter 8. Rounding modifiers have the following target requirements: .f64 requires sm_13 or later.f32 d. requires sm_13 . a rounding modifier is required for mad.b.f64 instructions having no rounding modifier will map to mad..rm.rz. In PTX ISA versions 2.. mad.f32. January 24.rn.0 and later.f32 supported on all target architectures.4 and later.f64..c.rm...

d. but is not fully IEEE 754 compliant and does not support rounding modifiers. div. a. approximate single-precision divides: div.4. 2010 .f64. b. . .0 Table 54.rz mantissa LSB rounds towards zero . Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn.f64 requires sm_13 or later.approx.rn mantissa LSB rounds to nearest even .ftz}. div Syntax Floating-Point Instructions: div Divide one value by another. subnormal numbers are supported.full. or . x.rnd.PTX ISA Version 2. The maximum ulp error is 2 across the full range of inputs.f64 requires sm_20 or later.rnd{.rnd is required.approx.rnd.full. .rnd = { .f32 div. div. Description Semantics Notes Divides a by b. div. Explicit modifiers . PTX ISA Notes div.ftz. d = a / b.f64 d.f32 div.f32.rm. a. // // // // fast. b. div. For b in [2-126.ftz.rz. xd.ftz}.f32 div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp}. y. b.3.f64 diam.rn.f64 defaults to div.rn. .rm. Fast.f32 and div. one of . Examples 90 January 24.rn. and rounding introduced in PTX ISA version 1.0. sm_1x: div. b. d.f32 supported on all target architectures. approximate division by zero creates a value of infinity (with same sign as a). div.approx.full. the maximum ulp error is 2.f64 supports subnormal numbers. computed as d = a * (1/b). div. div. . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 requires sm_20 or later.f64 introduced in PTX ISA version 1. d.{rz.f32 div.f32 flushes subnormal inputs and results to sign-preserving zero.f32 defaults to div. full-range approximation that scales operands to achieve better accuracy.rm mantissa LSB rounds towards negative infinity . div.4 and later.full. 2126]. For PTX ISA version 1. zd. Subnormal inputs and results are flushed to sign-preserving zero.f32 implements a relatively fast.full{.circum. Fast.14159.approx. z.f32 div. yd.f32 implements a fast approximation to divide.approx.ftz. a.ftz.ftz}.rp }. div.full. .approx{.approx.f32 flushes subnormal inputs and results to sign-preserving zero. and div. For PTX ISA versions 1. stores result in d.3.f32 and div. a.0 through 1.ftz. Target ISA Notes div.

Chapter 8. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Take the absolute value of a and store the result in d. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f32 supported on all target architectures. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. d. abs. 2010 91 .f32 x.ftz. Table 56.f64 d.f32 supported on all target architectures. abs{. neg. abs. subnormal numbers are supported. a.0. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f0.f0.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: neg. abs. NaN inputs yield an unspecified NaN. NaN inputs yield an unspecified NaN. a.f64 d. January 24. sm_1x: abs. Negate the sign of a and store the result in d.ftz. d.ftz}. neg{. d = -a.f64 requires sm_13 or later.ftz. neg.ftz. a. neg.f64 requires sm_13 or later.f32 neg.f32 x.f64 supports subnormal numbers. d = |a|. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 abs. abs.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. neg.0. Subnormal numbers: sm_20: By default. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. subnormal numbers are supported. Instruction Set Table 55.

sm_1x: min.f64 d. a.f32 flushes subnormal inputs and results to sign-preserving zero. a.f64 supports subnormal numbers. @p min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 . b.f64 z.c. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 92 January 24. b. Store the maximum of a and b in d.f64 d.f1.ftz}. b.f64 requires sm_13 or later.ftz. max{.0.f32 supported on all target architectures. a.f2. d.ftz.ftz}.f32 max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b. a. min.c. subnormal numbers are supported.ftz. min.f64 f0. b.f32 min.z. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f64 requires sm_13 or later.PTX ISA Version 2.b.f32 flushes subnormal inputs and results to sign-preserving zero. b. max. d. min.f64 supports subnormal numbers. max.0.x. Table 58. sm_1x: max.0 Table 57.b.f32 supported on all target architectures. a. d d d d = = = = NaN. (a < b) ? a : b.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 max. subnormal numbers are supported. d d d d = = = = NaN. (a > b) ? a : b. max. min.f32 min. Store the minimum of a and b in d. a. max. max. min{.

0 +subnormal +Inf NaN Result -0. a.f32 rcp. Target ISA Notes rcp. one of .ftz were introduced in PTX ISA version 1.approx.approx.f32 flushes subnormal inputs and results to sign-preserving zero. and rcp. General rounding modifiers were added in PTX ISA version 2. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . store result in d. rcp.rm. xi.ftz}.x.f32.rn.rn. The maximum absolute error is 2-23.0 +0.rz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz mantissa LSB rounds towards zero .f64 defaults to rcp.rnd = { .approx and . a.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . rcp.rnd.ftz.approx{. Instruction Set Table 59. Input -Inf -subnormal -0.0 over the range 1. d.f64 requires sm_20 or later.0 -Inf -Inf +Inf +Inf +0.f64 ri.ftz. . a.rnd{.f32 and rcp.f32 rcp.f32 supported on all target architectures.f64 requires sm_13 or later. Examples January 24.f32 rcp.0. // fast. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f64 supports subnormal numbers. d. sm_1x: rcp.rp }. rcp.4 and later.r. rcp.rn.ftz}.rn.f32 rcp. Description Semantics Notes Compute 1/a. .0 through 1. rcp.rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero. rcp. PTX ISA Notes rcp.approx.f32 requires sm_20 or later. For PTX ISA version 1.approx or . subnormal numbers are supported. rcp. .rm.0-2.rm mantissa LSB rounds towards negative infinity .rp}.approx.{rz.rn. rcp. d = 1 / a.ftz.rnd.x.Chapter 8. xi.f64 d.0. rcp.ftz.f64.0.rn.f64 introduced in PTX ISA version 1. rcp.f32 implements a fast approximation to reciprocal.f32 defaults to rcp.3.4.rnd is required. 2010 93 . For PTX ISA versions 1.f64 and explicit modifiers .

f32 and sqrt.f64 requires sm_20 or later. Description Semantics Notes Compute sqrt(a).ftz. store in d. sqrt. a.approx. PTX ISA Notes sqrt.PTX ISA Version 2. . // fast. For PTX ISA versions 1.f64 r. .3.4 and later.f64.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .0 Table 60.approx{.x.approx. // IEEE 754 compliant rounding d.f32 flushes subnormal inputs and results to sign-preserving zero.0.rn mantissa LSB rounds to nearest even .0 -0. sqrt. sqrt.rnd is required.rp }.rn.0 through 1. one of .rz mantissa LSB rounds towards zero .f32 sqrt.0.rn.f64 and explicit modifiers .rm.0 +0.ftz were introduced in PTX ISA version 1.rm.ftz}. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. d = sqrt(a).approx.f64 defaults to sqrt.rm mantissa LSB rounds towards negative infinity .f32 sqrt.f32. sqrt. a.approx or . sm_1x: sqrt.f32 implements a fast approximation to square root.rnd.f64 introduced in PTX ISA version 1.f64 requires sm_13 or later. sqrt.f64 supports subnormal numbers. For PTX ISA version 1. // IEEE 754 compliant rounding .f32 is TBD.approx and .0 +0. sqrt.rn. 2010 .rnd = { . Target ISA Notes sqrt.ftz}.x.rz.ftz.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. .rnd{. The maximum absolute error for sqrt.x.approx. subnormal numbers are supported.{rz.rn. a. sqrt.rn. and sqrt.approx. sqrt.f32 requires sm_20 or later. General rounding modifiers were added in PTX ISA version 2.f32 sqrt. r. Examples 94 January 24. approximate square root d.0 +subnormal +Inf NaN Result NaN NaN -0.f64 d. sqrt.f32 sqrt. r.rp}.f32 defaults to sqrt.rnd.rn.0 +0. Input -Inf -normal -subnormal -0.f32 supported on all target architectures.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.4. sqrt.ftz.

4 and later. Compute 1/sqrt(a). d.f64 is emulated in software and are relatively slow.f64 requires sm_13 or later.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt. 2010 95 . rsqrt.f32.f32 defaults to rsqrt.approx. For PTX ISA version 1.approx implements an approximation to the reciprocal square root.f64 d. rsqrt. X. PTX ISA Notes rsqrt.f32 is 2-22.approx.approx and .approx. store the result in d.Chapter 8.0 +0. subnormal numbers are supported. rsqrt.f64 isr. rsqrt. d = 1/sqrt(a). the .f32 and rsqrt. Explicit modifiers .f64 supports subnormal numbers.f64 were introduced in PTX ISA version 1.ftz}. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 NaN The maximum absolute error for rsqrt. Input -Inf -normal -subnormal -0. For PTX ISA versions 1.0 through 1.f64. The maximum absolute error for rsqrt. rsqrt. a.ftz. a.0.approx. rsqrt.approx.4 over the range 1.f32 rsqrt.approx modifier is required.3. x. and rsqrt. Note that rsqrt. January 24.ftz were introduced in PTX ISA version 1.0.f64 defaults to rsqrt. Subnormal numbers: sm_20: By default. sm_1x: rsqrt.0-4.f32 rsqrt.f32 supported on all target architectures. ISR.f64 is TBD.4.ftz. Target ISA Notes Examples rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. Instruction Set Table 61.approx.approx{.

For PTX ISA version 1. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.ftz.f32 implements a fast approximation to sine.4.0 NaN NaN The maximum absolute error is 2-20.ftz introduced in PTX ISA version 1. subnormal numbers are supported.ftz}.ftz. sin.PTX ISA Version 2.ftz. a.0 +0. 2010 .0 through 1. Input -Inf -subnormal -0. the .f32 sa.approx modifier is required.approx and . a.9 in quadrant 00. sin.0 +subnormal +Inf NaN Result NaN -0.f32 d. sm_1x: Subnormal inputs and results to sign-preserving zero.0 Table 62.approx{. Explicit modifiers . For PTX ISA versions 1. d = sin(a).f32 flushes subnormal inputs and results to sign-preserving zero.0 +0.4 and later.approx.3.f32. PTX ISA Notes sin. sin. sin. 96 January 24.f32 introduced in PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures.f32 defaults to sin. Subnormal numbers: sm_20: By default. sin.0 +0.0. Find the sine of the angle a (in radians).0 -0.approx.approx.

a. PTX ISA Notes cos.0 NaN NaN The maximum absolute error is 2-20.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 63. subnormal numbers are supported.approx.approx{.f32.0 +1.4.ftz. cos.0 +1.0 +0.f32 introduced in PTX ISA version 1.3. January 24. cos. cos.0 +1.4 and later.9 in quadrant 00.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 defaults to cos. For PTX ISA versions 1.f32 ca. Target ISA Notes Examples Supported on all target architectures. Find the cosine of the angle a (in radians).0.f32 d. Explicit modifiers .0 +subnormal +Inf NaN Result NaN +1. the .approx modifier is required.f32 implements a fast approximation to cosine. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.approx and .ftz}.ftz. For PTX ISA version 1. cos. 2010 97 . Input -Inf -subnormal -0. d = cos(a). a.approx.approx. cos.Chapter 8.ftz introduced in PTX ISA version 1.0 through 1. Subnormal numbers: sm_20: By default.

lg2.approx.ftz. 98 January 24.f32. For PTX ISA version 1.f32 la. d = log(a) / log(2). lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.approx and .6 for mantissa.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero.approx modifier is required. subnormal numbers are supported.ftz.ftz introduced in PTX ISA version 1.approx{. Subnormal numbers: sm_20: By default. a.ftz.4.approx.f32 implements a fast approximation to log2(a). The maximum absolute error is 2-22.f32 defaults to lg2.PTX ISA Version 2. a.0 Table 64.f32 introduced in PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +0.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. lg2. Explicit modifiers .0.3. lg2.f32 Determine the log2 of a. the . lg2.approx. Input -Inf -subnormal -0. For PTX ISA versions 1. lg2.4 and later. PTX ISA Notes lg2. 2010 . Target ISA Notes Examples Supported on all target architectures.ftz}.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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pred variables. then the result of these comparisons is true.u64.BoolOp{. p. le.f64 }. nan The Boolean operator BoolOp(A. neu. . gt.CmpOp.a. a. @q setp.0. setp.f32. hi.dtype.f32 flushes subnormal inputs to sign-preserving zero.b64.b.f32 comparisons.0 Table 67. The destinations p and q must be . num returns true if both operands are numeric values (not NaN). .ftz. ls. A related value computed using the complement of the compare result is written to the second destination operand.f64 source type requires sm_13 or later. setp. The comparison operator is a suffix on the instruction. and can be one of: eq. unordered versions are included: equ.type setp. Applies to all numeric types. If both operands are numeric values (not NaN). . 2010 . xor. respectively. Semantics t = (a CmpOp b) ? 1 : 0.s32.f32 flushes subnormal inputs to sign-preserving zero. ne.B) is one of: and. geu. If either operand is NaN. setp.PTX ISA Version 2. and higher-or-same may be used instead of lt.u16. gt. and nan returns true if either operand is NaN. p[|q]. leu. The signed and unsigned comparison operators are eq.s32 setp.f64 supports subnormal numbers. 102 January 24.ftz}. geu. p = BoolOp(t.b32.dtype. gtu. le. sm_1x: setp.lt. q = BoolOp(!t.eq.r.and. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.u32. b.b16.n. hs equ. This result is written to the first destination operand. num. b. setp with . {!}c.CmpOp{. gt. . then these comparisons have the same result as their ordered counterparts. ls. gtu. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and (optionally) combine this result with a predicate value by applying a Boolean operator. c). ge. . hi.type . lt. loweror-same. or. p[|q]. Subnormal numbers: sm_20: By default.s16. ne. gt.u32 p|q. . the comparison operators lo. ge. .ftz applies only to .ftz}. . higher. leu. . If either operand is NaN.s64. ge.i. subnormal numbers are supported. ltu. le. lt. and hs for lower. lt. a. bit-size comparisons are eq and ne. The untyped. Modifier .type = { . ge. To aid comparison operations in the presence of NaN values. the result is false. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. For unsigned values.dtype. c). ne. . ltu. lo. neu. Integer Notes Floating Point Notes The ordered comparisons are eq. le.

f32 comparisons. a.s16.s16.f64 }.dtype.b16. a.f64 }. slct.s32. .f64 requires sm_13 or later.f32 flushes subnormal values of operand c to sign-preserving zero.g.u16.b64.f64 requires sm_13 or later. a.dtype. selp.s32. a. b.f32 d. a is stored in d. If c is True. d = (c >= 0) ? a : b. If c ≥ 0.u16. @q selp. based on the value of the predicate source operand.xp.s64. b otherwise.u64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. z. b. .u64. Operands d. slct. Instruction Set Table 68.ftz. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. selp Syntax Comparison and Selection Instructions: selp Select between source operands. slct. .u32.b32. .Chapter 8. Description Conditional selection.f32 A. and b are treated as a bitsize type of the same width as the first instruction type. . otherwise b is stored in d. fval. and operand a is selected. C.f32 r0.type = { . slct. 2010 103 . . . . b. Modifier .ftz applies only to .dtype.f32. Table 69. The selected input is copied to the output without modification. c. . Semantics Floating Point Notes January 24. .0. Operands d. . B.u32. negative zero equals zero. . f0.type d.f32 comparisons.b32. Operand c is a predicate. Introduced in PTX ISA version 1.u64. a. d = (c == 1) ? a : b. the comparison is unordered and operand b is selected.s64.r. . and b must be of the same type. slct. . y. If operand c is NaN.0. . val.ftz}. d. Subnormal numbers: sm_20: By default. selp. c.t. . .ftz.s32 selp.s32 slct{.f32 flushes subnormal values of operand c to sign-preserving zero.b64.dtype. . c.p. sm_1x: slct.x. operand c must match the second instruction type. slct Syntax Comparison and Selection Instructions: slct Select one source operand. . and operand a is selected. based on the sign of the third operand.dtype = { . subnormal numbers are supported.u32. a is stored in d.s32 x. .f32. For . . .b16.

xor. or. performing bit-wise operations on operands of any type.PTX ISA Version 2. and not also operate on predicates.4. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. This permits bit-wise operations on floating point values without having to define a union to access the bits.7. Instructions and. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.0 8. provided the operands are of the same size.

Allowed types include predicate registers. Instruction Set Table 70.q. .r.type d. .Chapter 8. or.b32 mask mask. The size of the operands must match.pred p. Supported on all target architectures. b. 2010 105 . . .b16.b32 x. Introduced in PTX ISA version 1. . . and Syntax Logic and Shift Instructions: and Bitwise AND. but not necessarily the type.type d.0.0x80000000.pred. .fpvalue. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b16. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.0x00010001 or.pred. b. The size of the operands must match. but not necessarily the type.b64 }. a.0. a. or Syntax Logic and Shift Instructions: or Bitwise OR.q. Introduced in PTX ISA version 1. Table 71. Supported on all target architectures. January 24.r. .type = { .b64 }. d = a & b.type = { . and. d = a | b. Allowed types include predicate registers. sign.b32.b32.b32 and. and. or.

. d. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b64 }. . xor.0 Table 72.r.pred. a. The size of the operands must match.PTX ISA Version 2. Table 74.b16. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). .0x0001.0. d = (a==0) ? 1 : 0.type d.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.pred p. d = ~a. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.b16 d. not. Allowed types include predicate registers. Supported on all target architectures. The size of the operands must match.b16.b32. but not necessarily the type.b32. . d = a ^ b.b32. . not.type = { .type d.0. cnot.b64 }.pred. but not necessarily the type. Introduced in PTX ISA version 1. not. 2010 . a. .q.x.q. Table 73. xor. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. one’s complement.type d.0.a. Supported on all target architectures. but not necessarily the type.type = { . . . cnot.b32 d. a. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b16. Allowed types include predicates. The size of the operands must match. b. Supported on all target architectures.b32 mask.mask. .type = { . not Syntax Logic and Shift Instructions: not Bitwise negation. 106 January 24.b32 xor. .

regardless of the instruction type. . . i. . regardless of the instruction type.b32 q. PTX ISA Notes Target ISA Notes Examples Table 76. 2010 107 . Supported on all target architectures. The sizes of the destination and first source operand must match.a. . . The b operand must be a 32-bit value.u16 shr.i. Introduced in PTX ISA version 1. shl Syntax Logic and Shift Instructions: shl Shift bits left. . shl.1.b32. sign or zero fill on left. k. but not necessarily the type. zero-fill on right. Introduced in PTX ISA version 1. Signed shifts fill with the sign bit.type d.s32 shr. .s32. Shift amounts greater than the register width N are clamped to N.j. but not necessarily the type. The b operand must be a 32-bit value. Shift amounts greater than the register width N are clamped to N.2. The sizes of the destination and first source operand must match.type = { .b64.u16. a. d = a << b.b16. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.u32.type d. b.b16 c. a. . shl.u64. unsigned and untyped shifts fill with 0. b.i. . shr.b32.0.b16.b64 }. PTX ISA Notes Target ISA Notes Examples January 24. shr. shr Syntax Logic and Shift Instructions: shr Shift bits right.2.a. Instruction Set Table 75.type = { .s64 }. Bit-size types are included for symmetry with SHL. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.0. . . .Chapter 8. d = a >> b.s16. Supported on all target architectures.

and st operate on both scalar and vector types. and from state space to state space.5. Instructions ld. The cvta instruction converts addresses between generic and global. Data Movement and Conversion Instructions These instructions copy data from place to place.7. local. possibly converting it from one format to another.PTX ISA Version 2. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. st. ld. and sust support optional cache operations. ldu. 2010 . prefetchu isspacep cvta cvt 108 January 24. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. suld. mov. or shared state spaces.0 8.

which allocates cache lines in all levels (L1 and L2) with normal eviction policy.ca. but multiple L1 caches are not coherent for global data. the second thread may get stale L1 cache data.5. bypassing the L1 cache. The ld.cv Cache as volatile (consider cached system memory lines stale. and cache only in the L2 cache.cs) on global addresses. Cache Operators PTX 2. As a result of this request.cg to cache loads only globally. likely to be accessed again.cv to a frame buffer DRAM address is the same as ld.cs Cache streaming.lu operation. 2010 109 .Chapter 8. The ld. Global data is coherent at the L2 level.lu Last use. it performs the ld. the cache operators have the following definitions and behavior. evict-first. Operator .cs. when applied to a local address. The compiler / programmer may use ld. When ld. Table 77. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. The cache operators require a target architecture of sm_20 or later.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. A ld. .1. The ld.cs is applied to a Local window address.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.7. if the line is fully covered. The default load instruction cache operation is ld.lu instruction performs a load cached streaming operation (ld.lu load last use operation.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. to allow the thread program to poll a SysMem location written by the CPU. The ld. invalidates (discards) the local L1 line following the load. If one thread stores to global memory via one L1 cache. January 24. rather than the data stored by the first thread.ca. . not L1).ca loads cached in L1.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Instruction Set 8. .cg Cache at global level (cache in L2 and below. fetch again). For sm_20 and later. and a second thread loads that address via a second L1 cache with ld. Use ld. likely to be accessed once.0 introduces optional cache operators on load and store instructions. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. . any existing cache lines that match the requested address in L1 will be evicted.

cs Cache streaming. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. which writes back cache lines of coherent cache levels with normal eviction policy. 110 January 24.wt Cache write-through (to system memory).cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. and discard any L1 lines that match. . The st. In sm_20. not L1).cg is the same as st.ca.PTX ISA Version 2. .cg to local memory uses the L1 cache. However.wb could write-back global store data from L1. bypassing its L1 cache. Operator . and cache only in the L2 cache. st. to allow a CPU program to poll a SysMem location written by the GPU with st. . Future GPUs may have globally-coherent L1 caches. but st.0 Table 78.wt. Global stores bypass L1.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.ca loads. Addresses not in System Memory use normal write-back. regardless of the cache operation. rather than get the data from L2 or memory stored by the first thread. and marks local L1 lines evict-first. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. in which case st. If one thread stores to global memory.wt store write-through operation applied to a global System Memory address writes through the L2 cache.cg Cache at global level (cache in L2 and below. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. bypassing the L1 cache. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.cg to cache global store data only globally.wb for global data. The default store instruction cache operation is st.wb. The st. 2010 . likely to be accessed once. and a second thread in a different SM later loads from that address via a different L1 cache with ld. Use st. the second thread may get a hit on stale L1 cache data.

mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.f64 requires sm_13 or later. variable in an addressable memory space. local. Semantics d = a.s32. The generic address of a variable in global. Introduced in PTX ISA version 1. . . avar.Chapter 8. myFunc.0.b32. ptr. and . u. or function name.v. Write register d with the value of a.shared state spaces.local. // address is non-generic.type d. alternately.u32. Operand a may be a register.. .f32.u32 d.global. sreg. mov. .1.pred.a.s16. immediate. or shared state space.type mov. label.const.u16 mov.type mov.type = { .u16. within the variable’s declared state space Notes Although only predicate and bit-size types are required. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. d = sreg. local.e. For variables declared in . the generic address of a variable declared in global. . . the address of the variable in its state space) into the destination register. the parameter will be copied onto the stack and the address will be in the local state space. label. or shared state space may be taken directly using the cvta instruction.f64 }.. ptr. mov places the non-generic address of the variable (i. Note that if the address of a device function parameter is moved to a register. d. i. addr. . // get address of variable // get address of label or function . k.b64.s64. 2010 111 .f32 mov. Instruction Set Table 79. . a. . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. Description . d = &avar.type mov.u64. A. A[5].b16.u32 mov. special register. Take the non-generic address of a variable in global.f32 mov.u32 mov. mov. mov. . d. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. .0. . local. d = &label. d.e.

w have type ..b}.g.31] } // unpack 16-bit elements from .b have type .z. a[16..b.hi}..7].w << 24) d = a.y } = { a[0.a}.b32 %r1.y.{a.x. d..15] } // unpack 8-bit elements from .b32 { d. Description Write scalar register d with the packed value of vector register a.x.type = { .0 Table 80. a[48. Semantics d = a.b32 mov. .. a[8.z << 16) | (a.b8 r. a.15]. d.y << 8) d = a.y << 16) d = a.w } = { a[0.31].b32. a[32.b32 mov.b64 { d.x.y. d.z.23]. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. a[16.y } = { a[0. d. a[32.x | (a.x | (a..y } = { a[0..x | (a.x. 2010 .x | (a.w } = { a[0. d.b32 // pack four 16-bit elements into . .z..w}.b64 // pack two 32-bit elements into .b16.PTX ISA Version 2.63] } // unpack 16-bit elements from .31] } // unpack 8-bit elements from .b64 112 January 24.y << 32) // pack two 8-bit elements into ..15]. .%r1. d.. or write vector register d with the unpacked values from scalar register a.type d.b16 { d.u8 // unpack 32-bit elements from . a[16.y << 8) | (a.7]. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. {r.u32 x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). d.b64 { d...g. a[8.w << 48) d = a. For bit-size types.. d.15].b32 // pack two 16-bit elements into .x..b16 // pack four 8-bit elements into .x | (a. {lo.y. // // // // a. Supported on all target architectures.b64 }.{x. %r1.y << 16) | (a. %x.31].b64 mov.47]. d.b32 { d.z.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u16 %x is a double.hi are .0.a have type . lo.b. mov.z << 32) | (a.y. mov. a[24.

. .u32.vec = { . A destination register wider than the specified type may be used.cg. .param. an address maps to the corresponding location in local or shared memory.f32. .volatile{.global and . The address size may be either 32-bit or 64-bit. and truncated if the register width exceeds the state space address width for the target architecture.volatile may be used with .0. d. .b8. If no state space is given. . Cache operations are not permitted with ld. i.volatile.type d.s64. The .const space suffix may have an optional bank number to indicate constant banks other than bank zero.u8. ld{.s16.cop}. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. the resulting behavior is undefined.shared spaces to inhibit optimization of references to volatile memory. Instruction Set Table 81. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32 or .ss = { .cv }. Generic addressing and cache operations introduced in PTX ISA 2. an address maps to global memory unless it falls within the local memory window or the shared memory window. In generic addressing. Addresses are zero-extended to the specified width as needed.u64.b16. PTX ISA Notes January 24.reg state space..u16. .vec.ss}. *(immAddr). . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. The address must be naturally aligned to a multiple of the access size. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .ca. .ss}{. . . [a]. .f64 using cvt. Description Load register variable d from the location specified by the source address operand a in specified state space.lu.v2. Semantics d d d d = = = = a. *(a+immOff). // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .s32.cop = { . If an address is not properly aligned. [a]. i.f64 }.const. [a]. perform the load using generic addressing. . or [immAddr] an immediate absolute byte address (unsigned. . for example.e. .f16 data may be loaded using ld.ss}.b16.type ld{.type .vec. d.global.cop}. to enforce sequential consistency between threads accessing shared memory. ld.s8. . . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. and is zeroextended to the destination register width for unsigned and bit-size types. *a.v4 }. Within these windows.volatile introduced in PTX ISA version 1. or the instruction may fault.Chapter 8.local.shared }. d.e. The value loaded is sign-extended to the destination register width for signed integers. Generic addressing may be used with ld.volatile. [a].volatile{. . ld introduced in PTX ISA version 1. 2010 113 . . .1.cs.type ld. ld.0. . 32-bit).b64. an integer or bit-size type register reg containing a byte address. This may be used. 32-bit).ss}{. . .b32. and then converted to .type = { . .

f64 requires sm_13 or later.global. // negative offset %r.s32 ld.%r.f16 d.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[fs].global. // immediate address %r.[p].b32 ld. x.[240].v4.b32 ld.f32.b16 cvt.b64 ld. Q.b32 ld.f32 ld.[p+4].[buffer+64].local. // access incomplete array x.PTX ISA Version 2.[p+-8].local. 2010 .const. d. %r.shared. // load .const[4]. Generic addressing requires sm_20 or later.[a].0 Target ISA Notes ld. ld. Cache operations require sm_20 or later.

. Instruction Set Table 82. A destination register wider than the specified type may be used.f32 d. In generic addressing. an address maps to global memory unless it falls within the local memory window or the shared memory window. The address must be naturally aligned to a multiple of the access size.global. perform the load using generic addressing. If an address is not properly aligned. Introduced in PTX ISA version 2. i. The data at the specified address must be read-only.s8.f64 using cvt. . .e.b16. The addressable operand a is one of: [avar] the name of an addressable variable var.ss}.b32 d.b8. PTX ISA Notes Target ISA Notes Examples January 24.u32. For ldu. or the instruction may fault. i. and then converted to ..u64.f64 }.f16 data may be loaded using ldu. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. The value loaded is sign-extended to the destination register width for signed integers.[p].vec.f32. // load from address // vec load from address .s32. 2010 115 .v4 }. .type d.f32 or . ldu. . Semantics d d d d = = = = a. ldu{. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. *a. and is zeroextended to the destination register width for unsigned and bit-size types.type ldu{. A register containing an address may be declared as a bit-size type or integer type.b64. where the address is guaranteed to be the same across all threads in the warp.v2. only generic addresses that map to global memory are legal.Chapter 8. If no state space is given. the resulting behavior is undefined.[a]. and truncated if the register width exceeds the state space address width for the target architecture. *(immAddr).f64 requires sm_13 or later.e.global. // state space . .u8. d.type = { . [areg] a register reg containing a byte address. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .vec = { . an address maps to the corresponding location in local or shared memory. *(a+immOff). . ldu. ldu.b16. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. 32-bit). Addresses are zero-extended to the specified width as needed. . .global }.[p+4]. . .ss}.b32. 32-bit). The address size may be either 32-bit or 64-bit.global.s64.v4.u16. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [a]. . Within these windows.0. . [a]. . or [immAddr] an immediate absolute byte address (unsigned. ldu.ss = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32 Q.reg state space.s16. .

[a].b8.f64 }.ss}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. 32-bit). an address maps to the corresponding location in local or shared memory. Semantics d = a. i.volatile{.volatile.type st{. or the instruction may fault.vec.s32. st.type st. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.type .wb. . .volatile introduced in PTX ISA version 1.global and .type [a]. . st. The address size may be either 32-bit or 64-bit. *(d+immOffset) = a. the resulting behavior is undefined. The lower n bits corresponding to the instruction-type width are stored to memory.shared }.1. an address maps to global memory unless it falls within the local memory window or the shared memory window.v2. .vec. b. for example. . Generic addressing may be used with st.local.vec . .u64.b64.volatile{. If no state space is given. .0. . A source register wider than the specified type may be used. and truncated if the register width exceeds the state space address width for the target architecture. b.e. Within these windows. perform the store using generic addressing. . 32-bit).cg. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.shared spaces to inhibit optimization of references to volatile memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32. { .s64. PTX ISA Notes Target ISA Notes 116 January 24.type = = = = {. [a]. to enforce sequential consistency between threads accessing shared memory.ss}.PTX ISA Version 2. .cop}.wt }.u16. [a]. st{. *d = a. This may be used. If an address is not properly aligned.volatile. 2010 . Generic addressing requires sm_20 or later. . . .ss . .cs. st introduced in PTX ISA version 1. b. . In generic addressing.e.global. { .s16. Addresses are zero-extended to the specified width as needed. an integer or bit-size type register reg containing a byte address. .0. . st. Generic addressing and cache operations introduced in PTX ISA 2. .v4 }. .. i.0 Table 83. Cache operations are not permitted with st. The address must be naturally aligned to a multiple of the access size.s8.f16 data resulting from a cvt instruction may be stored using st. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Cache operations require sm_20 or later. or [immAddr] an immediate absolute byte address (unsigned. { .f64 requires sm_13 or later. b. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .ss}{.reg state space.u8.cop .b32.cop}.u32.b16. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.volatile may be used with .b16. *(immAddr) = a.ss}{.

[p].a.f32 st. 2010 117 .s32 cvt.b32 st.local.local.%r.a.f32 st.r7.b.v4.s32 st. [fs]. [q+-8]. // negative offset [100].%r.Chapter 8.global.global. [q+4].b16 [a].Q. // %r is 32-bit register // store lower 16 bits January 24.b32 st.f16. // immediate address %r. Instruction Set Examples st.local.

[reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 32-bit). an address maps to global memory unless it falls within the local memory window or the shared memory window. If no state space is given. In generic addressing.L1 [ptr].L1. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. .space = { . prefetchu. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. prefetch.global.local }. or [immAddr] an immediate absolute byte address (unsigned.level = { . Addresses are zero-extended to the specified width as needed. and truncated if the register width exceeds the state space address width for the target architecture.level prefetchu. an address maps to the corresponding location in local or shared memory. 32-bit).space}. The address size may be either 32-bit or 64-bit. prefetch{. the prefetch uses generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. a register reg containing a byte address. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. 118 January 24.e. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. .0. 2010 . Within these windows. // prefetch to data cache // prefetch to uniform cache . [a].L2 }. prefetch and prefetchu require sm_20 or later.PTX ISA Version 2. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. i. and no operation occurs if the address maps to a local or shared memory location. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 84.L1 [addr]. A prefetch into the uniform cache requires a generic address. . in specified state space.L1 [a]. A prefetch to a shared memory location performs no operation.global.

shared.local.u32. p.local isspacep.shared isglbl.size . local. PTX ISA Notes Target ISA Notes Examples Table 86.u64 or cvt. local. or shared address.space.space = { . the generic address of the variable may be taken using cvta.genptr. svar. gptr.global. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. local.local.0. or shared state space. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. The source and destination addresses must be the same size.u64 }.lptr.global.global. 2010 119 . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. // local. Description Convert a global.space. var.global isspacep. islcl. When converting a generic address into a global. local. a. isspacep requires sm_20 or later.shared }. // result is . . . Introduced in PTX ISA version 2.u32 to truncate or zero-extend addresses.local.u32 gptr. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. isspacep.u32 p. A program may use isspacep to guard against such incorrect behavior. lptr. The source address operand must be a register of type .shared }. local.pred . For variables declared in global.to. Take the generic address of a variable declared in global. cvta. or shared state space.u32. Instruction Set Table 85. or vice-versa. p.u64. .pred.Chapter 8. isspacep. // convert to generic address // get generic address of var // convert generic address to global.size cvta. The destination register must be of type . or shared state space to generic.space = { . cvta.size = { . or shared address to a generic address. .u64. cvta. a.0.to. or vice-versa. or shared address cvta. Use cvt.u32 p. . a.size p. // get generic address of svar cvta.u32 or .space p. . cvta requires sm_20 or later. January 24. sptr. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.space. isshrd.

ftz.rpi }.e. Saturation modifier: . Integer rounding modifiers: .dtype = . . . the result is clamped to the destination range by default.atype cvt{.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. . d = convert(a).u16. subnormal inputs are flushed to signpreserving zero. subnormal inputs are flushed to signpreserving zero. . .sat For integer destination types. . sm_1x: For cvt. choosing even integer if source is equidistant between two integers.rni round to nearest integer.irnd = { .rzi.u8. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.frnd}{.ftz modifier may be specified in these cases for clarity. .sat is redundant.s32.dtype. Note: In PTX ISA versions 1.sat}.atype = { .f32.rzi round to nearest integer in the direction of zero . subnormal numbers are supported.frnd = { . .f64 }. The compiler will preserve this behavior for legacy PTX code.s16. .s8.e. . The optional .MAXINT for the size of the operation. a.ftz}{. . Integer rounding is required for float-to-integer conversions.f32 float-tofloat conversions with integer rounding.. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. Note that saturation applies to both signed and unsigned integer types.atype d.f16.irnd}{. 2010 .rn. // integer rounding // fp rounding .rz. For float-to-integer conversions. . .f32. .PTX ISA Version 2. .4 and earlier.f32. .ftz.sat}.sat limits the result to MININT. . d. . i. .0 Table 87.u64.rm. the . i. 120 January 24.ftz.rni. cvt{. and for same-size float-tofloat conversions where the value is rounded to an integer.rmi.f32 float-to-integer conversions and cvt.ftz}{. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. Description Semantics Integer Notes Convert between different types and sizes.u32.rmi round to nearest integer in direction of negative infinity .dtype..dtype.ftz.rp }.f32 float-to-integer conversions and cvt.dtype. .f32 float-tofloat conversions with integer rounding. a.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. Integer rounding is illegal in all other instances. .s64. For cvt.

f32 x.f64 j. // round to nearest int.rn mantissa LSB rounds to nearest even .f64 types. // float-to-int saturates by default cvt. if the PTX .rni.rz mantissa LSB rounds towards zero .sat limits the result to the range [0.s32 f.f32.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).r.4 and earlier.s32. cvt. Floating-point rounding is illegal in all other instances. and cvt. result is fp cvt. .f32.y. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.f32. The result is an integral value.4 or earlier. Floating-point rounding modifiers: .f32.0].y. // note .sat For floating-point destination types.version is 1. 1. . Saturation modifier: . Applies to . cvt to or from . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32 x.ftz behavior for sm_1x targets January 24.Chapter 8. Note: In PTX ISA versions 1.f32 instructions. 2010 121 . cvt. The optional .ftz modifier may be specified in these cases for clarity.0. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . The operands must be of the same size.f64.f16. NaN results are flushed to positive zero.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. and for integer-to-float conversions. Modifier .rm mantissa LSB rounds towards negative infinity . cvt. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. Introduced in PTX ISA version 1.f16. and .f32. Specifically. subnormal numbers are supported.f64 requires sm_13 or later.f32.f16.f32.0. Subnormal numbers: sm_20: By default. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.i. The compiler will preserve this behavior for legacy PTX code. stored in floating-point format.

PTX supports the following operations on texture. // get tex1’s txq. [tex1]. and surfaces.2d. mul. r3.samplerref tsamp1 = { addr_mode_0 filter_mode }.f2}]. div. The advantage of independent mode is that textures and samplers can be mixed and matched. and surface descriptors: • • • Static initialization of texture. r3. the file is assumed to use unified mode.f32 r1. r1.f32 r1. samplers.u32 r5. = nearest width height tsamp1. Texture and Surface Instructions This section describes PTX instructions for accessing textures. Texturing modes For working with textures and samplers. A PTX module may declare only one texturing mode.entry compute_power ( . In the unified mode. } = clamp_to_border.target texmode_independent .texref tex1 ) { txq. [tex1].target options ‘texmode_unified’ and ‘texmode_independent’. sampler.height.f32 r1. r5.PTX ISA Version 2.global . . r5.f32. allowing them to be defined separately and combined at the site of usage in the program. Module-scope and per-entry scope definitions of texture. 122 January 24. but the number of samplers is greatly restricted to 16. cvt. r4. 2010 . r5. and surface descriptors. Ability to query fields within texture. r1.6. {f1. texture and sampler information is accessed through a single . The advantage of unified mode is that it allows 128 samplers. r6.u32 r5. // get tex1’s tex.r3.param . add. PTX has two modes of operation. If no texturing mode is declared. sampler. [tex1.width..texref handle.f32 {r1.7.r2. add. texture and sampler information each have their own handle.b32 r5.0 8. Example: calculate an element’s power contribution as element’s power/total number of elements. and surface descriptors.f32. r2. In the independent mode. sampler. The texturing mode is selected using .f32 r3.. .b32 r6. with the restriction that they correspond 1-to-1 with the 128 possible textures.v4. . sampler. r1.r4}. add. and surface descriptors.

dtype. If no sampler is specified.2d. sampler_x. c].r2.v4. Operand c is a scalar or singleton tuple for 1d textures.dtype = { .geom. The instruction always returns a four-element vector of 32-bit values. A texture base address is assumed to be aligned to a 16-byte address.1d.0.f32 }.v4.s32. . is a two-element vector for 2d textures. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.r2. If an address is not properly aligned. 2010 123 . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.v4 coordinate vectors are allowed for any geometry. // explicit sampler .geom. or the instruction may fault.r4}. . Unified mode texturing introduced in PTX ISA version 1. the square brackets are not required and .btype tex.s32.r3.btype d. .v4.geom = { .r4}.Chapter 8.r3.s32. the sampler behavior is a property of the named texture. {f1}].v4.f3. {f1.dtype. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a. Instruction Set These instructions provide access to texture and surface memory..e.1d.s32. .f32 {r1. b. . An optional texture sampler b may be specified. Notes For compatibility with prior versions of PTX. . c].f4}].5.u32. // Example of independent mode texturing tex. Description Texture lookup using a texture coordinate vector. tex txq suld sust sured suq Table 88. d.3d }.f2.s32 {r1. [a. and is a four-element vector for 3d textures. [tex_a. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples January 24. //Example of unified mode texturing tex.f32 }. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. .btype = { .3d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. tex. [tex_a. where the fourth element is ignored. with the extra elements being ignored. the resulting behavior is undefined. i.

[smpl_B].b32 %r1. d. clamp_ogl.5.depth .width. [tex_A]. Supported on all target architectures.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). addr_mode_1.normalized_coords }. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. clamp_to_edge.squery = { . .samplerref variable. txq. // unified mode // independent mode 124 January 24.width.b32 %r1. . sampler attributes are also accessed via a texref argument.b32 %r1. 2010 . Description Query an attribute of a texture or sampler. txq. Integer from enum { nearest. [a].normalized_coords .addr_mode_0 .b32 d.addr_mode_1 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .width .b32 txq.filter_mode. txq.PTX ISA Version 2. addr_mode_2 }. .filter_mode.height. [a]. .squery. In unified mode. txq. and in independent mode sampler attributes are accessed via a separate samplerref argument.addr_mode_0.addr_mode_0.depth. mirror. linear } Integer from enum { wrap. // texture attributes // sampler attributes .filter_mode . Query: .0 Table 89. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.tquery.height . [tex_A].texref or . Operand a is a .tquery = { .

SNORM. B.v2. // for suld.clamp suld.f32.geom{. where the fourth element is ignored.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. The lowest dimension coordinate represents a sample offset rather than a byte offset.zero }. suld. then .trap introduced in PTX ISA version 1. or .0.5.. A surface base address is assumed to be aligned to a 16-byte address.1d.cs. suld.p is currently unimplemented. // cache operation none.b. suld.p.u32.cv }.dtype. the surface sample elements are converted to .w}]. . If the destination type is .geom . additional clamp modifiers.trap clamping modifier.v4. .b64 }.b supported on all target architectures. .Chapter 8.s32. b].vec. .b. if the surface format contains SINT data.3d requires sm_20 or later.b . . or the instruction may fault. 2010 125 .cop}. .surfref variable. [a.3d.geom{.clamp = = = = = = { { { { { { d.b32. . suld.s32. then .v2. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b32.f32 }.e.dtype.f2.f32 is returned.b8 . and A components of the surface format.clamp. // unformatted d. {f1.clamp field specifies how to handle out-of-bounds addresses: .z. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32.1d. .trap . . Target ISA Notes Examples January 24. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Operand b is a scalar or singleton tuple for 1d surfaces.cop . and the size of the data transfer matches the size of destination operand d.u32 is returned. [a.cop}. then . or . Coordinate elements are of type .v4 }.p.b. .b performs an unformatted load of binary data. .trap. and cache operations introduced in PTX ISA version 2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. suld. Instruction Set Table 90. If the destination base type is .s32.vec . . . the resulting behavior is undefined.trap {r1.trap suld.3d }.dtype . or FLOAT data. // for suld.cg.2d.b64. suld. G.f32 based on the surface format as follows: If the surface format contains UNORM. . if the surface format contains UINT data. i. . . . suld.p requires sm_20 or later.y.f32.f3. If an address is not properly aligned. Cache operations require sm_20 or later. // formatted . {x.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. is a two-element vector for 2d surfaces. b]. size and type conversion is performed as needed to convert from the surface sample format to the destination type.b16. Description Load from surface memory using a surface coordinate vector.u32. and is a four-element vector for 3d surfaces. The . suld. [surf_B.p .s32. suld. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.r2}. [surf_A. Destination vector elements corresponding to components that do not appear in the surface format are not written. {x}].f4}. .v4.ca.p.s32 is returned. sm_1x targets support only the .dtype .clamp .clamp . Operand a is a .b32.

Source elements that do not occur in the surface sample are ignored. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f32.u32.ctype . The size of the data transfer matches the size of source operand c. Operand a is a . {x. .b performs an unformatted store of binary data.zero }.w}].p. . sust. These elements are written to the corresponding surface sample components. {x}].f32} are currently unimplemented.b32.r2}.clamp . . where the fourth element is ignored. . if the surface format contains SINT data.clamp sust.v4 }. sust. or . is a two-element vector for 2d surfaces.5.b64.b supported on all target architectures. and is a four-element vector for 3d surfaces.geom{.e. size and type conversions are performed as needed between the surface sample format and the destination type.trap .cop}. c. The source data is then converted from this type to the surface sample format.0 Table 91. sust.geom . sust Syntax Texture and Surface Instructions: sust Store to surface memory.b32.b. .wb.cop .ctype. sust. b].ctype.trap [surf_A. .trap.u32.f32 is assumed.p. 2010 .PTX ISA Version 2. or FLOAT data. .f32.3d requires sm_20 or later.trap introduced in PTX ISA version 1.b16.y. sm_1x targets support only the .b // for sust.p requires sm_20 or later.geom{.v4. . none.cg.v2. i. .. then . additional clamp modifiers.trap clamping modifier. .cs.s32.f4}. Coordinate elements are of type .ctype . the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32.p.wt }.vec. . If the source base type is . sust.p. // unformatted // formatted . . if the surface format contains UINT data. A surface base address is assumed to be aligned to a 16-byte address. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .f32 }. .vec . If an address is not properly aligned. and A surface components. sust.p Description Store to surface memory using a surface coordinate vector.s32 is assumed. The lowest dimension coordinate represents a sample offset rather than a byte offset.clamp .3d.3d }. .s32.b32.clamp = = = = = = { { { { { { [a.f3. // for sust.1d. Target ISA Notes Examples 126 January 24. The . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. and cache operations introduced in PTX ISA version 2. . The source vector elements are interpreted left-to-right as R.cop}.z. {f1. b]. [surf_B. . Operand b is a scalar or singleton tuple for 1d surfaces.p performs a formatted store of a vector of 32-bit data values to a surface sample.surfref variable.0. Cache operations require sm_20 or later.clamp field specifies how to handle out-of-bounds addresses: . or the instruction may fault. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.u32 is assumed. B.s32. .b.b.trap sust. c.2d.b8 . If the source type is .{u32. sust.clamp. G.v2. SNORM.1d. sust. [a.b64 }. then . . the resulting behavior is undefined. sust. then . Surface sample components that do not occur in the source vector will be written with an unpredictable value. {r1.f2. .vec.

.u32. // for sured. or .s32. is a two-element vector for 2d surfaces. then .b .p.b].b32 type.e. Coordinate elements are of type . where the fourth element is ignored. .clamp [a.3d }.ctype = { . and is a four-element vector for 3d surfaces.u32. .s32 is assumed. and . The instruction type is restricted to .op.b32 }.add. .b].c. January 24.0. r1.u32.1d.clamp.u64.u64 data. A surface base address is assumed to be aligned to a 16-byte address. The lowest dimension coordinate represents a sample offset rather than a byte offset.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.trap. r1.ctype.Chapter 8. Operand a is a . if the surface format contains SINT data.clamp = { .and. . .min.y}]. 2010 127 . . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.2d. . .s32.b32.u32. // sample addressing .c. . .s32 types.geom = { . or the instruction may fault.clamp [a.op = { . min and max apply to .trap [surf_A. and the data is interpreted as .trap . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.s32 or . the resulting behavior is undefined. // byte addressing sured.u32 and . the access may proceed by silently masking off low-order address bits to achieve proper rounding. i.1d. sured.clamp field specifies how to handle out-of-bounds addresses: . {x}].ctype. . Operand b is a scalar or singleton tuple for 1d surfaces. sured.ctype = { .p performs a reduction on sample-addressed 32-bit data.b.min. sured.b32. .add. Operations add applies to .2d.geom. operations and and or apply to .s32.u32 based on the surface sample format as follows: if the surface format contains UINT data.op.or }.b32.p . . . Instruction Set Table 92. .zero }.max. The .geom.surfref variable.b performs an unformatted reduction on .trap sured.u32 is assumed.clamp .u64. {x. then .p. // for sured. Reduction to surface memory using a surface coordinate vector. sured requires sm_20 or later. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b32 }. [surf_B.s32 types. . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. If an address is not properly aligned. sured.b.

suq. Supported on all target architectures.0 Table 93. 2010 . 128 January 24.height.width.query = { .width .surfref variable. Description Query an attribute of a surface.query. suq.PTX ISA Version 2. . . suq Syntax Texture and Surface Instructions: suq Query a surface attribute. [a].height .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Operand a is a .width. Query: . . [surf_A].depth }.b32 %r1.b32 d.5.

c. setp. Supported on all target architectures. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. Threads with a false guard predicate do nothing.s32 a.a.Chapter 8. mov.0. { add. Supported on all target architectures. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. { instructionList } The curly braces create a group of instructions.0. } PTX ISA Notes Target ISA Notes Examples Table 95. p.eq. @{!}p instruction. 2010 129 .7. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Execute an instruction or instruction block for threads that have the guard predicate true. {} Syntax Description Control Flow Instructions: { } Instruction grouping.s32 d. Instruction Set 8. If {!}p then instruction Introduced in PTX ISA version 1.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.7. Introduced in PTX ISA version 1.b.y.f32 @q bra L23.x.0. used primarily for defining a function body. ratio.f32 @!p div.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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b. thread count. the bar.version 2.or }.cta.popc).popc.sync and bar. PTX ISA Notes Target ISA Notes Examples bar. and then safely read values stored by other threads prior to the barrier. Register operands. a{. while . Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Since barriers are executed on a per-warp basis.arrive does not cause any waiting by the executing threads.15. 2010 133 .red also guarantee memory ordering among threads identical to membar.sync without a thread count introduced in PTX ISA 1. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. b. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.and..u32 bar. b}.sync) until the barrier count is met. and bar. bar. the final value is written to the destination register in all threads waiting at the barrier.{arrive. All threads in the warp are stalled until the barrier completes. {!}c.arrive using the same active barrier. In conditionally executed code. and d have type . bar. Operand b specifies the number of threads participating in the barrier. Execution in this case is unpredictable.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. Each CTA instance has sixteen barriers numbered 0. Thus. all-threads-true (.0. Once the barrier count is reached.red performs a reduction operation across threads.{arrive. bar. all threads in the CTA participate in the barrier. bar.Chapter 8. January 24.red delays the executing threads (similar to bar. bar. Description Performs barrier synchronization and communication within a CTA. The barrier instructions signal the arrival of the executing threads at the named barrier. Register operands. p. . a.arrive a{.red are population-count (. If no thread count is specified.op = { . a{. threads within a CTA that wish to communicate via memory can store to memory.sync or bar. it simply marks a thread's arrival at the barrier.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.op.red performs a predicate reduction across the threads participating in the barrier.sync 0.sync with an immediate barrier number is supported for sm_1x targets.or). the optional thread count must be a multiple of the warp size.red. it is as if all the threads in the warp have executed the bar instruction.popc is the number of threads with a true predicate. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).sync and bar. {!}c. the waiting threads are restarted without delay. When a barrier completes. The result of . Thus.0. Instruction Set Table 100.and and . if any thread in a warp executes a bar instruction. bar. and any-thread-true (.red. Only bar. execute a bar.sync bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. and bar. thread count. b}. bar. d. b}.red instruction.red should not be intermixed with bar.sync or bar. and the barrier is reinitialized so that it can be immediately reused. operands p and c are predicates. Note that a non-zero thread count is required for bar.arrive.pred . a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).u32.red} require sm_20 or later. In addition to signaling its arrival at the barrier.red} introduced in PTX . bar.and). bar. The reduction operations for bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. Operands a.

membar.sys Waits until all prior memory requests have been performed with respect to all clients.sys requires sm_20 or later. this is the appropriate level of membar. membar.{cta.sys will typically have much longer latency than membar. membar. .version 1.gl. including thoses communicating via PCI-E such as system and peer-to-peer memory. Waits until prior memory reads have been performed with respect to other threads in the CTA. membar.gl.level = { . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar.PTX ISA Version 2. by st. or system memory level.cta.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.0.version 2.4.g. membar.gl} introduced in PTX . level describes the scope of other clients for which membar is an ordering event. . 134 January 24. PTX ISA Notes Target ISA Notes Examples membar. A memory read (e.cta Waits until all prior memory writes are visible to other threads in the same CTA. membar. and memory reads by this thread can no longer be affected by other thread writes. 2010 .{cta. membar.gl will typically have a longer latency than membar.gl. when the previous value can no longer be read. membar.cta. . membar. global. For communication between threads in different CTAs or even different SMs. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level.sys.sys introduced in PTX .cta. A memory write (e. that is.0 Table 101. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.g.level. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar.sys }.gl} supported on all target architectures.

b.u32 only . . . .e. If an address is not properly aligned. The floating-point add.xor.type = { . min.u32.exch to store to locations accessed by other atomic operations.u32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.dec. The address size may be either 32-bit or 64-bit.space}.b]. A register containing an address may be declared as a bit-size type or integer type. .u64 . i.s32. and truncated if the register width exceeds the state space address width for the target architecture. min. or. . The floating-point operations are add. .f32 Atomically loads the original value at location a into destination register d. . the resulting behavior is undefined. . . e. . min. Operand a specifies a location in the specified state space.inc. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.global. . . d. Within these windows. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.max }. . xor. . .type d. the access may proceed by silently masking off low-order address bits to achieve proper rounding. i.add. The integer operations are add. 2010 135 . atom{.f32 }. .or. .b32 only . by inserting barriers between normal stores and atomic operations to a common address.f32. . or the instruction may fault. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.exch. [a]. and max operations are single-precision.Chapter 8. inc.space = { . accesses to local memory are illegal. Addresses are zero-extended to the specified width as needed.g. In generic addressing. max. perform the memory accesses using generic addressing. Instruction Set Table 102. and max. . Description // // // // // .op. January 24.space}. The address must be naturally aligned to a multiple of the access size. b.. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. performs a reduction operation with operand b and the value in location a.and.e.op.shared }. an address maps to global memory unless it falls within the local memory window or the shared memory window. or [immAddr] an immediate absolute byte address.s32.add. atom. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. an address maps to the corresponding location in local or shared memory.b64 .u64. . .min.op = { . c. overwriting the original value. and stores the result of the specified operation at location a. and exch (exchange). [a].b32. For atom. . dec.type atom{. If no state space is given. The bit-size operations are and.cas. .b32. a de-referenced register areg containing a byte address..s32. or by using atom. 32-bit operations. cas (compare-and-swap). The inc and dec operations return a result in the range [0.b64.

shared requires sm_12 or later.t) = (r == s) ? t operation(*a.shared operations require sm_20 or later. : r. atom.f32 atom. Use of generic addressing requires sm_20 or later.s.cas. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom.0 Semantics atomic { d = *a.add. b. c) operation(*a. : r-1.{add.PTX ISA Version 2.s32 atom.0.[x+4]. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.max.exch} requires sm_12 or later.f32.1. b).max} are unimplemented.b32 d. atom.shared. cas(r.add. Introduced in PTX ISA version 1.global. 64-bit atom.[a].{min.global requires sm_11 or later. *a = (operation == cas) ? : } where inc(r. 64-bit atom. d. d. : r+1.my_val. s) = (r > s) ? s exch(r.my_new_val. s) = s.0.f32 requires sm_20 or later.cas.[p].global. 2010 . s) = (r >= s) ? 0 dec(r. atom. atom. Release Notes Examples @p 136 January 24.

Notes Operand a must reside in either the global or shared state space. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. s) = (r >= s) ? 0 : r+1. . .min. The integer operations are add. Addresses are zero-extended to the specified width as needed.b]. b.op = { .u32.xor. min. The inc and dec operations return a result in the range [0. s) = (r > s) ? s : r-1.u64 . A register containing an address may be declared as a bit-size type or integer type. perform the memory accesses using generic addressing. e. b).dec.u64.s32.f32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. . Within these windows. 32-bit operations.Chapter 8. and max operations are single-precision.u32 only . For red. red. .g. max. January 24.u32. . . . .f32 Performs a reduction operation with operand b and the value in location a.add. or. Description // // // // . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. min. . Operand a specifies a location in the specified state space. dec(r. . where inc(r.add. The floating-point operations are add.exch to store to locations accessed by other reduction operations.op. and truncated if the register width exceeds the state space address width for the target architecture. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. The address size may be either 32-bit or 64-bit. an address maps to global memory unless it falls within the local memory window or the shared memory window. dec. i. . accesses to local memory are illegal. . .s32.b32 only .shared }. . .f32 }. If no state space is given.global. Instruction Set Table 103.and. red{.space}. . overwriting the original value.or. . an address maps to the corresponding location in local or shared memory. In generic addressing.space = { . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.b64.max }. Semantics *a = operation(*a. and max. the access may proceed by silently masking off low-order address bits to achieve proper rounding. min. . a de-referenced register areg containing a byte address.type = { . or by using atom.e. 2010 137 .e..b32. by inserting barriers between normal stores and reduction operations to a common address.type [a]. The bit-size operations are and. the resulting behavior is undefined. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s32. If an address is not properly aligned. or [immAddr] an immediate absolute byte address. The address must be naturally aligned to a multiple of the access size.inc. or the instruction may fault. inc. The floating-point add. i. . and xor. and stores the result of the specified operation at location a.u32..

add.global.and.{min.f32. red.add requires sm_12 or later. red.f32 red.global requires sm_11 or later red. 64-bit red.shared requires sm_12 or later. 64-bit red. 2010 .global.add.PTX ISA Version 2. red.max} are unimplemented. [p]. Release Notes Examples @p 138 January 24.f32 requires sm_20 or later.0.shared operations require sm_20 or later.s32 red.my_val. red.max.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.2.shared.b32 [a].1. [x+4]. Use of generic addressing requires sm_20 or later.

q. // get ‘ballot’ across warp January 24.all. The destination predicate value is the same across all threads in the warp. vote.b32 requires sm_20 or later. vote. vote.pred vote. not across an entire CTA. Description Performs a reduction of the source predicate across threads in a warp. 2010 139 .pred d. Negating the source predicate also computes . vote. // ‘ballot’ form. In the ‘ballot’ form. .ballot. Negate the source predicate to compute .p. .none.b32 p. {!}a. Instruction Set Table 104.any. where the bit position corresponds to the thread’s lane id.pred vote. .2.uni True if source predicate has the same value in all active threads in warp. The reduction modes are: .not_all. r1.Chapter 8.all True if source predicate is True for all active threads in warp.q. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. vote. Negate the source predicate to compute .uni. . p. Note that vote applies to threads in a single warp.ballot.ballot.mode = { .uni.uni }.any True if source predicate is True for some active thread in warp. vote requires sm_12 or later. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.ballot.mode.b32 d.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.all. returns bitmask . {!}a.

btype = { . The type of each operand (.min. .atype = . Using the atype/btype and asel/bsel specifiers.u32. perform a scalar arithmetic operation to produce a signed 34-bit result. 3. . optionally clamp the result to the range of the destination type.dsel.7.9. with optional data merge vop. The sign of the intermediate result depends on dtype. The source and destination operands are all 32-bit registers.btype{.or zero-extend byte. atype.bsel}.dtype = . 2010 .s32) is specified in the instruction type.extended internally to . or word values from its source operands.dtype. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.s33 values.h0.secop = { .atype. c. .secop d.add. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). a{.dtype. b{.s32 }.atype. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. all combinations of dtype.b0. a{. .dsel = . the input values are extracted and signor zero.b2. half-word. The general format of video instructions is as follows: // 32-bit scalar operation.sat} d. extract and sign. . .asel}. and btype are valid.dtype. taking into account the subword destination size in the case of optional data merging. b{. vop.u32 or .asel = . .bsel = { . .0 8.max }.btype{.b1. c. The primary operation is then performed to produce an . 140 January 24. 4.atype. .s34 intermediate result.asel}.h1 }.bsel}.asel}. . with optional secondary operation vop. // 32-bit scalar operation.sat}. b{. a{.bsel}. to produce signed 33-bit input values. Video Instructions All video instructions operate on 32-bit register operands.sat} d. 2.btype{.PTX ISA Version 2.b3.

s34 tmp.b0.b2. . . U16_MIN ). S32_MAX.b3: return ((tmp & 0xff) << 24) default: return tmp. Instruction Set . .s33 c ) switch ( dsel ) { case . The sign of the c operand is based on dtype. c). } } . U32_MAX. tmp.b1. U32_MIN ).s33 tmp. U8_MAX. S8_MAX.b3: if ( sign ) return CLAMP( else return CLAMP( case .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp.b2: return ((tmp & 0xff) << 16) case . . S16_MAX. c). c). default: return tmp. switch ( dsel ) { case . . .b0: return ((tmp & 0xff) case . c). S32_MIN ). as shown in the following pseudocode. The lower 32-bits are then written to the destination operand. U16_MAX. . c). tmp. c).h1: return ((tmp & 0xffff) << 16) case .s33 c) { switch ( secop ) { . . Bool sat. tmp.add: return tmp + c. January 24. U8_MIN ).max return MAX(tmp.h0.h0: return ((tmp & 0xffff) case . 2010 141 .min: return MIN(tmp. Modifier dsel ) { if ( !sat ) return tmp. tmp. . c).s33 tmp.s33 optMerge( Modifier dsel. .s33 optSaturate( .b1: return ((tmp & 0xff) << 8) case . . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). Bool sign. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.Chapter 8. S8_MIN ).s33 optSecOp(Modifier secop. S16_MIN ).

dtype.s32.op2 Description = = = = { vadd.s32. . vadd. vsub vabsdiff vmin.b0.btype{. tmp = ta – tb. r1. with optional data merge vop. vop. asel ). d = optSecondaryOp( op2.op2 d.s32. tmp = MIN( ta.asel}.sat vmin. vabsdiff. vabsdiff. r3.atype = .s32.u32. Integer byte/half-word/word minimum / maximum.sat} d. // optional merge with c operand 142 January 24. // extract byte/half-word/word and sign. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .bsel = { .bsel}. { .0.u32. vmin.atype.b1. a{. r2. tmp = | ta – tb |. vmax }. r2. r1. b{. a{.b2.asel}.sat vsub. // optional secondary operation d = optMerge( dsel. Perform scalar arithmetic operation with optional saturate.dtype.s32. and optional secondary arithmetic operation or subword data merge.dsel.asel}.add.s32.b3. r3. tb = partSelectSignExtend( b. .s32. sat.dsel .0 Table 105. c.atype. vsub. . . . vmax Syntax Integer byte/half-word/word addition / subtraction.asel = . b{. vsub.max }.dtype.b0. tmp. tmp.s32 }. tb ).h1 }.sat vabsdiff.h1. c. isSigned(dtype).add r1. atype. // 32-bit scalar operation. b{.vop . vmax require sm_20 or later. vmax vadd. r3. vmin. with optional secondary operation vop. Semantics // saturate. dsel ).btype{. c.b0. // 32-bit scalar operation. c ). c.s32.min. tmp = MAX( ta. r1. vabsdiff.u32.sat} d.dtype .b2. btype.bsel}. .btype = { . . vmin.h0. Video Instructions: vadd.h0.h0.PTX ISA Version 2.h1.atype. taking into account destination type and merge operations tmp = optSaturate( tmp. . c ).bsel}. Integer byte/half-word/word absolute value of difference.or zero-extend based on source operand type ta = partSelectSignExtend( a. 2010 .sat}. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. . a{. vadd.sat. vsub.btype{. r2.s32. . tb ). r2. r3. bsel ).s32.

with optional data merge vop.dtype. } // saturate.mode} d.wrap ) tb = tb & 0x1f.sat}{. Semantics // extract byte/half-word/word and sign. c. if ( mode == . Instruction Set Table 106.atype. bsel ). b{.asel}. isSigned(dtype).mode . sat. c ).0.bsel}.wrap r1. .atype = { . . and optional secondary arithmetic operation or subword data merge. a{. taking into account destination type and merge operations tmp = optSaturate( tmp. unsigned shift fills with zero. // default is .or zero-extend based on source operand type ta = partSelectSignExtend( a. { . vshr: Shift a right by unsigned amount in b with optional saturate. d = optSecondaryOp( op2. // 32-bit scalar operation. case vshr: tmp = ta >> tb. . Video Instructions: vshl. switch ( vop ) { case vshl: tmp = ta << tb. vshr Syntax Integer byte/half-word/word left / right shift.clamp && tb > 32 ) tb = 32. and optional secondary arithmetic operation or subword data merge. atype. . dsel ). if ( mode == .clamp.u32. .Chapter 8. with optional secondary operation vop. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. b{. a{.asel}. vshr vshl. b{.clamp . .asel = . Signed shift fills with the sign bit. r2.u32.u32. tmp.u32{.u32.dsel. r2.u32{. vshl. r3.dtype .op2 d. Left shift fills with zero.bsel = { . .atype. vshr require sm_20 or later.max }. .bsel}.h1 }. a{. 2010 143 .dsel .sat}{. .vop .s32. c ).mode}. // 32-bit scalar operation. .u32. .b0.b3.h1.s32 }. vop.b2.u32{. { . r1. vshl: Shift a left by unsigned amount in b with optional saturate.asel}.atype.add. vshl.u32 vshr.bsel}. January 24. c. r3. .op2 Description = = = = = { vshl.b1. // optional secondary operation d = optMerge( dsel. tb = partSelectSignExtend( b.dtype. asel ).sat}{.wrap }.h0. tmp.min. vshr }.mode} d.dtype.

S32 // intermediate signed.btype{. final signed (S32 * S32) + S32 // intermediate signed. {-}c. {-}a{.asel}.shr7.sat}{. which is used in computing averages. {-}b{. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. .atype. vmad.po mode.asel = .scale = { .scale} d.s32 }. The source operands support optional negation with some restrictions. .u32.b1. . Description Calculate (a*b) + c.bsel}. “plus one” mode.dtype.btype = { . The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed (U32 * S32) .S32 // intermediate signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. 144 January 24. a{.asel}.h1 }.b0. final signed The intermediate result is optionally scaled via right-shift.atype.po{. c.S32 // intermediate signed. final signed -(S32 * S32) + S32 // intermediate signed. Depending on the sign of the a and b operands.b3.dtype = . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. PTX allows negation of either (a*b) or c. and the operand negates. final signed (S32 * U32) .btype. (a*b) is negated if and only if exactly one of a or b is negated. b{. .po) computes (a*b) + c + 1. Source operands may not be negated in .0 Table 107. The “plus one” mode (. otherwise.dtype. . final signed -(S32 * U32) + S32 // intermediate signed.. // 32-bit scalar operation vmad.atype = .bsel}. . final signed -(U32 * S32) + S32 // intermediate signed. this result is sign-extended if the final result is signed. with optional operand negates. . final signed (U32 * S32) + S32 // intermediate signed. final unsigned -(U32 * U32) + S32 // intermediate signed.sat}{.scale} d. the intermediate result is signed.h0. Although PTX syntax allows separate negation of the a and b operands. That is.bsel = { . internally this is represented as negation of the product (a*b).b2.U32 // intermediate unsigned.shr15 }. Input c has the same sign as the intermediate result.PTX ISA Version 2. . and scaling. and zero-extended otherwise. final signed (S32 * S32) . final signed (S32 * U32) + S32 // intermediate signed. . . final signed (U32 * U32) . 2010 .

s32. } else if ( a. lsb = 1.h0.Chapter 8.shr15: result = (tmp >> 15) & 0xffffffffffffffff. lsb = 1. bsel ).u32.0.negate ^ b. r1. } if ( . tb = partSelectSignExtend( b. btype. S32_MIN).shr7: result = (tmp >> 7) & 0xffffffffffffffff.sat vmad. else result = CLAMP(result.negate. r2.sat ) { if (signedFinal) result = CLAMP(result.u32.u32. asel ).s32.negate ^ b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. atype. tmp[127:0] = ta * tb. Instruction Set Semantics // extract byte/half-word/word and sign. -r3.negate ) { tmp = ~tmp.shr15 r0. case . r0. r1. switch( scale ) { case . tmp = tmp + c128 + lsb. } else if ( c.h0. r2. vmad requires sm_20 or later. January 24. if ( .negate) || c. U32_MAX. U32_MIN).po ) { lsb = 1.u32.negate ) { c = ~c. 2010 145 . } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). signedFinal = isSigned(atype) || isSigned(btype) || (a. S32_MAX.or zero-extend based on source operand type ta = partSelectSignExtend( a. lsb = 0. r3. vmad.

u32.lt. cmp ) ? 1 : 0.atype.b3.atype .le.b1.cmp d.lt vset. a{. tb = partSelectSignExtend( b. r1. { .bsel}. tb.b2.s32.asel}. r2. . atype.max }. . . c. vset. with optional secondary operation vset.h1.0. r3.btype. .bsel = { . Semantics // extract byte/half-word/word and sign.bsel}. .h1 }.cmp .u32.op2 d.btype. .gt. .u32. asel ). Compare input values using specified comparison. { . and therefore the c operand and final result are also unsigned. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. tmp.atype. .dsel .s32 }.ne r1.op2 Description = = = = . vset requires sm_20 or later.ne. . with optional secondary arithmetic operation or subword data merge.asel}. b{. b{.b0.bsel}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // 32-bit scalar operation.add. The intermediate result of the comparison is always unsigned. 2010 . // 32-bit scalar operation.cmp. d = optSecondaryOp( op2. . a{.dsel.h0.btype = { . c.btype. . r2. with optional data merge vset. .0 Table 108. vset. tmp.eq.PTX ISA Version 2. . r3. tmp = compare( ta.cmp d. b{.asel = .u32. bsel ). a{. 146 January 24.or zero-extend based on source operand type ta = partSelectSignExtend( a.ge }.asel}. c ). // optional secondary operation d = optMerge( dsel. btype.atype. . c ). .min.

trap Abort execution and generate an interrupt to the host CPU. brkpt requires sm_11 or later.7. brkpt. brkpt. Supported on all target architectures.4. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. 2010 147 . Introduced in PTX ISA version 1. there are sixteen performance monitor events. numbered 0 through 15. brkpt Suspends execution Introduced in PTX ISA version 1.Chapter 8. The relationship between events and counters is programmed via API calls from the host. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Table 110. trap. @p pmevent 1.0. Notes PTX ISA Notes Target ISA Notes Examples Currently. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. pmevent 7. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. with index specified by immediate operand a. Supported on all target architectures. Table 111. January 24. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Instruction Set 8.0. Triggers one of a fixed number of performance monitor events. Introduced in PTX ISA version 1. trap. pmevent a.10.

0 148 January 24.PTX ISA Version 2. 2010 .

Chapter 9. %lanemask_le. …. %lanemask_lt. Special Registers PTX includes a number of predefined. %clock64 %pm0. 2010 149 . %lanemask_gt %clock. read-only variables. %pm3 January 24. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq.

x. %ntid.y * %ntid.u16 %rh.x.%tid. The total number of threads in a CTA is (%ntid. The number of threads in each dimension are specified by the predefined special register %ntid.z).u32 %h1.u32 %r1. Supported on all target architectures.x.%r0.%tid.%ntid.sreg .x code accessing 16-bit component of %tid mov. %tid.u32 %tid.z to %r2 Table 113.z. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.PTX ISA Version 2. %ntid.sreg .u32 %ntid.x to %rh Target ISA Notes Examples // legacy PTX 1. mov.0. mov.z. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.x 0 <= %tid.sreg .x. the %tid value in unused dimensions is 0. // CTA shape vector // CTA dimensions A predefined.v4 .z == 0 in 1D CTAs. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x.u32 %tid.v4 . // thread id vector // thread id components A predefined.z PTX ISA Notes Introduced in PTX ISA version 1. Redefined as . %tid.u32 type in PTX 2.%ntid.%tid.x.x < %ntid.x * %ntid.u16 %r2.sreg .u32 %ntid. Supported on all target architectures. . %ntid.z == 0 in 2D CTAs. // compute unified thread id for 2D CTA mov.0 Table 112. 2010 .%tid.0.u32 %h2. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. .0.u32 %r0. The fourth element is unused and always returns zero.y. %tid. The %tid special register contains a 1D. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.z < %ntid.%h1.%h2. cvt. Every thread in the CTA has a unique %tid. or 3D vector to match the CTA shape. the fourth element is unused and always returns zero.y 0 <= %tid.z == 1 in 1D CTAs. %tid. read-only special register initialized with the number of thread ids in each CTA dimension.z == 1 in 2D CTAs.u16 %rh. . PTX ISA Notes Introduced in PTX ISA version 1.y. mov.y < %ntid. // move tid.y == %ntid. per-thread special register initialized with the thread identifier within the CTA. // zero-extend tid. %ntid.y.0.%tid. mad.u32 type in PTX 2. CTA dimensions are non-zero. read-only.z.y == %tid. 2D.v4.u32. %tid component values range from 0 through %ntid–1 in each CTA dimension. mov. .x code Target ISA Notes Examples 150 January 24. It is guaranteed that: 0 <= %tid.v4.x.u32 %r0. Redefined as . // legacy PTX 1.

e. read-only special register that returns the thread’s lane within the warp.u32 %r. mov. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. read-only special register that returns the maximum number of warp identifiers. read-only special register that returns the thread’s warp identifier.0.u32 %warpid. Introduced in PTX ISA version 1. The warp identifier will be the same for all threads within a single warp. A predefined.3. Supported on all target architectures. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.u32 %r. For this reason. PTX ISA Notes Target ISA Notes Examples Table 116. A predefined. mov.3. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. Note that %warpid is volatile and returns the location of a thread at the moment when read. %nwarpid requires sm_20 or later. %nwarpid. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Introduced in PTX ISA version 2. A predefined.sreg . The lane identifier ranges from zero to WARP_SZ-1. . due to rescheduling of threads following preemption. Special Registers Table 114. . %laneid.u32 %nwarpid. 2010 151 . .sreg . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Introduced in PTX ISA version 1. January 24. Table 115.u32 %r. mov. %warpid.u32 %laneid.sreg .Chapter 9.g. Supported on all target architectures. but its value may change during execution.

%ctaid. The %ctaid special register contains a 1D. read-only special register initialized with the number of CTAs in each grid dimension.sreg .x. with each element having a value of at least 1.{x. Redefined as . 2010 . Redefined as . The fourth element is unused and always returns zero.536 PTX ISA Notes Introduced in PTX ISA version 1. %rh.v4. It is guaranteed that: 1 <= %nctaid.%nctaid.x.u32 %nctaid .x code Target ISA Notes Examples 152 January 24.sreg .u16 %r0.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u32 %ctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.x 0 <= %ctaid.z} < 65.x.%nctaid.0.0.z.%nctaid. mov.x. %rh.%nctaid. The %nctaid special register contains a 3D grid shape vector.y. The fourth element is unused and always returns zero.v4.u32 mov.u32 type in PTX 2.sreg . mov.PTX ISA Version 2.v4 . .0 Table 117. . 2D.u32 %nctaid.x.u32 mov.0. // legacy PTX 1.y < %nctaid.u16 %r0. or 3D vector. // CTA id vector // CTA id components A predefined.z < %nctaid. It is guaranteed that: 0 <= %ctaid.y 0 <= %ctaid. .y. Supported on all target architectures. Supported on all target architectures.y. read-only special register initialized with the CTA identifier within the CTA grid. // legacy PTX 1.%ctaid.%ctaid. Each vector element value is >= 0 and < 65535.sreg .z. // Grid shape vector // Grid dimensions A predefined. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. %ctaid.x code Target ISA Notes Examples Table 118.0.u32 type in PTX 2. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. depending on the shape and rank of the CTA grid.v4 .y.x < %nctaid.

3. due to rescheduling of threads following preemption. A predefined. but its value may change during execution. Introduced in PTX ISA version 1. so %nsmid may be larger than the physical number of SMs in the device.0. Introduced in PTX ISA version 1. read-only special register that returns the maximum number of SM identifiers.sreg .u32 %gridid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Note that %smid is volatile and returns the location of a thread at the moment when read. where each launch starts a grid-of-CTAs. mov.u32 %r.0. repeated launches of programs may occur. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. // initialized at grid launch A predefined.u32 %r.g. %gridid. mov. %nsmid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Special Registers Table 119. read-only special register initialized with the per-grid temporal grid identifier.u32 %r. PTX ISA Notes Target ISA Notes Examples January 24. This variable provides the temporal grid launch number for this context. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Table 121.Chapter 9. Notes PTX ISA Notes Target ISA Notes Examples Table 120. The SM identifier numbering is not guaranteed to be contiguous. During execution. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.u32 %nsmid. The SM identifier ranges from 0 to %nsmid-1. 2010 153 . Introduced in PTX ISA version 2.sreg . . %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.sreg . read-only special register that returns the processor (SM) identifier on which a particular thread is executing. . Supported on all target architectures. The SM identifier numbering is not guaranteed to be contiguous. . %smid. mov. A predefined. %nsmid requires sm_20 or later.u32 %smid. e.

. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. mov.0. mov.u32 %r.0.u32 %r. %lanemask_eq. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. %lanemask_le.u32 %lanemask_eq. . %lanemask_eq requires sm_20 or later. %lanemask_le requires sm_20 or later.PTX ISA Version 2. %lanemask_lt requires sm_20 or later. A predefined.sreg . Introduced in PTX ISA version 2.sreg . Table 124. Table 123.u32 %r.0 Table 122. 154 January 24. . A predefined.u32 %lanemask_le.sreg . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.0. mov. Introduced in PTX ISA version 2.u32 %lanemask_lt. %lanemask_lt. A predefined. 2010 . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.

Chapter 9. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %lanemask_ge.0. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt.sreg .0. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Table 126. January 24. mov.u32 %r. . %lanemask_ge. A predefined. %lanemask_gt requires sm_20 or later.u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg .u32 %lanemask_gt. 2010 155 . Special Registers Table 125. A predefined. Introduced in PTX ISA version 2. . Introduced in PTX ISA version 2. %lanemask_ge requires sm_20 or later. mov.

Special registers %pm0. . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.%clock. The lower 32-bits of %clock64 are identical to %clock.u32 r1.0. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. mov.%pm0. Their behavior is currently undefined.sreg . Introduced in PTX ISA version 1. %pm2. 156 January 24.u32 %pm0. %pm3 %pm0. %clock64 requires sm_20 or later. Introduced in PTX ISA version 1.3. %pm1. Table 128. Supported on all target architectures.u32 r1. .u64 r1.PTX ISA Version 2. read-only 64-bit unsigned cycle counter.u64 %clock64. mov. 2010 . Table 129. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. %pm1.0 Table 127.%clock64. ….0. . Special Registers: %pm0.sreg . Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Supported on all target architectures. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm1. Introduced in PTX ISA version 2.sreg . %pm2.u32 %clock. mov. %pm3. and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm2. read-only 32-bit unsigned cycle counter.

minor are integers Specifies the PTX language version number. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 157 . PTX File Directives: .0. Directives 10.4 January 24.target Table 130. and the target architecture for which the code was generated. Each ptx file must begin with a .version Syntax Description Semantics PTX version number.version 2.version major. Supported on all target architectures.version . Increments to the major number indicate incompatible changes to PTX.1. . Duplicate .Chapter 10.version 1. . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. .version directives are allowed provided they match the original .0 .version .version directive. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.minor // major.version directive.

texref descriptor. 158 January 24.target directive containing a target architecture and optional platform options.red}. Disallows use of map_f64_to_f32. PTX features are checked against the specified target architecture.red}.f64 instructions used. The following table summarizes the features in PTX that vary according to target architecture. Texturing mode introduced in PTX ISA version 1.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. A .samplerref descriptors. PTX code generated for a given target can be run on later generation devices. sm_10. and an error is generated if an unsupported feature is used.target directive specifies a single target architecture.texmode_unified) . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.f64 instructions used. texmode_unified. Adds {atom. Target sm_20 Description Baseline feature set for sm_20 architecture.PTX ISA Version 2.f64 storage remains as 64-bits.target Syntax Architecture and Platform target.f64 instructions used. sm_11. including expanded rounding modifiers.f32.red}. A program with multiple . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.version directive.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Texturing mode: (default is . texmode_independent. 64-bit {atom.0 Table 131.shared. PTX File Directives: . with only half being used by instructions converted from . brkpt instructions. but subsequent . Adds {atom. Each PTX file must begin with a . Supported on all target architectures. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Introduced in PTX ISA version 1.0. Note that . vote instructions.target .5. Description Specifies the set of features in the target architecture for which the current ptx code was generated.texmode_unified . Requires map_f64_to_f32 if any .global. . map_f64_to_f32 }. sm_12. Requires map_f64_to_f32 if any . In general. where each generation adds new features and retains all features of previous generations.target directives can be used to change the set of target features allowed during parsing. generations of SM architectures follow an “onion layer” model. The texturing mode is specified for an entire module and cannot be changed within the module.global.texmode_independent texture and sampler information is bound together and accessed via a single . 2010 . Therefore. immediately followed by a . sm_13.f64 to .texref and . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. texture and sampler information is referenced with independent . Requires map_f64_to_f32 if any . Adds double-precision support.

Directives Examples .target sm_20. texmode_independent January 24. 2010 159 .target sm_13 // supports double-precision .Chapter 10.target sm_10 // baseline target architecture .

etc.entry .b32 y.0 10.param.samplerref.b32 %r2. parameter variables are declared in the kernel body.0 through 1. and body for the kernel function. the kernel dimensions and properties are established and made available via special registers. In addition to normal parameters. ld. opaque .entry . with optional parameters.entry filter ( . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. For PTX ISA versions 1.reg . e. ld.entry kernel-name kernel-body Defines a kernel entry point name.4 and later.b32 %r3.g. The shape and size of the CTA executing the kernel are available in special registers. . store.0 through 1. %ntid.4. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. Kernel and Function Directives: . … } .PTX ISA Version 2. These parameters can only be referenced by name within texture and surface load. PTX ISA Notes For PTX ISA version 1. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. .surfref variables may be passed as parameters.entry Syntax Description Kernel entry point and body. . Supported on all target architectures. 2010 . .entry kernel-name ( param-list ) kernel-body . and . parameter variables are declared in the kernel parameter list. [z].2. ld.param { . parameters.param.texref.param instructions.5 and later.param. and query instructions and cannot be accessed via ld.param . . [y].3.b32 x. %nctaid.b32 z ) Target ISA Notes Examples [x]. . Parameters may be referenced by name within the kernel body and loaded into registers using ld. At kernel launch.func Table 132.param instructions.entry cta_fft .b32 %r<99>. Parameters are passed via .b32 %r1. 160 January 24. Semantics Specify the entry point for a kernel program.param .param space memory and are listed within an optional parenthesized parameter list.

b32 rval. if any. and supports recursion. Kernel and Function Directives: .reg .Chapter 10.param instructions in the body. val1). other code.reg .func . Parameters must be base types in either the register or parameter state space. PTX ISA 2.reg . .func fname (param-list) function-body .2 for a description of variadic functions.func fname function-body . . The parameter lists define locally-scoped variables in the function body. The implementation of parameter passing is left to the optimizing translator. including input and return parameters and optional function body. mov.param and st.func Syntax Function definition. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Release Notes For PTX ISA version 1. PTX 2. … Description // return value in fooval January 24.func definition with no body provides a function prototype. Supported on all target architectures.param state space. dbl. Variadic functions are currently unimplemented. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.b32 rval) foo (.func (. .func (ret-param) fname (param-list) function-body Defines a function. Directives Table 133.reg .0 with target sm_20 supports at most one return value. (val0. ret.param space are accessed using ld.0.b32 localVar.x code.result.0 with target sm_20 allows parameters in the . implements an ABI with stack. } … call (fooval). Parameters in register state space may be referenced directly within instructions in the function body. which may use a combination of registers and stack locations to pass parameters.f64 dbl) { .b32 N. foo. parameters must be in the register state space. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Variadic functions are represented using ellipsis following the last fixed argument. and recursion is illegal. Parameters in . 2010 161 . A . … use N. Parameter passing is call-by-value. there is no stack.

pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).0 10. A general . and the strings have no semantics within the PTX virtual machine model. PTX supports the following directives. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. The .maxntid directive specifies the maximum number of threads in a thread block (CTA). or as statements within a kernel or device function body.minnctapersm directives may be applied per-entry and must appear between an . .maxnctapersm (deprecated) . The interpretation of .PTX ISA Version 2.3. and the . at entry-scope.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. These can be used. Note that . Currently.entry directive and its body.minnctapersm . and .g. which pass information to the backend optimizing compiler. 2010 . The directives take precedence over any module-level constraints passed to the optimizing backend. to throttle the resource requirements (e.maxnreg. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxntid . registers) to increase total thread count and provide a greater opportunity to hide memory latency. .maxntid and . 162 January 24. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.pragma directives may appear at module (file) scope.maxnreg . for example.maxntid.pragma directive is supported for passing information to the PTX backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. the .pragma The . the . The directive passes a list of strings to the backend.

Introduced in PTX ISA version 1. . or the maximum number of registers may be further constrained by .3.maxctapersm. the backend may be able to compile to fewer registers. ny. Supported on all target architectures.Chapter 10. .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.entry foo .maxntid . Performance-Tuning Directives: .maxnreg n Declare the maximum number of registers per thread in a CTA. .maxntid nx.maxntid nx.maxntid 256 .maxntid and .maxnreg . Directives Table 134.3. Performance-Tuning Directives: . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. for example. The compiler guarantees that this limit will not be exceeded. The actual number of registers used may be less.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid Syntax Maximum number of threads in thread block (CTA).16. or 3D CTA. ny . Supported on all target architectures.entry bar .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. . nz Declare the maximum number of threads in the thread block (CTA). 2D.maxntid nx . 2010 163 . This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid 16. The maximum number of threads is the product of the maximum extent in each dimension. Exceeding any of these limits results in a runtime error or kernel launch failure.entry foo . Introduced in PTX ISA version 1.

0. Optimizations based on .0.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). . additional CTAs may be mapped to a single multiprocessor.maxnctapersm generally need . Deprecated in PTX ISA version 2.entry foo . .PTX ISA Version 2.minnctapersm in PTX ISA version 2.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. . Introduced in PTX ISA version 2.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.entry foo .maxnctapersm.maxntid and . Optimizations based on .maxnctapersm has been renamed to . 2010 .maxntid to be specified as well. Supported on all target architectures. For this reason.minnctapersm generally need .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxntid 256 . .0 Table 136. Performance-Tuning Directives: .minnctapersm 4 { … } 164 January 24. Introduced in PTX ISA version 1.maxntid to be specified as well.maxnctapersm (deprecated) .maxntid 256 .minnctapersm . However. Supported on all target architectures. The optimizing backend compiler uses . Performance-Tuning Directives: .3. . if the number of registers used by the backend is sufficiently lower than this bound.0 as a replacement for .

pragma “nounroll”. The interpretation of . at entry-scope.0.Chapter 10. .entry foo . { … } January 24. .pragma “nounroll”. entry-scoped. Directives Table 138. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Pass module-scoped.pragma list-of-strings . See Appendix A for descriptions of the pragma strings defined in ptxas. 2010 165 .pragma .pragma directive strings is implementation-specific and has no impact on PTX semantics. or at statementlevel.pragma directive may occur at module-scope. Introduced in PTX ISA version 2. The . Supported on all target architectures. or statement-level directives to the PTX backend compiler. Performance-Tuning Directives: .pragma Syntax Description Pass directives to PTX backend compiler.

0 but is supported for legacy PTX version 1.debug_pubnames.0.section directive. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .0 and replaces the @@DWARF syntax. 0x736d6172 . 0x61395a5f.4byte label .0 10.debug_info . 0x6150736f. replaced by . 0x00.section . 0x00 .file . 0x63613031..quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.4byte . 0x5f736f63 .4.4byte 0x000006b5.loc The .4byte int32-list // comma-separated hexadecimal integers in range [0. Deprecated as of PTX 2. 0x00. @progbits ..264-1] . @@DWARF dwarf-string dwarf-string may have one of the . Table 139. 0x00.x code.quad int64-list // comma-separated hexadecimal integers in range [0.PTX ISA Version 2. “”. 0x00. The @@DWARF syntax is deprecated as of PTX version 2. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00 166 January 24. Introduced in PTX ISA version 1.2.section .4byte 0x6e69616d. 0x00.byte 0x00.section directive is new in PTX ISA verison 2. 0x00000364. 0x02. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 2010 . Supported on all target architectures.byte 0x2b.byte byte-list // comma-separated hexadecimal byte values .232-1] . 0x00.

2010 167 . Debugging Directives: . 0x00. 0x00. 0x00.. Supported on all target architectures.debug_info . } 0x02.b8 0x2b. Source file information.b32 label . Directives Table 140.b32 .file . 0x736d6172 0x00 Table 141. 0x00.264-1] .section . 0x00. replaces @@DWARF syntax.b32 0x000006b5.debug_pubnames { . Supported on all target architectures.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x00.loc .b32 0x6e69616d. 0x00000364. Debugging Directives: .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00 0x61395a5f.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.section Syntax PTX section definition.section section_name { dwarf-lines } dwarf-lines have the following formats: . .Chapter 10. . 0x63613031. .section . . Debugging Directives: .b64 int64-list // comma-separated list of integers in range [0.232-1] .. .loc line_number January 24. . Supported on all target architectures.255] .b8 byte-list // comma-separated list of integers in range [0.0.0. .file filename Table 142.. 0x5f736f63 0x6150736f. Source file location.b32 int32-list // comma-separated list of integers in range [0.0.b8 0x00.

visible identifier Declares identifier to be externally visible.global . // foo will be externally visible 168 January 24.PTX ISA Version 2.extern . Supported on all target architectures. Introduced in PTX ISA version 1. . Supported on all target architectures.visible .b32 foo. Linking Directives: .extern .0 10. Introduced in PTX ISA version 1. . Linking Directives .0.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.b32 foo. Linking Directives: .0.visible . // foo is defined in another module Table 144.visible Table 143.global . . 2010 .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern . .extern identifier Declares identifier to be defined externally.6.

The first section describes ISA and implementation changes in the current release of PTX ISA 2.4 PTX ISA 1.1 PTX ISA 1. 2010 169 .3 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.0.0 CUDA 2.0 January 24.2 PTX ISA 1.2 CUDA 2.1 CUDA 2.3 driver r190 CUDA 3.Chapter 11.5 PTX ISA 2.0 CUDA 1.0 driver r195 PTX ISA Version PTX ISA 1.0 PTX ISA 1.1 CUDA 2. The release history is as follows. CUDA Release CUDA 1. and the remaining sections provide a record of changes in previous releases.

while maximizing backward compatibility with legacy PTX 1.f32. mad.f32 require a rounding modifier for sm_20 targets.f32 and mad. New Features 11.1. Both fma. Single. rcp. 2010 . The .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.1.x code and sm_1x targets.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 11. fma.0 11. These are indicated by the use of a rounding modifier and require sm_20.and double-precision div.PTX ISA Version 2. The fma.ftz modifier may be used to enforce backward compatibility with sm_1x. • • • • • 170 January 24. The goal is to achieve IEEE 754 compliance wherever possible. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.0 for sm_20 targets. Instructions testp and copysign have been added.ftz and .rp rounding modifiers for sm_20 targets. and mul now support . When code compiled for sm_1x is executed on sm_20 devices. and sqrt with IEEE 754 compliant rounding have been added. Changes in Version 2.rm and . The changes from PTX ISA 1.1.f32 instruction also supports .1. The mad.f32 for sm_20 targets.rn.f32 requires sm_20. Single-precision add. The mad. Floating-Point Extensions This section describes the floating-point changes in PTX 2.sat modifiers. sub.1.1.f32 maps to fma.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added.

bfind.le. %lanemask_{eq. brev. and shared addresses to generic address and vice-versa has been added. Bit field extract and insert instructions. st. Instruction cvta for converting global.clamp and . A system-level membar instruction. Cache operations have been added to instructions ld.or}.shared have been extended to handle 64-bit data types for sm_20 targets. Instructions prefetch and prefetchu have also been added. A “find leading non-sign bit” instruction.popc.add. Other new features Instructions ld. has been added.pred have been added.zero. ldu. prefetchu. The bar instruction has been extended as follows: • • • A bar. . 2010 171 .red}. New instructions A “load uniform” instruction. 11. A “vote ballot” instruction. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added.ge.red}.Chapter 11.1. January 24. The . Surface instructions support additional .1. has been added. have been added. for prefetching to specified level of memory hierarchy. A “count leading zeros” instruction. cvta. popc. Instruction sust now supports formatted surface stores.2. local. st.minnctapersm to better match its behavior and usage.f32 have been implemented.red. Instructions {atom.3.{and. A “bit reversal” instruction. bfe and bfi. and red now support generic addressing. A new directive. and sust.gt} have been added. Video instructions (includes prmt) have been added.u32 and bar. ldu.arrive instruction has been added. isspacep. Release Notes 11.maxnctapersm directive was deprecated and replaced with . e. has been added. A “population count” instruction. membar. clz.red. New special registers %nsmid.sys. vote.b32. bar now supports optional thread count and register operands. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. has been added.lt.clamp modifiers. atom.ballot. prefetch. has been added. .1.1. Instructions bar. Instructions {atom. suld.g.section. %clock64.

Support for variadic functions and alloca are unimplemented.1.f32} atom. cvt.s32. if . the correct number is sixteen.4 and earlier.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. .ftz for PTX ISA versions 1. See individual instruction descriptions for details.0 11. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.f32.5. Semantic Changes and Clarifications The errata in cvt. The underlying.{min.5 and later. 172 January 24. In PTX version 1. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.PTX ISA Version 2.max} are not implemented. Formatted surface load is unimplemented.p sust.u32. Formatted surface store with .1.{u32. {atom. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.red}.4 or earlier. 2010 . 11.f32 type is unimplemented.p. where . stack-based ABI is unimplemented. To maintain compatibility with legacy PTX code. has been fixed.ftz (and cvt for .2. or .target sm_1x.3. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.version is 1. call suld.s32. Instruction bra.

The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. { … } // do not unroll any loop in this function . and statement levels. including loops preceding the . The “nounroll” pragma is allowed at module. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma “nounroll”. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.func bar (…) { … L1_head: .pragma.entry foo (…) . L1_body: … L1_continue: bra L1_head.Appendix A. . Note that in order to have the desired effect at statement level. Supported only for sm_20 targets. disables unrolling of0 the loop for which the current block is the loop header. disables unrolling for all loops in the entry function body. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. L1_end: … } // do not unroll this loop January 24. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma strings defined by ptxas. Table 145. . … @p bra L1_end. Descriptions of . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma “nounroll”. 2010 173 .0. entry-function.pragma “nounroll”.pragma Strings This section describes the . Ignored for sm_1x targets.

PTX ISA Version 2.0 174 January 24. 2010 .

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