NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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........ 41 Using Addresses.......... 5.................................................. 43 Labels and Function Names as Operands ... 6.......................................1.................................................................. 5......................... 5............4..... 6....5............ 29 Local State Space ......... 5............. Types ......................................... 2010 .4............4.....1...7..... 33 5.......................................................................... 5........................6................ 44 Rounding Modifiers ..8......................................................................... 32 Texture State Space (deprecated) ................................................................2............................... 5............... and Variables ....... 5......................................................................PTX ISA Version 2........................................ 43 6.... 37 Array Declarations ... Operand Type Information ............ 27 Register State Space .............1................................4...................4........ Texture.........1........................................4.....5........................... 29 Parameter State Space ............................ Chapter 6.............2............................1................................4......................5.... Abstracting the ABI ............... 5......................................... 6.........0 4....................... 49 7........5.............4................................. 5.3..4............................................................................ 47 Chapter 7....................... 5............ Arrays..................................2..................4.............................................. 32 5...................................... 6.............3......................................... 42 Addresses as Operands .....................................................4.. 6..................................................1..2.........6.........6............1................4...............4.................................................. 25 Chapter 5............................5........... 49 ii January 24........ 6....................................................................... 41 6.2... 37 Variable Declarations ................................................. 29 Global State Space ............. 41 Destination Operands ..............3. 6................ 43 Vectors as Operands ........ 5....................................................... 27 5..... 5.................................................... Instruction Operands............................................................ 38 Initializers ..................................................... 39 5.................. 38 Alignment ...1......................1................................................... 30 Shared State Space.............................. 5...........................................4......... Summary of Constant Expression Evaluation Rules ............ 33 Restricted Use of Sub-Word Sizes .......... and Surface Types ......................................................................... State Spaces ................................................................................ 37 Vectors ................................................................................6................1..........3..............................................1......................................2.................. 46 6....................................................... Operand Costs ........... 42 Arrays as Operands ........................................ 34 Variables ........................ State Spaces..3. 28 Special Register State Space ........... 39 Parameterized Variable Names ............ 5...... 5......................................... 28 Constant State Space .............................1...... Sampler...............................................................................................1............................2..................................................1........4..............1.... 5..................... 44 Scalar Conversions .................2....2................1................ Type Conversion............................. Function declarations and definitions ... Types...5...................... 6....................................... 33 Fundamental Types ................................. 41 Source Operands.............. and Vectors ....... 6............................................................................................................................

.......... 62 Machine-Specific Semantics of 16-bit Code ....... Instruction Set ............2.. 52 Variadic functions .................3............ 62 8..... 63 Integer Arithmetic Instructions ....................................... 162 Debugging Directives ...................... 8......... 8.. Format and Semantics of Instruction Descriptions .................6......................... 8........................................ Type Information for Instructions and Operands ............................................................................................................................ 104 Data Movement and Conversion Instructions ...... 8........1........................3....3.....................................................7.........3..... 8................................................................ 55 Predicated Execution .. 8...6...........................................................................................................................4......... 57 Manipulating Predicates ................................................ 8...................................2...........1....... 122 Control Flow Instructions ...............................................5.......................... 140 Miscellaneous Instructions..........2...................... 129 Parallel Synchronization and Communication Instructions ......................4................................................................................. 160 Performance-Tuning Directives ............... PTX Version and Target Directives ................................................ 10................................................ 81 Comparison and Selection Instructions ....... 132 Video Instructions ...7.............................................. 62 Semantics ..................x ......................................... 60 8....................................... 8......1................................................... 170 New Features ......1.......................... Divergence of Threads in Control Constructs ...........1............................................................................................................. 7....................5.................7..... 8.... 53 Alloca ..........................................................4.................................. 8..............................7............ 11.. 157 Specifying Kernel Entry Points and Functions ....................... 8..................... 169 11....................................1................... 172 January 24......................................................................7..7..................1....................................... 56 Comparisons ... 147 8............................................2......... 58 8................................. 100 Logic and Shift Instructions ............. 168 Chapter 11....................................................1................................ 59 Operand Size Exceeding Instruction-Type Size ......................................... 55 8..............4.....................................................1.......7.....................7......... 11..................6......................7........................6...7......... 166 Linking Directives . 11.................... Release Notes ..7............. 149 Chapter 10.......... 8...................9.....10............... 7.............. 10....................... 2010 iii .................................................................................. 172 Unimplemented Features Remaining .................... 8... 63 Floating-Point Instructions .................................................................... 8.................................. 8................. 108 Texture and Surface Instructions .......................1................................................3.......... Special Registers .................................................................................................................................................8................ 10........................... 55 PTX Instructions .... 54 Chapter 8........2....1............1...........3...................................7.................................................3........... 10.................2. 8............................. 157 10....... Chapter 9..........1..0 .......... Changes from PTX 1......... Changes in Version 2..................... Instructions .....7........................................ Directives .. 170 Semantic Changes and Clarifications ..........

...........0 Appendix A.... 2010 ..........................pragma Strings....PTX ISA Version 2........ 173 iv January 24.......... Descriptions of .....

.......................... Unsigned Integer................................... 71 January 24................ Table 8............................ 67 Integer Arithmetic Instructions: mad .......................................... Table 25........................................ Table 22....................................... Table 2.............................................................. Table 32...................................................................... Table 4................... 64 Integer Arithmetic Instructions: add...... 58 Floating-Point Comparison Operators Testing for NaN ........... 33 Opaque Type Fields in Unified Texture Mode .....................................................................cc ................................ Table 30................................... 59 Relaxed Type-checking Rules for Source Operands .. Table 18.......... 27 Properties of State Spaces ............List of Tables Table 1................................. Table 12................................... 70 Integer Arithmetic Instructions: sad ..... Table 15....... 35 Convert Instruction Precision and Format .......................... Table 31................................................................... Table 16............................... Table 6........................................ 66 Integer Arithmetic Instructions: mul .................. PTX Directives .......... 57 Floating-Point Comparison Operators ............................................................... 58 Type Checking Rules ..cc ................................................................................................................ and Bit-Size Types ......................................................... Table 23..................... 25 State Spaces ...... 19 Predefined Identifiers ........................... 35 Opaque Type Fields in Independent Texture Mode .................. Table 7....... Table 20............................................................................ Table 21.............................................................................. 57 Floating-Point Comparison Operators Accepting NaN ............ 20 Operator Precedence ................................ Table 10.................. 68 Integer Arithmetic Instructions: mul24 ............................................ Table 9............... Table 13........... Table 26........................ 65 Integer Arithmetic Instructions: addc .................................... 69 Integer Arithmetic Instructions: mad24 ............................ 45 Floating-Point Rounding Modifiers ............... 66 Integer Arithmetic Instructions: subc ....... 23 Constant Expression Evaluation Rules .................................... Table 11........................ 28 Fundamental Type Specifiers .............. 61 Integer Arithmetic Instructions: add ........................... 47 Operators for Signed Integer.............................. 46 Integer Rounding Modifiers ................ Table 5..................... 18 Reserved Instruction Keywords ................................................................................ Table 28............................................................................................................................................................ 64 Integer Arithmetic Instructions: sub ........................ Table 27..... 60 Relaxed Type-checking Rules for Destination Operands............................... Table 14............................................................................. Table 24............ Table 17......... 65 Integer Arithmetic Instructions: sub....................................... Table 19.................................... Table 29................................................................................... Table 3................................... 2010 v .............. 46 Cost Estimates for Accessing State-Spaces ..........................

.............................................................................. 72 Integer Arithmetic Instructions: min .............. Table 43.................................................... 83 Floating-Point Instructions: copysign .......................................... 99 Comparison and Selection Instructions: set .................... 85 Floating-Point Instructions: mul ................ Table 40...................................... Table 57..... 86 Floating-Point Instructions: fma .................................... Integer Arithmetic Instructions: div ............................................. Table 35.................................................. 75 Integer Arithmetic Instructions: brev ........................ 73 Integer Arithmetic Instructions: max ................................................. 77 Integer Arithmetic Instructions: bfi .......... 91 Floating-Point Instructions: neg .............. 101 Comparison and Selection Instructions: setp .......................... Table 58............. Table 68............................... Table 56........ 83 Floating-Point Instructions: add ........................ Table 41.................. Table 37.................. Table 49.......... 97 Floating-Point Instructions: lg2 .......................... Table 69............................. 72 Integer Arithmetic Instructions: neg ....................................... 87 Floating-Point Instructions: mad .................................. Table 38................... 102 Comparison and Selection Instructions: selp ....................................................................... Table 44........................................................................................................ Table 42................................................... Table 65....................................................................................................................... 2010 ...................................................................................................... Table 53....................... Table 51............................................................................ 82 Floating-Point Instructions: testp ..............PTX ISA Version 2........................................... 78 Integer Arithmetic Instructions: prmt ...............................................................................0 Table 33.................................................. Table 63............................. Table 39......... Table 59.................................. Table 46............... 71 Integer Arithmetic Instructions: abs ......................... 103 vi January 24................................................................................... 94 Floating-Point Instructions: rsqrt .. 74 Integer Arithmetic Instructions: bfind ................................................................. Table 52.................... Table 34. Table 50................................. 88 Floating-Point Instructions: div ................................................. 73 Integer Arithmetic Instructions: popc ...... 84 Floating-Point Instructions: sub .... 90 Floating-Point Instructions: abs ............ 79 Summary of Floating-Point Instructions ........................................................................... 71 Integer Arithmetic Instructions: rem ................................................ 96 Floating-Point Instructions: cos ................. 76 Integer Arithmetic Instructions: bfe ..................... 74 Integer Arithmetic Instructions: clz ....................................... Table 36....................................... Table 55.................................................................... 92 Floating-Point Instructions: rcp .............................................................. 95 Floating-Point Instructions: sin ........... Table 66....................................... Table 67...................................... Table 60...... 93 Floating-Point Instructions: sqrt ................................. 98 Floating-Point Instructions: ex2 ............................................................................... 103 Comparison and Selection Instructions: slct ................................... Table 62........................................................ 92 Floating-Point Instructions: max .................. Table 45............................................................................................ 91 Floating-Point Instructions: min ............................................ Table 47......................... Table 48.................... Table 64........... Table 61.. Table 54...........................

........ 120 Texture and Surface Instructions: tex ............................................ 113 Data Movement and Conversion Instructions: ldu .......................... 105 Logic and Shift Instructions: or ............................... Table 76.................... Table 81................................................................................. Table 83................. Table 91.......... 107 Cache Operators for Memory Load Instructions ..... vabsdiff................ Table 102........................................... 126 Texture and Surface Instructions: sured......... 127 Texture and Surface Instructions: suq .................. 106 Logic and Shift Instructions: cnot ..... 142 Video Instructions: vshl......... 106 Logic and Shift Instructions: shl ................................................................ Table 106............................................. Table 92.. Table 87..................................................................................... Table 95...... 131 Control Flow Instructions: exit ......................... 2010 vii ................................... Table 101.......................................................................................................................... 116 Data Movement and Conversion Instructions: prefetch..................................................... Table 78...................... 139 Video Instructions: vadd................. vmax .......................... Table 105... Table 100... 130 Control Flow Instructions: ret ... 107 Logic and Shift Instructions: shr ...... Table 75........................................ vmin............................................................................................................... 125 Texture and Surface Instructions: sust ............................................ 129 Control Flow Instructions: @ ......................................................... Logic and Shift Instructions: and ..................... Table 88............ Table 86............ Table 96................ 119 Data Movement and Conversion Instructions: cvta ...... vshr ............................................... Table 80.... 143 January 24............................ 105 Logic and Shift Instructions: xor ..................... Table 84.......... Table 103........................................................ Table 90................ 135 Parallel Synchronization and Communication Instructions: red ..................................................... Table 85......... 115 Data Movement and Conversion Instructions: st ........ Table 72..................................... 128 Control Flow Instructions: { } ........................... 106 Logic and Shift Instructions: not ......................................... 137 Parallel Synchronization and Communication Instructions: vote ........ 130 Control Flow Instructions: call ...........................................Table 70........ 129 Control Flow Instructions: bra ..... 110 Data Movement and Conversion Instructions: mov .. Table 77.. Table 82......... Table 104.................................. Table 97............................................. Table 74......... 112 Data Movement and Conversion Instructions: ld ... 109 Cache Operators for Memory Store Instructions ................ Table 94....... Table 79.. 118 Data Movement and Conversion Instructions: isspacep .................... vsub..... Table 71........................ Table 93............ 134 Parallel Synchronization and Communication Instructions: atom ....... prefetchu ....................................................................... Table 99................................................. 123 Texture and Surface Instructions: txq ...... 111 Data Movement and Conversion Instructions: mov ............................................................................................... 119 Data Movement and Conversion Instructions: cvt .. 124 Texture and Surface Instructions: suld ............................................................. Table 73............................................................... 133 Parallel Synchronization and Communication Instructions: membar ...... Table 89....... Table 98..................... 131 Parallel Synchronization and Communication Instructions: bar ....................................................

... 156 Special Registers: %pm0. 158 Kernel and Function Directives: .... Table 109. Table 112.target .............................................................................................. Table 120......................... Table 118.................................................. 165 Debugging Directives: @@DWARF ....................................................... Table 135................ Table 136............... %pm2.......... 167 Debugging Directives: ............................................... Table 117...func ................................... Table 125.................................................. 167 Linking Directives: ................ Table 130......................................... 163 Performance-Tuning Directives: ......................................................................................................................... Table 124..................... Table 119........................ Table 131..0 Table 107........................................ Table 142....... 150 Special Registers: %ntid ....... 153 Special Registers: %gridid ............................. 168 viii January 24....................... Table 113.....................................................section ............................. 153 Special Registers: %lanemask_eq . Table 122....... 146 Miscellaneous Instructions: trap . 167 Debugging Directives: .........maxntid .................. 156 PTX File Directives: ........... Table 126............ Table 132..................................................... 154 Special Registers: %lanemask_le .... 144 Video Instructions: vset.........................................................entry..................maxnreg ................ 164 Performance-Tuning Directives: ... 164 Performance-Tuning Directives: ......................... Table 133................ 147 Miscellaneous Instructions: pmevent.............. 151 Special Registers: %warpid .................. Table 139........ 161 Performance-Tuning Directives: ........ Table 114. Table 140............................................. 155 Special Registers: %clock ............................ 157 PTX File Directives: .............................................. %pm3 ..................... %pm1... Table 134................................................... Table 137................ Table 128..................................................... 151 Special Registers: %nwarpid ................minnctapersm ........................................ 163 Performance-Tuning Directives: ................................................ Table 108.............................. 154 Special Registers: %lanemask_ge ............................................. 150 Special Registers: %laneid ......... 147 Special Registers: %tid .............................................. 154 Special Registers: %lanemask_lt ........................................................................................ Table 123.................................................................... Table 138............ Table 111.................................. Table 141............loc ....................................... 153 Special Registers: %nsmid ..............................................maxnctapersm (deprecated) ................ 152 Special Registers: %nctaid ..version............... 2010 ...........extern............................................. 160 Kernel and Function Directives: ................pragma ........................... 147 Miscellaneous Instructions: brkpt ........... Table 127.file .......... 155 Special Registers: %lanemask_gt .. 151 Special Registers: %ctaid .......................... Table 143............ 152 Special Registers: %smid .................. 166 Debugging Directives: ....................................... Video Instructions: vmad .................................................................................... Table 121... Table 116.......................................................................................................................... Table 115....................... Table 110....................................................................................................................................................................................................................... Table 129.....................................PTX ISA Version 2............................ 156 Special Registers: %clock64 ..........................................................

............ 168 Pragma Strings: “nounroll” ........................... Linking Directives: .................. 173 January 24................................................................... 2010 ix ..........Table 144........visible........ Table 145.....................

PTX ISA Version 2. 2010 .0 x January 24.

image and media processing applications such as post-processing of rendered images. In fact. stereo vision. which are optimized for and translated to native target-architecture instructions. and pattern recognition can map image blocks and pixels to parallel processing threads. the programmable GPU has evolved into a highly parallel. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Introduction This document describes PTX. there is a lower requirement for sophisticated flow control. and because it is executed on many data elements and has high arithmetic intensity. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. the memory access latency can be hidden with calculations instead of big data caches. PTX programs are translated at install time to the target hardware instruction set.1. high-definition 3D graphics.2. PTX defines a virtual machine and ISA for general purpose parallel thread execution. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. from general signal processing or physics simulation to computational finance or computational biology. video encoding and decoding. January 24. multithreaded. Similarly. Data-parallel processing maps data elements to parallel processing threads. PTX exposes the GPU as a data-parallel computing device. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Because the same program is executed for each data element. image scaling.Chapter 1. 1. 2010 1 . 1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations.

sat modifiers.f32 requires sm_20. Most of the new features require a sm_20 target.f32 for sm_20 targets.3.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. and the introduction of many new instructions. Provide a common source-level ISA for optimizing code generators and translators. which map PTX to specific target machines.PTX ISA Version 2. and mul now support .0 PTX ISA Version 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 are improved support for IEEE 754 floating-point operations. The mad. 1.ftz and . sub.ftz) modifier may be used to enforce backward compatibility with sm_1x. Both fma.0 is a superset of PTX 1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. surface. reduction. mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. and architecture tests. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. 1.3.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Single-precision add. A “flush-to-zero” (. PTX 2.x code will continue to run on sm_1x targets as well. The main areas of change in PTX 2.f32 instruction also supports .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. fma.f32 and mad. addition of generic addressing to facilitate the use of general-purpose pointers. including integer. Improved Floating-Point Support A main area of change in PTX 2.0 is in improved support for the IEEE 754 floating-point standard. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. The fma. Achieve performance in compiled applications comparable to native GPU performance.rp rounding modifiers for sm_20 targets. memory. Facilitate hand-coding of libraries. and video instructions. A single-precision fused multiply-add (fma) instruction has been added.1. The changes from PTX ISA 1. barrier. • • • 2 January 24. atomic. When code compiled for sm_1x is executed on sm_20 devices.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Provide a machine-independent ISA for C/C++ and other compilers to target. performance kernels. Legacy PTX 1. PTX ISA Version 2.f32 require a rounding modifier for sm_20 targets.rm and .rn.f32.f32 maps to fma. Provide a code distribution ISA for application and middleware developers. The mad.x features are supported on the new sm_20 target. 2010 . and all PTX 1.x. Instructions marked with .

rcp. so recursion is not yet supported. i. atom. and shared addresses to generic addresses. 1. Generic Addressing Another major change is the addition of generic addressing. New Instructions The following new instructions.and double-precision div. for prefetching to specified level of memory hierarchy. prefetchu. suld. instructions ld.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. • Taken as a whole. Surface Instructions • • Instruction sust now supports formatted surface stores. stack-based ABI. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. these changes bring PTX 2. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. e.0. A new cvta instruction has been added to convert global. Surface instructions support additional clamp modifiers. cvta. ldu. special registers. . These are indicated by the use of a rounding modifier and require sm_20.3. and sust.g. local. isspacep.0.Chapter 1.3. and Application Binary Interface (ABI).. 1.2. st. and sqrt with IEEE 754 compliant rounding have been added.4. an address that is the same across all threads in a warp. 2010 3 . stack layout. local. and shared addresses to generic address and vice-versa has been added. Instruction cvta for converting global. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.3.3. Support for an Application Binary Interface Rather than expose details of a particular calling convention. and red now support generic addressing. and shared state spaces.clamp and . PTX 2. local. Introduction • Single.zero.0 closer to full compliance with the IEEE 754 standard. January 24. Instructions testp and copysign have been added. Instructions prefetch and prefetchu have been added. and vice versa.e. st. prefetch. 1. and directives are introduced in PTX 2. In PTX 2. Generic addressing unifies the global. allowing memory instructions to access these spaces without needing to specify the state space. Cache operations have been added to instructions ld. NOTE: The current version of PTX does not implement the underlying.

Barrier Instructions • • A system-level membar instruction.red}.ge. 4 January 24.or}.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. New special registers %nsmid.ballot. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A bar. %clock64.popc. A “vote ballot” instruction. and Vote Instructions • • • New atomic and reduction instructions {atom. bar now supports an optional thread count and register operands.PTX ISA Version 2. .b32.{and. Instructions bar.f32 have been added.red}. bfi bit field extract and insert popc clz Atomic.le. %lanemask_{eq. has been added. 2010 .red.section.sys. has been added.pred have been added.shared have been extended to handle 64-bit data types for sm_20 targets. membar. Instructions {atom.lt. Reduction. vote. A new directive. Other Extensions • • • Video instructions (includes prmt) have been added.u32 and bar.arrive instruction has been added.add.gt} have been added.red.

and variable declarations. Chapter 11 provides release notes for PTX Version 2. Chapter 8 describes the instruction set. Chapter 5 describes state spaces. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 9 lists special registers. January 24. Chapter 7 describes the function and call syntax. Introduction 1. Chapter 3 gives an overview of the PTX virtual machine model.4. Chapter 10 lists the assembly directives supported in PTX. 2010 5 . types. Chapter 6 describes instruction operands. Chapter 4 describes the basic syntax of the PTX language.0. calling convention. and PTX support for abstracting the Application Binary Interface (ABI).Chapter 1.

2010 .0 6 January 24.PTX ISA Version 2.

x. January 24. but independently on different data. Threads within a CTA can communicate with each other. (with elements tid.2. one can specify synchronization points where threads wait until all threads in the CTA have arrived. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.2. Cooperative thread arrays (CTAs) implement CUDA thread blocks.1.z). Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Each thread has a unique thread identifier within the CTA. compute addresses. or CTA. or host: In other words. Each CTA has a 1D. 2. It operates as a coprocessor to the main CPU. and tid. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. work. ntid. To coordinate the communication of the threads within the CTA. To that effect.1. and results across the threads of the CTA.y.x. Each CTA thread uses its thread identifier to determine its assigned role. More precisely.y. 2D. or 3D shape specified by a three-element vector ntid (with elements ntid. data-parallel. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. tid. Programming Model 2.z) that specifies the thread’s position within a 1D. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. can be isolated into a kernel function that is executed on the GPU as many different threads. is an array of threads that execute a kernel concurrently or in parallel. compute-intensive portions of applications running on the host are off-loaded onto the device.Chapter 2. The thread identifier is a three-element vector tid. assign specific input and output positions. a portion of an application that is executed many times. and select work to perform. The vector ntid specifies the number of threads in each CTA dimension. Programs use a data parallel decomposition to partition inputs. and ntid. A cooperative thread array. or 3D CTA. 2D. 2. 2010 7 .

%ntid. 8 January 24.2. Threads within a warp are sequentially numbered.0 Threads within a CTA execute in SIMT (single-instruction. The host issues a succession of kernel invocations to the device. so PTX includes a run-time immediate constant. which may be used in any instruction where an immediate operand is allowed. Typically. WARP_SZ. so that the total number of threads that can be launched in a single kernel invocation is very large. The warp size is a machine-dependent constant. This comes at the expense of reduced thread communication and synchronization. and %gridid. However.2. 2010 . 2. such that the threads execute the same instructions at the same time. %ctaid. Multiple CTAs may execute concurrently and in parallel. %nctaid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Each grid of CTAs has a 1D. or sequentially. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). because threads in different CTAs cannot communicate and synchronize with each other. 2D . depending on the platform. a warp has 32 threads. read-only special registers %tid. Some applications may be able to maximize performance with knowledge of the warp size. or 3D shape specified by the parameter nctaid.PTX ISA Version 2. multiple-thread) fashion in groups called warps. Threads may read and use these values through predefined. Each grid also has a unique temporal grid identifier (gridid). Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. A warp is a maximal subset of threads from a single CTA. CTAs that execute the same kernel can be batched together into a grid of CTAs.

1) Thread (0. Thread Batching January 24. 0) Thread (4. 2) Thread (3. 1) Thread (1. 0) Thread (0. 0) Thread (2. 1) CTA (2. 0) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 2010 9 . 0) Thread (1. 1) Thread (4. 1) Thread (3. Figure 1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) CTA (2. 1) Thread (0. 0) CTA (1. 1) CTA (1. A grid is a set of CTAs that execute independently. 2) Thread (1. 0) CTA (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0.Chapter 2. 2) Thread (2. 2) Thread (4. 1) Thread (2.

Each thread has a private local memory. for more efficient transfer. Finally. for some specific data formats. Texture memory also offers different addressing modes. all threads have access to the same global memory.0 2. The device memory may be mapped and read or written by the host. 2010 . or. referred to as host memory and device memory.PTX ISA Version 2. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. The global. 10 January 24. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. constant. as well as data filtering. constant. and texture memory spaces are optimized for different memory usages.3. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. and texture memory spaces are persistent across kernel launches by the same application. The global. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. respectively. Both the host and the device maintain their own local memory.

0) Block (1. 2010 11 . 1) Block (2. 2) Block (1. 2) Figure 2. 0) Block (2. 1) Block (1. Memory Hierarchy January 24.Chapter 2. 1) Grid 1 Global memory Block (0. 0) Block (0. 0) Block (0. 0) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (1.

PTX ISA Version 2.0 12 January 24. 2010 .

a cell in a grid-based computation). Parallel Thread Execution Machine Model 3. January 24. manages. allowing. When a multiprocessor is given one or more thread blocks to execute. The multiprocessor maps each thread to one scalar processor core. a voxel in a volume. As thread blocks terminate. The multiprocessor creates. and executes threads in groups of parallel threads called warps. When a host program invokes a kernel grid. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. and executes concurrent threads in hardware with zero scheduling overhead. 2010 13 . the first parallel thread technology. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). each warp contains threads of consecutive. the warp serially executes each branch path taken.1. and when all paths complete. multiple-thread). If threads of a warp diverge via a data-dependent conditional branch. it splits them into warps that get scheduled by the SIMT unit. A warp executes one common instruction at a time. disabling threads that are not on that path. increasing thread IDs with the first warp containing thread 0. The way a block is split into warps is always the same.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. (This term originates from weaving. and each scalar thread executes independently with its own instruction address and register state.Chapter 3. manages. new blocks are launched on the vacated multiprocessors. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. At every instruction issue time. A multiprocessor consists of multiple Scalar Processor (SP) cores. a multithreaded instruction unit. and on-chip shared memory. It implements a single-instruction barrier synchronization. The multiprocessor SIMT unit creates. schedules. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. so full efficiency is realized when all threads of a warp agree on their execution path. Branch divergence occurs only within a warp. different warps execute independently regardless of whether they are executing common or disjointed code paths. the multiprocessor employs a new architecture we call SIMT (single-instruction. The threads of a thread block execute concurrently on one multiprocessor. the threads converge back to the same execution path. for example. To manage hundreds of threads running several different programs. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image.

the programmer can essentially ignore the SIMT behavior. require the software to coalesce loads into vectors and manage divergence manually. As illustrated by Figure 3. each read.PTX ISA Version 2. modify. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. the kernel will fail to launch. A multiprocessor can execute as many as eight thread blocks concurrently. as well as data-parallel code for coordinated threads. on the other hand. but one of the writes is guaranteed to succeed.0 SIMT architecture is akin to SIMD (Single Instruction. If there are not enough registers or shared memory available per multiprocessor to process at least one block. whereas SIMT instructions specify the execution and branching behavior of a single thread. and writes to the same location in global memory for more than one of the threads of the warp. SIMT enables programmers to write thread-level parallel code for independent. the number of serialized writes that occur to that location and the order in which they occur is undefined. write to that location occurs and they are all serialized. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. In practice. A key difference is that SIMD vector organizations expose the SIMD width to the software. For the purposes of correctness. which is a read-only region of device memory. Vector architectures. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. In contrast with SIMD vector machines. which is a read-only region of device memory. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. scalar threads. 2010 . but the order in which they occur is undefined. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. 14 January 24. modifies. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. however. • The local and global memory spaces are read-write regions of device memory and are not cached. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. If an atomic instruction executed by a warp reads.

Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Figure 3.Chapter 3. 2010 15 . Hardware Model January 24.

PTX ISA Version 2.0 16 January 24. 2010 .

All whitespace characters are equivalent. #endif. #ifdef. 2010 17 . The C preprocessor cpp may be used to process PTX source files. Comments Comments in PTX follow C/C++ syntax. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.version directive specifying the PTX language version. January 24. Lines are separated by the newline character (‘\n’). whitespace is ignored except for its use in separating tokens in the language. Lines beginning with # are preprocessor directives. using non-nested /* and */ for comments that may span multiple lines. PTX is case sensitive and uses lowercase for keywords.2. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Source Format Source files are ASCII text. 4. #else. Pseudo-operations specify symbol and addressing management. followed by a . #line.target directive specifying the target architecture assumed. Each PTX file must begin with a . See Section 9 for a more information on these directives. The following are common preprocessor directives: #include.1. 4. Syntax PTX programs are a collection of text source files. and using // to begin a comment that extends to the end of the current line. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.Chapter 4. Comments in PTX are treated as whitespace. #if. #define.

visible 4.align .shared .0 4.local . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. Table 1.const . written as @!p.b32 r1. Instruction keywords are listed in Table 2. 2.version . constant expressions. or label names.pragma . The guard predicate follows the optional label and precedes the opcode. and is written as @p.3.tex .1. Operands may be register variables.minnctapersm .param .maxntid . mov. The guard predicate may be optionally negated.reg . shl. followed by source operands.3.target . array[r1]. r1.file PTX Directives .b32 r1. Directive Statements Directive keywords begin with a dot. 0. All instruction keywords are reserved tokens in PTX. Statements A PTX statement is either a directive or an instruction. Examples: . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.PTX ISA Version 2.f32 r2. where p is a predicate register. r2.global start: .entry .f32 array[N]. %tid.maxnctapersm . and terminated with a semicolon. Instructions have an optional guard predicate which controls conditional execution. address expressions.loc .5.global .reg . .section .b32 r1. r2.func . so no conflict is possible with user-defined identifiers. 2010 .maxnreg . .3.b32 add. ld. r2.x.sreg . Statements begin with an optional label and end with a semicolon.2. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.global. The destination operand is first. 18 January 24.extern .

Syntax Table 2. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4.

except that the percentage sign is not allowed. dollar. digits.0 4.PTX ISA Version 2. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. The percentage sign can be used to avoid name conflicts. or dollar characters. or they start with an underscore.4. …. between user-defined variable names and compiler-generated names. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. 2010 . underscore. Many high-level languages such as C and C++ follow similar rules for identifier names. Table 3.g. listed in Table 3. digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign. %pm3 WARP_SZ 20 January 24. or percentage character followed by one or more letters. e. underscore. PTX allows the percentage sign as the first character of an identifier.

Floating-point literals may be written with an optional decimal point and an optional signed exponent. 4.u64). Type checking rules remain the same for integer. When used in an instruction or data initialization.s64) unless the value cannot be fully represented in .5.u64. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. 2010 21 . To specify IEEE 754 doubleprecision floating point values. For predicate-type data and instructions. To specify IEEE 754 single-precision floating point values. Integer literals may be written in decimal.2. integer constants are allowed and are interpreted as in C. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. the constant begins with 0f or 0F followed by 8 hex digits. Syntax 4. and bit-size types. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. The syntax follows that of C. octal. the constant begins with 0d or 0D followed by 16 hex digits.s64 or the unsigned suffix is specified.. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. the sm_1x and sm_20 targets have a WARP_SZ value of 32. where the behavior of the operation depends on the operand types. i. each integer constant is converted to the appropriate size based on the data or instruction type at its use.e. in which case the literal is unsigned (. or binary notation. 0[fF]{hexdigit}{8} // single-precision floating point January 24. hexadecimal.. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.e. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Unlike C and C++.1. there is no suffix letter to specify size. every integer constant has type . floating-point. 4. zero values are FALSE and non-zero values are TRUE.5. literals are always represented in 64-bit double-precision format.Chapter 4. Constants PTX supports integer and floating-point constants and constant expressions. i.s64 or . Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. These constants may be used in data initialization and as operands to instructions. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.5.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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f64 use usual conversions .s64 .f64 : .u64.u64 .s64 .s64.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .s64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.Chapter 4.u64 .s64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 use usual conversions .f64 integer .u64 .s64) + . Table 5. Syntax 4.f64 use usual conversions .6.s64 .u64 1st unchanged.f64 integer . .f64 integer integer integer integer integer int ?.f64 converted type constant literal + ! ~ Cast Binary (. 2nd is . or .s64 .5.s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 same as source .u64 .f64 converted type .u64 same as 1st operand .u64 .u64 .u64) (. 2010 25 .

PTX ISA Version 2.0 26 January 24. 2010 .

The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. pre-defined.global . shared by all threads. the kinds of resources will be common across platforms. addressability. and Variables While the specific resources available in a given target GPU will vary. Global memory. Table 6. . State Spaces. Shared.local . Read-only.Chapter 5. private to each thread. 2010 27 . State Spaces A state space is a storage area with particular characteristics. All variables reside in some state space.sreg . Kernel parameters. Addressable memory shared between threads in 1 CTA. Global texture memory (deprecated). and level of sharing between threads. access speed. Types. and properties of state spaces are shown in Table 5. fast. Special registers. and these resources are abstracted in PTX through state spaces and data types.param . access rights. defined per-grid.1. platform-specific.const . read-only memory.reg . The characteristics of a state space include its size. defined per-thread. The list of state spaces is shown in Table 4. or Function or local parameters.tex January 24. 5. Local memory. Name State Spaces Description Registers.shared .

or 64-bits.param instructions.1. 28 January 24. Register size is restricted. unsigned integer.global . predicate) or untyped.e.local . clock counters.param (used in functions) .reg state space) are fast storage locations. Registers may be typed (signed integer.const . 5. and thread parameters. The most common use of 8-bit registers is with ld. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . or 128-bits.reg . Device function input parameters may have their address taken via mov.param and st.sreg . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.sreg) state space holds predefined. The number of registers is limited. such as grid.. 1 Accessible only via the ld. the parameter is then located on the stack frame and its address is in the . All special registers are predefined. Special Register State Space The special register (. st. 64-. or as elements of vector tuples. 3 Accessible only via the tex instruction. and performance monitoring registers. and cvt instructions.local state space.2. For each architecture.0 Table 7. floating point.shared .param (as input to kernel) . 32-. Address may be taken via mov instruction. Register State Space Registers (. 2010 . Registers differ from the other state spaces in that they are not fully addressable. i. it is not possible to refer to the address of a register. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 32-.1.tex Restricted Yes No3 5. register variables will be spilled to memory. and vector registers have a width of 16-. and will vary from platform to platform. platform-specific registers.1. scalar registers have a width of 8-. causing changes in performance. CTA. aside from predicate registers which are 1-bit. Registers may have alignment boundaries required by multi-word loads and stores.PTX ISA Version 2. 16-. When the limit is exceeded. 2 Accessible via ld.param instruction.

local) is private memory for each thread to keep its own data. as in lock-free and wait-free style programming. each pointing to the start address of the specified constant bank.global to access global variables.const[2] . Constant State Space The constant (. whereas local memory variables declared January 24. For example. 5. This reiterates the kind of parallelism available in machines that run PTX. there are eleven 64KB banks. initialized by the host. Multiple incomplete array variables declared in the same bank become aliases. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.extern . bank zero is used.sync instruction are guaranteed to be visible to any reads after the barrier instruction. bank zero is used for all statically-sized constant variables. The size is limited. an incomplete array in bank 2 is accessed as follows: .local and st. Consider the case where one thread executes the following two assignments: a = a + 1.extern . If no bank number is given.1. Sequential consistency is provided by the bar. where the size is not known at compile time. For any thread in a context.Chapter 5.3. Types.b32 %r1. For example. All memory writes prior to the bar. the declaration .5.b32 const_buffer[]. State Spaces. and atom. This pointer can then be used to access the entire 64KB constant bank. and Variables 5. the bank number must be provided in the state space of the load instruction. where bank ranges from 0 to 10. It is typically standard memory with cache. If another thread sees the variable b change.const[bank] modifier. By convention. Global State Space The global (. as it must be allocated on a perthread basis.local to access local variables.1. the stack is in local memory. The remaining banks may be used to implement “incomplete” constant arrays (in C. 2010 29 . // load second word 5. Use ld.sync instruction.global) state space is memory that is accessible by all threads in a context. Banks are specified using the .1.const[2]. Global memory is not sequentially consistent. Threads must be able to do their work without waiting for other threads to do theirs.4. In implementations that support a stack. Use ld.global.const) state space is a read-only memory. Local State Space The local state space (. ld. all addresses are in global memory are shared. for example). results in const_buffer pointing to the start of constant bank two. The constant memory is organized into fixed size banks. For the current devices. [const_buffer+4].const[2] . b = b – 1. Module-scoped local memory variables are stored at fixed addresses.global. the store operation updating a may still be in flight. To access data in contant banks 1 through 10.b32 const_buffer[]. st. Threads wait at the barrier until all threads in the CTA have arrived. It is the mechanism by which different CTAs and different grids can communicate.

No access protection is provided between parameter and global space in this case. 2010 . The address of a kernel parameter may be moved into a register using the mov instruction. Values passed from the host to the kernel are accessed through these parameter variables using ld. Note: The location of parameter space is implementation specific.1. For example. typically for passing large structures by value to a function.reg .u32 %ptr.0 and requires target architecture sm_20. read-only variables declared in the . The resulting address is in the . 5.u32 %ptr.u32 %n.6. device function parameters were previously restricted to the register state space. Note that PTX ISA versions 1. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. These parameters are addressable.1. [%ptr]. PTX code should make no assumptions about the relative locations or ordering of . %n.entry bar ( .u32 %n. Therefore. In implementations that do not support a stack.1.param .param state space. .param instructions. The kernel parameter variables are shared across all CTAs within a grid.param) state space is used (1) to pass input arguments from the host to the kernel. ld.b8 buffer[64] ) { . … 30 January 24. ld. per-kernel versus per-thread).f64 %d.entry foo ( . .param space.param. Example: .b32 len ) { .f64 %d.reg .param space variables.align 8 .param instructions.reg .param state space and is accessed using ld. Similarly. (2a) to declare formal input and return parameters for device functions called from within kernel execution.6. The use of parameter state space for device function parameters is new to PTX ISA version 2.param. all local memory variables are stored at fixed addresses and recursive function calls are not supported.b32 N. [N]. ld.param. … Example: .0 within a function or kernel body are allocated on the stack. 5. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).u32 %n.PTX ISA Version 2. len. mov.param . Parameter State Space The parameter (. in some implementations kernel parameters reside in global memory.param .x supports only kernel function parameters in . [buffer]. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.

1.param.param space is also required whenever a formal parameter has its address taken within the called function. (4. Example: // pass object of type struct { double d. … See the section on function call syntax for more details.param.b8 mystruct.param formal parameter having the same size and alignment as the passed argument.s32 %y.s32 %y.reg .param and function return parameters may be written using st.param.f64 [mystruct+0].local instructions.f64 %d. Types. it is illegal to write to an input parameter or read from a return parameter. and so the address will be in the . x. such as C structures larger than 8 bytes.6. ld. is flattened.func foo ( . . }. It is not possible to use mov to get the address of a return parameter or a locally-scoped . Aside from passing structures by value. } mystruct. State Spaces. int y. call foo. Typically. ld. The most common use is for passing objects by value that do not fit within a PTX register. [buffer]. [buffer+8].reg . the address of a function input parameter may be moved into a register using the mov instruction.0 extends the use of parameter space to device function parameters.reg .local state space and is accessed via ld. dbl.align 8 .local and st.param. This will be passed by value to a callee. and Variables 5. . mystruct). int y. Function input parameters may be read via ld. passed to foo … . Note that the parameter will be copied to the stack if necessary. January 24.param.2.param byte array variable that represents a flattened C structure or union. the caller will declare a locally-scoped . st.s32 x.reg .param space variable.s32 [mystruct+8]. . … st. In this case. .f64 %d.Chapter 5. 2010 31 . .f64 dbl.param .b32 N.reg .b8 buffer[12] ) { . a byte array in parameter space is used.align 8 . Device Function Parameters PTX ISA version 2. In PTX. … } // code snippet from the caller // struct { double d. . which declares a .param .

Another is sequential access from sequential threads. Texture memory is read-only. tex_d.u32 tex_a. 32 January 24. Texture State Space (deprecated) The texture (.u32 .8. For example.u32 tex_a.1.tex .7. Multiple names may be bound to the same physical texture identifier. and variables declared in the .global . 5. Shared State Space The shared (.global state space.shared to access shared variables. The texture name must be of type .1.u32 or .shared) state space is a per-CTA region of memory for threads in a CTA to share data.7. One example is broadcast. and . is equivalent to .tex . tex_f.texref variables in the .texref tex_a. The . Shared memory typically has some optimizations to support the sharing. tex_d. Physical texture resources are allocated on a per-module granularity. A texture’s base address is assumed to be aligned to a 16-byte boundary.texref.shared and st.6 for its use in texture instructions. where all threads read from the same address. tex_c. It is shared by all threads in a context.tex state space are equivalent to module-scoped .u32 .tex directive is retained for backward compatibility.0 5.tex directive will bind the named texture memory variable to a hardware texture identifier.tex variables are required to be defined in the global scope.PTX ISA Version 2.tex . See Section 5. An address in shared memory can be read and written by any thread in a CTA. 2010 . The .tex) state space is global memory accessed via the texture instruction. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.texref type and Section 8.tex .tex . An error is generated if the maximum number of physical resources is exceeded. a legacy PTX definitions such as .3 for the description of the . where texture identifiers are allocated sequentially beginning with zero. and programs should instead reference texture memory through variables of type . Use ld.u64. Example: .u32 .

.f64 types. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Register variables are always of a fundamental type.b16. and Variables 5. or converted to other types and sizes. Restricted Use of Sub-Word Sizes The . For example. and . In principle. The same typesize specifiers are used for both variable definitions and for typing instructions. The .u64 . Signed and unsigned integer types are compatible if they have the same size. . . stored. Operand types and sizes are checked against instruction types for compatibility.2.pred Most instructions have one or more type specifiers.f32 and . Fundamental Types In PTX. . 2010 33 .f64 types.b64 . . st. The bitsize type is compatible with any fundamental type having the same size. .s32.f16. 5.f64 . and cvt instructions. stored. and converted using regular-width registers.b32.u16.b8 instruction types are restricted to ld.f32 and .u8.Chapter 5. January 24.2. ld. The following table lists the fundamental type specifiers for each basic type: Table 8. Types. . and instructions operate on these types. so their names are intentionally short. . st. Types 5.b8. but typed variables enhance program readability and allow for better operand type checking. so that narrow values may be loaded.s8.u32. . needed to fully specify instruction behavior. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.s16.u8. all variables (aside from predicates) could be declared using only bit-size types. A fundamental type specifies both a basic type and a size.f32. State Spaces.1.s64 .2. All floating-point instructions operate only on .2. the fundamental types reflect the native data types supported by the target architectures. .s8. . For convenience.f16 floating-point type is allowed only in conversions to and from . Two fundamental types are compatible if they have the same basic type and are the same size.

{u32. and Surface Types PTX includes built-in “opaque” types for defining texture. but the pointer cannot otherwise be treated as an address. but all information about layout. Sampler.e. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.texref handle. In the independent mode. or performing pointer arithmetic will result in undefined results. In independent mode the fields of the . passed as a parameter to functions. accessing the pointer with ld and st instructions.texref. and overall size is hidden to a PTX program. suq).u64} reg. texture and sampler information each have their own handle. Creating pointers to opaque variables using mov.samplerref variables. suld. In the unified mode. For working with textures and samplers.texref type that describe sampler properties are ignored. samplers. 2010 . Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. and de-referenced by texture and surface load. since these properties are defined by . hence the term “opaque”. The following tables list the named members of each type for unified and independent texture modes. sust. and query instructions. the resulting pointer may be stored to and loaded from memory. These types have named fields similar to structures. and . 34 January 24. PTX has two modes of operation. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists.3. opaque_var. and surface descriptor variables. field ordering. store. base address.0 5. i. Texture.. allowing them to be defined separately and combined at the site of usage in the program. . texture and sampler information is accessed through a single . The three built-in types are .surfref.PTX ISA Version 2. Retrieving the value of a named member via query instructions (txq. or surfaces via texture and surface load/store instructions (tex. sured). sampler.samplerref. Referencing textures.

Chapter 5.texref values .samplerref values N/A N/A N/A N/A nearest. clamp_to_edge.texref values in elements in elements in elements 0. Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9. linear wrap. Member width height depth Opaque Type Fields in Unified Texture Mode . Types. clamp_ogl.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. State Spaces. mirror. linear wrap. 1 ignored ignored ignored ignored . 1 nearest. 2010 35 .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_ogl. mirror. clamp_to_border 0. clamp_to_edge. clamp_to_border N/A N/A N/A N/A N/A .

samplerref tsamp1 = { addr_mode_0 = clamp_to_border.surfref my_surface_name.PTX ISA Version 2. As kernel parameters. 2010 . .texref tex1. When declared at module scope. filter_mode = nearest }.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. Example: . . these variables must be in the . Example: .global . At module scope.global . 36 January 24.global .global state space.param state space.global .global .texref my_texture_name. these variables are declared in the .samplerref my_sampler_name. . the types may be initialized using a list of static expressions assigning values to the named members.

global . 5.u16 uv. for example.v2 . to enable vector load and store instructions which require addresses aligned to a multiple of the access size.4.0. PTX supports types for simple aggregate objects such as vectors and arrays.v1. 0}.const . Examples: . vector variables are aligned to a multiple of their overall size (vector length times base-type size). In addition to fundamental types.v4 . 0. This is a common case for three-dimensional grids. // typedef . Vectors must be based on a fundamental type. 0.Chapter 5. Vectors cannot exceed 128-bits in length.v4.0}. its type and size.2.v4. and an optional fixed address for the variable. . Variables In PTX. .global .shared .4. . etc.struct float4 { . Three-element vectors may be handled by using a . .f64 is not allowed.v4 .v4 . r.pred p. and they may reside in the register space.global . Variable Declarations All storage for data is specified with variable declarations.f32 V. its name.s32 i. q. textures.v4 vector. // a length-4 vector of bytes By default.v3 }. January 24.1.reg . where the fourth element provides padding. . 2010 37 . 1. 5. State Spaces. Predicate variables may only be declared in the register state space.v2. Types. an optional array size.f32 accel.u32 loc.global . . // a length-4 vector of floats . Examples: . an optional initializer.4.f32 bias[] = {-1.reg .u8 bg[4] = {0.struct float4 coord. . // a length-2 vector of unsigned ints .f32 v0. Every variable must reside in one of the state spaces enumerated in the previous section. and Variables 5.v2 or .b8 v. a variable declaration describes both the variable’s type and its state space.reg .global . A variable declaration names the space in which the variable resides. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . Vectors Limited-length vector types are supported.

05.{. -1}. 0}.05}}.0 5.0}.u8 mailbox[128]. {0. Examples: ... variable initialization is supported only for constant and global state spaces. or is left empty.u16 kernel[19][19].global . Array Declarations Array declarations are provided to allow the programmer to reserve space.b32 ptr = rgba. 2010 . ..0.pred. being determined by an array initializer.0..0}.f32 blur_kernel[][] = {{. {0.global . this can be used to statically initialize a pointer to a variable. 5.s32 offset[][] = { {-1..1.v4 . 38 January 24.4.4. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.3.4.u64. 1} }. {0.shared . The size of the dimension is either a constant expression.f16 and . Initializers are allowed for all types except .1. .05. 19*19 (361) halfwords are reserved (722 bytes). Variable names appearing in initializers represent the address of the variable. 0}. . Similarly. A scalar takes a single value. this can be used to initialize a jump table to be used with indirect branches or calls. label names appearing in initializers represent the address of the next instruction following the label.05}.0.u8 rgba[3] = {{1.global . Variables that hold addresses of variables or instructions should be of type . Initializers Declared variables may specify an initial value using a syntax similar to C/C++. {1. // address of rgba into ptr Currently.global . {0.global . The size of the array specifies how many elements should be reserved.1.u32 or .1. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). To declare an array.1. .s32 n = 10. .{.local .4..PTX ISA Version 2.0}}. Here are some examples: . For the kernel declaration above.0.1}. where the variable name is followed by an equals sign and the initial value or values for the variable.

%r1. and may be preceded by an alignment specifier. not for individual elements. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.b8 bar[8] = {0. suppose a program uses a large number. named %r0. %r1. Examples: // allocate array at 4-byte aligned address.align byte-count specifier immediately following the state-space specifier. 2010 39 . The variable will be aligned to an address which is an integer multiple of byte-count. State Spaces. …. and Variables 5.0. The default alignment for scalar and array variables is to a multiple of the base-type size. .reg . of .4. Parameterized Variable Names Since PTX supports virtual registers. . 5.align 4 . Alignment is specified using an optional .b32 %r<100>. %r99. alignment specifies the address alignment for the starting address of the entire array. These 100 register variables can be declared as follows: . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.4.0}.Chapter 5. // declare %r0. it is quite common for a compiler frontend to generate a large number of register names.const . For example.6. say one hundred. For arrays. The default alignment for vector variables is to a multiple of the overall vector size..b32 variables..0. Types.. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Array variables cannot be declared this way. Elements are bytes.0. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.0. nor are initializers permitted.0. January 24.5.2. Rather than require explicit declaration of every name.

0 40 January 24.PTX ISA Version 2. 2010 .

Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Predicate operands are denoted by the names p. as its job is to convert from nearly any data type to any other data type (and size). . Operand Type Information All operands in instructions have a known type from their declarations. b. Source Operands The source operands are denoted in the instruction descriptions by the names a. For most operations. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. st. 6. the sizes of the operands must be consistent. January 24. The result operand is a scalar or vector variable in the register state space. and cvt instructions copy data from one location to another.Chapter 6. Each operand type must be compatible with the type determined by the instruction template and instruction type. q. There is no automatic conversion between types.3. so operands for ALU instructions must all be in variables declared in the .2. s. PTX describes a load-store machine. The cvt (convert) instruction takes a variety of operand types and sizes. The mov instruction copies data between registers. Instruction Operands 6. Most instructions have an optional predicate guard that controls conditional execution. 2010 41 . Integer types of a common size are compatible with each other.1. and a few instructions have additional predicate source operands. r. and c. mov.reg register state space. 6. The bit-size type is compatible with every type having the same size. The ld. Instructions ld and st move data from/to addressable state spaces to/from registers.

6.v4 .u16 r0. address registers. .const . p. The syntax is similar to that used in many assembly languages.reg . and Vectors Using scalar variables as operands is straightforward. Examples include pointer arithmetic and pointer comparisons. q.shared. .v4. arrays.4. Here are a few examples: .PTX ISA Version 2.0 6. [tbl+12].s32 mov. .u16 x. address register plus byte offset.u16 ld.const.s32 tbl[256]. . r0.reg .s32 q.global .[x]. ld.f32 ld. Arrays. Address expressions include variable names.4.reg . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.shared . The interesting capabilities begin with addresses. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. All addresses and address computations are byte-based.reg . and immediate address expressions which evaluate at compile-time to a constant address.f32 V. W. [V].u32 42 January 24. The address is an offset in the state space in which the variable is declared. tbl. 2010 . The mov instruction can be used to move the address of a variable into a pointer.v4 . Load and store operations move data between registers and locations in addressable state spaces. .f32 W. and vectors. .1.b32 p.gloal. Using Addresses. there is no support for C-style pointer arithmetic.

. for use in an indirect branch or call.x V. A brace-enclosed list is used for pattern matching to pull apart vectors.4. The size of the array is a constant in the program. mov.v2.r.b.v4. Rb.u32 s.reg . Vectors may also be passed as arguments to called functions. or by indexing into the array using square-bracket notation. and in move instructions to get the address of the label or function into a register. or a simple “register with constant offset” expression. say {Ra.a 6. .f32 ld. d. The registers in the load/store operations can be a vector.b V.4.d}.f32 a.b and . correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.f32 {a. ld. Rc. b. . or a braceenclosed list of similarly typed scalars. a[0].r V.w. as well as the typical color fields . // move address of a[1] into s 6. ld. The expression within square brackets is either a constant integer.w = = = = V.4. where the offset is a constant expression that is either added or subtracted from a register variable. January 24.global. mov. which may improve memory performance.z V. [addr+offset2]. c.global.z and .b. 2010 43 . . Here are examples: ld.c. V.c. Vector loads and stores can be used to implement wide loads and stores.u32 s. . Array elements can be accessed using an explicitly calculated byte address.3. a register variable.global.4.d}. [addr+offset]. and the identifier becomes an address constant in the space where the array is declared. Arrays as Operands Arrays of all types can be declared. Rd}. and tex. which include mov.a.v4 .Chapter 6. Instruction Operands 6. st. If more complicated indexing is desired.g V.global. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. a[N-1]. Vectors as Operands Vector operands are supported by a limited subset of instructions.2.u32 {a. .y. Examples are ld.x. a[1].u32 s. Vector elements can be extracted from the vector with the suffixes .g.v4. Elements in a brace-enclosed vector.y V.reg . V2. it must be written as an address calculation prior to use.f32 V.

000 for f16).s32. Type Conversion All operands to all arithmetic. 2010 . the u16 is zero-extended to s32.5. For example. 44 January 24. logic. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. and data movement instruction must be of the same type and size. 6.PTX ISA Version 2.5.u16 instruction is given a u16 source operand and s32 as a destination operand. Operands of different sizes or types must be converted prior to the operation. and ~131. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.1.0 6. if a cvt. except for operations where changing the size and/or type is part of the definition of the instruction.

then sign-extend to 32-bits. f2f = float-to-float. zext = zero-extend. chop = keep only low bits that fit.s16. Instruction Operands Table 11. January 24. s2f = signed-to-float. cvt. f2u = float-to-unsigned. the result is extended to the destination register width after chopping. f2s = float-to-signed. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. For example. u2f = unsigned-to-float. 2010 45 . The type of extension (sign or zero) is based on the destination format.u32 targeting a 32-bit register will first chop to 16-bits. Notes 1 If the destination register is wider than the destination format.Chapter 6.

Rounding Modifiers Conversion instructions may specify a rounding modifier. The following tables summarize the rounding modifiers. Table 12. choosing even integer if source is equidistant between two integers. there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 .PTX ISA Version 2. Modifier .rni .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rn . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.2.rm .rzi .rmi . Modifier .5. In PTX.rz .rpi Integer Rounding Modifiers Description round to nearest integer.0 6.

Registers are fastest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. 2010 47 . Much of the delay to memory can be hidden in a number of ways.Chapter 6. first access is high Notes January 24. Table 14. The register in a store operation is available much more quickly. Table 11 gives estimates of the costs of using different kinds of memory. while global memory is slowest. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Another way to hide latency is to issue the load instructions as early as possible. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution.6. Operand Costs Operands from different state spaces affect the speed of an operation. Instruction Operands 6.

2010 .0 48 January 24.PTX ISA Version 2.

stack layout. stack-based ABI. A function declaration specifies an optional list of return parameters. and is represented in PTX as follows: . These include syntax for function definitions. A function definition specifies both the interface and the body of the function.func foo { … ret. Abstracting the ABI Rather than expose details of a particular calling convention.Chapter 7.func directive. and return values may be placed directly into register variables. implicitly saving the return address. execution of the call instruction transfers control to foo. so recursion is not yet supported. } … call foo. or prototype. Scalar and vector base-type input and return parameters may be represented simply as register variables.1. In this section. Function declarations and definitions In PTX. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. 2010 49 . function calls. together these specify the function’s interface. the function name. parameter passing. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and memory allocated on the stack (“alloca”). functions are declared and defined using the . NOTE: The current version of PTX does not implement the underlying. At the call. we describe the features of PTX needed to achieve this hiding of the ABI. … Here. support for variadic functions (“varargs”). Execution of the ret instruction within foo transfers control to the instruction following the call. A function must be declared or defined prior to being called. The simplest function has no parameters or return values. 7. arguments may be register variables or constants. and an optional list of input parameters. and Application Binary Interface (ABI). January 24.

[y+9]. %rc1.b8 c1. byte array in . 2010 . Since memory accesses are required to be aligned to a multiple of the access size. consider the following C structure. [y+11].reg . ret. a . For example. … st. First.PTX ISA Version 2.param.c1.s32 x.u32 %ptr.param .u32 %res) inc_ptr ( .reg .b8 c4.param space call (%out).b8 [py+ 8]. st. %rc2.param variable y is used in function definition bar to represent a formal parameter. // scalar args in .func (. this structure will be flattened into a byte array. … ld.align 8 py[12]. char c[4].param. c4.reg . . }.param.param. (%r1. bumpptr. st.f64 f1.param.f1.param.b8 c3. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .b8 .param state space is used to pass the structure by value: .reg space.b32 c1.reg . [y+8]. c3.s32 out) bar (. %rc2. %ptr. } … call (%r1). ld. In PTX. st. . … In this example.c4.b64 [py+ 0].f64 field are aligned. inc_ptr.4). %rd. } { . The .b8 [py+ 9].func (. st.param. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .reg . .param . %inc. ld. ld. 50 January 24. %rc1.u32 %inc ) { add. (%x.c2. ld. [y+10].param. py).u32 %res. [y+0]. passed by value to a function: struct { double dbl.param space variables are used in two ways.param space memory. note that . … … // computation using x.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 .param.0 Example: .f64 f1.b8 [py+10].b8 c2.reg .c3.b8 [py+11]. a .param. Second.align 8 y[12]) { . c2.reg .

param variables or . Note that the choice of . A . . This enables backend optimization and ensures that the . 2010 51 . 8.param space byte array with matching type.param argument must be declared within the local scope of the caller.reg state space in this way provides legacy support. size.param arguments. The . Supporting the . January 24. • • • Input and return parameters may be . In the case of .reg space variable of matching type and size.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. a .param instructions used for argument passing must be contained in the basic block with the call instruction. all st.param variables. and alignment of parameters. For . or a constant that can be represented in the type of the formal parameter. Typically.reg state space can be used to receive and return base-type scalar and vector values.reg variables.param memory must be aligned to a multiple of 1.g.param byte array is used to collect together fields of a structure being passed by value. the corresponding argument may be either a . • • • For a callee. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. size. • The .reg space variable with matching type and size. For a caller. or constants.reg or .param space formal parameters that are base-type scalar or vector variables. In the case of ..param space formal parameters that are byte arrays. The following restrictions apply to parameter passing. Parameters in .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. 2.param or .reg variables. • The .param state space use in device functions.param or . or 16 bytes.param and ld. For a callee. or a constant that can be represented in the type of the formal parameter. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. the argument must also be a .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. In the case of . the corresponding argument may be either a .param state space is used to receive parameter values and/or pass return values back to the caller.reg space formal parameters. The . • • Arguments may be .Chapter 7. 4. and alignment. For a caller. Abstracting the ABI The following is a conceptual way to think about the .

0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays. PTX 2. For sm_2x targets. formal parameters may be in either .0 7.0 restricts functions to a single return value. 2010 . PTX 2. 52 January 24. formal parameters were restricted to .x In PTX ISA version 1.1.0.PTX ISA Version 2.1. and a .x. and .param byte array should be used to return objects that do not fit into a register. Changes from PTX 1.reg or .reg state space. and there was no support for array parameters. Objects such as C structures were flattened and passed or returned using multiple registers. PTX 1. In PTX ISA version 2.param state space.x supports multiple return values for this purpose.

bra Loop.s32 result ) maxN ( . 8. iteratively access.func %va_end (. .reg . call (val).reg . In both cases. This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg .reg . 2010 53 .pred p. %va_end is called to free the variable argument list handle.u32. setp. 2.b64 val) %va_arg64 (.2.func (. %va_start. maxN.h and varargs. (ap).b32 result. 2.u32 sz.reg .func (. 4. the size may be 1. (3. . ) { . %r2. %s1. variadic functions are declared with an ellipsis at the end of the input parameter list.u32 b. the alignment may be 1.h headers in C.ge p.s32 val. %r1. or 8 bytes.. 2. N.u32 N.reg .func baz ( .reg . To support functions with a variable number of arguments.reg . for %va_arg64.reg .reg .u32 ptr.reg . following zero or more fixed parameters: . For %va_arg.reg . // default to MININT mov. Variadic functions NOTE: The current version of PTX does not support variadic functions. bra Done. 0. or 16 bytes.s32 result. %s2). Abstracting the ABI 7. . %va_arg.reg .Chapter 7.reg . ret. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . … %va_start returns Loop: @p Done: January 24. } … call (%max). (ap. … ) . . PTX provides a high-level mechanism similar to the one provided by the stdarg. call (ap). 4. .u32 align) .b32 ctr. 4).u32 ptr) %va_start . along with the size and alignment of the next data value to be accessed.func okay ( … ) Built-in functions are provided to initialize. ctr.u32 ptr. (2. 0x8000000. .u32 a. val. In PTX.u32 sz.reg . . Once all arguments have been processed.func ( . and end access to a list of variable arguments. %r3). 4. The function prototypes are defined as follows: .reg .u32 align) . maxN. max.b32 val) %va_arg (. mov. the size may be 1.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 ap. ctr. . result.. or 4 bytes.func (.reg . … call (%max). call %va_end.

The array is then accessed with ld.reg . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.3.0 7. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. 2010 . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. defined as follows: . a function simply calls the built-in function %alloca. To allocate memory. Alloca NOTE: The current version of PTX does not support alloca.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.u32 ptr ) %alloca ( .func ( . 54 January 24.reg .PTX ISA Version 2.local and st.local instructions. If a particular alignment is required.

opcode D. the semantics are described. A. B.Chapter 8. For instructions that create a result value. 2010 55 .s32. PTX Instructions PTX instructions generally have from zero to four operands.2. // p = (a < b). We use a ‘|’ symbol to separate multiple destination registers. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. a. B. and C are the source operands. followed by some examples that attempt to show several possible instantiations of the instruction. b. For some instructions the destination operand is optional. B. 8. q = !(a < b). A. the D operand is the destination operand. The setp instruction writes two destination registers. while A. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. C. A.lt p|q. In addition to the name and the format of the instruction. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. Instruction Set 8. January 24. opcode A.1. setp. opcode D.

Instructions without a guard predicate are executed unconditionally. To implement the above example as a true conditional branch. j.s32 p.lt.reg . … // compare i to n // if false. 1. As an example. add.s32 p.3. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. i. consider the high-level code if (i < n) j = j + 1. optionally negated.pred as the type specifier. 1. i.lt. Predicates are most commonly set as the result of a comparison performed by the setp instruction.PTX ISA Version 2. add 1 to j To get a conditional branch or conditional function call. add. n. This can be written in PTX as @p setp. Predicated Execution In PTX. j. So.pred p. q. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.s32 j. where p is a predicate variable. the following PTX instruction sequence might be used: @!p L1: setp. 2010 .0 8.s32 j. predicate registers are virtual and have . branch over 56 January 24. n. predicate registers can be declared as . bra L1. // p = (i < n) // if i < n. use a predicate to control the execution of the branch or call instructions.

ne. lo (lower).1. ne. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.2. The following table shows the operators for signed integer. gt (greater-than). gt. The bit-size comparisons are eq and ne. Unsigned Integer. If either operand is NaN. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.Chapter 8. the result is false. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). hi (higher).3. unsigned integer. Table 16. Table 15. le (less-than-or-equal). and bitsize types.3. lt. and ge (greater-than-or-equal). The unsigned comparisons are eq.1. Instruction Set 8. ordering comparisons are not defined for bit-size types. ge. ne (not-equal). ls (lower-or-same). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. Comparisons 8. 2010 57 . lt (less-than). and hs (higher-or-same). le.1.3.1.

num returns true if both operands are numeric values (not NaN).3. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. unordered versions are included: equ. // convert predicate to 32-bit value 58 January 24. If both operands are numeric values (not NaN). Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. However. 2010 . There is no direct conversion between predicates and integer values. and no direct way to load or store predicate register values. two operators num (numeric) and nan (isNaN) are provided. ltu. setp can be used to generate a predicate from an integer.u32 %r1.1. then the result of these comparisons is true. or. and nan returns true if either operand is NaN. for example: selp. then these comparisons have the same result as their ordered counterparts. and mov. Table 17. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.PTX ISA Version 2. gtu.0 To aid comparison operations in the presence of NaN values. neu.0. xor. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. Table 18. leu. If either operand is NaN.%p.2. not. geu.

For example. i.uX ok ok ok inv . cvt. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.u16 d. Table 19. and these are placed in the same order as the operands. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.f32. and this information must be specified as a suffix to the opcode. b. b. It requires separate type-size modifiers for the result and source.sX . a.u16 a. Signed and unsigned integer types agree provided they have the same size.sX ok ok ok inv . Floating-point types agree only if they have the same size.f32 d. For example. For example: . different sizes).e.uX . a.bX . 2010 59 . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.reg . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.bX . Example: . they must match exactly. most notably the data conversion instruction cvt.reg . . float. a.fX ok inv inv ok Instruction Type . Instruction Set 8. the add instruction requires type and size information to properly perform the addition operation (signed.fX ok ok ok ok January 24.u16 d.4.. unsigned.u16 d. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.reg . Type Checking Rules Operand Type . and integer operands are silently cast to the instruction type if needed. • The following table summarizes these type checking rules. add.Chapter 8.

no conversion needed.bX instruction types. the data will be truncated. the cvt instruction does not support . the size must match exactly. Floating-point source registers can only be used with bit-size or floating-point instruction types. When used with a floating-point instruction type. 2010 . When used with a narrower bit-size type. st.4. so those rows are invalid for cvt. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types.PTX ISA Version 2. Bit-size source registers may be used with any appropriately-sized instruction type.1. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Source register size must be of equal or greater size than the instruction-type size. for example. so that narrow values may be loaded. parse error. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. inv = invalid. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. 2. and converted using regular-width registers. Notes 3. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. “-“ = allowed. stored. For example. 60 January 24. Note that some combinations may still be invalid for a particular instruction. 1. floating-point instruction types still require that the operand type-size matches exactly. 4. stored. The following table summarizes the relaxed type-checking rules for source operands.0 8. unless the operand is of bit-size type. The data is truncated to the instruction-type size and interpreted according to the instruction type. Operand Size Exceeding Instruction-Type Size For convenience. Table 20. or converted to other types and sizes. ld. When a source operand has a size that exceeds the instruction-type size.

and is zero-extended to the destination register width otherwise.Chapter 8. When used with a narrower bit-size instruction type. Notes 3.or sign-extended to the size of the destination register. the data will be zero-extended. zext = zero-extend. 1. Bit-size destination registers may be used with any appropriately-sized instruction type. 4. “-“ = Allowed but no conversion needed. the destination data is zero. January 24. 2010 61 . otherwise. inv = Invalid. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Destination register size must be of equal or greater size than the instruction-type size. 2. parse error. The data is sign-extended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer. Instruction Set When a destination operand has a size that exceeds the instruction-type size. When used with a floatingpoint instruction type. Table 21. The following table summarizes the relaxed type-checking rules for destination operands. the data is zeroextended. the data is sign-extended. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. The data is signextended to the destination register width for signed integer instruction types. the size must match exactly. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend.

A compiler or programmer may chose to enforce portable. 62 January 24. For divergent control flow. 8. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path.5. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. If threads execute down different control flow paths.1. If all of the threads act in unison and follow a single control flow path. 2010 . The semantics are described using C. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. 8.uni suffix.PTX ISA Version 2. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. this is not desirable. and 16-bit computations are “promoted” to 32-bit computations. conditional function call. the threads are called uniform. At the PTX language level. until C is not expressive enough. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. by a right-shift instruction. Therefore.0 8. for many performance-critical applications. the semantics of 16-bit instructions in PTX is machine-specific.6. the optimizing code generator automatically determines points of re-convergence. 16-bit registers in PTX are mapped to 32-bit physical registers. and for many applications the difference in execution is preferable to limiting performance. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. a compiler or code author targeting PTX can ignore the issue of divergent threads. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. These extra precision bits can become visible at the application level. or conditional return. using the . so it is important to have divergent threads re-converge as soon as possible. at least in appearance. Both situations occur often in programs. Divergence of Threads in Control Constructs Threads in a CTA execute together.6. until they come to a conditional control construct such as a conditional branch. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. When executing on a 32-bit data path. for example. However. the threads are called divergent.

cc.Chapter 8. In the following descriptions. 8. 2010 63 . subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7.7. addc sub. Instructions All PTX instructions may be predicated. The Integer arithmetic instructions are: add sub add.1. Instruction Set 8.cc. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. the optional guard predicate is omitted from the syntax.

.u64. d = a + b. .s64 }. b. . .s32 type. b. Description Semantics Notes Performs addition and writes the resulting value into a destination register.1.0. // .MAXINT (no overflow) for the size of the operation. Introduced in PTX ISA version 1. add. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. a.s32 . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.s16.sat limits result to MININT.s32 c. @p add.MAXINT (no overflow) for the size of the operation.z. . a.sat. Applies only to .u16.s32 type. Saturation modifier: .s32 d. // .u32. . Introduced in PTX ISA version 1. b.sat}. Applies only to .y.type = { . a.u32. a. . Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples 64 January 24. b.type add{. ..s64 }. Saturation modifier: .0 Table 22.sat}.a.sat applies only to .s32.u32 x. add. d.type sub{. 2010 . sub. PTX ISA Notes Target ISA Notes Examples Table 23. . ..u64.u16.type = { . add Syntax Integer Arithmetic Instructions: add Add two values.s32 c.s32 d. sub. d = a – b.0.s32.s32 .sat limits result to MININT. Supported on all target architectures. d.PTX ISA Version 2.sat applies only to .b.c.s16.

Introduced in PTX ISA version 1. . // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc Syntax Integer Arithmetic Instructions: add.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.z1. addc.b32 addc.z3.b32 x1.z4. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. @p @p @p @p add.cc}.CF. x3.z2.y2. Supported on all target architectures. addc{. carry-out written to CC.z1.cc.u32. No saturation.cc Add two values with carry-out.y2. Behavior is the same for unsigned and signed integers.z4. or testing the condition code.type = {. a.cc.cc. x2.CF No integer rounding modifiers. d = a + b + CC.s32 }.cc. sub. clearing. a. add.u32.type = { .s32 }. . carry-out written to CC.y4.z2. x2.CF No integer rounding modifiers.z3.Chapter 8. if . b. b. x4.type d.b32 addc.cc specified.y3.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.cc. and there is no support for setting.type d. No other instructions access the condition code. x4. Behavior is the same for unsigned and signed integers. d = a + b.b32 addc. No saturation. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. Introduced in PTX ISA version 1.y1. @p @p @p @p add.cc. x3.2. 2010 65 .2. Supported on all target architectures.cc.y3.b32 x1.CF) holding carry-in/carry-out or borrowin/borrow-out. Instruction Set Instructions add. .cc. These instructions support extended-precision integer addition and subtraction.b32 addc.cc.y4. Table 24.b32 addc. .b32 addc.y1. add. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.

y2. x3.cc}. a.z4. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. @p @p @p @p sub.type d. Introduced in PTX ISA version 1.z1. Behavior is the same for unsigned and signed integers.cc.z2.CF).3. No saturation.cc.type = { . .y3.cc. No saturation. x4.u32.y2. . x2.b32 subc. b. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.3. 2010 . Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.z1.y3.(b + CC.s32 }. borrow-out written to CC.cc. sub. @p @p @p @p sub.y4. if .b32 subc.cc.PTX ISA Version 2.z4.type d.cc. x3.u32.type = {. Supported on all target architectures.y1.CF No integer rounding modifiers.cc Subract one value from another.b32 x1.cc. Introduced in PTX ISA version 1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. . x2.0 Table 26.cc. x4. Supported on all target architectures.cc.z3.z3. a.y4. d = a – b.s32 }. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.b32 subc.z2. sub.b32 x1.cc Syntax Integer Arithmetic Instructions: sub.b32 subc. borrow-out written to CC. d = a .b32 subc.y1.cc specified. b.b32 subc. with borrow-out.CF No integer rounding modifiers. Behavior is the same for unsigned and signed integers. . withborrow-in and optional borrow-out. subc{.

wide. a.lo.lo.wide suffix is supported only for 16. . mul.wide is specified.fys.fxs. . Description Semantics Compute the product of two values.Chapter 8. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.s32.fxs. Supported on all target architectures. .lo is specified.fys.and 32-bit integer types.0>.s64 }. then d is twice as wide as a and b to receive the full result of the multiplication.u16.s16.type = { .wide // for .x. mul.wide.y. . t = a * b. 2010 67 .hi variant // for .wide}. If . d = t<n-1.hi. d = t<2n-1. and either the upper or lower half of the result is written to the destination register..s16 fa.u32. n = bitwidth of type. Instruction Set Table 28.0. The .type d. // for . mul. b. If . // 16*16 bits yields 32 bits // 16*16 bits.s32 z. then d is the same size as a and b.. mul{. d = t.n>. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u64.lo variant Notes The type of the operation represents the types of the a and b operands.s16 fa. save only the low 16 bits // 32*32 bits. creates 64 bit result January 24.. ..hi or .

.u64.lo variant Notes The type of the operation represents the types of the a and b operands.u32. t + c.c. Supported on all target architectures. then d and c are the same size as a and b.lo is specified.0 Table 29.s32 d.. 68 January 24.type mad. c.hi.hi variant // for .and 32-bit integer types.wide // for .lo.q.0. a. t<n-1.wide}. t<2n-1. Applies only to . .s16..s32 r. and either the upper or lower half of the result is written to the destination register. t n d d d = = = = = a * b.MAXINT (no overflow) for the size of the operation.u16. @p mad.sat limits result to MININT.type = { .r. Description Semantics Multiplies two values and adds a third. d.n> + c. If . bitwidth of type. and then writes the resulting value into a destination register.p.sat..b.wide is specified. .wide suffix is supported only for 16. mad. mad{. b. // for . c. . a.s32.hi mode.PTX ISA Version 2. The . Saturation modifier: . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.a. . . 2010 .s32 type in .hi or .lo.0> + c. then d and c are twice as wide as a and b to receive the result of the multiplication.s32 d.lo. If .s64 }. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.hi. b.. .

January 24.hi variant // for . i.s32 }.e.0>... 48bits. b. mul24. . mul24{.a. t = a * b. // for .Chapter 8.type d. d = t<47. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo}.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. d = t<31.u32. // low 32-bits of 24x24-bit signed multiply. 2010 69 .hi may be less efficient on machines without hardware support for 24-bit multiply.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.b. mul24.hi. and return either the high or low 32-bits of the 48-bit result.lo.16>.0. Supported on all target architectures. mul24. mul24. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.s32 d. Instruction Set Table 30.type = { .. All operands are of the same type and size. a.

d = t<31. b.PTX ISA Version 2.hi. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. i. and add a third.lo}..s32 }. // low 32-bits of 24x24-bit signed multiply.c. 48bits. a.lo.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. mad24.hi mode. mad24.MAXINT (no overflow). c. c.0> + c. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Return either the high or low 32-bits of the 48-bit result.type = { . t = a * b. b.sat limits result of 32-bit signed addition to MININT..u32. Applies only to . Description Compute the product of two 24-bit integer values held in 32-bit source registers. All operands are of the same type and size.b. .sat. Saturation modifier: .s32 d.hi. // for .s32 type in . 2010 . mad24. mad24{.0.type mad24. 70 January 24. d.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value..s32 d..e.hi variant // for . mad24. d = t<47. Supported on all target architectures.hi may be less efficient on machines without hardware support for 24-bit multiply. 32-bit value to either the high or low 32-bits of the 48-bit result. a.a.0 Table 31.16> + c.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b32. cnt.type = { . a = a >> 1. if (.0 Table 39.b64 type.type == .b64 }. popc. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. inclusively. mask = 0x8000000000000000.b64 d.b32 clz. a.u32 PTX ISA Notes Target ISA Notes Examples Table 40.u32 Semantics 74 January 24. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.b32 type. popc requires sm_20 or later. // cnt is . .type d. } while (d < max && (a&mask == 0) ) { d++. the number of leading zeros is between 0 and 64. while (a != 0) { if (a&0x1) d++. clz. a = a << 1.b64 d. X. popc.b64 }. inclusively. For . X.type d. clz.0. . cnt. d = 0.b32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. .PTX ISA Version 2. 2010 . } else { max = 64. popc Syntax Integer Arithmetic Instructions: popc Population count. a. . a. a.b32 popc. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.type = { . } Introduced in PTX ISA version 2. mask = 0x80000000.b32) { max = 32. For . clz requires sm_20 or later. the number of leading zeros is between 0 and 32. d = 0. // cnt is .

u64.shiftamt.shiftamt is specified. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. X.type d. break. d = -1.type==. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type = { .s32) ? 31 : 63.type bfind. a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Description Find the bit position of the most significant non-sign bit in a and place the result in d. i--) { if (a & (1<<i)) { d = i.u32 d. bfind. a. bfind requires sm_20 or later. bfind returns the bit position of the most significant “1”.u32. For signed integers. i>=0. Instruction Set Table 41. If . . for (i=msb. // cnt is . a.u32 || .Chapter 8.d. and operand d has type .s32.type==.shiftamt. bfind returns 0xFFFFFFFF if no non-sign bit is found.u32 January 24. 2010 75 . . . bfind.0. d. } } if (. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. Semantics msb = (. Operand a has the instruction type.shiftamt && d != -1) { d = msb . For unsigned integers.s64 cnt. . bfind.s64 }.u32.

76 January 24.0 Table 42. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i<=msb.b64 }.type==. brev.b32 d.PTX ISA Version 2. brev requires sm_20 or later. for (i=0. i++) { d[i] = a[msb-i]. . 2010 . msb = (. a. a. Description Semantics Perform bitwise reversal of input.0.type = { . .b32.b32) ? 31 : 63.type d. brev. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.

bfe requires sm_20 or later.s32. len = c. otherwise If the bit field length is zero. Source b gives the bit field starting bit position.u64: . the destination d is filled with the replicated sign bit of the extracted field. a. The sign bit of the extracted field is defined as: . .Chapter 8. January 24.u64 || len==0) sbit = 0. pos = b.type = { . Description Extract bit field from a and place the zero or sign-extended result in d. for (i=0.msb)].u64. 2010 77 .start. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.s32) ? 31 : 63. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32.u32.type==. bfe.s64 }. .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.u32. The destination d is padded with the sign bit of the extracted field. if (.b32 d. b. If the start position is beyond the msb of the input. and operands b and c are type . d = 0.u32 || . Instruction Set Table 43. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. the result is zero.len. Semantics msb = (.0. .type==. Operands a and d have the same type as the instruction type.a. . i<=msb. else sbit = a[min(pos+len-1. .type==. c. bfe. .type==.u32. and source c gives the bit field length in bits.u32 || .type d.

c.b.type==.type f. f = b. a.0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.PTX ISA Version 2. . pos = c. and place the result in f. bfi. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. bfi requires sm_20 or later. If the bit field length is zero. . 2010 .b32. d.a. i<len && pos+i<=msb. Source c gives the starting bit position for the insertion. and operands c and d are type . b. b.b32 d.type = { . and source d gives the bit field length in bits.u32. Operands a.start. the result is b.b32) ? 31 : 63. the result is b.b64 }. 78 January 24.0 Table 44. for (i=0. If the start position is beyond the msb of the input.len. bfi. i++) { f[pos+i] = a[i]. len = d. Semantics msb = (. and f have the same type as the instruction type. Description Align and insert a bit field from a into b.

Thus.b2 source select c[11:8] d. msb=0 means copy the literal value. . a. b2. b5.f4e.b1 source select c[7:4] d. 2010 79 . . b1. c.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.mode = { . The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. the permute control consists of four 4-bit selection values. the four 4-bit values fully specify an arbitrary byte permute.b3 source select c[15:12] d. msb=1 means replicate the sign.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. For each byte in the target register. Description Pick four arbitrary bytes from two 32-bit registers. a} = {{b7. b4}. b0}}. and reassemble them into a 32-bit destination register. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).Chapter 8. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. In the generic form (no mode specified). The msb defines if the byte value should be copied. The bytes in the two source registers are numbered from 0 to 7: {b.mode} d. Instruction Set Table 45. . . . b6. prmt.b4e.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. Note that the sign extension is only performed as part of generic form. b.rc8. a 4-bit selection value is defined. as a 16b permute code.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.ecl.ecr.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. {b3. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. .b32{. default mode index d.rc16 }.

tmp[31:24] = ReadByte( mode. ctl[2]. ctl[3] = (c >> 12) & 0xf. r1. ctl[2] = (c >> 8) & 0xf. r2. ctl[1]. tmp[23:16] = ReadByte( mode. r3.0 Semantics tmp64 = (b<<32) | a.b32. ctl[0]. ctl[1] = (c >> 4) & 0xf.f4e r1. r4.b32 prmt. r4. ctl[3].0. prmt. tmp64 ). prmt requires sm_20 or later. 2010 . tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. } tmp[07:00] = ReadByte( mode. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. tmp[15:08] = ReadByte( mode. r2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r3.PTX ISA Version 2. 80 January 24. tmp64 ). tmp64 ).

Chapter 8.2.f64 register operands and constant immediate values. Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .f32 and .7.

f32 {add.rn .0.f64 {sin.lg2.f32 .neg.rcp. {mad. No rounding modifier.sqrt}. default is . and mad support saturation of results to the range [0.32 and fma.min.rnd.fma}. default is .rn and instructions may be folded into a multiply-add.rnd.rnd. Single-precision add.sqrt}.0].rn and instructions may be folded into a multiply-add.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. .target sm_1x No rounding modifier.sub. The optional . {add.max}.max}.sqrt}.neg.rcp.rp .approx.f64 are the same.f64 rsqrt.f32 are the same. 1.mul}. NaN payloads are supported for double-precision instructions. 2010 . 82 January 24.cos.f32 {div.mul}.sat Notes If no rounding modifier is specified.fma}.f64 {abs.rcp.target sm_20 mad.rz .f32 rsqrt.f64 and fma.f32 {div. .rnd. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.ftz .sub.rnd.f32 {div.approx.f32 {abs.target sm_20 . with NaNs being flushed to positive zero. Table 46. If no rounding modifier is specified.approx.approx. Double-precision instructions support subnormal inputs and results.f64 div.full.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. Note that future implementations may support NaN payloads for single-precision instructions.ex2}.min.f64 mad.rnd.rm .f32 {mad. but single-precision instructions return an unspecified NaN.0 The following table summarizes floating-point instructions in PTX. sub. Instruction Summary of Floating-Point Instructions . mul. so PTX programs should not rely on the specific single-precision NaNs being generated.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.PTX ISA Version 2.

infinite.normal.f32. a. p. testp. not infinity). B.Chapter 8. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.f32 copysign.type = { .subnormal }.f32.type d. .notanumber. Instruction Set Table 47. Table 48. . copysign.infinite testp. A.notanumber. true if the input is a subnormal number (not NaN. y. . z. b. not infinity) As a special case. 2010 83 . copysign requires sm_20 or later. .f32 testp.normal testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. testp. // result is .number. .op. January 24.finite.finite testp.f64 isnan. a. . copysign.type = { . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.infinite. positive and negative zero are considered normal numbers. X. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and return the result as d. testp Syntax Floating-Point Instructions: testp Test floating-point property.op p. . .type .notanumber testp. Introduced in PTX ISA version 2. .pred = { . testp requires sm_20 or later.number testp.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.f64 }. C.f64 x.0. f0.0. testp.f64 }.

In particular. .rp }.f3.rz mantissa LSB rounds towards zero .f32 clamps the result to [0.rm.rp for add.ftz.rn mantissa LSB rounds to nearest even . add. b.ftz}{.rz. NaN results are flushed to +0. d = a + b.f32.rn): . 1. .rz.f64 supports subnormal numbers.sat}. .0. 84 January 24. add.f2.f64 requires sm_13 or later. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm mantissa LSB rounds towards negative infinity .f32 f1.0f.PTX ISA Version 2. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rm.f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { . .0]. a.0. d. Rounding modifiers have the following target requirements: .f32 supported on all target architectures.f64.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Rounding modifiers (default is .rz available for all targets . subnormal numbers are supported. . Saturation modifier: .f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. b.rnd}.rn. add Syntax Floating-Point Instructions: add Add two values. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. requires sm_20 Examples @p add. add. .rn. Description Semantics Notes Performs addition and writes the resulting value into a destination register. sm_1x: add. add. 2010 .rnd}{.f32 add{.0 Table 49. add.ftz. a. requires sm_13 for add.sat. add{.

PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.a. . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_20 Examples sub. d.b.rz available for all targets . a.rn.rn.f32 c. b.rp }.rn): . sub.rm.rm mantissa LSB rounds towards negative infinity . In particular. sm_1x: sub.f2.f64 requires sm_13 or later.b. sub.rp for sub.rn. 1.rz. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0f. a.0]. .Chapter 8.rnd}.f32 supported on all target architectures. sub Syntax Floating-Point Instructions: sub Subtract one value from another.f3. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. .f64. Rounding modifiers (default is . .f32 clamps the result to [0. sub{.f64 supports subnormal numbers. January 24. sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 f1. NaN results are flushed to +0.0. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. Instruction Set Table 50. requires sm_13 for sub.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. d = a .f32.f32 sub{. Rounding modifiers have the following target requirements: .rn mantissa LSB rounds to nearest even .rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero. Saturation modifier: sub. sub.ftz}{.sat.0.rnd = { . subnormal numbers are supported.f64 d. .rnd}{. b.ftz. .rm.sat}. sub. 2010 85 .

rn. Description Semantics Notes Compute the product of two values. .rm. . mul.rz mantissa LSB rounds towards zero .rnd}.f64. mul.rn.0. d = a * b. 1. . Rounding modifiers (default is .radius. .f32 clamps the result to [0. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Saturation modifier: mul.rz available for all targets . b. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.0f.rn): .sat}.f32 flushes subnormal inputs and results to sign-preserving zero.rn mantissa LSB rounds to nearest even . For floating-point multiplication.0. b. 2010 . mul.pi // a single-precision multiply 86 January 24. mul{.rnd = { .0]. a. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.PTX ISA Version 2.f32.f64 d. subnormal numbers are supported.rz. NaN results are flushed to +0. d. mul Syntax Floating-Point Instructions: mul Multiply two values. Rounding modifiers have the following target requirements: . In particular.ftz}{.rp }.rnd}{.f32 mul{.rm. requires sm_13 for mul. mul.f32 supported on all target architectures.f32 circumf.f64 supports subnormal numbers.0 Table 51. sm_1x: mul. . requires sm_20 Examples mul.rm mantissa LSB rounds towards negative infinity . a.ftz.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp for mul. all operands must be the same size.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.sat. .

b. NaN results are flushed to +0.0. b. d.rnd.f32 computes the product of a and b to infinite precision and then adds c to this product.y. .f32 flushes subnormal inputs and results to sign-preserving zero.f32 requires sm_20 or later.f32 fma.f64 introduced in PTX ISA version 1. fma.rnd. 2010 87 .0f. fma.f32 clamps the result to [0. The resulting value is then rounded to double precision using the rounding mode specified by .rn.a. fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.4. d.f64 requires sm_13 or later. again in infinite precision. 1. fma. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add.f64 w. PTX ISA Notes Target ISA Notes Examples January 24.0].sat.ftz.rnd = { .f64 is the same as mad. Rounding modifiers (no default): .rm. Saturation: fma.f64 computes the product of a and b to infinite precision and then adds c to this product. .rnd.c. The resulting value is then rounded to single precision using the rounding mode specified by .rnd{. c.f32 introduced in PTX ISA version 2.rz mantissa LSB rounds towards zero .rm mantissa LSB rounds towards negative infinity .f32 fma. subnormal numbers are supported. b.f64 d. c.ftz.x.Chapter 8.f32 is unimplemented in sm_1x. Instruction Set Table 52. @p fma.f64.ftz}{.sat}.0. fma. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.z. fma. sm_1x: fma.rn. fma.rn. a. .rz. fma. . a. fma. d = a*b + c.f64 supports subnormal numbers.rn mantissa LSB rounds to nearest even .rp }. again in infinite precision.

mad. the treatment of subnormal inputs and output follows IEEE 754 standard.f32. // . mad.rm. a.rnd = { . c.f32 computes the product of a and b at double precision. . Note that this is different from computing the product with mul.rz mantissa LSB rounds towards zero . sm_1x: mad.target sm_20: mad. mad.rnd{.rnd. NaN results are flushed to +0.ftz. but the exponent is preserved. b. Unlike mad.rnd.rz. again in infinite precision. fma.f32 is identical to the result computed using separate mul and add instructions. where the mantissa can be rounded and the exponent will be clamped. . subnormal numbers are supported.0 Table 53. mad.ftz.sat}. The exception for mad.target sm_1x d.rp }.0 devices.rn mantissa LSB rounds to nearest even .f64 computes the product of a and b to infinite precision and then adds c to this product.f64 d.rnd. Rounding modifiers (no default): .rm mantissa LSB rounds towards negative infinity . mad. mad{. // .f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to double precision using the rounding mode specified by .f64}.rn.f32 clamps the result to [0.ftz}{.f32 computes the product of a and b to infinite precision and then adds c to this product.sat}. For .0f.f32 mad.e. 1.f64. For . In this case.target sm_20 d.f32 is when c = +/-0.target sm_13 and later .f64} is the same as fma.f32 flushes subnormal inputs and results to sign-preserving zero. b. mad. again in infinite precision. The resulting value is then rounded to double precision using the rounding mode specified by . c. mad. Description Semantics Notes Multiplies two values and adds a third.PTX ISA Version 2.{f32.f64 computes the product of a and b to infinite precision and then adds c to this product.0.f64 is the same as fma. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.sat.0. c. b. mad. When JIT-compiled for SM 2.{f32. a. d = a*b + c.rnd.f32). mad. Saturation modifier: mad. and then writes the resulting value into a destination register.ftz}{.f64 supports subnormal numbers. // . and then the mantissa is truncated to 23 bits.0].. again in infinite precision.rn.f32 is implemented as a fused multiply-add (i.f32 mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . The resulting value is then rounded to single precision using the rounding mode specified by . 88 January 24. 2010 .target sm_1x: mad.

rz..f32 supported on all target architectures.rp for mad.f64 instructions having no rounding modifier will map to mad.rm.rm.4 and later.. a rounding modifier is required for mad...Chapter 8.. In PTX ISA versions 2. Rounding modifiers have the following target requirements: .rn.0 and later. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f32 for sm_20 targets.0.rz.f64. a rounding modifier is required for mad.f64. 2010 89 . In PTX ISA versions 1.f32 d. mad.f32. requires sm_20 Examples @p mad..a.f64 requires sm_13 or later. requires sm_13 .f64.c.rn.b.rp for mad.rn. Target ISA Notes mad. Legacy mad. January 24.

div.rnd = { .rz.f64 diam. a.full. Subnormal inputs and results are flushed to sign-preserving zero.rnd{.{rz.f64 d. div.f32 div.f32 div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 and div.f32 supported on all target architectures. stores result in d.f32 requires sm_20 or later. .f32 div. Examples 90 January 24.full{.0 through 1. For PTX ISA versions 1.f32 implements a fast approximation to divide.rn. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . the maximum ulp error is 2. b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. full-range approximation that scales operands to achieve better accuracy. subnormal numbers are supported. 2126].rn mantissa LSB rounds to nearest even .4 and later.rp }. The maximum ulp error is 2 across the full range of inputs.f32 and div.f64 requires sm_20 or later. div. Explicit modifiers .approx.rm.ftz}. Fast. Description Semantics Notes Divides a by b.full. a.approx. one of . .rn. a. // // // // fast.f64.f32 implements a relatively fast. or . x. and rounding introduced in PTX ISA version 1. For b in [2-126. . PTX ISA Notes div. div Syntax Floating-Point Instructions: div Divide one value by another. d.rm.rn. Fast.3.f32. . div.f64 supports subnormal numbers. 2010 . but is not fully IEEE 754 compliant and does not support rounding modifiers.ftz.rp}.f64 introduced in PTX ISA version 1. and div. d = a / b.approx{. zd.rnd. approximate single-precision divides: div.3. div. approximate division by zero creates a value of infinity (with same sign as a).rnd is required.full.ftz}. b.ftz.full.PTX ISA Version 2. .approx.full. computed as d = a * (1/b). a.f64 requires sm_13 or later.approx. For PTX ISA version 1.f64 defaults to div. div. xd. y.f32 div.approx.ftz}.circum.4.f32 div.14159. b.f32 flushes subnormal inputs and results to sign-preserving zero. div.0. d. . z.0 Table 54. Target ISA Notes div.rz mantissa LSB rounds towards zero . div.rn. sm_1x: div.f32 defaults to div.rnd. d.approx.rm mantissa LSB rounds towards negative infinity . yd.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. b.ftz. div.

sm_1x: abs.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.ftz}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.ftz.0.f64 d. neg.f0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.ftz. Negate the sign of a and store the result in d. Table 56. 2010 91 .f64 supports subnormal numbers. d = -a.f64 supports subnormal numbers.0. d. Instruction Set Table 55. a. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. abs. abs. sm_1x: neg.ftz}. neg.f32 x. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. neg.f64 d.f32 x.f0. Take the absolute value of a and store the result in d. d. abs.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. neg. subnormal numbers are supported. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. abs. Subnormal numbers: sm_20: By default. d = |a|. subnormal numbers are supported. abs{.Chapter 8. neg{. January 24.f32 abs. NaN inputs yield an unspecified NaN.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. a.f64 requires sm_13 or later. a. NaN inputs yield an unspecified NaN.f32 neg. neg.f64 requires sm_13 or later. abs.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.

b. b. subnormal numbers are supported. d. b.f64 f0. d d d d = = = = NaN. a. min{.PTX ISA Version 2.ftz.f32 min.f2. a.0.f32 supported on all target architectures. max.c.ftz. (a > b) ? a : b. min. min.f64 d. 2010 . max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. a.b. (a < b) ? a : b. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. max.f64 requires sm_13 or later. @p min.ftz}. Store the maximum of a and b in d. max{.f32 flushes subnormal inputs and results to sign-preserving zero. max.0.f64 supports subnormal numbers.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.z. Store the minimum of a and b in d.f32 min.c.ftz. Table 58. max. sm_1x: min. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. d d d d = = = = NaN. b.f64 supports subnormal numbers.0 Table 57. 92 January 24. max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. b.f32 max. subnormal numbers are supported. b. min.f64 z. sm_1x: max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f1. d. b. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. min. a.ftz.f32 max. a.x.f32 supported on all target architectures.f64 requires sm_13 or later.

rn mantissa LSB rounds to nearest even .ftz.f32 supported on all target architectures.rn. a. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . rcp. rcp. rcp.ftz}. Description Semantics Notes Compute 1/a. General rounding modifiers were added in PTX ISA version 2.rz mantissa LSB rounds towards zero .f64 introduced in PTX ISA version 1.Chapter 8.3.approx and .approx or .ftz.4 and later.f32 implements a fast approximation to reciprocal.0 +subnormal +Inf NaN Result -0.f64 d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 and explicit modifiers .f32 defaults to rcp.rn.0. xi. For PTX ISA version 1.approx{.approx. rcp.0. and rcp.f64 ri. subnormal numbers are supported. store result in d.approx.4.rnd.ftz. Input -Inf -subnormal -0. a.rnd = { .x.f32 rcp. // fast. rcp. d = 1 / a. Examples January 24.rn.rm mantissa LSB rounds towards negative infinity .approx.f32 rcp.0 +0.r.f32 flushes subnormal inputs and results to sign-preserving zero.x. rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . .rnd{.f32 rcp. rcp.ftz}. d.0 through 1.rm.rp }.{rz.f32. Target ISA Notes rcp.rz.f64. .rn.f32 and rcp.0.f32 requires sm_20 or later.f32 flushes subnormal inputs and results to sign-preserving zero.0-2.f32 rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. a.f64 supports subnormal numbers.0 over the range 1. For PTX ISA versions 1. 2010 93 .approx. d. one of . The maximum absolute error is 2-23. Instruction Set Table 59.f64 requires sm_13 or later. PTX ISA Notes rcp. xi.ftz.ftz were introduced in PTX ISA version 1.rm.f64 requires sm_20 or later.f64 defaults to rcp.rn.rp}.rn. rcp.0 -Inf -Inf +Inf +Inf +0.rnd is required. rcp. . sm_1x: rcp.rnd. rcp.

f32.rnd is required. PTX ISA Notes sqrt.approx and .rnd = { .f64 and explicit modifiers .f64 defaults to sqrt. // IEEE 754 compliant rounding .approx.ftz}.f32 sqrt.rz mantissa LSB rounds towards zero .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 requires sm_13 or later.x. sqrt.f64.rnd{.approx. a.f32 and sqrt. // IEEE 754 compliant rounding d. one of .rz.rn.0 +0. subnormal numbers are supported.rn.ftz}. General rounding modifiers were added in PTX ISA version 2.0 -0. .f32 sqrt.rnd. Target ISA Notes sqrt. approximate square root d.0 +0.f32 flushes subnormal inputs and results to sign-preserving zero.approx{. sm_1x: sqrt.3. sqrt.PTX ISA Version 2.f64 requires sm_20 or later.f32 implements a fast approximation to square root.f32 sqrt. r.4 and later. 2010 .0.0.x. a.f32 requires sm_20 or later. sqrt.approx.f32 is TBD. sqrt.4.ftz were introduced in PTX ISA version 1. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.ftz.approx. sqrt. sqrt. For PTX ISA versions 1.rm.rn. . sqrt.ftz. Input -Inf -normal -subnormal -0. For PTX ISA version 1.approx. and sqrt.f64 d.rn. sqrt.0 +subnormal +Inf NaN Result NaN NaN -0. sqrt. r.rn. Examples 94 January 24.0 through 1.f32 sqrt. a. sqrt.0 Table 60.f64 supports subnormal numbers.f64 r.approx or .ftz.ftz.f64 introduced in PTX ISA version 1.rm.rm mantissa LSB rounds towards negative infinity . store in d.f32 flushes subnormal inputs and results to sign-preserving zero. .rn mantissa LSB rounds to nearest even .{rz.rn.f32 supported on all target architectures.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 defaults to sqrt.x. Description Semantics Notes Compute sqrt(a). d = sqrt(a).rnd. // fast. The maximum absolute error for sqrt.0 +0.rp}.rp }.

3.0-4.f64 d.4 and later. Instruction Set Table 61.f32.approx implements an approximation to the reciprocal square root. Compute 1/sqrt(a). For PTX ISA versions 1. rsqrt. and rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. d. d = 1/sqrt(a).approx.4.ftz. Subnormal numbers: sm_20: By default.4 over the range 1.approx modifier is required.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. store the result in d. 2010 95 . rsqrt. The maximum absolute error for rsqrt.ftz.ftz were introduced in PTX ISA version 1. Target ISA Notes Examples rsqrt.f64 supports subnormal numbers.ftz.f32 is 2-22.f64 defaults to rsqrt. the .f64 requires sm_13 or later. For PTX ISA version 1.f32 rsqrt.0 +0. a.f64 were introduced in PTX ISA version 1. January 24.f64 is emulated in software and are relatively slow.f32 and rsqrt.0.f32 rsqrt.0.ftz}.f64 is TBD.approx.approx. rsqrt.f64 isr. Input -Inf -normal -subnormal -0.f64. ISR. rsqrt. x. Explicit modifiers .approx. rsqrt. subnormal numbers are supported. sm_1x: rsqrt. rsqrt. Note that rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 defaults to rsqrt.0 NaN The maximum absolute error for rsqrt. PTX ISA Notes rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.approx.approx and .0 through 1.approx.f32 supported on all target architectures.Chapter 8. rsqrt.approx{. X.

4.ftz introduced in PTX ISA version 1. sin.ftz.f32.0 +0. sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA versions 1.ftz.0 Table 62. sin.0 -0.0 through 1. Target ISA Notes Examples Supported on all target architectures.f32 implements a fast approximation to sine.0 +0.0 NaN NaN The maximum absolute error is 2-20. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.f32 defaults to sin. sin. Subnormal numbers: sm_20: By default. For PTX ISA version 1.f32 sa.approx.approx.PTX ISA Version 2. d = sin(a).9 in quadrant 00.approx{.0. a.0 +0. a. Explicit modifiers .approx. PTX ISA Notes sin. Find the sine of the angle a (in radians).4 and later. 96 January 24. the . 2010 . subnormal numbers are supported.0 +subnormal +Inf NaN Result NaN -0. Input -Inf -subnormal -0.ftz. sin.approx modifier is required.approx and .f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.f32 d. sin.f32 introduced in PTX ISA version 1.3.

ftz introduced in PTX ISA version 1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. PTX ISA Notes cos. Instruction Set Table 63. Explicit modifiers . d = cos(a). Target ISA Notes Examples Supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero.approx. cos.9 in quadrant 00.0 +subnormal +Inf NaN Result NaN +1. cos.approx and .3. subnormal numbers are supported.0 NaN NaN The maximum absolute error is 2-20.Chapter 8. cos. Input -Inf -subnormal -0.f32 introduced in PTX ISA version 1.ftz.0 +1.0 +1. cos. a. For PTX ISA versions 1.ftz}.0.0 through 1.0 +1. For PTX ISA version 1.f32 d. Find the cosine of the angle a (in radians).0 +0.f32 ca. January 24.approx. a.approx.4.approx modifier is required. 2010 97 . the . sm_1x: Subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default. cos.ftz.f32 implements a fast approximation to cosine.f32 defaults to cos.4 and later.approx{.f32.ftz.

f32 implements a fast approximation to log2(a).f32 defaults to lg2.ftz.approx modifier is required.4 and later. lg2. Input -Inf -subnormal -0.0.0 Table 64.0 through 1. d = log(a) / log(2). the .0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 la.approx and . Target ISA Notes Examples Supported on all target architectures. lg2. 98 January 24.4.approx.0 +0. PTX ISA Notes lg2. 2010 . The maximum absolute error is 2-22.f32. a.f32 introduced in PTX ISA version 1. a. lg2.PTX ISA Version 2. Subnormal numbers: sm_20: By default. Explicit modifiers .ftz.approx{. For PTX ISA versions 1.approx. subnormal numbers are supported.approx. lg2.ftz introduced in PTX ISA version 1.3.ftz. For PTX ISA version 1.f32 Determine the log2 of a. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz}. lg2.f32 flushes subnormal inputs and results to sign-preserving zero.6 for mantissa.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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. . The comparison operator is a suffix on the instruction. unordered versions are included: equ.s32 setp.f32. {!}c. loweror-same. A related value computed using the complement of the compare result is written to the second destination operand. c). Applies to all numeric types. 102 January 24.i. and nan returns true if either operand is NaN. then these comparisons have the same result as their ordered counterparts. The untyped. ls. leu. .b16. b. ltu. ne. q = BoolOp(!t. ne. higher. lo. respectively.BoolOp{.u16. a.b32.u32.dtype.f64 }. lt. b. p = BoolOp(t. . leu.CmpOp{. subnormal numbers are supported. . a. hi. setp.and.B) is one of: and. p[|q]. gt. setp with . ltu.f64 supports subnormal numbers. setp. ne. If either operand is NaN.type = { . 2010 .n.ftz. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. neu. le.ftz applies only to . Integer Notes Floating Point Notes The ordered comparisons are eq. xor.r. hs equ. le. Semantics t = (a CmpOp b) ? 1 : 0. p. c). .f64 source type requires sm_13 or later. . To aid comparison operations in the presence of NaN values.f32 flushes subnormal inputs to sign-preserving zero. The destinations p and q must be .f32 comparisons.ftz}.0.u64. If either operand is NaN. @q setp.u32 p|q. bit-size comparisons are eq and ne. gt. setp. This result is written to the first destination operand.0 Table 67. and can be one of: eq. and hs for lower. lt.type setp.type . and higher-or-same may be used instead of lt. and (optionally) combine this result with a predicate value by applying a Boolean operator. gt. ge. . num returns true if both operands are numeric values (not NaN).PTX ISA Version 2. sm_1x: setp. geu. gtu. le. then the result of these comparisons is true.s32. . Subnormal numbers: sm_20: By default.eq.f32 flushes subnormal inputs to sign-preserving zero.lt.dtype. p[|q]. If both operands are numeric values (not NaN). The signed and unsigned comparison operators are eq. For unsigned values.pred variables. ge.b. Modifier . neu. nan The Boolean operator BoolOp(A. or.s16. the result is false. . num. lt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. le.ftz}. the comparison operators lo.s64. gt. ge.a.dtype. gtu. hi. ge. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. geu. ls.b64.CmpOp.

b16. d.u32. The selected input is copied to the output without modification.u32. . Introduced in PTX ISA version 1. b. b. .s64.ftz. For .s32 x.dtype.b16. and operand a is selected. .s16.f64 }. slct. 2010 103 . a. @q selp. If operand c is NaN. .f32 flushes subnormal values of operand c to sign-preserving zero. Subnormal numbers: sm_20: By default. d = (c == 1) ? a : b.s16. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. .u64.dtype. . .u32. . .b32. .f32 r0. fval. y. selp.t.s32. f0. based on the value of the predicate source operand.xp. and b must be of the same type. the comparison is unordered and operand b is selected. Operands d. C. c.s32 slct{. operand c must match the second instruction type. Operands d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Operand c is a predicate.0.b64.u16. . negative zero equals zero.u16. otherwise b is stored in d. and b are treated as a bitsize type of the same width as the first instruction type. Modifier . . . slct.b32. Instruction Set Table 68.r. selp.ftz. If c ≥ 0. Description Conditional selection. a is stored in d.s32 selp.f32 A.dtype. . . slct.f32 comparisons. b otherwise. subnormal numbers are supported. a. a. d = (c >= 0) ? a : b.f32 flushes subnormal values of operand c to sign-preserving zero. .f32. slct Syntax Comparison and Selection Instructions: slct Select one source operand. B. slct.Chapter 8. z.p. .type d. If c is True.dtype = { . a.0. and operand a is selected. a is stored in d. val. selp Syntax Comparison and Selection Instructions: selp Select between source operands.f32.f32 comparisons.u64. .s64. . sm_1x: slct.type = { .u64. a. c.dtype.x.g. Semantics Floating Point Notes January 24.f64 requires sm_13 or later. based on the sign of the third operand. slct.f64 }.f32 d. Table 69. c. b.s32.ftz applies only to . . .f64 requires sm_13 or later.b64. .ftz}.

The logical shift instructions are: and or xor not cnot shl shr 104 January 24. Instructions and. This permits bit-wise operations on floating point values without having to define a union to access the bits. or. xor. and not also operate on predicates.4. provided the operands are of the same size. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.PTX ISA Version 2.7. performing bit-wise operations on operands of any type. 2010 .0 8.

but not necessarily the type.b16. . and.r. a. and. Allowed types include predicate registers.type = { . d = a | b. The size of the operands must match. Introduced in PTX ISA version 1. Instruction Set Table 70. Supported on all target architectures.0x00010001 or. . Introduced in PTX ISA version 1.b32 mask mask. Allowed types include predicate registers. a.b32 and.pred. and Syntax Logic and Shift Instructions: and Bitwise AND.b32 x. . Supported on all target architectures.0.q. but not necessarily the type.type = { .Chapter 8.b16. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.q. . sign.pred p.pred.type d.b32. b.r. b.0. . or.type d. or Syntax Logic and Shift Instructions: or Bitwise OR. . The size of the operands must match. d = a & b.0x80000000. . Table 71.fpvalue. January 24.b32.b64 }. or.b64 }. 2010 105 .

. but not necessarily the type.q.x. d = ~a.b16. .type = { . Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. d = a ^ b.0x0001.b32 mask.b64 }.b32 xor. a.type d.type = { . not. Allowed types include predicates.b16.PTX ISA Version 2.q. .0. one’s complement.b16 d. .type d. cnot. not Syntax Logic and Shift Instructions: not Bitwise negation.0.b32 d. but not necessarily the type. Supported on all target architectures. cnot.a. . Supported on all target architectures.b32. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. not. a. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. d.b16. a.0 Table 72. . The size of the operands must match. Table 74. xor. 2010 . Supported on all target architectures. .type = { . xor.pred.b64 }.pred p.pred. . Table 73. not.b32. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b64 }.type d. .b32. Introduced in PTX ISA version 1. 106 January 24. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. The size of the operands must match. b. . Introduced in PTX ISA version 1. The size of the operands must match.mask.0.r. d = (a==0) ? 1 : 0. .

The b operand must be a 32-bit value. shr Syntax Logic and Shift Instructions: shr Shift bits right. The sizes of the destination and first source operand must match.b16. .type d.b32 q. . Supported on all target architectures. shl. 2010 107 . a. The b operand must be a 32-bit value. .a.s32 shr. PTX ISA Notes Target ISA Notes Examples Table 76. The sizes of the destination and first source operand must match. but not necessarily the type. shr. .u64. PTX ISA Notes Target ISA Notes Examples January 24. . k.b64 }. shr. .s16.j. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.type = { . . Bit-size types are included for symmetry with SHL. . sign or zero fill on left. Signed shifts fill with the sign bit. regardless of the instruction type. Supported on all target architectures. d = a >> b.u16.s64 }.type = { . i.u32. .s32. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. b. b. d = a << b.b16 c. shl. a.a. .Chapter 8.type d. unsigned and untyped shifts fill with 0. Shift amounts greater than the register width N are clamped to N.0.0.b64. .i.1. Shift amounts greater than the register width N are clamped to N. shl Syntax Logic and Shift Instructions: shl Shift bits left.u16 shr. Introduced in PTX ISA version 1.b32.i. zero-fill on right. regardless of the instruction type. Introduced in PTX ISA version 1.2. but not necessarily the type. Instruction Set Table 75. .2.b16.b32.

The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.7. Data Movement and Conversion Instructions These instructions copy data from place to place. 2010 . st.0 8. suld.5. and st operate on both scalar and vector types. ld. and from state space to state space. Instructions ld. The cvta instruction converts addresses between generic and global. and sust support optional cache operations. possibly converting it from one format to another.PTX ISA Version 2. ldu. local. mov. prefetchu isspacep cvta cvt 108 January 24. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. or shared state spaces.

ca. When ld. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. likely to be accessed once.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. and cache only in the L2 cache.cs) on global addresses.7. .ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. Global data is coherent at the L2 level. rather than the data stored by the first thread. but multiple L1 caches are not coherent for global data.ca loads cached in L1. For sm_20 and later. and a second thread loads that address via a second L1 cache with ld. The default load instruction cache operation is ld.cv to a frame buffer DRAM address is the same as ld.cg Cache at global level (cache in L2 and below. bypassing the L1 cache.cs Cache streaming.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. not L1). A ld. The ld.lu operation.cv Cache as volatile (consider cached system memory lines stale. the cache operators have the following definitions and behavior. Use ld. Instruction Set 8. The ld.Chapter 8. . The cache operators require a target architecture of sm_20 or later.lu Last use. As a result of this request. invalidates (discards) the local L1 line following the load.lu load last use operation. when applied to a local address. . 2010 109 . to allow the thread program to poll a SysMem location written by the CPU. The ld. Operator . Table 77.1. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. January 24.ca. The ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.0 introduces optional cache operators on load and store instructions. The compiler / programmer may use ld.lu instruction performs a load cached streaming operation (ld.cg to cache loads only globally.cs is applied to a Local window address. .cs. it performs the ld.5. Cache Operators PTX 2. If one thread stores to global memory via one L1 cache. any existing cache lines that match the requested address in L1 will be evicted. fetch again). the second thread may get stale L1 cache data. evict-first. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. likely to be accessed again. if the line is fully covered.

wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. 110 January 24. In sm_20. and discard any L1 lines that match.cg to cache global store data only globally. Future GPUs may have globally-coherent L1 caches.wt Cache write-through (to system memory). but st.wb for global data.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. regardless of the cache operation.cg is the same as st. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.0 Table 78. rather than get the data from L2 or memory stored by the first thread. and a second thread in a different SM later loads from that address via a different L1 cache with ld. The st. Operator . not L1).cs Cache streaming. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.ca loads. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. The st.PTX ISA Version 2.cg Cache at global level (cache in L2 and below. the second thread may get a hit on stale L1 cache data.wt store write-through operation applied to a global System Memory address writes through the L2 cache. likely to be accessed once. .wb. If one thread stores to global memory. to allow a CPU program to poll a SysMem location written by the GPU with st. in which case st.wb could write-back global store data from L1. which writes back cache lines of coherent cache levels with normal eviction policy. . bypassing the L1 cache. The default store instruction cache operation is st. and marks local L1 lines evict-first. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. .wt. Addresses not in System Memory use normal write-back. However. st.cg to local memory uses the L1 cache. 2010 . Use st.ca. bypassing its L1 cache. and cache only in the L2 cache. Global stores bypass L1.

pred.global.e.type mov. special register.s16. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. local.f64 requires sm_13 or later. myFunc.local.shared state spaces. . Take the non-generic address of a variable in global. Operand a may be a register. mov.u64. The generic address of a variable in global. ptr. A.type d. avar.b16. label. . For variables declared in . d. 2010 111 .type = { . or function name.0.Chapter 8.. variable in an addressable memory space. d = sreg.s32. d.v. local. i.u32 d. d.type mov. Write register d with the value of a.f32 mov. the parameter will be copied onto the stack and the address will be in the local state space.a. and .0. mov places the non-generic address of the variable (i. sreg. d = &label.b64.f32. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. .u32.b32. immediate. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. Note that if the address of a device function parameter is moved to a register.1. // address is non-generic. Instruction Set Table 79. Semantics d = a.f64 }. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. .u32 mov. ptr. Introduced in PTX ISA version 1.u32 mov. u. the address of the variable in its state space) into the destination register. alternately.const. d = &avar. // get address of variable // get address of label or function .type mov. . . mov. label.. mov. . or shared state space. . Description . . the generic address of a variable declared in global. within the variable’s declared state space Notes Although only predicate and bit-size types are required. k.f32 mov. local.s64. . . a.u16. A[5]. . addr. or shared state space may be taken directly using the cvta instruction.u16 mov.e.

hi}. or write vector register d with the unpacked values from scalar register a. Semantics d = a. Supported on all target architectures.x.y } = { a[0.g. . a..z << 16) | (a.b. d.w have type .b64 112 January 24.b32.u16 %x is a double.type d.u8 // unpack 32-bit elements from ..w << 24) d = a. a[16.x | (a.a}.z.y. a[16.y << 8) d = a. // // // // a.y.b64 { d. 2010 .15].15]. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.z.31].g. For bit-size types.b16 // pack four 8-bit elements into . d..47]. d.15] } // unpack 8-bit elements from .x.PTX ISA Version 2. mov.y.hi are .7].b}.x | (a.b32 { d.x. %r1.b32 // pack two 16-bit elements into .15].x. d.y } = { a[0.b16 { d..b8 r.u32 x..b have type .z. d.. mov. a[32..w } = { a[0.a have type . d.b64 }.31] } // unpack 8-bit elements from .w } = { a[0.z.{x. .b32 // pack four 16-bit elements into .b32 mov...0. a[24.x | (a.31] } // unpack 16-bit elements from . .23].x | (a..b32 %r1.w << 48) d = a. a[8.x.b16.b64 mov. Description Write scalar register d with the packed value of vector register a..b.b32 { d. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. {lo. d.z << 32) | (a. {r.63] } // unpack 16-bit elements from .63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a[32. a[48.y << 8) | (a.type = { .b32 mov.y << 16) d = a.31].b64 { d. d..x | (a. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).{a.. lo. a[16. %x.%r1.y.b64 // pack two 32-bit elements into .w}. a[8..7].0 Table 80.y << 32) // pack two 8-bit elements into . d.y << 16) | (a.y } = { a[0.

ca. i. [a]. The .local. . This may be used.vec.type = { .const space suffix may have an optional bank number to indicate constant banks other than bank zero.f32.b16.shared spaces to inhibit optimization of references to volatile memory.ss}{.cop}. Cache operations are not permitted with ld. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. *(immAddr).f64 }. . d. . perform the load using generic addressing. . .s64.cg.s16.Chapter 8.b32. . .type ld{. *a.cop = { . d. d. [a].volatile may be used with . . i. 32-bit). .cop}. . In generic addressing.ss}. ld.cs.0.e.volatile.ss}.u32. .f64 using cvt. . The value loaded is sign-extended to the destination register width for signed integers.u16. . ld{. an address maps to global memory unless it falls within the local memory window or the shared memory window. and then converted to . Instruction Set Table 81. The address size may be either 32-bit or 64-bit. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .e. .global and . the resulting behavior is undefined. .1. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . PTX ISA Notes January 24. Description Load register variable d from the location specified by the source address operand a in specified state space. . .type d.vec.ss = { . .type .u8. Within these windows. ld.0. Generic addressing may be used with ld. . Generic addressing and cache operations introduced in PTX ISA 2. 2010 113 . .shared }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. [a].f32 or .volatile introduced in PTX ISA version 1. ld introduced in PTX ISA version 1. . [a]. .volatile{. to enforce sequential consistency between threads accessing shared memory. . and is zeroextended to the destination register width for unsigned and bit-size types.v4 }.s8. an address maps to the corresponding location in local or shared memory.v2.volatile{.f16 data may be loaded using ld. If an address is not properly aligned.type ld. The address must be naturally aligned to a multiple of the access size. . .lu..global. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.const.u64. an integer or bit-size type register reg containing a byte address.cv }. Semantics d d d d = = = = a.vec = { . Addresses are zero-extended to the specified width as needed. or [immAddr] an immediate absolute byte address (unsigned. If no state space is given. for example.b8.s32.b64. or the instruction may fault.reg state space.b16.ss}{.param. *(a+immOff). 32-bit). A destination register wider than the specified type may be used.volatile. and truncated if the register width exceeds the state space address width for the target architecture.

[240].[p].%r.b32 ld. Cache operations require sm_20 or later.local. // load .f16 d. %r. x.0 Target ISA Notes ld.v4. // access incomplete array x.const.[p+4].b32 ld.b64 ld. Q.global.s32 ld.f64 requires sm_13 or later.[a].f32 ld. Generic addressing requires sm_20 or later. d.f32.shared.[buffer+64].local.[fs].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.b32 ld. // negative offset %r.PTX ISA Version 2.b16 cvt. 2010 . ld.[p+-8].global. // immediate address %r.const[4].

A destination register wider than the specified type may be used. .u64. .global. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. *(immAddr). only generic addresses that map to global memory are legal. [a].f16 data may be loaded using ldu. .[p]. Semantics d d d d = = = = a. where the address is guaranteed to be the same across all threads in the warp. perform the load using generic addressing. PTX ISA Notes Target ISA Notes Examples January 24.f32 d.s16. and truncated if the register width exceeds the state space address width for the target architecture. Addresses are zero-extended to the specified width as needed. // load from address // vec load from address . *a.type = { . .v4 }.ss}. and then converted to . . ldu{. or the instruction may fault. Within these windows. ldu.u16.f64 using cvt. .reg state space. . 2010 115 .vec.v4.b32 d.f64 }. and is zeroextended to the destination register width for unsigned and bit-size types. *(a+immOff). The address must be naturally aligned to a multiple of the access size.b32. .b64. 32-bit).global }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. d.vec = { . The addressable operand a is one of: [avar] the name of an addressable variable var.ss = { . If no state space is given.. [a]. i.ss}.u8.0. .type ldu{. . The value loaded is sign-extended to the destination register width for signed integers. i.[p+4]. // state space . .u32. The address size may be either 32-bit or 64-bit.b16.global.f32. ldu.s32. For ldu. Instruction Set Table 82. The data at the specified address must be read-only. an address maps to global memory unless it falls within the local memory window or the shared memory window. [areg] a register reg containing a byte address. . ldu. A register containing an address may be declared as a bit-size type or integer type. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . .type d. 32-bit). Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.s8. In generic addressing.b16. the resulting behavior is undefined.f64 requires sm_13 or later.global. .[a].e.s64.v2. .Chapter 8.b8.f32 Q. Introduced in PTX ISA version 2. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. an address maps to the corresponding location in local or shared memory.e. ldu. or [immAddr] an immediate absolute byte address (unsigned.f32 or . If an address is not properly aligned.

The lower n bits corresponding to the instruction-type width are stored to memory.local. .f32. or the instruction may fault. st. . [a]. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.v4 }. b. an integer or bit-size type register reg containing a byte address. .ss}{.e.type [a]. { . . Generic addressing and cache operations introduced in PTX ISA 2. i.cop . . Cache operations are not permitted with st. or [immAddr] an immediate absolute byte address (unsigned.ss . Addresses are zero-extended to the specified width as needed. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.ss}{. b. st.b8. the resulting behavior is undefined.s16. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . an address maps to the corresponding location in local or shared memory.v2.1. The address size may be either 32-bit or 64-bit. Generic addressing requires sm_20 or later. PTX ISA Notes Target ISA Notes 116 January 24. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.cs.f16 data resulting from a cvt instruction may be stored using st. .volatile{. This may be used. to enforce sequential consistency between threads accessing shared memory. . .wt }. . .PTX ISA Version 2.b32.type . If an address is not properly aligned. . an address maps to global memory unless it falls within the local memory window or the shared memory window. [a]. and truncated if the register width exceeds the state space address width for the target architecture. Generic addressing may be used with st.ss}.s32.. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .0.shared spaces to inhibit optimization of references to volatile memory.s8. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. *d = a.e.cop}.volatile may be used with .b16.type = = = = {.f64 }.u8. perform the store using generic addressing. If no state space is given. st. Cache operations require sm_20 or later.type st{.wb.reg state space. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.cop}.b64. for example. .global and . In generic addressing.f64 requires sm_13 or later. { .volatile introduced in PTX ISA version 1.0 Table 83. . . st introduced in PTX ISA version 1. 2010 .vec. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st{.u64. i.ss}.volatile. Within these windows. 32-bit). b.0.u16. *(d+immOffset) = a.vec .s64.cg.volatile{.b16. The address must be naturally aligned to a multiple of the access size. A source register wider than the specified type may be used.global.u32.volatile. Semantics d = a.type st.shared }. .vec. b. . { . [a]. 32-bit). *(immAddr) = a. .

Chapter 8.b32 st. // %r is 32-bit register // store lower 16 bits January 24. // negative offset [100].v4.local.r7. // immediate address %r. [q+-8].f32 st. Instruction Set Examples st.local.s32 cvt.a.f16. 2010 117 .local.b. [q+4]. [fs].%r. [p].a.Q.global.f32 st.%r.b32 st.s32 st.b16 [a].global.

. i. or [immAddr] an immediate absolute byte address (unsigned. prefetch{.L2 }.space = { .PTX ISA Version 2.global. [a].e.0.0 Table 84. // prefetch to data cache // prefetch to uniform cache . 32-bit).L1 [ptr]. .L1. Within these windows. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. and no operation occurs if the address maps to a local or shared memory location. an address maps to global memory unless it falls within the local memory window or the shared memory window. A prefetch into the uniform cache requires a generic address. 118 January 24. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. . 32-bit). The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. Addresses are zero-extended to the specified width as needed. A prefetch to a shared memory location performs no operation. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. In generic addressing. the prefetch uses generic addressing. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.L1 [a]. an address maps to the corresponding location in local or shared memory.L1 [addr].global. 2010 . prefetch and prefetchu require sm_20 or later. in specified state space. prefetch. prefetchu. If no state space is given.level = { . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. and truncated if the register width exceeds the state space address width for the target architecture.level prefetchu. The address size may be either 32-bit or 64-bit.local }. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. a register reg containing a byte address.space}.

size p. Use cvt. January 24. cvta.space.lptr.pred .u32. The source address operand must be a register of type . // get generic address of svar cvta.genptr. cvta. or vice-versa. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. // convert to generic address // get generic address of var // convert generic address to global. or vice-versa. For variables declared in global. Description Convert a global.space. isshrd. isspacep.global.Chapter 8.u32 to truncate or zero-extend addresses. a.local.shared }.u32. p. The destination register must be of type . isspacep requires sm_20 or later.pred. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.local. or shared state space.u32 p.u64.u32 or .to. a. or shared state space to generic. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. or shared address cvta. .size = { . .u64.size .size cvta. local.space. cvta.shared.global isspacep. or shared state space. When converting a generic address into a global. cvta requires sm_20 or later.local isspacep. 2010 119 . Instruction Set Table 85. local.space = { . .0. . Introduced in PTX ISA version 2. islcl. local. local. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 gptr.0. PTX ISA Notes Target ISA Notes Examples Table 86. .shared }. lptr.space p. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. local. var. or shared address to a generic address.global.u64 }.local. a.u32 p. // result is . p.u64 or cvt. .to. the generic address of the variable may be taken using cvta. svar. or shared address.space = { . sptr. gptr. A program may use isspacep to guard against such incorrect behavior.shared isglbl.global. // local. The source and destination addresses must be the same size. isspacep. Take the generic address of a variable declared in global.

ftz. Note: In PTX ISA versions 1.f32 float-tofloat conversions with integer rounding. . For float-to-integer conversions. .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.rz. .e. sm_1x: For cvt. .rmi. . i.dtype.u16.atype = { . subnormal inputs are flushed to signpreserving zero.rni round to nearest integer.dtype.f32. d. The optional .ftz. . and for same-size float-tofloat conversions where the value is rounded to an integer.rn.PTX ISA Version 2.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.f16.s32. .sat}. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. the .4 and earlier.MAXINT for the size of the operation.ftz}{. // integer rounding // fp rounding . .f64 }. Integer rounding is illegal in all other instances.rzi. choosing even integer if source is equidistant between two integers.sat}.rmi round to nearest integer in direction of negative infinity .u32. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. Saturation modifier: .s16. 120 January 24. Note that saturation applies to both signed and unsigned integer types. .ftz.s64. the result is clamped to the destination range by default.frnd = { . .f32 float-to-integer conversions and cvt. 2010 .f32 float-tofloat conversions with integer rounding.ftz modifier may be specified in these cases for clarity. .sat limits the result to MININT.frnd}{. subnormal inputs are flushed to signpreserving zero. d = convert(a). . cvt{.sat is redundant.rzi round to nearest integer in the direction of zero .atype d. . Integer rounding is required for float-to-integer conversions.e. .irnd = { .f32. . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.0 Table 87. a. . subnormal numbers are supported. i. .rpi }. Integer rounding modifiers: .sat For integer destination types.rp }.u64.irnd}{.atype cvt{..ftz}{. .dtype = . Description Semantics Integer Notes Convert between different types and sizes.rni. The compiler will preserve this behavior for legacy PTX code. For cvt. .u8.rm. ..f32.ftz.dtype.f32 float-to-integer conversions and cvt. . a.dtype.s8.

Applies to . Introduced in PTX ISA version 1.f32 x.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.rni.f16. Specifically.Chapter 8.sat limits the result to the range [0.s32.f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. cvt to or from .rz mantissa LSB rounds towards zero . Saturation modifier: . 2010 121 . // float-to-int saturates by default cvt.s32 f.f32. and cvt. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. Modifier .f64 types. stored in floating-point format.0. Note: In PTX ISA versions 1. // round to nearest int. and for integer-to-float conversions.i.f32 x.f64.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).f64 requires sm_13 or later.y.f64 j. if the PTX . The operands must be of the same size.ftz behavior for sm_1x targets January 24.f32.f32.0.f16. 1.sat For floating-point destination types. subnormal numbers are supported. Floating-point rounding is illegal in all other instances. The result is an integral value. .4 and earlier. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.y. cvt. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .ftz modifier may be specified in these cases for clarity. .0]. Subnormal numbers: sm_20: By default. result is fp cvt.rm mantissa LSB rounds towards negative infinity . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. cvt.r.f32. The optional .rn mantissa LSB rounds to nearest even .4 or earlier. and . The compiler will preserve this behavior for legacy PTX code. NaN results are flushed to positive zero. // note .f32.version is 1.f32. cvt. Floating-point rounding modifiers: .f32 instructions.f16.

and surfaces. r3.u32 r5. sampler. div. . Module-scope and per-entry scope definitions of texture. PTX has two modes of operation. {f1.f32 r3. texture and sampler information is accessed through a single .samplerref tsamp1 = { addr_mode_0 filter_mode }.r2. If no texturing mode is declared. sampler. r5. r5.global . and surface descriptors.f32 r1. allowing them to be defined separately and combined at the site of usage in the program.2d. r6. In the independent mode. = nearest width height tsamp1.entry compute_power ( . .texref handle.f2}].f32 {r1. A PTX module may declare only one texturing mode. // get tex1’s txq. Ability to query fields within texture. add. add. Texturing modes For working with textures and samplers. In the unified mode. The advantage of independent mode is that textures and samplers can be mixed and matched.b32 r6.b32 r5. PTX supports the following operations on texture.texref tex1 ) { txq. [tex1. The texturing mode is selected using . // get tex1’s tex. with the restriction that they correspond 1-to-1 with the 128 possible textures.f32. 122 January 24. } = clamp_to_border. Example: calculate an element’s power contribution as element’s power/total number of elements.PTX ISA Version 2.f32 r1. r1. r4. add.u32 r5.target texmode_independent . Texture and Surface Instructions This section describes PTX instructions for accessing textures.. r1. texture and sampler information each have their own handle. and surface descriptors. [tex1].. sampler. r3.r4}.width.param .0 8. r2. and surface descriptors.r3. . The advantage of unified mode is that it allows 128 samplers. the file is assumed to use unified mode. mul. and surface descriptors: • • • Static initialization of texture.height.target options ‘texmode_unified’ and ‘texmode_independent’.6. 2010 .v4. sampler. r5.7. [tex1]. samplers. r1.f32 r1. but the number of samplers is greatly restricted to 16. cvt.f32.

e.v4. sampler_x.dtype. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. tex txq suld sust sured suq Table 88. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. . Instruction Set These instructions provide access to texture and surface memory.btype d. c]. .f32 }. Operand c is a scalar or singleton tuple for 1d textures.geom.u32.f3.s32. and is a four-element vector for 3d textures.3d. PTX ISA Notes Target ISA Notes Examples January 24.v4 coordinate vectors are allowed for any geometry. Unified mode texturing introduced in PTX ISA version 1.geom. An optional texture sampler b may be specified.f2. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. The instruction always returns a four-element vector of 32-bit values. . Notes For compatibility with prior versions of PTX.r2. with the extra elements being ignored. where the fourth element is ignored. //Example of unified mode texturing tex.btype tex.Chapter 8.1d. {f1.1d. is a two-element vector for 2d textures.geom = { . or the instruction may fault.5. [tex_a.2d. the sampler behavior is a property of the named texture. 2010 123 .r3. b.v4.r4}. c].r4}.0. i. Supported on all target architectures.f32 }. {f1}]. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32 {r1. // Example of independent mode texturing tex.f32 {r1. the square brackets are not required and .r2.dtype = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding.. [a. Description Texture lookup using a texture coordinate vector. tex. If no sampler is specified.s32.3d }.f4}].v4.btype = { .v4. d. If an address is not properly aligned.s32. . . [tex_a. A texture base address is assumed to be aligned to a 16-byte address.r3.s32. . the resulting behavior is undefined.dtype. [a. // explicit sampler . .

Supported on all target architectures.normalized_coords . Query: .b32 txq.addr_mode_1 . .addr_mode_0. addr_mode_2 }.normalized_coords }. 2010 . d.addr_mode_0. clamp_ogl. Operand a is a . [tex_A].b32 %r1.tquery = { . Integer from enum { nearest. txq.tquery. addr_mode_1.squery = { . .0 Table 89. [a]. and in independent mode sampler attributes are accessed via a separate samplerref argument. Description Query an attribute of a texture or sampler.width .b32 %r1.depth. In unified mode.filter_mode.filter_mode .b32 %r1. .height .addr_mode_0 . mirror.width.b32 d. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. // unified mode // independent mode 124 January 24. [tex_A].PTX ISA Version 2. txq.filter_mode.squery. . linear } Integer from enum { wrap. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. clamp_to_edge. [a].samplerref variable.width. . // texture attributes // sampler attributes .texref or . sampler attributes are also accessed via a texref argument. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.height.depth .5.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [smpl_B]. txq. txq.

geom . the resulting behavior is undefined. and is a four-element vector for 3d surfaces.geom{. If the destination type is .p requires sm_20 or later.cg. G.b32. Cache operations require sm_20 or later. b].b.r2}.b64 }. . Description Load from surface memory using a surface coordinate vector. suld. suld. the surface sample elements are converted to .b32. .cop . additional clamp modifiers.p .trap introduced in PTX ISA version 1. [a.b.f32 }. suld.dtype . or .trap . i.s32.y.cs.s32. b].geom{.cv }. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32. suld.f4}.cop}. The .trap.f2. // for suld. and the size of the data transfer matches the size of destination operand d.v4 }.b performs an unformatted load of binary data.w}].b16. . or FLOAT data. then .p is currently unimplemented.f32. Destination vector elements corresponding to components that do not appear in the surface format are not written.b8 .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. size and type conversion is performed as needed to convert from the surface sample format to the destination type. .b .clamp field specifies how to handle out-of-bounds addresses: . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. If an address is not properly aligned.trap suld.u32.clamp = = = = = = { { { { { { d. . .zero }. . suld.f3. is a two-element vector for 2d surfaces. 2010 125 . A surface base address is assumed to be aligned to a 16-byte address.vec. .b64.dtype.b32. Instruction Set Table 90. [a.s32.5. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. {f1. suld. .1d.trap {r1. // cache operation none. // unformatted d. suld.Chapter 8.f32 is returned.f32 based on the surface format as follows: If the surface format contains UNORM. [surf_B. // for suld. .dtype . Operand b is a scalar or singleton tuple for 1d surfaces. and cache operations introduced in PTX ISA version 2. suld.clamp.v4.clamp .v2. if the surface format contains SINT data.vec .surfref variable. SNORM.ca. The lowest dimension coordinate represents a sample offset rather than a byte offset.u32. and A components of the surface format..3d }. Coordinate elements are of type .f32.3d requires sm_20 or later.p.p.cop}. Operand a is a .e. or the instruction may fault.clamp suld. .dtype.3d. then .v4. sm_1x targets support only the . // formatted . [surf_A. {x.2d.b supported on all target architectures.z.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. if the surface format contains UINT data. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.0. .1d.v2. .clamp . .b. Target ISA Notes Examples January 24. . B. suld. or .s32. then . If the destination base type is .u32 is returned. {x}]. where the fourth element is ignored.p. suld Syntax Texture and Surface Instructions: suld Load from surface memory. . . .s32 is returned. .trap clamping modifier.

5. sust. b]. or the instruction may fault. .b32.0. The source data is then converted from this type to the surface sample format.s32 is assumed. Coordinate elements are of type .clamp .u32. sust.y. . Target ISA Notes Examples 126 January 24. {r1.trap introduced in PTX ISA version 1. .1d. c.cs.s32. {f1.p requires sm_20 or later. [a. 2010 . SNORM. If an address is not properly aligned. The lowest dimension coordinate represents a sample offset rather than a byte offset. . . .cop}.zero }. . and A surface components.f3.f4}.p.clamp .p performs a formatted store of a vector of 32-bit data values to a surface sample.ctype .f2. . .cop}.s32. . . sust.geom{. the resulting behavior is undefined. .ctype. .1d.3d }. c. sust.f32.p. b].trap clamping modifier.0 Table 91.v4. then . .3d.3d requires sm_20 or later.v2.b32. size and type conversions are performed as needed between the surface sample format and the destination type. [surf_B. // for sust. B.p.w}].{u32.PTX ISA Version 2.trap sust.wt }.b32. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.u32. Cache operations require sm_20 or later. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. if the surface format contains SINT data. .surfref variable.r2}. {x. or . .ctype . then . and is a four-element vector for 3d surfaces.vec.u32 is assumed.b64.v4 }. if the surface format contains UINT data.trap .f32} are currently unimplemented. .. sm_1x targets support only the .p. {x}]. sust Syntax Texture and Surface Instructions: sust Store to surface memory.trap [surf_A. The source vector elements are interpreted left-to-right as R. sust.p Description Store to surface memory using a surface coordinate vector. Operand b is a scalar or singleton tuple for 1d surfaces.s32. sust. Source elements that do not occur in the surface sample are ignored. These elements are written to the corresponding surface sample components. .vec.2d. Operand a is a .b. sust. is a two-element vector for 2d surfaces.e. The .f32.b supported on all target architectures. then . and cache operations introduced in PTX ISA version 2.clamp sust.ctype. . or FLOAT data. G.b64 }. // unformatted // formatted . none. Surface sample components that do not occur in the source vector will be written with an unpredictable value.b. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.cg.v2.geom{.vec .z.b16. If the source type is . the access may proceed by silently masking off low-order address bits to achieve proper rounding.b.clamp.b // for sust.cop . where the fourth element is ignored. The size of the data transfer matches the size of source operand c.wb. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. If the source base type is . A surface base address is assumed to be aligned to a 16-byte address.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.clamp = = = = = = { { { { { { [a.f32 is assumed.trap. .b performs an unformatted store of binary data. sust.geom . i.clamp field specifies how to handle out-of-bounds addresses: .f32 }.s32. additional clamp modifiers. sust.b8 .

clamp .b].1d.ctype.u32. Operations add applies to .op. A surface base address is assumed to be aligned to a 16-byte address.b32 }.surfref variable. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32.u64. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. where the fourth element is ignored.2d. The .s32 types. the resulting behavior is undefined.add. The lowest dimension coordinate represents a sample offset rather than a byte offset. . .b32. [surf_B. .op. .1d. or . r1.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b performs an unformatted reduction on . is a two-element vector for 2d surfaces. . sured requires sm_20 or later.b].u32. and is a four-element vector for 3d surfaces.geom.e. min and max apply to .u64 data.b32.trap. {x. . // for sured.p.geom.add.clamp [a.u32. If an address is not properly aligned. if the surface format contains SINT data.zero }. .s32 types.u32 and .clamp field specifies how to handle out-of-bounds addresses: .s32 is assumed. sured.clamp.max.ctype.p .0. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.u32 based on the surface sample format as follows: if the surface format contains UINT data. ..b.c.trap sured.clamp [a. Coordinate elements are of type . sured. or the instruction may fault. The instruction type is restricted to . . // byte addressing sured.3d }. r1. and .clamp = { .s32.trap [surf_A. i.or }.c. the access may proceed by silently masking off low-order address bits to achieve proper rounding. then .y}]. then . Reduction to surface memory using a surface coordinate vector.s32.b32 type. . Operand a is a . Operand b is a scalar or singleton tuple for 1d surfaces.ctype = { .ctype = { . . Instruction Set Table 92. 2010 127 .p performs a reduction on sample-addressed 32-bit data.and. January 24. sured.geom = { .2d. {x}].Chapter 8.trap .b . and the data is interpreted as . sured.u32 is assumed.op = { . .b.s32. operations and and or apply to . // for sured.s32 or . .p.b32.min.u64. .b32 }. // sample addressing . . .min.

Operand a is a . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.query = { .width.0 Table 93.depth }.height .PTX ISA Version 2. 128 January 24.b32 d.b32 %r1. Description Query an attribute of a surface. . [surf_A]. .query.width .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Supported on all target architectures.5.width. Query: .surfref variable.height. 2010 . [a]. suq. suq. .

2010 129 .7.a. { instructionList } The curly braces create a group of instructions. Execute an instruction or instruction block for threads that have the guard predicate true. Instruction Set 8.0.b.f32 @q bra L23. p. setp. } PTX ISA Notes Target ISA Notes Examples Table 95. mov. ratio. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.0. Introduced in PTX ISA version 1. Supported on all target architectures.c.Chapter 8.0.7.y. Threads with a false guard predicate do nothing.s32 a. Supported on all target architectures. { add.x.eq.s32 d. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.f32 @!p div. {} Syntax Description Control Flow Instructions: { } Instruction grouping. If {!}p then instruction Introduced in PTX ISA version 1. used primarily for defining a function body. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. @{!}p instruction.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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red} require sm_20 or later.cta. Description Performs barrier synchronization and communication within a CTA. d.0. bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. bar.arrive. it is as if all the threads in the warp have executed the bar instruction. the waiting threads are restarted without delay.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Operands a. PTX ISA Notes Target ISA Notes Examples bar. operands p and c are predicates.u32 bar.popc. and d have type .sync with an immediate barrier number is supported for sm_1x targets. 2010 133 .arrive a{. b}.red also guarantee memory ordering among threads identical to membar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. Note that a non-zero thread count is required for bar. b. b.red are population-count (. a.red delays the executing threads (similar to bar. a{. Once the barrier count is reached.arrive does not cause any waiting by the executing threads. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.red should not be intermixed with bar. Each CTA instance has sixteen barriers numbered 0.or). . it simply marks a thread's arrival at the barrier. b}. the optional thread count must be a multiple of the warp size. bar. Thus.popc is the number of threads with a true predicate. the bar. Since barriers are executed on a per-warp basis. Register operands.sync and bar. thread count. threads within a CTA that wish to communicate via memory can store to memory. the final value is written to the destination register in all threads waiting at the barrier. and any-thread-true (. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. January 24. Only bar. In conditionally executed code.. Instruction Set Table 100.{arrive.and and .op.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).or }.0.red} introduced in PTX . and bar. The result of .red performs a reduction operation across threads.sync without a thread count introduced in PTX ISA 1.red performs a predicate reduction across the threads participating in the barrier. all-threads-true (. bar.version 2.sync and bar.sync or bar. b}.arrive using the same active barrier. p. while . Execution in this case is unpredictable.op = { .and). a{. bar. and then safely read values stored by other threads prior to the barrier. Operand b specifies the number of threads participating in the barrier. Thus.sync 0.Chapter 8. Register operands. bar.red. When a barrier completes.popc).red instruction. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.15. The reduction operations for bar. {!}c.red. bar.{arrive. bar. {!}c. thread count. if any thread in a warp executes a bar instruction.sync bar.u32.and. and the barrier is reinitialized so that it can be immediately reused.pred . The barrier instructions signal the arrival of the executing threads at the named barrier. all threads in the CTA participate in the barrier. bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).sync or bar.sync) until the barrier count is met. and bar. If no thread count is specified. All threads in the warp are stalled until the barrier completes. In addition to signaling its arrival at the barrier. execute a bar.

For communication between threads in different CTAs or even different SMs. membar.gl. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.g. membar. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.version 2. and memory reads by this thread can no longer be affected by other thread writes. or system memory level.0 Table 101.sys introduced in PTX .sys will typically have much longer latency than membar.cta.gl.cta.gl will typically have a longer latency than membar.sys requires sm_20 or later. membar.0.{cta.gl. . membar. 2010 . by st. membar. membar.sys }.gl} introduced in PTX . level describes the scope of other clients for which membar is an ordering event.g. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. when the previous value can no longer be read.gl} supported on all target architectures. PTX ISA Notes Target ISA Notes Examples membar.sys Waits until all prior memory requests have been performed with respect to all clients.cta. A memory read (e.level. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.level = { .{cta. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. Waits until prior memory reads have been performed with respect to other threads in the CTA. membar. this is the appropriate level of membar. that is. global.PTX ISA Version 2. 134 January 24. including thoses communicating via PCI-E such as system and peer-to-peer memory. . membar. membar.version 1.4. A memory write (e.sys. .

It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. max. . atom. dec.type d. .u32.exch to store to locations accessed by other atomic operations.space}.u32.op. by inserting barriers between normal stores and atomic operations to a common address.b].f32. . . min. performs a reduction operation with operand b and the value in location a. . overwriting the original value. b. The inc and dec operations return a result in the range [0.f32 Atomically loads the original value at location a into destination register d.b64 .b32. 32-bit operations. The address must be naturally aligned to a multiple of the access size. and stores the result of the specified operation at location a. .op. . .cas. . an address maps to the corresponding location in local or shared memory. .space = { . i.e. The address size may be either 32-bit or 64-bit. ..Chapter 8.b32 only .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.u32.s32. The integer operations are add. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. the resulting behavior is undefined. b.. . and max.b32.s32. January 24. . cas (compare-and-swap). min. and exch (exchange).type = { . . . .dec. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.inc. the access may proceed by silently masking off low-order address bits to achieve proper rounding. xor. Description // // // // // . 2010 135 .min. accesses to local memory are illegal. Addresses are zero-extended to the specified width as needed.op = { . . .exch. Instruction Set Table 102. e.and. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.shared }. perform the memory accesses using generic addressing. or the instruction may fault.f32 }. .u64 . d. or [immAddr] an immediate absolute byte address.add. and max operations are single-precision.s32. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.e. [a].u64. . .max }. The floating-point operations are add. atom{. and truncated if the register width exceeds the state space address width for the target architecture. In generic addressing. c. The bit-size operations are and. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. If an address is not properly aligned.g. . a de-referenced register areg containing a byte address. For atom. min. or by using atom.xor.b64.or. Operand a specifies a location in the specified state space. . or. Within these windows. . If no state space is given.global. [a]. The floating-point add.u32 only . an address maps to global memory unless it falls within the local memory window or the shared memory window.type atom{.add.space}. A register containing an address may be declared as a bit-size type or integer type. i. inc.

atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. : r-1. Release Notes Examples @p 136 January 24.exch} requires sm_12 or later.[x+4].global. 64-bit atom. : r.f32.add.{add. atom.{min. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. atom.my_new_val. d.[a].PTX ISA Version 2. b). atom. s) = (r >= s) ? 0 dec(r. s) = s.cas. 2010 .f32 requires sm_20 or later.global requires sm_11 or later.0 Semantics atomic { d = *a.b32 d.1.[p]. cas(r.s.add.max.cas.global.shared.f32 atom.s32 atom. 64-bit atom.t) = (r == s) ? t operation(*a. : r+1. d.0.shared requires sm_12 or later. b. s) = (r > s) ? s exch(r.0. Introduced in PTX ISA version 1. *a = (operation == cas) ? : } where inc(r.max} are unimplemented.my_val. c) operation(*a.shared operations require sm_20 or later. atom. Use of generic addressing requires sm_20 or later.

g. and stores the result of the specified operation at location a. e.f32 }. a de-referenced register areg containing a byte address.b32 only . The floating-point add. perform the memory accesses using generic addressing. Operand a specifies a location in the specified state space. For red.dec. . 2010 137 . . .space = { . and xor. 32-bit operations.u64.Chapter 8. ..e. . Instruction Set Table 103.b32. b. In generic addressing. A register containing an address may be declared as a bit-size type or integer type. The integer operations are add. or the instruction may fault.type = { . red. The address must be naturally aligned to a multiple of the access size. The floating-point operations are add.shared }. .inc. If an address is not properly aligned. .u32. .s32. s) = (r >= s) ? 0 : r+1. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. the resulting behavior is undefined. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.b].. an address maps to the corresponding location in local or shared memory. . i. b). .u32. overwriting the original value.exch to store to locations accessed by other reduction operations.op. Description // // // // .add.s32. red{.u64 .f32 Performs a reduction operation with operand b and the value in location a. . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .e.max }. or by using atom. .u32.global. or.f32.op = { . .and. Notes Operand a must reside in either the global or shared state space. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.s32. i.xor. where inc(r. accesses to local memory are illegal.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and max operations are single-precision.type [a]. January 24. . . min.b64. dec. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. Within these windows. The inc and dec operations return a result in the range [0.add. an address maps to global memory unless it falls within the local memory window or the shared memory window. by inserting barriers between normal stores and reduction operations to a common address. inc. . . min. dec(r. max. and truncated if the register width exceeds the state space address width for the target architecture. min. . The bit-size operations are and. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The address size may be either 32-bit or 64-bit.min. If no state space is given.u32 only . Addresses are zero-extended to the specified width as needed. or [immAddr] an immediate absolute byte address. Semantics *a = operation(*a. and max.space}.or. s) = (r > s) ? s : r-1.

s32 red.add.f32 red.max} are unimplemented.global. red. 64-bit red.f32.and.shared requires sm_12 or later.0. red. Release Notes Examples @p 138 January 24.global.{min. red.2.shared.global requires sm_11 or later red.1.add requires sm_12 or later.b32 [a].shared operations require sm_20 or later.add. [x+4]. [p].my_val. red.f32 requires sm_20 or later. 2010 .max.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.PTX ISA Version 2. Use of generic addressing requires sm_20 or later. 64-bit red.

all True if source predicate is True for all active threads in warp. Negate the source predicate to compute .uni True if source predicate has the same value in all active threads in warp. . vote.b32 d. .pred d. Negating the source predicate also computes . Note that vote applies to threads in a single warp. Description Performs a reduction of the source predicate across threads in a warp.ballot.mode.all. The destination predicate value is the same across all threads in the warp. 2010 139 .Chapter 8.pred vote.p. vote. r1.mode = { . vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. // ‘ballot’ form. // get ‘ballot’ across warp January 24.ballot. Instruction Set Table 104. vote. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.pred vote. Negate the source predicate to compute .q. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. . The reduction modes are: . vote. In the ‘ballot’ form.uni. vote requires sm_12 or later. not across an entire CTA.ballot.uni }.q.none. where the bit position corresponds to the thread’s lane id.uni. returns bitmask .b32 requires sm_20 or later.all. p.any True if source predicate is True for some active thread in warp.any.2. {!}a.ballot. .not_all.b32 p. {!}a.

. 4. taking into account the subword destination size in the case of optional data merging. b{.9. . or word values from its source operands. b{.b3.max }. vop. 140 January 24. . b{.b0.s33 values.dtype. with optional data merge vop. c. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).dtype. a{. . . c.min.atype. .asel}. optionally clamp the result to the range of the destination type. 2. .dsel.atype.atype = . a{. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. with optional secondary operation vop. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.btype{.b2.PTX ISA Version 2.add. perform a scalar arithmetic operation to produce a signed 34-bit result. Using the atype/btype and asel/bsel specifiers.dtype. 2010 .bsel = { .dsel = . . extract and sign. The primary operation is then performed to produce an .btype{.u32.s32) is specified in the instruction type. the input values are extracted and signor zero.secop = { . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.s34 intermediate result.btype{. // 32-bit scalar operation. .b1.bsel}.extended internally to . to produce signed 33-bit input values.asel}. The type of each operand (.sat}. .s32 }. atype.sat} d.bsel}.h0. The sign of the intermediate result depends on dtype.7. a{. The source and destination operands are all 32-bit registers. .dtype = .btype = { .asel = .bsel}. all combinations of dtype.or zero-extend byte.h1 }.0 8.secop d. The general format of video instructions is as follows: // 32-bit scalar operation.u32 or . 3.atype. half-word.asel}. and btype are valid. Video Instructions All video instructions operate on 32-bit register operands.sat} d.

Bool sat. S32_MIN ). c). S16_MIN ). The lower 32-bits are then written to the destination operand. U8_MAX.b2. 2010 141 .b0: return ((tmp & 0xff) case .max return MAX(tmp. .Chapter 8.s33 tmp.add: return tmp + c.s33 optSaturate( .b3: if ( sign ) return CLAMP( else return CLAMP( case . c). The sign of the c operand is based on dtype.b3: return ((tmp & 0xff) << 24) default: return tmp. S32_MAX. . Instruction Set . .min: return MIN(tmp. tmp. U32_MAX. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. c).s33 tmp. S8_MIN ).h0. U16_MAX.s34 tmp. . switch ( dsel ) { case .h1: return ((tmp & 0xffff) << 16) case . tmp. January 24. Modifier dsel ) { if ( !sat ) return tmp.b2: return ((tmp & 0xff) << 16) case . c). c). tmp.s33 c ) switch ( dsel ) { case . c). U16_MIN ). } } . Bool sign. .b1. tmp. default: return tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).b0.h0: return ((tmp & 0xffff) case . as shown in the following pseudocode. S8_MAX.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.s33 c) { switch ( secop ) { . . c).s33 optMerge( Modifier dsel. . . S16_MAX. . .s33 optSecOp(Modifier secop. . U32_MIN ). tmp. U8_MIN ).b1: return ((tmp & 0xff) << 8) case .

0 Table 105. .asel = . 2010 .0. and optional secondary arithmetic operation or subword data merge.h1. r1.asel}.h0.add r1. . r2.sat. d = optSecondaryOp( op2.b3.s32.add. vmax Syntax Integer byte/half-word/word addition / subtraction.b2. r3. b{. vsub.bsel = { . vmax }. btype. // extract byte/half-word/word and sign.s32.bsel}. tmp = MIN( ta. b{. vsub.dsel. vop. tmp = MAX( ta.b0. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.sat vsub. c. c ).s32. .u32.atype = .sat vmin. { .atype. vadd. .dsel . r2.op2 Description = = = = { vadd.or zero-extend based on source operand type ta = partSelectSignExtend( a.b2. // 32-bit scalar operation.h0.btype{.min.s32.atype. vabsdiff. asel ). tmp = ta – tb.PTX ISA Version 2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // optional merge with c operand 142 January 24. dsel ). r3. // 32-bit scalar operation. c. r1. // optional secondary operation d = optMerge( dsel.h1. r2. a{. Semantics // saturate.sat}. taking into account destination type and merge operations tmp = optSaturate( tmp. b{. a{. bsel ).s32. . vmax require sm_20 or later. r2.btype{. . tb ). c.dtype. vadd.bsel}. isSigned(dtype). vabsdiff. vsub.sat} d. with optional secondary operation vop. r3. vmin.dtype . r1. . atype. . tmp = | ta – tb |. vabsdiff. tb = partSelectSignExtend( b.sat} d.s32.atype. Integer byte/half-word/word absolute value of difference.h1 }.btype = { . Video Instructions: vadd. vsub vabsdiff vmin.h0.dtype.b0.op2 d.s32.bsel}. sat. .s32. with optional data merge vop. vmin.sat vabsdiff. tmp.s32 }.asel}. Perform scalar arithmetic operation with optional saturate.btype{.max }. r3.u32. tb ). c.dtype. c ). . vmax vadd.b1.vop .s32. Integer byte/half-word/word minimum / maximum.b0. vmin.asel}. a{.u32.s32. . tmp.

b1. d = optSecondaryOp( op2. and optional secondary arithmetic operation or subword data merge. r1. . vshl. } // saturate. vshr }.dsel .clamp && tb > 32 ) tb = 32. b{. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp. // 32-bit scalar operation. a{. . c ). atype. .asel = . .atype. isSigned(dtype).dtype.mode . 2010 143 .bsel}.h1.u32. sat. asel ).asel}.atype. { . vshr vshl.u32{.u32.wrap ) tb = tb & 0x1f.wrap r1. r2.dtype . a{. . . with optional secondary operation vop. bsel ). Semantics // extract byte/half-word/word and sign. r3. . .b3.u32 vshr.dtype.sat}{. Signed shift fills with the sign bit. r2. c ).b2. .asel}.op2 Description = = = = = { vshl. tb = partSelectSignExtend( b.h1 }.sat}{.dsel. vshr: Shift a right by unsigned amount in b with optional saturate. and optional secondary arithmetic operation or subword data merge. vshl.bsel = { .op2 d. Instruction Set Table 106.u32.b0.u32. vshr require sm_20 or later.asel}.sat}{. case vshr: tmp = ta >> tb. // optional secondary operation d = optMerge( dsel. b{.or zero-extend based on source operand type ta = partSelectSignExtend( a.atype = { . Video Instructions: vshl. unsigned shift fills with zero. // default is .mode}.max }.u32{. { .bsel}. vshl: Shift a left by unsigned amount in b with optional saturate.h0.add. b{.mode} d.0. a{. c.mode} d. if ( mode == . . Left shift fills with zero.clamp.clamp .bsel}.u32.u32.min. .vop . dsel ).dtype. switch ( vop ) { case vshl: tmp = ta << tb. vshr Syntax Integer byte/half-word/word left / right shift. vop. January 24.s32 }. if ( mode == .atype. // 32-bit scalar operation.u32{. .wrap }. with optional data merge vop. r3. c. taking into account destination type and merge operations tmp = optSaturate( tmp.s32.Chapter 8. tmp.

The source operands support optional negation with some restrictions. The “plus one” mode (. PTX allows negation of either (a*b) or c. .PTX ISA Version 2.po) computes (a*b) + c + 1.scale} d. b{.dtype. vmad.h1 }.atype. // 32-bit scalar operation vmad.shr7. final signed -(S32 * S32) + S32 // intermediate signed. this result is sign-extended if the final result is signed.bsel = { . {-}b{. and zero-extended otherwise.asel = . Input c has the same sign as the intermediate result. . “plus one” mode.dtype = .b2.btype{. 144 January 24. otherwise.S32 // intermediate signed.po mode. final signed -(U32 * S32) + S32 // intermediate signed.atype.sat}{. final signed The intermediate result is optionally scaled via right-shift. Source operands may not be negated in . final signed (S32 * U32) + S32 // intermediate signed. .u32.S32 // intermediate signed. c.. final signed (S32 * S32) . internally this is represented as negation of the product (a*b). the intermediate result is signed. final signed (S32 * S32) + S32 // intermediate signed. The final result is unsigned if the intermediate result is unsigned and c is not negated. Description Calculate (a*b) + c. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. .bsel}. .0 Table 107.U32 // intermediate unsigned.b3. and scaling. a{. final unsigned -(U32 * U32) + S32 // intermediate signed.h0.asel}. final signed (U32 * S32) + S32 // intermediate signed.scale} d. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.atype = . final signed (S32 * U32) . {-}c. .sat}{.scale = { . which is used in computing averages.asel}. . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. Although PTX syntax allows separate negation of the a and b operands.dtype. and the operand negates.S32 // intermediate signed.btype = { .bsel}. final signed (U32 * S32) . 2010 . (a*b) is negated if and only if exactly one of a or b is negated.po{. with optional operand negates.shr15 }. . . . Depending on the sign of the a and b operands. {-}a{. final signed (U32 * U32) . That is. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed -(S32 * U32) + S32 // intermediate signed.b0.btype.s32 }.b1.

} if ( . switch( scale ) { case . lsb = 1.shr15: result = (tmp >> 15) & 0xffffffffffffffff. S32_MIN). vmad requires sm_20 or later.sat ) { if (signedFinal) result = CLAMP(result. } else if ( c.negate ) { tmp = ~tmp.or zero-extend based on source operand type ta = partSelectSignExtend( a. r2.s32. 2010 145 . Instruction Set Semantics // extract byte/half-word/word and sign. atype. r1. if ( .po ) { lsb = 1. tmp[127:0] = ta * tb. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).h0.negate ^ b.negate ^ b. U32_MAX.sat vmad. lsb = 1. S32_MAX. r2.negate) || c.0.h0.u32. } else if ( a.negate ) { c = ~c. January 24.u32. vmad. asel ). r3.shr7: result = (tmp >> 7) & 0xffffffffffffffff. case . lsb = 0.u32. else result = CLAMP(result.u32.shr15 r0.negate. r1. btype. tb = partSelectSignExtend( b. bsel ). -r3. r0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Chapter 8.s32. tmp = tmp + c128 + lsb. U32_MIN). signedFinal = isSigned(atype) || isSigned(btype) || (a.

dsel . with optional secondary arithmetic operation or subword data merge.b2. 146 January 24.btype.asel}.b1.h1 }. // optional secondary operation d = optMerge( dsel. a{.gt. atype. a{. r1.btype.bsel = { . . vset. with optional data merge vset. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. c. .btype = { .lt.cmp. // 32-bit scalar operation. Semantics // extract byte/half-word/word and sign. vset.bsel}. c ).atype.u32.s32.b3. . c ).atype. a{.cmp d. .b0.op2 d. The intermediate result of the comparison is always unsigned.0.u32.s32 }.u32.ne. cmp ) ? 1 : 0. .ne r1. .cmp . { . r2.h0. asel ). c.atype . 2010 . tb. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.min.add.eq.cmp d. .op2 Description = = = = . . Compare input values using specified comparison. bsel ). b{. . r2. .ge }.0 Table 108. tmp.asel}. .lt vset.max }. tmp = compare( ta.btype. . d = optSecondaryOp( op2.PTX ISA Version 2.bsel}. btype.asel = .dsel.asel}.h1.le. b{.bsel}.or zero-extend based on source operand type ta = partSelectSignExtend( a. . r3. r3. { . b{. // 32-bit scalar operation. . tb = partSelectSignExtend( b. and therefore the c operand and final result are also unsigned.u32.atype. vset requires sm_20 or later. with optional secondary operation vset. tmp. .

Supported on all target architectures. 2010 147 . trap. Introduced in PTX ISA version 1. pmevent 7. brkpt. there are sixteen performance monitor events. The relationship between events and counters is programmed via API calls from the host. Supported on all target architectures.0. pmevent a. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. @p pmevent 1.10. trap. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. brkpt Suspends execution Introduced in PTX ISA version 1.0. brkpt requires sm_11 or later. Introduced in PTX ISA version 1. with index specified by immediate operand a.Chapter 8. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Table 110. numbered 0 through 15. January 24.4. trap Abort execution and generate an interrupt to the host CPU. brkpt. Instruction Set 8.7. Triggers one of a fixed number of performance monitor events. Table 111. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.

2010 .0 148 January 24.PTX ISA Version 2.

read-only variables. 2010 149 . %lanemask_le. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_ge.Chapter 9. Special Registers PTX includes a number of predefined. %pm3 January 24. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %clock64 %pm0. %lanemask_gt %clock. %lanemask_lt. ….

%tid.%ntid.z < %ntid. // compute unified thread id for 2D CTA mov.z == 0 in 1D CTAs.z to %r2 Table 113.x.u32 %h1. %tid. %tid.%tid.z.y == %tid.%h1.u32 %h2.u32 %ntid.v4 .x 0 <= %tid.v4.y. mov. mov.u16 %r2.u32 %ntid. 2D. // zero-extend tid. PTX ISA Notes Introduced in PTX ISA version 1. %ntid. the %tid value in unused dimensions is 0.PTX ISA Version 2.y * %ntid. Every thread in the CTA has a unique %tid.v4.z PTX ISA Notes Introduced in PTX ISA version 1.sreg . cvt. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.z.u32 type in PTX 2.sreg . %tid.x.u16 %rh.u32 %r1.u16 %rh.x * %ntid.z == 1 in 2D CTAs.%h2. read-only. mov. // move tid.x code Target ISA Notes Examples 150 January 24.0. The number of threads in each dimension are specified by the predefined special register %ntid.sreg .x. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. The fourth element is unused and always returns zero.v4 .%ntid. .u32 %tid. It is guaranteed that: 0 <= %tid. %ntid. .0.0.z == 1 in 1D CTAs. The %tid special register contains a 1D.%tid. Supported on all target architectures. %ntid.y. mad. .%r0.x. the fourth element is unused and always returns zero. %tid. // legacy PTX 1.y 0 <= %tid. 2010 .y == %ntid. per-thread special register initialized with the thread identifier within the CTA. %tid component values range from 0 through %ntid–1 in each CTA dimension.u32 %r0. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. mov. read-only special register initialized with the number of thread ids in each CTA dimension.0. or 3D vector to match the CTA shape.x to %rh Target ISA Notes Examples // legacy PTX 1. The total number of threads in a CTA is (%ntid. Redefined as .z.x.x.%tid. // CTA shape vector // CTA dimensions A predefined. . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u32 type in PTX 2.x < %ntid.z).u32 %tid.sreg .x.y < %ntid.%tid.0 Table 112. %ntid. Redefined as . Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.x code accessing 16-bit component of %tid mov. Supported on all target architectures.u32. CTA dimensions are non-zero. // thread id vector // thread id components A predefined.u32 %r0.y.z == 0 in 2D CTAs.

sreg . Note that %warpid is volatile and returns the location of a thread at the moment when read. mov. Introduced in PTX ISA version 1. %laneid.u32 %r.u32 %warpid. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. read-only special register that returns the thread’s warp identifier.u32 %laneid.Chapter 9.3.sreg . due to rescheduling of threads following preemption. For this reason. Table 115. %warpid. The lane identifier ranges from zero to WARP_SZ-1.0. Supported on all target architectures. read-only special register that returns the maximum number of warp identifiers. A predefined.u32 %nwarpid. Introduced in PTX ISA version 2. %nwarpid requires sm_20 or later. but its value may change during execution. . mov.sreg . Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. read-only special register that returns the thread’s lane within the warp.u32 %r. PTX ISA Notes Target ISA Notes Examples Table 116. . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %nwarpid.3. A predefined. Introduced in PTX ISA version 1. Special Registers Table 114. January 24. . A predefined. mov. Supported on all target architectures.g. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. The warp identifier will be the same for all threads within a single warp.u32 %r. e. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. 2010 151 .

536 PTX ISA Notes Introduced in PTX ISA version 1. // CTA id vector // CTA id components A predefined. The fourth element is unused and always returns zero.u32 type in PTX 2. Supported on all target architectures. depending on the shape and rank of the CTA grid.u32 %nctaid.PTX ISA Version 2. The %ctaid special register contains a 1D.%nctaid.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %ctaid.z} < 65.z. // legacy PTX 1.u16 %r0.v4.%ctaid.y 0 <= %ctaid.u32 mov. . read-only special register initialized with the number of CTAs in each grid dimension.sreg . The %nctaid special register contains a 3D grid shape vector. 2010 .%nctaid.y.y.x.x. or 3D vector. %rh.sreg .0. %rh.0.z < %nctaid. It is guaranteed that: 1 <= %nctaid.%nctaid. Redefined as . Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. The fourth element is unused and always returns zero.v4 .x. Each vector element value is >= 0 and < 65535.v4. .x < %nctaid. Supported on all target architectures.0.%nctaid.u16 %r0.v4 .sreg .y. mov.x 0 <= %ctaid.0 Table 117.y < %nctaid.0.x. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. It is guaranteed that: 0 <= %ctaid.u32 type in PTX 2. %ctaid.u32 %nctaid .x. // legacy PTX 1. . Redefined as .sreg . %ctaid. // Grid shape vector // Grid dimensions A predefined.%ctaid. read-only special register initialized with the CTA identifier within the CTA grid. mov. 2D.x code Target ISA Notes Examples 152 January 24. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u32 %ctaid.x code Target ISA Notes Examples Table 118.u32 mov.{x.z. with each element having a value of at least 1.y.

PTX ISA Notes Target ISA Notes Examples Table 121.sreg . The SM identifier numbering is not guaranteed to be contiguous.sreg . PTX ISA Notes Target ISA Notes Examples January 24. %gridid. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Introduced in PTX ISA version 1. .u32 %r. Supported on all target architectures. mov. %nsmid requires sm_20 or later.0.u32 %gridid. Introduced in PTX ISA version 2. A predefined. . due to rescheduling of threads following preemption. read-only special register initialized with the per-grid temporal grid identifier. repeated launches of programs may occur. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.3. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. .u32 %r. read-only special register that returns the maximum number of SM identifiers. // initialized at grid launch A predefined. During execution.u32 %nsmid.sreg . A predefined. Note that %smid is volatile and returns the location of a thread at the moment when read. so %nsmid may be larger than the physical number of SMs in the device. %smid.0.u32 %r. e. mov. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.g. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. but its value may change during execution. mov. Introduced in PTX ISA version 1. where each launch starts a grid-of-CTAs.u32 %smid.Chapter 9. This variable provides the temporal grid launch number for this context. Supported on all target architectures. The SM identifier numbering is not guaranteed to be contiguous. 2010 153 . %nsmid. The SM identifier ranges from 0 to %nsmid-1. Special Registers Table 119.

%lanemask_eq requires sm_20 or later.u32 %r. A predefined.u32 %lanemask_lt. mov. . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_le.u32 %r.sreg .0.0 Table 122. 2010 . %lanemask_lt requires sm_20 or later.0.u32 %r. Introduced in PTX ISA version 2. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. . mov. %lanemask_eq. Table 123. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. Table 124. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. .u32 %lanemask_eq. A predefined.PTX ISA Version 2. Introduced in PTX ISA version 2.sreg . 154 January 24.0. A predefined. %lanemask_le requires sm_20 or later.sreg .u32 %lanemask_le. %lanemask_lt. mov. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.

A predefined. A predefined. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_gt. mov.u32 %lanemask_gt. mov. Table 126.u32 %lanemask_ge. 2010 155 . read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg .0.sreg . Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. %lanemask_ge requires sm_20 or later. %lanemask_gt requires sm_20 or later.u32 %r. .0.Chapter 9.u32 %r. %lanemask_ge. Special Registers Table 125. January 24. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. .

u32 r1. 156 January 24. %pm2. . read-only 64-bit unsigned cycle counter.0.0 Table 127. Table 128. Table 129. Introduced in PTX ISA version 1. Supported on all target architectures.u32 %clock.%clock. %clock64 requires sm_20 or later.u32 r1. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u64 %clock64. mov. The lower 32-bits of %clock64 are identical to %clock.sreg . Introduced in PTX ISA version 1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. mov. Supported on all target architectures. Introduced in PTX ISA version 2. . and %pm3 are unsigned 32-bit read-only performance monitor counters.sreg . …. mov. %pm2.3.u64 r1. Special Registers: %pm0. 2010 . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.0.u32 %pm0. %pm2.%clock64. read-only 32-bit unsigned cycle counter.%pm0. %pm1.PTX ISA Version 2. Their behavior is currently undefined. %pm1. %pm1. %pm3. Special registers %pm0. . %pm3 %pm0.sreg .

. .0 . Each ptx file must begin with a . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Increments to the major number indicate incompatible changes to PTX.minor // major.1. Directives 10.target Table 130. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. and the target architecture for which the code was generated. .4 January 24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version directive. Duplicate .version Syntax Description Semantics PTX version number.version directive.version major.0.version 2.version .version directives are allowed provided they match the original . minor are integers Specifies the PTX language version number.version 1.Chapter 10. PTX File Directives: . Supported on all target architectures.version . 2010 157 .

Each PTX file must begin with a . PTX code generated for a given target can be run on later generation devices. . vote instructions. texture and sampler information is referenced with independent . sm_11. Requires map_f64_to_f32 if any .f64 to . sm_13. sm_10. Description Specifies the set of features in the target architecture for which the current ptx code was generated. including expanded rounding modifiers.texref descriptor.f32.texmode_independent texture and sampler information is bound together and accessed via a single .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. texmode_unified.red}. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.texmode_unified) . 64-bit {atom. Requires map_f64_to_f32 if any . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.5.samplerref descriptors. immediately followed by a . Adds {atom. Disallows use of map_f64_to_f32.target Syntax Architecture and Platform target.f64 storage remains as 64-bits. The texturing mode is specified for an entire module and cannot be changed within the module.target . PTX features are checked against the specified target architecture. generations of SM architectures follow an “onion layer” model. A . but subsequent . Texturing mode introduced in PTX ISA version 1. texmode_independent. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. The following table summarizes the features in PTX that vary according to target architecture. sm_12.PTX ISA Version 2. brkpt instructions. Supported on all target architectures.shared. Target sm_20 Description Baseline feature set for sm_20 architecture.version directive. where each generation adds new features and retains all features of previous generations. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.target directive specifies a single target architecture. Texturing mode: (default is .texmode_unified .global. Introduced in PTX ISA version 1. Adds double-precision support. PTX File Directives: .red}.f64 instructions used. 2010 . and an error is generated if an unsupported feature is used. Note that .0.f64 instructions used. Therefore.red}. with only half being used by instructions converted from .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. In general.f64 instructions used. A program with multiple . Requires map_f64_to_f32 if any . map_f64_to_f32 }.target directive containing a target architecture and optional platform options.0 Table 131.texref and . 158 January 24.global. Adds {atom.target directives can be used to change the set of target features allowed during parsing.

Chapter 10. 2010 159 . Directives Examples . texmode_independent January 24.target sm_10 // baseline target architecture .target sm_20.target sm_13 // supports double-precision .

and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.0 through 1. store.param { .samplerref. %ntid.param instructions. parameter variables are declared in the kernel body.b32 %r1. e. parameters. .PTX ISA Version 2.b32 %r<99>.entry cta_fft .4. the kernel dimensions and properties are established and made available via special registers. ld.entry kernel-name ( param-list ) kernel-body . Semantics Specify the entry point for a kernel program.g. ld.entry . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.b32 z ) Target ISA Notes Examples [x]. [z]. parameter variables are declared in the kernel parameter list.surfref variables may be passed as parameters.0 through 1. Kernel and Function Directives: .b32 %r2. . opaque .param. . 160 January 24. etc. Parameters are passed via .b32 y. with optional parameters. Parameters may be referenced by name within the kernel body and loaded into registers using ld.param . . In addition to normal parameters. and body for the kernel function.b32 x.entry Syntax Description Kernel entry point and body. ld.0 10.b32 %r3. … } .entry kernel-name kernel-body Defines a kernel entry point name. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.4 and later. PTX ISA Notes For PTX ISA version 1. .param instructions. At kernel launch. Supported on all target architectures.param space memory and are listed within an optional parenthesized parameter list. These parameters can only be referenced by name within texture and surface load. .texref. [y].func Table 132.2.entry .3. For PTX ISA versions 1. and .entry filter ( .param . 2010 . %nctaid. The shape and size of the CTA executing the kernel are available in special registers.5 and later.reg .param. and query instructions and cannot be accessed via ld.param.

Parameters in register state space may be referenced directly within instructions in the function body.b32 rval. Directives Table 133. Release Notes For PTX ISA version 1. Variadic functions are currently unimplemented. … use N. Supported on all target architectures. } … call (fooval).0 with target sm_20 supports at most one return value. . there is no stack. parameters must be in the register state space. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.reg . A .reg . PTX ISA 2.func definition with no body provides a function prototype.func (. The implementation of parameter passing is left to the optimizing translator. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.b32 rval) foo (.reg .0. (val0. which may use a combination of registers and stack locations to pass parameters.Chapter 10. implements an ABI with stack. dbl.func .reg . Parameters must be base types in either the register or parameter state space. PTX 2.func Syntax Function definition. val1).func fname function-body . . and recursion is illegal.x code. Parameters in . The parameter lists define locally-scoped variables in the function body.b32 localVar.func (ret-param) fname (param-list) function-body Defines a function.param state space.param instructions in the body. other code. including input and return parameters and optional function body. … Description // return value in fooval January 24.param space are accessed using ld.f64 dbl) { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Parameter passing is call-by-value.0 with target sm_20 allows parameters in the . foo. if any.func fname (param-list) function-body . mov.result. Variadic functions are represented using ellipsis following the last fixed argument.param and st.b32 N.2 for a description of variadic functions. 2010 161 . and supports recursion. Kernel and Function Directives: . ret. .

g.pragma directive is supported for passing information to the PTX backend.minnctapersm .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. The interpretation of .PTX ISA Version 2.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. or as statements within a kernel or device function body. The directive passes a list of strings to the backend. and the strings have no semantics within the PTX virtual machine model. 2010 .maxnreg. and the . A general .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. . the . which pass information to the backend optimizing compiler. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.maxntid directive specifies the maximum number of threads in a thread block (CTA).0 10.minnctapersm directives may be applied per-entry and must appear between an .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).pragma directives may appear at module (file) scope. PTX supports the following directives. for example. at entry-scope.maxnctapersm (deprecated) . the . to throttle the resource requirements (e. These can be used.maxnreg .maxntid and . Currently. The . 162 January 24. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.pragma The . and . Note that . .maxntid. registers) to increase total thread count and provide a greater opportunity to hide memory latency. The directives take precedence over any module-level constraints passed to the optimizing backend.maxntid .3.entry directive and its body.

ny .maxntid 256 .entry foo . 2010 163 . The maximum number of threads is the product of the maximum extent in each dimension.3. Introduced in PTX ISA version 1.Chapter 10. 2D.16.maxntid nx .maxntid nx. Directives Table 134. Performance-Tuning Directives: .entry foo . This maximum is specified by giving the maximum extent of each dimention of the 1D. . Supported on all target architectures. Introduced in PTX ISA version 1. Exceeding any of these limits results in a runtime error or kernel launch failure. . Performance-Tuning Directives: .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxntid 16. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid nx.maxntid . ny. The actual number of registers used may be less. .maxntid and . Supported on all target architectures. or 3D CTA. or the maximum number of registers may be further constrained by . the backend may be able to compile to fewer registers.entry bar .maxnreg n Declare the maximum number of registers per thread in a CTA. nz Declare the maximum number of threads in the thread block (CTA).3.maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxctapersm. The compiler guarantees that this limit will not be exceeded. for example. .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.

minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Supported on all target architectures. Optimizations based on . Introduced in PTX ISA version 1.PTX ISA Version 2.minnctapersm generally need . Optimizations based on .3. Deprecated in PTX ISA version 2.maxnctapersm (deprecated) .0.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0 as a replacement for . additional CTAs may be mapped to a single multiprocessor. 2010 . Performance-Tuning Directives: . Supported on all target architectures. . The optimizing backend compiler uses .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. .0.maxntid to be specified as well.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.0 Table 136. if the number of registers used by the backend is sufficiently lower than this bound. .maxnctapersm generally need .maxntid and .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm in PTX ISA version 2.minnctapersm 4 { … } 164 January 24.maxntid to be specified as well.maxntid 256 .entry foo . .maxnctapersm. Introduced in PTX ISA version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.entry foo . . For this reason. Performance-Tuning Directives: . However.minnctapersm .maxnctapersm has been renamed to .maxntid 256 .

.pragma “nounroll”. or statement-level directives to the PTX backend compiler.entry foo .pragma “nounroll”. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . The interpretation of .pragma Syntax Description Pass directives to PTX backend compiler. Pass module-scoped. Performance-Tuning Directives: .Chapter 10. The . at entry-scope.pragma list-of-strings . or at statementlevel. . Directives Table 138. See Appendix A for descriptions of the pragma strings defined in ptxas. Introduced in PTX ISA version 2. 2010 165 .0. entry-scoped.pragma directive may occur at module-scope.pragma .pragma directive strings is implementation-specific and has no impact on PTX semantics. { … } January 24. Supported on all target architectures.

Table 139.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0. The @@DWARF syntax is deprecated as of PTX version 2.0 and replaces the @@DWARF syntax.section . @@DWARF dwarf-string dwarf-string may have one of the .debug_info .PTX ISA Version 2. @progbits . 0x6150736f.4byte label .byte byte-list // comma-separated hexadecimal byte values . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .4byte .section directive.section . 0x00000364. 0x736d6172 .. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. Introduced in PTX ISA version 1.0 10. 0x5f736f63 .debug_pubnames. 0x63613031. 0x00. 0x00 . 2010 .file .4.byte 0x2b. 0x61395a5f.264-1] .section directive is new in PTX ISA verison 2. 0x02. “”.4byte 0x6e69616d.loc The .quad int64-list // comma-separated hexadecimal integers in range [0.0 but is supported for legacy PTX version 1.4byte 0x000006b5. 0x00. 0x00. 0x00 166 January 24.byte 0x00.x code. Supported on all target architectures.. replaced by . Deprecated as of PTX 2.0. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x00.232-1] .2. 0x00.

. 0x00.232-1] . Debugging Directives: . 0x5f736f63 0x6150736f.b32 .debug_info . .b32 0x000006b5. Supported on all target architectures..Chapter 10. .debug_pubnames { .264-1] .255] .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . 0x00000364. 0x736d6172 0x00 Table 141. .section Syntax PTX section definition.file filename Table 142. 2010 167 . Directives Table 140. .section . Source file location. 0x00 0x61395a5f.b32 int32-list // comma-separated list of integers in range [0.b8 byte-list // comma-separated list of integers in range [0. 0x00.0.section .loc .section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00. 0x00.0. Supported on all target architectures.file .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.. Debugging Directives: . replaces @@DWARF syntax. 0x63613031. Source file information.b8 0x00.b32 0x6e69616d.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00.b32 label .0.b8 0x2b. } 0x02.b64 int64-list // comma-separated list of integers in range [0.loc line_number January 24. Supported on all target architectures. . Debugging Directives: .. 0x00.

extern . . Linking Directives: .extern . // foo is defined in another module Table 144. .extern identifier Declares identifier to be defined externally. . Linking Directives: .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.0.visible . 2010 . Introduced in PTX ISA version 1. // foo will be externally visible 168 January 24.6. Introduced in PTX ISA version 1. . Supported on all target architectures.global .b32 foo.global .extern .visible Table 143.PTX ISA Version 2.b32 foo.visible identifier Declares identifier to be externally visible.0 10.0.visible . Supported on all target architectures. Linking Directives .

3 driver r190 CUDA 3.4 PTX ISA 1.0.1 CUDA 2.0 January 24. The release history is as follows.Chapter 11.1 CUDA 2.3 PTX ISA 1.0 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2. and the remaining sections provide a record of changes in previous releases.0 driver r195 PTX ISA Version PTX ISA 1.2 CUDA 2.2 PTX ISA 1.0 CUDA 1.1 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 2. 2010 169 .5 PTX ISA 2. CUDA Release CUDA 1.

New Features 11. Floating-Point Extensions This section describes the floating-point changes in PTX 2. • • • • • 170 January 24. and sqrt with IEEE 754 compliant rounding have been added. rcp.f32 and mad.f32. Single-precision add. fma.x code and sm_1x targets. The mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 instruction also supports .and double-precision div. When code compiled for sm_1x is executed on sm_20 devices.sat modifiers. while maximizing backward compatibility with legacy PTX 1.rp rounding modifiers for sm_20 targets.0 11. and mul now support . mad. The mad.f32 requires sm_20. Single. A single-precision fused multiply-add (fma) instruction has been added.ftz modifier may be used to enforce backward compatibility with sm_1x.0 11. The changes from PTX ISA 1.rn.ftz and . 2010 .1. The fma.1.f32 maps to fma.0 for sm_20 targets.f32 require a rounding modifier for sm_20 targets.1. The .f32 for sm_20 targets.1. Changes in Version 2.PTX ISA Version 2. These are indicated by the use of a rounding modifier and require sm_20. Both fma.rm and .1. Instructions testp and copysign have been added.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The goal is to achieve IEEE 754 compliance wherever possible.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.1. sub.

arrive instruction has been added. suld. bfind. January 24.g. e. and shared addresses to generic address and vice-versa has been added.ge.2. Instruction sust now supports formatted surface stores.pred have been added. bar now supports optional thread count and register operands. for prefetching to specified level of memory hierarchy. brev. A new directive. Video instructions (includes prmt) have been added. 2010 171 . A “bit reversal” instruction. 11.red. cvta. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.f32 have been implemented.1. has been added.u32 and bar.add. Surface instructions support additional .b32. A “count leading zeros” instruction. .ballot.clamp and . A system-level membar instruction. %lanemask_{eq. ldu.Chapter 11. Bit field extract and insert instructions. prefetchu. have been added.red}. isspacep. has been added.gt} have been added. A “population count” instruction. ldu.1. atom. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.section. and sust. New instructions A “load uniform” instruction. A “find leading non-sign bit” instruction.clamp modifiers. has been added. The . has been added. Instruction cvta for converting global. Instructions {atom.red}. Other new features Instructions ld.minnctapersm to better match its behavior and usage. clz.3. vote. %clock64.{and. Instructions {atom. Instructions bar. and red now support generic addressing.1. prefetch. Cache operations have been added to instructions ld.shared have been extended to handle 64-bit data types for sm_20 targets.1. A “vote ballot” instruction.or}. st. Release Notes 11. New special registers %nsmid. bfe and bfi. local. Instructions prefetch and prefetchu have also been added. st. has been added.maxnctapersm directive was deprecated and replaced with .red. The bar instruction has been extended as follows: • • • A bar. . membar. popc.lt.popc.zero. has been added.le.sys.

version is 1. 172 January 24. In PTX version 1. 11.5.3.target sm_1x. . Unimplemented Features Remaining The following table summarizes unimplemented instruction features. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.f32.1.{min.4 and earlier.red}. has been fixed.max} are not implemented. {atom.4 or earlier.5 and later. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. Instruction bra.1.{u32.2.PTX ISA Version 2.p. Semantic Changes and Clarifications The errata in cvt. To maintain compatibility with legacy PTX code. 2010 .ftz for PTX ISA versions 1. The underlying. if . the correct number is sixteen.f32 type is unimplemented. cvt. Formatted surface load is unimplemented.u32.0 11. See individual instruction descriptions for details. call suld.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. stack-based ABI is unimplemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.s32.f32} atom. Support for variadic functions and alloca are unimplemented.ftz (and cvt for .p sust. or . where . Formatted surface store with .s32.

. including loops preceding the . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. and statement levels.pragma Strings This section describes the .pragma “nounroll”. L1_body: … L1_continue: bra L1_head. Descriptions of . Supported only for sm_20 targets. disables unrolling of0 the loop for which the current block is the loop header.pragma “nounroll”.Appendix A. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.func bar (…) { … L1_head: . entry-function. Note that in order to have the desired effect at statement level.pragma.pragma strings defined by ptxas. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. { … } // do not unroll any loop in this function . Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. The “nounroll” pragma is allowed at module.pragma “nounroll”.entry foo (…) . L1_end: … } // do not unroll this loop January 24. … @p bra L1_end. Table 145. Ignored for sm_1x targets. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. . disables unrolling for all loops in the entry function body. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. 2010 173 . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.

2010 .PTX ISA Version 2.0 174 January 24.

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