NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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. and Vectors ................6.............. Abstracting the ABI ............................ 5...........................................................................................2....... 6....................................... 29 Parameter State Space ............................................... Arrays....................... 33 Fundamental Types ............ 47 Chapter 7..........................1..............2..4. 5......... 6................. 5.................................................................................................................. 5.........1..4....................... 38 Initializers ..........4.. 39 Parameterized Variable Names .............. 5..................................................................... Sampler..4. 5...5.................................. 38 Alignment ............ 6............................................................1.. 5.....1. 29 Global State Space ..........3.................................................4............................. 6............. 6..........5.....................................................................................................................................1..................................... Operand Costs .....2.............................................. 5.. 5......1......................... 6....3....................1....................... 5.......................................... 5......4..................... 43 Labels and Function Names as Operands ........................1......................... 43 6........1..... 42 Arrays as Operands ........................................................................ 25 Chapter 5........................ 5........ 2010 ......... Summary of Constant Expression Evaluation Rules ...........................................4......6.6................... 28 Special Register State Space ............................................................... 34 Variables ........... 43 Vectors as Operands . 37 Vectors ... 5.......................3...........PTX ISA Version 2........4.................................4..........................4.........................7.......................................................................... Types............................ Operand Type Information ....2....................................2................................................. 33 5......................................1......................1.................................8......................3............................................................................................. 6.......5.................................................. 41 Destination Operands .........................1.........2.............................................................4........................................4.................. 49 ii January 24............................................. 37 Array Declarations .....6. and Surface Types .......1............................................................................................... 5...................... 32 Texture State Space (deprecated) ..................... 44 Scalar Conversions ................. 28 Constant State Space ............................................. 6.................. 27 Register State Space ............................1..........2...................................... 41 6.................................................... Types .................. 33 Restricted Use of Sub-Word Sizes .............................0 4....................... 46 6........................................................... and Variables .................................. 32 5.... Type Conversion...................................... 29 Local State Space ..........................4............................. 44 Rounding Modifiers ............... 5.........5................. Function declarations and definitions . Texture............................................................................1............................................................................. 49 7...................... Instruction Operands.......................2.......................... 42 Addresses as Operands .. State Spaces ........ 5............... 39 5...................................... 27 5......3........................ 30 Shared State Space.............. 41 Using Addresses....4.......... State Spaces......................2....... 6................5........4................. 41 Source Operands......................5........ 37 Variable Declarations ...................................................... Chapter 6..............................1...........

..............................4...................................... 104 Data Movement and Conversion Instructions ................................ 100 Logic and Shift Instructions ............................... 63 Integer Arithmetic Instructions .............................................................7...............................................2...........7...............................2...............................1.. 53 Alloca ....... Special Registers .......................................... 56 Comparisons ........................... 169 11................................ 8............5............. 11.....6.... 11................................... 157 Specifying Kernel Entry Points and Functions ...... 55 8..................................................3.............1.............................................................. Changes from PTX 1................................................................. 8.................................................... 7....... 160 Performance-Tuning Directives ............................................ 8..... 8.. 8..... 8................7....................... Instruction Set .......... 166 Linking Directives ....... 8........................ Format and Semantics of Instruction Descriptions ........................................................... 10......... 108 Texture and Surface Instructions .....7........................ 55 Predicated Execution .. 11................................ 162 Debugging Directives ....7......0 .................7............................ 63 Floating-Point Instructions ..........2...5........ 157 10........7.............................................................. 149 Chapter 10....... 57 Manipulating Predicates ..............3.....................................6...............................4..4............. 59 Operand Size Exceeding Instruction-Type Size .................................6.............................. Type Information for Instructions and Operands ................. 8..................... 172 Unimplemented Features Remaining ................. Directives ............................................... 122 Control Flow Instructions .................................... 62 Semantics .... 10.......4..............................................................3............................. 132 Video Instructions .................7...........2.................................................................................6................................. 81 Comparison and Selection Instructions ....... 52 Variadic functions ..................................................3................................................. Divergence of Threads in Control Constructs ............................ 58 8....................3..................................7.......................... 8.................................... 8.................. 8..................................................................... Instructions .7........................ 7.1...... 10............................................9...................................... 62 Machine-Specific Semantics of 16-bit Code ............................. 140 Miscellaneous Instructions.........1..........2...................7......3............1........................................................................7................1....................................... 55 PTX Instructions ... 10........................ 170 Semantic Changes and Clarifications ......x .......................................... 8...................................................................1.................. 8................. 170 New Features ............... 129 Parallel Synchronization and Communication Instructions ..................................................................... Release Notes . 8.........................8. 2010 iii .....................................................................1................. 60 8....2......................................................................... 147 8......................3............................... Chapter 9....................1............................1............... PTX Version and Target Directives .. 172 January 24..... 8..............................1.............................. 168 Chapter 11..................... 8.........7...1...........................................1................................ Changes in Version 2............10....................... 62 8........ 54 Chapter 8.........

......... Descriptions of ...........pragma Strings......... 2010 ..........................PTX ISA Version 2....0 Appendix A....... 173 iv January 24..

...... Table 24....................................................................... and Bit-Size Types .............................. Table 20............................. 35 Convert Instruction Precision and Format ........................ Table 21........... 33 Opaque Type Fields in Unified Texture Mode ....................................................................................................... 64 Integer Arithmetic Instructions: sub .. 66 Integer Arithmetic Instructions: mul ................................................... 35 Opaque Type Fields in Independent Texture Mode ................. Table 14.............. Table 11.......................................... Table 2......................... Table 30...... 66 Integer Arithmetic Instructions: subc ................................................................... 60 Relaxed Type-checking Rules for Destination Operands........................................................................... 65 Integer Arithmetic Instructions: sub..................................... Table 16...... Table 18....................................................................................................... 28 Fundamental Type Specifiers ........ Table 32.......................................................... Table 29.... Table 31.. 59 Relaxed Type-checking Rules for Source Operands ..................................................................cc .................. Table 4....................... Table 8...................................................................................................................................... 25 State Spaces . 19 Predefined Identifiers ................................... Table 27............................................................................................... Table 26............ 20 Operator Precedence ........... 23 Constant Expression Evaluation Rules .. Table 9....... 27 Properties of State Spaces ............ PTX Directives ... 68 Integer Arithmetic Instructions: mul24 .. Table 28................................................List of Tables Table 1.......... 57 Floating-Point Comparison Operators Accepting NaN .......................................cc ... 64 Integer Arithmetic Instructions: add........ Unsigned Integer.. 67 Integer Arithmetic Instructions: mad ......... Table 23.................................................................... 70 Integer Arithmetic Instructions: sad . 46 Cost Estimates for Accessing State-Spaces ................. Table 15............................................................................. 45 Floating-Point Rounding Modifiers ................................................. Table 5......................................................................................................... 58 Type Checking Rules ........................................................... Table 3..................... 69 Integer Arithmetic Instructions: mad24 ....... 2010 v ........................ 57 Floating-Point Comparison Operators ........................................ 58 Floating-Point Comparison Operators Testing for NaN ............................................................................................ Table 25.................................................................... Table 6............. 47 Operators for Signed Integer. Table 12...................................................................... Table 10.......... 18 Reserved Instruction Keywords ....................... 65 Integer Arithmetic Instructions: addc ................................................. Table 19.......................................... 46 Integer Rounding Modifiers ......................... 61 Integer Arithmetic Instructions: add ............................................. Table 7......... Table 22............ 71 January 24....................................... Table 13.......... Table 17.......................

.............. 77 Integer Arithmetic Instructions: bfi ......................................... Table 46................................................................................................................................ Table 44.... 92 Floating-Point Instructions: rcp ........................... Table 55......... Table 43......................................... Table 40..... Table 41............................................................... 90 Floating-Point Instructions: abs .................................................................................................................. Table 48............................. 78 Integer Arithmetic Instructions: prmt ......... 85 Floating-Point Instructions: mul ............... 93 Floating-Point Instructions: sqrt ......... Table 38..................................................................... Table 35.................................. Table 56................ 84 Floating-Point Instructions: sub . 103 vi January 24............................................................. Table 61................................................... Table 36.... 101 Comparison and Selection Instructions: setp ................................ 98 Floating-Point Instructions: ex2 ..................................... 72 Integer Arithmetic Instructions: neg .................... 71 Integer Arithmetic Instructions: abs .................................................... 91 Floating-Point Instructions: min ................. Table 52... 92 Floating-Point Instructions: max ......................................................................................................... Table 50........................................................................................ Table 39................PTX ISA Version 2............................. Table 57.................... 94 Floating-Point Instructions: rsqrt ............ Table 69........................................... Table 67....... 95 Floating-Point Instructions: sin .............................................................. Table 63..................... 74 Integer Arithmetic Instructions: bfind ........................................... 88 Floating-Point Instructions: div ............. 73 Integer Arithmetic Instructions: popc ............. Table 62................. 99 Comparison and Selection Instructions: set .................................... 103 Comparison and Selection Instructions: slct ...................... Table 64.............................................................. 102 Comparison and Selection Instructions: selp .......... 79 Summary of Floating-Point Instructions ............... 91 Floating-Point Instructions: neg .......... 86 Floating-Point Instructions: fma .................................. Table 49................. 71 Integer Arithmetic Instructions: rem .................................................................. Integer Arithmetic Instructions: div ...... 87 Floating-Point Instructions: mad .......... 83 Floating-Point Instructions: copysign .............................................................................................................................................. Table 54.................................................... 2010 ............................................................................................................................. Table 53.................................................... Table 37....................................... 96 Floating-Point Instructions: cos ..........................0 Table 33....................................... 73 Integer Arithmetic Instructions: max .. Table 68..... Table 58.................................................... Table 42...... 72 Integer Arithmetic Instructions: min ...... 74 Integer Arithmetic Instructions: clz ..................... Table 45.................................................... 82 Floating-Point Instructions: testp .. Table 34............................................................................................. 97 Floating-Point Instructions: lg2 ............................................................... Table 47...... 75 Integer Arithmetic Instructions: brev .............................. 76 Integer Arithmetic Instructions: bfe ....................................................................................................................... Table 51....... Table 59......................................................................................................................... Table 60.......................................... 83 Floating-Point Instructions: add ...... Table 65................... Table 66...

................... 2010 vii ...... Table 74............ Table 91................ Table 72........................................ 115 Data Movement and Conversion Instructions: st ....... 118 Data Movement and Conversion Instructions: isspacep .................... Table 100......... 119 Data Movement and Conversion Instructions: cvt ............................................................................... 131 Control Flow Instructions: exit ................ Table 78.................. Table 94.............. 128 Control Flow Instructions: { } ........................................ Table 85....................... 120 Texture and Surface Instructions: tex ....................................... Table 99............................................................. Table 77......... Table 82............................................................................................................. 127 Texture and Surface Instructions: suq ....................................................... Table 92............................................... 130 Control Flow Instructions: call .. Table 75................................. Table 95.................................................... Table 86........ 112 Data Movement and Conversion Instructions: ld ......... Table 102.............. Table 89.. 131 Parallel Synchronization and Communication Instructions: bar . Table 105.... 119 Data Movement and Conversion Instructions: cvta .. vshr ........ 125 Texture and Surface Instructions: sust . 126 Texture and Surface Instructions: sured..... Table 101....................................... Logic and Shift Instructions: and ............................................................................................................... 106 Logic and Shift Instructions: shl ....................... 105 Logic and Shift Instructions: or .. 110 Data Movement and Conversion Instructions: mov ................................................................................... vmin...... Table 88.......................... 107 Cache Operators for Memory Load Instructions ...................... Table 79................................................................ Table 103................ 142 Video Instructions: vshl..... 139 Video Instructions: vadd............. vmax ... 106 Logic and Shift Instructions: cnot .................... Table 106........................ 133 Parallel Synchronization and Communication Instructions: membar ............... Table 83............................... Table 104.................................... 109 Cache Operators for Memory Store Instructions ............................ 111 Data Movement and Conversion Instructions: mov ............. Table 81........ 123 Texture and Surface Instructions: txq .................. 134 Parallel Synchronization and Communication Instructions: atom ........................................................................... Table 93............ Table 71. vsub..... Table 98.............................................. prefetchu ........................ 124 Texture and Surface Instructions: suld ... 113 Data Movement and Conversion Instructions: ldu . 130 Control Flow Instructions: ret .. vabsdiff.............................. 107 Logic and Shift Instructions: shr ..................................................................................................... 135 Parallel Synchronization and Communication Instructions: red ............................ Table 97......................... Table 76...............................................................Table 70........... Table 80..................................... 106 Logic and Shift Instructions: not .................... 143 January 24...... 129 Control Flow Instructions: bra ................................................................. Table 90.............................................................................. Table 73......................... Table 96... 116 Data Movement and Conversion Instructions: prefetch............... Table 84................. 137 Parallel Synchronization and Communication Instructions: vote ............................................... 129 Control Flow Instructions: @ ..................................... 105 Logic and Shift Instructions: xor .......................................... Table 87........................

.......................................... 158 Kernel and Function Directives: ......... 144 Video Instructions: vset......................................... Table 125...........minnctapersm .................... Table 115....... 154 Special Registers: %lanemask_lt .......................... Table 112.........version................................................................... 156 Special Registers: %pm0.......................... Table 118........................................................ Table 123....................................extern..................................... %pm1............................. 150 Special Registers: %laneid .......................... Table 116................................................... Table 121.................................. 164 Performance-Tuning Directives: ........... Table 137....................loc .......... Table 143...maxntid ....... 153 Special Registers: %lanemask_eq .......... 154 Special Registers: %lanemask_ge ........ Table 131......................... 155 Special Registers: %lanemask_gt .................................................. 147 Miscellaneous Instructions: brkpt .....................................................................................................maxnreg ............................. Video Instructions: vmad .... 160 Kernel and Function Directives: ....... 146 Miscellaneous Instructions: trap .................................PTX ISA Version 2.......... Table 113...... Table 127... Table 141.................................... 163 Performance-Tuning Directives: ......................... 147 Miscellaneous Instructions: pmevent.......................................... Table 132... 154 Special Registers: %lanemask_le ................... %pm3 ............. Table 122.................... 155 Special Registers: %clock ................... Table 126....... Table 128....... 166 Debugging Directives: ....... Table 136..................................... 157 PTX File Directives: ...... 150 Special Registers: %ntid ......... Table 111.......................................................................target ......... 2010 ............................ 164 Performance-Tuning Directives: ..................... 151 Special Registers: %warpid ......................................................................................... Table 114..................0 Table 107............ Table 135........................................func ... Table 129.. Table 110.................................................... Table 130....... 167 Debugging Directives: ............................entry..file .... Table 119. 147 Special Registers: %tid ............................................................................. Table 120......................... 156 PTX File Directives: ........................................pragma ......................... 153 Special Registers: %gridid ............................ Table 140................................................................. 165 Debugging Directives: @@DWARF ........................................................................................................................................... Table 142............................................................. 167 Linking Directives: ................................ Table 108.......................................................... Table 117...... Table 109........................................................................ Table 134......... Table 139.................................................. 156 Special Registers: %clock64 ............... 161 Performance-Tuning Directives: .. 152 Special Registers: %nctaid .......................................... Table 124...... 167 Debugging Directives: ............ %pm2................................................................................................ 151 Special Registers: %nwarpid ....... 163 Performance-Tuning Directives: ..section ............................................................................................................................. 151 Special Registers: %ctaid ...................... 152 Special Registers: %smid ........ 168 viii January 24........ 153 Special Registers: %nsmid ......................................................... Table 133............. Table 138.........................................................................................................................maxnctapersm (deprecated) ................

............visible............... Table 145............... Linking Directives: ........................................................ 173 January 24.............................Table 144............ 2010 ix ...... 168 Pragma Strings: “nounroll” ..........................

0 x January 24.PTX ISA Version 2. 2010 .

In fact. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. PTX programs are translated at install time to the target hardware instruction set. January 24. image and media processing applications such as post-processing of rendered images. there is a lower requirement for sophisticated flow control. stereo vision. and because it is executed on many data elements and has high arithmetic intensity. Introduction This document describes PTX. which are optimized for and translated to native target-architecture instructions. from general signal processing or physics simulation to computational finance or computational biology. video encoding and decoding. 1. Similarly. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. high-definition 3D graphics. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. multithreaded. 1. Because the same program is executed for each data element. the memory access latency can be hidden with calculations instead of big data caches. and pattern recognition can map image blocks and pixels to parallel processing threads. image scaling. Data-parallel processing maps data elements to parallel processing threads.1. many-core processor with tremendous computational horsepower and very high memory bandwidth. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time.2. 2010 1 . Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. PTX exposes the GPU as a data-parallel computing device. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. a low-level parallel thread execution virtual machine and instruction set architecture (ISA).Chapter 1. the programmable GPU has evolved into a highly parallel. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. PTX defines a virtual machine and ISA for general purpose parallel thread execution.

1. including integer. performance kernels. 2010 . and all PTX 1. A “flush-to-zero” (.0 is a superset of PTX 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. Both fma.3.rn. and architecture tests. Achieve performance in compiled applications comparable to native GPU performance.0 are improved support for IEEE 754 floating-point operations.0 is in improved support for the IEEE 754 floating-point standard. and mul now support . 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. mad. atomic. The main areas of change in PTX 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.sat modifiers. Improved Floating-Point Support A main area of change in PTX 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32.f32 requires sm_20. Provide a machine-independent ISA for C/C++ and other compilers to target. The mad. Legacy PTX 1. reduction. memory.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Instructions marked with . Facilitate hand-coding of libraries. Provide a code distribution ISA for application and middleware developers. Provide a common source-level ISA for optimizing code generators and translators. barrier.ftz) modifier may be used to enforce backward compatibility with sm_1x. The fma. fma. Most of the new features require a sm_20 target.f32 require a rounding modifier for sm_20 targets.3. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. • • • 2 January 24. and the introduction of many new instructions.1. A single-precision fused multiply-add (fma) instruction has been added. addition of generic addressing to facilitate the use of general-purpose pointers. sub. and video instructions.f32 maps to fma.f32 for sm_20 targets.f32 and mad.rp rounding modifiers for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices.x features are supported on the new sm_20 target. surface.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.ftz and . Single-precision add.f32 instruction also supports . The mad.0 PTX ISA Version 2. PTX ISA Version 2.x.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.rm and . PTX 2. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. which map PTX to specific target machines.x code will continue to run on sm_1x targets as well.PTX ISA Version 2. The changes from PTX ISA 1.

e.3.0 closer to full compliance with the IEEE 754 standard. an address that is the same across all threads in a warp. Instructions prefetch and prefetchu have been added. stack layout. and shared addresses to generic address and vice-versa has been added. Instructions testp and copysign have been added. i. e. Surface instructions support additional clamp modifiers. ldu. Surface Instructions • • Instruction sust now supports formatted surface stores. atom. and Application Binary Interface (ABI).Chapter 1. cvta. 1.0. prefetch.clamp and . rcp. PTX 2. Introduction • Single.3. and vice versa. and shared addresses to generic addresses. for prefetching to specified level of memory hierarchy. 1. • Taken as a whole.2. Generic addressing unifies the global. special registers. . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. isspacep. NOTE: The current version of PTX does not implement the underlying. local. Cache operations have been added to instructions ld. stack-based ABI. allowing memory instructions to access these spaces without needing to specify the state space. Generic Addressing Another major change is the addition of generic addressing. and shared state spaces. In PTX 2. and red now support generic addressing. Support for an Application Binary Interface Rather than expose details of a particular calling convention. New Instructions The following new instructions. st. instructions ld. these changes bring PTX 2.0. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. 2010 3 .3. January 24. local.g. suld.zero. so recursion is not yet supported. local. prefetchu..3.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. 1.4. st. and directives are introduced in PTX 2.and double-precision div. and sqrt with IEEE 754 compliant rounding have been added. These are indicated by the use of a rounding modifier and require sm_20. Instruction cvta for converting global. A new cvta instruction has been added to convert global. and sust.

lt. vote. A new directive. Barrier Instructions • • A system-level membar instruction. Reduction. New special registers %nsmid. has been added. 4 January 24.add. has been added. A bar.popc.b32.shared have been extended to handle 64-bit data types for sm_20 targets.le. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.u32 and bar.gt} have been added.or}. %clock64.red}. Other Extensions • • • Video instructions (includes prmt) have been added. Instructions bar.PTX ISA Version 2.red. .section. 2010 .0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.sys.ballot.red. Instructions {atom.pred have been added. membar.red}. bar now supports an optional thread count and register operands. bfi bit field extract and insert popc clz Atomic. A “vote ballot” instruction. %lanemask_{eq.f32 have been added.arrive instruction has been added.ge.{and. and Vote Instructions • • • New atomic and reduction instructions {atom.

and PTX support for abstracting the Application Binary Interface (ABI). January 24. Chapter 4 describes the basic syntax of the PTX language. Chapter 11 provides release notes for PTX Version 2. Chapter 5 describes state spaces. Chapter 7 describes the function and call syntax.Chapter 1. Chapter 10 lists the assembly directives supported in PTX. Chapter 8 describes the instruction set. Chapter 3 gives an overview of the PTX virtual machine model. calling convention. types. Chapter 6 describes instruction operands.0. 2010 5 . Chapter 9 lists special registers.4. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and variable declarations. Introduction 1.

PTX ISA Version 2.0 6 January 24. 2010 .

To coordinate the communication of the threads within the CTA. is an array of threads that execute a kernel concurrently or in parallel. To that effect. A cooperative thread array.z) that specifies the thread’s position within a 1D. one can specify synchronization points where threads wait until all threads in the CTA have arrived. or CTA. or host: In other words. tid. but independently on different data. 2. Each CTA has a 1D. Programming Model 2. ntid. can be isolated into a kernel function that is executed on the GPU as many different threads. (with elements tid. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.x.1.Chapter 2.2. or 3D shape specified by a three-element vector ntid (with elements ntid. or 3D CTA. Programs use a data parallel decomposition to partition inputs. a portion of an application that is executed many times. The thread identifier is a three-element vector tid.x.y. The vector ntid specifies the number of threads in each CTA dimension. and ntid. 2D. Each CTA thread uses its thread identifier to determine its assigned role. Threads within a CTA can communicate with each other. January 24. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.z). It operates as a coprocessor to the main CPU. compute addresses.1. 2010 7 . Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. 2D.y. and results across the threads of the CTA. assign specific input and output positions. Cooperative thread arrays (CTAs) implement CUDA thread blocks. compute-intensive portions of applications running on the host are off-loaded onto the device. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. and select work to perform. and tid. Each thread has a unique thread identifier within the CTA. 2. work. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.2. data-parallel. More precisely.

%ntid. 2. Threads may read and use these values through predefined. so that the total number of threads that can be launched in a single kernel invocation is very large. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. such that the threads execute the same instructions at the same time. WARP_SZ.0 Threads within a CTA execute in SIMT (single-instruction. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). or sequentially. Each grid of CTAs has a 1D. because threads in different CTAs cannot communicate and synchronize with each other. so PTX includes a run-time immediate constant. a warp has 32 threads. %ctaid. Typically. Some applications may be able to maximize performance with knowledge of the warp size. The warp size is a machine-dependent constant. Each grid also has a unique temporal grid identifier (gridid). and %gridid. CTAs that execute the same kernel can be batched together into a grid of CTAs. 2D . or 3D shape specified by the parameter nctaid. Multiple CTAs may execute concurrently and in parallel. This comes at the expense of reduced thread communication and synchronization. which may be used in any instruction where an immediate operand is allowed. However. read-only special registers %tid. %nctaid.PTX ISA Version 2. depending on the platform.2.2. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Threads within a warp are sequentially numbered. 2010 . multiple-thread) fashion in groups called warps. A warp is a maximal subset of threads from a single CTA. The host issues a succession of kernel invocations to the device. 8 January 24.

0) Thread (2. 2) Thread (3. 1) Thread (0. 0) Thread (1. 0) CTA (0. 1) Thread (4. 0) Thread (3. Thread Batching January 24. 2) Thread (1. 0) Thread (0. 1) CTA (2. 2) Thread (2. A grid is a set of CTAs that execute independently. 0) Thread (4. 1) Thread (3. 1) Thread (1. 0) CTA (1. 1) Thread (0. 0) CTA (2. 1) Grid 2 Kernel 2 CTA (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) CTA (1. 2010 9 . Figure 1. 1) Thread (2. 2) Thread (4. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program.Chapter 2.

The device memory may be mapped and read or written by the host. 2010 . constant. respectively. and texture memory spaces are optimized for different memory usages. as well as data filtering. referred to as host memory and device memory. Texture memory also offers different addressing modes. The global. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2.3. 10 January 24. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. and texture memory spaces are persistent across kernel launches by the same application. The global.PTX ISA Version 2. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. for more efficient transfer.0 2. or. all threads have access to the same global memory. Finally. constant. for some specific data formats. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Each thread has a private local memory. Both the host and the device maintain their own local memory.

2) Figure 2. Memory Hierarchy January 24. 0) Block (2. 0) Block (1. 1) Block (1. 0) Block (1. 0) Block (0. 2) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (2. 1) Block (1. 2010 11 . 1) Grid 1 Global memory Block (0. 0) Block (0. 1) Block (0.Chapter 2.

PTX ISA Version 2.0 12 January 24. 2010 .

manages. Branch divergence occurs only within a warp. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs).) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. schedules. At every instruction issue time. the multiprocessor employs a new architecture we call SIMT (single-instruction. and executes threads in groups of parallel threads called warps. manages.Chapter 3. (This term originates from weaving. A warp executes one common instruction at a time. It implements a single-instruction barrier synchronization. To manage hundreds of threads running several different programs. As thread blocks terminate. the threads converge back to the same execution path. and executes concurrent threads in hardware with zero scheduling overhead. a multithreaded instruction unit. When a host program invokes a kernel grid. new blocks are launched on the vacated multiprocessors. The multiprocessor SIMT unit creates. a voxel in a volume. different warps execute independently regardless of whether they are executing common or disjointed code paths. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. allowing. 2010 13 . January 24. The multiprocessor creates. Parallel Thread Execution Machine Model 3. so full efficiency is realized when all threads of a warp agree on their execution path. When a multiprocessor is given one or more thread blocks to execute. increasing thread IDs with the first warp containing thread 0. multiple-thread). A multiprocessor consists of multiple Scalar Processor (SP) cores. The way a block is split into warps is always the same. a cell in a grid-based computation). for example. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image.1. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. The multiprocessor maps each thread to one scalar processor core. the warp serially executes each branch path taken. each warp contains threads of consecutive. and on-chip shared memory. and each scalar thread executes independently with its own instruction address and register state. and when all paths complete. disabling threads that are not on that path. If threads of a warp diverge via a data-dependent conditional branch. it splits them into warps that get scheduled by the SIMT unit. the first parallel thread technology. The threads of a thread block execute concurrently on one multiprocessor.

If an atomic instruction executed by a warp reads. modifies. write to that location occurs and they are all serialized. the kernel will fail to launch. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. however. require the software to coalesce loads into vectors and manage divergence manually. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. A multiprocessor can execute as many as eight thread blocks concurrently. scalar threads. on the other hand. which is a read-only region of device memory. 14 January 24. Vector architectures. If there are not enough registers or shared memory available per multiprocessor to process at least one block.PTX ISA Version 2. the programmer can essentially ignore the SIMT behavior. In contrast with SIMD vector machines. whereas SIMT instructions specify the execution and branching behavior of a single thread. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A key difference is that SIMD vector organizations expose the SIMD width to the software. In practice. modify. which is a read-only region of device memory. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. each read. 2010 . but one of the writes is guaranteed to succeed. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. and writes to the same location in global memory for more than one of the threads of the warp. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. as well as data-parallel code for coordinated threads. For the purposes of correctness. As illustrated by Figure 3.0 SIMT architecture is akin to SIMD (Single Instruction. SIMT enables programmers to write thread-level parallel code for independent. • The local and global memory spaces are read-write regions of device memory and are not cached. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. but the order in which they occur is undefined. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. the number of serialized writes that occur to that location and the order in which they occur is undefined.

Hardware Model January 24.Chapter 3. Figure 3. 2010 15 . Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

0 16 January 24. 2010 .PTX ISA Version 2.

#ifdef. The C preprocessor cpp may be used to process PTX source files. Lines are separated by the newline character (‘\n’). whitespace is ignored except for its use in separating tokens in the language. #endif. #if. Each PTX file must begin with a . 4.1. Source Format Source files are ASCII text. 2010 17 . January 24. #line. Syntax PTX programs are a collection of text source files. Lines beginning with # are preprocessor directives. Pseudo-operations specify symbol and addressing management. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.2.target directive specifying the target architecture assumed. followed by a .Chapter 4.version directive specifying the PTX language version. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. See Section 9 for a more information on these directives. Comments Comments in PTX follow C/C++ syntax. using non-nested /* and */ for comments that may span multiple lines. and using // to begin a comment that extends to the end of the current line. #define. #else. PTX is case sensitive and uses lowercase for keywords. The following are common preprocessor directives: #include. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Comments in PTX are treated as whitespace. 4. All whitespace characters are equivalent.

Instruction keywords are listed in Table 2.reg .0 4. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.param . followed by source operands.b32 r1.pragma .2.global. %tid.const . The guard predicate may be optionally negated. constant expressions.3. and is written as @p. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. or label names.5.visible 4. and terminated with a semicolon. 2. 0.loc .PTX ISA Version 2. ld.sreg . array[r1]. 2010 . Table 1.tex .x.maxnreg .func .entry .b32 r1. so no conflict is possible with user-defined identifiers. where p is a predicate register. r1. Operands may be register variables.minnctapersm . Statements begin with an optional label and end with a semicolon.local .f32 array[N]. 18 January 24.3. All instruction keywords are reserved tokens in PTX. The destination operand is first. Statements A PTX statement is either a directive or an instruction. Examples: . address expressions.extern . r2. . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.version .1.section . Instructions have an optional guard predicate which controls conditional execution.maxntid . r2.f32 r2.reg . Directive Statements Directive keywords begin with a dot.global . The guard predicate follows the optional label and precedes the opcode. mov.b32 r1.shared . written as @!p.target .align . . shl.3.global start: .b32 add.maxnctapersm .file PTX Directives . r2.

2010 19 .Chapter 4. Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

dollar. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.g. e. %pm3 WARP_SZ 20 January 24. listed in Table 3. 2010 . The percentage sign can be used to avoid name conflicts. Table 3. or dollar characters. Many high-level languages such as C and C++ follow similar rules for identifier names. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. except that the percentage sign is not allowed. PTX predefines one constant and a small number of special registers that begin with the percentage sign. digits. or percentage character followed by one or more letters. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.4. …. digits. between user-defined variable names and compiler-generated names.0 4.PTX ISA Version 2. or they start with an underscore. underscore. PTX allows the percentage sign as the first character of an identifier. underscore.

0[fF]{hexdigit}{8} // single-precision floating point January 24. 4. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. When used in an instruction or data initialization. Unlike C and C++. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.. hexadecimal.s64 or .5. i.u64). the constant begins with 0f or 0F followed by 8 hex digits. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.5. there is no suffix letter to specify size. Constants PTX supports integer and floating-point constants and constant expressions. 4. each integer constant is converted to the appropriate size based on the data or instruction type at its use. the constant begins with 0d or 0D followed by 16 hex digits. octal. zero values are FALSE and non-zero values are TRUE. Integer literals may be written in decimal. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. integer constants are allowed and are interpreted as in C. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. These constants may be used in data initialization and as operands to instructions. where the behavior of the operation depends on the operand types. Syntax 4.1. Floating-point literals may be written with an optional decimal point and an optional signed exponent.e. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. To specify IEEE 754 doubleprecision floating point values.5.u64.2. i. in which case the literal is unsigned (. the sm_1x and sm_20 targets have a WARP_SZ value of 32. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.. every integer constant has type . The syntax follows that of C. 2010 21 . PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.e.s64) unless the value cannot be fully represented in . Type checking rules remain the same for integer. literals are always represented in 64-bit double-precision format. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. To specify IEEE 754 single-precision floating point values. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.s64 or the unsigned suffix is specified. and bit-size types. For predicate-type data and instructions. floating-point. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. or binary notation.Chapter 4.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64. 2nd is .u64 .s64 .u64) (.s64.f64 same as source .f64 converted type .s64 . or .u64 same as 1st operand .s64 .s64 .u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 integer integer integer integer integer int ?.s64) + . Syntax 4.u64 .Chapter 4.f64 use usual conversions .u64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 integer .f64 converted type constant literal + ! ~ Cast Binary (.f64 integer .u64 .6. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 : .s64 .f64 use usual conversions .5.s64 .u64 1st unchanged.u64 zero or non-zero same as sources use usual conversions Result Type same as source . .f64 use usual conversions . Table 5.s64 .s64 . 2010 25 .u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .

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shared . Kernel parameters. 2010 27 . addressability.param .const .tex January 24. read-only memory. or Function or local parameters. Special registers. 5.local . Global texture memory (deprecated).reg . private to each thread. Addressable memory shared between threads in 1 CTA. defined per-grid. pre-defined. Read-only. and level of sharing between threads. and Variables While the specific resources available in a given target GPU will vary. the kinds of resources will be common across platforms. Types. Table 6.global . shared by all threads.Chapter 5. The list of state spaces is shown in Table 4. and these resources are abstracted in PTX through state spaces and data types. platform-specific.sreg . State Spaces A state space is a storage area with particular characteristics. access rights. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Global memory. fast. access speed. Name State Spaces Description Registers. and properties of state spaces are shown in Table 5. defined per-thread. The characteristics of a state space include its size. State Spaces. All variables reside in some state space. Local memory.1. Shared. .

sreg . 32-. st.param and st.2. and performance monitoring registers. The number of registers is limited.e. or as elements of vector tuples. All special registers are predefined.PTX ISA Version 2.param instruction. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Register size is restricted. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 2010 .param instructions.const . 5. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. 28 January 24. unsigned integer.param (as input to kernel) . The most common use of 8-bit registers is with ld. Address may be taken via mov instruction. Registers differ from the other state spaces in that they are not fully addressable. or 128-bits.param (used in functions) . Registers may have alignment boundaries required by multi-word loads and stores. causing changes in performance. scalar registers have a width of 8-. Register State Space Registers (. Registers may be typed (signed integer. 2 Accessible via ld. register variables will be spilled to memory. aside from predicate registers which are 1-bit.local state space.sreg) state space holds predefined. and thread parameters. Device function input parameters may have their address taken via mov.reg state space) are fast storage locations.0 Table 7.shared .global . clock counters.local . floating point. or 64-bits.1. Special Register State Space The special register (. For each architecture. CTA.1. platform-specific registers. and vector registers have a width of 16-. 32-. 64-. predicate) or untyped. and will vary from platform to platform. i. it is not possible to refer to the address of a register. and cvt instructions. such as grid.1.. 16-.tex Restricted Yes No3 5. the parameter is then located on the stack frame and its address is in the . 3 Accessible only via the tex instruction.reg . When the limit is exceeded. 1 Accessible only via the ld.

for example). 2010 29 .1. Global memory is not sequentially consistent. b = b – 1. Threads must be able to do their work without waiting for other threads to do theirs. st. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.3.1. the bank number must be provided in the state space of the load instruction. For example.const[2]. Module-scoped local memory variables are stored at fixed addresses. For the current devices.extern . all addresses are in global memory are shared.global. whereas local memory variables declared January 24.local to access local variables.b32 const_buffer[]. [const_buffer+4].global to access global variables. ld. Banks are specified using the .1. This pointer can then be used to access the entire 64KB constant bank. Global State Space The global (. results in const_buffer pointing to the start of constant bank two. If no bank number is given. Types.extern . The constant memory is organized into fixed size banks. To access data in contant banks 1 through 10. If another thread sees the variable b change. and Variables 5. For any thread in a context. In implementations that support a stack. This reiterates the kind of parallelism available in machines that run PTX. bank zero is used. there are eleven 64KB banks. The size is limited. 5. It is the mechanism by which different CTAs and different grids can communicate. The remaining banks may be used to implement “incomplete” constant arrays (in C. the declaration . State Spaces. initialized by the host.const) state space is a read-only memory.5.global) state space is memory that is accessible by all threads in a context. All memory writes prior to the bar. Use ld. Local State Space The local state space (.local) is private memory for each thread to keep its own data. where the size is not known at compile time.b32 %r1. Multiple incomplete array variables declared in the same bank become aliases.const[2] . as it must be allocated on a perthread basis. as in lock-free and wait-free style programming. and atom. where bank ranges from 0 to 10.sync instruction are guaranteed to be visible to any reads after the barrier instruction. By convention. Constant State Space The constant (. Use ld. Threads wait at the barrier until all threads in the CTA have arrived.sync instruction.Chapter 5. the store operation updating a may still be in flight. the stack is in local memory.global. bank zero is used for all statically-sized constant variables.const[2] .local and st. // load second word 5. an incomplete array in bank 2 is accessed as follows: . For example.4. Consider the case where one thread executes the following two assignments: a = a + 1. It is typically standard memory with cache. Sequential consistency is provided by the bar. each pointing to the start address of the specified constant bank.const[bank] modifier.b32 const_buffer[].

read-only variables declared in the . [%ptr].param space variables. ld.u32 %n. (2a) to declare formal input and return parameters for device functions called from within kernel execution. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.1. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. The resulting address is in the . No access protection is provided between parameter and global space in this case. … 30 January 24. For example. Similarly. Note: The location of parameter space is implementation specific. Example: . 2010 .6. 5. [N].f64 %d. .param. ld. %n. The address of a kernel parameter may be moved into a register using the mov instruction.reg . device function parameters were previously restricted to the register state space.f64 %d.0 and requires target architecture sm_20.param instructions.param instructions. per-kernel versus per-thread).param state space and is accessed using ld.align 8 . The use of parameter state space for device function parameters is new to PTX ISA version 2. in some implementations kernel parameters reside in global memory. Note that PTX ISA versions 1. . and (2b) to declare locally-scoped byte array variables that serve as function call arguments.b8 buffer[64] ) { .PTX ISA Version 2.u32 %n.b32 N.param) state space is used (1) to pass input arguments from the host to the kernel.entry bar ( . PTX code should make no assumptions about the relative locations or ordering of . [buffer]. … Example: . 5.reg .1.b32 len ) { . In implementations that do not support a stack. The kernel parameter variables are shared across all CTAs within a grid. These parameters are addressable.param.reg .1.6.param state space. Therefore.param .param .param . typically for passing large structures by value to a function. Values passed from the host to the kernel are accessed through these parameter variables using ld.entry foo ( . ld. mov. Parameter State Space The parameter (.u32 %n.u32 %ptr.param. all local memory variables are stored at fixed addresses and recursive function calls are not supported. len. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).x supports only kernel function parameters in .u32 %ptr.param space.0 within a function or kernel body are allocated on the stack.

.param space is also required whenever a formal parameter has its address taken within the called function. It is not possible to use mov to get the address of a return parameter or a locally-scoped . Types. such as C structures larger than 8 bytes.param byte array variable that represents a flattened C structure or union. and so the address will be in the .1. dbl. … See the section on function call syntax for more details. … } // code snippet from the caller // struct { double d. the caller will declare a locally-scoped . a byte array in parameter space is used. [buffer]. the address of a function input parameter may be moved into a register using the mov instruction. mystruct). Device Function Parameters PTX ISA version 2.param formal parameter having the same size and alignment as the passed argument.param .b8 mystruct.local state space and is accessed via ld.0 extends the use of parameter space to device function parameters. and Variables 5. .func foo ( . .reg .param.6. } mystruct. . }. In this case.f64 [mystruct+0]. January 24.Chapter 5. int y. 2010 31 .param space variable. x.reg .param and function return parameters may be written using st. This will be passed by value to a callee.param. Note that the parameter will be copied to the stack if necessary.align 8 . In PTX. . which declares a . The most common use is for passing objects by value that do not fit within a PTX register. Typically. … st. State Spaces.reg . is flattened. Function input parameters may be read via ld.f64 dbl.f64 %d. ld.local instructions.s32 [mystruct+8]. passed to foo … .2. it is illegal to write to an input parameter or read from a return parameter.param . (4. st. int y. call foo.reg . .s32 %y.s32 x. Aside from passing structures by value.s32 %y.param. ld. [buffer+8]. Example: // pass object of type struct { double d.reg .local and st.align 8 .param.f64 %d.b8 buffer[12] ) { .b32 N.param.

is equivalent to .6 for its use in texture instructions. The texture name must be of type .u32 . 5.u32 .shared) state space is a per-CTA region of memory for threads in a CTA to share data. and .tex . Physical texture resources are allocated on a per-module granularity. and variables declared in the .tex state space are equivalent to module-scoped .tex . Texture State Space (deprecated) The texture (.tex directive is retained for backward compatibility. tex_f.texref. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). Multiple names may be bound to the same physical texture identifier. A texture’s base address is assumed to be aligned to a 16-byte boundary.1. For example.7.texref tex_a.u32 .u32 tex_a. Use ld.8. An error is generated if the maximum number of physical resources is exceeded. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.tex directive will bind the named texture memory variable to a hardware texture identifier.texref variables in the . The . Shared State Space The shared (. tex_c. a legacy PTX definitions such as .shared and st. Example: . An address in shared memory can be read and written by any thread in a CTA.u32 or . See Section 5. where texture identifiers are allocated sequentially beginning with zero.0 5.tex . Texture memory is read-only. and programs should instead reference texture memory through variables of type . where all threads read from the same address.tex .shared to access shared variables. tex_d.3 for the description of the .u64. It is shared by all threads in a context. The .global . Shared memory typically has some optimizations to support the sharing.tex .1. tex_d.7.global state space. One example is broadcast. 2010 .tex) state space is global memory accessed via the texture instruction.texref type and Section 8. Another is sequential access from sequential threads. 32 January 24.tex variables are required to be defined in the global scope.PTX ISA Version 2.u32 tex_a.

and cvt instructions. needed to fully specify instruction behavior. January 24. Types.u8. stored.f32. .b8 instruction types are restricted to ld.f64 types.b16. . all variables (aside from predicates) could be declared using only bit-size types.2. Register variables are always of a fundamental type. All floating-point instructions operate only on . For convenience.s64 . so their names are intentionally short. Operand types and sizes are checked against instruction types for compatibility.f16 floating-point type is allowed only in conversions to and from .Chapter 5.s8.s32. stored. .s8.1. ld. the fundamental types reflect the native data types supported by the target architectures. and converted using regular-width registers.s16.b8.f64 . and Variables 5. st.u32. but typed variables enhance program readability and allow for better operand type checking. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.u8.2. .pred Most instructions have one or more type specifiers. .f16. 2010 33 .b64 .2. . st. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.u16. Restricted Use of Sub-Word Sizes The . The bitsize type is compatible with any fundamental type having the same size.f64 types. and instructions operate on these types. .u64 . In principle.f32 and . 5.b32. . A fundamental type specifies both a basic type and a size. The . The same typesize specifiers are used for both variable definitions and for typing instructions. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . . For example.f32 and . State Spaces. Fundamental Types In PTX. and . Types 5. Two fundamental types are compatible if they have the same basic type and are the same size. . The following table lists the fundamental type specifiers for each basic type: Table 8. or converted to other types and sizes. so that narrow values may be loaded. Signed and unsigned integer types are compatible if they have the same size. .2.

texref type that describe sampler properties are ignored. Retrieving the value of a named member via query instructions (txq. The three built-in types are . 34 January 24. texture and sampler information each have their own handle. PTX has two modes of operation. sust. base address.samplerref variables. sured). suld. and Surface Types PTX includes built-in “opaque” types for defining texture.0 5.surfref. field ordering. hence the term “opaque”. and de-referenced by texture and surface load. accessing the pointer with ld and st instructions.samplerref. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. texture and sampler information is accessed through a single .. but the pointer cannot otherwise be treated as an address. samplers. and surface descriptor variables. Sampler. passed as a parameter to functions. or performing pointer arithmetic will result in undefined results.u64} reg. In the independent mode. For working with textures and samplers. or surfaces via texture and surface load/store instructions (tex. and query instructions.PTX ISA Version 2. 2010 . Referencing textures.texref handle. store.texref. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. . and overall size is hidden to a PTX program. In independent mode the fields of the . opaque_var. i. but all information about layout. suq). Creating pointers to opaque variables using mov. The following tables list the named members of each type for unified and independent texture modes. the resulting pointer may be stored to and loaded from memory.3. since these properties are defined by . These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. allowing them to be defined separately and combined at the site of usage in the program. These types have named fields similar to structures. In the unified mode. and . sampler. Texture.e.{u32.

mirror. 1 nearest. clamp_to_border N/A N/A N/A N/A N/A . Types. 2010 35 . clamp_ogl. clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode . linear wrap. and Variables Table 9. clamp_to_edge. linear wrap.samplerref values N/A N/A N/A N/A nearest. State Spaces.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge.texref values in elements in elements in elements 0.Chapter 5.texref values . clamp_to_border 0.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. mirror. Member width height depth Opaque Type Fields in Unified Texture Mode . 1 ignored ignored ignored ignored .

samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global . Example: . . When declared at module scope. At module scope. these variables are declared in the . . As kernel parameters.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. these variables must be in the . .PTX ISA Version 2.texref tex1. filter_mode = nearest }. Example: .global .global . the types may be initialized using a list of static expressions assigning values to the named members.global .param state space.global state space.samplerref my_sampler_name.global .surfref my_surface_name. 2010 . 36 January 24.texref my_texture_name.

q. where the fourth element provides padding. an optional array size.v4 vector.v2 or .v3 }.global . This is a common case for three-dimensional grids. Examples: . for example.pred p.reg .4.v4 .s32 i. Vectors must be based on a fundamental type.f32 accel.u32 loc. . 5. In addition to fundamental types.v1. . Every variable must reside in one of the state spaces enumerated in the previous section. Variable Declarations All storage for data is specified with variable declarations.shared .global .Chapter 5. Types. 0.v4. // a length-4 vector of bytes By default. . Predicate variables may only be declared in the register state space. and Variables 5. 0.2. 0}.struct float4 coord.u8 bg[4] = {0.0}.global . 2010 37 . January 24.4. a variable declaration describes both the variable’s type and its state space.1.0. .const .b8 v. // a length-4 vector of floats . A variable declaration names the space in which the variable resides. its name. 1.reg . Vectors cannot exceed 128-bits in length.v4 .f32 V.v4.f32 v0. // typedef . Vectors Limited-length vector types are supported.f64 is not allowed.4. . . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .v2 . and they may reside in the register space. PTX supports types for simple aggregate objects such as vectors and arrays.u16 uv. // a length-2 vector of unsigned ints . etc. its type and size.v4 . textures. and an optional fixed address for the variable.v2. vector variables are aligned to a multiple of their overall size (vector length times base-type size). Examples: . an optional initializer. Variables In PTX. r. Three-element vectors may be handled by using a . State Spaces. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.reg . 5.struct float4 { .f32 bias[] = {-1. .global .global .

where the variable name is followed by an equals sign and the initial value or values for the variable. 0}.0}}. To declare an array..0. Here are some examples: .shared . 2010 . // address of rgba into ptr Currently.global ... {1.u8 mailbox[128]. Variables that hold addresses of variables or instructions should be of type .05.global .global . 19*19 (361) halfwords are reserved (722 bytes). 0}.{.1.1.1}.0. 38 January 24. .0}.PTX ISA Version 2.1. 5.pred.s32 offset[][] = { {-1. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.05}. this can be used to initialize a jump table to be used with indirect branches or calls. Initializers are allowed for all types except .local .4.{.4. variable initialization is supported only for constant and global state spaces.u16 kernel[19][19]. The size of the dimension is either a constant expression.global .s32 n = 10.global .0.u64.f32 blur_kernel[][] = {{. Similarly. .u8 rgba[3] = {{1. Examples: . {0. label names appearing in initializers represent the address of the next instruction following the label. For the kernel declaration above. or is left empty.4. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.0 5. A scalar takes a single value. {0. Array Declarations Array declarations are provided to allow the programmer to reserve space.05}}.3. .05.v4 .4. -1}. Variable names appearing in initializers represent the address of the variable. . {0. The size of the array specifies how many elements should be reserved.1. {0.0}..f16 and . 1} }. being determined by an array initializer. . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).0... this can be used to statically initialize a pointer to a variable.1.b32 ptr = rgba.u32 or .

2..align 4 .. it is quite common for a compiler frontend to generate a large number of register names. State Spaces.6.0.b32 variables. say one hundred. The default alignment for scalar and array variables is to a multiple of the base-type size. %r1. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. // declare %r0.4. Examples: // allocate array at 4-byte aligned address. %r1. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. alignment specifies the address alignment for the starting address of the entire array. The variable will be aligned to an address which is an integer multiple of byte-count. ….Chapter 5. Alignment is specified using an optional . These 100 register variables can be declared as follows: .0. and Variables 5.0. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Array variables cannot be declared this way. 5. January 24. . Parameterized Variable Names Since PTX supports virtual registers. Rather than require explicit declaration of every name. of .0. not for individual elements. For example. .0}. 2010 39 . named %r0.b8 bar[8] = {0.b32 %r<100>.reg .0. The default alignment for vector variables is to a multiple of the overall vector size. Types.align byte-count specifier immediately following the state-space specifier. For arrays. nor are initializers permitted.4. suppose a program uses a large number. %r99. Elements are bytes. and may be preceded by an alignment specifier.. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.const .5.

0 40 January 24.PTX ISA Version 2. 2010 .

6. r. st. The ld. Each operand type must be compatible with the type determined by the instruction template and instruction type. mov. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. q. Operand Type Information All operands in instructions have a known type from their declarations. 2010 41 . Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Instruction Operands 6. January 24. so operands for ALU instructions must all be in variables declared in the . The result operand is a scalar or vector variable in the register state space. PTX describes a load-store machine.1. The bit-size type is compatible with every type having the same size.3. There is no automatic conversion between types. The cvt (convert) instruction takes a variety of operand types and sizes. Predicate operands are denoted by the names p. 6. Instructions ld and st move data from/to addressable state spaces to/from registers. Source Operands The source operands are denoted in the instruction descriptions by the names a. The mov instruction copies data between registers. s.2. and cvt instructions copy data from one location to another. For most operations. Most instructions have an optional predicate guard that controls conditional execution. as its job is to convert from nearly any data type to any other data type (and size). and c.Chapter 6. b. and a few instructions have additional predicate source operands. .reg register state space. Integer types of a common size are compatible with each other. the sizes of the operands must be consistent.

arrays.s32 tbl[256]. . The interesting capabilities begin with addresses.b32 p.s32 q.shared. address registers.u16 ld.4. Using Addresses. . tbl.v4. . Examples include pointer arithmetic and pointer comparisons. W.const.const .global . [tbl+12].u16 r0. The mov instruction can be used to move the address of a variable into a pointer.reg . there is no support for C-style pointer arithmetic. q.reg . The syntax is similar to that used in many assembly languages. r0. Here are a few examples: . Arrays.u16 x.gloal. 2010 . [V].f32 W.u32 42 January 24. Load and store operations move data between registers and locations in addressable state spaces.[x]. . address register plus byte offset. .0 6.reg .v4 . ld. p. The address is an offset in the state space in which the variable is declared.f32 V.v4 . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.f32 ld.1. and immediate address expressions which evaluate at compile-time to a constant address. . and Vectors Using scalar variables as operands is straightforward. Address expressions include variable names.s32 mov.reg .shared . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. 6.4. and vectors.PTX ISA Version 2. All addresses and address computations are byte-based.

f32 {a.g. for use in an indirect branch or call. // move address of a[1] into s 6.c.x.g V. .f32 ld.a. a[N-1].global. Array elements can be accessed using an explicitly calculated byte address. V.reg . .z V. If more complicated indexing is desired.z and .b. mov. .y V. which may improve memory performance. a register variable. d. V2.Chapter 6. Arrays as Operands Arrays of all types can be declared.4.4. Elements in a brace-enclosed vector.c. Vector loads and stores can be used to implement wide loads and stores.b V. Rc.u32 s.v4 .r V. The registers in the load/store operations can be a vector. and the identifier becomes an address constant in the space where the array is declared. a[1].4. Rb.b and . [addr+offset]. [addr+offset2].r. ld. where the offset is a constant expression that is either added or subtracted from a register variable. mov. A brace-enclosed list is used for pattern matching to pull apart vectors.f32 V. say {Ra. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.3. a[0].reg . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.b. Here are examples: ld. The size of the array is a constant in the program. 2010 43 .global.d}. or a braceenclosed list of similarly typed scalars.2.u32 {a. . .w = = = = V. and in move instructions to get the address of the label or function into a register. or a simple “register with constant offset” expression. ld.u32 s.u32 s. .d}.v4. which include mov. as well as the typical color fields . Vectors may also be passed as arguments to called functions. Instruction Operands 6. b.a 6. and tex.x V.f32 a. Vectors as Operands Vector operands are supported by a limited subset of instructions. Vector elements can be extracted from the vector with the suffixes . st. January 24.global.v2.global.4. Examples are ld. The expression within square brackets is either a constant integer. Rd}. it must be written as an address calculation prior to use. c.y.w.v4. or by indexing into the array using square-bracket notation.

and ~131.u16 instruction is given a u16 source operand and s32 as a destination operand.5.PTX ISA Version 2. logic. Operands of different sizes or types must be converted prior to the operation. 44 January 24. the u16 is zero-extended to s32. if a cvt. except for operations where changing the size and/or type is part of the definition of the instruction. 2010 . and data movement instruction must be of the same type and size. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 6. Type Conversion All operands to all arithmetic.000 for f16).1.0 6. For example.s32. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.5.

January 24. zext = zero-extend. 2010 45 . s2f = signed-to-float. then sign-extend to 32-bits. chop = keep only low bits that fit. Instruction Operands Table 11. u2f = unsigned-to-float.u32 targeting a 32-bit register will first chop to 16-bits.s16. f2s = float-to-signed. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. For example. f2u = float-to-unsigned. Notes 1 If the destination register is wider than the destination format. f2f = float-to-float. the result is extended to the destination register width after chopping. cvt.Chapter 6. The type of extension (sign or zero) is based on the destination format.

rni .rz .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.PTX ISA Version 2. choosing even integer if source is equidistant between two integers.rmi . Modifier . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. there are four integer rounding modifiers and four floating-point rounding modifiers.rn . The following tables summarize the rounding modifiers.5.rm .0 6.rpi Integer Rounding Modifiers Description round to nearest integer. Table 12.rzi . Modifier . 2010 .2. In PTX. Rounding Modifiers Conversion instructions may specify a rounding modifier.

first access is high Notes January 24.6.Chapter 6. Operand Costs Operands from different state spaces affect the speed of an operation. Instruction Operands 6. The register in a store operation is available much more quickly. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Registers are fastest. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Another way to hide latency is to issue the load instructions as early as possible. 2010 47 . Table 11 gives estimates of the costs of using different kinds of memory. Table 14. Much of the delay to memory can be hidden in a number of ways. while global memory is slowest.

0 48 January 24. 2010 .PTX ISA Version 2.

together these specify the function’s interface. and is represented in PTX as follows: . A function must be declared or defined prior to being called. Scalar and vector base-type input and return parameters may be represented simply as register variables. and Application Binary Interface (ABI). support for variadic functions (“varargs”). function calls. Abstracting the ABI Rather than expose details of a particular calling convention. and memory allocated on the stack (“alloca”). These include syntax for function definitions. NOTE: The current version of PTX does not implement the underlying. functions are declared and defined using the . Execution of the ret instruction within foo transfers control to the instruction following the call. Function declarations and definitions In PTX. A function declaration specifies an optional list of return parameters. so recursion is not yet supported. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. 7. and return values may be placed directly into register variables. execution of the call instruction transfers control to foo. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations.func foo { … ret. the function name. 2010 49 . stack-based ABI. and an optional list of input parameters. A function definition specifies both the interface and the body of the function. … Here. we describe the features of PTX needed to achieve this hiding of the ABI.1. or prototype.Chapter 7. stack layout. arguments may be register variables or constants. parameter passing. } … call foo. January 24. implicitly saving the return address. The simplest function has no parameters or return values.func directive. At the call. In this section.

b32 c1.reg .u32 %inc ) { add. [y+9].param.b8 c1.param space variables are used in two ways. // scalar args in . }.param. [y+10].param. inc_ptr.param.align 8 y[12]) { . Second. %ptr.align 8 py[12].param. 2010 .reg .c4.reg .f1. bumpptr. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . %inc. ld.func (.0 Example: . ld. a .reg space. passed by value to a function: struct { double dbl. . c3.b64 [py+ 0]. (%r1. st.param.s32 out) bar (.f64 f1.b8 [py+10].b8 c2.f64 f1. st. [y+11]. byte array in .param . st. For example.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. The . %rc1.u32 %res) inc_ptr ( . … st. %rc1. Since memory accesses are required to be aligned to a multiple of the access size.param. a .b8 .c3. consider the following C structure.param space memory.c2. c2. ld.param space call (%out). … … // computation using x.param variable y is used in function definition bar to represent a formal parameter. (%x. ret.reg . st. this structure will be flattened into a byte array. char c[4].s32 x. py).b8 .reg .b8 c3.u32 %ptr.f64 field are aligned.u32 %res.b8 [py+ 9].param. In PTX. .func (.param.b8 c4. note that .b8 [py+ 8]. 50 January 24.c1. First. %rc2.4). } … call (%r1). .param .PTX ISA Version 2. … In this example. } { . ld.reg . … ld.b8 [py+11]. %rc2.reg . [y+8]. c4. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param. %rd. [y+0].param state space is used to pass the structure by value: .

. A .param argument must be declared within the local scope of the caller. For a callee. The .reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.reg state space in this way provides legacy support.Chapter 7.param and ld.param byte array is used to collect together fields of a structure being passed by value. size. Note that the choice of . • The .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param space byte array with matching type. the argument must also be a . In the case of . • The .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. and alignment of parameters. For . Abstracting the ABI The following is a conceptual way to think about the .param arguments. Typically. The ..reg space formal parameters. the corresponding argument may be either a . the corresponding argument may be either a . In the case of .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.reg or .reg space variable with matching type and size.param variables or .param state space use in device functions.param space formal parameters that are base-type scalar or vector variables. January 24.param memory must be aligned to a multiple of 1. • • Arguments may be . 4. or a constant that can be represented in the type of the formal parameter. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. The following restrictions apply to parameter passing.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.reg state space can be used to receive and return base-type scalar and vector values. or constants.reg variables. or a constant that can be represented in the type of the formal parameter. 2.param space formal parameters that are byte arrays. all st.param instructions used for argument passing must be contained in the basic block with the call instruction. size. • • • For a callee. For a caller. Supporting the .param variables. 2010 51 . a . 8. This enables backend optimization and ensures that the .g. • • • Input and return parameters may be .param or .param or . or 16 bytes. For a caller. Parameters in .reg space variable of matching type and size. In the case of . and alignment.param state space is used to receive parameter values and/or pass return values back to the caller.

param byte array should be used to return objects that do not fit into a register. formal parameters were restricted to . PTX 1.0 7.0. 2010 .reg state space. and there was no support for array parameters.0 continues to support multiple return registers for sm_1x targets.1. Objects such as C structures were flattened and passed or returned using multiple registers.1. and .param state space. and a .x. 52 January 24.x supports multiple return values for this purpose.PTX ISA Version 2. Changes from PTX 1.x In PTX ISA version 1. For sm_2x targets. PTX 2. PTX 2.reg or .0 restricts functions to a single return value.param space parameters support arrays. In PTX ISA version 2. formal parameters may be in either .

reg .b64 val) %va_arg64 (. setp. 2010 53 .2. or 4 bytes.h and varargs.reg . and end access to a list of variable arguments.pred p. PTX provides a high-level mechanism similar to the one provided by the stdarg.reg . 2.reg . 2. In both cases.. 0.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . .. %va_arg. 4. variadic functions are declared with an ellipsis at the end of the input parameter list. // default to MININT mov. … ) . 2. max. ) { . .u32 align) .h headers in C. the size may be 1. or 8 bytes. (2.u32 sz.func (. Once all arguments have been processed.func baz ( . … call (%max).b32 result. %s2). ret. .reg . iteratively access. .u32 sz.reg . 4. Abstracting the ABI 7. val.reg . . maxN. call (val). The function prototypes are defined as follows: .func (.reg . bra Loop.u32 N. To support functions with a variable number of arguments.func ( . for %va_arg64. N. … %va_start returns Loop: @p Done: January 24. %va_end is called to free the variable argument list handle. ctr.reg .s32 val. Variadic functions NOTE: The current version of PTX does not support variadic functions. } … call (%max). call (ap).func okay ( … ) Built-in functions are provided to initialize. %r3). 0x8000000. result. 4).u32. along with the size and alignment of the next data value to be accessed.s32 result ) maxN ( . the size may be 1. (3.u32 align) . (ap. maxN. %r2.func (.reg . following zero or more fixed parameters: . 4. bra Done. . %s1. the alignment may be 1.s32 result. . %r1.b32 val) %va_arg (.u32 ptr) %va_start .reg .u32 ap. (ap).u32 ptr.reg .reg . .b32 ctr. For %va_arg. In PTX.Chapter 7.reg . mov.u32 ptr.u32 a.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg .reg . 8. call %va_end. ctr. %va_start.u32 b. This handle is then passed to the %va_arg and %va_arg64 built-in functions. or 16 bytes.func %va_end (.ge p.

PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. The array is then accessed with ld. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. 54 January 24.func ( . To allocate memory.u32 ptr ) %alloca ( . Alloca NOTE: The current version of PTX does not support alloca.local and st.reg . a function simply calls the built-in function %alloca.3.local instructions.reg . If a particular alignment is required. defined as follows: . 2010 . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.PTX ISA Version 2.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.0 7.

a. the D operand is the destination operand. A. The setp instruction writes two destination registers. opcode D. For instructions that create a result value. B. January 24. C. We use a ‘|’ symbol to separate multiple destination registers. the semantics are described. opcode A. 8. B. A. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. In addition to the name and the format of the instruction. setp.Chapter 8.lt p|q. // p = (a < b). opcode D. A. followed by some examples that attempt to show several possible instantiations of the instruction. q = !(a < b). 2010 55 . A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. opcode D. and C are the source operands.2.s32.1. PTX Instructions PTX instructions generally have from zero to four operands. b. while A. Instruction Set 8. For some instructions the destination operand is optional. B.

pred as the type specifier.lt. 1. add 1 to j To get a conditional branch or conditional function call.0 8.PTX ISA Version 2.s32 p. where p is a predicate variable. the following PTX instruction sequence might be used: @!p L1: setp. add.reg . i. optionally negated. 1. j. This can be written in PTX as @p setp. q. 2010 . branch over 56 January 24.3. bra L1. To implement the above example as a true conditional branch. j.s32 j. As an example.s32 p. use a predicate to control the execution of the branch or call instructions.lt. … // compare i to n // if false. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. Instructions without a guard predicate are executed unconditionally. add. n. Predicates are most commonly set as the result of a comparison performed by the setp instruction.pred p. n. Predicated Execution In PTX. So.s32 j. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. consider the high-level code if (i < n) j = j + 1. predicate registers are virtual and have . predicate registers can be declared as . i. // p = (i < n) // if i < n.

2. lo (lower). and bitsize types. unsigned integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). If either operand is NaN. The bit-size comparisons are eq and ne. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.3.1. ne (not-equal). lt. Unsigned Integer. Table 15. ordering comparisons are not defined for bit-size types. and ge (greater-than-or-equal). le (less-than-or-equal). Table 16.Chapter 8. ls (lower-or-same). Instruction Set 8. Comparisons 8. ne. gt (greater-than). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. hi (higher).3. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. and hs (higher-or-same). le. ge.1. 2010 57 . The following table shows the operators for signed integer.3. ne. The unsigned comparisons are eq. gt.1. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.1. the result is false. lt (less-than).

Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. unordered versions are included: equ. If either operand is NaN. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. There is no direct conversion between predicates and integer values. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. If both operands are numeric values (not NaN). leu. ltu.PTX ISA Version 2. then the result of these comparisons is true. xor. However. or. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. neu. num returns true if both operands are numeric values (not NaN).1.2. Table 18.3.u32 %r1. Table 17. geu. and mov. for example: selp. then these comparisons have the same result as their ordered counterparts. and no direct way to load or store predicate register values. and nan returns true if either operand is NaN. two operators num (numeric) and nan (isNaN) are provided.0 To aid comparison operations in the presence of NaN values. gtu. not.0.%p. setp can be used to generate a predicate from an integer. // convert predicate to 32-bit value 58 January 24. 2010 .

bX . Instruction Set 8.. i.uX ok ok ok inv . b. unsigned. float. and these are placed in the same order as the operands. For example.reg .sX . Signed and unsigned integer types agree provided they have the same size. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.u16 d.e. and integer operands are silently cast to the instruction type if needed. It requires separate type-size modifiers for the result and source. • The following table summarizes these type checking rules. a.u16 d.reg .4. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. the add instruction requires type and size information to properly perform the addition operation (signed.sX ok ok ok inv .bX .u16 d. Example: .reg . For example: . Table 19. a.fX ok ok ok ok January 24.f32 d.u16 a. they must match exactly.Chapter 8. Type Checking Rules Operand Type . different sizes). most notably the data conversion instruction cvt. add. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.f32.fX ok inv inv ok Instruction Type . and this information must be specified as a suffix to the opcode. Floating-point types agree only if they have the same size. . b. cvt. a. 2010 59 . For example. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.uX .

the size must match exactly. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. Table 20. ld. The following table summarizes the relaxed type-checking rules for source operands. When a source operand has a size that exceeds the instruction-type size.1. Source register size must be of equal or greater size than the instruction-type size. Floating-point source registers can only be used with bit-size or floating-point instruction types. st. parse error. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. “-“ = allowed. so those rows are invalid for cvt. or converted to other types and sizes. Note that some combinations may still be invalid for a particular instruction. For example.PTX ISA Version 2. inv = invalid. 2. the data will be truncated. When used with a narrower bit-size type. floating-point instruction types still require that the operand type-size matches exactly. When used with a floating-point instruction type. and converted using regular-width registers.bX instruction types. so that narrow values may be loaded.4. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. for example. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Bit-size source registers may be used with any appropriately-sized instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Notes 3. 1. 4. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Operand Size Exceeding Instruction-Type Size For convenience. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. the cvt instruction does not support . 60 January 24. stored.0 8. no conversion needed. The data is truncated to the instruction-type size and interpreted according to the instruction type. 2010 . stored. unless the operand is of bit-size type.

inv = Invalid. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Bit-size destination registers may be used with any appropriately-sized instruction type. Notes 3. When used with a narrower bit-size instruction type. The data is sign-extended to the destination register width for signed integer instruction types. zext = zero-extend. January 24. The following table summarizes the relaxed type-checking rules for destination operands. 2. 1. 2010 61 . Destination register size must be of equal or greater size than the instruction-type size. otherwise. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Table 21. the data is zeroextended. The data is signextended to the destination register width for signed integer instruction types. 4. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the size must match exactly. parse error. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. the destination data is zero. the data is sign-extended. If the corresponding instruction type is signed integer.or sign-extended to the size of the destination register.Chapter 8. When used with a floatingpoint instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. “-“ = Allowed but no conversion needed. the data will be zero-extended. and is zero-extended to the destination register width otherwise.

the optimizing code generator automatically determines points of re-convergence. until C is not expressive enough. for example. conditional function call. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Both situations occur often in programs. A compiler or programmer may chose to enforce portable. 62 January 24. or conditional return. the threads are called divergent. by a right-shift instruction. the threads are called uniform.6. 8. If threads execute down different control flow paths. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers.1. this is not desirable. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. so it is important to have divergent threads re-converge as soon as possible. 16-bit registers in PTX are mapped to 32-bit physical registers. 8. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.0 8. For divergent control flow. 2010 . and for many applications the difference in execution is preferable to limiting performance. the semantics of 16-bit instructions in PTX is machine-specific. and 16-bit computations are “promoted” to 32-bit computations. Therefore. When executing on a 32-bit data path. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. a compiler or code author targeting PTX can ignore the issue of divergent threads. Divergence of Threads in Control Constructs Threads in a CTA execute together. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. using the . Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. for many performance-critical applications.PTX ISA Version 2. at least in appearance. At the PTX language level.uni suffix.5. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. However. These extra precision bits can become visible at the application level.6. until they come to a conditional control construct such as a conditional branch. The semantics are described using C. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. If all of the threads act in unison and follow a single control flow path. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.

The Integer arithmetic instructions are: add sub add.7. addc sub.7. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.Chapter 8. 2010 63 . 8. the optional guard predicate is omitted from the syntax. Instructions All PTX instructions may be predicated. In the following descriptions.cc.1.cc. Instruction Set 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.

PTX ISA Version 2.b. a.0 Table 22. PTX ISA Notes Target ISA Notes Examples Table 23.s32 .u32. Applies only to . Saturation modifier: . . a.s16.type = { .s32 c.s32 d. a. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. b.s16.z.sat applies only to . Supported on all target architectures.sat.MAXINT (no overflow) for the size of the operation. .s32 type.u32.u16. Supported on all target architectures.c. b.. d.sat applies only to . Introduced in PTX ISA version 1. . d = a + b.y. sub. sub. b.u32 x.s32 d.s64 }. Introduced in PTX ISA version 1.type add{.s32 c.1. a. @p add.MAXINT (no overflow) for the size of the operation. PTX ISA Notes Target ISA Notes Examples 64 January 24.sat limits result to MININT. 2010 .0. add Syntax Integer Arithmetic Instructions: add Add two values.sat limits result to MININT. // . add. .sat}.type = { . b.s32.0. . .u16.s32. d.type sub{. . Applies only to .s32 type.s32 .sat}. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. .u64. . d = a – b.. Description Semantics Notes Performs addition and writes the resulting value into a destination register.s64 }. // . add.u64. Saturation modifier: .a.

x2.cc.z4.b32 addc. add.y3.2.cc Syntax Integer Arithmetic Instructions: add.z4. x4. x2. Supported on all target architectures.cc. b.CF.type d.cc specified. .cc. .z2. add.y1.b32 addc.y4. No saturation. and there is no support for setting. x4.b32 x1.z3.2.cc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.cc. x3. Table 24. @p @p @p @p add. No saturation. . sub.b32 addc.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.CF No integer rounding modifiers.b32 addc.cc.type = {.CF No integer rounding modifiers. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. clearing. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. a.cc Add two values with carry-out. Behavior is the same for unsigned and signed integers.CF) holding carry-in/carry-out or borrowin/borrow-out. b. No other instructions access the condition code. addc{.s32 }.cc. d = a + b. 2010 65 .y4.b32 x1.b32 addc. carry-out written to CC.z1.cc}.cc. x3.Chapter 8.z2.s32 }. @p @p @p @p add.type d.y2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.cc. Instruction Set Instructions add. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. Supported on all target architectures.cc. if . d = a + b + CC.type = { .z1.b32 addc. a.y3. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.y2. Behavior is the same for unsigned and signed integers.z3. or testing the condition code.u32. Introduced in PTX ISA version 1.y1. Introduced in PTX ISA version 1. These instructions support extended-precision integer addition and subtraction. . addc. carry-out written to CC.u32.

Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. . Introduced in PTX ISA version 1.y2.y2. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.z2.b32 x1. d = a .b32 subc.z4.type d.y4.cc specified. Behavior is the same for unsigned and signed integers.PTX ISA Version 2.cc.cc. . x4.b32 subc.cc.type = {.cc. a. d = a – b.cc Subract one value from another.CF No integer rounding modifiers.cc}.b32 subc. Introduced in PTX ISA version 1. borrow-out written to CC.u32.CF No integer rounding modifiers.b32 subc.y1. No saturation.u32. sub. sub. x4.0 Table 26. b.cc.y3.z2. @p @p @p @p sub.y3. withborrow-in and optional borrow-out. borrow-out written to CC. @p @p @p @p sub.z3. 2010 . Supported on all target architectures.3.cc.z4. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc.cc Syntax Integer Arithmetic Instructions: sub.z1. x2.z1.s32 }.type = { . if . Supported on all target architectures.cc. subc{.y4.s32 }. with borrow-out. .b32 subc. b.b32 subc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.b32 x1.z3. a. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.cc. x2. x3.CF).(b + CC. x3.3. . Behavior is the same for unsigned and signed integers. No saturation.y1.type d.

.x.wide}. and either the upper or lower half of the result is written to the destination register.fxs.y. then d is twice as wide as a and b to receive the full result of the multiplication.type d. 2010 67 .fxs.0>. .hi variant // for . mul. t = a * b. Supported on all target architectures.and 32-bit integer types. . b. mul. . If .u16.lo is specified.type = { .s16 fa.lo. creates 64 bit result January 24.u64. save only the low 16 bits // 32*32 bits.hi or .wide.s16 fa. mul{.fys.Chapter 8.lo. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.s32. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s16. If . a. // 16*16 bits yields 32 bits // 16*16 bits. d = t<2n-1. // for . d = t. n = bitwidth of type. .wide // for .n>.. d = t<n-1.s64 }.wide.wide suffix is supported only for 16. then d is the same size as a and b.0.wide is specified.hi..u32. Description Semantics Compute the product of two values.s32 z.. The . . Instruction Set Table 28. mul.lo variant Notes The type of the operation represents the types of the a and b operands.fys.

then d and c are the same size as a and b. mad. a. @p mad.sat limits result to MININT.u64.lo is specified. 2010 . b. Supported on all target architectures.. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value..n> + c.sat. 68 January 24.lo. and then writes the resulting value into a destination register. . . t + c.p.wide}.type mad.u16.s32 type in .and 32-bit integer types.wide // for . Description Semantics Multiplies two values and adds a third. If .s32 d. . d...s64 }.0 Table 29.lo. and either the upper or lower half of the result is written to the destination register. t n d d d = = = = = a * b.c.s32.a.wide suffix is supported only for 16.r. c. If . // for . . b.wide is specified. then d and c are twice as wide as a and b to receive the result of the multiplication.hi.s16. t<2n-1. . bitwidth of type.MAXINT (no overflow) for the size of the operation.s32 r. ..b. a.0> + c.lo variant Notes The type of the operation represents the types of the a and b operands. t<n-1.q.type = { .hi or .hi mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32 d.hi variant // for . The . Saturation modifier: .PTX ISA Version 2.u32.lo. mad{.0. c.hi. Applies only to .

mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.lo. a.b. mul24.s32 d. mul24.u32.type d.16>. d = t<47.a. All operands are of the same type and size. i.lo}. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.hi may be less efficient on machines without hardware support for 24-bit multiply. 2010 69 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. January 24.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. and return either the high or low 32-bits of the 48-bit result.hi variant // for .. Supported on all target architectures.type = { . // low 32-bits of 24x24-bit signed multiply.0.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.0>. // for ..hi. t = a * b. .e. Instruction Set Table 30. mul24{. . d = t<31.. mul24. mul24.s32 }. b.Chapter 8. 48bits.

s32 d. a. // low 32-bits of 24x24-bit signed multiply.type = { .0 Table 31. d = t<31. 2010 .hi.hi.hi variant // for . Saturation modifier: . 48bits. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..e. . b. 70 January 24. d = t<47. i..16> + c. mad24.lo. All operands are of the same type and size.MAXINT (no overflow). a. mad24. mad24. mad24.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. 32-bit value to either the high or low 32-bits of the 48-bit result.hi may be less efficient on machines without hardware support for 24-bit multiply.sat. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. and add a third. c.PTX ISA Version 2. // for .u32.a. b.hi mode.lo}. Description Compute the product of two 24-bit integer values held in 32-bit source registers.c. t = a * b. d.type mad24.0> + c. Applies only to .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. Return either the high or low 32-bits of the 48-bit result.s32 type in .0. Supported on all target architectures.s32 }..s32 d.. c. .b. mad24{.sat limits result of 32-bit signed addition to MININT.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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popc. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. a.b64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b64 }. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.PTX ISA Version 2.u32 Semantics 74 January 24. a. while (a != 0) { if (a&0x1) d++.0 Table 39.type == . a. // cnt is . a. a = a >> 1. } Introduced in PTX ISA version 2. popc. X. clz requires sm_20 or later. . a = a << 1. cnt. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. .b64 type.b64 d.0. popc Syntax Integer Arithmetic Instructions: popc Population count.u32 PTX ISA Notes Target ISA Notes Examples Table 40. popc requires sm_20 or later.type = { .0. inclusively.b64 d. For . // cnt is . X.b32 popc. if (. cnt. For . .type = { . } else { max = 64.b32) { max = 32. 2010 . inclusively. mask = 0x80000000. the number of leading zeros is between 0 and 32.b32 clz.b32. d = 0. clz.b32. clz. } while (d < max && (a&mask == 0) ) { d++.type d.b32 type. the number of leading zeros is between 0 and 64. mask = 0x8000000000000000.type d. d = 0. .

s32) ? 31 : 63. For signed integers. bfind requires sm_20 or later. X. 2010 75 .shiftamt && d != -1) { d = msb . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==. Semantics msb = (. and operand d has type . d = -1. .d.u32 January 24. . bfind returns 0xFFFFFFFF if no non-sign bit is found. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.u32. i--) { if (a & (1<<i)) { d = i. // cnt is .type d. Operand a has the instruction type.u64.shiftamt. Instruction Set Table 41. d. . bfind returns the bit position of the most significant “1”. a. bfind.s64 }.shiftamt.u32. } } if (.type = { . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.shiftamt is specified. bfind. For unsigned integers.s64 cnt.Chapter 8.u32 d. for (i=msb. a.u32 || . bfind. break. Description Find the bit position of the most significant non-sign bit in a and place the result in d.type bfind. .s32.type==.0. i>=0. a. If .

b32. a. .type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 . for (i=0. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.type = { .PTX ISA Version 2. brev requires sm_20 or later. brev.b32) ? 31 : 63. . Description Semantics Perform bitwise reversal of input.b64 }. a. i<=msb.type d. msb = (. brev.b32 d.0.0 Table 42. i++) { d[i] = a[msb-i]. 76 January 24.

len. if (. b.s32) ? 31 : 63.s32.s32. d = 0.u32. and operands b and c are type .Chapter 8.u64 || len==0) sbit = 0.msb)]. len = c. . .type = { . bfe. January 24. else sbit = a[min(pos+len-1. a.type==.u32. Semantics msb = (.u64: . .u32 || . . bfe.u32 || .type==. pos = b.type==.b32 d. Instruction Set Table 43.0.u32. Source b gives the bit field starting bit position. . c. and source c gives the bit field length in bits. Description Extract bit field from a and place the zero or sign-extended result in d.type==. If the start position is beyond the msb of the input. Operands a and d have the same type as the instruction type. . The destination d is padded with the sign bit of the extracted field. otherwise If the bit field length is zero. bfe requires sm_20 or later. 2010 77 .s64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the destination d is filled with the replicated sign bit of the extracted field.a. The sign bit of the extracted field is defined as: . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. for (i=0.start.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.u64. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.type d. i<=msb. the result is zero.

f = b. If the start position is beyond the msb of the input.b64 }.b32 d. len = d. .b32. If the bit field length is zero. b. and f have the same type as the instruction type. 78 January 24. . bfi requires sm_20 or later. Operands a. Description Align and insert a bit field from a into b. bfi.u32.PTX ISA Version 2. for (i=0. i++) { f[pos+i] = a[i]. b. and place the result in f. i<len && pos+i<=msb. and source d gives the bit field length in bits.start.b32) ? 31 : 63.len.b.a.type f. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. d. the result is b. pos = c. Semantics msb = (. a.type==. and operands c and d are type .type = { . c. 2010 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Source c gives the starting bit position for the insertion.0 Table 44. the result is b. bfi.0.

.mode} d. Note that the sign extension is only performed as part of generic form. . {b3. Instruction Set Table 45. the four 4-bit values fully specify an arbitrary byte permute. and reassemble them into a 32-bit destination register. b0}}. Thus. b1. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. For each byte in the target register. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. the permute control consists of four 4-bit selection values. b6.b1 source select c[7:4] d. default mode index d.b4e. . c. b. b4}. The bytes in the two source registers are numbered from 0 to 7: {b. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.rc16 }. In the generic form (no mode specified).b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. a.ecl. .b32{. as a 16b permute code. b5.rc8.b2 source select c[11:8] d.ecr. . The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. Description Pick four arbitrary bytes from two 32-bit registers.Chapter 8. 2010 79 . a} = {{b7.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.mode = { . .f4e. b2.b3 source select c[15:12] d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. prmt. a 4-bit selection value is defined. msb=0 means copy the literal value. The msb defines if the byte value should be copied. msb=1 means replicate the sign.

tmp[15:08] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 . r3.PTX ISA Version 2. ctl[2] = (c >> 8) & 0xf. r4. tmp64 ). tmp[23:16] = ReadByte( mode. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r2.b32. } tmp[07:00] = ReadByte( mode. ctl[2]. ctl[0]. tmp64 ). tmp[31:24] = ReadByte( mode. r2.0. prmt.0 Semantics tmp64 = (b<<32) | a. r1. prmt requires sm_20 or later. ctl[3]. ctl[1]. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ). r4. ctl[1] = (c >> 4) & 0xf. tmp64 ). r3.f4e r1.b32 prmt. 80 January 24. ctl[3] = (c >> 12) & 0xf.

The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on .Chapter 8. Instruction Set 8. 2010 81 .2.7.f32 and .

target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. sub.rn .f32 rsqrt.min.f64 rsqrt. and mad support saturation of results to the range [0.PTX ISA Version 2.rcp.sqrt}.rcp.fma}.min.sqrt}.rn and instructions may be folded into a multiply-add. Table 46.rm .rnd.approx. If no rounding modifier is specified. .rz .approx. The optional . but single-precision instructions return an unspecified NaN.rnd.f32 {abs. NaN payloads are supported for double-precision instructions. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f64 mad.sub.mul}. mul.max}. default is .approx.rnd.rnd.f32 are the same. default is .cos.neg.max}.rnd. Single-precision add.f32 {mad.ftz .rcp.f32 {add. Note that future implementations may support NaN payloads for single-precision instructions.ex2}.sqrt}.target sm_1x No rounding modifier. .sat Notes If no rounding modifier is specified. so PTX programs should not rely on the specific single-precision NaNs being generated.f64 and fma.f32 {div.approx.rnd.rn and instructions may be folded into a multiply-add. No rounding modifier. with NaNs being flushed to positive zero.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. {add. 1.f64 are the same.f64 div.rp .f32 .32 and fma.f64 {abs.f64 {sin.f32 {div. 2010 .target sm_20 .target sm_20 mad.fma}. {mad.0.sub.neg.mul}.f32 {div.lg2.0]. 82 January 24.0 The following table summarizes floating-point instructions in PTX. Double-precision instructions support subnormal inputs and results. Instruction Summary of Floating-Point Instructions .full.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.

copysign requires sm_20 or later.f64 }. . z. copysign.type . not infinity).op p. copysign.type d.notanumber testp. and return the result as d.op.type = { .number testp.0. .Chapter 8.number. // result is .f64 isnan.finite. testp Syntax Floating-Point Instructions: testp Test floating-point property. . . testp. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Table 48. . January 24. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.notanumber.normal testp. .0. not infinity) As a special case. A.f32. Introduced in PTX ISA version 2.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. testp requires sm_20 or later. b. testp. f0. p.type = { . true if the input is a subnormal number (not NaN.infinite testp. testp. y.infinite. Instruction Set Table 47.pred = { . .f32 testp. C. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. X. .notanumber. 2010 83 . B.f32. a.f64 }.infinite.finite testp.f32 copysign. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.subnormal }. .f64 x.normal. positive and negative zero are considered normal numbers.

add.0. 2010 . Description Semantics Notes Performs addition and writes the resulting value into a destination register.rm. Rounding modifiers have the following target requirements: .f32 f1. NaN results are flushed to +0. add.rm.f2. . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 requires sm_13 or later. .rp }.rz available for all targets .rz. . Rounding modifiers (default is . d.rnd}. d = a + b. Saturation modifier: . add.rnd}{.0f.ftz}{.rn. add{. subnormal numbers are supported. a. b.ftz. sm_1x: add.f64 supports subnormal numbers.rp for add. requires sm_13 for add.f32 flushes subnormal inputs and results to sign-preserving zero. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. add.rz mantissa LSB rounds towards zero .f32 clamps the result to [0. add Syntax Floating-Point Instructions: add Add two values.rn.0.f3. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. add. b.0].rn): . .f32 add{.f32 supported on all target architectures.rnd = { .PTX ISA Version 2. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. . 84 January 24.rz.ftz.sat}. In particular.sat.0 Table 49.f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_20 Examples @p add.f32. a.rm mantissa LSB rounds towards negative infinity . .f64 d.rn mantissa LSB rounds to nearest even .f64.

. sub.f32 f1.f64 requires sm_13 or later.rp }. 1.f64. sub.f2. b.f32.b.rn mantissa LSB rounds to nearest even .0f. . sub Syntax Floating-Point Instructions: sub Subtract one value from another. . requires sm_20 Examples sub. sub. Rounding modifiers (default is .a.0].sat}.rn.ftz}{.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. NaN results are flushed to +0.rp for sub.f3.f32 c.f64 d. sm_1x: sub. a.rz available for all targets . .sat.rm. Rounding modifiers have the following target requirements: .0.0. subnormal numbers are supported.rnd}. d = a .f64 supports subnormal numbers. .f32 sub{. Saturation modifier: sub. In particular.rnd = { . requires sm_13 for sub.b. Instruction Set Table 50. sub. sub{. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero . sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rn. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. b.rz. 2010 85 . January 24.rn): .f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 clamps the result to [0.f32 supported on all target architectures.rn.rm mantissa LSB rounds towards negative infinity . d. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 flushes subnormal inputs and results to sign-preserving zero.rm. .Chapter 8.ftz.rnd}{.

rz. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rn mantissa LSB rounds to nearest even . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rm.f32.rz available for all targets . NaN results are flushed to +0. b. b. requires sm_20 Examples mul. 2010 . Description Semantics Notes Compute the product of two values. a. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64 requires sm_13 or later. sm_1x: mul. requires sm_13 for mul.f64 d. all operands must be the same size.f32 clamps the result to [0.0].pi // a single-precision multiply 86 January 24. Rounding modifiers (default is .f32 mul{. d = a * b.rn. d. a. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64. subnormal numbers are supported.rnd}.ftz.0 Table 51.f32 circumf.rm mantissa LSB rounds towards negative infinity .rp for mul. . For floating-point multiplication.radius. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. .rp }.sat}. mul.sat. mul Syntax Floating-Point Instructions: mul Multiply two values.rn. Rounding modifiers have the following target requirements: .f64 supports subnormal numbers. mul.ftz.0.PTX ISA Version 2. .f32 flushes subnormal inputs and results to sign-preserving zero. 1.0. mul.rm.rz mantissa LSB rounds towards zero .rn): .ftz}{. In particular. mul{. mul.0f.rnd}{.rnd = { . . .f32 flushes subnormal inputs and results to sign-preserving zero. Saturation modifier: mul.f32 supported on all target architectures.

rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. PTX ISA Notes Target ISA Notes Examples January 24.f64 w.rn mantissa LSB rounds to nearest even .f32 is unimplemented in sm_1x.0]. a. fma.rnd.b.f32 fma. d.rm.0.f32 clamps the result to [0.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz. Instruction Set Table 52.rz.rnd{. . fma.a. fma. The resulting value is then rounded to double precision using the rounding mode specified by . @p fma. fma.f64 requires sm_13 or later.c. again in infinite precision. d = a*b + c. NaN results are flushed to +0. The resulting value is then rounded to single precision using the rounding mode specified by . 1.sat.rm mantissa LSB rounds towards negative infinity . fma Syntax Floating-Point Instructions: fma Fused multiply-add.sat}.f32 computes the product of a and b to infinite precision and then adds c to this product.f64 is the same as mad.f32 requires sm_20 or later. .f64 introduced in PTX ISA version 1. a.f32 fma.0f. Rounding modifiers (no default): . b. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. fma. subnormal numbers are supported. c. fma.rnd. fma. b. c.f64 supports subnormal numbers. Saturation: fma.rp }. .z. d.rn. sm_1x: fma.0.rn.f32 introduced in PTX ISA version 2.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 87 . .f64 d. fma.rz mantissa LSB rounds towards zero .ftz. again in infinite precision.rnd = { .4.x.Chapter 8.ftz}{.rn.y.f64. fma.rnd. fma.

sat. 2010 .0f.rz mantissa LSB rounds towards zero .ftz.target sm_20 d. 1.target sm_1x d.rnd{. a. Description Semantics Notes Multiplies two values and adds a third. mad. a. NaN results are flushed to +0. b. b.f64 d. .rm mantissa LSB rounds towards negative infinity . In this case.rnd. // . // . The resulting value is then rounded to single precision using the rounding mode specified by .rz.f32). mad. Saturation modifier: mad.rnd = { .0.0 devices.sat}.target sm_13 and later .f32 computes the product of a and b at double precision.rnd. Note that this is different from computing the product with mul.0.f64}.f32 flushes subnormal inputs and results to sign-preserving zero. c. mad.rn mantissa LSB rounds to nearest even . but the exponent is preserved.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. and then writes the resulting value into a destination register.rnd.rn. . mad.f32 is when c = +/-0.rm.f64 is the same as fma.PTX ISA Version 2. mad. mad.sat}. mad{.ftz}{.f32 clamps the result to [0.ftz. mad.{f32. where the mantissa can be rounded and the exponent will be clamped.f64 computes the product of a and b to infinite precision and then adds c to this product. again in infinite precision. the treatment of subnormal inputs and output follows IEEE 754 standard. sm_1x: mad. For . mad. again in infinite precision. fma. When JIT-compiled for SM 2.f64} is the same as fma.. 88 January 24.f32 is identical to the result computed using separate mul and add instructions. .ftz}{.rn. a. Rounding modifiers (no default): .rp }. and then the mantissa is truncated to 23 bits. The resulting value is then rounded to double precision using the rounding mode specified by .f64.0].e.f32 mad.f64 supports subnormal numbers. c. Unlike mad. mad.f32 mad.rnd. // . b.f32. The resulting value is then rounded to double precision using the rounding mode specified by .0 Table 53.target sm_20: mad.target sm_1x: mad. subnormal numbers are supported. The exception for mad. c.{f32. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. again in infinite precision.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. For . d = a*b + c.f32 is implemented as a fused multiply-add (i.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero.

Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rz.f32. Rounding modifiers have the following target requirements: .f64. In PTX ISA versions 1.f64 requires sm_13 or later. a rounding modifier is required for mad.rn.0. Legacy mad.f64 instructions having no rounding modifier will map to mad.rz.0 and later...a.rn. In PTX ISA versions 2. a rounding modifier is required for mad.rp for mad. requires sm_20 Examples @p mad.c. 2010 89 . January 24.rm. requires sm_13 .. mad..4 and later.rm.rn.f32 d.f64.f64..b.Chapter 8..f32 for sm_20 targets.rp for mad.f32 supported on all target architectures. Target ISA Notes mad.

d.f32 supported on all target architectures. Description Semantics Notes Divides a by b.rnd = { .4 and later. Subnormal inputs and results are flushed to sign-preserving zero. and rounding introduced in PTX ISA version 1.f32. . a.0 through 1.f32 div.f32 div. div.full.ftz}. approximate division by zero creates a value of infinity (with same sign as a). Explicit modifiers .ftz.{rz. // // // // fast. a.rn.f32 div.ftz}.f64 introduced in PTX ISA version 1.3.rn mantissa LSB rounds to nearest even . or . d.approx. For PTX ISA versions 1. For b in [2-126.f32 requires sm_20 or later. subnormal numbers are supported.ftz}. div.approx.f32 defaults to div.rnd. div.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero.circum.f32 div.ftz.f64 d. d = a / b.approx.f32 implements a fast approximation to divide.f32 flushes subnormal inputs and results to sign-preserving zero. xd. 2126].0.rz.14159.rnd.rn.f32 div.full. .PTX ISA Version 2.approx{.rm.f32 and div.full. . stores result in d. Fast. Examples 90 January 24.full. full-range approximation that scales operands to achieve better accuracy.ftz. PTX ISA Notes div. .full. x. one of .rp}.4. z.rn.0 Table 54.rm mantissa LSB rounds towards negative infinity . yd. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . a. zd. computed as d = a * (1/b). b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b.f32 implements a relatively fast.rnd is required.f64 requires sm_20 or later. but is not fully IEEE 754 compliant and does not support rounding modifiers.approx. Fast.f64.f32 and div. div.f64 defaults to div. 2010 .rp }.rz mantissa LSB rounds towards zero .3. div Syntax Floating-Point Instructions: div Divide one value by another. For PTX ISA version 1. div.full{. Target ISA Notes div.rm. sm_1x: div. div. d. The maximum ulp error is 2 across the full range of inputs.approx. div. .ftz.rnd{. div. and div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .ftz.f64 supports subnormal numbers.approx.rn. b. a.f64 diam. the maximum ulp error is 2. approximate single-precision divides: div. . b. y. div.

subnormal numbers are supported. abs{. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.ftz.ftz.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. January 24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 supported on all target architectures. abs.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg. neg{. Instruction Set Table 55.f64 requires sm_13 or later.f32 x.f0. d = -a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 requires sm_13 or later. a. a. abs. Subnormal numbers: sm_20: By default.ftz}. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 abs. abs.f64 supports subnormal numbers.f64 d. a. neg. neg. abs.Chapter 8.0. NaN inputs yield an unspecified NaN. neg. d. NaN inputs yield an unspecified NaN.f0.f32 supported on all target architectures. 2010 91 .0. a. Negate the sign of a and store the result in d. Table 56. Subnormal numbers: sm_20: By default. d = |a|. neg. d.f32 neg. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. sm_1x: abs. Take the absolute value of a and store the result in d. abs.ftz}. sm_1x: neg.f32 x. subnormal numbers are supported.f64 d.

f32 min.ftz}.b.f32 flushes subnormal inputs and results to sign-preserving zero.c.f64 d. @p min.b.PTX ISA Version 2. max{.f64 supports subnormal numbers. b. max. max.0.f32 flushes subnormal inputs and results to sign-preserving zero. d. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.f32 flushes subnormal inputs and results to sign-preserving zero. a.ftz}.ftz. b. subnormal numbers are supported.f64 requires sm_13 or later. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. d d d d = = = = NaN.f1. a. d d d d = = = = NaN.f32 supported on all target architectures.f32 supported on all target architectures.x. b. a. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. sm_1x: max. max. min.f32 flushes subnormal inputs and results to sign-preserving zero. 92 January 24. min.f64 d. (a < b) ? a : b.f32 max. Store the minimum of a and b in d.c. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.ftz. Store the maximum of a and b in d. b.f64 requires sm_13 or later. (a > b) ? a : b. min.f2.ftz. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. b. d. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. max.f64 z.f32 max. subnormal numbers are supported. a. Table 58. 2010 . sm_1x: min. a.z.0.f32 min.ftz. a. max.0 Table 57.f64 f0.f64 supports subnormal numbers. min{. min.

0.ftz.f32.0 over the range 1.3. .f32 flushes subnormal inputs and results to sign-preserving zero.x.rm mantissa LSB rounds towards negative infinity .ftz}.ftz. .0 through 1. Instruction Set Table 59.f64 requires sm_20 or later.f32 rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.Chapter 8. The maximum absolute error is 2-23.f64 introduced in PTX ISA version 1.rn.rn.approx or .f32 supported on all target architectures.f32 rcp.f32 requires sm_20 or later. rcp.approx. subnormal numbers are supported. Target ISA Notes rcp.f64 supports subnormal numbers.f64.approx.approx{.f64 ri. 2010 93 . // fast.ftz.f32 and rcp.rnd.rn mantissa LSB rounds to nearest even .rnd is required.rm. rcp. Description Semantics Notes Compute 1/a. a. a. For PTX ISA versions 1.0.0. rcp. xi.4 and later.rnd{.rn.f32 rcp.0 +subnormal +Inf NaN Result -0. Input -Inf -subnormal -0.rm.x.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 rcp.rp}.0-2. and rcp.f64 defaults to rcp.rnd.rz.0 +0.f32 defaults to rcp.f32 implements a fast approximation to reciprocal.rnd = { .rn. rcp. .approx and . rcp.f64 requires sm_13 or later. Examples January 24.4.rn. store result in d. one of . approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .ftz.0 -Inf -Inf +Inf +Inf +0. rcp.{rz.approx. rcp. xi.f64 and explicit modifiers . rcp.rn.approx. d.f32 flushes subnormal inputs and results to sign-preserving zero. d. General rounding modifiers were added in PTX ISA version 2.f64 d.rp }. PTX ISA Notes rcp. For PTX ISA version 1. sm_1x: rcp. a. rcp.rz mantissa LSB rounds towards zero .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .ftz}.r.ftz were introduced in PTX ISA version 1. rcp. d = 1 / a.

4 and later.rm.f32 requires sm_20 or later.ftz.0 +0.f64 d.approx.0 Table 60.f32 implements a fast approximation to square root. store in d.0. sqrt.f64 supports subnormal numbers.f32 and sqrt. one of .rn mantissa LSB rounds to nearest even .rn.rm. // IEEE 754 compliant rounding .f64 requires sm_13 or later.rn. For PTX ISA versions 1.f64 defaults to sqrt. // IEEE 754 compliant rounding d.x. sqrt. approximate square root d.ftz. // fast.x.approx{.ftz.ftz}.{rz. sqrt.rn.rm mantissa LSB rounds towards negative infinity .ftz. PTX ISA Notes sqrt. .approx or . r. sqrt.ftz were introduced in PTX ISA version 1.rnd is required.PTX ISA Version 2.rnd{.f32 sqrt.f32 defaults to sqrt.rp}.3. d = sqrt(a).f64 and explicit modifiers . Examples 94 January 24.0 +0.0 -0.f64 introduced in PTX ISA version 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32. r. sqrt. sm_1x: sqrt. Description Semantics Notes Compute sqrt(a). sqrt.4.approx.approx.f64 r.approx. For PTX ISA version 1.rnd = { .f32 sqrt.f32 sqrt. General rounding modifiers were added in PTX ISA version 2. .f64 requires sm_20 or later. sqrt.0 through 1.rn. subnormal numbers are supported.f32 is TBD.rnd.rnd.rz. 2010 .x.approx and .0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .0.rn.ftz}. Target ISA Notes sqrt.0 +0.rz mantissa LSB rounds towards zero . a.f32 sqrt. and sqrt.approx. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt.rn. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. a.f32 flushes subnormal inputs and results to sign-preserving zero. a.0 +subnormal +Inf NaN Result NaN NaN -0.f32 supported on all target architectures. Input -Inf -normal -subnormal -0.f64. . sqrt.rp }. The maximum absolute error for sqrt.

approx.0-4. Compute 1/sqrt(a). rsqrt. Note that rsqrt.f32 defaults to rsqrt. a.4 over the range 1. PTX ISA Notes rsqrt.0 NaN The maximum absolute error for rsqrt.f32 is 2-22.f32 flushes subnormal inputs and results to sign-preserving zero.3. rsqrt.ftz}.4. Instruction Set Table 61.f64 is TBD.0 +0.f64 isr.4 and later. rsqrt.f64. the . For PTX ISA version 1.ftz. 2010 95 . subnormal numbers are supported. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f64 is emulated in software and are relatively slow.f64 defaults to rsqrt. Explicit modifiers .f64 supports subnormal numbers. Input -Inf -normal -subnormal -0.f32 and rsqrt.f32.0 through 1.approx{. sm_1x: rsqrt.f32 rsqrt.approx. January 24. X. and rsqrt. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f64 requires sm_13 or later.f64 were introduced in PTX ISA version 1. store the result in d.approx. rsqrt. x. Target ISA Notes Examples rsqrt. rsqrt.ftz. rsqrt.approx.f32 rsqrt.f32 supported on all target architectures.approx.ftz were introduced in PTX ISA version 1.approx.approx and .approx implements an approximation to the reciprocal square root. Subnormal numbers: sm_20: By default. ISR.0. d = 1/sqrt(a).f64 d. a.ftz.approx modifier is required. For PTX ISA versions 1.Chapter 8.0. d. The maximum absolute error for rsqrt.

d = sin(a).0 +0.0 NaN NaN The maximum absolute error is 2-20.f32 flushes subnormal inputs and results to sign-preserving zero.f32.0 -0.f32 sa.0 +subnormal +Inf NaN Result NaN -0. Find the sine of the angle a (in radians).ftz introduced in PTX ISA version 1.ftz}.f32 introduced in PTX ISA version 1. 2010 . Explicit modifiers . For PTX ISA versions 1.ftz.f32 defaults to sin.ftz. sin. subnormal numbers are supported. Input -Inf -subnormal -0. a. the . PTX ISA Notes sin.f32 d.3.approx.ftz.0 +0. 96 January 24. sin. sin. sin.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero.0. sin.f32 implements a fast approximation to sine.approx and .approx.PTX ISA Version 2. For PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures.9 in quadrant 00.approx. a.0 through 1.approx{.4.0 +0. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.4 and later.0 Table 62. Subnormal numbers: sm_20: By default.

a.approx. cos. For PTX ISA version 1.0 +1.ftz.f32 d. a.approx{.f32 defaults to cos.f32 ca. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes cos. Input -Inf -subnormal -0.Chapter 8.ftz. Target ISA Notes Examples Supported on all target architectures.ftz introduced in PTX ISA version 1.0.0 +subnormal +Inf NaN Result NaN +1.0 NaN NaN The maximum absolute error is 2-20.0 +1. cos. the . subnormal numbers are supported.f32.3.approx modifier is required.f32 implements a fast approximation to cosine. January 24. cos.0 +1.0 +0. For PTX ISA versions 1.4. sm_1x: Subnormal inputs and results to sign-preserving zero. Instruction Set Table 63.approx.9 in quadrant 00.approx.f32 introduced in PTX ISA version 1.ftz. cos. d = cos(a). cos.4 and later.ftz}. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 through 1. 2010 97 .approx and . Find the cosine of the angle a (in radians). Subnormal numbers: sm_20: By default.

approx modifier is required.PTX ISA Version 2.0 +0.approx and . lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. 98 January 24.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.0 Table 64. d = log(a) / log(2).f32 implements a fast approximation to log2(a).ftz introduced in PTX ISA version 1.f32 Determine the log2 of a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. For PTX ISA versions 1.ftz.4 and later. Target ISA Notes Examples Supported on all target architectures.6 for mantissa.ftz. lg2.f32 introduced in PTX ISA version 1. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero.3. a. The maximum absolute error is 2-22. lg2. PTX ISA Notes lg2.4.0. For PTX ISA version 1. lg2.0 through 1. Subnormal numbers: sm_20: By default. a.approx.ftz}. the .f32 la.f32.f32 defaults to lg2. subnormal numbers are supported.approx{.approx. lg2. 2010 . lg2. Input -Inf -subnormal -0.approx.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

a. If both operands are numeric values (not NaN).b64. .ftz applies only to . neu.dtype.u64. 102 January 24. gt. num returns true if both operands are numeric values (not NaN).BoolOp{. p[|q].i. Modifier . or.f32 flushes subnormal inputs to sign-preserving zero.b32. p. c). gtu. setp with . le. lt. ge. bit-size comparisons are eq and ne. . le.type .CmpOp. ne. hi.ftz. . {!}c. the result is false. and nan returns true if either operand is NaN. loweror-same. higher.B) is one of: and.a. To aid comparison operations in the presence of NaN values. .n. c).f32.f32 flushes subnormal inputs to sign-preserving zero.dtype.0. hs equ.s32 setp. leu.s64. lt.PTX ISA Version 2. .u32 p|q. lt.b. If either operand is NaN.dtype. subnormal numbers are supported. sm_1x: setp. neu. unordered versions are included: equ. . The comparison operator is a suffix on the instruction. gt.s32. geu. setp. setp. ge.0 Table 67. a.ftz}. ne. A related value computed using the complement of the compare result is written to the second destination operand. . ls. The untyped. num.f32 comparisons. then these comparisons have the same result as their ordered counterparts. b. p = BoolOp(t. the comparison operators lo. lo. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. and higher-or-same may be used instead of lt. p[|q].u32. and can be one of: eq.type = { .type setp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. geu. hi.s16. ge. ne. le. Subnormal numbers: sm_20: By default. If either operand is NaN. 2010 . This result is written to the first destination operand. The destinations p and q must be . respectively. .CmpOp{. ltu.pred variables. gt.u16.f64 source type requires sm_13 or later. b.f64 }. ltu. leu. Semantics t = (a CmpOp b) ? 1 : 0.ftz}. Applies to all numeric types.r. le. @q setp.b16. . ls. .eq. ge. The signed and unsigned comparison operators are eq. For unsigned values. gt.and. q = BoolOp(!t. then the result of these comparisons is true. nan The Boolean operator BoolOp(A. gtu.f64 supports subnormal numbers. and hs for lower. and (optionally) combine this result with a predicate value by applying a Boolean operator.lt. xor. Integer Notes Floating Point Notes The ordered comparisons are eq. setp.

Introduced in PTX ISA version 1. Modifier . and b are treated as a bitsize type of the same width as the first instruction type.b32.dtype. and b must be of the same type.f32 A.dtype. f0. slct.f32 d.s32. . For . . .s64. .u32.f32 flushes subnormal values of operand c to sign-preserving zero.dtype = { .f32.b64.u16.f32 comparisons. negative zero equals zero.ftz applies only to . c. . slct. c. and operand a is selected. .b16. a.f32 r0. a.Chapter 8. If c ≥ 0.b64.f64 }.0. otherwise b is stored in d. selp. a. Operands d.b16.p. y. C. The selected input is copied to the output without modification. . . a. a is stored in d.s16.u32. slct Syntax Comparison and Selection Instructions: slct Select one source operand. Operand c is a predicate. d = (c == 1) ? a : b.g.u64. b. .x. Semantics Floating Point Notes January 24.u16.0. Operands d. . slct. sm_1x: slct. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. . b. . based on the sign of the third operand. c. If c is True.s32 slct{. Table 69. b.u64.b32. . .f64 requires sm_13 or later. and operand a is selected. based on the value of the predicate source operand.type = { .type d.s32. . z. Description Conditional selection.xp. Instruction Set Table 68. 2010 103 .s64. slct. b otherwise. the comparison is unordered and operand b is selected. .f32 flushes subnormal values of operand c to sign-preserving zero. a is stored in d.u32.f64 }. d. selp. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz.f64 requires sm_13 or later. @q selp. val. . . slct.ftz}.ftz.t. If operand c is NaN.dtype. subnormal numbers are supported. . fval. operand c must match the second instruction type. selp Syntax Comparison and Selection Instructions: selp Select between source operands.s32 x. a.f32 comparisons.r.dtype.f32.u64. . . d = (c >= 0) ? a : b. B.s16. Subnormal numbers: sm_20: By default.s32 selp.

or. This permits bit-wise operations on floating point values without having to define a union to access the bits.4. provided the operands are of the same size. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.7.0 8. Instructions and. 2010 . performing bit-wise operations on operands of any type.PTX ISA Version 2. and not also operate on predicates. xor. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.

or.b32.b64 }. Introduced in PTX ISA version 1. Table 71.b16. Supported on all target architectures. .0x00010001 or.pred.b64 }. . and. . Supported on all target architectures. Instruction Set Table 70. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type d.q. sign.b32.type d.b16. .r. but not necessarily the type.type = { . d = a | b. b. .fpvalue. 2010 105 . and. The size of the operands must match. The size of the operands must match.type = { .0. a. d = a & b. b.b32 x. . and Syntax Logic and Shift Instructions: and Bitwise AND.pred. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. or. . Allowed types include predicate registers. but not necessarily the type. Allowed types include predicate registers.r. Introduced in PTX ISA version 1.b32 mask mask.0x80000000.b32 and.Chapter 8.pred p.0.q. or Syntax Logic and Shift Instructions: or Bitwise OR. a. January 24.

0 Table 72. xor. Allowed types include predicates. but not necessarily the type. d = (a==0) ? 1 : 0.0.type = { .0.b64 }.a. .q. b.b32 xor.r. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Table 74. The size of the operands must match. Allowed types include predicate registers.pred.b16. a.0x0001. . a.b16.b16 d.b64 }. not.q. d = ~a. not. but not necessarily the type. Supported on all target architectures. cnot.b32. not. . xor.type = { . . 106 January 24. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. d.b32 mask. 2010 .type = { .b32 d.0. .b32. not Syntax Logic and Shift Instructions: not Bitwise negation. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.type d. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. .type d.pred p.type d. .b32. Introduced in PTX ISA version 1. Table 73. .PTX ISA Version 2. The size of the operands must match. a. but not necessarily the type. .b16. The size of the operands must match.mask. . cnot. d = a ^ b.x. Supported on all target architectures. one’s complement.pred. Supported on all target architectures.b64 }. Introduced in PTX ISA version 1.

2. .0. . 2010 107 . unsigned and untyped shifts fill with 0. shr.1.s64 }. zero-fill on right. . .b16.b32 q.s32. . regardless of the instruction type.u16 shr.0.b16.j. Supported on all target architectures. shl Syntax Logic and Shift Instructions: shl Shift bits left. shl. PTX ISA Notes Target ISA Notes Examples January 24. The sizes of the destination and first source operand must match. The sizes of the destination and first source operand must match. .type = { . Bit-size types are included for symmetry with SHL. .u64.type d.b16 c. shl. The b operand must be a 32-bit value.a.u16. but not necessarily the type. d = a >> b. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. b. Shift amounts greater than the register width N are clamped to N. sign or zero fill on left. . Signed shifts fill with the sign bit.s32 shr.u32. . Instruction Set Table 75. regardless of the instruction type.b64 }. but not necessarily the type. Introduced in PTX ISA version 1. . shr Syntax Logic and Shift Instructions: shr Shift bits right. PTX ISA Notes Target ISA Notes Examples Table 76. Supported on all target architectures. shr.b32.b32. i.i. a.Chapter 8.b64.a.i.type = { . The b operand must be a 32-bit value.type d. b.s16. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.2. k. Introduced in PTX ISA version 1. a. . . d = a << b. Shift amounts greater than the register width N are clamped to N.

or shared state spaces. local. ldu.7. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. Instructions ld. and sust support optional cache operations. and from state space to state space. and st operate on both scalar and vector types. mov. possibly converting it from one format to another.0 8. Data Movement and Conversion Instructions These instructions copy data from place to place. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.5. prefetchu isspacep cvta cvt 108 January 24. 2010 . suld. The cvta instruction converts addresses between generic and global. st. ld.PTX ISA Version 2.

Chapter 8.lu operation. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. When ld. For sm_20 and later. The ld. if the line is fully covered.cg Cache at global level (cache in L2 and below.cs is applied to a Local window address. likely to be accessed again.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. likely to be accessed once. and a second thread loads that address via a second L1 cache with ld. bypassing the L1 cache. The ld. As a result of this request. fetch again).1. The ld. The ld. rather than the data stored by the first thread. and cache only in the L2 cache. The default load instruction cache operation is ld.lu load last use operation.5.cv Cache as volatile (consider cached system memory lines stale. not L1). invalidates (discards) the local L1 line following the load. .7. when applied to a local address. Operator . evict-first. to allow the thread program to poll a SysMem location written by the CPU. any existing cache lines that match the requested address in L1 will be evicted. Cache Operators PTX 2.ca loads cached in L1. The cache operators require a target architecture of sm_20 or later. If one thread stores to global memory via one L1 cache.cs Cache streaming.cg to cache loads only globally. .0 introduces optional cache operators on load and store instructions. Table 77. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. it performs the ld. .cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.ca. but multiple L1 caches are not coherent for global data.cs) on global addresses.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. Global data is coherent at the L2 level. the second thread may get stale L1 cache data. Use ld.ca.lu Last use.lu instruction performs a load cached streaming operation (ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. Instruction Set 8. the cache operators have the following definitions and behavior.cv to a frame buffer DRAM address is the same as ld. 2010 109 . . January 24. The compiler / programmer may use ld.cs. A ld.

The st. 110 January 24. and a second thread in a different SM later loads from that address via a different L1 cache with ld. rather than get the data from L2 or memory stored by the first thread.cg Cache at global level (cache in L2 and below.wb could write-back global store data from L1. bypassing the L1 cache.wt Cache write-through (to system memory).cg is the same as st. and cache only in the L2 cache. to allow a CPU program to poll a SysMem location written by the GPU with st. Future GPUs may have globally-coherent L1 caches.ca loads. The default store instruction cache operation is st.0 Table 78. and discard any L1 lines that match. in which case st. the second thread may get a hit on stale L1 cache data. .wb. but st.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. If one thread stores to global memory. not L1). 2010 . Use st.wb for global data.PTX ISA Version 2. st. regardless of the cache operation. bypassing its L1 cache.ca. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. Addresses not in System Memory use normal write-back. and marks local L1 lines evict-first.cg to local memory uses the L1 cache. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. However. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.cs Cache streaming. In sm_20.cg to cache global store data only globally. which writes back cache lines of coherent cache levels with normal eviction policy. .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. Global stores bypass L1. likely to be accessed once.wt. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. . The st. Operator .wt store write-through operation applied to a global System Memory address writes through the L2 cache.

v.shared state spaces.global.u32.. . A. .0.s16.s32.1. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. addr. d.. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. . local. avar. . the generic address of a variable declared in global. mov. ptr. The generic address of a variable in global.e.f64 requires sm_13 or later. mov places the non-generic address of the variable (i. k. mov.u16 mov. or shared state space. a. within the variable’s declared state space Notes Although only predicate and bit-size types are required. sreg. d. d = &avar. d.u16.u32 d.f64 }.f32 mov. For variables declared in .b32.type mov. . . Take the non-generic address of a variable in global. Instruction Set Table 79. myFunc.type d. Semantics d = a. Operand a may be a register.const. i. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. the parameter will be copied onto the stack and the address will be in the local state space.local.f32. label. Description . local.s64. . . .type = { .f32 mov. special register. d = &label. local.Chapter 8. .type mov. // address is non-generic. A[5].a.u32 mov.b16. mov. the address of the variable in its state space) into the destination register. or shared state space may be taken directly using the cvta instruction. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.pred.b64. variable in an addressable memory space. Introduced in PTX ISA version 1. // get address of variable // get address of label or function . ptr.type mov.e. d = sreg. alternately. or function name. and . . Write register d with the value of a. . label. immediate.u32 mov. Note that if the address of a device function parameter is moved to a register. u.u64.0. 2010 111 .

d. or write vector register d with the unpacked values from scalar register a.b16 // pack four 8-bit elements into . a[8.w have type .y } = { a[0.47].u32 x. d. 2010 .15] } // unpack 8-bit elements from .b64 { d.15].b32 %r1..31].7].PTX ISA Version 2.x. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. a[24.31]..y } = { a[0.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.y << 8) d = a.. a[32. d.b32 { d.x | (a. {lo. .y << 16) d = a. For bit-size types.w}.a have type .type d. d..a}..b32 mov.w << 24) d = a..y.x | (a. d.y.0 Table 80.g.15].b32 // pack four 16-bit elements into . %x.type = { .%r1.x. Supported on all target architectures. d.. d. Semantics d = a. mov. lo.w } = { a[0..z << 16) | (a.7]. // // // // a.y << 32) // pack two 8-bit elements into .y << 16) | (a.b. d.y.b64 112 January 24.x.hi are .31] } // unpack 8-bit elements from .{a.. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).63] } // unpack 16-bit elements from .y << 8) | (a..b32 { d. a[48.b32 mov.z << 32) | (a.b64 { d. a[16.u8 // unpack 32-bit elements from .u16 %x is a double.b16.hi}. a[16.b32 // pack two 16-bit elements into .g.15]. Description Write scalar register d with the packed value of vector register a.b64 mov.x | (a. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.b8 r.. mov.b64 // pack two 32-bit elements into . %r1.23].w } = { a[0.w << 48) d = a. a[8.x | (a.x. a[32.. {r.31] } // unpack 16-bit elements from . . a.y } = { a[0.b}..z.b have type .z.z.0.{x.b. .b64 }.x. d.b16 { d.b32. a[16.z.x | (a..y.

cv }. . .Chapter 8.b16. d. This may be used.f64 using cvt.volatile. an integer or bit-size type register reg containing a byte address.b64. . an address maps to global memory unless it falls within the local memory window or the shared memory window.type ld{. ld.type = { .global and . the access may proceed by silently masking off low-order address bits to achieve proper rounding.cg. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.type d. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . and then converted to .type . Description Load register variable d from the location specified by the source address operand a in specified state space.ss}.volatile.type ld. The address size may be either 32-bit or 64-bit. The value loaded is sign-extended to the destination register width for signed integers. . 32-bit).const. . The .f64 }. .0. 2010 113 . Cache operations are not permitted with ld.vec. for example.volatile{. The address must be naturally aligned to a multiple of the access size. . Generic addressing and cache operations introduced in PTX ISA 2. .ss}{.. [a].volatile introduced in PTX ISA version 1. *(a+immOff). . and truncated if the register width exceeds the state space address width for the target architecture. .local.f32.b16. ld introduced in PTX ISA version 1.lu. ld{.u32.1.0. . or the instruction may fault. If an address is not properly aligned.global. the resulting behavior is undefined.e. 32-bit).volatile may be used with . .volatile{.ca. Semantics d d d d = = = = a. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.shared }. . to enforce sequential consistency between threads accessing shared memory.v2.u16.u64. *a. Generic addressing may be used with ld. Instruction Set Table 81.cop = { .cop}. In generic addressing.const space suffix may have an optional bank number to indicate constant banks other than bank zero.cs. PTX ISA Notes January 24.ss}{. .f32 or . an address maps to the corresponding location in local or shared memory. and is zeroextended to the destination register width for unsigned and bit-size types.b8.b32. . d. . . i. ld. Within these windows.reg state space.v4 }. . .s16.param. . [a].ss}. . . Addresses are zero-extended to the specified width as needed.ss = { . *(immAddr). [a]. A destination register wider than the specified type may be used. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. or [immAddr] an immediate absolute byte address (unsigned. [a].vec = { .s8.u8. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.f16 data may be loaded using ld.cop}.e. d. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .vec. perform the load using generic addressing.s64.shared spaces to inhibit optimization of references to volatile memory. If no state space is given.s32. i.

[p]. %r.[240].f16 d.b32 ld.[fs]. x. 2010 .s32 ld.shared.f32.b64 ld. Q.[p+-8]. // negative offset %r.b32 ld.global. // load .f32 ld.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.const[4].b32 ld. // access incomplete array x. // immediate address %r.f64 requires sm_13 or later.local.v4.%r. Cache operations require sm_20 or later. ld. d.[a].local.PTX ISA Version 2. Generic addressing requires sm_20 or later.global.const.b16 cvt.[p+4].0 Target ISA Notes ld.[buffer+64].

only generic addresses that map to global memory are legal.global. and is zeroextended to the destination register width for unsigned and bit-size types.f64 requires sm_13 or later. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f16 data may be loaded using ldu.f64 using cvt. the resulting behavior is undefined. *(immAddr).v4. . A destination register wider than the specified type may be used. . 2010 115 . . In generic addressing. . d. // load from address // vec load from address .f32 Q. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. ldu.b16.b8..ss}. // state space .s16. . and then converted to .global. The addressable operand a is one of: [avar] the name of an addressable variable var.vec = { . ldu. PTX ISA Notes Target ISA Notes Examples January 24.type = { . For ldu.vec.f32 d.u64.[a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. .v2.b16. ldu.[p+4]. . *(a+immOff). Introduced in PTX ISA version 2. Semantics d d d d = = = = a.u8.0. Instruction Set Table 82. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or the instruction may fault.Chapter 8.b64. *a. [areg] a register reg containing a byte address. Within these windows.v4 }.reg state space. .global }.[p]. .global.b32 d.f64 }. an address maps to the corresponding location in local or shared memory. [a]. The address must be naturally aligned to a multiple of the access size.ss = { . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . ldu{. A register containing an address may be declared as a bit-size type or integer type.u16.s32. or [immAddr] an immediate absolute byte address (unsigned. .f32 or .ss}. . If no state space is given. and truncated if the register width exceeds the state space address width for the target architecture.type d. .u32. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The data at the specified address must be read-only. 32-bit). . The value loaded is sign-extended to the destination register width for signed integers. 32-bit). perform the load using generic addressing. ldu.f32. The address size may be either 32-bit or 64-bit.type ldu{.e.s64. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.b32. Addresses are zero-extended to the specified width as needed.e. [a]. i. If an address is not properly aligned.s8. i. where the address is guaranteed to be the same across all threads in the warp. .

.ss}.cop . .wb.vec.volatile may be used with . . and truncated if the register width exceeds the state space address width for the target architecture. { .vec . Cache operations require sm_20 or later.local. { .ss}{. [a]. i. . an address maps to the corresponding location in local or shared memory. .cs. 2010 . .type [a]. i. the resulting behavior is undefined.volatile{.wt }.f64 }.type st. Cache operations are not permitted with st. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .f32.u64.shared }. { . . This may be used.cg.b8. . 32-bit).type . st{.shared spaces to inhibit optimization of references to volatile memory.b16.s32.s64. st. Within these windows. *(immAddr) = a. or [immAddr] an immediate absolute byte address (unsigned. b.volatile{. . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. . Addresses are zero-extended to the specified width as needed. . or the instruction may fault.ss}.reg state space.vec. for example. . .b16. Generic addressing and cache operations introduced in PTX ISA 2.type st{. .0.s16.volatile. b.s8. The lower n bits corresponding to the instruction-type width are stored to memory. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Generic addressing requires sm_20 or later. Semantics d = a. . The address must be naturally aligned to a multiple of the access size. perform the store using generic addressing.global and . A source register wider than the specified type may be used. The address size may be either 32-bit or 64-bit. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .v2. st introduced in PTX ISA version 1.u32. In generic addressing. [a]. Generic addressing may be used with st. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.ss . If an address is not properly aligned.b64. . [a]. 32-bit).ss}{.. b.volatile introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes 116 January 24.volatile.cop}. to enforce sequential consistency between threads accessing shared memory.u16.f16 data resulting from a cvt instruction may be stored using st.f64 requires sm_13 or later. st.type = = = = {.0 Table 83.u8.global.b32. If no state space is given. st.e. *(d+immOffset) = a. .PTX ISA Version 2.1. b.0.e. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.cop}. an integer or bit-size type register reg containing a byte address. *d = a. . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. an address maps to global memory unless it falls within the local memory window or the shared memory window.v4 }.

// %r is 32-bit register // store lower 16 bits January 24.b32 st.b. [fs].local.a.v4.Q. [p].%r.s32 cvt. Instruction Set Examples st.r7. // negative offset [100].f32 st. [q+-8].a.f32 st.f16.b16 [a]. [q+4].local.global.Chapter 8.%r. // immediate address %r. 2010 117 .s32 st.local.b32 st.global.

and truncated if the register width exceeds the state space address width for the target architecture.L1 [ptr]. Within these windows. i. an address maps to the corresponding location in local or shared memory. . [a].0 Table 84. A prefetch to a shared memory location performs no operation. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. // prefetch to data cache // prefetch to uniform cache .level = { .e. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 32-bit). an address maps to global memory unless it falls within the local memory window or the shared memory window. in specified state space. 2010 . In generic addressing. If no state space is given.space = { .L1 [a]. 118 January 24. or [immAddr] an immediate absolute byte address (unsigned.PTX ISA Version 2. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. . a register reg containing a byte address. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.local }. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. prefetchu. Addresses are zero-extended to the specified width as needed. 32-bit).level prefetchu. and no operation occurs if the address maps to a local or shared memory location.L2 }.L1 [addr]. prefetch and prefetchu require sm_20 or later.L1.space}. prefetch{.global. the prefetch uses generic addressing. The address size may be either 32-bit or 64-bit.0. A prefetch into the uniform cache requires a generic address.global. prefetch. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.

space = { . p.space = { . lptr. or shared state space to generic. or shared address. the generic address of the variable may be taken using cvta. isshrd.to.space. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.0. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. 2010 119 . svar. gptr. or shared address cvta. var. The source and destination addresses must be the same size. a.u32 p. When converting a generic address into a global. .lptr. local. cvta requires sm_20 or later. Use cvt. Take the generic address of a variable declared in global.shared.genptr. cvta.u32 or .space p.u32.local isspacep.global. . isspacep. or vice-versa.u32 to truncate or zero-extend addresses.0. cvta.u64. isspacep.shared isglbl. local.global. . The destination register must be of type . January 24. The source address operand must be a register of type .pred. // result is . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u64. islcl. or vice-versa. local.shared }.pred . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. .u32 p.to.global.u32. PTX ISA Notes Target ISA Notes Examples Table 86.size cvta. isspacep requires sm_20 or later.local.global isspacep. Introduced in PTX ISA version 2. p. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. Instruction Set Table 85.u64 }.u32 gptr.local. local.size . or shared state space. local.Chapter 8. For variables declared in global.size p. . sptr.space. or shared address to a generic address.size = { . a. // local. A program may use isspacep to guard against such incorrect behavior. cvta. // get generic address of svar cvta. a. // convert to generic address // get generic address of var // convert generic address to global. .shared }. Description Convert a global.u64 or cvt.local. or shared state space.space.

ftz modifier may be specified in these cases for clarity.dtype.sat}.ftz.dtype.u8.rm. i.s8.u32. subnormal numbers are supported. . .rpi }.rni round to nearest integer. .0 Table 87.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.rz.dtype = . .frnd}{.ftz}{.ftz. .u16. 2010 .f32 float-tofloat conversions with integer rounding.sat limits the result to MININT. subnormal inputs are flushed to signpreserving zero. ..f32 float-to-integer conversions and cvt.sat For integer destination types. Saturation modifier: . .irnd}{. For cvt.e. .rmi. cvt{.rzi.rni. .irnd = { . the .. .s64. . . choosing even integer if source is equidistant between two integers.f32.f32. 120 January 24.atype cvt{. . Integer rounding is illegal in all other instances.ftz.PTX ISA Version 2. d = convert(a).s32.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. a.f16.ftz}{. Note that saturation applies to both signed and unsigned integer types.sat is redundant. Integer rounding modifiers: .f32 float-to-integer conversions and cvt.s16. The compiler will preserve this behavior for legacy PTX code. and for same-size float-tofloat conversions where the value is rounded to an integer.rmi round to nearest integer in direction of negative infinity .4 and earlier. . .f64 }.dtype. Description Semantics Integer Notes Convert between different types and sizes. the result is clamped to the destination range by default.rn.f32 float-tofloat conversions with integer rounding.dtype.atype = { . subnormal inputs are flushed to signpreserving zero. . d. sm_1x: For cvt.MAXINT for the size of the operation. a.rzi round to nearest integer in the direction of zero .sat}. i.f32. Note: In PTX ISA versions 1. For float-to-integer conversions. . . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. . . . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.frnd = { .ftz. The optional . Integer rounding is required for float-to-integer conversions. // integer rounding // fp rounding .rp }. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.e.atype d.u64.

Note: In PTX ISA versions 1.ftz modifier may be specified in these cases for clarity. 1.f16.f32. subnormal numbers are supported.y.sat limits the result to the range [0. 2010 121 . cvt.f64 requires sm_13 or later. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. . . // round to nearest int.rz mantissa LSB rounds towards zero . NaN results are flushed to positive zero.f32. and . Saturation modifier: .f16.f32.s32 f. The operands must be of the same size.rni.f64 j.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. cvt.f32. Modifier . The result is an integral value.4 or earlier. Subnormal numbers: sm_20: By default. Floating-point rounding modifiers: .f32.rm mantissa LSB rounds towards negative infinity .s32.f32 x.ftz behavior for sm_1x targets January 24.Chapter 8. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f32 x.r. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64. // note . result is fp cvt. if the PTX .f32. cvt to or from . Floating-point rounding is illegal in all other instances. stored in floating-point format.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).version is 1.0]. Specifically. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.rn mantissa LSB rounds to nearest even .f32 instructions. The compiler will preserve this behavior for legacy PTX code.f32. cvt. // float-to-int saturates by default cvt. The optional .f16.0. Applies to . and cvt. Introduced in PTX ISA version 1.i.y.sat For floating-point destination types. and for integer-to-float conversions.4 and earlier.f64 types.0.

r4. and surface descriptors. r5. = nearest width height tsamp1. sampler. The advantage of unified mode is that it allows 128 samplers. add.v4. The advantage of independent mode is that textures and samplers can be mixed and matched. PTX has two modes of operation. r6.target texmode_independent . The texturing mode is selected using . and surface descriptors: • • • Static initialization of texture.r2. r2. and surfaces.f32 r1. Ability to query fields within texture.. . mul.f32 r1. r3. r1. Texture and Surface Instructions This section describes PTX instructions for accessing textures.r3. r1.entry compute_power ( . . A PTX module may declare only one texturing mode.6. . add. div.b32 r5.b32 r6. r3. If no texturing mode is declared. Texturing modes For working with textures and samplers.texref handle.height. PTX supports the following operations on texture. texture and sampler information is accessed through a single .texref tex1 ) { txq. sampler. sampler.PTX ISA Version 2. 122 January 24. r1.u32 r5. samplers.samplerref tsamp1 = { addr_mode_0 filter_mode }. but the number of samplers is greatly restricted to 16.7.f32 {r1. the file is assumed to use unified mode. texture and sampler information each have their own handle.u32 r5.r4}.f32 r1. [tex1]. with the restriction that they correspond 1-to-1 with the 128 possible textures.width.target options ‘texmode_unified’ and ‘texmode_independent’. sampler. and surface descriptors. 2010 . Module-scope and per-entry scope definitions of texture. [tex1]. // get tex1’s txq. r5. [tex1.f32 r3. // get tex1’s tex. cvt.f32. In the independent mode..f2}]. In the unified mode. allowing them to be defined separately and combined at the site of usage in the program.2d.0 8.f32.global . } = clamp_to_border. and surface descriptors. add. {f1. Example: calculate an element’s power contribution as element’s power/total number of elements.param . r5.

v4. An optional texture sampler b may be specified. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.geom = { . Supported on all target architectures. tex txq suld sust sured suq Table 88. where the fourth element is ignored. . //Example of unified mode texturing tex. A texture base address is assumed to be aligned to a 16-byte address. [tex_a. // Example of independent mode texturing tex. Notes For compatibility with prior versions of PTX. . Operand c is a scalar or singleton tuple for 1d textures. the access may proceed by silently masking off low-order address bits to achieve proper rounding. is a two-element vector for 2d textures.s32. .v4.3d. Instruction Set These instructions provide access to texture and surface memory.s32. [a. or the instruction may fault.1d.r2. // explicit sampler . [a. c].3d }. the resulting behavior is undefined.dtype = { .geom. 2010 123 .dtype.e. and is a four-element vector for 3d textures. [tex_a.v4. If no sampler is specified.s32 {r1. {f1}]. with the extra elements being ignored.v4 coordinate vectors are allowed for any geometry. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.f32 {r1. Unified mode texturing introduced in PTX ISA version 1.f2.v4.btype = { . tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.s32.r3.u32.f3.f4}].geom.btype tex.f32 }.btype d. {f1.0. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. the square brackets are not required and .r3. . sampler_x. i.f32 }.. c]. d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.Chapter 8. tex. .r4}. b.2d.s32. . The instruction always returns a four-element vector of 32-bit values. Description Texture lookup using a texture coordinate vector. PTX ISA Notes Target ISA Notes Examples January 24. .r2.5.dtype.r4}. If an address is not properly aligned. the sampler behavior is a property of the named texture.1d.

// unified mode // independent mode 124 January 24.0 Table 89. Integer from enum { nearest.depth . [smpl_B].width. clamp_ogl. Description Query an attribute of a texture or sampler.b32 %r1.b32 txq. txq.width .width. In unified mode. txq. [tex_A]. . . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and in independent mode sampler attributes are accessed via a separate samplerref argument.filter_mode . [a].addr_mode_0. txq.samplerref variable.tquery = { .5.squery = { .height.tquery.squery.texref or . addr_mode_1.b32 %r1.normalized_coords .addr_mode_0 . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.PTX ISA Version 2. . sampler attributes are also accessed via a texref argument. . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.height . Query: .filter_mode. [tex_A]. [a]. Supported on all target architectures. // texture attributes // sampler attributes . txq.b32 d. addr_mode_2 }.filter_mode. Operand a is a .b32 %r1. . mirror.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).normalized_coords }. d.addr_mode_0.depth. linear } Integer from enum { wrap.addr_mode_1 . 2010 . clamp_to_edge.

b.b supported on all target architectures.clamp field specifies how to handle out-of-bounds addresses: .3d.dtype . .b . . or .cv }.s32. . [surf_B.b64. .clamp = = = = = = { { { { { { d.5.3d requires sm_20 or later.trap. suld.s32.trap introduced in PTX ISA version 1. size and type conversion is performed as needed to convert from the surface sample format to the destination type.0.f32 based on the surface format as follows: If the surface format contains UNORM. if the surface format contains SINT data.geom . If the destination type is .dtype .b. then . .v2.clamp . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.p. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. is a two-element vector for 2d surfaces.s32. the resulting behavior is undefined. suld. . SNORM. B. . Operand b is a scalar or singleton tuple for 1d surfaces.v4. i.s32 is returned. the surface sample elements are converted to . b]. b]. If an address is not properly aligned. suld.2d.cs. suld.cop}. or . . and the size of the data transfer matches the size of destination operand d.z.dtype. where the fourth element is ignored.clamp.b32.vec .b performs an unformatted load of binary data.b16.e. Destination vector elements corresponding to components that do not appear in the surface format are not written. A surface base address is assumed to be aligned to a 16-byte address. {x.y..p requires sm_20 or later. .surfref variable. Target ISA Notes Examples January 24.r2}.cg.u32.f4}. .b8 . or FLOAT data.1d. if the surface format contains UINT data.vec. then . suld. {f1.p. suld. Cache operations require sm_20 or later.trap . .v4.clamp . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f32.p .f32 is returned.p is currently unimplemented. // unformatted d.s32. [surf_A. and A components of the surface format.f32 }.trap {r1.b64 }.p. // for suld.3d }. .Chapter 8. sm_1x targets support only the .trap suld. or the instruction may fault. suld.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. . [a.cop}. Operand a is a . The . suld. then .f32.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. // formatted .u32.b32.trap clamping modifier.geom{.b. .b32. 2010 125 . G. Coordinate elements are of type . .w}].f2. If the destination base type is .v4 }. The lowest dimension coordinate represents a sample offset rather than a byte offset. .u32 is returned. // cache operation none. {x}]. additional clamp modifiers. and cache operations introduced in PTX ISA version 2.geom{. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. and is a four-element vector for 3d surfaces.zero }. Description Load from surface memory using a surface coordinate vector.clamp suld.f3. [a. .dtype.cop .v2.1d. // for suld. Instruction Set Table 90.ca. suld. suld Syntax Texture and Surface Instructions: suld Load from surface memory.u32. .

e.geom{. B.b supported on all target architectures.u32. The size of the data transfer matches the size of source operand c.s32. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.p performs a formatted store of a vector of 32-bit data values to a surface sample.clamp field specifies how to handle out-of-bounds addresses: . is a two-element vector for 2d surfaces.b32.ctype . Operand a is a .vec. // unformatted // formatted .p. These elements are written to the corresponding surface sample components. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.ctype. and cache operations introduced in PTX ISA version 2.f32.f32} are currently unimplemented. or the instruction may fault.geom{. sust Syntax Texture and Surface Instructions: sust Store to surface memory. {r1. .wb. then .b // for sust. // for sust.y. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .cs.0 Table 91.cop . where the fourth element is ignored. . {x.clamp .b performs an unformatted store of binary data. 2010 .p. c. {f1. .trap sust.p. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. Source elements that do not occur in the surface sample are ignored.{u32. SNORM.b64.geom .b32. sust.1d. Cache operations require sm_20 or later.b.vec.s32 is assumed.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. The lowest dimension coordinate represents a sample offset rather than a byte offset. sust. none.f2. sust. If the source type is .clamp sust.f4}. if the surface format contains UINT data. sm_1x targets support only the . the resulting behavior is undefined.b. If the source base type is . .b.w}].f32 }. . [surf_B.f3.p. sust.clamp . Surface sample components that do not occur in the source vector will be written with an unpredictable value.trap .r2}.f32 is assumed.3d }. b].b8 . .v2. The source data is then converted from this type to the surface sample format. size and type conversions are performed as needed between the surface sample format and the destination type.p requires sm_20 or later.b32. or FLOAT data. A surface base address is assumed to be aligned to a 16-byte address.p Description Store to surface memory using a surface coordinate vector.s32. additional clamp modifiers.trap [surf_A. Coordinate elements are of type .cop}. . {x}]. .5. if the surface format contains SINT data. .3d requires sm_20 or later. If an address is not properly aligned. The . .s32. The source vector elements are interpreted left-to-right as R. b].vec .s32.PTX ISA Version 2. sust. and is a four-element vector for 3d surfaces.zero }.3d.0.f32.u32 is assumed.u32. [a. sust.clamp = = = = = = { { { { { { [a.v4. Target ISA Notes Examples 126 January 24. then .1d. sust. . c.ctype.ctype .b16.trap. and A surface components. .trap clamping modifier. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.v4 }.2d.v2. G. sust.b64 }. .wt }.z. i. Operand b is a scalar or singleton tuple for 1d surfaces. . .cg. .cop}. . or .clamp.trap introduced in PTX ISA version 1. then .surfref variable.. sust.

y}].op = { .add. Instruction Set Table 92. Operand a is a .trap.1d. and the data is interpreted as . The .2d. the resulting behavior is undefined.2d. // for sured. Coordinate elements are of type . r1.p performs a reduction on sample-addressed 32-bit data.p.clamp.u64. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.u32.c. . sured.u32 and .b.b32 }.or }. operations and and or apply to .1d.max.s32 types. where the fourth element is ignored.add. // sample addressing . .ctype = { .b32 }. {x}]. Operations add applies to .b.s32 or . i.ctype.u64 data. .s32 types.b32.u32.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.clamp field specifies how to handle out-of-bounds addresses: . .0.min. // byte addressing sured.b].b performs an unformatted reduction on . .3d }. .b32 type..op.c.geom.u32 is assumed.trap [surf_A. [surf_B.surfref variable. is a two-element vector for 2d surfaces.ctype. . if the surface format contains SINT data. min and max apply to . and is a four-element vector for 3d surfaces.clamp [a.geom = { . The instruction type is restricted to .b32. Reduction to surface memory using a surface coordinate vector.zero }. A surface base address is assumed to be aligned to a 16-byte address. and . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. sured.clamp [a. If an address is not properly aligned. The lowest dimension coordinate represents a sample offset rather than a byte offset. sured. or . . .p . .s32.clamp = { . . .clamp .trap sured. then . . then .s32 is assumed. . January 24.u64.geom. r1.b]. sured. 2010 127 .ctype = { .p. sured requires sm_20 or later.trap . .and.u32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32 based on the surface sample format as follows: if the surface format contains UINT data.e.Chapter 8.u32.b .s32. {x.b32. .min. // for sured.op. or the instruction may fault.s32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Operand b is a scalar or singleton tuple for 1d surfaces.

height. Query: .b32 d.query.5. [surf_A]. . Supported on all target architectures.surfref variable. [a]. 128 January 24. Operand a is a .width .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.0 Table 93. 2010 .depth }.width.width. . suq. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. suq.b32 %r1.query = { . Description Query an attribute of a surface.height .PTX ISA Version 2. .

7. used primarily for defining a function body. mov. Threads with a false guard predicate do nothing. If {!}p then instruction Introduced in PTX ISA version 1.f32 @!p div. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.c. p. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.Chapter 8. Supported on all target architectures.s32 a.0.eq.7. Introduced in PTX ISA version 1. ratio. } PTX ISA Notes Target ISA Notes Examples Table 95.b. setp. { add. 2010 129 .y.f32 @q bra L23.s32 d. {} Syntax Description Control Flow Instructions: { } Instruction grouping. Execute an instruction or instruction block for threads that have the guard predicate true. Instruction Set 8.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.0. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. @{!}p instruction.x. { instructionList } The curly braces create a group of instructions.0.a. Supported on all target architectures.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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red instruction.red also guarantee memory ordering among threads identical to membar. b}. it is as if all the threads in the warp have executed the bar instruction.popc. while .red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. the waiting threads are restarted without delay. all threads in the CTA participate in the barrier. bar. Thus. execute a bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. all-threads-true (.u32 bar.and).red performs a reduction operation across threads. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. the optional thread count must be a multiple of the warp size. and then safely read values stored by other threads prior to the barrier. the bar. Instruction Set Table 100. {!}c. bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. thread count.arrive using the same active barrier. bar. bar.sync without a thread count introduced in PTX ISA 1. When a barrier completes. The result of .red are population-count (. The barrier instructions signal the arrival of the executing threads at the named barrier.sync and bar.red delays the executing threads (similar to bar. bar. a. and the barrier is reinitialized so that it can be immediately reused. threads within a CTA that wish to communicate via memory can store to memory. b.op. Only bar.red} introduced in PTX . bar. January 24. Once the barrier count is reached. In conditionally executed code. and bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.Chapter 8.sync) until the barrier count is met.red should not be intermixed with bar.sync or bar. and any-thread-true (. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). b}. Note that a non-zero thread count is required for bar.. b. {!}c. All threads in the warp are stalled until the barrier completes.0. Register operands. Since barriers are executed on a per-warp basis. bar.sync 0. If no thread count is specified.red} require sm_20 or later.popc). operands p and c are predicates.arrive.red performs a predicate reduction across the threads participating in the barrier.u32.pred . a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).popc is the number of threads with a true predicate. thread count. and bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.red. Description Performs barrier synchronization and communication within a CTA. bar. p. bar. and d have type . Thus.sync with an immediate barrier number is supported for sm_1x targets. a{.and and .version 2. Barriers are executed on a per-warp basis as if all the threads in a warp are active.red. b}.{arrive. Register operands. PTX ISA Notes Target ISA Notes Examples bar. Execution in this case is unpredictable. Each CTA instance has sixteen barriers numbered 0. Operands a. if any thread in a warp executes a bar instruction.0.15.sync bar.arrive a{. the final value is written to the destination register in all threads waiting at the barrier.op = { .sync or bar.cta.sync and bar. d. . a{. 2010 133 .and.or). it simply marks a thread's arrival at the barrier. In addition to signaling its arrival at the barrier. Operand b specifies the number of threads participating in the barrier.arrive does not cause any waiting by the executing threads.{arrive.or }. The reduction operations for bar.

4. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. .gl. by st. 2010 . by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.cta. A memory write (e.{cta. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. that is. membar.sys }. membar. and memory reads by this thread can no longer be affected by other thread writes. membar.sys will typically have much longer latency than membar. membar. this is the appropriate level of membar.gl. including thoses communicating via PCI-E such as system and peer-to-peer memory.sys Waits until all prior memory requests have been performed with respect to all clients. . . membar.gl} introduced in PTX . membar.sys.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar. membar.gl. level describes the scope of other clients for which membar is an ordering event.level. For communication between threads in different CTAs or even different SMs. red or atom) has been performed when the value written has become visible to other clients at the specified level. or system memory level. PTX ISA Notes Target ISA Notes Examples membar.sys requires sm_20 or later. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.cta Waits until all prior memory writes are visible to other threads in the same CTA.version 2.gl will typically have a longer latency than membar. membar.version 1.PTX ISA Version 2.0 Table 101. global. when the previous value can no longer be read.cta.sys introduced in PTX . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar.gl} supported on all target architectures. 134 January 24.{cta.g.0.cta. A memory read (e. membar.level = { .g.

2010 135 . The integer operations are add.b64. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32. d.b64 . Addresses are zero-extended to the specified width as needed.Chapter 8. b. e. 32-bit operations.xor.add. .exch to store to locations accessed by other atomic operations.f32 }. . In generic addressing. The floating-point add. or by using atom. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. i. The inc and dec operations return a result in the range [0.u32 only .u32. Instruction Set Table 102.s32. atom{. The floating-point operations are add. cas (compare-and-swap). Description // // // // // .u64. . If no state space is given.global.b32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. the resulting behavior is undefined. If an address is not properly aligned.and.. Within these windows. The bit-size operations are and. inc.s32.type d. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. or.e. a de-referenced register areg containing a byte address. . . For atom.max }. . i. . . b.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Operand a specifies a location in the specified state space.f32 Atomically loads the original value at location a into destination register d. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.or.f32. min.type atom{. .s32. or [immAddr] an immediate absolute byte address. January 24. A register containing an address may be declared as a bit-size type or integer type. . .add. . max. and max.inc.exch. perform the memory accesses using generic addressing. an address maps to global memory unless it falls within the local memory window or the shared memory window. . . .cas. or the instruction may fault. xor.g. performs a reduction operation with operand b and the value in location a.u64 . atom. and max operations are single-precision. and stores the result of the specified operation at location a.e. The address size may be either 32-bit or 64-bit.b]. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. and exch (exchange). . .space}. . dec.op. min. [a]. .dec.op = { . overwriting the original value. . and truncated if the register width exceeds the state space address width for the target architecture.space}.space = { . .b32 only . by inserting barriers between normal stores and atomic operations to a common address. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. [a]. an address maps to the corresponding location in local or shared memory. .min. .u32.shared }. accesses to local memory are illegal.. c.type = { .op. The address must be naturally aligned to a multiple of the access size. min.b32.

f32 atom.{add.0. Introduced in PTX ISA version 1. atom. atom. s) = (r > s) ? s exch(r.t) = (r == s) ? t operation(*a. b).s.0. atom.shared.cas.b32 d. s) = s. c) operation(*a. d. Release Notes Examples @p 136 January 24.max} are unimplemented. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.1.my_val. atom.exch} requires sm_12 or later.global.my_new_val.[p]. b.s32 atom. : r+1.add. 64-bit atom. cas(r. s) = (r >= s) ? 0 dec(r.add.PTX ISA Version 2. *a = (operation == cas) ? : } where inc(r.shared operations require sm_20 or later.0 Semantics atomic { d = *a. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.[a].f32. 2010 . : r. atom.cas. Use of generic addressing requires sm_20 or later. d.max. 64-bit atom.global requires sm_11 or later. : r-1.global.shared requires sm_12 or later.{min.[x+4].f32 requires sm_20 or later.

Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. and max operations are single-precision. and xor. The integer operations are add. .u64.u32. i. .Chapter 8. . dec. . In generic addressing. .u64 .f32 }. b).space = { .b].type = { .add. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. a de-referenced register areg containing a byte address. The bit-size operations are and. the resulting behavior is undefined.xor..exch to store to locations accessed by other reduction operations.e. by inserting barriers between normal stores and reduction operations to a common address. max. Instruction Set Table 103. . dec(r.e.and. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. i. .s32. The floating-point operations are add. and truncated if the register width exceeds the state space address width for the target architecture.type [a].op. . The address size may be either 32-bit or 64-bit.min. red. s) = (r >= s) ? 0 : r+1.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.add. .f32 Performs a reduction operation with operand b and the value in location a. . an address maps to global memory unless it falls within the local memory window or the shared memory window. accesses to local memory are illegal. The inc and dec operations return a result in the range [0. For red. 32-bit operations. Addresses are zero-extended to the specified width as needed. the access may proceed by silently masking off low-order address bits to achieve proper rounding.op = { . Description // // // // . inc. min. January 24.s32. red{. s) = (r > s) ? s : r-1. . The address must be naturally aligned to a multiple of the access size.b32 only .global. .dec.s32. .f32. . Semantics *a = operation(*a.max }. b. an address maps to the corresponding location in local or shared memory. or the instruction may fault. e.or. or by using atom. If an address is not properly aligned. min. . . . and max. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.g. and stores the result of the specified operation at location a. . If no state space is given.u32. or. min. A register containing an address may be declared as a bit-size type or integer type. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.shared }.b64. Within these windows.u32 only . overwriting the original value. perform the memory accesses using generic addressing.space}. ..u32. Notes Operand a must reside in either the global or shared state space. where inc(r. Operand a specifies a location in the specified state space.inc.b32. or [immAddr] an immediate absolute byte address. . 2010 137 . The floating-point add. .

global.max} are unimplemented.and. 64-bit red.max.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Release Notes Examples @p 138 January 24.global.shared operations require sm_20 or later.PTX ISA Version 2.{min.f32 requires sm_20 or later.0.1.my_val.f32 red. red.add.add.shared.b32 [a].global requires sm_11 or later red. red.f32.2.s32 red. 64-bit red.add requires sm_12 or later. red. Use of generic addressing requires sm_20 or later. [p]. [x+4]. red. 2010 .shared requires sm_12 or later.

{!}a. p.ballot. Negating the source predicate also computes . vote. Negate the source predicate to compute . .q. Description Performs a reduction of the source predicate across threads in a warp. The destination predicate value is the same across all threads in the warp. In the ‘ballot’ form.pred vote. vote requires sm_12 or later.all True if source predicate is True for all active threads in warp.ballot.uni.all.2.b32 requires sm_20 or later.uni True if source predicate has the same value in all active threads in warp. vote.ballot. not across an entire CTA.pred vote. // get ‘ballot’ across warp January 24. The reduction modes are: .mode.any.uni }. {!}a.q.not_all. Negate the source predicate to compute . Note that vote applies to threads in a single warp.mode = { .ballot. r1.p. 2010 139 . .all. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. returns bitmask .any True if source predicate is True for some active thread in warp. where the bit position corresponds to the thread’s lane id.Chapter 8. vote.uni. . vote.b32 p.b32 d. vote. . Instruction Set Table 104. // ‘ballot’ form. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.none.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.pred d.

.atype = . . 140 January 24. with optional secondary operation vop.h1 }. all combinations of dtype. The source and destination operands are all 32-bit registers. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.extended internally to .9. half-word. The sign of the intermediate result depends on dtype. The type of each operand (.dtype.b2.sat} d. . a{. Using the atype/btype and asel/bsel specifiers. taking into account the subword destination size in the case of optional data merging.secop = { . 2010 . . and btype are valid. . the input values are extracted and signor zero.sat} d. to produce signed 33-bit input values.asel}. a{. // 32-bit scalar operation. .add.bsel = { .btype = { .PTX ISA Version 2.btype{.dsel.7. . atype.btype{.dsel = . b{.atype. 3. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. perform a scalar arithmetic operation to produce a signed 34-bit result. with optional data merge vop. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).max }.asel}.min.asel = .bsel}. extract and sign. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. Video Instructions All video instructions operate on 32-bit register operands.b0.dtype.b3. 4.btype{.s33 values. c. .0 8. . b{.s34 intermediate result.sat}. optionally clamp the result to the range of the destination type.or zero-extend byte.b1. b{.bsel}.dtype = . a{.bsel}. vop. 2.u32.secop d.atype. or word values from its source operands. c.atype. The general format of video instructions is as follows: // 32-bit scalar operation.s32 }.asel}.h0. .dtype. The primary operation is then performed to produce an .u32 or . .s32) is specified in the instruction type.

min: return MIN(tmp. The sign of the c operand is based on dtype.s33 optSecOp(Modifier secop. U16_MAX. . Bool sat.s33 tmp.b0. U32_MAX.h0: return ((tmp & 0xffff) case .add: return tmp + c. c). c).s33 optMerge( Modifier dsel. tmp. . . Instruction Set . default: return tmp. . Bool sign. 2010 141 .h0.s34 tmp. c).s33 tmp. c). c). } } . .b2: return ((tmp & 0xff) << 16) case .b1. . .b1: return ((tmp & 0xff) << 8) case . tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. S16_MIN ).b2. The lower 32-bits are then written to the destination operand.b3: return ((tmp & 0xff) << 24) default: return tmp. U32_MIN ). . tmp. c). tmp. switch ( dsel ) { case . January 24. c).s33 c) { switch ( secop ) { . S32_MIN ). S8_MIN ).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp. S32_MAX.Chapter 8.s33 c ) switch ( dsel ) { case . . .max return MAX(tmp. . U8_MAX. S8_MAX. as shown in the following pseudocode. S16_MAX.b0: return ((tmp & 0xff) case . Modifier dsel ) { if ( !sat ) return tmp.h1: return ((tmp & 0xffff) << 16) case .s33 optSaturate( .b3: if ( sign ) return CLAMP( else return CLAMP( case . U8_MIN ). U16_MIN ). } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).

a{. bsel ). Integer byte/half-word/word minimum / maximum. tmp = | ta – tb |. vabsdiff. vop. r3. btype.bsel}.max }.sat vmin. with optional secondary operation vop.asel}.asel}. atype.dsel.b1. sat. vmin. Integer byte/half-word/word absolute value of difference.bsel}.PTX ISA Version 2. isSigned(dtype).sat} d.h0. tb = partSelectSignExtend( b. with optional data merge vop. d = optSecondaryOp( op2.dtype .u32. r1.h0.btype{.b3. r1.op2 Description = = = = { vadd. Video Instructions: vadd. . b{.sat}.sat. vadd.s32.h1 }. tb ). { . .s32.atype.dtype.u32.min. vmin. c ). b{.s32. r2. c. vadd. vmax require sm_20 or later. vsub.btype = { . vsub vabsdiff vmin.sat} d.sat vsub. tmp. r3. .op2 d. vsub.atype. r1. Perform scalar arithmetic operation with optional saturate. vabsdiff. asel ).s32.dtype. dsel ).b0.vop .0.b0.or zero-extend based on source operand type ta = partSelectSignExtend( a.bsel}. c. .b0.btype{.s32. // extract byte/half-word/word and sign. r2.b2.atype = . vmin.b2. vmax }.dsel . c. b{.s32. 2010 . c ). .bsel = { . .u32. tmp.asel = .asel}.0 Table 105. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.btype{.s32.dtype.add.sat vabsdiff. and optional secondary arithmetic operation or subword data merge. vmax Syntax Integer byte/half-word/word addition / subtraction. tmp = MAX( ta. r2.h0.h1. vsub.add r1. r2. c. vabsdiff. r3.s32 }. tmp = ta – tb. tb ). a{. . // optional secondary operation d = optMerge( dsel.s32. // optional merge with c operand 142 January 24.atype. tmp = MIN( ta. . // 32-bit scalar operation.s32. // 32-bit scalar operation. Semantics // saturate. . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. a{.s32. r3. . taking into account destination type and merge operations tmp = optSaturate( tmp. vmax vadd.h1. .

Left shift fills with zero. atype. r3.h1 }.s32 }.dsel.atype.atype.or zero-extend based on source operand type ta = partSelectSignExtend( a. . r2. a{. c ). a{.b3.asel}.u32. . // default is .u32. // 32-bit scalar operation. d = optSecondaryOp( op2. { . and optional secondary arithmetic operation or subword data merge. vop. and optional secondary arithmetic operation or subword data merge. vshl: Shift a left by unsigned amount in b with optional saturate. . vshr vshl. case vshr: tmp = ta >> tb. .clamp . a{.u32{. c ). tmp. bsel ).clamp && tb > 32 ) tb = 32.mode}. Semantics // extract byte/half-word/word and sign. if ( mode == . . .sat}{. Instruction Set Table 106.sat}{. isSigned(dtype). . c. vshr: Shift a right by unsigned amount in b with optional saturate. January 24. Video Instructions: vshl.s32.h0.u32 vshr. . vshr Syntax Integer byte/half-word/word left / right shift.h1. sat. } // saturate. r2.u32. r3.vop . tmp. .asel}. with optional data merge vop. . switch ( vop ) { case vshl: tmp = ta << tb. unsigned shift fills with zero. vshr require sm_20 or later.u32{.dtype . .min.atype = { . // 32-bit scalar operation. vshl. tb = partSelectSignExtend( b.u32{.u32. asel ).asel = . b{.Chapter 8. { .mode} d.b0.b2. .op2 d. taking into account destination type and merge operations tmp = optSaturate( tmp.bsel}.max }.bsel}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.clamp.mode} d.u32.0.dtype. b{.b1.wrap ) tb = tb & 0x1f. dsel ).mode . if ( mode == . vshl.u32.wrap r1. vshr }.add. // optional secondary operation d = optMerge( dsel. 2010 143 .wrap }.bsel = { .dtype.dtype.bsel}. with optional secondary operation vop.op2 Description = = = = = { vshl.asel}.atype. Signed shift fills with the sign bit. b{. r1. c.sat}{.dsel .

. The final result is unsigned if the intermediate result is unsigned and c is not negated. Description Calculate (a*b) + c. vmad.. final signed -(S32 * U32) + S32 // intermediate signed.btype = { .btype{. final signed (U32 * S32) . . // 32-bit scalar operation vmad.b3.shr7.btype.sat}{. “plus one” mode. The source operands support optional negation with some restrictions. internally this is represented as negation of the product (a*b). and scaling. final signed The intermediate result is optionally scaled via right-shift. c. b{.S32 // intermediate signed.sat}{.bsel}.b1. and zero-extended otherwise. with optional operand negates. final signed (S32 * S32) + S32 // intermediate signed. 144 January 24.scale} d.scale} d. final signed -(S32 * S32) + S32 // intermediate signed. otherwise. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.u32. the intermediate result is signed.scale = { . .atype = .dtype.po) computes (a*b) + c + 1.dtype = .U32 // intermediate unsigned. .po mode.bsel = { .atype. which is used in computing averages. The “plus one” mode (.PTX ISA Version 2. this result is sign-extended if the final result is signed.s32 }.h1 }. {-}a{. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. and the operand negates.shr15 }.dtype. final unsigned -(U32 * U32) + S32 // intermediate signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. That is. .S32 // intermediate signed. Although PTX syntax allows separate negation of the a and b operands. final signed (S32 * S32) .b2.atype.asel}. final signed (S32 * U32) . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.b0. (a*b) is negated if and only if exactly one of a or b is negated.S32 // intermediate signed.asel = . Source operands may not be negated in . final signed (S32 * U32) + S32 // intermediate signed. {-}b{.asel}. final signed (U32 * S32) + S32 // intermediate signed. . a{. PTX allows negation of either (a*b) or c.po{. final signed -(U32 * S32) + S32 // intermediate signed. Input c has the same sign as the intermediate result. .bsel}. Depending on the sign of the a and b operands.h0. {-}c. . . final signed (U32 * U32) .0 Table 107. . 2010 .

r1. btype. r2. vmad. tmp[127:0] = ta * tb.shr7: result = (tmp >> 7) & 0xffffffffffffffff. } else if ( c.sat ) { if (signedFinal) result = CLAMP(result.po ) { lsb = 1. vmad requires sm_20 or later. switch( scale ) { case .or zero-extend based on source operand type ta = partSelectSignExtend( a. bsel ). -r3. S32_MAX. r3.negate ) { tmp = ~tmp.u32.u32. r2. } if ( .0.s32. else result = CLAMP(result. U32_MIN). 2010 145 . U32_MAX. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 1. January 24. lsb = 1. tb = partSelectSignExtend( b.shr15: result = (tmp >> 15) & 0xffffffffffffffff.Chapter 8. r1.shr15 r0. if ( .s32.negate ^ b. } else if ( a. asel ). tmp = tmp + c128 + lsb.negate) || c.u32. S32_MIN).sat vmad.negate ) { c = ~c. case . Instruction Set Semantics // extract byte/half-word/word and sign.negate. lsb = 0. signedFinal = isSigned(atype) || isSigned(btype) || (a.h0. r0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.negate ^ b.h0. atype.

btype.u32. . asel ).s32 }. Compare input values using specified comparison. { .asel}. tmp = compare( ta. . r2.bsel}. b{.b3. . bsel ).atype.gt.add. d = optSecondaryOp( op2.eq. cmp ) ? 1 : 0. a{. . c. r3. and therefore the c operand and final result are also unsigned. .asel}.btype. atype. // optional secondary operation d = optMerge( dsel.bsel = { . 146 January 24. tmp. 2010 .asel}.cmp. with optional secondary arithmetic operation or subword data merge. .asel = .bsel}. b{.u32. // 32-bit scalar operation.u32.h1 }. .lt vset.btype. r3. tb = partSelectSignExtend( b.btype = { . r1. { .dsel. a{.lt.0. . with optional secondary operation vset. .b1. vset.ge }. // 32-bit scalar operation.atype .op2 Description = = = = .cmp d.PTX ISA Version 2.ne.atype. . . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. r2.min.0 Table 108. c. c ).s32. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.cmp .b2.max }. . b{.cmp d. vset. tmp.h1. The intermediate result of the comparison is always unsigned. .dsel .b0.le. . c ).or zero-extend based on source operand type ta = partSelectSignExtend( a.bsel}. vset requires sm_20 or later.atype. btype.op2 d. .ne r1. Semantics // extract byte/half-word/word and sign.u32.h0. a{. tb. with optional data merge vset.

brkpt.Chapter 8. Notes PTX ISA Notes Target ISA Notes Examples Currently. pmevent 7. Triggers one of a fixed number of performance monitor events.4.7. Instruction Set 8. pmevent a. The relationship between events and counters is programmed via API calls from the host. numbered 0 through 15.10. January 24. brkpt Suspends execution Introduced in PTX ISA version 1. brkpt requires sm_11 or later. Introduced in PTX ISA version 1. Table 111.0. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. with index specified by immediate operand a. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. there are sixteen performance monitor events. trap. Supported on all target architectures. @p pmevent 1. Table 110. Supported on all target architectures. trap Abort execution and generate an interrupt to the host CPU. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.0. Introduced in PTX ISA version 1. trap. 2010 147 . brkpt.

PTX ISA Version 2. 2010 .0 148 January 24.

which are visible as special registers and accessed through mov or cvt instructions.Chapter 9. …. %clock64 %pm0. %lanemask_le. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_lt. read-only variables. %lanemask_gt %clock. %lanemask_ge. %pm3 January 24. Special Registers PTX includes a number of predefined. 2010 149 .

or 3D vector to match the CTA shape.x < %ntid. %ntid.y < %ntid. PTX ISA Notes Introduced in PTX ISA version 1. Redefined as .%tid.x. // compute unified thread id for 2D CTA mov. // thread id vector // thread id components A predefined.u32 type in PTX 2.z < %ntid. %ntid. mov.sreg .z == 1 in 1D CTAs.%tid.z PTX ISA Notes Introduced in PTX ISA version 1.z.z == 0 in 1D CTAs.u32 %h1. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. Redefined as . mov. the fourth element is unused and always returns zero.x.sreg .u32 %r1.x.x code Target ISA Notes Examples 150 January 24.u32 %ntid. %ntid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. . 2D.x code accessing 16-bit component of %tid mov. CTA dimensions are non-zero.u32 %tid.y. .x.0. // move tid.PTX ISA Version 2. It is guaranteed that: 0 <= %tid.x 0 <= %tid.u32 %r0. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.x * %ntid. %tid.%ntid.x. // zero-extend tid.u32 %tid.%tid.%tid. Every thread in the CTA has a unique %tid. read-only.y == %ntid.0.%h1. The %tid special register contains a 1D.sreg .sreg .x.u32 type in PTX 2.y 0 <= %tid. The number of threads in each dimension are specified by the predefined special register %ntid.0 Table 112.u32 %ntid. . %tid. // CTA shape vector // CTA dimensions A predefined.u32 %h2.z == 1 in 2D CTAs.%h2.y * %ntid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.v4 . .%tid.z == 0 in 2D CTAs. cvt.0.%ntid.v4 . mad.u32. read-only special register initialized with the number of thread ids in each CTA dimension.y.x to %rh Target ISA Notes Examples // legacy PTX 1.y. mov. The total number of threads in a CTA is (%ntid.v4. mov.u32 %r0.y == %tid.z. %tid.%r0. // legacy PTX 1.x. Supported on all target architectures. %ntid.0.z to %r2 Table 113.z. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. per-thread special register initialized with the thread identifier within the CTA.z). %tid component values range from 0 through %ntid–1 in each CTA dimension. Supported on all target architectures. The fourth element is unused and always returns zero.u16 %rh. the %tid value in unused dimensions is 0.v4. 2010 .u16 %rh. %tid.u16 %r2.

A predefined. Note that %warpid is volatile and returns the location of a thread at the moment when read. %nwarpid. A predefined.sreg . but its value may change during execution. The warp identifier will be the same for all threads within a single warp. Supported on all target architectures.g. January 24. 2010 151 . e. . %laneid. Supported on all target architectures. Introduced in PTX ISA version 2.u32 %warpid. %nwarpid requires sm_20 or later. due to rescheduling of threads following preemption.Chapter 9.0. read-only special register that returns the thread’s lane within the warp. mov.sreg .u32 %r. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Table 115. For this reason. mov. A predefined. The lane identifier ranges from zero to WARP_SZ-1.u32 %r. read-only special register that returns the maximum number of warp identifiers.u32 %r.sreg . . Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Table 116. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. read-only special register that returns the thread’s warp identifier.u32 %laneid. . mov. Introduced in PTX ISA version 1.u32 %nwarpid. Special Registers Table 114. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %warpid.3. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.3.

Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. Redefined as . Redefined as . or 3D vector.0 Table 117.%ctaid. // legacy PTX 1.u32 %nctaid .y.PTX ISA Version 2.z PTX ISA Notes Introduced in PTX ISA version 1.z} < 65.y.v4.z.v4 . mov.u16 %r0.u32 %ctaid.sreg . . It is guaranteed that: 1 <= %nctaid.x code Target ISA Notes Examples Table 118.0. read-only special register initialized with the number of CTAs in each grid dimension. with each element having a value of at least 1. %ctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u32 mov.%ctaid.%nctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. mov. depending on the shape and rank of the CTA grid.u32 type in PTX 2.u32 %ctaid. The %nctaid special register contains a 3D grid shape vector. The %ctaid special register contains a 1D.x.x.z < %nctaid.%nctaid. %rh.x code Target ISA Notes Examples 152 January 24. The fourth element is unused and always returns zero. 2D.y 0 <= %ctaid.x. . .x 0 <= %ctaid. The fourth element is unused and always returns zero.u16 %r0.z.0.v4 .u32 type in PTX 2. 2010 . It is guaranteed that: 0 <= %ctaid.sreg .0. // CTA id vector // CTA id components A predefined.536 PTX ISA Notes Introduced in PTX ISA version 1.u32 mov.y < %nctaid. Each vector element value is >= 0 and < 65535.sreg .%nctaid.{x.%nctaid.x. %ctaid.sreg . Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. %rh.v4.x < %nctaid.u32 %nctaid.y. Supported on all target architectures. read-only special register initialized with the CTA identifier within the CTA grid. // legacy PTX 1.y.x. Supported on all target architectures. // Grid shape vector // Grid dimensions A predefined.0.

sreg .u32 %r. read-only special register initialized with the per-grid temporal grid identifier.u32 %r. . Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. mov. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples January 24. but its value may change during execution. Introduced in PTX ISA version 1. 2010 153 . A predefined.0. %nsmid.sreg . A predefined. repeated launches of programs may occur. %smid. so %nsmid may be larger than the physical number of SMs in the device. due to rescheduling of threads following preemption.Chapter 9. mov.u32 %gridid. During execution. Note that %smid is volatile and returns the location of a thread at the moment when read. The SM identifier numbering is not guaranteed to be contiguous. The SM identifier numbering is not guaranteed to be contiguous.u32 %nsmid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. . e.sreg . %gridid. . Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Table 121.u32 %r. This variable provides the temporal grid launch number for this context.0.3.u32 %smid. where each launch starts a grid-of-CTAs.g. // initialized at grid launch A predefined. Supported on all target architectures. Introduced in PTX ISA version 2. Notes PTX ISA Notes Target ISA Notes Examples Table 120. mov. The SM identifier ranges from 0 to %nsmid-1. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Special Registers Table 119. read-only special register that returns the maximum number of SM identifiers. %nsmid requires sm_20 or later. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.

A predefined. Introduced in PTX ISA version 2. %lanemask_le.PTX ISA Version 2.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg . .u32 %r. . A predefined. A predefined. . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. mov. Introduced in PTX ISA version 2.0. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later.u32 %lanemask_le. %lanemask_eq.u32 %r.u32 %r. 2010 .u32 %lanemask_eq. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Table 123. Introduced in PTX ISA version 2.0 Table 122. %lanemask_lt.0.0. %lanemask_le requires sm_20 or later.sreg .u32 %lanemask_lt. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Table 124. mov. 154 January 24. mov. %lanemask_eq requires sm_20 or later.

. Introduced in PTX ISA version 2.0.u32 %r.u32 %lanemask_gt.Chapter 9. %lanemask_ge.u32 %lanemask_ge. Special Registers Table 125. .sreg . January 24.0. mov.u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge requires sm_20 or later.sreg . A predefined. Introduced in PTX ISA version 2. mov. %lanemask_gt. 2010 155 . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Table 126. %lanemask_gt requires sm_20 or later. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. A predefined.

….%clock.sreg .0 Table 127.PTX ISA Version 2. Their behavior is currently undefined. %pm1. read-only 64-bit unsigned cycle counter. Special registers %pm0.0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.u32 %pm0. Supported on all target architectures. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. mov. %pm1. Table 128. and %pm3 are unsigned 32-bit read-only performance monitor counters.3.sreg . Introduced in PTX ISA version 1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Table 129. %pm3. 2010 .u32 r1. %clock64 requires sm_20 or later. . read-only 32-bit unsigned cycle counter. %pm3 %pm0. Introduced in PTX ISA version 2. %pm1. %pm2. .%pm0. 156 January 24. Supported on all target architectures.u32 %clock.u64 %clock64. The lower 32-bits of %clock64 are identical to %clock. mov. %pm2. mov.sreg . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. %pm2.%clock64.0.u64 r1. Introduced in PTX ISA version 1. Special Registers: %pm0.u32 r1. .

version directive. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. 2010 157 . Increments to the major number indicate incompatible changes to PTX. Directives 10. .version 2.version 1.minor // major.version directive.version .0 .version major. Supported on all target architectures.0. Duplicate .1.Chapter 10. . Each ptx file must begin with a . minor are integers Specifies the PTX language version number. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.4 January 24. .version .version directives are allowed provided they match the original .target Table 130.version Syntax Description Semantics PTX version number. PTX File Directives: . and the target architecture for which the code was generated.

global. Requires map_f64_to_f32 if any . Description Specifies the set of features in the target architecture for which the current ptx code was generated. texture and sampler information is referenced with independent . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. with only half being used by instructions converted from . texmode_independent.texmode_independent texture and sampler information is bound together and accessed via a single .red}. A .target directive containing a target architecture and optional platform options.target . Note that . brkpt instructions. sm_13.f64 instructions used. Texturing mode introduced in PTX ISA version 1. sm_10.f64 to . The following table summarizes the features in PTX that vary according to target architecture. 64-bit {atom. The texturing mode is specified for an entire module and cannot be changed within the module. Introduced in PTX ISA version 1.f32.shared. Adds {atom. Texturing mode: (default is . texmode_unified. Each PTX file must begin with a .red}. Therefore.target directive specifies a single target architecture.f64 storage remains as 64-bits.global.texmode_unified) . Requires map_f64_to_f32 if any . and an error is generated if an unsupported feature is used. sm_11. PTX File Directives: . sm_12. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.version directive. Supported on all target architectures.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 instructions used. including expanded rounding modifiers.0. Requires map_f64_to_f32 if any . .PTX ISA Version 2. generations of SM architectures follow an “onion layer” model. Adds double-precision support.target Syntax Architecture and Platform target. 2010 . PTX features are checked against the specified target architecture. Adds {atom. PTX code generated for a given target can be run on later generation devices.texmode_unified . map_f64_to_f32 }.samplerref descriptors. Target sm_20 Description Baseline feature set for sm_20 architecture. but subsequent . immediately followed by a .red}.0 Table 131. A program with multiple .5.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. In general.texref and . vote instructions.target directives can be used to change the set of target features allowed during parsing. where each generation adds new features and retains all features of previous generations. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.f64 instructions used. Disallows use of map_f64_to_f32.texref descriptor. 158 January 24.

target sm_13 // supports double-precision .target sm_20.Chapter 10. Directives Examples . 2010 159 . texmode_independent January 24.target sm_10 // baseline target architecture .

b32 %r<99>. the kernel dimensions and properties are established and made available via special registers.param.entry Syntax Description Kernel entry point and body. %nctaid.0 through 1. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.b32 z ) Target ISA Notes Examples [x].entry kernel-name kernel-body Defines a kernel entry point name.entry kernel-name ( param-list ) kernel-body . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. In addition to normal parameters. [y]. Parameters may be referenced by name within the kernel body and loaded into registers using ld.texref. parameters. and query instructions and cannot be accessed via ld. PTX ISA Notes For PTX ISA version 1.b32 %r1.PTX ISA Version 2. At kernel launch.param space memory and are listed within an optional parenthesized parameter list.b32 x.4 and later.param. … } . .3. For PTX ISA versions 1.param instructions.entry filter ( . e.surfref variables may be passed as parameters.5 and later. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. . . ld. Parameters are passed via . etc. Kernel and Function Directives: . [z].param . . opaque . parameter variables are declared in the kernel parameter list.samplerref.param . store.entry .b32 %r2.b32 %r3. Supported on all target architectures.entry cta_fft . . . ld.2.entry . The shape and size of the CTA executing the kernel are available in special registers. ld.4. %ntid. with optional parameters. and body for the kernel function.reg .param. 160 January 24. parameter variables are declared in the kernel body.0 through 1.0 10.g. These parameters can only be referenced by name within texture and surface load.func Table 132. Semantics Specify the entry point for a kernel program.param instructions.param { . and . 2010 .b32 y.

.param state space. PTX 2. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Variadic functions are represented using ellipsis following the last fixed argument. A .b32 localVar. … Description // return value in fooval January 24. Parameters in register state space may be referenced directly within instructions in the function body.0.reg . The parameter lists define locally-scoped variables in the function body. including input and return parameters and optional function body.b32 N.func (. and recursion is illegal. .reg . Parameters in . } … call (fooval).func Syntax Function definition.0 with target sm_20 supports at most one return value.func fname (param-list) function-body . Parameters must be base types in either the register or parameter state space. which may use a combination of registers and stack locations to pass parameters.b32 rval) foo (. Release Notes For PTX ISA version 1.param space are accessed using ld. Variadic functions are currently unimplemented. foo. … use N. there is no stack. Directives Table 133.func definition with no body provides a function prototype. The implementation of parameter passing is left to the optimizing translator.f64 dbl) { .reg . (val0. Parameter passing is call-by-value. ret. Supported on all target architectures. parameters must be in the register state space.param and st.2 for a description of variadic functions. if any.func . val1). implements an ABI with stack.b32 rval.result.func (ret-param) fname (param-list) function-body Defines a function.Chapter 10. 2010 161 . dbl.x code. Kernel and Function Directives: .reg .0 with target sm_20 allows parameters in the .func fname function-body . . PTX ISA 2. other code. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.param instructions in the body. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mov. and supports recursion.

which pass information to the backend optimizing compiler.0 10.PTX ISA Version 2.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). PTX supports the following directives. These can be used. and the strings have no semantics within the PTX virtual machine model. at entry-scope.maxntid directive specifies the maximum number of threads in a thread block (CTA). The interpretation of .pragma The . Currently. registers) to increase total thread count and provide a greater opportunity to hide memory latency. the .g.entry directive and its body. Note that . Performance-Tuning Directives To provide a mechanism for low-level performance tuning.minnctapersm . for example. 2010 . and . The . to throttle the resource requirements (e.maxntid and . the .pragma directives may appear at module (file) scope. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. A general . The directive passes a list of strings to the backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.maxnctapersm (deprecated) . .maxntid. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxntid . The directives take precedence over any module-level constraints passed to the optimizing backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. 162 January 24. or as statements within a kernel or device function body.3.maxnreg. and the .maxnreg .pragma directive is supported for passing information to the PTX backend.minnctapersm directives may be applied per-entry and must appear between an .

maxntid nx .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. nz Declare the maximum number of threads in the thread block (CTA). Introduced in PTX ISA version 1. 2010 163 . Supported on all target architectures. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Directives Table 134.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Performance-Tuning Directives: . This maximum is specified by giving the maximum extent of each dimention of the 1D. The compiler guarantees that this limit will not be exceeded. 2D. Exceeding any of these limits results in a runtime error or kernel launch failure. ny .maxctapersm. or 3D CTA. .entry foo . Supported on all target architectures. ny. The maximum number of threads is the product of the maximum extent in each dimension.maxntid nx. .maxntid Syntax Maximum number of threads in thread block (CTA). or the maximum number of registers may be further constrained by . .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.16. The actual number of registers used may be less.maxntid nx. the backend may be able to compile to fewer registers.Chapter 10.3. Performance-Tuning Directives: .maxntid 16.maxnreg . Introduced in PTX ISA version 1. for example.entry bar .maxntid . .maxntid 256 .maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid and .3.entry foo .

maxntid and . Introduced in PTX ISA version 1. However.minnctapersm in PTX ISA version 2. Optimizations based on .maxnctapersm (deprecated) .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxnctapersm has been renamed to .minnctapersm 4 { … } 164 January 24.maxnctapersm. Supported on all target architectures.maxntid to be specified as well.minnctapersm generally need . .maxnctapersm generally need .3.0. The optimizing backend compiler uses . additional CTAs may be mapped to a single multiprocessor.entry foo . . 2010 .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). . .minnctapersm . Deprecated in PTX ISA version 2.maxntid to be specified as well.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid 256 . Supported on all target architectures.PTX ISA Version 2.0. Optimizations based on . .0 as a replacement for .entry foo . Performance-Tuning Directives: .maxntid 256 .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. if the number of registers used by the backend is sufficiently lower than this bound. Performance-Tuning Directives: .0 Table 136.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Introduced in PTX ISA version 2. For this reason.

pragma directive may occur at module-scope. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Directives Table 138.entry foo .pragma Syntax Description Pass directives to PTX backend compiler. entry-scoped. or at statementlevel. { … } January 24. Pass module-scoped. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma .0. . at entry-scope.Chapter 10.pragma “nounroll”. Performance-Tuning Directives: . Supported on all target architectures. or statement-level directives to the PTX backend compiler.pragma list-of-strings . 2010 165 . The interpretation of . Introduced in PTX ISA version 2. The . .pragma “nounroll”.pragma directive strings is implementation-specific and has no impact on PTX semantics.

@@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .byte byte-list // comma-separated hexadecimal byte values .x code.4byte .loc The .byte 0x2b.debug_info .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.PTX ISA Version 2. 0x02. “”.section .. 0x00 166 January 24.0. 2010 .section .0 but is supported for legacy PTX version 1. 0x5f736f63 . Table 139.file .quad int64-list // comma-separated hexadecimal integers in range [0. 0x00. 0x6150736f. 0x00.section directive.4byte 0x000006b5. Deprecated as of PTX 2. 0x00.4.section directive is new in PTX ISA verison 2. 0x00. Supported on all target architectures.232-1] . replaced by .2. The @@DWARF syntax is deprecated as of PTX version 2.debug_pubnames.0 10.4byte label . 0x00. Introduced in PTX ISA version 1. 0x63613031.4byte 0x6e69616d. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00000364.264-1] . 0x61395a5f. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.. 0x00. 0x736d6172 . @@DWARF dwarf-string dwarf-string may have one of the .4byte int32-list // comma-separated hexadecimal integers in range [0.byte 0x00. 0x00 . @progbits .0 and replaces the @@DWARF syntax.

b64 int64-list // comma-separated list of integers in range [0. 0x63613031. Supported on all target architectures. 0x00. 0x00. .b8 byte-list // comma-separated list of integers in range [0. . Debugging Directives: .debug_pubnames { . 0x00.b32 int32-list // comma-separated list of integers in range [0.section .section section_name { dwarf-lines } dwarf-lines have the following formats: . 2010 167 .b32 . .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 0x6e69616d. .b32 0x000006b5.Chapter 10. 0x736d6172 0x00 Table 141.file .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.section .264-1] .loc line_number January 24. } 0x02. Source file information. .file filename Table 142.0.b8 0x2b. Source file location. Supported on all target architectures. Directives Table 140. 0x00.loc . 0x5f736f63 0x6150736f. . 0x00.232-1] .debug_info . replaces @@DWARF syntax. Debugging Directives: . 0x00.255] . 0x00000364.b32 label .. 0x00 0x61395a5f.. Supported on all target architectures..file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b8 0x00.section Syntax PTX section definition. Debugging Directives: .0. .

Introduced in PTX ISA version 1.visible . // foo is defined in another module Table 144.extern .extern .global .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. 2010 .visible identifier Declares identifier to be externally visible. .0 10. Supported on all target architectures.global .6.PTX ISA Version 2. Linking Directives .0.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. . // foo will be externally visible 168 January 24. Supported on all target architectures. .b32 foo. Introduced in PTX ISA version 1.b32 foo. Linking Directives: .visible . Linking Directives: .0.extern . .visible Table 143.extern identifier Declares identifier to be defined externally.

0.3 PTX ISA 1.1 CUDA 2.0 January 24.0 CUDA 1. and the remaining sections provide a record of changes in previous releases.1 CUDA 2.0 CUDA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.2 PTX ISA 1.1 PTX ISA 1.5 PTX ISA 2.2 CUDA 2.3 driver r190 CUDA 3. 2010 169 .0 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1. CUDA Release CUDA 1. Release Notes This section describes the history of change in the PTX ISA and implementation. The release history is as follows.4 PTX ISA 1.Chapter 11.

sat modifiers.f32 for sm_20 targets. The goal is to achieve IEEE 754 compliance wherever possible.1.1.1. fma. 2010 .0 11. The mad. These are indicated by the use of a rounding modifier and require sm_20.f32 and mad. while maximizing backward compatibility with legacy PTX 1. Both fma. sub. mad. The mad. • • • • • 170 January 24.0 for sm_20 targets.rm and .x code and sm_1x targets. and mul now support .and double-precision div.1. Single-precision add.f32 requires sm_20.ftz modifier may be used to enforce backward compatibility with sm_1x. and sqrt with IEEE 754 compliant rounding have been added. The .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.0 11.rn. Single. The fma.PTX ISA Version 2.f32 require a rounding modifier for sm_20 targets.1. A single-precision fused multiply-add (fma) instruction has been added. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32. The changes from PTX ISA 1.1. Changes in Version 2.f32 instruction also supports .ftz and . New Features 11. When code compiled for sm_1x is executed on sm_20 devices.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Instructions testp and copysign have been added.rp rounding modifiers for sm_20 targets. Floating-Point Extensions This section describes the floating-point changes in PTX 2. rcp.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 maps to fma.

bar now supports optional thread count and register operands.section. has been added. st.arrive instruction has been added. has been added.clamp modifiers.maxnctapersm directive was deprecated and replaced with . and sust. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. ldu. %lanemask_{eq.g.{and. for prefetching to specified level of memory hierarchy. has been added. membar.add.2.f32 have been implemented. Instructions prefetch and prefetchu have also been added.gt} have been added. January 24. ldu. st. brev. A “bit reversal” instruction. local.red}.zero. A “find leading non-sign bit” instruction.lt.ballot. 2010 171 .shared have been extended to handle 64-bit data types for sm_20 targets. Instruction cvta for converting global. has been added.red. New special registers %nsmid. Instructions {atom.pred have been added. Release Notes 11. e. A “count leading zeros” instruction.1. Instructions {atom. A new directive. atom. clz.sys.1.popc. isspacep. popc. Instructions bar. A system-level membar instruction. The bar instruction has been extended as follows: • • • A bar.red.ge. A “population count” instruction.clamp and . . Surface instructions support additional . Other new features Instructions ld. cvta. Video instructions (includes prmt) have been added. vote.1.1.b32. prefetchu. and shared addresses to generic address and vice-versa has been added.le.red}. have been added. Cache operations have been added to instructions ld. bfind. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.or}.Chapter 11.u32 and bar. 11. bfe and bfi.3. has been added. has been added. Bit field extract and insert instructions.minnctapersm to better match its behavior and usage. has been added. . suld. %clock64. Instruction sust now supports formatted surface stores. A “vote ballot” instruction. and red now support generic addressing. New instructions A “load uniform” instruction. prefetch. The .

p. See individual instruction descriptions for details.u32.ftz (and cvt for . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.1.f32 type is unimplemented.PTX ISA Version 2.p sust. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.red}. The underlying.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.version is 1. if .s32.{min. 11. To maintain compatibility with legacy PTX code. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.2. the correct number is sixteen.5. stack-based ABI is unimplemented. Instruction bra. Support for variadic functions and alloca are unimplemented. has been fixed. Semantic Changes and Clarifications The errata in cvt.max} are not implemented. In PTX version 1. or . 172 January 24. call suld. 2010 . cvt. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.0 11. where .f32.4 and earlier.ftz for PTX ISA versions 1. Formatted surface store with . {atom.3. Formatted surface load is unimplemented. .1.f32} atom. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.s32.{u32.target sm_1x.5 and later.4 or earlier.

L1_body: … L1_continue: bra L1_head. Descriptions of . .pragma “nounroll”.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. Note that in order to have the desired effect at statement level.entry foo (…) . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. 2010 173 .pragma Strings This section describes the . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. disables unrolling for all loops in the entry function body. L1_end: … } // do not unroll this loop January 24. and statement levels. Supported only for sm_20 targets. entry-function. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. { … } // do not unroll any loop in this function .Appendix A. Ignored for sm_1x targets.func bar (…) { … L1_head: . including loops preceding the .pragma.pragma “nounroll”. The “nounroll” pragma is allowed at module. … @p bra L1_end.pragma “nounroll”. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. . disables unrolling of0 the loop for which the current block is the loop header. Table 145.pragma strings defined by ptxas.

2010 .0 174 January 24.PTX ISA Version 2.

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