NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

........ Texture.......... Sampler.................................... 32 Texture State Space (deprecated) .1.......1....................... and Variables .. 5.........1. 28 Constant State Space .. Chapter 6.........5................ 39 Parameterized Variable Names . 47 Chapter 7................................................................................................................ 43 Labels and Function Names as Operands .................. 6..........................................3.....1........ State Spaces ..... 37 Vectors ...... 33 5. 6..................8.................................................... 42 Addresses as Operands ............. 2010 ............ 41 6.1.......... 49 7............................................................................... 29 Parameter State Space .............1..............................2... 5. 5..........2. 6....................4.........2........................ Function declarations and definitions .......................4............... 5.................. Type Conversion.................................................................4....................................... 49 ii January 24....... 5.........................................4.... 5................1....................... 5..1................................. 33 Restricted Use of Sub-Word Sizes .................1..... and Vectors .................................................................................................... 29 Global State Space ........................................................1............................................................................................4...1.... Instruction Operands................. 43 6................................................. 5.. 37 Variable Declarations .............5..................4...........3..........4.............................. 5....................5.....3. 6........................ Summary of Constant Expression Evaluation Rules .1..4..................................5..6......3.................................4................................... 5........................................... 28 Special Register State Space .... Abstracting the ABI ................. Operand Type Information .......................................................... 6......................... 34 Variables ........7................................................ Types.......................... 33 Fundamental Types .3.............................. 5..................................................................... 5........................ Types ..................2..................................................................................................................... Operand Costs ....... 27 Register State Space ........................................PTX ISA Version 2....................................................................... 6..... 42 Arrays as Operands ............................. 27 5........2........... Arrays...1......6..... 46 6.....................................0 4............................ 44 Scalar Conversions .......................................... 5..................................................................................2...........................................................................2.................................................................................................................. 44 Rounding Modifiers .................................4........................................ 5.. 5............................. 30 Shared State Space.......................5................................................ 41 Destination Operands ................................................................................................................1............. 25 Chapter 5...............................4.......................................1....2............ 41 Using Addresses........ 32 5..................... 6...4....................................... 38 Alignment .. 38 Initializers ...6............................................................................... 37 Array Declarations ..4............ State Spaces................... 6.................................................................2..5......................... 41 Source Operands.................4........ and Surface Types ......................... 6......................... 43 Vectors as Operands .......................1.................................4..........6.................... 39 5.. 29 Local State Space ...................................................................................................... 5..................

.....................................6..............2................4..5............. Format and Semantics of Instruction Descriptions ..............................................10.................. 169 11................................9..............2.......................7....1............................................ 54 Chapter 8.............. 81 Comparison and Selection Instructions ...................... 10.2..3.................1.......................1.......................................................7........................................... 122 Control Flow Instructions ........... 147 8.................. 62 Semantics ........................ 8............................ 11...................................................... 157 10............................... 62 8.....2................................... 8..........................................................7................. Changes from PTX 1................... 59 Operand Size Exceeding Instruction-Type Size .......7....................... 8......1...............6..................................................................................................................................... 55 Predicated Execution ............6.8.......... 140 Miscellaneous Instructions.................................... 100 Logic and Shift Instructions ..................3......................1.3......................... 8............ Release Notes ............................................. Chapter 9........................................................... Changes in Version 2......... Special Registers ..3..................... PTX Version and Target Directives .....................................4.........................................................4.......... 10...........................7....... 8........................................... 60 8..................................... 132 Video Instructions .....2.............7........ 108 Texture and Surface Instructions ......... 129 Parallel Synchronization and Communication Instructions .......................... 55 PTX Instructions .................................... Type Information for Instructions and Operands .......................... Instructions ........3...............7................x .....................7.......................... 58 8.............................. 8........................... 8............. 8......... 8...................................................................................................................7.................................... 166 Linking Directives ............................... 162 Debugging Directives ....... 8......................................................7.. 8. 168 Chapter 11.....7........... Divergence of Threads in Control Constructs .......................................................... 172 January 24...................................................................1............... 55 8..................................1................................. 63 Integer Arithmetic Instructions ..... 170 New Features ........................... 10....... 149 Chapter 10........................ 11................................................................................. 52 Variadic functions ........................6... 7.................................................1.............. 160 Performance-Tuning Directives .................................................................. 11........................ 57 Manipulating Predicates ........ Directives ......................4.................... 157 Specifying Kernel Entry Points and Functions ...1........................... 8............. 2010 iii ........... 56 Comparisons ................ 53 Alloca .................................................................................7.......... 8...............................2..............................................................1................. 8......... Instruction Set ....................... 8.1............1..................................................5.. 10......................... 104 Data Movement and Conversion Instructions ..........0 ..............................7..........................................3. 7............... 63 Floating-Point Instructions ..................................3.................................................. 62 Machine-Specific Semantics of 16-bit Code ...................... 8..........1.... 172 Unimplemented Features Remaining . 170 Semantic Changes and Clarifications .......

............................. Descriptions of ...... 173 iv January 24....pragma Strings.... 2010 ...PTX ISA Version 2...................0 Appendix A...

............................................ and Bit-Size Types .................................cc .................................................................................................................. Table 12............................... 68 Integer Arithmetic Instructions: mul24 .................. Table 20...................... 61 Integer Arithmetic Instructions: add ................................................ Unsigned Integer........................... Table 14.. Table 17.................. Table 16............................................................................ Table 28.......................................... 25 State Spaces ............................. 60 Relaxed Type-checking Rules for Destination Operands............................ Table 19..................................................... 28 Fundamental Type Specifiers . Table 30...... 58 Floating-Point Comparison Operators Testing for NaN ............................................................................................. 64 Integer Arithmetic Instructions: add........ 46 Cost Estimates for Accessing State-Spaces ..... 59 Relaxed Type-checking Rules for Source Operands ............................ Table 23............................................................................................................................................................................................ 46 Integer Rounding Modifiers ................................ Table 8........... Table 29....................................................... Table 18............................................. Table 22............ 27 Properties of State Spaces .............................................List of Tables Table 1................................................ Table 6............................... 71 January 24... 58 Type Checking Rules .... Table 2....................... Table 10.................................................................................... 23 Constant Expression Evaluation Rules . 45 Floating-Point Rounding Modifiers .................... 66 Integer Arithmetic Instructions: subc .................................... Table 3............ 67 Integer Arithmetic Instructions: mad .......................... 19 Predefined Identifiers .....................cc ............ 33 Opaque Type Fields in Unified Texture Mode ...... 57 Floating-Point Comparison Operators Accepting NaN ............... 47 Operators for Signed Integer..................... Table 9....................................... 20 Operator Precedence ............ Table 26.................................... Table 4.......... Table 21.............................................................................. Table 15........................................................... Table 7................... Table 11.......................................... Table 5.......... Table 13................................................................. 70 Integer Arithmetic Instructions: sad ........................................................ 65 Integer Arithmetic Instructions: sub.................. 65 Integer Arithmetic Instructions: addc ................................................................................... Table 32..... 35 Convert Instruction Precision and Format ........................... 57 Floating-Point Comparison Operators ..................................... 35 Opaque Type Fields in Independent Texture Mode ................. 18 Reserved Instruction Keywords ....... 66 Integer Arithmetic Instructions: mul ......................... Table 31......... Table 24............................................ Table 27......................................... Table 25................................................ 69 Integer Arithmetic Instructions: mad24 ........... 2010 v ........................................ PTX Directives ...... 64 Integer Arithmetic Instructions: sub .........

................ Table 46.......... Table 51............... 103 Comparison and Selection Instructions: slct ...... 99 Comparison and Selection Instructions: set .............. 96 Floating-Point Instructions: cos ... Table 64................... 74 Integer Arithmetic Instructions: clz ...... Table 39.......PTX ISA Version 2....................................................................... 78 Integer Arithmetic Instructions: prmt .................................................... 92 Floating-Point Instructions: rcp .............................................. Table 54....................................... Table 59................................................................................................................. 92 Floating-Point Instructions: max ..................................................... Table 37.................................. 102 Comparison and Selection Instructions: selp .................................................. 75 Integer Arithmetic Instructions: brev ................................................ 95 Floating-Point Instructions: sin ........................................................... Table 69......... Table 34.. Table 66................................................................................................. Table 45...................................................................... Table 61.......... 2010 ............................................................ 88 Floating-Point Instructions: div .................................................... 79 Summary of Floating-Point Instructions . 73 Integer Arithmetic Instructions: popc ................ Table 60............................................................ 71 Integer Arithmetic Instructions: abs .......... 76 Integer Arithmetic Instructions: bfe ...................................................................................................................................................... 72 Integer Arithmetic Instructions: min ................................................ 91 Floating-Point Instructions: neg .......... Table 57....................................... Integer Arithmetic Instructions: div ..................... 90 Floating-Point Instructions: abs ......... Table 44............................................... Table 42........ Table 65............................... 91 Floating-Point Instructions: min .. 83 Floating-Point Instructions: add ................................................................................... Table 38............................. Table 56................................................................................................................................................................................................................................................................ Table 63..... 101 Comparison and Selection Instructions: setp ............. Table 62........................................................................... Table 68............................... 73 Integer Arithmetic Instructions: max ........ 71 Integer Arithmetic Instructions: rem ... Table 53................................................................................................................ Table 58.................. 77 Integer Arithmetic Instructions: bfi .........0 Table 33.......... 85 Floating-Point Instructions: mul .................. Table 52....................................... 98 Floating-Point Instructions: ex2 ................................. 87 Floating-Point Instructions: mad ................................................................................. Table 43....................................... 82 Floating-Point Instructions: testp ...................................................... Table 55..................................................................................... 72 Integer Arithmetic Instructions: neg ........ Table 49................................... 97 Floating-Point Instructions: lg2 ....................... 84 Floating-Point Instructions: sub .......... Table 47.. Table 67............................................................ Table 50............. 74 Integer Arithmetic Instructions: bfind ....... 83 Floating-Point Instructions: copysign ....... Table 36.. 103 vi January 24.......................................................................................... Table 35................. 93 Floating-Point Instructions: sqrt .... 94 Floating-Point Instructions: rsqrt ..................................... 86 Floating-Point Instructions: fma ........ Table 40............ Table 48......................................... Table 41......................

........... 118 Data Movement and Conversion Instructions: isspacep ........... Table 97. Table 95..... 137 Parallel Synchronization and Communication Instructions: vote ....................................................... Table 98.................................................. Table 94....... Table 91.................................... vsub.................. 129 Control Flow Instructions: bra ........................... Table 90............................................................ Table 75..................................... Table 103.... vmax .............................. 113 Data Movement and Conversion Instructions: ldu ................................................... prefetchu ........ vshr ................................................... 110 Data Movement and Conversion Instructions: mov ..... 139 Video Instructions: vadd...................................................................................................................... 109 Cache Operators for Memory Store Instructions ... Table 104.......... 106 Logic and Shift Instructions: shl .. 127 Texture and Surface Instructions: suq ................ 106 Logic and Shift Instructions: not ........................................ 124 Texture and Surface Instructions: suld ........ 134 Parallel Synchronization and Communication Instructions: atom ... 119 Data Movement and Conversion Instructions: cvta ................................. Table 100....... vabsdiff..... Table 105........................ Table 77...................................................................................................................................................................................................................................................................... 107 Logic and Shift Instructions: shr ........... Table 96............ 105 Logic and Shift Instructions: or .......................................... 130 Control Flow Instructions: ret ...... vmin................. Table 102.................. Table 74...................... Table 83........................................................ 119 Data Movement and Conversion Instructions: cvt . 130 Control Flow Instructions: call ....... Table 93........Table 70............... 107 Cache Operators for Memory Load Instructions .......................... Table 87.. Table 82....................................................................... 135 Parallel Synchronization and Communication Instructions: red .................... Table 85........... 131 Control Flow Instructions: exit ................................................................................................................. Table 72. Table 76... 120 Texture and Surface Instructions: tex ............................ 111 Data Movement and Conversion Instructions: mov ............... Table 88............................................................................................... Logic and Shift Instructions: and . 2010 vii ........... 115 Data Movement and Conversion Instructions: st .. 131 Parallel Synchronization and Communication Instructions: bar ......... 116 Data Movement and Conversion Instructions: prefetch............. 133 Parallel Synchronization and Communication Instructions: membar .................. 126 Texture and Surface Instructions: sured................... 142 Video Instructions: vshl...... Table 73............................................................................................. Table 99................................ Table 101... 128 Control Flow Instructions: { } ................. 112 Data Movement and Conversion Instructions: ld ...................................... Table 81....... 123 Texture and Surface Instructions: txq ..................................... 105 Logic and Shift Instructions: xor ................. Table 106.................................................... 106 Logic and Shift Instructions: cnot ................ Table 86.... Table 71. Table 78............................................ 143 January 24... 129 Control Flow Instructions: @ . Table 84............ Table 79............................... 125 Texture and Surface Instructions: sust ..................................... Table 92. Table 89................................................................ Table 80..........................................

................................target .................... 153 Special Registers: %nsmid .................................... Table 133................................................................. Table 109.............................................................................................. Table 122.... 147 Special Registers: %tid .... Table 135....................................... 146 Miscellaneous Instructions: trap ............. Table 127..........func ..................... Table 123.... Table 143.............................................................................. Table 108...........................0 Table 107............................................................................................................................... 167 Debugging Directives: ........................................... 150 Special Registers: %laneid .....................file ...................... 166 Debugging Directives: ........ 2010 ... 153 Special Registers: %gridid ..................................................................... 154 Special Registers: %lanemask_lt ............................ Table 113.......................... 147 Miscellaneous Instructions: brkpt ........................................... 151 Special Registers: %warpid ... 156 Special Registers: %clock64 ................ 157 PTX File Directives: .......... Table 129. 158 Kernel and Function Directives: ................................................................... 155 Special Registers: %lanemask_gt ............................. 152 Special Registers: %smid ..section ......... Table 121....... 167 Debugging Directives: ........................... Table 118..................................................... Table 116........ Table 120... Table 117............................. Table 112............................................ 153 Special Registers: %lanemask_eq ........ Table 128.................................................................................. %pm1. %pm3 .... 164 Performance-Tuning Directives: .................................................................................................................... Table 130..................................................... 164 Performance-Tuning Directives: ........................................................................... 167 Linking Directives: ................................................................... 144 Video Instructions: vset.......maxnreg .......................................... Table 124.maxnctapersm (deprecated) .................... Table 139........... Table 125.. 151 Special Registers: %ctaid ............ 165 Debugging Directives: @@DWARF ....................... 161 Performance-Tuning Directives: ........minnctapersm ................ %pm2...................................... Table 110.....................extern...................entry................................................................. Table 140.............................................. 150 Special Registers: %ntid ............. Video Instructions: vmad ........................... Table 119........................ Table 141.................. 155 Special Registers: %clock ......... Table 115..PTX ISA Version 2............... Table 137......................... Table 138................................................ 160 Kernel and Function Directives: ................... Table 134.................................loc ................................. 156 PTX File Directives: ..................................................... 154 Special Registers: %lanemask_le .......... Table 114.................................................................................................................... 163 Performance-Tuning Directives: ............. 156 Special Registers: %pm0........ 154 Special Registers: %lanemask_ge .. Table 111............................................................... Table 132............. 163 Performance-Tuning Directives: .. 151 Special Registers: %nwarpid ............ Table 142...................... 147 Miscellaneous Instructions: pmevent....................... Table 136................. 152 Special Registers: %nctaid ...........pragma ..................................................... 168 viii January 24.........version......................... Table 126..................... Table 131.....................................maxntid ..................................................................................

................. Table 145................... Linking Directives: ...............visible........................................ 168 Pragma Strings: “nounroll” .Table 144....................... 2010 ix ...... 173 January 24..................................................

2010 .PTX ISA Version 2.0 x January 24.

It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). In fact. which are optimized for and translated to native target-architecture instructions. the memory access latency can be hidden with calculations instead of big data caches. there is a lower requirement for sophisticated flow control. PTX exposes the GPU as a data-parallel computing device. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. PTX programs are translated at install time to the target hardware instruction set.1. many-core processor with tremendous computational horsepower and very high memory bandwidth. from general signal processing or physics simulation to computational finance or computational biology. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. image and media processing applications such as post-processing of rendered images. the programmable GPU has evolved into a highly parallel. multithreaded. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. video encoding and decoding. image scaling. PTX defines a virtual machine and ISA for general purpose parallel thread execution. 2010 1 . and pattern recognition can map image blocks and pixels to parallel processing threads. Similarly. Introduction This document describes PTX. 1. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. 1. and because it is executed on many data elements and has high arithmetic intensity. high-definition 3D graphics. January 24.2. stereo vision. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing.Chapter 1. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Because the same program is executed for each data element. Data-parallel processing maps data elements to parallel processing threads.

Instructions marked with .ftz) modifier may be used to enforce backward compatibility with sm_1x. and mul now support .f32 and mad. 1. The fma.sat modifiers.rm and . The main areas of change in PTX 2.x features are supported on the new sm_20 target. Facilitate hand-coding of libraries.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Single-precision add. • • • 2 January 24.rp rounding modifiers for sm_20 targets. memory.0 is a superset of PTX 1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The changes from PTX ISA 1. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.x.f32 instruction also supports . atomic. Both fma.rn. surface. and video instructions.f32 maps to fma.0 are improved support for IEEE 754 floating-point operations.f32 for sm_20 targets. fma.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.0 is in improved support for the IEEE 754 floating-point standard. mad.3. Achieve performance in compiled applications comparable to native GPU performance. Improved Floating-Point Support A main area of change in PTX 2. addition of generic addressing to facilitate the use of general-purpose pointers. Provide a common source-level ISA for optimizing code generators and translators. barrier. A “flush-to-zero” (. performance kernels.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Legacy PTX 1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. PTX 2. and the introduction of many new instructions.PTX ISA Version 2. Provide a code distribution ISA for application and middleware developers.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. Provide a machine-independent ISA for C/C++ and other compilers to target. including integer.ftz and .f32 require a rounding modifier for sm_20 targets.0 PTX ISA Version 2. and all PTX 1. When code compiled for sm_1x is executed on sm_20 devices. reduction. 1. PTX ISA Version 2.3.1. and architecture tests. 2010 . A single-precision fused multiply-add (fma) instruction has been added.x code will continue to run on sm_1x targets as well. sub.f32 requires sm_20. The mad.f32. The mad. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. Most of the new features require a sm_20 target. which map PTX to specific target machines.

3. These are indicated by the use of a rounding modifier and require sm_20. Instruction cvta for converting global. • Taken as a whole. local. prefetchu. and red now support generic addressing. Surface Instructions • • Instruction sust now supports formatted surface stores.0. an address that is the same across all threads in a warp. January 24. e. and sqrt with IEEE 754 compliant rounding have been added. these changes bring PTX 2.e. 2010 3 . Generic Addressing Another major change is the addition of generic addressing. instructions ld. allowing memory instructions to access these spaces without needing to specify the state space.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. rcp.and double-precision div. suld. 1. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.0 closer to full compliance with the IEEE 754 standard.4. PTX 2. stack layout. and sust.2..3.0. atom. cvta. . Instructions prefetch and prefetchu have been added. Generic addressing unifies the global. New Instructions The following new instructions. local. and shared addresses to generic addresses. local. prefetch. Surface instructions support additional clamp modifiers. A new cvta instruction has been added to convert global. NOTE: The current version of PTX does not implement the underlying. and shared addresses to generic address and vice-versa has been added. Instructions testp and copysign have been added. 1.3. isspacep. and shared state spaces.zero. stack-based ABI. special registers. 1.g. and Application Binary Interface (ABI).Chapter 1. and vice versa. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. i. Cache operations have been added to instructions ld. so recursion is not yet supported. and directives are introduced in PTX 2. Introduction • Single. for prefetching to specified level of memory hierarchy. Support for an Application Binary Interface Rather than expose details of a particular calling convention.clamp and . ldu. st. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. st.3. In PTX 2.

0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.b32. Instructions {atom.or}. Other Extensions • • • Video instructions (includes prmt) have been added. Instructions bar. .section. has been added.u32 and bar.shared have been extended to handle 64-bit data types for sm_20 targets.PTX ISA Version 2.red. Barrier Instructions • • A system-level membar instruction. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. 2010 . bfi bit field extract and insert popc clz Atomic.red. bar now supports an optional thread count and register operands.lt.pred have been added.red}.ge.le. %clock64.gt} have been added. A “vote ballot” instruction.popc.f32 have been added.sys. membar.add.arrive instruction has been added. Reduction. %lanemask_{eq. New special registers %nsmid. vote.{and. 4 January 24. A bar. has been added.red}. and Vote Instructions • • • New atomic and reduction instructions {atom.ballot. A new directive.

Chapter 9 lists special registers.0. Chapter 5 describes state spaces. Chapter 6 describes instruction operands. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. 2010 5 . Chapter 8 describes the instruction set. January 24.Chapter 1. Introduction 1. and variable declarations. Chapter 7 describes the function and call syntax. Chapter 4 describes the basic syntax of the PTX language. calling convention.4. types. Chapter 10 lists the assembly directives supported in PTX. Chapter 11 provides release notes for PTX Version 2. Chapter 3 gives an overview of the PTX virtual machine model. and PTX support for abstracting the Application Binary Interface (ABI).

2010 .PTX ISA Version 2.0 6 January 24.

2. Threads within a CTA can communicate with each other. A cooperative thread array.z). and results across the threads of the CTA.1. Each CTA thread uses its thread identifier to determine its assigned role. and select work to perform.1. Programs use a data parallel decomposition to partition inputs. The thread identifier is a three-element vector tid. tid. 2D. More precisely. or 3D shape specified by a three-element vector ntid (with elements ntid. ntid. a portion of an application that is executed many times. but independently on different data. or 3D CTA.z) that specifies the thread’s position within a 1D. To coordinate the communication of the threads within the CTA. 2. compute addresses. work. and tid. Each CTA has a 1D.2.Chapter 2. or host: In other words. or CTA. one can specify synchronization points where threads wait until all threads in the CTA have arrived. is an array of threads that execute a kernel concurrently or in parallel. compute-intensive portions of applications running on the host are off-loaded onto the device.2. (with elements tid. It operates as a coprocessor to the main CPU.x. data-parallel. The vector ntid specifies the number of threads in each CTA dimension.y. can be isolated into a kernel function that is executed on the GPU as many different threads. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. To that effect. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. January 24. assign specific input and output positions. Each thread has a unique thread identifier within the CTA. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. 2D. Programming Model 2. 2010 7 .y. and ntid. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Cooperative thread arrays (CTAs) implement CUDA thread blocks.x.

PTX ISA Version 2. depending on the platform. The warp size is a machine-dependent constant. Threads within a warp are sequentially numbered. or 3D shape specified by the parameter nctaid. WARP_SZ. A warp is a maximal subset of threads from a single CTA. However. 2D . which may be used in any instruction where an immediate operand is allowed. This comes at the expense of reduced thread communication and synchronization. Threads may read and use these values through predefined. multiple-thread) fashion in groups called warps. Multiple CTAs may execute concurrently and in parallel. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Each grid of CTAs has a 1D. Each grid also has a unique temporal grid identifier (gridid). such that the threads execute the same instructions at the same time. CTAs that execute the same kernel can be batched together into a grid of CTAs. so PTX includes a run-time immediate constant. %nctaid.0 Threads within a CTA execute in SIMT (single-instruction. %ctaid. 8 January 24. 2. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. read-only special registers %tid. 2010 . because threads in different CTAs cannot communicate and synchronize with each other. or sequentially. %ntid. so that the total number of threads that can be launched in a single kernel invocation is very large. The host issues a succession of kernel invocations to the device.2. Typically. Some applications may be able to maximize performance with knowledge of the warp size. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. a warp has 32 threads.2. and %gridid.

Chapter 2. A grid is a set of CTAs that execute independently. 1) Thread (0. 1) Thread (0. 2) Thread (2. 0) Thread (1. Figure 1. 1) Thread (1. 0) Thread (0. 1) Thread (4. 1) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) Thread (4. Thread Batching January 24. 2) Thread (4. 2) Thread (3. 0) Thread (3. 1) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 0) CTA (2. 2010 9 . 0) CTA (0. 1) CTA (1. 0) Thread (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) CTA (2. 0) CTA (1. 2) Thread (1.

The global. 2010 . 10 January 24. and texture memory spaces are persistent across kernel launches by the same application. Both the host and the device maintain their own local memory. as well as data filtering.PTX ISA Version 2. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.3. respectively. The global. and texture memory spaces are optimized for different memory usages. Finally. for some specific data formats. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. The device memory may be mapped and read or written by the host. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. or.0 2. for more efficient transfer. referred to as host memory and device memory. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant. constant. Texture memory also offers different addressing modes. Each thread has a private local memory. all threads have access to the same global memory.

0) Block (0. 1) Grid 1 Global memory Block (0. 0) Block (2.Chapter 2. 2) Block (1. 1) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2010 11 . 1) Block (0. 2) Figure 2. 0) Block (1. 0) Block (0. 1) Block (2. Memory Hierarchy January 24. 1) Block (1. 0) Block (1.

PTX ISA Version 2.0 12 January 24. 2010 .

a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. To manage hundreds of threads running several different programs. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. schedules. The multiprocessor SIMT unit creates. When a host program invokes a kernel grid. If threads of a warp diverge via a data-dependent conditional branch. it splits them into warps that get scheduled by the SIMT unit. When a multiprocessor is given one or more thread blocks to execute. a multithreaded instruction unit. and when all paths complete. The threads of a thread block execute concurrently on one multiprocessor. a cell in a grid-based computation). the warp serially executes each branch path taken. different warps execute independently regardless of whether they are executing common or disjointed code paths. and executes concurrent threads in hardware with zero scheduling overhead. Parallel Thread Execution Machine Model 3. each warp contains threads of consecutive. and each scalar thread executes independently with its own instruction address and register state. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. the first parallel thread technology. and executes threads in groups of parallel threads called warps. for example. the threads converge back to the same execution path. the multiprocessor employs a new architecture we call SIMT (single-instruction. so full efficiency is realized when all threads of a warp agree on their execution path.1. a voxel in a volume. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. increasing thread IDs with the first warp containing thread 0. and on-chip shared memory. The multiprocessor creates. disabling threads that are not on that path.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. manages.Chapter 3. new blocks are launched on the vacated multiprocessors. allowing. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). multiple-thread). A multiprocessor consists of multiple Scalar Processor (SP) cores. The multiprocessor maps each thread to one scalar processor core. manages. 2010 13 . As thread blocks terminate. January 24. A warp executes one common instruction at a time. Branch divergence occurs only within a warp. It implements a single-instruction barrier synchronization. (This term originates from weaving. The way a block is split into warps is always the same. At every instruction issue time.

SIMT enables programmers to write thread-level parallel code for independent. A multiprocessor can execute as many as eight thread blocks concurrently. but one of the writes is guaranteed to succeed. the kernel will fail to launch. but the order in which they occur is undefined. however. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space.PTX ISA Version 2. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. each read. Vector architectures. modifies. whereas SIMT instructions specify the execution and branching behavior of a single thread. If there are not enough registers or shared memory available per multiprocessor to process at least one block. and writes to the same location in global memory for more than one of the threads of the warp. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. 14 January 24. 2010 . A key difference is that SIMD vector organizations expose the SIMD width to the software. modify. which is a read-only region of device memory. as well as data-parallel code for coordinated threads. • The local and global memory spaces are read-write regions of device memory and are not cached. the number of serialized writes that occur to that location and the order in which they occur is undefined. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. In contrast with SIMD vector machines. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. write to that location occurs and they are all serialized. require the software to coalesce loads into vectors and manage divergence manually. As illustrated by Figure 3. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. If an atomic instruction executed by a warp reads. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. scalar threads. For the purposes of correctness. the programmer can essentially ignore the SIMT behavior. In practice. on the other hand. which is a read-only region of device memory. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space.0 SIMT architecture is akin to SIMD (Single Instruction.

Figure 3.Chapter 3. 2010 15 . Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

2010 .PTX ISA Version 2.0 16 January 24.

followed by a . Pseudo-operations specify symbol and addressing management. using non-nested /* and */ for comments that may span multiple lines. #endif. Syntax PTX programs are a collection of text source files. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #else. whitespace is ignored except for its use in separating tokens in the language.target directive specifying the target architecture assumed. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.2. #line. All whitespace characters are equivalent. and using // to begin a comment that extends to the end of the current line.1. PTX is case sensitive and uses lowercase for keywords. Each PTX file must begin with a . Comments Comments in PTX follow C/C++ syntax. Comments in PTX are treated as whitespace.version directive specifying the PTX language version. #ifdef. 4. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. 4. The following are common preprocessor directives: #include. The C preprocessor cpp may be used to process PTX source files. #if. Lines are separated by the newline character (‘\n’). Lines beginning with # are preprocessor directives. Source Format Source files are ASCII text. See Section 9 for a more information on these directives. 2010 17 .Chapter 4. January 24. #define.

The guard predicate may be optionally negated. followed by source operands.3.param .entry .reg . constant expressions. ld.func .0 4.version .maxnreg .loc .3. %tid. The guard predicate follows the optional label and precedes the opcode.maxntid . Instruction keywords are listed in Table 2. Statements begin with an optional label and end with a semicolon. . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.b32 r1. address expressions. Instructions have an optional guard predicate which controls conditional execution. Examples: .global .PTX ISA Version 2. and is written as @p.5. shl. r2.reg . All instruction keywords are reserved tokens in PTX. The destination operand is first.extern .b32 add. so no conflict is possible with user-defined identifiers.b32 r1.const . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.target .tex .maxnctapersm . Table 1.local .minnctapersm . or label names. written as @!p.sreg . 2.global. where p is a predicate register.f32 r2. r2.b32 r1.pragma .1.visible 4. and terminated with a semicolon.f32 array[N]. array[r1]. . Directive Statements Directive keywords begin with a dot.shared .3.align . mov. r1.file PTX Directives . Statements A PTX statement is either a directive or an instruction.2. 2010 . 0.global start: .section . 18 January 24. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. Operands may be register variables. r2.x.

Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 . Syntax Table 2.

or percentage character followed by one or more letters. PTX predefines one constant and a small number of special registers that begin with the percentage sign. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. listed in Table 3. except that the percentage sign is not allowed. Table 3. digits. Many high-level languages such as C and C++ follow similar rules for identifier names. e. PTX allows the percentage sign as the first character of an identifier. between user-defined variable names and compiler-generated names. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.4. underscore.0 4. or dollar characters.PTX ISA Version 2. …. or they start with an underscore. 2010 . The percentage sign can be used to avoid name conflicts. underscore. %pm3 WARP_SZ 20 January 24.g. dollar. digits. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.

s64) unless the value cannot be fully represented in . where the behavior of the operation depends on the operand types. hexadecimal. i. Unlike C and C++. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.u64.e. every integer constant has type . or binary notation. i. The syntax follows that of C.. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.s64 or the unsigned suffix is specified. Syntax 4.1. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. For predicate-type data and instructions. the constant begins with 0d or 0D followed by 16 hex digits. These constants may be used in data initialization and as operands to instructions. literals are always represented in 64-bit double-precision format. 4.5. the constant begins with 0f or 0F followed by 8 hex digits. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. 0[fF]{hexdigit}{8} // single-precision floating point January 24.. octal. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.u64). To specify IEEE 754 doubleprecision floating point values. When used in an instruction or data initialization. each integer constant is converted to the appropriate size based on the data or instruction type at its use. floating-point. Type checking rules remain the same for integer.5. 2010 21 .e. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. Floating-point literals may be written with an optional decimal point and an optional signed exponent. 4. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. the sm_1x and sm_20 targets have a WARP_SZ value of 32. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. and bit-size types.5. integer constants are allowed and are interpreted as in C.s64 or . Constants PTX supports integer and floating-point constants and constant expressions. Integer literals may be written in decimal. there is no suffix letter to specify size. zero values are FALSE and non-zero values are TRUE. in which case the literal is unsigned (.2.Chapter 4. To specify IEEE 754 single-precision floating point values.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero . Syntax 4. .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .u64 .f64 use usual conversions .5. Table 5.Chapter 4. 2nd is .u64 .u64 same as 1st operand .f64 integer .u64 .u64.s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 .f64 : .f64 same as source .u64 .s64) + .6.f64 integer .s64 . 2010 25 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 .f64 converted type constant literal + ! ~ Cast Binary (.f64 converted type . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .f64 use usual conversions .f64 use usual conversions .u64 . or .f64 integer integer integer integer integer int ?.u64 1st unchanged.s64.s64 .s64 .u64) (.

0 26 January 24.PTX ISA Version 2. 2010 .

and properties of state spaces are shown in Table 5. . The list of state spaces is shown in Table 4. 2010 27 . pre-defined. Name State Spaces Description Registers. platform-specific. and these resources are abstracted in PTX through state spaces and data types.local .reg . or Function or local parameters. Read-only. access rights.shared .1. Addressable memory shared between threads in 1 CTA.Chapter 5. Shared. All variables reside in some state space. Table 6.param . The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Global texture memory (deprecated). 5. read-only memory. Types. and level of sharing between threads. defined per-grid. Local memory.const . the kinds of resources will be common across platforms. addressability. Special registers. shared by all threads. private to each thread. State Spaces. Global memory. State Spaces A state space is a storage area with particular characteristics. defined per-thread. access speed. fast.tex January 24. Kernel parameters. and Variables While the specific resources available in a given target GPU will vary.global . The characteristics of a state space include its size.sreg .

Address may be taken via mov instruction. Register size is restricted. or as elements of vector tuples. and will vary from platform to platform. Registers may be typed (signed integer. Device function input parameters may have their address taken via mov. When the limit is exceeded. Special Register State Space The special register (. All special registers are predefined. register variables will be spilled to memory.param (used in functions) . and performance monitoring registers.param instruction.e. 32-. 2010 .const . scalar registers have a width of 8-. 1 Accessible only via the ld. 16-.PTX ISA Version 2. Register State Space Registers (.local .. For each architecture. and thread parameters. causing changes in performance. and vector registers have a width of 16-.reg state space) are fast storage locations.reg . platform-specific registers.2.1. 28 January 24. aside from predicate registers which are 1-bit. st. unsigned integer. the parameter is then located on the stack frame and its address is in the . i. The most common use of 8-bit registers is with ld. 2 Accessible via ld.tex Restricted Yes No3 5. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.1.local state space.param instructions. clock counters. it is not possible to refer to the address of a register.sreg . and cvt instructions. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). such as grid. floating point.param and st. or 128-bits. 3 Accessible only via the tex instruction.1.sreg) state space holds predefined. CTA. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 64-.0 Table 7.shared . 32-. or 64-bits. Registers may have alignment boundaries required by multi-word loads and stores. The number of registers is limited. 5. predicate) or untyped.global .param (as input to kernel) . Registers differ from the other state spaces in that they are not fully addressable.

The remaining banks may be used to implement “incomplete” constant arrays (in C. b = b – 1. Constant State Space The constant (.1. initialized by the host.sync instruction are guaranteed to be visible to any reads after the barrier instruction. By convention. each pointing to the start address of the specified constant bank.1. Multiple incomplete array variables declared in the same bank become aliases. It is the mechanism by which different CTAs and different grids can communicate.local) is private memory for each thread to keep its own data.Chapter 5. Sequential consistency is provided by the bar. as in lock-free and wait-free style programming. ld.const) state space is a read-only memory. // load second word 5. st. Consider the case where one thread executes the following two assignments: a = a + 1. The size is limited. Global memory is not sequentially consistent.extern . there are eleven 64KB banks. Local State Space The local state space (. Module-scoped local memory variables are stored at fixed addresses. Banks are specified using the . To access data in contant banks 1 through 10.global to access global variables.global) state space is memory that is accessible by all threads in a context. the declaration . results in const_buffer pointing to the start of constant bank two.5. and atom. For example. 2010 29 . Global State Space The global (. Threads must be able to do their work without waiting for other threads to do theirs.local and st. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. and Variables 5. The constant memory is organized into fixed size banks. the bank number must be provided in the state space of the load instruction. For any thread in a context. If no bank number is given. an incomplete array in bank 2 is accessed as follows: .b32 %r1. If another thread sees the variable b change.const[bank] modifier.global.3.const[2]. It is typically standard memory with cache. In implementations that support a stack. where bank ranges from 0 to 10.b32 const_buffer[]. For example. Use ld.extern .1. Threads wait at the barrier until all threads in the CTA have arrived.const[2] .global. whereas local memory variables declared January 24. State Spaces. the stack is in local memory.sync instruction.b32 const_buffer[]. This reiterates the kind of parallelism available in machines that run PTX. Types. bank zero is used. All memory writes prior to the bar. as it must be allocated on a perthread basis. 5. [const_buffer+4].const[2] . all addresses are in global memory are shared. the store operation updating a may still be in flight. For the current devices. for example).4.local to access local variables. This pointer can then be used to access the entire 64KB constant bank. where the size is not known at compile time. bank zero is used for all statically-sized constant variables. Use ld.

read-only variables declared in the .param instructions. per-kernel versus per-thread).reg . [N].u32 %n. … Example: . and (2b) to declare locally-scoped byte array variables that serve as function call arguments.1. In implementations that do not support a stack.param state space.0 and requires target architecture sm_20.u32 %n.u32 %n.param.1. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.reg .param .f64 %d. Note: The location of parameter space is implementation specific. mov. ld.b32 N.x supports only kernel function parameters in .b8 buffer[64] ) { .param .f64 %d.u32 %ptr. in some implementations kernel parameters reside in global memory.param .b32 len ) { .u32 %ptr. Therefore.param space variables. For example. ld.param) state space is used (1) to pass input arguments from the host to the kernel.param. The resulting address is in the . [buffer]. 5. typically for passing large structures by value to a function.6. Similarly. These parameters are addressable. Note that PTX ISA versions 1. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).reg .align 8 . %n. ld. Example: .param space. The address of a kernel parameter may be moved into a register using the mov instruction. The kernel parameter variables are shared across all CTAs within a grid. No access protection is provided between parameter and global space in this case. The use of parameter state space for device function parameters is new to PTX ISA version 2. Parameter State Space The parameter (. 2010 .6. len. 5. PTX code should make no assumptions about the relative locations or ordering of . … 30 January 24.param instructions.param.PTX ISA Version 2. (2a) to declare formal input and return parameters for device functions called from within kernel execution. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. all local memory variables are stored at fixed addresses and recursive function calls are not supported. . Values passed from the host to the kernel are accessed through these parameter variables using ld.1.entry bar ( .0 within a function or kernel body are allocated on the stack.param state space and is accessed using ld. . device function parameters were previously restricted to the register state space. [%ptr].entry foo ( .

State Spaces.param.reg . the caller will declare a locally-scoped . [buffer+8].param .b8 buffer[12] ) { .f64 dbl. Aside from passing structures by value.param space is also required whenever a formal parameter has its address taken within the called function. and Variables 5.reg .param. . st. int y.reg . [buffer]. Typically. which declares a . . 2010 31 . ld. passed to foo … .param .align 8 .s32 x.s32 %y. Device Function Parameters PTX ISA version 2.0 extends the use of parameter space to device function parameters. The most common use is for passing objects by value that do not fit within a PTX register. In PTX. }.local state space and is accessed via ld.local and st. Types. x.param.f64 [mystruct+0].f64 %d. … } // code snippet from the caller // struct { double d. Example: // pass object of type struct { double d. January 24. (4. .2. . . In this case. It is not possible to use mov to get the address of a return parameter or a locally-scoped .b8 mystruct.1.param byte array variable that represents a flattened C structure or union.reg .param and function return parameters may be written using st.reg .s32 %y. This will be passed by value to a callee. … See the section on function call syntax for more details.b32 N.Chapter 5. a byte array in parameter space is used.param. call foo. and so the address will be in the . Note that the parameter will be copied to the stack if necessary.6. … st. the address of a function input parameter may be moved into a register using the mov instruction. such as C structures larger than 8 bytes. Function input parameters may be read via ld. is flattened.param formal parameter having the same size and alignment as the passed argument. . ld.func foo ( .param.local instructions.param space variable.s32 [mystruct+8]. mystruct). } mystruct.align 8 . int y. dbl.f64 %d. it is illegal to write to an input parameter or read from a return parameter.

The . tex_d. Example: .u32 . and variables declared in the . is equivalent to .u64.1.6 for its use in texture instructions.8. Shared memory typically has some optimizations to support the sharing. tex_c.u32 . and .texref variables in the .tex state space are equivalent to module-scoped . Another is sequential access from sequential threads.tex . tex_f. 2010 .0 5. Texture State Space (deprecated) The texture (.7. tex_d.tex) state space is global memory accessed via the texture instruction.7. The .tex directive is retained for backward compatibility. 5. and programs should instead reference texture memory through variables of type . Physical texture resources are allocated on a per-module granularity. Multiple names may be bound to the same physical texture identifier. where all threads read from the same address.shared to access shared variables.shared and st.shared) state space is a per-CTA region of memory for threads in a CTA to share data.u32 tex_a. The texture name must be of type .3 for the description of the .tex . Use ld. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.u32 .u32 tex_a. Texture memory is read-only. An error is generated if the maximum number of physical resources is exceeded.u32 or .global state space. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex directive will bind the named texture memory variable to a hardware texture identifier. For example.1. A texture’s base address is assumed to be aligned to a 16-byte boundary.tex .tex . See Section 5. It is shared by all threads in a context.PTX ISA Version 2.texref. a legacy PTX definitions such as .tex . 32 January 24.texref tex_a.tex variables are required to be defined in the global scope.texref type and Section 8. An address in shared memory can be read and written by any thread in a CTA. One example is broadcast.global . Shared State Space The shared (. where texture identifiers are allocated sequentially beginning with zero.

f32. . Signed and unsigned integer types are compatible if they have the same size. . all variables (aside from predicates) could be declared using only bit-size types. and Variables 5. Two fundamental types are compatible if they have the same basic type and are the same size. stored. . but typed variables enhance program readability and allow for better operand type checking. For example. A fundamental type specifies both a basic type and a size. ld. and cvt instructions. or converted to other types and sizes.2. The same typesize specifiers are used for both variable definitions and for typing instructions.f64 types. The following table lists the fundamental type specifiers for each basic type: Table 8. The bitsize type is compatible with any fundamental type having the same size. the fundamental types reflect the native data types supported by the target architectures.s8. Fundamental Types In PTX. The . so that narrow values may be loaded. All floating-point instructions operate only on . Types.f32 and .2.b8 instruction types are restricted to ld. In principle. 5. .1. Restricted Use of Sub-Word Sizes The . 2010 33 .2.s8.u32. stored. needed to fully specify instruction behavior. . st.2. st. and . For convenience.pred Most instructions have one or more type specifiers. Register variables are always of a fundamental type. Types 5. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. .s16.b32. January 24. State Spaces.f64 .b8. and instructions operate on these types.b16. Operand types and sizes are checked against instruction types for compatibility. so their names are intentionally short. .f16.u8. . . and converted using regular-width registers.u16. .u8.f32 and .b64 .s32.s64 .f16 floating-point type is allowed only in conversions to and from .Chapter 5. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .f64 types.u64 . .

u64} reg. PTX has two modes of operation. since these properties are defined by . and .samplerref. the resulting pointer may be stored to and loaded from memory. Retrieving the value of a named member via query instructions (txq. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. sampler. or performing pointer arithmetic will result in undefined results. and de-referenced by texture and surface load.texref handle. samplers. passed as a parameter to functions. suq). Creating pointers to opaque variables using mov. but all information about layout. sured).0 5. allowing them to be defined separately and combined at the site of usage in the program.surfref. texture and sampler information is accessed through a single . base address. Referencing textures. The following tables list the named members of each type for unified and independent texture modes.texref type that describe sampler properties are ignored.e. i. 2010 . and Surface Types PTX includes built-in “opaque” types for defining texture. Sampler. These types have named fields similar to structures. Texture.texref. In the independent mode. and overall size is hidden to a PTX program. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. The three built-in types are .PTX ISA Version 2. store. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. or surfaces via texture and surface load/store instructions (tex. hence the term “opaque”. In independent mode the fields of the . . For working with textures and samplers. texture and sampler information each have their own handle. 34 January 24.. field ordering. and surface descriptor variables. In the unified mode. accessing the pointer with ld and st instructions. opaque_var.samplerref variables. suld. and query instructions. sust.3.{u32. but the pointer cannot otherwise be treated as an address.

clamp_ogl. mirror. State Spaces.Chapter 5. linear wrap. linear wrap. clamp_to_border N/A N/A N/A N/A N/A . Member width height depth Opaque Type Fields in Independent Texture Mode . Member width height depth Opaque Type Fields in Unified Texture Mode .samplerref values N/A N/A N/A N/A nearest. clamp_to_edge. clamp_ogl. 1 nearest. clamp_to_edge.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. and Variables Table 9. 1 ignored ignored ignored ignored .texref values in elements in elements in elements 0. mirror. 2010 35 . Types.texref values .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_border 0.

. At module scope. When declared at module scope. the types may be initialized using a list of static expressions assigning values to the named members. Example: . Example: .global state space.texref tex1.global .global . filter_mode = nearest }. .surfref my_surface_name.samplerref my_sampler_name.param state space. As kernel parameters. . 36 January 24.global .global .global . these variables must be in the . 2010 .texref my_texture_name.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.PTX ISA Version 2. these variables are declared in the .0 Variables using these types may be declared at module scope or within kernel entry parameter lists.

. its name.Chapter 5. . q. // a length-2 vector of unsigned ints .const .shared . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . for example. In addition to fundamental types. 5.v2. 5.reg . Types.v4 . January 24. r. vector variables are aligned to a multiple of their overall size (vector length times base-type size).4. and they may reside in the register space. and an optional fixed address for the variable. . PTX supports types for simple aggregate objects such as vectors and arrays. // a length-4 vector of floats .u8 bg[4] = {0. // a length-4 vector of bytes By default.v4 vector. Vectors Limited-length vector types are supported. Vectors cannot exceed 128-bits in length. . 1. A variable declaration names the space in which the variable resides.reg .pred p. Variables In PTX.0}.global . . to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v2 .global . an optional initializer.b8 v.reg . // typedef . Predicate variables may only be declared in the register state space. and Variables 5. Variable Declarations All storage for data is specified with variable declarations.u16 uv.f32 v0. 0. textures.global . where the fourth element provides padding.v4 .f32 bias[] = {-1.1.0. 0.2.v4 .struct float4 { .s32 i.4.4.f64 is not allowed. State Spaces. etc.global .f32 accel.u32 loc.f32 V.v2 or . Every variable must reside in one of the state spaces enumerated in the previous section. Three-element vectors may be handled by using a . a variable declaration describes both the variable’s type and its state space. Examples: . .v1. 2010 37 . Examples: .v3 }. .v4.v4. its type and size. 0}. Vectors must be based on a fundamental type. This is a common case for three-dimensional grids.global . an optional array size.struct float4 coord.

1.u64.shared . . Initializers Declared variables may specify an initial value using a syntax similar to C/C++. 1} }.global .3.05.PTX ISA Version 2.1.4. . 2010 . A scalar takes a single value. Here are some examples: . . where the variable name is followed by an equals sign and the initial value or values for the variable.local . Variable names appearing in initializers represent the address of the variable. 38 January 24. {0.global .0.f16 and . {0.global .s32 offset[][] = { {-1. To declare an array.s32 n = 10.u8 rgba[3] = {{1. For the kernel declaration above. variable initialization is supported only for constant and global state spaces.1. 0}.f32 blur_kernel[][] = {{. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).pred. . this can be used to initialize a jump table to be used with indirect branches or calls..u32 or . {1.b32 ptr = rgba.4.0..05..0 5.{. Initializers are allowed for all types except . -1}.u8 mailbox[128].global . Array Declarations Array declarations are provided to allow the programmer to reserve space.. The size of the dimension is either a constant expression. Similarly. .1.{.0. this can be used to statically initialize a pointer to a variable. The size of the array specifies how many elements should be reserved.1}. // address of rgba into ptr Currently.0}. label names appearing in initializers represent the address of the next instruction following the label. Variables that hold addresses of variables or instructions should be of type .. or is left empty.global .4. 5.05}}. 0}.0}}.0.05}.v4 ..0}.4. 19*19 (361) halfwords are reserved (722 bytes). {0. Examples: .u16 kernel[19][19]. being determined by an array initializer. {0.1. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.

suppose a program uses a large number. January 24. State Spaces.0. of . The default alignment for vector variables is to a multiple of the overall vector size. and Variables 5. . …. %r99. Array variables cannot be declared this way. For example. %r1. These 100 register variables can be declared as follows: . nor are initializers permitted. Parameterized Variable Names Since PTX supports virtual registers.reg . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.0.b32 %r<100>.0. The variable will be aligned to an address which is an integer multiple of byte-count. say one hundred. The default alignment for scalar and array variables is to a multiple of the base-type size.b32 variables.4.0}. . %r1. it is quite common for a compiler frontend to generate a large number of register names.const . Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.. Elements are bytes. Alignment is specified using an optional . alignment specifies the address alignment for the starting address of the entire array.6. named %r0.2. 2010 39 . PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Examples: // allocate array at 4-byte aligned address.b8 bar[8] = {0. not for individual elements. Types. 5..4. and may be preceded by an alignment specifier. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.align byte-count specifier immediately following the state-space specifier.5.align 4 .Chapter 5. // declare %r0. For arrays. Rather than require explicit declaration of every name..0.0.

2010 .PTX ISA Version 2.0 40 January 24.

r. 6. 6.3. Instructions ld and st move data from/to addressable state spaces to/from registers. the sizes of the operands must be consistent. The bit-size type is compatible with every type having the same size. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Source Operands The source operands are denoted in the instruction descriptions by the names a. Most instructions have an optional predicate guard that controls conditional execution. 2010 41 .Chapter 6. and c. s. as its job is to convert from nearly any data type to any other data type (and size). For most operations. b. There is no automatic conversion between types. Predicate operands are denoted by the names p. The mov instruction copies data between registers. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. and cvt instructions copy data from one location to another.reg register state space.2. st. PTX describes a load-store machine. Integer types of a common size are compatible with each other. mov. Instruction Operands 6. Each operand type must be compatible with the type determined by the instruction template and instruction type. . January 24. The ld. The cvt (convert) instruction takes a variety of operand types and sizes. q. The result operand is a scalar or vector variable in the register state space. Operand Type Information All operands in instructions have a known type from their declarations. so operands for ALU instructions must all be in variables declared in the .1. and a few instructions have additional predicate source operands.

4. .b32 p.v4. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.reg . 2010 .u16 ld.1. q.f32 ld. Using Addresses.reg .global . .v4 .[x]. and immediate address expressions which evaluate at compile-time to a constant address.shared.PTX ISA Version 2. r0. The interesting capabilities begin with addresses.reg . . The syntax is similar to that used in many assembly languages. address register plus byte offset. tbl.s32 tbl[256]. Examples include pointer arithmetic and pointer comparisons. The address is an offset in the state space in which the variable is declared.u32 42 January 24. [V].s32 mov. Here are a few examples: . ld.u16 r0. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. . 6. .f32 V. Load and store operations move data between registers and locations in addressable state spaces.v4 .u16 x. Address expressions include variable names.const . address registers. The mov instruction can be used to move the address of a variable into a pointer. Arrays. there is no support for C-style pointer arithmetic. and Vectors Using scalar variables as operands is straightforward.f32 W. W. .s32 q.0 6. arrays. [tbl+12]. p.const. All addresses and address computations are byte-based.shared .gloal.reg . and vectors.4.

Arrays as Operands Arrays of all types can be declared.3. or a simple “register with constant offset” expression. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.f32 {a. . [addr+offset].u32 s.w. . and in move instructions to get the address of the label or function into a register.global. mov. Rb.b and .reg .global. The expression within square brackets is either a constant integer. a[N-1]. Array elements can be accessed using an explicitly calculated byte address.4. which include mov. say {Ra. V. Vectors as Operands Vector operands are supported by a limited subset of instructions. it must be written as an address calculation prior to use.b.b. Elements in a brace-enclosed vector. The size of the array is a constant in the program.v4 .global. If more complicated indexing is desired. // move address of a[1] into s 6.f32 ld. and the identifier becomes an address constant in the space where the array is declared.Chapter 6.reg . . where the offset is a constant expression that is either added or subtracted from a register variable. .z and . January 24. A brace-enclosed list is used for pattern matching to pull apart vectors.b V.d}.r.u32 s.z V. Here are examples: ld. 2010 43 .4. Vectors may also be passed as arguments to called functions. st.u32 {a.w = = = = V. [addr+offset2].v4.g.x.r V. or by indexing into the array using square-bracket notation.f32 a. Instruction Operands 6. d. which may improve memory performance.f32 V.y.4. a[0].global. Rd}.c. or a braceenclosed list of similarly typed scalars.u32 s.x V. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. Vector elements can be extracted from the vector with the suffixes .v4.v2. for use in an indirect branch or call.d}.a 6. as well as the typical color fields . c.4. V2. a register variable. and tex.y V.a. Vector loads and stores can be used to implement wide loads and stores. mov. . b. ld. The registers in the load/store operations can be a vector. ld.2. a[1]. .g V. Examples are ld.c. Rc.

and data movement instruction must be of the same type and size.5. Operands of different sizes or types must be converted prior to the operation.1.PTX ISA Version 2. except for operations where changing the size and/or type is part of the definition of the instruction. 2010 .0 6.000 for f16). and ~131. logic. the u16 is zero-extended to s32.u16 instruction is given a u16 source operand and s32 as a destination operand. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. Type Conversion All operands to all arithmetic. if a cvt. 6.5. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.s32. For example. 44 January 24.

Notes 1 If the destination register is wider than the destination format. the result is extended to the destination register width after chopping. 2010 45 . For example. The type of extension (sign or zero) is based on the destination format. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.s16. f2s = float-to-signed.u32 targeting a 32-bit register will first chop to 16-bits. January 24. Instruction Operands Table 11. f2u = float-to-unsigned. cvt. s2f = signed-to-float. zext = zero-extend.Chapter 6. f2f = float-to-float. then sign-extend to 32-bits. chop = keep only low bits that fit. u2f = unsigned-to-float.

Table 12.rm . Modifier .5. there are four integer rounding modifiers and four floating-point rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rzi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rz .0 6.PTX ISA Version 2.rni . The following tables summarize the rounding modifiers.rmi .rn . Modifier . Rounding Modifiers Conversion instructions may specify a rounding modifier.rpi Integer Rounding Modifiers Description round to nearest integer. choosing even integer if source is equidistant between two integers. In PTX.2. 2010 .

Much of the delay to memory can be hidden in a number of ways. Operand Costs Operands from different state spaces affect the speed of an operation. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. first access is high Notes January 24.Chapter 6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Table 14. The register in a store operation is available much more quickly. Table 11 gives estimates of the costs of using different kinds of memory.6. Registers are fastest. Instruction Operands 6. 2010 47 . Another way to hide latency is to issue the load instructions as early as possible. while global memory is slowest.

PTX ISA Version 2. 2010 .0 48 January 24.

and return values may be placed directly into register variables. 7. Function declarations and definitions In PTX. execution of the call instruction transfers control to foo. NOTE: The current version of PTX does not implement the underlying. In this section. These include syntax for function definitions. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. } … call foo. stack layout. we describe the features of PTX needed to achieve this hiding of the ABI. 2010 49 . the function name. or prototype. Abstracting the ABI Rather than expose details of a particular calling convention. The simplest function has no parameters or return values. implicitly saving the return address. and Application Binary Interface (ABI). January 24. Scalar and vector base-type input and return parameters may be represented simply as register variables. Execution of the ret instruction within foo transfers control to the instruction following the call. A function definition specifies both the interface and the body of the function.1.Chapter 7. and memory allocated on the stack (“alloca”).func directive. and is represented in PTX as follows: . together these specify the function’s interface. … Here. support for variadic functions (“varargs”). arguments may be register variables or constants. A function must be declared or defined prior to being called. and an optional list of input parameters.func foo { … ret. At the call. so recursion is not yet supported. A function declaration specifies an optional list of return parameters. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. parameter passing. function calls. functions are declared and defined using the . stack-based ABI.

param space memory. [y+11].u32 %inc ) { add.reg space.c1. st.f64 field are aligned. py).reg . note that .param space variables are used in two ways. %rc2. [y+8]. this structure will be flattened into a byte array. .func (.b8 .param. char c[4].param . %rd. For example. … ld. %ptr. ld.s32 out) bar (.param. … In this example. . c3.u32 %ptr. [y+0]. In PTX. inc_ptr.param.reg .b8 c2. %rc2.param . (%x. ld.reg . st. ld. [y+10].param.0 Example: .u32 %res. c2. %rc1. %rc1.f64 f1.reg . ld. }.b8 [py+10].b8 c4.b8 c1. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param variable y is used in function definition bar to represent a formal parameter. bumpptr. Since memory accesses are required to be aligned to a multiple of the access size.b8 c3. st. 50 January 24. (%r1. a . %inc. consider the following C structure.param.param.b64 [py+ 0]. … … // computation using x. } { . ret.f1.PTX ISA Version 2. .b8 [py+ 9].func (.param state space is used to pass the structure by value: . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . … st.f64 f1.u32 %res) inc_ptr ( . passed by value to a function: struct { double dbl. Second.b8 [py+11].c4.reg . } … call (%r1).param. First. a . 2010 .align 8 py[12].4).param space call (%out).param.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. The . byte array in .reg .b8 [py+ 8].param.align 8 y[12]) { . // scalar args in . st.c3. [y+9].reg .param.b8 .c2.s32 x.b32 c1. c4.

Note that the choice of . In the case of . • • • For a callee. or a constant that can be represented in the type of the formal parameter.param arguments. or 16 bytes.param space formal parameters that are byte arrays. 2010 51 .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. For a caller. Parameters in . • The . and alignment.reg state space in this way provides legacy support.reg or .param or . In the case of . • • Arguments may be .param instructions used for argument passing must be contained in the basic block with the call instruction. Supporting the . A . January 24. or constants.param state space use in device functions. The following restrictions apply to parameter passing. This enables backend optimization and ensures that the .reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. The . Abstracting the ABI The following is a conceptual way to think about the . a .param space formal parameters that are base-type scalar or vector variables. all st.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. the argument must also be a . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. 2.param byte array is used to collect together fields of a structure being passed by value. the corresponding argument may be either a . size. The . For a caller. For a callee. For . • The .param variables.reg space formal parameters.g.param argument must be declared within the local scope of the caller. 8.param or .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. size. In the case of .param space byte array with matching type.Chapter 7. the corresponding argument may be either a . Typically.param variables or .reg state space can be used to receive and return base-type scalar and vector values. 4. . and alignment of parameters.param memory must be aligned to a multiple of 1. or a constant that can be represented in the type of the formal parameter.param state space is used to receive parameter values and/or pass return values back to the caller.reg space variable with matching type and size..reg space variable of matching type and size. • • • Input and return parameters may be .reg variables.param and ld.

reg or .reg state space. PTX 2.0. 2010 .1.1.x supports multiple return values for this purpose. formal parameters may be in either .0 7.0 continues to support multiple return registers for sm_1x targets. In PTX ISA version 2. For sm_2x targets.param state space.x.x In PTX ISA version 1. and there was no support for array parameters.0 restricts functions to a single return value. and . Objects such as C structures were flattened and passed or returned using multiple registers. and a . PTX 1. PTX 2. formal parameters were restricted to . Changes from PTX 1.param byte array should be used to return objects that do not fit into a register. 52 January 24.param space parameters support arrays.PTX ISA Version 2.

… %va_start returns Loop: @p Done: January 24. max.h and varargs.s32 result ) maxN ( . 4).s32 val. bra Done. maxN.reg . 4.u32 a. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . In PTX.u32 ap. ) { .reg . Abstracting the ABI 7. (2. N. Once all arguments have been processed. 0x8000000.reg .reg . (ap.reg . 2. %va_start. setp.reg . ctr. for %va_arg64.func (. bra Loop. . along with the size and alignment of the next data value to be accessed.reg .u32 sz. ..func ( . . result. (ap).Chapter 7. %va_arg.b32 ctr.u32 b. Variadic functions NOTE: The current version of PTX does not support variadic functions. To support functions with a variable number of arguments. and end access to a list of variable arguments. or 4 bytes. %s1. ctr. 2.2.h headers in C. . (3. ret. 8. .reg . val.u32 align) . iteratively access.reg .reg . 2010 53 . } … call (%max). For %va_arg. This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg . 4. %s2). variadic functions are declared with an ellipsis at the end of the input parameter list.func %va_end (.reg . 4. … ) . %r1.func (. %r3). // default to MININT mov. or 8 bytes.u32 sz. PTX provides a high-level mechanism similar to the one provided by the stdarg.u32 N.b32 val) %va_arg (. call (val).reg . call %va_end. The function prototypes are defined as follows: . In both cases. or 16 bytes.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. . the alignment may be 1. . call (ap).func (.u32 ptr) %va_start .pred p..b64 val) %va_arg64 (. mov. the size may be 1. .s32 result.u32 ptr. following zero or more fixed parameters: .func baz ( . maxN.b32 result. the size may be 1. … call (%max).reg .ge p.u32.func okay ( … ) Built-in functions are provided to initialize.u32 align) .reg .u32 ptr. 0. %r2. 2. %va_end is called to free the variable argument list handle.reg .reg .

PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.reg . 54 January 24. Alloca NOTE: The current version of PTX does not support alloca. To allocate memory.u32 ptr ) %alloca ( .reg .3.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.0 7.local instructions. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. The array is then accessed with ld. If a particular alignment is required. 2010 . a function simply calls the built-in function %alloca.func ( . defined as follows: .PTX ISA Version 2.local and st.

setp. 8. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. 2010 55 . A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. We use a ‘|’ symbol to separate multiple destination registers.2. For some instructions the destination operand is optional.1. B. opcode D. Instruction Set 8. In addition to the name and the format of the instruction. The setp instruction writes two destination registers. opcode A. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. B. while A. PTX Instructions PTX instructions generally have from zero to four operands. A. // p = (a < b). A. q = !(a < b). A.s32. B. the D operand is the destination operand. a.Chapter 8. opcode D. and C are the source operands. January 24. opcode D. followed by some examples that attempt to show several possible instantiations of the instruction. For instructions that create a result value. b. the semantics are described.lt p|q. C.

To implement the above example as a true conditional branch. Instructions without a guard predicate are executed unconditionally.PTX ISA Version 2. optionally negated.s32 p.lt.lt. predicate registers can be declared as .pred p. add. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. 1. add 1 to j To get a conditional branch or conditional function call. q.3. i. branch over 56 January 24. 1. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. n.reg . This can be written in PTX as @p setp. j. 2010 . n. where p is a predicate variable. So. i. … // compare i to n // if false. As an example. j.pred as the type specifier.s32 p. the following PTX instruction sequence might be used: @!p L1: setp. add. use a predicate to control the execution of the branch or call instructions.s32 j. predicate registers are virtual and have .s32 j. bra L1. // p = (i < n) // if i < n.0 8. Predicates are most commonly set as the result of a comparison performed by the setp instruction. consider the high-level code if (i < n) j = j + 1. Predicated Execution In PTX.

gt. lt (less-than). ne. If either operand is NaN. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). The unsigned comparisons are eq. unsigned integer. le. le (less-than-or-equal). Table 16. Unsigned Integer. ge. ls (lower-or-same). Table 15. and hs (higher-or-same).2. lo (lower). Instruction Set 8. Comparisons 8. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. lt. The following table shows the operators for signed integer. and ge (greater-than-or-equal).1. gt (greater-than). The bit-size comparisons are eq and ne. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ne. ne (not-equal).3.3. ordering comparisons are not defined for bit-size types. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.Chapter 8.1. and bitsize types. 2010 57 .1.1. hi (higher).3. the result is false. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.

Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.PTX ISA Version 2. two operators num (numeric) and nan (isNaN) are provided.2. unordered versions are included: equ. and nan returns true if either operand is NaN. and mov. If both operands are numeric values (not NaN). num returns true if both operands are numeric values (not NaN). neu. for example: selp. Table 17. However. geu. If either operand is NaN. Table 18. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. ltu. not. or.1.0. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. xor. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. then these comparisons have the same result as their ordered counterparts.3. setp can be used to generate a predicate from an integer. 2010 .0 To aid comparison operations in the presence of NaN values.%p. gtu. and no direct way to load or store predicate register values. then the result of these comparisons is true. There is no direct conversion between predicates and integer values. // convert predicate to 32-bit value 58 January 24.u32 %r1. leu.

Type Checking Rules Operand Type . and this information must be specified as a suffix to the opcode. the add instruction requires type and size information to properly perform the addition operation (signed. Table 19. b. Example: .e.reg .reg . 2010 59 .uX ok ok ok inv . Floating-point types agree only if they have the same size. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. For example.bX . • The following table summarizes these type checking rules. . and these are placed in the same order as the operands. they must match exactly. a. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 d.u16 a.fX ok ok ok ok January 24. Instruction Set 8.u16 d. unsigned. different sizes). The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Signed and unsigned integer types agree provided they have the same size. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. It requires separate type-size modifiers for the result and source. b. a.sX ok ok ok inv .f32. a. For example. i.u16 d. float. add. cvt. and integer operands are silently cast to the instruction type if needed.f32 d. For example: .Chapter 8..bX . most notably the data conversion instruction cvt.sX .uX . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.reg .fX ok inv inv ok Instruction Type .4.

1. The data is truncated to the instruction-type size and interpreted according to the instruction type. 4. the size must match exactly. so those rows are invalid for cvt. 2. Note that some combinations may still be invalid for a particular instruction.4. the data will be truncated.0 8. Floating-point source registers can only be used with bit-size or floating-point instruction types. for example. For example. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. When used with a narrower bit-size type. stored. st. so that narrow values may be loaded. The following table summarizes the relaxed type-checking rules for source operands. When used with a floating-point instruction type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. 1. Table 20. inv = invalid.bX instruction types. floating-point instruction types still require that the operand type-size matches exactly. and converted using regular-width registers. parse error. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Source register size must be of equal or greater size than the instruction-type size. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.PTX ISA Version 2. Operand Size Exceeding Instruction-Type Size For convenience. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Notes 3. no conversion needed. “-“ = allowed. unless the operand is of bit-size type. When a source operand has a size that exceeds the instruction-type size. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. 60 January 24. ld. stored. the cvt instruction does not support . or converted to other types and sizes. 2010 . Bit-size source registers may be used with any appropriately-sized instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.

the size must match exactly. January 24. parse error. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the data is sign-extended. “-“ = Allowed but no conversion needed. otherwise. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Bit-size destination registers may be used with any appropriately-sized instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size. When used with a narrower bit-size instruction type. the destination data is zero. Table 21. inv = Invalid. The following table summarizes the relaxed type-checking rules for destination operands. Notes 3.or sign-extended to the size of the destination register. 1. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. When used with a floatingpoint instruction type. Destination register size must be of equal or greater size than the instruction-type size. the data is zeroextended. and is zero-extended to the destination register width otherwise. 2010 61 .Chapter 8. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. zext = zero-extend. The data is signextended to the destination register width for signed integer instruction types. The data is sign-extended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer. 4. 2. the data will be zero-extended.

This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. the semantics of 16-bit instructions in PTX is machine-specific. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. Divergence of Threads in Control Constructs Threads in a CTA execute together.PTX ISA Version 2.0 8. this is not desirable. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. until C is not expressive enough. The semantics are described using C. If threads execute down different control flow paths. 62 January 24. 2010 . for many performance-critical applications. so it is important to have divergent threads re-converge as soon as possible. When executing on a 32-bit data path. until they come to a conditional control construct such as a conditional branch.5. If all of the threads act in unison and follow a single control flow path. a compiler or code author targeting PTX can ignore the issue of divergent threads. the threads are called divergent. For divergent control flow. conditional function call. by a right-shift instruction. using the . Both situations occur often in programs. 8. 8. Therefore. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. A compiler or programmer may chose to enforce portable. the optimizing code generator automatically determines points of re-convergence.6. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. at least in appearance. or conditional return.1. However. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers.uni suffix. These extra precision bits can become visible at the application level. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path.6. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. 16-bit registers in PTX are mapped to 32-bit physical registers. and 16-bit computations are “promoted” to 32-bit computations. the threads are called uniform. for example. and for many applications the difference in execution is preferable to limiting performance. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. At the PTX language level.

Chapter 8. Instructions All PTX instructions may be predicated. 2010 63 . The Integer arithmetic instructions are: add sub add.cc. 8.7. the optional guard predicate is omitted from the syntax. addc sub.1. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.cc. In the following descriptions. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8.7.

// .y. . b.s64 }.sat.sat}.0 Table 22. . a.0. add. . Applies only to . .sat applies only to . Supported on all target architectures.u32 x.z. d = a – b.u32.sat applies only to .s32 type.0. Description Semantics Notes Performs addition and writes the resulting value into a destination register. d. @p add. . add.u64. a.b. Introduced in PTX ISA version 1. . sub. PTX ISA Notes Target ISA Notes Examples 64 January 24. .u16. // . b. .sat limits result to MININT. Introduced in PTX ISA version 1. sub.s64 }.u32. PTX ISA Notes Target ISA Notes Examples Table 23.s32 d.sat limits result to MININT. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.type sub{.sat}.1.. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. Saturation modifier: .s32 .s32 .type = { . b.PTX ISA Version 2. a.s32 c. add Syntax Integer Arithmetic Instructions: add Add two values. d = a + b.s32.c. 2010 . Applies only to .s32.s32 d.. Saturation modifier: . d.a. .MAXINT (no overflow) for the size of the operation.type = { . Supported on all target architectures.s32 c.s16.type add{.MAXINT (no overflow) for the size of the operation.s32 type.u16. a.s16. b.u64. .

z2. x4. sub.b32 addc. addc{.cc. Instruction Set Instructions add.b32 addc.cc. Supported on all target architectures.y4. Supported on all target architectures.z2. d = a + b + CC.cc.z1.z3.y1. No saturation. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.y2.cc. x3. x2.b32 addc.y3.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.b32 x1. .s32 }.z4. @p @p @p @p add.u32.type d. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. or testing the condition code. No other instructions access the condition code. Introduced in PTX ISA version 1.Chapter 8.z4.cc.b32 x1.cc.cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.z1. clearing.cc.y2.CF No integer rounding modifiers.b32 addc. Table 24.CF.y4. These instructions support extended-precision integer addition and subtraction.y1. and there is no support for setting. No saturation. b.CF No integer rounding modifiers.type d.y3. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. b.cc Syntax Integer Arithmetic Instructions: add. @p @p @p @p add.2.cc Add two values with carry-out.b32 addc.type = { .cc specified.type = {. addc. carry-out written to CC.z3.u32. . x3. Behavior is the same for unsigned and signed integers. x2. d = a + b.cc. . . add. carry-out written to CC. Introduced in PTX ISA version 1.CF) holding carry-in/carry-out or borrowin/borrow-out. a. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. x4.b32 addc. if .s32 }. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc. Behavior is the same for unsigned and signed integers. add.cc}. a.2. 2010 65 .

3.s32 }.cc.cc.y1.z1.z3.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. b.z4. withborrow-in and optional borrow-out. .cc.cc. d = a . b. Introduced in PTX ISA version 1. sub. No saturation.cc.u32.0 Table 26. if .b32 x1.y4.b32 subc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.y4. @p @p @p @p sub.(b + CC.cc Syntax Integer Arithmetic Instructions: sub. Behavior is the same for unsigned and signed integers. subc{.cc Subract one value from another. Introduced in PTX ISA version 1.type = {.y2. x3.y2.y1.3. .u32.type d. No saturation.y3.cc.cc specified. Supported on all target architectures. a. x3. d = a – b.b32 subc. x2. x4.b32 x1. x2.s32 }.z4.z3.cc.type = { . Behavior is the same for unsigned and signed integers.cc.CF No integer rounding modifiers. . 2010 .b32 subc.cc. x4.y3. a. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.z2. borrow-out written to CC. borrow-out written to CC.CF).PTX ISA Version 2.z1. . sub. @p @p @p @p sub.CF No integer rounding modifiers.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.type d.cc}. Supported on all target architectures.z2. with borrow-out. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.b32 subc.

. Instruction Set Table 28. .u32.n>.fxs. b. If . then d is the same size as a and b.y. Description Semantics Compute the product of two values.hi or .hi variant // for .s64 }. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.wide. a..lo is specified. The ..wide}. .lo. then d is twice as wide as a and b to receive the full result of the multiplication.type = { .fys.lo variant Notes The type of the operation represents the types of the a and b operands.x.and 32-bit integer types.wide // for . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul.s32.type d. ..wide suffix is supported only for 16.s16. creates 64 bit result January 24.s16 fa. save only the low 16 bits // 32*32 bits. . n = bitwidth of type. 2010 67 .u64. If . // for .lo..wide is specified. .fxs. mul{.fys. and either the upper or lower half of the result is written to the destination register. mul.wide. mul. t = a * b.hi.u16.0. d = t. d = t<n-1.s16 fa.Chapter 8. // 16*16 bits yields 32 bits // 16*16 bits.0>. d = t<2n-1. Supported on all target architectures.s32 z.

. t<2n-1.. The .u32. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.lo variant Notes The type of the operation represents the types of the a and b operands.s32. t n d d d = = = = = a * b.hi.a.b.. then d and c are the same size as a and b.0> + c. mad.p. c. d.sat.hi variant // for .q. c. .wide suffix is supported only for 16. 2010 .wide is specified. mad{.c. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 68 January 24.lo is specified. b. and either the upper or lower half of the result is written to the destination register. . .s32 type in .s32 d.wide // for . Supported on all target architectures. If . then d and c are twice as wide as a and b to receive the result of the multiplication. Description Semantics Multiplies two values and adds a third. Applies only to . .PTX ISA Version 2. and then writes the resulting value into a destination register.s32 d.type = { . @p mad. // for . a.s32 r. If .hi or .0.lo.MAXINT (no overflow) for the size of the operation. bitwidth of type. t + c.type mad..r.s64 }.s16.sat limits result to MININT.lo.lo. a.u16. t<n-1. Saturation modifier: .hi. . b.hi mode.0 Table 29.wide}.u64.n> + c. ..and 32-bit integer types.

type = { .hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. .hi may be less efficient on machines without hardware support for 24-bit multiply. Instruction Set Table 30. i. d = t<47. mul24{...s32 }. b.0.a.hi variant // for . d = t<31. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. .0>. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.Chapter 8.b.16>. January 24.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. a.s32 d. Supported on all target architectures.u32.lo}.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. // low 32-bits of 24x24-bit signed multiply.lo. mul24. 2010 69 . 48bits. and return either the high or low 32-bits of the 48-bit result. mul24. All operands are of the same type and size.hi. // for .e. mul24.. t = a * b.type d. mul24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

. Description Compute the product of two 24-bit integer values held in 32-bit source registers. // for .hi mode.a.hi.. mad24.s32 }.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.s32 type in .sat. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.lo.s32 d.MAXINT (no overflow). . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. i. 70 January 24.s32 d. 2010 .sat limits result of 32-bit signed addition to MININT. . // low 32-bits of 24x24-bit signed multiply. d. c. All operands are of the same type and size. d = t<31.hi may be less efficient on machines without hardware support for 24-bit multiply.PTX ISA Version 2.u32.. Applies only to .b.. mad24. 48bits. c.hi.0 Table 31. Return either the high or low 32-bits of the 48-bit result.16> + c. 32-bit value to either the high or low 32-bits of the 48-bit result. d = t<47.c.0. Supported on all target architectures. mad24.lo}. a. mad24{. Saturation modifier: .lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. mad24. b. a.0> + c.hi variant // for .type = { .e. and add a third. b. t = a * b.type mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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a. inclusively.b32.PTX ISA Version 2. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. cnt. X.b64 d. if (.b64 }. clz. 2010 . // cnt is .type d.b64 type.b32) { max = 32.b32 clz. } else { max = 64.b64 }.b64 d. a. mask = 0x80000000. . popc. a. cnt.type = { . // cnt is .b32 popc. popc Syntax Integer Arithmetic Instructions: popc Population count. mask = 0x8000000000000000. inclusively.u32 Semantics 74 January 24. clz.0. d = 0. . X.b32 type. a = a << 1. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.type == . For .b32. . popc. the number of leading zeros is between 0 and 64. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. For . a = a >> 1. popc requires sm_20 or later.type d. the number of leading zeros is between 0 and 32. clz requires sm_20 or later.type = { . } Introduced in PTX ISA version 2.0 Table 39. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. d = 0. . a. while (a != 0) { if (a&0x1) d++.u32 PTX ISA Notes Target ISA Notes Examples Table 40. } while (d < max && (a&mask == 0) ) { d++.0.

type bfind. and operand d has type . If .s64 cnt. i>=0. } } if (.u32 January 24. .shiftamt is specified. break.shiftamt. a.shiftamt. bfind returns the bit position of the most significant “1”.u32 d.s32) ? 31 : 63.d. Semantics msb = (.u32.type==. i--) { if (a & (1<<i)) { d = i. for (i=msb. . d = -1.type = { . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. 2010 75 . Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind. . Instruction Set Table 41. // cnt is .s64 }. d. Operand a has the instruction type. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shiftamt && d != -1) { d = msb . a. bfind returns 0xFFFFFFFF if no non-sign bit is found.u32 || . a.u64.Chapter 8.s32. bfind requires sm_20 or later. X. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. bfind.0. bfind. For unsigned integers.type d.type==.u32. For signed integers. .

brev requires sm_20 or later. Description Semantics Perform bitwise reversal of input. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. msb = (.0.type d.b32) ? 31 : 63. a.0 Table 42. for (i=0. a. 2010 . 76 January 24. . brev.PTX ISA Version 2. i<=msb. i++) { d[i] = a[msb-i].type==.b32 d.type = { .b32. .b64 }. brev.

The destination d is padded with the sign bit of the extracted field. and source c gives the bit field length in bits.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. for (i=0. 2010 77 . d = 0.start. Operands a and d have the same type as the instruction type.s32) ? 31 : 63.type==.u32. if (. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .s64 }. January 24. Instruction Set Table 43. the destination d is filled with the replicated sign bit of the extracted field. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.u32 || .s32. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. a.type==. bfe.msb)]. Source b gives the bit field starting bit position. len = c.u64: . . c. i<=msb. bfe requires sm_20 or later.u32 || .u32.u32. else sbit = a[min(pos+len-1.type==. Description Extract bit field from a and place the zero or sign-extended result in d.Chapter 8.s32. . The sign bit of the extracted field is defined as: .b32 d.u64 || len==0) sbit = 0.type==.0. the result is zero.len. bfe. . If the start position is beyond the msb of the input. pos = b. otherwise If the bit field length is zero. b.a. . Semantics msb = (.type d.type = { . . and operands b and c are type .u64.

b32) ? 31 : 63. b. the result is b. i++) { f[pos+i] = a[i]. a. f = b.b32 d.b32. Semantics msb = (. d. len = d.0.b. . pos = c. bfi. and source d gives the bit field length in bits. for (i=0. c. Description Align and insert a bit field from a into b.len. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. If the bit field length is zero. Operands a.u32. 2010 . and operands c and d are type . and f have the same type as the instruction type. and place the result in f. bfi.type = { . . the result is b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If the start position is beyond the msb of the input.a.0 Table 44.PTX ISA Version 2. b.type==. i<len && pos+i<=msb. 78 January 24.start.type f. bfi requires sm_20 or later.b64 }. Source c gives the starting bit position for the insertion.

rc8.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. b0}}.b1 source select c[7:4] d.ecr. as a 16b permute code. {b3.ecl. c. In the generic form (no mode specified). default mode index d. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). prmt.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. For each byte in the target register. msb=0 means copy the literal value. . Instruction Set Table 45. . b. Note that the sign extension is only performed as part of generic form. . msb=1 means replicate the sign. the permute control consists of four 4-bit selection values. .mode = { . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. Thus. The msb defines if the byte value should be copied. b5. a 4-bit selection value is defined. The bytes in the two source registers are numbered from 0 to 7: {b.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. 2010 79 . Description Pick four arbitrary bytes from two 32-bit registers.f4e. b6.b4e.mode} d. b2.b3 source select c[15:12] d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. a. the four 4-bit values fully specify an arbitrary byte permute. .Chapter 8. a} = {{b7.b2 source select c[11:8] d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b32{. b1. b4}.rc16 }. and reassemble them into a 32-bit destination register.

ctl[0]. tmp[23:16] = ReadByte( mode. tmp64 ). r3. tmp[15:08] = ReadByte( mode. tmp[31:24] = ReadByte( mode.PTX ISA Version 2. 80 January 24.b32 prmt. 2010 . prmt requires sm_20 or later. r3. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.f4e r1. r1.b32. ctl[3] = (c >> 12) & 0xf. tmp64 ).0 Semantics tmp64 = (b<<32) | a. r2. ctl[1] = (c >> 4) & 0xf. ctl[1]. r4. ctl[3]. prmt. r4. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[2]. ctl[2] = (c >> 8) & 0xf. } tmp[07:00] = ReadByte( mode.0. tmp64 ). r2. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3.

f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on .2.f32 and . 2010 81 . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Instruction Set 8.7.Chapter 8.

rnd.mul}.ftz .f32 {div.rnd.fma}.f32 {abs.rp .ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. with NaNs being flushed to positive zero.sat Notes If no rounding modifier is specified.f64 and fma. mul.rcp.sqrt}.rcp.f32 rsqrt. 2010 . The optional .f64 {sin.neg. .f32 {div.f64 div.sub.rn and instructions may be folded into a multiply-add.32 and fma.rn and instructions may be folded into a multiply-add.fma}.0. Note that future implementations may support NaN payloads for single-precision instructions. so PTX programs should not rely on the specific single-precision NaNs being generated.approx.rcp.neg.0].min. but single-precision instructions return an unspecified NaN. . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. default is . Single-precision add.rnd.approx.lg2. sub.full.PTX ISA Version 2.target sm_20 mad.min.rnd. and mad support saturation of results to the range [0. No rounding modifier.f64 mad.cos.f32 {mad.approx.rn . Table 46.mul}. NaN payloads are supported for double-precision instructions.f32 {div.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. {mad.sqrt}.approx.ex2}. Instruction Summary of Floating-Point Instructions .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. 82 January 24.f64 are the same.rz .sub.f32 .target sm_20 .f32 are the same. Double-precision instructions support subnormal inputs and results.max}.rm .max}. If no rounding modifier is specified. {add.sqrt}.rnd.rnd.0 The following table summarizes floating-point instructions in PTX. default is .target sm_1x No rounding modifier. 1.f64 {abs.f64 rsqrt.f32 {add.

normal testp. b. 2010 83 .f64 x. Introduced in PTX ISA version 2.type = { . testp.op. .0.finite. z. January 24. .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.type = { .notanumber.infinite testp. Table 48.notanumber. testp Syntax Floating-Point Instructions: testp Test floating-point property. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. y.infinite.pred = { .Chapter 8.number.infinite. . B.f32 testp. .f32. testp. copysign requires sm_20 or later.0. a.normal.f64 }. copysign. not infinity) As a special case. C.number testp. copysign. . true if the input is a subnormal number (not NaN.op p. and return the result as d. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.type d.subnormal }. .notanumber testp.f32 copysign. testp. . p. f0. testp requires sm_20 or later. Instruction Set Table 47.type . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. X.f32.f64 }. a. positive and negative zero are considered normal numbers. A. // result is .finite testp. not infinity). . . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.f64 isnan.

0. .rz. 1.rn.sat}. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn): .rm. add{.f32 flushes subnormal inputs and results to sign-preserving zero.PTX ISA Version 2. b.f64 requires sm_13 or later. 2010 .f2. add.f32 f1.ftz}{.rm mantissa LSB rounds towards negative infinity .rz available for all targets .rz. NaN results are flushed to +0. add. a. sm_1x: add.rz mantissa LSB rounds towards zero .ftz. .rp for add.0f.rn mantissa LSB rounds to nearest even . requires sm_13 for add.f64 d. subnormal numbers are supported. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 add{. . 84 January 24.rnd}{.rn. . . Rounding modifiers (default is . add.f32 flushes subnormal inputs and results to sign-preserving zero. b. d = a + b. requires sm_20 Examples @p add.f3. a.rm. In particular.f64. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.0.f32. Rounding modifiers have the following target requirements: .rp }.ftz.sat.f64 supports subnormal numbers.f32 clamps the result to [0. add. add Syntax Floating-Point Instructions: add Add two values.rnd}.0].0 Table 49.f32 supported on all target architectures. Saturation modifier: . d. add. .rnd = { .

b. requires sm_20 Examples sub.b.rnd}{.rm. sub.f32 flushes subnormal inputs and results to sign-preserving zero.0].ftz. 2010 85 . sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers (default is . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_13 for sub.f32 flushes subnormal inputs and results to sign-preserving zero.sat.f32.rn. Saturation modifier: sub.f64.f3.rn mantissa LSB rounds to nearest even . . .rn. . January 24.f64 requires sm_13 or later. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0. sm_1x: sub. d.f32 c. Instruction Set Table 50.rm. .0.rnd = { . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f32 supported on all target architectures.f2. NaN results are flushed to +0.ftz. sub Syntax Floating-Point Instructions: sub Subtract one value from another. subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 sub{.Chapter 8.f64 supports subnormal numbers.f64 d. In particular.rp for sub.rz mantissa LSB rounds towards zero .rz available for all targets . sub.rp }.f32 clamps the result to [0. sub.f32 f1. sub{.sat}.ftz}{.rn. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. d = a . . sub.a.rnd}.rm mantissa LSB rounds towards negative infinity .b. Rounding modifiers have the following target requirements: . 1. b.rn): . a.0f. a. .rz.

rm. b. . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. 2010 .0. subnormal numbers are supported.rn. mul. sm_1x: mul. requires sm_13 for mul. requires sm_20 Examples mul.sat}. .f64 d.f32 mul{. . A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0 Table 51. mul{. mul.rn): .rz mantissa LSB rounds towards zero . mul.radius. For floating-point multiplication.0.f32. .rnd}{.0].rn. a. d = a * b.rm.PTX ISA Version 2. . d.ftz.rp for mul. b. a. In particular.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0.pi // a single-precision multiply 86 January 24.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat.f32 supported on all target architectures. NaN results are flushed to +0. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . all operands must be the same size. Saturation modifier: mul.ftz}{. mul.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero.rp }.rn mantissa LSB rounds to nearest even . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.f32 circumf.f64.ftz. Description Semantics Notes Compute the product of two values.f64 requires sm_13 or later.rz. Rounding modifiers (default is . 1. mul Syntax Floating-Point Instructions: mul Multiply two values.rz available for all targets .rnd}. Rounding modifiers have the following target requirements: .0f.rm mantissa LSB rounds towards negative infinity .f64 supports subnormal numbers.

rnd{.f64 w. d = a*b + c. fma.f32 requires sm_20 or later. c.rz mantissa LSB rounds towards zero .rp }.0.f32 fma.a. b.f64.rn.f32 introduced in PTX ISA version 2. c. fma. d.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 is unimplemented in sm_1x.ftz.rn mantissa LSB rounds to nearest even . subnormal numbers are supported. sm_1x: fma. again in infinite precision. fma.0f. NaN results are flushed to +0. fma.rnd = { .sat.rnd. The resulting value is then rounded to double precision using the rounding mode specified by .rn.c.x. .rm. Saturation: fma.ftz}{.f64 computes the product of a and b to infinite precision and then adds c to this product.sat}. b.rn. d.f64 d. PTX ISA Notes Target ISA Notes Examples January 24.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.f64 introduced in PTX ISA version 1. Rounding modifiers (no default): . .f32 clamps the result to [0.4. fma.0.Chapter 8.z. Instruction Set Table 52.0]. 2010 87 . a. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd.ftz.f64 supports subnormal numbers.rm mantissa LSB rounds towards negative infinity . fma Syntax Floating-Point Instructions: fma Fused multiply-add. . fma. again in infinite precision. fma.rz. The resulting value is then rounded to single precision using the rounding mode specified by .b. @p fma.y. fma. a.f64 is the same as mad. . fma.rnd. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. fma.f32 fma.

and then writes the resulting value into a destination register. Saturation modifier: mad.0.rz mantissa LSB rounds towards zero . . b. Unlike mad. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. The exception for mad.sat}.0. .rn.0 devices.ftz.rp }. but the exponent is preserved.target sm_13 and later .f32 is when c = +/-0. mad. again in infinite precision.rz. // . b.f32 computes the product of a and b at double precision. subnormal numbers are supported.0].ftz}{.f64 is the same as fma.rnd.f64 computes the product of a and b to infinite precision and then adds c to this product. the treatment of subnormal inputs and output follows IEEE 754 standard. mad.target sm_1x: mad.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0. again in infinite precision. a.target sm_1x d.PTX ISA Version 2.f64}.f64. mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.target sm_20 d. c. and then the mantissa is truncated to 23 bits. a.ftz.f64 supports subnormal numbers.sat}. fma. // . c.rn mantissa LSB rounds to nearest even .f32.rnd.f32).f64 computes the product of a and b to infinite precision and then adds c to this product. NaN results are flushed to +0.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to double precision using the rounding mode specified by . mad. For .target sm_20: mad. In this case. mad{.ftz}{.0 Table 53.e.rm mantissa LSB rounds towards negative infinity . Note that this is different from computing the product with mul. The resulting value is then rounded to single precision using the rounding mode specified by .{f32.0f. Description Semantics Notes Multiplies two values and adds a third. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 mad. Rounding modifiers (no default): . . mad.f32 is implemented as a fused multiply-add (i. 2010 . again in infinite precision.f32 mad.rn.{f32. d = a*b + c. where the mantissa can be rounded and the exponent will be clamped. mad. // . The resulting value is then rounded to double precision using the rounding mode specified by .f64} is the same as fma.rm. For .rnd.f32 computes the product of a and b to infinite precision and then adds c to this product. a.rnd{. sm_1x: mad. c. b. mad.rnd. mad. mad.f32 is identical to the result computed using separate mul and add instructions.f64 d. When JIT-compiled for SM 2. 88 January 24.sat..

rz.rp for mad.0.rm..rp for mad.f64 instructions having no rounding modifier will map to mad.f64. Legacy mad.f64.a..rn.b. requires sm_13 . requires sm_20 Examples @p mad..f64... Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. January 24.f32. 2010 89 . a rounding modifier is required for mad.rz.rm.0 and later.. In PTX ISA versions 2.4 and later.f32 for sm_20 targets. In PTX ISA versions 1. mad. Target ISA Notes mad.rn.f64 requires sm_13 or later. a rounding modifier is required for mad.f32 d.Chapter 8.c. Rounding modifiers have the following target requirements: .f32 supported on all target architectures.rn.

a. div.full. div. y. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .approx.f32. subnormal numbers are supported.f64 d. b.f32 defaults to div.f64 introduced in PTX ISA version 1.ftz.approx{. d.rm.rnd. Fast.f64 diam. one of .f64 supports subnormal numbers. b. div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. PTX ISA Notes div. 2126]. Target ISA Notes div. full-range approximation that scales operands to achieve better accuracy.rz.approx. d = a / b. For PTX ISA versions 1.ftz.4.f32 requires sm_20 or later. and div.rp}. // // // // fast.f32 and div.f64 requires sm_13 or later. .f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. d. x. yd. b.approx.full. b.full.full{. Description Semantics Notes Divides a by b.0 Table 54.3. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . . div.circum. computed as d = a * (1/b).f32 implements a fast approximation to divide. approximate single-precision divides: div.full.f32 and div.rnd{. a.f64 defaults to div. xd.approx.f32 div.f64.rm.0 through 1. sm_1x: div.rn. For b in [2-126.f32 supported on all target architectures. div.f64 requires sm_20 or later. zd.14159. div. the maximum ulp error is 2.PTX ISA Version 2.ftz. .f32 div. Examples 90 January 24.rn.3. approximate division by zero creates a value of infinity (with same sign as a). .f32 div. div.rn.f32 implements a relatively fast.rnd is required.rnd = { . div Syntax Floating-Point Instructions: div Divide one value by another. a.rn. stores result in d. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. d. a. The maximum ulp error is 2 across the full range of inputs. or .f32 div.approx. and rounding introduced in PTX ISA version 1.0.ftz.full. Subnormal inputs and results are flushed to sign-preserving zero. Fast.rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity .rz mantissa LSB rounds towards zero . div. . but is not fully IEEE 754 compliant and does not support rounding modifiers.f32 div.ftz.rnd.ftz}. For PTX ISA version 1. .ftz}.{rz.rp }. div. 2010 . z.4 and later.approx.

neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. Take the absolute value of a and store the result in d.ftz}.f32 supported on all target architectures.f32 x. d.f32 x. abs{. Subnormal numbers: sm_20: By default.f32 supported on all target architectures. neg.f64 d. sm_1x: neg. neg.f32 abs. neg{.ftz. NaN inputs yield an unspecified NaN. Subnormal numbers: sm_20: By default.f32 neg.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. abs. d = |a|. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. neg. Instruction Set Table 55. NaN inputs yield an unspecified NaN. a.ftz.ftz. neg. a. sm_1x: abs.f0.f0.0.f64 supports subnormal numbers. subnormal numbers are supported. abs. abs. subnormal numbers are supported. abs.Chapter 8. abs.ftz}. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. d = -a. 2010 91 . Negate the sign of a and store the result in d. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 supports subnormal numbers.f64 requires sm_13 or later. January 24. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f64 d. neg.f64 requires sm_13 or later. a. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Table 56. d.0.

c.f64 f0.0 Table 57.c.f64 d. (a < b) ? a : b.f64 z.f64 requires sm_13 or later. min{.f64 supports subnormal numbers. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b.f32 supported on all target architectures. a. a. Store the maximum of a and b in d. max. d d d d = = = = NaN.f32 flushes subnormal inputs and results to sign-preserving zero. b. max{. max.f1. d. d. min. max. subnormal numbers are supported. subnormal numbers are supported. b.f2.x.ftz.f32 max. a. a. 92 January 24.f32 flushes subnormal inputs and results to sign-preserving zero. a. min.ftz}. a.f32 max. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.b. @p min.f64 d. sm_1x: min.ftz. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later. Table 58.f32 supported on all target architectures.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. Store the minimum of a and b in d. (a > b) ? a : b.f64 supports subnormal numbers.0. 2010 . b.ftz}. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. b.f32 min. d d d d = = = = NaN. a.f32 min. max. b. max. min.ftz.z. sm_1x: max. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f32 flushes subnormal inputs and results to sign-preserving zero.b. min.

rnd{.0-2.f32 and rcp. rcp.f32 rcp.ftz}. subnormal numbers are supported. d = 1 / a.x.rnd is required.approx. rcp.ftz.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . store result in d.f32 implements a fast approximation to reciprocal. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f32 defaults to rcp.f64. rcp.approx. d. xi.f32 flushes subnormal inputs and results to sign-preserving zero.rn.f32 supported on all target architectures. a.3.rnd.approx and .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. rcp.rn.4 and later.approx. a. Examples January 24.ftz.f32 rcp.f32 rcp.approx. rcp.f32 rcp.r.rm.f64 introduced in PTX ISA version 1.0 -Inf -Inf +Inf +Inf +0. . and rcp. Instruction Set Table 59.rn.x.ftz were introduced in PTX ISA version 1.0. For PTX ISA version 1. Description Semantics Notes Compute 1/a. rcp.ftz. sm_1x: rcp. rcp. 2010 93 .f64 requires sm_20 or later.0 through 1. PTX ISA Notes rcp. d.f64 ri. Target ISA Notes rcp.rn. // fast. For PTX ISA versions 1.0 +subnormal +Inf NaN Result -0. rcp.f32. General rounding modifiers were added in PTX ISA version 2. rcp.rp }.rn mantissa LSB rounds to nearest even .ftz}. one of .rp}. .rnd = { . approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 defaults to rcp.f64 supports subnormal numbers.f32 requires sm_20 or later.rn.rm mantissa LSB rounds towards negative infinity .0 +0.rn. rcp.approx or .rnd.approx{.rz mantissa LSB rounds towards zero .0 over the range 1.f64 requires sm_13 or later. a.rm. The maximum absolute error is 2-23. .4.0.Chapter 8.{rz.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.f64 and explicit modifiers . xi.0.rz. Input -Inf -subnormal -0.

f32 sqrt.rn mantissa LSB rounds to nearest even . subnormal numbers are supported.approx or . r.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt. r.rn. one of . sqrt.4.f32 supported on all target architectures.rz.f64 supports subnormal numbers.f64 defaults to sqrt.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.0 through 1.f64. sqrt. sqrt.0 +0.ftz}.0 -0.rp}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.approx{. Input -Inf -normal -subnormal -0.rnd{. // IEEE 754 compliant rounding d. // IEEE 754 compliant rounding . sqrt.rn.approx and .0.4 and later. For PTX ISA versions 1. store in d.f32 sqrt.rm.rm mantissa LSB rounds towards negative infinity .0 +subnormal +Inf NaN Result NaN NaN -0.ftz were introduced in PTX ISA version 1. Examples 94 January 24.0 Table 60.approx.f64 requires sm_13 or later. General rounding modifiers were added in PTX ISA version 2. .approx.x.{rz.0 +0.ftz.rn.rn.f64 d.rnd = { .f64 requires sm_20 or later.approx.f32 sqrt.f32 and sqrt.f64 r.f32 is TBD.approx. sqrt.rnd. Target ISA Notes sqrt.f64 introduced in PTX ISA version 1. a.f32.ftz.ftz.x. a.x. // fast.f32 defaults to sqrt.0. PTX ISA Notes sqrt.f32 requires sm_20 or later.PTX ISA Version 2.rn.rnd is required.rnd.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 .rm. sqrt. sm_1x: sqrt. d = sqrt(a). approximate square root d.0 +0.ftz.f32 sqrt.rz mantissa LSB rounds towards zero .3. sqrt. .f64 and explicit modifiers . and sqrt. a. For PTX ISA version 1. The maximum absolute error for sqrt. sqrt. Description Semantics Notes Compute sqrt(a). .ftz}.rp }.approx.f32 implements a fast approximation to square root. sqrt.

rsqrt.f64 were introduced in PTX ISA version 1. January 24.0 NaN The maximum absolute error for rsqrt.0.f64 d.approx{.ftz.f64 isr.f32.ftz. rsqrt.0-4.0 through 1. Target ISA Notes Examples rsqrt. d = 1/sqrt(a).approx.0.f32 and rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.ftz. a.approx and .f32 flushes subnormal inputs and results to sign-preserving zero.approx. For PTX ISA version 1.approx implements an approximation to the reciprocal square root. Instruction Set Table 61.f32 supported on all target architectures.Chapter 8. rsqrt.4.f64 supports subnormal numbers. rsqrt.4 over the range 1.f64 defaults to rsqrt. and rsqrt.f32 rsqrt. a.approx.4 and later.f32 is 2-22. subnormal numbers are supported.ftz were introduced in PTX ISA version 1.f64.3. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. X. For PTX ISA versions 1. PTX ISA Notes rsqrt. sm_1x: rsqrt.approx.f32 rsqrt.f64 is emulated in software and are relatively slow.ftz}. store the result in d.approx. d. ISR. rsqrt. Subnormal numbers: sm_20: By default. Input -Inf -normal -subnormal -0. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt. 2010 95 . the .f64 is TBD. Note that rsqrt. rsqrt.approx. Compute 1/sqrt(a). x.f64 requires sm_13 or later.f32 defaults to rsqrt.0 +0. The maximum absolute error for rsqrt.approx modifier is required.

4 and later. subnormal numbers are supported. Input -Inf -subnormal -0.f32.3.0 -0.f32 defaults to sin. For PTX ISA versions 1.0 +0.4.approx.0 NaN NaN The maximum absolute error is 2-20. Explicit modifiers .PTX ISA Version 2. sin.0 +subnormal +Inf NaN Result NaN -0.approx. sm_1x: Subnormal inputs and results to sign-preserving zero.0 through 1. 96 January 24.ftz. d = sin(a). sin.ftz.0 +0. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx modifier is required. For PTX ISA version 1. Subnormal numbers: sm_20: By default.ftz introduced in PTX ISA version 1.approx{.f32 introduced in PTX ISA version 1.0 Table 62. Target ISA Notes Examples Supported on all target architectures. a.9 in quadrant 00.f32 sa.f32 d. Find the sine of the angle a (in radians). a.0 +0. sin.f32 implements a fast approximation to sine.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.0.ftz. sin. 2010 . the . sin.approx and .approx. PTX ISA Notes sin.

f32.approx{.approx. 2010 97 . For PTX ISA version 1. January 24.f32 introduced in PTX ISA version 1.ftz. cos. the .0 +1. cos.0 +subnormal +Inf NaN Result NaN +1.0 NaN NaN The maximum absolute error is 2-20. Target ISA Notes Examples Supported on all target architectures.approx modifier is required. For PTX ISA versions 1.4.ftz introduced in PTX ISA version 1.9 in quadrant 00.Chapter 8.0.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero. d = cos(a).approx and . subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero.0 +0. Subnormal numbers: sm_20: By default.f32 implements a fast approximation to cosine. Explicit modifiers . Find the cosine of the angle a (in radians).4 and later. Input -Inf -subnormal -0.ftz}.f32 ca. Instruction Set Table 63. a. a.0 +1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.f32 defaults to cos.0 through 1.approx.0 +1. cos. PTX ISA Notes cos. cos. cos.3.approx.ftz.f32 d.

0.ftz}.4 and later.ftz. For PTX ISA versions 1. a.0 +0.f32 defaults to lg2.ftz. lg2. lg2.approx modifier is required. d = log(a) / log(2).3.6 for mantissa. a.approx.0 Table 64.0 through 1.f32 implements a fast approximation to log2(a).4. 98 January 24.PTX ISA Version 2. Input -Inf -subnormal -0.approx{. Target ISA Notes Examples Supported on all target architectures.approx and .ftz.f32 Determine the log2 of a.f32. the . lg2.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers .f32 la. lg2.approx.f32 introduced in PTX ISA version 1.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz introduced in PTX ISA version 1. lg2. PTX ISA Notes lg2. The maximum absolute error is 2-22. sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.approx. 2010 . Subnormal numbers: sm_20: By default. subnormal numbers are supported.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

gt. b. . unordered versions are included: equ. and (optionally) combine this result with a predicate value by applying a Boolean operator. le. neu.lt. Integer Notes Floating Point Notes The ordered comparisons are eq. 102 January 24.dtype. subnormal numbers are supported. c).ftz.dtype. num. hi. then these comparisons have the same result as their ordered counterparts. setp.f32.f64 source type requires sm_13 or later. gtu. a.and. For unsigned values.pred variables. ge. ne. The comparison operator is a suffix on the instruction. .0 Table 67. Subnormal numbers: sm_20: By default. leu. . If either operand is NaN. then the result of these comparisons is true. If both operands are numeric values (not NaN). A related value computed using the complement of the compare result is written to the second destination operand. 2010 . c).b32. le. If either operand is NaN. xor. gt. gt.s32. loweror-same. p. lt.dtype. num returns true if both operands are numeric values (not NaN). p[|q]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. the comparison operators lo.f32 comparisons. gtu. . {!}c.i. ltu. . nan The Boolean operator BoolOp(A. or. neu.s16.PTX ISA Version 2. The destinations p and q must be . p[|q].a. sm_1x: setp. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. higher. To aid comparison operations in the presence of NaN values. This result is written to the first destination operand.type setp.BoolOp{.B) is one of: and.f64 }. setp with . setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. Semantics t = (a CmpOp b) ? 1 : 0.s32 setp.eq.0. hi. lt.u16. .f32 flushes subnormal inputs to sign-preserving zero. ne. ge. and higher-or-same may be used instead of lt. ls. lt.n.f64 supports subnormal numbers.u32 p|q. hs equ. The untyped.r.b. setp. geu. and nan returns true if either operand is NaN. Modifier . b.type = { . ge. The signed and unsigned comparison operators are eq. . le.ftz}.ftz}. @q setp. and can be one of: eq. leu.u64. .ftz applies only to . ne. ge. lo. ls. gt.type . . bit-size comparisons are eq and ne.b16.CmpOp. and hs for lower. a.f32 flushes subnormal inputs to sign-preserving zero. q = BoolOp(!t. respectively. setp. the result is false.b64. Applies to all numeric types. le. p = BoolOp(t. ltu. .CmpOp{. geu.s64.u32.

Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. .s32. Instruction Set Table 68.s32 slct{.f32.0.g.f32 flushes subnormal values of operand c to sign-preserving zero. 2010 103 . Modifier .ftz applies only to . . Table 69. d = (c == 1) ? a : b. based on the value of the predicate source operand. based on the sign of the third operand. c. @q selp. and b must be of the same type. . negative zero equals zero.s16. y. slct.ftz.f32 A. d = (c >= 0) ? a : b. .f32 flushes subnormal values of operand c to sign-preserving zero.type d. .type = { . Semantics Floating Point Notes January 24. .b16. slct Syntax Comparison and Selection Instructions: slct Select one source operand.u16.s32 selp.s64. selp Syntax Comparison and Selection Instructions: selp Select between source operands.dtype.f32 d.b32. .b64.t. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. selp. Introduced in PTX ISA version 1. fval. a is stored in d. If c is True. and b are treated as a bitsize type of the same width as the first instruction type. . .f32 comparisons.dtype. . sm_1x: slct.u64.xp. val.x. b. If operand c is NaN. . c. a is stored in d. selp. operand c must match the second instruction type. subnormal numbers are supported. a. b. a.s16. .u32. otherwise b is stored in d. .f32 r0.f64 requires sm_13 or later. .u64. Operands d.u16. slct. a. f0.p. For . Description Conditional selection. d.dtype = { . and operand a is selected.s32.ftz}.0.f32. .b32.ftz. slct. the comparison is unordered and operand b is selected.Chapter 8.r. Operand c is a predicate.dtype. c. .b64.f32 comparisons. The selected input is copied to the output without modification.f64 }. b. . Subnormal numbers: sm_20: By default.s64.u32. .u64. Operands d. slct. .s32 x. and operand a is selected. .dtype.b16. If c ≥ 0. a. B. b otherwise.f64 requires sm_13 or later. slct. z. .f64 }. . C.u32.

Instructions and. and not also operate on predicates. performing bit-wise operations on operands of any type.7. or. 2010 . This permits bit-wise operations on floating point values without having to define a union to access the bits.0 8.PTX ISA Version 2. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. provided the operands are of the same size. xor. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4.

Supported on all target architectures.r. d = a & b. Supported on all target architectures. January 24. or Syntax Logic and Shift Instructions: or Bitwise OR. a. b. .pred. .b32 and.0. .b32 mask mask. . and.q.b16.q. b. a.pred. Instruction Set Table 70.fpvalue.type d.b32.pred p. and Syntax Logic and Shift Instructions: and Bitwise AND. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. Introduced in PTX ISA version 1. 2010 105 . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.b32. Table 71. or.b16.0. d = a | b. Allowed types include predicate registers.type = { .0x80000000.Chapter 8. Introduced in PTX ISA version 1.b64 }. .0x00010001 or. . or.type = { .b32 x. . . Allowed types include predicate registers. The size of the operands must match.r.b64 }. sign. and. but not necessarily the type.type d. The size of the operands must match.

a. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. d = ~a.0x0001.q.type = { .r. but not necessarily the type. Introduced in PTX ISA version 1. cnot.mask. a.b32.b64 }.x. . Allowed types include predicate registers. .0 Table 72. not.0.b16.b32.b32 xor. The size of the operands must match. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Allowed types include predicates.b32 mask. .q.pred.0. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. Table 74. d.b16 d.b32. xor. 106 January 24. . but not necessarily the type.type = { . . The size of the operands must match.type = { . Supported on all target architectures. The size of the operands must match. b.b16. Introduced in PTX ISA version 1. .pred p. not Syntax Logic and Shift Instructions: not Bitwise negation.b32 d.type d.PTX ISA Version 2. Supported on all target architectures. 2010 . but not necessarily the type.pred.b64 }. Supported on all target architectures. Table 73. cnot.0.type d. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.a. one’s complement. Introduced in PTX ISA version 1.type d. not. d = (a==0) ? 1 : 0.b16. . a. d = a ^ b. .b64 }. xor. . not. .

b16. shr. . PTX ISA Notes Target ISA Notes Examples January 24. but not necessarily the type. b. The b operand must be a 32-bit value. .b64. . shr. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.s32 shr.b16. a. PTX ISA Notes Target ISA Notes Examples Table 76. The b operand must be a 32-bit value. d = a >> b. shl. Signed shifts fill with the sign bit.u16 shr. shl.Chapter 8. .u16. The sizes of the destination and first source operand must match. Introduced in PTX ISA version 1. Instruction Set Table 75.i.u32. i. . Shift amounts greater than the register width N are clamped to N. .s16. sign or zero fill on left.type = { . regardless of the instruction type. The sizes of the destination and first source operand must match. shr Syntax Logic and Shift Instructions: shr Shift bits right.b64 }.b32. Shift amounts greater than the register width N are clamped to N.a.i. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.type = { . . b. Supported on all target architectures. . but not necessarily the type.type d.s32.0. .u64. regardless of the instruction type.s64 }. . Introduced in PTX ISA version 1.2.type d.0. 2010 107 . zero-fill on right.a. shl Syntax Logic and Shift Instructions: shl Shift bits left.1.b16 c. . . d = a << b. Supported on all target architectures.b32. k. a.j.2.b32 q. Bit-size types are included for symmetry with SHL. unsigned and untyped shifts fill with 0.

5. Data Movement and Conversion Instructions These instructions copy data from place to place. or shared state spaces. suld. The cvta instruction converts addresses between generic and global.PTX ISA Version 2.7. possibly converting it from one format to another. ld. local. mov. and st operate on both scalar and vector types. prefetchu isspacep cvta cvt 108 January 24. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and from state space to state space. st. 2010 . Instructions ld. and sust support optional cache operations. ldu. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.0 8.

likely to be accessed again.ca.cs) on global addresses. it performs the ld. A ld.cs is applied to a Local window address. Cache Operators PTX 2.lu load last use operation. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. As a result of this request. Table 77.1. . not L1). evict-first. If one thread stores to global memory via one L1 cache.ca loads cached in L1.cs Cache streaming. invalidates (discards) the local L1 line following the load. The cache operators require a target architecture of sm_20 or later. and a second thread loads that address via a second L1 cache with ld. Instruction Set 8. Use ld. and cache only in the L2 cache.lu operation. to allow the thread program to poll a SysMem location written by the CPU.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. . . The driver must invalidate global L1 cache lines between dependent grids of parallel threads. the second thread may get stale L1 cache data.cs. For sm_20 and later. rather than the data stored by the first thread.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. The ld. The ld.cg Cache at global level (cache in L2 and below. Global data is coherent at the L2 level.lu instruction performs a load cached streaming operation (ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. any existing cache lines that match the requested address in L1 will be evicted. if the line is fully covered. when applied to a local address. Operator . the cache operators have the following definitions and behavior. likely to be accessed once. The compiler / programmer may use ld. but multiple L1 caches are not coherent for global data. fetch again). bypassing the L1 cache. The default load instruction cache operation is ld.0 introduces optional cache operators on load and store instructions.7. 2010 109 . which allocates cache lines in all levels (L1 and L2) with normal eviction policy. The ld.cv to a frame buffer DRAM address is the same as ld. January 24.5.cv Cache as volatile (consider cached system memory lines stale.ca.Chapter 8. .ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. When ld.lu Last use.cg to cache loads only globally. The ld.

ca. and marks local L1 lines evict-first. but st.cg to local memory uses the L1 cache. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. regardless of the cache operation. bypassing its L1 cache.cg is the same as st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. If one thread stores to global memory. In sm_20.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. and discard any L1 lines that match. The st. Future GPUs may have globally-coherent L1 caches. The default store instruction cache operation is st.wb for global data.cg to cache global store data only globally. However. to allow a CPU program to poll a SysMem location written by the GPU with st. in which case st. The st. Global stores bypass L1. the second thread may get a hit on stale L1 cache data. . . and cache only in the L2 cache.wb. .wt Cache write-through (to system memory). Addresses not in System Memory use normal write-back.0 Table 78. rather than get the data from L2 or memory stored by the first thread. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. bypassing the L1 cache.ca loads.PTX ISA Version 2.wt store write-through operation applied to a global System Memory address writes through the L2 cache. likely to be accessed once.cs Cache streaming. Use st.wb could write-back global store data from L1. and a second thread in a different SM later loads from that address via a different L1 cache with ld. 110 January 24. which writes back cache lines of coherent cache levels with normal eviction policy. Operator .cg Cache at global level (cache in L2 and below. st.wt.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. not L1). 2010 .

ptr. Description . the generic address of a variable declared in global. or shared state space. addr. mov places the non-generic address of the variable (i.a.s64. .pred. d = &avar.global.e. // get address of variable // get address of label or function .e.u16.u16 mov.b64..type mov. The generic address of a variable in global. alternately. Semantics d = a. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. d. or shared state space may be taken directly using the cvta instruction. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. For variables declared in .f64 requires sm_13 or later. Note that if the address of a device function parameter is moved to a register. . mov. . local. A[5]. sreg. .type d.u64. mov. d.f32 mov. .b32. avar. A.b16. myFunc. .const.u32 d. u. Operand a may be a register. 2010 111 . d. label. Take the non-generic address of a variable in global. immediate. mov.shared state spaces.u32 mov.u32 mov.Chapter 8.0. i.s16..1. d = &label. local. within the variable’s declared state space Notes Although only predicate and bit-size types are required. k. ptr. or function name. . label. the parameter will be copied onto the stack and the address will be in the local state space.f32. a.type mov. special register. . . Write register d with the value of a. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. .type = { .u32. . and .v.s32. Introduced in PTX ISA version 1. variable in an addressable memory space. the address of the variable in its state space) into the destination register. // address is non-generic. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. local.type mov.local.f32 mov.f64 }. d = sreg.0. . Instruction Set Table 79.

y } = { a[0.g. d..b16.{a.0 Table 80.b64 112 January 24. a[16.y.b32 { d.x.15] } // unpack 8-bit elements from . d.b64 { d.b16 // pack four 8-bit elements into .w have type ..y.. Supported on all target architectures. mov. a[32.b16 { d.47].31] } // unpack 16-bit elements from . a[16..b32.15]. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b64 { d. a[48.b64 mov.type = { .b32 // pack four 16-bit elements into . mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.15]. a[8.7].31].b8 r.%r1.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b}.b32 mov.z.x | (a. d.. d.x | (a.0.x | (a.b32 mov. mov.. Semantics d = a.w << 24) d = a.31] } // unpack 8-bit elements from . d.b64 }. %r1.g. d. {lo.7].b32 // pack two 16-bit elements into . Description Write scalar register d with the packed value of vector register a.31]. a.b64 // pack two 32-bit elements into ..z. .23].z << 16) | (a. For bit-size types.x | (a.y << 16) | (a.y } = { a[0.y << 8) d = a.y << 8) | (a. d.w } = { a[0.z.w } = { a[0.b32 { d.. .y.u16 %x is a double.{x.63] } // unpack 16-bit elements from .. d. %x.y.b32 %r1.x | (a.z. a[16.. or write vector register d with the unpacked values from scalar register a.w}. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). a[24.w << 48) d = a.x.type d..y << 32) // pack two 8-bit elements into .15]. a[8.hi}.y } = { a[0.x. // // // // a.a}.b have type .y << 16) d = a.u32 x.hi are .PTX ISA Version 2. .b.z << 32) | (a.u8 // unpack 32-bit elements from .x.x. lo..b.. a[32. 2010 . {r. d.a have type ..

. . .s8. .s32. i. 2010 113 . 32-bit).volatile may be used with . . . . an address maps to the corresponding location in local or shared memory.vec. The address must be naturally aligned to a multiple of the access size. i.v2. *a.u8. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. [a]. ld. . PTX ISA Notes January 24.f64 }.ss}. *(a+immOff).cop = { .volatile introduced in PTX ISA version 1.type ld{. If no state space is given. Generic addressing and cache operations introduced in PTX ISA 2.shared spaces to inhibit optimization of references to volatile memory.global.1.type ld. .v4 }.param.ss}{.f64 using cvt. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.volatile. d. . *(immAddr). [a].vec.volatile.0. . or the instruction may fault. . [a]. 32-bit). If an address is not properly aligned.f16 data may be loaded using ld.u32.b8. . Semantics d d d d = = = = a. or [immAddr] an immediate absolute byte address (unsigned.const space suffix may have an optional bank number to indicate constant banks other than bank zero. . Description Load register variable d from the location specified by the source address operand a in specified state space. Instruction Set Table 81.s64.u64.b32. d.local.shared }. . .reg state space.global and .ss}. perform the load using generic addressing.volatile{. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.type = { .cs. the resulting behavior is undefined. Generic addressing may be used with ld. The value loaded is sign-extended to the destination register width for signed integers.f32.u16.volatile{. . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. to enforce sequential consistency between threads accessing shared memory. ld introduced in PTX ISA version 1.b64. d. and truncated if the register width exceeds the state space address width for the target architecture.0. Cache operations are not permitted with ld. Within these windows.s16. ld. .e.vec = { . an integer or bit-size type register reg containing a byte address.type . [a]. This may be used.cop}. .const. for example.ss}{. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. . .type d. and is zeroextended to the destination register width for unsigned and bit-size types.cg.f32 or .cop}. .e. Addresses are zero-extended to the specified width as needed. A destination register wider than the specified type may be used. ld{. .Chapter 8.cv }..b16. and then converted to . an address maps to global memory unless it falls within the local memory window or the shared memory window. In generic addressing.ss = { . .ca.lu.b16. The address size may be either 32-bit or 64-bit. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The . .

Generic addressing requires sm_20 or later.b32 ld.PTX ISA Version 2.[240].s32 ld. // negative offset %r.f32 ld. // access incomplete array x.f64 requires sm_13 or later.b32 ld. %r.[fs]. 2010 .[p].f16 d. Q.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.global.global.b32 ld.b64 ld.[buffer+64].const[4].local. // immediate address %r.[p+4]. x. Cache operations require sm_20 or later.[a].b16 cvt. ld.f32.v4.%r. d.[p+-8]. // load .shared.local.0 Target ISA Notes ld.const.

. .v2. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Instruction Set Table 82.type = { . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.v4.b32. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .f32. *(a+immOff). [areg] a register reg containing a byte address. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f64 requires sm_13 or later. 32-bit).s32. . .ss}.f64 using cvt.[p+4]. .global.[a].b8..f32 Q.ss}. i. . an address maps to global memory unless it falls within the local memory window or the shared memory window. // state space . where the address is guaranteed to be the same across all threads in the warp. . Introduced in PTX ISA version 2.u64.ss = { .u8. d. an address maps to the corresponding location in local or shared memory.vec = { . ldu{. If an address is not properly aligned. 32-bit). i. ldu.f32 or . or the instruction may fault.global. 2010 115 . The value loaded is sign-extended to the destination register width for signed integers. ldu. ldu. .s16.v4 }. . and then converted to .b16. .type d.u16.global.u32.f32 d. A destination register wider than the specified type may be used. . Semantics d d d d = = = = a.f64 }.0. .f16 data may be loaded using ldu. and is zeroextended to the destination register width for unsigned and bit-size types. Within these windows.b16. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.[p].b64. and truncated if the register width exceeds the state space address width for the target architecture. In generic addressing.e. The address size may be either 32-bit or 64-bit. . ldu. Addresses are zero-extended to the specified width as needed. [a]. A register containing an address may be declared as a bit-size type or integer type. or [immAddr] an immediate absolute byte address (unsigned.s8. . . // load from address // vec load from address . *a.type ldu{.reg state space.vec.s64. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.e. The address must be naturally aligned to a multiple of the access size.Chapter 8.b32 d. *(immAddr). [a].global }. The data at the specified address must be read-only. The addressable operand a is one of: [avar] the name of an addressable variable var. only generic addresses that map to global memory are legal. PTX ISA Notes Target ISA Notes Examples January 24. For ldu. the resulting behavior is undefined. If no state space is given. perform the load using generic addressing.

wb.volatile introduced in PTX ISA version 1. .ss . to enforce sequential consistency between threads accessing shared memory. A source register wider than the specified type may be used.0. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . [a]. . *d = a.vec. .s64. [a]. *(immAddr) = a.f16 data resulting from a cvt instruction may be stored using st.u32. Generic addressing and cache operations introduced in PTX ISA 2.cg.0.PTX ISA Version 2.type .ss}{.type [a]. for example. b. .s8.f64 requires sm_13 or later. { .b8. . st. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.f64 }.type st{.ss}.u64. . or the instruction may fault. b.wt }.local. . . the resulting behavior is undefined. Cache operations require sm_20 or later. 2010 . [a]. Generic addressing may be used with st. an address maps to the corresponding location in local or shared memory.s16.volatile may be used with . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. { .e.u8. the access may proceed by silently masking off low-order address bits to achieve proper rounding. an integer or bit-size type register reg containing a byte address. If no state space is given. .global.b32.cs.type st.cop}. Cache operations are not permitted with st.b64. or [immAddr] an immediate absolute byte address (unsigned.type = = = = {.0 Table 83.u16. In generic addressing.reg state space. Generic addressing requires sm_20 or later.e.shared }. .vec. This may be used. st. .v4 }.volatile{. . st{. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. The address size may be either 32-bit or 64-bit.global and . . i. . { . If an address is not properly aligned. .1. perform the store using generic addressing.cop .v2. . b.volatile. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.vec .b16. b. an address maps to global memory unless it falls within the local memory window or the shared memory window.cop}. 32-bit). . PTX ISA Notes Target ISA Notes 116 January 24..volatile.ss}{.ss}.s32. 32-bit). Within these windows. Addresses are zero-extended to the specified width as needed.b16. and truncated if the register width exceeds the state space address width for the target architecture. *(d+immOffset) = a. st. st introduced in PTX ISA version 1. i. Semantics d = a. .f32. The lower n bits corresponding to the instruction-type width are stored to memory.volatile{. The address must be naturally aligned to a multiple of the access size.shared spaces to inhibit optimization of references to volatile memory. .

a.b.Q. // %r is 32-bit register // store lower 16 bits January 24.f16.f32 st.local.%r. [fs].f32 st.s32 cvt.a. // immediate address %r.Chapter 8. Instruction Set Examples st. 2010 117 .local.v4.global.b32 st.b32 st. [q+-8].local. [p].s32 st.global. [q+4].b16 [a].r7. // negative offset [100].%r.

a register reg containing a byte address. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.space}.level = { .e. prefetch and prefetchu require sm_20 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 32-bit). prefetch{. The address size may be either 32-bit or 64-bit. // prefetch to data cache // prefetch to uniform cache . an address maps to global memory unless it falls within the local memory window or the shared memory window.global. and no operation occurs if the address maps to a local or shared memory location. . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. Within these windows. prefetchu.space = { . A prefetch into the uniform cache requires a generic address. [a]. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L2 }. i.L1 [a]. prefetch. 2010 . Addresses are zero-extended to the specified width as needed. 32-bit). In generic addressing. an address maps to the corresponding location in local or shared memory. or [immAddr] an immediate absolute byte address (unsigned.local }. in specified state space.L1.level prefetchu.L1 [ptr]. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. A prefetch to a shared memory location performs no operation. .0. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.0 Table 84. and truncated if the register width exceeds the state space address width for the target architecture. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.global. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.L1 [addr]. the prefetch uses generic addressing. 118 January 24. If no state space is given.PTX ISA Version 2.

lptr.pred. The source address operand must be a register of type .0. isspacep. When converting a generic address into a global.Chapter 8.u32. . p.shared }.u32 gptr.local. PTX ISA Notes Target ISA Notes Examples Table 86.size p. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u32 or . isshrd.space p.shared isglbl.genptr. local. lptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. or shared state space.space = { .u32 p. isspacep. // result is . the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32 to truncate or zero-extend addresses. a.space. var. p.shared.space.u32. or shared state space.pred .space = { .local isspacep. the generic address of the variable may be taken using cvta. // get generic address of svar cvta.u64 or cvt.global. gptr.to. 2010 119 .shared }. . cvta.local. The destination register must be of type . a.to.local. cvta. // convert to generic address // get generic address of var // convert generic address to global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. local.space.u64. isspacep requires sm_20 or later. Take the generic address of a variable declared in global. Introduced in PTX ISA version 2.u64 }.size = { . cvta.0. For variables declared in global. sptr. or shared address.u64.global isspacep. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. January 24. Description Convert a global. The source and destination addresses must be the same size. or vice-versa. or shared state space to generic. . // local. or shared address cvta. or shared address to a generic address. . . local. svar. Use cvt. islcl. or vice-versa.size cvta.global.size .global. A program may use isspacep to guard against such incorrect behavior.u32 p. a. . local. local. cvta requires sm_20 or later. Instruction Set Table 85.

.0 Table 87. . choosing even integer if source is equidistant between two integers. d = convert(a).rzi round to nearest integer in the direction of zero .e. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.u64.frnd}{.MAXINT for the size of the operation. .dtype = .rni round to nearest integer. and for same-size float-tofloat conversions where the value is rounded to an integer. For cvt.s32. .dtype. subnormal inputs are flushed to signpreserving zero.sat}. The optional . subnormal numbers are supported.atype d.atype = { .sat modifier is illegal in cases where saturation is not possible based on the source and destination types. The compiler will preserve this behavior for legacy PTX code. Note: In PTX ISA versions 1.f32 float-tofloat conversions with integer rounding. . 2010 .. Note that saturation applies to both signed and unsigned integer types.ftz modifier may be specified in these cases for clarity. .rm.rz. subnormal inputs are flushed to signpreserving zero.ftz.u8.f32.s16.sat is redundant.u32. the .4 and earlier. . . Saturation modifier: .irnd}{. the result is clamped to the destination range by default. . sm_1x: For cvt. Integer rounding is illegal in all other instances. .irnd = { .ftz}{.f32. // integer rounding // fp rounding .rn. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rp }.atype cvt{.rmi round to nearest integer in direction of negative infinity . Integer rounding modifiers: .f32 float-to-integer conversions and cvt.ftz.ftz. i. d. . Description Semantics Integer Notes Convert between different types and sizes.dtype.u16.f64 }.PTX ISA Version 2. i. .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.f16.frnd = { . 120 January 24.e.f32. . .f32 float-tofloat conversions with integer rounding.ftz}{. a. a.dtype. . . . Integer rounding is required for float-to-integer conversions.rpi }. . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. For float-to-integer conversions. . .s8.dtype.sat limits the result to MININT.sat}.s64.f32 float-to-integer conversions and cvt. cvt{.rni. . .rmi.rzi.ftz.sat For integer destination types.

f64 requires sm_13 or later.sat For floating-point destination types. Floating-point rounding modifiers: .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. // round to nearest int. cvt.i.f16.f32. . Subnormal numbers: sm_20: By default. .s32 f. and cvt. Floating-point rounding is illegal in all other instances. cvt.f32.f32 x. The compiler will preserve this behavior for legacy PTX code. result is fp cvt. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. Note: In PTX ISA versions 1.s32.f16. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.ftz modifier may be specified in these cases for clarity.f32.4 and earlier. and .rn mantissa LSB rounds to nearest even . Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.f32.r. The result is an integral value. // float-to-int saturates by default cvt. Introduced in PTX ISA version 1. 1. cvt to or from .f32.f64 j. Saturation modifier: . The optional .0.f32 x.f64 types.y. stored in floating-point format.Chapter 8. The operands must be of the same size.rni. and for integer-to-float conversions.ftz behavior for sm_1x targets January 24.0.f32.f32 instructions. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .0].4 or earlier. Applies to .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).sat limits the result to the range [0.f16.version is 1.rm mantissa LSB rounds towards negative infinity .f32. cvt. subnormal numbers are supported. NaN results are flushed to positive zero.f64. Specifically. 2010 121 . if the PTX . // note .y.rz mantissa LSB rounds towards zero . Modifier .

add. sampler. In the independent mode. } = clamp_to_border. . sampler.2d. add. the file is assumed to use unified mode. // get tex1’s txq. r1. [tex1. add.v4. A PTX module may declare only one texturing mode. {f1. r3.f32.r3.texref handle. and surface descriptors. mul.f32. samplers.param .height. r1. and surface descriptors. with the restriction that they correspond 1-to-1 with the 128 possible textures. r5. r5. r4. Texture and Surface Instructions This section describes PTX instructions for accessing textures. but the number of samplers is greatly restricted to 16. 2010 .f2}].r2.target options ‘texmode_unified’ and ‘texmode_independent’.f32 {r1. If no texturing mode is declared.f32 r3. PTX has two modes of operation.samplerref tsamp1 = { addr_mode_0 filter_mode }. and surfaces. [tex1]. . r6.6. and surface descriptors: • • • Static initialization of texture. Texturing modes For working with textures and samplers. sampler. PTX supports the following operations on texture. and surface descriptors. r3. Example: calculate an element’s power contribution as element’s power/total number of elements.. The texturing mode is selected using .0 8. // get tex1’s tex.global .u32 r5. div. [tex1].b32 r6. .b32 r5.texref tex1 ) { txq.f32 r1. cvt.. In the unified mode. texture and sampler information each have their own handle. The advantage of independent mode is that textures and samplers can be mixed and matched.u32 r5. Module-scope and per-entry scope definitions of texture.target texmode_independent .entry compute_power ( .7.width. 122 January 24.PTX ISA Version 2. sampler.f32 r1. r2. r1. = nearest width height tsamp1. The advantage of unified mode is that it allows 128 samplers. allowing them to be defined separately and combined at the site of usage in the program. texture and sampler information is accessed through a single .f32 r1.r4}. Ability to query fields within texture. r5.

[a.geom = { .0. Supported on all target architectures. tex. 2010 123 . Instruction Set These instructions provide access to texture and surface memory.btype tex. . Description Texture lookup using a texture coordinate vector. // Example of independent mode texturing tex. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.r4}.. The instruction always returns a four-element vector of 32-bit values.1d.f32 {r1. Unified mode texturing introduced in PTX ISA version 1.s32. .r2.geom. sampler_x.r3. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32.dtype.1d. b. {f1.f32 }.geom. d. c]. Operand c is a scalar or singleton tuple for 1d textures. the square brackets are not required and . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. and is a four-element vector for 3d textures. the resulting behavior is undefined. . Notes For compatibility with prior versions of PTX.dtype. // explicit sampler . .btype = { . [tex_a.s32 {r1.f32 }.r4}. is a two-element vector for 2d textures.3d }.v4 coordinate vectors are allowed for any geometry.r3. {f1}].f4}].v4. If an address is not properly aligned.v4.v4.s32.2d. .5. [tex_a.e.dtype = { .f3. the sampler behavior is a property of the named texture. //Example of unified mode texturing tex.v4.u32. [a. tex txq suld sust sured suq Table 88.r2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. . A texture base address is assumed to be aligned to a 16-byte address.f2. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.btype d.3d. or the instruction may fault. PTX ISA Notes Target ISA Notes Examples January 24. i. with the extra elements being ignored. If no sampler is specified. An optional texture sampler b may be specified. where the fourth element is ignored.s32.Chapter 8. . c].

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. clamp_to_edge. Supported on all target architectures. txq. 2010 . . addr_mode_2 }. [a]. . . txq.filter_mode. addr_mode_1. d. Integer from enum { nearest.b32 d. Description Query an attribute of a texture or sampler.normalized_coords }.addr_mode_1 .width .texref or .normalized_coords . txq.squery. [a]. [tex_A].5.PTX ISA Version 2.samplerref variable. Query: .addr_mode_0.addr_mode_0 . mirror.b32 %r1.width. txq.filter_mode. . In unified mode. and in independent mode sampler attributes are accessed via a separate samplerref argument. .b32 txq. [smpl_B].addr_mode_0.tquery = { .b32 %r1. // texture attributes // sampler attributes .height.b32 %r1.depth. // unified mode // independent mode 124 January 24.0 Table 89.height . linear } Integer from enum { wrap. clamp_ogl.squery = { . [tex_A].width. Operand a is a .depth . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. sampler attributes are also accessed via a texref argument.tquery.filter_mode . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).

the resulting behavior is undefined. Description Load from surface memory using a surface coordinate vector.2d. [surf_B.clamp = = = = = = { { { { { { d.trap introduced in PTX ISA version 1. . . the surface sample elements are converted to . and the size of the data transfer matches the size of destination operand d.dtype. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. If the destination type is .zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. The lowest dimension coordinate represents a sample offset rather than a byte offset.clamp .s32 is returned. [a. {f1. then .p. then . .dtype .5. suld. G. b]. // unformatted d.f32 is returned.p.b.vec.b.trap {r1.b64. // formatted .3d requires sm_20 or later. .. Destination vector elements corresponding to components that do not appear in the surface format are not written.f32 based on the surface format as follows: If the surface format contains UNORM. size and type conversion is performed as needed to convert from the surface sample format to the destination type.cop}. [a. .u32 is returned. is a two-element vector for 2d surfaces.w}].v2.f2. b].dtype .v2. suld. If the destination base type is .z.3d.b . // cache operation none. . .s32.v4.clamp field specifies how to handle out-of-bounds addresses: . Instruction Set Table 90. suld.clamp. If an address is not properly aligned. .clamp . i. B.3d }. Target ISA Notes Examples January 24. suld.trap clamping modifier.geom .clamp suld. or .1d.zero }.f32.b performs an unformatted load of binary data.y.geom{.trap suld. A surface base address is assumed to be aligned to a 16-byte address.Chapter 8.cs.p.cop}. 2010 125 . suld. .cv }.u32. Operand b is a scalar or singleton tuple for 1d surfaces. SNORM. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32.cop .s32. sm_1x targets support only the .s32. and cache operations introduced in PTX ISA version 2.e.b32.trap . [surf_A.1d. suld. // for suld.0.b supported on all target architectures. . suld. or .p . suld.vec . The .f32.p requires sm_20 or later. . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. Coordinate elements are of type . suld Syntax Texture and Surface Instructions: suld Load from surface memory. and A components of the surface format.v4 }.f3. where the fourth element is ignored. Cache operations require sm_20 or later. or the instruction may fault. .ca. . . Operand a is a .cg.b32. // for suld. .dtype.p is currently unimplemented.u32.r2}. . additional clamp modifiers.b.f32 }. .surfref variable. .b8 .b64 }. if the surface format contains SINT data. then . {x. {x}].f4}.trap.geom{.s32.b16. .v4.u32.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. suld. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. and is a four-element vector for 3d surfaces. or FLOAT data. if the surface format contains UINT data.

v2. The . . i.trap . If the source base type is . sust. Coordinate elements are of type .z. Operand a is a . . {x. . // for sust.clamp .3d }. SNORM. and A surface components. sust.clamp = = = = = = { { { { { { [a.{u32. . or .f3.1d.zero }. .trap clamping modifier.cop .2d.ctype.trap introduced in PTX ISA version 1. The lowest dimension coordinate represents a sample offset rather than a byte offset.e. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. The source data is then converted from this type to the surface sample format. then . b].u32 is assumed.3d requires sm_20 or later.clamp. sm_1x targets support only the .ctype .b16.1d. sust. . {x}].PTX ISA Version 2.r2}. The size of the data transfer matches the size of source operand c. sust Syntax Texture and Surface Instructions: sust Store to surface memory. sust. {f1.b // for sust. . and cache operations introduced in PTX ISA version 2.p Description Store to surface memory using a surface coordinate vector. .b64 }. size and type conversions are performed as needed between the surface sample format and the destination type.s32. the resulting behavior is undefined.clamp .f32} are currently unimplemented. {r1.0 Table 91. G.b. . [a.wt }.geom{.b32.wb. If the source type is .f32.f32 is assumed. and is a four-element vector for 3d surfaces.s32. These elements are written to the corresponding surface sample components. sust. Surface sample components that do not occur in the source vector will be written with an unpredictable value. c.b64.0.u32. . // unformatted // formatted .trap [surf_A.. or the instruction may fault. Target ISA Notes Examples 126 January 24. additional clamp modifiers.v2. .p.v4.vec.f4}. . where the fourth element is ignored.3d.b32. The source vector elements are interpreted left-to-right as R.cop}. or FLOAT data. .b32. . [surf_B. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Operand b is a scalar or singleton tuple for 1d surfaces. sust.u32.b.f32 }.p requires sm_20 or later. none.clamp sust. Source elements that do not occur in the surface sample are ignored. A surface base address is assumed to be aligned to a 16-byte address.cop}.w}]. B.b.ctype.clamp field specifies how to handle out-of-bounds addresses: .5.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. b]. then . sust. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . .s32 is assumed. if the surface format contains UINT data.geom .b performs an unformatted store of binary data.cs. then .s32. if the surface format contains SINT data.v4 }. is a two-element vector for 2d surfaces.surfref variable.trap sust.ctype . .b8 . .trap.p. the access may proceed by silently masking off low-order address bits to achieve proper rounding.vec. sust. Cache operations require sm_20 or later.y. sust. . c.f2. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. If an address is not properly aligned. 2010 .s32.vec .b supported on all target architectures.cg.f32.p. .p.p performs a formatted store of a vector of 32-bit data values to a surface sample.geom{.

p .b].b32.ctype. is a two-element vector for 2d surfaces. min and max apply to .b32 }.u32.u32.Chapter 8.c.u64.ctype.geom. . .geom.ctype = { . then . Instruction Set Table 92.u32.1d.0.b32 type. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.op = { .ctype = { . Operand b is a scalar or singleton tuple for 1d surfaces. or . .2d.p. sured.p performs a reduction on sample-addressed 32-bit data. sured.u64.e. . // for sured. operations and and or apply to . Reduction to surface memory using a surface coordinate vector. January 24. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. sured.b32 }.u64 data.b .op.surfref variable.trap .s32. sured. . and .b performs an unformatted reduction on .clamp .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.clamp [a. then . Operations add applies to . r1. // sample addressing . the resulting behavior is undefined.b.p. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32. .2d.s32 or .s32. 2010 127 . If an address is not properly aligned. .or }. . A surface base address is assumed to be aligned to a 16-byte address. [surf_B.max. i.y}].clamp. if the surface format contains SINT data.trap [surf_A.geom = { . .clamp field specifies how to handle out-of-bounds addresses: . sured requires sm_20 or later.u32 based on the surface sample format as follows: if the surface format contains UINT data.s32. where the fourth element is ignored. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. {x}].clamp [a. .trap. {x.trap sured.1d. and the data is interpreted as .b].add. Operand a is a .b32.. and is a four-element vector for 3d surfaces.b32.clamp = { .s32 is assumed. .and. .u32 and .b.add.s32 types.op. . // for sured. . // byte addressing sured. . The instruction type is restricted to .u32 is assumed. The .min.c. r1.zero }.3d }.s32 types. Coordinate elements are of type . The lowest dimension coordinate represents a sample offset rather than a byte offset. or the instruction may fault.min. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .

query = { . 2010 .width. Query: . Operand a is a .width .0 Table 93.depth }.surfref variable. [a].b32 d.PTX ISA Version 2.5. suq.height.width. Description Query an attribute of a surface. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq. Supported on all target architectures. .b32 %r1. [surf_A]. . 128 January 24.height .query.

f32 @q bra L23.Chapter 8.7. used primarily for defining a function body. setp. } PTX ISA Notes Target ISA Notes Examples Table 95. Introduced in PTX ISA version 1.0. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. If {!}p then instruction Introduced in PTX ISA version 1. ratio. 2010 129 . { instructionList } The curly braces create a group of instructions. {} Syntax Description Control Flow Instructions: { } Instruction grouping. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.a. Supported on all target architectures.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Supported on all target architectures. @{!}p instruction. Instruction Set 8. Execute an instruction or instruction block for threads that have the guard predicate true.c.eq.s32 a.0.x.s32 d. { add.y. mov.0. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. Threads with a false guard predicate do nothing.b. p.7.f32 @!p div.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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execute a bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.cta. the bar. The reduction operations for bar. the optional thread count must be a multiple of the warp size. The result of .sync 0.sync or bar.{arrive.and. threads within a CTA that wish to communicate via memory can store to memory.arrive does not cause any waiting by the executing threads.red} introduced in PTX . In conditionally executed code.sync without a thread count introduced in PTX ISA 1. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. 2010 133 .red.0. b}.red instruction.u32 bar. thread count. b}. b.sync and bar. bar. and the barrier is reinitialized so that it can be immediately reused. {!}c. b. PTX ISA Notes Target ISA Notes Examples bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active.red delays the executing threads (similar to bar. Instruction Set Table 100. All threads in the warp are stalled until the barrier completes. while . and bar. p. and d have type .or }. bar.{arrive. bar. If no thread count is specified. Thus.or).popc is the number of threads with a true predicate. it simply marks a thread's arrival at the barrier. Once the barrier count is reached. Since barriers are executed on a per-warp basis.popc.red performs a reduction operation across threads. the waiting threads are restarted without delay. Execution in this case is unpredictable.red are population-count (. {!}c.red also guarantee memory ordering among threads identical to membar. a. and any-thread-true (. if any thread in a warp executes a bar instruction. Only bar. operands p and c are predicates. Register operands.red} require sm_20 or later..0. bar. bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).pred . bar.sync or bar. The barrier instructions signal the arrival of the executing threads at the named barrier. all threads in the CTA participate in the barrier.version 2. In addition to signaling its arrival at the barrier. thread count. Operand b specifies the number of threads participating in the barrier. Register operands. a{. bar. and then safely read values stored by other threads prior to the barrier. Each CTA instance has sixteen barriers numbered 0.u32.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. b}.popc). and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). bar.sync) until the barrier count is met.and and . Operands a. . it is as if all the threads in the warp have executed the bar instruction.red should not be intermixed with bar.arrive. Description Performs barrier synchronization and communication within a CTA. a{. the final value is written to the destination register in all threads waiting at the barrier. Note that a non-zero thread count is required for bar. all-threads-true (. January 24. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. bar.arrive a{.arrive using the same active barrier. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.op.Chapter 8. and bar.red performs a predicate reduction across the threads participating in the barrier. When a barrier completes.sync with an immediate barrier number is supported for sm_1x targets.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.sync bar. d.sync and bar. Thus.and).red.op = { .15.

PTX ISA Notes Target ISA Notes Examples membar. level describes the scope of other clients for which membar is an ordering event.sys will typically have much longer latency than membar. membar. membar.gl.sys Waits until all prior memory requests have been performed with respect to all clients. including thoses communicating via PCI-E such as system and peer-to-peer memory. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys requires sm_20 or later. A memory read (e.version 1.cta Waits until all prior memory writes are visible to other threads in the same CTA.sys. and memory reads by this thread can no longer be affected by other thread writes. this is the appropriate level of membar.{cta.g.gl.gl.{cta.cta. . . by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar. membar.0 Table 101. 2010 . membar. membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.level. when the previous value can no longer be read. membar.sys }. membar. that is.4.version 2. membar.gl} introduced in PTX . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. A memory write (e. global. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. by st. 134 January 24.cta. membar.level = { . .cta. For communication between threads in different CTAs or even different SMs.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.0. red or atom) has been performed when the value written has become visible to other clients at the specified level. or system memory level. membar.sys introduced in PTX .gl} supported on all target architectures.PTX ISA Version 2.gl will typically have a longer latency than membar.g. membar.

. i.e. and truncated if the register width exceeds the state space address width for the target architecture. Addresses are zero-extended to the specified width as needed. . perform the memory accesses using generic addressing. . The inc and dec operations return a result in the range [0..u32 only .s32. .max }.dec.shared }.and. Within these windows. cas (compare-and-swap). [a]. For atom. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. and exch (exchange).type = { . .g. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. performs a reduction operation with operand b and the value in location a.f32 }.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. a de-referenced register areg containing a byte address.u64.space}.type atom{.e. Instruction Set Table 102. b. c. 32-bit operations. . or the instruction may fault. . .Chapter 8.u32.u32. . .add. .b32 only . .op = { . dec. .cas. In generic addressing. [a]. If no state space is given. min. d. or [immAddr] an immediate absolute byte address. max. or by using atom.add.b64. Description // // // // // .or.exch. an address maps to global memory unless it falls within the local memory window or the shared memory window. January 24.b64 . the resulting behavior is undefined. . .type d. A register containing an address may be declared as a bit-size type or integer type.f32 Atomically loads the original value at location a into destination register d. e. and max operations are single-precision. . and stores the result of the specified operation at location a.b32. . . atom{.inc. Operand a specifies a location in the specified state space. If an address is not properly aligned. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. overwriting the original value. min.op. accesses to local memory are illegal. . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u64 . or.min. min. The address must be naturally aligned to a multiple of the access size. . .xor. The floating-point add. an address maps to the corresponding location in local or shared memory. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.b]. b. inc.space}. xor. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . atom. by inserting barriers between normal stores and atomic operations to a common address. .s32. and max. i. .op.f32.u32. 2010 135 . The integer operations are add. the access may proceed by silently masking off low-order address bits to achieve proper rounding.exch to store to locations accessed by other atomic operations. The address size may be either 32-bit or 64-bit.b32. The bit-size operations are and.space = { . The floating-point operations are add.s32.global.

[a].global. c) operation(*a.f32 atom.[p].cas.shared requires sm_12 or later. : r-1.s32 atom. atom. 64-bit atom.max. Release Notes Examples @p 136 January 24. s) = (r > s) ? s exch(r.0 Semantics atomic { d = *a.0. *a = (operation == cas) ? : } where inc(r.t) = (r == s) ? t operation(*a. atom.add. b.shared operations require sm_20 or later.[x+4].my_val.add.my_new_val.1. d.f32. Use of generic addressing requires sm_20 or later.b32 d. : r. b).0. 2010 .{add. Introduced in PTX ISA version 1.{min. d.PTX ISA Version 2.shared. s) = (r >= s) ? 0 dec(r.exch} requires sm_12 or later.global requires sm_11 or later. : r+1. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. s) = s.global.f32 requires sm_20 or later. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. atom. atom. 64-bit atom.max} are unimplemented.cas. cas(r.s. atom.

u32 only .s32.type = { .f32 }. or [immAddr] an immediate absolute byte address.op.global. . . The bit-size operations are and.f32 Performs a reduction operation with operand b and the value in location a. .space = { . b. 2010 137 . min. . and truncated if the register width exceeds the state space address width for the target architecture. . b). . . overwriting the original value. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. a de-referenced register areg containing a byte address. The floating-point operations are add.b64. Semantics *a = operation(*a. Instruction Set Table 103. where inc(r. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.g.space}.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. The inc and dec operations return a result in the range [0.and. or. . the resulting behavior is undefined.u32. Notes Operand a must reside in either the global or shared state space. the access may proceed by silently masking off low-order address bits to achieve proper rounding.op = { .inc.Chapter 8.xor. 32-bit operations.b].f32.shared }. The integer operations are add. .e. i. min. Operand a specifies a location in the specified state space. and max operations are single-precision. by inserting barriers between normal stores and reduction operations to a common address. s) = (r > s) ? s : r-1. red{. min. . or by using atom. and stores the result of the specified operation at location a. .add.min. . The address size may be either 32-bit or 64-bit.s32. If no state space is given. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. accesses to local memory are illegal. Description // // // // . .b32. January 24. dec(r. inc.type [a]. dec. and xor. .or. . max.u64. . The address must be naturally aligned to a multiple of the access size. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.e. or the instruction may fault. In generic addressing. red.add.max }. .exch to store to locations accessed by other reduction operations. e. i. The floating-point add. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. Addresses are zero-extended to the specified width as needed. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. If an address is not properly aligned.. s) = (r >= s) ? 0 : r+1. . .s32. .u64 .dec.. an address maps to the corresponding location in local or shared memory.u32.b32 only . perform the memory accesses using generic addressing. Within these windows.u32. and max. A register containing an address may be declared as a bit-size type or integer type. For red. an address maps to global memory unless it falls within the local memory window or the shared memory window.

f32.and.b32 [a].add. 2010 . 64-bit red.max} are unimplemented.add requires sm_12 or later.global requires sm_11 or later red.add.f32 red. Release Notes Examples @p 138 January 24.shared operations require sm_20 or later.max.global.2.my_val. red.{min.f32 requires sm_20 or later. [p].1.global.PTX ISA Version 2.shared. Use of generic addressing requires sm_20 or later.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.0.shared requires sm_12 or later. [x+4].s32 red. red. red. red. 64-bit red.

vote.none.ballot. The reduction modes are: .b32 requires sm_20 or later. vote requires sm_12 or later.pred vote.q. where the bit position corresponds to the thread’s lane id.b32 d.b32 p.pred vote. 2010 139 . .any True if source predicate is True for some active thread in warp. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. not across an entire CTA.q. p.uni }. returns bitmask . .ballot.uni. Negate the source predicate to compute . vote. r1. Negate the source predicate to compute . Description Performs a reduction of the source predicate across threads in a warp.mode. // ‘ballot’ form.pred d. // get ‘ballot’ across warp January 24.uni. Note that vote applies to threads in a single warp.all. . {!}a. {!}a. Instruction Set Table 104.not_all.ballot.uni True if source predicate has the same value in all active threads in warp. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.mode = { .p.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. .all.Chapter 8.all True if source predicate is True for all active threads in warp. The destination predicate value is the same across all threads in the warp.any.ballot. Negating the source predicate also computes . vote. vote. vote.2. In the ‘ballot’ form.

PTX ISA Version 2. 4.s33 values.u32 or . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).dtype.h1 }. b{.s34 intermediate result.extended internally to .dtype = .b0. vop. .dtype. perform a scalar arithmetic operation to produce a signed 34-bit result.b2. 2. Video Instructions All video instructions operate on 32-bit register operands. the input values are extracted and signor zero. atype.dsel = . .btype{. .s32) is specified in the instruction type. or word values from its source operands.btype = { . The sign of the intermediate result depends on dtype. The type of each operand (.btype{.dtype. a{. 140 January 24. 3.atype. . a{. .min. extract and sign. The primary operation is then performed to produce an .sat} d. The general format of video instructions is as follows: // 32-bit scalar operation. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. a{.0 8. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. to produce signed 33-bit input values.asel}.bsel}. b{.s32 }. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.or zero-extend byte.bsel}.secop = { . half-word. and btype are valid. b{. .dsel. .b1.atype.bsel = { . . Using the atype/btype and asel/bsel specifiers.asel}. with optional secondary operation vop. c. . // 32-bit scalar operation.add.9. The source and destination operands are all 32-bit registers.sat} d.atype = . 2010 . with optional data merge vop.u32.max }.b3.sat}.7.secop d. c. .asel = . . optionally clamp the result to the range of the destination type.btype{.bsel}.atype. taking into account the subword destination size in the case of optional data merging. all combinations of dtype.asel}.h0.

s33 c ) switch ( dsel ) { case . . tmp. . switch ( dsel ) { case . c). Instruction Set . January 24. c).s34 tmp. tmp.min: return MIN(tmp. .b1: return ((tmp & 0xff) << 8) case . } } .h0. . S32_MIN ). . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).Chapter 8. 2010 141 .b2. c). The sign of the c operand is based on dtype. as shown in the following pseudocode. .b3: return ((tmp & 0xff) << 24) default: return tmp.b1. .s33 optMerge( Modifier dsel.s33 tmp. . .s33 c) { switch ( secop ) { . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. U16_MIN ).b0.s33 tmp. U32_MAX.b0: return ((tmp & 0xff) case . tmp.s33 optSaturate( . S8_MIN ). U8_MIN ). S32_MAX. tmp. U32_MIN ). . S8_MAX.b3: if ( sign ) return CLAMP( else return CLAMP( case . Bool sat. S16_MIN ).max return MAX(tmp. U8_MAX. U16_MAX. . c).s33 optSecOp(Modifier secop. tmp. c). c). Bool sign.b2: return ((tmp & 0xff) << 16) case .add: return tmp + c. default: return tmp.h0: return ((tmp & 0xffff) case . c).h1: return ((tmp & 0xffff) << 16) case . Modifier dsel ) { if ( !sat ) return tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. The lower 32-bits are then written to the destination operand. S16_MAX.

vmin. and optional secondary arithmetic operation or subword data merge. vmax vadd.dsel .asel}. isSigned(dtype). vmax }.btype{. tmp = MAX( ta.h0. .h1 }.btype{.s32. .u32. btype. r2. Semantics // saturate. r3. r2. // 32-bit scalar operation. b{. sat.sat vabsdiff. vop. bsel ).s32.min. vabsdiff. vadd.asel = .s32.s32. . .h0.atype.sat vmin. Integer byte/half-word/word absolute value of difference.b3. // optional merge with c operand 142 January 24. vmax Syntax Integer byte/half-word/word addition / subtraction. asel ).sat}. tb ). vmax require sm_20 or later. tmp.bsel}.b2. c ). r1.sat vsub. vsub. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.op2 d.sat} d.b0. .0 Table 105.h1.dtype . Integer byte/half-word/word minimum / maximum. r1.u32. // 32-bit scalar operation. vmin. vadd. r2.u32.b2. r3. r3. tmp = | ta – tb |.atype.bsel = { . c. vabsdiff. with optional data merge vop.or zero-extend based on source operand type ta = partSelectSignExtend( a. tmp = ta – tb. a{.sat.0. r2.add r1.dtype.b0. dsel ). vabsdiff.btype = { . tb = partSelectSignExtend( b.h1. . . b{. { .bsel}. c ).asel}. a{.atype = . r1.sat} d.PTX ISA Version 2. vsub.s32.h0.add.s32 }. 2010 . a{.s32. Video Instructions: vadd.op2 Description = = = = { vadd. c. c.bsel}. vsub vabsdiff vmin.max }.atype.asel}.btype{. vsub.b1.s32.b0. r3.s32. taking into account destination type and merge operations tmp = optSaturate( tmp. tb ). . atype.s32. d = optSecondaryOp( op2. vmin. // extract byte/half-word/word and sign. . c.dsel.dtype. .vop . tmp = MIN( ta. Perform scalar arithmetic operation with optional saturate. . with optional secondary operation vop. b{. // optional secondary operation d = optMerge( dsel.s32.dtype.

bsel}. b{. if ( mode == . if ( mode == . asel ). with optional data merge vop.u32{.Chapter 8.clamp. with optional secondary operation vop.u32.u32. a{. Semantics // extract byte/half-word/word and sign.u32.clamp && tb > 32 ) tb = 32.dtype. tb = partSelectSignExtend( b. January 24. vshr vshl.s32. switch ( vop ) { case vshl: tmp = ta << tb. unsigned shift fills with zero. Video Instructions: vshl.b3. c. . vshl. c. .mode}.wrap ) tb = tb & 0x1f. and optional secondary arithmetic operation or subword data merge. and optional secondary arithmetic operation or subword data merge. } // saturate.max }. r1. vshl. r2. . d = optSecondaryOp( op2.0.vop . sat. vshr }.add. b{.atype.min. . { .s32 }.bsel}. r2.u32{. Instruction Set Table 106. .wrap r1. isSigned(dtype). tmp. .h0. .b0. .bsel = { . { .h1 }.dsel .op2 Description = = = = = { vshl.asel}. tmp.u32{. vshl: Shift a left by unsigned amount in b with optional saturate. vop.sat}{.u32. r3. . // default is . 2010 143 .wrap }. bsel ). // optional secondary operation d = optMerge( dsel. .h1. taking into account destination type and merge operations tmp = optSaturate( tmp. vshr require sm_20 or later. . // 32-bit scalar operation. vshr Syntax Integer byte/half-word/word left / right shift.dtype. a{. Left shift fills with zero.atype.or zero-extend based on source operand type ta = partSelectSignExtend( a.dtype.asel}.mode} d.clamp .u32.u32.bsel}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .sat}{.asel = .b1. c ).u32 vshr.atype = { .op2 d.b2.asel}. case vshr: tmp = ta >> tb. dsel ).mode .dtype . r3.dsel.sat}{. b{. vshr: Shift a right by unsigned amount in b with optional saturate. atype. a{. c ).mode} d.atype. // 32-bit scalar operation. Signed shift fills with the sign bit.

.shr15 }.po mode. a{. . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.b0. {-}c. PTX allows negation of either (a*b) or c.scale} d.bsel = { .0 Table 107.sat}{. The source operands support optional negation with some restrictions. b{.S32 // intermediate signed.s32 }. .btype = { . the intermediate result is signed. . (a*b) is negated if and only if exactly one of a or b is negated.h0.. final signed (S32 * S32) + S32 // intermediate signed. which is used in computing averages. and scaling. this result is sign-extended if the final result is signed.po{. .b2.b3. c.sat}{. {-}b{. final signed -(U32 * S32) + S32 // intermediate signed.scale = { .atype. .asel}.shr7. final signed The intermediate result is optionally scaled via right-shift. . . . {-}a{. 144 January 24. Input c has the same sign as the intermediate result. final signed -(S32 * S32) + S32 // intermediate signed. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.dtype. final signed (S32 * U32) + S32 // intermediate signed.h1 }. and the operand negates. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.b1. final signed (S32 * U32) . That is.po) computes (a*b) + c + 1. // 32-bit scalar operation vmad.PTX ISA Version 2. Depending on the sign of the a and b operands. Source operands may not be negated in .asel = .asel}.S32 // intermediate signed. final signed -(S32 * U32) + S32 // intermediate signed. 2010 .S32 // intermediate signed.dtype = .U32 // intermediate unsigned. The “plus one” mode (. with optional operand negates. final signed (U32 * S32) + S32 // intermediate signed.atype = .scale} d. internally this is represented as negation of the product (a*b).btype.bsel}. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.dtype. final signed (U32 * S32) .btype{. otherwise. The final result is unsigned if the intermediate result is unsigned and c is not negated. . final signed (U32 * U32) . Description Calculate (a*b) + c. and zero-extended otherwise. vmad. Although PTX syntax allows separate negation of the a and b operands. “plus one” mode. final unsigned -(U32 * U32) + S32 // intermediate signed.bsel}.atype. final signed (S32 * S32) .u32.

} else if ( a. 2010 145 .u32.Chapter 8. r0. vmad. bsel ).0. January 24. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 1.u32.sat vmad. r2.po ) { lsb = 1. -r3. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.h0. if ( . tmp = tmp + c128 + lsb.sat ) { if (signedFinal) result = CLAMP(result. tb = partSelectSignExtend( b. lsb = 1.s32.negate ) { c = ~c. U32_MIN). r1. tmp[127:0] = ta * tb.shr7: result = (tmp >> 7) & 0xffffffffffffffff. switch( scale ) { case . lsb = 0.or zero-extend based on source operand type ta = partSelectSignExtend( a.h0. S32_MIN).negate ^ b.negate) || c. r3. r1. U32_MAX. case . } else if ( c. asel ). else result = CLAMP(result. S32_MAX. Instruction Set Semantics // extract byte/half-word/word and sign.u32. r2.u32. } if ( .s32. atype.negate.negate ) { tmp = ~tmp. signedFinal = isSigned(atype) || isSigned(btype) || (a.shr15 r0. vmad requires sm_20 or later.negate ^ b.shr15: result = (tmp >> 15) & 0xffffffffffffffff. btype.

btype = { . r1.asel}.dsel . . bsel ). .ne r1.add. .h1.bsel}. with optional data merge vset. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.PTX ISA Version 2. // optional secondary operation d = optMerge( dsel.lt vset. with optional secondary arithmetic operation or subword data merge.u32.b2. b{. r3.bsel}.dsel. c ).h1 }. vset requires sm_20 or later.bsel}. asel ). { .asel}. c. // 32-bit scalar operation. a{. and therefore the c operand and final result are also unsigned. . 146 January 24. vset.ne. d = optSecondaryOp( op2.btype.atype . . . . atype.cmp d. btype. vset.gt. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .min.op2 Description = = = = . tb. . a{. tmp = compare( ta. .or zero-extend based on source operand type ta = partSelectSignExtend( a.b1. .max }.cmp.u32.b0. The intermediate result of the comparison is always unsigned.s32 }. b{. r3.eq.b3.atype.s32.bsel = { .cmp .lt. 2010 . a{.cmp d. . c.le. tb = partSelectSignExtend( b. c ). tmp.asel = . .u32.h0. Semantics // extract byte/half-word/word and sign.atype.0 Table 108. cmp ) ? 1 : 0. .btype. . // 32-bit scalar operation. b{. Compare input values using specified comparison.op2 d.btype.ge }.asel}. r2. tmp. r2.0.atype. with optional secondary operation vset. { .u32.

Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Table 110. Notes PTX ISA Notes Target ISA Notes Examples Currently.0. Instruction Set 8. brkpt. pmevent a.Chapter 8. Supported on all target architectures. Introduced in PTX ISA version 1. trap. brkpt.0. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. brkpt requires sm_11 or later.7. Supported on all target architectures. pmevent 7. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. numbered 0 through 15.10. trap.4. January 24. 2010 147 . there are sixteen performance monitor events. with index specified by immediate operand a. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Triggers one of a fixed number of performance monitor events. Introduced in PTX ISA version 1. The relationship between events and counters is programmed via API calls from the host. @p pmevent 1. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. trap Abort execution and generate an interrupt to the host CPU. Table 111. brkpt Suspends execution Introduced in PTX ISA version 1.

PTX ISA Version 2. 2010 .0 148 January 24.

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. read-only variables. %clock64 %pm0. %lanemask_ge. …. %pm3 January 24. Special Registers PTX includes a number of predefined. %lanemask_gt %clock. %lanemask_lt. %lanemask_le.Chapter 9. which are visible as special registers and accessed through mov or cvt instructions. 2010 149 .

Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.x 0 <= %tid. // move tid.z == 0 in 1D CTAs.0.x. PTX ISA Notes Introduced in PTX ISA version 1. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u32 %h1.%tid. Redefined as . 2010 . %tid. %tid.0.u32.x * %ntid.v4 . // thread id vector // thread id components A predefined. .y * %ntid.z.0.z. the fourth element is unused and always returns zero.%h2.y == %tid.z. per-thread special register initialized with the thread identifier within the CTA.%ntid. %ntid.y 0 <= %tid. mov. mov.x < %ntid.z).x.%tid.u32 %ntid.u16 %rh.y.x code accessing 16-bit component of %tid mov.u32 %tid. CTA dimensions are non-zero.y < %ntid.0.PTX ISA Version 2. %ntid.x. Supported on all target architectures. The fourth element is unused and always returns zero.sreg . mov. It is guaranteed that: 0 <= %tid. %ntid.%h1. . Supported on all target architectures. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.x.z < %ntid. .z PTX ISA Notes Introduced in PTX ISA version 1. // CTA shape vector // CTA dimensions A predefined.x to %rh Target ISA Notes Examples // legacy PTX 1.u16 %r2. The total number of threads in a CTA is (%ntid.u32 type in PTX 2.x. %ntid. %tid.y. mov.u32 %h2. // legacy PTX 1.x.y == %ntid. // compute unified thread id for 2D CTA mov. cvt. The number of threads in each dimension are specified by the predefined special register %ntid. 2D.sreg . or 3D vector to match the CTA shape.v4 . read-only.z == 1 in 2D CTAs.v4. read-only special register initialized with the number of thread ids in each CTA dimension.x. Redefined as .%ntid. the %tid value in unused dimensions is 0.u32 %r0.z == 0 in 2D CTAs.u32 %tid. Every thread in the CTA has a unique %tid.%tid.%r0. The %tid special register contains a 1D.z == 1 in 1D CTAs.z to %r2 Table 113.u32 %r1.y.u32 type in PTX 2. %tid component values range from 0 through %ntid–1 in each CTA dimension.u16 %rh.sreg .u32 %r0.v4.u32 %ntid. // zero-extend tid.0 Table 112.x code Target ISA Notes Examples 150 January 24. mad. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.%tid.%tid. . %tid.sreg .

u32 %r.3.u32 %r. Introduced in PTX ISA version 2.u32 %laneid. Table 115. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. January 24. %nwarpid. read-only special register that returns the thread’s warp identifier.3. read-only special register that returns the maximum number of warp identifiers. e.sreg . mov. %nwarpid requires sm_20 or later. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. mov. %warpid.u32 %warpid.0. The lane identifier ranges from zero to WARP_SZ-1. Introduced in PTX ISA version 1.Chapter 9.u32 %nwarpid. Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Table 116. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. due to rescheduling of threads following preemption. .g.sreg . The warp identifier will be the same for all threads within a single warp. 2010 151 . read-only special register that returns the thread’s lane within the warp.sreg . . mov. A predefined. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. A predefined. For this reason.u32 %r. Note that %warpid is volatile and returns the location of a thread at the moment when read. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. but its value may change during execution. Supported on all target architectures. Special Registers Table 114. %laneid. Supported on all target architectures. . A predefined.

z < %nctaid.536 PTX ISA Notes Introduced in PTX ISA version 1.v4.u32 type in PTX 2. %ctaid.sreg .sreg .u32 mov. The fourth element is unused and always returns zero.0 Table 117. with each element having a value of at least 1.u32 %nctaid .x.y < %nctaid. or 3D vector. 2010 . .x.%nctaid. read-only special register initialized with the number of CTAs in each grid dimension. The %nctaid special register contains a 3D grid shape vector.x code Target ISA Notes Examples 152 January 24. %rh. // Grid shape vector // Grid dimensions A predefined. Supported on all target architectures. mov. %ctaid. The %ctaid special register contains a 1D.{x. read-only special register initialized with the CTA identifier within the CTA grid. mov.0.0.u16 %r0. It is guaranteed that: 0 <= %ctaid.u32 mov. // CTA id vector // CTA id components A predefined.sreg .%nctaid.z.v4 .z. // legacy PTX 1.u16 %r0. Redefined as .u32 %nctaid.%nctaid.y.y. Each vector element value is >= 0 and < 65535.sreg . 2D.u32 type in PTX 2. . It is guaranteed that: 1 <= %nctaid. Supported on all target architectures.y.%ctaid.v4.v4 .%ctaid.x 0 <= %ctaid. %rh. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. Redefined as .z PTX ISA Notes Introduced in PTX ISA version 1.y 0 <= %ctaid.x. The fourth element is unused and always returns zero.x.PTX ISA Version 2.x.x code Target ISA Notes Examples Table 118. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.y. .u32 %ctaid.u32 %ctaid. // legacy PTX 1.0. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. depending on the shape and rank of the CTA grid.z} < 65.0.%nctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.x < %nctaid.

Introduced in PTX ISA version 2. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.sreg . The SM identifier numbering is not guaranteed to be contiguous. mov. 2010 153 . Note that %smid is volatile and returns the location of a thread at the moment when read. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.sreg . Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. read-only special register that returns the maximum number of SM identifiers. mov. PTX ISA Notes Target ISA Notes Examples Table 121. %nsmid. Special Registers Table 119. but its value may change during execution.0. where each launch starts a grid-of-CTAs. Introduced in PTX ISA version 1. A predefined. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %nsmid. PTX ISA Notes Target ISA Notes Examples January 24.sreg . read-only special register initialized with the per-grid temporal grid identifier. %gridid. The SM identifier numbering is not guaranteed to be contiguous. %nsmid requires sm_20 or later. e. .u32 %smid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.u32 %r. // initialized at grid launch A predefined. The SM identifier ranges from 0 to %nsmid-1. . Supported on all target architectures.3. Introduced in PTX ISA version 1. mov.Chapter 9.g.u32 %gridid. Notes PTX ISA Notes Target ISA Notes Examples Table 120. This variable provides the temporal grid launch number for this context. so %nsmid may be larger than the physical number of SMs in the device. repeated launches of programs may occur. . During execution. due to rescheduling of threads following preemption. Supported on all target architectures. %smid.u32 %r.u32 %r.0. A predefined.

2010 . %lanemask_le requires sm_20 or later. A predefined. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. mov. . A predefined. mov. %lanemask_eq. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg . %lanemask_eq requires sm_20 or later.u32 %r.u32 %lanemask_lt.u32 %r. .u32 %lanemask_eq. Introduced in PTX ISA version 2. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. mov.sreg . Introduced in PTX ISA version 2. Table 123.0 Table 122. 154 January 24. %lanemask_le. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. . Introduced in PTX ISA version 2.0.PTX ISA Version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later.u32 %lanemask_le. A predefined.0.u32 %r. Table 124. %lanemask_lt.0.sreg .

%lanemask_ge requires sm_20 or later.u32 %r. Table 126. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg . mov. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r.0. Introduced in PTX ISA version 2. mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. A predefined.sreg . %lanemask_gt requires sm_20 or later. 2010 155 .Chapter 9. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. January 24. %lanemask_gt. Introduced in PTX ISA version 2.u32 %lanemask_ge.0. Special Registers Table 125. . .u32 %lanemask_gt. A predefined. %lanemask_ge.

Introduced in PTX ISA version 1. . Supported on all target architectures. Their behavior is currently undefined.u64 r1.%clock64. %pm1. and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.PTX ISA Version 2. Special registers %pm0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.0 Table 127. read-only 64-bit unsigned cycle counter. Supported on all target architectures.u32 %clock.%pm0.3. Table 128.0. mov. 2010 . mov. %pm2. Introduced in PTX ISA version 2. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.u32 r1. %pm2. %pm3. 156 January 24.u64 %clock64. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. %clock64 requires sm_20 or later. %pm1. . read-only 32-bit unsigned cycle counter. mov. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Special Registers: %pm0. The lower 32-bits of %clock64 are identical to %clock. %pm2. %pm3 %pm0.u32 r1. …. . Table 129.%clock.0.sreg .sreg .u32 %pm0.sreg . Introduced in PTX ISA version 1.

version 1. minor are integers Specifies the PTX language version number.target Table 130. 2010 157 . .Chapter 10. . Duplicate . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . and the target architecture for which the code was generated.version major. Directives 10.4 January 24.version directive.version 2. Each ptx file must begin with a .version .0.version . PTX File Directives: . Supported on all target architectures. Increments to the major number indicate incompatible changes to PTX.version Syntax Description Semantics PTX version number.version directive.version directives are allowed provided they match the original .minor // major. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.1.0 .

where each generation adds new features and retains all features of previous generations. but subsequent . The following table summarizes the features in PTX that vary according to target architecture. sm_10. 158 January 24.f32.red}. A .global.texmode_unified) .f64 to .texmode_independent texture and sampler information is bound together and accessed via a single . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Therefore.target directives can be used to change the set of target features allowed during parsing.red}.0.red}. Requires map_f64_to_f32 if any . Each PTX file must begin with a . sm_12. Adds {atom. Introduced in PTX ISA version 1. Supported on all target architectures. texmode_independent. sm_11.target . map_f64_to_f32 }. The texturing mode is specified for an entire module and cannot be changed within the module. A program with multiple . sm_13. and an error is generated if an unsupported feature is used.0 Table 131.PTX ISA Version 2. generations of SM architectures follow an “onion layer” model. In general. Adds double-precision support. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. PTX code generated for a given target can be run on later generation devices. Texturing mode: (default is .f64 instructions used. Description Specifies the set of features in the target architecture for which the current ptx code was generated. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. texture and sampler information is referenced with independent . PTX File Directives: . .target Syntax Architecture and Platform target. PTX features are checked against the specified target architecture.target directive containing a target architecture and optional platform options.5. Disallows use of map_f64_to_f32.f64 instructions used. with only half being used by instructions converted from .target directive specifies a single target architecture. including expanded rounding modifiers.samplerref descriptors.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. 64-bit {atom. 2010 . Target sm_20 Description Baseline feature set for sm_20 architecture.texref descriptor. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.global. Requires map_f64_to_f32 if any . brkpt instructions. texmode_unified.f64 instructions used. immediately followed by a . Adds {atom. Note that .texref and . vote instructions. Texturing mode introduced in PTX ISA version 1.version directive.shared.f64 storage remains as 64-bits.texmode_unified . Requires map_f64_to_f32 if any .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.

Directives Examples . texmode_independent January 24. 2010 159 .Chapter 10.target sm_13 // supports double-precision .target sm_20.target sm_10 // baseline target architecture .

and query instructions and cannot be accessed via ld.4 and later. store. %ntid.param.param instructions. parameter variables are declared in the kernel body. . For PTX ISA versions 1. and body for the kernel function.0 through 1. parameter variables are declared in the kernel parameter list.reg .param.entry kernel-name ( param-list ) kernel-body . Supported on all target architectures.5 and later.param { .param .func Table 132. .0 10. ld. 160 January 24.entry . ld. Kernel and Function Directives: . The shape and size of the CTA executing the kernel are available in special registers.surfref variables may be passed as parameters. .PTX ISA Version 2.b32 x. Parameters are passed via . [z].b32 %r<99>. These parameters can only be referenced by name within texture and surface load. etc. In addition to normal parameters. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.2. At kernel launch.param. 2010 . %nctaid. [y]. … } . and .b32 %r2.texref.b32 z ) Target ISA Notes Examples [x]. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.0 through 1.param .param instructions.3. opaque . e.g.b32 y.entry cta_fft .entry filter ( .entry kernel-name kernel-body Defines a kernel entry point name. Semantics Specify the entry point for a kernel program. with optional parameters. the kernel dimensions and properties are established and made available via special registers.4. . .entry Syntax Description Kernel entry point and body.param space memory and are listed within an optional parenthesized parameter list.b32 %r3. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. PTX ISA Notes For PTX ISA version 1.b32 %r1.samplerref. Parameters may be referenced by name within the kernel body and loaded into registers using ld. ld.entry . parameters. .

param state space.reg .reg . implements an ABI with stack.b32 localVar.Chapter 10. mov.f64 dbl) { .b32 N.reg . … Description // return value in fooval January 24. including input and return parameters and optional function body. … use N.func (ret-param) fname (param-list) function-body Defines a function. if any. which may use a combination of registers and stack locations to pass parameters. . } … call (fooval). The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Parameters in register state space may be referenced directly within instructions in the function body.0 with target sm_20 allows parameters in the .param and st. PTX 2. ret. and recursion is illegal.func .0.func (. PTX ISA 2. A . The parameter lists define locally-scoped variables in the function body. Kernel and Function Directives: .x code. Variadic functions are represented using ellipsis following the last fixed argument. and supports recursion.param instructions in the body. dbl.func fname function-body . Parameters must be base types in either the register or parameter state space. Variadic functions are currently unimplemented. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.func definition with no body provides a function prototype.2 for a description of variadic functions.b32 rval) foo (. foo.param space are accessed using ld. (val0. val1).func Syntax Function definition. Supported on all target architectures. Parameters in . Directives Table 133. Parameter passing is call-by-value.0 with target sm_20 supports at most one return value.result. other code. parameters must be in the register state space. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. there is no stack.reg . The implementation of parameter passing is left to the optimizing translator.func fname (param-list) function-body .b32 rval. . . Release Notes For PTX ISA version 1. 2010 161 .

pragma directive is supported for passing information to the PTX backend.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. to throttle the resource requirements (e. or as statements within a kernel or device function body. .maxnreg. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.maxntid . registers) to increase total thread count and provide a greater opportunity to hide memory latency. Note that . for example. at entry-scope. The .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.minnctapersm directives may be applied per-entry and must appear between an .3.maxntid. PTX supports the following directives. and . .entry directive and its body.maxnreg . the . Currently. The interpretation of .g. the . The directive passes a list of strings to the backend.pragma The . and the .0 10. which pass information to the backend optimizing compiler.maxnctapersm (deprecated) . 2010 . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. 162 January 24. The directives take precedence over any module-level constraints passed to the optimizing backend.maxntid directive specifies the maximum number of threads in a thread block (CTA).minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).pragma directives may appear at module (file) scope.PTX ISA Version 2.minnctapersm . A general .maxntid and . These can be used. and the strings have no semantics within the PTX virtual machine model.maxnreg directive specifies the maximum number of registers to be allocated to a single thread.

Introduced in PTX ISA version 1. or the maximum number of registers may be further constrained by .entry foo .maxntid nx .3.maxntid and .maxntid nx. The actual number of registers used may be less. Supported on all target architectures. for example.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. the backend may be able to compile to fewer registers. .maxntid nx.entry foo .maxntid 256 .maxntid Syntax Maximum number of threads in thread block (CTA). ny.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. The maximum number of threads is the product of the maximum extent in each dimension.maxntid . The compiler guarantees that this limit will not be exceeded.maxntid 16. Introduced in PTX ISA version 1. Performance-Tuning Directives: .3. ny .Chapter 10. . or 3D CTA. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Performance-Tuning Directives: . .16. . Directives Table 134. 2010 163 . Supported on all target architectures.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxctapersm. This maximum is specified by giving the maximum extent of each dimention of the 1D. 2D. nz Declare the maximum number of threads in the thread block (CTA).maxnreg . Exceeding any of these limits results in a runtime error or kernel launch failure.entry bar .maxnreg n Declare the maximum number of registers per thread in a CTA.

minnctapersm .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm (deprecated) .3. additional CTAs may be mapped to a single multiprocessor.maxntid to be specified as well.0 Table 136. Deprecated in PTX ISA version 2.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). The optimizing backend compiler uses .0 as a replacement for .maxntid and . Optimizations based on . .PTX ISA Version 2. Performance-Tuning Directives: . For this reason.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Performance-Tuning Directives: . Introduced in PTX ISA version 2. if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). .entry foo .minnctapersm in PTX ISA version 2. However.0.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. Supported on all target architectures.entry foo . .maxntid 256 .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm has been renamed to .maxntid 256 . Optimizations based on . 2010 .minnctapersm 4 { … } 164 January 24.maxntid to be specified as well. .maxnctapersm generally need . Introduced in PTX ISA version 1.0. Supported on all target architectures. .maxnctapersm.minnctapersm generally need .

pragma directive strings is implementation-specific and has no impact on PTX semantics. 2010 165 .pragma “nounroll”. .0.pragma . Introduced in PTX ISA version 2.pragma directive may occur at module-scope.pragma list-of-strings . { … } January 24. The interpretation of . Supported on all target architectures.pragma “nounroll”. The . or at statementlevel.Chapter 10. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .entry foo . . Performance-Tuning Directives: . entry-scoped. at entry-scope. or statement-level directives to the PTX backend compiler.pragma Syntax Description Pass directives to PTX backend compiler. Pass module-scoped. Directives Table 138. See Appendix A for descriptions of the pragma strings defined in ptxas.

@progbits .byte 0x00. 0x61395a5f.. 0x00.2. 2010 .section directive is new in PTX ISA verison 2. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x00.PTX ISA Version 2.4byte label . Introduced in PTX ISA version 1.quad int64-list // comma-separated hexadecimal integers in range [0.232-1] .264-1] .0 but is supported for legacy PTX version 1. 0x6150736f.byte 0x2b.section directive. 0x00000364.x code. 0x63613031.4byte 0x6e69616d. Deprecated as of PTX 2. 0x736d6172 .debug_info .4.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.debug_pubnames. 0x00. 0x00. Table 139. replaced by . 0x02. @@DWARF dwarf-string dwarf-string may have one of the .section . 0x00 .0 and replaces the @@DWARF syntax.4byte . 0x5f736f63 . The @@DWARF syntax is deprecated as of PTX version 2.0 10. Supported on all target architectures.4byte int32-list // comma-separated hexadecimal integers in range [0. 0x00 166 January 24. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .loc The . “”.file . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF ..0. 0x00.4byte 0x000006b5.section . 0x00.byte byte-list // comma-separated hexadecimal byte values .

b32 int32-list // comma-separated list of integers in range [0. .. 0x00.232-1] . 0x736d6172 0x00 Table 141.264-1] . Source file information.0.file . Supported on all target architectures. Debugging Directives: .b64 int64-list // comma-separated list of integers in range [0. 0x00.b32 . 0x00.section Syntax PTX section definition..b8 0x2b. . . replaces @@DWARF syntax.b32 label . Supported on all target architectures.section . Debugging Directives: . 0x5f736f63 0x6150736f. .section ..b32 0x000006b5.0.255] . 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b8 byte-list // comma-separated list of integers in range [0.debug_pubnames { . 0x00. .loc line_number January 24.b8 0x00. Directives Table 140.0. 0x00. 0x63613031. Source file location. } 0x02. . 0x00000364.b32 0x6e69616d. 2010 167 . 0x00 0x61395a5f. .file filename Table 142.Chapter 10. Debugging Directives: .section section_name { dwarf-lines } dwarf-lines have the following formats: .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Supported on all target architectures.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.debug_info .loc .

0 10.b32 foo. . Supported on all target architectures. // foo is defined in another module Table 144. .b32 foo. . Linking Directives: . 2010 .extern identifier Declares identifier to be defined externally. Linking Directives: .visible .extern .global .visible Table 143.visible identifier Declares identifier to be externally visible.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern . // foo will be externally visible 168 January 24.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures. Linking Directives .0.extern .global .visible .0.6. Introduced in PTX ISA version 1.PTX ISA Version 2. . Introduced in PTX ISA version 1.

4 PTX ISA 1.0.0 driver r195 PTX ISA Version PTX ISA 1. and the remaining sections provide a record of changes in previous releases. CUDA Release CUDA 1.0 CUDA 2.2 CUDA 2.1 CUDA 2.3 PTX ISA 1.2 PTX ISA 1.0 CUDA 1.3 driver r190 CUDA 3. 2010 169 . The first section describes ISA and implementation changes in the current release of PTX ISA 2.Chapter 11.1 CUDA 2.0 PTX ISA 1.0 January 24.5 PTX ISA 2. The release history is as follows. Release Notes This section describes the history of change in the PTX ISA and implementation.1 PTX ISA 1.

and double-precision div.f32 and mad. New Features 11.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.1. and mul now support .1. rcp.PTX ISA Version 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. sub.f32 for sm_20 targets. A single-precision fused multiply-add (fma) instruction has been added.0 11. The changes from PTX ISA 1.1. When code compiled for sm_1x is executed on sm_20 devices. while maximizing backward compatibility with legacy PTX 1. Single-precision add.0 11. • • • • • 170 January 24.sat modifiers. Floating-Point Extensions This section describes the floating-point changes in PTX 2.1. mad.rp rounding modifiers for sm_20 targets. Changes in Version 2. The fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 require a rounding modifier for sm_20 targets.rm and . fma. The goal is to achieve IEEE 754 compliance wherever possible.0 for sm_20 targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.ftz modifier may be used to enforce backward compatibility with sm_1x. and sqrt with IEEE 754 compliant rounding have been added. The . Instructions testp and copysign have been added.x code and sm_1x targets. Both fma. These are indicated by the use of a rounding modifier and require sm_20.f32 instruction also supports .f32 maps to fma. 2010 .1. The mad. The mad.1.f32 requires sm_20.rn.ftz and . Single.f32.

Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. A “find leading non-sign bit” instruction. January 24. st. Cache operations have been added to instructions ld.b32.ge. New special registers %nsmid.u32 and bar.lt.Chapter 11. ldu. %clock64.red. has been added. The . suld. has been added. The bar instruction has been extended as follows: • • • A bar.1. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. bar now supports optional thread count and register operands. Instructions bar.2. st. A “population count” instruction. prefetch.minnctapersm to better match its behavior and usage. Instructions {atom. has been added.gt} have been added.1.g. vote. Instructions prefetch and prefetchu have also been added.red}. A “vote ballot” instruction. A system-level membar instruction. Instruction sust now supports formatted surface stores. and red now support generic addressing. New instructions A “load uniform” instruction. local.section.red}.f32 have been implemented.clamp and . has been added. and sust.popc.1. A “bit reversal” instruction. brev. Other new features Instructions ld. has been added. Instructions {atom. Instruction cvta for converting global. for prefetching to specified level of memory hierarchy.ballot.or}.le. e. bfind. Video instructions (includes prmt) have been added.arrive instruction has been added. Surface instructions support additional . and shared addresses to generic address and vice-versa has been added. prefetchu. A new directive.{and. bfe and bfi. 11. Bit field extract and insert instructions. atom. Release Notes 11.pred have been added. %lanemask_{eq. 2010 171 . have been added. cvta. A “count leading zeros” instruction. popc.zero. . .sys.red. membar.1. ldu.3. has been added. has been added.maxnctapersm directive was deprecated and replaced with .add. isspacep.clamp modifiers.shared have been extended to handle 64-bit data types for sm_20 targets. clz.

{u32. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.3.1.p.f32} atom. Formatted surface load is unimplemented. To maintain compatibility with legacy PTX code. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.f32 type is unimplemented. Support for variadic functions and alloca are unimplemented.version is 1. .4 or earlier. 172 January 24. cvt.p sust. Semantic Changes and Clarifications The errata in cvt. Formatted surface store with .4 and earlier.0 11.u32.s32. 2010 .target sm_1x. See individual instruction descriptions for details. if . {atom.ftz for PTX ISA versions 1. or . 11. has been fixed.max} are not implemented. In PTX version 1.ftz (and cvt for . call suld. Instruction bra.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.5.1.PTX ISA Version 2.s32. The underlying. where .5 and later.f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.{min. stack-based ABI is unimplemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. the correct number is sixteen.2.red}.

Supported only for sm_20 targets.Appendix A. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. Note that in order to have the desired effect at statement level.pragma. disables unrolling for all loops in the entry function body.pragma “nounroll”.pragma “nounroll”. { … } // do not unroll any loop in this function . 2010 173 . .0. disables unrolling of0 the loop for which the current block is the loop header.func bar (…) { … L1_head: . . and statement levels. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma “nounroll”. including loops preceding the . The “nounroll” pragma is allowed at module. Table 145.pragma Strings This section describes the . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. entry-function. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. Ignored for sm_1x targets. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. L1_body: … L1_continue: bra L1_head. L1_end: … } // do not unroll this loop January 24. Descriptions of .entry foo (…) . … @p bra L1_end. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma strings defined by ptxas.

PTX ISA Version 2.0 174 January 24. 2010 .

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