NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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....... 42 Arrays as Operands ........................2... Operand Type Information ...........................................3......... 47 Chapter 7...........1........................................................2..1...........................4...4........................................... 5..................... 39 Parameterized Variable Names .. Texture.............................5................... 6........................... 32 5............... 41 6.......2.................... Operand Costs ........ 32 Texture State Space (deprecated) ..... 5.....6.... Sampler..................3............................ 25 Chapter 5....... 5....................................................... 39 5................................. 5.............. 27 Register State Space .......... 37 Vectors ........... 29 Local State Space .........................5......................4..... 6......... 6. 6.................. 41 Using Addresses..6............4.................... 33 Restricted Use of Sub-Word Sizes ..1.........................8.......4................................... and Surface Types ...............................................................................1......................... 5...........................2............................................................................................................... State Spaces .... 33 5. 5...............................3...................... 37 Array Declarations ..1.... and Vectors ....................................................... 30 Shared State Space.......................................................2...................................................................................3................................ 6............................... 5.......... State Spaces.........6....... 43 6............................................................. 46 6................................ 44 Rounding Modifiers ........5.........4............................. Types ....................................................... 43 Labels and Function Names as Operands ....4..................................6...............................................................................................4............................. 29 Parameter State Space .................................................. 42 Addresses as Operands .................................................. 5............................ 41 Destination Operands ... Summary of Constant Expression Evaluation Rules ...........1.................................................4..............1.......................... Chapter 6................................................................................... Types..........4..2............................................7.......................................................................................5........................................... 49 ii January 24................................................ and Variables ..................... 49 7...... 38 Alignment ........................... Function declarations and definitions ................... 28 Constant State Space ..............1.....3....1..................................................... 2010 .....2..................... 41 Source Operands....... 6..............2...........................4................ 43 Vectors as Operands .... Type Conversion.........1.................. 33 Fundamental Types ............................................................... 5............................................2......................PTX ISA Version 2...........................................0 4. Instruction Operands..... 38 Initializers ............1...........................................................................................................................4............1...................1..........4............................... 6.....5.... 5................................... 6............. 5..........4............. 5...................... 27 5......................1........................... Arrays.....5.............1..............................4............................................ 37 Variable Declarations ........................................................... 5....... 34 Variables .................... 5........ Abstracting the ABI .................................. 44 Scalar Conversions ...... 6.................................1........................................ 28 Special Register State Space ........ 5................................ 29 Global State Space ................................................................................................. 5...........

...3..0 ..................7...........6......... 8.............2.... 62 Machine-Specific Semantics of 16-bit Code ...............................1.................................... 2010 iii .. Format and Semantics of Instruction Descriptions ....... 62 Semantics .....4...........3................ Chapter 9............... 53 Alloca ........ 132 Video Instructions ............... 10......... 52 Variadic functions ............... 104 Data Movement and Conversion Instructions ..................................................................... 60 8....3.................. 10...............................8.........................x ..............................................................4.... Directives .....................1........ 59 Operand Size Exceeding Instruction-Type Size ............. Changes from PTX 1.................................................7...... 7.....................................................7......................... 122 Control Flow Instructions ......... 55 8....................... 8........... 172 Unimplemented Features Remaining ........2..................................................7................................................................................. 63 Integer Arithmetic Instructions ............................................................7.......................................................7.....7..7........................................................................................................... 81 Comparison and Selection Instructions ............................................ 11....................................................................... Divergence of Threads in Control Constructs .................................. 8....................5...................... 8..................................... 170 Semantic Changes and Clarifications ............................. 100 Logic and Shift Instructions .................................1. 11...................................... 8................. Release Notes .......3................1............................ 58 8............9..........................6.............. PTX Version and Target Directives ............................. 172 January 24.................1............................ 54 Chapter 8............................................................... 149 Chapter 10. 168 Chapter 11.........................1.........7.......... 157 Specifying Kernel Entry Points and Functions ............... 166 Linking Directives ..... Instruction Set ..... 160 Performance-Tuning Directives .. 129 Parallel Synchronization and Communication Instructions ............1.........2.............................. 8..................7.......................7..................6...............1........... Instructions ....................... Special Registers .. 170 New Features ............6.................... 10..............4.......... 63 Floating-Point Instructions ................... 8.................................................................... 8........1................................................................................ 8........2............................................................................................................... 8............. 10................................................................. Changes in Version 2.. 8........ 169 11.........................4......... 8...............................5. 140 Miscellaneous Instructions.............................................3................................. 8.... 157 10...............................................2..............................................1. 162 Debugging Directives . 55 PTX Instructions ......................7........ 62 8........................................1.............7...............3...............................1.... 7...................2................. 8....10........................................... 55 Predicated Execution .1................ 8..................................................... Type Information for Instructions and Operands ........................................ 108 Texture and Surface Instructions ............................................................................................................ 57 Manipulating Predicates ......................................... 56 Comparisons ............................................................. 147 8............................. 8.....3................................................... 11...............

... 173 iv January 24... Descriptions of ............pragma Strings...0 Appendix A.......................... 2010 ..........PTX ISA Version 2...........

........... 45 Floating-Point Rounding Modifiers .................... 46 Cost Estimates for Accessing State-Spaces ...... 70 Integer Arithmetic Instructions: sad ........................................................................................ 67 Integer Arithmetic Instructions: mad ........ 23 Constant Expression Evaluation Rules ........................... 28 Fundamental Type Specifiers ................................... Table 19............... Table 26............. 61 Integer Arithmetic Instructions: add ............ Table 22........List of Tables Table 1........... 57 Floating-Point Comparison Operators Accepting NaN ..................... 66 Integer Arithmetic Instructions: mul ... 27 Properties of State Spaces .. 18 Reserved Instruction Keywords ............................................................................................................................................ Table 13............................................................ Table 21.. 19 Predefined Identifiers ........................... 66 Integer Arithmetic Instructions: subc ................... Table 23... Table 11.............................. Table 31........................................ Unsigned Integer.............................................. Table 10................ Table 24.... 2010 v ... and Bit-Size Types .................................................................... 64 Integer Arithmetic Instructions: sub ....................... Table 9................................................. 65 Integer Arithmetic Instructions: addc ........................... 68 Integer Arithmetic Instructions: mul24 ......................... 64 Integer Arithmetic Instructions: add.. 20 Operator Precedence ... 47 Operators for Signed Integer............................................................................................................... Table 28.. Table 15.................................................................................................................................................................... 33 Opaque Type Fields in Unified Texture Mode .............................................................................. Table 18....................................................... PTX Directives ................................................... Table 29. Table 7............................................ Table 20....................... Table 5......................... 57 Floating-Point Comparison Operators ............................ Table 8...... 60 Relaxed Type-checking Rules for Destination Operands............................ Table 16..... 65 Integer Arithmetic Instructions: sub......................... 25 State Spaces ............................................... 71 January 24......................................cc ............... 58 Type Checking Rules ...................................... Table 25............. Table 30.................................................................... 35 Convert Instruction Precision and Format .................................................................. Table 3............................................................. Table 2........... Table 32... Table 6..................................................................... Table 27.......... 69 Integer Arithmetic Instructions: mad24 .................................................................. Table 12.............................................. Table 17................................. 35 Opaque Type Fields in Independent Texture Mode ................. 58 Floating-Point Comparison Operators Testing for NaN ................................... Table 14............................ 59 Relaxed Type-checking Rules for Source Operands ........................... 46 Integer Rounding Modifiers ............................................................................................................................ Table 4.cc .

.......................................... 85 Floating-Point Instructions: mul .. Table 58.......... Table 56...... 98 Floating-Point Instructions: ex2 .......... 91 Floating-Point Instructions: min ................................................................................ Table 45........................... 101 Comparison and Selection Instructions: setp .............. 94 Floating-Point Instructions: rsqrt ................................. Table 39.................................................. 74 Integer Arithmetic Instructions: bfind .................................................. 99 Comparison and Selection Instructions: set ................. Table 62.......................................................... Table 52........... Table 60............ Integer Arithmetic Instructions: div .............................................................................. 88 Floating-Point Instructions: div ............... 103 Comparison and Selection Instructions: slct ... Table 37....................... Table 51...........................................0 Table 33............. 71 Integer Arithmetic Instructions: rem ....... Table 35................................................. Table 43........................... 83 Floating-Point Instructions: copysign ...... Table 48............................................................................................................................... Table 34........................................ Table 67....................................................................................... 86 Floating-Point Instructions: fma .... Table 64............................ 72 Integer Arithmetic Instructions: neg ................ 92 Floating-Point Instructions: max ..................... 96 Floating-Point Instructions: cos ............................. 83 Floating-Point Instructions: add ... Table 65.......................................... 92 Floating-Point Instructions: rcp ................................................................................................................................................................... 103 vi January 24... Table 61........................................... 102 Comparison and Selection Instructions: selp ........................................ 73 Integer Arithmetic Instructions: popc .......PTX ISA Version 2..................................................................................................................... Table 53................... 75 Integer Arithmetic Instructions: brev ........................................................................................................ 73 Integer Arithmetic Instructions: max ...................... 74 Integer Arithmetic Instructions: clz ................................... Table 55....................... 82 Floating-Point Instructions: testp ................ Table 66....... Table 63.......................... Table 46............................ Table 40............... 78 Integer Arithmetic Instructions: prmt ............................................................................................... 2010 ............. 77 Integer Arithmetic Instructions: bfi ......................................................................... Table 69........................................ Table 47............. 97 Floating-Point Instructions: lg2 ............ Table 38..................... 79 Summary of Floating-Point Instructions ........................................................... Table 44................................... 84 Floating-Point Instructions: sub ....................................................... 76 Integer Arithmetic Instructions: bfe ............... 87 Floating-Point Instructions: mad .................... 72 Integer Arithmetic Instructions: min ............................................. Table 36....................... Table 42......................... 91 Floating-Point Instructions: neg ..................... Table 57.............. Table 50... 71 Integer Arithmetic Instructions: abs ............................................................................................................... Table 49.................... Table 41......................................................................................................... Table 59.. 95 Floating-Point Instructions: sin ..................................... Table 68............................. 90 Floating-Point Instructions: abs ............................................................. 93 Floating-Point Instructions: sqrt ........................................................................................ Table 54..........................

.. Table 91. Table 102......................... 133 Parallel Synchronization and Communication Instructions: membar ..... 113 Data Movement and Conversion Instructions: ldu .............. Table 75..................... vmin....................................................... Table 81... Table 106........................................................................................ 131 Parallel Synchronization and Communication Instructions: bar ......... 125 Texture and Surface Instructions: sust ..................................... 119 Data Movement and Conversion Instructions: cvta .... Table 98....... Table 97............................ Table 100.................................. 124 Texture and Surface Instructions: suld ................................................ 143 January 24.............. 112 Data Movement and Conversion Instructions: ld ... 105 Logic and Shift Instructions: xor .................. 123 Texture and Surface Instructions: txq ......... 135 Parallel Synchronization and Communication Instructions: red .......................... 106 Logic and Shift Instructions: cnot . 142 Video Instructions: vshl................ 128 Control Flow Instructions: { } ........................ 120 Texture and Surface Instructions: tex ............................................... 116 Data Movement and Conversion Instructions: prefetch.................. 2010 vii ........ 134 Parallel Synchronization and Communication Instructions: atom ................................... 130 Control Flow Instructions: call ... Table 95............... Table 80......... Table 73. Table 103............................................. 107 Logic and Shift Instructions: shr ................................................................ Table 85........ Table 77................................................... Table 82.... 129 Control Flow Instructions: bra ................ 115 Data Movement and Conversion Instructions: st .......................................... Table 79............ 109 Cache Operators for Memory Store Instructions ...... Table 90.................................................. Table 78...... prefetchu . Table 89........... Table 86............................................... Table 92................... 139 Video Instructions: vadd................. Table 87.......... 107 Cache Operators for Memory Load Instructions ......................................................... 110 Data Movement and Conversion Instructions: mov ............................................ Table 93....................................................................... 106 Logic and Shift Instructions: shl ......... 119 Data Movement and Conversion Instructions: cvt ................................ 130 Control Flow Instructions: ret .............. 126 Texture and Surface Instructions: sured.............. 127 Texture and Surface Instructions: suq .............. 106 Logic and Shift Instructions: not ..... 105 Logic and Shift Instructions: or ........................................... Table 96....... Logic and Shift Instructions: and ....................................... Table 94.......... Table 76.............................. 129 Control Flow Instructions: @ .................................... Table 83........... vabsdiff........................................ vmax .................................................... 131 Control Flow Instructions: exit .............................. Table 72...................................................... Table 88..................... 137 Parallel Synchronization and Communication Instructions: vote ..................... Table 104.......... 111 Data Movement and Conversion Instructions: mov ........................................................................................................................ Table 84........................................................................... Table 101............................. 118 Data Movement and Conversion Instructions: isspacep ..... Table 99................................. Table 71....................Table 70.............................. Table 74.............. vshr ...................................................................................................................................................................................... Table 105......... vsub...........

................. 161 Performance-Tuning Directives: ...................................................... 154 Special Registers: %lanemask_ge ............ Table 138....................section ......... Table 135..... 154 Special Registers: %lanemask_le ................................................... Video Instructions: vmad ......... 163 Performance-Tuning Directives: ... 151 Special Registers: %warpid .. %pm2............................................ Table 114............................................................................... 167 Linking Directives: ................ Table 124............................................... 152 Special Registers: %nctaid ................. 147 Miscellaneous Instructions: pmevent......... Table 120............................................................................................. Table 125............ Table 116. %pm3 ................minnctapersm ..................................................... Table 115..file ............................................ Table 123......... 152 Special Registers: %smid ..................................................................................... 154 Special Registers: %lanemask_lt ...........version.................. 151 Special Registers: %nwarpid ........PTX ISA Version 2.. 164 Performance-Tuning Directives: .......................................................func ....................... 2010 .................................................................... 157 PTX File Directives: ...................................................................................0 Table 107................. Table 113...................... Table 137........................................... Table 121....................... Table 126................................... 144 Video Instructions: vset................................................. 155 Special Registers: %lanemask_gt ................... 147 Special Registers: %tid .. Table 142....... Table 132........................................................................................................... Table 139............................... Table 136........................maxntid ...........................................target ......................... %pm1.............................................................................. 150 Special Registers: %ntid ........................................................ Table 133.............................................................................................. 160 Kernel and Function Directives: . Table 127....................... Table 122..... Table 108................maxnctapersm (deprecated) ................................... 153 Special Registers: %nsmid ..... Table 130.......................... Table 109.. 153 Special Registers: %lanemask_eq ....... Table 143............................. 167 Debugging Directives: . Table 140..... 163 Performance-Tuning Directives: ................................................................................. Table 141......... Table 134............. 151 Special Registers: %ctaid . 156 Special Registers: %clock64 ........................................ Table 131..... 168 viii January 24... 158 Kernel and Function Directives: ............. Table 117.................. 153 Special Registers: %gridid ...................................................... 166 Debugging Directives: ............................maxnreg ................ 165 Debugging Directives: @@DWARF .................................. 147 Miscellaneous Instructions: brkpt ..............pragma ............................................................. 156 Special Registers: %pm0............................................................................................ Table 110..................................... Table 119..... 150 Special Registers: %laneid .............................................. 155 Special Registers: %clock ................. Table 118...................................................................................entry................................. Table 129..loc ..... 146 Miscellaneous Instructions: trap ..................................... Table 112.......................... Table 128............... 156 PTX File Directives: .... Table 111........................................ 167 Debugging Directives: ........................................................... 164 Performance-Tuning Directives: ........................................extern..

.................................................. Table 145....................... 173 January 24...... 2010 ix ................visible............................ 168 Pragma Strings: “nounroll” ................. Linking Directives: ..........Table 144.....................

0 x January 24. 2010 .PTX ISA Version 2.

Chapter 1. In fact.1. and because it is executed on many data elements and has high arithmetic intensity. from general signal processing or physics simulation to computational finance or computational biology. high-definition 3D graphics. multithreaded. PTX programs are translated at install time to the target hardware instruction set. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. January 24. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions.2. which are optimized for and translated to native target-architecture instructions. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. image and media processing applications such as post-processing of rendered images. the memory access latency can be hidden with calculations instead of big data caches. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. PTX defines a virtual machine and ISA for general purpose parallel thread execution. 1. Because the same program is executed for each data element. there is a lower requirement for sophisticated flow control. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. PTX exposes the GPU as a data-parallel computing device. video encoding and decoding. 1. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. many-core processor with tremendous computational horsepower and very high memory bandwidth. stereo vision. Data-parallel processing maps data elements to parallel processing threads. and pattern recognition can map image blocks and pixels to parallel processing threads. 2010 1 . image scaling. Introduction This document describes PTX. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Similarly. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). the programmable GPU has evolved into a highly parallel.

A “flush-to-zero” (.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.0 is in improved support for the IEEE 754 floating-point standard. Provide a machine-independent ISA for C/C++ and other compilers to target.0 PTX ISA Version 2.f32. Facilitate hand-coding of libraries. and all PTX 1. • • • 2 January 24. 1. The mad. addition of generic addressing to facilitate the use of general-purpose pointers. memory. 2010 .ftz and . Instructions marked with . and architecture tests.x features are supported on the new sm_20 target. A single-precision fused multiply-add (fma) instruction has been added. The mad. Both fma.f32 requires sm_20. Achieve performance in compiled applications comparable to native GPU performance. surface. When code compiled for sm_1x is executed on sm_20 devices. The changes from PTX ISA 1.f32 maps to fma.x. Provide a common source-level ISA for optimizing code generators and translators.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.rm and .x code will continue to run on sm_1x targets as well. 1.f32 and mad.f32 for sm_20 targets. Most of the new features require a sm_20 target. sub. which map PTX to specific target machines. and video instructions. Legacy PTX 1. and mul now support . performance kernels. Single-precision add.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Improved Floating-Point Support A main area of change in PTX 2. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. reduction. including integer. The main areas of change in PTX 2. The fma.rn.ftz) modifier may be used to enforce backward compatibility with sm_1x. PTX 2.3.rp rounding modifiers for sm_20 targets.sat modifiers. mad.f32 require a rounding modifier for sm_20 targets. fma. and the introduction of many new instructions.1. barrier. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.0 is a superset of PTX 1.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. PTX ISA Version 2.3.0 are improved support for IEEE 754 floating-point operations.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 instruction also supports . Provide a code distribution ISA for application and middleware developers.PTX ISA Version 2. atomic.

PTX 2. and directives are introduced in PTX 2.zero. Instructions testp and copysign have been added. st. 2010 3 .Chapter 1. and shared addresses to generic address and vice-versa has been added.3. prefetchu. A new cvta instruction has been added to convert global. local. suld. In PTX 2.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Introduction • Single. local. and Application Binary Interface (ABI).g.2. and sust. so recursion is not yet supported. NOTE: The current version of PTX does not implement the underlying.clamp and . New Instructions The following new instructions. and red now support generic addressing. . Instruction cvta for converting global. prefetch. local.3. Support for an Application Binary Interface Rather than expose details of a particular calling convention. cvta. Cache operations have been added to instructions ld. These are indicated by the use of a rounding modifier and require sm_20. 1.3. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.0. e. stack layout. Generic addressing unifies the global.0. 1. and shared state spaces. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.and double-precision div. st. • Taken as a whole. an address that is the same across all threads in a warp. and shared addresses to generic addresses.3. rcp. Instructions prefetch and prefetchu have been added. for prefetching to specified level of memory hierarchy. atom. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. special registers.e. and vice versa. and sqrt with IEEE 754 compliant rounding have been added. January 24. allowing memory instructions to access these spaces without needing to specify the state space. instructions ld. these changes bring PTX 2. i.0 closer to full compliance with the IEEE 754 standard. Generic Addressing Another major change is the addition of generic addressing. Surface Instructions • • Instruction sust now supports formatted surface stores. stack-based ABI.4. 1.. isspacep. ldu. Surface instructions support additional clamp modifiers.

ballot. and Vote Instructions • • • New atomic and reduction instructions {atom. Barrier Instructions • • A system-level membar instruction. vote.red.red. A new directive.or}.shared have been extended to handle 64-bit data types for sm_20 targets.arrive instruction has been added. Reduction. A “vote ballot” instruction.gt} have been added. A bar.add. New special registers %nsmid.f32 have been added.b32.lt.ge. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.red}.{and. Instructions bar. has been added. bfi bit field extract and insert popc clz Atomic.PTX ISA Version 2.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. Other Extensions • • • Video instructions (includes prmt) have been added.red}.sys. 4 January 24.section.popc. Instructions {atom. . 2010 .le. has been added.u32 and bar. bar now supports an optional thread count and register operands.pred have been added. membar. %clock64. %lanemask_{eq.

Chapter 8 describes the instruction set.Chapter 1. Chapter 5 describes state spaces. Chapter 9 lists special registers. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.0. Introduction 1. January 24. Chapter 7 describes the function and call syntax. Chapter 11 provides release notes for PTX Version 2. and PTX support for abstracting the Application Binary Interface (ABI). types. Chapter 10 lists the assembly directives supported in PTX.4. Chapter 4 describes the basic syntax of the PTX language. Chapter 3 gives an overview of the PTX virtual machine model. calling convention. 2010 5 . Chapter 6 describes instruction operands. and variable declarations.

2010 .PTX ISA Version 2.0 6 January 24.

and select work to perform. and results across the threads of the CTA. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.x.2. and ntid. 2. Threads within a CTA can communicate with each other.2. can be isolated into a kernel function that is executed on the GPU as many different threads. but independently on different data. or CTA. January 24. Programming Model 2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. compute-intensive portions of applications running on the host are off-loaded onto the device. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. (with elements tid. To coordinate the communication of the threads within the CTA. or 3D CTA. 2010 7 . and tid. ntid.z). or 3D shape specified by a three-element vector ntid (with elements ntid. one can specify synchronization points where threads wait until all threads in the CTA have arrived.x. The thread identifier is a three-element vector tid.1. To that effect. assign specific input and output positions. Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2D. Programs use a data parallel decomposition to partition inputs.Chapter 2.1. a portion of an application that is executed many times.y. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.z) that specifies the thread’s position within a 1D. More precisely.y. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. The vector ntid specifies the number of threads in each CTA dimension. Each CTA thread uses its thread identifier to determine its assigned role. or host: In other words. A cooperative thread array. data-parallel. work. compute addresses. 2D. It operates as a coprocessor to the main CPU. tid. Each CTA has a 1D. is an array of threads that execute a kernel concurrently or in parallel. 2. Each thread has a unique thread identifier within the CTA.

The warp size is a machine-dependent constant. 2. which may be used in any instruction where an immediate operand is allowed. and %gridid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. depending on the platform. Threads within a warp are sequentially numbered. or sequentially. 2010 . %ntid. because threads in different CTAs cannot communicate and synchronize with each other. so PTX includes a run-time immediate constant. The host issues a succession of kernel invocations to the device.0 Threads within a CTA execute in SIMT (single-instruction. Multiple CTAs may execute concurrently and in parallel. %nctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs.PTX ISA Version 2. Typically. Each grid also has a unique temporal grid identifier (gridid). or 3D shape specified by the parameter nctaid. %ctaid. 2D .2. Threads may read and use these values through predefined. read-only special registers %tid. A warp is a maximal subset of threads from a single CTA. Each grid of CTAs has a 1D. However. This comes at the expense of reduced thread communication and synchronization. CTAs that execute the same kernel can be batched together into a grid of CTAs. such that the threads execute the same instructions at the same time.2. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). 8 January 24. a warp has 32 threads. WARP_SZ. Some applications may be able to maximize performance with knowledge of the warp size. multiple-thread) fashion in groups called warps. so that the total number of threads that can be launched in a single kernel invocation is very large.

2) Thread (2. Figure 1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) CTA (2. 1) Thread (4.Chapter 2. 1) CTA (1. 0) Thread (0. 0) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (2. 2) Thread (3. 2) Thread (1. 1) Thread (1. 1) Thread (2. Thread Batching January 24. 0) CTA (1. 1) Thread (3. 0) CTA (0. A grid is a set of CTAs that execute independently. 2010 9 . 0) Thread (4. 1) CTA (2. 1) Thread (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (4. 0) Thread (1. 1) Thread (0.

constant.3. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Each thread has a private local memory. for more efficient transfer. respectively. Texture memory also offers different addressing modes. Both the host and the device maintain their own local memory. and texture memory spaces are persistent across kernel launches by the same application. as well as data filtering. and texture memory spaces are optimized for different memory usages. or. constant. referred to as host memory and device memory. The device memory may be mapped and read or written by the host. all threads have access to the same global memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Finally. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. The global. 10 January 24.PTX ISA Version 2.0 2. The global. 2010 . Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. for some specific data formats.

1) Block (2. 0) Block (1. 0) Block (2. 2010 11 .Chapter 2. Memory Hierarchy January 24. 1) Block (1. 1) Grid 1 Global memory Block (0. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (0. 2) Block (1. 0) Block (1. 0) Block (0. 2) Figure 2. 1) Block (1.

2010 .0 12 January 24.PTX ISA Version 2.

January 24. and on-chip shared memory. different warps execute independently regardless of whether they are executing common or disjointed code paths. each warp contains threads of consecutive. When a multiprocessor is given one or more thread blocks to execute.1. and each scalar thread executes independently with its own instruction address and register state. manages. schedules. increasing thread IDs with the first warp containing thread 0. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). As thread blocks terminate. A multiprocessor consists of multiple Scalar Processor (SP) cores. manages. a cell in a grid-based computation).Chapter 3. (This term originates from weaving. a voxel in a volume. Branch divergence occurs only within a warp. the warp serially executes each branch path taken. the multiprocessor employs a new architecture we call SIMT (single-instruction. new blocks are launched on the vacated multiprocessors. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. The multiprocessor SIMT unit creates. To manage hundreds of threads running several different programs. and when all paths complete. for example. multiple-thread). the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. The threads of a thread block execute concurrently on one multiprocessor. a multithreaded instruction unit. At every instruction issue time. 2010 13 . so full efficiency is realized when all threads of a warp agree on their execution path. A warp executes one common instruction at a time. disabling threads that are not on that path.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. Parallel Thread Execution Machine Model 3. It implements a single-instruction barrier synchronization. If threads of a warp diverge via a data-dependent conditional branch. and executes concurrent threads in hardware with zero scheduling overhead. the threads converge back to the same execution path. the first parallel thread technology. The multiprocessor creates. The way a block is split into warps is always the same. allowing. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. When a host program invokes a kernel grid. The multiprocessor maps each thread to one scalar processor core. and executes threads in groups of parallel threads called warps. it splits them into warps that get scheduled by the SIMT unit. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism.

require the software to coalesce loads into vectors and manage divergence manually. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. 14 January 24. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides.0 SIMT architecture is akin to SIMD (Single Instruction. modify. scalar threads. A multiprocessor can execute as many as eight thread blocks concurrently. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. Vector architectures. • The local and global memory spaces are read-write regions of device memory and are not cached. on the other hand. the kernel will fail to launch. which is a read-only region of device memory. write to that location occurs and they are all serialized. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. but the order in which they occur is undefined. If there are not enough registers or shared memory available per multiprocessor to process at least one block. whereas SIMT instructions specify the execution and branching behavior of a single thread. and writes to the same location in global memory for more than one of the threads of the warp. SIMT enables programmers to write thread-level parallel code for independent.PTX ISA Version 2. which is a read-only region of device memory. For the purposes of correctness. 2010 . In practice. A key difference is that SIMD vector organizations expose the SIMD width to the software. each read. As illustrated by Figure 3. If an atomic instruction executed by a warp reads. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. modifies. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. but one of the writes is guaranteed to succeed. In contrast with SIMD vector machines. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. the programmer can essentially ignore the SIMT behavior. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. however. the number of serialized writes that occur to that location and the order in which they occur is undefined. as well as data-parallel code for coordinated threads.

2010 15 . Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3. Hardware Model January 24. Figure 3.

0 16 January 24.PTX ISA Version 2. 2010 .

Source Format Source files are ASCII text. #else. and using // to begin a comment that extends to the end of the current line. Syntax PTX programs are a collection of text source files. Lines are separated by the newline character (‘\n’). 4. Comments Comments in PTX follow C/C++ syntax. whitespace is ignored except for its use in separating tokens in the language. Comments in PTX are treated as whitespace. using non-nested /* and */ for comments that may span multiple lines. #endif. 2010 17 . 4. PTX is case sensitive and uses lowercase for keywords. #define. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #line. The following are common preprocessor directives: #include. followed by a . Lines beginning with # are preprocessor directives. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #if.1. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. All whitespace characters are equivalent. The C preprocessor cpp may be used to process PTX source files.version directive specifying the PTX language version.target directive specifying the target architecture assumed. Pseudo-operations specify symbol and addressing management.2. Each PTX file must begin with a .Chapter 4. January 24. #ifdef. See Section 9 for a more information on these directives.

All instruction keywords are reserved tokens in PTX.reg .f32 array[N]. Statements A PTX statement is either a directive or an instruction. 2010 . 2.func . Directive Statements Directive keywords begin with a dot. array[r1]. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. or label names. The destination operand is first.target .reg . and is written as @p.1.b32 r1.0 4.global .global.section . The guard predicate may be optionally negated. r1.maxnctapersm .shared .maxntid . followed by source operands. Operands may be register variables. r2.param .3.3. .3. constant expressions. Table 1.pragma . ld.entry . mov.x.5. 0.PTX ISA Version 2. r2.align . Examples: . %tid. Instructions have an optional guard predicate which controls conditional execution.sreg . written as @!p.minnctapersm .extern .version .global start: . so no conflict is possible with user-defined identifiers. and terminated with a semicolon. Statements begin with an optional label and end with a semicolon.file PTX Directives .local . address expressions.f32 r2. . The guard predicate follows the optional label and precedes the opcode. r2.loc . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.visible 4.b32 r1. Instruction keywords are listed in Table 2.const .maxnreg .2. 18 January 24. shl.b32 add. where p is a predicate register.tex . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.b32 r1.

Syntax Table 2.Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

e.g.4. or dollar characters. underscore. PTX allows the percentage sign as the first character of an identifier.PTX ISA Version 2. digits. or percentage character followed by one or more letters. listed in Table 3. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.0 4. %pm3 WARP_SZ 20 January 24. Many high-level languages such as C and C++ follow similar rules for identifier names. dollar. between user-defined variable names and compiler-generated names. or they start with an underscore. …. PTX predefines one constant and a small number of special registers that begin with the percentage sign. digits. underscore. Table 3. 2010 . except that the percentage sign is not allowed. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. The percentage sign can be used to avoid name conflicts. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.

5. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. integer constants are allowed and are interpreted as in C. or binary notation.5. octal. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. For predicate-type data and instructions. in which case the literal is unsigned (.. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. every integer constant has type . Floating-point literals may be written with an optional decimal point and an optional signed exponent. and bit-size types. floating-point. Constants PTX supports integer and floating-point constants and constant expressions. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. The syntax follows that of C. the sm_1x and sm_20 targets have a WARP_SZ value of 32.2. 0[fF]{hexdigit}{8} // single-precision floating point January 24. i. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. 4..u64.e. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. 2010 21 . and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. Syntax 4. hexadecimal. Integer literals may be written in decimal. the constant begins with 0d or 0D followed by 16 hex digits. These constants may be used in data initialization and as operands to instructions. where the behavior of the operation depends on the operand types.1.Chapter 4. the constant begins with 0f or 0F followed by 8 hex digits. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.5. literals are always represented in 64-bit double-precision format. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. When used in an instruction or data initialization.s64 or the unsigned suffix is specified. each integer constant is converted to the appropriate size based on the data or instruction type at its use. zero values are FALSE and non-zero values are TRUE. 4.s64) unless the value cannot be fully represented in .s64 or . To specify IEEE 754 single-precision floating point values. Unlike C and C++. To specify IEEE 754 doubleprecision floating point values. there is no suffix letter to specify size. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. i.e.u64). Type checking rules remain the same for integer.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

u64.u64 .f64 use usual conversions .u64 same as 1st operand .Chapter 4.u64 .s64 .f64 use usual conversions . .f64 integer integer integer integer integer int ?.u64 .s64 .s64 .s64. 2010 25 . Syntax 4.s64 .u64 .s64 .u64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table. 2nd is .f64 converted type .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .f64 integer .f64 use usual conversions .f64 : .6.u64 1st unchanged.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64) + .f64 converted type constant literal + ! ~ Cast Binary (. or .f64 same as source .s64 .u64) (.5. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 . Table 5.f64 integer .

0 26 January 24. 2010 .PTX ISA Version 2.

or Function or local parameters. State Spaces A state space is a storage area with particular characteristics. Name State Spaces Description Registers. Addressable memory shared between threads in 1 CTA. Shared. Global memory.const . Local memory. 2010 27 . and level of sharing between threads.reg . Types. The characteristics of a state space include its size. The list of state spaces is shown in Table 4. State Spaces. Kernel parameters. shared by all threads. access speed. fast.global . and these resources are abstracted in PTX through state spaces and data types. Global texture memory (deprecated).local .shared . and properties of state spaces are shown in Table 5.sreg . pre-defined. the kinds of resources will be common across platforms. Table 6.param . read-only memory. Special registers.Chapter 5. 5. Read-only.tex January 24.1. All variables reside in some state space. platform-specific. . defined per-thread. access rights. and Variables While the specific resources available in a given target GPU will vary. defined per-grid. addressability. private to each thread. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.

register variables will be spilled to memory. and thread parameters. it is not possible to refer to the address of a register. 5. 64-.1.2.param instruction. or 128-bits. and cvt instructions. platform-specific registers.param instructions.shared . The most common use of 8-bit registers is with ld. The number of registers is limited. Registers differ from the other state spaces in that they are not fully addressable.. and performance monitoring registers.param and st.local . or 64-bits. 2010 . Registers may have alignment boundaries required by multi-word loads and stores.reg state space) are fast storage locations.local state space. All special registers are predefined.reg .param (used in functions) . the parameter is then located on the stack frame and its address is in the . Address may be taken via mov instruction. 16-.e. or as elements of vector tuples.const . Special Register State Space The special register (. 3 Accessible only via the tex instruction. i. CTA. 2 Accessible via ld. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Registers may be typed (signed integer. and will vary from platform to platform. and vector registers have a width of 16-. Device function input parameters may have their address taken via mov. 32-. scalar registers have a width of 8-. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. 28 January 24.tex Restricted Yes No3 5. clock counters. Register size is restricted. st.sreg) state space holds predefined.PTX ISA Version 2.sreg . such as grid. aside from predicate registers which are 1-bit. causing changes in performance.0 Table 7. Register State Space Registers (. predicate) or untyped. unsigned integer. For each architecture.param (as input to kernel) . 1 Accessible only via the ld. When the limit is exceeded.1. floating point. 32-.global .1. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).

All memory writes prior to the bar. Consider the case where one thread executes the following two assignments: a = a + 1. For example. b = b – 1. Types. The constant memory is organized into fixed size banks.sync instruction.global. [const_buffer+4]. the declaration . an incomplete array in bank 2 is accessed as follows: . It is the mechanism by which different CTAs and different grids can communicate.4.1. bank zero is used for all statically-sized constant variables. For example. State Spaces. the store operation updating a may still be in flight. where the size is not known at compile time. Constant State Space The constant (.const[bank] modifier. For any thread in a context. For the current devices. all addresses are in global memory are shared. as in lock-free and wait-free style programming.b32 const_buffer[]. In implementations that support a stack. To access data in contant banks 1 through 10.sync instruction are guaranteed to be visible to any reads after the barrier instruction. bank zero is used. The remaining banks may be used to implement “incomplete” constant arrays (in C. Use ld.local and st. whereas local memory variables declared January 24. Use ld. the bank number must be provided in the state space of the load instruction. the stack is in local memory. The size is limited.b32 const_buffer[].local) is private memory for each thread to keep its own data. Sequential consistency is provided by the bar.1. for example). // load second word 5.global to access global variables. 2010 29 . Threads must be able to do their work without waiting for other threads to do theirs. By convention. It is typically standard memory with cache. each pointing to the start address of the specified constant bank. Module-scoped local memory variables are stored at fixed addresses. initialized by the host. If no bank number is given.const) state space is a read-only memory.b32 %r1. Global State Space The global (.global) state space is memory that is accessible by all threads in a context. Local State Space The local state space (. Banks are specified using the . and atom.3. Threads wait at the barrier until all threads in the CTA have arrived.local to access local variables. ld. This pointer can then be used to access the entire 64KB constant bank.global.extern . This reiterates the kind of parallelism available in machines that run PTX.const[2] . Multiple incomplete array variables declared in the same bank become aliases. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.1.Chapter 5.const[2]. results in const_buffer pointing to the start of constant bank two. If another thread sees the variable b change. Global memory is not sequentially consistent. st. 5. as it must be allocated on a perthread basis.extern . there are eleven 64KB banks.const[2] . where bank ranges from 0 to 10. and Variables 5.5.

For example.x supports only kernel function parameters in .0 within a function or kernel body are allocated on the stack.1. These parameters are addressable.1.f64 %d. %n.param.entry bar ( .u32 %n.param . Therefore.6. The resulting address is in the . device function parameters were previously restricted to the register state space. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param space variables.u32 %ptr. Note: The location of parameter space is implementation specific.param. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.u32 %ptr. Parameter State Space The parameter (.0 and requires target architecture sm_20. in some implementations kernel parameters reside in global memory.param space. .param) state space is used (1) to pass input arguments from the host to the kernel. read-only variables declared in the .param state space. Similarly.reg . The use of parameter state space for device function parameters is new to PTX ISA version 2. [buffer]. 5. In implementations that do not support a stack.param state space and is accessed using ld. [N]. The address of a kernel parameter may be moved into a register using the mov instruction. 5. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).param . Values passed from the host to the kernel are accessed through these parameter variables using ld.b32 len ) { .reg .f64 %d.param. Example: .1.entry foo ( . per-kernel versus per-thread). … Example: .param instructions. No access protection is provided between parameter and global space in this case.b32 N. ld. The kernel parameter variables are shared across all CTAs within a grid. len. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. typically for passing large structures by value to a function. [%ptr].u32 %n.param . . PTX code should make no assumptions about the relative locations or ordering of .b8 buffer[64] ) { . mov.6. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.align 8 .u32 %n. ld.param instructions.reg .PTX ISA Version 2. ld. … 30 January 24. 2010 . Note that PTX ISA versions 1. all local memory variables are stored at fixed addresses and recursive function calls are not supported.

It is not possible to use mov to get the address of a return parameter or a locally-scoped . Device Function Parameters PTX ISA version 2.Chapter 5.s32 x.reg .reg .param. ld. January 24. .param.param .reg . int y. [buffer]. The most common use is for passing objects by value that do not fit within a PTX register.local state space and is accessed via ld. .f64 %d. such as C structures larger than 8 bytes. is flattened.param and function return parameters may be written using st.reg .b32 N. x. } mystruct. and so the address will be in the . Aside from passing structures by value. the caller will declare a locally-scoped .param space variable. the address of a function input parameter may be moved into a register using the mov instruction.param.b8 mystruct. call foo. … See the section on function call syntax for more details. [buffer+8]. Function input parameters may be read via ld. 2010 31 .param .align 8 . dbl.0 extends the use of parameter space to device function parameters.s32 %y.func foo ( . mystruct). and Variables 5. In PTX. In this case. passed to foo … . (4. Example: // pass object of type struct { double d.s32 [mystruct+8]. This will be passed by value to a callee.align 8 . Types.param. .param formal parameter having the same size and alignment as the passed argument. . which declares a .s32 %y. Typically.local instructions.f64 [mystruct+0].1. it is illegal to write to an input parameter or read from a return parameter.f64 dbl. . a byte array in parameter space is used. ld.6.b8 buffer[12] ) { . }. State Spaces. Note that the parameter will be copied to the stack if necessary.f64 %d.param. .2.param byte array variable that represents a flattened C structure or union. int y.local and st. st.reg . … } // code snippet from the caller // struct { double d. … st.param space is also required whenever a formal parameter has its address taken within the called function.

tex_f.tex .tex . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).global . where texture identifiers are allocated sequentially beginning with zero.global state space. An address in shared memory can be read and written by any thread in a CTA. 2010 . The . Shared State Space The shared (.u32 . tex_d.shared) state space is a per-CTA region of memory for threads in a CTA to share data. tex_d.texref type and Section 8. Shared memory typically has some optimizations to support the sharing.tex) state space is global memory accessed via the texture instruction. Texture memory is read-only. Use ld.tex . One example is broadcast. Physical texture resources are allocated on a per-module granularity.7.8. The texture name must be of type . and .texref variables in the . 32 January 24. It is shared by all threads in a context.u32 tex_a.1.u64. A texture’s base address is assumed to be aligned to a 16-byte boundary. Example: .tex variables are required to be defined in the global scope. tex_c. and programs should instead reference texture memory through variables of type .7. where all threads read from the same address.u32 . For example. Another is sequential access from sequential threads. Texture State Space (deprecated) The texture (.tex directive will bind the named texture memory variable to a hardware texture identifier.u32 .u32 tex_a.tex .1. is equivalent to . a legacy PTX definitions such as .texref tex_a.shared to access shared variables. An error is generated if the maximum number of physical resources is exceeded.u32 or . The .tex directive is retained for backward compatibility.tex . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.texref.3 for the description of the . See Section 5.tex state space are equivalent to module-scoped . Multiple names may be bound to the same physical texture identifier. and variables declared in the .PTX ISA Version 2.shared and st. 5.6 for its use in texture instructions.0 5.

. State Spaces.s64 . For convenience.s32. so that narrow values may be loaded. . Types 5. . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . The same typesize specifiers are used for both variable definitions and for typing instructions. the fundamental types reflect the native data types supported by the target architectures. 2010 33 . Restricted Use of Sub-Word Sizes The . . st. st. Fundamental Types In PTX.2. Types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.f32 and . 5.b8 instruction types are restricted to ld.s8.f16 floating-point type is allowed only in conversions to and from . The . . stored. stored. needed to fully specify instruction behavior.u16.b16. All floating-point instructions operate only on .2.f64 types.u32.f64 .b64 . .Chapter 5.f16. Operand types and sizes are checked against instruction types for compatibility. all variables (aside from predicates) could be declared using only bit-size types. ld. . but typed variables enhance program readability and allow for better operand type checking.2. Signed and unsigned integer types are compatible if they have the same size. In principle. January 24. . and .f32 and . The following table lists the fundamental type specifiers for each basic type: Table 8. and cvt instructions. For example. Register variables are always of a fundamental type. . and Variables 5. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. or converted to other types and sizes. Two fundamental types are compatible if they have the same basic type and are the same size.u64 . The bitsize type is compatible with any fundamental type having the same size.b32.f32. A fundamental type specifies both a basic type and a size. so their names are intentionally short. .s16.b8.s8.f64 types.u8.u8.1. and instructions operate on these types.2. .pred Most instructions have one or more type specifiers. . and converted using regular-width registers.

but all information about layout. and overall size is hidden to a PTX program.texref type that describe sampler properties are ignored. 2010 . 34 January 24. the resulting pointer may be stored to and loaded from memory. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. The three built-in types are .{u32. Creating pointers to opaque variables using mov. and de-referenced by texture and surface load. field ordering. and Surface Types PTX includes built-in “opaque” types for defining texture.. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. i. store.e. Texture.u64} reg. Sampler. . In independent mode the fields of the . These types have named fields similar to structures.3. or performing pointer arithmetic will result in undefined results. base address.texref. In the unified mode. PTX has two modes of operation. accessing the pointer with ld and st instructions. allowing them to be defined separately and combined at the site of usage in the program. and surface descriptor variables. and query instructions. Retrieving the value of a named member via query instructions (txq. texture and sampler information is accessed through a single .samplerref. since these properties are defined by . suld. The following tables list the named members of each type for unified and independent texture modes.0 5.texref handle. opaque_var. hence the term “opaque”. For working with textures and samplers. sust.PTX ISA Version 2. sured). suq). texture and sampler information each have their own handle. In the independent mode.surfref. and . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. sampler. or surfaces via texture and surface load/store instructions (tex.samplerref variables. samplers. passed as a parameter to functions. Referencing textures. but the pointer cannot otherwise be treated as an address.

samplerref values N/A N/A N/A N/A nearest. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_ogl. clamp_to_border 0. and Variables Table 9. linear wrap.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. Types.texref values in elements in elements in elements 0.texref values . clamp_to_edge. clamp_to_edge. mirror. State Spaces. linear wrap. 1 nearest. clamp_to_border N/A N/A N/A N/A N/A . mirror. Member width height depth Opaque Type Fields in Independent Texture Mode . clamp_ogl.Chapter 5. 2010 35 . 1 ignored ignored ignored ignored .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.

param state space. . Example: .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. Example: . these variables are declared in the .PTX ISA Version 2.texref tex1.global .global . At module scope. the types may be initialized using a list of static expressions assigning values to the named members. 2010 .global state space. filter_mode = nearest }. .samplerref my_sampler_name. When declared at module scope.global .surfref my_surface_name. As kernel parameters. 36 January 24.texref my_texture_name. .global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global . these variables must be in the .

Three-element vectors may be handled by using a . . Every variable must reside in one of the state spaces enumerated in the previous section. .global .0}. Vectors must be based on a fundamental type.0.u16 uv. .reg .u32 loc. 0. Vectors Limited-length vector types are supported.pred p. textures. 0}. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . 0. Variable Declarations All storage for data is specified with variable declarations. and an optional fixed address for the variable. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v1.v2. an optional array size. .4. State Spaces.global . 5. Examples: . q.reg .v4 .struct float4 coord.b8 v. and Variables 5.global . .struct float4 { . This is a common case for three-dimensional grids. January 24. Vectors cannot exceed 128-bits in length. Examples: . for example.shared .Chapter 5.const . A variable declaration names the space in which the variable resides. r. an optional initializer. .global . its name.2.global .v3 }.1. a variable declaration describes both the variable’s type and its state space. .v2 or .f64 is not allowed. etc. // a length-4 vector of bytes By default.reg .u8 bg[4] = {0.4. where the fourth element provides padding. // a length-2 vector of unsigned ints . Types.v4 . and they may reside in the register space.f32 bias[] = {-1.4. Predicate variables may only be declared in the register state space.f32 accel.v4 . PTX supports types for simple aggregate objects such as vectors and arrays. 1.f32 v0.v2 . its type and size. 5.v4 vector. // typedef .v4. 2010 37 .v4. Variables In PTX. In addition to fundamental types.s32 i. vector variables are aligned to a multiple of their overall size (vector length times base-type size). // a length-4 vector of floats .f32 V.

0}.0 5.s32 n = 10. being determined by an array initializer.4. . Initializers Declared variables may specify an initial value using a syntax similar to C/C++.u16 kernel[19][19]. 1} }. Variables that hold addresses of variables or instructions should be of type .f16 and . To declare an array.global .{.local .0}}. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. The size of the dimension is either a constant expression.05}. The size of the array specifies how many elements should be reserved. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). 2010 .global . 5.{. 0}.0..global .. Variable names appearing in initializers represent the address of the variable.4.1}. this can be used to statically initialize a pointer to a variable.b32 ptr = rgba.s32 offset[][] = { {-1.0}.0. // address of rgba into ptr Currently.v4 . Examples: . this can be used to initialize a jump table to be used with indirect branches or calls. Here are some examples: .PTX ISA Version 2.05}}.u8 rgba[3] = {{1.. -1}.u8 mailbox[128].u32 or .. For the kernel declaration above. {0. A scalar takes a single value..3. {1.global . or is left empty.05. 19*19 (361) halfwords are reserved (722 bytes).4. variable initialization is supported only for constant and global state spaces. . {0. Similarly. {0.1.1. 38 January 24. {0.1.05.pred. Initializers are allowed for all types except . .1.4.0.. 0}.global . Array Declarations Array declarations are provided to allow the programmer to reserve space. . .0.f32 blur_kernel[][] = {{.u64. where the variable name is followed by an equals sign and the initial value or values for the variable. label names appearing in initializers represent the address of the next instruction following the label.1.shared .

4. For arrays. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. Examples: // allocate array at 4-byte aligned address. ….reg . Array variables cannot be declared this way.. January 24.5. Alignment is specified using an optional . %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. suppose a program uses a large number. These 100 register variables can be declared as follows: . // declare %r0. .2. %r99. The default alignment for scalar and array variables is to a multiple of the base-type size. 2010 39 . %r1. Types. say one hundred. . The default alignment for vector variables is to a multiple of the overall vector size.0.0}.0. and Variables 5. The variable will be aligned to an address which is an integer multiple of byte-count. alignment specifies the address alignment for the starting address of the entire array.const . PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.4. %r1.b32 variables. Rather than require explicit declaration of every name. not for individual elements. 5. and may be preceded by an alignment specifier.Chapter 5. Elements are bytes. of .6.0.align byte-count specifier immediately following the state-space specifier. For example.. Parameterized Variable Names Since PTX supports virtual registers. State Spaces.0. nor are initializers permitted.b32 %r<100>.b8 bar[8] = {0. it is quite common for a compiler frontend to generate a large number of register names..align 4 . named %r0.

2010 .PTX ISA Version 2.0 40 January 24.

Instructions ld and st move data from/to addressable state spaces to/from registers. 2010 41 . Predicate operands are denoted by the names p. For most operations. and cvt instructions copy data from one location to another. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Integer types of a common size are compatible with each other. the sizes of the operands must be consistent.3. so operands for ALU instructions must all be in variables declared in the . Instruction Operands 6. s. . Operand Type Information All operands in instructions have a known type from their declarations. r.Chapter 6. mov. and a few instructions have additional predicate source operands. 6. There is no automatic conversion between types.reg register state space. as its job is to convert from nearly any data type to any other data type (and size). The mov instruction copies data between registers. The ld. The result operand is a scalar or vector variable in the register state space. Each operand type must be compatible with the type determined by the instruction template and instruction type. PTX describes a load-store machine. The bit-size type is compatible with every type having the same size.1. b. Most instructions have an optional predicate guard that controls conditional execution. Source Operands The source operands are denoted in the instruction descriptions by the names a. January 24. st. Operands having type different from but compatible with the instruction type are silently cast to the instruction type.2. 6. and c. The cvt (convert) instruction takes a variety of operand types and sizes. q.

All addresses and address computations are byte-based. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. The interesting capabilities begin with addresses. Here are a few examples: .v4 .f32 V.global .f32 ld. Examples include pointer arithmetic and pointer comparisons.f32 W. .b32 p. 2010 . and immediate address expressions which evaluate at compile-time to a constant address.u16 r0. ld. [V]. r0.s32 mov. .reg . The mov instruction can be used to move the address of a variable into a pointer. there is no support for C-style pointer arithmetic.4. Using Addresses.reg .s32 tbl[256].shared .const. Arrays. . The address is an offset in the state space in which the variable is declared. address register plus byte offset. p. Address expressions include variable names. and Vectors Using scalar variables as operands is straightforward. 6.0 6.s32 q. q. [tbl+12].[x].v4 . .gloal. arrays.u32 42 January 24. address registers. The syntax is similar to that used in many assembly languages. tbl. .4. and vectors.v4.1.PTX ISA Version 2. Load and store operations move data between registers and locations in addressable state spaces. W.reg .const .u16 ld.reg . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. .shared.u16 x.

y V.z and .4. January 24.f32 ld. a[N-1].b.w = = = = V. Here are examples: ld. Array elements can be accessed using an explicitly calculated byte address. and tex. Rb. where the offset is a constant expression that is either added or subtracted from a register variable.d}. c.reg . ld. .3. [addr+offset2].g V. or by indexing into the array using square-bracket notation. [addr+offset]. mov.global.b and . mov. Vectors may also be passed as arguments to called functions. 2010 43 . st. If more complicated indexing is desired. A brace-enclosed list is used for pattern matching to pull apart vectors.x.b. for use in an indirect branch or call.f32 a.4. a[0].global.x V.y. which include mov. V.v4. say {Ra. a register variable.z V. The expression within square brackets is either a constant integer.v4 .2. // move address of a[1] into s 6. Elements in a brace-enclosed vector. and in move instructions to get the address of the label or function into a register. V2.reg .u32 s. . The registers in the load/store operations can be a vector. Arrays as Operands Arrays of all types can be declared. Examples are ld. b.c.f32 V.u32 {a. Vector loads and stores can be used to implement wide loads and stores. ld.4.v2.u32 s.a.global.4. .global.b V. it must be written as an address calculation prior to use. Rd}. and the identifier becomes an address constant in the space where the array is declared.d}.w. or a braceenclosed list of similarly typed scalars. . which may improve memory performance. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.u32 s.f32 {a. d. as well as the typical color fields . or a simple “register with constant offset” expression.Chapter 6.v4. The size of the array is a constant in the program.g. . Instruction Operands 6.a 6.r.c.r V. Vectors as Operands Vector operands are supported by a limited subset of instructions. a[1]. Rc. . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. Vector elements can be extracted from the vector with the suffixes .

Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. For example. and ~131. Operands of different sizes or types must be converted prior to the operation. 6. 2010 .0 6.PTX ISA Version 2. the u16 is zero-extended to s32.000 for f16).5. and data movement instruction must be of the same type and size. except for operations where changing the size and/or type is part of the definition of the instruction.1. logic. if a cvt. 44 January 24.5.s32.u16 instruction is given a u16 source operand and s32 as a destination operand. Type Conversion All operands to all arithmetic. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.

zext = zero-extend. cvt.u32 targeting a 32-bit register will first chop to 16-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2s = float-to-signed. f2f = float-to-float. 2010 45 .s16. u2f = unsigned-to-float. For example. Notes 1 If the destination register is wider than the destination format. the result is extended to the destination register width after chopping. January 24. then sign-extend to 32-bits. Instruction Operands Table 11.Chapter 6. s2f = signed-to-float. f2u = float-to-unsigned. The type of extension (sign or zero) is based on the destination format. chop = keep only low bits that fit.

Modifier . choosing even integer if source is equidistant between two integers. Modifier .rmi .rpi Integer Rounding Modifiers Description round to nearest integer.rm .2. there are four integer rounding modifiers and four floating-point rounding modifiers.0 6.rz . Table 12.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.5. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. In PTX.rn . 2010 .rni .rzi .PTX ISA Version 2. Rounding Modifiers Conversion instructions may specify a rounding modifier. The following tables summarize the rounding modifiers.

Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. while global memory is slowest. Another way to hide latency is to issue the load instructions as early as possible. The register in a store operation is available much more quickly. as execution is not blocked until the desired result is used in a subsequent (in time) instruction.6. Table 14. Registers are fastest. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Operand Costs Operands from different state spaces affect the speed of an operation. Table 11 gives estimates of the costs of using different kinds of memory. first access is high Notes January 24. Instruction Operands 6.Chapter 6. 2010 47 . Much of the delay to memory can be hidden in a number of ways.

0 48 January 24. 2010 .PTX ISA Version 2.

… Here. and memory allocated on the stack (“alloca”). implicitly saving the return address. and an optional list of input parameters. A function must be declared or defined prior to being called. 2010 49 . or prototype.func foo { … ret. and return values may be placed directly into register variables. A function definition specifies both the interface and the body of the function. so recursion is not yet supported. Function declarations and definitions In PTX. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and Application Binary Interface (ABI). stack-based ABI. January 24. arguments may be register variables or constants. function calls. A function declaration specifies an optional list of return parameters. Execution of the ret instruction within foo transfers control to the instruction following the call.func directive. support for variadic functions (“varargs”). NOTE: The current version of PTX does not implement the underlying. The simplest function has no parameters or return values. we describe the features of PTX needed to achieve this hiding of the ABI. Scalar and vector base-type input and return parameters may be represented simply as register variables. stack layout. In this section. These include syntax for function definitions. functions are declared and defined using the . execution of the call instruction transfers control to foo. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. the function name. } … call foo. together these specify the function’s interface. parameter passing. 7. and is represented in PTX as follows: .Chapter 7.1. At the call. Abstracting the ABI Rather than expose details of a particular calling convention.

b8 . ld.u32 %res. }.param space variables are used in two ways. … In this example. st. st.param. this structure will be flattened into a byte array.c1.c3. byte array in .f64 field are aligned. … st. 50 January 24. %rc1. py). consider the following C structure.param space call (%out). … ld.b8 c4. Since memory accesses are required to be aligned to a multiple of the access size.b8 [py+11].b8 c1. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . inc_ptr. passed by value to a function: struct { double dbl. %inc. 2010 .param.b8 c2. } … call (%r1). [y+10].align 8 y[12]) { . st.func (.f1.reg .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. (%r1. %rc2. // scalar args in . The .param. a . [y+9].b8 [py+10].param.align 8 py[12]. %rc1.b64 [py+ 0].param variable y is used in function definition bar to represent a formal parameter.param. st. ret.param.param space memory. .param . In PTX. [y+11].reg space.param.reg . . Second. bumpptr. . First.param.b8 c3. a .param.param state space is used to pass the structure by value: . … … // computation using x. (%x.b8 .b8 [py+ 8]. For example.reg . c4.f64 f1. %ptr. note that . ld. ld. [y+8].c4.u32 %res) inc_ptr ( .4). } { . c3. char c[4].u32 %ptr.b32 c1.s32 out) bar (. %rc2.PTX ISA Version 2.reg . ld.reg . [y+0]. c2.b8 [py+ 9].reg .s32 x.f64 f1.func (.reg .u32 %inc ) { add.0 Example: .c2. %rd.param.param . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .

param arguments.param argument must be declared within the local scope of the caller. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. Typically.param or .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg variables. The .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. • The .param and ld.reg variables. . In the case of .reg space formal parameters. January 24.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. For . or a constant that can be represented in the type of the formal parameter. Supporting the .reg state space in this way provides legacy support. and alignment of parameters.param byte array is used to collect together fields of a structure being passed by value. 2. or a constant that can be represented in the type of the formal parameter. • The . or constants. the corresponding argument may be either a .Chapter 7.param space byte array with matching type. • • Arguments may be . size. For a callee.reg state space can be used to receive and return base-type scalar and vector values. In the case of . The following restrictions apply to parameter passing. • • • Input and return parameters may be .param state space use in device functions. 2010 51 . all st. In the case of .reg or .param variables or . For a caller.g.param space formal parameters that are byte arrays. • • • For a callee. Abstracting the ABI The following is a conceptual way to think about the .reg space variable with matching type and size. size. For a caller. the argument must also be a .param instructions used for argument passing must be contained in the basic block with the call instruction.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. 8. A .. The . a . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. and alignment. This enables backend optimization and ensures that the .reg space variable of matching type and size.param variables.param state space is used to receive parameter values and/or pass return values back to the caller. or 16 bytes. Parameters in . the corresponding argument may be either a .param memory must be aligned to a multiple of 1. 4.param or .param space formal parameters that are base-type scalar or vector variables. Note that the choice of .

52 January 24. Changes from PTX 1. PTX 1.0 continues to support multiple return registers for sm_1x targets.x In PTX ISA version 1.0 restricts functions to a single return value.PTX ISA Version 2. For sm_2x targets.1. and . Objects such as C structures were flattened and passed or returned using multiple registers. and there was no support for array parameters.0 7. formal parameters were restricted to . and a .param byte array should be used to return objects that do not fit into a register. PTX 2.x. PTX 2. 2010 . formal parameters may be in either .0.x supports multiple return values for this purpose. In PTX ISA version 2.reg or .param state space.reg state space.param space parameters support arrays.1.

along with the size and alignment of the next data value to be accessed. 4. (ap. .func %va_end (. Variadic functions NOTE: The current version of PTX does not support variadic functions. . 4.reg .func (.u32 sz. .u32 N. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . . . 2.. %s2).b32 result.reg . bra Done.func baz ( .u32 b. %va_end is called to free the variable argument list handle. or 8 bytes.u32 align) . max.u32 ptr.b64 val) %va_arg64 (. the alignment may be 1. 4. or 4 bytes.reg .b32 ctr. Once all arguments have been processed.u32.reg .reg . This handle is then passed to the %va_arg and %va_arg64 built-in functions. N.h headers in C. 2. . 4).func (.reg .reg .reg . (ap). (2. maxN. // default to MININT mov.2. In PTX. To support functions with a variable number of arguments.reg . 2. (3. In both cases. 0x8000000.reg . For %va_arg. ) { .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 ptr.func okay ( … ) Built-in functions are provided to initialize.func ( . Abstracting the ABI 7. 0. the size may be 1.reg . %r3).reg . %va_start.u32 align) . result. call (val). … %va_start returns Loop: @p Done: January 24. the size may be 1. %r2. %s1.s32 val..u32 a. or 16 bytes.u32 sz.s32 result ) maxN ( . call (ap).u32 ap. val.u32 ptr) %va_start .func (. setp. and end access to a list of variable arguments.s32 result.reg . following zero or more fixed parameters: . … ) . ctr.b32 val) %va_arg (. … call (%max). ret. for %va_arg64. } … call (%max). bra Loop. The function prototypes are defined as follows: . call %va_end. 2010 53 .Chapter 7.reg .ge p. variadic functions are declared with an ellipsis at the end of the input parameter list.reg . %r1.h and varargs. %va_arg. mov. .reg . maxN.reg . iteratively access. ctr.pred p. PTX provides a high-level mechanism similar to the one provided by the stdarg. 8. .

The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. 2010 .func ( .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.u32 ptr ) %alloca ( . To allocate memory.local and st. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.0 7.reg . 54 January 24. defined as follows: . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.3. The array is then accessed with ld. If a particular alignment is required.local instructions. Alloca NOTE: The current version of PTX does not support alloca. a function simply calls the built-in function %alloca.reg .PTX ISA Version 2.

1. B. opcode D. q = !(a < b). A.2.Chapter 8. b. A. followed by some examples that attempt to show several possible instantiations of the instruction. opcode D. We use a ‘|’ symbol to separate multiple destination registers. In addition to the name and the format of the instruction. 8. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. and C are the source operands. B. a. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. Instruction Set 8.lt p|q. For instructions that create a result value. setp. The setp instruction writes two destination registers.s32. the semantics are described. the D operand is the destination operand. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. For some instructions the destination operand is optional. C. A. PTX Instructions PTX instructions generally have from zero to four operands. 2010 55 . // p = (a < b). opcode D. while A. opcode A. B. January 24.

predicate registers are virtual and have . The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. This can be written in PTX as @p setp. the following PTX instruction sequence might be used: @!p L1: setp.lt. optionally negated. branch over 56 January 24.pred as the type specifier. predicate registers can be declared as . bra L1. i. add.s32 p. add. n. i.s32 p. use a predicate to control the execution of the branch or call instructions. where p is a predicate variable. // p = (i < n) // if i < n.PTX ISA Version 2. To implement the above example as a true conditional branch.s32 j. So. Predicates are most commonly set as the result of a comparison performed by the setp instruction. n.3. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.0 8. 1. Predicated Execution In PTX. j. add 1 to j To get a conditional branch or conditional function call. As an example.s32 j. Instructions without a guard predicate are executed unconditionally. … // compare i to n // if false. 1.reg . j. q. consider the high-level code if (i < n) j = j + 1. 2010 .pred p.lt.

2. le. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. lt. gt. lt (less-than). gt (greater-than).3.3. the result is false. Table 16. ge.3. ne.1. Comparisons 8. Unsigned Integer. If either operand is NaN. unsigned integer. The following table shows the operators for signed integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).1. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. ls (lower-or-same). Instruction Set 8. Table 15.Chapter 8. lo (lower).1. 2010 57 . and ge (greater-than-or-equal). and hs (higher-or-same). le (less-than-or-equal). ne (not-equal). ne. The unsigned comparisons are eq. hi (higher). and bitsize types.1. The bit-size comparisons are eq and ne. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ordering comparisons are not defined for bit-size types.

u32 %r1.1. then these comparisons have the same result as their ordered counterparts. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. and nan returns true if either operand is NaN. gtu. 2010 . for example: selp. // convert predicate to 32-bit value 58 January 24. geu. There is no direct conversion between predicates and integer values. setp can be used to generate a predicate from an integer.0 To aid comparison operations in the presence of NaN values. Table 18. xor.%p. If either operand is NaN.3. unordered versions are included: equ. leu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.PTX ISA Version 2. or. If both operands are numeric values (not NaN). However.0. not. num returns true if both operands are numeric values (not NaN). neu. then the result of these comparisons is true.2. two operators num (numeric) and nan (isNaN) are provided. and no direct way to load or store predicate register values. ltu. Table 17. and mov.

For example.4.u16 d. add. a. Instruction Set 8.e.u16 d. Type Checking Rules Operand Type . and these are placed in the same order as the operands.sX ok ok ok inv .. It requires separate type-size modifiers for the result and source. Table 19. and this information must be specified as a suffix to the opcode.u16 d. and integer operands are silently cast to the instruction type if needed. i. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. unsigned. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. a. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.reg . float.u16 a.uX . Signed and unsigned integer types agree provided they have the same size. they must match exactly. Floating-point types agree only if they have the same size. b. Example: . 2010 59 . the add instruction requires type and size information to properly perform the addition operation (signed.bX .fX ok inv inv ok Instruction Type .reg .bX . cvt. b.sX . For example.fX ok ok ok ok January 24. For example: .Chapter 8. different sizes). most notably the data conversion instruction cvt. a.f32 d.reg .uX ok ok ok inv . • The following table summarizes these type checking rules.f32.

Table 20. 60 January 24.1. stored.PTX ISA Version 2. ld. 4. 2. Floating-point source registers can only be used with bit-size or floating-point instruction types. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. 1. the size must match exactly. st. Operand Size Exceeding Instruction-Type Size For convenience. no conversion needed. When used with a narrower bit-size type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. Note that some combinations may still be invalid for a particular instruction. and converted using regular-width registers. Notes 3. or converted to other types and sizes. floating-point instruction types still require that the operand type-size matches exactly. for example. so that narrow values may be loaded. For example. When a source operand has a size that exceeds the instruction-type size. the data will be truncated. The following table summarizes the relaxed type-checking rules for source operands. 2010 . the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. When used with a floating-point instruction type.bX instruction types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. stored.0 8. The data is truncated to the instruction-type size and interpreted according to the instruction type. unless the operand is of bit-size type. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Bit-size source registers may be used with any appropriately-sized instruction type. parse error. inv = invalid.4. Source register size must be of equal or greater size than the instruction-type size. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. “-“ = allowed. so those rows are invalid for cvt. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. the cvt instruction does not support .

b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. If the corresponding instruction type is signed integer. Floating-point destination registers can only be used with bit-size or floating-point instruction types. When used with a floatingpoint instruction type. parse error. the destination data is zero. The data is signextended to the destination register width for signed integer instruction types. Notes 3. otherwise. When used with a narrower bit-size instruction type. inv = Invalid. The data is sign-extended to the destination register width for signed integer instruction types. 2010 61 . Instruction Set When a destination operand has a size that exceeds the instruction-type size. Bit-size destination registers may be used with any appropriately-sized instruction type. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. Table 21. the data is zeroextended. January 24. the data is sign-extended. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. 1. “-“ = Allowed but no conversion needed. zext = zero-extend. 2. Destination register size must be of equal or greater size than the instruction-type size. the data will be zero-extended. The following table summarizes the relaxed type-checking rules for destination operands. and is zero-extended to the destination register width otherwise.or sign-extended to the size of the destination register.Chapter 8. the size must match exactly. 4.

uni suffix. for many performance-critical applications. so it is important to have divergent threads re-converge as soon as possible. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. for example. Divergence of Threads in Control Constructs Threads in a CTA execute together. and for many applications the difference in execution is preferable to limiting performance. A compiler or programmer may chose to enforce portable. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. this is not desirable. until they come to a conditional control construct such as a conditional branch. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent.1. 16-bit registers in PTX are mapped to 32-bit physical registers. the threads are called divergent. using the . 62 January 24. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. Therefore. conditional function call. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. The semantics are described using C.6. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. until C is not expressive enough.6. When executing on a 32-bit data path. 8. 2010 . and 16-bit computations are “promoted” to 32-bit computations. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. At the PTX language level. the optimizing code generator automatically determines points of re-convergence. by a right-shift instruction.0 8. at least in appearance. However. If threads execute down different control flow paths. If all of the threads act in unison and follow a single control flow path.PTX ISA Version 2. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine.5. the threads are called uniform. For divergent control flow. 8. the semantics of 16-bit instructions in PTX is machine-specific. a compiler or code author targeting PTX can ignore the issue of divergent threads. Both situations occur often in programs. These extra precision bits can become visible at the application level. or conditional return. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path.

8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. The Integer arithmetic instructions are: add sub add.7.1.cc. 2010 63 . Instruction Set 8.cc. Instructions All PTX instructions may be predicated.Chapter 8. addc sub. the optional guard predicate is omitted from the syntax. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7. In the following descriptions.

s16.b. d.s32.sat limits result to MININT. d = a – b.u64.s64 }. b. 2010 .PTX ISA Version 2.u64.MAXINT (no overflow) for the size of the operation. add Syntax Integer Arithmetic Instructions: add Add two values. // . Saturation modifier: . b.1. . add.y.s32 d.s64 }.s32. .. a. sub.type sub{.s32 type. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. . PTX ISA Notes Target ISA Notes Examples 64 January 24. // .u16.sat applies only to . .u32 x. .s32 c. Introduced in PTX ISA version 1.sat}.0. sub. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.type = { .type add{.type = { . Introduced in PTX ISA version 1.s32 . a.s32 type. Applies only to . Supported on all target architectures.. b. b.u32. .z.sat}.a.sat limits result to MININT. .0.s32 d.0 Table 22. Supported on all target architectures. Saturation modifier: . @p add.sat applies only to . d = a + b.MAXINT (no overflow) for the size of the operation. . . a. add. a.s32 c. Description Semantics Notes Performs addition and writes the resulting value into a destination register. Applies only to . d. .u16.c.u32. PTX ISA Notes Target ISA Notes Examples Table 23.s16.sat.s32 .

addc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.type d.CF No integer rounding modifiers.y3. No saturation.2.cc. Supported on all target architectures. No other instructions access the condition code.b32 addc.type = { .CF No integer rounding modifiers.cc Syntax Integer Arithmetic Instructions: add. @p @p @p @p add.z4.b32 x1.s32 }.b32 x1.z1.y4. . . add. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y2. Behavior is the same for unsigned and signed integers.type = {.y1.cc}.u32.cc.b32 addc. a. b. x2. Introduced in PTX ISA version 1.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.CF.cc. x3. x4. x4. These instructions support extended-precision integer addition and subtraction. carry-out written to CC.2.cc.b32 addc.b32 addc.cc. d = a + b + CC. addc{. Instruction Set Instructions add. d = a + b. b. Table 24.s32 }.cc Add two values with carry-out. or testing the condition code.cc specified. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.cc.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.z3.Chapter 8.z4. x3.z1.b32 addc. x2. add.y3. @p @p @p @p add. No saturation. Behavior is the same for unsigned and signed integers. Supported on all target architectures.y4. . if .cc.y1.cc. and there is no support for setting.CF) holding carry-in/carry-out or borrowin/borrow-out.cc. clearing.y2. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.type d.b32 addc. 2010 65 . Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. carry-out written to CC.z3.u32. a. Introduced in PTX ISA version 1. sub. .z2.z2.

. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y4. x2.cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. sub. Behavior is the same for unsigned and signed integers.cc Subract one value from another.z4.cc.b32 x1.cc.b32 subc.CF). if . No saturation. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. @p @p @p @p sub.b32 subc.z1. .z2.y1.z3.3.PTX ISA Version 2. a. b. .s32 }.y3.3. with borrow-out.cc specified.b32 subc.cc.cc. sub.z4.z3.y2.u32.type = { . 2010 .y1.z2. d = a – b.type d.type d.0 Table 26.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. x3.cc.b32 x1.s32 }.cc Syntax Integer Arithmetic Instructions: sub. No saturation.cc.z1.(b + CC.CF No integer rounding modifiers. Supported on all target architectures.y4.b32 subc. subc{.cc}.u32. Supported on all target architectures.cc. x2.type = {. b.y3. x4. borrow-out written to CC.CF No integer rounding modifiers.cc.b32 subc. Introduced in PTX ISA version 1. Behavior is the same for unsigned and signed integers. borrow-out written to CC. withborrow-in and optional borrow-out. d = a . x3. x4. @p @p @p @p sub. a. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. Introduced in PTX ISA version 1. .y2.

If .type d.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide // for . d = t<2n-1. Supported on all target architectures.type = { . creates 64 bit result January 24.n>. then d is the same size as a and b. mul. The . // for . .lo is specified. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. and either the upper or lower half of the result is written to the destination register. . If . . n = bitwidth of type.y.wide}.s16 fa.hi.hi variant // for . 2010 67 . save only the low 16 bits // 32*32 bits.fxs.wide.wide. d = t<n-1. then d is twice as wide as a and b to receive the full result of the multiplication.s16.x.fys. a.. mul. d = t. ..s64 }. b.wide is specified.s32.s32 z. mul{.0.wide suffix is supported only for 16.lo. mul. t = a * b.lo..and 32-bit integer types.u16.lo variant Notes The type of the operation represents the types of the a and b operands.Chapter 8.fxs.s16 fa.0>. Description Semantics Compute the product of two values. .fys.u64. // 16*16 bits yields 32 bits // 16*16 bits.hi or .u32. . Instruction Set Table 28.

s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. bitwidth of type.type = { . mad{.type mad.sat.u32.sat limits result to MININT. 2010 .s32 r.s16. The . . c.and 32-bit integer types. Supported on all target architectures. .hi mode.c. .hi or . .wide suffix is supported only for 16.. Applies only to .lo. b.a. Saturation modifier: . and either the upper or lower half of the result is written to the destination register. 68 January 24.MAXINT (no overflow) for the size of the operation..PTX ISA Version 2. @p mad.u16..b.hi. // for .lo is specified. mad. t<n-1.lo.s64 }. b. Description Semantics Multiplies two values and adds a third. a.0. a. If .. c.0 Table 29. d.wide}. .s32 d.wide // for .. t<2n-1.r. t + c.u64. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.0> + c.hi variant // for .wide is specified.q.s32 type in .s32. then d and c are twice as wide as a and b to receive the result of the multiplication. t n d d d = = = = = a * b.hi.n> + c.lo.lo variant Notes The type of the operation represents the types of the a and b operands. If .p. and then writes the resulting value into a destination register. . then d and c are the same size as a and b.

. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.. and return either the high or low 32-bits of the 48-bit result.type = { . Supported on all target architectures.a.lo.lo}. January 24.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.0.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. mul24. b.b.s32 }. mul24. i.s32 d. // low 32-bits of 24x24-bit signed multiply.e.type d.hi.16>.Chapter 8. Instruction Set Table 30. . // for .0>. All operands are of the same type and size.. 2010 69 . mul24.u32.hi may be less efficient on machines without hardware support for 24-bit multiply. d = t<47. d = t<31. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. t = a * b.hi variant // for . . mul24{.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. 48bits. mul24. a.

mad24.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.hi. Saturation modifier: .. 70 January 24. a. All operands are of the same type and size.hi variant // for . . 48bits.lo.u32..e.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. .PTX ISA Version 2. // for .lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. Applies only to . // low 32-bits of 24x24-bit signed multiply.type = { .s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.sat. d = t<31.MAXINT (no overflow). 2010 .. i.lo}. Return either the high or low 32-bits of the 48-bit result.hi may be less efficient on machines without hardware support for 24-bit multiply.b.hi mode. mad24. Description Compute the product of two 24-bit integer values held in 32-bit source registers.s32 }. d = t<47.c. b.sat limits result of 32-bit signed addition to MININT.hi.. mad24{. Supported on all target architectures.0> + c. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.0. and add a third.0 Table 31. a.16> + c.s32 type in .type mad24. c.s32 d. b. 32-bit value to either the high or low 32-bits of the 48-bit result.a. mad24. mad24. d. t = a * b. c.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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cnt. while (a != 0) { if (a&0x1) d++. clz. } Introduced in PTX ISA version 2.b32 popc. a = a << 1. } else { max = 64. 2010 .0. // cnt is . inclusively. a. cnt.type d.PTX ISA Version 2. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. clz. a.b32 type. X. a.type = { . . popc Syntax Integer Arithmetic Instructions: popc Population count.u32 Semantics 74 January 24.u32 PTX ISA Notes Target ISA Notes Examples Table 40. // cnt is . popc requires sm_20 or later. X. clz requires sm_20 or later.b64 type.b32 clz.type d.b64 }.b64 d. . clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. } while (d < max && (a&mask == 0) ) { d++. a. d = 0. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. a = a >> 1.type == . mask = 0x8000000000000000.b32) { max = 32. the number of leading zeros is between 0 and 32. popc.0. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 39. For . . popc. d = 0. mask = 0x80000000. if (.b64 }. the number of leading zeros is between 0 and 64. inclusively.type = { .b64 d.b32. For .b32.

u32.type = { .0. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. i>=0. For signed integers. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.s64 }. d = -1.Chapter 8. a. bfind.type==.shiftamt. // cnt is . bfind.u32 d. and operand d has type . 2010 75 .u64.u32. break. bfind requires sm_20 or later. Semantics msb = (.type d. . d. i--) { if (a & (1<<i)) { d = i.s32) ? 31 : 63. bfind returns 0xFFFFFFFF if no non-sign bit is found. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If .d. } } if (. .shiftamt && d != -1) { d = msb .u32 || .s64 cnt. Description Find the bit position of the most significant non-sign bit in a and place the result in d.shiftamt is specified. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. For unsigned integers. . . a. X. a. Operand a has the instruction type.shiftamt.s32. bfind returns the bit position of the most significant “1”. for (i=msb. Instruction Set Table 41. bfind.u32 January 24.type bfind.type==.

for (i=0. 76 January 24.0 Table 42. Description Semantics Perform bitwise reversal of input. . a. .b32) ? 31 : 63. i<=msb. i++) { d[i] = a[msb-i]. brev.PTX ISA Version 2. brev. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a.0. msb = (. 2010 .b32 d. brev requires sm_20 or later.b64 }.type==.type d.type = { .b32.

else sbit = a[min(pos+len-1. if (. . . i<=msb.b32 d.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.u64. If the start position is beyond the msb of the input. otherwise If the bit field length is zero.a.s32) ? 31 : 63. Operands a and d have the same type as the instruction type. . bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. for (i=0.s32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. bfe. d = 0. January 24. Instruction Set Table 43. The sign bit of the extracted field is defined as: . .type==. bfe requires sm_20 or later. the destination d is filled with the replicated sign bit of the extracted field.type = { .len. Source b gives the bit field starting bit position.u64: .u32. c.type==.u32 || .type d. Semantics msb = (.msb)].type==.u64 || len==0) sbit = 0.0.start. Description Extract bit field from a and place the zero or sign-extended result in d. and operands b and c are type . The destination d is padded with the sign bit of the extracted field.s64 }.type==. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. pos = b. and source c gives the bit field length in bits.u32. a. .Chapter 8. . len = c. 2010 77 . the result is zero. bfe.u32 || . b.s32.

and operands c and d are type .type f. Description Align and insert a bit field from a into b. the result is b. for (i=0. Operands a. f = b. d. If the bit field length is zero. Source c gives the starting bit position for the insertion. pos = c.a. bfi.type = { . bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. and source d gives the bit field length in bits.PTX ISA Version 2. . and f have the same type as the instruction type. len = d.type==. Semantics msb = (. c. bfi requires sm_20 or later.b32.len.b32) ? 31 : 63.b64 }. b.b32 d. 78 January 24. i<len && pos+i<=msb.start. i++) { f[pos+i] = a[i]. b.0 Table 44. a. 2010 . bfi.0. and place the result in f. the result is b.b. . If the start position is beyond the msb of the input.u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

. Instruction Set Table 45. prmt. and reassemble them into a 32-bit destination register.b1 source select c[7:4] d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.Chapter 8.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. For each byte in the target register.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. Note that the sign extension is only performed as part of generic form. b. . Description Pick four arbitrary bytes from two 32-bit registers. b0}}. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.ecr. The msb defines if the byte value should be copied. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. b5.b4e.ecl. default mode index d. 2010 79 . the permute control consists of four 4-bit selection values. Thus. In the generic form (no mode specified). as a 16b permute code. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.rc16 }. b1. b6.mode = { . .b3 source select c[15:12] d. b2.f4e. a.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b32{. a 4-bit selection value is defined. . msb=0 means copy the literal value. . c. a} = {{b7.rc8. The bytes in the two source registers are numbered from 0 to 7: {b. the four 4-bit values fully specify an arbitrary byte permute. . {b3. b4}.mode} d. msb=1 means replicate the sign.b2 source select c[11:8] d.

f4e r1.0. ctl[0]. tmp[31:24] = ReadByte( mode. tmp64 ). r4. tmp64 ). prmt. tmp64 ). ctl[3]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. } tmp[07:00] = ReadByte( mode. r4. tmp64 ). tmp[15:08] = ReadByte( mode.b32 prmt. ctl[1] = (c >> 4) & 0xf. 2010 . r2. ctl[1]. ctl[3] = (c >> 12) & 0xf. r1. tmp[23:16] = ReadByte( mode. r3. ctl[2]. r3.b32. prmt requires sm_20 or later. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3.0 Semantics tmp64 = (b<<32) | a.PTX ISA Version 2. 80 January 24. r2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[2] = (c >> 8) & 0xf.

f32 and . 2010 81 .7. Floating-Point Instructions Floating-point instructions operate on .Chapter 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values. Instruction Set 8.2.

rnd.approx.mul}.ftz .f32 {div. If no rounding modifier is specified. default is . sub.rnd.fma}. so PTX programs should not rely on the specific single-precision NaNs being generated.min.f32 {div. {mad.lg2.f32 {add. with NaNs being flushed to positive zero. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. 2010 .target sm_1x No rounding modifier.sqrt}.rnd.f64 mad.rnd.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. {add.rn and instructions may be folded into a multiply-add.rcp.PTX ISA Version 2.f64 {abs.rnd. 1.rz .min.neg.rnd.sat Notes If no rounding modifier is specified.0 The following table summarizes floating-point instructions in PTX.approx.f32 {mad.cos.max}.rn and instructions may be folded into a multiply-add. and mad support saturation of results to the range [0.rcp.sub. Single-precision add.target sm_20 mad.rcp. but single-precision instructions return an unspecified NaN.mul}.f32 are the same.full. default is .sqrt}.rm .f64 are the same.0. The optional . Instruction Summary of Floating-Point Instructions . mul.rn .f32 {div. NaN payloads are supported for double-precision instructions.f32 rsqrt.sqrt}.fma}.approx. Double-precision instructions support subnormal inputs and results. Note that future implementations may support NaN payloads for single-precision instructions.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f64 div.f64 and fma.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f64 rsqrt.f64 {sin. 82 January 24. Table 46.approx.0].ex2}. .neg.rp .max}.32 and fma.f32 .sub. .target sm_20 .f32 {abs. No rounding modifier.

testp. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.Chapter 8. copysign. X.infinite. copysign. a. B. Instruction Set Table 47. z. A. Introduced in PTX ISA version 2.f64 isnan.normal.notanumber testp. and return the result as d. Table 48. .normal testp.notanumber.op. testp.type d. p.f32 testp. . y. C. not infinity) As a special case. .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. .type = { . .f32. not infinity). testp. positive and negative zero are considered normal numbers.op p. testp requires sm_20 or later. January 24. . .subnormal }. b.infinite testp.pred = { .0.infinite. copysign requires sm_20 or later. testp Syntax Floating-Point Instructions: testp Test floating-point property.type = { .type . . a.f64 }. // result is .f64 x. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.notanumber.finite. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.f64 }.f32.0.number testp. true if the input is a subnormal number (not NaN.finite testp.number. .f32 copysign. 2010 83 . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. f0.

sm_1x: add.rz.rnd}. requires sm_20 Examples @p add.rn mantissa LSB rounds to nearest even .rm. 1. subnormal numbers are supported. .0].f32 supported on all target architectures. Saturation modifier: . add Syntax Floating-Point Instructions: add Add two values.f3. b. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rz. . In particular.rn): .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. add. add. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f64 supports subnormal numbers.0. b. a.ftz. .f64 d. d.0 Table 49. NaN results are flushed to +0.PTX ISA Version 2.f32 add{. d = a + b. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero.rn.0. add. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. a.ftz}{.sat}. requires sm_13 for add. add{.rz available for all targets .0f.f32 flushes subnormal inputs and results to sign-preserving zero.rp for add. .f32. add.f32 f1.rm. 84 January 24. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. Rounding modifiers (default is .ftz.rn. .rnd}{. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64.f64 requires sm_13 or later.f32 clamps the result to [0. .rnd = { .f2.sat. add. Rounding modifiers have the following target requirements: .rp }.rz mantissa LSB rounds towards zero .rm mantissa LSB rounds towards negative infinity .

January 24.0].f32. a.f3.f64.rm mantissa LSB rounds towards negative infinity .sat}.ftz.f32 clamps the result to [0. Rounding modifiers (default is . . b.rnd}.a.b. .rm. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sm_1x: sub. .rnd}{.rn.0. requires sm_13 for sub.rn mantissa LSB rounds to nearest even . sub. Rounding modifiers have the following target requirements: . requires sm_20 Examples sub. . sub Syntax Floating-Point Instructions: sub Subtract one value from another.rz available for all targets .0. subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}{. NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero. d.b.Chapter 8.f64 supports subnormal numbers.rn): .f32 flushes subnormal inputs and results to sign-preserving zero.rp }. Saturation modifier: sub.rn. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.0f.f32 sub{.f64 requires sm_13 or later. . In particular. sub. sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. b. sub{. d = a .sat.f32 supported on all target architectures. sub.f2. .f32 f1.rnd = { .f32 c.rn.f64 d. a.ftz.rz mantissa LSB rounds towards zero .rp for sub. 2010 85 .rm. Instruction Set Table 50. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. sub. 1.rz. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.

0f. all operands must be the same size.f32 circumf.sat}. Saturation modifier: mul.rp }. a. d. NaN results are flushed to +0.rn mantissa LSB rounds to nearest even . requires sm_20 Examples mul. mul.rz.rnd = { .0]. 1.f32 supported on all target architectures.ftz}{.f32 clamps the result to [0.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 51. requires sm_13 for mul.rnd}. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rn. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rz mantissa LSB rounds towards zero .f64 supports subnormal numbers.rm mantissa LSB rounds towards negative infinity .rm.sat. sm_1x: mul.0. mul{.ftz. Description Semantics Notes Compute the product of two values.PTX ISA Version 2.f32.rm. b. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64. mul Syntax Floating-Point Instructions: mul Multiply two values. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. subnormal numbers are supported. Rounding modifiers (default is .rn. Rounding modifiers have the following target requirements: . . mul.rp for mul.rnd}{. .0. In particular.pi // a single-precision multiply 86 January 24.radius. d = a * b.f32 mul{.f64 d. mul. 2010 .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 requires sm_13 or later.rn): . b. . . For floating-point multiplication. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rz available for all targets . mul.ftz. . .

a.rm mantissa LSB rounds towards negative infinity .rn. fma.rnd. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. @p fma. sm_1x: fma.rn mantissa LSB rounds to nearest even .ftz. a.a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. again in infinite precision. d.0.y. fma. 2010 87 .rm.f32 introduced in PTX ISA version 2.f32 clamps the result to [0.0f. NaN results are flushed to +0. fma. c.f32 flushes subnormal inputs and results to sign-preserving zero.f64 is the same as mad.f64 computes the product of a and b to infinite precision and then adds c to this product. c. . . Saturation: fma.f64 requires sm_13 or later.rz.4. Rounding modifiers (no default): . Instruction Set Table 52. b.f64 w.rnd = { .f32 fma.sat}.0].rp }.rn.rnd. fma. . again in infinite precision. fma. fma.rn.ftz}{.f32 computes the product of a and b to infinite precision and then adds c to this product. b.f64 introduced in PTX ISA version 1.0.c. PTX ISA Notes Target ISA Notes Examples January 24.rz mantissa LSB rounds towards zero . fma. 1.x.f64 supports subnormal numbers. The resulting value is then rounded to single precision using the rounding mode specified by . fma.f64.rnd.z.f32 fma. The resulting value is then rounded to double precision using the rounding mode specified by .f32 is unimplemented in sm_1x.f32 requires sm_20 or later.ftz. d.sat.f64 d.b. fma. . fma.rnd{.Chapter 8. subnormal numbers are supported. d = a*b + c. fma Syntax Floating-Point Instructions: fma Fused multiply-add.

subnormal numbers are supported. again in infinite precision..PTX ISA Version 2.target sm_1x: mad.{f32. The exception for mad.f32 is when c = +/-0. mad.rp }. In this case. where the mantissa can be rounded and the exponent will be clamped. mad. NaN results are flushed to +0. Saturation modifier: mad.f32 clamps the result to [0.0f. // .target sm_13 and later .rn mantissa LSB rounds to nearest even .f32.f64 supports subnormal numbers. c. again in infinite precision.f32 mad. Unlike mad. Description Semantics Notes Multiplies two values and adds a third.rn.0].rnd = { .f32 mad. Rounding modifiers (no default): . // .rm mantissa LSB rounds towards negative infinity .{f32. but the exponent is preserved.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.target sm_20 d.rz mantissa LSB rounds towards zero . . 88 January 24. a. The resulting value is then rounded to single precision using the rounding mode specified by . mad. d = a*b + c.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}{.rnd.f64 computes the product of a and b to infinite precision and then adds c to this product. fma. again in infinite precision. The resulting value is then rounded to double precision using the rounding mode specified by . mad.f64. When JIT-compiled for SM 2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. For .f32 is implemented as a fused multiply-add (i. b. b.rz.0.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz}{. and then the mantissa is truncated to 23 bits.f64 d. // .sat.rnd.0 Table 53. mad. 1.f64 is the same as fma. The resulting value is then rounded to double precision using the rounding mode specified by . c. For . mad. mad. Note that this is different from computing the product with mul.rnd. . .rn. the treatment of subnormal inputs and output follows IEEE 754 standard.ftz. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. mad{. and then writes the resulting value into a destination register.f32 computes the product of a and b to infinite precision and then adds c to this product.target sm_1x d. 2010 . b.f64} is the same as fma.target sm_20: mad. c. sm_1x: mad. mad.f64}. a.f32 is identical to the result computed using separate mul and add instructions.f32).rnd{.rm.sat}. a.sat}.0.rnd.f32 flushes subnormal inputs and results to sign-preserving zero.f32 computes the product of a and b at double precision. mad.e.0 devices.

f64 instructions having no rounding modifier will map to mad.f64 requires sm_13 or later.c.0 and later.rp for mad. Target ISA Notes mad.rm..rn. a rounding modifier is required for mad.f64. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f32 d. a rounding modifier is required for mad. Legacy mad..b.rn.f64.f32.f32 for sm_20 targets.Chapter 8.4 and later. January 24. mad.a. 2010 89 . requires sm_13 ... requires sm_20 Examples @p mad.rn.0.rz.f64.rm.rz..f32 supported on all target architectures. In PTX ISA versions 1. In PTX ISA versions 2..rp for mad. Rounding modifiers have the following target requirements: .

y. xd. .f32 supported on all target architectures.full.f32. a. a. div.rz. Subnormal inputs and results are flushed to sign-preserving zero. PTX ISA Notes div. the maximum ulp error is 2. d.f64 supports subnormal numbers.rn mantissa LSB rounds to nearest even .full{. d = a / b.rm. approximate single-precision divides: div.approx{. div. Fast. approximate division by zero creates a value of infinity (with same sign as a).f64 introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_20 or later.full.approx. .rnd = { . computed as d = a * (1/b). For b in [2-126. Fast.rm mantissa LSB rounds towards negative infinity .f64.f64 diam.f32 div. yd. z.f32 defaults to div.f32 div.rn.f32 implements a fast approximation to divide.0 through 1. and rounding introduced in PTX ISA version 1.rn.rnd. .3.f32 requires sm_20 or later. a.ftz. div. div Syntax Floating-Point Instructions: div Divide one value by another. For PTX ISA version 1.f32 div. b.ftz}. For PTX ISA versions 1. subnormal numbers are supported. b.f64 defaults to div.f64 d. x. 2010 . d. d.f32 and div.rnd{. Target ISA Notes div.full.14159.ftz.approx.f32 div. a. div.f64 requires sm_13 or later. div.approx. full-range approximation that scales operands to achieve better accuracy.approx. .ftz. or .3. // // // // fast.f32 and div. Explicit modifiers .full.ftz}. zd.4. b.f32 div.rp }.rn.f32 flushes subnormal inputs and results to sign-preserving zero. and div.ftz.f32 implements a relatively fast. div. one of .rp}. .0 Table 54.4 and later.rm.{rz. div. div. b.rn.rnd is required. div. Description Semantics Notes Divides a by b. sm_1x: div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.PTX ISA Version 2.rnd.circum.approx.ftz.approx. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .0.full. The maximum ulp error is 2 across the full range of inputs.ftz}. .rz mantissa LSB rounds towards zero . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . but is not fully IEEE 754 compliant and does not support rounding modifiers. stores result in d. 2126]. Examples 90 January 24.

Negate the sign of a and store the result in d. abs{.ftz. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.Chapter 8. abs. NaN inputs yield an unspecified NaN. Table 56.f64 d. abs.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero.f32 x.ftz. Take the absolute value of a and store the result in d. abs. neg.f64 requires sm_13 or later.f32 neg. sm_1x: neg. d = -a.f64 supports subnormal numbers. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero. d = |a|. neg. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 abs. d.f0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.0.f32 flushes subnormal inputs and results to sign-preserving zero. a. a.f64 d. NaN inputs yield an unspecified NaN. Subnormal numbers: sm_20: By default. neg.f32 supported on all target architectures. a.ftz. January 24. sm_1x: abs. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f32 supported on all target architectures. abs.0. neg{. Subnormal numbers: sm_20: By default.f64 requires sm_13 or later. subnormal numbers are supported.ftz. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f64 supports subnormal numbers. Instruction Set Table 55. a. d.f0.ftz}. 2010 91 . abs.

f64 requires sm_13 or later.f2. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.c.f32 flushes subnormal inputs and results to sign-preserving zero.f32 min. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. subnormal numbers are supported. a.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. min.f32 flushes subnormal inputs and results to sign-preserving zero. b. 2010 . d. a.f64 f0. a. @p min.ftz.f32 max. a.0 Table 57. max{. min.f64 z. a. d d d d = = = = NaN.f64 d. subnormal numbers are supported.0. max.f32 supported on all target architectures. a. b. d d d d = = = = NaN.f32 min.ftz.f64 supports subnormal numbers. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. a. 92 January 24. max.ftz}. b.f64 requires sm_13 or later. Table 58. (a > b) ? a : b.z. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. sm_1x: max.b. Store the maximum of a and b in d.ftz}. d.x. b.f1.f32 max. a. min.b.c. max.0.ftz. (a < b) ? a : b. Store the minimum of a and b in d.ftz. sm_1x: min. b. min{. max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.PTX ISA Version 2. b.f64 supports subnormal numbers. min.f32 supported on all target architectures.

approx{. one of .rm.x.4 and later.rn.approx. a.f32 and rcp. Input -Inf -subnormal -0.rp }.r.0.ftz were introduced in PTX ISA version 1. .rz. xi.Chapter 8.3.ftz. rcp.f64 supports subnormal numbers.0 -Inf -Inf +Inf +Inf +0. d. The maximum absolute error is 2-23.f32 supported on all target architectures.0 +0.rn. sm_1x: rcp.approx.{rz.0.f64 requires sm_13 or later. // fast. Examples January 24. . Instruction Set Table 59. 2010 93 . d. Target ISA Notes rcp. rcp. d = 1 / a.approx and .rnd. rcp. . and rcp. a. a. subnormal numbers are supported.approx or .f64 defaults to rcp.f32 rcp. rcp.rnd{.rn mantissa LSB rounds to nearest even . store result in d.rm mantissa LSB rounds towards negative infinity .f32 implements a fast approximation to reciprocal.f64 ri.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64 introduced in PTX ISA version 1.f64. rcp.f32 rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. rcp. PTX ISA Notes rcp. rcp.rn.ftz}.0. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rnd is required.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 defaults to rcp.f64 requires sm_20 or later.rz mantissa LSB rounds towards zero . For PTX ISA versions 1. Description Semantics Notes Compute 1/a.rn.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.f32 rcp.ftz.x.rn.rn. xi.f64 d. General rounding modifiers were added in PTX ISA version 2.f32 rcp.ftz. rcp.0-2.ftz.f32 requires sm_20 or later. For PTX ISA version 1.0 over the range 1.4.rnd = { .approx.0 through 1. rcp.rp}.f32 flushes subnormal inputs and results to sign-preserving zero.rnd.rm.0 +subnormal +Inf NaN Result -0.f64 and explicit modifiers .approx. rcp.f32.

sqrt.f64 introduced in PTX ISA version 1. subnormal numbers are supported. a.rm.f32 sqrt. Examples 94 January 24. Target ISA Notes sqrt.rp}.f64 requires sm_13 or later.ftz.f64 defaults to sqrt. and sqrt.rm mantissa LSB rounds towards negative infinity .rnd = { .f64 d.f32 sqrt. 2010 .rn.f64 requires sm_20 or later. PTX ISA Notes sqrt.rnd{. r.0 +0.0.approx and . // fast. General rounding modifiers were added in PTX ISA version 2. sqrt.approx.f64 and explicit modifiers .rn.f32 implements a fast approximation to square root.ftz.approx. Input -Inf -normal -subnormal -0.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . The maximum absolute error for sqrt.3.PTX ISA Version 2. // IEEE 754 compliant rounding . sqrt.f64.f32. sqrt.0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.x.f32 requires sm_20 or later.{rz.rm.rz.approx or .f32 supported on all target architectures.f32 sqrt.0 +subnormal +Inf NaN Result NaN NaN -0.ftz}. .4.f32 is TBD. approximate square root d.0 through 1.0 Table 60.approx. For PTX ISA version 1.rn. store in d. sqrt. sqrt.approx. sm_1x: sqrt.rnd.f64 r.f64 supports subnormal numbers.0 +0.rn mantissa LSB rounds to nearest even . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. For PTX ISA versions 1. a.f32 sqrt.rnd is required.rz mantissa LSB rounds towards zero .rn.rn. a.x. // IEEE 754 compliant rounding d.ftz}. . r. sqrt. sqrt.0 +0.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt.x.rnd.ftz were introduced in PTX ISA version 1. d = sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero.approx{. .4 and later.ftz.approx.0 -0. Description Semantics Notes Compute sqrt(a). sqrt.rp }.f32 and sqrt.rn. one of .ftz.f32 defaults to sqrt.

a.0 through 1.approx.f64 is TBD. store the result in d. X.ftz. ISR. Compute 1/sqrt(a). January 24.approx implements an approximation to the reciprocal square root.approx.ftz}. Subnormal numbers: sm_20: By default.approx and .0 NaN The maximum absolute error for rsqrt. 2010 95 . rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 +0.f32 supported on all target architectures.approx modifier is required. rsqrt.3. For PTX ISA versions 1.approx.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.approx{. the .f64 supports subnormal numbers. Explicit modifiers . d.f64 is emulated in software and are relatively slow.f64. Instruction Set Table 61.4 and later.f64 were introduced in PTX ISA version 1.4.f32 flushes subnormal inputs and results to sign-preserving zero. d = 1/sqrt(a).f64 defaults to rsqrt.f32 rsqrt.ftz.0-4.f32 defaults to rsqrt.ftz.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt. PTX ISA Notes rsqrt.approx.0.0. subnormal numbers are supported. rsqrt. rsqrt.f32. x.f32 is 2-22. Target ISA Notes Examples rsqrt.f64 isr. Note that rsqrt.4 over the range 1. and rsqrt.Chapter 8.approx.ftz were introduced in PTX ISA version 1. The maximum absolute error for rsqrt.f32 rsqrt. Input -Inf -normal -subnormal -0.approx. For PTX ISA version 1. a. rsqrt. sm_1x: rsqrt. rsqrt.f64 d.f32 and rsqrt. rsqrt.

PTX ISA Version 2. Target ISA Notes Examples Supported on all target architectures.approx{.3.0 +subnormal +Inf NaN Result NaN -0. sin.0 +0.ftz}. d = sin(a).f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 introduced in PTX ISA version 1.ftz introduced in PTX ISA version 1.approx. 2010 . 96 January 24. sin.9 in quadrant 00. Find the sine of the angle a (in radians). PTX ISA Notes sin.approx modifier is required. the . For PTX ISA versions 1.f32 sa. Explicit modifiers .f32 d.0 Table 62.f32.approx. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. For PTX ISA version 1.0 through 1.4.approx. Subnormal numbers: sm_20: By default. sin.ftz. a.0 +0.0 -0.approx and .f32 defaults to sin. sin. sin.0 NaN NaN The maximum absolute error is 2-20.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to sine.0. subnormal numbers are supported.4 and later.0 +0.ftz. Input -Inf -subnormal -0.

f32 ca.f32 flushes subnormal inputs and results to sign-preserving zero. Input -Inf -subnormal -0. Find the cosine of the angle a (in radians).4.0 +1.0.4 and later. a. Subnormal numbers: sm_20: By default. the .f32 d.0 +1. Target ISA Notes Examples Supported on all target architectures.f32.0 through 1. January 24.approx. cos.Chapter 8.0 +subnormal +Inf NaN Result NaN +1.ftz.approx.approx. d = cos(a).approx{. Explicit modifiers .0 +1.approx and . cos.ftz. cos.9 in quadrant 00.approx modifier is required.f32 introduced in PTX ISA version 1.f32 implements a fast approximation to cosine.0 +0. a.3. For PTX ISA version 1. PTX ISA Notes cos. subnormal numbers are supported.0 NaN NaN The maximum absolute error is 2-20. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz}. cos.f32 defaults to cos. For PTX ISA versions 1. sm_1x: Subnormal inputs and results to sign-preserving zero. 2010 97 . cos.ftz.ftz introduced in PTX ISA version 1. Instruction Set Table 63.

approx. a. PTX ISA Notes lg2. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. the .f32 implements a fast approximation to log2(a).0 Table 64. a.ftz.f32 defaults to lg2.4 and later. For PTX ISA version 1.ftz. Input -Inf -subnormal -0. Target ISA Notes Examples Supported on all target architectures. Explicit modifiers .0.f32 flushes subnormal inputs and results to sign-preserving zero. 98 January 24. Subnormal numbers: sm_20: By default.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.approx. lg2.0 +0.ftz}.approx. d = log(a) / log(2). lg2. 2010 .approx and .PTX ISA Version 2.6 for mantissa.4. lg2. The maximum absolute error is 2-22.ftz.0 through 1.f32 la.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.approx{. lg2.3.f32 Determine the log2 of a.f32 introduced in PTX ISA version 1. For PTX ISA versions 1.ftz introduced in PTX ISA version 1.f32. lg2.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

Applies to all numeric types. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.ftz applies only to . ne. lo. p[|q]. p. and higher-or-same may be used instead of lt. geu. This result is written to the first destination operand. . then these comparisons have the same result as their ordered counterparts. ge.PTX ISA Version 2. a. unordered versions are included: equ. .f64 supports subnormal numbers. .b. . and (optionally) combine this result with a predicate value by applying a Boolean operator. ge. ls. xor.f32.type . b. ne. le. . For unsigned values. .s32 setp.dtype.u64. higher.s32. loweror-same. and can be one of: eq. le.pred variables. the result is false.lt. hi. and hs for lower. setp. The comparison operator is a suffix on the instruction.dtype. 102 January 24. gtu.n. sm_1x: setp.f64 source type requires sm_13 or later. ge.ftz.0.s64. If either operand is NaN. q = BoolOp(!t. lt. setp. ls. and nan returns true if either operand is NaN. ltu. then the result of these comparisons is true.CmpOp{. le. Subnormal numbers: sm_20: By default.b32. {!}c. gt.dtype.b64.f32 flushes subnormal inputs to sign-preserving zero.s16. hs equ. nan The Boolean operator BoolOp(A. a. the comparison operators lo. c). neu. ltu.and. subnormal numbers are supported. . num.b16. gt. respectively. gt. leu. . The destinations p and q must be . @q setp. If both operands are numeric values (not NaN). Modifier .type setp. le.f32 comparisons. setp. Integer Notes Floating Point Notes The ordered comparisons are eq.u16.ftz}. lt. b. gtu. . Description Compares two values and combines the result with another predicate value by applying a Boolean operator.f64 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. c).type = { .f32 flushes subnormal inputs to sign-preserving zero. geu.r. neu. lt.a. The untyped.i. or. ge.u32.0 Table 67.eq. hi.CmpOp.BoolOp{. leu.u32 p|q. 2010 . . The signed and unsigned comparison operators are eq. p[|q].ftz}. If either operand is NaN. ne. p = BoolOp(t. num returns true if both operands are numeric values (not NaN).B) is one of: and. gt. To aid comparison operations in the presence of NaN values. bit-size comparisons are eq and ne. A related value computed using the complement of the compare result is written to the second destination operand. Semantics t = (a CmpOp b) ? 1 : 0. setp with .

fval. slct. .u32. b. .f32 flushes subnormal values of operand c to sign-preserving zero. d. b otherwise. 2010 103 . The selected input is copied to the output without modification. f0. negative zero equals zero. the comparison is unordered and operand b is selected. based on the sign of the third operand. and b must be of the same type. a is stored in d.u16.f64 }. . .u64. slct.ftz applies only to .b16. . selp. otherwise b is stored in d. For . .g. Table 69.s64. . a.s32.b32. If c is True. .ftz. C. a. slct. based on the value of the predicate source operand. slct. .f32 A.s32 slct{.dtype. Description Conditional selection.b64. sm_1x: slct. . d = (c >= 0) ? a : b.f32. d = (c == 1) ? a : b.0. c.0.f64 }.type = { . a.s16.s32.u32. and b are treated as a bitsize type of the same width as the first instruction type. Instruction Set Table 68. Introduced in PTX ISA version 1. .s64. and operand a is selected.dtype.p. subnormal numbers are supported. operand c must match the second instruction type. selp Syntax Comparison and Selection Instructions: selp Select between source operands.ftz}. Subnormal numbers: sm_20: By default. b. Modifier .dtype = { . .f32 comparisons. and operand a is selected. slct Syntax Comparison and Selection Instructions: slct Select one source operand. a.type d. slct.dtype. b. . .s32 selp. a is stored in d.t. @q selp. z.b64.f32 d.f32 flushes subnormal values of operand c to sign-preserving zero. c. c. .u32. . val. Operands d. .f64 requires sm_13 or later. . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.r.dtype.f64 requires sm_13 or later.f32 comparisons. If c ≥ 0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Operands d.b32.Chapter 8.s32 x. If operand c is NaN. a.f32 r0. Semantics Floating Point Notes January 24.u64. selp. . y.ftz.u64.u16. Operand c is a predicate.x.xp. . B. .s16. .b16.f32.

0 8. xor. or. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. performing bit-wise operations on operands of any type.4. 2010 . Instructions and. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.7.PTX ISA Version 2. and not also operate on predicates. provided the operands are of the same size. This permits bit-wise operations on floating point values without having to define a union to access the bits.

and.fpvalue. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b16. Introduced in PTX ISA version 1. . or. Allowed types include predicate registers. .b32 and.b32.b16.q.b32 x. or Syntax Logic and Shift Instructions: or Bitwise OR. but not necessarily the type.q. a.type d. a. or. . Instruction Set Table 70. Introduced in PTX ISA version 1. and.r. b. b.r. .0x00010001 or. Allowed types include predicate registers. Table 71. . but not necessarily the type.b32. . Supported on all target architectures.pred. The size of the operands must match.b64 }.0x80000000. and Syntax Logic and Shift Instructions: and Bitwise AND.pred.0.0.b64 }. . d = a | b. . Supported on all target architectures. January 24. The size of the operands must match.Chapter 8. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type = { . 2010 105 .b32 mask mask.type = { .type d. d = a & b.pred p. sign.

Allowed types include predicate registers. d. The size of the operands must match. . not.type = { . Introduced in PTX ISA version 1.r.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.type d. Supported on all target architectures. d = (a==0) ? 1 : 0.b32.b32 d.a.b32. Introduced in PTX ISA version 1.0. . .mask.b16. b. not. xor.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.q.b32 xor. .b32 mask. a. . a. .type = { . d = a ^ b. cnot.b16.pred. The size of the operands must match. but not necessarily the type. . Table 73.pred.0x0001. d = ~a.pred p. . . The size of the operands must match. Supported on all target architectures.0.type = { . Table 74.b32. Introduced in PTX ISA version 1. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). cnot.b16 d. but not necessarily the type. . Allowed types include predicates. 2010 . xor.b16. not Syntax Logic and Shift Instructions: not Bitwise negation.PTX ISA Version 2.type d.type d. a. not. one’s complement.b64 }.0. .x. 106 January 24. Supported on all target architectures.q.0 Table 72. but not necessarily the type. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.

. shl. b. The b operand must be a 32-bit value.i. a. PTX ISA Notes Target ISA Notes Examples January 24.s32. b. Signed shifts fill with the sign bit.type = { .b16.type d.u16. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. regardless of the instruction type. Introduced in PTX ISA version 1. . .b16. d = a >> b.s16.1. .0.2. but not necessarily the type. but not necessarily the type.j.0. Supported on all target architectures.2. Shift amounts greater than the register width N are clamped to N.b32. shl. Supported on all target architectures. Shift amounts greater than the register width N are clamped to N.type d. .i. sign or zero fill on left. shl Syntax Logic and Shift Instructions: shl Shift bits left.b64 }. shr Syntax Logic and Shift Instructions: shr Shift bits right. regardless of the instruction type. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. .u64. shr. Introduced in PTX ISA version 1. unsigned and untyped shifts fill with 0.Chapter 8. i. . . Instruction Set Table 75.u32. a.s64 }.b32 q. . Bit-size types are included for symmetry with SHL. d = a << b. The sizes of the destination and first source operand must match. The sizes of the destination and first source operand must match. PTX ISA Notes Target ISA Notes Examples Table 76. zero-fill on right.b32.type = { . .a.a.s32 shr.u16 shr. The b operand must be a 32-bit value.b16 c.b64. . k. 2010 107 . shr. .

st.PTX ISA Version 2. or shared state spaces. ld. 2010 . suld. and from state space to state space. local. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.5. possibly converting it from one format to another. prefetchu isspacep cvta cvt 108 January 24. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.0 8. Data Movement and Conversion Instructions These instructions copy data from place to place. The cvta instruction converts addresses between generic and global. Instructions ld. and sust support optional cache operations. ldu. and st operate on both scalar and vector types.7. mov.

The default load instruction cache operation is ld. Table 77.lu load last use operation.cg to cache loads only globally.cs Cache streaming. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.1. January 24. any existing cache lines that match the requested address in L1 will be evicted. Instruction Set 8.lu Last use. The ld. Use ld. The ld. For sm_20 and later. and cache only in the L2 cache. Operator .cv Cache as volatile (consider cached system memory lines stale. evict-first.ca.cg Cache at global level (cache in L2 and below.7.lu operation. The cache operators require a target architecture of sm_20 or later. the cache operators have the following definitions and behavior.ca. 2010 109 . but multiple L1 caches are not coherent for global data. and a second thread loads that address via a second L1 cache with ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Global data is coherent at the L2 level. likely to be accessed once.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.0 introduces optional cache operators on load and store instructions. the second thread may get stale L1 cache data. Cache Operators PTX 2.Chapter 8. . likely to be accessed again.cs) on global addresses. when applied to a local address.cv to a frame buffer DRAM address is the same as ld. it performs the ld. The ld. As a result of this request. fetch again).cs. A ld. to allow the thread program to poll a SysMem location written by the CPU. bypassing the L1 cache. . The driver must invalidate global L1 cache lines between dependent grids of parallel threads. invalidates (discards) the local L1 line following the load.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. not L1).cs is applied to a Local window address. When ld. If one thread stores to global memory via one L1 cache. . if the line is fully covered.ca loads cached in L1. The compiler / programmer may use ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.5. rather than the data stored by the first thread.lu instruction performs a load cached streaming operation (ld. . The ld.

Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wb. the second thread may get a hit on stale L1 cache data. rather than get the data from L2 or memory stored by the first thread.PTX ISA Version 2. The st. . bypassing the L1 cache. However. In sm_20. and marks local L1 lines evict-first. The default store instruction cache operation is st. not L1). likely to be accessed once. . in which case st. st. Future GPUs may have globally-coherent L1 caches.cs Cache streaming.cg to cache global store data only globally.wt. but st. .wt Cache write-through (to system memory).0 Table 78. 110 January 24.cg to local memory uses the L1 cache. Use st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. If one thread stores to global memory.ca loads. and a second thread in a different SM later loads from that address via a different L1 cache with ld. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. bypassing its L1 cache.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Operator .wb could write-back global store data from L1.wb for global data. which writes back cache lines of coherent cache levels with normal eviction policy. 2010 . regardless of the cache operation. Addresses not in System Memory use normal write-back. and discard any L1 lines that match.cg Cache at global level (cache in L2 and below. to allow a CPU program to poll a SysMem location written by the GPU with st. and cache only in the L2 cache.ca.cg is the same as st. Global stores bypass L1.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. The st.

mov. . label. addr. . a.. Introduced in PTX ISA version 1.1. ptr.Chapter 8.e. immediate. variable in an addressable memory space. and .type mov.b16. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. label.s16. // get address of variable // get address of label or function . alternately. d. Note that if the address of a device function parameter is moved to a register. The generic address of a variable in global. special register.f32 mov.global. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.type d..b32.s64.f32.u32 mov. i.u32 d. . d = sreg.pred.shared state spaces. . d = &avar.f64 requires sm_13 or later.a.b64.type mov.u16.u16 mov. Write register d with the value of a.u32 mov. .0. sreg.const. mov places the non-generic address of the variable (i. the parameter will be copied onto the stack and the address will be in the local state space. u.f32 mov. .type = { . mov.e.u32. ptr. . // address is non-generic. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. For variables declared in . the address of the variable in its state space) into the destination register. d = &label.local. . mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. local.f64 }.s32. the generic address of a variable declared in global. A[5]. Instruction Set Table 79. d. or shared state space. within the variable’s declared state space Notes Although only predicate and bit-size types are required.u64. Semantics d = a. avar. . . Take the non-generic address of a variable in global. A. Operand a may be a register.v. k. or shared state space may be taken directly using the cvta instruction. or function name. mov.type mov. . local.0. local. . 2010 111 . myFunc. d. Description .

z. mov.x. a.x | (a.x | (a. a[8. {lo.b32 %r1.w << 48) d = a. or write vector register d with the unpacked values from scalar register a.z. Description Write scalar register d with the packed value of vector register a.z << 16) | (a.g..15]. d.y << 8) | (a. .a}. mov.. d.z << 32) | (a.u32 x.31].{a.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1... d.15].z.x.b64 { d.b16.47].x. d. a[16. Semantics d = a. a[24.w}. // // // // a.7].b32 // pack two 16-bit elements into .type = { ..b32 // pack four 16-bit elements into ..y << 8) d = a.b16 // pack four 8-bit elements into .b64 mov. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b32 { d.b16 { d. a[32.w } = { a[0.y.b32.x.0. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.. a[48. {r.y } = { a[0. d.63] } // unpack 16-bit elements from .y << 16) d = a. a[32.15] } // unpack 8-bit elements from ..x | (a.. d.y. 2010 . Supported on all target architectures.b64 { d. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).0 Table 80.b64 112 January 24.31] } // unpack 8-bit elements from .y } = { a[0.y << 16) | (a. %r1.g. For bit-size types.7].b32 { d.hi are .w } = { a[0. lo.%r1..hi}.x | (a.y.u16 %x is a double.y << 32) // pack two 8-bit elements into .b64 // pack two 32-bit elements into .PTX ISA Version 2..b64 }. d. d. a[16.b8 r. %x. d.b32 mov..b}.y.b have type . a[16.u8 // unpack 32-bit elements from .type d.15].z.x | (a..{x.23].b32 mov..w have type .b. .a have type . a[8.x.y } = { a[0.31].31] } // unpack 16-bit elements from . .b.w << 24) d = a.

type d.b16.f16 data may be loaded using ld.cv }. . the resulting behavior is undefined. an address maps to the corresponding location in local or shared memory.ss}.type ld. Addresses are zero-extended to the specified width as needed. . [a]. *a.cop}.type .e.shared }. Within these windows. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.vec. Instruction Set Table 81. Generic addressing and cache operations introduced in PTX ISA 2. ld{.ss}{. ld introduced in PTX ISA version 1. . to enforce sequential consistency between threads accessing shared memory.s8.s32. perform the load using generic addressing. *(a+immOff).f64 using cvt.local. 2010 113 . [a]. .e.const.cop}.0. d.const space suffix may have an optional bank number to indicate constant banks other than bank zero. . . A destination register wider than the specified type may be used.cg.volatile.u32. PTX ISA Notes January 24.s64.u8. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .f32 or . .global. an integer or bit-size type register reg containing a byte address. Semantics d d d d = = = = a. and is zeroextended to the destination register width for unsigned and bit-size types. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.lu. d. . In generic addressing.b32. . and truncated if the register width exceeds the state space address width for the target architecture.v2.shared spaces to inhibit optimization of references to volatile memory.f32.volatile{. Generic addressing may be used with ld.f64 }. .global and . . .cop = { . The . *(immAddr).s16.reg state space. The value loaded is sign-extended to the destination register width for signed integers. d.0.u64. for example.volatile.b64.volatile introduced in PTX ISA version 1.ss}{. ld. This may be used.type ld{. . or [immAddr] an immediate absolute byte address (unsigned.b16.ss}. an address maps to global memory unless it falls within the local memory window or the shared memory window. 32-bit). Cache operations are not permitted with ld. .. . 32-bit).vec = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. ld.volatile{. .volatile may be used with .u16.type = { . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. If an address is not properly aligned.ca. The address must be naturally aligned to a multiple of the access size. i.v4 }. or the instruction may fault. Description Load register variable d from the location specified by the source address operand a in specified state space.vec. . [a].param. . . . [a]. i. . and then converted to . . .ss = { .b8.cs. If no state space is given.1.Chapter 8. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . . The address size may be either 32-bit or 64-bit.

%r.f32.f32 ld. // load .[a]. Generic addressing requires sm_20 or later.v4. 2010 . // immediate address %r.f16 d. x. // negative offset %r. ld.0 Target ISA Notes ld.global. %r.b32 ld.b64 ld.[fs].[p]. Cache operations require sm_20 or later.[p+4].const[4].const.global.b32 ld.local.s32 ld.b16 cvt. d.b32 ld.f64 requires sm_13 or later.PTX ISA Version 2.shared. Q.[p+-8].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. // access incomplete array x.local.[240].[buffer+64].

For ldu.v4. [areg] a register reg containing a byte address. In generic addressing. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Addresses are zero-extended to the specified width as needed. .ss}.s64.b64.s32. .type d.vec.type = { . ldu.ss}.[p+4]. . and then converted to . only generic addresses that map to global memory are legal.global }. .global. the access may proceed by silently masking off low-order address bits to achieve proper rounding.e. 32-bit).b8. i. A destination register wider than the specified type may be used. *(a+immOff). Instruction Set Table 82.f16 data may be loaded using ldu.u16. *(immAddr).f64 using cvt. . ldu. . [a]. // load from address // vec load from address . [a].reg state space.f32 d. ldu{. ldu. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.[a]. If no state space is given. or the instruction may fault. If an address is not properly aligned. or [immAddr] an immediate absolute byte address (unsigned. The addressable operand a is one of: [avar] the name of an addressable variable var.0. The data at the specified address must be read-only.s8. // state space . . perform the load using generic addressing. . i.u64. . The value loaded is sign-extended to the destination register width for signed integers.. where the address is guaranteed to be the same across all threads in the warp. an address maps to global memory unless it falls within the local memory window or the shared memory window. The address size may be either 32-bit or 64-bit.Chapter 8.e.v2. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.u32. .v4 }. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . .b32 d. the resulting behavior is undefined.b16.s16.f64 requires sm_13 or later. .u8.type ldu{. d. PTX ISA Notes Target ISA Notes Examples January 24. . Within these windows.b16.[p]. Introduced in PTX ISA version 2. . ldu. and truncated if the register width exceeds the state space address width for the target architecture.f32.f32 Q. 32-bit).b32. *a.global. The address must be naturally aligned to a multiple of the access size. an address maps to the corresponding location in local or shared memory.global. and is zeroextended to the destination register width for unsigned and bit-size types. .f64 }.ss = { .vec = { .f32 or . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. A register containing an address may be declared as a bit-size type or integer type. 2010 115 . Semantics d d d d = = = = a.

volatile{. . st{.s8.0 Table 83. .s32. The lower n bits corresponding to the instruction-type width are stored to memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b16.. an integer or bit-size type register reg containing a byte address. an address maps to the corresponding location in local or shared memory. b. A source register wider than the specified type may be used.volatile may be used with . perform the store using generic addressing. The address must be naturally aligned to a multiple of the access size.shared spaces to inhibit optimization of references to volatile memory. st. { .local.1. . *(immAddr) = a. st.volatile.0.f64 }. the resulting behavior is undefined. The address size may be either 32-bit or 64-bit. .e.s64. If an address is not properly aligned. 2010 .f16 data resulting from a cvt instruction may be stored using st. i.cg. .volatile introduced in PTX ISA version 1.vec . Generic addressing and cache operations introduced in PTX ISA 2.ss}. b. b. Cache operations are not permitted with st.ss}{. i. Semantics d = a.e.global.vec.cop}.ss . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . { . . .type st. .ss}. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . .b64.u8. 32-bit). . *(d+immOffset) = a.cop . The addressable operand a is one of: [var] [reg] the name of an addressable variable var.b8.wb.wt }.u64. or the instruction may fault. an address maps to global memory unless it falls within the local memory window or the shared memory window. 32-bit).global and . . . This may be used. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. [a]. Generic addressing may be used with st.reg state space.s16. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. to enforce sequential consistency between threads accessing shared memory. st.b16. Cache operations require sm_20 or later. Addresses are zero-extended to the specified width as needed.volatile.0.b32. Generic addressing requires sm_20 or later. or [immAddr] an immediate absolute byte address (unsigned.PTX ISA Version 2. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.type . .v4 }. Within these windows. In generic addressing. PTX ISA Notes Target ISA Notes 116 January 24.u32.v2.ss}{. st introduced in PTX ISA version 1. and truncated if the register width exceeds the state space address width for the target architecture.u16.type st{. . . [a].shared }. .vec. b.f64 requires sm_13 or later.f32. . If no state space is given.cs.type [a].volatile{.cop}. . . *d = a. for example. [a].type = = = = {. { .

local. Instruction Set Examples st.s32 st.Q.a.b32 st. [fs]. [p]. [q+-8]. // %r is 32-bit register // store lower 16 bits January 24.a.%r.s32 cvt.Chapter 8.local.b16 [a]. 2010 117 . [q+4].f32 st.global. // immediate address %r.b.f16. // negative offset [100].%r.b32 st.local.global.f32 st.r7.v4.

A prefetch to a shared memory location performs no operation. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.level = { .0 Table 84. 2010 . .global. prefetch. Within these windows. 32-bit). The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. 118 January 24. in specified state space. and truncated if the register width exceeds the state space address width for the target architecture.level prefetchu. i.0. If no state space is given. Addresses are zero-extended to the specified width as needed.L1 [ptr]. // prefetch to data cache // prefetch to uniform cache . or [immAddr] an immediate absolute byte address (unsigned.space}. an address maps to global memory unless it falls within the local memory window or the shared memory window.global. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. 32-bit). prefetch and prefetchu require sm_20 or later. the prefetch uses generic addressing.local }. prefetchu. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. The address size may be either 32-bit or 64-bit.e. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.L1. and no operation occurs if the address maps to a local or shared memory location.space = { .PTX ISA Version 2.L1 [a]. A prefetch into the uniform cache requires a generic address.L2 }. an address maps to the corresponding location in local or shared memory. prefetch{. In generic addressing. a register reg containing a byte address. [a].L1 [addr].

isshrd. Introduced in PTX ISA version 2. a. Description Convert a global. isspacep requires sm_20 or later. local. or shared address.u32 to truncate or zero-extend addresses.global.shared isglbl. The source address operand must be a register of type . The source and destination addresses must be the same size.u32.shared }. or shared address cvta. p. the generic address of the variable may be taken using cvta. For variables declared in global. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. A program may use isspacep to guard against such incorrect behavior.Chapter 8. local.shared.0. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. // local. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The destination register must be of type .u64 }.space p. When converting a generic address into a global.size = { . . .u64. 2010 119 .shared }. a.u32 p.size cvta. local. local. sptr. islcl. .size . svar. January 24.u64.u64 or cvt. cvta. // get generic address of svar cvta. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32 gptr. or shared state space.u32. // result is .u32 or . or shared address to a generic address.space. isspacep. cvta requires sm_20 or later. cvta.to. lptr.space.local isspacep. // convert to generic address // get generic address of var // convert generic address to global. .0.pred . or shared state space to generic.local.space = { .genptr. isspacep. . gptr.global isspacep.global. var. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.to.local.size p. PTX ISA Notes Target ISA Notes Examples Table 86. local. or vice-versa. p. . cvta. Instruction Set Table 85. or vice-versa.lptr.local. Use cvt.u32 p. a.global.space = { .pred. or shared state space. Take the generic address of a variable declared in global.space.

rmi round to nearest integer in direction of negative infinity .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. Integer rounding is illegal in all other instances.rni. For float-to-integer conversions. // integer rounding // fp rounding .f32.s16. .irnd}{.sat}.ftz. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. . .f32. subnormal inputs are flushed to signpreserving zero.s32. and for same-size float-tofloat conversions where the value is rounded to an integer.4 and earlier. . . the result is clamped to the destination range by default. d.u16.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. 2010 . Note that saturation applies to both signed and unsigned integer types.sat limits the result to MININT.f32 float-to-integer conversions and cvt.rmi. Integer rounding modifiers: . .sat}. The compiler will preserve this behavior for legacy PTX code.dtype. .f32 float-to-integer conversions and cvt.ftz}{. Saturation modifier: .sat For integer destination types. .PTX ISA Version 2.ftz..rzi round to nearest integer in the direction of zero .ftz modifier may be specified in these cases for clarity. d = convert(a).. For cvt. .dtype = . cvt{.rm.ftz.dtype.0 Table 87. i. subnormal inputs are flushed to signpreserving zero. . . 120 January 24.rni round to nearest integer.e.f64 }.rz.atype = { .s8. .rpi }.s64.e.irnd = { . The optional . a. i.rp }.atype d. sm_1x: For cvt.MAXINT for the size of the operation. . Integer rounding is required for float-to-integer conversions.u32.u64.dtype. .atype cvt{. subnormal numbers are supported. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.ftz}{. Description Semantics Integer Notes Convert between different types and sizes.sat is redundant. .f32 float-tofloat conversions with integer rounding. . . .rzi. . a. Note: In PTX ISA versions 1. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.f32 float-tofloat conversions with integer rounding.dtype. the . .u8.f32.frnd = { . choosing even integer if source is equidistant between two integers.frnd}{.f16.ftz. .rn.

f64 types. The operands must be of the same size. Floating-point rounding is illegal in all other instances.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.rm mantissa LSB rounds towards negative infinity . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32 x.s32. Subnormal numbers: sm_20: By default. cvt. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32. cvt.s32 f.f16. result is fp cvt.rni. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . 1.f64. subnormal numbers are supported. // note . if the PTX . The optional . NaN results are flushed to positive zero. and . Applies to .version is 1. Note: In PTX ISA versions 1.4 or earlier.f32.0]. .rn mantissa LSB rounds to nearest even .f64 j.r.0. The compiler will preserve this behavior for legacy PTX code. cvt. Saturation modifier: . Modifier . stored in floating-point format.f32 instructions.ftz modifier may be specified in these cases for clarity. and for integer-to-float conversions.f16.f32.f32. 2010 121 . and cvt.f32.f64 requires sm_13 or later.ftz behavior for sm_1x targets January 24.f16. // float-to-int saturates by default cvt.4 and earlier. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. // round to nearest int.Chapter 8. Specifically.0. . The result is an integral value. Floating-point rounding modifiers: .sat limits the result to the range [0. cvt to or from .f32 x.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero .sat For floating-point destination types.f32.y.f32.i. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.y.

. sampler. PTX has two modes of operation.param . Ability to query fields within texture.f32 {r1. sampler.height. r2. // get tex1’s txq. and surface descriptors: • • • Static initialization of texture. add. add. r5. and surface descriptors.PTX ISA Version 2. r1.0 8.samplerref tsamp1 = { addr_mode_0 filter_mode }.r2.6.entry compute_power ( . texture and sampler information is accessed through a single . . 122 January 24. and surfaces.f32 r3.f32 r1. but the number of samplers is greatly restricted to 16. samplers. Example: calculate an element’s power contribution as element’s power/total number of elements.f2}]. r3. Texturing modes For working with textures and samplers. add.texref handle.u32 r5. // get tex1’s tex.b32 r5. cvt. [tex1]. The advantage of unified mode is that it allows 128 samplers. r1. r5. } = clamp_to_border.global . with the restriction that they correspond 1-to-1 with the 128 possible textures. r1.target texmode_independent . the file is assumed to use unified mode.target options ‘texmode_unified’ and ‘texmode_independent’. [tex1.r4}. [tex1]. and surface descriptors. = nearest width height tsamp1. div.u32 r5.f32.texref tex1 ) { txq. r3. Texture and Surface Instructions This section describes PTX instructions for accessing textures. The texturing mode is selected using . If no texturing mode is declared..r3.7. In the unified mode. mul.2d. texture and sampler information each have their own handle. r5.b32 r6. In the independent mode. sampler. {f1.f32 r1. r6. .. PTX supports the following operations on texture. r4. The advantage of independent mode is that textures and samplers can be mixed and matched. and surface descriptors. sampler.width.v4.f32 r1. Module-scope and per-entry scope definitions of texture. allowing them to be defined separately and combined at the site of usage in the program. 2010 .f32. A PTX module may declare only one texturing mode.

[tex_a. and is a four-element vector for 3d textures.s32. If an address is not properly aligned.3d.btype tex. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.v4.r2. where the fourth element is ignored. // Example of independent mode texturing tex. [a.r2.btype = { . b.dtype. tex txq suld sust sured suq Table 88. c]. //Example of unified mode texturing tex.dtype. {f1}].s32. the sampler behavior is a property of the named texture..r4}. 2010 123 .f32 }. .v4 coordinate vectors are allowed for any geometry. // explicit sampler . the resulting behavior is undefined.3d }.1d.f4}]. Notes For compatibility with prior versions of PTX. c].e. . Operand c is a scalar or singleton tuple for 1d textures.0. The instruction always returns a four-element vector of 32-bit values. . [a. with the extra elements being ignored. or the instruction may fault. An optional texture sampler b may be specified.r3. the square brackets are not required and .v4.s32. i. .5.s32 {r1. Instruction Set These instructions provide access to texture and surface memory. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.r4}.v4.geom = { . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.1d.Chapter 8.f32 }. tex. d. Supported on all target architectures.f2. .f32 {r1.2d. .s32. [tex_a. the access may proceed by silently masking off low-order address bits to achieve proper rounding.btype d.geom.f3.r3. sampler_x. Unified mode texturing introduced in PTX ISA version 1. Description Texture lookup using a texture coordinate vector. If no sampler is specified.dtype = { .v4. PTX ISA Notes Target ISA Notes Examples January 24.u32. is a two-element vector for 2d textures.geom. . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. A texture base address is assumed to be aligned to a 16-byte address. {f1.

mirror. // unified mode // independent mode 124 January 24.b32 d.texref or .filter_mode.0 Table 89. d.b32 %r1. // texture attributes // sampler attributes .addr_mode_0. txq.tquery.height. txq. Operand a is a .samplerref variable.squery = { .5. In unified mode.height . clamp_ogl. [a]. [a]. addr_mode_1. . and in independent mode sampler attributes are accessed via a separate samplerref argument.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).tquery = { . Integer from enum { nearest. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures. . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. Query: .b32 %r1. txq. .PTX ISA Version 2.width. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. clamp_to_edge.normalized_coords .addr_mode_1 .filter_mode . sampler attributes are also accessed via a texref argument.width.addr_mode_0 . Description Query an attribute of a texture or sampler.filter_mode.normalized_coords }. linear } Integer from enum { wrap.depth . txq. [tex_A]. [smpl_B].width .squery. [tex_A]. .b32 %r1.depth.addr_mode_0. 2010 . .b32 txq. addr_mode_2 }.

f32. and is a four-element vector for 3d surfaces.s32. sm_1x targets support only the .b32.e. If the destination base type is .2d. [surf_A.z. or FLOAT data. A surface base address is assumed to be aligned to a 16-byte address.f32 is returned.dtype. is a two-element vector for 2d surfaces.b32. G.1d. suld Syntax Texture and Surface Instructions: suld Load from surface memory. or the instruction may fault. the access may proceed by silently masking off low-order address bits to achieve proper rounding. suld. // unformatted d. b].trap. .u32.w}]. additional clamp modifiers.p. size and type conversion is performed as needed to convert from the surface sample format to the destination type. . Target ISA Notes Examples January 24.v2.b supported on all target architectures.s32. or .f32. then . [surf_B.cv }.zero }. . and the size of the data transfer matches the size of destination operand d.b64 }. If the destination type is . // cache operation none. or . . .b . Destination vector elements corresponding to components that do not appear in the surface format are not written. b]. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.y. // for suld. [a.u32 is returned. Operand a is a .cs. {x. if the surface format contains SINT data. . .u32.b. .p.f4}.Chapter 8.b16.s32. B. .0. Coordinate elements are of type . Instruction Set Table 90. and cache operations introduced in PTX ISA version 2.s32. suld. . 2010 125 .trap .s32 is returned. . if the surface format contains UINT data. where the fourth element is ignored. . suld. // for suld. The lowest dimension coordinate represents a sample offset rather than a byte offset. suld.clamp . suld.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.b performs an unformatted load of binary data.trap introduced in PTX ISA version 1.geom{. Cache operations require sm_20 or later. {x}]. . and A components of the surface format..f32 based on the surface format as follows: If the surface format contains UNORM. {f1.surfref variable.b.ca.1d. the resulting behavior is undefined.b32. .v4 }.trap suld. then . the surface sample elements are converted to . suld.v4. SNORM. .clamp .r2}.clamp field specifies how to handle out-of-bounds addresses: .5.v4. then . .p. // formatted . suld.dtype .f3.clamp suld. Description Load from surface memory using a surface coordinate vector.p requires sm_20 or later. suld.clamp.cg.trap {r1.p . .3d }.cop . Operand b is a scalar or singleton tuple for 1d surfaces.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. [a.u32.3d requires sm_20 or later.p is currently unimplemented.vec.b. .trap clamping modifier.geom{. i.3d.dtype.clamp = = = = = = { { { { { { d.cop}.vec .b8 . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. .geom .v2.f32 }.b64. suld. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The . If an address is not properly aligned.dtype .f2.cop}.

. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. the resulting behavior is undefined. is a two-element vector for 2d surfaces. sust. . . .wb.u32 is assumed. Operand a is a .vec. or the instruction may fault.clamp .cop}.e.p Description Store to surface memory using a surface coordinate vector. if the surface format contains SINT data. [a. .clamp.ctype . A surface base address is assumed to be aligned to a 16-byte address. The . Source elements that do not occur in the surface sample are ignored. {r1. sust.p.r2}.3d requires sm_20 or later. .0 Table 91. b]. additional clamp modifiers. . and is a four-element vector for 3d surfaces. or .f32. [surf_B. sust.f32 }.wt }. size and type conversions are performed as needed between the surface sample format and the destination type. .clamp = = = = = = { { { { { { [a.b supported on all target architectures. then .s32. sust.s32.f3.clamp sust. The lowest dimension coordinate represents a sample offset rather than a byte offset.f32 is assumed. Surface sample components that do not occur in the source vector will be written with an unpredictable value.trap introduced in PTX ISA version 1.cop . c. sust. The source data is then converted from this type to the surface sample format.{u32. Coordinate elements are of type . {x}]. The source vector elements are interpreted left-to-right as R.cg. // unformatted // formatted .trap .z.b // for sust.geom .geom{. If the source base type is .b performs an unformatted store of binary data. .ctype. i.1d.b16.trap sust.p performs a formatted store of a vector of 32-bit data values to a surface sample. and A surface components. .p.clamp field specifies how to handle out-of-bounds addresses: . The size of the data transfer matches the size of source operand c. .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.v2.p.cs.trap. or FLOAT data.p requires sm_20 or later.v4 }.f32. {x.b64.0. . G.u32. Target ISA Notes Examples 126 January 24.ctype . and cache operations introduced in PTX ISA version 2.1d. .trap [surf_A. .b32. sm_1x targets support only the . . . Operand b is a scalar or singleton tuple for 1d surfaces.y. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp . .p.3d }.v2.b8 . . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. sust.b.vec. If an address is not properly aligned. These elements are written to the corresponding surface sample components.surfref variable.s32. SNORM. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32.b64 }. none. // for sust.s32 is assumed. sust Syntax Texture and Surface Instructions: sust Store to surface memory. b]. c.b. . . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.ctype.5. if the surface format contains UINT data.w}]. then .cop}.2d.f32} are currently unimplemented.PTX ISA Version 2. If the source type is . {f1. sust.3d. Cache operations require sm_20 or later.b. 2010 .vec . B.f4}. .geom{. then .b32.b32. where the fourth element is ignored. sust.trap clamping modifier.s32. sust.f2.v4.zero }.

or the instruction may fault. r1.ctype. Operations add applies to . Reduction to surface memory using a surface coordinate vector. Operand b is a scalar or singleton tuple for 1d surfaces.zero }. .u32.b]. // for sured.. sured. {x. . is a two-element vector for 2d surfaces.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .ctype = { . and the data is interpreted as . min and max apply to . .op.b32 type.3d }.clamp [a.max. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b].or }. [surf_B.b32 }.s32. . January 24.e.clamp [a.2d.p .b. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32 is assumed.geom = { . then .s32. if the surface format contains SINT data.clamp .trap .s32 or . Operand a is a . then . .u32.trap. i.u64.b. sured.trap sured.c. operations and and or apply to .and. .geom.u64.clamp field specifies how to handle out-of-bounds addresses: .p performs a reduction on sample-addressed 32-bit data. 2010 127 .clamp = { . .op = { .clamp. the access may proceed by silently masking off low-order address bits to achieve proper rounding.p. A surface base address is assumed to be aligned to a 16-byte address.u32 based on the surface sample format as follows: if the surface format contains UINT data. .b32 }.s32 is assumed.u32 and .surfref variable.s32 types.b performs an unformatted reduction on .2d.geom.u64 data. or . Coordinate elements are of type . // sample addressing .ctype = { . The instruction type is restricted to .1d. . . and .p. sured. where the fourth element is ignored. . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.b32.trap [surf_A.u32. . .ctype.min.op.u32.y}].s32. // byte addressing sured.c. the resulting behavior is undefined. The lowest dimension coordinate represents a sample offset rather than a byte offset. Instruction Set Table 92.s32 types. . sured requires sm_20 or later. {x}].add. The .b32. . and is a four-element vector for 3d surfaces. // for sured.0.1d. If an address is not properly aligned.min. sured.b . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.add.Chapter 8.b32. r1.

b32 d.PTX ISA Version 2.width. [a].5.width . 2010 . Supported on all target architectures.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.0 Table 93. .width. .surfref variable.query. Description Query an attribute of a surface. Query: . Operand a is a . suq.depth }.query = { . suq. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. . 128 January 24. [surf_A].height.height .b32 %r1.

@ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.a. Introduced in PTX ISA version 1.b. {} Syntax Description Control Flow Instructions: { } Instruction grouping. { add.x. ratio. 2010 129 .y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. @{!}p instruction. Execute an instruction or instruction block for threads that have the guard predicate true.0.y. { instructionList } The curly braces create a group of instructions. Supported on all target architectures.0.s32 a. p. mov.7. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. used primarily for defining a function body. If {!}p then instruction Introduced in PTX ISA version 1.f32 @!p div.c.0. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Instruction Set 8. Threads with a false guard predicate do nothing. Supported on all target architectures.eq.s32 d.Chapter 8.7. } PTX ISA Notes Target ISA Notes Examples Table 95. setp.f32 @q bra L23.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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{!}c.. All threads in the warp are stalled until the barrier completes. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. and d have type .red.popc. and the barrier is reinitialized so that it can be immediately reused. thread count. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.popc).or indicate if all the threads had a true predicate or if any of the threads had a true predicate. execute a bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Operands a. . bar. The result of .red performs a predicate reduction across the threads participating in the barrier. all threads in the CTA participate in the barrier.u32.15. Only bar.arrive does not cause any waiting by the executing threads.red} introduced in PTX .sync with an immediate barrier number is supported for sm_1x targets. bar. b}.u32 bar.sync and bar. Operand b specifies the number of threads participating in the barrier. the waiting threads are restarted without delay. the optional thread count must be a multiple of the warp size.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. the final value is written to the destination register in all threads waiting at the barrier.or }.red} require sm_20 or later.op.sync or bar. If no thread count is specified. In addition to signaling its arrival at the barrier. and bar. Register operands. Instruction Set Table 100.Chapter 8.red instruction. Barriers are executed on a per-warp basis as if all the threads in a warp are active. The barrier instructions signal the arrival of the executing threads at the named barrier.op = { . PTX ISA Notes Target ISA Notes Examples bar. The reduction operations for bar.red are population-count (. Note that a non-zero thread count is required for bar. all-threads-true (. bar. {!}c.sync or bar.arrive.red.sync bar.{arrive.0. In conditionally executed code.sync 0. threads within a CTA that wish to communicate via memory can store to memory. a.red performs a reduction operation across threads. the bar. bar. and any-thread-true (. d. while .version 2. 2010 133 . bar. a{. b.sync) until the barrier count is met.sync and bar. Thus. bar. it is as if all the threads in the warp have executed the bar instruction. Register operands.arrive using the same active barrier. Execution in this case is unpredictable. b}.pred . bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. January 24.0. it simply marks a thread's arrival at the barrier.and and . When a barrier completes.cta. bar. Description Performs barrier synchronization and communication within a CTA. Once the barrier count is reached. and then safely read values stored by other threads prior to the barrier. operands p and c are predicates. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. b.popc is the number of threads with a true predicate.arrive a{.sync without a thread count introduced in PTX ISA 1. Each CTA instance has sixteen barriers numbered 0.and. and bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).and). p. thread count. bar. a{. Thus.red also guarantee memory ordering among threads identical to membar. b}. if any thread in a warp executes a bar instruction. Since barriers are executed on a per-warp basis.red should not be intermixed with bar.red delays the executing threads (similar to bar.{arrive.or).

red or atom) has been performed when the value written has become visible to other clients at the specified level. .{cta.4.version 1. membar. level describes the scope of other clients for which membar is an ordering event. membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. membar. A memory read (e. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.cta. .gl} supported on all target architectures. that is. For communication between threads in different CTAs or even different SMs. membar.gl.cta. .sys will typically have much longer latency than membar. by st.cta Waits until all prior memory writes are visible to other threads in the same CTA.level.gl} introduced in PTX . or system memory level. this is the appropriate level of membar.level = { .gl.sys Waits until all prior memory requests have been performed with respect to all clients.0.gl will typically have a longer latency than membar. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. and memory reads by this thread can no longer be affected by other thread writes.sys introduced in PTX .sys. PTX ISA Notes Target ISA Notes Examples membar.sys }. membar. global.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.g.version 2. A memory write (e. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar. membar. 2010 . Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. including thoses communicating via PCI-E such as system and peer-to-peer memory. membar. membar.cta. membar.g.0 Table 101.{cta. membar. membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. 134 January 24.PTX ISA Version 2.gl. when the previous value can no longer be read.sys requires sm_20 or later.

u32 only .s32. . A register containing an address may be declared as a bit-size type or integer type. overwriting the original value. min.min. . xor. For atom.space}.b32.global. .f32 }. e.op.b64 . Operand a specifies a location in the specified state space. [a]. ..inc.. . . The inc and dec operations return a result in the range [0. . The integer operations are add. c. min. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . Addresses are zero-extended to the specified width as needed. cas (compare-and-swap). max.u64. perform the memory accesses using generic addressing. the resulting behavior is undefined.s32. The bit-size operations are and.space = { .type d.b32. The address must be naturally aligned to a multiple of the access size. and exch (exchange). . and max.cas.u64 . The floating-point operations are add. 2010 135 . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.and. and truncated if the register width exceeds the state space address width for the target architecture.space}.type atom{. or the instruction may fault.b]. and max operations are single-precision. b. .exch to store to locations accessed by other atomic operations.b32 only . If no state space is given. atom.type = { . b.f32 Atomically loads the original value at location a into destination register d. dec. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.g.shared }. or. .exch. an address maps to the corresponding location in local or shared memory. Within these windows. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. an address maps to global memory unless it falls within the local memory window or the shared memory window.e. . . .u32. . In generic addressing.max }. .op. The address size may be either 32-bit or 64-bit.dec. accesses to local memory are illegal. Description // // // // // .b64.s32. Instruction Set Table 102.xor.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.op = { .add.u32. The floating-point add. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. and stores the result of the specified operation at location a.or. min.f32. or by using atom.add.e. If an address is not properly aligned. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. i. . 32-bit operations. . . . performs a reduction operation with operand b and the value in location a. . i.u32. . atom{. a de-referenced register areg containing a byte address.Chapter 8. inc. by inserting barriers between normal stores and atomic operations to a common address. d. January 24. [a]. or [immAddr] an immediate absolute byte address.

: r-1. d. Use of generic addressing requires sm_20 or later. : r. s) = s. : r+1. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. Release Notes Examples @p 136 January 24.max.cas. atom. cas(r.[a]. atom. *a = (operation == cas) ? : } where inc(r. atom. s) = (r > s) ? s exch(r. b).add.0 Semantics atomic { d = *a. b.f32 requires sm_20 or later.global. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. atom.1.cas.PTX ISA Version 2.0. 64-bit atom.[x+4].my_new_val.[p].max} are unimplemented. 64-bit atom. 2010 .s. atom.shared operations require sm_20 or later. c) operation(*a.f32 atom.global requires sm_11 or later. d.my_val. Introduced in PTX ISA version 1.global.0. s) = (r >= s) ? 0 dec(r.b32 d.shared requires sm_12 or later.add.{add.f32.t) = (r == s) ? t operation(*a.shared.{min.exch} requires sm_12 or later.s32 atom.

u32. dec(r.u32.add. s) = (r >= s) ? 0 : r+1. e. The integer operations are add. .or.b64. and max. . a de-referenced register areg containing a byte address.dec.f32. . red{.max }. . Within these windows.type = { .space = { . . If no state space is given. . the resulting behavior is undefined. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. .b32.exch to store to locations accessed by other reduction operations. or [immAddr] an immediate absolute byte address. . i. an address maps to global memory unless it falls within the local memory window or the shared memory window. January 24. min. The address must be naturally aligned to a multiple of the access size.op. Semantics *a = operation(*a.b32 only . . 32-bit operations. The address size may be either 32-bit or 64-bit.s32.Chapter 8. . and truncated if the register width exceeds the state space address width for the target architecture.xor. and stores the result of the specified operation at location a. Instruction Set Table 103. min. b).inc. The bit-size operations are and.op = { .f32 Performs a reduction operation with operand b and the value in location a. or. In generic addressing. where inc(r. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. If an address is not properly aligned. accesses to local memory are illegal.shared }. The floating-point operations are add. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u64 . Operand a specifies a location in the specified state space.u32 only . .add. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.g. . . 2010 137 .u64. Description // // // // . . A register containing an address may be declared as a bit-size type or integer type. . overwriting the original value.s32. or by using atom. an address maps to the corresponding location in local or shared memory. b. by inserting barriers between normal stores and reduction operations to a common address.type [a]. or the instruction may fault. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s32. inc.global.e. . Addresses are zero-extended to the specified width as needed.b]. . . For red. ..e. dec. and xor.space}.u32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. perform the memory accesses using generic addressing. s) = (r > s) ? s : r-1. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. Notes Operand a must reside in either the global or shared state space. . red. i. The inc and dec operations return a result in the range [0.min. min. .f32 }. and max operations are single-precision. The floating-point add. max.and.. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.

shared requires sm_12 or later. Release Notes Examples @p 138 January 24.f32 requires sm_20 or later.f32.add requires sm_12 or later. 2010 .0. red. red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.{min. red.global.add.max.f32 red. red.1.s32 red.global requires sm_11 or later red.global.max} are unimplemented. 64-bit red. [x+4].my_val.b32 [a].2.add. Use of generic addressing requires sm_20 or later. [p].and. 64-bit red.PTX ISA Version 2.shared operations require sm_20 or later.shared.

any True if source predicate is True for some active thread in warp. .2. Negate the source predicate to compute .q.none. p.mode. // ‘ballot’ form.any. r1.p.ballot.mode = { . returns bitmask .uni.pred d. vote. // get ‘ballot’ across warp January 24. vote.Chapter 8.not_all. vote. vote.pred vote.all. The destination predicate value is the same across all threads in the warp.b32 d. . Note that vote applies to threads in a single warp.all True if source predicate is True for all active threads in warp. .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. 2010 139 . vote.ballot.all. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.uni }. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. {!}a.b32 p. The reduction modes are: .ballot. {!}a.q. vote requires sm_12 or later.ballot.b32 requires sm_20 or later. In the ‘ballot’ form. Instruction Set Table 104.uni True if source predicate has the same value in all active threads in warp. .pred vote. not across an entire CTA. Negating the source predicate also computes . Description Performs a reduction of the source predicate across threads in a warp.uni. Negate the source predicate to compute . where the bit position corresponds to the thread’s lane id.

or word values from its source operands. a{. c.btype{. c. b{.sat} d. 2010 . with optional data merge vop. perform a scalar arithmetic operation to produce a signed 34-bit result. . Using the atype/btype and asel/bsel specifiers.PTX ISA Version 2.7. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. 3. half-word. the input values are extracted and signor zero. . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.atype. with optional secondary operation vop.extended internally to . vop. . atype.u32 or . Video Instructions All video instructions operate on 32-bit register operands.9. b{. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. The source and destination operands are all 32-bit registers.asel = .s32 }.h1 }. . . .dtype.u32.secop = { . optionally clamp the result to the range of the destination type. .bsel = { . // 32-bit scalar operation.bsel}.bsel}.sat}. a{. 2. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).asel}.s32) is specified in the instruction type.b2. to produce signed 33-bit input values.asel}.dtype.h0.btype = { .atype. extract and sign. .dtype = . all combinations of dtype.secop d. 140 January 24. .atype.dtype.b1.s34 intermediate result.or zero-extend byte.s33 values. The type of each operand (.atype = . The general format of video instructions is as follows: // 32-bit scalar operation. a{. The primary operation is then performed to produce an . 4.btype{.btype{. taking into account the subword destination size in the case of optional data merging. .asel}. .bsel}.0 8.max }.dsel = .b0.min. b{.add. The sign of the intermediate result depends on dtype. and btype are valid.b3.sat} d.dsel.

b0.s33 optMerge( Modifier dsel. c).b2: return ((tmp & 0xff) << 16) case .Chapter 8. January 24. S16_MIN ). tmp.s34 tmp. c). Instruction Set .h0: return ((tmp & 0xffff) case . S32_MIN ).h1: return ((tmp & 0xffff) << 16) case . . c). S16_MAX. U16_MIN ). U16_MAX. The lower 32-bits are then written to the destination operand. . 2010 141 . tmp. U32_MIN ).s33 optSaturate( .b1: return ((tmp & 0xff) << 8) case .b1.b2. default: return tmp. as shown in the following pseudocode. The sign of the c operand is based on dtype.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. .s33 tmp. U8_MIN ).s33 optSecOp(Modifier secop. . U32_MAX. S32_MAX. Bool sign.s33 c ) switch ( dsel ) { case .b3: return ((tmp & 0xff) << 24) default: return tmp. . c). tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).min: return MIN(tmp.max return MAX(tmp. Modifier dsel ) { if ( !sat ) return tmp. S8_MIN ). . tmp.b0: return ((tmp & 0xff) case .s33 tmp.s33 c) { switch ( secop ) { . . c). . S8_MAX.b3: if ( sign ) return CLAMP( else return CLAMP( case . switch ( dsel ) { case . Bool sat. . } } . U8_MAX. tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. c).add: return tmp + c. .h0. . c).

tb ). vmin. r2. vabsdiff.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32.s32. vmax }. r1.dsel . tmp = ta – tb. vmax require sm_20 or later. . . c. // 32-bit scalar operation. .s32. c.sat}.vop .h0. . tmp. vadd.s32.b0. vabsdiff.b1. tb ). // extract byte/half-word/word and sign.b2.atype. with optional data merge vop.btype{.dtype. and optional secondary arithmetic operation or subword data merge. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. . r1. r2.atype. c ).u32.bsel = { . vop. vsub. sat.min. bsel ).add. tmp = | ta – tb |. Integer byte/half-word/word minimum / maximum.h1 }.atype.b3.sat} d.add r1. // 32-bit scalar operation.sat} d.sat vmin. a{. Video Instructions: vadd. r3. btype. vsub. r3. Semantics // saturate.asel}. .s32 }. tmp = MIN( ta.s32. b{.0. 2010 . a{.s32. tb = partSelectSignExtend( b. vadd.op2 Description = = = = { vadd.PTX ISA Version 2. .u32.dtype.asel}.max }. dsel ).bsel}.asel}.atype = . vmax Syntax Integer byte/half-word/word addition / subtraction. // optional merge with c operand 142 January 24.bsel}. vsub vabsdiff vmin. r3.b0. . b{.sat vabsdiff. c ).btype = { . c. r1. asel ). . r2. vsub. b{.0 Table 105.dtype .u32.btype{. a{. isSigned(dtype).sat vsub. with optional secondary operation vop. atype. tmp = MAX( ta.s32.b0.h0. r2.b2. vmin.s32. c. . r3.h1.btype{. vabsdiff. Perform scalar arithmetic operation with optional saturate. { .s32.h1. d = optSecondaryOp( op2.dtype.bsel}.op2 d.asel = .dsel.h0. taking into account destination type and merge operations tmp = optSaturate( tmp. vmin. // optional secondary operation d = optMerge( dsel.s32. . vmax vadd.sat. Integer byte/half-word/word absolute value of difference. tmp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

u32{. Signed shift fills with the sign bit. vshl.add.or zero-extend based on source operand type ta = partSelectSignExtend( a.b2.op2 Description = = = = = { vshl.u32 vshr. { .vop .u32.dtype. r1. vshl: Shift a left by unsigned amount in b with optional saturate.b0.clamp && tb > 32 ) tb = 32. January 24.dtype .h1 }.atype.bsel}. tb = partSelectSignExtend( b.sat}{. and optional secondary arithmetic operation or subword data merge. vshr Syntax Integer byte/half-word/word left / right shift.h1. c ). vop.Chapter 8. taking into account destination type and merge operations tmp = optSaturate( tmp.u32. vshr vshl. a{. isSigned(dtype). a{. tmp. .max }.dtype. // default is .wrap r1.asel}.asel}.asel}. Semantics // extract byte/half-word/word and sign.sat}{.dtype. . d = optSecondaryOp( op2. vshl.b1.clamp .s32. { . r2. c.bsel}. switch ( vop ) { case vshl: tmp = ta << tb.wrap ) tb = tb & 0x1f.bsel = { . .bsel}. Video Instructions: vshl.mode} d.wrap }.u32. if ( mode == . tmp. b{.mode}. if ( mode == .asel = .sat}{. and optional secondary arithmetic operation or subword data merge. } // saturate. c. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Left shift fills with zero. vshr }. bsel ).clamp. vshr: Shift a right by unsigned amount in b with optional saturate.0.u32.atype = { . with optional data merge vop. with optional secondary operation vop.min. b{. c ). a{. . . // 32-bit scalar operation. Instruction Set Table 106.s32 }. // optional secondary operation d = optMerge( dsel. unsigned shift fills with zero.atype. // 32-bit scalar operation. case vshr: tmp = ta >> tb.atype. 2010 143 . .dsel. dsel ). . .u32{. atype. .u32. . vshr require sm_20 or later. sat.dsel . r2.u32.mode . b{.b3. r3. .u32{. .h0. r3. asel ).mode} d.op2 d.

U32 // intermediate unsigned.dtype. internally this is represented as negation of the product (a*b). // 32-bit scalar operation vmad.shr15 }.S32 // intermediate signed.scale = { . . {-}a{. 144 January 24.b2. Description Calculate (a*b) + c.b1. vmad. {-}b{.0 Table 107.atype. .asel}.atype = .h1 }. . The source operands support optional negation with some restrictions.b0.asel = . final signed (S32 * U32) + S32 // intermediate signed.bsel}.sat}{. final signed (U32 * S32) + S32 // intermediate signed..bsel}.S32 // intermediate signed.btype. c. final signed The intermediate result is optionally scaled via right-shift.u32. 2010 . . final signed (S32 * U32) .po{. {-}c. Source operands may not be negated in .atype. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.sat}{. (a*b) is negated if and only if exactly one of a or b is negated.b3. a{. final signed -(S32 * U32) + S32 // intermediate signed. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.btype = { . Depending on the sign of the a and b operands.scale} d.PTX ISA Version 2.shr7. The final result is unsigned if the intermediate result is unsigned and c is not negated. and scaling.dtype. That is.po mode. “plus one” mode.asel}. final signed (S32 * S32) + S32 // intermediate signed. final signed -(S32 * S32) + S32 // intermediate signed.bsel = { . and the operand negates. Input c has the same sign as the intermediate result.po) computes (a*b) + c + 1. . and zero-extended otherwise.s32 }. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. with optional operand negates.btype{.dtype = . final unsigned -(U32 * U32) + S32 // intermediate signed. . The “plus one” mode (. otherwise. . b{.S32 // intermediate signed.h0. PTX allows negation of either (a*b) or c. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. the intermediate result is signed. Although PTX syntax allows separate negation of the a and b operands. final signed -(U32 * S32) + S32 // intermediate signed. this result is sign-extended if the final result is signed. final signed (U32 * U32) . final signed (S32 * S32) . . which is used in computing averages. . .scale} d. final signed (U32 * S32) .

u32. January 24. U32_MIN).h0. } else if ( a.Chapter 8. Instruction Set Semantics // extract byte/half-word/word and sign.h0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. U32_MAX. tmp[127:0] = ta * tb.negate ) { tmp = ~tmp. atype.sat ) { if (signedFinal) result = CLAMP(result.u32. r1. lsb = 1. r1. r3. asel ).negate) || c.u32. signedFinal = isSigned(atype) || isSigned(btype) || (a.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32. vmad. -r3. S32_MIN). vmad requires sm_20 or later.negate ) { c = ~c.0. lsb = 0.negate ^ b. tmp = tmp + c128 + lsb. switch( scale ) { case . r0. bsel ). tb = partSelectSignExtend( b. } if ( . 2010 145 .s32.negate ^ b.negate. S32_MAX. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).sat vmad.u32. case . btype. lsb = 1. else result = CLAMP(result.po ) { lsb = 1. r2. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else if ( c. if ( .shr7: result = (tmp >> 7) & 0xffffffffffffffff. r2.shr15 r0.

0. .u32.asel = . with optional secondary arithmetic operation or subword data merge.bsel}.h1. .max }.atype. asel ).op2 d. . c ).u32.u32. { .min. b{. 146 January 24. . tmp.b2. .asel}. c. The intermediate result of the comparison is always unsigned. . with optional data merge vset.0 Table 108.btype.bsel = { . c ).ne. // optional secondary operation d = optMerge( dsel. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.atype. c. a{. . 2010 . tmp = compare( ta. .or zero-extend based on source operand type ta = partSelectSignExtend( a.cmp d. vset. Compare input values using specified comparison. // 32-bit scalar operation.asel}.asel}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . a{. vset.b0. r2. r3.bsel}. r3. btype. . with optional secondary operation vset.ne r1. a{.bsel}. tb.h1 }.gt. { . cmp ) ? 1 : 0.u32.le. .cmp.b1. b{.s32.btype.dsel.atype . tb = partSelectSignExtend( b. bsel ). d = optSecondaryOp( op2.op2 Description = = = = . atype.lt vset. tmp.add.btype.dsel .btype = { . . r1.PTX ISA Version 2.eq. . r2. // 32-bit scalar operation. . Semantics // extract byte/half-word/word and sign. and therefore the c operand and final result are also unsigned.atype. b{.s32 }. .b3.h0.ge }.cmp . vset requires sm_20 or later.cmp d.lt.

Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. trap. Supported on all target architectures. brkpt Suspends execution Introduced in PTX ISA version 1.0. Table 111. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Examples Currently. pmevent a. brkpt. there are sixteen performance monitor events. January 24. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. trap. brkpt requires sm_11 or later.0.7. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Table 110.Chapter 8.10. Triggers one of a fixed number of performance monitor events. numbered 0 through 15. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. @p pmevent 1. brkpt. The relationship between events and counters is programmed via API calls from the host.4. Instruction Set 8. 2010 147 . pmevent 7. with index specified by immediate operand a. Introduced in PTX ISA version 1. Supported on all target architectures. trap Abort execution and generate an interrupt to the host CPU.

0 148 January 24.PTX ISA Version 2. 2010 .

%clock64 %pm0. …. read-only variables. %lanemask_ge. which are visible as special registers and accessed through mov or cvt instructions. Special Registers PTX includes a number of predefined. %lanemask_le. %lanemask_gt %clock.Chapter 9. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_lt. %pm3 January 24. 2010 149 .

y. Redefined as . Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.u32 %tid.x to %rh Target ISA Notes Examples // legacy PTX 1.y == %ntid.z == 0 in 1D CTAs.0.%tid. cvt.y * %ntid.x.0. It is guaranteed that: 0 <= %tid. The fourth element is unused and always returns zero. // move tid.u32 %r0. %tid.PTX ISA Version 2.0 Table 112.%tid. . mov.%h2.y 0 <= %tid.x code Target ISA Notes Examples 150 January 24.u32 %h2. // zero-extend tid.x.%tid. mov. Supported on all target architectures. Redefined as .u16 %rh. 2D.z. per-thread special register initialized with the thread identifier within the CTA. The %tid special register contains a 1D. mov. %ntid.u32 %r1.u32 type in PTX 2. // compute unified thread id for 2D CTA mov.%tid.z.u32 %r0.z < %ntid. or 3D vector to match the CTA shape.y < %ntid.sreg .x. Supported on all target architectures.x.x 0 <= %tid.x.v4 .z == 0 in 2D CTAs.u32.0. // CTA shape vector // CTA dimensions A predefined.y.%tid. . // legacy PTX 1. %tid component values range from 0 through %ntid–1 in each CTA dimension.sreg .v4 .u32 %tid. CTA dimensions are non-zero. 2010 .z. mad.x * %ntid. %ntid.sreg .z == 1 in 1D CTAs.u32 %ntid. read-only special register initialized with the number of thread ids in each CTA dimension.y. %tid.%r0. the %tid value in unused dimensions is 0.z PTX ISA Notes Introduced in PTX ISA version 1.u16 %r2.u32 type in PTX 2.z to %r2 Table 113.x. the fourth element is unused and always returns zero. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. Every thread in the CTA has a unique %tid. %ntid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x code accessing 16-bit component of %tid mov.x < %ntid. . Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. %ntid.v4.sreg .y == %tid. read-only.v4. The total number of threads in a CTA is (%ntid.%h1.u32 %h1.u16 %rh. . %tid. mov.0.u32 %ntid. // thread id vector // thread id components A predefined. PTX ISA Notes Introduced in PTX ISA version 1.%ntid. The number of threads in each dimension are specified by the predefined special register %ntid.%ntid. %tid.z).z == 1 in 2D CTAs.x.

u32 %r.3. %warpid. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. The warp identifier will be the same for all threads within a single warp. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.sreg . e.u32 %warpid.3. mov.u32 %nwarpid. %nwarpid requires sm_20 or later. Introduced in PTX ISA version 1. For this reason. Table 115. Note that %warpid is volatile and returns the location of a thread at the moment when read.0. read-only special register that returns the maximum number of warp identifiers.u32 %laneid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. mov. . . 2010 151 . Special Registers Table 114. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Supported on all target architectures. . but its value may change during execution. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. The lane identifier ranges from zero to WARP_SZ-1. January 24. read-only special register that returns the thread’s warp identifier. PTX ISA Notes Target ISA Notes Examples Table 116. A predefined. %nwarpid.sreg .u32 %r. A predefined.Chapter 9. %laneid. Introduced in PTX ISA version 1. read-only special register that returns the thread’s lane within the warp. Supported on all target architectures. Introduced in PTX ISA version 2.u32 %r. A predefined. due to rescheduling of threads following preemption. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.sreg . mov.g.

z. .sreg .0. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.y 0 <= %ctaid.y. read-only special register initialized with the number of CTAs in each grid dimension.sreg .%nctaid.0 Table 117.sreg .u32 mov.u32 mov. mov.%nctaid. The fourth element is unused and always returns zero.x. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.u32 type in PTX 2.x.y. Supported on all target architectures.z < %nctaid.y. %ctaid.u32 %nctaid.PTX ISA Version 2.u32 %ctaid. %rh.0. .{x.0. Supported on all target architectures.0. mov.z} < 65.u32 %ctaid. depending on the shape and rank of the CTA grid.%ctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. with each element having a value of at least 1.536 PTX ISA Notes Introduced in PTX ISA version 1.u32 %nctaid .y < %nctaid. %ctaid. // legacy PTX 1.%nctaid.x code Target ISA Notes Examples Table 118. It is guaranteed that: 1 <= %nctaid.%nctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.x code Target ISA Notes Examples 152 January 24. The %nctaid special register contains a 3D grid shape vector.y.u32 type in PTX 2.x.u16 %r0. read-only special register initialized with the CTA identifier within the CTA grid.v4 . // CTA id vector // CTA id components A predefined.u16 %r0. // legacy PTX 1.%ctaid. It is guaranteed that: 0 <= %ctaid.x 0 <= %ctaid. or 3D vector. The %ctaid special register contains a 1D.x. The fourth element is unused and always returns zero. %rh.sreg .z PTX ISA Notes Introduced in PTX ISA version 1.x < %nctaid. Each vector element value is >= 0 and < 65535. Redefined as .v4.v4. 2010 . 2D. Redefined as .x.z. . // Grid shape vector // Grid dimensions A predefined.v4 .

mov. %smid. A predefined. where each launch starts a grid-of-CTAs. . %nsmid. // initialized at grid launch A predefined. Special Registers Table 119. During execution.sreg . read-only special register initialized with the per-grid temporal grid identifier. . PTX ISA Notes Target ISA Notes Examples January 24. repeated launches of programs may occur. The SM identifier ranges from 0 to %nsmid-1. 2010 153 .g. PTX ISA Notes Target ISA Notes Examples Table 121. mov.0. Introduced in PTX ISA version 2.Chapter 9.sreg . %nsmid requires sm_20 or later. %gridid. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. due to rescheduling of threads following preemption.u32 %smid. Supported on all target architectures. The SM identifier numbering is not guaranteed to be contiguous.u32 %r. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. so %nsmid may be larger than the physical number of SMs in the device.0.u32 %r.sreg . e. Introduced in PTX ISA version 1. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. read-only special register that returns the maximum number of SM identifiers. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Introduced in PTX ISA version 1. A predefined.u32 %r.3. This variable provides the temporal grid launch number for this context. mov. .u32 %gridid. The SM identifier numbering is not guaranteed to be contiguous. but its value may change during execution. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Supported on all target architectures.u32 %nsmid. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Note that %smid is volatile and returns the location of a thread at the moment when read.

sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. .0 Table 122. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. .u32 %r. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.0. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. . Table 124.0. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.sreg . mov. 2010 . %lanemask_lt.u32 %r. A predefined. Table 123.0.u32 %lanemask_le. Introduced in PTX ISA version 2.sreg . Introduced in PTX ISA version 2. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined. mov. %lanemask_le requires sm_20 or later. Introduced in PTX ISA version 2. A predefined. 154 January 24. %lanemask_le. %lanemask_eq requires sm_20 or later. mov.u32 %lanemask_eq.u32 %r.PTX ISA Version 2. %lanemask_lt requires sm_20 or later. %lanemask_eq.u32 %lanemask_lt.

u32 %lanemask_ge. A predefined.0. Introduced in PTX ISA version 2. .u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. . mov.u32 %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge requires sm_20 or later.sreg .0. %lanemask_gt requires sm_20 or later. A predefined. mov. Introduced in PTX ISA version 2. %lanemask_gt. Table 126.u32 %r.Chapter 9. 2010 155 . Special Registers Table 125. %lanemask_ge. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg . January 24.

0. %pm2. Supported on all target architectures. mov. Introduced in PTX ISA version 1. %pm1.u64 %clock64. %pm3.u32 r1.u32 %clock. 156 January 24. %pm2. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Their behavior is currently undefined. . . ….sreg . Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. read-only 64-bit unsigned cycle counter. %pm3 %pm0.%clock64. The lower 32-bits of %clock64 are identical to %clock.sreg . mov. Introduced in PTX ISA version 1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.%pm0.3. %pm1. read-only 32-bit unsigned cycle counter. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm1. Supported on all target architectures. Table 128.PTX ISA Version 2.0. %clock64 requires sm_20 or later. %pm2.sreg . 2010 . Special registers %pm0.%clock.0 Table 127.u32 %pm0.u64 r1. Table 129. and %pm3 are unsigned 32-bit read-only performance monitor counters. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. mov. Introduced in PTX ISA version 2. Special Registers: %pm0.u32 r1. .

version directive. .4 January 24.minor // major.version 2.version 1. . Increments to the major number indicate incompatible changes to PTX. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version .1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. . and the target architecture for which the code was generated.Chapter 10.version directive.version directives are allowed provided they match the original . Supported on all target architectures. Each ptx file must begin with a .version Syntax Description Semantics PTX version number. minor are integers Specifies the PTX language version number.0. 2010 157 .version . PTX File Directives: . Directives 10. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0 .version major. Duplicate .target Table 130.

texref descriptor.red}.target directives can be used to change the set of target features allowed during parsing.target directive specifies a single target architecture. Introduced in PTX ISA version 1.global. Adds {atom. Texturing mode introduced in PTX ISA version 1.red}. sm_10. The following table summarizes the features in PTX that vary according to target architecture. texmode_independent.texmode_unified . Each PTX file must begin with a . Target sm_20 Description Baseline feature set for sm_20 architecture. Note that . PTX features are checked against the specified target architecture.5.texmode_independent texture and sampler information is bound together and accessed via a single . with only half being used by instructions converted from .target Syntax Architecture and Platform target.samplerref descriptors. 158 January 24. Requires map_f64_to_f32 if any . Supported on all target architectures.PTX ISA Version 2. but subsequent .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. A .version directive. generations of SM architectures follow an “onion layer” model.f64 instructions used.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. PTX File Directives: .f64 instructions used.red}. and an error is generated if an unsupported feature is used. including expanded rounding modifiers. where each generation adds new features and retains all features of previous generations.target .global. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Therefore. Disallows use of map_f64_to_f32. sm_12.texmode_unified) . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.0 Table 131. immediately followed by a . PTX code generated for a given target can be run on later generation devices. Description Specifies the set of features in the target architecture for which the current ptx code was generated.texref and . texmode_unified.f32. sm_13. texture and sampler information is referenced with independent . The texturing mode is specified for an entire module and cannot be changed within the module. Texturing mode: (default is . Adds double-precision support. Adds {atom. map_f64_to_f32 }. 64-bit {atom.f64 instructions used. Requires map_f64_to_f32 if any .0.f64 storage remains as 64-bits. Requires map_f64_to_f32 if any . A program with multiple . In general.f64 to . sm_11. brkpt instructions. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.shared. vote instructions. 2010 .target directive containing a target architecture and optional platform options.

target sm_13 // supports double-precision . 2010 159 . Directives Examples .target sm_10 // baseline target architecture .target sm_20.Chapter 10. texmode_independent January 24.

%ntid.param . .b32 x.b32 y. Supported on all target architectures. 2010 . PTX ISA Notes For PTX ISA version 1.param space memory and are listed within an optional parenthesized parameter list.b32 %r2. . At kernel launch. opaque .entry kernel-name ( param-list ) kernel-body .param .entry . ld. Parameters are passed via .b32 %r3. parameters. [z]. and . . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. For PTX ISA versions 1. .entry cta_fft . ld.2. parameter variables are declared in the kernel parameter list. the kernel dimensions and properties are established and made available via special registers. [y]. 160 January 24. ld.param.4 and later. .0 10.4.entry Syntax Description Kernel entry point and body.b32 z ) Target ISA Notes Examples [x]. parameter variables are declared in the kernel body.g.param instructions.reg . In addition to normal parameters. e.entry kernel-name kernel-body Defines a kernel entry point name. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Semantics Specify the entry point for a kernel program. and body for the kernel function. . Kernel and Function Directives: .5 and later. The shape and size of the CTA executing the kernel are available in special registers. store.PTX ISA Version 2.param { .b32 %r<99>.samplerref.0 through 1.func Table 132. etc. Parameters may be referenced by name within the kernel body and loaded into registers using ld.b32 %r1. These parameters can only be referenced by name within texture and surface load.texref. with optional parameters. and query instructions and cannot be accessed via ld. %nctaid.3. … } .entry filter ( .param. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.param.param instructions.entry .0 through 1.surfref variables may be passed as parameters.

implements an ABI with stack.func definition with no body provides a function prototype.b32 localVar. (val0. ret.reg . … use N. if any. there is no stack. Variadic functions are currently unimplemented. Parameters in register state space may be referenced directly within instructions in the function body.2 for a description of variadic functions.func (ret-param) fname (param-list) function-body Defines a function. mov.0. The parameter lists define locally-scoped variables in the function body. dbl. other code.f64 dbl) { . … Description // return value in fooval January 24. including input and return parameters and optional function body.param instructions in the body.x code.b32 rval) foo (. A . Supported on all target architectures.b32 rval.0 with target sm_20 supports at most one return value. 2010 161 .reg . The implementation of parameter passing is left to the optimizing translator.b32 N. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. which may use a combination of registers and stack locations to pass parameters. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. } … call (fooval).func fname (param-list) function-body . val1).Chapter 10.reg .func (. Directives Table 133. PTX 2. Parameter passing is call-by-value.param and st. .func .func Syntax Function definition. parameters must be in the register state space. Kernel and Function Directives: . . and recursion is illegal. Parameters in .param state space. and supports recursion. .param space are accessed using ld. Variadic functions are represented using ellipsis following the last fixed argument.result. PTX ISA 2.0 with target sm_20 allows parameters in the . Semantics The PTX syntax hides all details of the underlying calling convention and ABI.reg . foo.func fname function-body . Release Notes For PTX ISA version 1. Parameters must be base types in either the register or parameter state space.

PTX ISA Version 2.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. which pass information to the backend optimizing compiler.minnctapersm . Currently. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.maxntid.maxnreg. the . The directive passes a list of strings to the backend. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.maxntid directive specifies the maximum number of threads in a thread block (CTA). The .minnctapersm directives may be applied per-entry and must appear between an .3. A general . or as statements within a kernel or device function body. .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.pragma directives may appear at module (file) scope. The directives take precedence over any module-level constraints passed to the optimizing backend.pragma directive is supported for passing information to the PTX backend. registers) to increase total thread count and provide a greater opportunity to hide memory latency. These can be used. and .g. for example. PTX supports the following directives.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. the . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxnreg . Note that . 162 January 24.maxntid and . 2010 . and the . The interpretation of .pragma The .maxntid . at entry-scope.entry directive and its body. and the strings have no semantics within the PTX virtual machine model. to throttle the resource requirements (e.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).0 10. .maxnctapersm (deprecated) .

maxctapersm.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. ny. Performance-Tuning Directives: .maxntid . the backend may be able to compile to fewer registers. ny . Supported on all target architectures.entry foo . . . Performance-Tuning Directives: . Supported on all target architectures. This maximum is specified by giving the maximum extent of each dimention of the 1D.entry bar . The actual number of registers used may be less. Introduced in PTX ISA version 1. Directives Table 134. . . for example.maxntid nx . or 3D CTA.maxnreg . or the maximum number of registers may be further constrained by .Chapter 10.16.3. The maximum number of threads is the product of the maximum extent in each dimension. Exceeding any of these limits results in a runtime error or kernel launch failure. Introduced in PTX ISA version 1.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. 2D. 2010 163 .maxntid 256 .maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid nx.entry foo . nz Declare the maximum number of threads in the thread block (CTA). The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid 16.maxnreg n Declare the maximum number of registers per thread in a CTA.3. The compiler guarantees that this limit will not be exceeded.maxntid and .maxntid nx.

.0.maxntid to be specified as well.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid 256 .0 Table 136.maxntid and . Optimizations based on . The optimizing backend compiler uses .maxnctapersm. .0. Performance-Tuning Directives: .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. if the number of registers used by the backend is sufficiently lower than this bound.entry foo .minnctapersm .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Introduced in PTX ISA version 1.minnctapersm in PTX ISA version 2. For this reason.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm has been renamed to .entry foo .3. Deprecated in PTX ISA version 2. Supported on all target architectures. Introduced in PTX ISA version 2. However.maxntid to be specified as well. .maxnctapersm (deprecated) . Optimizations based on . . Supported on all target architectures.maxntid 256 .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Performance-Tuning Directives: .minnctapersm 4 { … } 164 January 24. additional CTAs may be mapped to a single multiprocessor. 2010 .PTX ISA Version 2.maxnctapersm generally need .0 as a replacement for .minnctapersm generally need .

or at statementlevel.Chapter 10. { … } January 24. Directives Table 138.pragma list-of-strings . Introduced in PTX ISA version 2.pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma Syntax Description Pass directives to PTX backend compiler. at entry-scope. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . or statement-level directives to the PTX backend compiler.pragma directive may occur at module-scope.entry foo . Pass module-scoped. entry-scoped. Performance-Tuning Directives: . Supported on all target architectures. The .pragma “nounroll”. .0. . The interpretation of . 2010 165 .pragma .pragma directive strings is implementation-specific and has no impact on PTX semantics.

section .0 but is supported for legacy PTX version 1.2.232-1] . replaced by .4byte 0x000006b5. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .4.debug_info .PTX ISA Version 2.section directive is new in PTX ISA verison 2. Introduced in PTX ISA version 1.. 0x00. 0x736d6172 . Table 139.section directive. 0x63613031. 2010 . 0x00.byte 0x2b.0 10. 0x5f736f63 .4byte 0x6e69616d. “”. Deprecated as of PTX 2. @@DWARF dwarf-string dwarf-string may have one of the . 0x00. @progbits . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .byte 0x00.264-1] . 0x6150736f.0 and replaces the @@DWARF syntax. 0x00. Supported on all target architectures.. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.byte byte-list // comma-separated hexadecimal byte values . 0x00. 0x02.4byte label .loc The . 0x00000364. 0x00 .x code.0.quad int64-list // comma-separated hexadecimal integers in range [0.4byte int32-list // comma-separated hexadecimal integers in range [0.debug_pubnames. The @@DWARF syntax is deprecated as of PTX version 2.4byte . 0x61395a5f.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x00 166 January 24. 0x00.section .file .

b64 int64-list // comma-separated list of integers in range [0.section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00.debug_pubnames { . 0x00. Directives Table 140.264-1] . 0x00 0x61395a5f. Source file information.0.b32 int32-list // comma-separated list of integers in range [0. Supported on all target architectures.section .b32 0x000006b5. 0x00.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Chapter 10. Supported on all target architectures. 0x00.loc line_number January 24.b32 .section Syntax PTX section definition. ..loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.232-1] ..section . Supported on all target architectures.b8 0x00.loc .255] .0. .b8 0x2b.file .b32 label .b8 byte-list // comma-separated list of integers in range [0. 0x00. 0x00. Debugging Directives: . Debugging Directives: . 0x736d6172 0x00 Table 141. Source file location. Debugging Directives: .. 0x5f736f63 0x6150736f. } 0x02.file filename Table 142.0. . .debug_info . .b32 0x6e69616d. 0x00000364. 0x63613031. replaces @@DWARF syntax. . 2010 167 . .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

Supported on all target architectures.0. Linking Directives .0 10.b32 foo. Linking Directives: .PTX ISA Version 2. Supported on all target architectures. . Linking Directives: .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern identifier Declares identifier to be defined externally.global .6. .0. // foo will be externally visible 168 January 24. 2010 .extern .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern .extern .b32 foo. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.visible .global . .visible . .visible Table 143. // foo is defined in another module Table 144.visible identifier Declares identifier to be externally visible.

4 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.1 CUDA 2.0 January 24. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 CUDA 1.2 PTX ISA 1.5 PTX ISA 2.3 driver r190 CUDA 3. 2010 169 .2 CUDA 2.1 PTX ISA 1.0 CUDA 2.0 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.Chapter 11. CUDA Release CUDA 1.3 PTX ISA 1.1 CUDA 2.0 driver r195 PTX ISA Version PTX ISA 1. The release history is as follows.0.

fma.1.f32 for sm_20 targets.ftz and .f32 and mad.f32 maps to fma.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. sub. The mad. The mad. Single.f32 instruction also supports . When code compiled for sm_1x is executed on sm_20 devices.1. The goal is to achieve IEEE 754 compliance wherever possible.0 for sm_20 targets.f32.PTX ISA Version 2. The .ftz modifier may be used to enforce backward compatibility with sm_1x. while maximizing backward compatibility with legacy PTX 1. The fma. Instructions testp and copysign have been added. The changes from PTX ISA 1. Floating-Point Extensions This section describes the floating-point changes in PTX 2. A single-precision fused multiply-add (fma) instruction has been added. and mul now support .x code and sm_1x targets.f32 require a rounding modifier for sm_20 targets. 2010 .rn. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rp rounding modifiers for sm_20 targets. These are indicated by the use of a rounding modifier and require sm_20.1.0 11. rcp.and double-precision div.f32 requires sm_20. and sqrt with IEEE 754 compliant rounding have been added.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. mad. Changes in Version 2. New Features 11. Single-precision add.1.sat modifiers. Both fma. • • • • • 170 January 24.1.1.0 11.rm and .

f32 have been implemented. has been added. prefetch.{and. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. has been added. brev.le. has been added. %clock64. prefetchu.b32.shared have been extended to handle 64-bit data types for sm_20 targets.red. ldu. Instructions prefetch and prefetchu have also been added.zero. 2010 171 .1.red.2.ballot. bfe and bfi.1. Instructions bar. atom. A “find leading non-sign bit” instruction. st. Release Notes 11.1. A new directive. A “bit reversal” instruction. Surface instructions support additional . membar.3. st. Video instructions (includes prmt) have been added. Instructions {atom. The bar instruction has been extended as follows: • • • A bar. Instructions {atom. and red now support generic addressing. . A “population count” instruction. clz. has been added.minnctapersm to better match its behavior and usage.pred have been added. January 24. A system-level membar instruction.1.sys. New instructions A “load uniform” instruction. vote. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added.or}.red}.lt. suld. Instruction cvta for converting global.clamp and .add.red}. local.clamp modifiers. bar now supports optional thread count and register operands. ldu. Bit field extract and insert instructions. Cache operations have been added to instructions ld. for prefetching to specified level of memory hierarchy. and shared addresses to generic address and vice-versa has been added. Instruction sust now supports formatted surface stores. e. %lanemask_{eq. 11. A “vote ballot” instruction.u32 and bar.gt} have been added. New special registers %nsmid. The . popc.Chapter 11. isspacep. cvta. and sust. Other new features Instructions ld. .arrive instruction has been added.maxnctapersm directive was deprecated and replaced with . bfind.ge.g. A “count leading zeros” instruction. has been added. has been added. have been added.popc.section.

single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. Formatted surface load is unimplemented. stack-based ABI is unimplemented.5. if .{min. 172 January 24.version is 1. See individual instruction descriptions for details. Instruction bra. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. cvt. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. call suld.5 and later.ftz for PTX ISA versions 1.0 11.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.ftz (and cvt for .red}. To maintain compatibility with legacy PTX code.1.PTX ISA Version 2.f32} atom. Support for variadic functions and alloca are unimplemented. 2010 . In PTX version 1.{u32.max} are not implemented.4 or earlier. the correct number is sixteen.p sust. has been fixed. 11.target sm_1x.2. Formatted surface store with . where . The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.p.f32.1.u32.4 and earlier. or . {atom.s32.s32. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. Semantic Changes and Clarifications The errata in cvt. The underlying.3.f32 type is unimplemented. .

pragma “nounroll”. . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.0. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.entry foo (…) . entry-function. . disables unrolling of0 the loop for which the current block is the loop header. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 173 . Ignored for sm_1x targets.pragma Strings This section describes the . disables unrolling for all loops in the entry function body. L1_end: … } // do not unroll this loop January 24. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. and statement levels. including loops preceding the . { … } // do not unroll any loop in this function .pragma. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. The “nounroll” pragma is allowed at module. L1_body: … L1_continue: bra L1_head.Appendix A.pragma “nounroll”.func bar (…) { … L1_head: . Table 145. Note that in order to have the desired effect at statement level.pragma “nounroll”.pragma strings defined by ptxas. … @p bra L1_end. Descriptions of . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Supported only for sm_20 targets.

0 174 January 24.PTX ISA Version 2. 2010 .

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