NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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......................... 6...... Types ...........................................4...... 43 Vectors as Operands ................................. 5.................1..................1.....2..........................7...........3. 5................. Abstracting the ABI .............. 5............................................................... 29 Local State Space .... and Variables ......1...... 25 Chapter 5............... 2010 ............. 5....................................... Arrays....................................................................................................................................... Types................................... 28 Special Register State Space .................. 39 Parameterized Variable Names .1.............. 5...........2...1...............4...............................................1................................ 33 Fundamental Types ......................................................... 5......................... 41 6...................... 5..................4..............................5.... 41 Source Operands.........................................2........................................ Operand Costs .......6............... 41 Using Addresses......................5..........2............. 32 Texture State Space (deprecated) ............................................................................6.................................5................................................. 43 6................... 6............................................ 39 5..................... 33 Restricted Use of Sub-Word Sizes ......... Function declarations and definitions ............................4. 27 5............................. 6...................................................................... and Surface Types .......................................1................................... 37 Array Declarations ......................................................... Chapter 6................... 5.......................... 30 Shared State Space. 43 Labels and Function Names as Operands ... 49 ii January 24...................6.........1................................................................................................................4.......3..........................5................................ 37 Variable Declarations ......................................4................................ and Vectors ............ 5........ 6...................1................... 6..........................................................1.....PTX ISA Version 2...................................................................................................................... 28 Constant State Space .....................3.............................. 38 Alignment .............1....... 34 Variables .................................... 41 Destination Operands .......... 38 Initializers .........................................4.........1.............................. Texture................ 32 5............4......................... State Spaces...................... 5........1...............................2........................... 33 5............... 6.............................. 49 7.................................................2..............4.........................................................4......... Operand Type Information ......................4.........4. Summary of Constant Expression Evaluation Rules ...............6.........................................3................................... Sampler..1.................................................2.....................................................3.... 6..................... 5................................................ State Spaces ....... 42 Addresses as Operands ........2................ 46 6...... 5.......................................4...1.......................2...4............0 4........................... 27 Register State Space .......................................... Instruction Operands........8.......................................................... 5.............. 29 Global State Space ........4..........................1..............5............ 6............................................. 6........ 5.................. Type Conversion.........5............................... 29 Parameter State Space ...................................................................... 37 Vectors .................. 5........................... 5.. 42 Arrays as Operands ................................ 47 Chapter 7.. 44 Scalar Conversions .................. 44 Rounding Modifiers ....................

..................... Changes in Version 2.............. 81 Comparison and Selection Instructions ............................ 8......................................................... 2010 iii ........................... 63 Integer Arithmetic Instructions ......2.....................2... Directives ..................................7.........5...............................................................7........................ 7..................................................... 8..6...........................................1. Divergence of Threads in Control Constructs .................7.......................... 8... 11............................. Special Registers ........... 122 Control Flow Instructions .........1...............4........................................... Instruction Set ................................................................................................... 11.................. 11.............................2................... 62 Machine-Specific Semantics of 16-bit Code ...........2................................... 62 Semantics ................ 129 Parallel Synchronization and Communication Instructions .......... 8. 157 10.......2..........................1.................... 8.....................................................................................9........................ 170 Semantic Changes and Clarifications ..................4.. 160 Performance-Tuning Directives ............................................................................ 172 Unimplemented Features Remaining .......... 10.....1.............. 10.....7........... PTX Version and Target Directives .7...... 162 Debugging Directives ..................1.......................................... 8.......6..................................... 52 Variadic functions ......7................................................ 166 Linking Directives .......... 8..... 10.................................. 8................................1......1.....................................3..........8............................................... 172 January 24.................7.................................................. 7....1.............3............................................................................................................................................... 8....................................... 55 PTX Instructions .................................................................... Chapter 9.............x ............................................ 56 Comparisons ......... 8.............................6............................7....... 59 Operand Size Exceeding Instruction-Type Size .................................... Type Information for Instructions and Operands .... 10...... 55 Predicated Execution ............ 140 Miscellaneous Instructions..................3................3....................... 8................................... 169 11.................... Changes from PTX 1.................................1........1...................... 8................................... 108 Texture and Surface Instructions ........................................... 53 Alloca ................... 100 Logic and Shift Instructions ............. 132 Video Instructions .....................0 ..1. 8........................ 63 Floating-Point Instructions ..................... Format and Semantics of Instruction Descriptions .......10... 55 8...............................................3.............6................................................ Instructions .............................................5...................................................... 8................................ 168 Chapter 11............3...............................7................................................. 60 8....................................1...................................4....1.. 58 8.7........................................................................ 149 Chapter 10...4........... 8....3.... 147 8..... 62 8.............................................. 170 New Features ........... 57 Manipulating Predicates .............................. 54 Chapter 8................................. 157 Specifying Kernel Entry Points and Functions ...................................................................7...2............................................................. 104 Data Movement and Conversion Instructions ......7..... 8........7................... Release Notes ....................................

PTX ISA Version 2....... 173 iv January 24.... Descriptions of .....0 Appendix A...................................... 2010 .......pragma Strings.......

.......... 2010 v ......... 65 Integer Arithmetic Instructions: addc ................................... Table 6......... Table 15...... Table 10........................... 27 Properties of State Spaces ...... 59 Relaxed Type-checking Rules for Source Operands ..................................................................................................................................... 64 Integer Arithmetic Instructions: add............................. 58 Type Checking Rules ................... 18 Reserved Instruction Keywords . PTX Directives ............................................................................................................................ 20 Operator Precedence ..... 46 Cost Estimates for Accessing State-Spaces .............................. Table 30........................ Table 2..................................... 46 Integer Rounding Modifiers .......................................................................................... 58 Floating-Point Comparison Operators Testing for NaN ................................................................... 35 Opaque Type Fields in Independent Texture Mode . 33 Opaque Type Fields in Unified Texture Mode ............. 57 Floating-Point Comparison Operators Accepting NaN ......... 19 Predefined Identifiers ................... 69 Integer Arithmetic Instructions: mad24 ...... 61 Integer Arithmetic Instructions: add .cc ........................................ 35 Convert Instruction Precision and Format ............. Table 19.................................. 23 Constant Expression Evaluation Rules ..... Table 8.................. 64 Integer Arithmetic Instructions: sub ........... Table 31................ Table 22...................................................... 57 Floating-Point Comparison Operators .............................................................................................................. Table 18................. Table 17............. Table 3........ 68 Integer Arithmetic Instructions: mul24 ............... 66 Integer Arithmetic Instructions: mul ............................ 47 Operators for Signed Integer......................................................................... Table 13...................................................................................................................................................................................cc ............................................. Table 12................................................ Table 11....... 65 Integer Arithmetic Instructions: sub.................. Table 4..... and Bit-Size Types ..List of Tables Table 1....... 70 Integer Arithmetic Instructions: sad ........................... 66 Integer Arithmetic Instructions: subc ................................................... 45 Floating-Point Rounding Modifiers .......................................................................... Unsigned Integer............. 25 State Spaces ................. Table 16.................. Table 5............ 67 Integer Arithmetic Instructions: mad .................................................... Table 20......... Table 32........... Table 23........................... Table 14............ Table 26........................................................................................................................... Table 7......................................................................... Table 24............ 71 January 24.... Table 27............................................................................................. Table 25...................................... 60 Relaxed Type-checking Rules for Destination Operands...... Table 21.............. 28 Fundamental Type Specifiers ........ Table 28...................................................................................... Table 9....................... Table 29...................................................

.......................... Table 56..................................................................................................... Table 34......................... Table 66............. 79 Summary of Floating-Point Instructions ................................................................................................ 71 Integer Arithmetic Instructions: rem ...... Table 65................................. Table 68..................... Table 38................................. 74 Integer Arithmetic Instructions: bfind ..................................................................................... Table 48... Table 58......... 91 Floating-Point Instructions: min ....... Table 62..................... 74 Integer Arithmetic Instructions: clz ................................................. 94 Floating-Point Instructions: rsqrt .............................. 103 Comparison and Selection Instructions: slct ....... Table 54............................................................................................................ Table 50..................................................................................................................... 84 Floating-Point Instructions: sub .... 87 Floating-Point Instructions: mad ..................................................... Table 45.............. Table 43. 72 Integer Arithmetic Instructions: min ................................................ 86 Floating-Point Instructions: fma ......................................................... 75 Integer Arithmetic Instructions: brev .. Table 46................................ 88 Floating-Point Instructions: div .......................... 77 Integer Arithmetic Instructions: bfi ......................................................... Table 47............................................ 102 Comparison and Selection Instructions: selp ..................................................... 95 Floating-Point Instructions: sin ............................ Table 69....... Table 55......... Table 51............................................................ Table 61............................................................................................................... Table 59............ 83 Floating-Point Instructions: add ...... 103 vi January 24............ 73 Integer Arithmetic Instructions: popc ... 73 Integer Arithmetic Instructions: max .................................................. 90 Floating-Point Instructions: abs .. 71 Integer Arithmetic Instructions: abs ................................................................................................................................................................................ 85 Floating-Point Instructions: mul ..................... Table 63....... Table 41........................................................................... Table 49.................... Table 37................................. 76 Integer Arithmetic Instructions: bfe ...................PTX ISA Version 2. Table 60............................... 83 Floating-Point Instructions: copysign ......... Table 35.............. 92 Floating-Point Instructions: rcp .................. Integer Arithmetic Instructions: div ................. 97 Floating-Point Instructions: lg2 ...................................................0 Table 33.... 82 Floating-Point Instructions: testp ........................... Table 52............................................ 92 Floating-Point Instructions: max ............................................................................................................................................................................................ Table 39.................... Table 53..... 78 Integer Arithmetic Instructions: prmt ................................. Table 67...................... 91 Floating-Point Instructions: neg ............ 98 Floating-Point Instructions: ex2 ............................................. 2010 .......... 99 Comparison and Selection Instructions: set ..................... Table 40... Table 64.......................................... 101 Comparison and Selection Instructions: setp ................................................................................ Table 36.......... Table 57................................................................ 72 Integer Arithmetic Instructions: neg ...................................... Table 44.................... Table 42................................. 93 Floating-Point Instructions: sqrt ...................................................... 96 Floating-Point Instructions: cos ................................................................

... Table 86.......... 128 Control Flow Instructions: { } .................................................................................................................... Table 96...................................................... Table 99..................................... vabsdiff......Table 70........................................................................ 106 Logic and Shift Instructions: cnot . 125 Texture and Surface Instructions: sust .. 109 Cache Operators for Memory Store Instructions ........................ 142 Video Instructions: vshl............................... 130 Control Flow Instructions: ret ................ 115 Data Movement and Conversion Instructions: st .................... Table 80........... Table 77............................................ Table 88.................................................................................................................. Table 91......... Table 71.................................. 105 Logic and Shift Instructions: or .......... 133 Parallel Synchronization and Communication Instructions: membar .......... 137 Parallel Synchronization and Communication Instructions: vote ....... 139 Video Instructions: vadd... 112 Data Movement and Conversion Instructions: ld .......... 113 Data Movement and Conversion Instructions: ldu ....................... 105 Logic and Shift Instructions: xor ....................................................................... Table 76... Table 97........................................................................ Logic and Shift Instructions: and ............................................... 116 Data Movement and Conversion Instructions: prefetch......................... Table 84. 130 Control Flow Instructions: call ................................. 2010 vii ............ 119 Data Movement and Conversion Instructions: cvt ............................. 131 Parallel Synchronization and Communication Instructions: bar ....................... vshr ......................... vsub........................................................... Table 87.. Table 72.......................... Table 93................................. vmax ..................................... Table 92..... Table 90.............................. 134 Parallel Synchronization and Communication Instructions: atom .......................................................... Table 103............................. Table 98...... Table 75.................... 127 Texture and Surface Instructions: suq ...................................................... 107 Logic and Shift Instructions: shr ......................... 111 Data Movement and Conversion Instructions: mov ........ Table 101. 131 Control Flow Instructions: exit ..................... 143 January 24................................................. 107 Cache Operators for Memory Load Instructions ..................................................................... 123 Texture and Surface Instructions: txq ........... Table 89.................... 106 Logic and Shift Instructions: shl .. Table 106........ Table 94.............................................................. Table 104. Table 79.......... 110 Data Movement and Conversion Instructions: mov .......... 106 Logic and Shift Instructions: not ..................... Table 78................. vmin.............................. 129 Control Flow Instructions: @ .................. 135 Parallel Synchronization and Communication Instructions: red ......... 124 Texture and Surface Instructions: suld ......................... 126 Texture and Surface Instructions: sured............. Table 81.... Table 85............................. 120 Texture and Surface Instructions: tex .... Table 102.............................................. prefetchu ........................................... Table 83.......................... Table 100... 118 Data Movement and Conversion Instructions: isspacep ...................................... Table 74............................ Table 73........... Table 105................................. 129 Control Flow Instructions: bra ............................... Table 82...................... Table 95........... 119 Data Movement and Conversion Instructions: cvta .......................................................................................................

.... 154 Special Registers: %lanemask_le ................................................................................ Table 129......maxnreg .. 168 viii January 24........ Table 116.........................PTX ISA Version 2......... 144 Video Instructions: vset......................................func .....maxntid ......................... 156 Special Registers: %clock64 .. %pm2................................. 167 Debugging Directives: ...entry..................................................................version.................................................................................... 146 Miscellaneous Instructions: trap ................ 165 Debugging Directives: @@DWARF ...... Table 115............................................................................ 164 Performance-Tuning Directives: ............................... 152 Special Registers: %nctaid ............................. 153 Special Registers: %nsmid ............ Table 108..... Video Instructions: vmad ............. 158 Kernel and Function Directives: ...0 Table 107... 152 Special Registers: %smid .... 151 Special Registers: %warpid .......................................................................................................... Table 126....................... 150 Special Registers: %laneid .. 160 Kernel and Function Directives: ....................................... Table 117.............................................. Table 120...................................... 167 Linking Directives: ................................... Table 138....... Table 141... Table 130................... Table 139... Table 135........................................................... Table 125..................... 163 Performance-Tuning Directives: .......................................................................... 151 Special Registers: %nwarpid .... Table 137.................................... 157 PTX File Directives: .pragma ................................... Table 142..................................extern..............................loc ......................................................... 161 Performance-Tuning Directives: ......... 153 Special Registers: %gridid .. 166 Debugging Directives: ..................................... Table 114.......................................... 155 Special Registers: %clock ........ Table 113............ Table 128.................................... Table 111....................... %pm3 .........................maxnctapersm (deprecated) ................. Table 121........................... 156 PTX File Directives: ...................... Table 143...................minnctapersm ................................. 156 Special Registers: %pm0....... 147 Miscellaneous Instructions: pmevent.................................. Table 122............... Table 123... 2010 ......... 154 Special Registers: %lanemask_ge ..... 150 Special Registers: %ntid ...................................... Table 109........ 167 Debugging Directives: ................................................................................... Table 134............................................................... 147 Miscellaneous Instructions: brkpt ................................................................................................. 154 Special Registers: %lanemask_lt .................... 155 Special Registers: %lanemask_gt .......................................................................................... Table 133.........target .............................................................. 151 Special Registers: %ctaid ..................................... Table 140........................ Table 136................................... Table 131........file .................................................................... Table 132....................... Table 124........................... Table 119................................................................................................................................... 164 Performance-Tuning Directives: ............................. %pm1.................... 153 Special Registers: %lanemask_eq ........................... 147 Special Registers: %tid .... 163 Performance-Tuning Directives: ............................................................................................................... Table 112................................ Table 118............................. Table 110.....section .............. Table 127.

...........................Table 144. 168 Pragma Strings: “nounroll” ......................visible...... Linking Directives: ......................... 173 January 24.. 2010 ix .............. Table 145..........................................................................

PTX ISA Version 2.0 x January 24. 2010 .

2010 1 . from general signal processing or physics simulation to computational finance or computational biology. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. and pattern recognition can map image blocks and pixels to parallel processing threads. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. stereo vision. video encoding and decoding. January 24. In fact. image and media processing applications such as post-processing of rendered images. 1. Because the same program is executed for each data element. the memory access latency can be hidden with calculations instead of big data caches. 1. In 3D rendering large sets of pixels and vertices are mapped to parallel threads.2. there is a lower requirement for sophisticated flow control. Data-parallel processing maps data elements to parallel processing threads.1. image scaling. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Introduction This document describes PTX. high-definition 3D graphics.Chapter 1. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. which are optimized for and translated to native target-architecture instructions. PTX programs are translated at install time to the target hardware instruction set. Similarly. PTX defines a virtual machine and ISA for general purpose parallel thread execution. and because it is executed on many data elements and has high arithmetic intensity. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. many-core processor with tremendous computational horsepower and very high memory bandwidth. multithreaded. PTX exposes the GPU as a data-parallel computing device. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). the programmable GPU has evolved into a highly parallel.

0 is a superset of PTX 1.x features are supported on the new sm_20 target. The mad. The changes from PTX ISA 1. surface. A single-precision fused multiply-add (fma) instruction has been added. addition of generic addressing to facilitate the use of general-purpose pointers.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. and architecture tests. When code compiled for sm_1x is executed on sm_20 devices.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Achieve performance in compiled applications comparable to native GPU performance.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. PTX ISA Version 2. reduction. PTX 2.3.0 are improved support for IEEE 754 floating-point operations.rp rounding modifiers for sm_20 targets. The fma. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. 1.1. fma.3.0 is in improved support for the IEEE 754 floating-point standard. A “flush-to-zero” (.f32 for sm_20 targets. Provide a machine-independent ISA for C/C++ and other compilers to target. The mad. Both fma. atomic.0 PTX ISA Version 2.f32. Legacy PTX 1.f32 require a rounding modifier for sm_20 targets. sub. Improved Floating-Point Support A main area of change in PTX 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. • • • 2 January 24. Provide a common source-level ISA for optimizing code generators and translators.f32 and mad.x code will continue to run on sm_1x targets as well. Facilitate hand-coding of libraries. Provide a code distribution ISA for application and middleware developers. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The main areas of change in PTX 2.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. which map PTX to specific target machines. mad. and mul now support .PTX ISA Version 2.f32 instruction also supports . and the introduction of many new instructions. memory.sat modifiers.ftz) modifier may be used to enforce backward compatibility with sm_1x.ftz and . and all PTX 1. 2010 . Single-precision add. performance kernels.f32 maps to fma. including integer. 1. Instructions marked with .x. Most of the new features require a sm_20 target. and video instructions.rn. barrier.rm and .f32 requires sm_20.

3. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Generic addressing unifies the global. so recursion is not yet supported. local. Generic Addressing Another major change is the addition of generic addressing. Surface instructions support additional clamp modifiers. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. and directives are introduced in PTX 2. and sqrt with IEEE 754 compliant rounding have been added. local. prefetchu.and double-precision div.3. Cache operations have been added to instructions ld. these changes bring PTX 2. and shared addresses to generic addresses. ldu. st. and red now support generic addressing. and sust. an address that is the same across all threads in a warp. stack-based ABI. and shared state spaces. Surface Instructions • • Instruction sust now supports formatted surface stores. and shared addresses to generic address and vice-versa has been added.Chapter 1. suld.0. i.3. Introduction • Single. stack layout. st. In PTX 2. for prefetching to specified level of memory hierarchy. special registers. New Instructions The following new instructions. isspacep. 2010 3 . • Taken as a whole. A new cvta instruction has been added to convert global.4. NOTE: The current version of PTX does not implement the underlying. local. atom. cvta.3.e. allowing memory instructions to access these spaces without needing to specify the state space. Instructions testp and copysign have been added. and Application Binary Interface (ABI). Instruction cvta for converting global. 1. e.0 closer to full compliance with the IEEE 754 standard. . prefetch.clamp and ..zero.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Support for an Application Binary Interface Rather than expose details of a particular calling convention.0. These are indicated by the use of a rounding modifier and require sm_20. Instructions prefetch and prefetchu have been added. and vice versa. 1. 1.2. PTX 2. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. January 24. rcp.g. instructions ld.

gt} have been added.sys. membar. 4 January 24.red.ballot.red. A new directive. %lanemask_{eq. Other Extensions • • • Video instructions (includes prmt) have been added.le. Instructions bar. bar now supports an optional thread count and register operands. Reduction.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.shared have been extended to handle 64-bit data types for sm_20 targets.or}. Instructions {atom. A bar.section.f32 have been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.popc.u32 and bar. Barrier Instructions • • A system-level membar instruction. has been added.b32.ge. New special registers %nsmid.add. vote.lt. has been added. and Vote Instructions • • • New atomic and reduction instructions {atom. bfi bit field extract and insert popc clz Atomic. %clock64.arrive instruction has been added.red}. 2010 .{and.pred have been added. A “vote ballot” instruction.PTX ISA Version 2.red}. .

Chapter 11 provides release notes for PTX Version 2. January 24.Chapter 1. Chapter 5 describes state spaces. Chapter 4 describes the basic syntax of the PTX language. Chapter 10 lists the assembly directives supported in PTX. and variable declarations. Chapter 3 gives an overview of the PTX virtual machine model. Introduction 1. Chapter 7 describes the function and call syntax. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.0.4. calling convention. types. Chapter 6 describes instruction operands. and PTX support for abstracting the Application Binary Interface (ABI). 2010 5 . Chapter 9 lists special registers. Chapter 8 describes the instruction set.

0 6 January 24. 2010 .PTX ISA Version 2.

is an array of threads that execute a kernel concurrently or in parallel.y.1. Threads within a CTA can communicate with each other.z) that specifies the thread’s position within a 1D.1. data-parallel. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. assign specific input and output positions. or 3D CTA. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. compute-intensive portions of applications running on the host are off-loaded onto the device. More precisely. and results across the threads of the CTA. To coordinate the communication of the threads within the CTA. tid. The vector ntid specifies the number of threads in each CTA dimension.x.z). Programming Model 2.x. The thread identifier is a three-element vector tid. Programs use a data parallel decomposition to partition inputs. Each CTA has a 1D. or CTA. compute addresses.2. and ntid.y. 2. It operates as a coprocessor to the main CPU. work. To that effect. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. (with elements tid. Cooperative thread arrays (CTAs) implement CUDA thread blocks.Chapter 2. 2. a portion of an application that is executed many times. or 3D shape specified by a three-element vector ntid (with elements ntid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. and select work to perform. 2010 7 . A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. January 24.2. and tid. Each CTA thread uses its thread identifier to determine its assigned role. 2D. A cooperative thread array. 2D. ntid. but independently on different data. or host: In other words. can be isolated into a kernel function that is executed on the GPU as many different threads. Each thread has a unique thread identifier within the CTA. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.

Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 2D .2. because threads in different CTAs cannot communicate and synchronize with each other. Each grid also has a unique temporal grid identifier (gridid). Some applications may be able to maximize performance with knowledge of the warp size. The host issues a succession of kernel invocations to the device. Multiple CTAs may execute concurrently and in parallel. such that the threads execute the same instructions at the same time. The warp size is a machine-dependent constant. %ntid. multiple-thread) fashion in groups called warps. read-only special registers %tid. 2010 . This comes at the expense of reduced thread communication and synchronization. WARP_SZ. %nctaid. Typically. a warp has 32 threads.2. and %gridid.0 Threads within a CTA execute in SIMT (single-instruction. or 3D shape specified by the parameter nctaid. so PTX includes a run-time immediate constant.PTX ISA Version 2. Threads may read and use these values through predefined. so that the total number of threads that can be launched in a single kernel invocation is very large. However. CTAs that execute the same kernel can be batched together into a grid of CTAs. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. depending on the platform. A warp is a maximal subset of threads from a single CTA. which may be used in any instruction where an immediate operand is allowed. Each grid of CTAs has a 1D. 8 January 24. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). or sequentially. %ctaid. 2. Threads within a warp are sequentially numbered.

0) Thread (0. 1) Thread (1. 1) Thread (0. 0) Thread (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (2. 0) Thread (1. 2) Thread (4. 1) Thread (0. Figure 1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) CTA (1. 0) CTA (0. 2) Thread (1. 0) Thread (4. 2) Thread (3. 1) Thread (4. 2010 9 . 1) CTA (2. 0) Thread (3.Chapter 2. Thread Batching January 24. 1) Thread (3. 1) Thread (2. 0) CTA (2. A grid is a set of CTAs that execute independently. 0) CTA (1.

as well as data filtering. all threads have access to the same global memory. The global. and texture memory spaces are optimized for different memory usages.0 2. Texture memory also offers different addressing modes. Each thread has a private local memory. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2.3. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. respectively. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. and texture memory spaces are persistent across kernel launches by the same application. for more efficient transfer. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. constant.PTX ISA Version 2. The device memory may be mapped and read or written by the host. 10 January 24. for some specific data formats. referred to as host memory and device memory. 2010 . Both the host and the device maintain their own local memory. constant. Finally. The global. or.

0) Block (2. 0) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Block (1. 0) Block (0. 2010 11 . 1) Block (1. Memory Hierarchy January 24.Chapter 2. 0) Block (0. 0) Block (1. 1) Block (1. 2) Figure 2. 1) Block (2. 1) Grid 1 Global memory Block (0. 1) Block (0.

0 12 January 24.PTX ISA Version 2. 2010 .

so full efficiency is realized when all threads of a warp agree on their execution path. The multiprocessor SIMT unit creates. (This term originates from weaving. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. and executes concurrent threads in hardware with zero scheduling overhead. and on-chip shared memory. the first parallel thread technology. As thread blocks terminate. and executes threads in groups of parallel threads called warps. disabling threads that are not on that path. At every instruction issue time.1. manages. schedules. If threads of a warp diverge via a data-dependent conditional branch. manages. and each scalar thread executes independently with its own instruction address and register state. new blocks are launched on the vacated multiprocessors. different warps execute independently regardless of whether they are executing common or disjointed code paths. each warp contains threads of consecutive. increasing thread IDs with the first warp containing thread 0. 2010 13 . multiple-thread). The threads of a thread block execute concurrently on one multiprocessor. Parallel Thread Execution Machine Model 3. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. the threads converge back to the same execution path. When a host program invokes a kernel grid. and when all paths complete. To manage hundreds of threads running several different programs. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. allowing. It implements a single-instruction barrier synchronization. a cell in a grid-based computation). January 24. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. The multiprocessor creates. The way a block is split into warps is always the same. the multiprocessor employs a new architecture we call SIMT (single-instruction. A warp executes one common instruction at a time. Branch divergence occurs only within a warp. for example. the warp serially executes each branch path taken. The multiprocessor maps each thread to one scalar processor core. a multithreaded instruction unit. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). A multiprocessor consists of multiple Scalar Processor (SP) cores. a voxel in a volume. it splits them into warps that get scheduled by the SIMT unit.Chapter 3. When a multiprocessor is given one or more thread blocks to execute.

A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. If an atomic instruction executed by a warp reads. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. which is a read-only region of device memory. modify. but the order in which they occur is undefined. the programmer can essentially ignore the SIMT behavior. • The local and global memory spaces are read-write regions of device memory and are not cached. require the software to coalesce loads into vectors and manage divergence manually. which is a read-only region of device memory. A key difference is that SIMD vector organizations expose the SIMD width to the software. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. but one of the writes is guaranteed to succeed. scalar threads. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. As illustrated by Figure 3. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. 14 January 24. whereas SIMT instructions specify the execution and branching behavior of a single thread. however. as well as data-parallel code for coordinated threads.0 SIMT architecture is akin to SIMD (Single Instruction. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance.PTX ISA Version 2. the kernel will fail to launch. In contrast with SIMD vector machines. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. the number of serialized writes that occur to that location and the order in which they occur is undefined. Vector architectures. In practice. A multiprocessor can execute as many as eight thread blocks concurrently. 2010 . For the purposes of correctness. modifies. each read. on the other hand. If there are not enough registers or shared memory available per multiprocessor to process at least one block. SIMT enables programmers to write thread-level parallel code for independent. and writes to the same location in global memory for more than one of the threads of the warp. write to that location occurs and they are all serialized.

2010 15 . Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Figure 3.Chapter 3.

PTX ISA Version 2. 2010 .0 16 January 24.

All whitespace characters are equivalent. #ifdef. Source Format Source files are ASCII text. Lines beginning with # are preprocessor directives. See Section 9 for a more information on these directives. 4. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #if. Syntax PTX programs are a collection of text source files. 2010 17 .1. Comments in PTX are treated as whitespace.target directive specifying the target architecture assumed. Lines are separated by the newline character (‘\n’).version directive specifying the PTX language version. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Each PTX file must begin with a . #endif. #define. 4. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #line. #else. using non-nested /* and */ for comments that may span multiple lines. The C preprocessor cpp may be used to process PTX source files. The following are common preprocessor directives: #include.Chapter 4. Pseudo-operations specify symbol and addressing management. followed by a . Comments Comments in PTX follow C/C++ syntax. and using // to begin a comment that extends to the end of the current line.2. PTX is case sensitive and uses lowercase for keywords. whitespace is ignored except for its use in separating tokens in the language. January 24.

The guard predicate follows the optional label and precedes the opcode. r1.0 4. 0. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.const .x. mov. or label names. .pragma . 18 January 24.section . Instruction keywords are listed in Table 2.param . Table 1.entry .maxnreg . array[r1].1.local .f32 r2.b32 r1.global. The destination operand is first.extern .3. Instructions have an optional guard predicate which controls conditional execution.visible 4.target .tex .file PTX Directives . ld. so no conflict is possible with user-defined identifiers.2. and terminated with a semicolon. Statements A PTX statement is either a directive or an instruction. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.reg . shl.PTX ISA Version 2. All instruction keywords are reserved tokens in PTX. followed by source operands.align . address expressions. and is written as @p.sreg . Examples: .b32 r1.shared . 2010 . Operands may be register variables.global . The guard predicate may be optionally negated. written as @!p. . r2.3. r2. where p is a predicate register. %tid. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.b32 add.func .maxnctapersm .loc .maxntid . constant expressions.reg .f32 array[N].5. 2.global start: . Statements begin with an optional label and end with a semicolon. Directive Statements Directive keywords begin with a dot.3.minnctapersm .b32 r1. r2.version .

Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2. 2010 19 .

The percentage sign can be used to avoid name conflicts.4. except that the percentage sign is not allowed. or dollar characters. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. between user-defined variable names and compiler-generated names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. listed in Table 3.0 4. digits.PTX ISA Version 2. ….g. Many high-level languages such as C and C++ follow similar rules for identifier names. %pm3 WARP_SZ 20 January 24. PTX predefines one constant and a small number of special registers that begin with the percentage sign. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. digits. 2010 . or they start with an underscore. Table 3. underscore. or percentage character followed by one or more letters. e. underscore. dollar. PTX allows the percentage sign as the first character of an identifier.

where the behavior of the operation depends on the operand types. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Integer literals may be written in decimal. Unlike C and C++. 0[fF]{hexdigit}{8} // single-precision floating point January 24.5. To specify IEEE 754 single-precision floating point values.s64 or . These constants may be used in data initialization and as operands to instructions.e.5. Type checking rules remain the same for integer. or binary notation.s64 or the unsigned suffix is specified. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. literals are always represented in 64-bit double-precision format.Chapter 4. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. and bit-size types.e. octal. Constants PTX supports integer and floating-point constants and constant expressions. 4. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. there is no suffix letter to specify size. integer constants are allowed and are interpreted as in C.5. zero values are FALSE and non-zero values are TRUE. To specify IEEE 754 doubleprecision floating point values. 2010 21 . Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. When used in an instruction or data initialization. 4. the constant begins with 0f or 0F followed by 8 hex digits. each integer constant is converted to the appropriate size based on the data or instruction type at its use. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. i. the constant begins with 0d or 0D followed by 16 hex digits. every integer constant has type . Syntax 4.u64). in which case the literal is unsigned (. the sm_1x and sm_20 targets have a WARP_SZ value of 32. For predicate-type data and instructions. floating-point.u64. hexadecimal. Floating-point literals may be written with an optional decimal point and an optional signed exponent.2.1.. i.s64) unless the value cannot be fully represented in . The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. The syntax follows that of C. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

u64 same as 1st operand .u64 . or . 2nd is .f64 use usual conversions .s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 converted type constant literal + ! ~ Cast Binary (.s64) + . Syntax 4.f64 use usual conversions .u64.u64 1st unchanged.f64 same as source .s64 . . Table 5.f64 use usual conversions .f64 integer .s64 . 2010 25 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64 .u64 .Chapter 4.s64 .f64 : .6.s64 .u64 .u64 .f64 integer .s64 .s64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64) (. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 .f64 converted type .s64.f64 integer integer integer integer integer int ?.u64 .5.

2010 .0 26 January 24.PTX ISA Version 2.

fast.tex January 24. Global memory. Local memory. addressability. Kernel parameters. Name State Spaces Description Registers. The characteristics of a state space include its size. All variables reside in some state space.global . defined per-thread.reg . 5. .1. pre-defined.local . and these resources are abstracted in PTX through state spaces and data types. 2010 27 .param . State Spaces A state space is a storage area with particular characteristics. State Spaces. Types. shared by all threads. access rights. and properties of state spaces are shown in Table 5.sreg . and Variables While the specific resources available in a given target GPU will vary. Addressable memory shared between threads in 1 CTA. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. defined per-grid. read-only memory.const . Read-only. and level of sharing between threads.shared . The list of state spaces is shown in Table 4. Table 6.Chapter 5. Special registers. Shared. access speed. platform-specific. private to each thread. Global texture memory (deprecated). or Function or local parameters. the kinds of resources will be common across platforms.

and will vary from platform to platform. Register State Space Registers (.e. causing changes in performance. Register size is restricted. 3 Accessible only via the tex instruction.sreg . 2010 . 1 Accessible only via the ld. Device function input parameters may have their address taken via mov.0 Table 7.param instructions. unsigned integer. st. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). Registers may have alignment boundaries required by multi-word loads and stores. The number of registers is limited. Registers may be typed (signed integer.param (used in functions) .global . The most common use of 8-bit registers is with ld.. it is not possible to refer to the address of a register. 32-. aside from predicate registers which are 1-bit. Registers differ from the other state spaces in that they are not fully addressable. 16-. For each architecture. 32-. platform-specific registers.param instruction.local state space. 5. clock counters. CTA.1.param and st. register variables will be spilled to memory. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.sreg) state space holds predefined.PTX ISA Version 2. 2 Accessible via ld. or 64-bits.tex Restricted Yes No3 5. Address may be taken via mov instruction. and thread parameters. i.1.1.2. and vector registers have a width of 16-. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .param (as input to kernel) . predicate) or untyped.const . the parameter is then located on the stack frame and its address is in the .reg . scalar registers have a width of 8-.shared . When the limit is exceeded. Special Register State Space The special register (. or as elements of vector tuples. such as grid. All special registers are predefined. or 128-bits.local . and performance monitoring registers. floating point.reg state space) are fast storage locations. 64-. 28 January 24. and cvt instructions.

initialized by the host. For example.b32 const_buffer[]. and Variables 5.sync instruction are guaranteed to be visible to any reads after the barrier instruction.const[2] . where the size is not known at compile time. the declaration . the store operation updating a may still be in flight. st. as in lock-free and wait-free style programming.4. The remaining banks may be used to implement “incomplete” constant arrays (in C. Use ld.extern . Types. whereas local memory variables declared January 24. where bank ranges from 0 to 10.const[2]. [const_buffer+4]. Banks are specified using the . Module-scoped local memory variables are stored at fixed addresses.b32 const_buffer[]. 5. Multiple incomplete array variables declared in the same bank become aliases. If another thread sees the variable b change. It is the mechanism by which different CTAs and different grids can communicate. Global memory is not sequentially consistent.local and st. results in const_buffer pointing to the start of constant bank two. Threads wait at the barrier until all threads in the CTA have arrived. Threads must be able to do their work without waiting for other threads to do theirs.sync instruction.extern . the stack is in local memory. State Spaces.global to access global variables. bank zero is used.const) state space is a read-only memory. In implementations that support a stack. By convention.1. All memory writes prior to the bar. Consider the case where one thread executes the following two assignments: a = a + 1. b = b – 1. all addresses are in global memory are shared.const[2] .Chapter 5. for example).b32 %r1. It is typically standard memory with cache. // load second word 5. 2010 29 . bank zero is used for all statically-sized constant variables. For example.local) is private memory for each thread to keep its own data. Global State Space The global (. The constant memory is organized into fixed size banks. To access data in contant banks 1 through 10. The size is limited.3. This reiterates the kind of parallelism available in machines that run PTX. If no bank number is given. Use ld. Local State Space The local state space (.global. For the current devices.global.1. ld.1. the bank number must be provided in the state space of the load instruction. each pointing to the start address of the specified constant bank. For any thread in a context. Sequential consistency is provided by the bar. as it must be allocated on a perthread basis. an incomplete array in bank 2 is accessed as follows: . there are eleven 64KB banks. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.local to access local variables. Constant State Space The constant (.const[bank] modifier. and atom. This pointer can then be used to access the entire 64KB constant bank.5.global) state space is memory that is accessible by all threads in a context.

function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).reg .param space. . … Example: . Example: .b8 buffer[64] ) { . ld. 5. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. (2a) to declare formal input and return parameters for device functions called from within kernel execution. Therefore.reg .f64 %d. . The resulting address is in the .param .param state space and is accessed using ld.param. device function parameters were previously restricted to the register state space. len. ld. 5.f64 %d.u32 %n.u32 %ptr. %n. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. The use of parameter state space for device function parameters is new to PTX ISA version 2.6. … 30 January 24.1. Similarly. For example.param) state space is used (1) to pass input arguments from the host to the kernel.u32 %ptr.entry foo ( .param instructions. [N]. typically for passing large structures by value to a function.PTX ISA Version 2.param space variables.b32 len ) { . In implementations that do not support a stack. No access protection is provided between parameter and global space in this case. The kernel parameter variables are shared across all CTAs within a grid. all local memory variables are stored at fixed addresses and recursive function calls are not supported.param. The address of a kernel parameter may be moved into a register using the mov instruction.b32 N.6.param . These parameters are addressable.u32 %n. read-only variables declared in the . [%ptr].reg . Note that PTX ISA versions 1.1.1.x supports only kernel function parameters in . per-kernel versus per-thread). Parameter State Space The parameter (. 2010 . Note: The location of parameter space is implementation specific.param instructions. ld.0 and requires target architecture sm_20.param state space.align 8 .u32 %n. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. PTX code should make no assumptions about the relative locations or ordering of .param.0 within a function or kernel body are allocated on the stack.entry bar ( . Values passed from the host to the kernel are accessed through these parameter variables using ld. [buffer].param . in some implementations kernel parameters reside in global memory. mov.

reg . which declares a .align 8 . passed to foo … .b8 buffer[12] ) { . It is not possible to use mov to get the address of a return parameter or a locally-scoped .param . . [buffer].param.2. Note that the parameter will be copied to the stack if necessary. .local instructions. the caller will declare a locally-scoped . int y. is flattened. January 24. Types. Device Function Parameters PTX ISA version 2. In this case. } mystruct. [buffer+8].param.param and function return parameters may be written using st.local and st. ld. .6. Typically. Example: // pass object of type struct { double d. a byte array in parameter space is used. call foo. Aside from passing structures by value. }.reg .b8 mystruct.func foo ( . State Spaces. (4.param.s32 x. int y. st. .align 8 . 2010 31 .f64 %d.0 extends the use of parameter space to device function parameters. The most common use is for passing objects by value that do not fit within a PTX register.f64 %d. dbl.reg .Chapter 5.s32 %y.f64 dbl.1.s32 %y. Function input parameters may be read via ld.param space is also required whenever a formal parameter has its address taken within the called function.b32 N.f64 [mystruct+0].param . the address of a function input parameter may be moved into a register using the mov instruction. .s32 [mystruct+8].reg . x.param.param space variable.param. mystruct). and Variables 5. This will be passed by value to a callee. it is illegal to write to an input parameter or read from a return parameter. In PTX. … See the section on function call syntax for more details. and so the address will be in the . … st. … } // code snippet from the caller // struct { double d.local state space and is accessed via ld.param byte array variable that represents a flattened C structure or union. ld.param formal parameter having the same size and alignment as the passed argument. such as C structures larger than 8 bytes. .reg .

is equivalent to . See Section 5.tex variables are required to be defined in the global scope. 32 January 24.tex state space are equivalent to module-scoped . and variables declared in the .PTX ISA Version 2.texref tex_a.tex . and . Texture memory is read-only. An error is generated if the maximum number of physical resources is exceeded.shared) state space is a per-CTA region of memory for threads in a CTA to share data.3 for the description of the . tex_d.shared to access shared variables. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.tex directive is retained for backward compatibility. One example is broadcast.global state space.tex .0 5. 2010 .texref.global . The . It is shared by all threads in a context.tex . Shared State Space The shared (. where texture identifiers are allocated sequentially beginning with zero. a legacy PTX definitions such as . For example.1. Multiple names may be bound to the same physical texture identifier. tex_f.1.texref variables in the . The texture name must be of type .7.texref type and Section 8.u32 or .tex . Use ld.tex directive will bind the named texture memory variable to a hardware texture identifier. 5. Another is sequential access from sequential threads.tex) state space is global memory accessed via the texture instruction. where all threads read from the same address. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). tex_c.u32 tex_a.u32 . and programs should instead reference texture memory through variables of type . Physical texture resources are allocated on a per-module granularity.7.u32 . An address in shared memory can be read and written by any thread in a CTA.u64. tex_d.tex .6 for its use in texture instructions. Texture State Space (deprecated) The texture (. Shared memory typically has some optimizations to support the sharing. A texture’s base address is assumed to be aligned to a 16-byte boundary.8.u32 . Example: . The .u32 tex_a.shared and st.

.u64 .f64 types. stored. the fundamental types reflect the native data types supported by the target architectures.f64 . State Spaces.Chapter 5. .s8. . st. 2010 33 . . In principle.u16. or converted to other types and sizes. needed to fully specify instruction behavior. and Variables 5. The following table lists the fundamental type specifiers for each basic type: Table 8. . . The .f16. and converted using regular-width registers. For convenience. .pred Most instructions have one or more type specifiers. and .u8. Fundamental Types In PTX. but typed variables enhance program readability and allow for better operand type checking. Operand types and sizes are checked against instruction types for compatibility. ld.u8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. For example.2.b8 instruction types are restricted to ld.1.u32.f64 types.b16. so their names are intentionally short.2. all variables (aside from predicates) could be declared using only bit-size types.2. Signed and unsigned integer types are compatible if they have the same size. . stored. The same typesize specifiers are used for both variable definitions and for typing instructions. A fundamental type specifies both a basic type and a size. . 5. and cvt instructions. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . and instructions operate on these types.s32. . All floating-point instructions operate only on .f32 and .f32 and . Restricted Use of Sub-Word Sizes The . .f32.f16 floating-point type is allowed only in conversions to and from . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Types 5. Register variables are always of a fundamental type.s8. so that narrow values may be loaded. Two fundamental types are compatible if they have the same basic type and are the same size.2.s64 .b8. January 24.b32.b64 . Types. st.s16. The bitsize type is compatible with any fundamental type having the same size.

These types have named fields similar to structures. allowing them to be defined separately and combined at the site of usage in the program. Referencing textures. The three built-in types are . The following tables list the named members of each type for unified and independent texture modes. In the unified mode. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.texref type that describe sampler properties are ignored. and overall size is hidden to a PTX program. Retrieving the value of a named member via query instructions (txq. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.texref handle. sured). In the independent mode. but all information about layout. the resulting pointer may be stored to and loaded from memory. In independent mode the fields of the .3. suld. Texture. or surfaces via texture and surface load/store instructions (tex.PTX ISA Version 2. Sampler. 2010 .samplerref. accessing the pointer with ld and st instructions..0 5. and Surface Types PTX includes built-in “opaque” types for defining texture.surfref. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. and de-referenced by texture and surface load. . or performing pointer arithmetic will result in undefined results.u64} reg. passed as a parameter to functions. and query instructions. texture and sampler information each have their own handle. store. Creating pointers to opaque variables using mov. i. For working with textures and samplers. PTX has two modes of operation. samplers. since these properties are defined by .samplerref variables. opaque_var. sampler. and . but the pointer cannot otherwise be treated as an address. hence the term “opaque”. suq). and surface descriptor variables.e. base address. sust.{u32.texref. 34 January 24. texture and sampler information is accessed through a single . field ordering.

surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.texref values in elements in elements in elements 0. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_to_edge. State Spaces. clamp_to_border N/A N/A N/A N/A N/A . clamp_to_border 0.samplerref values N/A N/A N/A N/A nearest. linear wrap.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.Chapter 5. clamp_to_edge. 1 nearest. 2010 35 . clamp_ogl. mirror.texref values . clamp_ogl. 1 ignored ignored ignored ignored . Member width height depth Opaque Type Fields in Independent Texture Mode . Types. mirror. and Variables Table 9. linear wrap.

global . At module scope. .global .texref my_texture_name.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global .samplerref my_sampler_name. Example: . Example: . the types may be initialized using a list of static expressions assigning values to the named members. When declared at module scope. filter_mode = nearest }. As kernel parameters. 2010 .global state space.param state space. these variables are declared in the .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global .global . . 36 January 24. .PTX ISA Version 2.surfref my_surface_name.texref tex1. these variables must be in the .

global . 0}. 1.v2 or .reg . vector variables are aligned to a multiple of their overall size (vector length times base-type size).v4 .v4 .2.b8 v.s32 i. etc. and an optional fixed address for the variable. A variable declaration names the space in which the variable resides. a variable declaration describes both the variable’s type and its state space. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. // a length-2 vector of unsigned ints .v4 vector. State Spaces.reg . 5. Variables In PTX. Examples: . r.0. 0.global . .f32 v0. Every variable must reside in one of the state spaces enumerated in the previous section. // typedef .f32 accel. and they may reside in the register space.1. // a length-4 vector of floats . . .struct float4 { . its type and size.v4. where the fourth element provides padding.const .struct float4 coord.f64 is not allowed. 0.f32 V. q.v2 .global .u32 loc.4.global .v3 }.v4 . Vectors cannot exceed 128-bits in length. In addition to fundamental types.0}.pred p. 2010 37 . an optional initializer. Vectors Limited-length vector types are supported.4. January 24. Types.v4. PTX supports types for simple aggregate objects such as vectors and arrays.u16 uv. its name. Variable Declarations All storage for data is specified with variable declarations. an optional array size. for example. . This is a common case for three-dimensional grids.u8 bg[4] = {0.v1.reg . . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . textures. Vectors must be based on a fundamental type. . Examples: . . 5. Predicate variables may only be declared in the register state space.global .4.Chapter 5. // a length-4 vector of bytes By default. Three-element vectors may be handled by using a .f32 bias[] = {-1.shared . and Variables 5.v2.

the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. 0}.u8 mailbox[128].0. 19*19 (361) halfwords are reserved (722 bytes). being determined by an array initializer.0.{. {0. To declare an array.PTX ISA Version 2. Array Declarations Array declarations are provided to allow the programmer to reserve space.0.shared .0 5.v4 ..u32 or .4. 0}. {0.05.1. For the kernel declaration above.u16 kernel[19][19]. The size of the array specifies how many elements should be reserved. {1.0. 1} }.{.0}}. this can be used to statically initialize a pointer to a variable.1. {0.4.global . .4. label names appearing in initializers represent the address of the next instruction following the label. where the variable name is followed by an equals sign and the initial value or values for the variable.. .1.05}}. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.05}. 5.1}. 2010 .u64.1. Similarly. . // address of rgba into ptr Currently.0}. The size of the dimension is either a constant expression. or is left empty.4.global . Initializers are allowed for all types except . {0. variable initialization is supported only for constant and global state spaces..global ...b32 ptr = rgba.global . . -1}. A scalar takes a single value.global .1.0}.f32 blur_kernel[][] = {{.pred.u8 rgba[3] = {{1.05.local . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). .. Here are some examples: . Variable names appearing in initializers represent the address of the variable.s32 n = 10.3.s32 offset[][] = { {-1. Examples: . this can be used to initialize a jump table to be used with indirect branches or calls.f16 and . Variables that hold addresses of variables or instructions should be of type . 38 January 24.

Rather than require explicit declaration of every name. The variable will be aligned to an address which is an integer multiple of byte-count. alignment specifies the address alignment for the starting address of the entire array.0. Types. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. and Variables 5. not for individual elements. suppose a program uses a large number..2. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.b8 bar[8] = {0. Elements are bytes. Parameterized Variable Names Since PTX supports virtual registers.Chapter 5.reg .0. For arrays. State Spaces. %r1. say one hundred. it is quite common for a compiler frontend to generate a large number of register names. January 24. Examples: // allocate array at 4-byte aligned address.0.0}.. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.align byte-count specifier immediately following the state-space specifier. . . 5.align 4 . These 100 register variables can be declared as follows: . The default alignment for vector variables is to a multiple of the overall vector size.5.4. nor are initializers permitted.b32 %r<100>. ….4. The default alignment for scalar and array variables is to a multiple of the base-type size. Array variables cannot be declared this way.0. // declare %r0.6. named %r0.. For example. 2010 39 . %r99. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.b32 variables.const . %r1. and may be preceded by an alignment specifier. of .0. Alignment is specified using an optional .

PTX ISA Version 2. 2010 .0 40 January 24.

s. so operands for ALU instructions must all be in variables declared in the . PTX describes a load-store machine. 6. and a few instructions have additional predicate source operands. Most instructions have an optional predicate guard that controls conditional execution. b. Operands having type different from but compatible with the instruction type are silently cast to the instruction type.1. and c. . Integer types of a common size are compatible with each other. Instructions ld and st move data from/to addressable state spaces to/from registers. r. as its job is to convert from nearly any data type to any other data type (and size). Each operand type must be compatible with the type determined by the instruction template and instruction type. The result operand is a scalar or vector variable in the register state space. q. For most operations. Predicate operands are denoted by the names p. The mov instruction copies data between registers.Chapter 6. The bit-size type is compatible with every type having the same size. mov. Source Operands The source operands are denoted in the instruction descriptions by the names a. Operand Type Information All operands in instructions have a known type from their declarations. 6. the sizes of the operands must be consistent.3. January 24.2. st. The cvt (convert) instruction takes a variety of operand types and sizes. The ld. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. 2010 41 . Instruction Operands 6. and cvt instructions copy data from one location to another.reg register state space. There is no automatic conversion between types.

b32 p. Address expressions include variable names. W. The address is an offset in the state space in which the variable is declared.s32 tbl[256]. .u16 r0.PTX ISA Version 2. tbl.global . All addresses and address computations are byte-based. address registers.shared . [V]. Load and store operations move data between registers and locations in addressable state spaces. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.const.1.4.reg . p. The mov instruction can be used to move the address of a variable into a pointer. arrays. The syntax is similar to that used in many assembly languages. .u16 ld.reg . and immediate address expressions which evaluate at compile-time to a constant address.const . r0. . and Vectors Using scalar variables as operands is straightforward. ld. The interesting capabilities begin with addresses.v4. 2010 .f32 W.v4 .s32 mov. [tbl+12].f32 V. address register plus byte offset. . . Arrays.gloal. 6. Here are a few examples: .s32 q. Using Addresses.v4 .u32 42 January 24.f32 ld. .reg .[x]. Examples include pointer arithmetic and pointer comparisons. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.0 6.shared.reg .u16 x.4. q. there is no support for C-style pointer arithmetic. and vectors.

correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. A brace-enclosed list is used for pattern matching to pull apart vectors. [addr+offset]. for use in an indirect branch or call.y. and the identifier becomes an address constant in the space where the array is declared. say {Ra. Vector elements can be extracted from the vector with the suffixes .global.4.u32 s. d.f32 {a.r. // move address of a[1] into s 6. .x V. it must be written as an address calculation prior to use.reg . st.g. Here are examples: ld. ld.4. ld.global.4.u32 s. Instruction Operands 6. a[N-1]. Examples are ld. a register variable. Rd}.b.4.b V.global. . The size of the array is a constant in the program.c.w. Arrays as Operands Arrays of all types can be declared. Array elements can be accessed using an explicitly calculated byte address.b and .c.a. a[1]. . Vectors may also be passed as arguments to called functions. . mov. January 24. c. . Rb.v2.y V.a 6.u32 {a. which include mov.v4. Vector loads and stores can be used to implement wide loads and stores. Vectors as Operands Vector operands are supported by a limited subset of instructions. 2010 43 .f32 V.g V.b. and tex. mov.3. V.w = = = = V. or a simple “register with constant offset” expression. If more complicated indexing is desired.f32 a. and in move instructions to get the address of the label or function into a register.2. b.r V.global.d}.Chapter 6.x.v4.d}. Rc.v4 . a[0]. or by indexing into the array using square-bracket notation.u32 s. where the offset is a constant expression that is either added or subtracted from a register variable. The expression within square brackets is either a constant integer. .z V. or a braceenclosed list of similarly typed scalars. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.reg .z and . Elements in a brace-enclosed vector. The registers in the load/store operations can be a vector. as well as the typical color fields . [addr+offset2]. which may improve memory performance. V2.f32 ld.

0 6. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.s32. the u16 is zero-extended to s32. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. For example. Operands of different sizes or types must be converted prior to the operation. 6.000 for f16).5. 2010 .PTX ISA Version 2.1. Type Conversion All operands to all arithmetic.5. and data movement instruction must be of the same type and size. except for operations where changing the size and/or type is part of the definition of the instruction. 44 January 24. logic.u16 instruction is given a u16 source operand and s32 as a destination operand. if a cvt. and ~131.

s16. then sign-extend to 32-bits.Chapter 6. January 24. the result is extended to the destination register width after chopping. u2f = unsigned-to-float. 2010 45 . chop = keep only low bits that fit. s2f = signed-to-float. cvt. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2f = float-to-float. Instruction Operands Table 11.u32 targeting a 32-bit register will first chop to 16-bits. Notes 1 If the destination register is wider than the destination format. f2s = float-to-signed. f2u = float-to-unsigned. The type of extension (sign or zero) is based on the destination format. zext = zero-extend. For example.

rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. 2010 . Rounding Modifiers Conversion instructions may specify a rounding modifier.rzi .rn .rm . choosing even integer if source is equidistant between two integers. Modifier .rpi Integer Rounding Modifiers Description round to nearest integer.0 6. Table 12.5. there are four integer rounding modifiers and four floating-point rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. The following tables summarize the rounding modifiers.PTX ISA Version 2.rni . Modifier .rmi . In PTX.2.rz .

Registers are fastest.6.Chapter 6. Much of the delay to memory can be hidden in a number of ways. The register in a store operation is available much more quickly. Table 14. Operand Costs Operands from different state spaces affect the speed of an operation. while global memory is slowest. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Table 11 gives estimates of the costs of using different kinds of memory. Instruction Operands 6. first access is high Notes January 24. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. 2010 47 . Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Another way to hide latency is to issue the load instructions as early as possible.

2010 .0 48 January 24.PTX ISA Version 2.

arguments may be register variables or constants. and is represented in PTX as follows: . Function declarations and definitions In PTX. or prototype. functions are declared and defined using the . Abstracting the ABI Rather than expose details of a particular calling convention. A function declaration specifies an optional list of return parameters. At the call. Scalar and vector base-type input and return parameters may be represented simply as register variables. 7. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. These include syntax for function definitions. support for variadic functions (“varargs”).func foo { … ret.Chapter 7. and Application Binary Interface (ABI). Execution of the ret instruction within foo transfers control to the instruction following the call. we describe the features of PTX needed to achieve this hiding of the ABI. stack-based ABI. In this section.1. execution of the call instruction transfers control to foo. } … call foo. A function must be declared or defined prior to being called. implicitly saving the return address. and return values may be placed directly into register variables.func directive. NOTE: The current version of PTX does not implement the underlying. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. and an optional list of input parameters. January 24. A function definition specifies both the interface and the body of the function. 2010 49 . and memory allocated on the stack (“alloca”). together these specify the function’s interface. stack layout. parameter passing. … Here. The simplest function has no parameters or return values. the function name. so recursion is not yet supported. function calls.

s32 x. … ld. .param.u32 %inc ) { add. char c[4].param. py).u32 %res.reg .b8 c1.reg .u32 %ptr. byte array in .f64 f1.param space call (%out).b8 [py+10].param. [y+0]. Second.align 8 y[12]) { .param variable y is used in function definition bar to represent a formal parameter. ld.param.b8 c3.param . %ptr. Since memory accesses are required to be aligned to a multiple of the access size.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.0 Example: .c3.b64 [py+ 0].b8 . … In this example. [y+9]. a . bumpptr. (%r1.param . consider the following C structure.func (.b8 [py+ 9]. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . this structure will be flattened into a byte array. . note that . For example.f1. %rc1. … st.param state space is used to pass the structure by value: . }. In PTX. st. %inc.4).param.reg .param. inc_ptr. 50 January 24.c2.b8 [py+11].b32 c1. c3.u32 %res) inc_ptr ( . } … call (%r1). First.func (.c1. st. [y+8]. c4. 2010 . passed by value to a function: struct { double dbl. } { .reg space.param space memory.f64 f1.align 8 py[12]. c2. %rc1.b8 c2.s32 out) bar (. ret.c4. // scalar args in .b8 c4.reg . ld. … … // computation using x. (%x. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .PTX ISA Version 2.b8 [py+ 8]. %rd.param. %rc2. st. %rc2.reg . The . . st. ld.param space variables are used in two ways.f64 field are aligned.param.reg . a . ld. [y+10].param.param. [y+11].reg .b8 .

param arguments. In the case of . Note that the choice of . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param state space use in device functions.reg variables.param and ld.param space formal parameters that are byte arrays.param state space is used to receive parameter values and/or pass return values back to the caller.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. • The . Typically. a . 8. For a caller. For . all st.reg state space can be used to receive and return base-type scalar and vector values.g. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. and alignment.reg state space in this way provides legacy support. 2010 51 . Supporting the .param variables or . the corresponding argument may be either a . the argument must also be a . For a caller. or 16 bytes. In the case of . • • • For a callee.reg space formal parameters. January 24.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. For a callee. .reg space variable with matching type and size. or a constant that can be represented in the type of the formal parameter.param argument must be declared within the local scope of the caller.param or .reg space variable of matching type and size. The .Chapter 7.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param instructions used for argument passing must be contained in the basic block with the call instruction.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. In the case of . size. A .param memory must be aligned to a multiple of 1. and alignment of parameters.param space formal parameters that are base-type scalar or vector variables. or a constant that can be represented in the type of the formal parameter. the corresponding argument may be either a . Abstracting the ABI The following is a conceptual way to think about the . 2. or constants. • The . Parameters in . • • • Input and return parameters may be . This enables backend optimization and ensures that the .param byte array is used to collect together fields of a structure being passed by value.reg variables. size. • • Arguments may be .reg or .param variables. 4. The . The following restrictions apply to parameter passing.param or ..param space byte array with matching type.

and there was no support for array parameters.x In PTX ISA version 1.x. PTX 2.param state space. Changes from PTX 1.0.PTX ISA Version 2. formal parameters were restricted to .0 7. formal parameters may be in either .param byte array should be used to return objects that do not fit into a register. Objects such as C structures were flattened and passed or returned using multiple registers. PTX 1.reg or .1. and a .0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays.1. For sm_2x targets. 52 January 24. PTX 2.0 restricts functions to a single return value. In PTX ISA version 2.x supports multiple return values for this purpose.reg state space. and . 2010 .

Chapter 7.pred p. 4.h and varargs. %r1.reg .s32 result ) maxN ( .reg . Abstracting the ABI 7. setp.u32 ptr) %va_start . following zero or more fixed parameters: .s32 result.func okay ( … ) Built-in functions are provided to initialize. call (ap). (2.u32 sz. %s1. (3. 4. call (val).s32 val. max. for %va_arg64.reg . iteratively access. along with the size and alignment of the next data value to be accessed. . } … call (%max).u32 a. %r2. maxN. For %va_arg.u32 ptr. PTX provides a high-level mechanism similar to the one provided by the stdarg.u32 align) .reg .b64 val) %va_arg64 (.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. N. (ap). the size may be 1.reg .u32.reg .2. and end access to a list of variable arguments.func %va_end (.reg .func (. 2. or 8 bytes. %va_arg. val. ) { .func baz ( .reg . Once all arguments have been processed. maxN. 2.u32 ap. ctr.reg . 4).reg . call %va_end. ret. variadic functions are declared with an ellipsis at the end of the input parameter list.ge p. 2. 8. bra Done.reg .. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .func (. . … call (%max).func ( . This handle is then passed to the %va_arg and %va_arg64 built-in functions. the alignment may be 1. .b32 val) %va_arg (. . %r3). Variadic functions NOTE: The current version of PTX does not support variadic functions. %va_end is called to free the variable argument list handle.b32 result.h headers in C. . The function prototypes are defined as follows: . In both cases. … %va_start returns Loop: @p Done: January 24. 4. %s2).. .u32 sz. 0x8000000. bra Loop.reg .reg .u32 b. (ap. or 4 bytes. 2010 53 . . or 16 bytes.reg .b32 ctr. To support functions with a variable number of arguments. // default to MININT mov. %va_start.u32 ptr.u32 align) . .u32 N. … ) .reg .reg . In PTX. ctr. result. 0.func (.reg . the size may be 1. mov.

u32 ptr ) %alloca ( .PTX ISA Version 2.local instructions. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. 2010 .reg .3. 54 January 24. defined as follows: . The array is then accessed with ld.func ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. a function simply calls the built-in function %alloca. If a particular alignment is required. To allocate memory. Alloca NOTE: The current version of PTX does not support alloca.local and st.reg .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.0 7.

while A. We use a ‘|’ symbol to separate multiple destination registers. and C are the source operands. Instruction Set 8. the semantics are described. B. January 24. b.Chapter 8. A. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. the D operand is the destination operand. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. opcode A.1. 8.2. The setp instruction writes two destination registers.lt p|q. setp. opcode D. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. // p = (a < b). q = !(a < b). opcode D. In addition to the name and the format of the instruction. 2010 55 . a. A. For instructions that create a result value. PTX Instructions PTX instructions generally have from zero to four operands. B. For some instructions the destination operand is optional. A.s32. followed by some examples that attempt to show several possible instantiations of the instruction. C. B.

add 1 to j To get a conditional branch or conditional function call. This can be written in PTX as @p setp. consider the high-level code if (i < n) j = j + 1. n. add. Instructions without a guard predicate are executed unconditionally. where p is a predicate variable.PTX ISA Version 2.3.s32 p.lt.s32 p. q. So.0 8. As an example. n. Predicated Execution In PTX. 1.pred p.s32 j. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. 2010 . use a predicate to control the execution of the branch or call instructions. predicate registers can be declared as .reg . predicate registers are virtual and have . … // compare i to n // if false. i. add. Predicates are most commonly set as the result of a comparison performed by the setp instruction. j.s32 j. To implement the above example as a true conditional branch. 1. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. bra L1.pred as the type specifier. branch over 56 January 24. j. i. the following PTX instruction sequence might be used: @!p L1: setp.lt. optionally negated. // p = (i < n) // if i < n.

unsigned integer. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.Chapter 8. the result is false. ne.3. and ge (greater-than-or-equal).1. 2010 57 . Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Table 16. lt. and bitsize types. gt. Table 15.1. and hs (higher-or-same). and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.2. le. ordering comparisons are not defined for bit-size types.1.1. Instruction Set 8. Unsigned Integer. le (less-than-or-equal). The following table shows the operators for signed integer. Comparisons 8.3.3. hi (higher). If either operand is NaN. gt (greater-than). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ge. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. The bit-size comparisons are eq and ne. ne (not-equal). lo (lower). The unsigned comparisons are eq. ls (lower-or-same). lt (less-than). ne.

then the result of these comparisons is true. Table 17. gtu. for example: selp. unordered versions are included: equ. If either operand is NaN. xor. num returns true if both operands are numeric values (not NaN). not. two operators num (numeric) and nan (isNaN) are provided. setp can be used to generate a predicate from an integer.2. leu. and mov.3. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. or. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. Table 18. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. If both operands are numeric values (not NaN). neu. // convert predicate to 32-bit value 58 January 24. However.1. and no direct way to load or store predicate register values. 2010 . ltu. and nan returns true if either operand is NaN. geu.0. then these comparisons have the same result as their ordered counterparts.%p.0 To aid comparison operations in the presence of NaN values.u32 %r1. There is no direct conversion between predicates and integer values.PTX ISA Version 2.

bX .. Signed and unsigned integer types agree provided they have the same size.fX ok inv inv ok Instruction Type . 2010 59 .uX . .sX ok ok ok inv . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.reg . and this information must be specified as a suffix to the opcode. Floating-point types agree only if they have the same size.u16 d.bX .fX ok ok ok ok January 24.e. the add instruction requires type and size information to properly perform the addition operation (signed. unsigned. a. and these are placed in the same order as the operands. a. It requires separate type-size modifiers for the result and source. b. a. Instruction Set 8. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. different sizes). For example: . For example. Table 19. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. cvt.Chapter 8.u16 d.reg .uX ok ok ok inv . Type Checking Rules Operand Type . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. • The following table summarizes these type checking rules. i. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. For example. b.f32 d. most notably the data conversion instruction cvt. float.f32. and integer operands are silently cast to the instruction type if needed. Example: .reg . they must match exactly. add.4.u16 d.sX .u16 a.

the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. unless the operand is of bit-size type. st.4. or converted to other types and sizes. ld. and converted using regular-width registers.1. For example. Floating-point source registers can only be used with bit-size or floating-point instruction types. Source register size must be of equal or greater size than the instruction-type size. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types.0 8. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. Operand Size Exceeding Instruction-Type Size For convenience. so that narrow values may be loaded. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. stored. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. for example. the size must match exactly. The data is truncated to the instruction-type size and interpreted according to the instruction type. no conversion needed. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Bit-size source registers may be used with any appropriately-sized instruction type. When used with a narrower bit-size type. 1. stored. so those rows are invalid for cvt. “-“ = allowed. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. When a source operand has a size that exceeds the instruction-type size. parse error. 2. 4. inv = invalid. Note that some combinations may still be invalid for a particular instruction.bX instruction types.PTX ISA Version 2. When used with a floating-point instruction type. the data will be truncated. Table 20. Notes 3. 60 January 24. floating-point instruction types still require that the operand type-size matches exactly. The following table summarizes the relaxed type-checking rules for source operands. the cvt instruction does not support . 2010 .

inv = Invalid. The data is sign-extended to the destination register width for signed integer instruction types. the data is sign-extended.Chapter 8. 2.or sign-extended to the size of the destination register. parse error. Bit-size destination registers may be used with any appropriately-sized instruction type. The data is signextended to the destination register width for signed integer instruction types. Notes 3. the destination data is zero. 2010 61 . 1. the data will be zero-extended. January 24. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. When used with a floatingpoint instruction type. Table 21. the size must match exactly. Destination register size must be of equal or greater size than the instruction-type size. Instruction Set When a destination operand has a size that exceeds the instruction-type size. When used with a narrower bit-size instruction type. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. “-“ = Allowed but no conversion needed. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. the data is zeroextended. zext = zero-extend. Floating-point destination registers can only be used with bit-size or floating-point instruction types. 4. If the corresponding instruction type is signed integer. The following table summarizes the relaxed type-checking rules for destination operands. otherwise. and is zero-extended to the destination register width otherwise.

These extra precision bits can become visible at the application level. 62 January 24. 8. the semantics of 16-bit instructions in PTX is machine-specific. 16-bit registers in PTX are mapped to 32-bit physical registers. Divergence of Threads in Control Constructs Threads in a CTA execute together.PTX ISA Version 2.uni suffix. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. Therefore.6. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers.6. At the PTX language level. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. If threads execute down different control flow paths. When executing on a 32-bit data path. this is not desirable. by a right-shift instruction. If all of the threads act in unison and follow a single control flow path. for example. or conditional return. using the . conditional function call. so it is important to have divergent threads re-converge as soon as possible. The semantics are described using C.1. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.0 8. and for many applications the difference in execution is preferable to limiting performance. 8. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. until they come to a conditional control construct such as a conditional branch. For divergent control flow. at least in appearance. the threads are called divergent. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. for many performance-critical applications. 2010 . but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. a compiler or code author targeting PTX can ignore the issue of divergent threads. However. the threads are called uniform. Both situations occur often in programs.5. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. until C is not expressive enough. and 16-bit computations are “promoted” to 32-bit computations. the optimizing code generator automatically determines points of re-convergence. A compiler or programmer may chose to enforce portable. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.

1.7.cc. The Integer arithmetic instructions are: add sub add. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 8. the optional guard predicate is omitted from the syntax.7. addc sub. 2010 63 . Instructions All PTX instructions may be predicated. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.cc.Chapter 8. In the following descriptions. Instruction Set 8.

d = a – b. Introduced in PTX ISA version 1. .s32. PTX ISA Notes Target ISA Notes Examples 64 January 24. d = a + b. Applies only to .z.sat}. PTX ISA Notes Target ISA Notes Examples Table 23. b.sat applies only to .sat limits result to MININT.s32 .u16. .s64 }.0.u64.type = { .s32 .s32 c.u32 x. a. Description Semantics Notes Performs addition and writes the resulting value into a destination register.b.s32 type.s16.s32 d. . d. b.1. 2010 .s16. b. Supported on all target architectures. Supported on all target architectures.sat applies only to . Applies only to .type sub{. add Syntax Integer Arithmetic Instructions: add Add two values. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. @p add.type = { . .a. add.y. Saturation modifier: .MAXINT (no overflow) for the size of the operation. .type add{.s64 }.0.c.sat. a.u32.u64. sub.. . add. b.s32 d.MAXINT (no overflow) for the size of the operation. Introduced in PTX ISA version 1. // .s32 type. // .u16.PTX ISA Version 2. a. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sub..0 Table 22. .s32 c.s32. .u32. Saturation modifier: . a. d.sat limits result to MININT. .sat}. .

addc{. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. . Introduced in PTX ISA version 1.2.cc.b32 x1. Supported on all target architectures.b32 addc. b. . or testing the condition code.cc specified.b32 x1. No saturation.cc. b. Table 24.z2. clearing.Chapter 8. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.y1.y4. Supported on all target architectures.cc. a.CF) holding carry-in/carry-out or borrowin/borrow-out. Instruction Set Instructions add. x4. x2.y4.CF. x3.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.z3.z3. 2010 65 .s32 }. d = a + b + CC. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.cc.cc.b32 addc.y2.cc. d = a + b. if .cc Syntax Integer Arithmetic Instructions: add.u32. These instructions support extended-precision integer addition and subtraction. a.z1. .CF No integer rounding modifiers. @p @p @p @p add. sub.z4.cc. carry-out written to CC.s32 }. @p @p @p @p add.y1.CF No integer rounding modifiers. Behavior is the same for unsigned and signed integers.b32 addc.cc. Introduced in PTX ISA version 1.b32 addc.z4.cc Add two values with carry-out.b32 addc. carry-out written to CC. addc. .cc. x2.cc.type d.2. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. x3.z1.b32 addc. add.z2.type = { .type = {. No saturation.u32. x4. and there is no support for setting. Behavior is the same for unsigned and signed integers. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.y3.cc}.type d.y3.y2. No other instructions access the condition code. add. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.

cc. x3. @p @p @p @p sub.PTX ISA Version 2.cc. No saturation.cc Syntax Integer Arithmetic Instructions: sub. a. Introduced in PTX ISA version 1.z4.b32 x1.3. d = a .y2. x4. . Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.s32 }.s32 }.y3. with borrow-out. if .cc}.z1.b32 subc.b32 subc. b.CF No integer rounding modifiers. .0 Table 26. No saturation.cc.b32 subc.CF No integer rounding modifiers.y3. Introduced in PTX ISA version 1.CF).type = {.y4. Behavior is the same for unsigned and signed integers.u32. subc{.z3. @p @p @p @p sub.z2. x2. x3.type = { . withborrow-in and optional borrow-out.y1. borrow-out written to CC. sub.cc specified.type d.z2.y1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Behavior is the same for unsigned and signed integers. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.z4. Supported on all target architectures.cc.b32 subc.z3.y4.u32. d = a – b.3. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.z1. sub. .y2.cc.b32 subc.b32 subc. Supported on all target architectures. x4. a.b32 x1. borrow-out written to CC. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.cc Subract one value from another.cc.cc.(b + CC. .cc. b.cc.type d. 2010 . x2.

lo variant Notes The type of the operation represents the types of the a and b operands. .x.u64. t = a * b. The .hi variant // for .lo.. mul.0>. // 16*16 bits yields 32 bits // 16*16 bits. mul.. Supported on all target architectures. d = t<n-1. b.n>. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // for .type = { . .wide is specified. If . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.. Instruction Set Table 28.hi or ..y.0.wide suffix is supported only for 16. a.s16.lo.s32.s16 fa.u16.fys. then d is the same size as a and b.u32.s16 fa. mul{.Chapter 8.wide // for . creates 64 bit result January 24. d = t. .and 32-bit integer types. and either the upper or lower half of the result is written to the destination register. Description Semantics Compute the product of two values. mul. d = t<2n-1. .wide.fxs.type d.s32 z. save only the low 16 bits // 32*32 bits.s64 }. . n = bitwidth of type. then d is twice as wide as a and b to receive the full result of the multiplication.wide}.fys.wide.fxs.hi. 2010 67 . If .lo is specified. .

// for .and 32-bit integer types.lo.q. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. b..MAXINT (no overflow) for the size of the operation. a.wide}. If .s32 d. t n d d d = = = = = a * b.n> + c.0> + c.hi variant // for . d. Supported on all target architectures. . Description Semantics Multiplies two values and adds a third.0.s32 d..a..sat. mad.u64. 68 January 24.u16.lo.lo. . Saturation modifier: .s16. and either the upper or lower half of the result is written to the destination register.type mad. .hi or . mad{. t<2n-1. @p mad. bitwidth of type.0 Table 29.wide suffix is supported only for 16. a. c.s32. . c.s32 type in .lo is specified. The .r.type = { .lo variant Notes The type of the operation represents the types of the a and b operands. 2010 . b. then d and c are twice as wide as a and b to receive the result of the multiplication.. t<n-1. . Applies only to .u32. .hi. then d and c are the same size as a and b.c.wide // for .PTX ISA Version 2.p.s32 r.sat limits result to MININT..hi. t + c.s64 }.hi mode.b. and then writes the resulting value into a destination register. If .wide is specified.

b.u32. // for . mul24.lo}. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values..hi. Instruction Set Table 30.s32 d. All operands are of the same type and size. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .lo. d = t<31.hi may be less efficient on machines without hardware support for 24-bit multiply. 2010 69 .lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.e.a. d = t<47. // low 32-bits of 24x24-bit signed multiply. mul24.Chapter 8.0. a. 48bits. and return either the high or low 32-bits of the 48-bit result. January 24. i. t = a * b. b.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. Supported on all target architectures.hi variant // for .hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.16>.. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.0>.type d.type = { . mul24. ..s32 }. mul24. mul24{.

t = a * b. mad24. All operands are of the same type and size.hi.s32 type in . Supported on all target architectures. mad24.type mad24. Description Compute the product of two 24-bit integer values held in 32-bit source registers.0 Table 31.lo. c.16> + c. mad24. 70 January 24. d = t<47.sat.lo}. a.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .hi.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. mad24{.PTX ISA Version 2. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.b. ..hi mode.c..MAXINT (no overflow). b.. Return either the high or low 32-bits of the 48-bit result.. a.hi may be less efficient on machines without hardware support for 24-bit multiply. Applies only to .s32 d. 32-bit value to either the high or low 32-bits of the 48-bit result.type = { . 48bits. d = t<31. i.hi variant // for . d.a.sat limits result of 32-bit signed addition to MININT.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.e. and add a third.s32 d.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.u32.0> + c. Saturation modifier: . b. c. 2010 . // low 32-bits of 24x24-bit signed multiply.s32 }. // for . mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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popc requires sm_20 or later. popc. X.b32 clz. 2010 . a.type d. a. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. clz requires sm_20 or later. inclusively.type d.b64 d.u32 Semantics 74 January 24. .0. . clz.b32 type.0 Table 39. . // cnt is .b64 type. } else { max = 64. cnt. popc Syntax Integer Arithmetic Instructions: popc Population count. } while (d < max && (a&mask == 0) ) { d++.b64 }.b32. inclusively.0. For . .b32) { max = 32. the number of leading zeros is between 0 and 64. // cnt is .b32. the number of leading zeros is between 0 and 32. popc. d = 0. X. a. a = a >> 1. while (a != 0) { if (a&0x1) d++. a.b32 popc. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { . For . cnt. a = a << 1.b64 d. mask = 0x80000000. } Introduced in PTX ISA version 2. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. d = 0.type == .type = { .u32 PTX ISA Notes Target ISA Notes Examples Table 40.PTX ISA Version 2. clz.b64 }. if (. mask = 0x8000000000000000. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.

u32 || . i--) { if (a & (1<<i)) { d = i. a. i>=0. For signed integers. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. If . .type bfind.type d. bfind. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.shiftamt.type==.u64. // cnt is .s32) ? 31 : 63.Chapter 8. d = -1. bfind returns the bit position of the most significant “1”. and operand d has type . bfind returns 0xFFFFFFFF if no non-sign bit is found. . Semantics msb = (. bfind requires sm_20 or later. a. For unsigned integers. Instruction Set Table 41. bfind.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.d.u32 January 24.shiftamt is specified. bfind. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. . X.u32 d.u32. break. } } if (.shiftamt.shiftamt && d != -1) { d = msb .type = { . d. for (i=msb.u32.s32.s64 }. Description Find the bit position of the most significant non-sign bit in a and place the result in d. 2010 75 .s64 cnt. .0. Operand a has the instruction type. a.

type = { . Description Semantics Perform bitwise reversal of input. msb = (. 2010 . brev. 76 January 24.b32) ? 31 : 63. brev requires sm_20 or later. brev. i++) { d[i] = a[msb-i]. . a.b32 d.0.b32. a. .type==.0 Table 42. i<=msb.type d.b64 }. for (i=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.PTX ISA Version 2. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.

If the start position is beyond the msb of the input.type==.s32.u64 || len==0) sbit = 0.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.u32 || . Semantics msb = (. 2010 77 . pos = b.type = { .type==.u32 || . bfe. and source c gives the bit field length in bits.a. Instruction Set Table 43.u32. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. .u64: . .Chapter 8. .b32 d. The sign bit of the extracted field is defined as: . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. otherwise If the bit field length is zero. January 24.type==. bfe requires sm_20 or later. bfe. Description Extract bit field from a and place the zero or sign-extended result in d. if (.msb)].u32.type==.0.s32.u64. Operands a and d have the same type as the instruction type. . len = c. Source b gives the bit field starting bit position. a. .len. i<=msb.s64 }.start.type d. The destination d is padded with the sign bit of the extracted field. else sbit = a[min(pos+len-1. .s32) ? 31 : 63. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. c. the destination d is filled with the replicated sign bit of the extracted field. d = 0. and operands b and c are type . b. for (i=0. the result is zero.

type f. and place the result in f.len. If the bit field length is zero. pos = c. Semantics msb = (. len = d. i++) { f[pos+i] = a[i]. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . bfi.0 Table 44.0.u32. bfi. c. the result is b. d. i<len && pos+i<=msb. b. and f have the same type as the instruction type. for (i=0.b32. 78 January 24. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.b.type==. . and operands c and d are type .b32) ? 31 : 63.b32 d. bfi requires sm_20 or later. and source d gives the bit field length in bits. b. a.PTX ISA Version 2. 2010 .b64 }. Description Align and insert a bit field from a into b. f = b. If the start position is beyond the msb of the input. Source c gives the starting bit position for the insertion.type = { .start.a. the result is b. Operands a.

2010 79 .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.Chapter 8.ecl. b. as a 16b permute code. a 4-bit selection value is defined. b0}}. Instruction Set Table 45. b6. . msb=0 means copy the literal value.b1 source select c[7:4] d.rc8. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.mode = { . . the permute control consists of four 4-bit selection values. Description Pick four arbitrary bytes from two 32-bit registers. . The bytes in the two source registers are numbered from 0 to 7: {b. b1. b5. .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. For each byte in the target register. b2. Thus. {b3.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. default mode index d. . c. prmt.b32{. The msb defines if the byte value should be copied.rc16 }.b4e. a} = {{b7.b3 source select c[15:12] d.b2 source select c[11:8] d.mode} d.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. a. . and reassemble them into a 32-bit destination register. In the generic form (no mode specified). msb=1 means replicate the sign.f4e. b4}. Note that the sign extension is only performed as part of generic form. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. the four 4-bit values fully specify an arbitrary byte permute.ecr.

f4e r1. } tmp[07:00] = ReadByte( mode. r2.0.0 Semantics tmp64 = (b<<32) | a. ctl[3] = (c >> 12) & 0xf.PTX ISA Version 2. tmp64 ). r3. ctl[1]. prmt. tmp64 ). ctl[1] = (c >> 4) & 0xf. r4. r4. ctl[2].b32. r2. tmp64 ). prmt requires sm_20 or later. tmp[31:24] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r3. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. 80 January 24. tmp64 ). ctl[3].b32 prmt. ctl[0]. tmp[23:16] = ReadByte( mode. r1. tmp[15:08] = ReadByte( mode. ctl[2] = (c >> 8) & 0xf. 2010 .

2.7. 2010 81 .f32 and .Chapter 8. Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on .

ex2}. Instruction Summary of Floating-Point Instructions .rz .f64 are the same.f32 {add.rnd.sqrt}.max}.approx. Note that future implementations may support NaN payloads for single-precision instructions.approx.rn and instructions may be folded into a multiply-add.PTX ISA Version 2.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. Single-precision add. default is .rcp.max}.rnd. NaN payloads are supported for double-precision instructions.f64 {abs. sub.target sm_20 mad.approx.f32 {div. 1.f64 div.target sm_20 .0 The following table summarizes floating-point instructions in PTX.f64 mad.rnd.rn . If no rounding modifier is specified.f64 and fma. 82 January 24.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.neg.neg. {add. but single-precision instructions return an unspecified NaN.rm .sub.rn and instructions may be folded into a multiply-add. default is .target sm_1x No rounding modifier. {mad.cos.sub.f64 {sin.ftz .full. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.rnd.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.fma}.fma}.mul}.lg2.0].rp . so PTX programs should not rely on the specific single-precision NaNs being generated.f32 .sat Notes If no rounding modifier is specified. with NaNs being flushed to positive zero.f32 {mad.0. No rounding modifier.f32 are the same.rcp. mul.min.f32 {div.32 and fma.rnd.rcp. .approx. Double-precision instructions support subnormal inputs and results.rnd.f32 rsqrt. 2010 . Table 46.sqrt}. .sqrt}.min.f32 {abs.mul}. and mad support saturation of results to the range [0. The optional .f64 rsqrt.f32 {div.

type . Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. a.f64 }. copysign. not infinity) As a special case.number. . A.finite. a. .0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { . z. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. testp requires sm_20 or later. copysign.infinite.0.subnormal }. .Chapter 8. b.f64 x. true if the input is a subnormal number (not NaN. Table 48. not infinity). . testp.type = { . January 24.op.finite testp. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Introduced in PTX ISA version 2. C. copysign requires sm_20 or later. f0. positive and negative zero are considered normal numbers. 2010 83 . B. p. .f32.type d. and return the result as d. Instruction Set Table 47. testp Syntax Floating-Point Instructions: testp Test floating-point property.infinite testp.notanumber.normal.normal testp. testp.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.op p.f32. X.notanumber testp. y.f64 }.number testp. . . testp. .f64 isnan.f32 testp.f32 copysign.pred = { . // result is . .infinite.notanumber.

f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures.f64 supports subnormal numbers.0. .ftz}{.f32 add{.0.f32.sat.f64 requires sm_13 or later. a. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64 d.f64.ftz.PTX ISA Version 2.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. add.0]. add.rp for add.rm.rm mantissa LSB rounds towards negative infinity . . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rnd}{. .sat}. 1.f32 flushes subnormal inputs and results to sign-preserving zero. d. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm. b. Rounding modifiers (default is .0 Table 49.rnd = { .f32 f1.rz. 2010 .f32 clamps the result to [0. . requires sm_20 Examples @p add. NaN results are flushed to +0.0f. a.rz mantissa LSB rounds towards zero .rn. add. requires sm_13 for add. add Syntax Floating-Point Instructions: add Add two values. subnormal numbers are supported.rn. add.rn mantissa LSB rounds to nearest even . Rounding modifiers have the following target requirements: . Description Semantics Notes Performs addition and writes the resulting value into a destination register. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rnd}. .rn): . . b. add. sm_1x: add. 84 January 24. In particular.rp }. add{. d = a + b.rz.f3. Saturation modifier: .f2.rz available for all targets .

ftz. d. a.0f.rp for sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. .0]. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz}{.sat}.f32 f1.f32 clamps the result to [0. .f64 supports subnormal numbers. 2010 85 . January 24. Saturation modifier: sub. NaN results are flushed to +0. .f32 supported on all target architectures. 1.0.rz mantissa LSB rounds towards zero .a.f64. Rounding modifiers have the following target requirements: .f3. sub. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.b. sub. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero. sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn. b.f32 c.f64 requires sm_13 or later. sub Syntax Floating-Point Instructions: sub Subtract one value from another. requires sm_20 Examples sub.f32 sub{.rm.sat. sub{.rn.rn mantissa LSB rounds to nearest even .rnd}{.rnd = { .f64 d. b. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. sm_1x: sub.rz. .rm mantissa LSB rounds towards negative infinity .rnd}.b. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sub. requires sm_13 for sub.rm. In particular. sub. Rounding modifiers (default is .f32.rn.ftz. Instruction Set Table 50. a.rn): . d = a .f32 flushes subnormal inputs and results to sign-preserving zero.rp }.f2.0.rz available for all targets .Chapter 8.

mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.ftz. requires sm_20 Examples mul.f32 clamps the result to [0.rnd}{. mul.rnd}.f32 mul{. mul. NaN results are flushed to +0. mul. requires sm_13 for mul.sat}.rp for mul.rn mantissa LSB rounds to nearest even . Rounding modifiers have the following target requirements: . For floating-point multiplication.0].PTX ISA Version 2.rn.f32. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz.rm mantissa LSB rounds towards negative infinity . Description Semantics Notes Compute the product of two values.f32 flushes subnormal inputs and results to sign-preserving zero. 1.f64.f32 flushes subnormal inputs and results to sign-preserving zero. In particular. a.ftz}{.f64 d. mul{. sm_1x: mul.f32 circumf. subnormal numbers are supported.rn.sat. Saturation modifier: mul.rnd = { . mul.rz mantissa LSB rounds towards zero .rn): . a. . .rm. d = a * b. Rounding modifiers (default is .0f. all operands must be the same size.f64 supports subnormal numbers. .0 Table 51. mul Syntax Floating-Point Instructions: mul Multiply two values. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rm.0. b.pi // a single-precision multiply 86 January 24. 2010 . A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0.ftz. d.radius. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64 requires sm_13 or later.f32 supported on all target architectures.rz available for all targets .rp }. . b.

ftz}{.rn.rnd. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add.rp }. c.f64 w. d = a*b + c.rnd.f32 introduced in PTX ISA version 2. again in infinite precision.f32 fma. sm_1x: fma. 1. fma.rz. d.rn.x. Rounding modifiers (no default): . 2010 87 . PTX ISA Notes Target ISA Notes Examples January 24.a. fma.rnd{. again in infinite precision. .f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 52. . .rz mantissa LSB rounds towards zero .0. b.f32 fma. subnormal numbers are supported.rn mantissa LSB rounds to nearest even .f64 d.rnd = { .ftz. b. @p fma. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f64.sat. fma.rm mantissa LSB rounds towards negative infinity .f32 is unimplemented in sm_1x.ftz.z.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm. c. The resulting value is then rounded to double precision using the rounding mode specified by . fma.4.f64 is the same as mad.b.f32 computes the product of a and b to infinite precision and then adds c to this product.Chapter 8.0].0f. d. fma.0. a. NaN results are flushed to +0. fma. a.f32 clamps the result to [0. .f64 supports subnormal numbers. Saturation: fma. fma. The resulting value is then rounded to single precision using the rounding mode specified by .rnd.c. fma.sat}. fma.f64 introduced in PTX ISA version 1.rn.y.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 requires sm_20 or later.

f32 computes the product of a and b at double precision.f64 supports subnormal numbers.0. again in infinite precision.target sm_13 and later .f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. c.PTX ISA Version 2. Note that this is different from computing the product with mul.f32 clamps the result to [0. mad.f64.f32 is identical to the result computed using separate mul and add instructions. mad{.rp }.{f32. The resulting value is then rounded to double precision using the rounding mode specified by .f32). sm_1x: mad. .0f.sat}.f32 flushes subnormal inputs and results to sign-preserving zero. c. 88 January 24.f32.target sm_1x: mad.target sm_20 d.0].rn mantissa LSB rounds to nearest even .rnd. NaN results are flushed to +0.0.rnd.ftz. the treatment of subnormal inputs and output follows IEEE 754 standard. // . mad.rnd. For .0 devices. and then the mantissa is truncated to 23 bits. 1. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.target sm_1x d. Description Semantics Notes Multiplies two values and adds a third.rn.f64 computes the product of a and b to infinite precision and then adds c to this product. mad.ftz}{.f32 mad. Saturation modifier: mad.{f32.rm. The resulting value is then rounded to double precision using the rounding mode specified by . // .f32 is when c = +/-0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. When JIT-compiled for SM 2. and then writes the resulting value into a destination register. The exception for mad.f32 mad. b.f64}. mad.sat}. mad. b. 2010 .sat.rm mantissa LSB rounds towards negative infinity . .f64} is the same as fma. c.target sm_20: mad.f64 is the same as fma. mad. fma. d = a*b + c.. mad. b.rnd. For .rnd = { . a. In this case. // .f32 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero.rz mantissa LSB rounds towards zero . a. where the mantissa can be rounded and the exponent will be clamped. a.f64 d.rnd{.f32 is implemented as a fused multiply-add (i. The resulting value is then rounded to single precision using the rounding mode specified by . . mad.ftz. Rounding modifiers (no default): . again in infinite precision. but the exponent is preserved.rn.0 Table 53. again in infinite precision. mad.f64 computes the product of a and b to infinite precision and then adds c to this product. subnormal numbers are supported. Unlike mad.ftz}{.rz.e.

c.f64 instructions having no rounding modifier will map to mad.f64... Rounding modifiers have the following target requirements: .0..rn. a rounding modifier is required for mad..f64 requires sm_13 or later. mad. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f64. January 24.4 and later. Target ISA Notes mad. Legacy mad.rn. In PTX ISA versions 1.rp for mad. a rounding modifier is required for mad.f32 for sm_20 targets.a..f32 supported on all target architectures.f64.rm.Chapter 8..f32.b.rn. requires sm_13 . In PTX ISA versions 2.0 and later. requires sm_20 Examples @p mad.rz.rz. 2010 89 .rm.f32 d.rp for mad.

approx{.approx. d.0 through 1.f64 defaults to div. div Syntax Floating-Point Instructions: div Divide one value by another.rn.approx.f32 flushes subnormal inputs and results to sign-preserving zero. b.4.f64 requires sm_20 or later. For PTX ISA versions 1.f32 supported on all target architectures.rn mantissa LSB rounds to nearest even .rnd{.rp}. a. div. one of .rm mantissa LSB rounds towards negative infinity . div.f32 defaults to div. Subnormal inputs and results are flushed to sign-preserving zero. div.rn.f32 implements a fast approximation to divide. div. .f64 introduced in PTX ISA version 1.ftz. div. xd. a.circum.{rz.f64 diam. x.rn. but is not fully IEEE 754 compliant and does not support rounding modifiers.ftz.4 and later.rnd is required. d. approximate division by zero creates a value of infinity (with same sign as a).full{. sm_1x: div.rn. 2010 . PTX ISA Notes div. Fast. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . b.rnd. Description Semantics Notes Divides a by b.ftz}.f32 div.f32 div.f32 div. The maximum ulp error is 2 across the full range of inputs. and div.f64 d. div. y. Fast. z.3.f32 div.ftz}.f32 and div. .rm. the maximum ulp error is 2. approximate single-precision divides: div. div.f32 and div. div. a.rnd.rnd = { .rz. . or .f64 requires sm_13 or later. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 implements a relatively fast. zd. b. For b in [2-126.ftz.ftz.full.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . // // // // fast. d = a / b. Examples 90 January 24.approx.full. 2126].rp }.f64.full. Target ISA Notes div. div. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. a.approx. yd.ftz}.approx.full.PTX ISA Version 2.ftz. .rm.3.f64 supports subnormal numbers.f32 div.rz mantissa LSB rounds towards zero . full-range approximation that scales operands to achieve better accuracy.f32 requires sm_20 or later.0. and rounding introduced in PTX ISA version 1.f32.full.approx.0 Table 54. d. stores result in d. computed as d = a * (1/b). For PTX ISA version 1. b. subnormal numbers are supported.14159. .

neg{. abs. a. d = -a.f32 x. sm_1x: neg.ftz. Subnormal numbers: sm_20: By default. Table 56. d. Instruction Set Table 55. neg.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. Take the absolute value of a and store the result in d.ftz.f32 neg. a.ftz. neg.0.ftz}. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.Chapter 8.f64 requires sm_13 or later. subnormal numbers are supported.f64 requires sm_13 or later.ftz}. Negate the sign of a and store the result in d. abs{. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. a.f0. d = |a|.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero. January 24.f64 d.f32 supported on all target architectures. Subnormal numbers: sm_20: By default.f64 d. abs.f64 supports subnormal numbers.f32 supported on all target architectures. NaN inputs yield an unspecified NaN. NaN inputs yield an unspecified NaN.ftz. d.f32 x. neg.f0. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: abs. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. neg.f32 abs. 2010 91 . a. abs. abs.

b. sm_1x: min. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.0.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 . min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. d d d d = = = = NaN. a.ftz}. min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.f32 min.c. (a > b) ? a : b.x. min.f64 requires sm_13 or later. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz. 92 January 24.f32 supported on all target architectures. max.f32 flushes subnormal inputs and results to sign-preserving zero. max. d. a. min.b.ftz}. d. a.c. max{. Store the maximum of a and b in d.f2. a. Store the minimum of a and b in d. a. a.ftz. sm_1x: max. subnormal numbers are supported. (a < b) ? a : b.f64 supports subnormal numbers. min. b. a. b. max.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. min{.PTX ISA Version 2.ftz. d d d d = = = = NaN.f64 supports subnormal numbers. b.f32 flushes subnormal inputs and results to sign-preserving zero.f32 max.b. a. max.f32 supported on all target architectures.ftz. @p min.f1.f64 f0.f64 z.0.f64 d.z. subnormal numbers are supported. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f32 min.0 Table 57.f64 requires sm_13 or later. Table 58. b.f32 max.

store result in d.f64 ri.f32 defaults to rcp.f64 d.Chapter 8.0 +0.approx.rn.0 through 1. General rounding modifiers were added in PTX ISA version 2. xi.rn mantissa LSB rounds to nearest even . rcp.rm mantissa LSB rounds towards negative infinity .0 -Inf -Inf +Inf +Inf +0.x.f64 and explicit modifiers . PTX ISA Notes rcp. a. rcp. rcp.approx or .rm.ftz. rcp.ftz}.ftz were introduced in PTX ISA version 1.0 over the range 1.f32 flushes subnormal inputs and results to sign-preserving zero.rn. d.4 and later.4.f32 rcp. d. rcp.approx. Description Semantics Notes Compute 1/a.rnd{.f64 supports subnormal numbers.0-2.f64 requires sm_13 or later.rm.0.3.f32.0. subnormal numbers are supported. . one of .ftz. // fast. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . rcp. For PTX ISA versions 1.rnd.f32 rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 implements a fast approximation to reciprocal. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f64 introduced in PTX ISA version 1.f64 defaults to rcp. Instruction Set Table 59. .approx and .f32 supported on all target architectures.f64 requires sm_20 or later.approx.rn. and rcp.ftz. Input -Inf -subnormal -0.rn.{rz. The maximum absolute error is 2-23.approx.rnd = { . a. d = 1 / a.rz. 2010 93 .rp}. rcp.f32 requires sm_20 or later.f64. a.f32 rcp. For PTX ISA version 1.ftz. .f32 rcp.approx{.0 +subnormal +Inf NaN Result -0.0. rcp.rnd.r. xi.x. rcp.rz mantissa LSB rounds towards zero . sm_1x: rcp.rp }.f32 and rcp. Examples January 24.rnd is required.rn.rn. Target ISA Notes rcp. rcp.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.

sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f32 sqrt.rp}. // IEEE 754 compliant rounding d.f32 supported on all target architectures. sqrt.f64 requires sm_13 or later.rnd.f32 requires sm_20 or later. The maximum absolute error for sqrt.0 +subnormal +Inf NaN Result NaN NaN -0. and sqrt. 2010 .f32 and sqrt.approx.0 Table 60.approx.0. approximate square root d.ftz were introduced in PTX ISA version 1.4 and later.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. a.rz.approx.rn mantissa LSB rounds to nearest even .ftz.f32 implements a fast approximation to square root.rn.{rz. // fast. sqrt.0 -0.f32 defaults to sqrt.rm. General rounding modifiers were added in PTX ISA version 2. sm_1x: sqrt.rm.approx.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. sqrt.rnd{. // IEEE 754 compliant rounding .approx or . Input -Inf -normal -subnormal -0.f32 sqrt. a.approx{.f64 introduced in PTX ISA version 1. r.ftz.f32 sqrt.0 +0.f64 r.PTX ISA Version 2.x. For PTX ISA versions 1.f64 supports subnormal numbers.f64 and explicit modifiers .f32 sqrt.4.rn.rp }. subnormal numbers are supported. sqrt.rn.f32.rn.rn.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.x.0 through 1. PTX ISA Notes sqrt.0. sqrt. Target ISA Notes sqrt.f64. Examples 94 January 24. sqrt.approx and . a. . r.3.x. For PTX ISA version 1. sqrt. .rnd.0 +0. one of .f32 is TBD.rnd = { .0 +0. sqrt.f64 defaults to sqrt.rz mantissa LSB rounds towards zero .ftz.ftz}.rnd is required. sqrt.rm mantissa LSB rounds towards negative infinity . Description Semantics Notes Compute sqrt(a).f64 requires sm_20 or later. d = sqrt(a). sqrt.rn.ftz}.approx. . store in d.

0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f64 is emulated in software and are relatively slow.f32 rsqrt. d.approx. Compute 1/sqrt(a). store the result in d.f64.f64 requires sm_13 or later.approx. the .approx.ftz.f64 were introduced in PTX ISA version 1.approx.f32 defaults to rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.4 over the range 1. Subnormal numbers: sm_20: By default. The maximum absolute error for rsqrt. Explicit modifiers . January 24. Target ISA Notes Examples rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is 2-22. rsqrt.Chapter 8.approx. rsqrt. PTX ISA Notes rsqrt.f64 is TBD.approx. and rsqrt.approx modifier is required.approx implements an approximation to the reciprocal square root. For PTX ISA versions 1. rsqrt. rsqrt. Note that rsqrt. subnormal numbers are supported.f32 supported on all target architectures.4. Input -Inf -normal -subnormal -0. a. 2010 95 . ISR. For PTX ISA version 1.0-4.approx and .0 NaN The maximum absolute error for rsqrt. rsqrt.ftz were introduced in PTX ISA version 1.0.ftz}.f64 supports subnormal numbers. a.f32 and rsqrt.f64 defaults to rsqrt. Instruction Set Table 61.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero.4 and later. d = 1/sqrt(a). rsqrt.f64 isr.ftz.f32 rsqrt. x.f32.approx{. sm_1x: rsqrt.3.f64 d. rsqrt.0 +0.ftz. X.0.

Find the sine of the angle a (in radians). PTX ISA Notes sin. sm_1x: Subnormal inputs and results to sign-preserving zero.approx. Target ISA Notes Examples Supported on all target architectures.f32 sa.approx.0 Table 62.ftz}. For PTX ISA version 1.4 and later. sin. 96 January 24.ftz. Explicit modifiers .0 +0.f32.9 in quadrant 00.f32 flushes subnormal inputs and results to sign-preserving zero.4. sin.approx modifier is required.approx{.f32 defaults to sin.0 through 1. For PTX ISA versions 1.0.0 -0.approx.0 NaN NaN The maximum absolute error is 2-20. a. 2010 .0 +0. a. the .PTX ISA Version 2. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. subnormal numbers are supported.ftz.approx and .ftz introduced in PTX ISA version 1.0 +0.3. Subnormal numbers: sm_20: By default. sin.f32 implements a fast approximation to sine. sin.0 +subnormal +Inf NaN Result NaN -0.f32 introduced in PTX ISA version 1. d = sin(a). sin. Input -Inf -subnormal -0.ftz.f32 d.

cos.0 NaN NaN The maximum absolute error is 2-20. subnormal numbers are supported.0 +subnormal +Inf NaN Result NaN +1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 through 1.approx.approx modifier is required.ftz introduced in PTX ISA version 1. the . Subnormal numbers: sm_20: By default. cos.9 in quadrant 00.ftz}.f32 ca.0 +1.0. PTX ISA Notes cos.0 +1.f32.0 +1. d = cos(a). Target ISA Notes Examples Supported on all target architectures.3. a.approx.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. January 24. cos. 2010 97 . cos.4. Find the cosine of the angle a (in radians). cos. Input -Inf -subnormal -0.approx and .0 +0.ftz.4 and later. For PTX ISA versions 1. a.f32 introduced in PTX ISA version 1. For PTX ISA version 1. Instruction Set Table 63.f32 defaults to cos.Chapter 8.f32 d.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.approx. Explicit modifiers .approx{.f32 implements a fast approximation to cosine.

d = log(a) / log(2). a. the . lg2. Target ISA Notes Examples Supported on all target architectures.approx modifier is required.f32 implements a fast approximation to log2(a).4. Input -Inf -subnormal -0.f32 introduced in PTX ISA version 1.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.PTX ISA Version 2.f32 defaults to lg2.ftz}. 98 January 24.ftz introduced in PTX ISA version 1.approx. subnormal numbers are supported.ftz. PTX ISA Notes lg2.f32 la.ftz.0 through 1.6 for mantissa.0 Table 64.4 and later. For PTX ISA version 1.f32 Determine the log2 of a. Subnormal numbers: sm_20: By default. sm_1x: Subnormal inputs and results to sign-preserving zero. The maximum absolute error is 2-22.ftz.approx.approx and . lg2. a.f32.0 +0.0. lg2. For PTX ISA versions 1.approx.3.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers . 2010 . lg2. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. lg2.approx{.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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setp. . setp. To aid comparison operations in the presence of NaN values. A related value computed using the complement of the compare result is written to the second destination operand.a. If either operand is NaN. higher. gt. @q setp. ne. hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. the result is false. p[|q].s32. ne.type setp. setp. ge. p. and hs for lower. p[|q]. geu. neu.dtype. le.CmpOp. gt.ftz applies only to . .u32. Semantics t = (a CmpOp b) ? 1 : 0. gtu. Subnormal numbers: sm_20: By default. le. . If both operands are numeric values (not NaN). setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. Modifier . neu. setp with .f32.b32.s16. For unsigned values. num. lt. subnormal numbers are supported. and (optionally) combine this result with a predicate value by applying a Boolean operator.b16. and higher-or-same may be used instead of lt. gt. c). lt.ftz. loweror-same. ge. . The signed and unsigned comparison operators are eq.f64 }. q = BoolOp(!t. leu.f64 supports subnormal numbers.lt. xor. 102 January 24. unordered versions are included: equ. bit-size comparisons are eq and ne.ftz}. b.r. The comparison operator is a suffix on the instruction. then these comparisons have the same result as their ordered counterparts.and.CmpOp{. ltu. ltu.0 Table 67. le. .B) is one of: and.b. num returns true if both operands are numeric values (not NaN).ftz}. . ls.n. {!}c. leu. ge.PTX ISA Version 2. . or. a.f32 comparisons.0. p = BoolOp(t. Integer Notes Floating Point Notes The ordered comparisons are eq.b64. ne. If either operand is NaN. le. lo. c).eq.u16. geu. The destinations p and q must be .type . .s64. gt.f32 flushes subnormal inputs to sign-preserving zero. . a.s32 setp. ge. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. lt. then the result of these comparisons is true. and nan returns true if either operand is NaN. This result is written to the first destination operand. .i. 2010 .f32 flushes subnormal inputs to sign-preserving zero. ls.dtype. gtu. hi.u64. and can be one of: eq. The untyped.f64 source type requires sm_13 or later.BoolOp{. sm_1x: setp. the comparison operators lo.type = { . b.pred variables.u32 p|q. Applies to all numeric types. nan The Boolean operator BoolOp(A. respectively.dtype. hs equ.

fval. . sm_1x: slct. a is stored in d. .s16.p.s64. slct.f32.s64.dtype. Operands d. val. . For . b. and b must be of the same type.s32 selp. . . . . Description Conditional selection. b.f64 }.s32.dtype. c. selp. . based on the value of the predicate source operand.f32.u16.r.f32 flushes subnormal values of operand c to sign-preserving zero. Semantics Floating Point Notes January 24.type d. y.type = { .0.ftz applies only to . Introduced in PTX ISA version 1. Operand c is a predicate.s32 x.f32 A. . d = (c == 1) ? a : b.b64.u64. slct. The selected input is copied to the output without modification.x. the comparison is unordered and operand b is selected. a.ftz. If operand c is NaN.s32.f32 flushes subnormal values of operand c to sign-preserving zero. a. . selp Syntax Comparison and Selection Instructions: selp Select between source operands.f32 comparisons. . If c is True. If c ≥ 0.f32 r0. 2010 103 . z.b64. selp. .f32 d.u32. slct.u64.f32 comparisons.g.u16. B. d = (c >= 0) ? a : b.b16. subnormal numbers are supported. slct Syntax Comparison and Selection Instructions: slct Select one source operand. a. and operand a is selected. slct.dtype = { . C.b16. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. . . b. a. . @q selp. a. slct.b32.ftz}.Chapter 8. Subnormal numbers: sm_20: By default.u32. and operand a is selected. c.s32 slct{.f64 requires sm_13 or later. . Operands d.s16. Instruction Set Table 68.dtype. operand c must match the second instruction type. c.f64 requires sm_13 or later. .u32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Modifier . . and b are treated as a bitsize type of the same width as the first instruction type. d. Table 69. based on the sign of the third operand. . a is stored in d. negative zero equals zero.f64 }. . otherwise b is stored in d.b32. . f0.ftz.dtype. .t.0. b otherwise.u64.xp.

This permits bit-wise operations on floating point values without having to define a union to access the bits. provided the operands are of the same size. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. performing bit-wise operations on operands of any type. or. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4. xor.7.PTX ISA Version 2.0 8. 2010 . and not also operate on predicates. Instructions and.

Allowed types include predicate registers.0x00010001 or. Supported on all target architectures. Instruction Set Table 70. or.Chapter 8. a.b16. Introduced in PTX ISA version 1.0x80000000. Table 71. Allowed types include predicate registers. The size of the operands must match. .pred.q. or. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. d = a | b. but not necessarily the type. .b64 }.b32 mask mask.b32 and. .type d.b32 x.r. . or Syntax Logic and Shift Instructions: or Bitwise OR. and. a.fpvalue.b32. and. .b16.pred p. . and Syntax Logic and Shift Instructions: and Bitwise AND. b. The size of the operands must match. d = a & b.0. sign.b64 }.0. but not necessarily the type. 2010 105 . Supported on all target architectures. January 24.pred.q. b.type d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. .r.type = { .type = { .b32. Introduced in PTX ISA version 1.

cnot.b64 }. Introduced in PTX ISA version 1. but not necessarily the type. .b16.0x0001. not.0. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. not. a.type d.0 Table 72. .b16. The size of the operands must match. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).pred.type = { .PTX ISA Version 2. Allowed types include predicate registers. . d = ~a. The size of the operands must match.b32. Allowed types include predicates. Supported on all target architectures.b32 xor.q.type = { . Supported on all target architectures.a.b32 mask. .x. Supported on all target architectures.q. .mask. Table 74. Table 73. Introduced in PTX ISA version 1.b16 d. .0.type d. .b64 }. a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. The size of the operands must match. but not necessarily the type. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b32.pred. not Syntax Logic and Shift Instructions: not Bitwise negation.b16. cnot.type = { .b32 d. xor. . d.r. but not necessarily the type. . b. d = a ^ b. Introduced in PTX ISA version 1.b64 }.b32. xor.pred p. a. 2010 . one’s complement.type d. 106 January 24.0. not. d = (a==0) ? 1 : 0. .

i. shl.u64.a.j. Introduced in PTX ISA version 1. b. Instruction Set Table 75.i.type d.b32. . . shl. Shift amounts greater than the register width N are clamped to N. Bit-size types are included for symmetry with SHL.u32.2. regardless of the instruction type. The sizes of the destination and first source operand must match. .s16. shr Syntax Logic and Shift Instructions: shr Shift bits right. regardless of the instruction type. i.type d. The b operand must be a 32-bit value. d = a << b.1. but not necessarily the type.2.a. Introduced in PTX ISA version 1. Supported on all target architectures. sign or zero fill on left. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.u16 shr.b16. PTX ISA Notes Target ISA Notes Examples Table 76.s32.b16 c. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. Signed shifts fill with the sign bit.b64 }. .type = { . .u16. d = a >> b. .type = { .b16. but not necessarily the type. The sizes of the destination and first source operand must match. . 2010 107 .Chapter 8. Shift amounts greater than the register width N are clamped to N.s32 shr. a. . PTX ISA Notes Target ISA Notes Examples January 24. shl Syntax Logic and Shift Instructions: shl Shift bits left. k.0.s64 }. shr. . . unsigned and untyped shifts fill with 0. shr.b64. . . Supported on all target architectures.b32. b. The b operand must be a 32-bit value. a.b32 q. zero-fill on right.0.

The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.PTX ISA Version 2. or shared state spaces. suld. possibly converting it from one format to another. 2010 . local. st.5. ld. and sust support optional cache operations. The cvta instruction converts addresses between generic and global. Data Movement and Conversion Instructions These instructions copy data from place to place. Instructions ld. mov.7. and st operate on both scalar and vector types. ldu.0 8. prefetchu isspacep cvta cvt 108 January 24. and from state space to state space. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.

lu instruction performs a load cached streaming operation (ld. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Instruction Set 8.ca. Global data is coherent at the L2 level. evict-first.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. . The ld. invalidates (discards) the local L1 line following the load. . As a result of this request. The ld. . fetch again).ca. likely to be accessed once. and cache only in the L2 cache.cg to cache loads only globally. and a second thread loads that address via a second L1 cache with ld. For sm_20 and later.cs. when applied to a local address.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. Operator . If one thread stores to global memory via one L1 cache. January 24.5.lu Last use.lu load last use operation. The cache operators require a target architecture of sm_20 or later.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The default load instruction cache operation is ld.Chapter 8. The compiler / programmer may use ld. Table 77. rather than the data stored by the first thread. the cache operators have the following definitions and behavior.cs) on global addresses. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. any existing cache lines that match the requested address in L1 will be evicted.cs is applied to a Local window address.7.cv to a frame buffer DRAM address is the same as ld.lu operation. the second thread may get stale L1 cache data.0 introduces optional cache operators on load and store instructions.cg Cache at global level (cache in L2 and below. Cache Operators PTX 2. . likely to be accessed again. The ld. it performs the ld. if the line is fully covered. 2010 109 .ca loads cached in L1.1. to allow the thread program to poll a SysMem location written by the CPU. but multiple L1 caches are not coherent for global data.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cv Cache as volatile (consider cached system memory lines stale.cs Cache streaming. The ld. When ld. not L1). A ld. Use ld. bypassing the L1 cache.

PTX ISA Version 2. and marks local L1 lines evict-first. regardless of the cache operation. bypassing its L1 cache. the second thread may get a hit on stale L1 cache data.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cg Cache at global level (cache in L2 and below. rather than get the data from L2 or memory stored by the first thread. The st. bypassing the L1 cache. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. st.wb could write-back global store data from L1.wt Cache write-through (to system memory). but st.wt store write-through operation applied to a global System Memory address writes through the L2 cache.wt. . In sm_20. and discard any L1 lines that match. 110 January 24. Use st. which writes back cache lines of coherent cache levels with normal eviction policy. likely to be accessed once.cg is the same as st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.0 Table 78. and cache only in the L2 cache. and a second thread in a different SM later loads from that address via a different L1 cache with ld. Future GPUs may have globally-coherent L1 caches. Global stores bypass L1. Addresses not in System Memory use normal write-back. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. The st. However. . .wb. Operator .cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. in which case st. The default store instruction cache operation is st. 2010 .cs Cache streaming.ca loads. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. If one thread stores to global memory.cg to cache global store data only globally.ca.wb for global data. to allow a CPU program to poll a SysMem location written by the GPU with st. not L1).cg to local memory uses the L1 cache.

f32 mov.u32. . Write register d with the value of a.u32 d.u64. The generic address of a variable in global. Description . Semantics d = a. d.u16 mov. a. or function name.type = { . Note that if the address of a device function parameter is moved to a register. For variables declared in . d. . i.a. avar.f64 }. special register.s64. local. k.type mov. the parameter will be copied onto the stack and the address will be in the local state space. . and . local. u. d = &avar.Chapter 8. mov places the non-generic address of the variable (i. A.0. // address is non-generic. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. .f32. or shared state space may be taken directly using the cvta instruction. d = sreg.type mov.e.pred. mov.e. the address of the variable in its state space) into the destination register. alternately. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. local.f32 mov. Introduced in PTX ISA version 1. d = &label. .u32 mov..type mov.shared state spaces.v. immediate.b32. // get address of variable // get address of label or function .u32 mov.0. mov. sreg. . ptr. addr. d. Operand a may be a register. Instruction Set Table 79. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.f64 requires sm_13 or later.const.s32. mov.b64.s16. label. .global. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. variable in an addressable memory space. within the variable’s declared state space Notes Although only predicate and bit-size types are required. 2010 111 . . or shared state space.type d..local.b16. . the generic address of a variable declared in global. ptr. .1. Take the non-generic address of a variable in global. label. . . A[5]. myFunc.u16.

15] } // unpack 8-bit elements from .b have type ... d.x | (a.0.w } = { a[0.b16.{x. a[24.. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. d.u8 // unpack 32-bit elements from . d.x | (a.y << 16) d = a.hi}..y.31] } // unpack 16-bit elements from .31].47].z.b32 { d. lo.b32 mov.y } = { a[0..u16 %x is a double. {r.15].b32.z << 32) | (a.b16 // pack four 8-bit elements into .x..31].b. or write vector register d with the unpacked values from scalar register a.. a[48. a[16.b8 r.y } = { a[0.w have type . mov.y..b64 // pack two 32-bit elements into .a have type .b32 mov.u32 x. a[8.g.63] } // unpack 16-bit elements from . 2010 . d.w}.w } = { a[0.z. {lo.0 Table 80.b64 }.y << 16) | (a. a[16. Description Write scalar register d with the packed value of vector register a. a[32. // // // // a.a}.b.b64 { d.. For bit-size types.b32 %r1.b32 // pack two 16-bit elements into ..z << 16) | (a. d.15].x | (a.y << 8) | (a.x.b64 { d.x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).7].. %x.x | (a.w << 24) d = a. a[8. d. d.z.b16 { d. d.PTX ISA Version 2.y << 8) d = a..7]. Semantics d = a.b64 112 January 24. a.x.y. mov.31] } // unpack 8-bit elements from . d. .y.y } = { a[0.type d.{a.hi are .x | (a.y << 32) // pack two 8-bit elements into .g.15]. .. . a[32.b32 // pack four 16-bit elements into .23]. %r1.type = { .b}.x. a[16. Supported on all target architectures.b32 { d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.%r1.z.w << 48) d = a.b64 mov..

. 2010 113 . . .ss}{.b8.const.v2.f32. d. d. ld{.volatile introduced in PTX ISA version 1. d. Semantics d d d d = = = = a.b16.e.const space suffix may have an optional bank number to indicate constant banks other than bank zero. Generic addressing may be used with ld.type . *(a+immOff).reg state space.volatile.s8.lu.f64 }. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . and is zeroextended to the destination register width for unsigned and bit-size types. Generic addressing and cache operations introduced in PTX ISA 2. i. .f16 data may be loaded using ld. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.type ld. the resulting behavior is undefined.shared }. to enforce sequential consistency between threads accessing shared memory. . 32-bit). Cache operations are not permitted with ld.v4 }. The address size may be either 32-bit or 64-bit. In generic addressing.global. .s32. for example.volatile{. .. Within these windows. .type d.cv }.b32.ss}. *a. or [immAddr] an immediate absolute byte address (unsigned. an integer or bit-size type register reg containing a byte address.type ld{. . . . The address must be naturally aligned to a multiple of the access size. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. If an address is not properly aligned. [a].cop}.ss}{. .vec. *(immAddr).b64. The .f64 using cvt. and truncated if the register width exceeds the state space address width for the target architecture. PTX ISA Notes January 24. [a]. A destination register wider than the specified type may be used.ss = { .vec = { . [a].u32.f32 or .cop}. ld.cs.cg. Description Load register variable d from the location specified by the source address operand a in specified state space. perform the load using generic addressing.local.volatile. Addresses are zero-extended to the specified width as needed.u8.Chapter 8.u16. ld.volatile may be used with . . .0.e.0. .vec.1. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. i.b16. . and then converted to . If no state space is given.type = { . . .s16. The value loaded is sign-extended to the destination register width for signed integers. .u64.param.ca. Instruction Set Table 81.global and .volatile{. an address maps to the corresponding location in local or shared memory. . 32-bit).cop = { . ld introduced in PTX ISA version 1.s64. an address maps to global memory unless it falls within the local memory window or the shared memory window. . or the instruction may fault.ss}. . [a]. This may be used.shared spaces to inhibit optimization of references to volatile memory.

const[4]. // negative offset %r.f16 d.[fs].[a].shared.global. Cache operations require sm_20 or later.s32 ld.const. x.b32 ld. Generic addressing requires sm_20 or later.f64 requires sm_13 or later.b32 ld.[buffer+64].[p+4].0 Target ISA Notes ld. d.%r.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[240].b64 ld.v4.[p]. %r.b32 ld.f32 ld.PTX ISA Version 2. Q.f32. // load . // access incomplete array x.[p+-8].b16 cvt.global.local.local. ld. // immediate address %r. 2010 .

type d. or the instruction may fault. ldu. i. [a].[p]. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . the access may proceed by silently masking off low-order address bits to achieve proper rounding. Addresses are zero-extended to the specified width as needed. The value loaded is sign-extended to the destination register width for signed integers.b16.ss = { . . and truncated if the register width exceeds the state space address width for the target architecture. .u64. 32-bit). [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Introduced in PTX ISA version 2. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.global }. . d. Within these windows. // load from address // vec load from address . [areg] a register reg containing a byte address. Semantics d d d d = = = = a.. 2010 115 .global.s8.s64.reg state space.global.f64 requires sm_13 or later.ss}. the resulting behavior is undefined.b32 d.0. perform the load using generic addressing.v4 }. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.v2. . ldu. only generic addresses that map to global memory are legal. The data at the specified address must be read-only. i. Instruction Set Table 82. or [immAddr] an immediate absolute byte address (unsigned.v4.type ldu{. . . If no state space is given. PTX ISA Notes Target ISA Notes Examples January 24.vec = { .[a].Chapter 8. .global.s16. .b64.s32. ldu{.f32 or .f16 data may be loaded using ldu.[p+4]. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.u8. an address maps to global memory unless it falls within the local memory window or the shared memory window. The addressable operand a is one of: [avar] the name of an addressable variable var. [a]. . where the address is guaranteed to be the same across all threads in the warp.u16.b16. an address maps to the corresponding location in local or shared memory. and is zeroextended to the destination register width for unsigned and bit-size types.e.f32. The address must be naturally aligned to a multiple of the access size. // state space .f64 }. ldu.vec. . For ldu. A register containing an address may be declared as a bit-size type or integer type. A destination register wider than the specified type may be used. . .b32.u32.f64 using cvt. . *(a+immOff).e. *a. . If an address is not properly aligned. In generic addressing.f32 Q.f32 d. *(immAddr). . The address size may be either 32-bit or 64-bit. 32-bit). ldu.ss}.type = { .b8. and then converted to .

e. In generic addressing. an integer or bit-size type register reg containing a byte address.ss}.type = = = = {. .shared spaces to inhibit optimization of references to volatile memory. Within these windows.vec . Cache operations require sm_20 or later. If an address is not properly aligned. b.u16. .wb. st. [a].PTX ISA Version 2.ss}. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. 2010 . *(d+immOffset) = a.volatile. { .f64 }.ss}{. .s8.v4 }. . . *(immAddr) = a.v2. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. st{.cop}. . 32-bit). Semantics d = a.0. an address maps to global memory unless it falls within the local memory window or the shared memory window. b. .volatile may be used with . the resulting behavior is undefined.0 Table 83.global. { . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space..b16. to enforce sequential consistency between threads accessing shared memory.type [a]. for example. .u64.cs. This may be used.local.b32. . . If no state space is given.0. or the instruction may fault. an address maps to the corresponding location in local or shared memory. .ss}{.u32.volatile{. Addresses are zero-extended to the specified width as needed.type st.volatile{. Cache operations are not permitted with st. Generic addressing and cache operations introduced in PTX ISA 2. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st. and truncated if the register width exceeds the state space address width for the target architecture.shared }. [a]. or [immAddr] an immediate absolute byte address (unsigned. . st. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 32-bit). { .vec. b. b.e. st introduced in PTX ISA version 1.f64 requires sm_13 or later. i. *d = a. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. . The address size may be either 32-bit or 64-bit.s32. . .ss . .global and .b8.s64.cop .b64.type st{. . . PTX ISA Notes Target ISA Notes 116 January 24.b16. [a].u8. i.s16. The lower n bits corresponding to the instruction-type width are stored to memory. Generic addressing may be used with st. . perform the store using generic addressing. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.reg state space. A source register wider than the specified type may be used.cop}.vec.cg.wt }.1. Generic addressing requires sm_20 or later.volatile. . The address must be naturally aligned to a multiple of the access size.type .f16 data resulting from a cvt instruction may be stored using st.volatile introduced in PTX ISA version 1.

local. // immediate address %r.Chapter 8.v4.f16.f32 st.b. [fs].Q. [q+4].s32 cvt.local. [q+-8].b32 st. 2010 117 .a.%r.local. Instruction Set Examples st.%r.f32 st.global. // %r is 32-bit register // store lower 16 bits January 24.b16 [a]. // negative offset [100].s32 st. [p].b32 st.global.a.r7.

a register reg containing a byte address. A prefetch to a shared memory location performs no operation.L1 [a]. . . or [immAddr] an immediate absolute byte address (unsigned. 2010 . in specified state space. Addresses are zero-extended to the specified width as needed. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Within these windows. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. prefetch and prefetchu require sm_20 or later.global. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.space = { .e. i.space}. [a].L2 }.0. an address maps to the corresponding location in local or shared memory. .level = { . and no operation occurs if the address maps to a local or shared memory location. The address size may be either 32-bit or 64-bit. // prefetch to data cache // prefetch to uniform cache . prefetch{.L1.L1 [addr]. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.L1 [ptr]. 118 January 24. If no state space is given. an address maps to global memory unless it falls within the local memory window or the shared memory window. A prefetch into the uniform cache requires a generic address. prefetch.local }.global. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.PTX ISA Version 2. the prefetch uses generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. prefetchu. 32-bit). In generic addressing. 32-bit). to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.0 Table 84.level prefetchu.

2010 119 . isshrd. sptr. or vice-versa. Take the generic address of a variable declared in global. .size cvta.u64.space p. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or shared address.space.u32 p.shared.u64 }. cvta. . gptr. islcl. the generic address of the variable may be taken using cvta.local.u32 gptr. cvta.shared }.global. svar.u32 p.space = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .space. . // get generic address of svar cvta.0. a.u32 to truncate or zero-extend addresses. p. isspacep. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.global isspacep.genptr. or vice-versa. .space = { .lptr. Instruction Set Table 85.u64. isspacep requires sm_20 or later. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.to. // result is . Introduced in PTX ISA version 2. . January 24. or shared address cvta. or shared address to a generic address.size p.u32. The source address operand must be a register of type . or shared state space. Use cvt. For variables declared in global. When converting a generic address into a global.pred.size . a.u32.0. cvta requires sm_20 or later.local. // local.shared isglbl.u32 or . local. A program may use isspacep to guard against such incorrect behavior. local. cvta.local.size = { . PTX ISA Notes Target ISA Notes Examples Table 86. a. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. Description Convert a global.to.shared }.global. p. or shared state space.space. The source and destination addresses must be the same size.pred . local.Chapter 8.local isspacep. local. local. The destination register must be of type . // convert to generic address // get generic address of var // convert generic address to global. var. isspacep.global. or shared state space to generic. lptr.u64 or cvt.

a.rz.u8. sm_1x: For cvt. . subnormal numbers are supported.rm.rp }.ftz. .f32 float-to-integer conversions and cvt.f16.0 Table 87. 2010 .dtype = . d.dtype.sat For integer destination types.ftz. Note that saturation applies to both signed and unsigned integer types. . a.f32.ftz}{.atype cvt{.ftz. .rpi }.u16.atype = { . The compiler will preserve this behavior for legacy PTX code.rni round to nearest integer. .f32 float-tofloat conversions with integer rounding. // integer rounding // fp rounding . and for same-size float-tofloat conversions where the value is rounded to an integer. Note: In PTX ISA versions 1. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. choosing even integer if source is equidistant between two integers. .f32 float-to-integer conversions and cvt.4 and earlier. . .rn. the result is clamped to the destination range by default.sat limits the result to MININT.f32 float-tofloat conversions with integer rounding.frnd}{.e.e.frnd = { . .sat}. .s16..rni.f64 }. For float-to-integer conversions. the .s64. . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.u32. i. . For cvt..ftz}{.dtype. Description Semantics Integer Notes Convert between different types and sizes.irnd = { . cvt{.rmi.f32. . i. . .dtype. subnormal inputs are flushed to signpreserving zero. Integer rounding is illegal in all other instances.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.f32. . . Integer rounding is required for float-to-integer conversions. Saturation modifier: .u64. Integer rounding modifiers: .s32. 120 January 24. .ftz modifier may be specified in these cases for clarity. .irnd}{.rzi. The optional .rmi round to nearest integer in direction of negative infinity .sat is redundant.PTX ISA Version 2.atype d.MAXINT for the size of the operation. d = convert(a). .rzi round to nearest integer in the direction of zero . subnormal inputs are flushed to signpreserving zero.ftz.dtype.s8. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. .sat}.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.

.f64 j. cvt.0.s32 f.ftz behavior for sm_1x targets January 24.ftz modifier may be specified in these cases for clarity.4 or earlier.4 and earlier. result is fp cvt. The result is an integral value. Note: In PTX ISA versions 1.sat limits the result to the range [0.f16.f32 x. Applies to .Chapter 8.r.rni.f32.0.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f32. NaN results are flushed to positive zero.f32.rz mantissa LSB rounds towards zero .rm mantissa LSB rounds towards negative infinity . // float-to-int saturates by default cvt. and cvt. and for integer-to-float conversions.s32. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. The optional . cvt.0].f32.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Saturation modifier: . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.version is 1. Floating-point rounding modifiers: .f16. 2010 121 .rn mantissa LSB rounds to nearest even . and . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.i.f64.f32. 1. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . // note . Introduced in PTX ISA version 1. Floating-point rounding is illegal in all other instances. if the PTX . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. // round to nearest int. . The compiler will preserve this behavior for legacy PTX code.f32 x.f16.y. subnormal numbers are supported. Subnormal numbers: sm_20: By default.f32. Specifically.f64 types. Modifier . The operands must be of the same size.f32 instructions.sat For floating-point destination types. cvt. cvt to or from . stored in floating-point format.y.f64 requires sm_13 or later.f32.

u32 r5.target options ‘texmode_unified’ and ‘texmode_independent’. [tex1. In the independent mode.r2. Texturing modes For working with textures and samplers.entry compute_power ( . sampler.r4}. cvt. mul. } = clamp_to_border. r3. r3.f32. r5.PTX ISA Version 2. 2010 . r1. = nearest width height tsamp1.texref handle. r2. If no texturing mode is declared.param . the file is assumed to use unified mode. add. sampler. . A PTX module may declare only one texturing mode. [tex1].f32 r1. div.samplerref tsamp1 = { addr_mode_0 filter_mode }. but the number of samplers is greatly restricted to 16.r3. and surface descriptors. and surfaces. add.. {f1.global . texture and sampler information each have their own handle. . // get tex1’s tex. r5.b32 r6. sampler. r6. // get tex1’s txq.target texmode_independent .2d. allowing them to be defined separately and combined at the site of usage in the program. 122 January 24. add. PTX has two modes of operation. r5.0 8.f32 {r1.7. Example: calculate an element’s power contribution as element’s power/total number of elements. . Ability to query fields within texture. and surface descriptors. In the unified mode.texref tex1 ) { txq. r1.height.f32 r1. [tex1]. The texturing mode is selected using .f32. texture and sampler information is accessed through a single .u32 r5. and surface descriptors.6.b32 r5..v4. r4. Texture and Surface Instructions This section describes PTX instructions for accessing textures. r1.f2}].width.f32 r3. The advantage of independent mode is that textures and samplers can be mixed and matched. sampler. samplers.f32 r1. Module-scope and per-entry scope definitions of texture. The advantage of unified mode is that it allows 128 samplers. and surface descriptors: • • • Static initialization of texture. with the restriction that they correspond 1-to-1 with the 128 possible textures. PTX supports the following operations on texture.

btype = { .dtype = { .f32 {r1.btype tex. Unified mode texturing introduced in PTX ISA version 1..5.f4}]. i.dtype.s32. Notes For compatibility with prior versions of PTX.s32. tex txq suld sust sured suq Table 88.dtype. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.s32 {r1. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. with the extra elements being ignored. sampler_x. The instruction always returns a four-element vector of 32-bit values. If no sampler is specified. is a two-element vector for 2d textures. // explicit sampler .r2. Instruction Set These instructions provide access to texture and surface memory. b. c]. the square brackets are not required and .f2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. PTX ISA Notes Target ISA Notes Examples January 24.r4}. .s32. .r3. Operand c is a scalar or singleton tuple for 1d textures. the sampler behavior is a property of the named texture. // Example of independent mode texturing tex. the resulting behavior is undefined.3d. . [tex_a. .3d }. tex.u32.v4. d.2d.f32 }.1d.v4. {f1.v4 coordinate vectors are allowed for any geometry. 2010 123 .v4.r4}. //Example of unified mode texturing tex. or the instruction may fault.s32.geom = { . Supported on all target architectures. {f1}]. [a.f32 }. [tex_a.e. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. A texture base address is assumed to be aligned to a 16-byte address. .r2.v4. Description Texture lookup using a texture coordinate vector. If an address is not properly aligned. [a. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. where the fourth element is ignored.geom. An optional texture sampler b may be specified.geom.0. .1d.btype d. and is a four-element vector for 3d textures. c].Chapter 8.f3.r3. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .

width.texref or .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [tex_A].squery.width . linear } Integer from enum { wrap. In unified mode.0 Table 89. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.samplerref variable. txq. Integer from enum { nearest.tquery. [tex_A]. . mirror. [a]. .addr_mode_1 . . 2010 .depth. sampler attributes are also accessed via a texref argument.b32 txq.normalized_coords }. clamp_to_edge. .addr_mode_0.depth .PTX ISA Version 2. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.b32 d. .filter_mode . Query: .filter_mode.normalized_coords .width. Supported on all target architectures.addr_mode_0.squery = { . Operand a is a . Description Query an attribute of a texture or sampler. addr_mode_2 }.height . txq.height.b32 %r1. and in independent mode sampler attributes are accessed via a separate samplerref argument.b32 %r1.filter_mode. txq. addr_mode_1.5. clamp_ogl. // unified mode // independent mode 124 January 24.addr_mode_0 . [smpl_B]. [a].tquery = { .b32 %r1. txq. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d. // texture attributes // sampler attributes .

v2. suld.s32.dtype. If an address is not properly aligned.cg. A surface base address is assumed to be aligned to a 16-byte address. . where the fourth element is ignored. then . the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32.f3.f4}.b32. Coordinate elements are of type .dtype.ca.v4 }.clamp .f32 }.f32. The lowest dimension coordinate represents a sample offset rather than a byte offset. suld.v4. sm_1x targets support only the .vec .geom{. and is a four-element vector for 3d surfaces. SNORM.trap clamping modifier. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. the resulting behavior is undefined.trap {r1. suld. [a.surfref variable.b32.clamp suld. The .zero }. .1d.p. or . if the surface format contains SINT data.0. // for suld. then .trap. Description Load from surface memory using a surface coordinate vector. // unformatted d. i.cs.trap .cv }. b].b16. Operand b is a scalar or singleton tuple for 1d surfaces.p requires sm_20 or later.b64 }.cop}. .e.b . . .clamp = = = = = = { { { { { { d. // for suld.geom{. G. or the instruction may fault.cop}. suld.cop . and A components of the surface format. // formatted . and the size of the data transfer matches the size of destination operand d. then . {f1. suld Syntax Texture and Surface Instructions: suld Load from surface memory.u32 is returned. and cache operations introduced in PTX ISA version 2. .r2}.clamp. .u32.s32.f32 is returned. Instruction Set Table 90. or . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f2.trap suld.geom .zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.vec. the surface sample elements are converted to .b32. size and type conversion is performed as needed to convert from the surface sample format to the destination type. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. suld.s32 is returned. suld.f32 based on the surface format as follows: If the surface format contains UNORM.z. .5.v2.b8 . .b64.Chapter 8.3d requires sm_20 or later.s32.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R..f32. Destination vector elements corresponding to components that do not appear in the surface format are not written. . additional clamp modifiers. Target ISA Notes Examples January 24.dtype .p.2d. B. If the destination type is . . is a two-element vector for 2d surfaces.3d }.w}].b performs an unformatted load of binary data. {x. // cache operation none.y. {x}]. if the surface format contains UINT data.s32.dtype .p.clamp field specifies how to handle out-of-bounds addresses: . .1d.3d. [surf_A. . .b.v4.b.p is currently unimplemented. [surf_B. suld.b. b]. . 2010 125 . . Cache operations require sm_20 or later. [a.u32. .trap introduced in PTX ISA version 1.clamp .p . Operand a is a . . suld. or FLOAT data. suld. If the destination base type is .b supported on all target architectures. .

or .2d. The source data is then converted from this type to the surface sample format.cop . A surface base address is assumed to be aligned to a 16-byte address.p requires sm_20 or later. sust. The lowest dimension coordinate represents a sample offset rather than a byte offset.p Description Store to surface memory using a surface coordinate vector.clamp field specifies how to handle out-of-bounds addresses: . .w}]. the resulting behavior is undefined.u32. . and is a four-element vector for 3d surfaces. If the source type is . . sust. .b64 }. {r1. if the surface format contains UINT data.1d.trap sust. .b.f4}.trap.clamp sust. and cache operations introduced in PTX ISA version 2.3d requires sm_20 or later.s32 is assumed. . . Coordinate elements are of type .geom .0. Cache operations require sm_20 or later. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. The size of the data transfer matches the size of source operand c. . size and type conversions are performed as needed between the surface sample format and the destination type.3d }.b.trap introduced in PTX ISA version 1.clamp .s32. {f1.y.cop}.p. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b32. . then . . . {x}].cop}.wb. Operand b is a scalar or singleton tuple for 1d surfaces.v4 }. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. sust Syntax Texture and Surface Instructions: sust Store to surface memory. or FLOAT data.cg. Source elements that do not occur in the surface sample are ignored.clamp.wt }.0 Table 91.v2. or the instruction may fault.geom{.b16.ctype.e.1d.ctype . [surf_B.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. if the surface format contains SINT data. B.u32 is assumed.5. If the source base type is . c. sust.3d.b // for sust.f32 }.vec.trap [surf_A. is a two-element vector for 2d surfaces.f32 is assumed.cs.u32. The . and A surface components.z.b32.p. .f3. .trap .b64.{u32.zero }. i. sm_1x targets support only the . If an address is not properly aligned. .p.f2. c.surfref variable.vec .r2}.v4.trap clamping modifier.p performs a formatted store of a vector of 32-bit data values to a surface sample.s32. .b8 .ctype . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. These elements are written to the corresponding surface sample components. .s32. sust.s32. Target ISA Notes Examples 126 January 24. {x. none. G. then . where the fourth element is ignored. sust.ctype.p. sust.b32. .. // for sust.PTX ISA Version 2. Surface sample components that do not occur in the source vector will be written with an unpredictable value.f32. b]. sust. . Operand a is a .f32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. 2010 . The source vector elements are interpreted left-to-right as R.clamp . . SNORM.b supported on all target architectures.b performs an unformatted store of binary data. additional clamp modifiers.clamp = = = = = = { { { { { { [a.vec. then .f32} are currently unimplemented. .b.geom{. b].v2. sust. [a. sust. // unformatted // formatted .

trap.b .trap sured.2d. min and max apply to . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.add. .b. Reduction to surface memory using a surface coordinate vector. then .b]. Operations add applies to .p.0.b32.geom.e.clamp [a. Instruction Set Table 92.clamp. and . where the fourth element is ignored.surfref variable.Chapter 8.s32 is assumed.u64. sured. or . A surface base address is assumed to be aligned to a 16-byte address. sured.u32.c.u64.ctype.2d. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .or }.op = { .b32 }. .b]. The . .clamp = { . . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. . then .ctype = { ..s32 types.s32.trap [surf_A.clamp .s32 types.u32 and .min. the resulting behavior is undefined.p performs a reduction on sample-addressed 32-bit data.max.u32. is a two-element vector for 2d surfaces. i. .u32 is assumed.geom = { . . operations and and or apply to . .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. [surf_B.op. sured.min. // for sured.ctype = { . Operand a is a . The lowest dimension coordinate represents a sample offset rather than a byte offset. r1.u32 based on the surface sample format as follows: if the surface format contains UINT data. The instruction type is restricted to . Coordinate elements are of type . January 24. If an address is not properly aligned.clamp field specifies how to handle out-of-bounds addresses: . .b performs an unformatted reduction on .and.s32 or .b32. Operand b is a scalar or singleton tuple for 1d surfaces. {x}].geom.1d.1d.s32.trap . sured.ctype.y}]. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .zero }.b. and the data is interpreted as .p.u64 data.b32 type. // sample addressing . .b32 }.op. .p .b32.u32. if the surface format contains SINT data. . {x. // for sured. r1.u32.s32.3d }. .c. and is a four-element vector for 3d surfaces.clamp [a.add. 2010 127 . // byte addressing sured. sured requires sm_20 or later. . or the instruction may fault.

Operand a is a .b32 %r1.query. 2010 . 128 January 24.width. Query: . . . suq.PTX ISA Version 2. [a].width . suq.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth }.query = { . Description Query an attribute of a surface.surfref variable.5.height .height.width.b32 d. Supported on all target architectures.0 Table 93. [surf_A].

Chapter 8. { add. If {!}p then instruction Introduced in PTX ISA version 1.a. Threads with a false guard predicate do nothing.y.0. @{!}p instruction. Supported on all target architectures. 2010 129 .s32 d. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.s32 a. } PTX ISA Notes Target ISA Notes Examples Table 95.f32 @q bra L23. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.x. used primarily for defining a function body.f32 @!p div. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.7. Supported on all target architectures. {} Syntax Description Control Flow Instructions: { } Instruction grouping.b.eq.0. Execute an instruction or instruction block for threads that have the guard predicate true. { instructionList } The curly braces create a group of instructions. ratio. Instruction Set 8.7. Introduced in PTX ISA version 1. p. mov.c.0. setp.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

January 24, 2010

131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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sync bar. {!}c.cta. a{.or). Once the barrier count is reached.red instruction.sync or bar. p.red delays the executing threads (similar to bar.sync 0. and bar.version 2.popc. b. Only bar. Thus. Description Performs barrier synchronization and communication within a CTA. bar.red are population-count (. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. {!}c.sync and bar.Chapter 8. Since barriers are executed on a per-warp basis.pred . The barrier instructions signal the arrival of the executing threads at the named barrier. Barriers are executed on a per-warp basis as if all the threads in a warp are active.sync with an immediate barrier number is supported for sm_1x targets. execute a bar. In addition to signaling its arrival at the barrier.u32 bar. b}.and). and any-thread-true (.sync and bar. bar.red. Each CTA instance has sixteen barriers numbered 0.and and . Operands a.op = { . and bar. it is as if all the threads in the warp have executed the bar instruction. PTX ISA Notes Target ISA Notes Examples bar.arrive using the same active barrier. all-threads-true (.{arrive. Instruction Set Table 100.red performs a reduction operation across threads. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. operands p and c are predicates. The result of . a{. bar.arrive does not cause any waiting by the executing threads.arrive.{arrive.popc).red also guarantee memory ordering among threads identical to membar.red} introduced in PTX . thread count. the optional thread count must be a multiple of the warp size.arrive a{. Operand b specifies the number of threads participating in the barrier. The reduction operations for bar.sync) until the barrier count is met. thread count.op. All threads in the warp are stalled until the barrier completes. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.red should not be intermixed with bar. Register operands. When a barrier completes. bar.sync or bar. all threads in the CTA participate in the barrier.u32.. Thus. 2010 133 . b}. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). and the barrier is reinitialized so that it can be immediately reused.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. bar. while . a. . it simply marks a thread's arrival at the barrier. d. b. bar. and d have type .sync without a thread count introduced in PTX ISA 1. Note that a non-zero thread count is required for bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). threads within a CTA that wish to communicate via memory can store to memory. and then safely read values stored by other threads prior to the barrier. bar. if any thread in a warp executes a bar instruction. b}. the waiting threads are restarted without delay. Register operands. In conditionally executed code. January 24.popc is the number of threads with a true predicate.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.red.0. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.15.or }. the bar.red} require sm_20 or later. the final value is written to the destination register in all threads waiting at the barrier. bar.0.red performs a predicate reduction across the threads participating in the barrier. If no thread count is specified. bar.and. Execution in this case is unpredictable.

2010 .cta Waits until all prior memory writes are visible to other threads in the same CTA.0 Table 101.version 1.gl. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar.sys }. membar. global. this is the appropriate level of membar.{cta. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar.PTX ISA Version 2. 134 January 24. PTX ISA Notes Target ISA Notes Examples membar. level describes the scope of other clients for which membar is an ordering event.cta.version 2. membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. .4. . membar. membar. when the previous value can no longer be read. by st. that is. membar. membar.gl will typically have a longer latency than membar. membar. membar.level. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. A memory write (e.gl.gl} introduced in PTX .sys requires sm_20 or later.cta. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.{cta.sys introduced in PTX . including thoses communicating via PCI-E such as system and peer-to-peer memory. or system memory level.sys Waits until all prior memory requests have been performed with respect to all clients. A memory read (e.gl.cta.gl} supported on all target architectures.0. membar. For communication between threads in different CTAs or even different SMs. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level.sys. and memory reads by this thread can no longer be affected by other thread writes.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.level = { .sys will typically have much longer latency than membar.g.g. Waits until prior memory reads have been performed with respect to other threads in the CTA. .

. . .type = { . . The integer operations are add. [a]. or.type atom{. min. b.add. and truncated if the register width exceeds the state space address width for the target architecture. . . .inc. The inc and dec operations return a result in the range [0.or.global.space}. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.b32.b32 only . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. [a]. accesses to local memory are illegal. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . and stores the result of the specified operation at location a. . Operand a specifies a location in the specified state space. inc. c.s32.u64. performs a reduction operation with operand b and the value in location a.op = { . e. a de-referenced register areg containing a byte address. 32-bit operations. For atom. . . Description // // // // // . max.op. i. Within these windows. . The bit-size operations are and. or [immAddr] an immediate absolute byte address. . xor.g.e. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. .exch. atom. perform the memory accesses using generic addressing. The address must be naturally aligned to a multiple of the access size.b]. or the instruction may fault. .u32. . an address maps to global memory unless it falls within the local memory window or the shared memory window. Instruction Set Table 102.Chapter 8. January 24.b64 .space}.u32. min. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. dec. The floating-point operations are add.type d. an address maps to the corresponding location in local or shared memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32. by inserting barriers between normal stores and atomic operations to a common address.dec. . atom{.op. the resulting behavior is undefined. .exch to store to locations accessed by other atomic operations.space = { . .and.b64.shared }. Addresses are zero-extended to the specified width as needed. i. and max operations are single-precision.u32 only . overwriting the original value. cas (compare-and-swap).. and exch (exchange). .add. . The floating-point add.b32. min. and max. . 2010 135 .f32 }. . The address size may be either 32-bit or 64-bit. or by using atom.xor. A register containing an address may be declared as a bit-size type or integer type. d. . If no state space is given. b.f32 Atomically loads the original value at location a into destination register d.s32. If an address is not properly aligned.max }.u64 ..f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.cas.s32.e.min.u32. In generic addressing.

global requires sm_11 or later. : r-1.1. Use of generic addressing requires sm_20 or later. 64-bit atom.cas.shared operations require sm_20 or later.b32 d. atom. : r+1. atom. 2010 .{add. s) = (r >= s) ? 0 dec(r. b). atom. cas(r.my_new_val.s. s) = (r > s) ? s exch(r.max.0.shared requires sm_12 or later. d.f32 requires sm_20 or later. s) = s.PTX ISA Version 2.[p]. atom.f32 atom.{min.add.shared. : r.max} are unimplemented. *a = (operation == cas) ? : } where inc(r.global.s32 atom.f32.[x+4]. d. 64-bit atom.0. atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.exch} requires sm_12 or later.[a].cas.0 Semantics atomic { d = *a.my_val. Release Notes Examples @p 136 January 24. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.add. c) operation(*a.t) = (r == s) ? t operation(*a.global. b. Introduced in PTX ISA version 1.

b). dec(r. The floating-point operations are add.dec. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32..type [a]. . Instruction Set Table 103. January 24.add. accesses to local memory are illegal. and max operations are single-precision. If an address is not properly aligned. Semantics *a = operation(*a. .or.b32 only . The bit-size operations are and. min. The integer operations are add.type = { . an address maps to global memory unless it falls within the local memory window or the shared memory window. .. an address maps to the corresponding location in local or shared memory.u32 only . a de-referenced register areg containing a byte address. or [immAddr] an immediate absolute byte address.g. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. s) = (r > s) ? s : r-1. b. . . max.op = { . i.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . e. 32-bit operations. by inserting barriers between normal stores and reduction operations to a common address.u32. Operand a specifies a location in the specified state space.s32. red. where inc(r.f32 }. Notes Operand a must reside in either the global or shared state space.u32. overwriting the original value.space = { . . . min. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. red{. .exch to store to locations accessed by other reduction operations.space}. The inc and dec operations return a result in the range [0.Chapter 8. .s32.u32. and xor. . or. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.inc. The address must be naturally aligned to a multiple of the access size. .add. perform the memory accesses using generic addressing.xor. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.shared }. min.f32. inc.s32.and.min. Addresses are zero-extended to the specified width as needed. The address size may be either 32-bit or 64-bit.global. i. 2010 137 . the resulting behavior is undefined.u64 . A register containing an address may be declared as a bit-size type or integer type. Within these windows. . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f32 Performs a reduction operation with operand b and the value in location a. or the instruction may fault.op. and max. . .b].max }. or by using atom. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Description // // // // . and stores the result of the specified operation at location a. s) = (r >= s) ? 0 : r+1. dec. .e. and truncated if the register width exceeds the state space address width for the target architecture. . If no state space is given. . In generic addressing.b64. .u64. The floating-point add.e. For red.

64-bit red.add.f32 red. red.add requires sm_12 or later. [p].{min.shared.shared operations require sm_20 or later.2.add. red.b32 [a].f32 requires sm_20 or later.my_val. red.global. red. 2010 .global. [x+4].and.0.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.1. Use of generic addressing requires sm_20 or later. 64-bit red.s32 red. Release Notes Examples @p 138 January 24.max.f32.PTX ISA Version 2.max} are unimplemented.global requires sm_11 or later red.shared requires sm_12 or later.

pred vote. returns bitmask . Negate the source predicate to compute .all. where the bit position corresponds to the thread’s lane id.mode. Description Performs a reduction of the source predicate across threads in a warp. The destination predicate value is the same across all threads in the warp. vote. Note that vote applies to threads in a single warp. // ‘ballot’ form.b32 d.ballot. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. vote. p. vote. r1. .Chapter 8. The reduction modes are: .ballot.2.q.ballot. Negate the source predicate to compute .none. {!}a.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.pred vote. vote.any True if source predicate is True for some active thread in warp.pred d.uni. 2010 139 .all.b32 p.p.uni }.not_all. In the ‘ballot’ form. .any. Negating the source predicate also computes . . vote. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.ballot. vote requires sm_12 or later. Instruction Set Table 104. .uni True if source predicate has the same value in all active threads in warp. // get ‘ballot’ across warp January 24.b32 requires sm_20 or later. not across an entire CTA.uni.mode = { .q.all True if source predicate is True for all active threads in warp. {!}a.

atype = .u32.atype.s34 intermediate result.atype.PTX ISA Version 2. the input values are extracted and signor zero.asel}. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. taking into account the subword destination size in the case of optional data merging. or word values from its source operands.9.dtype. optionally clamp the result to the range of the destination type. half-word. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). .atype. 2. . Using the atype/btype and asel/bsel specifiers. perform a scalar arithmetic operation to produce a signed 34-bit result. 3. extract and sign.h1 }. .h0.add.bsel}. and btype are valid. 140 January 24. b{.dtype.b2. a{.secop = { .sat}.b1.0 8. . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.min. vop. The primary operation is then performed to produce an .asel}. to produce signed 33-bit input values.u32 or . all combinations of dtype. .or zero-extend byte. .sat} d.btype{. // 32-bit scalar operation. with optional secondary operation vop. with optional data merge vop.btype{.dsel. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.bsel}.s32 }. a{. . . . c.bsel = { . Video Instructions All video instructions operate on 32-bit register operands.btype = { . The sign of the intermediate result depends on dtype. The source and destination operands are all 32-bit registers.asel = .extended internally to . b{.b3.dtype.btype{. 4. 2010 .7. .s32) is specified in the instruction type. The type of each operand (. The general format of video instructions is as follows: // 32-bit scalar operation. c.dsel = .s33 values. .secop d. a{.bsel}. b{.max }.asel}.dtype = .b0.sat} d. atype.

U8_MAX. S8_MIN ).max return MAX(tmp.s33 optSecOp(Modifier secop.Chapter 8.b1: return ((tmp & 0xff) << 8) case . . U16_MIN ). S32_MAX.s33 tmp. . c). . U32_MIN ). . S8_MAX.b1.h0: return ((tmp & 0xffff) case . .s33 tmp. as shown in the following pseudocode. S32_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. 2010 141 . c). c). } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).s33 c) { switch ( secop ) { .h0. The lower 32-bits are then written to the destination operand. S16_MIN ).b2. default: return tmp.add: return tmp + c. tmp.h1: return ((tmp & 0xffff) << 16) case . S16_MAX. January 24. Instruction Set . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. The sign of the c operand is based on dtype.s33 optSaturate( . Bool sat. . c).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.b0.b0: return ((tmp & 0xff) case . . tmp. Bool sign. . tmp. tmp. . c).s33 c ) switch ( dsel ) { case . U32_MAX. tmp. Modifier dsel ) { if ( !sat ) return tmp.s34 tmp.s33 optMerge( Modifier dsel. . } } . switch ( dsel ) { case .b2: return ((tmp & 0xff) << 16) case . c). U16_MAX. c). .min: return MIN(tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case . U8_MIN ).

r3. r2. vmax }. 2010 .0.b3.btype{.vop .dtype.max }.or zero-extend based on source operand type ta = partSelectSignExtend( a. tmp. // optional secondary operation d = optMerge( dsel.u32.add r1. b{.atype. vabsdiff.op2 d. with optional data merge vop.atype. c ).b2. tmp = ta – tb.PTX ISA Version 2.s32. Perform scalar arithmetic operation with optional saturate. r2.0 Table 105.btype = { .sat} d. vsub.h0. r3.u32. Video Instructions: vadd.s32 }. . b{.s32.b1. r2. vmax require sm_20 or later.b2.sat}.s32.h1 }. tb = partSelectSignExtend( b. // 32-bit scalar operation. .dsel. isSigned(dtype).s32. a{. vsub.add.asel}. c.u32. btype. tmp = MIN( ta. // 32-bit scalar operation. r1. taking into account destination type and merge operations tmp = optSaturate( tmp. .s32. r3. vabsdiff. tmp.s32. r1.min.bsel = { . dsel ). .sat vabsdiff. tmp = MAX( ta.asel}.h0. asel ). . . b{. bsel ). vabsdiff. vop. a{. vsub vabsdiff vmin.s32. and optional secondary arithmetic operation or subword data merge.s32. vadd. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. sat. vmin. r3. . r1.dtype.sat. // extract byte/half-word/word and sign.h1.atype = .sat} d. c.btype{.asel = .bsel}.dtype .h0. a{. vmax Syntax Integer byte/half-word/word addition / subtraction.sat vmin.atype.bsel}.op2 Description = = = = { vadd.h1. with optional secondary operation vop. tmp = | ta – tb |. c. .b0.bsel}. vmin. c ).s32. { . tb ).asel}. . . r2.btype{.dtype.b0. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. . vmax vadd. vsub. tb ). c. vmin. Semantics // saturate. atype. vadd. // optional merge with c operand 142 January 24.dsel . d = optSecondaryOp( op2.b0.sat vsub.s32. Integer byte/half-word/word absolute value of difference. Integer byte/half-word/word minimum / maximum.

isSigned(dtype).asel = .atype. r3. c.asel}. // 32-bit scalar operation. vshl: Shift a left by unsigned amount in b with optional saturate. unsigned shift fills with zero.min. c ). vshl. a{.dtype .clamp && tb > 32 ) tb = 32.mode}.s32.max }. vop. .b1.mode} d. d = optSecondaryOp( op2. { .u32.add.asel}. // 32-bit scalar operation.sat}{. vshr require sm_20 or later. c.dsel .wrap ) tb = tb & 0x1f. and optional secondary arithmetic operation or subword data merge. vshr Syntax Integer byte/half-word/word left / right shift. c ). .h1 }.clamp. with optional data merge vop.u32{. 2010 143 . Video Instructions: vshl. . .vop .mode} d. .bsel = { . Signed shift fills with the sign bit.u32. tmp. tmp. atype. Instruction Set Table 106.dsel. with optional secondary operation vop. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. sat. case vshr: tmp = ta >> tb. and optional secondary arithmetic operation or subword data merge. r1.b0. b{.or zero-extend based on source operand type ta = partSelectSignExtend( a.u32. } // saturate.h0.atype.u32{. . vshl.clamp . r2. if ( mode == .b3. bsel ). if ( mode == . b{.sat}{.b2.sat}{. .u32.u32. January 24.atype = { . tb = partSelectSignExtend( b. { . r3.atype.op2 Description = = = = = { vshl. .Chapter 8.mode .bsel}.wrap }. . . . asel ). vshr: Shift a right by unsigned amount in b with optional saturate. // optional secondary operation d = optMerge( dsel. a{.dtype.dtype.0. Semantics // extract byte/half-word/word and sign.wrap r1. b{.u32{.u32 vshr.asel}.s32 }.h1. dsel ). vshr vshl.dtype. taking into account destination type and merge operations tmp = optSaturate( tmp. a{. vshr }. switch ( vop ) { case vshl: tmp = ta << tb. Left shift fills with zero. . r2.bsel}. // default is .bsel}.op2 d.

shr15 }. otherwise. .h0. and scaling.btype{.bsel}.S32 // intermediate signed.dtype = . the intermediate result is signed.dtype.s32 }.. with optional operand negates. // 32-bit scalar operation vmad.b1. c.u32.b2. {-}a{. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. a{.bsel}. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. Source operands may not be negated in . final signed (U32 * S32) .btype = { . {-}b{. final signed -(S32 * U32) + S32 // intermediate signed. .shr7. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.PTX ISA Version 2. Although PTX syntax allows separate negation of the a and b operands.asel = . 144 January 24. {-}c.S32 // intermediate signed. and the operand negates.U32 // intermediate unsigned.0 Table 107. . The source operands support optional negation with some restrictions. Input c has the same sign as the intermediate result.asel}. final unsigned -(U32 * U32) + S32 // intermediate signed. . That is. (a*b) is negated if and only if exactly one of a or b is negated. internally this is represented as negation of the product (a*b). final signed -(U32 * S32) + S32 // intermediate signed.po) computes (a*b) + c + 1.atype.atype = . .atype. PTX allows negation of either (a*b) or c.scale} d.bsel = { . .sat}{. 2010 . final signed (U32 * S32) + S32 // intermediate signed.b3.sat}{.scale} d. final signed (S32 * U32) . this result is sign-extended if the final result is signed. vmad. final signed (U32 * U32) . final signed -(S32 * S32) + S32 // intermediate signed. final signed (S32 * S32) + S32 // intermediate signed. The “plus one” mode (. .po mode. . “plus one” mode.btype.dtype.h1 }.po{.asel}. Description Calculate (a*b) + c. and zero-extended otherwise. which is used in computing averages. b{.S32 // intermediate signed. final signed (S32 * S32) . final signed The intermediate result is optionally scaled via right-shift. The final result is unsigned if the intermediate result is unsigned and c is not negated. .b0. Depending on the sign of the a and b operands. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. final signed (S32 * U32) + S32 // intermediate signed. .scale = { .

r2. vmad requires sm_20 or later. tmp = tmp + c128 + lsb. } else if ( c.sat vmad. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). r1. } else if ( a. S32_MIN). U32_MAX. 2010 145 . r1. switch( scale ) { case .negate ^ b. btype.shr15 r0. January 24.negate.u32.negate ) { tmp = ~tmp.sat ) { if (signedFinal) result = CLAMP(result.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a.0. vmad. lsb = 1. U32_MIN).shr7: result = (tmp >> 7) & 0xffffffffffffffff. atype. bsel ). S32_MAX. tmp[127:0] = ta * tb.u32.h0.s32. -r3. r3. if ( . lsb = 1. tb = partSelectSignExtend( b. signedFinal = isSigned(atype) || isSigned(btype) || (a. lsb = 0. asel ). case . } if ( .h0.po ) { lsb = 1. r0. r2.s32.negate ^ b. else result = CLAMP(result. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.shr15: result = (tmp >> 15) & 0xffffffffffffffff.Chapter 8.negate) || c. Instruction Set Semantics // extract byte/half-word/word and sign.negate ) { c = ~c.

eq. .asel}.b0.lt vset. a{.btype. and therefore the c operand and final result are also unsigned.0. .u32. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. btype.btype = { . a{. .dsel . r1.le. r2. // optional secondary operation d = optMerge( dsel.btype. { .s32. r3. asel ).min.or zero-extend based on source operand type ta = partSelectSignExtend( a. c ). . Compare input values using specified comparison. r2. c ). with optional secondary operation vset.gt.btype.asel = .ne r1.h1. . .asel}. tmp = compare( ta. . .ge }. 146 January 24. vset.b1. c. with optional data merge vset. 2010 .cmp .s32 }. Semantics // extract byte/half-word/word and sign. .bsel = { .ne.max }.cmp. { . // 32-bit scalar operation. . tmp.u32.bsel}.atype. vset.PTX ISA Version 2. a{. tb.h1 }.cmp d.cmp d.atype.bsel}.u32.dsel.atype.h0. d = optSecondaryOp( op2. . cmp ) ? 1 : 0. b{. bsel ). with optional secondary arithmetic operation or subword data merge.asel}. .add. .0 Table 108. tmp. . b{.atype .lt. . r3. tb = partSelectSignExtend( b.u32. vset requires sm_20 or later. // 32-bit scalar operation.op2 Description = = = = .b2.b3.op2 d. b{.bsel}. atype. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. The intermediate result of the comparison is always unsigned. c.

Chapter 8. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Notes PTX ISA Notes Target ISA Notes Examples Currently. brkpt requires sm_11 or later. trap Abort execution and generate an interrupt to the host CPU.0.4. trap. Supported on all target architectures. brkpt Suspends execution Introduced in PTX ISA version 1. trap. January 24.0. Table 111. Supported on all target architectures. Introduced in PTX ISA version 1. with index specified by immediate operand a. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Instruction Set 8. @p pmevent 1. Table 110. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. pmevent 7. pmevent a.10. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. 2010 147 . The relationship between events and counters is programmed via API calls from the host. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.7. brkpt. numbered 0 through 15. brkpt. there are sixteen performance monitor events. Introduced in PTX ISA version 1. Triggers one of a fixed number of performance monitor events.

0 148 January 24.PTX ISA Version 2. 2010 .

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_le. which are visible as special registers and accessed through mov or cvt instructions.Chapter 9. …. %pm3 January 24. %lanemask_ge. read-only variables. %lanemask_gt %clock. Special Registers PTX includes a number of predefined. 2010 149 . %clock64 %pm0. %lanemask_lt.

z PTX ISA Notes Introduced in PTX ISA version 1.x.x code Target ISA Notes Examples 150 January 24. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. mov. mov.v4 .y * %ntid.x code accessing 16-bit component of %tid mov. %ntid.sreg .%h2.u32 %h2. .x.0 Table 112.z). It is guaranteed that: 0 <= %tid. %tid. The total number of threads in a CTA is (%ntid. mov.y.u16 %r2. .x to %rh Target ISA Notes Examples // legacy PTX 1.0.y < %ntid.0.z == 0 in 2D CTAs. The fourth element is unused and always returns zero.u32 %tid. // move tid.0. %ntid. %tid. Supported on all target architectures. the fourth element is unused and always returns zero.%tid.u32 %tid. PTX ISA Notes Introduced in PTX ISA version 1. Redefined as . Supported on all target architectures.x * %ntid.u32 %ntid.x.x.%ntid. .%tid. Redefined as .u32 type in PTX 2.sreg . %tid.u32 %h1. CTA dimensions are non-zero. .%tid.%tid. The number of threads in each dimension are specified by the predefined special register %ntid.y.z == 1 in 1D CTAs.x 0 <= %tid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. %tid component values range from 0 through %ntid–1 in each CTA dimension. The %tid special register contains a 1D.%tid.PTX ISA Version 2. %tid.z == 1 in 2D CTAs. // legacy PTX 1.u32 type in PTX 2.z < %ntid.sreg .x.0. read-only. // thread id vector // thread id components A predefined.x < %ntid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. %ntid.u16 %rh.y == %ntid.%ntid. // CTA shape vector // CTA dimensions A predefined.y == %tid. mov.v4.sreg . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.z == 0 in 1D CTAs.u32.u16 %rh.z.y.u32 %r0. // compute unified thread id for 2D CTA mov. mad. cvt.%r0.x.v4 .u32 %ntid. or 3D vector to match the CTA shape.x.z.%h1. per-thread special register initialized with the thread identifier within the CTA.v4.u32 %r1.u32 %r0. // zero-extend tid. 2D.y 0 <= %tid.z. read-only special register initialized with the number of thread ids in each CTA dimension. %ntid. the %tid value in unused dimensions is 0.z to %r2 Table 113. Every thread in the CTA has a unique %tid. 2010 .

u32 %laneid. %nwarpid. mov. read-only special register that returns the thread’s lane within the warp. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. due to rescheduling of threads following preemption. 2010 151 . Note that %warpid is volatile and returns the location of a thread at the moment when read. The warp identifier will be the same for all threads within a single warp. A predefined.0. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %laneid.u32 %warpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. January 24. Introduced in PTX ISA version 1. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. e. read-only special register that returns the maximum number of warp identifiers. A predefined. but its value may change during execution. Introduced in PTX ISA version 2. . The lane identifier ranges from zero to WARP_SZ-1. PTX ISA Notes Target ISA Notes Examples Table 116. Supported on all target architectures.sreg .u32 %r. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. %nwarpid requires sm_20 or later.u32 %r.u32 %nwarpid.g. For this reason. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Supported on all target architectures.sreg . Introduced in PTX ISA version 1.sreg . %warpid. A predefined. . . mov.Chapter 9. Table 115. mov.u32 %r. read-only special register that returns the thread’s warp identifier.3. Special Registers Table 114.3.

Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. .v4 .y 0 <= %ctaid. read-only special register initialized with the number of CTAs in each grid dimension. // legacy PTX 1. Supported on all target architectures.sreg .%ctaid.0.u32 %ctaid.z} < 65.u16 %r0.y. It is guaranteed that: 1 <= %nctaid.0. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.sreg .0 Table 117.z < %nctaid. mov.%ctaid.u32 %nctaid. // legacy PTX 1.x. The %ctaid special register contains a 1D.x < %nctaid.v4.u16 %r0. 2010 .x.%nctaid.%nctaid. %ctaid. with each element having a value of at least 1.0. .x.v4.sreg . Each vector element value is >= 0 and < 65535. The fourth element is unused and always returns zero.y < %nctaid.u32 %ctaid.z PTX ISA Notes Introduced in PTX ISA version 1. %rh.u32 type in PTX 2.x code Target ISA Notes Examples 152 January 24.x.536 PTX ISA Notes Introduced in PTX ISA version 1. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.z. depending on the shape and rank of the CTA grid.x code Target ISA Notes Examples Table 118. %rh.PTX ISA Version 2. read-only special register initialized with the CTA identifier within the CTA grid. The %nctaid special register contains a 3D grid shape vector.y.sreg .z. It is guaranteed that: 0 <= %ctaid.y.%nctaid. or 3D vector.y.%nctaid.u32 mov.{x.x 0 <= %ctaid. . 2D. Redefined as . %ctaid. The fourth element is unused and always returns zero.0. mov.u32 type in PTX 2. // Grid shape vector // Grid dimensions A predefined.x.u32 mov. // CTA id vector // CTA id components A predefined. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. Supported on all target architectures.v4 . Redefined as .u32 %nctaid .

. . Supported on all target architectures.u32 %r. %gridid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Introduced in PTX ISA version 1. The SM identifier numbering is not guaranteed to be contiguous. This variable provides the temporal grid launch number for this context.0.sreg .u32 %smid.u32 %nsmid. During execution.0. mov.3. A predefined. The SM identifier ranges from 0 to %nsmid-1. PTX ISA Notes Target ISA Notes Examples January 24.g. read-only special register initialized with the per-grid temporal grid identifier. %nsmid requires sm_20 or later. so %nsmid may be larger than the physical number of SMs in the device. %smid. Introduced in PTX ISA version 2. PTX ISA Notes Target ISA Notes Examples Table 121. due to rescheduling of threads following preemption. // initialized at grid launch A predefined. where each launch starts a grid-of-CTAs. mov. read-only special register that returns the maximum number of SM identifiers.sreg . repeated launches of programs may occur. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.Chapter 9. Notes PTX ISA Notes Target ISA Notes Examples Table 120. The SM identifier numbering is not guaranteed to be contiguous. Supported on all target architectures. but its value may change during execution.sreg . Note that %smid is volatile and returns the location of a thread at the moment when read. .u32 %r. Special Registers Table 119. %nsmid. 2010 153 . Introduced in PTX ISA version 1. e. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. A predefined. mov.u32 %r.u32 %gridid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.

read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_eq. Table 124.0. mov. 2010 .sreg . A predefined.u32 %lanemask_lt.0. 154 January 24. .0.u32 %r. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg .u32 %r.0 Table 122. Introduced in PTX ISA version 2. %lanemask_le. %lanemask_eq.PTX ISA Version 2. %lanemask_lt requires sm_20 or later. %lanemask_le requires sm_20 or later.sreg . . mov. %lanemask_eq requires sm_20 or later. Introduced in PTX ISA version 2. Table 123.u32 %lanemask_le. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_lt. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. A predefined. Introduced in PTX ISA version 2. . mov.u32 %r. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.

read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.Chapter 9. %lanemask_ge requires sm_20 or later. %lanemask_gt. A predefined. %lanemask_gt requires sm_20 or later. Special Registers Table 125. A predefined.sreg .u32 %r. January 24.u32 %lanemask_gt.u32 %r. . .0. %lanemask_ge. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Table 126. Introduced in PTX ISA version 2.u32 %lanemask_ge.0. mov. 2010 155 .sreg . Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. mov.

Special Registers: %pm0. mov. Supported on all target architectures.3.u32 r1. read-only 64-bit unsigned cycle counter. and %pm3 are unsigned 32-bit read-only performance monitor counters. .u32 %pm0.sreg . %pm2. Their behavior is currently undefined.u32 %clock. %pm1. Supported on all target architectures. mov. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.0 Table 127. Table 129.0. Introduced in PTX ISA version 1.PTX ISA Version 2. mov.sreg . 2010 .u32 r1. %pm3. %pm1.u64 r1. 156 January 24.%clock. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm2. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. The lower 32-bits of %clock64 are identical to %clock.u64 %clock64.sreg .0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. .%clock64. . …. Special registers %pm0.%pm0. %pm1. %pm2. Introduced in PTX ISA version 2. %clock64 requires sm_20 or later. %pm3 %pm0. read-only 32-bit unsigned cycle counter. Table 128. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Introduced in PTX ISA version 1.

version .4 January 24. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.Chapter 10. Increments to the major number indicate incompatible changes to PTX. Each ptx file must begin with a . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Directives 10.minor // major. . minor are integers Specifies the PTX language version number.version directives are allowed provided they match the original .version directive. and the target architecture for which the code was generated. . PTX File Directives: .version 1.0.version .version major. Supported on all target architectures. . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.target Table 130.version 2.version directive.0 . Duplicate .version Syntax Description Semantics PTX version number. 2010 157 .1.

including expanded rounding modifiers.target .texref and . 2010 . brkpt instructions. The texturing mode is specified for an entire module and cannot be changed within the module.f32. Adds double-precision support.texmode_independent texture and sampler information is bound together and accessed via a single . The following table summarizes the features in PTX that vary according to target architecture. sm_11. Supported on all target architectures. immediately followed by a . Note that .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. PTX features are checked against the specified target architecture. Disallows use of map_f64_to_f32.f64 storage remains as 64-bits. Therefore.version directive.f64 instructions used. texmode_unified. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. texture and sampler information is referenced with independent . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. but subsequent .target Syntax Architecture and Platform target. vote instructions. 64-bit {atom. sm_12. 158 January 24. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. with only half being used by instructions converted from . PTX code generated for a given target can be run on later generation devices.samplerref descriptors. generations of SM architectures follow an “onion layer” model.f64 instructions used.target directives can be used to change the set of target features allowed during parsing. texmode_independent. PTX File Directives: . Requires map_f64_to_f32 if any .f64 to .5.f64 instructions used. A program with multiple . Requires map_f64_to_f32 if any .red}. Requires map_f64_to_f32 if any . map_f64_to_f32 }.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. where each generation adds new features and retains all features of previous generations.texmode_unified . In general. Each PTX file must begin with a . sm_13.0.PTX ISA Version 2.global.target directive containing a target architecture and optional platform options.0 Table 131. Target sm_20 Description Baseline feature set for sm_20 architecture. Introduced in PTX ISA version 1.red}. A . sm_10.red}. Adds {atom.target directive specifies a single target architecture.global. Texturing mode: (default is . Adds {atom. .texref descriptor. and an error is generated if an unsupported feature is used. Texturing mode introduced in PTX ISA version 1. Description Specifies the set of features in the target architecture for which the current ptx code was generated.shared.texmode_unified) . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.

Directives Examples . texmode_independent January 24.target sm_13 // supports double-precision .target sm_10 // baseline target architecture .target sm_20.Chapter 10. 2010 159 .

with optional parameters. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. e.b32 %r2.entry . parameter variables are declared in the kernel body. %nctaid.b32 y. ld. Kernel and Function Directives: .4 and later.0 10. Parameters are passed via .param .5 and later. PTX ISA Notes For PTX ISA version 1. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. . store.g. and .entry cta_fft .param. These parameters can only be referenced by name within texture and surface load. In addition to normal parameters. the kernel dimensions and properties are established and made available via special registers.0 through 1.param space memory and are listed within an optional parenthesized parameter list. %ntid. opaque .b32 z ) Target ISA Notes Examples [x]. . parameters.b32 %r<99>. 2010 . At kernel launch. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.0 through 1.param.entry filter ( .entry Syntax Description Kernel entry point and body.param instructions. . Supported on all target architectures. Semantics Specify the entry point for a kernel program. .param.3. The shape and size of the CTA executing the kernel are available in special registers. parameter variables are declared in the kernel parameter list.4.b32 %r3.2. [z].func Table 132.entry kernel-name ( param-list ) kernel-body . For PTX ISA versions 1.param .entry kernel-name kernel-body Defines a kernel entry point name. ld. .samplerref.texref. [y]. and body for the kernel function. ld. … } .surfref variables may be passed as parameters. Parameters may be referenced by name within the kernel body and loaded into registers using ld.b32 %r1.param instructions.entry . .param { . and query instructions and cannot be accessed via ld. 160 January 24.PTX ISA Version 2.b32 x.reg . etc.

Parameters in register state space may be referenced directly within instructions in the function body. val1).0 with target sm_20 allows parameters in the .Chapter 10. Variadic functions are currently unimplemented.b32 rval. . Parameters in . PTX 2.b32 localVar. ret. .func (.func fname (param-list) function-body .param space are accessed using ld.param instructions in the body. Parameter passing is call-by-value. … Description // return value in fooval January 24. implements an ABI with stack. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.x code. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Parameters must be base types in either the register or parameter state space. parameters must be in the register state space. and recursion is illegal. and supports recursion. … use N.0. which may use a combination of registers and stack locations to pass parameters.func fname function-body . there is no stack. foo. PTX ISA 2.b32 N. mov. including input and return parameters and optional function body. if any.result.reg . other code. 2010 161 .f64 dbl) { .reg .param and st. Variadic functions are represented using ellipsis following the last fixed argument.func . The parameter lists define locally-scoped variables in the function body. The implementation of parameter passing is left to the optimizing translator. (val0. Directives Table 133.reg .func Syntax Function definition.0 with target sm_20 supports at most one return value. .param state space. Supported on all target architectures. } … call (fooval).2 for a description of variadic functions.reg .func (ret-param) fname (param-list) function-body Defines a function.func definition with no body provides a function prototype. Kernel and Function Directives: .b32 rval) foo (. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. dbl. Release Notes For PTX ISA version 1. A .

PTX ISA Version 2. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. Note that . The .g. or as statements within a kernel or device function body. at entry-scope. The interpretation of .maxntid and . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. 162 January 24. the . and the strings have no semantics within the PTX virtual machine model.pragma directive is supported for passing information to the PTX backend.3.maxnctapersm (deprecated) . and . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.minnctapersm directives may be applied per-entry and must appear between an .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. registers) to increase total thread count and provide a greater opportunity to hide memory latency.entry directive and its body.pragma directives may appear at module (file) scope.maxntid directive specifies the maximum number of threads in a thread block (CTA). and the . the .maxntid.maxnreg. which pass information to the backend optimizing compiler. The directives take precedence over any module-level constraints passed to the optimizing backend. The directive passes a list of strings to the backend. 2010 .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. . for example. PTX supports the following directives.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxntid .maxnreg . A general .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).minnctapersm . .0 10.pragma The . These can be used. to throttle the resource requirements (e. Currently.

This maximum is specified by giving the maximum extent of each dimention of the 1D. . 2D. Introduced in PTX ISA version 1. the backend may be able to compile to fewer registers.maxntid . The compiler guarantees that this limit will not be exceeded.maxntid nx . Supported on all target architectures. ny . The actual number of registers used may be less.maxnreg n Declare the maximum number of registers per thread in a CTA. Introduced in PTX ISA version 1. ny.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Directives Table 134.3.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.entry bar .entry foo .maxntid nx. The maximum number of threads is the product of the maximum extent in each dimension. .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. . Performance-Tuning Directives: .16. or the maximum number of registers may be further constrained by . for example. .entry foo .maxntid and . 2010 163 .maxntid 16.maxctapersm.maxntid Syntax Maximum number of threads in thread block (CTA). Supported on all target architectures.maxntid 256 . Exceeding any of these limits results in a runtime error or kernel launch failure.Chapter 10.maxntid nx.3. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxnreg . Performance-Tuning Directives: . nz Declare the maximum number of threads in the thread block (CTA). or 3D CTA.

minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).entry foo .maxnctapersm. additional CTAs may be mapped to a single multiprocessor.maxntid and .maxntid 256 .0 Table 136. For this reason.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.entry foo .minnctapersm in PTX ISA version 2.maxnctapersm (deprecated) . Performance-Tuning Directives: .maxntid to be specified as well.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. .0.minnctapersm generally need .minnctapersm .maxntid to be specified as well.3. Supported on all target architectures. .0. Introduced in PTX ISA version 2. The optimizing backend compiler uses .PTX ISA Version 2. 2010 . . Introduced in PTX ISA version 1.maxnctapersm has been renamed to .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm generally need . However. Optimizations based on .0 as a replacement for .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Deprecated in PTX ISA version 2. .minnctapersm 4 { … } 164 January 24. Supported on all target architectures. . Optimizations based on . if the number of registers used by the backend is sufficiently lower than this bound.maxntid 256 . Performance-Tuning Directives: .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.

0.pragma Syntax Description Pass directives to PTX backend compiler.pragma directive strings is implementation-specific and has no impact on PTX semantics. Directives Table 138.pragma directive may occur at module-scope. See Appendix A for descriptions of the pragma strings defined in ptxas.Chapter 10. { … } January 24. or at statementlevel. .pragma “nounroll”. Pass module-scoped. Supported on all target architectures. . entry-scoped. 2010 165 . Introduced in PTX ISA version 2. or statement-level directives to the PTX backend compiler. Performance-Tuning Directives: . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . The .pragma .pragma list-of-strings .pragma “nounroll”.entry foo . The interpretation of . at entry-scope.

.0.4.0 and replaces the @@DWARF syntax. replaced by .0 10.. 0x00. 0x00.loc The . 0x5f736f63 .file .4byte .section directive.byte byte-list // comma-separated hexadecimal byte values . 0x00 166 January 24.4byte 0x000006b5.debug_info .2.section . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x00.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Table 139.0 but is supported for legacy PTX version 1. “”.4byte 0x6e69616d. 0x61395a5f. 0x00000364.4byte int32-list // comma-separated hexadecimal integers in range [0. 0x63613031. 0x00.PTX ISA Version 2. 0x02. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . Introduced in PTX ISA version 1. Supported on all target architectures.debug_pubnames.section directive is new in PTX ISA verison 2.232-1] . 0x00. The @@DWARF syntax is deprecated as of PTX version 2. 0x6150736f.264-1] .byte 0x2b. @progbits . Deprecated as of PTX 2. 0x00 . 0x736d6172 .section .byte 0x00. 2010 . @@DWARF dwarf-string dwarf-string may have one of the .x code.quad int64-list // comma-separated hexadecimal integers in range [0. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x00.4byte label .

debug_pubnames { . 0x00. . .debug_info .b32 0x000006b5.264-1] .. .232-1] . . .section . 0x63613031.section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00. Debugging Directives: .b64 int64-list // comma-separated list of integers in range [0.b8 byte-list // comma-separated list of integers in range [0. } 0x02. Source file location.0.section Syntax PTX section definition. Supported on all target architectures.b32 int32-list // comma-separated list of integers in range [0.b32 .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.file . 0x00. Supported on all target architectures. replaces @@DWARF syntax. 2010 167 .b8 0x2b.b32 0x6e69616d.255] . 0x00.Chapter 10. . Supported on all target architectures..loc line_number January 24.0.b8 0x00. 0x00. Debugging Directives: . .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 label ..loc .section . Directives Table 140. 0x00 0x61395a5f.0.file filename Table 142.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x736d6172 0x00 Table 141. 0x5f736f63 0x6150736f. 0x00. 0x00000364. Source file information. Debugging Directives: .

extern . Linking Directives: .0. Supported on all target architectures. Linking Directives .extern .0 10. .PTX ISA Version 2.visible identifier Declares identifier to be externally visible. . 2010 .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.b32 foo.global .extern .extern identifier Declares identifier to be defined externally.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.b32 foo.visible Table 143.visible .visible . Introduced in PTX ISA version 1. // foo will be externally visible 168 January 24. . Introduced in PTX ISA version 1. .0.global . // foo is defined in another module Table 144.6. Supported on all target architectures. Linking Directives: .

0.0 driver r195 PTX ISA Version PTX ISA 1.0 CUDA 2.0 PTX ISA 1.3 driver r190 CUDA 3.1 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.2 CUDA 2.Chapter 11.4 PTX ISA 1.3 PTX ISA 1. CUDA Release CUDA 1.0 CUDA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.0 January 24. The first section describes ISA and implementation changes in the current release of PTX ISA 2. 2010 169 .1 CUDA 2.1 CUDA 2.5 PTX ISA 2.2 PTX ISA 1. The release history is as follows.

The mad.ftz and . The .x code and sm_1x targets. fma.rp rounding modifiers for sm_20 targets. Single-precision add. Both fma. The fma.and double-precision div. rcp. sub.1. Single. 2010 .rn.f32 require a rounding modifier for sm_20 targets. while maximizing backward compatibility with legacy PTX 1.1.1.f32 requires sm_20.ftz modifier may be used to enforce backward compatibility with sm_1x. The mad.1. and mul now support .0 for sm_20 targets.f32 for sm_20 targets.f32 maps to fma. The changes from PTX ISA 1. New Features 11.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. • • • • • 170 January 24.0 11. Floating-Point Extensions This section describes the floating-point changes in PTX 2.f32.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices.f32 instruction also supports .f32 and mad. and sqrt with IEEE 754 compliant rounding have been added.sat modifiers.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 11.PTX ISA Version 2. Instructions testp and copysign have been added.rm and . mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Changes in Version 2.1. The goal is to achieve IEEE 754 compliance wherever possible. A single-precision fused multiply-add (fma) instruction has been added.1. These are indicated by the use of a rounding modifier and require sm_20.

3.1.1. has been added. 11. bar now supports optional thread count and register operands. isspacep. for prefetching to specified level of memory hierarchy.lt. has been added.red}. Bit field extract and insert instructions. A “bit reversal” instruction. prefetch. New instructions A “load uniform” instruction. st. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.arrive instruction has been added.red.{and. bfe and bfi. A “count leading zeros” instruction. Instruction sust now supports formatted surface stores. st. Video instructions (includes prmt) have been added. have been added. .clamp modifiers. Instructions {atom.maxnctapersm directive was deprecated and replaced with . 2010 171 . cvta. has been added. January 24. has been added.le.ballot. A system-level membar instruction. Instructions prefetch and prefetchu have also been added.f32 have been implemented. %lanemask_{eq. Other new features Instructions ld.Chapter 11. prefetchu. New special registers %nsmid.shared have been extended to handle 64-bit data types for sm_20 targets.gt} have been added. membar.section. Release Notes 11. vote. has been added. Surface instructions support additional .add. A new directive.1. and shared addresses to generic address and vice-versa has been added.u32 and bar. e. Instructions {atom. . Cache operations have been added to instructions ld. has been added.clamp and .ge.b32.or}.red}. Instructions bar. and sust.minnctapersm to better match its behavior and usage. brev. A “population count” instruction. popc. The .zero. ldu.sys.red. and red now support generic addressing. The bar instruction has been extended as follows: • • • A bar. A “vote ballot” instruction.1. has been added. bfind. A “find leading non-sign bit” instruction.g. local. clz.pred have been added. Instruction cvta for converting global. %clock64. atom.popc. ldu. suld.2. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.

p. has been fixed. or .1. 11.3. See individual instruction descriptions for details. Formatted surface load is unimplemented.p sust.0 11.f32. 2010 .2. if .f32 type is unimplemented. 172 January 24. Formatted surface store with .{min. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. where .PTX ISA Version 2.f32} atom.5 and later. stack-based ABI is unimplemented. Instruction bra.1. The underlying.4 and earlier. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.{u32.ftz for PTX ISA versions 1.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.5. Support for variadic functions and alloca are unimplemented.version is 1. cvt. call suld. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.s32. To maintain compatibility with legacy PTX code. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. the correct number is sixteen.u32. In PTX version 1. {atom. .ftz (and cvt for . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.max} are not implemented.target sm_1x. Semantic Changes and Clarifications The errata in cvt.red}.4 or earlier.s32.

with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Descriptions of . Table 145. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Appendix A. Ignored for sm_1x targets.pragma. .pragma “nounroll”. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. 2010 173 . . L1_body: … L1_continue: bra L1_head. disables unrolling of0 the loop for which the current block is the loop header. and statement levels. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. L1_end: … } // do not unroll this loop January 24. entry-function.pragma Strings This section describes the .func bar (…) { … L1_head: .pragma “nounroll”.pragma strings defined by ptxas. including loops preceding the . … @p bra L1_end.entry foo (…) . disables unrolling for all loops in the entry function body. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.0. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. The “nounroll” pragma is allowed at module. Note that in order to have the desired effect at statement level. Supported only for sm_20 targets. { … } // do not unroll any loop in this function .pragma “nounroll”.

PTX ISA Version 2. 2010 .0 174 January 24.

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