NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

.. 33 Fundamental Types ... and Vectors .............. 29 Global State Space ................... 6............................... 5........ 6..... Abstracting the ABI ..............................5.............................................................2........5................................................. 29 Local State Space ......................PTX ISA Version 2........................ 37 Vectors ................ 5..2....4............................... 27 Register State Space .................. 46 6................ 42 Addresses as Operands .......1..................................................... 30 Shared State Space............................................................................. 6............................................. 34 Variables ................................................................ State Spaces ...... 38 Alignment ..............................................................4.............. 5.................4.............. 49 7........1........................................ 5. Operand Costs ........... 41 Source Operands..................................................4...............4............................... 28 Special Register State Space ...................................................................................................................................................................... 28 Constant State Space ............................................. 5.............2.....................................................................3.................2......................4....... 6.... 47 Chapter 7........................4...........1... 5...1..... 43 6....... 5.... Operand Type Information ............................................. 6.......................................................................1........................................................... Function declarations and definitions ..... Type Conversion........3.............. 37 Variable Declarations ................................................4................... 5......2.............. 42 Arrays as Operands .3........................4....................................................................................................................5......................1............ 5.1.............4....1............ Types........ 41 Using Addresses. 33 Restricted Use of Sub-Word Sizes .............1.....1..........0 4................ Types .........................................................1.......... 5........................... 6.......................... 43 Labels and Function Names as Operands .............................................1.................................................1................5........ 41 6....................................... 49 ii January 24................................................... and Variables ..........................3........................................3.....................4....................................... 37 Array Declarations ................................................5.............. 44 Rounding Modifiers ............................................ 5....................................4....6.... 6................................................ 27 5......................... 6....... State Spaces.......... 5..............................................2....................4........................................4.............................. 5....................... 39 Parameterized Variable Names .............................................................2................... Arrays........ Sampler.................6..... 33 5... 25 Chapter 5............................1......1.............................................. 41 Destination Operands .. 38 Initializers ....... Chapter 6............................... Summary of Constant Expression Evaluation Rules ........6........ Instruction Operands.7...............2.................................. 5.................................... 6..............2.................................................................................... 43 Vectors as Operands ......................................... 5........4... 44 Scalar Conversions ..6...................... 29 Parameter State Space ............. 32 Texture State Space (deprecated) ................5..................................... and Surface Types .......... Texture........................................... 5.............1.......................................... 32 5................... 2010 .............................................................................................. 39 5...................8.

....................x ....... 52 Variadic functions .. 53 Alloca ......1........... Chapter 9......................................................6....................................................... 8................... 104 Data Movement and Conversion Instructions ............7...................... Changes from PTX 1................................................. 10........................................................ 129 Parallel Synchronization and Communication Instructions .....................................1...................... 149 Chapter 10............................................................ 8...................................... Divergence of Threads in Control Constructs .........7.....1.......................................................... 7.......................................... PTX Version and Target Directives ...2.................... 56 Comparisons ................................. 8.. 58 8................................................. 132 Video Instructions ... 170 New Features ...........5.. 60 8........... 62 Semantics .................4.......... 8........... 8...................................... 172 January 24..................................7.................................................................................................................. 62 Machine-Specific Semantics of 16-bit Code ............0 ........................... 172 Unimplemented Features Remaining .... 8............................................................................... 62 8....1................ 8....... 166 Linking Directives .. 8.............. 108 Texture and Surface Instructions ............................ Type Information for Instructions and Operands ..1...............1.................................1.................................................................................................1.......... 81 Comparison and Selection Instructions ...................... 55 8.................... 147 8. 55 PTX Instructions ............................................... Instruction Set ........................................ 140 Miscellaneous Instructions................. 169 11........................ 11.. 11...................................................................................... 10.... 8................... 8..8.. 8............................ 157 10. 168 Chapter 11............................................................................................................7.......................................................... 7.......... 11...................................................1........................9..........3................... Changes in Version 2.6... 8..... 8... 8...................................................... 162 Debugging Directives ......... 63 Integer Arithmetic Instructions ............. 157 Specifying Kernel Entry Points and Functions .. 59 Operand Size Exceeding Instruction-Type Size ..............2............................................ 63 Floating-Point Instructions ........3................2.....................4..1.7.................................................... Directives ........10................................................. 170 Semantic Changes and Clarifications ........................2........................2.. 122 Control Flow Instructions .......3......................................3........................................................1..........................................................3... 8............7...............................................................................4..................... 54 Chapter 8.......................................... 55 Predicated Execution .... 2010 iii ................................................3. Format and Semantics of Instruction Descriptions ............ Special Registers ........4..................................7...............7......................................................... Instructions ................................................... 160 Performance-Tuning Directives ......5................7............... 8..6..........1...............................................................................6.....7.............................1...................... 10.. 10..........7...........................7.... Release Notes .................. 57 Manipulating Predicates ........7....2................................................................3.................................... 100 Logic and Shift Instructions ....................

................ 173 iv January 24.........pragma Strings.... Descriptions of .0 Appendix A......... 2010 ..........PTX ISA Version 2...................

........................................... Unsigned Integer........................................................... 57 Floating-Point Comparison Operators Accepting NaN . 64 Integer Arithmetic Instructions: sub .......................................................................... Table 21......................................................................................................... 60 Relaxed Type-checking Rules for Destination Operands................................................................................... 25 State Spaces ... Table 4.............. Table 28.. 59 Relaxed Type-checking Rules for Source Operands ................................................................................ Table 22............ 28 Fundamental Type Specifiers .. Table 15............................ 46 Integer Rounding Modifiers ............. 64 Integer Arithmetic Instructions: add... Table 14..................................... Table 24....................................................................................... and Bit-Size Types ................ Table 29.... 35 Opaque Type Fields in Independent Texture Mode ... 66 Integer Arithmetic Instructions: subc ............................................. Table 6....... 70 Integer Arithmetic Instructions: sad .................................... 23 Constant Expression Evaluation Rules ...................................................................... Table 20................................................................. 58 Type Checking Rules ...................... 19 Predefined Identifiers ....................... Table 25......................................................... Table 13........... Table 16.............................. Table 12..................... 67 Integer Arithmetic Instructions: mad ... 69 Integer Arithmetic Instructions: mad24 ................... Table 19............................ 18 Reserved Instruction Keywords ................................. 46 Cost Estimates for Accessing State-Spaces ....... 20 Operator Precedence .................... 57 Floating-Point Comparison Operators ................................................ 71 January 24.................................. Table 9......................................................................................................................................................... 66 Integer Arithmetic Instructions: mul ...................cc ................................................ Table 2........... Table 17................................................... 65 Integer Arithmetic Instructions: sub...................................................... 65 Integer Arithmetic Instructions: addc .......................................... Table 7..... 58 Floating-Point Comparison Operators Testing for NaN ...............List of Tables Table 1...................................................... Table 31.. 2010 v ............. Table 27.................................................................... Table 23........................... Table 8................... 47 Operators for Signed Integer................................. Table 3........................ 45 Floating-Point Rounding Modifiers ................... Table 30............................... Table 10................................................................................. 33 Opaque Type Fields in Unified Texture Mode ................... Table 5........ Table 32.......................................................................................................... Table 18...... 27 Properties of State Spaces .cc ....................................................... Table 11................................. Table 26............................... 61 Integer Arithmetic Instructions: add ............ PTX Directives ... 35 Convert Instruction Precision and Format .... 68 Integer Arithmetic Instructions: mul24 ...................................

.......................... Table 45................... Table 48................ Table 62............................................................... 82 Floating-Point Instructions: testp ............................................................................. 71 Integer Arithmetic Instructions: abs ... 71 Integer Arithmetic Instructions: rem ........................ Table 63............................................... 95 Floating-Point Instructions: sin ........................................................... Table 60...................... Table 39............. Table 40.................................... 83 Floating-Point Instructions: add ...................... Table 43......................................................................... Table 35....................................... Table 65.......... Table 37............................................................... Table 53........................................................................ 91 Floating-Point Instructions: neg ........... Table 52............................................................................. 76 Integer Arithmetic Instructions: bfe ................................................................ 88 Floating-Point Instructions: div . 102 Comparison and Selection Instructions: selp .................................................. Table 42................................................................................................................................ Table 54.............................................................. Table 49....PTX ISA Version 2............................... 79 Summary of Floating-Point Instructions ......... 72 Integer Arithmetic Instructions: min .................. 74 Integer Arithmetic Instructions: bfind ............. 99 Comparison and Selection Instructions: set ......................... 73 Integer Arithmetic Instructions: popc ................................ 83 Floating-Point Instructions: copysign ..... 85 Floating-Point Instructions: mul ........ 93 Floating-Point Instructions: sqrt . 91 Floating-Point Instructions: min .... 90 Floating-Point Instructions: abs .............................................................. 98 Floating-Point Instructions: ex2 .............................................................. Table 58........................................................................... 86 Floating-Point Instructions: fma ................... 77 Integer Arithmetic Instructions: bfi .............. 87 Floating-Point Instructions: mad ..................... 103 Comparison and Selection Instructions: slct .. Table 47.................... Table 38.................................................................... Table 66...... 92 Floating-Point Instructions: max .. Table 61................................................... 92 Floating-Point Instructions: rcp ....... 73 Integer Arithmetic Instructions: max ................................................................................................................................. 101 Comparison and Selection Instructions: setp ... Table 67...................... 75 Integer Arithmetic Instructions: brev ..........................................0 Table 33.......................................... Table 56.... 84 Floating-Point Instructions: sub .... 103 vi January 24......................................... 94 Floating-Point Instructions: rsqrt .................................................................. Table 50........ 2010 ............................... Table 51...................................................... 74 Integer Arithmetic Instructions: clz .. 72 Integer Arithmetic Instructions: neg ...... Table 55............................................................................... 97 Floating-Point Instructions: lg2 .................. 78 Integer Arithmetic Instructions: prmt ..................... 96 Floating-Point Instructions: cos ........................................................................................................................................................... Table 64................. Table 46........... Table 69....................... Table 44............................................................... Table 59....................................................................................................................................... Table 68................... Table 34.. Table 36....... Table 41........................................................................................... Table 57................................................................................ Integer Arithmetic Instructions: div .

... Table 75................ vshr .............................................................. Table 72............... Table 101............................. 106 Logic and Shift Instructions: not .............................................................................. Table 89.............................................................................. 105 Logic and Shift Instructions: or ...................................... Table 88..................................................................... Table 71............... 110 Data Movement and Conversion Instructions: mov ..................................................... Table 81................................. 2010 vii .............................. 120 Texture and Surface Instructions: tex ..... 123 Texture and Surface Instructions: txq .............................. Table 87.............Table 70............ 142 Video Instructions: vshl.............................................. Table 99... Table 73...................................................... Logic and Shift Instructions: and ............. 106 Logic and Shift Instructions: cnot .................................................... Table 80............ 130 Control Flow Instructions: ret ...................................... 105 Logic and Shift Instructions: xor ......... Table 86.......................................................... Table 94...... Table 84........... vabsdiff................. 143 January 24.............................. prefetchu ...... Table 105....................................................... vmin.................... 133 Parallel Synchronization and Communication Instructions: membar ............. 112 Data Movement and Conversion Instructions: ld ................ Table 74............. 118 Data Movement and Conversion Instructions: isspacep .... 119 Data Movement and Conversion Instructions: cvt .................... 113 Data Movement and Conversion Instructions: ldu ......... vmax ................................................................. 129 Control Flow Instructions: bra .............. 135 Parallel Synchronization and Communication Instructions: red ... Table 78...... Table 85............... Table 77............ 129 Control Flow Instructions: @ ............................. 128 Control Flow Instructions: { } ................................................ Table 96......................... 107 Logic and Shift Instructions: shr ................................... 124 Texture and Surface Instructions: suld .... 125 Texture and Surface Instructions: sust ....................................................................... 137 Parallel Synchronization and Communication Instructions: vote .............. Table 100.. 134 Parallel Synchronization and Communication Instructions: atom ...................................................................... 131 Parallel Synchronization and Communication Instructions: bar ..... vsub............. Table 83......... 107 Cache Operators for Memory Load Instructions ............ 119 Data Movement and Conversion Instructions: cvta ...................................... 127 Texture and Surface Instructions: suq ... Table 93.. 130 Control Flow Instructions: call .......... 106 Logic and Shift Instructions: shl ............................ 126 Texture and Surface Instructions: sured............................... 139 Video Instructions: vadd............................................... 116 Data Movement and Conversion Instructions: prefetch.......... 111 Data Movement and Conversion Instructions: mov ............................................ Table 79......................... Table 92......................... Table 104........... Table 103........................................... Table 98.......... Table 76............................................................................ 131 Control Flow Instructions: exit ..................................................... 109 Cache Operators for Memory Store Instructions .......... Table 106.......................... Table 95......................... Table 102............... Table 97................................................................................................................ Table 91.......... Table 90............. 115 Data Movement and Conversion Instructions: st ................. Table 82.........

............ Table 129...............................................................................................maxnctapersm (deprecated) ... Table 133....version.................. Table 142............ Table 112........................... 167 Debugging Directives: . Table 126.. 156 Special Registers: %clock64 ........................................................... Table 113....................... Table 114..... Table 108............... 151 Special Registers: %nwarpid ............ Table 137....................... Table 119........ Table 136......................................................... 150 Special Registers: %laneid ........extern................................... 154 Special Registers: %lanemask_lt .......... 146 Miscellaneous Instructions: trap .... 166 Debugging Directives: ... 155 Special Registers: %lanemask_gt ..............maxntid ........... 163 Performance-Tuning Directives: .................... 155 Special Registers: %clock .............. 160 Kernel and Function Directives: .........section .................................... Table 131.................. Table 127..... Table 124.... Table 143............... Table 138..............target ........ 164 Performance-Tuning Directives: ...................... 154 Special Registers: %lanemask_le ................. 167 Debugging Directives: ......................... Table 116...................................................... 165 Debugging Directives: @@DWARF ............................................................. %pm1....................................................................................................func ................................. 152 Special Registers: %nctaid . Table 135........... Table 139. 153 Special Registers: %lanemask_eq ..................... Table 111.................... 156 Special Registers: %pm0............. %pm2.... %pm3 ...................................... Video Instructions: vmad ............loc ..................................................................................... Table 125......................................... 164 Performance-Tuning Directives: .. 168 viii January 24...................................................................................................... 157 PTX File Directives: .......... Table 118......................................................................................... 152 Special Registers: %smid ................................................................................................... Table 115........................................................................................................ Table 128....................................... 151 Special Registers: %warpid ....PTX ISA Version 2.................................................. 156 PTX File Directives: .......................................... Table 132... Table 130........... Table 121................................................................................................ Table 110.... 153 Special Registers: %nsmid ... Table 134......................................... 147 Miscellaneous Instructions: brkpt .......... 158 Kernel and Function Directives: ....... Table 122...file ............................................................................. Table 117................ 154 Special Registers: %lanemask_ge ... Table 120................................................................... 163 Performance-Tuning Directives: ...................................... 150 Special Registers: %ntid ......maxnreg .................... 151 Special Registers: %ctaid .... Table 140.......pragma .. Table 141...................................minnctapersm ................... Table 123...... 147 Special Registers: %tid ................................................................................................................................................................................. Table 109............................................................................entry...................0 Table 107............................ 2010 .......... 144 Video Instructions: vset.......................... 161 Performance-Tuning Directives: .................................................................................................................................................... 167 Linking Directives: .............. 147 Miscellaneous Instructions: pmevent...................... 153 Special Registers: %gridid ......................................

......................Table 144................................. 2010 ix ............. 173 January 24..... 168 Pragma Strings: “nounroll” ..... Table 145............................ Linking Directives: ..............................................visible...................

2010 .PTX ISA Version 2.0 x January 24.

1. the programmable GPU has evolved into a highly parallel. high-definition 3D graphics.Chapter 1. stereo vision.2. from general signal processing or physics simulation to computational finance or computational biology. and pattern recognition can map image blocks and pixels to parallel processing threads. image and media processing applications such as post-processing of rendered images. video encoding and decoding. Because the same program is executed for each data element. PTX defines a virtual machine and ISA for general purpose parallel thread execution. and because it is executed on many data elements and has high arithmetic intensity. Similarly. Introduction This document describes PTX. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. 1. PTX exposes the GPU as a data-parallel computing device. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. In fact. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). image scaling. Data-parallel processing maps data elements to parallel processing threads. which are optimized for and translated to native target-architecture instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. multithreaded. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. the memory access latency can be hidden with calculations instead of big data caches. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. January 24.1. 2010 1 . PTX programs are translated at install time to the target hardware instruction set. there is a lower requirement for sophisticated flow control.

with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Provide a common source-level ISA for optimizing code generators and translators. fma. addition of generic addressing to facilitate the use of general-purpose pointers. Improved Floating-Point Support A main area of change in PTX 2.f32 requires sm_20. PTX 2. Instructions marked with . 1. and all PTX 1. barrier. Facilitate hand-coding of libraries. 2010 .0 is a superset of PTX 1.rn.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. and architecture tests.3.0 PTX ISA Version 2.x features are supported on the new sm_20 target. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.f32. The mad.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. A “flush-to-zero” (.3.PTX ISA Version 2.0 are improved support for IEEE 754 floating-point operations. When code compiled for sm_1x is executed on sm_20 devices. PTX ISA Version 2. • • • 2 January 24.ftz) modifier may be used to enforce backward compatibility with sm_1x. Provide a machine-independent ISA for C/C++ and other compilers to target.1. atomic.f32 and mad. Both fma.f32 require a rounding modifier for sm_20 targets.f32 instruction also supports .rp rounding modifiers for sm_20 targets.sat modifiers.f32 maps to fma. and video instructions.x code will continue to run on sm_1x targets as well. and mul now support . sub.rm and .ftz and .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Legacy PTX 1. The main areas of change in PTX 2. reduction.f32 for sm_20 targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Achieve performance in compiled applications comparable to native GPU performance. including integer. surface. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. A single-precision fused multiply-add (fma) instruction has been added. Provide a code distribution ISA for application and middleware developers. The changes from PTX ISA 1.0 is in improved support for the IEEE 754 floating-point standard. 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. memory. Most of the new features require a sm_20 target. and the introduction of many new instructions. The mad.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.x. Single-precision add. mad. performance kernels. The fma. which map PTX to specific target machines.

and red now support generic addressing. and shared state spaces. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. instructions ld. • Taken as a whole. prefetch. so recursion is not yet supported. local. for prefetching to specified level of memory hierarchy. January 24. 2010 3 . 1. New Instructions The following new instructions. . Introduction • Single.3. these changes bring PTX 2.g.and double-precision div. Cache operations have been added to instructions ld. cvta.2. and sust.zero.0 closer to full compliance with the IEEE 754 standard. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.4. e. Support for an Application Binary Interface Rather than expose details of a particular calling convention. Generic addressing unifies the global.3.. st. atom.clamp and . stack-based ABI. and directives are introduced in PTX 2. ldu. suld. These are indicated by the use of a rounding modifier and require sm_20.0. A new cvta instruction has been added to convert global. local. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. prefetchu. st. Instruction cvta for converting global. and shared addresses to generic address and vice-versa has been added. stack layout. Generic Addressing Another major change is the addition of generic addressing. allowing memory instructions to access these spaces without needing to specify the state space.e. Surface Instructions • • Instruction sust now supports formatted surface stores. and sqrt with IEEE 754 compliant rounding have been added. and shared addresses to generic addresses. an address that is the same across all threads in a warp. Surface instructions support additional clamp modifiers. and vice versa.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Instructions testp and copysign have been added. i. special registers. 1. Instructions prefetch and prefetchu have been added. and Application Binary Interface (ABI).3. rcp. NOTE: The current version of PTX does not implement the underlying.Chapter 1. In PTX 2. local. isspacep. 1. PTX 2.3.0.

has been added. A new directive. vote.PTX ISA Version 2.red.red.shared have been extended to handle 64-bit data types for sm_20 targets. New special registers %nsmid.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.le. A “vote ballot” instruction. bfi bit field extract and insert popc clz Atomic. Instructions bar.ge.add. and Vote Instructions • • • New atomic and reduction instructions {atom. A bar.red}.section.f32 have been added.popc. Instructions {atom.arrive instruction has been added. %lanemask_{eq.pred have been added. 2010 .u32 and bar.ballot. bar now supports an optional thread count and register operands.or}. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Reduction.b32. Other Extensions • • • Video instructions (includes prmt) have been added. has been added. %clock64.lt.red}.gt} have been added. Barrier Instructions • • A system-level membar instruction.{and. . membar. 4 January 24.sys.

types. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.0. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 8 describes the instruction set. Chapter 10 lists the assembly directives supported in PTX.Chapter 1. Chapter 5 describes state spaces. Chapter 9 lists special registers. Chapter 6 describes instruction operands.4. calling convention. Chapter 3 gives an overview of the PTX virtual machine model. and variable declarations. Chapter 11 provides release notes for PTX Version 2. January 24. Chapter 7 describes the function and call syntax. 2010 5 . Introduction 1. Chapter 4 describes the basic syntax of the PTX language.

2010 .0 6 January 24.PTX ISA Version 2.

compute addresses. To that effect.2. A cooperative thread array. or 3D CTA. The vector ntid specifies the number of threads in each CTA dimension. can be isolated into a kernel function that is executed on the GPU as many different threads.1. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. (with elements tid.z) that specifies the thread’s position within a 1D. Each CTA thread uses its thread identifier to determine its assigned role. Threads within a CTA can communicate with each other. 2D. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2D. Each CTA has a 1D. ntid. Each thread has a unique thread identifier within the CTA.y. tid. but independently on different data. compute-intensive portions of applications running on the host are off-loaded onto the device. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. is an array of threads that execute a kernel concurrently or in parallel.z). or host: In other words. or 3D shape specified by a three-element vector ntid (with elements ntid.x. assign specific input and output positions. Programming Model 2.y.1. It operates as a coprocessor to the main CPU. January 24. Cooperative thread arrays (CTAs) implement CUDA thread blocks. To coordinate the communication of the threads within the CTA. a portion of an application that is executed many times.x. More precisely. work. 2. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. Programs use a data parallel decomposition to partition inputs. data-parallel. and results across the threads of the CTA. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. 2010 7 .Chapter 2. 2.2. The thread identifier is a three-element vector tid. and tid. and ntid. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. or CTA. and select work to perform.

PTX ISA Version 2.2. because threads in different CTAs cannot communicate and synchronize with each other. so PTX includes a run-time immediate constant. Threads within a warp are sequentially numbered. CTAs that execute the same kernel can be batched together into a grid of CTAs. 2D . The host issues a succession of kernel invocations to the device. Each grid also has a unique temporal grid identifier (gridid). %ntid. Multiple CTAs may execute concurrently and in parallel. However. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. %nctaid. 2010 . and %gridid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. The warp size is a machine-dependent constant. which may be used in any instruction where an immediate operand is allowed. such that the threads execute the same instructions at the same time. depending on the platform. %ctaid. so that the total number of threads that can be launched in a single kernel invocation is very large. or sequentially. WARP_SZ. multiple-thread) fashion in groups called warps.0 Threads within a CTA execute in SIMT (single-instruction. a warp has 32 threads. 2. A warp is a maximal subset of threads from a single CTA. This comes at the expense of reduced thread communication and synchronization. or 3D shape specified by the parameter nctaid. Typically. read-only special registers %tid. Some applications may be able to maximize performance with knowledge of the warp size. Each grid of CTAs has a 1D. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1).2. Threads may read and use these values through predefined. 8 January 24.

1) Thread (0. 0) Thread (3. Figure 1. 2) Thread (4.Chapter 2. A grid is a set of CTAs that execute independently. 0) CTA (0. 2010 9 . 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2) Thread (1. 0) Thread (2. 1) Thread (3. 0) Thread (1. Thread Batching January 24. 2) Thread (3. 1) Thread (2. 0) CTA (2. 1) Thread (1. 1) Thread (4. 1) Thread (0. 0) Thread (0. 0) CTA (1. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) CTA (1. 1) CTA (2. 0) Thread (4.

Both the host and the device maintain their own local memory. 2010 . Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant.PTX ISA Version 2. and texture memory spaces are optimized for different memory usages. respectively. The device memory may be mapped and read or written by the host. Finally. for some specific data formats. referred to as host memory and device memory. all threads have access to the same global memory. or.0 2. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. 10 January 24. and texture memory spaces are persistent across kernel launches by the same application. constant. The global. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2.3. Texture memory also offers different addressing modes. for more efficient transfer. as well as data filtering. Each thread has a private local memory.

2) Figure 2. 1) Block (1. 0) Block (0.Chapter 2. 0) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Block (1. 2010 11 . 1) Grid 1 Global memory Block (0. 0) Block (2. 0) Block (0. 1) Block (1. 1) Block (2. Memory Hierarchy January 24. 0) Block (1.

2010 .PTX ISA Version 2.0 12 January 24.

the warp serially executes each branch path taken. multiple-thread). a multithreaded instruction unit. the first parallel thread technology. each warp contains threads of consecutive. a voxel in a volume. (This term originates from weaving. If threads of a warp diverge via a data-dependent conditional branch. 2010 13 . A multiprocessor consists of multiple Scalar Processor (SP) cores. allowing. it splits them into warps that get scheduled by the SIMT unit. A warp executes one common instruction at a time. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. manages. and executes concurrent threads in hardware with zero scheduling overhead. When a host program invokes a kernel grid. manages. To manage hundreds of threads running several different programs. Parallel Thread Execution Machine Model 3. When a multiprocessor is given one or more thread blocks to execute. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. The multiprocessor maps each thread to one scalar processor core. The way a block is split into warps is always the same. the multiprocessor employs a new architecture we call SIMT (single-instruction. different warps execute independently regardless of whether they are executing common or disjointed code paths.1. and on-chip shared memory. schedules. disabling threads that are not on that path. As thread blocks terminate. Branch divergence occurs only within a warp. for example. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). and executes threads in groups of parallel threads called warps. The multiprocessor creates. January 24. a cell in a grid-based computation). the threads converge back to the same execution path. At every instruction issue time. so full efficiency is realized when all threads of a warp agree on their execution path. and each scalar thread executes independently with its own instruction address and register state.Chapter 3. The multiprocessor SIMT unit creates. It implements a single-instruction barrier synchronization. and when all paths complete. increasing thread IDs with the first warp containing thread 0. new blocks are launched on the vacated multiprocessors. The threads of a thread block execute concurrently on one multiprocessor.

Vector architectures. as well as data-parallel code for coordinated threads. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. If an atomic instruction executed by a warp reads. which is a read-only region of device memory. which is a read-only region of device memory. but one of the writes is guaranteed to succeed. 2010 . A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. As illustrated by Figure 3. on the other hand. A multiprocessor can execute as many as eight thread blocks concurrently. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. In practice. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. 14 January 24. scalar threads. For the purposes of correctness. A key difference is that SIMD vector organizations expose the SIMD width to the software. write to that location occurs and they are all serialized. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. require the software to coalesce loads into vectors and manage divergence manually. In contrast with SIMD vector machines. modifies. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. the number of serialized writes that occur to that location and the order in which they occur is undefined. whereas SIMT instructions specify the execution and branching behavior of a single thread. each read. the programmer can essentially ignore the SIMT behavior. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. however. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. and writes to the same location in global memory for more than one of the threads of the warp. but the order in which they occur is undefined. SIMT enables programmers to write thread-level parallel code for independent.0 SIMT architecture is akin to SIMD (Single Instruction. the kernel will fail to launch. modify. If there are not enough registers or shared memory available per multiprocessor to process at least one block.PTX ISA Version 2. • The local and global memory spaces are read-write regions of device memory and are not cached.

2010 15 . Hardware Model January 24. Figure 3.Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

0 16 January 24. 2010 .PTX ISA Version 2.

Chapter 4. Source Format Source files are ASCII text. #if. whitespace is ignored except for its use in separating tokens in the language. Each PTX file must begin with a . Lines are separated by the newline character (‘\n’).version directive specifying the PTX language version. The following are common preprocessor directives: #include.1. See Section 9 for a more information on these directives. Syntax PTX programs are a collection of text source files. 4.target directive specifying the target architecture assumed. Lines beginning with # are preprocessor directives.2. and using // to begin a comment that extends to the end of the current line. followed by a . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. PTX is case sensitive and uses lowercase for keywords. 4. January 24. All whitespace characters are equivalent. #ifdef. using non-nested /* and */ for comments that may span multiple lines. The C preprocessor cpp may be used to process PTX source files. Pseudo-operations specify symbol and addressing management. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. Comments Comments in PTX follow C/C++ syntax. #line. #define. 2010 17 . #else. #endif. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Comments in PTX are treated as whitespace.

b32 r1.global . Directive Statements Directive keywords begin with a dot. . 2010 . and terminated with a semicolon.param .version . Statements begin with an optional label and end with a semicolon. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.x. %tid. Statements A PTX statement is either a directive or an instruction. The destination operand is first. where p is a predicate register. r2. Instructions have an optional guard predicate which controls conditional execution.minnctapersm . 18 January 24.reg . or label names. r2.0 4.shared . and is written as @p.entry .3.3. r1.func . so no conflict is possible with user-defined identifiers. array[r1].PTX ISA Version 2.maxnctapersm .1.local .maxntid . ld. 0. mov. Examples: . Instruction keywords are listed in Table 2. The guard predicate follows the optional label and precedes the opcode. Operands may be register variables. The guard predicate may be optionally negated. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.b32 r1. address expressions. Table 1.align . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.reg .loc .tex .pragma .2. written as @!p.b32 r1. All instruction keywords are reserved tokens in PTX. 2.maxnreg .5. r2.global start: .visible 4. followed by source operands.global.f32 r2. shl. .target . constant expressions.extern .f32 array[N].const .3.section .sreg .file PTX Directives .b32 add.

Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.

digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign.4. underscore. digits. dollar. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. between user-defined variable names and compiler-generated names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or percentage character followed by one or more letters. or dollar characters.g.PTX ISA Version 2. or they start with an underscore. PTX allows the percentage sign as the first character of an identifier. 2010 . Table 3. listed in Table 3. %pm3 WARP_SZ 20 January 24. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. Many high-level languages such as C and C++ follow similar rules for identifier names. The percentage sign can be used to avoid name conflicts. ….0 4. e. except that the percentage sign is not allowed. underscore.

Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. 4. and bit-size types. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. These constants may be used in data initialization and as operands to instructions. 2010 21 . The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. Constants PTX supports integer and floating-point constants and constant expressions.5. the sm_1x and sm_20 targets have a WARP_SZ value of 32. floating-point. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. each integer constant is converted to the appropriate size based on the data or instruction type at its use. The syntax follows that of C.s64 or .u64. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. every integer constant has type . Syntax 4. Type checking rules remain the same for integer. hexadecimal. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.s64) unless the value cannot be fully represented in . When used in an instruction or data initialization. 4.Chapter 4. or binary notation.. i.2. To specify IEEE 754 single-precision floating point values.1. there is no suffix letter to specify size.s64 or the unsigned suffix is specified. literals are always represented in 64-bit double-precision format.e.. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. Integer literals may be written in decimal. octal. To specify IEEE 754 doubleprecision floating point values. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. the constant begins with 0d or 0D followed by 16 hex digits.u64).5.e. i. For predicate-type data and instructions. where the behavior of the operation depends on the operand types. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.5. Floating-point literals may be written with an optional decimal point and an optional signed exponent. Unlike C and C++. the constant begins with 0f or 0F followed by 8 hex digits. in which case the literal is unsigned (. zero values are FALSE and non-zero values are TRUE. integer constants are allowed and are interpreted as in C. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. 0[fF]{hexdigit}{8} // single-precision floating point January 24.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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f64 converted type constant literal + ! ~ Cast Binary (.u64 .Chapter 4.u64) (.f64 : .s64 .6.u64 .u64 .u64 .s64 .f64 integer integer integer integer integer int ?.f64 use usual conversions . .u64 1st unchanged.u64.u64 .f64 converted type .f64 integer .s64) + .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 . Syntax 4.s64 .s64 .s64 . Table 5.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 same as 1st operand .f64 use usual conversions .u64 zero or non-zero same as sources use usual conversions Result Type same as source . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 same as source . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 . 2010 25 .f64 use usual conversions .u64 . or .s64.s64 . 2nd is .5.f64 integer .

2010 .0 26 January 24.PTX ISA Version 2.

State Spaces A state space is a storage area with particular characteristics. shared by all threads. Name State Spaces Description Registers. defined per-grid.tex January 24. Shared. Global texture memory (deprecated). and properties of state spaces are shown in Table 5. access rights. The characteristics of a state space include its size. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. . 5. pre-defined. and level of sharing between threads. read-only memory. The list of state spaces is shown in Table 4. Special registers. Kernel parameters. and these resources are abstracted in PTX through state spaces and data types. defined per-thread. private to each thread. fast.reg . All variables reside in some state space. access speed. Addressable memory shared between threads in 1 CTA. platform-specific. Global memory.sreg .local . Read-only.const . addressability. Types.Chapter 5. the kinds of resources will be common across platforms. Table 6. Local memory.param .1. 2010 27 . or Function or local parameters.global . State Spaces. and Variables While the specific resources available in a given target GPU will vary.shared .

Address may be taken via mov instruction.param instruction. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).param (used in functions) . or as elements of vector tuples. Registers differ from the other state spaces in that they are not fully addressable. 2010 .e. Registers may be typed (signed integer. The number of registers is limited. causing changes in performance. 32-.1. and will vary from platform to platform. 28 January 24. floating point.reg . such as grid. or 64-bits.param instructions.0 Table 7.global .const . The most common use of 8-bit registers is with ld. predicate) or untyped.sreg . and cvt instructions. unsigned integer. 3 Accessible only via the tex instruction. For each architecture. 1 Accessible only via the ld. platform-specific registers. and vector registers have a width of 16-.tex Restricted Yes No3 5. Special Register State Space The special register (.sreg) state space holds predefined. Register State Space Registers (.2. st. it is not possible to refer to the address of a register. i.reg state space) are fast storage locations.param (as input to kernel) .local . When the limit is exceeded. and performance monitoring registers. the parameter is then located on the stack frame and its address is in the . scalar registers have a width of 8-. Registers may have alignment boundaries required by multi-word loads and stores. 32-.local state space.1. aside from predicate registers which are 1-bit.. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.1. All special registers are predefined. and thread parameters.shared . Device function input parameters may have their address taken via mov. Register size is restricted. clock counters. CTA. 2 Accessible via ld.param and st. 5. 64-. 16-. register variables will be spilled to memory. or 128-bits.PTX ISA Version 2. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .

Multiple incomplete array variables declared in the same bank become aliases. It is the mechanism by which different CTAs and different grids can communicate.sync instruction. Types. bank zero is used. By convention.5. Local State Space The local state space (. Use ld. initialized by the host. the stack is in local memory. In implementations that support a stack. This pointer can then be used to access the entire 64KB constant bank.Chapter 5. all addresses are in global memory are shared.1.1. It is typically standard memory with cache.const[2] . State Spaces. Sequential consistency is provided by the bar.global to access global variables.const) state space is a read-only memory.const[bank] modifier. the bank number must be provided in the state space of the load instruction. Global State Space The global (.4. The size is limited. For any thread in a context. The remaining banks may be used to implement “incomplete” constant arrays (in C.global. each pointing to the start address of the specified constant bank.b32 const_buffer[].1. This reiterates the kind of parallelism available in machines that run PTX. as in lock-free and wait-free style programming.local to access local variables. for example). [const_buffer+4]. b = b – 1.3. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. as it must be allocated on a perthread basis. All memory writes prior to the bar. the declaration .sync instruction are guaranteed to be visible to any reads after the barrier instruction. To access data in contant banks 1 through 10. whereas local memory variables declared January 24.extern . where bank ranges from 0 to 10. results in const_buffer pointing to the start of constant bank two. Global memory is not sequentially consistent. 5. Module-scoped local memory variables are stored at fixed addresses. Threads wait at the barrier until all threads in the CTA have arrived. Consider the case where one thread executes the following two assignments: a = a + 1. If no bank number is given. where the size is not known at compile time. ld. Threads must be able to do their work without waiting for other threads to do theirs.global) state space is memory that is accessible by all threads in a context. st. For example. Use ld. there are eleven 64KB banks.global. an incomplete array in bank 2 is accessed as follows: . // load second word 5.const[2].extern .b32 %r1. and Variables 5. Constant State Space The constant (. For example.b32 const_buffer[]. The constant memory is organized into fixed size banks. Banks are specified using the . If another thread sees the variable b change. and atom.local) is private memory for each thread to keep its own data.local and st. For the current devices. bank zero is used for all statically-sized constant variables.const[2] . the store operation updating a may still be in flight. 2010 29 .

ld. Parameter State Space The parameter (.0 within a function or kernel body are allocated on the stack.PTX ISA Version 2. Example: . Note that PTX ISA versions 1. No access protection is provided between parameter and global space in this case.param instructions.1.entry foo ( . all local memory variables are stored at fixed addresses and recursive function calls are not supported. PTX code should make no assumptions about the relative locations or ordering of .u32 %n.6. 2010 .b32 len ) { . … 30 January 24. in some implementations kernel parameters reside in global memory. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param. Values passed from the host to the kernel are accessed through these parameter variables using ld.param space.u32 %ptr.reg .param .f64 %d.u32 %n. ld.param state space. [buffer]. … Example: . Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param instructions.0 and requires target architecture sm_20.param space variables.param.u32 %n. The resulting address is in the .reg . [%ptr].1. mov.1. Similarly. per-kernel versus per-thread). and (2b) to declare locally-scoped byte array variables that serve as function call arguments. typically for passing large structures by value to a function. 5.f64 %d.u32 %ptr. In implementations that do not support a stack. Therefore.align 8 . ld. The use of parameter state space for device function parameters is new to PTX ISA version 2.param. Note: The location of parameter space is implementation specific.param state space and is accessed using ld. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. device function parameters were previously restricted to the register state space. The address of a kernel parameter may be moved into a register using the mov instruction.b8 buffer[64] ) { .b32 N. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). 5. The kernel parameter variables are shared across all CTAs within a grid.x supports only kernel function parameters in .6. These parameters are addressable.param) state space is used (1) to pass input arguments from the host to the kernel.reg . read-only variables declared in the . For example. %n.param . len. .param . . [N].entry bar ( .

. Example: // pass object of type struct { double d.local and st. dbl. Aside from passing structures by value.f64 %d.param .param. the caller will declare a locally-scoped .s32 %y.param.1. State Spaces. int y. int y. which declares a . it is illegal to write to an input parameter or read from a return parameter.s32 x. st.param. Device Function Parameters PTX ISA version 2. }. a byte array in parameter space is used.reg . . and Variables 5.align 8 . … st.param . In PTX. . January 24. ld.param formal parameter having the same size and alignment as the passed argument. mystruct).func foo ( .6. such as C structures larger than 8 bytes. … See the section on function call syntax for more details.param.Chapter 5.s32 [mystruct+8]. The most common use is for passing objects by value that do not fit within a PTX register. . passed to foo … . It is not possible to use mov to get the address of a return parameter or a locally-scoped . is flattened. .b32 N. the address of a function input parameter may be moved into a register using the mov instruction.align 8 . (4.param. In this case.reg .b8 mystruct. Function input parameters may be read via ld.s32 %y.param space is also required whenever a formal parameter has its address taken within the called function. } mystruct. Types.f64 [mystruct+0].reg .local instructions.reg . … } // code snippet from the caller // struct { double d.f64 %d.0 extends the use of parameter space to device function parameters. [buffer+8]. This will be passed by value to a callee. .b8 buffer[12] ) { .param space variable. 2010 31 .f64 dbl. Typically.param byte array variable that represents a flattened C structure or union. ld. and so the address will be in the .local state space and is accessed via ld.param and function return parameters may be written using st.reg . call foo. [buffer]. Note that the parameter will be copied to the stack if necessary.2. x.

The texture name must be of type . For example. Multiple names may be bound to the same physical texture identifier.tex .tex) state space is global memory accessed via the texture instruction.texref.u32 . Another is sequential access from sequential threads.tex state space are equivalent to module-scoped . a legacy PTX definitions such as . An error is generated if the maximum number of physical resources is exceeded.6 for its use in texture instructions. An address in shared memory can be read and written by any thread in a CTA. A texture’s base address is assumed to be aligned to a 16-byte boundary.global state space. where texture identifiers are allocated sequentially beginning with zero.0 5.texref tex_a.u32 tex_a.PTX ISA Version 2.u64.shared) state space is a per-CTA region of memory for threads in a CTA to share data. It is shared by all threads in a context.tex . Use ld. 5.texref variables in the . See Section 5. tex_d.1. Shared memory typically has some optimizations to support the sharing.global . Physical texture resources are allocated on a per-module granularity.1.tex .7.tex directive will bind the named texture memory variable to a hardware texture identifier.tex .tex . Texture State Space (deprecated) The texture (. Shared State Space The shared (. Texture memory is read-only. tex_d.shared to access shared variables.shared and st. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. One example is broadcast. is equivalent to .3 for the description of the . 32 January 24.u32 tex_a. and variables declared in the .8. where all threads read from the same address.u32 . Example: . and programs should instead reference texture memory through variables of type .texref type and Section 8. 2010 . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). tex_c. and . The .u32 or .tex variables are required to be defined in the global scope.tex directive is retained for backward compatibility. The .7. tex_f.u32 .

s64 . and .Chapter 5.2. stored. The bitsize type is compatible with any fundamental type having the same size. the fundamental types reflect the native data types supported by the target architectures. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . .s8. Operand types and sizes are checked against instruction types for compatibility.2. . . Types 5. For example.u64 .u32. .f64 .u8.f16 floating-point type is allowed only in conversions to and from .2.f16. 5. stored. . needed to fully specify instruction behavior. and Variables 5. but typed variables enhance program readability and allow for better operand type checking. Register variables are always of a fundamental type. ld. For convenience. The following table lists the fundamental type specifiers for each basic type: Table 8. January 24. A fundamental type specifies both a basic type and a size.f32 and .b16.b8. and cvt instructions. The .s16. . State Spaces. The same typesize specifiers are used for both variable definitions and for typing instructions. so that narrow values may be loaded.2. st. all variables (aside from predicates) could be declared using only bit-size types.b8 instruction types are restricted to ld.b32. .u16. . Fundamental Types In PTX. . Restricted Use of Sub-Word Sizes The . . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Two fundamental types are compatible if they have the same basic type and are the same size.f32 and .u8.f64 types.f64 types. st. and instructions operate on these types. 2010 33 . so their names are intentionally short. or converted to other types and sizes. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. . In principle.s32.b64 . and converted using regular-width registers. Signed and unsigned integer types are compatible if they have the same size. All floating-point instructions operate only on .s8.f32.1.pred Most instructions have one or more type specifiers. Types. .

The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. and de-referenced by texture and surface load. texture and sampler information each have their own handle. Sampler. base address. and query instructions. and overall size is hidden to a PTX program. . or performing pointer arithmetic will result in undefined results. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. These types have named fields similar to structures. suld.0 5. Texture. allowing them to be defined separately and combined at the site of usage in the program. Referencing textures. sampler. and Surface Types PTX includes built-in “opaque” types for defining texture.surfref. and . but all information about layout. PTX has two modes of operation.texref. store. The following tables list the named members of each type for unified and independent texture modes. sust. In independent mode the fields of the . samplers. For working with textures and samplers. field ordering. but the pointer cannot otherwise be treated as an address.samplerref.texref type that describe sampler properties are ignored. 34 January 24. The three built-in types are . and surface descriptor variables. Retrieving the value of a named member via query instructions (txq. sured). texture and sampler information is accessed through a single . Creating pointers to opaque variables using mov. accessing the pointer with ld and st instructions. hence the term “opaque”.PTX ISA Version 2.texref handle. opaque_var. suq).3. the resulting pointer may be stored to and loaded from memory. since these properties are defined by .u64} reg.e. or surfaces via texture and surface load/store instructions (tex. In the unified mode. passed as a parameter to functions.{u32. 2010 .. i. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.samplerref variables. In the independent mode.

clamp_ogl. clamp_to_edge. clamp_to_edge. Member width height depth Opaque Type Fields in Independent Texture Mode . clamp_to_border N/A N/A N/A N/A N/A . Types. linear wrap. linear wrap.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. mirror.samplerref values N/A N/A N/A N/A nearest. 1 ignored ignored ignored ignored . 1 nearest. 2010 35 . clamp_to_border 0. clamp_ogl. State Spaces. and Variables Table 9.texref values in elements in elements in elements 0.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. Member width height depth Opaque Type Fields in Unified Texture Mode . mirror.texref values .Chapter 5.

param state space.global .PTX ISA Version 2. . At module scope. .global . Example: . As kernel parameters. the types may be initialized using a list of static expressions assigning values to the named members.global .global .texref tex1. Example: . 36 January 24. these variables are declared in the .samplerref my_sampler_name. When declared at module scope. filter_mode = nearest }.texref my_texture_name.surfref my_surface_name. 2010 . these variables must be in the .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global .global state space. .

4.v2 or .4.f32 v0. 0. etc. State Spaces. Predicate variables may only be declared in the register state space. Variable Declarations All storage for data is specified with variable declarations.0.f32 accel.v4.v4 . its type and size. 0.const . and an optional fixed address for the variable. // a length-4 vector of floats .reg .f32 bias[] = {-1. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. Every variable must reside in one of the state spaces enumerated in the previous section.f64 is not allowed. Vectors must be based on a fundamental type.u32 loc. Variables In PTX. // a length-4 vector of bytes By default. Examples: . vector variables are aligned to a multiple of their overall size (vector length times base-type size). In addition to fundamental types.4.f32 V.v4 . A variable declaration names the space in which the variable resides. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . where the fourth element provides padding.s32 i. Vectors cannot exceed 128-bits in length. r.global .global . and they may reside in the register space.1. 2010 37 . PTX supports types for simple aggregate objects such as vectors and arrays. .global .u16 uv.Chapter 5.global . Examples: . 5. January 24. 0}. . textures.v2.v1.b8 v. 5. q. its name.2.v2 . Types.v4 . an optional array size. // a length-2 vector of unsigned ints . a variable declaration describes both the variable’s type and its state space.0}. // typedef . .v3 }. . .reg . Vectors Limited-length vector types are supported. This is a common case for three-dimensional grids. for example.v4 vector. and Variables 5. an optional initializer.pred p.v4.struct float4 { . 1. .reg .u8 bg[4] = {0. . Three-element vectors may be handled by using a .struct float4 coord.shared .global .

0}. Examples: .s32 n = 10. . .global .{. being determined by an array initializer... The size of the dimension is either a constant expression.4.v4 ..3.05. label names appearing in initializers represent the address of the next instruction following the label.global . {0.1.0}}.u8 mailbox[128].4. . variable initialization is supported only for constant and global state spaces.u8 rgba[3] = {{1. {0.{. 1} }.0. Variables that hold addresses of variables or instructions should be of type .PTX ISA Version 2.u64.u16 kernel[19][19]. A scalar takes a single value.1}.1. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. . where the variable name is followed by an equals sign and the initial value or values for the variable.1. The size of the array specifies how many elements should be reserved.4.0.0..05.local .global . Here are some examples: .f16 and .0}.pred. For the kernel declaration above. Array Declarations Array declarations are provided to allow the programmer to reserve space.shared . or is left empty. . 0}. -1}. 5. {1. {0. 2010 . To declare an array. this can be used to initialize a jump table to be used with indirect branches or calls.global .b32 ptr = rgba.05}. this can be used to statically initialize a pointer to a variable. 19*19 (361) halfwords are reserved (722 bytes). Initializers Declared variables may specify an initial value using a syntax similar to C/C++. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).4.u32 or .0 5. Similarly.0}.0. 38 January 24.1.. Variable names appearing in initializers represent the address of the variable. Initializers are allowed for all types except .1. // address of rgba into ptr Currently.global .f32 blur_kernel[][] = {{.s32 offset[][] = { {-1. {0.05}}..

January 24. alignment specifies the address alignment for the starting address of the entire array. The default alignment for vector variables is to a multiple of the overall vector size. 5. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Types. For arrays. . it is quite common for a compiler frontend to generate a large number of register names. The default alignment for scalar and array variables is to a multiple of the base-type size.0}.Chapter 5.0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.align 4 . %r1.. %r99. say one hundred.b8 bar[8] = {0.b32 %r<100>.b32 variables.0. Alignment is specified using an optional . Elements are bytes. 2010 39 . and may be preceded by an alignment specifier.2. Parameterized Variable Names Since PTX supports virtual registers. %r1.. not for individual elements. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. suppose a program uses a large number. Array variables cannot be declared this way. These 100 register variables can be declared as follows: . State Spaces. .4.align byte-count specifier immediately following the state-space specifier. and Variables 5. Examples: // allocate array at 4-byte aligned address. Rather than require explicit declaration of every name.4. The variable will be aligned to an address which is an integer multiple of byte-count. // declare %r0.reg .. For example.0.0. nor are initializers permitted.6. of .const .0.5. …. named %r0.

0 40 January 24. 2010 .PTX ISA Version 2.

as its job is to convert from nearly any data type to any other data type (and size). Each operand type must be compatible with the type determined by the instruction template and instruction type. s. There is no automatic conversion between types.Chapter 6. b. Most instructions have an optional predicate guard that controls conditional execution.1. The result operand is a scalar or vector variable in the register state space. 6. PTX describes a load-store machine. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The mov instruction copies data between registers. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. the sizes of the operands must be consistent.3. Predicate operands are denoted by the names p. and cvt instructions copy data from one location to another. The cvt (convert) instruction takes a variety of operand types and sizes. 2010 41 . Instructions ld and st move data from/to addressable state spaces to/from registers. The bit-size type is compatible with every type having the same size. q. st. so operands for ALU instructions must all be in variables declared in the . Source Operands The source operands are denoted in the instruction descriptions by the names a.2. For most operations.reg register state space. 6. Operand Type Information All operands in instructions have a known type from their declarations. Instruction Operands 6. mov. and c. Integer types of a common size are compatible with each other. January 24. The ld. and a few instructions have additional predicate source operands. r. .

u16 r0.f32 V. . . Address expressions include variable names. and vectors. The address is an offset in the state space in which the variable is declared.s32 q.s32 mov. ld. p. q. . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.const . [tbl+12]. All addresses and address computations are byte-based. arrays.v4 . The mov instruction can be used to move the address of a variable into a pointer.[x]. Examples include pointer arithmetic and pointer comparisons. W.v4 . r0.f32 W.u32 42 January 24. . 2010 .f32 ld. Load and store operations move data between registers and locations in addressable state spaces. Arrays.PTX ISA Version 2. The interesting capabilities begin with addresses. Here are a few examples: . and immediate address expressions which evaluate at compile-time to a constant address.shared.shared . tbl.reg .const. The syntax is similar to that used in many assembly languages.v4.u16 ld.4.4.global .gloal. . and Vectors Using scalar variables as operands is straightforward. 6.s32 tbl[256].1.reg . [V].0 6. address registers. address register plus byte offset.reg .reg . . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.b32 p. Using Addresses.u16 x. there is no support for C-style pointer arithmetic.

v4.x V. and in move instructions to get the address of the label or function into a register. [addr+offset2].v2. Vectors as Operands Vector operands are supported by a limited subset of instructions.b. If more complicated indexing is desired. mov. st. Rb.v4 . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. Rc.z and . . Vector loads and stores can be used to implement wide loads and stores. where the offset is a constant expression that is either added or subtracted from a register variable. a[N-1].c. mov. The size of the array is a constant in the program.w = = = = V. Elements in a brace-enclosed vector. Arrays as Operands Arrays of all types can be declared. d. Instruction Operands 6.f32 V.b and .global.reg . A brace-enclosed list is used for pattern matching to pull apart vectors. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.b.d}. which may improve memory performance.global. or a simple “register with constant offset” expression. say {Ra.z V.d}.global. for use in an indirect branch or call.4. The registers in the load/store operations can be a vector.reg .b V.u32 s.u32 s.r V.a 6. . as well as the typical color fields . .y.3. a[0]. Here are examples: ld.g. it must be written as an address calculation prior to use. and tex.f32 ld.global. January 24.w. Rd}. Array elements can be accessed using an explicitly calculated byte address.4.y V. The expression within square brackets is either a constant integer.4. a register variable.x. 2010 43 . a[1].f32 {a. Vector elements can be extracted from the vector with the suffixes . b. ld.f32 a. c.a. or by indexing into the array using square-bracket notation.u32 s.u32 {a.r.c. V. Examples are ld. or a braceenclosed list of similarly typed scalars. . . V2. Vectors may also be passed as arguments to called functions.g V. ld. // move address of a[1] into s 6. and the identifier becomes an address constant in the space where the array is declared. .2.4. which include mov. [addr+offset].v4.Chapter 6.

6.s32. logic. Type Conversion All operands to all arithmetic.5.u16 instruction is given a u16 source operand and s32 as a destination operand. if a cvt. 2010 . Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.000 for f16).PTX ISA Version 2. except for operations where changing the size and/or type is part of the definition of the instruction. Operands of different sizes or types must be converted prior to the operation. the u16 is zero-extended to s32.1. 44 January 24. and data movement instruction must be of the same type and size. For example. and ~131.0 6. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.5.

u2f = unsigned-to-float. zext = zero-extend. cvt.u32 targeting a 32-bit register will first chop to 16-bits. f2s = float-to-signed. Notes 1 If the destination register is wider than the destination format. The type of extension (sign or zero) is based on the destination format. For example. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2f = float-to-float. Instruction Operands Table 11.Chapter 6. the result is extended to the destination register width after chopping. 2010 45 . chop = keep only low bits that fit.s16. then sign-extend to 32-bits. f2u = float-to-unsigned. s2f = signed-to-float. January 24.

there are four integer rounding modifiers and four floating-point rounding modifiers.rzi . The following tables summarize the rounding modifiers.rn . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. choosing even integer if source is equidistant between two integers.rz . Table 12. Rounding Modifiers Conversion instructions may specify a rounding modifier.rmi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rpi Integer Rounding Modifiers Description round to nearest integer.0 6.2.5.rni . 2010 . Modifier . In PTX.rm . Modifier .PTX ISA Version 2.

Instruction Operands 6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Table 11 gives estimates of the costs of using different kinds of memory. The register in a store operation is available much more quickly. Another way to hide latency is to issue the load instructions as early as possible. Table 14. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. while global memory is slowest. Much of the delay to memory can be hidden in a number of ways. first access is high Notes January 24. Registers are fastest. Operand Costs Operands from different state spaces affect the speed of an operation. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.6.Chapter 6. 2010 47 .

2010 .0 48 January 24.PTX ISA Version 2.

A function declaration specifies an optional list of return parameters.1. functions are declared and defined using the . Execution of the ret instruction within foo transfers control to the instruction following the call. A function must be declared or defined prior to being called. together these specify the function’s interface. 2010 49 .Chapter 7. or prototype. stack-based ABI. January 24. and memory allocated on the stack (“alloca”).func directive. support for variadic functions (“varargs”). function calls. Abstracting the ABI Rather than expose details of a particular calling convention. and return values may be placed directly into register variables. and an optional list of input parameters. } … call foo. 7. Function declarations and definitions In PTX. In this section. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. A function definition specifies both the interface and the body of the function. so recursion is not yet supported. Scalar and vector base-type input and return parameters may be represented simply as register variables.func foo { … ret. … Here. implicitly saving the return address. execution of the call instruction transfers control to foo. we describe the features of PTX needed to achieve this hiding of the ABI. parameter passing. and is represented in PTX as follows: . the function name. stack layout. and Application Binary Interface (ABI). These include syntax for function definitions. arguments may be register variables or constants. The simplest function has no parameters or return values. NOTE: The current version of PTX does not implement the underlying. At the call.

c1.param. … st. [y+0].0 Example: . 2010 .param space variables are used in two ways.param state space is used to pass the structure by value: .reg .reg .param space memory.b8 [py+11]. st.reg .reg .b8 [py+ 9]. st. 50 January 24.reg .reg . The . st. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param. In PTX. }. %rc2.c2.param.c4. c3.func (.u32 %res) inc_ptr ( . ld. this structure will be flattened into a byte array. First. // scalar args in . %inc.param.b8 [py+10]. c2. %ptr. Second.param .b8 c1. … ld. For example.PTX ISA Version 2.align 8 y[12]) { .s32 x.param. bumpptr.4).param.param. . consider the following C structure. … In this example.b8 .param. [y+9].param variable y is used in function definition bar to represent a formal parameter. ld. (%x.b8 c4. } { . c4.f64 f1. } … call (%r1).b8 c3. ld. ld.c3.param .f64 field are aligned.f64 f1.reg space.b32 c1. a . %rc2. .f1. %rd. ret. %rc1.u32 %inc ) { add.func (. %rc1.reg . byte array in . a .b8 [py+ 8].param.u32 %ptr. [y+10]. (%r1.align 8 py[12]. passed by value to a function: struct { double dbl. char c[4]. st. [y+8]. . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . py).u32 %res. note that .b8 .param.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 c2. inc_ptr. [y+11]. Since memory accesses are required to be aligned to a multiple of the access size. … … // computation using x.s32 out) bar (.param space call (%out).b64 [py+ 0].

and alignment.param space formal parameters that are byte arrays.Chapter 7.param or . or constants. For . For a caller.param space byte array with matching type. a . Parameters in . the corresponding argument may be either a . 8. The . or 16 bytes. Typically. the argument must also be a .reg space variable of matching type and size. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. A .param or . size. For a callee.param instructions used for argument passing must be contained in the basic block with the call instruction. For a caller. • The . The . 4.param memory must be aligned to a multiple of 1.param arguments.reg state space can be used to receive and return base-type scalar and vector values. . all st.reg variables. 2010 51 . In the case of .param space formal parameters that are base-type scalar or vector variables.param argument must be declared within the local scope of the caller. • • • For a callee. or a constant that can be represented in the type of the formal parameter. This enables backend optimization and ensures that the . or a constant that can be represented in the type of the formal parameter. In the case of .param variables. 2.param and ld. In the case of . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. size.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The following restrictions apply to parameter passing.reg variables.param variables or . Supporting the .reg space formal parameters.g.reg or .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param state space use in device functions. Abstracting the ABI The following is a conceptual way to think about the . January 24.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg space variable with matching type and size. Note that the choice of . the corresponding argument may be either a . and alignment of parameters.param state space is used to receive parameter values and/or pass return values back to the caller. • The .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.reg state space in this way provides legacy support.. • • Arguments may be . • • • Input and return parameters may be .param byte array is used to collect together fields of a structure being passed by value.

param state space.reg or .x In PTX ISA version 1. For sm_2x targets. 52 January 24. and .1. In PTX ISA version 2. formal parameters may be in either .x supports multiple return values for this purpose. Changes from PTX 1. PTX 2.reg state space.x. and there was no support for array parameters.1.param byte array should be used to return objects that do not fit into a register. PTX 2. formal parameters were restricted to . 2010 .0 continues to support multiple return registers for sm_1x targets.0. PTX 1.0 7. and a .0 restricts functions to a single return value.param space parameters support arrays.PTX ISA Version 2. Objects such as C structures were flattened and passed or returned using multiple registers.

u32 ap. the size may be 1.func okay ( … ) Built-in functions are provided to initialize.s32 result ) maxN ( . maxN. %r1.reg . call (ap). } … call (%max). 4. … ) . // default to MININT mov.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg . In PTX. 0. 2.b32 ctr.reg . (ap. or 8 bytes. Variadic functions NOTE: The current version of PTX does not support variadic functions.func baz ( . following zero or more fixed parameters: .2. . ) { .reg .h headers in C. along with the size and alignment of the next data value to be accessed.s32 val.b64 val) %va_arg64 (. or 4 bytes. To support functions with a variable number of arguments. %va_end is called to free the variable argument list handle. . val.pred p.b32 val) %va_arg (.reg . the alignment may be 1. (2. 8.func ( .reg . ret.u32 ptr.u32.reg . The function prototypes are defined as follows: .u32 sz.reg . iteratively access. %r3). (ap).u32 N.h and varargs. . 4). ctr. . … call (%max). setp. %va_start. mov. and end access to a list of variable arguments.reg . variadic functions are declared with an ellipsis at the end of the input parameter list. . . result.. This handle is then passed to the %va_arg and %va_arg64 built-in functions. 4.b32 result. %r2. call (val). 2. Once all arguments have been processed. In both cases. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .u32 a.u32 align) .reg .u32 align) .func (. bra Loop. the size may be 1. … %va_start returns Loop: @p Done: January 24. Abstracting the ABI 7..reg .reg .reg .reg .reg . call %va_end. . N.Chapter 7. maxN. bra Done.reg . For %va_arg.ge p. (3. for %va_arg64.u32 ptr) %va_start .reg . 2010 53 . %s1.u32 sz. 2.s32 result. ctr. PTX provides a high-level mechanism similar to the one provided by the stdarg.func (.func %va_end (. %s2). %va_arg.u32 b. 4.func (. 0x8000000. max.u32 ptr. or 16 bytes. .

local and st.PTX ISA Version 2. 2010 .func ( .3. 54 January 24.reg .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. Alloca NOTE: The current version of PTX does not support alloca. a function simply calls the built-in function %alloca. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.local instructions.u32 ptr ) %alloca ( . The array is then accessed with ld.reg . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. To allocate memory. If a particular alignment is required.0 7. defined as follows: .

the semantics are described. B.2.s32. while A. setp. A. b. For instructions that create a result value. 2010 55 . and C are the source operands. opcode A. the D operand is the destination operand.lt p|q. q = !(a < b). For some instructions the destination operand is optional. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. B. We use a ‘|’ symbol to separate multiple destination registers. A. a. C. January 24. In addition to the name and the format of the instruction.Chapter 8. The setp instruction writes two destination registers. opcode D. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. B. PTX Instructions PTX instructions generally have from zero to four operands. Instruction Set 8. followed by some examples that attempt to show several possible instantiations of the instruction. A. 8.1. opcode D. // p = (a < b). opcode D.

the following PTX instruction sequence might be used: @!p L1: setp. add 1 to j To get a conditional branch or conditional function call. n. j. n.3. j. To implement the above example as a true conditional branch. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. 2010 . predicate registers can be declared as . Predicated Execution In PTX. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. consider the high-level code if (i < n) j = j + 1.s32 p. This can be written in PTX as @p setp. branch over 56 January 24.0 8. As an example. q. optionally negated. predicate registers are virtual and have . i.PTX ISA Version 2. add. where p is a predicate variable. add.reg . Predicates are most commonly set as the result of a comparison performed by the setp instruction. i. bra L1.lt. … // compare i to n // if false. use a predicate to control the execution of the branch or call instructions.s32 j. 1.s32 p.pred as the type specifier. 1. So. // p = (i < n) // if i < n.lt.pred p.s32 j. Instructions without a guard predicate are executed unconditionally.

and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.1. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ls (lower-or-same). gt (greater-than). lt (less-than).2. and bitsize types. Comparisons 8. and hs (higher-or-same). unsigned integer. lt. ne. If either operand is NaN. ge.3.1. and ge (greater-than-or-equal). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. The bit-size comparisons are eq and ne. ordering comparisons are not defined for bit-size types.1. ne (not-equal). Table 15. The unsigned comparisons are eq. The following table shows the operators for signed integer. hi (higher). Table 16. gt. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). lo (lower).3. Instruction Set 8. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. ne.1. le. the result is false.Chapter 8. le (less-than-or-equal). 2010 57 . Unsigned Integer.3.

Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. setp can be used to generate a predicate from an integer. Table 18. and mov. leu.2. However. then the result of these comparisons is true. If both operands are numeric values (not NaN). There is no direct conversion between predicates and integer values.PTX ISA Version 2. for example: selp. If either operand is NaN. num returns true if both operands are numeric values (not NaN). unordered versions are included: equ. ltu. two operators num (numeric) and nan (isNaN) are provided. geu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. 2010 . // convert predicate to 32-bit value 58 January 24.3. gtu.%p. not. and nan returns true if either operand is NaN. then these comparisons have the same result as their ordered counterparts.u32 %r1. and no direct way to load or store predicate register values. neu.0.1. or. xor. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.0 To aid comparison operations in the presence of NaN values. Table 17.

Instruction Set 8.uX . unsigned. and integer operands are silently cast to the instruction type if needed.bX . i. float..uX ok ok ok inv . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. different sizes).f32.sX .fX ok ok ok ok January 24. Signed and unsigned integer types agree provided they have the same size.reg .u16 d. a. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. the add instruction requires type and size information to properly perform the addition operation (signed. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. It requires separate type-size modifiers for the result and source. Table 19. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.fX ok inv inv ok Instruction Type .u16 a.reg . and these are placed in the same order as the operands. • The following table summarizes these type checking rules.4. b.u16 d. Example: .sX ok ok ok inv . For example. they must match exactly. Floating-point types agree only if they have the same size. add. For example.reg . most notably the data conversion instruction cvt.u16 d. 2010 59 . . b. a.bX .e. Type Checking Rules Operand Type . and this information must be specified as a suffix to the opcode.Chapter 8. cvt.f32 d. a. For example: .

b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. stored. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. The data is truncated to the instruction-type size and interpreted according to the instruction type.0 8. so that narrow values may be loaded.4. the data will be truncated. 2010 . 1.1. When a source operand has a size that exceeds the instruction-type size. inv = invalid. st. and converted using regular-width registers. For example. Table 20. Note that some combinations may still be invalid for a particular instruction. ld. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. When used with a narrower bit-size type. Floating-point source registers can only be used with bit-size or floating-point instruction types. floating-point instruction types still require that the operand type-size matches exactly. Notes 3. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Source register size must be of equal or greater size than the instruction-type size.PTX ISA Version 2. Bit-size source registers may be used with any appropriately-sized instruction type. no conversion needed. 4. unless the operand is of bit-size type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Operand Size Exceeding Instruction-Type Size For convenience. for example. The following table summarizes the relaxed type-checking rules for source operands. 60 January 24. so those rows are invalid for cvt. “-“ = allowed. the cvt instruction does not support . or converted to other types and sizes. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. the size must match exactly. When used with a floating-point instruction type. parse error. stored.bX instruction types. 2.

Instruction Set When a destination operand has a size that exceeds the instruction-type size. Notes 3. 2. If the corresponding instruction type is signed integer. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types.Chapter 8. the size must match exactly. When used with a narrower bit-size instruction type. otherwise. January 24. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. The data is sign-extended to the destination register width for signed integer instruction types. Bit-size destination registers may be used with any appropriately-sized instruction type. 2010 61 . parse error. Destination register size must be of equal or greater size than the instruction-type size. zext = zero-extend. the data is sign-extended. When used with a floatingpoint instruction type. inv = Invalid. “-“ = Allowed but no conversion needed. 4. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the destination data is zero. 1. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. the data will be zero-extended. The data is signextended to the destination register width for signed integer instruction types. The following table summarizes the relaxed type-checking rules for destination operands. the data is zeroextended. Table 21.or sign-extended to the size of the destination register. and is zero-extended to the destination register width otherwise.

6. 16-bit registers in PTX are mapped to 32-bit physical registers. For divergent control flow. for example. When executing on a 32-bit data path. 8. At the PTX language level. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. until C is not expressive enough. the semantics of 16-bit instructions in PTX is machine-specific. and 16-bit computations are “promoted” to 32-bit computations. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. If threads execute down different control flow paths.1. Divergence of Threads in Control Constructs Threads in a CTA execute together. 8.6. a compiler or code author targeting PTX can ignore the issue of divergent threads.uni suffix. by a right-shift instruction. and for many applications the difference in execution is preferable to limiting performance. Therefore. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. A compiler or programmer may chose to enforce portable. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. These extra precision bits can become visible at the application level. the threads are called uniform. the optimizing code generator automatically determines points of re-convergence. for many performance-critical applications.PTX ISA Version 2. 62 January 24. or conditional return. conditional function call.0 8. this is not desirable. However. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. at least in appearance. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. Both situations occur often in programs. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. the threads are called divergent.5. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. so it is important to have divergent threads re-converge as soon as possible. The semantics are described using C. 2010 . If all of the threads act in unison and follow a single control flow path. until they come to a conditional control construct such as a conditional branch. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. using the .

2010 63 .7.cc.Chapter 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. The Integer arithmetic instructions are: add sub add.1. In the following descriptions. Instruction Set 8. addc sub.7. Instructions All PTX instructions may be predicated.cc. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 8. the optional guard predicate is omitted from the syntax.

u32 x.MAXINT (no overflow) for the size of the operation.u32.sat applies only to .s32 d.PTX ISA Version 2.sat applies only to .0.y.s64 }. . .u64. // .. Applies only to . sub. a. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Description Semantics Notes Performs addition and writes the resulting value into a destination register.z.sat.u32. Supported on all target architectures.s32.s16.c. 2010 . PTX ISA Notes Target ISA Notes Examples 64 January 24.sat}. add.u64. . a. Supported on all target architectures.s32 type.0 Table 22. b. Introduced in PTX ISA version 1.type add{. Introduced in PTX ISA version 1.MAXINT (no overflow) for the size of the operation.u16.s32. a.s32 . .s16. a.u16. b.sat}. d = a + b.a.s32 type. add.type = { . add Syntax Integer Arithmetic Instructions: add Add two values. Applies only to . @p add.s32 d. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. PTX ISA Notes Target ISA Notes Examples Table 23.sat limits result to MININT. d. . sub. b.s32 c.1. . d.type = { . // .type sub{.0.sat limits result to MININT. . . Saturation modifier: .s32 . b. Saturation modifier: .b..s32 c. d = a – b.s64 }. . .

CF. carry-out written to CC.CF No integer rounding modifiers. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.b32 addc.cc Add two values with carry-out. x2. x4. add. add. if . The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.b32 addc.cc.type d.cc. @p @p @p @p add.s32 }. x3.CF No integer rounding modifiers.b32 addc. clearing.Chapter 8.y2.z4. Table 24.z3.CF) holding carry-in/carry-out or borrowin/borrow-out. sub.y4. addc{.cc. No saturation. . x4. Introduced in PTX ISA version 1.cc. Introduced in PTX ISA version 1. or testing the condition code.cc. @p @p @p @p add.z2.y2. b. d = a + b + CC.y3. . d = a + b.b32 addc.y4.2. These instructions support extended-precision integer addition and subtraction. x3.z4. a.y1. addc.cc.type = { .u32.y1.b32 x1. Behavior is the same for unsigned and signed integers. b.b32 x1.y3.u32. Instruction Set Instructions add.b32 addc.s32 }.z1.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. and there is no support for setting. 2010 65 .cc. a.type = {. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.cc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.2.z2.cc}.cc. . Behavior is the same for unsigned and signed integers. x2. Supported on all target architectures.type d.cc. Supported on all target architectures.b32 addc. No other instructions access the condition code. . No saturation.z3.z1.cc Syntax Integer Arithmetic Instructions: add. carry-out written to CC.cc specified. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.

y4. 2010 .b32 subc.z1.y1.cc. d = a – b.y2. x3.type d.3. Behavior is the same for unsigned and signed integers.z2. a. No saturation.u32. x4.cc}.(b + CC.s32 }.3. Introduced in PTX ISA version 1.type = {. @p @p @p @p sub.b32 subc. borrow-out written to CC.b32 subc. . @p @p @p @p sub. Supported on all target architectures. a.0 Table 26.u32. d = a .CF). .b32 x1. withborrow-in and optional borrow-out.y1.cc.cc. No saturation. x2.z4.b32 subc.cc. .cc. x3. Introduced in PTX ISA version 1.cc.cc Syntax Integer Arithmetic Instructions: sub.cc Subract one value from another.b32 subc. sub.cc.b32 subc.type d. Supported on all target architectures. b.PTX ISA Version 2.cc specified.z4. x4. .cc.CF No integer rounding modifiers.y2.b32 x1.y3. with borrow-out. x2. Behavior is the same for unsigned and signed integers.z1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.s32 }. if . b.z3.cc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. sub.type = { .y4.CF No integer rounding modifiers.y3.z3. borrow-out written to CC. subc{. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.z2.

Description Semantics Compute the product of two values. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..n>. mul{.type = { .hi or .lo.wide suffix is supported only for 16. Instruction Set Table 28. n = bitwidth of type. // 16*16 bits yields 32 bits // 16*16 bits.hi variant // for .0. // for .wide // for .s16 fa. mul. d = t<2n-1. d = t. If . .0>. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.u32.fxs.. t = a * b.fxs.lo. Supported on all target architectures. .s16. save only the low 16 bits // 32*32 bits.x.wide}.s32 z. mul. and either the upper or lower half of the result is written to the destination register. . .u16. . then d is the same size as a and b.wide.wide is specified.s16 fa. b. mul. creates 64 bit result January 24.fys. 2010 67 . d = t<n-1.lo variant Notes The type of the operation represents the types of the a and b operands. a..and 32-bit integer types.hi.s32.u64. If .wide.type d.fys.lo is specified.y. then d is twice as wide as a and b to receive the full result of the multiplication. . The .Chapter 8..s64 }.

b.MAXINT (no overflow) for the size of the operation. c.s32. Saturation modifier: . Description Semantics Multiplies two values and adds a third.s32 r. The .u64.and 32-bit integer types.u32.a.s32 d. If . t + c.wide // for ..sat limits result to MININT.hi mode. .hi. and then writes the resulting value into a destination register.lo.q.0. t n d d d = = = = = a * b. mad.lo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and either the upper or lower half of the result is written to the destination register.p. mad{. Applies only to .hi. // for .s32 type in .s16.hi or . t<n-1..lo variant Notes The type of the operation represents the types of the a and b operands. bitwidth of type.r.wide is specified.lo is specified.wide}.sat.b. If . Supported on all target architectures.u16. then d and c are twice as wide as a and b to receive the result of the multiplication. d.type = { .type mad.n> + c.0> + c. ..PTX ISA Version 2.0 Table 29. a. . c...c.s32 d.lo.s64 }. @p mad. a. t<2n-1. .wide suffix is supported only for 16. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. . b. . 68 January 24.hi variant // for . 2010 . then d and c are the same size as a and b.

and return either the high or low 32-bits of the 48-bit result.hi variant // for .lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.lo}.u32.s32 }. a.16>. 2010 69 .hi. .hi may be less efficient on machines without hardware support for 24-bit multiply..a. mul24. Supported on all target architectures. January 24.0>. mul24{. mul24.Chapter 8. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b. 48bits...s32 d. d = t<31. // low 32-bits of 24x24-bit signed multiply. i.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. d = t<47. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. // for . mul24.lo.type = { . Instruction Set Table 30.b. .0.type d. All operands are of the same type and size.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. t = a * b. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.e. mul24.

mad24.hi mode. 2010 .hi variant // for . mad24{. d = t<31. i. 70 January 24. d. Applies only to .. a. Return either the high or low 32-bits of the 48-bit result.hi may be less efficient on machines without hardware support for 24-bit multiply. 48bits. Supported on all target architectures. t = a * b.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. mad24. // for .e.hi. Description Compute the product of two 24-bit integer values held in 32-bit source registers. a.s32 type in . All operands are of the same type and size. 32-bit value to either the high or low 32-bits of the 48-bit result.s32 d. b.hi.a. b.type = { . mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.PTX ISA Version 2.0. c.type mad24.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo. mad24.sat.. // low 32-bits of 24x24-bit signed multiply. .lo}.s32 d. Saturation modifier: .MAXINT (no overflow).lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. mad24.c.16> + c.b. and add a third. c. d = t<47.s32 }.0 Table 31. .sat limits result of 32-bit signed addition to MININT.0> + c.u32..

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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cnt.type d. } else { max = 64. popc.PTX ISA Version 2.u32 Semantics 74 January 24. while (a != 0) { if (a&0x1) d++.type = { .b32 type.type d. clz. popc Syntax Integer Arithmetic Instructions: popc Population count.u32 PTX ISA Notes Target ISA Notes Examples Table 40. cnt. popc requires sm_20 or later. clz requires sm_20 or later.0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. inclusively. mask = 0x80000000.0 Table 39. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. d = 0.type == . d = 0. a. . 2010 . For . the number of leading zeros is between 0 and 64. the number of leading zeros is between 0 and 32.b64 }. // cnt is . For . popc.0.b32) { max = 32. a = a << 1.type = { .b32 clz. // cnt is . . clz.b64 }. mask = 0x8000000000000000.b32. a. . if (. } while (d < max && (a&mask == 0) ) { d++.b64 d. a.b64 type. . inclusively.b64 d. X. a = a >> 1.b32. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. X. a. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b32 popc. } Introduced in PTX ISA version 2.

bfind. a.d. Semantics msb = (.u64. For signed integers.type==. i>=0. break. . bfind returns the bit position of the most significant “1”. Description Find the bit position of the most significant non-sign bit in a and place the result in d. X.shiftamt is specified. bfind. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. } } if (. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.u32 || . For unsigned integers.Chapter 8. If .shiftamt.0.shiftamt && d != -1) { d = msb . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfind returns 0xFFFFFFFF if no non-sign bit is found. and operand d has type .u32.u32 January 24. . a. bfind requires sm_20 or later. .type d.u32.type = { . Instruction Set Table 41. d = -1. i--) { if (a & (1<<i)) { d = i. bfind. for (i=msb.s32.shiftamt. a. // cnt is .s64 cnt.s32) ? 31 : 63.s64 }.type bfind. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type==.u32 d. . 2010 75 . d. Operand a has the instruction type.

i<=msb. i++) { d[i] = a[msb-i].type = { . msb = (.0.b64 }. a. brev requires sm_20 or later.b32. a.b32) ? 31 : 63.0 Table 42.type==. for (i=0.type d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.PTX ISA Version 2. Description Semantics Perform bitwise reversal of input. . 76 January 24.b32 d. brev. . 2010 . brev.

.len. the result is zero. . i<=msb. else sbit = a[min(pos+len-1. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the destination d is filled with the replicated sign bit of the extracted field.type==. Semantics msb = (.b32 d. c. len = c.type==.0.start. d = 0.type d. . January 24.u32 || . and operands b and c are type . Instruction Set Table 43.s32. . If the start position is beyond the msb of the input.msb)]. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.type==.u64 || len==0) sbit = 0. b. Description Extract bit field from a and place the zero or sign-extended result in d. Operands a and d have the same type as the instruction type. pos = b. for (i=0.type==.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.Chapter 8.u32. bfe requires sm_20 or later. . The destination d is padded with the sign bit of the extracted field. otherwise If the bit field length is zero. bfe. if (.a.u64: .u32.type = { . Source b gives the bit field starting bit position.s32.u32. bfe. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u64.s32) ? 31 : 63. and source c gives the bit field length in bits. a. The sign bit of the extracted field is defined as: . 2010 77 .u32 || .s64 }.

. for (i=0.b. c.len.0.PTX ISA Version 2.b32 d. 78 January 24. . and source d gives the bit field length in bits.b32) ? 31 : 63. Operands a.type==. i++) { f[pos+i] = a[i].0 Table 44.a.b64 }.u32. 2010 . and operands c and d are type . bfi. and f have the same type as the instruction type. the result is b.type = { . d. f = b.start. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the result is b.type f. If the start position is beyond the msb of the input. Source c gives the starting bit position for the insertion. If the bit field length is zero. Semantics msb = (. bfi. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. b.b32. b. a. pos = c. Description Align and insert a bit field from a into b. and place the result in f. len = d. bfi requires sm_20 or later. i<len && pos+i<=msb.

prmt. 2010 79 . msb=1 means replicate the sign.ecl. and reassemble them into a 32-bit destination register.rc8. a} = {{b7. . {b3. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. b1.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.mode} d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.mode = { . Thus.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. b. b4}. For each byte in the target register. the permute control consists of four 4-bit selection values. .b1 source select c[7:4] d. The msb defines if the byte value should be copied.Chapter 8.b2 source select c[11:8] d. a. b2.b32{. b6.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. The bytes in the two source registers are numbered from 0 to 7: {b. the four 4-bit values fully specify an arbitrary byte permute.rc16 }. Note that the sign extension is only performed as part of generic form. default mode index d. In the generic form (no mode specified). a 4-bit selection value is defined. b5. as a 16b permute code.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.f4e.b4e.ecr. msb=0 means copy the literal value. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. Description Pick four arbitrary bytes from two 32-bit registers. . . . c. .b3 source select c[15:12] d. b0}}. Instruction Set Table 45.

r4.b32. r3. ctl[3] = (c >> 12) & 0xf. ctl[3]. } tmp[07:00] = ReadByte( mode. ctl[1] = (c >> 4) & 0xf. ctl[2] = (c >> 8) & 0xf. prmt requires sm_20 or later.0. ctl[2]. 2010 . prmt. r1. tmp[31:24] = ReadByte( mode. r2. tmp64 ). tmp64 ). 80 January 24. ctl[1].0 Semantics tmp64 = (b<<32) | a. tmp[15:08] = ReadByte( mode.f4e r1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r4. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.b32 prmt. tmp[23:16] = ReadByte( mode. tmp64 ). r3. ctl[0]. r2.PTX ISA Version 2.

f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Instruction Set 8.2. Floating-Point Instructions Floating-point instructions operate on .7. 2010 81 .Chapter 8.f64 register operands and constant immediate values.

rcp.sqrt}.ftz . The optional .max}.ex2}.sqrt}.max}.f64 {abs. {add.f64 div. Double-precision instructions support subnormal inputs and results.sat Notes If no rounding modifier is specified.f64 and fma. {mad.min.full.target sm_20 mad.mul}.rnd.rn .ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.f32 .f32 rsqrt.approx.fma}. Single-precision add.rz .f32 {add.rnd.rp .f32 {div.target sm_20 . Note that future implementations may support NaN payloads for single-precision instructions.neg. NaN payloads are supported for double-precision instructions.f64 mad.approx.rn and instructions may be folded into a multiply-add. mul.rcp.cos.rm .f32 {abs.f32 {div.rn and instructions may be folded into a multiply-add.mul}.rnd.PTX ISA Version 2.fma}. No rounding modifier.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.target sm_1x No rounding modifier.approx.32 and fma.rnd.0 The following table summarizes floating-point instructions in PTX.f32 {mad.sub. 2010 . but single-precision instructions return an unspecified NaN.f64 {sin. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.rnd. . If no rounding modifier is specified.min.rcp.sqrt}.f32 are the same. sub.0]. Table 46.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f64 rsqrt. and mad support saturation of results to the range [0. with NaNs being flushed to positive zero.f32 {div. default is .0.rnd. 82 January 24.sub. Instruction Summary of Floating-Point Instructions .neg. so PTX programs should not rely on the specific single-precision NaNs being generated. . 1.lg2. default is .approx.f64 are the same.

January 24. .type = { .f64 x. Introduced in PTX ISA version 2. . .infinite. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a. .op.finite.normal.0. . C.0.infinite testp. A.pred = { .f32 copysign. . not infinity) As a special case. f0. positive and negative zero are considered normal numbers.notanumber. p.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. and return the result as d.notanumber.op p. Table 48.finite testp. testp. .f64 }.number. copysign requires sm_20 or later.number testp.f64 }.f32. // result is . a.Chapter 8. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.f64 isnan.type d. B.subnormal }.normal testp. copysign. y.notanumber testp. 2010 83 . testp requires sm_20 or later. true if the input is a subnormal number (not NaN. testp Syntax Floating-Point Instructions: testp Test floating-point property. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. z. X. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.infinite. testp.type = { .f32. .f32 testp. copysign. not infinity). Instruction Set Table 47. . testp.type . b.

An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn.f32 supported on all target architectures. 2010 .rnd}.0]. Rounding modifiers (default is .rn.rnd = { . add.f32. add{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. requires sm_20 Examples @p add. Saturation modifier: . Rounding modifiers have the following target requirements: .rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. .rz mantissa LSB rounds towards zero . . add.f32 clamps the result to [0.0.0f. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f64 d. sm_1x: add.rm.f2. b.rz available for all targets . b. 84 January 24. a. add Syntax Floating-Point Instructions: add Add two values.f64. requires sm_13 for add. add.ftz. a.ftz}{.rnd}{.rn mantissa LSB rounds to nearest even . add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. .f32 add{.sat}.0. d.f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. d = a + b.rz.rp }. In particular.rm. add. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .0 Table 49.rn): .f64 supports subnormal numbers. .rz.f32 f1. 1.PTX ISA Version 2. NaN results are flushed to +0.f3.sat.rp for add. .

f32.0.f32 flushes subnormal inputs and results to sign-preserving zero. .b. b. sub. sub.0f. sub. .f64 d.Chapter 8.0.f2.a. . a.sat}.rnd}. a.f32 supported on all target architectures.rm mantissa LSB rounds towards negative infinity .rz available for all targets .f64 supports subnormal numbers.ftz.f64.rn. 1. In particular.f3.rnd}{.rn): . b. Instruction Set Table 50. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rp }.rnd = { . Saturation modifier: sub.f32 sub{. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. d = a .rm.sat. . 2010 85 . sub. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. .f32 f1.rz.rn.f64 requires sm_13 or later. NaN results are flushed to +0. . sm_1x: sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f32 c.f32 clamps the result to [0. sub{. subnormal numbers are supported.0]. d. Rounding modifiers (default is . January 24. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. requires sm_13 for sub.f32 flushes subnormal inputs and results to sign-preserving zero.rn mantissa LSB rounds to nearest even .b.rz mantissa LSB rounds towards zero .rm. requires sm_20 Examples sub. sub.ftz}{.rn. Rounding modifiers have the following target requirements: .rp for sub.

In particular. requires sm_13 for mul. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.f64 supports subnormal numbers. requires sm_20 Examples mul. d.f64. Rounding modifiers have the following target requirements: .f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz.rz available for all targets . .rm mantissa LSB rounds towards negative infinity .0. a.rz mantissa LSB rounds towards zero .pi // a single-precision multiply 86 January 24. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.sat. mul. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .rz. .PTX ISA Version 2.ftz}{.0f.f64 d.rn mantissa LSB rounds to nearest even . NaN results are flushed to +0.rnd = { .rm. . 2010 .f32 clamps the result to [0. For floating-point multiplication.f32 flushes subnormal inputs and results to sign-preserving zero.rm. a.f32 circumf. mul. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. b. mul Syntax Floating-Point Instructions: mul Multiply two values.f32 supported on all target architectures.rn.f32 flushes subnormal inputs and results to sign-preserving zero. . subnormal numbers are supported. Description Semantics Notes Compute the product of two values.f32 mul{.0]. Rounding modifiers (default is . mul{. Saturation modifier: mul.rn): . 1.rnd}. sm_1x: mul.rnd}{. .rn.rp for mul.0.radius. d = a * b. mul.sat}. all operands must be the same size. b.0 Table 51. mul.rp }.ftz.f64 requires sm_13 or later.

fma.z.4. fma. Rounding modifiers (no default): . fma.0].rnd = { . a.ftz}{.f64 d.Chapter 8.b. PTX ISA Notes Target ISA Notes Examples January 24. Saturation: fma. b. The resulting value is then rounded to single precision using the rounding mode specified by .rn. 1. 2010 87 .f64 introduced in PTX ISA version 1.f32 fma. @p fma.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 fma.f32 is unimplemented in sm_1x.sat}.rm mantissa LSB rounds towards negative infinity .f32 requires sm_20 or later. NaN results are flushed to +0. .f32 introduced in PTX ISA version 2.rnd.sat. d. .rnd{. Instruction Set Table 52.c.ftz.rp }.rz mantissa LSB rounds towards zero . fma. c.y.f64.rn.x.f32 clamps the result to [0.f64 computes the product of a and b to infinite precision and then adds c to this product. fma. .rn.f64 requires sm_13 or later.f64 is the same as mad. a.0.0.rnd. again in infinite precision. b. again in infinite precision. c. d = a*b + c.rz.rn mantissa LSB rounds to nearest even .rm.f64 w.f32 flushes subnormal inputs and results to sign-preserving zero.a. fma.f64 supports subnormal numbers. fma. sm_1x: fma. subnormal numbers are supported. fma. fma. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add.rnd. The resulting value is then rounded to double precision using the rounding mode specified by . . d.ftz.0f.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.

Note that this is different from computing the product with mul. .rnd = { .{f32. subnormal numbers are supported. Saturation modifier: mad. // . c. where the mantissa can be rounded and the exponent will be clamped.0f. c. and then writes the resulting value into a destination register. // . The resulting value is then rounded to double precision using the rounding mode specified by .0.rnd. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.target sm_1x d.0 devices.f64 supports subnormal numbers.rnd.e.target sm_13 and later . In this case.0 Table 53. When JIT-compiled for SM 2.0].ftz.f32 is identical to the result computed using separate mul and add instructions.rz mantissa LSB rounds towards zero . The exception for mad. mad{. The resulting value is then rounded to single precision using the rounding mode specified by .ftz}{. d = a*b + c.f32. mad. fma.PTX ISA Version 2.f32).rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}{. b. mad.rn.f64}. again in infinite precision.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz.sat}.f64 is the same as fma. mad.f32 clamps the result to [0.sat}.f32 is implemented as a fused multiply-add (i.0.f32 computes the product of a and b at double precision.f32 mad. again in infinite precision. The resulting value is then rounded to double precision using the rounding mode specified by .rm mantissa LSB rounds towards negative infinity . sm_1x: mad. b.rp }. mad.target sm_20 d.target sm_1x: mad.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero. mad.f32 mad. again in infinite precision.rn.f64 computes the product of a and b to infinite precision and then adds c to this product. mad. NaN results are flushed to +0. Rounding modifiers (no default): . a.rn mantissa LSB rounds to nearest even . mad. 88 January 24. the treatment of subnormal inputs and output follows IEEE 754 standard.. .rnd. Description Semantics Notes Multiplies two values and adds a third. b. For . mad.f64. c. but the exponent is preserved. mad. a.rz.rnd{. // .f64} is the same as fma.{f32. 2010 .rm.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. Unlike mad.f32 is when c = +/-0. 1.f32 flushes subnormal inputs and results to sign-preserving zero. and then the mantissa is truncated to 23 bits.sat.f64 d. .rnd. a. For .target sm_20: mad.

Rounding modifiers have the following target requirements: .f32 supported on all target architectures.rm.b.rn.. a rounding modifier is required for mad..0.f32.f64.. In PTX ISA versions 1. mad. a rounding modifier is required for mad.rp for mad.Chapter 8.rm...a. In PTX ISA versions 2.rn.rp for mad..rz. Target ISA Notes mad.rz.f64. January 24. Legacy mad.rn.f64 requires sm_13 or later.f32 d. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. requires sm_20 Examples @p mad. requires sm_13 .0 and later.f64.4 and later.f32 for sm_20 targets. 2010 89 .c.f64 instructions having no rounding modifier will map to mad.

rz mantissa LSB rounds towards zero . .14159.full.rn mantissa LSB rounds to nearest even . . .f32 implements a fast approximation to divide.ftz. b. div.PTX ISA Version 2. div.full{.f64 defaults to div. // // // // fast. stores result in d. For PTX ISA versions 1.approx. and rounding introduced in PTX ISA version 1.rp }.f32 implements a relatively fast. d.rm. sm_1x: div. x. Examples 90 January 24. 2126]. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . or .full. Fast.full.f64 introduced in PTX ISA version 1.rnd is required. b.4.f32 and div.approx.rm mantissa LSB rounds towards negative infinity . xd. approximate single-precision divides: div.rnd{.ftz}.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero.f32 div.rp}.f64 supports subnormal numbers. Explicit modifiers . one of .ftz. div. div. Description Semantics Notes Divides a by b.approx. div Syntax Floating-Point Instructions: div Divide one value by another.approx.rn.3. d.f32 requires sm_20 or later.4 and later. d = a / b. a. div.ftz.f32 div. zd.approx{. a. div. PTX ISA Notes div.rnd = { . b.rm.full. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . b.f32 div.rz.f32 div. d. full-range approximation that scales operands to achieve better accuracy. approximate division by zero creates a value of infinity (with same sign as a). z.circum. div. Fast. div.ftz.f32 defaults to div.f64 requires sm_13 or later.0.f32.ftz}. 2010 .rn.rnd. .approx. and div. y. but is not fully IEEE 754 compliant and does not support rounding modifiers. For PTX ISA version 1. the maximum ulp error is 2. computed as d = a * (1/b). yd.ftz}. div. The maximum ulp error is 2 across the full range of inputs. Target ISA Notes div.f64 requires sm_20 or later. a.full.rn.f32 div.{rz.f64. a. subnormal numbers are supported.ftz.approx. For b in [2-126.f64 diam.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .f32 supported on all target architectures.f32 and div. Subnormal inputs and results are flushed to sign-preserving zero.3.0 Table 54.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.rn. .rnd.

neg. abs. sm_1x: abs.Chapter 8. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. d = -a.f64 supports subnormal numbers. abs{.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.f32 neg. a. d. Negate the sign of a and store the result in d. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Subnormal numbers: sm_20: By default. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg.ftz. Table 56.f64 requires sm_13 or later. subnormal numbers are supported.ftz. d.f64 d.f32 x. abs. a. Subnormal numbers: sm_20: By default. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz}.f32 supported on all target architectures. Instruction Set Table 55.ftz. neg{.f32 flushes subnormal inputs and results to sign-preserving zero. NaN inputs yield an unspecified NaN.f32 supported on all target architectures. d = |a|.0.f0.f32 flushes subnormal inputs and results to sign-preserving zero. abs.ftz.f0.f64 d. Take the absolute value of a and store the result in d.f32 x.0. abs.f64 requires sm_13 or later.f32 abs. a. 2010 91 . sm_1x: neg. NaN inputs yield an unspecified NaN. neg. subnormal numbers are supported. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs. neg.f32 flushes subnormal inputs and results to sign-preserving zero. January 24. a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. neg.f64 supports subnormal numbers.

max. Table 58.ftz}.x.f32 flushes subnormal inputs and results to sign-preserving zero.0. subnormal numbers are supported.ftz. b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 supports subnormal numbers. 92 January 24.c. min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b. a. (a > b) ? a : b. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later.0 Table 57.f32 min.0. b.z.f64 f0. max. min. min.f32 min.f2. max. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. b.f32 supported on all target architectures. a. a.b. a.f1. sm_1x: min. min{. max.f64 z.ftz}. max{. sm_1x: max. Store the maximum of a and b in d.ftz. d. d. min.f32 max. a.PTX ISA Version 2. a. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. b.f32 flushes subnormal inputs and results to sign-preserving zero.b. d d d d = = = = NaN. @p min. subnormal numbers are supported.c. Store the minimum of a and b in d.f64 d.f64 d. b. d d d d = = = = NaN.f32 supported on all target architectures.f32 max. max.f64 requires sm_13 or later. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. a. 2010 .f64 supports subnormal numbers. (a < b) ? a : b.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.

General rounding modifiers were added in PTX ISA version 2.rm.rn.f64.rm mantissa LSB rounds towards negative infinity . rcp.3.approx.0.f32 defaults to rcp.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. one of .ftz.{rz.4 and later. .approx{.rz.Chapter 8.ftz. subnormal numbers are supported.f32 implements a fast approximation to reciprocal.rnd is required. .0.0-2.f64 requires sm_20 or later. For PTX ISA version 1.rn.rn.rn mantissa LSB rounds to nearest even .rn. rcp. and rcp. rcp. Description Semantics Notes Compute 1/a.4.ftz.f64 and explicit modifiers . store result in d. d.f32 rcp. Target ISA Notes rcp. a.rnd.x.approx.ftz}. rcp.approx or .approx.rn. sm_1x: rcp.f32 flushes subnormal inputs and results to sign-preserving zero. .f64 defaults to rcp.rm.f32.0 +0.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz mantissa LSB rounds towards zero . rcp.approx.f32 rcp.rp }. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 supports subnormal numbers.x. // fast. 2010 93 .f64 introduced in PTX ISA version 1.0 through 1. d.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . a.f64 d.f32 and rcp.f32 requires sm_20 or later. rcp. Instruction Set Table 59.rn. xi.0 -Inf -Inf +Inf +Inf +0.f64 ri.ftz were introduced in PTX ISA version 1. PTX ISA Notes rcp.f32 rcp. a. rcp.approx and .ftz}. rcp. Input -Inf -subnormal -0. rcp.rnd = { . The maximum absolute error is 2-23.rp}. xi. Examples January 24.0 +subnormal +Inf NaN Result -0. rcp.rnd.0 over the range 1.rnd{.f64 requires sm_13 or later.0.f32 rcp. d = 1 / a. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.r. For PTX ISA versions 1.

f32 sqrt.rnd.0 +subnormal +Inf NaN Result NaN NaN -0.approx{.f64 r. sqrt.f64 and explicit modifiers .x.approx.0 +0.rm.0 through 1.ftz.rnd.approx and .rn.f64.4 and later.approx. sqrt. .approx.ftz}. sqrt. sm_1x: sqrt.ftz. subnormal numbers are supported. 2010 .ftz.rn mantissa LSB rounds to nearest even .f32 supported on all target architectures. sqrt.rn.rp }.f32 requires sm_20 or later.rn. Description Semantics Notes Compute sqrt(a).rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f64 defaults to sqrt. .ftz.f32 flushes subnormal inputs and results to sign-preserving zero.approx or .f32 is TBD.x. Examples 94 January 24.f64 supports subnormal numbers. r.0.rn.rnd = { .rm. d = sqrt(a).0 +0. a. sqrt.f32 sqrt.0 -0.f64 introduced in PTX ISA version 1. sqrt. For PTX ISA version 1. approximate square root d. store in d.f32 sqrt. a.rm mantissa LSB rounds towards negative infinity .f32 defaults to sqrt. a.{rz.0. // IEEE 754 compliant rounding .rz mantissa LSB rounds towards zero .f64 d. General rounding modifiers were added in PTX ISA version 2. Input -Inf -normal -subnormal -0.f32.f32 sqrt.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .x.approx. r. sqrt.PTX ISA Version 2. sqrt. sqrt.rn. // IEEE 754 compliant rounding d.4.rz.0 +0. . one of .rnd{. For PTX ISA versions 1.f32 flushes subnormal inputs and results to sign-preserving zero.rn. The maximum absolute error for sqrt.f32 and sqrt.rnd is required. PTX ISA Notes sqrt.3.f64 requires sm_20 or later. // fast.ftz were introduced in PTX ISA version 1.f64 requires sm_13 or later.ftz}.f32 implements a fast approximation to square root.0 Table 60. sqrt.rp}. Target ISA Notes sqrt. and sqrt.

approx. Subnormal numbers: sm_20: By default.4 and later. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. For PTX ISA version 1.0 +0.approx modifier is required.approx. 2010 95 . a.f64 supports subnormal numbers. sm_1x: rsqrt. rsqrt.ftz were introduced in PTX ISA version 1. d = 1/sqrt(a).0-4.f64 were introduced in PTX ISA version 1. The maximum absolute error for rsqrt. rsqrt.f32 and rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.approx{. Input -Inf -normal -subnormal -0.f64 requires sm_13 or later.approx implements an approximation to the reciprocal square root. d. January 24. Note that rsqrt. ISR. subnormal numbers are supported. Instruction Set Table 61.f32. Explicit modifiers . a. rsqrt.ftz.f64 is TBD. Compute 1/sqrt(a). For PTX ISA versions 1.f64 defaults to rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is 2-22.f32 rsqrt. and rsqrt.ftz. rsqrt.f32 rsqrt.3.approx and . X.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f64 d.f64 isr.approx.Chapter 8.f32 supported on all target architectures.ftz.f64.0.f32 defaults to rsqrt. Target ISA Notes Examples rsqrt.approx. rsqrt.4.0 through 1. the . rsqrt.0. PTX ISA Notes rsqrt.4 over the range 1.0 NaN The maximum absolute error for rsqrt.approx.approx.ftz}. rsqrt. x. store the result in d.f64 is emulated in software and are relatively slow.

ftz.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1.ftz}.approx and .PTX ISA Version 2.approx{. sin.4 and later. sin. Subnormal numbers: sm_20: By default. d = sin(a).0 NaN NaN The maximum absolute error is 2-20. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. sm_1x: Subnormal inputs and results to sign-preserving zero.9 in quadrant 00. 2010 . PTX ISA Notes sin. 96 January 24.0 +0.3. sin. For PTX ISA version 1.f32.f32 d.f32 implements a fast approximation to sine. Target ISA Notes Examples Supported on all target architectures. Explicit modifiers .0 +0.f32 introduced in PTX ISA version 1.approx.ftz.0 -0.approx. a.ftz introduced in PTX ISA version 1.4.f32 sa.approx. Input -Inf -subnormal -0.ftz. Find the sine of the angle a (in radians).0 +0. the . subnormal numbers are supported. a. For PTX ISA versions 1.0 +subnormal +Inf NaN Result NaN -0.0 Table 62.0. sin. sin.approx modifier is required.f32 defaults to sin.

cos. Subnormal numbers: sm_20: By default. cos. cos.0.approx.0 +1. a.0 +1. Find the cosine of the angle a (in radians). Explicit modifiers . Target ISA Notes Examples Supported on all target architectures.f32 introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.approx{.0 +0.f32 ca.9 in quadrant 00.f32 implements a fast approximation to cosine. Input -Inf -subnormal -0.ftz.approx and .0 +subnormal +Inf NaN Result NaN +1.4. d = cos(a).0 through 1.ftz}. a.approx modifier is required.f32 d.ftz.f32. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +1. For PTX ISA version 1.approx. Instruction Set Table 63. 2010 97 . subnormal numbers are supported.f32 defaults to cos. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz.3.4 and later. the . January 24.Chapter 8. cos. PTX ISA Notes cos. cos.ftz introduced in PTX ISA version 1. For PTX ISA versions 1.approx.0 NaN NaN The maximum absolute error is 2-20.

PTX ISA Notes lg2. The maximum absolute error is 2-22. lg2.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to log2(a).f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default.approx.approx.approx and .ftz.ftz. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. the .PTX ISA Version 2.3.0 Table 64.ftz. d = log(a) / log(2). For PTX ISA versions 1.approx modifier is required. For PTX ISA version 1.f32 defaults to lg2.ftz introduced in PTX ISA version 1. 2010 .0 through 1. Explicit modifiers .ftz}. lg2. lg2.f32 Determine the log2 of a. lg2. Input -Inf -subnormal -0.4 and later. lg2. 98 January 24.0 +0. a.approx{.0. Target ISA Notes Examples Supported on all target architectures.f32. subnormal numbers are supported.approx.f32 la.f32 flushes subnormal inputs and results to sign-preserving zero. a.4.6 for mantissa.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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p[|q].and. or. geu. p. setp.eq. then these comparisons have the same result as their ordered counterparts. lt. neu. ls. To aid comparison operations in the presence of NaN values. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. . lo.type setp. Semantics t = (a CmpOp b) ? 1 : 0. geu. sm_1x: setp.dtype.f32. lt. ltu. loweror-same. If both operands are numeric values (not NaN).CmpOp{. ge. .s32 setp.i.type .ftz}. and higher-or-same may be used instead of lt. a.b32. subnormal numbers are supported.u16. gtu. nan The Boolean operator BoolOp(A.a. The comparison operator is a suffix on the instruction. ne. le. a. setp with . ne. This result is written to the first destination operand. If either operand is NaN. ne. bit-size comparisons are eq and ne. hi.BoolOp{.u32 p|q.ftz applies only to .f64 supports subnormal numbers. leu. c). and nan returns true if either operand is NaN. lt. setp. and can be one of: eq.r. Modifier . setp. {!}c.s32. A related value computed using the complement of the compare result is written to the second destination operand.f32 comparisons. and (optionally) combine this result with a predicate value by applying a Boolean operator.dtype. ge. hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. For unsigned values. p[|q]. q = BoolOp(!t. c).f32 flushes subnormal inputs to sign-preserving zero.b. xor.B) is one of: and. hs equ. gt. If either operand is NaN.0 Table 67. num.lt. gt.type = { . . and hs for lower. gt. then the result of these comparisons is true.b16. Subnormal numbers: sm_20: By default. gt. unordered versions are included: equ.s16. @q setp. respectively. Applies to all numeric types. num returns true if both operands are numeric values (not NaN). p = BoolOp(t. The destinations p and q must be . setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. . .ftz}. 2010 . .f64 source type requires sm_13 or later.dtype. le. ls.s64. .pred variables. . . b. the result is false.PTX ISA Version 2. le.f64 }.f32 flushes subnormal inputs to sign-preserving zero. neu. The signed and unsigned comparison operators are eq. 102 January 24. le. The untyped.n. ge.0. .u32. leu. higher.b64.CmpOp.u64. ltu. Integer Notes Floating Point Notes The ordered comparisons are eq. gtu. b. ge. the comparison operators lo.ftz.

f64 requires sm_13 or later. . . 2010 103 .u32.xp. operand c must match the second instruction type. . sm_1x: slct.ftz applies only to . a.r.u32.f32 A. slct. b. and operand a is selected.dtype.s32 x.type d.t. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. B. Operands d. selp Syntax Comparison and Selection Instructions: selp Select between source operands. . .s32. f0.f32 comparisons.s64. slct.b16. d = (c >= 0) ? a : b. .x. . d.f32 flushes subnormal values of operand c to sign-preserving zero. a.u32.0. Operands d. otherwise b is stored in d. . y. Instruction Set Table 68. . slct Syntax Comparison and Selection Instructions: slct Select one source operand.f32 comparisons.dtype.s16. slct. . a. . . fval. . .u16.Chapter 8. and b must be of the same type. Introduced in PTX ISA version 1. The selected input is copied to the output without modification. based on the value of the predicate source operand. and b are treated as a bitsize type of the same width as the first instruction type.f32. and operand a is selected. .0.u64. .u64.f64 requires sm_13 or later.type = { .f32 d.dtype = { . a is stored in d.f64 }. Subnormal numbers: sm_20: By default. the comparison is unordered and operand b is selected.s32 slct{. For .ftz}. Description Conditional selection. Operand c is a predicate.s64. c. z.b32. a. . Modifier .b64. b. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. . subnormal numbers are supported. c.f32 r0. Semantics Floating Point Notes January 24.dtype.g. based on the sign of the third operand.u16.f64 }. slct. b. .f32 flushes subnormal values of operand c to sign-preserving zero. Table 69.p.s16. b otherwise. C. a is stored in d. If c is True.f32. selp.b32.s32 selp. selp. c.b64. . .u64.s32. If c ≥ 0. If operand c is NaN. @q selp.b16. .ftz. val. a. negative zero equals zero.dtype.ftz. slct. d = (c == 1) ? a : b.

The logical shift instructions are: and or xor not cnot shl shr 104 January 24. xor. or.PTX ISA Version 2. This permits bit-wise operations on floating point values without having to define a union to access the bits.7. Instructions and.4.0 8. performing bit-wise operations on operands of any type. and not also operate on predicates. provided the operands are of the same size. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.

b.b32 and.b64 }. or. Allowed types include predicate registers. The size of the operands must match. sign.b16. The size of the operands must match. . and. a.r. and Syntax Logic and Shift Instructions: and Bitwise AND.type d.b32. b. January 24.type = { . Supported on all target architectures. and. . Table 71.0. .pred.pred.q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. a. d = a | b.Chapter 8.type d.r.b32 x.b32. . . Instruction Set Table 70. Introduced in PTX ISA version 1.b32 mask mask. .q.b64 }. . but not necessarily the type.0. or.0x00010001 or.b16.pred p. 2010 105 .0x80000000. . but not necessarily the type.type = { . d = a & b.fpvalue. or Syntax Logic and Shift Instructions: or Bitwise OR. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. Allowed types include predicate registers. Introduced in PTX ISA version 1. Supported on all target architectures.

b16. . cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b64 }.b32. The size of the operands must match.type = { .0.b32 d.pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. . 106 January 24. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Supported on all target architectures.q.b32.pred.0. Supported on all target architectures. d = ~a.b64 }. but not necessarily the type. but not necessarily the type. The size of the operands must match.q. d = (a==0) ? 1 : 0. . xor.type = { . . not. not. Table 74.type d.0. . Introduced in PTX ISA version 1.type = { .b32.r. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Allowed types include predicates. Supported on all target architectures.0 Table 72. cnot.a. Introduced in PTX ISA version 1.b16. a.b32 xor.pred p. 2010 .b32 mask. a.0x0001.x. one’s complement. but not necessarily the type. xor.type d. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).type d. b.b64 }. cnot.mask. not Syntax Logic and Shift Instructions: not Bitwise negation. not.PTX ISA Version 2. .b16. a. . The size of the operands must match.b16 d. d = a ^ b. . Introduced in PTX ISA version 1. . d. Allowed types include predicate registers. Table 73.

a.s32 shr. .Chapter 8. shr Syntax Logic and Shift Instructions: shr Shift bits right. k.2. Supported on all target architectures. a. Shift amounts greater than the register width N are clamped to N. .u16 shr. a.s16. The sizes of the destination and first source operand must match. shl. . 2010 107 . The sizes of the destination and first source operand must match. regardless of the instruction type. .b32.b32 q. The b operand must be a 32-bit value.s64 }.type d.type = { . Shift amounts greater than the register width N are clamped to N. shr. PTX ISA Notes Target ISA Notes Examples Table 76. . .type d.u32. Introduced in PTX ISA version 1.a. .u64. shl. but not necessarily the type. . but not necessarily the type. regardless of the instruction type.u16. .b64.0.i.0. shl Syntax Logic and Shift Instructions: shl Shift bits left. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.b16. shr. Introduced in PTX ISA version 1. . Instruction Set Table 75. i. unsigned and untyped shifts fill with 0. .b16.type = { . sign or zero fill on left. Supported on all target architectures.1.b64 }. b. d = a >> b.b16 c. d = a << b.i.b32.s32. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. Signed shifts fill with the sign bit. The b operand must be a 32-bit value. Bit-size types are included for symmetry with SHL. PTX ISA Notes Target ISA Notes Examples January 24. .j.2. b. zero-fill on right.

The cvta instruction converts addresses between generic and global. prefetchu isspacep cvta cvt 108 January 24. suld. mov. and sust support optional cache operations.PTX ISA Version 2. ldu. possibly converting it from one format to another. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. Instructions ld.5. Data Movement and Conversion Instructions These instructions copy data from place to place. or shared state spaces. ld. 2010 . and st operate on both scalar and vector types. and from state space to state space.7. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.0 8. local. st.

cs. Use ld.cv to a frame buffer DRAM address is the same as ld.lu Last use. When ld.lu instruction performs a load cached streaming operation (ld. . the cache operators have the following definitions and behavior. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.ca.lu load last use operation. The compiler / programmer may use ld. the second thread may get stale L1 cache data. As a result of this request.cs is applied to a Local window address. but multiple L1 caches are not coherent for global data. The default load instruction cache operation is ld. A ld. and cache only in the L2 cache. 2010 109 . likely to be accessed once. The ld. not L1). The ld.Chapter 8.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. evict-first. when applied to a local address. For sm_20 and later.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. Table 77. and a second thread loads that address via a second L1 cache with ld.7. any existing cache lines that match the requested address in L1 will be evicted. If one thread stores to global memory via one L1 cache. Instruction Set 8. Operator .lu operation. January 24.cg Cache at global level (cache in L2 and below. if the line is fully covered.cg to cache loads only globally.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. . to allow the thread program to poll a SysMem location written by the CPU. it performs the ld.0 introduces optional cache operators on load and store instructions. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. . rather than the data stored by the first thread. fetch again). The ld.ca loads cached in L1.cs Cache streaming. bypassing the L1 cache. likely to be accessed again.1. invalidates (discards) the local L1 line following the load.5.cs) on global addresses. The cache operators require a target architecture of sm_20 or later.cv Cache as volatile (consider cached system memory lines stale.ca. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Global data is coherent at the L2 level. . Cache Operators PTX 2.

wt Cache write-through (to system memory).wt store write-through operation applied to a global System Memory address writes through the L2 cache. not L1). . rather than get the data from L2 or memory stored by the first thread.ca loads.PTX ISA Version 2. to allow a CPU program to poll a SysMem location written by the GPU with st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. the second thread may get a hit on stale L1 cache data. However. In sm_20. which writes back cache lines of coherent cache levels with normal eviction policy. bypassing its L1 cache. 110 January 24. and discard any L1 lines that match. but st. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.cs Cache streaming. and cache only in the L2 cache. Global stores bypass L1.0 Table 78. Operator . and a second thread in a different SM later loads from that address via a different L1 cache with ld.cg to cache global store data only globally. likely to be accessed once. bypassing the L1 cache. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. The st. regardless of the cache operation. 2010 .wt. Use st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.wb. st. Future GPUs may have globally-coherent L1 caches. . If one thread stores to global memory. .wb for global data. The default store instruction cache operation is st.cg is the same as st. Addresses not in System Memory use normal write-back. The st. in which case st.ca.cg Cache at global level (cache in L2 and below. and marks local L1 lines evict-first.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.cg to local memory uses the L1 cache.wb could write-back global store data from L1.

d = sreg.b64. .v. mov. .f64 requires sm_13 or later. or shared state space may be taken directly using the cvta instruction. // get address of variable // get address of label or function . local. d = &avar. label. sreg.a.0. .e. addr. Introduced in PTX ISA version 1.. and . the generic address of a variable declared in global.. .s64. mov. Note that if the address of a device function parameter is moved to a register.local. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. 2010 111 . d = &label. For variables declared in . Semantics d = a.f32 mov. Take the non-generic address of a variable in global. Instruction Set Table 79.u32 mov. . or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. the address of the variable in its state space) into the destination register. Write register d with the value of a. . alternately.type mov. label. .type mov. d.f32.type mov.e. d. The generic address of a variable in global. d.shared state spaces.1. ptr.s32.u32 mov.pred. mov. u. .u64.u16 mov.b32. or shared state space. A. variable in an addressable memory space. myFunc.u16. . Operand a may be a register.u32 d.type d. // address is non-generic.f64 }.s16. mov places the non-generic address of the variable (i.global. a. .0. the parameter will be copied onto the stack and the address will be in the local state space. avar. . local.const.f32 mov. A[5]. or function name. immediate.u32. Description . special register. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.b16. i. . ptr. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.Chapter 8.type = { . within the variable’s declared state space Notes Although only predicate and bit-size types are required. local. k.

31].b32 mov...z..y << 16) d = a.u8 // unpack 32-bit elements from . d. Description Write scalar register d with the packed value of vector register a..y << 16) | (a.0 Table 80.b.. Supported on all target architectures.b16..15]. a[32. d. d.b8 r.b32.z << 16) | (a.w}. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.7].15]. a[16.hi}. d.y.y } = { a[0.b32 { d.63] } // unpack 16-bit elements from .{a.x | (a. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). .type = { .w << 48) d = a. d. a[8.%r1.w << 24) d = a. a[24. a[16.a}. a[48..x | (a.15].b64 }.u32 x.a have type .w have type ..b64 112 January 24.b32 // pack two 16-bit elements into .z. d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.y.b64 mov. a[32.47].g.x | (a.31] } // unpack 16-bit elements from .z. // // // // a.z << 32) | (a..b64 // pack two 32-bit elements into .31].u16 %x is a double. d.y } = { a[0. a[16.b}. Semantics d = a.hi are ..x.31] } // unpack 8-bit elements from . or write vector register d with the unpacked values from scalar register a. d. For bit-size types.b32 mov. {lo. a[8.b32 // pack four 16-bit elements into .b32 %r1. lo. a.type d..w } = { a[0.y.w } = { a[0.{x.b64 { d.b. . d.0. 2010 .x | (a.b16 { d.7]. mov.x.y << 8) d = a. mov.b16 // pack four 8-bit elements into ..g.y. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.PTX ISA Version 2.x. %x.z. .b have type .y } = { a[0. %r1.23].b64 { d.x.y << 8) | (a. {r...x.y << 32) // pack two 8-bit elements into .b32 { d.15] } // unpack 8-bit elements from .x | (a.

Cache operations are not permitted with ld. 32-bit).0. an address maps to the corresponding location in local or shared memory. . If no state space is given.shared }. [a].param.ss}{. Semantics d d d d = = = = a. In generic addressing.const. .b8. .s32. an address maps to global memory unless it falls within the local memory window or the shared memory window.cs.cop}.e. Generic addressing may be used with ld. . . . i.. *(a+immOff). This may be used.f32 or . . The address must be naturally aligned to a multiple of the access size. Description Load register variable d from the location specified by the source address operand a in specified state space.volatile{. . Within these windows.f16 data may be loaded using ld. . . d. and then converted to . and is zeroextended to the destination register width for unsigned and bit-size types. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.cop = { .f64 }.b64. Generic addressing and cache operations introduced in PTX ISA 2.volatile introduced in PTX ISA version 1. The address size may be either 32-bit or 64-bit. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . A destination register wider than the specified type may be used. .volatile may be used with .s64.ss}.global.cop}.f32.ss}. d. for example.b32.u16.lu.e.volatile{.v4 }. ld introduced in PTX ISA version 1. The . d.u32. an integer or bit-size type register reg containing a byte address. *a.Chapter 8. ld.volatile.volatile.cg. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.vec = { . . .local.ca. 2010 113 . . the access may proceed by silently masking off low-order address bits to achieve proper rounding.type ld.const space suffix may have an optional bank number to indicate constant banks other than bank zero. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ld. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.reg state space.0. Instruction Set Table 81. or [immAddr] an immediate absolute byte address (unsigned.shared spaces to inhibit optimization of references to volatile memory.b16. 32-bit). perform the load using generic addressing. . [a]. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.type d.vec.v2.s8.ss}{.vec.f64 using cvt.ss = { .type = { . the resulting behavior is undefined. . i. and truncated if the register width exceeds the state space address width for the target architecture.type ld{. If an address is not properly aligned. . .1.s16. [a]. . [a]. . .u8. PTX ISA Notes January 24. .cv }. *(immAddr). to enforce sequential consistency between threads accessing shared memory.b16. Addresses are zero-extended to the specified width as needed.global and . . ld{. The value loaded is sign-extended to the destination register width for signed integers. .type . or the instruction may fault.u64.

ld.%r. // negative offset %r.b64 ld.[a]. // immediate address %r.const.[p+-8].v4.f64 requires sm_13 or later. Q. 2010 .f32.f16 d.local.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. d.b32 ld. %r.const[4].global.[buffer+64].[fs].PTX ISA Version 2.f32 ld. Cache operations require sm_20 or later.[p]. x.b32 ld.local.b32 ld.0 Target ISA Notes ld.s32 ld.[p+4].[240]. // access incomplete array x. // load .b16 cvt.shared.global. Generic addressing requires sm_20 or later.

. i. an address maps to global memory unless it falls within the local memory window or the shared memory window. and is zeroextended to the destination register width for unsigned and bit-size types. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. The data at the specified address must be read-only. Addresses are zero-extended to the specified width as needed. .f64 }..Chapter 8.[p]. 32-bit). .global. 2010 115 . // state space .b32 d.f32 or . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. . .vec = { .ss}. and truncated if the register width exceeds the state space address width for the target architecture.global. .u16.s32.s64.v4. ldu. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. i. If no state space is given. where the address is guaranteed to be the same across all threads in the warp. perform the load using generic addressing.ss = { . . The address size may be either 32-bit or 64-bit. .f64 requires sm_13 or later. *a.e. A destination register wider than the specified type may be used. [a].e.type d.vec. . Introduced in PTX ISA version 2.f64 using cvt.s16.b16. If an address is not properly aligned. .type = { .v4 }.b16. ldu{. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b8.type ldu{. // load from address // vec load from address .u64.s8. only generic addresses that map to global memory are legal. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. .f32. A register containing an address may be declared as a bit-size type or integer type. ldu. ldu. For ldu.u32. . d. .f32 Q.v2.global }. Instruction Set Table 82.ss}. and then converted to . or the instruction may fault.u8.f16 data may be loaded using ldu. an address maps to the corresponding location in local or shared memory.[a].reg state space. The addressable operand a is one of: [avar] the name of an addressable variable var. *(a+immOff). .0. The address must be naturally aligned to a multiple of the access size. [a].b64. Within these windows. PTX ISA Notes Target ISA Notes Examples January 24.f32 d.global. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The value loaded is sign-extended to the destination register width for signed integers. In generic addressing. [areg] a register reg containing a byte address. 32-bit). Semantics d d d d = = = = a. ldu.[p+4]. or [immAddr] an immediate absolute byte address (unsigned. *(immAddr).b32. .

[a]. .type [a]. .b32.vec .type st{.cop}.b16.f16 data resulting from a cvt instruction may be stored using st.ss . . This may be used. . The addressable operand a is one of: [var] [reg] the name of an addressable variable var.e.b8.b16. 2010 . *(d+immOffset) = a. .wt }. . If an address is not properly aligned. st. The address size may be either 32-bit or 64-bit. b. Cache operations require sm_20 or later. . b.ss}{.cg. A source register wider than the specified type may be used. . . . the resulting behavior is undefined.v4 }.u8.b64.volatile{. an address maps to the corresponding location in local or shared memory.volatile. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. Generic addressing requires sm_20 or later.ss}.s16. In generic addressing.reg state space.type st.0. *d = a. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. . an address maps to global memory unless it falls within the local memory window or the shared memory window.shared spaces to inhibit optimization of references to volatile memory. Generic addressing and cache operations introduced in PTX ISA 2.vec. The lower n bits corresponding to the instruction-type width are stored to memory.0 Table 83. PTX ISA Notes Target ISA Notes 116 January 24. The address must be naturally aligned to a multiple of the access size. 32-bit). the access may proceed by silently masking off low-order address bits to achieve proper rounding. Addresses are zero-extended to the specified width as needed. . to enforce sequential consistency between threads accessing shared memory. and truncated if the register width exceeds the state space address width for the target architecture.PTX ISA Version 2.. st{.ss}.local. st. b.u32.wb. st. for example. or [immAddr] an immediate absolute byte address (unsigned.shared }.f64 }. [a].global. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.volatile. { .vec.volatile introduced in PTX ISA version 1. b.u64. or the instruction may fault.s8.s32. *(immAddr) = a. Cache operations are not permitted with st. { . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . .f64 requires sm_13 or later. an integer or bit-size type register reg containing a byte address.cop}.s64. st introduced in PTX ISA version 1. 32-bit).v2. Within these windows. i. . .type = = = = {.volatile{. perform the store using generic addressing. i. . Generic addressing may be used with st.volatile may be used with . Semantics d = a.type .e.u16.0.cs.cop .f32. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. .ss}{. [a].1. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . { . If no state space is given. .global and .

// negative offset [100].Chapter 8.local. [fs].global.a. [q+-8]. // %r is 32-bit register // store lower 16 bits January 24.s32 cvt.b32 st.%r. // immediate address %r.r7.v4.f32 st.local.Q.f32 st.global. Instruction Set Examples st. [p]. 2010 117 .%r.local.b16 [a].f16. [q+4].s32 st.b32 st.b.a.

L1 [ptr]. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. A prefetch to a shared memory location performs no operation.PTX ISA Version 2. an address maps to the corresponding location in local or shared memory. an address maps to global memory unless it falls within the local memory window or the shared memory window. [a]. .L1 [addr]. and no operation occurs if the address maps to a local or shared memory location.L1. or [immAddr] an immediate absolute byte address (unsigned.global. 2010 . In generic addressing.global. 32-bit).level prefetchu. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. // prefetch to data cache // prefetch to uniform cache .level = { .0 Table 84. Within these windows.space}. prefetch{.L1 [a]. A prefetch into the uniform cache requires a generic address. 32-bit). prefetchu. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. a register reg containing a byte address. prefetch. Addresses are zero-extended to the specified width as needed.space = { . 118 January 24.e. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.0.local }. . prefetch and prefetchu require sm_20 or later. . in specified state space. The address size may be either 32-bit or 64-bit. i. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.L2 }. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. the prefetch uses generic addressing. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and truncated if the register width exceeds the state space address width for the target architecture. If no state space is given. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.

local. // local. For variables declared in global.space p.size cvta. svar. cvta requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Table 86.local.shared }. lptr.space. a.pred.space = { .u32 p.u64 or cvt. isshrd. .local. or shared address.0. isspacep requires sm_20 or later.Chapter 8.u64 }. cvta. Take the generic address of a variable declared in global.global.size p. cvta.to.local isspacep. the generic address of the variable may be taken using cvta.space.u32 p. isspacep.global. p. or shared address to a generic address. . // get generic address of svar cvta. // convert to generic address // get generic address of var // convert generic address to global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. local.u32 to truncate or zero-extend addresses. When converting a generic address into a global.shared isglbl. // result is . local.u64.shared }. or shared state space. Instruction Set Table 85. The destination register must be of type .space = { .to. The source and destination addresses must be the same size. gptr. .global isspacep.shared.local. A program may use isspacep to guard against such incorrect behavior.size . islcl.u32 gptr. or vice-versa.u32. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. a. .global. var. local.0.pred .space. local. . The source address operand must be a register of type . Use cvt. sptr.u32 or . the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.lptr. Introduced in PTX ISA version 2. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.u64. or shared state space. Description Convert a global. or shared address cvta. or vice-versa. 2010 119 . January 24. isspacep. cvta. p.genptr. or shared state space to generic. . a.size = { .u32.

cvt{. . Note: In PTX ISA versions 1. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. Description Semantics Integer Notes Convert between different types and sizes.rp }.rni.frnd}{.irnd = { .rni round to nearest integer. subnormal inputs are flushed to signpreserving zero.sat}.ftz.dtype. . i. .atype = { .rmi round to nearest integer in direction of negative infinity .rpi }. Integer rounding modifiers: . . .ftz. 120 January 24.s8.dtype.f32.rz.atype cvt{. Saturation modifier: .u16.frnd = { .sat For integer destination types. Integer rounding is required for float-to-integer conversions. The optional .f16.f32.ftz modifier may be specified in these cases for clarity.irnd}{.ftz. // integer rounding // fp rounding . . .4 and earlier..sat is redundant. .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.ftz}{. For float-to-integer conversions.atype d.f32 float-to-integer conversions and cvt. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. . .0 Table 87. a. choosing even integer if source is equidistant between two integers. .f32 float-tofloat conversions with integer rounding.e.sat limits the result to MININT. d = convert(a). Integer rounding is illegal in all other instances.dtype. .u32. a.PTX ISA Version 2.rzi.rn.rm. .ftz}{.s32. Note that saturation applies to both signed and unsigned integer types.f64 }. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. 2010 .s16. The compiler will preserve this behavior for legacy PTX code.u64.f32.ftz.MAXINT for the size of the operation. sm_1x: For cvt. . . .rmi. subnormal inputs are flushed to signpreserving zero. i.rzi round to nearest integer in the direction of zero .s64. .sat}. .dtype = . the . the result is clamped to the destination range by default.f32 float-to-integer conversions and cvt. subnormal numbers are supported. d. For cvt.f32 float-tofloat conversions with integer rounding.u8.e..rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.dtype. . . and for same-size float-tofloat conversions where the value is rounded to an integer. .

rm mantissa LSB rounds towards negative infinity .f32. NaN results are flushed to positive zero.rni. cvt to or from .4 and earlier. stored in floating-point format.ftz behavior for sm_1x targets January 24.Chapter 8. The result is an integral value. Note: In PTX ISA versions 1.sat For floating-point destination types. Modifier .s32 f. cvt.0. // round to nearest int. Applies to .f16. Floating-point rounding modifiers: .f32.version is 1. Specifically.i. result is fp cvt.sat limits the result to the range [0.f32 x. The operands must be of the same size.f32. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. and for integer-to-float conversions.f32 instructions.f32 x.4 or earlier.y. Saturation modifier: .rn mantissa LSB rounds to nearest even .f32. Introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f32.y. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .s32.f64 j.r. Subnormal numbers: sm_20: By default. The compiler will preserve this behavior for legacy PTX code.0]. . subnormal numbers are supported. // float-to-int saturates by default cvt.f32.f16.f32. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. and . and cvt. cvt.f64 types. . Floating-point rounding is illegal in all other instances. The optional .f64 requires sm_13 or later.0.f64. cvt. 2010 121 . 1. // note . if the PTX .ftz modifier may be specified in these cases for clarity.

= nearest width height tsamp1.width. Module-scope and per-entry scope definitions of texture.target texmode_independent .height.f32 r1.f32.entry compute_power ( .f32.texref tex1 ) { txq. The advantage of unified mode is that it allows 128 samplers. . samplers. the file is assumed to use unified mode. PTX has two modes of operation.target options ‘texmode_unified’ and ‘texmode_independent’. add. 122 January 24. but the number of samplers is greatly restricted to 16.samplerref tsamp1 = { addr_mode_0 filter_mode }.. // get tex1’s txq.r4}. A PTX module may declare only one texturing mode.f32 r1.u32 r5.0 8. r5. Ability to query fields within texture. Example: calculate an element’s power contribution as element’s power/total number of elements. r2. PTX supports the following operations on texture.r3. .global .. and surface descriptors. } = clamp_to_border. If no texturing mode is declared. sampler. r3. r3. and surface descriptors. 2010 . [tex1. [tex1]. cvt. [tex1]. r1.7.texref handle. r6. Texturing modes For working with textures and samplers.param . r1. texture and sampler information each have their own handle. allowing them to be defined separately and combined at the site of usage in the program. r4.6.v4. Texture and Surface Instructions This section describes PTX instructions for accessing textures. add.f32 {r1. with the restriction that they correspond 1-to-1 with the 128 possible textures. In the unified mode. add.f32 r1. The advantage of independent mode is that textures and samplers can be mixed and matched. // get tex1’s tex. r1. sampler. div. {f1. In the independent mode. texture and sampler information is accessed through a single .f32 r3.2d. r5. and surfaces. and surface descriptors: • • • Static initialization of texture. and surface descriptors.b32 r5. r5.f2}]. The texturing mode is selected using . sampler.r2. .PTX ISA Version 2.u32 r5. mul. sampler.b32 r6.

dtype. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .geom. Unified mode texturing introduced in PTX ISA version 1. c].btype = { .dtype = { .Chapter 8.geom = { .f32 {r1. Description Texture lookup using a texture coordinate vector. PTX ISA Notes Target ISA Notes Examples January 24. or the instruction may fault.1d.btype tex. [a.r3. . b.v4. A texture base address is assumed to be aligned to a 16-byte address.f32 }. sampler_x.5.r3. .s32 {r1. // explicit sampler . [tex_a. // Example of independent mode texturing tex. . {f1}].s32. .s32.s32. the resulting behavior is undefined.3d }. If an address is not properly aligned. //Example of unified mode texturing tex. and is a four-element vector for 3d textures.2d.r4}.btype d.e.0. {f1.f3.v4.v4 coordinate vectors are allowed for any geometry.dtype.u32. . If no sampler is specified. is a two-element vector for 2d textures. i.3d. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. Notes For compatibility with prior versions of PTX. An optional texture sampler b may be specified. Operand c is a scalar or singleton tuple for 1d textures. tex. 2010 123 .s32.r4}. . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.1d. [tex_a. d.r2. the square brackets are not required and . Instruction Set These instructions provide access to texture and surface memory.geom. [a.r2. the sampler behavior is a property of the named texture. where the fourth element is ignored.f4}].f32 }. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. tex txq suld sust sured suq Table 88. c]. Supported on all target architectures. The instruction always returns a four-element vector of 32-bit values. with the extra elements being ignored.v4.f2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.v4.

addr_mode_0.width . Description Query an attribute of a texture or sampler.addr_mode_0 . [a].filter_mode .normalized_coords }.b32 %r1.b32 %r1. [a]. linear } Integer from enum { wrap.filter_mode.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.width.5.normalized_coords . txq. txq. mirror.0 Table 89. [tex_A]. clamp_ogl. // unified mode // independent mode 124 January 24. addr_mode_2 }. [smpl_B].b32 %r1.samplerref variable.height. . .texref or . Operand a is a .filter_mode. and in independent mode sampler attributes are accessed via a separate samplerref argument. In unified mode.tquery.PTX ISA Version 2.squery = { .depth . addr_mode_1. sampler attributes are also accessed via a texref argument. clamp_to_edge.height .addr_mode_1 . d. . [tex_A]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. txq.depth.b32 d. Supported on all target architectures. // texture attributes // sampler attributes .squery. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. .b32 txq.width. Query: . 2010 . Integer from enum { nearest. .tquery = { .addr_mode_0. txq.

[a. is a two-element vector for 2d surfaces.z. if the surface format contains SINT data. or .cv }.1d. b]. suld Syntax Texture and Surface Instructions: suld Load from surface memory.v4.dtype .clamp field specifies how to handle out-of-bounds addresses: .w}].b16. or the instruction may fault.5.clamp . Coordinate elements are of type . // unformatted d. B. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. suld. . suld. . // for suld.b32.0. A surface base address is assumed to be aligned to a 16-byte address.clamp . The .vec . i. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap introduced in PTX ISA version 1. then . suld. .cs. .b supported on all target architectures. and is a four-element vector for 3d surfaces.p.b8 . . sm_1x targets support only the . .3d }. or FLOAT data.b32.cop}.2d. Target ISA Notes Examples January 24.u32.zero }. suld. If an address is not properly aligned.cop}.u32 is returned.trap suld. size and type conversion is performed as needed to convert from the surface sample format to the destination type.b. // for suld.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. [surf_A.b performs an unformatted load of binary data.cg. . and the size of the data transfer matches the size of destination operand d.f32 is returned. [surf_B.geom .u32. and cache operations introduced in PTX ISA version 2.y. the resulting behavior is undefined. Instruction Set Table 90.3d requires sm_20 or later.trap clamping modifier.dtype . . where the fourth element is ignored.e. suld.b . Operand a is a .b32.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.dtype. or . .v4 }. additional clamp modifiers. {x}].p requires sm_20 or later. .s32. suld.trap.p is currently unimplemented. // cache operation none. if the surface format contains UINT data. the surface sample elements are converted to . . the access may proceed by silently masking off low-order address bits to achieve proper rounding. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.p .cop .vec.f32. SNORM.clamp. 2010 125 ..trap .p. suld. If the destination base type is . Cache operations require sm_20 or later. .3d.f32 based on the surface format as follows: If the surface format contains UNORM. . .s32.s32 is returned. suld.Chapter 8.clamp = = = = = = { { { { { { d. The lowest dimension coordinate represents a sample offset rather than a byte offset.b. If the destination type is .b64.b64 }. {f1.ca.geom{.clamp suld.f32. . Destination vector elements corresponding to components that do not appear in the surface format are not written. then .s32. G.surfref variable.r2}.dtype. b].v2.f32 }.v4.f4}. Description Load from surface memory using a surface coordinate vector. .p. . and A components of the surface format. Operand b is a scalar or singleton tuple for 1d surfaces.1d.s32.f3.f2.trap {r1. . {x. suld. [a.geom{.b.v2.u32. then . // formatted . .

.u32. If an address is not properly aligned.1d.3d }.0.clamp. sust. i. sust.b // for sust. [surf_B. G. Operand a is a .{u32.f2. 2010 . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.v4 }.clamp . the access may proceed by silently masking off low-order address bits to achieve proper rounding.trap .wt }. {f1. sm_1x targets support only the .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. // unformatted // formatted . The size of the data transfer matches the size of source operand c. B.surfref variable. if the surface format contains SINT data.geom{.s32. if the surface format contains UINT data. . If the source base type is . .clamp field specifies how to handle out-of-bounds addresses: . sust Syntax Texture and Surface Instructions: sust Store to surface memory. and cache operations introduced in PTX ISA version 2. Operand b is a scalar or singleton tuple for 1d surfaces.z.cop . Target ISA Notes Examples 126 January 24.vec . Cache operations require sm_20 or later. . .clamp .geom{.b8 .v4.0 Table 91.f32.1d.b. and A surface components.b16.cop}. sust. If the source type is . . . is a two-element vector for 2d surfaces.b. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. {x}].y. then . Surface sample components that do not occur in the source vector will be written with an unpredictable value. additional clamp modifiers.e.. The source data is then converted from this type to the surface sample format. Source elements that do not occur in the surface sample are ignored.p. b].p. The . sust.p. sust.2d.trap clamping modifier.u32 is assumed. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32. or . A surface base address is assumed to be aligned to a 16-byte address. These elements are written to the corresponding surface sample components.b supported on all target architectures.vec.b64. SNORM.w}].cg. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.zero }.f32 }.v2.b64 }.ctype .PTX ISA Version 2.r2}.p. b]. . the resulting behavior is undefined.b32.vec.trap. .trap sust. {x. Coordinate elements are of type .clamp = = = = = = { { { { { { [a. sust. sust.wb.geom . sust. and is a four-element vector for 3d surfaces.p Description Store to surface memory using a surface coordinate vector.b.trap [surf_A. where the fourth element is ignored.f32 is assumed.trap introduced in PTX ISA version 1.u32. .clamp sust.b performs an unformatted store of binary data.f32} are currently unimplemented. .ctype . . The lowest dimension coordinate represents a sample offset rather than a byte offset. [a. . .p requires sm_20 or later. .b32. c.p performs a formatted store of a vector of 32-bit data values to a surface sample. // for sust.ctype.f4}. or FLOAT data.f32.5. . or the instruction may fault.cop}.cs.f3. sust.3d. .s32 is assumed. size and type conversions are performed as needed between the surface sample format and the destination type. . .b32. . The source vector elements are interpreted left-to-right as R.v2.ctype.s32. {r1. none. then . c. then .3d requires sm_20 or later.s32.

or the instruction may fault.add. The .geom. . .u64 data. then . the resulting behavior is undefined.clamp [a.ctype. sured. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. {x}].e.clamp . sured. .clamp [a. .u32 based on the surface sample format as follows: if the surface format contains UINT data.u32 is assumed.clamp field specifies how to handle out-of-bounds addresses: . . r1. r1. and the data is interpreted as .min. Coordinate elements are of type . if the surface format contains SINT data. and .b32.b]. [surf_B.trap sured. . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. .b32 }.s32 types.b]. // sample addressing .p performs a reduction on sample-addressed 32-bit data.clamp = { .u64. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.b .b. .2d. .op.Chapter 8.min. i. sured. .geom.b.c. The lowest dimension coordinate represents a sample offset rather than a byte offset. is a two-element vector for 2d surfaces.op = { .1d.s32 or . // for sured.s32. Reduction to surface memory using a surface coordinate vector.u32 and . // for sured.add.u32. Instruction Set Table 92.or }.u64.3d }.s32 is assumed.p. operations and and or apply to . . Operand b is a scalar or singleton tuple for 1d surfaces.u32.u32.ctype.max. 2010 127 .surfref variable. min and max apply to . then .clamp.0. the access may proceed by silently masking off low-order address bits to achieve proper rounding.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.p . sured.p. A surface base address is assumed to be aligned to a 16-byte address. and is a four-element vector for 3d surfaces..y}].s32.2d.ctype = { .b32 type. {x. Operations add applies to .trap .1d.s32 types. Operand a is a . If an address is not properly aligned.b32 }. or . // byte addressing sured. .ctype = { .geom = { .c. January 24. The instruction type is restricted to .trap. . sured requires sm_20 or later. .and.zero }.op.b performs an unformatted reduction on .b32.u32. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.s32. where the fourth element is ignored.b32. .trap [surf_A. .

height .PTX ISA Version 2.query. Supported on all target architectures.query = { .width . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. [a].b32 %r1. 2010 . . [surf_A]. Operand a is a .width.surfref variable.5.depth }. suq.b32 d.0 Table 93.height. . . Query: . 128 January 24.width. suq. Description Query an attribute of a surface.

c.7.0. Supported on all target architectures. Execute an instruction or instruction block for threads that have the guard predicate true. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. Threads with a false guard predicate do nothing. Instruction Set 8. { instructionList } The curly braces create a group of instructions.b. Supported on all target architectures.f32 @q bra L23.s32 a. @{!}p instruction. { add.7. used primarily for defining a function body. mov. Introduced in PTX ISA version 1. ratio.f32 @!p div.x. setp. 2010 129 . p.0.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Table 95. {} Syntax Description Control Flow Instructions: { } Instruction grouping.a.eq.y. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.s32 d. If {!}p then instruction Introduced in PTX ISA version 1.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.0. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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popc is the number of threads with a true predicate.version 2. The barrier instructions signal the arrival of the executing threads at the named barrier.15. the bar. and any-thread-true (. Only bar. and d have type . it is as if all the threads in the warp have executed the bar instruction.{arrive.sync without a thread count introduced in PTX ISA 1.and. The reduction operations for bar. threads within a CTA that wish to communicate via memory can store to memory.red} require sm_20 or later. if any thread in a warp executes a bar instruction.op = { . b. In conditionally executed code. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.red performs a reduction operation across threads. thread count.{arrive. and bar. the waiting threads are restarted without delay. Execution in this case is unpredictable. {!}c. Operands a. All threads in the warp are stalled until the barrier completes.red delays the executing threads (similar to bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. {!}c. bar.red are population-count (. bar. When a barrier completes. and then safely read values stored by other threads prior to the barrier.red. bar. bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. Since barriers are executed on a per-warp basis. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. . while .red instruction. b}. If no thread count is specified.arrive a{..sync with an immediate barrier number is supported for sm_1x targets. b}. Once the barrier count is reached.u32. it simply marks a thread's arrival at the barrier. execute a bar. bar. and the barrier is reinitialized so that it can be immediately reused. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). The result of .sync 0. In addition to signaling its arrival at the barrier. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.cta.and and . operands p and c are predicates.op.arrive does not cause any waiting by the executing threads.0.red. bar. bar. PTX ISA Notes Target ISA Notes Examples bar.sync) until the barrier count is met. January 24. Register operands. bar. Description Performs barrier synchronization and communication within a CTA.arrive. all-threads-true (. Operand b specifies the number of threads participating in the barrier.pred . b}. a{. p.sync or bar. bar.popc). a{.Chapter 8. b.or). a.sync bar. 2010 133 .sync and bar.arrive using the same active barrier.red should not be intermixed with bar.0. Instruction Set Table 100. the final value is written to the destination register in all threads waiting at the barrier. Thus.or }. Each CTA instance has sixteen barriers numbered 0. Register operands. Thus.u32 bar.red also guarantee memory ordering among threads identical to membar. all threads in the CTA participate in the barrier.red performs a predicate reduction across the threads participating in the barrier. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. the optional thread count must be a multiple of the warp size. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).and).popc.sync or bar. d. Note that a non-zero thread count is required for bar. and bar.red} introduced in PTX . thread count.sync and bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.

level = { .cta.version 2. membar. membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.sys. . Waits until prior memory reads have been performed with respect to other threads in the CTA.gl} supported on all target architectures.level.sys will typically have much longer latency than membar.0 Table 101. For communication between threads in different CTAs or even different SMs.gl} introduced in PTX . global. . when the previous value can no longer be read.version 1. membar.sys introduced in PTX .cta.{cta. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. level describes the scope of other clients for which membar is an ordering event.gl. that is. membar.gl. or system memory level. 134 January 24. membar. membar.gl will typically have a longer latency than membar.{cta. .sys Waits until all prior memory requests have been performed with respect to all clients. PTX ISA Notes Target ISA Notes Examples membar. membar. membar. this is the appropriate level of membar.gl. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.4. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.cta.g. red or atom) has been performed when the value written has become visible to other clients at the specified level. A memory read (e.PTX ISA Version 2. and memory reads by this thread can no longer be affected by other thread writes. membar. membar.sys requires sm_20 or later. by st.cta Waits until all prior memory writes are visible to other threads in the same CTA. membar.0.sys }. A memory write (e.g. including thoses communicating via PCI-E such as system and peer-to-peer memory. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. 2010 .

Chapter 8. January 24. . . The address size may be either 32-bit or 64-bit.shared }. Addresses are zero-extended to the specified width as needed. i.type atom{.s32.space}..f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . .u64 .u32 only .cas. [a]. . . cas (compare-and-swap). Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. .e.op.f32 }. c. xor. . A register containing an address may be declared as a bit-size type or integer type.dec. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The floating-point operations are add.g.type d. a de-referenced register areg containing a byte address. The floating-point add. 32-bit operations.f32.op.max }. and stores the result of the specified operation at location a. . Operand a specifies a location in the specified state space. [a].exch to store to locations accessed by other atomic operations. accesses to local memory are illegal.b].b64. The integer operations are add. .space}. the resulting behavior is undefined. or by using atom.u32. .and.space = { .min. perform the memory accesses using generic addressing. . Description // // // // // . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. .add. If an address is not properly aligned. . For atom. or.inc. Within these windows. .e. .b32. i. dec.s32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. by inserting barriers between normal stores and atomic operations to a common address. .b32 only . .or. .u32.b64 . inc. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. atom{.b32. .s32.f32 Atomically loads the original value at location a into destination register d. min. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. b. and exch (exchange). The address must be naturally aligned to a multiple of the access size. max.global. performs a reduction operation with operand b and the value in location a. . In generic addressing. an address maps to global memory unless it falls within the local memory window or the shared memory window.exch. and max.op = { . or the instruction may fault. 2010 135 . . Instruction Set Table 102. an address maps to the corresponding location in local or shared memory. min.xor. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u64. min. b.u32. atom.add. overwriting the original value. and max operations are single-precision. The inc and dec operations return a result in the range [0. d. or [immAddr] an immediate absolute byte address.type = { . The bit-size operations are and. and truncated if the register width exceeds the state space address width for the target architecture. .. If no state space is given. . e.

0.shared.PTX ISA Version 2. cas(r.{min. s) = (r >= s) ? 0 dec(r. 2010 .cas.f32. *a = (operation == cas) ? : } where inc(r. b.b32 d.f32 atom. 64-bit atom. : r-1. Introduced in PTX ISA version 1.1. Use of generic addressing requires sm_20 or later.exch} requires sm_12 or later. atom.[a].cas.max} are unimplemented. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.t) = (r == s) ? t operation(*a.add.s32 atom.add.0. : r.global.my_new_val.s.[x+4].f32 requires sm_20 or later. 64-bit atom.0 Semantics atomic { d = *a. : r+1. b).global requires sm_11 or later. Release Notes Examples @p 136 January 24.[p].my_val.shared requires sm_12 or later. d. s) = s.shared operations require sm_20 or later. c) operation(*a.global. s) = (r > s) ? s exch(r.{add. atom. atom. atom. d.max.

perform the memory accesses using generic addressing. If no state space is given. the resulting behavior is undefined. The address must be naturally aligned to a multiple of the access size. Instruction Set Table 103. e.op = { . i.op. and xor. The integer operations are add. and max operations are single-precision.max }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. where inc(r. red{. In generic addressing. or the instruction may fault.s32. The address size may be either 32-bit or 64-bit. Notes Operand a must reside in either the global or shared state space. or. . . Description // // // // . Semantics *a = operation(*a. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u32. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. min. red. and truncated if the register width exceeds the state space address width for the target architecture. . . Within these windows. 2010 137 . min.and.add.inc. by inserting barriers between normal stores and reduction operations to a common address. The floating-point operations are add.g.s32.b64.dec. b.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . .b]. Addresses are zero-extended to the specified width as needed.e. max.space}.min.or. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .f32 Performs a reduction operation with operand b and the value in location a. inc. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. The bit-size operations are and. dec(r. . and max. an address maps to global memory unless it falls within the local memory window or the shared memory window.f32 }.xor. . For red. . A register containing an address may be declared as a bit-size type or integer type. The inc and dec operations return a result in the range [0. Operand a specifies a location in the specified state space.u32 only . . s) = (r > s) ? s : r-1. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. s) = (r >= s) ? 0 : r+1. . .u64. If an address is not properly aligned.s32.space = { .add. and stores the result of the specified operation at location a.u64 .b32. ..shared }. or [immAddr] an immediate absolute byte address. . 32-bit operations. overwriting the original value.global.. b). .e. . January 24. The floating-point add. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.type [a]. min.Chapter 8. i.type = { .f32. or by using atom.exch to store to locations accessed by other reduction operations. .b32 only .u32. an address maps to the corresponding location in local or shared memory. dec.u32. a de-referenced register areg containing a byte address. accesses to local memory are illegal.

global.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [p]. red. 64-bit red. red.max.f32. [x+4].add.f32 requires sm_20 or later. 2010 . Release Notes Examples @p 138 January 24.b32 [a]. red.2. red. Use of generic addressing requires sm_20 or later.shared requires sm_12 or later.{min.my_val.f32 red.add requires sm_12 or later.and.1.shared.add.global.0.max} are unimplemented.PTX ISA Version 2.shared operations require sm_20 or later.global requires sm_11 or later red. 64-bit red.s32 red.

In the ‘ballot’ form. The destination predicate value is the same across all threads in the warp.b32 requires sm_20 or later.ballot. Negate the source predicate to compute .ballot. vote.pred d.q.ballot. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.all True if source predicate is True for all active threads in warp.ballot. returns bitmask .q.Chapter 8. Description Performs a reduction of the source predicate across threads in a warp.uni. where the bit position corresponds to the thread’s lane id.none.b32 p. Note that vote applies to threads in a single warp. vote.pred vote.uni. {!}a. // get ‘ballot’ across warp January 24. . Instruction Set Table 104. {!}a.all.any.2. r1. . not across an entire CTA.b32 d.uni True if source predicate has the same value in all active threads in warp. vote. .mode = { . vote. Negating the source predicate also computes . .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. vote.all. vote requires sm_12 or later.any True if source predicate is True for some active thread in warp.p.uni }. // ‘ballot’ form.not_all. 2010 139 . p. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.mode.pred vote. The reduction modes are: . Negate the source predicate to compute .

dsel = . .secop = { . . The general format of video instructions is as follows: // 32-bit scalar operation.h0.sat} d.b2. . optionally clamp the result to the range of the destination type.s33 values.btype{.dtype.u32 or . 4. half-word.dtype.bsel}. 2010 .s32) is specified in the instruction type.b3.s34 intermediate result. .add. . a{.min. the input values are extracted and signor zero. Using the atype/btype and asel/bsel specifiers. or word values from its source operands.sat}. c. The primary operation is then performed to produce an .asel}.dtype = .asel}. .btype{.9.btype = { . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). a{. vop. . extract and sign.s32 }.extended internally to . The type of each operand (.sat} d.b0.atype. . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.7.PTX ISA Version 2. b{. with optional data merge vop. Video Instructions All video instructions operate on 32-bit register operands. b{.asel = .b1. with optional secondary operation vop.atype = .bsel}. b{. . 140 January 24. c.bsel}. taking into account the subword destination size in the case of optional data merging.h1 }. 2.asel}.or zero-extend byte.secop d. perform a scalar arithmetic operation to produce a signed 34-bit result. // 32-bit scalar operation.dsel. 3.atype.u32. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.bsel = { . all combinations of dtype.0 8. . . atype.max }.dtype. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.atype. a{. The source and destination operands are all 32-bit registers.btype{. to produce signed 33-bit input values. The sign of the intermediate result depends on dtype. and btype are valid.

U16_MIN ). The sign of the c operand is based on dtype. S32_MIN ).b1: return ((tmp & 0xff) << 8) case . tmp. c). S8_MIN ). tmp. tmp. U32_MIN ). . . c).h0.h1: return ((tmp & 0xffff) << 16) case . .min: return MIN(tmp. U8_MIN ). S8_MAX.s33 tmp. U16_MAX. January 24.s33 c) { switch ( secop ) { . switch ( dsel ) { case . . tmp. Bool sign. . as shown in the following pseudocode. c). U32_MAX. U8_MAX. . . Bool sat.b0: return ((tmp & 0xff) case . S16_MIN ). Instruction Set .h0: return ((tmp & 0xffff) case .Chapter 8.b0.b3: return ((tmp & 0xff) << 24) default: return tmp. } } .b3: if ( sign ) return CLAMP( else return CLAMP( case . default: return tmp.add: return tmp + c. c). Modifier dsel ) { if ( !sat ) return tmp.max return MAX(tmp.b1. .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. c).b2. . 2010 141 . S16_MAX. .s33 optSaturate( .b2: return ((tmp & 0xff) << 16) case .s33 tmp.s33 optSecOp(Modifier secop. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. c). S32_MAX. c). . The lower 32-bits are then written to the destination operand. tmp.s33 c ) switch ( dsel ) { case .s33 optMerge( Modifier dsel.s34 tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).

sat} d. r3. // optional secondary operation d = optMerge( dsel.u32. b{. b{. vabsdiff. // 32-bit scalar operation. // extract byte/half-word/word and sign. vmax }.h0.PTX ISA Version 2. // optional merge with c operand 142 January 24. vabsdiff.sat. b{. c. Perform scalar arithmetic operation with optional saturate.h1. taking into account destination type and merge operations tmp = optSaturate( tmp. vmin. . with optional secondary operation vop. tmp.s32. r2. r3.s32. r2. Integer byte/half-word/word minimum / maximum. vmax Syntax Integer byte/half-word/word addition / subtraction. and optional secondary arithmetic operation or subword data merge. Semantics // saturate. btype. vsub. with optional data merge vop.op2 Description = = = = { vadd.s32.dtype. r3. vmin. vadd.b0.btype = { .bsel}. tmp = MIN( ta.sat vabsdiff.btype{. c ).h0. c.max }. asel ). vmax require sm_20 or later. c ). tmp = MAX( ta. .vop .h1 }.atype. . // 32-bit scalar operation.bsel = { .sat vsub. isSigned(dtype). . .atype = .sat vmin. Integer byte/half-word/word absolute value of difference.u32.s32. r1. c. r3.bsel}.sat}. a{. vabsdiff. vmin.b2.dtype .op2 d. 2010 .atype. sat. vsub. bsel ).b1.s32. vsub vabsdiff vmin.add. tb ).or zero-extend based on source operand type ta = partSelectSignExtend( a. tb = partSelectSignExtend( b.dtype. a{.b0.bsel}.s32 }. vmax vadd. atype.asel = . . tmp = ta – tb. r2. d = optSecondaryOp( op2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.btype{. tb ). vadd. r1.h1. Video Instructions: vadd. dsel ). { .atype.b0. r2.s32. vsub. tmp = | ta – tb |.s32.dsel .btype{.s32.s32.u32. r1.0. . .0 Table 105.asel}.add r1.dtype.b3. .b2. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.min.h0. vop.s32. c.sat} d.dsel.asel}. a{. . tmp.asel}. .

b{. Left shift fills with zero. if ( mode == . asel ). isSigned(dtype).atype = { . d = optSecondaryOp( op2. if ( mode == . vshl: Shift a left by unsigned amount in b with optional saturate.dtype.clamp && tb > 32 ) tb = 32.asel}.u32.u32.bsel = { .u32 vshr.u32{.asel}. . a{.clamp. taking into account destination type and merge operations tmp = optSaturate( tmp. a{.wrap r1.s32.mode . bsel ). . vshr }. Instruction Set Table 106. // 32-bit scalar operation. b{. .mode}.mode} d. unsigned shift fills with zero. Video Instructions: vshl.bsel}. a{.b3.add. // optional secondary operation d = optMerge( dsel. c. tmp.0. r2.u32{.h0.dtype . and optional secondary arithmetic operation or subword data merge.dtype. vshr vshl.sat}{.atype. tmp. Signed shift fills with the sign bit.atype. tb = partSelectSignExtend( b. atype.u32. c ). with optional data merge vop.u32.asel}. . .sat}{. with optional secondary operation vop.bsel}. vshl.max }. .wrap }.u32.asel = . . .b1. switch ( vop ) { case vshl: tmp = ta << tb.dtype. .clamp . . vshr require sm_20 or later. vop. case vshr: tmp = ta >> tb. vshr Syntax Integer byte/half-word/word left / right shift. r3.wrap ) tb = tb & 0x1f. r1. r2. c ).atype. January 24. vshl.h1. dsel ). r3.or zero-extend based on source operand type ta = partSelectSignExtend( a. { .dsel. } // saturate. // default is . sat. Semantics // extract byte/half-word/word and sign.dsel . and optional secondary arithmetic operation or subword data merge.b0.b2.op2 Description = = = = = { vshl.s32 }.min. . // 32-bit scalar operation.u32{.h1 }. . b{.Chapter 8.bsel}. vshr: Shift a right by unsigned amount in b with optional saturate.op2 d.vop .mode} d. 2010 143 .u32. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat}{. c. { .

final signed The intermediate result is optionally scaled via right-shift.U32 // intermediate unsigned. . .asel}.dtype. . (a*b) is negated if and only if exactly one of a or b is negated.dtype = . . PTX allows negation of either (a*b) or c. Depending on the sign of the a and b operands.po mode. . final signed (S32 * S32) + S32 // intermediate signed. internally this is represented as negation of the product (a*b). c. The source operands support optional negation with some restrictions. otherwise. final signed -(S32 * U32) + S32 // intermediate signed. the intermediate result is signed. final signed (U32 * S32) .S32 // intermediate signed. and the operand negates.btype = { .PTX ISA Version 2. The final result is unsigned if the intermediate result is unsigned and c is not negated.0 Table 107. 2010 . Input c has the same sign as the intermediate result.. Although PTX syntax allows separate negation of the a and b operands.b2. which is used in computing averages. final signed (S32 * U32) . Source operands may not be negated in . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.btype{. .b0.asel}.btype. and zero-extended otherwise. 144 January 24.dtype. final signed (U32 * U32) . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.scale} d. this result is sign-extended if the final result is signed.shr15 }.h0.S32 // intermediate signed.sat}{.po{.scale = { . vmad. and scaling.bsel}. final signed -(S32 * S32) + S32 // intermediate signed.shr7. final signed (S32 * U32) + S32 // intermediate signed. .b1.po) computes (a*b) + c + 1. {-}c. {-}b{.s32 }.sat}{.bsel = { . Description Calculate (a*b) + c. “plus one” mode. .b3. with optional operand negates.asel = .scale} d. final signed (U32 * S32) + S32 // intermediate signed. . The “plus one” mode (.bsel}. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. a{.u32. final signed -(U32 * S32) + S32 // intermediate signed.atype.atype.atype = . That is. {-}a{. b{.h1 }.S32 // intermediate signed. // 32-bit scalar operation vmad. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (S32 * S32) . . final unsigned -(U32 * U32) + S32 // intermediate signed.

case .negate ) { c = ~c. } else if ( c. 2010 145 . lsb = 1.u32. bsel ).u32. r3. U32_MIN). S32_MAX. -r3.h0. January 24.sat vmad.0.h0. tmp[127:0] = ta * tb. vmad requires sm_20 or later. switch( scale ) { case . } else if ( a. Instruction Set Semantics // extract byte/half-word/word and sign. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. btype. asel ). signedFinal = isSigned(atype) || isSigned(btype) || (a. U32_MAX.shr15: result = (tmp >> 15) & 0xffffffffffffffff. tb = partSelectSignExtend( b. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).Chapter 8. r0.negate ^ b.negate.or zero-extend based on source operand type ta = partSelectSignExtend( a. atype.s32.shr15 r0. lsb = 1. S32_MIN). if ( .u32. r2.s32. } if ( .po ) { lsb = 1.negate ) { tmp = ~tmp.negate ^ b. r1. r1. vmad. tmp = tmp + c128 + lsb.u32. else result = CLAMP(result.negate) || c.shr7: result = (tmp >> 7) & 0xffffffffffffffff.sat ) { if (signedFinal) result = CLAMP(result. lsb = 0. r2.

asel = . { .gt.dsel .atype.cmp d. with optional secondary operation vset. tb. atype. cmp ) ? 1 : 0.b2. with optional secondary arithmetic operation or subword data merge. tmp = compare( ta.u32.ge }.ne r1.u32.0 Table 108.u32. with optional data merge vset.le. vset. . . . Semantics // extract byte/half-word/word and sign.op2 d.lt vset.s32 }. and therefore the c operand and final result are also unsigned. a{. .PTX ISA Version 2. asel ). Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. .ne. { .bsel}.h1. .cmp. . bsel ).add.atype. . 146 January 24. vset requires sm_20 or later. 2010 .asel}.cmp .asel}. .cmp d.bsel}.eq. Compare input values using specified comparison. r3.btype.btype. tmp. .h1 }. . // 32-bit scalar operation. . tmp. // 32-bit scalar operation.atype .s32. c. // optional secondary operation d = optMerge( dsel.b1. b{. r3.0.op2 Description = = = = . vset.bsel}. c ). c ).min.u32. tb = partSelectSignExtend( b.bsel = { . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c.btype = { .lt.max }.or zero-extend based on source operand type ta = partSelectSignExtend( a.b0. . d = optSecondaryOp( op2. b{.b3. . r1. a{. a{.btype. The intermediate result of the comparison is always unsigned.asel}. btype.atype. r2.h0. r2. b{.dsel. .

The relationship between events and counters is programmed via API calls from the host. trap. brkpt. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. numbered 0 through 15. Supported on all target architectures. with index specified by immediate operand a.7. trap. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Triggers one of a fixed number of performance monitor events. pmevent 7.0. brkpt. 2010 147 . pmevent a. Table 110. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. @p pmevent 1.0.10. Introduced in PTX ISA version 1.4. there are sixteen performance monitor events. January 24. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. trap Abort execution and generate an interrupt to the host CPU. brkpt requires sm_11 or later. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Introduced in PTX ISA version 1. Instruction Set 8. Table 111.Chapter 8. Supported on all target architectures. brkpt Suspends execution Introduced in PTX ISA version 1.

PTX ISA Version 2.0 148 January 24. 2010 .

%clock64 %pm0. %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. 2010 149 .Chapter 9. %lanemask_gt %clock. read-only variables. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_lt. Special Registers PTX includes a number of predefined. %pm3 January 24. …. %lanemask_le.

x to %rh Target ISA Notes Examples // legacy PTX 1.x. .x.x 0 <= %tid.x * %ntid.0.u32 type in PTX 2. %ntid.u32 %r1. // compute unified thread id for 2D CTA mov.z == 1 in 2D CTAs. Redefined as . PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures. %tid. mov. It is guaranteed that: 0 <= %tid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.x. The fourth element is unused and always returns zero. The %tid special register contains a 1D.x < %ntid. .u32 %ntid. %ntid. . mov. The total number of threads in a CTA is (%ntid. read-only special register initialized with the number of thread ids in each CTA dimension.%tid. %ntid. 2010 . Supported on all target architectures.u32. read-only.u32 %h1.x code accessing 16-bit component of %tid mov. 2D.u32 type in PTX 2.0 Table 112.z < %ntid.z == 0 in 2D CTAs. .u32 %h2.sreg .%tid.y == %ntid.v4. The number of threads in each dimension are specified by the predefined special register %ntid.u32 %r0.v4 . Every thread in the CTA has a unique %tid. // legacy PTX 1. %ntid.u16 %rh. the fourth element is unused and always returns zero.z == 1 in 1D CTAs.%tid. // move tid.sreg . cvt.y * %ntid. // zero-extend tid.y. the %tid value in unused dimensions is 0.y.y. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.z).%h1.z == 0 in 1D CTAs.%tid. mov.z.x.x.%ntid. CTA dimensions are non-zero.y < %ntid.v4.z.x code Target ISA Notes Examples 150 January 24.u32 %tid.x. %tid.y 0 <= %tid.%r0.%ntid. %tid.PTX ISA Version 2.u16 %r2.u32 %tid.0. %tid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. mov.sreg . // CTA shape vector // CTA dimensions A predefined. per-thread special register initialized with the thread identifier within the CTA. %tid component values range from 0 through %ntid–1 in each CTA dimension.z PTX ISA Notes Introduced in PTX ISA version 1. mad. or 3D vector to match the CTA shape.0.u16 %rh. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.%tid.z to %r2 Table 113.v4 .z.y == %tid. Redefined as .0.%h2.sreg .x.u32 %ntid.u32 %r0. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. // thread id vector // thread id components A predefined.

u32 %nwarpid.3.u32 %r. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %r. Note that %warpid is volatile and returns the location of a thread at the moment when read.0. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. .u32 %warpid. Introduced in PTX ISA version 1. mov. Special Registers Table 114. The lane identifier ranges from zero to WARP_SZ-1. The warp identifier will be the same for all threads within a single warp. A predefined. mov.g. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Introduced in PTX ISA version 1. . mov. Supported on all target architectures.Chapter 9. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. read-only special register that returns the thread’s warp identifier. 2010 151 .sreg . %nwarpid requires sm_20 or later. A predefined. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. %warpid. For this reason. Supported on all target architectures. . but its value may change during execution. read-only special register that returns the thread’s lane within the warp. Introduced in PTX ISA version 2. PTX ISA Notes Target ISA Notes Examples Table 116. A predefined.u32 %r.sreg . Table 115. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. read-only special register that returns the maximum number of warp identifiers. January 24. %nwarpid. e. due to rescheduling of threads following preemption. %laneid.3.u32 %laneid.sreg .

The %ctaid special register contains a 1D.x. The fourth element is unused and always returns zero. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.x 0 <= %ctaid.0.0.sreg . It is guaranteed that: 1 <= %nctaid.%ctaid. Redefined as . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. depending on the shape and rank of the CTA grid.y.z < %nctaid.y.v4. %rh.u32 type in PTX 2.y 0 <= %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.u32 mov.sreg . read-only special register initialized with the number of CTAs in each grid dimension.x code Target ISA Notes Examples Table 118.u16 %r0. The fourth element is unused and always returns zero.y.z.z} < 65. // CTA id vector // CTA id components A predefined. mov.u32 mov.v4 .%nctaid.u32 %ctaid. Supported on all target architectures.x.u32 %nctaid .x.z.%nctaid.y. // Grid shape vector // Grid dimensions A predefined. %rh.z PTX ISA Notes Introduced in PTX ISA version 1. 2010 . . read-only special register initialized with the CTA identifier within the CTA grid.PTX ISA Version 2. or 3D vector.%nctaid. with each element having a value of at least 1.536 PTX ISA Notes Introduced in PTX ISA version 1.%nctaid.v4 . Redefined as .x.0.sreg .u32 %ctaid. 2D. mov. Each vector element value is >= 0 and < 65535.sreg .0 Table 117.x. . .y < %nctaid.{x.0. It is guaranteed that: 0 <= %ctaid.%ctaid. // legacy PTX 1. The %nctaid special register contains a 3D grid shape vector.x code Target ISA Notes Examples 152 January 24.v4.u32 type in PTX 2. %ctaid. // legacy PTX 1.u16 %r0.u32 %nctaid. %ctaid.x < %nctaid. Supported on all target architectures.

u32 %r. e.Chapter 9. The SM identifier numbering is not guaranteed to be contiguous.u32 %smid. repeated launches of programs may occur. read-only special register that returns the maximum number of SM identifiers. This variable provides the temporal grid launch number for this context.sreg . %nsmid requires sm_20 or later. mov.u32 %gridid. Introduced in PTX ISA version 2.u32 %nsmid. %gridid. . PTX ISA Notes Target ISA Notes Examples Table 121. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. due to rescheduling of threads following preemption. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. but its value may change during execution.0. Special Registers Table 119.3.0. Note that %smid is volatile and returns the location of a thread at the moment when read. . so %nsmid may be larger than the physical number of SMs in the device. During execution. A predefined. Supported on all target architectures. The SM identifier ranges from 0 to %nsmid-1. PTX ISA Notes Target ISA Notes Examples January 24. where each launch starts a grid-of-CTAs. read-only special register initialized with the per-grid temporal grid identifier. . mov. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. // initialized at grid launch A predefined. Supported on all target architectures. A predefined.sreg .u32 %r. Introduced in PTX ISA version 1.sreg . read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. %nsmid. Notes PTX ISA Notes Target ISA Notes Examples Table 120. The SM identifier numbering is not guaranteed to be contiguous. 2010 153 . mov.g. Introduced in PTX ISA version 1.u32 %r. %smid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.

%lanemask_eq requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. mov. mov. %lanemask_le. A predefined. Introduced in PTX ISA version 2.u32 %r. %lanemask_eq.sreg . Introduced in PTX ISA version 2. 154 January 24. .0 Table 122.PTX ISA Version 2.u32 %r.u32 %lanemask_eq.sreg .u32 %r.0. %lanemask_lt requires sm_20 or later. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_lt. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %lanemask_lt.u32 %lanemask_le. A predefined. . Table 124. . %lanemask_le requires sm_20 or later. mov. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg .0.0. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. A predefined. Table 123. 2010 .

Introduced in PTX ISA version 2. %lanemask_ge requires sm_20 or later. . %lanemask_gt. mov.Chapter 9. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg .0.u32 %r. Introduced in PTX ISA version 2. mov.u32 %r. %lanemask_gt requires sm_20 or later. %lanemask_ge. .u32 %lanemask_ge.sreg . read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. 2010 155 . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. January 24.0. A predefined. Table 126.u32 %lanemask_gt. Special Registers Table 125. A predefined.

156 January 24. Supported on all target architectures. Supported on all target architectures.sreg . Special Registers: %pm0. mov. read-only 64-bit unsigned cycle counter. Introduced in PTX ISA version 1. %pm3. %pm3 %pm0. Introduced in PTX ISA version 1.sreg .u32 %clock.%clock.u64 r1. .u64 %clock64. Special registers %pm0. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm1. Introduced in PTX ISA version 2. read-only 32-bit unsigned cycle counter.PTX ISA Version 2.u32 r1. %pm2. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm2. and %pm3 are unsigned 32-bit read-only performance monitor counters. The lower 32-bits of %clock64 are identical to %clock.0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u32 r1. %pm2.u32 %pm0. %clock64 requires sm_20 or later. . ….sreg . Table 128. mov.%clock64.0 Table 127. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Their behavior is currently undefined.%pm0. .3. Table 129.0. %pm1. 2010 . mov. %pm1.

PTX File Directives: .version directives are allowed provided they match the original .version .version 1.version directive. .4 January 24.1. and the target architecture for which the code was generated.0 . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.target Table 130. Supported on all target architectures.version Syntax Description Semantics PTX version number.version .minor // major. 2010 157 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.version directive. . minor are integers Specifies the PTX language version number. .version major.version 2. Increments to the major number indicate incompatible changes to PTX. Duplicate .Chapter 10. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. Directives 10. Each ptx file must begin with a .

PTX ISA Version 2.f64 instructions used. PTX features are checked against the specified target architecture. Supported on all target architectures.samplerref descriptors. PTX File Directives: . Introduced in PTX ISA version 1. vote instructions. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.texref and . 2010 .red}.texmode_independent texture and sampler information is bound together and accessed via a single . Adds {atom. with only half being used by instructions converted from . and an error is generated if an unsupported feature is used. 64-bit {atom.global. In general. A program with multiple .target directive containing a target architecture and optional platform options. Requires map_f64_to_f32 if any .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. sm_10. generations of SM architectures follow an “onion layer” model. map_f64_to_f32 }.red}. .f64 instructions used. Disallows use of map_f64_to_f32. sm_13.f64 instructions used. Adds double-precision support.0.5. Texturing mode: (default is .f64 to . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.target directives can be used to change the set of target features allowed during parsing.target .target Syntax Architecture and Platform target. texture and sampler information is referenced with independent . sm_11. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.f64 storage remains as 64-bits. Each PTX file must begin with a . A .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.texmode_unified . sm_12.shared. Description Specifies the set of features in the target architecture for which the current ptx code was generated.f32.texref descriptor. texmode_independent.target directive specifies a single target architecture. Target sm_20 Description Baseline feature set for sm_20 architecture.0 Table 131. Texturing mode introduced in PTX ISA version 1. immediately followed by a . Adds {atom. but subsequent .texmode_unified) . PTX code generated for a given target can be run on later generation devices.red}. 158 January 24. texmode_unified. Note that . including expanded rounding modifiers. brkpt instructions. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Requires map_f64_to_f32 if any .global. Requires map_f64_to_f32 if any .version directive. Therefore. The texturing mode is specified for an entire module and cannot be changed within the module. The following table summarizes the features in PTX that vary according to target architecture. where each generation adds new features and retains all features of previous generations.

Chapter 10. 2010 159 .target sm_10 // baseline target architecture . Directives Examples .target sm_20. texmode_independent January 24.target sm_13 // supports double-precision .

func Table 132. Semantics Specify the entry point for a kernel program. ld.2. opaque . Supported on all target architectures. The shape and size of the CTA executing the kernel are available in special registers. PTX ISA Notes For PTX ISA version 1.param instructions.param. Parameters may be referenced by name within the kernel body and loaded into registers using ld. [y]. parameters.b32 x.param instructions. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. .b32 %r3. ld. In addition to normal parameters. with optional parameters.b32 y.entry kernel-name ( param-list ) kernel-body . .0 through 1. [z].entry .b32 z ) Target ISA Notes Examples [x]. parameter variables are declared in the kernel body.entry cta_fft .5 and later. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. .0 through 1.entry kernel-name kernel-body Defines a kernel entry point name. ld.b32 %r<99>.entry . 2010 . . the kernel dimensions and properties are established and made available via special registers.param { . parameter variables are declared in the kernel parameter list. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. Kernel and Function Directives: . Parameters are passed via .param .3. 160 January 24. .PTX ISA Version 2. These parameters can only be referenced by name within texture and surface load.samplerref.4 and later.reg .entry filter ( .4.param . store. %nctaid.param space memory and are listed within an optional parenthesized parameter list.param. and .texref.b32 %r2. %ntid.surfref variables may be passed as parameters.g.0 10.param.b32 %r1. .entry Syntax Description Kernel entry point and body. e. and query instructions and cannot be accessed via ld. At kernel launch. For PTX ISA versions 1. and body for the kernel function. … } . etc.

Variadic functions are currently unimplemented.reg .b32 N.reg . A . ret. Kernel and Function Directives: . Variadic functions are represented using ellipsis following the last fixed argument. mov.b32 rval) foo (. foo. Parameters in register state space may be referenced directly within instructions in the function body. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. PTX ISA 2. which may use a combination of registers and stack locations to pass parameters. and recursion is illegal.func (ret-param) fname (param-list) function-body Defines a function.Chapter 10.func (.0 with target sm_20 allows parameters in the .param and st. parameters must be in the register state space. Release Notes For PTX ISA version 1. . implements an ABI with stack.func Syntax Function definition. if any. PTX 2. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. } … call (fooval). . . Directives Table 133.0 with target sm_20 supports at most one return value. there is no stack.reg .0. val1).result.f64 dbl) { . other code. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The parameter lists define locally-scoped variables in the function body.param state space. The implementation of parameter passing is left to the optimizing translator.func fname function-body .reg . 2010 161 .func . … Description // return value in fooval January 24. and supports recursion. Parameters in .b32 localVar. including input and return parameters and optional function body.func definition with no body provides a function prototype.func fname (param-list) function-body . Parameters must be base types in either the register or parameter state space.param instructions in the body.param space are accessed using ld. Parameter passing is call-by-value. … use N. dbl.x code.b32 rval.2 for a description of variadic functions. (val0.

registers) to increase total thread count and provide a greater opportunity to hide memory latency. The interpretation of .0 10.minnctapersm . A general .entry directive and its body.g.3. . and the .pragma directives may appear at module (file) scope. for example. the .maxnreg .maxntid. PTX supports the following directives. which pass information to the backend optimizing compiler.pragma directive is supported for passing information to the PTX backend.maxnreg.maxnctapersm (deprecated) .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxntid .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. Currently. . at entry-scope. and . Note that . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. 162 January 24.PTX ISA Version 2.minnctapersm directives may be applied per-entry and must appear between an . The directives take precedence over any module-level constraints passed to the optimizing backend. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. The directive passes a list of strings to the backend.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). the . or as statements within a kernel or device function body.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.maxntid and . The . and the strings have no semantics within the PTX virtual machine model.maxntid directive specifies the maximum number of threads in a thread block (CTA). to throttle the resource requirements (e. 2010 . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. These can be used.pragma The .

The maximum number of threads is the product of the maximum extent in each dimension.entry foo .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Supported on all target architectures. 2010 163 .entry foo . . ny.maxntid 256 . The compiler guarantees that this limit will not be exceeded.maxntid and . Introduced in PTX ISA version 1.maxnreg . 2D.maxntid Syntax Maximum number of threads in thread block (CTA). The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. .3.maxnreg n Declare the maximum number of registers per thread in a CTA.16.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. This maximum is specified by giving the maximum extent of each dimention of the 1D. for example. The actual number of registers used may be less. Supported on all target architectures. .maxntid 16. or the maximum number of registers may be further constrained by . Performance-Tuning Directives: . or 3D CTA.entry bar . Directives Table 134.Chapter 10.maxntid nx .maxntid nx. Exceeding any of these limits results in a runtime error or kernel launch failure.maxctapersm.maxntid nx.3. . Performance-Tuning Directives: .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. the backend may be able to compile to fewer registers.maxntid . nz Declare the maximum number of threads in the thread block (CTA). ny . Introduced in PTX ISA version 1.

maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm 4 { … } 164 January 24.minnctapersm in PTX ISA version 2.minnctapersm generally need . .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid to be specified as well. .maxntid to be specified as well.maxntid and . .0 Table 136. .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.0.maxnctapersm generally need . Optimizations based on . Supported on all target architectures. Optimizations based on .maxntid 256 .maxntid 256 .0. Deprecated in PTX ISA version 2.minnctapersm . However. 2010 . Introduced in PTX ISA version 2.maxnctapersm (deprecated) . Performance-Tuning Directives: .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0 as a replacement for . .entry foo . For this reason. Performance-Tuning Directives: . Supported on all target architectures.entry foo .maxnctapersm has been renamed to . if the number of registers used by the backend is sufficiently lower than this bound.PTX ISA Version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.3. The optimizing backend compiler uses . additional CTAs may be mapped to a single multiprocessor.maxnctapersm. Introduced in PTX ISA version 1.

pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma “nounroll”. 2010 165 . .pragma directive may occur at module-scope. Performance-Tuning Directives: . { … } January 24.pragma Syntax Description Pass directives to PTX backend compiler. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . or at statementlevel. entry-scoped. The .pragma list-of-strings .Chapter 10. Introduced in PTX ISA version 2. Supported on all target architectures.entry foo .pragma . Directives Table 138.0.pragma directive strings is implementation-specific and has no impact on PTX semantics. Pass module-scoped. or statement-level directives to the PTX backend compiler. The interpretation of . . at entry-scope.

debug_pubnames.4byte label .file . “”. 0x00 .section .byte byte-list // comma-separated hexadecimal byte values . Supported on all target architectures.section directive is new in PTX ISA verison 2. 0x00 166 January 24.4byte int32-list // comma-separated hexadecimal integers in range [0.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.4byte .quad int64-list // comma-separated hexadecimal integers in range [0.section directive.4byte 0x6e69616d. 0x00. Table 139.section . 0x6150736f.0 10.. 2010 . The @@DWARF syntax is deprecated as of PTX version 2.0 but is supported for legacy PTX version 1.0 and replaces the @@DWARF syntax.4byte 0x000006b5. 0x02. 0x00. 0x00.0. Introduced in PTX ISA version 1. 0x63613031.byte 0x00. Deprecated as of PTX 2. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .PTX ISA Version 2.loc The .4. 0x61395a5f.debug_info . 0x736d6172 . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. replaced by .232-1] .x code. 0x00000364. 0x00. 0x5f736f63 .byte 0x2b. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .. @progbits . @@DWARF dwarf-string dwarf-string may have one of the . 0x00. 0x00.2.264-1] .

replaces @@DWARF syntax.. . .section . 0x736d6172 0x00 Table 141.232-1] . Debugging Directives: .264-1] .b64 int64-list // comma-separated list of integers in range [0.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } 0x02. 0x00.255] .section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00. Debugging Directives: . Directives Table 140.debug_pubnames { .section Syntax PTX section definition. 0x00. 2010 167 . . Source file information. Debugging Directives: . 0x00 0x61395a5f. 0x00. 0x00.0.0. 0x63613031.b8 byte-list // comma-separated list of integers in range [0. 0x00.b32 .b8 0x2b. . .0. Source file location.loc line_number January 24.Chapter 10. Supported on all target architectures. 0x00000364. .file .b8 0x00.section .b32 label .. Supported on all target architectures.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.loc .b32 0x000006b5..file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 int32-list // comma-separated list of integers in range [0.b32 0x6e69616d. Supported on all target architectures. .debug_info .file filename Table 142. 0x5f736f63 0x6150736f.

visible identifier Declares identifier to be externally visible.PTX ISA Version 2.0 10. Linking Directives: . Supported on all target architectures. // foo will be externally visible 168 January 24.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.global . Supported on all target architectures. 2010 . Introduced in PTX ISA version 1.visible .b32 foo.6. . Introduced in PTX ISA version 1. . Linking Directives .visible .global .extern . . Linking Directives: . // foo is defined in another module Table 144.visible Table 143.0.extern identifier Declares identifier to be defined externally.0.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern .b32 foo.extern . .

and the remaining sections provide a record of changes in previous releases.0.3 driver r190 CUDA 3.0 driver r195 PTX ISA Version PTX ISA 1.0 January 24.2 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.1 CUDA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2. 2010 169 .3 PTX ISA 1.1 PTX ISA 1.1 CUDA 2.5 PTX ISA 2.0 CUDA 2.2 PTX ISA 1. CUDA Release CUDA 1. The release history is as follows.Chapter 11.0 PTX ISA 1.4 PTX ISA 1.0 CUDA 1.

ftz and .sat modifiers. The .f32.x code and sm_1x targets.1. The fma. The changes from PTX ISA 1. A single-precision fused multiply-add (fma) instruction has been added. Single-precision add.f32 and mad. rcp. Single.1. New Features 11.ftz modifier may be used to enforce backward compatibility with sm_1x. and mul now support . These are indicated by the use of a rounding modifier and require sm_20. Instructions testp and copysign have been added.1.f32 instruction also supports . The mad.f32 maps to fma. fma. mad.rm and . When code compiled for sm_1x is executed on sm_20 devices.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. 2010 . The goal is to achieve IEEE 754 compliance wherever possible.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.rp rounding modifiers for sm_20 targets.1.f32 requires sm_20.0 for sm_20 targets.0 11.PTX ISA Version 2. while maximizing backward compatibility with legacy PTX 1. and sqrt with IEEE 754 compliant rounding have been added.rn.and double-precision div. Both fma.1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. sub. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 require a rounding modifier for sm_20 targets. • • • • • 170 January 24.f32 for sm_20 targets. Changes in Version 2. The mad. Floating-Point Extensions This section describes the floating-point changes in PTX 2.1.0 11.

1. membar. has been added.minnctapersm to better match its behavior and usage. Instructions {atom.Chapter 11. Instructions bar. bfind.ballot. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.pred have been added. A “vote ballot” instruction. Cache operations have been added to instructions ld.sys.zero. %clock64. %lanemask_{eq. Video instructions (includes prmt) have been added.arrive instruction has been added. for prefetching to specified level of memory hierarchy.1. suld.section.f32 have been implemented. A “bit reversal” instruction. st. st.maxnctapersm directive was deprecated and replaced with .le. bar now supports optional thread count and register operands. Instruction sust now supports formatted surface stores. atom. has been added.gt} have been added. A “population count” instruction.{and. brev. January 24. and red now support generic addressing. have been added.lt.add.1.1.b32. prefetch. A system-level membar instruction. New special registers %nsmid. The .red}. 2010 171 . Surface instructions support additional . and shared addresses to generic address and vice-versa has been added. Release Notes 11. The bar instruction has been extended as follows: • • • A bar. has been added.3.shared have been extended to handle 64-bit data types for sm_20 targets.red}. . cvta. prefetchu. has been added.u32 and bar. clz. . vote. A “count leading zeros” instruction. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. popc. ldu. Instructions prefetch and prefetchu have also been added.2. New instructions A “load uniform” instruction.clamp modifiers. A new directive.g. Other new features Instructions ld.popc.or}. Bit field extract and insert instructions. A “find leading non-sign bit” instruction. bfe and bfi. has been added. isspacep.ge. has been added. Instruction cvta for converting global. Instructions {atom. local. has been added.red. e. and sust. ldu.red. 11.clamp and .

ftz (and cvt for . Formatted surface store with .target sm_1x.4 and earlier. 172 January 24.1. where . 2010 .p sust. or . the correct number is sixteen. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.0 11. The underlying.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. .red}.5.u32.s32. Instruction bra.version is 1. {atom.4 or earlier. To maintain compatibility with legacy PTX code.f32} atom. Formatted surface load is unimplemented. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.p. Support for variadic functions and alloca are unimplemented.2.1.s32. call suld.{u32.3. In PTX version 1.max} are not implemented. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. 11. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. cvt. stack-based ABI is unimplemented. has been fixed.5 and later. Semantic Changes and Clarifications The errata in cvt.f32 type is unimplemented.{min. if . Unimplemented Features Remaining The following table summarizes unimplemented instruction features.f32. See individual instruction descriptions for details.ftz for PTX ISA versions 1.PTX ISA Version 2.

The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. … @p bra L1_end.pragma “nounroll”. Table 145. Note that in order to have the desired effect at statement level. and statement levels. Ignored for sm_1x targets.pragma “nounroll”.func bar (…) { … L1_head: . disables unrolling of0 the loop for which the current block is the loop header. Supported only for sm_20 targets. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . Descriptions of .pragma “nounroll”. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. L1_end: … } // do not unroll this loop January 24. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. including loops preceding the .pragma. { … } // do not unroll any loop in this function . disables unrolling for all loops in the entry function body. L1_body: … L1_continue: bra L1_head.0. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. The “nounroll” pragma is allowed at module. 2010 173 . entry-function.pragma Strings This section describes the .entry foo (…) . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma strings defined by ptxas.Appendix A. .

0 174 January 24.PTX ISA Version 2. 2010 .

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