NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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...............4...2.......6....3....... 6...........................................1.4.............................2....4............................................ 27 Register State Space ........................... 41 Source Operands.............................................3.3.....1............................ Abstracting the ABI ......................................5..........4.......................... Type Conversion... 5.................................. 25 Chapter 5...... 5..................2......1...........................................................1.............. Texture.................................................................................................................................. 43 6..................... 5................. 6............................. Types.........................2........................ 30 Shared State Space... 6.................................. 5..................... 33 Restricted Use of Sub-Word Sizes ...... and Variables ............................. 37 Variable Declarations ...... 5... 38 Initializers ............................................. Instruction Operands.......................... Function declarations and definitions .......6.... State Spaces.................................1......................................... 33 Fundamental Types ...................................................................................................................................5............ 39 5.... 5..................... 32 Texture State Space (deprecated) ..................... 5........................ 5....................................... Operand Costs ............2.............................. Sampler.................. State Spaces ... 41 Using Addresses.............4....................3.5.... 39 Parameterized Variable Names ........................... 42 Addresses as Operands ..........................5.............................. and Vectors ...................................4....................................................1..............2.......... 5.....4................................................PTX ISA Version 2.................. 6............1.....................................................................................4....... 44 Rounding Modifiers ......... 5...........................................1..............................1....................1.........3.......... 6.................................................................................1............................................................... Types ................ 29 Global State Space ........ 47 Chapter 7.. 49 ii January 24...........................1........... 42 Arrays as Operands .............. 34 Variables ............. 41 6. 49 7.....1.............................................................................. 28 Special Register State Space .................... 38 Alignment .......................................................... 37 Vectors ............................... 5..............4....... Chapter 6...........................4...................................................6...... 6....... 6............5..................................... and Surface Types ..........................................4................................6..... 5......4........... 33 5........................................... 5.....1................................ Arrays... 32 5.... 5................... Operand Type Information ............................................................................................................0 4.......................................................................................4..2.................... 43 Labels and Function Names as Operands .... 2010 ............................... 5.......2.......................... 41 Destination Operands ..................... 37 Array Declarations ......... 46 6................... 44 Scalar Conversions ............... 6....................................................................5...... Summary of Constant Expression Evaluation Rules ......................... 43 Vectors as Operands ............................... 27 5....................1..........................................................................4............ 6.....................................................................8................2................................ 29 Parameter State Space .................7........................... 28 Constant State Space ............................ 5....................................1................. 29 Local State Space ......4..............................................

..........3............... 8.................4.......... 8........................................... PTX Version and Target Directives ..................1.............1....................... 166 Linking Directives .......... 169 11................................... 172 Unimplemented Features Remaining .............3..............................6.........7...................................... 58 8..........3................................. Format and Semantics of Instruction Descriptions ................................. Divergence of Threads in Control Constructs .......................7................................. Changes from PTX 1.......5..................9....................................1..................1................. 10....2........ 8................8............................................................................................ 62 8............................................ 157 Specifying Kernel Entry Points and Functions .............. 8.......................6.................... 104 Data Movement and Conversion Instructions ................. 168 Chapter 11..........2...........................................................1................ 59 Operand Size Exceeding Instruction-Type Size .............................................................................. 7.................... Instruction Set ..................7......................................................................... 57 Manipulating Predicates ...2........ Release Notes ............7........................ 52 Variadic functions .1........1...........1.....x ............................................4........... 10..............................2................. 56 Comparisons ..... 2010 iii ......... 8........................................................1........................... 147 8....................................... 60 8..................................... 62 Semantics ........... 11......................3.............................. 8....................3..........................................7......................... 162 Debugging Directives ...................................... 8................................ 8.......................... 63 Floating-Point Instructions .............. 10......................................................... 55 8...........................7...........................7.............................. 149 Chapter 10....................0 ..2.......1........... 108 Texture and Surface Instructions .............4......7. 8.............. 7.. 54 Chapter 8.............................................. Chapter 9.................................................. 11...................... 81 Comparison and Selection Instructions ................. 55 PTX Instructions ................................................ 63 Integer Arithmetic Instructions ....................................7.....................7..............................................7...............3.....5.............................. 170 New Features ... 172 January 24....1................................2............. Changes in Version 2............... Instructions .................6....... Type Information for Instructions and Operands ............ 157 10....1.................................. 170 Semantic Changes and Clarifications ....... 8.................... 8.............. 129 Parallel Synchronization and Communication Instructions ..7.. 55 Predicated Execution ..................................... 8....... 8...................... Special Registers ................. 140 Miscellaneous Instructions................................................6............ 160 Performance-Tuning Directives ....... 132 Video Instructions ................................................7......................... Directives ............................................................................ 8..................4.............................................. 8.................................................................10...................................... 100 Logic and Shift Instructions ................ 122 Control Flow Instructions .......................................................... 11................................................ 8.............. 10....................................................... 62 Machine-Specific Semantics of 16-bit Code .......................................................3........... 53 Alloca ..................................................1......................

....pragma Strings...0 Appendix A.................................. 173 iv January 24.........PTX ISA Version 2... 2010 ..... Descriptions of ..........

............................ 25 State Spaces ......... 46 Cost Estimates for Accessing State-Spaces .......................................... Table 22.. 19 Predefined Identifiers ........... Table 15.................................... Table 6...................................................... Table 10................. 18 Reserved Instruction Keywords ........................................... Table 2... Table 30.............. 65 Integer Arithmetic Instructions: sub......... 66 Integer Arithmetic Instructions: subc ............................................................. and Bit-Size Types ............. 35 Opaque Type Fields in Independent Texture Mode ............................ 35 Convert Instruction Precision and Format ................ 67 Integer Arithmetic Instructions: mad .............................................. 61 Integer Arithmetic Instructions: add ........................................................................................................................................................ Table 26........... Table 27........................List of Tables Table 1................................................................................ Table 23............. Table 32................................................................... 46 Integer Rounding Modifiers .. Table 9.................. Table 19............................................. 71 January 24.............................. Table 3.............................................................................................. 65 Integer Arithmetic Instructions: addc ............................................................................... 66 Integer Arithmetic Instructions: mul ............................................ 64 Integer Arithmetic Instructions: sub ............................................ 33 Opaque Type Fields in Unified Texture Mode ........ 2010 v ............................ 60 Relaxed Type-checking Rules for Destination Operands.................................................................................. Table 14............... PTX Directives ........... 57 Floating-Point Comparison Operators Accepting NaN .......... Table 20........... 59 Relaxed Type-checking Rules for Source Operands ................cc ...... 47 Operators for Signed Integer....... 27 Properties of State Spaces ............. Table 17.............. 58 Type Checking Rules ................................................................................................. 20 Operator Precedence ...... 68 Integer Arithmetic Instructions: mul24 ........ Table 24.. Table 7................................................... Table 8............... Unsigned Integer............ Table 4..................... 23 Constant Expression Evaluation Rules .......... Table 21. Table 12.......cc .................... 28 Fundamental Type Specifiers ............................................................................................................................................................................................ 45 Floating-Point Rounding Modifiers .......................................... Table 5... Table 18. Table 25.............. Table 16........................ 69 Integer Arithmetic Instructions: mad24 ....................................................... Table 13....................................................................................................................................................................................................................................................... Table 28........... Table 29. 58 Floating-Point Comparison Operators Testing for NaN ....................... Table 31. Table 11................... 70 Integer Arithmetic Instructions: sad ................................. 64 Integer Arithmetic Instructions: add.............. 57 Floating-Point Comparison Operators ................................................

...... Table 38............. 86 Floating-Point Instructions: fma ..................................................................................... Table 47.................................................................................... 94 Floating-Point Instructions: rsqrt ................................. 76 Integer Arithmetic Instructions: bfe ........................................ 88 Floating-Point Instructions: div .............................. 103 Comparison and Selection Instructions: slct ........................ 90 Floating-Point Instructions: abs .......................................................................................................................................................................................................... 97 Floating-Point Instructions: lg2 ....................................................... 91 Floating-Point Instructions: neg ...................................... Table 56................. Table 65........ 87 Floating-Point Instructions: mad ..................... Table 51....................................................................... Table 62...................... Table 52............................................................. Integer Arithmetic Instructions: div ............................................ Table 67............ 102 Comparison and Selection Instructions: selp ............................................ Table 60.... 84 Floating-Point Instructions: sub .......................................................................................................... 72 Integer Arithmetic Instructions: neg .. 98 Floating-Point Instructions: ex2 ............... Table 37................................ Table 43............................... Table 41............ Table 35................................................... 83 Floating-Point Instructions: add ................................PTX ISA Version 2................................................................ Table 64....... 103 vi January 24........... 92 Floating-Point Instructions: rcp ........... 96 Floating-Point Instructions: cos .............................................................................................. 75 Integer Arithmetic Instructions: brev ................ Table 46........................................................................................ Table 36............. 101 Comparison and Selection Instructions: setp .......................... Table 57................................................. 77 Integer Arithmetic Instructions: bfi ............. 71 Integer Arithmetic Instructions: rem ...................... Table 53.................... Table 45............. 99 Comparison and Selection Instructions: set .............................................. Table 42........... 92 Floating-Point Instructions: max ........ Table 40........................................................... 71 Integer Arithmetic Instructions: abs .............................. Table 39........................................ 2010 ... 72 Integer Arithmetic Instructions: min ...................................................... 73 Integer Arithmetic Instructions: popc ........................ 74 Integer Arithmetic Instructions: clz .... Table 58.......................................... 85 Floating-Point Instructions: mul ........................ Table 48............................................ 74 Integer Arithmetic Instructions: bfind ....... Table 54........ 78 Integer Arithmetic Instructions: prmt ................................... 82 Floating-Point Instructions: testp .................... Table 44.......................... 95 Floating-Point Instructions: sin .... 83 Floating-Point Instructions: copysign . Table 34................................................................................ 73 Integer Arithmetic Instructions: max ........................................................... 93 Floating-Point Instructions: sqrt ........................................ Table 69................................... Table 55.......... Table 63....................................................................................................................................................... Table 61.. Table 66............................................................. 79 Summary of Floating-Point Instructions .....0 Table 33..................... 91 Floating-Point Instructions: min .......... Table 49................................................................. Table 68..................................... Table 59..................................................................................... Table 50...................

..... 107 Logic and Shift Instructions: shr .. 118 Data Movement and Conversion Instructions: isspacep .......... 113 Data Movement and Conversion Instructions: ldu ........................................................ Table 90.... 110 Data Movement and Conversion Instructions: mov ................... Table 96....... 123 Texture and Surface Instructions: txq ....... 111 Data Movement and Conversion Instructions: mov ................... vshr ................................................................ Table 71............... 129 Control Flow Instructions: @ ............ Table 81................ vmax ............................................................................................................... vsub......... 109 Cache Operators for Memory Store Instructions ................. Table 86........................................................................................ Table 93........... 126 Texture and Surface Instructions: sured.................. Table 84......... 119 Data Movement and Conversion Instructions: cvt .................... Table 104... 125 Texture and Surface Instructions: sust .......Table 70...................................................... Table 76..................... Table 94.............................. Table 82....... 143 January 24................ prefetchu .............................................. 105 Logic and Shift Instructions: or ................. Table 75................. Table 100.............. 115 Data Movement and Conversion Instructions: st ................ Table 102... Table 103................................................................ 130 Control Flow Instructions: ret .................. 106 Logic and Shift Instructions: not .. 142 Video Instructions: vshl.................................. vabsdiff.... 128 Control Flow Instructions: { } ........................ Table 105.................... 131 Control Flow Instructions: exit .................................................... 119 Data Movement and Conversion Instructions: cvta .. Table 79............. 137 Parallel Synchronization and Communication Instructions: vote .............................................................................................................................................................. Table 77....................................... Table 95....... 2010 vii ....... Table 87..... 106 Logic and Shift Instructions: shl .......................... Table 106............... 105 Logic and Shift Instructions: xor .............. Table 73.................... 112 Data Movement and Conversion Instructions: ld ..... Table 99......................... Table 101................................. Table 83........................................... Logic and Shift Instructions: and .............................................. Table 98. Table 74............................................................................................ Table 85. 131 Parallel Synchronization and Communication Instructions: bar .... 124 Texture and Surface Instructions: suld .................................. vmin........ Table 80........ 129 Control Flow Instructions: bra ............. 134 Parallel Synchronization and Communication Instructions: atom ............... 127 Texture and Surface Instructions: suq . 106 Logic and Shift Instructions: cnot ............................................. Table 89............. 107 Cache Operators for Memory Load Instructions .......................................................................................... Table 92............ Table 97...................... Table 91. 139 Video Instructions: vadd....................................... 130 Control Flow Instructions: call ............................................... 133 Parallel Synchronization and Communication Instructions: membar .......................................... Table 78............................................. Table 88................................................................ 120 Texture and Surface Instructions: tex ......................................... 116 Data Movement and Conversion Instructions: prefetch........................................................................................ Table 72............................................. 135 Parallel Synchronization and Communication Instructions: red ............

........... 167 Debugging Directives: ...........maxntid ...................................................pragma ................................... Table 120.....................section ........................................................ 153 Special Registers: %nsmid .............................................................................................................................................................. Table 135................. Table 123.................................. %pm2..... 160 Kernel and Function Directives: .................... Table 142...... Table 130.................................................................. 166 Debugging Directives: ......PTX ISA Version 2........... Table 124........extern............................... 150 Special Registers: %ntid ............... Table 140........................................file ...... 146 Miscellaneous Instructions: trap ...................................... Table 119........................ Table 141................................................................................ 154 Special Registers: %lanemask_le ....................................................... 154 Special Registers: %lanemask_ge ............... Table 108........loc ........ 157 PTX File Directives: ................................................................................................minnctapersm .......... 161 Performance-Tuning Directives: . 153 Special Registers: %gridid ...................................... Table 139....maxnctapersm (deprecated) ....................... 151 Special Registers: %ctaid ........................ Table 131........ 165 Debugging Directives: @@DWARF ................. 156 PTX File Directives: ........................... Table 126............. Table 138................................... Table 128....... %pm1......................................................................................... Table 134................................................ Table 114............... Table 121.........................................................maxnreg ................................ 147 Miscellaneous Instructions: pmevent............ 156 Special Registers: %clock64 ........ 155 Special Registers: %lanemask_gt ........................................... 167 Linking Directives: ..................... 168 viii January 24......... 144 Video Instructions: vset.................. 154 Special Registers: %lanemask_lt ................................................. 151 Special Registers: %warpid ................................ Table 112....................................... Table 118...................................................................................... 147 Special Registers: %tid .........0 Table 107.................. 164 Performance-Tuning Directives: ............................. 152 Special Registers: %nctaid ................................................................................... 164 Performance-Tuning Directives: ......................... 151 Special Registers: %nwarpid ..................... 152 Special Registers: %smid .. 2010 ........................... 156 Special Registers: %pm0. Table 137..............target .... Table 109....................version........ Table 117........................................... Table 127................... Video Instructions: vmad ...................... Table 111.............................. %pm3 ........................................................................................................................................................... Table 113.............. Table 136.............................. 167 Debugging Directives: ...... 158 Kernel and Function Directives: ...... Table 122. 155 Special Registers: %clock .................. 163 Performance-Tuning Directives: ....... Table 115..................................................func .............. 150 Special Registers: %laneid ...... Table 133......................................... 153 Special Registers: %lanemask_eq ................................................................ Table 110.............................................. 163 Performance-Tuning Directives: ..........................entry....... Table 143..................... Table 116............. 147 Miscellaneous Instructions: brkpt ............ Table 129........................................................................................ Table 125................................ Table 132...........

....... 168 Pragma Strings: “nounroll” ..................................... 173 January 24............................. 2010 ix ... Table 145..... Linking Directives: ..........................visible...............................................................Table 144.

PTX ISA Version 2. 2010 .0 x January 24.

and because it is executed on many data elements and has high arithmetic intensity. 2010 1 . PTX exposes the GPU as a data-parallel computing device. PTX defines a virtual machine and ISA for general purpose parallel thread execution. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. the programmable GPU has evolved into a highly parallel. stereo vision. Because the same program is executed for each data element. 1. from general signal processing or physics simulation to computational finance or computational biology. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. the memory access latency can be hidden with calculations instead of big data caches. Data-parallel processing maps data elements to parallel processing threads. image scaling. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). which are optimized for and translated to native target-architecture instructions. In fact. PTX programs are translated at install time to the target hardware instruction set. January 24. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. image and media processing applications such as post-processing of rendered images. Similarly. 1. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. high-definition 3D graphics.2. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.Chapter 1.1. many-core processor with tremendous computational horsepower and very high memory bandwidth. multithreaded. there is a lower requirement for sophisticated flow control. Introduction This document describes PTX. and pattern recognition can map image blocks and pixels to parallel processing threads. video encoding and decoding. Many applications that process large data sets can use a data-parallel programming model to speed up the computations.

x features are supported on the new sm_20 target.0 PTX ISA Version 2.x. The main areas of change in PTX 2.x code will continue to run on sm_1x targets as well. Single-precision add. When code compiled for sm_1x is executed on sm_20 devices. Facilitate hand-coding of libraries.f32 for sm_20 targets. and all PTX 1.0 are improved support for IEEE 754 floating-point operations.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.f32 instruction also supports . Provide a common source-level ISA for optimizing code generators and translators. addition of generic addressing to facilitate the use of general-purpose pointers. and video instructions.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Provide a machine-independent ISA for C/C++ and other compilers to target. Legacy PTX 1. The fma.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.ftz and . Instructions marked with . atomic. surface. Most of the new features require a sm_20 target. The mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. fma.sat modifiers.rn.ftz) modifier may be used to enforce backward compatibility with sm_1x. and architecture tests.f32 and mad. Provide a code distribution ISA for application and middleware developers. including integer. PTX ISA Version 2. The changes from PTX ISA 1.f32 requires sm_20. sub. barrier. A “flush-to-zero” (. 2010 . which map PTX to specific target machines.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. A single-precision fused multiply-add (fma) instruction has been added.0 is in improved support for the IEEE 754 floating-point standard.rm and . Improved Floating-Point Support A main area of change in PTX 2. Achieve performance in compiled applications comparable to native GPU performance. 1. • • • 2 January 24. and the introduction of many new instructions.PTX ISA Version 2.1.rp rounding modifiers for sm_20 targets. The mad. PTX 2. Both fma.3. and mul now support . mad.f32 maps to fma. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. memory.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. performance kernels.0 is a superset of PTX 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.3. reduction.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32.f32 require a rounding modifier for sm_20 targets. 1.

2010 3 . for prefetching to specified level of memory hierarchy. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. 1. special registers. ldu. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.and double-precision div. NOTE: The current version of PTX does not implement the underlying. • Taken as a whole. and sust.g. Generic Addressing Another major change is the addition of generic addressing. These are indicated by the use of a rounding modifier and require sm_20. PTX 2.3. and vice versa. New Instructions The following new instructions.. allowing memory instructions to access these spaces without needing to specify the state space.2. Introduction • Single. local.zero. st. isspacep. . January 24.3. stack layout.clamp and . suld. i.3. Support for an Application Binary Interface Rather than expose details of a particular calling convention. stack-based ABI. and Application Binary Interface (ABI). and shared state spaces.0. prefetch. and shared addresses to generic addresses. A new cvta instruction has been added to convert global. local. e. and sqrt with IEEE 754 compliant rounding have been added. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. Instructions testp and copysign have been added. and red now support generic addressing.0. 1. instructions ld. Instructions prefetch and prefetchu have been added.3. an address that is the same across all threads in a warp. and shared addresses to generic address and vice-versa has been added. so recursion is not yet supported. local. these changes bring PTX 2.Chapter 1.4. Cache operations have been added to instructions ld. In PTX 2. cvta. and directives are introduced in PTX 2. atom. rcp. Instruction cvta for converting global. 1. Generic addressing unifies the global.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. prefetchu.e. Surface instructions support additional clamp modifiers.0 closer to full compliance with the IEEE 754 standard. Surface Instructions • • Instruction sust now supports formatted surface stores. st.

f32 have been added. A new directive. bfi bit field extract and insert popc clz Atomic.red}. A bar.le.arrive instruction has been added.red}.ballot.shared have been extended to handle 64-bit data types for sm_20 targets. vote.{and. . membar. has been added.section. New special registers %nsmid. Reduction.add.or}.ge. A “vote ballot” instruction. has been added.red.red.u32 and bar. bar now supports an optional thread count and register operands. Barrier Instructions • • A system-level membar instruction.pred have been added. and Vote Instructions • • • New atomic and reduction instructions {atom.gt} have been added.popc.lt. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. 2010 . %lanemask_{eq. Instructions {atom. %clock64. Other Extensions • • • Video instructions (includes prmt) have been added.b32. 4 January 24.sys.PTX ISA Version 2. Instructions bar.

Chapter 10 lists the assembly directives supported in PTX. Chapter 8 describes the instruction set. Introduction 1. types.4. Chapter 11 provides release notes for PTX Version 2. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 3 gives an overview of the PTX virtual machine model. Chapter 4 describes the basic syntax of the PTX language. January 24. and variable declarations. Chapter 6 describes instruction operands.Chapter 1. Chapter 5 describes state spaces. 2010 5 . calling convention. Chapter 9 lists special registers. Chapter 7 describes the function and call syntax. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.0.

PTX ISA Version 2.0 6 January 24. 2010 .

Each CTA thread uses its thread identifier to determine its assigned role. Cooperative thread arrays (CTAs) implement CUDA thread blocks. compute-intensive portions of applications running on the host are off-loaded onto the device. and results across the threads of the CTA. or 3D CTA. 2. To that effect. or 3D shape specified by a three-element vector ntid (with elements ntid. A cooperative thread array. 2D.z) that specifies the thread’s position within a 1D. The vector ntid specifies the number of threads in each CTA dimension. Each CTA has a 1D. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.1.z).2. It operates as a coprocessor to the main CPU. is an array of threads that execute a kernel concurrently or in parallel. (with elements tid. can be isolated into a kernel function that is executed on the GPU as many different threads. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2D. and tid. assign specific input and output positions. a portion of an application that is executed many times. To coordinate the communication of the threads within the CTA.2. Programs use a data parallel decomposition to partition inputs.y. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. compute addresses. and select work to perform. tid. but independently on different data. or CTA.y. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.x. Programming Model 2. 2010 7 . Each thread has a unique thread identifier within the CTA. 2. The thread identifier is a three-element vector tid. January 24. More precisely. ntid. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.1.Chapter 2. and ntid. or host: In other words.x. Threads within a CTA can communicate with each other. work. data-parallel.

However. %ntid. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). %ctaid. The host issues a succession of kernel invocations to the device. Typically. This comes at the expense of reduced thread communication and synchronization. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 2. Each grid of CTAs has a 1D. which may be used in any instruction where an immediate operand is allowed. so PTX includes a run-time immediate constant. and %gridid. multiple-thread) fashion in groups called warps. Threads within a warp are sequentially numbered. read-only special registers %tid. CTAs that execute the same kernel can be batched together into a grid of CTAs.0 Threads within a CTA execute in SIMT (single-instruction. WARP_SZ. such that the threads execute the same instructions at the same time. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. or sequentially.2. The warp size is a machine-dependent constant.2. 2010 . 8 January 24. so that the total number of threads that can be launched in a single kernel invocation is very large. depending on the platform. 2D . because threads in different CTAs cannot communicate and synchronize with each other. A warp is a maximal subset of threads from a single CTA. Each grid also has a unique temporal grid identifier (gridid). %nctaid. Multiple CTAs may execute concurrently and in parallel. or 3D shape specified by the parameter nctaid. Threads may read and use these values through predefined. Some applications may be able to maximize performance with knowledge of the warp size.PTX ISA Version 2. a warp has 32 threads.

2) Thread (4. 2) Thread (1. 0) CTA (2. 1) Thread (1. Thread Batching January 24. 1) Thread (4. 2010 9 . 1) Thread (0. 1) CTA (1. 1) Grid 2 Kernel 2 CTA (1. 1) Thread (3. 0) Thread (1. A grid is a set of CTAs that execute independently. 2) Thread (2. Figure 1. 1) CTA (2. 0) Thread (0. 0) CTA (1. 0) Thread (2. 0) CTA (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (0. 0) Thread (3. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (2. 2) Thread (3.Chapter 2. 0) Thread (4.

3. and texture memory spaces are optimized for different memory usages. as well as data filtering. or. The device memory may be mapped and read or written by the host. 10 January 24. The global. referred to as host memory and device memory. for more efficient transfer. constant.0 2. constant. Both the host and the device maintain their own local memory. for some specific data formats. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. and texture memory spaces are persistent across kernel launches by the same application.PTX ISA Version 2. The global. Each thread has a private local memory. Finally. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. 2010 . Texture memory also offers different addressing modes. all threads have access to the same global memory. respectively. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.

2010 11 . 0) Block (1. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0.Chapter 2. 2) Block (1. 1) Block (1. 1) Block (1. 0) Block (1. 1) Block (2. Memory Hierarchy January 24. 0) Block (2. 1) Block (0. 0) Block (0. 2) Figure 2. 1) Grid 1 Global memory Block (0.

PTX ISA Version 2. 2010 .0 12 January 24.

As thread blocks terminate. A multiprocessor consists of multiple Scalar Processor (SP) cores. When a multiprocessor is given one or more thread blocks to execute. the threads converge back to the same execution path. multiple-thread). A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). The multiprocessor creates. different warps execute independently regardless of whether they are executing common or disjointed code paths. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. new blocks are launched on the vacated multiprocessors. If threads of a warp diverge via a data-dependent conditional branch. for example. allowing. manages. Branch divergence occurs only within a warp. so full efficiency is realized when all threads of a warp agree on their execution path. The way a block is split into warps is always the same. increasing thread IDs with the first warp containing thread 0. Parallel Thread Execution Machine Model 3. January 24. and executes threads in groups of parallel threads called warps. The threads of a thread block execute concurrently on one multiprocessor. and each scalar thread executes independently with its own instruction address and register state. a voxel in a volume. A warp executes one common instruction at a time. and when all paths complete. and on-chip shared memory. a cell in a grid-based computation).Chapter 3. manages. the first parallel thread technology. The multiprocessor SIMT unit creates. To manage hundreds of threads running several different programs. it splits them into warps that get scheduled by the SIMT unit. a multithreaded instruction unit. disabling threads that are not on that path. It implements a single-instruction barrier synchronization. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. (This term originates from weaving. the multiprocessor employs a new architecture we call SIMT (single-instruction. the warp serially executes each branch path taken. When a host program invokes a kernel grid. and executes concurrent threads in hardware with zero scheduling overhead. 2010 13 . the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. each warp contains threads of consecutive. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. At every instruction issue time. The multiprocessor maps each thread to one scalar processor core. schedules.1.

SIMT enables programmers to write thread-level parallel code for independent. scalar threads. A key difference is that SIMD vector organizations expose the SIMD width to the software. on the other hand. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. and writes to the same location in global memory for more than one of the threads of the warp. which is a read-only region of device memory. As illustrated by Figure 3. modifies. 2010 . Multiple Data) vector organizations in that a single instruction controls multiple processing elements. write to that location occurs and they are all serialized. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. For the purposes of correctness. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp.0 SIMT architecture is akin to SIMD (Single Instruction. Vector architectures. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. • The local and global memory spaces are read-write regions of device memory and are not cached. modify. In practice. which is a read-only region of device memory. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. whereas SIMT instructions specify the execution and branching behavior of a single thread. 14 January 24. In contrast with SIMD vector machines. but one of the writes is guaranteed to succeed. the number of serialized writes that occur to that location and the order in which they occur is undefined. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. the programmer can essentially ignore the SIMT behavior. each read. If there are not enough registers or shared memory available per multiprocessor to process at least one block. require the software to coalesce loads into vectors and manage divergence manually.PTX ISA Version 2. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. however. but the order in which they occur is undefined. If an atomic instruction executed by a warp reads. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. as well as data-parallel code for coordinated threads. A multiprocessor can execute as many as eight thread blocks concurrently. the kernel will fail to launch.

Hardware Model January 24.Chapter 3. Figure 3. 2010 15 . Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

2010 .PTX ISA Version 2.0 16 January 24.

All whitespace characters are equivalent. January 24. See Section 9 for a more information on these directives. Source Format Source files are ASCII text. 4. Syntax PTX programs are a collection of text source files. #ifdef. #endif. 4. Comments Comments in PTX follow C/C++ syntax. Lines beginning with # are preprocessor directives. The C preprocessor cpp may be used to process PTX source files. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.1. #line. Each PTX file must begin with a . Comments in PTX are treated as whitespace. using non-nested /* and */ for comments that may span multiple lines.Chapter 4. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor.2. The following are common preprocessor directives: #include. PTX is case sensitive and uses lowercase for keywords. 2010 17 . #else. followed by a . #define. #if. whitespace is ignored except for its use in separating tokens in the language. Pseudo-operations specify symbol and addressing management.target directive specifying the target architecture assumed. Lines are separated by the newline character (‘\n’).version directive specifying the PTX language version. and using // to begin a comment that extends to the end of the current line.

reg .maxnctapersm . Statements A PTX statement is either a directive or an instruction. 2010 . address expressions.b32 r1. %tid.shared . r2.target .maxnreg . The guard predicate may be optionally negated.sreg .f32 array[N].maxntid .0 4.PTX ISA Version 2. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. and is written as @p. .param .visible 4.b32 add.extern .3. 18 January 24.const . so no conflict is possible with user-defined identifiers.global.loc .5.2.entry .version .func .reg . The guard predicate follows the optional label and precedes the opcode. .minnctapersm . 0.pragma .f32 r2. shl. Statements begin with an optional label and end with a semicolon. Table 1.file PTX Directives . written as @!p.3. Instructions have an optional guard predicate which controls conditional execution. followed by source operands. r1.tex . constant expressions.align .x. r2. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. Directive Statements Directive keywords begin with a dot.1. or label names.global start: . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. array[r1].global . Instruction keywords are listed in Table 2.3.section . where p is a predicate register. 2. and terminated with a semicolon. mov. ld. Examples: . Operands may be register variables. The destination operand is first. All instruction keywords are reserved tokens in PTX.local .b32 r1.b32 r1. r2.

Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.

PTX ISA Version 2. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. dollar. or they start with an underscore. e. Many high-level languages such as C and C++ follow similar rules for identifier names. underscore. Table 3. The percentage sign can be used to avoid name conflicts. %pm3 WARP_SZ 20 January 24. PTX allows the percentage sign as the first character of an identifier. or percentage character followed by one or more letters. except that the percentage sign is not allowed. digits.4.0 4. digits. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. between user-defined variable names and compiler-generated names. 2010 . …. PTX predefines one constant and a small number of special registers that begin with the percentage sign.g. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or dollar characters. underscore. listed in Table 3.

The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. hexadecimal. in which case the literal is unsigned (. The syntax follows that of C. the constant begins with 0f or 0F followed by 8 hex digits. integer constants are allowed and are interpreted as in C. 2010 21 . every integer constant has type . or binary notation.s64) unless the value cannot be fully represented in . The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. each integer constant is converted to the appropriate size based on the data or instruction type at its use. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. the sm_1x and sm_20 targets have a WARP_SZ value of 32.5. octal. i.. These constants may be used in data initialization and as operands to instructions. literals are always represented in 64-bit double-precision format.2. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. To specify IEEE 754 single-precision floating point values.e.s64 or the unsigned suffix is specified.e. floating-point. zero values are FALSE and non-zero values are TRUE. and bit-size types. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. 4.s64 or . Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.5.Chapter 4.1. For predicate-type data and instructions. 4. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Constants PTX supports integer and floating-point constants and constant expressions. there is no suffix letter to specify size. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. i. Integer literals may be written in decimal. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. the constant begins with 0d or 0D followed by 16 hex digits. Type checking rules remain the same for integer.5. where the behavior of the operation depends on the operand types. When used in an instruction or data initialization. Unlike C and C++. To specify IEEE 754 doubleprecision floating point values. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Floating-point literals may be written with an optional decimal point and an optional signed exponent.u64). The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons..u64. Syntax 4. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

s64 .s64 .s64) + . Syntax 4.u64 .6. 2010 25 .u64 .s64.f64 converted type . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 same as source .5.f64 integer integer integer integer integer int ?.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .f64 : .u64 .u64.Chapter 4.u64 same as 1st operand .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 .u64 . or .f64 integer .u64 1st unchanged.f64 use usual conversions .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 use usual conversions .u64 .u64 .s64 .s64 .f64 integer . .s64 . 2nd is . Table 5.u64) (.s64 .f64 converted type constant literal + ! ~ Cast Binary (.f64 use usual conversions .

2010 .PTX ISA Version 2.0 26 January 24.

and Variables While the specific resources available in a given target GPU will vary. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.Chapter 5. 5. Addressable memory shared between threads in 1 CTA. defined per-thread. Shared.sreg . Local memory. read-only memory. addressability. pre-defined. Read-only. State Spaces A state space is a storage area with particular characteristics. and level of sharing between threads. Global texture memory (deprecated).shared . Special registers.global . platform-specific.tex January 24. Table 6. or Function or local parameters. State Spaces. Kernel parameters. Global memory. Name State Spaces Description Registers. and properties of state spaces are shown in Table 5. The characteristics of a state space include its size.reg . access speed.1. access rights. .param . All variables reside in some state space. fast.const . defined per-grid. 2010 27 . Types. the kinds of resources will be common across platforms. shared by all threads. private to each thread. and these resources are abstracted in PTX through state spaces and data types.local . The list of state spaces is shown in Table 4.

causing changes in performance.param instruction.1. and performance monitoring registers. Device function input parameters may have their address taken via mov. or 128-bits.sreg) state space holds predefined. The most common use of 8-bit registers is with ld. and cvt instructions.param instructions.tex Restricted Yes No3 5. clock counters.reg state space) are fast storage locations. predicate) or untyped.local state space..1. 28 January 24. st.PTX ISA Version 2. 3 Accessible only via the tex instruction. 64-. 32-.global . Registers may be typed (signed integer. Register size is restricted. floating point. platform-specific registers.local . When the limit is exceeded. Registers differ from the other state spaces in that they are not fully addressable. For each architecture. Address may be taken via mov instruction.2.const . aside from predicate registers which are 1-bit. or 64-bits. it is not possible to refer to the address of a register. The number of registers is limited.sreg . Registers may have alignment boundaries required by multi-word loads and stores. 1 Accessible only via the ld.param and st. All special registers are predefined. register variables will be spilled to memory.shared . or as elements of vector tuples. and thread parameters. Special Register State Space The special register (.e. 2010 .1. 16-. 2 Accessible via ld. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .reg . scalar registers have a width of 8-.param (used in functions) . such as grid. CTA. and vector registers have a width of 16-. 5. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). Register State Space Registers (. the parameter is then located on the stack frame and its address is in the . unsigned integer. i. and will vary from platform to platform. 32-.0 Table 7.param (as input to kernel) .

initialized by the host.1.1. the declaration . Multiple incomplete array variables declared in the same bank become aliases. It is the mechanism by which different CTAs and different grids can communicate. Consider the case where one thread executes the following two assignments: a = a + 1. results in const_buffer pointing to the start of constant bank two. an incomplete array in bank 2 is accessed as follows: . If no bank number is given. there are eleven 64KB banks. Constant State Space The constant (.1. // load second word 5. The remaining banks may be used to implement “incomplete” constant arrays (in C. For the current devices.const[2] . To access data in contant banks 1 through 10. For any thread in a context. The constant memory is organized into fixed size banks. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. It is typically standard memory with cache. All memory writes prior to the bar.extern . Threads must be able to do their work without waiting for other threads to do theirs.3.global. Sequential consistency is provided by the bar. the store operation updating a may still be in flight.local) is private memory for each thread to keep its own data. For example.local and st. b = b – 1.b32 const_buffer[].b32 %r1. 5. Local State Space The local state space (. as it must be allocated on a perthread basis. 2010 29 . where bank ranges from 0 to 10.sync instruction are guaranteed to be visible to any reads after the barrier instruction.global. This reiterates the kind of parallelism available in machines that run PTX.5. each pointing to the start address of the specified constant bank.extern . Threads wait at the barrier until all threads in the CTA have arrived. Types. where the size is not known at compile time. In implementations that support a stack.const) state space is a read-only memory. the bank number must be provided in the state space of the load instruction.sync instruction.const[2] . This pointer can then be used to access the entire 64KB constant bank. all addresses are in global memory are shared. ld.const[2]. [const_buffer+4]. for example). Global State Space The global (. State Spaces. The size is limited.local to access local variables. as in lock-free and wait-free style programming. Global memory is not sequentially consistent.const[bank] modifier. and atom. Use ld. Module-scoped local memory variables are stored at fixed addresses.global to access global variables. st. By convention.4.Chapter 5. and Variables 5. bank zero is used for all statically-sized constant variables. whereas local memory variables declared January 24. the stack is in local memory. If another thread sees the variable b change.b32 const_buffer[]. Banks are specified using the . bank zero is used. Use ld. For example.global) state space is memory that is accessible by all threads in a context.

Kernel Function Parameters Each kernel function definition includes an optional list of parameters. … Example: . (2a) to declare formal input and return parameters for device functions called from within kernel execution. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.x supports only kernel function parameters in .1.param instructions.reg . device function parameters were previously restricted to the register state space. ld. Example: . The use of parameter state space for device function parameters is new to PTX ISA version 2.0 within a function or kernel body are allocated on the stack.reg . per-kernel versus per-thread). For example. read-only variables declared in the . 2010 . %n. These parameters are addressable.param space.param . ld. all local memory variables are stored at fixed addresses and recursive function calls are not supported.param) state space is used (1) to pass input arguments from the host to the kernel. … 30 January 24. Note: The location of parameter space is implementation specific. The address of a kernel parameter may be moved into a register using the mov instruction. Parameter State Space The parameter (.param space variables. 5. .b32 N. Note that PTX ISA versions 1.6.param state space and is accessed using ld.u32 %n.param instructions.b8 buffer[64] ) { .entry bar ( .u32 %ptr. . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). [buffer]. ld. mov. In implementations that do not support a stack.reg . 5.f64 %d.1. len.param.param .u32 %ptr.6.0 and requires target architecture sm_20. Therefore.f64 %d.1. Values passed from the host to the kernel are accessed through these parameter variables using ld. typically for passing large structures by value to a function.align 8 .param state space.param. The kernel parameter variables are shared across all CTAs within a grid. [N]. No access protection is provided between parameter and global space in this case. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param .u32 %n.param. Similarly.u32 %n. [%ptr].b32 len ) { . The resulting address is in the . PTX code should make no assumptions about the relative locations or ordering of .entry foo ( .PTX ISA Version 2. in some implementations kernel parameters reside in global memory.

b32 N.f64 dbl. int y. call foo. a byte array in parameter space is used.reg .0 extends the use of parameter space to device function parameters. Example: // pass object of type struct { double d.s32 x.param.reg . mystruct). Function input parameters may be read via ld.local instructions. and so the address will be in the . January 24. (4. … See the section on function call syntax for more details.param byte array variable that represents a flattened C structure or union.param formal parameter having the same size and alignment as the passed argument. [buffer]. 2010 31 .s32 %y.param .param and function return parameters may be written using st.b8 buffer[12] ) { . the address of a function input parameter may be moved into a register using the mov instruction. is flattened. ld. the caller will declare a locally-scoped .param. st. }. int y. This will be passed by value to a callee.reg .6.param space variable.func foo ( . such as C structures larger than 8 bytes.f64 [mystruct+0]. passed to foo … .local and st.reg . ld. Aside from passing structures by value. In PTX. Types. } mystruct.param space is also required whenever a formal parameter has its address taken within the called function. The most common use is for passing objects by value that do not fit within a PTX register.param. … } // code snippet from the caller // struct { double d. . [buffer+8].align 8 .Chapter 5. In this case.2. Typically.align 8 . .1.param . which declares a . dbl.param. . it is illegal to write to an input parameter or read from a return parameter. … st.f64 %d. x.b8 mystruct. . It is not possible to use mov to get the address of a return parameter or a locally-scoped .s32 %y. Device Function Parameters PTX ISA version 2. State Spaces. . .f64 %d. Note that the parameter will be copied to the stack if necessary.local state space and is accessed via ld.s32 [mystruct+8]. and Variables 5.reg .param.

Another is sequential access from sequential threads.texref variables in the .u64.tex variables are required to be defined in the global scope. and programs should instead reference texture memory through variables of type .u32 or . Shared State Space The shared (.texref.1. An error is generated if the maximum number of physical resources is exceeded.tex) state space is global memory accessed via the texture instruction. and variables declared in the .tex .tex .0 5. where texture identifiers are allocated sequentially beginning with zero. Use ld.u32 .3 for the description of the .texref tex_a. Multiple names may be bound to the same physical texture identifier. 2010 .global state space.tex directive will bind the named texture memory variable to a hardware texture identifier.tex directive is retained for backward compatibility.u32 tex_a. 32 January 24. tex_d.shared to access shared variables.7. 5.tex .global . and . tex_c.tex state space are equivalent to module-scoped . For example.6 for its use in texture instructions.texref type and Section 8. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Texture memory is read-only. is equivalent to .1. An address in shared memory can be read and written by any thread in a CTA. Shared memory typically has some optimizations to support the sharing.tex .PTX ISA Version 2.shared and st.u32 .u32 tex_a. The texture name must be of type . Example: .shared) state space is a per-CTA region of memory for threads in a CTA to share data. A texture’s base address is assumed to be aligned to a 16-byte boundary. It is shared by all threads in a context. The . a legacy PTX definitions such as . See Section 5. where all threads read from the same address. The . Physical texture resources are allocated on a per-module granularity. tex_f. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 .7.tex .8. Texture State Space (deprecated) The texture (. tex_d. One example is broadcast.

. January 24.f16 floating-point type is allowed only in conversions to and from .2.s8.f64 . but typed variables enhance program readability and allow for better operand type checking. so that narrow values may be loaded. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. For convenience. State Spaces. . . 2010 33 . stored. st.s32. . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.2.b32.pred Most instructions have one or more type specifiers. and converted using regular-width registers.b8. Restricted Use of Sub-Word Sizes The . The bitsize type is compatible with any fundamental type having the same size. . Register variables are always of a fundamental type. Types 5. and cvt instructions. st.s8.u16.u8. stored.f64 types. In principle. Fundamental Types In PTX. . or converted to other types and sizes.b64 .u8.2.u64 . . needed to fully specify instruction behavior. All floating-point instructions operate only on . Signed and unsigned integer types are compatible if they have the same size.u32.f16. The following table lists the fundamental type specifiers for each basic type: Table 8. . The .f32 and . and instructions operate on these types.b8 instruction types are restricted to ld. . For example. .f32.f64 types. the fundamental types reflect the native data types supported by the target architectures. so their names are intentionally short. A fundamental type specifies both a basic type and a size. . Two fundamental types are compatible if they have the same basic type and are the same size. all variables (aside from predicates) could be declared using only bit-size types. ld.s64 . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . The same typesize specifiers are used for both variable definitions and for typing instructions. 5.Chapter 5. and . Operand types and sizes are checked against instruction types for compatibility.b16.f32 and .1.2. Types. and Variables 5. .s16.

the resulting pointer may be stored to and loaded from memory. but all information about layout. or performing pointer arithmetic will result in undefined results. and . Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. i. Texture. field ordering. . The following tables list the named members of each type for unified and independent texture modes. and Surface Types PTX includes built-in “opaque” types for defining texture. sampler.texref type that describe sampler properties are ignored. In the independent mode. accessing the pointer with ld and st instructions. In independent mode the fields of the .. samplers. suq). texture and sampler information each have their own handle. base address.3.samplerref. texture and sampler information is accessed through a single . 34 January 24.{u32.surfref.e. Sampler. Retrieving the value of a named member via query instructions (txq. In the unified mode.texref. and surface descriptor variables.samplerref variables. allowing them to be defined separately and combined at the site of usage in the program. but the pointer cannot otherwise be treated as an address. suld. Creating pointers to opaque variables using mov. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. 2010 .u64} reg. sured). sust. Referencing textures. PTX has two modes of operation.PTX ISA Version 2.texref handle. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. passed as a parameter to functions. since these properties are defined by . The three built-in types are . and query instructions. or surfaces via texture and surface load/store instructions (tex. and overall size is hidden to a PTX program. store.0 5. opaque_var. For working with textures and samplers. These types have named fields similar to structures. hence the term “opaque”. and de-referenced by texture and surface load.

clamp_to_edge.Chapter 5.texref values . mirror. clamp_to_border 0. Member width height depth Opaque Type Fields in Unified Texture Mode .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. 1 ignored ignored ignored ignored . Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9. linear wrap. 2010 35 . clamp_to_border N/A N/A N/A N/A N/A . State Spaces. mirror. linear wrap. clamp_ogl. clamp_to_edge.samplerref values N/A N/A N/A N/A nearest. Types.texref values in elements in elements in elements 0. 1 nearest. clamp_ogl.

samplerref my_sampler_name. When declared at module scope.surfref my_surface_name. . these variables are declared in the . Example: .global . At module scope. 36 January 24.global .global .texref tex1.global . As kernel parameters.param state space.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.texref my_texture_name. filter_mode = nearest }.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. these variables must be in the . . Example: . . the types may be initialized using a list of static expressions assigning values to the named members. 2010 .global .global state space.PTX ISA Version 2.

struct float4 coord. January 24. // typedef . . Variables In PTX.v4. // a length-4 vector of floats . q. PTX supports types for simple aggregate objects such as vectors and arrays. Examples: .global .v4 vector. // a length-4 vector of bytes By default. r.v2.2. Predicate variables may only be declared in the register state space.Chapter 5. 5. Every variable must reside in one of the state spaces enumerated in the previous section.global . Vectors cannot exceed 128-bits in length.v4 .reg .f32 accel.reg . for example. where the fourth element provides padding. 2010 37 .reg .v4.v2 . textures.f32 v0. . an optional array size. Vectors Limited-length vector types are supported. 0.v4 .const .u32 loc.shared . .0. . and Variables 5. 0. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . This is a common case for three-dimensional grids.4. 0}.v4 . an optional initializer. // a length-2 vector of unsigned ints .struct float4 { .v2 or .global .4. a variable declaration describes both the variable’s type and its state space.global .pred p. State Spaces. .b8 v.4.f32 bias[] = {-1.u8 bg[4] = {0.s32 i. Variable Declarations All storage for data is specified with variable declarations. its name.f64 is not allowed. 5. etc.0}. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. Three-element vectors may be handled by using a . Types. A variable declaration names the space in which the variable resides. . Vectors must be based on a fundamental type. .1.v3 }. In addition to fundamental types. 1.u16 uv. Examples: . vector variables are aligned to a multiple of their overall size (vector length times base-type size).f32 V. its type and size. and they may reside in the register space.global .v1. and an optional fixed address for the variable.

.{..0}}. .1.f16 and .global . The size of the array specifies how many elements should be reserved. -1}..v4 .b32 ptr = rgba. .u32 or . this can be used to initialize a jump table to be used with indirect branches or calls.global .PTX ISA Version 2.. Array Declarations Array declarations are provided to allow the programmer to reserve space.global .0. {0.0}.global .0.0}.4.1}.3..0. {0. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). {0. Similarly. where the variable name is followed by an equals sign and the initial value or values for the variable.. label names appearing in initializers represent the address of the next instruction following the label. 2010 .f32 blur_kernel[][] = {{. Variables that hold addresses of variables or instructions should be of type .05. variable initialization is supported only for constant and global state spaces.1.{. or is left empty.shared . 0}.0 5. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.pred. 19*19 (361) halfwords are reserved (722 bytes). // address of rgba into ptr Currently. Variable names appearing in initializers represent the address of the variable.05. To declare an array. 38 January 24.s32 offset[][] = { {-1.05}}. The size of the dimension is either a constant expression.4.u8 rgba[3] = {{1.0. .u64. {1.1. A scalar takes a single value. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. 1} }. being determined by an array initializer.1.local ..05}.4.u16 kernel[19][19].global . Here are some examples: . Initializers are allowed for all types except . {0. Examples: . .s32 n = 10.4. For the kernel declaration above.1. this can be used to statically initialize a pointer to a variable. 0}. 5.u8 mailbox[128].

6. For example.0.b32 variables. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Types. not for individual elements.0. .const .reg . say one hundred.align byte-count specifier immediately following the state-space specifier. The default alignment for vector variables is to a multiple of the overall vector size.b8 bar[8] = {0. . %r1.0. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. For arrays. …. it is quite common for a compiler frontend to generate a large number of register names. Alignment is specified using an optional .Chapter 5. 2010 39 . The default alignment for scalar and array variables is to a multiple of the base-type size.5.. named %r0.0.align 4 . State Spaces.. Parameterized Variable Names Since PTX supports virtual registers. of .4.0. and may be preceded by an alignment specifier.b32 %r<100>.2. suppose a program uses a large number.0}. // declare %r0. Elements are bytes. and Variables 5. %r99. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. 5.4. The variable will be aligned to an address which is an integer multiple of byte-count. These 100 register variables can be declared as follows: . Array variables cannot be declared this way. Rather than require explicit declaration of every name. alignment specifies the address alignment for the starting address of the entire array.. January 24. Examples: // allocate array at 4-byte aligned address. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. nor are initializers permitted. %r1.

0 40 January 24.PTX ISA Version 2. 2010 .

so operands for ALU instructions must all be in variables declared in the . The bit-size type is compatible with every type having the same size. For most operations. and a few instructions have additional predicate source operands. the sizes of the operands must be consistent. 6. The mov instruction copies data between registers. PTX describes a load-store machine. Integer types of a common size are compatible with each other. Most instructions have an optional predicate guard that controls conditional execution. and cvt instructions copy data from one location to another.Chapter 6. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. . b. Operand Type Information All operands in instructions have a known type from their declarations. The result operand is a scalar or vector variable in the register state space.3. as its job is to convert from nearly any data type to any other data type (and size). Instruction Operands 6. 2010 41 .1. Instructions ld and st move data from/to addressable state spaces to/from registers. st. There is no automatic conversion between types. Source Operands The source operands are denoted in the instruction descriptions by the names a. mov. The cvt (convert) instruction takes a variety of operand types and sizes. 6.2. s. q. Predicate operands are denoted by the names p. January 24. r. The ld. Each operand type must be compatible with the type determined by the instruction template and instruction type.reg register state space. and c.

reg .const. Here are a few examples: . r0.s32 tbl[256].PTX ISA Version 2. The syntax is similar to that used in many assembly languages. ld. . The address is an offset in the state space in which the variable is declared. q.f32 W.global . [tbl+12]. . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.4. there is no support for C-style pointer arithmetic.1.u16 ld.u32 42 January 24.f32 V.v4 .shared .reg . Address expressions include variable names. .[x]. 6.reg . and immediate address expressions which evaluate at compile-time to a constant address.s32 q.reg .gloal. tbl. and Vectors Using scalar variables as operands is straightforward.s32 mov. p. and vectors. The interesting capabilities begin with addresses. . arrays.0 6.u16 r0.const .u16 x. Arrays. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.shared. . 2010 . The mov instruction can be used to move the address of a variable into a pointer.v4 . [V].b32 p. Load and store operations move data between registers and locations in addressable state spaces. address registers.v4. W. Examples include pointer arithmetic and pointer comparisons. Using Addresses.f32 ld. . address register plus byte offset.4. All addresses and address computations are byte-based.

If more complicated indexing is desired. Vector elements can be extracted from the vector with the suffixes . .y V. and tex. Vector loads and stores can be used to implement wide loads and stores. and in move instructions to get the address of the label or function into a register.a 6. V2.z and . or by indexing into the array using square-bracket notation. mov. Instruction Operands 6. say {Ra. V. which may improve memory performance. Examples are ld. a[N-1].global. and the identifier becomes an address constant in the space where the array is declared.3.w = = = = V.r.u32 s. as well as the typical color fields .2. c.u32 {a.d}. [addr+offset2].f32 ld.b V. Vectors as Operands Vector operands are supported by a limited subset of instructions. Array elements can be accessed using an explicitly calculated byte address.c.b. Vectors may also be passed as arguments to called functions. Rb. Here are examples: ld.f32 a. The size of the array is a constant in the program. where the offset is a constant expression that is either added or subtracted from a register variable. Arrays as Operands Arrays of all types can be declared.c.4.v4. The expression within square brackets is either a constant integer.x. 2010 43 . January 24. or a simple “register with constant offset” expression. Elements in a brace-enclosed vector.global.f32 V. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.f32 {a.4. mov.y.a. it must be written as an address calculation prior to use.4.g V.u32 s. A brace-enclosed list is used for pattern matching to pull apart vectors. a register variable. .v4 .Chapter 6.global. .u32 s.v2. a[0]. ld.v4. The registers in the load/store operations can be a vector. .b and . . ld. for use in an indirect branch or call. Rd}.z V.d}.reg . b. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. st. // move address of a[1] into s 6. which include mov.4. or a braceenclosed list of similarly typed scalars. d.x V.g.r V. Rc.global. a[1].b.reg . .w. [addr+offset].

1. 6.5. logic.PTX ISA Version 2. if a cvt. 44 January 24. and data movement instruction must be of the same type and size. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. Operands of different sizes or types must be converted prior to the operation. the u16 is zero-extended to s32. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. except for operations where changing the size and/or type is part of the definition of the instruction. For example. Type Conversion All operands to all arithmetic.000 for f16).s32.5.u16 instruction is given a u16 source operand and s32 as a destination operand. 2010 .0 6. and ~131.

January 24. cvt. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2s = float-to-signed. The type of extension (sign or zero) is based on the destination format. Notes 1 If the destination register is wider than the destination format. 2010 45 . For example. s2f = signed-to-float. then sign-extend to 32-bits. chop = keep only low bits that fit. f2u = float-to-unsigned. u2f = unsigned-to-float. the result is extended to the destination register width after chopping.s16.u32 targeting a 32-bit register will first chop to 16-bits.Chapter 6. Instruction Operands Table 11. zext = zero-extend. f2f = float-to-float.

rni . choosing even integer if source is equidistant between two integers. Table 12. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rn .rzi . there are four integer rounding modifiers and four floating-point rounding modifiers.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.PTX ISA Version 2.rm . Modifier . In PTX.rz .rpi Integer Rounding Modifiers Description round to nearest integer. Rounding Modifiers Conversion instructions may specify a rounding modifier.2.5. 2010 .0 6.rmi . The following tables summarize the rounding modifiers. Modifier .

Chapter 6. while global memory is slowest. Operand Costs Operands from different state spaces affect the speed of an operation.6. Instruction Operands 6. Another way to hide latency is to issue the load instructions as early as possible. Much of the delay to memory can be hidden in a number of ways. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Registers are fastest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. 2010 47 . Table 11 gives estimates of the costs of using different kinds of memory. The register in a store operation is available much more quickly. Table 14. first access is high Notes January 24. as execution is not blocked until the desired result is used in a subsequent (in time) instruction.

2010 .0 48 January 24.PTX ISA Version 2.

At the call. so recursion is not yet supported. and memory allocated on the stack (“alloca”).func directive. These include syntax for function definitions. A function declaration specifies an optional list of return parameters. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. function calls. and an optional list of input parameters. Execution of the ret instruction within foo transfers control to the instruction following the call. A function definition specifies both the interface and the body of the function. support for variadic functions (“varargs”). execution of the call instruction transfers control to foo. together these specify the function’s interface. In this section. or prototype. functions are declared and defined using the . … Here. Scalar and vector base-type input and return parameters may be represented simply as register variables. 7. stack-based ABI. The simplest function has no parameters or return values. } … call foo. Function declarations and definitions In PTX.1. and return values may be placed directly into register variables. the function name. implicitly saving the return address. we describe the features of PTX needed to achieve this hiding of the ABI. A function must be declared or defined prior to being called. parameter passing. Abstracting the ABI Rather than expose details of a particular calling convention. stack layout. 2010 49 . and Application Binary Interface (ABI). January 24. arguments may be register variables or constants.Chapter 7. NOTE: The current version of PTX does not implement the underlying. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and is represented in PTX as follows: .func foo { … ret.

[y+10].param .reg .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.align 8 py[12].u32 %res. %rc2.f64 f1. st. . ld.b32 c1. bumpptr. c3. c2. // scalar args in . note that .b8 [py+ 8].b8 [py+10]. st. %ptr. 50 January 24.reg .u32 %res) inc_ptr ( . %rc2. %rd. passed by value to a function: struct { double dbl. (%r1.reg .c4.u32 %ptr. Since memory accesses are required to be aligned to a multiple of the access size.param variable y is used in function definition bar to represent a formal parameter. st.4).func (.param. In PTX.b8 c1. a . ld.param space call (%out).param.param . For example.param space variables are used in two ways.reg . consider the following C structure.b8 [py+11].func (. Second. }. [y+9].b8 c2.f1.u32 %inc ) { add. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . First.0 Example: .c1. %rc1. ld. … ld.reg space.align 8 y[12]) { . .param. char c[4].param. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . ld. The .s32 x.c2.param.param. … st.param.reg .param state space is used to pass the structure by value: . (%x.param.reg .b8 c4. py). this structure will be flattened into a byte array.s32 out) bar (.f64 f1.reg .b8 .param. [y+0].param. [y+8]. [y+11].b8 c3. a . . st. %inc.b8 [py+ 9]. c4. byte array in . … … // computation using x.PTX ISA Version 2.c3.b64 [py+ 0]. } { . … In this example.f64 field are aligned. } … call (%r1). %rc1.param space memory. ret. inc_ptr.b8 . 2010 .

Abstracting the ABI The following is a conceptual way to think about the . all st.param space formal parameters that are base-type scalar or vector variables. size.reg space variable with matching type and size.param instructions used for argument passing must be contained in the basic block with the call instruction. a . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.reg space variable of matching type and size. For a callee.param or . • • • For a callee.. In the case of . and alignment. The following restrictions apply to parameter passing. or 16 bytes.reg state space can be used to receive and return base-type scalar and vector values. The . or a constant that can be represented in the type of the formal parameter.param variables or . Supporting the . The .param variables.reg variables. In the case of .param state space use in device functions. 2010 51 . 2.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. Note that the choice of .param byte array is used to collect together fields of a structure being passed by value.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. For . • • • Input and return parameters may be . the corresponding argument may be either a .param and ld.param arguments. January 24. For a caller. the corresponding argument may be either a .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. Parameters in . . • The . and alignment of parameters.reg space formal parameters. In the case of .reg state space in this way provides legacy support. • • Arguments may be .param space formal parameters that are byte arrays. 8.param space byte array with matching type.param state space is used to receive parameter values and/or pass return values back to the caller.reg or .g.param memory must be aligned to a multiple of 1. • The .param argument must be declared within the local scope of the caller.param or . This enables backend optimization and ensures that the .Chapter 7. A . size. or constants. Typically. For a caller. the argument must also be a . 4.reg variables. or a constant that can be represented in the type of the formal parameter.

PTX 2.PTX ISA Version 2. formal parameters were restricted to . 52 January 24.0 7. formal parameters may be in either .param byte array should be used to return objects that do not fit into a register.param space parameters support arrays. 2010 .1.0 continues to support multiple return registers for sm_1x targets.reg or . In PTX ISA version 2. Changes from PTX 1.x In PTX ISA version 1.x. and there was no support for array parameters.param state space.reg state space. For sm_2x targets. PTX 2. PTX 1.0 restricts functions to a single return value. and .1. Objects such as C structures were flattened and passed or returned using multiple registers.x supports multiple return values for this purpose.0. and a .

Once all arguments have been processed. .u32 sz.reg . 2. bra Done. (2. bra Loop.func (. For %va_arg.b64 val) %va_arg64 (.func ( .s32 val.reg .reg .u32 sz. along with the size and alignment of the next data value to be accessed.reg .reg . (3.pred p.reg . 4. ) { . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers ..reg . 2. setp. … ) . 4. variadic functions are declared with an ellipsis at the end of the input parameter list.u32 ap. or 16 bytes.u32 ptr. the size may be 1. Variadic functions NOTE: The current version of PTX does not support variadic functions.ge p. or 8 bytes.reg . // default to MININT mov.reg .reg . %r1. maxN. Abstracting the ABI 7.b32 ctr.b32 result. . (ap).u32 ptr. following zero or more fixed parameters: . 2. %s2). … %va_start returns Loop: @p Done: January 24. call (ap). .u32 ptr) %va_start .. maxN.reg . %va_arg.reg . %va_start.s32 result ) maxN ( . %r3).u32 N.u32.reg . . call %va_end. mov.func %va_end (. In PTX.func okay ( … ) Built-in functions are provided to initialize. 0.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. the size may be 1. max. (ap. N. for %va_arg64. 2010 53 . . ret. call (val).Chapter 7. PTX provides a high-level mechanism similar to the one provided by the stdarg. 0x8000000. In both cases.u32 align) . %r2.reg .func baz ( . 4). ctr.func (.h headers in C. } … call (%max). This handle is then passed to the %va_arg and %va_arg64 built-in functions. %s1.reg . To support functions with a variable number of arguments.reg .u32 align) . … call (%max). or 4 bytes.u32 b. 8.h and varargs. iteratively access. ctr. %va_end is called to free the variable argument list handle. and end access to a list of variable arguments. The function prototypes are defined as follows: . . .2.b32 val) %va_arg (.reg . .u32 a.func (. result. the alignment may be 1.s32 result. 4. val.

PTX ISA Version 2.0 7. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. To allocate memory.u32 ptr ) %alloca ( . If a particular alignment is required. The array is then accessed with ld.local and st.reg . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.reg .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. a function simply calls the built-in function %alloca. 54 January 24. 2010 .local instructions. Alloca NOTE: The current version of PTX does not support alloca.func ( .3. defined as follows: . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.

opcode A. For some instructions the destination operand is optional. PTX Instructions PTX instructions generally have from zero to four operands. 8. opcode D. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. In addition to the name and the format of the instruction. C. Instruction Set 8. the D operand is the destination operand.1.s32.lt p|q. setp. 2010 55 . the semantics are described. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. // p = (a < b). opcode D. q = !(a < b). B. January 24. while A. A.2. A. For instructions that create a result value. a. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.Chapter 8. and C are the source operands. b. We use a ‘|’ symbol to separate multiple destination registers. B. B. The setp instruction writes two destination registers. opcode D. A. followed by some examples that attempt to show several possible instantiations of the instruction.

predicate registers can be declared as . i. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.reg . r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. 1.lt. where p is a predicate variable. Predicated Execution In PTX. n. bra L1.3. This can be written in PTX as @p setp. j. To implement the above example as a true conditional branch.s32 j.s32 j. 2010 . optionally negated.pred as the type specifier. the following PTX instruction sequence might be used: @!p L1: setp.s32 p. predicate registers are virtual and have . add. use a predicate to control the execution of the branch or call instructions. Instructions without a guard predicate are executed unconditionally. // p = (i < n) // if i < n.lt. j. q. n.s32 p.0 8. So. Predicates are most commonly set as the result of a comparison performed by the setp instruction.pred p. consider the high-level code if (i < n) j = j + 1.PTX ISA Version 2. add. branch over 56 January 24. i. add 1 to j To get a conditional branch or conditional function call. 1. … // compare i to n // if false. As an example.

Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.3. unsigned integer. lt (less-than). Unsigned Integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Table 15. Table 16. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).3. ordering comparisons are not defined for bit-size types. hi (higher).1. The unsigned comparisons are eq. and hs (higher-or-same). and bitsize types. The following table shows the operators for signed integer.1. Comparisons 8. lo (lower). le. the result is false. If either operand is NaN. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. gt. le (less-than-or-equal). ne (not-equal). ls (lower-or-same). 2010 57 . ge.3.1.Chapter 8. ne. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. Instruction Set 8. lt. ne. The bit-size comparisons are eq and ne. and ge (greater-than-or-equal).1.2. gt (greater-than).

leu. Table 17. then the result of these comparisons is true.3.0 To aid comparison operations in the presence of NaN values. There is no direct conversion between predicates and integer values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. xor. neu. then these comparisons have the same result as their ordered counterparts. and mov. setp can be used to generate a predicate from an integer.u32 %r1. If both operands are numeric values (not NaN).2. num returns true if both operands are numeric values (not NaN).0. geu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. ltu. gtu. However. for example: selp.%p. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.1. If either operand is NaN.PTX ISA Version 2. two operators num (numeric) and nan (isNaN) are provided. Table 18. 2010 . Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. or. not. and nan returns true if either operand is NaN. unordered versions are included: equ. and no direct way to load or store predicate register values. // convert predicate to 32-bit value 58 January 24.

the add instruction requires type and size information to properly perform the addition operation (signed. different sizes).u16 d.u16 a. a.f32 d. float. b.u16 d.Chapter 8. It requires separate type-size modifiers for the result and source. Floating-point types agree only if they have the same size. and this information must be specified as a suffix to the opcode. cvt. and these are placed in the same order as the operands.u16 d. add. most notably the data conversion instruction cvt. and integer operands are silently cast to the instruction type if needed.uX . . For example.sX ok ok ok inv .f32. 2010 59 . a. Table 19. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.e. Type Checking Rules Operand Type .4. they must match exactly.sX .fX ok inv inv ok Instruction Type . a. Example: . unsigned.bX . • The following table summarizes these type checking rules.bX . For example: . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. Signed and unsigned integer types agree provided they have the same size.reg .. b. i.fX ok ok ok ok January 24.reg .reg .uX ok ok ok inv . For example. Instruction Set 8.

The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. 1.1. so that narrow values may be loaded. the data will be truncated.4. stored. The data is truncated to the instruction-type size and interpreted according to the instruction type. or converted to other types and sizes. 60 January 24. When a source operand has a size that exceeds the instruction-type size. Bit-size source registers may be used with any appropriately-sized instruction type. floating-point instruction types still require that the operand type-size matches exactly. ld. no conversion needed. When used with a narrower bit-size type. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. 4. The following table summarizes the relaxed type-checking rules for source operands. the cvt instruction does not support . Notes 3. 2.0 8. Table 20. “-“ = allowed. parse error. Note that some combinations may still be invalid for a particular instruction. Source register size must be of equal or greater size than the instruction-type size. the size must match exactly.PTX ISA Version 2. Operand Size Exceeding Instruction-Type Size For convenience. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. unless the operand is of bit-size type. for example. When used with a floating-point instruction type. Floating-point source registers can only be used with bit-size or floating-point instruction types. st. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. inv = invalid.bX instruction types. so those rows are invalid for cvt. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. stored. and converted using regular-width registers. For example. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 2010 .

the destination data is zero. Bit-size destination registers may be used with any appropriately-sized instruction type. 2010 61 . Destination register size must be of equal or greater size than the instruction-type size. When used with a floatingpoint instruction type. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. the size must match exactly. 2. “-“ = Allowed but no conversion needed. the data is sign-extended. Instruction Set When a destination operand has a size that exceeds the instruction-type size. inv = Invalid. Floating-point destination registers can only be used with bit-size or floating-point instruction types. zext = zero-extend. parse error. When used with a narrower bit-size instruction type. 4. Notes 3. Table 21. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. The following table summarizes the relaxed type-checking rules for destination operands. the data will be zero-extended. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. If the corresponding instruction type is signed integer.or sign-extended to the size of the destination register. and is zero-extended to the destination register width otherwise. The data is signextended to the destination register width for signed integer instruction types. January 24. The data is sign-extended to the destination register width for signed integer instruction types.Chapter 8. the data is zeroextended. 1. otherwise.

62 January 24. until C is not expressive enough. 8. so it is important to have divergent threads re-converge as soon as possible. 16-bit registers in PTX are mapped to 32-bit physical registers. If threads execute down different control flow paths. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. 2010 . Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. a compiler or code author targeting PTX can ignore the issue of divergent threads. or conditional return. Divergence of Threads in Control Constructs Threads in a CTA execute together. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. using the .1.5. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. the threads are called divergent. the semantics of 16-bit instructions in PTX is machine-specific. These extra precision bits can become visible at the application level. 8. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. until they come to a conditional control construct such as a conditional branch. the optimizing code generator automatically determines points of re-convergence. and 16-bit computations are “promoted” to 32-bit computations.uni suffix. by a right-shift instruction. However. At the PTX language level. A compiler or programmer may chose to enforce portable. Both situations occur often in programs.PTX ISA Version 2. The semantics are described using C. For divergent control flow. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. If all of the threads act in unison and follow a single control flow path.6. for example. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. and for many applications the difference in execution is preferable to limiting performance. this is not desirable. at least in appearance. for many performance-critical applications. conditional function call. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. Therefore.6.0 8. When executing on a 32-bit data path. the threads are called uniform. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.

Chapter 8. Instructions All PTX instructions may be predicated.cc.cc.7. Instruction Set 8.7. addc sub. The Integer arithmetic instructions are: add sub add. the optional guard predicate is omitted from the syntax. 2010 63 .1. In the following descriptions. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. 8.

a. . Applies only to . sub.s32 d. add.0. a.u64. b. a. b.s32 type. .0 Table 22. d = a + b.u32.type add{. @p add.type = { .c.s32 .sat applies only to . .s32. . .sat applies only to . PTX ISA Notes Target ISA Notes Examples 64 January 24. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Introduced in PTX ISA version 1.sat limits result to MININT. . d = a – b. Description Semantics Notes Performs addition and writes the resulting value into a destination register. // . Saturation modifier: . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. // . Applies only to . .z.s32 c.u32. sub. 2010 .MAXINT (no overflow) for the size of the operation. Supported on all target architectures.s16. .0.sat}.s32 d...MAXINT (no overflow) for the size of the operation.s16. PTX ISA Notes Target ISA Notes Examples Table 23.type = { .sat}.1.a.b.u16.s64 }. add.s64 }. b. . Saturation modifier: .s32 .sat.s32 c. d.u32 x.sat limits result to MININT.u64.s32. a. . add Syntax Integer Arithmetic Instructions: add Add two values.y.s32 type.type sub{.u16. b.PTX ISA Version 2. d. Introduced in PTX ISA version 1. Supported on all target architectures.

Behavior is the same for unsigned and signed integers.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.b32 addc.CF) holding carry-in/carry-out or borrowin/borrow-out. and there is no support for setting. No saturation.y1. x4.y3. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. a.b32 x1. sub.2.CF. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. b.y1. addc.z4.z1.y3.z1.b32 addc.2. .cc Add two values with carry-out. Supported on all target architectures. @p @p @p @p add. 2010 65 . Instruction Set Instructions add.type = { .b32 addc. Introduced in PTX ISA version 1. No saturation. add. addc{.cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. x4. Behavior is the same for unsigned and signed integers.b32 x1. Table 24. No other instructions access the condition code.b32 addc.cc.type = {.z4.z3. a. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.y2.cc.y2.cc.z3.type d. Supported on all target architectures.cc.cc.s32 }. clearing.y4.cc Syntax Integer Arithmetic Instructions: add.y4.CF No integer rounding modifiers. carry-out written to CC. x3. x2. b. d = a + b + CC.cc.cc}. if .u32.Chapter 8. . @p @p @p @p add.b32 addc.cc. .cc. .cc specified. Introduced in PTX ISA version 1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. d = a + b. x2. or testing the condition code.u32.type d. carry-out written to CC.z2.b32 addc. These instructions support extended-precision integer addition and subtraction. x3.s32 }. add.CF No integer rounding modifiers.cc.z2.

z3. withborrow-in and optional borrow-out. sub.0 Table 26. Supported on all target architectures. x3.b32 x1.z4. borrow-out written to CC.cc Syntax Integer Arithmetic Instructions: sub. . x2. sub.z3.y1. b.cc}.CF).cc specified.y1.3. Supported on all target architectures.cc. No saturation. a. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.z1. borrow-out written to CC.b32 subc. b. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. @p @p @p @p sub. x2. subc{. No saturation.cc. Introduced in PTX ISA version 1.y3. Behavior is the same for unsigned and signed integers.y4.y2.cc. @p @p @p @p sub.z2.type d.CF No integer rounding modifiers.(b + CC.cc. x4. if .z1. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. .cc.b32 subc. x3.3.b32 x1.y2. d = a – b. Behavior is the same for unsigned and signed integers.cc Subract one value from another.z2. with borrow-out.u32. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. .z4. x4.PTX ISA Version 2.s32 }.type d.cc.cc. Introduced in PTX ISA version 1.cc.CF No integer rounding modifiers.b32 subc.u32.cc.b32 subc.y3.s32 }. a.type = { .b32 subc. 2010 . .y4.b32 subc.type = {. d = a .

mul{. .u64. a.u32.lo.type d.hi or . creates 64 bit result January 24. 2010 67 .Chapter 8. Description Semantics Compute the product of two values. If . d = t<n-1.wide is specified.and 32-bit integer types. then d is twice as wide as a and b to receive the full result of the multiplication.fxs. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.x. . and either the upper or lower half of the result is written to the destination register.s16 fa..fxs. mul.hi variant // for . .hi. . .s32.fys.u16.type = { . mul.s16.wide // for . t = a * b.wide.0.s16 fa.wide. n = bitwidth of type. Instruction Set Table 28. d = t<2n-1. d = t. mul..y. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. then d is the same size as a and b.n>. // for .lo variant Notes The type of the operation represents the types of the a and b operands. Supported on all target architectures.lo.s32 z. save only the low 16 bits // 32*32 bits.. b. .0>.s64 }.wide suffix is supported only for 16.. The . If . // 16*16 bits yields 32 bits // 16*16 bits.wide}.lo is specified.fys.

lo is specified.hi. b. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. Supported on all target architectures. t + c. . a.c.wide suffix is supported only for 16. @p mad..s32 r. mad. .lo. . c.q. If . 2010 .sat.s32 d.type = { .lo variant Notes The type of the operation represents the types of the a and b operands. 68 January 24. t<2n-1. bitwidth of type.hi.r.lo.hi or .type mad.0.s32. The . // for .u32.wide is specified.MAXINT (no overflow) for the size of the operation. and then writes the resulting value into a destination register.a.b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi mode. d.lo. . Saturation modifier: . .u16.s16.hi variant // for .PTX ISA Version 2. a.p.u64.. t<n-1.. then d and c are the same size as a and b. t n d d d = = = = = a * b.s32 type in .0 Table 29. .s32 d. Description Semantics Multiplies two values and adds a third..wide // for .wide}. and either the upper or lower half of the result is written to the destination register.0> + c. Applies only to .and 32-bit integer types. then d and c are twice as wide as a and b to receive the result of the multiplication.. b. If .sat limits result to MININT. mad{.s64 }.n> + c. c.

a.hi may be less efficient on machines without hardware support for 24-bit multiply. d = t<47. d = t<31.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.Chapter 8.u32. All operands are of the same type and size.a.lo}.type = { . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // low 32-bits of 24x24-bit signed multiply. Instruction Set Table 30. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. 2010 69 . and return either the high or low 32-bits of the 48-bit result.s32 }.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. 48bits. t = a * b. mul24. mul24.b. i.lo.16>.0>.. mul24{.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24..s32 d. Supported on all target architectures. .0.hi.e. . January 24.hi variant // for . // for .type d. b. mul24.

sat. 70 January 24. d = t<47.lo. d = t<31. Applies only to . All operands are of the same type and size. mad24{. // for . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.a. Return either the high or low 32-bits of the 48-bit result.0> + c.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.e.type = { .u32. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. Description Compute the product of two 24-bit integer values held in 32-bit source registers. 2010 . mad24.hi.c. a. 48bits. a.s32 d.hi may be less efficient on machines without hardware support for 24-bit multiply. ... d.s32 }.type mad24. Saturation modifier: .sat limits result of 32-bit signed addition to MININT. Supported on all target architectures.MAXINT (no overflow). mad24.PTX ISA Version 2. b.hi mode. mad24. c.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. t = a * b.0 Table 31.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.s32 d.. mad24. 32-bit value to either the high or low 32-bits of the 48-bit result. // low 32-bits of 24x24-bit signed multiply.b.hi.16> + c. c.hi variant // for . b.0.lo}.. .s32 type in . i. and add a third.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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. a. X.b64 d. inclusively. mask = 0x8000000000000000. clz. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. mask = 0x80000000. the number of leading zeros is between 0 and 64. popc Syntax Integer Arithmetic Instructions: popc Population count. . a = a << 1. .type == . Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.0 Table 39.type d. a = a >> 1. . d = 0.b32.b64 }. if (.PTX ISA Version 2. popc. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. while (a != 0) { if (a&0x1) d++. clz.u32 PTX ISA Notes Target ISA Notes Examples Table 40. } else { max = 64.b64 }. the number of leading zeros is between 0 and 32. a. popc.type d.0. // cnt is .0.b32 clz.u32 Semantics 74 January 24.b32) { max = 32.type = { . 2010 . a. cnt.b64 type. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. popc requires sm_20 or later. For . } Introduced in PTX ISA version 2. cnt.b64 d.type = { .b32 type.b32 popc. d = 0.b32. inclusively. clz requires sm_20 or later. For . a. // cnt is . } while (d < max && (a&mask == 0) ) { d++. X.

bfind. Operand a has the instruction type.Chapter 8. bfind. For signed integers. d = -1. // cnt is .s64 cnt. bfind. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a. . Semantics msb = (.s32. } } if (.s64 }. and operand d has type .type d.0. .shiftamt && d != -1) { d = msb . 2010 75 . X.type = { . break. . For unsigned integers.type bfind.shiftamt.s32) ? 31 : 63.u64. a.u32 January 24. . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. d. bfind requires sm_20 or later. If .shiftamt is specified.type==.type==.u32.shiftamt. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. Description Find the bit position of the most significant non-sign bit in a and place the result in d. Instruction Set Table 41.d. bfind returns 0xFFFFFFFF if no non-sign bit is found.u32 d. i>=0. i--) { if (a & (1<<i)) { d = i.u32.u32 || . a. for (i=msb. bfind returns the bit position of the most significant “1”.

brev requires sm_20 or later.type==. brev. i<=msb. a. 76 January 24.b32. brev.0.type = { . .b32 d. Description Semantics Perform bitwise reversal of input.0 Table 42. for (i=0. 2010 .PTX ISA Version 2. .type d. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. a. i++) { d[i] = a[msb-i]. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. msb = (.b32) ? 31 : 63.b64 }.

s32) ? 31 : 63.u64: .start.s64 }. If the start position is beyond the msb of the input.msb)]. else sbit = a[min(pos+len-1.type d. d = 0. for (i=0.type==.u32.u64. bfe. the destination d is filled with the replicated sign bit of the extracted field.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. len = c. . bfe requires sm_20 or later. and operands b and c are type .u32 || .a. i<=msb.0. Instruction Set Table 43.u32 || . and source c gives the bit field length in bits. Source b gives the bit field starting bit position. . .u32. c. .b32 d.s32. if (. otherwise If the bit field length is zero.u64 || len==0) sbit = 0.type==.Chapter 8. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. b. the result is zero.len. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. .s32. Semantics msb = (.type==. pos = b. Operands a and d have the same type as the instruction type. January 24. The sign bit of the extracted field is defined as: . The destination d is padded with the sign bit of the extracted field.u32. a.type==. Description Extract bit field from a and place the zero or sign-extended result in d. 2010 77 . bfe.type = { . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .

i++) { f[pos+i] = a[i].u32.start. If the start position is beyond the msb of the input.type==.b32) ? 31 : 63. pos = c. and operands c and d are type . Semantics msb = (.0. for (i=0. . . c.type = { . 78 January 24. b. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.b32. bfi requires sm_20 or later. the result is b. i<len && pos+i<=msb. the result is b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfi. f = b.type f. b. len = d. 2010 .0 Table 44. and f have the same type as the instruction type.b32 d. a. If the bit field length is zero. Operands a.a. Description Align and insert a bit field from a into b.PTX ISA Version 2. d.b64 }.len. and place the result in f. and source d gives the bit field length in bits.b. Source c gives the starting bit position for the insertion. bfi.

b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. b0}}. {b3. b2. Description Pick four arbitrary bytes from two 32-bit registers.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.rc8. msb=0 means copy the literal value. In the generic form (no mode specified).b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. 2010 79 . default mode index d.Chapter 8.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.rc16 }. . Instruction Set Table 45. the four 4-bit values fully specify an arbitrary byte permute.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. a 4-bit selection value is defined.b2 source select c[11:8] d.ecl. as a 16b permute code.b32{. the permute control consists of four 4-bit selection values. Thus. The msb defines if the byte value should be copied. and reassemble them into a 32-bit destination register. msb=1 means replicate the sign. b4}. b6. . . . a.b1 source select c[7:4] d. b.mode = { . Note that the sign extension is only performed as part of generic form. prmt. The bytes in the two source registers are numbered from 0 to 7: {b.f4e. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.ecr. For each byte in the target register.mode} d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. c. a} = {{b7. b5. .b3 source select c[15:12] d. . b1.b4e.

ctl[2]. r2. r3.0 Semantics tmp64 = (b<<32) | a. ctl[0]. r3. r2. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r4. ctl[1] = (c >> 4) & 0xf. ctl[1].b32 prmt.f4e r1. tmp64 ). tmp64 ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prmt.0.b32. 2010 . r1. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. prmt requires sm_20 or later. ctl[2] = (c >> 8) & 0xf. tmp64 ). ctl[3]. } tmp[07:00] = ReadByte( mode. tmp[15:08] = ReadByte( mode. tmp[23:16] = ReadByte( mode. ctl[3] = (c >> 12) & 0xf.PTX ISA Version 2. 80 January 24. r4. tmp[31:24] = ReadByte( mode.

7.2.f64 register operands and constant immediate values.Chapter 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Floating-Point Instructions Floating-point instructions operate on .f32 and . 2010 81 . Instruction Set 8.

min. 2010 .rnd.max}.neg.neg.sqrt}. Single-precision add.32 and fma.f32 are the same.f32 rsqrt.f64 rsqrt.approx.min.max}.rcp.rnd.approx. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.0 The following table summarizes floating-point instructions in PTX.rnd.sub. No rounding modifier.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 {mad.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.rz .f64 {abs. 1.approx.approx.sat Notes If no rounding modifier is specified. with NaNs being flushed to positive zero.rnd.fma}.f64 are the same. If no rounding modifier is specified.lg2.rcp.f32 {add.rnd. and mad support saturation of results to the range [0.rm .full.mul}.f32 {div.ex2}.f32 {abs.cos.f64 mad.sqrt}.f64 div.rcp.target sm_1x No rounding modifier. . . 82 January 24. NaN payloads are supported for double-precision instructions. so PTX programs should not rely on the specific single-precision NaNs being generated.target sm_20 .0].sqrt}.mul}.rnd.rn . Note that future implementations may support NaN payloads for single-precision instructions.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.0. {add.f64 and fma.fma}. default is .ftz .rp . Instruction Summary of Floating-Point Instructions . default is . Double-precision instructions support subnormal inputs and results.f32 . {mad.PTX ISA Version 2. Table 46. mul.f32 {div. but single-precision instructions return an unspecified NaN.target sm_20 mad. sub.rn and instructions may be folded into a multiply-add.f64 {sin.sub.rn and instructions may be folded into a multiply-add. The optional .f32 {div.

Instruction Set Table 47. .f32 copysign.normal testp.0. .subnormal }. z.f32 testp. copysign. testp requires sm_20 or later. b. testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . // result is .notanumber.f32. positive and negative zero are considered normal numbers. and return the result as d.f64 x. a. C. . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. A. a. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. B. not infinity) As a special case.op.notanumber.Chapter 8. copysign requires sm_20 or later.number testp. y. .f64 }. 2010 83 . copysign.f64 }. testp. p. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.op p.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.type = { . Introduced in PTX ISA version 2.finite testp.type = { .type d.infinite. f0.number.notanumber testp.infinite testp. not infinity). Table 48. testp Syntax Floating-Point Instructions: testp Test floating-point property. . . testp.normal.f64 isnan. . January 24.0.finite.f32.type . X.pred = { .infinite. true if the input is a subnormal number (not NaN. .

NaN results are flushed to +0. add Syntax Floating-Point Instructions: add Add two values. Rounding modifiers (default is .f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Saturation modifier: . a.f64.rm mantissa LSB rounds towards negative infinity .0]. 2010 . d = a + b. add.f64 d.rn): .f32 f1.rm.ftz.0 Table 49. 84 January 24.rz mantissa LSB rounds towards zero .0.f32.rn mantissa LSB rounds to nearest even . add. .sat}. In particular.rp for add.f2.f3. d.rnd = { . . add. b. add. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.0f. add{. .rn.f64 requires sm_13 or later. .rnd}{.ftz}{. sm_1x: add.0. b.f64 supports subnormal numbers.rn.f32 add{. 1. subnormal numbers are supported.rz. .ftz.rnd}. Description Semantics Notes Performs addition and writes the resulting value into a destination register.rz available for all targets . a. Rounding modifiers have the following target requirements: . requires sm_13 for add.rp }.f32 flushes subnormal inputs and results to sign-preserving zero. .rz. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 supported on all target architectures.rm.f32 clamps the result to [0. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.sat. requires sm_20 Examples @p add.PTX ISA Version 2. add.

rm.rp for sub.f64.0f. subnormal numbers are supported. sub. sub.f32 flushes subnormal inputs and results to sign-preserving zero. b. sm_1x: sub.0]. a. In particular.rz available for all targets .f64 requires sm_13 or later.rp }.rnd = { .f64 d. Instruction Set Table 50.rm.rn. 2010 85 .rn mantissa LSB rounds to nearest even . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rn): .f32. .f32 c.f32 supported on all target architectures. requires sm_13 for sub. . b. January 24. . d.b. NaN results are flushed to +0. sub Syntax Floating-Point Instructions: sub Subtract one value from another.rnd}. Rounding modifiers (default is . requires sm_20 Examples sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. sub{. d = a . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. . sub.f2.f32 sub{. .ftz}{.rz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1.rm mantissa LSB rounds towards negative infinity .0. . Rounding modifiers have the following target requirements: . Saturation modifier: sub.f64 supports subnormal numbers.f32 clamps the result to [0.rz mantissa LSB rounds towards zero . a.a. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f3.rn.ftz.0.rn.b.sat.Chapter 8. sub.ftz.f32 f1. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.sat}.rnd}{. sub.

a.rnd}. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rnd = { . Rounding modifiers (default is .0.sat}.0 Table 51. mul. Saturation modifier: mul.0. . In particular. mul Syntax Floating-Point Instructions: mul Multiply two values.rm. .rn): .ftz.0].f64 supports subnormal numbers. .f64 d. 2010 .rm mantissa LSB rounds towards negative infinity . requires sm_20 Examples mul.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. mul. .f32 clamps the result to [0. . mul. 1.0f.ftz}{. mul{.rz mantissa LSB rounds towards zero .f32. mul.f32 flushes subnormal inputs and results to sign-preserving zero.rp }. d. all operands must be the same size.rz available for all targets . A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm. d = a * b.f32 circumf. b.rn. Description Semantics Notes Compute the product of two values.rn. NaN results are flushed to +0. . subnormal numbers are supported.rn mantissa LSB rounds to nearest even .rnd}{. sm_1x: mul.pi // a single-precision multiply 86 January 24.ftz.f64 requires sm_13 or later. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rp for mul.sat. requires sm_13 for mul. For floating-point multiplication.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b.f64.PTX ISA Version 2.f32 mul{. a.radius.rz. Rounding modifiers have the following target requirements: .

a. . Saturation: fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.b.ftz}{. 1. again in infinite precision. . fma. subnormal numbers are supported. d.rnd = { .4.0.f64 w.sat.0f.f64 d.z.f64 requires sm_13 or later.rn.rn. b.x. The resulting value is then rounded to single precision using the rounding mode specified by . NaN results are flushed to +0.f64 computes the product of a and b to infinite precision and then adds c to this product. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rn mantissa LSB rounds to nearest even . Instruction Set Table 52. c. fma.f32 fma. 2010 87 . sm_1x: fma. fma. d.rm mantissa LSB rounds towards negative infinity .f32 introduced in PTX ISA version 2.f64 is the same as mad. a.rnd{.rp }.0].rn.f32 clamps the result to [0. fma. fma. fma.f32 is unimplemented in sm_1x. c.Chapter 8.rnd. fma. b.rz mantissa LSB rounds towards zero . @p fma. .f32 fma. again in infinite precision.f64.rnd. fma.ftz.f32 requires sm_20 or later. d = a*b + c. PTX ISA Notes Target ISA Notes Examples January 24.rnd. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma.f64 introduced in PTX ISA version 1. fma.c. .rm.rz.f32 computes the product of a and b to infinite precision and then adds c to this product.f64 supports subnormal numbers.sat}.ftz.0. The resulting value is then rounded to double precision using the rounding mode specified by .f32 flushes subnormal inputs and results to sign-preserving zero. Rounding modifiers (no default): .a.y.

Description Semantics Notes Multiplies two values and adds a third. .f32 is identical to the result computed using separate mul and add instructions. but the exponent is preserved.ftz. Unlike mad. and then writes the resulting value into a destination register. again in infinite precision..f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.f32 computes the product of a and b to infinite precision and then adds c to this product. Note that this is different from computing the product with mul. d = a*b + c.f32). For .{f32.{f32. mad. // . fma. . a.f64 is the same as fma. c. mad. again in infinite precision.rp }.rnd.f64 supports subnormal numbers.rnd. mad.sat.rm.target sm_1x d.target sm_13 and later .0 Table 53.rnd = { . For .target sm_1x: mad.f32 is when c = +/-0. Rounding modifiers (no default): . where the mantissa can be rounded and the exponent will be clamped.ftz.f32 mad. The exception for mad.0]. b.0f. mad. b. The resulting value is then rounded to single precision using the rounding mode specified by .rnd.0. // .rn.f32 mad.sat}.rnd. mad{.PTX ISA Version 2. // . 88 January 24. a. the treatment of subnormal inputs and output follows IEEE 754 standard. NaN results are flushed to +0.rz. sm_1x: mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. mad.f64 computes the product of a and b to infinite precision and then adds c to this product. again in infinite precision.sat}. mad. In this case.ftz}{. 2010 . and then the mantissa is truncated to 23 bits. b. Saturation modifier: mad. c.f32.f32 is implemented as a fused multiply-add (i. .f64 computes the product of a and b to infinite precision and then adds c to this product.f64.f32 computes the product of a and b at double precision. subnormal numbers are supported. The resulting value is then rounded to double precision using the rounding mode specified by .rm mantissa LSB rounds towards negative infinity .f32 clamps the result to [0. mad.0.target sm_20: mad. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.rnd{. c.target sm_20 d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64} is the same as fma.rn. a. The resulting value is then rounded to double precision using the rounding mode specified by .rz mantissa LSB rounds towards zero . mad.e.ftz}{.f64 d. 1.0 devices. When JIT-compiled for SM 2.rn mantissa LSB rounds to nearest even .f64}. mad.

c.f64. In PTX ISA versions 2.rn. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.a. Target ISA Notes mad. requires sm_13 .f64.b.. 2010 89 . a rounding modifier is required for mad.rz.rm...f64 requires sm_13 or later. January 24.rm.rz.f64 instructions having no rounding modifier will map to mad.rn.. requires sm_20 Examples @p mad. Rounding modifiers have the following target requirements: .f32 for sm_20 targets.f32 d.0 and later.rp for mad.4 and later.f32 supported on all target architectures.. a rounding modifier is required for mad.0.Chapter 8.rp for mad.f32. Legacy mad.. In PTX ISA versions 1.rn. mad.f64.

b.full.rnd.PTX ISA Version 2.f64.ftz}. d. a. the maximum ulp error is 2. d.full. but is not fully IEEE 754 compliant and does not support rounding modifiers. and rounding introduced in PTX ISA version 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. div.approx. approximate division by zero creates a value of infinity (with same sign as a). div.0 through 1. b.ftz.ftz.0 Table 54.rm mantissa LSB rounds towards negative infinity . sm_1x: div. PTX ISA Notes div.4.approx.f64 supports subnormal numbers. . computed as d = a * (1/b). Fast. 2126]. stores result in d. yd.f32 implements a relatively fast.f64 diam. b. y. Description Semantics Notes Divides a by b. a. Fast.f32.rn.f32 div.full.approx. and div.approx.f32 defaults to div.ftz}.{rz.approx{. div Syntax Floating-Point Instructions: div Divide one value by another.f64 requires sm_13 or later. Subnormal inputs and results are flushed to sign-preserving zero. div.4 and later.rnd is required.f64 defaults to div.rnd{.approx.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { . approximate single-precision divides: div.rn.3. For PTX ISA versions 1.rn mantissa LSB rounds to nearest even . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . . b. . d.0. div. d = a / b.rn. zd. . subnormal numbers are supported.rz.full.ftz}.rm. The maximum ulp error is 2 across the full range of inputs.f32 requires sm_20 or later. x.f32 implements a fast approximation to divide. . Explicit modifiers .rp}.f32 supported on all target architectures.approx.f64 introduced in PTX ISA version 1.f32 div.ftz.f32 and div. 2010 . For b in [2-126.rnd.14159. .f32 div.f32 flushes subnormal inputs and results to sign-preserving zero.3.ftz.ftz. a. div. // // // // fast.full. div.full{.rp }. Examples 90 January 24. z.f32 div. or .f32 and div. one of .rz mantissa LSB rounds towards zero . For PTX ISA version 1.circum.f64 requires sm_20 or later. Target ISA Notes div.rn. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . full-range approximation that scales operands to achieve better accuracy.rm. a. div.f32 div. xd. div. div.

Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. subnormal numbers are supported. abs. NaN inputs yield an unspecified NaN.0. a.0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero.f32 neg.ftz. sm_1x: abs. NaN inputs yield an unspecified NaN. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. neg. d = |a|. Subnormal numbers: sm_20: By default. abs. abs.f32 x. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs. d.f64 requires sm_13 or later. abs{. subnormal numbers are supported.f64 d.ftz}.f64 supports subnormal numbers. neg. d. Take the absolute value of a and store the result in d.f32 supported on all target architectures. Negate the sign of a and store the result in d. Instruction Set Table 55.ftz}. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.ftz.f32 x. Table 56.f0.f64 requires sm_13 or later.f64 d. d = -a. neg{. sm_1x: neg.f32 abs. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. January 24.Chapter 8.ftz. 2010 91 . neg. a. abs.f0.f32 supported on all target architectures.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. a.ftz. neg.

0 Table 57. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. Store the minimum of a and b in d.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. max. a. d d d d = = = = NaN.0.f32 max.f32 min. sm_1x: max.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.ftz. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. min.c.f32 supported on all target architectures. d d d d = = = = NaN.0.f64 z. b. subnormal numbers are supported. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b.f64 f0. max.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero. a. Table 58.f32 supported on all target architectures. max{.b. a. 92 January 24. max.f64 d. b. a. min.ftz}.f64 d. d. max.ftz.f1.z. (a > b) ? a : b. min. a. sm_1x: min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.PTX ISA Version 2. b. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. max.f64 supports subnormal numbers. a. 2010 . min{. @p min.x.ftz.f64 requires sm_13 or later. d. a. min.ftz.f32 max. b. b.f32 min. Store the maximum of a and b in d.b. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f2. (a < b) ? a : b.c.ftz}.

approx.approx. Description Semantics Notes Compute 1/a. rcp.rnd.f64 and explicit modifiers . rcp.4 and later. rcp.rn. Instruction Set Table 59.4.f32.f32 rcp.f64 ri.f64 introduced in PTX ISA version 1.ftz.rnd is required.rn. Target ISA Notes rcp.f32 rcp.rnd = { . one of .ftz}.f64 supports subnormal numbers.approx.f32 requires sm_20 or later.ftz.f32 implements a fast approximation to reciprocal. d.rn mantissa LSB rounds to nearest even . General rounding modifiers were added in PTX ISA version 2.f64 requires sm_20 or later. rcp.rn.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.ftz. rcp. rcp.ftz. xi.rnd{. PTX ISA Notes rcp.f64.rz.approx and .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 rcp. store result in d.rp }. rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. xi.0 through 1.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 defaults to rcp.f32 and rcp.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. For PTX ISA version 1.ftz}. For PTX ISA versions 1.approx.f64 d.0 over the range 1. a.0-2.r.rz mantissa LSB rounds towards zero .ftz were introduced in PTX ISA version 1.x.rm.0.f64 requires sm_13 or later. d = 1 / a.rn.3.approx or .rm.0. 2010 93 . . Examples January 24.x.{rz.rnd. .rn. .f32 supported on all target architectures.approx{.f32 rcp.rm mantissa LSB rounds towards negative infinity . and rcp.Chapter 8. sm_1x: rcp.rn.f32 defaults to rcp. // fast.0 -Inf -Inf +Inf +Inf +0. The maximum absolute error is 2-23.0 +subnormal +Inf NaN Result -0.rp}. a. rcp.0 +0. rcp. a.0. Input -Inf -subnormal -0. d.

f32 sqrt. sqrt.approx{.f64 requires sm_13 or later.rp }. The maximum absolute error for sqrt.rn.x.0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.x. .0 +0. General rounding modifiers were added in PTX ISA version 2.approx.approx and . r.f32 requires sm_20 or later. approximate square root d. sqrt. sqrt.f32 supported on all target architectures.ftz.f64 supports subnormal numbers. sqrt.rn. sqrt.f32 and sqrt.approx.rp}.rnd.x.f64 d.0 +subnormal +Inf NaN Result NaN NaN -0.ftz. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. a. Description Semantics Notes Compute sqrt(a).{rz. 2010 .rm.ftz. // IEEE 754 compliant rounding d.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32. Input -Inf -normal -subnormal -0.f64 and explicit modifiers . sqrt.rnd = { . store in d. and sqrt. For PTX ISA versions 1.rz. a. For PTX ISA version 1. // IEEE 754 compliant rounding .0 +0.f32 is TBD.rnd{.rn mantissa LSB rounds to nearest even .f32 sqrt.rm mantissa LSB rounds towards negative infinity .f64 introduced in PTX ISA version 1. Target ISA Notes sqrt.4.rn.ftz}. // fast.f64 requires sm_20 or later.ftz}.approx.ftz.0 +0. a.rn. PTX ISA Notes sqrt. sqrt.approx.rnd is required.rm. .0 through 1.0 Table 60. sqrt.0.ftz were introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero .4 and later.PTX ISA Version 2.f32 defaults to sqrt.3. r.f64. sm_1x: sqrt.0 -0. Examples 94 January 24.f32 sqrt.f64 r.rn.rnd.f64 defaults to sqrt. one of . d = sqrt(a). subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.approx or . .f32 sqrt.approx.f32 implements a fast approximation to square root.rn.

f32. X.f32 flushes subnormal inputs and results to sign-preserving zero. Input -Inf -normal -subnormal -0. and rsqrt.4 and later. ISR.0. For PTX ISA version 1.4. subnormal numbers are supported.f64 d.f32 and rsqrt.0 through 1.ftz.f64 is TBD.f64 supports subnormal numbers.ftz were introduced in PTX ISA version 1.ftz.0.0 NaN The maximum absolute error for rsqrt.f32 defaults to rsqrt. rsqrt.4 over the range 1. rsqrt.f64 isr. rsqrt. store the result in d. sm_1x: rsqrt.f32 rsqrt. Note that rsqrt.f64. rsqrt.approx. the .approx. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. d = 1/sqrt(a). January 24.f64 requires sm_13 or later.f32 rsqrt.f64 were introduced in PTX ISA version 1.ftz.approx{.approx. For PTX ISA versions 1.f32 is 2-22. rsqrt.0 +0.approx.f64 defaults to rsqrt. 2010 95 .ftz}.approx modifier is required.approx and . rsqrt.0-4. Target ISA Notes Examples rsqrt. Explicit modifiers . a.approx. a.approx.approx implements an approximation to the reciprocal square root.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 61.f64 is emulated in software and are relatively slow. x. The maximum absolute error for rsqrt. d.f32 supported on all target architectures. PTX ISA Notes rsqrt. rsqrt. Subnormal numbers: sm_20: By default. Compute 1/sqrt(a).3.Chapter 8.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.

Explicit modifiers . a. sin.ftz introduced in PTX ISA version 1.approx modifier is required.f32 flushes subnormal inputs and results to sign-preserving zero.f32 d. the .approx. sin.approx.approx{.0 +0. sin.ftz.0 +0.0 +0. a.0 through 1.4 and later.0 NaN NaN The maximum absolute error is 2-20.0 +subnormal +Inf NaN Result NaN -0.0 Table 62.ftz. Input -Inf -subnormal -0. sin. 2010 . d = sin(a).ftz.ftz}. For PTX ISA version 1.approx and .4.f32.approx. PTX ISA Notes sin.0.9 in quadrant 00.0 -0. sin. For PTX ISA versions 1.3.f32 implements a fast approximation to sine. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. 96 January 24. sm_1x: Subnormal inputs and results to sign-preserving zero. Find the sine of the angle a (in radians). subnormal numbers are supported. Target ISA Notes Examples Supported on all target architectures.PTX ISA Version 2.f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default.f32 defaults to sin.f32 sa.

approx and .approx.0 +1. a.f32 introduced in PTX ISA version 1.4. For PTX ISA versions 1.4 and later. cos.approx modifier is required. January 24. For PTX ISA version 1.f32 ca. Explicit modifiers .0 +0. Target ISA Notes Examples Supported on all target architectures.ftz. PTX ISA Notes cos.approx. d = cos(a).approx. cos. 2010 97 .f32. cos. Input -Inf -subnormal -0.f32 implements a fast approximation to cosine.ftz.0 through 1. subnormal numbers are supported.ftz introduced in PTX ISA version 1. a. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz.0 +subnormal +Inf NaN Result NaN +1.3. cos. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 NaN NaN The maximum absolute error is 2-20.Chapter 8. Instruction Set Table 63.f32 defaults to cos.ftz}. Subnormal numbers: sm_20: By default. the .f32 d. cos. Find the cosine of the angle a (in radians).f32 flushes subnormal inputs and results to sign-preserving zero.9 in quadrant 00.0 +1.0 +1.approx{.0.

sm_1x: Subnormal inputs and results to sign-preserving zero. 98 January 24. a.f32 introduced in PTX ISA version 1.0.6 for mantissa. Subnormal numbers: sm_20: By default.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. lg2.3.0 Table 64.f32 Determine the log2 of a. Input -Inf -subnormal -0. lg2.0 through 1.0 +0.4 and later. lg2.approx.f32 flushes subnormal inputs and results to sign-preserving zero. The maximum absolute error is 2-22.ftz. For PTX ISA version 1.f32 la.approx.approx{.approx.approx modifier is required.ftz. lg2. the . lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz}.f32 defaults to lg2. lg2. Target ISA Notes Examples Supported on all target architectures.ftz introduced in PTX ISA version 1. subnormal numbers are supported. For PTX ISA versions 1. PTX ISA Notes lg2. a.ftz.f32 implements a fast approximation to log2(a). 2010 .4. Explicit modifiers .approx and . d = log(a) / log(2).f32.PTX ISA Version 2.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

b32.0 Table 67. gtu.ftz}. 2010 .CmpOp.u16. sm_1x: setp. or. q = BoolOp(!t. gt. then these comparisons have the same result as their ordered counterparts. num. . hi.0.dtype.r. ls. leu. gt.f32 comparisons.s16. a. p[|q]. ltu. If both operands are numeric values (not NaN). Subnormal numbers: sm_20: By default. unordered versions are included: equ. gt. ls. le. and higher-or-same may be used instead of lt.s32 setp. c). For unsigned values.CmpOp{. @q setp. . the result is false.f32.and. p = BoolOp(t. loweror-same. .a. The signed and unsigned comparison operators are eq.type = { .u32. the comparison operators lo.BoolOp{.type setp. setp. ge. ltu.ftz applies only to . p. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. To aid comparison operations in the presence of NaN values. subnormal numbers are supported. setp with . lt. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. 102 January 24. hs equ. geu. and (optionally) combine this result with a predicate value by applying a Boolean operator.pred variables. and nan returns true if either operand is NaN. setp. le. and hs for lower. The destinations p and q must be .b16. Applies to all numeric types. If either operand is NaN. The untyped. hi. lo.ftz. . p[|q]. Semantics t = (a CmpOp b) ? 1 : 0. le.i. then the result of these comparisons is true. ge. higher.n. A related value computed using the complement of the compare result is written to the second destination operand. . ge. nan The Boolean operator BoolOp(A. lt. xor. and can be one of: eq. . ge.type .f64 supports subnormal numbers.s64. . ne. If either operand is NaN.f64 }. le. ne. b.eq. a. {!}c. setp. lt. ne.ftz}. b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u64.f32 flushes subnormal inputs to sign-preserving zero. neu.s32.dtype.f32 flushes subnormal inputs to sign-preserving zero.u32 p|q.b64. leu. bit-size comparisons are eq and ne. Integer Notes Floating Point Notes The ordered comparisons are eq. num returns true if both operands are numeric values (not NaN). geu. The comparison operator is a suffix on the instruction.dtype. respectively.f64 source type requires sm_13 or later. . c).PTX ISA Version 2. neu.lt.b.B) is one of: and. . gtu. . gt. Modifier . This result is written to the first destination operand.

y. and b must be of the same type.s32.u32. B. . Operands d. z. and operand a is selected. d = (c == 1) ? a : b. . Operands d.f32 flushes subnormal values of operand c to sign-preserving zero.u32. slct. If c ≥ 0. .f32.s16.dtype. . . and b are treated as a bitsize type of the same width as the first instruction type. the comparison is unordered and operand b is selected. If c is True. a is stored in d. c. f0. Modifier . The selected input is copied to the output without modification.p.r. .u64. b.f32 d. @q selp.b16. a. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. 2010 103 .f64 }. based on the sign of the third operand. . Table 69.s64.dtype. b otherwise.0.f64 requires sm_13 or later.b16. otherwise b is stored in d. b.s32. slct. . slct. b. selp.f32 comparisons.Chapter 8.s32 selp. . slct. . operand c must match the second instruction type. C.ftz.f32 A. . val. a.u16. .type = { .dtype. . c.b64. . sm_1x: slct.u64.s32 slct{.f64 }. slct.f32. . negative zero equals zero.t.ftz}. selp. . subnormal numbers are supported.x. .f32 r0. slct Syntax Comparison and Selection Instructions: slct Select one source operand. a.u32.s16. a. selp Syntax Comparison and Selection Instructions: selp Select between source operands. Semantics Floating Point Notes January 24.u64. based on the value of the predicate source operand. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32. Introduced in PTX ISA version 1. and operand a is selected.ftz applies only to .u16. For .s64.f32 comparisons.b32. Description Conditional selection. Subnormal numbers: sm_20: By default.ftz. If operand c is NaN.dtype = { . a. .g. fval. .xp.f32 flushes subnormal values of operand c to sign-preserving zero.s32 x. c. . d = (c >= 0) ? a : b.type d. d.dtype.b64. . .0. a is stored in d. Instruction Set Table 68.f64 requires sm_13 or later. Operand c is a predicate.

or.0 8. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. provided the operands are of the same size. Instructions and.4.PTX ISA Version 2. 2010 . xor. performing bit-wise operations on operands of any type.7. and not also operate on predicates. This permits bit-wise operations on floating point values without having to define a union to access the bits.

0x00010001 or. . d = a & b. Instruction Set Table 70. and Syntax Logic and Shift Instructions: and Bitwise AND.type d. .type = { . Allowed types include predicate registers.type = { . January 24. . Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.q.r. but not necessarily the type. d = a | b. sign. Introduced in PTX ISA version 1.b16.Chapter 8.0x80000000. .b32.0.fpvalue. but not necessarily the type. a. Table 71.q. .b16.b32. b. . .b32 mask mask. or.b32 and. or Syntax Logic and Shift Instructions: or Bitwise OR. Allowed types include predicate registers. or. Introduced in PTX ISA version 1.pred. and. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. b.pred p.b64 }.b32 x. a.0. . and.r.b64 }. The size of the operands must match. Supported on all target architectures.type d. 2010 105 . The size of the operands must match.pred.

pred p. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.q. d = a ^ b. .b32 mask.b16. xor. not.b32. The size of the operands must match. 106 January 24. xor.b64 }. Supported on all target architectures. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). one’s complement. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.type d. d = ~a.q.b16 d. Supported on all target architectures. b.b16. but not necessarily the type. Table 73.b64 }. cnot.x. Allowed types include predicate registers.mask. d = (a==0) ? 1 : 0. .b32 d. not.0x0001.type = { . Table 74. Introduced in PTX ISA version 1. d.0 Table 72. . 2010 .pred.PTX ISA Version 2. . not. a. a.b16.0.b32.0. but not necessarily the type. cnot. Allowed types include predicates. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. . Supported on all target architectures. but not necessarily the type.b32. . . The size of the operands must match. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.0. not Syntax Logic and Shift Instructions: not Bitwise negation.type = { . .r.a. The size of the operands must match.type d. .type = { .b64 }.pred. Introduced in PTX ISA version 1.type d.b32 xor. Introduced in PTX ISA version 1. a.

a. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. PTX ISA Notes Target ISA Notes Examples Table 76. Supported on all target architectures. .u16. The sizes of the destination and first source operand must match. 2010 107 . The sizes of the destination and first source operand must match.type d.2. b.s64 }. Supported on all target architectures. .b64 }.2.s32 shr. Instruction Set Table 75.b16.b32. Shift amounts greater than the register width N are clamped to N.i. shr Syntax Logic and Shift Instructions: shr Shift bits right.u16 shr. zero-fill on right.0.type = { .u64. shl. . sign or zero fill on left. .a.s32. . .b16 c. d = a << b. . Bit-size types are included for symmetry with SHL.b16. Introduced in PTX ISA version 1. i.i. . shr. Signed shifts fill with the sign bit. b.s16. unsigned and untyped shifts fill with 0.b64. but not necessarily the type. a. . shr. The b operand must be a 32-bit value. . . The b operand must be a 32-bit value. Shift amounts greater than the register width N are clamped to N.b32. regardless of the instruction type. shl Syntax Logic and Shift Instructions: shl Shift bits left. k. shl. Introduced in PTX ISA version 1.j. regardless of the instruction type.0.Chapter 8. .type = { . but not necessarily the type.type d.u32.b32 q.1. d = a >> b. a. PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.

and from state space to state space. The cvta instruction converts addresses between generic and global. suld. st. and sust support optional cache operations. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. or shared state spaces. Data Movement and Conversion Instructions These instructions copy data from place to place. and st operate on both scalar and vector types.7. possibly converting it from one format to another. local. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. mov.5.0 8. ld. ldu. Instructions ld. prefetchu isspacep cvta cvt 108 January 24. 2010 .PTX ISA Version 2.

Table 77. Operator . fetch again). The driver must invalidate global L1 cache lines between dependent grids of parallel threads. The ld. . not L1). A ld.1. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. when applied to a local address. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. and a second thread loads that address via a second L1 cache with ld. The ld. The compiler / programmer may use ld. When ld. likely to be accessed once.cs Cache streaming.cv Cache as volatile (consider cached system memory lines stale. .lu load last use operation. If one thread stores to global memory via one L1 cache. it performs the ld. Global data is coherent at the L2 level.ca loads cached in L1. 2010 109 . As a result of this request.cs) on global addresses. Instruction Set 8. The ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. likely to be accessed again.lu operation. For sm_20 and later. bypassing the L1 cache. Cache Operators PTX 2.Chapter 8.0 introduces optional cache operators on load and store instructions. to allow the thread program to poll a SysMem location written by the CPU. the cache operators have the following definitions and behavior.ca. January 24. The cache operators require a target architecture of sm_20 or later.7. any existing cache lines that match the requested address in L1 will be evicted.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. the second thread may get stale L1 cache data.cs is applied to a Local window address. Use ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.lu Last use. The ld. evict-first. but multiple L1 caches are not coherent for global data.5. if the line is fully covered. The default load instruction cache operation is ld.cg Cache at global level (cache in L2 and below.cg to cache loads only globally.cv to a frame buffer DRAM address is the same as ld. and cache only in the L2 cache. . . rather than the data stored by the first thread.cs.lu instruction performs a load cached streaming operation (ld.ca. invalidates (discards) the local L1 line following the load.

Addresses not in System Memory use normal write-back. The default store instruction cache operation is st. in which case st. If one thread stores to global memory.cg to local memory uses the L1 cache. and a second thread in a different SM later loads from that address via a different L1 cache with ld. and discard any L1 lines that match. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. but st. Global stores bypass L1. to allow a CPU program to poll a SysMem location written by the GPU with st. Future GPUs may have globally-coherent L1 caches. rather than get the data from L2 or memory stored by the first thread. 2010 .cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Use st.ca. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wb for global data. . and marks local L1 lines evict-first. likely to be accessed once. However.cg is the same as st.wb could write-back global store data from L1. bypassing its L1 cache. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wt Cache write-through (to system memory). and cache only in the L2 cache.0 Table 78.cg Cache at global level (cache in L2 and below.wt store write-through operation applied to a global System Memory address writes through the L2 cache.ca loads.wb. regardless of the cache operation.cs Cache streaming. In sm_20. Operator . st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. 110 January 24. The st. not L1).wt. . which writes back cache lines of coherent cache levels with normal eviction policy.PTX ISA Version 2. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.cg to cache global store data only globally. . The st. bypassing the L1 cache. the second thread may get a hit on stale L1 cache data.

1.0. d = sreg. the generic address of a variable declared in global.u16.. . d. addr. // get address of variable // get address of label or function . avar.s64.type mov.. ptr. or shared state space may be taken directly using the cvta instruction. ptr.e. . myFunc. Instruction Set Table 79.type mov. sreg. d. or function name. .type = { . special register. local. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.global.u32 mov.b16. or shared state space. .0.v. mov.u32.u16 mov. u.s32. d = &avar.type d. local. label.b64. mov. For variables declared in .shared state spaces. variable in an addressable memory space. . alternately.type mov.f32. within the variable’s declared state space Notes Although only predicate and bit-size types are required. label. Note that if the address of a device function parameter is moved to a register. . mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.u64. A. .pred. immediate. 2010 111 . a.b32. A[5]. Description . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. The generic address of a variable in global.const. and . the address of the variable in its state space) into the destination register. .f32 mov.s16. . Operand a may be a register. . Introduced in PTX ISA version 1. mov. Take the non-generic address of a variable in global. Semantics d = a. // address is non-generic. . the parameter will be copied onto the stack and the address will be in the local state space. d. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.u32 d. Write register d with the value of a.u32 mov. k.local. local. i. mov places the non-generic address of the variable (i.e.f32 mov. d = &label.Chapter 8. .a.f64 }.f64 requires sm_13 or later.

y.b64 { d.7].y << 16) | (a.15] } // unpack 8-bit elements from .y.x.type = { .g. a[32. Both the overall size of the vector and the size of the scalar must match the size of the instruction type..b32 // pack two 16-bit elements into . {lo.type d.{a. or write vector register d with the unpacked values from scalar register a.PTX ISA Version 2.15].w << 48) d = a.%r1. mov.x. {r..x.b. mov. a[32...b32 { d.b16 // pack four 8-bit elements into .31] } // unpack 8-bit elements from .x. d.y << 8) d = a. d.hi are .x | (a.x | (a. . a[16.b32 %r1.y } = { a[0.w}.47].b64 112 January 24. d.31] } // unpack 16-bit elements from .b8 r.63] } // unpack 16-bit elements from .hi}. a[16..0 Table 80.g.15]..y << 32) // pack two 8-bit elements into .. %x.w have type .a}. For bit-size types.z.23].z << 16) | (a.u32 x.b16 { d.b32 { d. d. d. a[48. d.w } = { a[0.z. Supported on all target architectures.{x. lo..b32 // pack four 16-bit elements into .63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.31].y.b32.b32 mov.b32 mov. a[8.b64 // pack two 32-bit elements into . .x | (a.31].b64 mov..7]..x | (a.w << 24) d = a. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). %r1. d.u16 %x is a double.15].a have type .y } = { a[0. a[24.b16.z.0. .x | (a.z. 2010 . // // // // a. d. a[8.y } = { a[0. Description Write scalar register d with the packed value of vector register a..u8 // unpack 32-bit elements from .z << 32) | (a. a.b64 { d.y << 8) | (a. d... Semantics d = a.y << 16) d = a.b have type .w } = { a[0.b.b64 }.y. a[16..x. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.b}.

perform the load using generic addressing.volatile{.f64 using cvt. Generic addressing may be used with ld.type d.ca.reg state space. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .b8. .ss = { . . [a].const. The value loaded is sign-extended to the destination register width for signed integers. In generic addressing.param. . .v2. 32-bit).ss}. .b16. d. and then converted to .volatile.b32. or the instruction may fault. an address maps to global memory unless it falls within the local memory window or the shared memory window.cs. If an address is not properly aligned. Within these windows.. . .type ld. Generic addressing and cache operations introduced in PTX ISA 2. 2010 113 . .ss}.s16.global. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.s8. Description Load register variable d from the location specified by the source address operand a in specified state space.lu.vec = { .volatile. 32-bit). *(a+immOff).global and . The .s64. to enforce sequential consistency between threads accessing shared memory.f32. . the resulting behavior is undefined. If no state space is given.v4 }. *(immAddr).ss}{.type = { . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. i.f64 }.u32.cop = { . The address must be naturally aligned to a multiple of the access size. [a]. Cache operations are not permitted with ld. or [immAddr] an immediate absolute byte address (unsigned.cop}.s32. and is zeroextended to the destination register width for unsigned and bit-size types. . PTX ISA Notes January 24.Chapter 8. *a. .ss}{. .volatile may be used with . the access may proceed by silently masking off low-order address bits to achieve proper rounding. .vec.b64.vec.volatile introduced in PTX ISA version 1.u16. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.const space suffix may have an optional bank number to indicate constant banks other than bank zero. . an address maps to the corresponding location in local or shared memory.type . ld. an integer or bit-size type register reg containing a byte address. .e. Instruction Set Table 81.1.b16.0. [a]. A destination register wider than the specified type may be used.cg.volatile{. . The address size may be either 32-bit or 64-bit.shared spaces to inhibit optimization of references to volatile memory. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . d.cv }.u64. .u8.e. for example. Semantics d d d d = = = = a. ld.type ld{.0.f32 or . . .local. d. [a]. . . This may be used.cop}. ld{. i.shared }. . . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. ld introduced in PTX ISA version 1. .f16 data may be loaded using ld. Addresses are zero-extended to the specified width as needed. and truncated if the register width exceeds the state space address width for the target architecture.

[p]. // immediate address %r.[240].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.PTX ISA Version 2.[buffer+64].b32 ld.[p+-8].b64 ld. Generic addressing requires sm_20 or later.s32 ld.b32 ld. Q.f32 ld. // negative offset %r.[p+4]. %r.f32.%r. d.[a].b16 cvt. Cache operations require sm_20 or later.shared. // access incomplete array x.const[4]. // load .[fs]. 2010 .0 Target ISA Notes ld.const.global.f16 d.local.f64 requires sm_13 or later.global. x.local. ld.v4.b32 ld.

If an address is not properly aligned. where the address is guaranteed to be the same across all threads in the warp. and then converted to . only generic addresses that map to global memory are legal.v4 }.b32 d.Chapter 8. Semantics d d d d = = = = a. 32-bit). The data at the specified address must be read-only.f64 }.s8. . . . ldu. If no state space is given. . . The address size may be either 32-bit or 64-bit. .vec = { . . Within these windows.f16 data may be loaded using ldu. an address maps to global memory unless it falls within the local memory window or the shared memory window. *a. . i. Introduced in PTX ISA version 2. . ldu. ldu.[p+4].f64 using cvt. [areg] a register reg containing a byte address.b16.global.global.ss = { .u16.e.global }.type = { .b64. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // state space . [a]. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.f32 or .s64. an address maps to the corresponding location in local or shared memory.f32. i. . or the instruction may fault. *(a+immOff). . ldu{.u8. // load from address // vec load from address .b16. PTX ISA Notes Target ISA Notes Examples January 24. Addresses are zero-extended to the specified width as needed.f32 Q. For ldu. or [immAddr] an immediate absolute byte address (unsigned. and truncated if the register width exceeds the state space address width for the target architecture. and is zeroextended to the destination register width for unsigned and bit-size types. .b32.s16. the access may proceed by silently masking off low-order address bits to achieve proper rounding.ss}.vec. 2010 115 .v4.u64. perform the load using generic addressing. ldu.reg state space.0. the resulting behavior is undefined. [a]. . The address must be naturally aligned to a multiple of the access size.ss}.type ldu{.s32.[p].global.e. 32-bit). d.[a]. A destination register wider than the specified type may be used. .. In generic addressing. A register containing an address may be declared as a bit-size type or integer type. Instruction Set Table 82.type d. The value loaded is sign-extended to the destination register width for signed integers. The addressable operand a is one of: [avar] the name of an addressable variable var.f64 requires sm_13 or later.b8. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. .f32 d. *(immAddr).u32.v2. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .

st. an integer or bit-size type register reg containing a byte address.volatile{.cop}.shared }. perform the store using generic addressing.u32. .wb. [a].global and . . Generic addressing may be used with st. Addresses are zero-extended to the specified width as needed. Generic addressing requires sm_20 or later.s8.volatile may be used with . If no state space is given. b. . .type .f16 data resulting from a cvt instruction may be stored using st. . The address size may be either 32-bit or 64-bit. The lower n bits corresponding to the instruction-type width are stored to memory.ss .u64.shared spaces to inhibit optimization of references to volatile memory. . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.0. .f64 }. A source register wider than the specified type may be used. st introduced in PTX ISA version 1.volatile introduced in PTX ISA version 1.volatile.0.type = = = = {. { . i.global.v2. { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.local.v4 }. PTX ISA Notes Target ISA Notes 116 January 24. . [a]. or the instruction may fault. . [a]. *(immAddr) = a. Within these windows. 2010 . .vec.cop . st.cg. .0 Table 83. The address must be naturally aligned to a multiple of the access size. { . .u16. 32-bit). i. 32-bit).volatile.s16.s32. .f32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.u8. for example. .cop}. or [immAddr] an immediate absolute byte address (unsigned.ss}. . b.ss}{.1. the resulting behavior is undefined. This may be used. If an address is not properly aligned.vec.. an address maps to the corresponding location in local or shared memory.b8. . Cache operations require sm_20 or later. to enforce sequential consistency between threads accessing shared memory.ss}. b. . *(d+immOffset) = a.reg state space.PTX ISA Version 2. .e. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.type st{. In generic addressing. and truncated if the register width exceeds the state space address width for the target architecture.s64. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.vec . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . b.f64 requires sm_13 or later.b32.cs. . st{.type st.ss}{. an address maps to global memory unless it falls within the local memory window or the shared memory window. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. Cache operations are not permitted with st.b64.volatile{.b16. . *d = a. Semantics d = a. Generic addressing and cache operations introduced in PTX ISA 2.wt }.type [a]. st.e.b16.

b32 st. [q+-8]. 2010 117 .a.global.Chapter 8.a. [p].f32 st. // immediate address %r.local.r7.local.global.s32 cvt.b16 [a].local.f16.Q.%r. // %r is 32-bit register // store lower 16 bits January 24.%r. [fs].s32 st. [q+4].v4.b32 st. Instruction Set Examples st. // negative offset [100].f32 st.b.

space = { . an address maps to global memory unless it falls within the local memory window or the shared memory window. If no state space is given. .global. prefetch and prefetchu require sm_20 or later. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.global. 32-bit). i. . an address maps to the corresponding location in local or shared memory. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.L1. In generic addressing. a register reg containing a byte address. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. [a]. The address size may be either 32-bit or 64-bit.L1 [ptr]. prefetch{. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.space}.level = { . Addresses are zero-extended to the specified width as needed.L2 }. . and no operation occurs if the address maps to a local or shared memory location. A prefetch to a shared memory location performs no operation.PTX ISA Version 2. and truncated if the register width exceeds the state space address width for the target architecture.L1 [addr]. in specified state space.0 Table 84. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetchu.0. the prefetch uses generic addressing. // prefetch to data cache // prefetch to uniform cache . 2010 . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.local }. 118 January 24.level prefetchu. prefetch. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. Within these windows. A prefetch into the uniform cache requires a generic address.L1 [a]. 32-bit). or [immAddr] an immediate absolute byte address (unsigned.e.

cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. PTX ISA Notes Target ISA Notes Examples Table 86.to. When converting a generic address into a global. local. .shared }.u32 or .space.size p.genptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.shared isglbl. A program may use isspacep to guard against such incorrect behavior. or vice-versa. or shared address.global. January 24. .space. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.u64 }. local.0. local.u64.u32. // get generic address of svar cvta. or shared address cvta. Description Convert a global. . cvta requires sm_20 or later.u32.global.space. the generic address of the variable may be taken using cvta. a. cvta. For variables declared in global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.global isspacep. Introduced in PTX ISA version 2. var. or shared state space.u32 gptr.lptr.space = { . islcl. or shared state space to generic. isspacep. p.local. . svar. .size .u64 or cvt. cvta.global. isshrd. a. or shared address to a generic address.0. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or vice-versa.local isspacep. local.to. The destination register must be of type .pred. p.Chapter 8.u32 p.u64.size cvta. local. isspacep. The source address operand must be a register of type . .size = { . cvta.space p. // result is . Instruction Set Table 85. gptr. lptr. Use cvt. 2010 119 .u32 to truncate or zero-extend addresses. // convert to generic address // get generic address of var // convert generic address to global. sptr. // local. a.u32 p. or shared state space.space = { . Take the generic address of a variable declared in global.shared.local. The source and destination addresses must be the same size.pred . isspacep requires sm_20 or later.shared }.local.

rzi. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.u16. . Integer rounding modifiers: . // integer rounding // fp rounding .sat limits the result to MININT.s64.u8.ftz}{. . sm_1x: For cvt. .sat}. . Description Semantics Integer Notes Convert between different types and sizes. . . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. cvt{.ftz}{..sat is redundant.u64. Note: In PTX ISA versions 1.dtype. .4 and earlier.rn. . .rm.frnd}{. . subnormal numbers are supported.atype cvt{.f32.f16.f32 float-tofloat conversions with integer rounding. ..irnd = { . subnormal inputs are flushed to signpreserving zero. .e.f64 }.atype = { . 2010 . The compiler will preserve this behavior for legacy PTX code. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. .f32 float-to-integer conversions and cvt.e.f32.ftz.rmi. choosing even integer if source is equidistant between two integers.ftz.0 Table 87. Integer rounding is illegal in all other instances.PTX ISA Version 2. .u32. .atype d.irnd}{.ftz modifier may be specified in these cases for clarity. i. Note that saturation applies to both signed and unsigned integer types.dtype = . .dtype. subnormal inputs are flushed to signpreserving zero.rzi round to nearest integer in the direction of zero .sat For integer destination types. a. d = convert(a). The optional . .s8.sat}. i.rp }.dtype. the result is clamped to the destination range by default.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.MAXINT for the size of the operation. the .rpi }. 120 January 24. d.s32.s16. .rz. Saturation modifier: . For cvt.ftz.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.f32.frnd = { .f32 float-tofloat conversions with integer rounding. and for same-size float-tofloat conversions where the value is rounded to an integer.rni round to nearest integer. .ftz. . For float-to-integer conversions. .dtype.rni.f32 float-to-integer conversions and cvt. Integer rounding is required for float-to-integer conversions.rmi round to nearest integer in direction of negative infinity . a.

4 or earlier.rz mantissa LSB rounds towards zero .s32.r. stored in floating-point format.ftz modifier may be specified in these cases for clarity.y. 1.f32. NaN results are flushed to positive zero.Chapter 8.f16. and cvt.4 and earlier. // round to nearest int. Specifically. Applies to . Modifier .rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity . Introduced in PTX ISA version 1.f64 requires sm_13 or later. // note .i.f64 j.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. cvt. The compiler will preserve this behavior for legacy PTX code. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16.0.f64. Subnormal numbers: sm_20: By default. cvt. The operands must be of the same size.sat For floating-point destination types. The result is an integral value.f32. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . subnormal numbers are supported.f32. Saturation modifier: . cvt to or from .version is 1.f32.s32 f.ftz behavior for sm_1x targets January 24. .f32 x. 2010 121 . and for integer-to-float conversions.0. Note: In PTX ISA versions 1. and . .f32 instructions.f32 x.sat limits the result to the range [0. result is fp cvt. if the PTX . // float-to-int saturates by default cvt.f32.f32.0]. Floating-point rounding is illegal in all other instances. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. cvt. The optional . Floating-point rounding modifiers: .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).f32.f16. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.y.f64 types. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.rni.

sampler.f32 r3.0 8. Ability to query fields within texture. add.r2. [tex1].. div.f32 r1. PTX has two modes of operation. r5. [tex1. PTX supports the following operations on texture.samplerref tsamp1 = { addr_mode_0 filter_mode }.f32 r1. // get tex1’s tex. In the independent mode.texref handle. Texture and Surface Instructions This section describes PTX instructions for accessing textures.v4.height. If no texturing mode is declared. [tex1]. = nearest width height tsamp1. sampler.texref tex1 ) { txq. but the number of samplers is greatly restricted to 16.f32. A PTX module may declare only one texturing mode.u32 r5. allowing them to be defined separately and combined at the site of usage in the program. Module-scope and per-entry scope definitions of texture. sampler. the file is assumed to use unified mode. {f1. r5. Texturing modes For working with textures and samplers.u32 r5. and surface descriptors. r2.f32 r1. samplers.param .target texmode_independent . cvt. and surface descriptors. } = clamp_to_border. and surface descriptors. In the unified mode.r4}.f2}]. Example: calculate an element’s power contribution as element’s power/total number of elements. The advantage of unified mode is that it allows 128 samplers.entry compute_power ( . r3. r1. add.global . r4. and surface descriptors: • • • Static initialization of texture. 2010 .width. r1. . // get tex1’s txq. The texturing mode is selected using .b32 r6.f32. and surfaces.6. r1. add. 122 January 24.r3. with the restriction that they correspond 1-to-1 with the 128 possible textures. sampler. . mul. r6. .target options ‘texmode_unified’ and ‘texmode_independent’.f32 {r1.. r5.b32 r5.2d.7. texture and sampler information each have their own handle. The advantage of independent mode is that textures and samplers can be mixed and matched.PTX ISA Version 2. r3. texture and sampler information is accessed through a single .

s32. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.1d.2d. the sampler behavior is a property of the named texture.geom.s32. // explicit sampler .dtype.5.v4. PTX ISA Notes Target ISA Notes Examples January 24. [tex_a.btype tex. [a. i.3d.r4}.r3.Chapter 8. the square brackets are not required and . c]. Operand c is a scalar or singleton tuple for 1d textures. //Example of unified mode texturing tex. {f1.v4 coordinate vectors are allowed for any geometry. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .dtype.s32. The instruction always returns a four-element vector of 32-bit values.3d }.s32 {r1.e. Notes For compatibility with prior versions of PTX.0. . where the fourth element is ignored. is a two-element vector for 2d textures.geom = { .1d.dtype = { . Instruction Set These instructions provide access to texture and surface memory. .v4. .btype = { . {f1}].. .btype d.f32 {r1. [tex_a.v4. or the instruction may fault. with the extra elements being ignored. and is a four-element vector for 3d textures. An optional texture sampler b may be specified. b.r4}. c]. 2010 123 . . Supported on all target architectures.u32. tex txq suld sust sured suq Table 88. tex. d.r2. . A texture base address is assumed to be aligned to a 16-byte address. [a. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.r2. Description Texture lookup using a texture coordinate vector. the resulting behavior is undefined.v4.geom.f32 }.r3.f2. If no sampler is specified. Unified mode texturing introduced in PTX ISA version 1.f32 }. sampler_x. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f3. // Example of independent mode texturing tex. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. If an address is not properly aligned.f4}].s32. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.

. txq. .height . .width . addr_mode_2 }. linear } Integer from enum { wrap.tquery = { .normalized_coords . [smpl_B].tquery.filter_mode.b32 %r1.filter_mode . Query: .samplerref variable.b32 %r1. .addr_mode_0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 d. 2010 . and in independent mode sampler attributes are accessed via a separate samplerref argument.width.filter_mode. Description Query an attribute of a texture or sampler.b32 txq. [tex_A]. txq.depth .PTX ISA Version 2.5. [tex_A]. txq.height. // texture attributes // sampler attributes . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.texref or .normalized_coords }. .width. Integer from enum { nearest.addr_mode_1 .squery. clamp_to_edge. Supported on all target architectures. [a]. [a].0 Table 89.depth.addr_mode_0. Operand a is a . txq. d. // unified mode // independent mode 124 January 24.addr_mode_0 . addr_mode_1.b32 %r1. clamp_ogl.squery = { .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. sampler attributes are also accessed via a texref argument. In unified mode. mirror.

e.clamp .b. Operand b is a scalar or singleton tuple for 1d surfaces.geom . then . the surface sample elements are converted to . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f2. // for suld.b .surfref variable. Description Load from surface memory using a surface coordinate vector. .1d.geom{. .u32.s32 is returned. Cache operations require sm_20 or later. [a.geom{.u32. The . and the size of the data transfer matches the size of destination operand d.trap introduced in PTX ISA version 1.v2.f32 based on the surface format as follows: If the surface format contains UNORM.1d.b32. If an address is not properly aligned. B. // unformatted d.s32. . .Chapter 8.b16. .b64.f3. . suld..f32.clamp .clamp.s32.clamp field specifies how to handle out-of-bounds addresses: .dtype . sm_1x targets support only the .dtype. then .trap . {f1.cg.v4.f32 is returned. . the resulting behavior is undefined.3d requires sm_20 or later.vec.b32. .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.trap {r1. suld. Coordinate elements are of type .2d.b.5. Target ISA Notes Examples January 24. or the instruction may fault.v4 }.v4. {x.f32.clamp = = = = = = { { { { { { d. 2010 125 . where the fourth element is ignored. . .ca.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. // cache operation none.s32.z.dtype.cop}.3d.y.dtype . The lowest dimension coordinate represents a sample offset rather than a byte offset.0.p.b. and A components of the surface format. If the destination type is . or .cs.p requires sm_20 or later. b]. or .vec .u32. Destination vector elements corresponding to components that do not appear in the surface format are not written. suld. . suld.r2}. and cache operations introduced in PTX ISA version 2.cop}.s32. additional clamp modifiers. [a. size and type conversion is performed as needed to convert from the surface sample format to the destination type. Instruction Set Table 90.cv }. A surface base address is assumed to be aligned to a 16-byte address. if the surface format contains SINT data.b8 .u32 is returned. .b supported on all target architectures.p is currently unimplemented.f32 }. and is a four-element vector for 3d surfaces. [surf_B.trap suld. or FLOAT data.zero }.b performs an unformatted load of binary data. then . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. suld. // formatted . // for suld. b].trap clamping modifier. i. .b64 }. .p.v2. [surf_A. suld.3d }. SNORM.cop .trap. . .b32.p. Operand a is a .clamp suld. is a two-element vector for 2d surfaces. . suld. If the destination base type is . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. suld. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. .w}]. suld.p . G. if the surface format contains UINT data. . suld Syntax Texture and Surface Instructions: suld Load from surface memory. {x}].f4}.

If the source type is . . .f3.clamp .v4 }.1d.geom . // unformatted // formatted . sust.b // for sust. is a two-element vector for 2d surfaces.f4}. b].p.w}].v2.b64. .clamp = = = = = = { { { { { { [a.b32. SNORM.f32.b. sust. . sust Syntax Texture and Surface Instructions: sust Store to surface memory.trap clamping modifier. where the fourth element is ignored. sm_1x targets support only the . Source elements that do not occur in the surface sample are ignored. .p. The . The source vector elements are interpreted left-to-right as R.p.f32 is assumed. These elements are written to the corresponding surface sample components. If the source base type is . or .r2}. The source data is then converted from this type to the surface sample format. sust. . . B. i.f32 }. or the instruction may fault.{u32.geom{.vec. none.PTX ISA Version 2.v4.s32.clamp sust. .3d requires sm_20 or later. [a.5. If an address is not properly aligned.3d }.z.cop}.cs. then . {f1.ctype . [surf_B.ctype. Cache operations require sm_20 or later. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Target ISA Notes Examples 126 January 24. additional clamp modifiers. sust.clamp field specifies how to handle out-of-bounds addresses: . {x}]. A surface base address is assumed to be aligned to a 16-byte address.s32.u32 is assumed.ctype .v2.b32. .f32.trap introduced in PTX ISA version 1.trap [surf_A. sust. Operand b is a scalar or singleton tuple for 1d surfaces.wt }.f32} are currently unimplemented. if the surface format contains UINT data. The size of the data transfer matches the size of source operand c.p requires sm_20 or later. if the surface format contains SINT data.b performs an unformatted store of binary data. sust.surfref variable. . .geom{. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.cop .f2. Operand a is a .p Description Store to surface memory using a surface coordinate vector. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. .s32 is assumed. or FLOAT data.trap .b16.e..b supported on all target architectures.wb.p. {x. c.trap sust. the access may proceed by silently masking off low-order address bits to achieve proper rounding.vec. The lowest dimension coordinate represents a sample offset rather than a byte offset. then .zero }. {r1. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.cop}. Coordinate elements are of type . 2010 . // for sust. .b32.2d. sust. sust. and cache operations introduced in PTX ISA version 2. . .b64 }.vec .b.trap. and A surface components.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. G.1d. c. .p performs a formatted store of a vector of 32-bit data values to a surface sample.u32.clamp. Surface sample components that do not occur in the source vector will be written with an unpredictable value.b8 . . the resulting behavior is undefined. size and type conversions are performed as needed between the surface sample format and the destination type.3d. sust.s32.0. .b.0 Table 91. b].s32. .y.clamp . then .ctype.u32.cg. . and is a four-element vector for 3d surfaces.

Instruction Set Table 92.b32. .b32. {x}].add. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.ctype.c. .trap. January 24. the resulting behavior is undefined.u64 data. sured. min and max apply to .ctype = { . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. Reduction to surface memory using a surface coordinate vector.b32.p.clamp [a.s32 or .trap sured.y}].s32.b32 }.s32 types. then .. or . Operand a is a .s32. .min.p .p performs a reduction on sample-addressed 32-bit data. then . r1.u32.ctype = { . If an address is not properly aligned. sured. sured. The instruction type is restricted to .u32.op = { .2d. and . .op.and.u64.clamp .clamp.geom = { . sured. 2010 127 .trap [surf_A. Coordinate elements are of type . . and the data is interpreted as .b]. and is a four-element vector for 3d surfaces.geom. . operations and and or apply to . .e. Operand b is a scalar or singleton tuple for 1d surfaces.b].clamp = { .u32.min. // byte addressing sured.trap .b32 }. if the surface format contains SINT data.2d. or the instruction may fault. . .u64.zero }.s32 types.0.geom. .u32 based on the surface sample format as follows: if the surface format contains UINT data.op. Operations add applies to . // for sured.1d. .s32 is assumed. // sample addressing .s32.u32 and . {x.b . i. r1.b.u32. is a two-element vector for 2d surfaces. [surf_B. .b. The .1d.max.surfref variable.c. sured requires sm_20 or later. .b performs an unformatted reduction on .u32 is assumed. .3d }.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the access may proceed by silently masking off low-order address bits to achieve proper rounding.p.clamp field specifies how to handle out-of-bounds addresses: . The lowest dimension coordinate represents a sample offset rather than a byte offset. .Chapter 8. A surface base address is assumed to be aligned to a 16-byte address. // for sured. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.or }. .b32 type.clamp [a.add. where the fourth element is ignored.ctype. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.

[surf_A]. Description Query an attribute of a surface. .width .width.height. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth }.surfref variable. suq. Supported on all target architectures. .PTX ISA Version 2.5.0 Table 93. . 128 January 24.query.width. 2010 .height . [a].query = { . suq.b32 d. Query: .b32 %r1.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Operand a is a .

Supported on all target architectures.7. {} Syntax Description Control Flow Instructions: { } Instruction grouping.Chapter 8.y.f32 @q bra L23. @{!}p instruction. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.f32 @!p div.c. p. } PTX ISA Notes Target ISA Notes Examples Table 95. Execute an instruction or instruction block for threads that have the guard predicate true. used primarily for defining a function body.x. { instructionList } The curly braces create a group of instructions.0.0. If {!}p then instruction Introduced in PTX ISA version 1.a. setp.7.eq. 2010 129 .s32 d. Threads with a false guard predicate do nothing. ratio. Introduced in PTX ISA version 1. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. Instruction Set 8.0. mov.s32 a.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. { add.b. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Supported on all target architectures.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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a{.red should not be intermixed with bar. while .0. d. threads within a CTA that wish to communicate via memory can store to memory. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). b}. Since barriers are executed on a per-warp basis. the optional thread count must be a multiple of the warp size.or).or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Thus.sync) until the barrier count is met.red instruction.Chapter 8. Instruction Set Table 100. . b.cta. Description Performs barrier synchronization and communication within a CTA.sync and bar.sync bar. The reduction operations for bar. {!}c. b. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. and d have type . and bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. a{.arrive does not cause any waiting by the executing threads.red are population-count (.red} require sm_20 or later.u32.popc. execute a bar. Each CTA instance has sixteen barriers numbered 0. it simply marks a thread's arrival at the barrier. p.red performs a predicate reduction across the threads participating in the barrier.sync and bar. and any-thread-true (. bar. bar. Execution in this case is unpredictable.sync without a thread count introduced in PTX ISA 1. In addition to signaling its arrival at the barrier. In conditionally executed code.popc is the number of threads with a true predicate. bar. it is as if all the threads in the warp have executed the bar instruction. Note that a non-zero thread count is required for bar. January 24. b}. The result of .arrive a{. If no thread count is specified. if any thread in a warp executes a bar instruction.0. all threads in the CTA participate in the barrier. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. and bar.or }.red delays the executing threads (similar to bar. PTX ISA Notes Target ISA Notes Examples bar. The barrier instructions signal the arrival of the executing threads at the named barrier.pred . bar. thread count.red.red also guarantee memory ordering among threads identical to membar.{arrive. and then safely read values stored by other threads prior to the barrier. When a barrier completes.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.sync or bar. Once the barrier count is reached. and the barrier is reinitialized so that it can be immediately reused. b}. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.op. Register operands.and). thread count. the bar.15. operands p and c are predicates. bar.op = { .popc). the waiting threads are restarted without delay.arrive using the same active barrier. Register operands.sync or bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).sync with an immediate barrier number is supported for sm_1x targets. bar.sync 0. 2010 133 . a.. all-threads-true (. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.{arrive.red. bar.u32 bar. {!}c. Only bar.arrive.and.red performs a reduction operation across threads. Thus.version 2. bar.and and .red} introduced in PTX . All threads in the warp are stalled until the barrier completes. Operand b specifies the number of threads participating in the barrier. bar. the final value is written to the destination register in all threads waiting at the barrier. Operands a.

2010 . this is the appropriate level of membar.0.version 1. membar.sys requires sm_20 or later. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.sys introduced in PTX . including thoses communicating via PCI-E such as system and peer-to-peer memory. membar.gl. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.level. PTX ISA Notes Target ISA Notes Examples membar. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar. membar.g.gl} supported on all target architectures. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. A memory write (e.version 2.sys will typically have much longer latency than membar.gl will typically have a longer latency than membar.cta.gl.level = { . 134 January 24.g.4.sys Waits until all prior memory requests have been performed with respect to all clients.sys }.cta Waits until all prior memory writes are visible to other threads in the same CTA. membar. . membar. and memory reads by this thread can no longer be affected by other thread writes. membar.PTX ISA Version 2. or system memory level. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.gl} introduced in PTX . global. that is. membar. membar. membar.{cta.gl. membar. Waits until prior memory reads have been performed with respect to other threads in the CTA.cta. level describes the scope of other clients for which membar is an ordering event.cta. . For communication between threads in different CTAs or even different SMs.sys.{cta. A memory read (e. by st.0 Table 101. when the previous value can no longer be read. .

b32. .op = { .u32 only . In generic addressing.Chapter 8.inc.b64. 32-bit operations. . . min. overwriting the original value. i. .u64 . [a]. [a].or.exch. The floating-point add.u32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Operand a specifies a location in the specified state space. . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.s32.type = { .b32 only .and.add. . min. . or.s32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. the access may proceed by silently masking off low-order address bits to achieve proper rounding. atom.add. . . . and exch (exchange).min. b. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.u64. the resulting behavior is undefined. . . .global. d.b64 . .f32 Atomically loads the original value at location a into destination register d. min. If no state space is given. A register containing an address may be declared as a bit-size type or integer type. The address size may be either 32-bit or 64-bit.g. The inc and dec operations return a result in the range [0. . i.op. . or [immAddr] an immediate absolute byte address. dec. The floating-point operations are add.exch to store to locations accessed by other atomic operations. max. a de-referenced register areg containing a byte address. b. The address must be naturally aligned to a multiple of the access size. accesses to local memory are illegal.e. Description // // // // // .space}. .dec. . For atom.space}. . . The integer operations are add.u32.type atom{.cas. performs a reduction operation with operand b and the value in location a. xor.. and max. January 24. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. by inserting barriers between normal stores and atomic operations to a common address.xor. Instruction Set Table 102. Addresses are zero-extended to the specified width as needed. .b32.op. If an address is not properly aligned.type d. or by using atom.space = { .max }. The bit-size operations are and.u32.. e. an address maps to the corresponding location in local or shared memory. and truncated if the register width exceeds the state space address width for the target architecture.b]. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. .s32. perform the memory accesses using generic addressing. inc.shared }. Within these windows. c. an address maps to global memory unless it falls within the local memory window or the shared memory window. . or the instruction may fault. atom{. and max operations are single-precision. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.f32.f32 }. 2010 135 . cas (compare-and-swap). and stores the result of the specified operation at location a. .e.

1.global. 2010 . atom.0 Semantics atomic { d = *a. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom. cas(r. Use of generic addressing requires sm_20 or later.0.add.b32 d.cas.s32 atom. Introduced in PTX ISA version 1. Release Notes Examples @p 136 January 24.cas.add. atom. d.[a]. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.global requires sm_11 or later.[x+4].f32 atom. 64-bit atom.shared.f32.{min. : r.my_val.shared operations require sm_20 or later.shared requires sm_12 or later.PTX ISA Version 2.t) = (r == s) ? t operation(*a. b). atom.{add.s. c) operation(*a.global.[p].max. : r+1. *a = (operation == cas) ? : } where inc(r.exch} requires sm_12 or later. s) = (r >= s) ? 0 dec(r.my_new_val. s) = s. s) = (r > s) ? s exch(r.f32 requires sm_20 or later. : r-1.max} are unimplemented.0. 64-bit atom. b. atom. d.

u32. Semantics *a = operation(*a.dec. The floating-point add.space}. . red{. January 24. and truncated if the register width exceeds the state space address width for the target architecture. e.g. an address maps to the corresponding location in local or shared memory.. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.xor. If an address is not properly aligned. Notes Operand a must reside in either the global or shared state space. For red. dec. . accesses to local memory are illegal. . 2010 137 . .op = { .b32 only .f32 }.op. red. the resulting behavior is undefined.f32. In generic addressing.type = { .add. . .or. . where inc(r. . Within these windows. The inc and dec operations return a result in the range [0. . an address maps to global memory unless it falls within the local memory window or the shared memory window. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.u64 .u32. and max. The bit-size operations are and.e.b]. If no state space is given. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.max }.min. b). dec(r. the access may proceed by silently masking off low-order address bits to achieve proper rounding.inc. overwriting the original value. The integer operations are add.space = { . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.u64.. max. The address size may be either 32-bit or 64-bit.s32. . . min. . and stores the result of the specified operation at location a. . Operand a specifies a location in the specified state space.e. s) = (r > s) ? s : r-1.type [a]. and xor. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.s32.b32. The address must be naturally aligned to a multiple of the access size. and max operations are single-precision. A register containing an address may be declared as a bit-size type or integer type.and. . . 32-bit operations. i. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The floating-point operations are add. Description // // // // .s32. by inserting barriers between normal stores and reduction operations to a common address.exch to store to locations accessed by other reduction operations.f32 Performs a reduction operation with operand b and the value in location a.b64. . inc.shared }.Chapter 8. perform the memory accesses using generic addressing. Addresses are zero-extended to the specified width as needed.global. or.u32. a de-referenced register areg containing a byte address. or by using atom. i.add. s) = (r >= s) ? 0 : r+1. . Instruction Set Table 103. min.u32 only . min. or [immAddr] an immediate absolute byte address. . b.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . or the instruction may fault. .

64-bit red. red.my_val. Release Notes Examples @p 138 January 24. 64-bit red. [p].and.add.s32 red.add.shared requires sm_12 or later.global.f32 red.shared operations require sm_20 or later.max} are unimplemented. Use of generic addressing requires sm_20 or later.f32.b32 [a]. [x+4]. red. red.f32 requires sm_20 or later. red.add requires sm_12 or later.{min.global requires sm_11 or later red.max.PTX ISA Version 2. 2010 .0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.global.0.2.shared.1.

vote requires sm_12 or later. Negate the source predicate to compute .q. r1. Description Performs a reduction of the source predicate across threads in a warp. p.uni True if source predicate has the same value in all active threads in warp.uni. Instruction Set Table 104. Negate the source predicate to compute .q.mode.pred vote. {!}a. . . // get ‘ballot’ across warp January 24. {!}a.ballot. where the bit position corresponds to the thread’s lane id. not across an entire CTA.all.all True if source predicate is True for all active threads in warp. Note that vote applies to threads in a single warp.ballot.ballot.mode = { .pred vote. vote.any True if source predicate is True for some active thread in warp. vote.b32 requires sm_20 or later. The destination predicate value is the same across all threads in the warp.Chapter 8. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. vote.b32 d.uni }.pred d. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. 2010 139 .not_all. vote. In the ‘ballot’ form. Negating the source predicate also computes . // ‘ballot’ form. returns bitmask .all.uni.none. vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.any.p.ballot. The reduction modes are: .b32 p. . .2.

PTX ISA Version 2.atype. The primary operation is then performed to produce an .s34 intermediate result.dtype.atype = . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.min. a{. vop.9.btype{. the input values are extracted and signor zero. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.btype = { .b0. b{.bsel}.atype.b2. Using the atype/btype and asel/bsel specifiers.bsel}. The sign of the intermediate result depends on dtype. .secop = { .u32 or . .dtype. . The general format of video instructions is as follows: // 32-bit scalar operation. . with optional data merge vop. b{. b{.asel = . .dsel = . The source and destination operands are all 32-bit registers.7. taking into account the subword destination size in the case of optional data merging. a{.btype{. 140 January 24. . optionally clamp the result to the range of the destination type. and btype are valid. The type of each operand (.asel}.0 8. // 32-bit scalar operation. or word values from its source operands. . all combinations of dtype. to produce signed 33-bit input values. .max }. c.h0.extended internally to .add. . c.s32 }.sat} d.or zero-extend byte. 4.atype.dsel.dtype = . with optional secondary operation vop. Video Instructions All video instructions operate on 32-bit register operands.b1. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). a{.bsel = { .bsel}. 2010 .s32) is specified in the instruction type. half-word. perform a scalar arithmetic operation to produce a signed 34-bit result. 3. .dtype.asel}. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. 2.btype{.secop d. .sat}.s33 values.sat} d. extract and sign.asel}. atype.h1 }.u32.b3.

tmp. tmp. S8_MIN ). U8_MIN ). Modifier dsel ) { if ( !sat ) return tmp. The sign of the c operand is based on dtype.s33 tmp.b0. .min: return MIN(tmp. Bool sign. c). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 c) { switch ( secop ) { . . U32_MIN ). tmp. c). .b3: if ( sign ) return CLAMP( else return CLAMP( case . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). . tmp. U32_MAX.s33 optSaturate( . c). January 24. . 2010 141 . . The lower 32-bits are then written to the destination operand. S32_MAX. U16_MIN ).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. .b2: return ((tmp & 0xff) << 16) case . default: return tmp.h0. S16_MIN ). c). switch ( dsel ) { case . S8_MAX. S16_MAX. . .h1: return ((tmp & 0xffff) << 16) case . . as shown in the following pseudocode. } } .b1. c).s34 tmp.b2.h0: return ((tmp & 0xffff) case .s33 optSecOp(Modifier secop. c). S32_MIN ).b0: return ((tmp & 0xff) case . U16_MAX. .s33 optMerge( Modifier dsel.b1: return ((tmp & 0xff) << 8) case . U8_MAX.s33 c ) switch ( dsel ) { case .Chapter 8.s33 tmp. Instruction Set .add: return tmp + c.max return MAX(tmp. tmp.b3: return ((tmp & 0xff) << 24) default: return tmp. c). Bool sat.

0. .atype. vsub vabsdiff vmin. isSigned(dtype). c.b0. c. r2.s32. tmp = MAX( ta. r1.sat} d.btype{. and optional secondary arithmetic operation or subword data merge. r3. c. Integer byte/half-word/word minimum / maximum.bsel = { . a{. Perform scalar arithmetic operation with optional saturate.s32.sat vmin.dtype.b3.min. tb ). tmp = | ta – tb |.h1 }. // optional merge with c operand 142 January 24. . vadd. vabsdiff. vmax require sm_20 or later. vmax vadd. { . . vabsdiff.add. b{.dtype .s32.bsel}.op2 d.sat.atype.h0.bsel}.h1.add r1. asel ). a{. dsel ). vmax Syntax Integer byte/half-word/word addition / subtraction. r2. r3. tmp = ta – tb.bsel}. Semantics // saturate. b{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.atype = . tmp = MIN( ta. btype.btype{.s32.sat vsub.s32. atype. . r3. vsub. .btype = { .b0.s32. a{. .b1. c. vmin.btype{. Integer byte/half-word/word absolute value of difference.sat}. b{. tb = partSelectSignExtend( b. . vabsdiff. r2. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. . vmax }.s32. tb ).u32.u32. .op2 Description = = = = { vadd. with optional secondary operation vop. taking into account destination type and merge operations tmp = optSaturate( tmp. 2010 . vop. tmp.b2.atype.s32 }. // extract byte/half-word/word and sign.PTX ISA Version 2.s32. r1. c ).dtype. vmin.h1. r1. // 32-bit scalar operation.asel}.h0.asel}.or zero-extend based on source operand type ta = partSelectSignExtend( a.max }.s32. // 32-bit scalar operation. with optional data merge vop. // optional secondary operation d = optMerge( dsel. bsel ).dtype. tmp. r3.dsel.sat vabsdiff.b2. c ). . vadd. vsub. r2. d = optSecondaryOp( op2.b0. vsub. Video Instructions: vadd.asel = . sat.sat} d.dsel .s32.h0.vop . vmin.asel}.u32. .0 Table 105.

bsel ). asel ).u32{. with optional secondary operation vop.dsel.sat}{. .bsel}.h1 }.atype.h1. . c ). case vshr: tmp = ta >> tb. dsel ). . { . taking into account destination type and merge operations tmp = optSaturate( tmp.b3.u32 vshr.mode . vshr }. b{.u32.sat}{. .bsel}. Semantics // extract byte/half-word/word and sign. a{. Video Instructions: vshl.atype = { . and optional secondary arithmetic operation or subword data merge. . b{. isSigned(dtype). January 24.or zero-extend based on source operand type ta = partSelectSignExtend( a. . r3. with optional data merge vop. vshr Syntax Integer byte/half-word/word left / right shift.min.mode} d. b{. sat.h0. .dtype.u32. switch ( vop ) { case vshl: tmp = ta << tb.u32{. atype. // 32-bit scalar operation.asel}.u32.0. vop. c ). // default is .wrap r1. c. .dsel .op2 d.vop . } // saturate. c.Chapter 8.s32 }. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.asel = . if ( mode == . vshr vshl. d = optSecondaryOp( op2. 2010 143 .u32.wrap ) tb = tb & 0x1f. tb = partSelectSignExtend( b. r3. // 32-bit scalar operation. Signed shift fills with the sign bit.u32. and optional secondary arithmetic operation or subword data merge.b1.b2.op2 Description = = = = = { vshl. Instruction Set Table 106.atype. unsigned shift fills with zero. tmp.mode} d. .dtype. vshl. r2. { .u32{. tmp.mode}.sat}{.asel}.wrap }.bsel}.dtype . vshl: Shift a left by unsigned amount in b with optional saturate. vshl. . if ( mode == .add. a{.b0.s32. Left shift fills with zero.dtype. .u32.asel}. . r2.max }. a{. r1.atype.clamp && tb > 32 ) tb = 32. // optional secondary operation d = optMerge( dsel.clamp.bsel = { .clamp . vshr require sm_20 or later. vshr: Shift a right by unsigned amount in b with optional saturate.

with optional operand negates. . final signed (U32 * S32) + S32 // intermediate signed. // 32-bit scalar operation vmad.scale} d. internally this is represented as negation of the product (a*b). otherwise.asel = . which is used in computing averages.scale} d.asel}. {-}a{.S32 // intermediate signed.u32.bsel = { .po mode. . .h0. The “plus one” mode (. final signed -(U32 * S32) + S32 // intermediate signed. The final result is unsigned if the intermediate result is unsigned and c is not negated. .dtype.atype.U32 // intermediate unsigned.scale = { . final signed (S32 * U32) + S32 // intermediate signed. (a*b) is negated if and only if exactly one of a or b is negated. The source operands support optional negation with some restrictions. .PTX ISA Version 2. final signed (S32 * U32) .shr7.atype = . a{. .sat}{.b0. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. {-}c.S32 // intermediate signed. final signed -(S32 * S32) + S32 // intermediate signed. . final signed (S32 * S32) . and scaling. final signed (U32 * U32) .btype = { .atype. “plus one” mode.po{. final signed -(S32 * U32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift.bsel}. {-}b{. .shr15 }.asel}.S32 // intermediate signed. 2010 .b2. That is.b1. and the operand negates. Input c has the same sign as the intermediate result. PTX allows negation of either (a*b) or c. . Although PTX syntax allows separate negation of the a and b operands.s32 }. 144 January 24. vmad.b3. Description Calculate (a*b) + c.sat}{. c. the intermediate result is signed. and zero-extended otherwise. Depending on the sign of the a and b operands.dtype. .po) computes (a*b) + c + 1.h1 }. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. Source operands may not be negated in . final unsigned -(U32 * U32) + S32 // intermediate signed.0 Table 107.btype{.bsel}..dtype = . final signed (S32 * S32) + S32 // intermediate signed. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. b{. final signed (U32 * S32) . this result is sign-extended if the final result is signed.btype.

r3.po ) { lsb = 1.u32. -r3. lsb = 0.s32. asel ). 2010 145 . tmp[127:0] = ta * tb. Instruction Set Semantics // extract byte/half-word/word and sign.negate) || c.h0. case . tb = partSelectSignExtend( b. switch( scale ) { case .negate ^ b. r2. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).Chapter 8.negate ) { c = ~c. atype. r2. bsel ).h0. vmad requires sm_20 or later. January 24. } if ( .0.or zero-extend based on source operand type ta = partSelectSignExtend( a.negate ^ b. } else if ( c. if ( . r0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. S32_MAX. S32_MIN). signedFinal = isSigned(atype) || isSigned(btype) || (a.negate.s32. } else if ( a.u32. U32_MIN).negate ) { tmp = ~tmp.u32. lsb = 1. U32_MAX.sat vmad. else result = CLAMP(result. btype. lsb = 1.sat ) { if (signedFinal) result = CLAMP(result.shr7: result = (tmp >> 7) & 0xffffffffffffffff. r1.shr15 r0. tmp = tmp + c128 + lsb.u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vmad. r1.

cmp ) ? 1 : 0. . Semantics // extract byte/half-word/word and sign. tb = partSelectSignExtend( b.h0. // 32-bit scalar operation.max }. b{.b1.atype. .b2. vset. .op2 d. b{.lt vset.0 Table 108. r3. . . bsel ). btype.bsel}. { . .ne r1.cmp. .cmp . tb.btype.bsel}.ge }. . Compare input values using specified comparison. tmp. asel ).u32.btype. with optional data merge vset.s32 }. The intermediate result of the comparison is always unsigned. . with optional secondary arithmetic operation or subword data merge. with optional secondary operation vset. and therefore the c operand and final result are also unsigned. r1. .atype. // 32-bit scalar operation.ne. vset requires sm_20 or later. d = optSecondaryOp( op2. c ).lt. 146 January 24.atype.h1.le. c. .0. .u32. c.cmp d. . { .asel}. a{.PTX ISA Version 2.bsel}. r3. tmp.asel}. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.u32.b0. r2. .or zero-extend based on source operand type ta = partSelectSignExtend( a.cmp d.btype = { .b3.asel = . b{.dsel.gt.dsel .atype . tmp = compare( ta. r2. // optional secondary operation d = optMerge( dsel.h1 }.add. a{.op2 Description = = = = .eq.bsel = { . vset. 2010 .btype. c ).asel}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a{. atype. .s32.u32.min.

Chapter 8. trap. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Introduced in PTX ISA version 1.0. Supported on all target architectures. January 24. trap Abort execution and generate an interrupt to the host CPU. there are sixteen performance monitor events. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Notes PTX ISA Notes Target ISA Notes Examples Currently. with index specified by immediate operand a. trap. brkpt.4. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. The relationship between events and counters is programmed via API calls from the host. Introduced in PTX ISA version 1. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. pmevent 7. Supported on all target architectures.10.0. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.7. brkpt Suspends execution Introduced in PTX ISA version 1. @p pmevent 1. numbered 0 through 15. brkpt requires sm_11 or later. Table 111. Instruction Set 8. Triggers one of a fixed number of performance monitor events. pmevent a. Table 110. 2010 147 . brkpt.

2010 .0 148 January 24.PTX ISA Version 2.

%clock64 %pm0. 2010 149 . %lanemask_gt %clock. %lanemask_ge.Chapter 9. %pm3 January 24. read-only variables. …. %lanemask_lt. %lanemask_le. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. Special Registers PTX includes a number of predefined. which are visible as special registers and accessed through mov or cvt instructions.

v4.u32 %r0.z == 1 in 2D CTAs. cvt. Redefined as . // compute unified thread id for 2D CTA mov.0 Table 112. .x < %ntid.u16 %rh.0.u32 %r1.y == %tid.x.v4 . %tid.u32 %h1.u32 type in PTX 2. // legacy PTX 1. The fourth element is unused and always returns zero.u16 %r2. The %tid special register contains a 1D.z.sreg .z == 1 in 1D CTAs.0. %ntid.y.x to %rh Target ISA Notes Examples // legacy PTX 1.%tid. .z).x.y == %ntid.x.sreg .u32 %ntid.u32 %tid.sreg .%h2.v4 . mov.y 0 <= %tid.u32 type in PTX 2. read-only.u32.x code accessing 16-bit component of %tid mov. %ntid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u32 %tid. %tid. // CTA shape vector // CTA dimensions A predefined.%tid. . %ntid. CTA dimensions are non-zero. the fourth element is unused and always returns zero. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.z.v4. // zero-extend tid. %tid component values range from 0 through %ntid–1 in each CTA dimension.0.y.y < %ntid.%tid.%h1. Redefined as . Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. %tid.%ntid.z == 0 in 1D CTAs. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x. read-only special register initialized with the number of thread ids in each CTA dimension. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. // thread id vector // thread id components A predefined.%ntid. Supported on all target architectures. Every thread in the CTA has a unique %tid. PTX ISA Notes Introduced in PTX ISA version 1.x.u32 %ntid. mov.0.%tid.u16 %rh.z to %r2 Table 113. %ntid.%r0.y.x.u32 %h2. the %tid value in unused dimensions is 0. mov. mov.x 0 <= %tid.y * %ntid.z < %ntid. . The number of threads in each dimension are specified by the predefined special register %ntid. 2D.u32 %r0.z PTX ISA Notes Introduced in PTX ISA version 1. 2010 .x code Target ISA Notes Examples 150 January 24. per-thread special register initialized with the thread identifier within the CTA.sreg . Supported on all target architectures. It is guaranteed that: 0 <= %tid. mad. // move tid. or 3D vector to match the CTA shape.z == 0 in 2D CTAs.%tid. The total number of threads in a CTA is (%ntid.x * %ntid.z.x.PTX ISA Version 2. %tid.

mov. %warpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.u32 %nwarpid.0.u32 %r. A predefined. Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Table 116.3. read-only special register that returns the thread’s lane within the warp. e. %laneid. 2010 151 .sreg . Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.Chapter 9.u32 %warpid. . %nwarpid. read-only special register that returns the maximum number of warp identifiers. Introduced in PTX ISA version 1. Table 115. Supported on all target architectures. Special Registers Table 114. .sreg . Note that %warpid is volatile and returns the location of a thread at the moment when read.sreg .u32 %laneid. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. The lane identifier ranges from zero to WARP_SZ-1. due to rescheduling of threads following preemption. A predefined. %nwarpid requires sm_20 or later. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov. A predefined. mov. For this reason.g. Introduced in PTX ISA version 2. January 24.3. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %r. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. . read-only special register that returns the thread’s warp identifier. Supported on all target architectures. but its value may change during execution.u32 %r. The warp identifier will be the same for all threads within a single warp.

u32 %ctaid.x. %ctaid.y < %nctaid.0. The %nctaid special register contains a 3D grid shape vector. with each element having a value of at least 1.0.{x. It is guaranteed that: 0 <= %ctaid.z < %nctaid.x. The fourth element is unused and always returns zero.u32 mov. // Grid shape vector // Grid dimensions A predefined.%ctaid.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %nctaid . Supported on all target architectures.y.%ctaid. Supported on all target architectures.sreg .u16 %r0.sreg .x code Target ISA Notes Examples 152 January 24.536 PTX ISA Notes Introduced in PTX ISA version 1.u32 mov. Each vector element value is >= 0 and < 65535.z.v4 .x.x < %nctaid. It is guaranteed that: 1 <= %nctaid.%nctaid. depending on the shape and rank of the CTA grid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. %rh. 2D.y 0 <= %ctaid. mov. // CTA id vector // CTA id components A predefined.x code Target ISA Notes Examples Table 118. read-only special register initialized with the number of CTAs in each grid dimension.x. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. // legacy PTX 1. The %ctaid special register contains a 1D. mov.PTX ISA Version 2. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. .y.u32 %ctaid. read-only special register initialized with the CTA identifier within the CTA grid.u16 %r0.v4 .z.z} < 65.%nctaid. // legacy PTX 1. Redefined as . %rh. 2010 . . Redefined as .y.%nctaid.%nctaid.0.sreg .v4.y.x 0 <= %ctaid. .0. %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. or 3D vector.u32 %nctaid.v4.x. The fourth element is unused and always returns zero.sreg .0 Table 117.u32 type in PTX 2.u32 type in PTX 2.

u32 %r.0.u32 %gridid. so %nsmid may be larger than the physical number of SMs in the device. due to rescheduling of threads following preemption. mov. The SM identifier numbering is not guaranteed to be contiguous. Notes PTX ISA Notes Target ISA Notes Examples Table 120. e. A predefined. .g. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. 2010 153 . PTX ISA Notes Target ISA Notes Examples Table 121. . The SM identifier numbering is not guaranteed to be contiguous.u32 %nsmid. mov.sreg .Chapter 9. repeated launches of programs may occur. Note that %smid is volatile and returns the location of a thread at the moment when read.u32 %r. read-only special register initialized with the per-grid temporal grid identifier.u32 %smid. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. A predefined. . %smid. Supported on all target architectures. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Introduced in PTX ISA version 1. %nsmid. read-only special register that returns the maximum number of SM identifiers.3.sreg . PTX ISA Notes Target ISA Notes Examples January 24.u32 %r. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. mov. %gridid. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. // initialized at grid launch A predefined. This variable provides the temporal grid launch number for this context. %nsmid requires sm_20 or later. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. During execution.0. Supported on all target architectures. Introduced in PTX ISA version 2. where each launch starts a grid-of-CTAs. The SM identifier ranges from 0 to %nsmid-1.sreg . but its value may change during execution. Special Registers Table 119. Introduced in PTX ISA version 1.

%lanemask_eq. Table 123.u32 %r.u32 %r.u32 %lanemask_lt.sreg .u32 %r. . %lanemask_lt. mov. . %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Table 124. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. A predefined. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. A predefined.u32 %lanemask_eq. Introduced in PTX ISA version 2.0.u32 %lanemask_le.0.0. %lanemask_eq requires sm_20 or later. mov. %lanemask_le requires sm_20 or later. . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.sreg . 2010 . mov.PTX ISA Version 2. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg . Introduced in PTX ISA version 2.0 Table 122. 154 January 24. %lanemask_le.

%lanemask_ge. %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %lanemask_gt. mov. A predefined.0.u32 %r.sreg . .0. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Special Registers Table 125. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt requires sm_20 or later.u32 %lanemask_ge. Table 126.sreg . Introduced in PTX ISA version 2. mov. January 24. Introduced in PTX ISA version 2.Chapter 9. 2010 155 . %lanemask_ge requires sm_20 or later. A predefined. .

Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.u64 %clock64. Table 128.u64 r1. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.u32 %clock.%clock64.u32 r1. Their behavior is currently undefined. Special Registers: %pm0. . 2010 . 156 January 24. %clock64 requires sm_20 or later. %pm3.sreg . .u32 %pm0. %pm2.PTX ISA Version 2. %pm1. read-only 32-bit unsigned cycle counter. Table 129. read-only 64-bit unsigned cycle counter. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. mov. and %pm3 are unsigned 32-bit read-only performance monitor counters.u32 r1.0 Table 127.0. %pm3 %pm0. Introduced in PTX ISA version 2.0. %pm1. mov. . %pm1. Supported on all target architectures. The lower 32-bits of %clock64 are identical to %clock. mov. Special registers %pm0.3. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.%clock. Supported on all target architectures. %pm2. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.sreg . ….sreg . %pm2.%pm0.

version 1. Directives 10.1.version directive.Chapter 10.version .4 January 24. .target Table 130. Increments to the major number indicate incompatible changes to PTX.version directives are allowed provided they match the original . . Duplicate . Each ptx file must begin with a . PTX File Directives: .version Syntax Description Semantics PTX version number. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. 2010 157 .version . minor are integers Specifies the PTX language version number.version 2.version directive. and the target architecture for which the code was generated. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Supported on all target architectures.version major.0.0 . .minor // major.

including expanded rounding modifiers. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Target sm_20 Description Baseline feature set for sm_20 architecture.target directives can be used to change the set of target features allowed during parsing.texmode_unified) .global. with only half being used by instructions converted from . Texturing mode: (default is . vote instructions. sm_13. PTX File Directives: .texmode_independent texture and sampler information is bound together and accessed via a single . and an error is generated if an unsupported feature is used.red}.red}.PTX ISA Version 2.target Syntax Architecture and Platform target. Introduced in PTX ISA version 1.target directive specifies a single target architecture.texmode_unified . PTX code generated for a given target can be run on later generation devices. sm_11.f64 instructions used.texref descriptor. sm_10.red}. Requires map_f64_to_f32 if any . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. 64-bit {atom. A program with multiple .f64 instructions used.f64 instructions used. 158 January 24. Adds {atom.f64 to .shared. Disallows use of map_f64_to_f32. sm_12. A . Supported on all target architectures.0. texture and sampler information is referenced with independent . Adds {atom. map_f64_to_f32 }.f64 storage remains as 64-bits.samplerref descriptors. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.texref and .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. generations of SM architectures follow an “onion layer” model. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.5.target . . Texturing mode introduced in PTX ISA version 1. PTX features are checked against the specified target architecture. Each PTX file must begin with a . immediately followed by a .global.version directive. Adds double-precision support. texmode_independent. Requires map_f64_to_f32 if any . texmode_unified. Description Specifies the set of features in the target architecture for which the current ptx code was generated.0 Table 131.f32. brkpt instructions. The texturing mode is specified for an entire module and cannot be changed within the module. where each generation adds new features and retains all features of previous generations. In general. Requires map_f64_to_f32 if any . Therefore. The following table summarizes the features in PTX that vary according to target architecture.target directive containing a target architecture and optional platform options.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. 2010 . Note that . but subsequent .

texmode_independent January 24.Chapter 10.target sm_13 // supports double-precision .target sm_20.target sm_10 // baseline target architecture . Directives Examples . 2010 159 .

Kernel and Function Directives: . .5 and later. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. Supported on all target architectures. .entry kernel-name kernel-body Defines a kernel entry point name.param space memory and are listed within an optional parenthesized parameter list.b32 x. … } . PTX ISA Notes For PTX ISA version 1. with optional parameters. store. the kernel dimensions and properties are established and made available via special registers.param .param.2.entry .param .surfref variables may be passed as parameters.entry filter ( .reg . 2010 . In addition to normal parameters.b32 %r2.b32 %r<99>. opaque .entry . parameters.param instructions.func Table 132. e. Semantics Specify the entry point for a kernel program. parameter variables are declared in the kernel body.param. ld. %ntid. . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. ld.3. %nctaid.0 through 1. For PTX ISA versions 1. 160 January 24. [y]. . These parameters can only be referenced by name within texture and surface load.0 10.param instructions. etc.4 and later.b32 z ) Target ISA Notes Examples [x]. Parameters are passed via . The shape and size of the CTA executing the kernel are available in special registers.g.PTX ISA Version 2.entry Syntax Description Kernel entry point and body. . At kernel launch.param { .b32 y.0 through 1.b32 %r3. and query instructions and cannot be accessed via ld.b32 %r1.4.entry kernel-name ( param-list ) kernel-body .entry cta_fft . and body for the kernel function.texref. and . [z].param.samplerref. ld. parameter variables are declared in the kernel parameter list. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Parameters may be referenced by name within the kernel body and loaded into registers using ld. .

and recursion is illegal.reg . Directives Table 133. } … call (fooval). parameters must be in the register state space. mov. if any. . foo.func definition with no body provides a function prototype.param state space. .func (.result.b32 rval) foo (.reg . which may use a combination of registers and stack locations to pass parameters. Parameters must be base types in either the register or parameter state space.b32 localVar. 2010 161 .reg . Variadic functions are currently unimplemented.b32 rval. . Parameters in . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The implementation of parameter passing is left to the optimizing translator. … Description // return value in fooval January 24. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. ret. and supports recursion.2 for a description of variadic functions.b32 N. there is no stack. Parameters in register state space may be referenced directly within instructions in the function body.func fname (param-list) function-body .Chapter 10. implements an ABI with stack. Parameter passing is call-by-value.param and st. Variadic functions are represented using ellipsis following the last fixed argument.reg . PTX 2. … use N. The parameter lists define locally-scoped variables in the function body.x code.func Syntax Function definition.param instructions in the body. A . val1).0. Supported on all target architectures. PTX ISA 2.func (ret-param) fname (param-list) function-body Defines a function. Kernel and Function Directives: .func .0 with target sm_20 allows parameters in the . other code.param space are accessed using ld. including input and return parameters and optional function body. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. (val0. dbl.0 with target sm_20 supports at most one return value.func fname function-body . Release Notes For PTX ISA version 1.f64 dbl) { .

minnctapersm . 2010 .maxnreg.pragma The . for example. .entry directive and its body. The directives take precedence over any module-level constraints passed to the optimizing backend.maxnctapersm (deprecated) . PTX supports the following directives. . The interpretation of .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.minnctapersm directives may be applied per-entry and must appear between an . Currently.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxntid directive specifies the maximum number of threads in a thread block (CTA). and .3.pragma directives may appear at module (file) scope. and the strings have no semantics within the PTX virtual machine model. or as statements within a kernel or device function body. the .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). 162 January 24. registers) to increase total thread count and provide a greater opportunity to hide memory latency. A general .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. at entry-scope. These can be used.maxntid and .pragma directive is supported for passing information to the PTX backend. to throttle the resource requirements (e.PTX ISA Version 2.maxntid. and the . which pass information to the backend optimizing compiler. Note that .maxntid . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. The directive passes a list of strings to the backend. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. the . The .g.0 10.maxnreg .

maxntid 256 .maxnreg n Declare the maximum number of registers per thread in a CTA.16. Supported on all target architectures. Directives Table 134.maxntid . 2010 163 . Performance-Tuning Directives: . Introduced in PTX ISA version 1.maxctapersm.maxntid and . the backend may be able to compile to fewer registers. or 3D CTA. .Chapter 10. .maxntid 16.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid nx . The actual number of registers used may be less.entry foo . or the maximum number of registers may be further constrained by .entry bar . Supported on all target architectures.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. for example. . ny . 2D. Introduced in PTX ISA version 1.entry foo .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. nz Declare the maximum number of threads in the thread block (CTA).3.maxntid nx. The compiler guarantees that this limit will not be exceeded. .maxntid nx.maxnreg . The maximum number of threads is the product of the maximum extent in each dimension. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Performance-Tuning Directives: . ny. Exceeding any of these limits results in a runtime error or kernel launch failure. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid Syntax Maximum number of threads in thread block (CTA).3.

Supported on all target architectures. Performance-Tuning Directives: .maxntid to be specified as well.entry foo .0 Table 136. additional CTAs may be mapped to a single multiprocessor.maxnctapersm.minnctapersm generally need . Performance-Tuning Directives: .maxntid and .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.minnctapersm .PTX ISA Version 2. Supported on all target architectures.minnctapersm in PTX ISA version 2.maxnctapersm has been renamed to . .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. .maxnctapersm generally need .0 as a replacement for .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid to be specified as well. .maxntid 256 . However.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. Optimizations based on .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. .maxntid 256 . The optimizing backend compiler uses . if the number of registers used by the backend is sufficiently lower than this bound. Deprecated in PTX ISA version 2. 2010 . .3.entry foo .0. For this reason. Introduced in PTX ISA version 1.0.minnctapersm 4 { … } 164 January 24.maxnctapersm (deprecated) . Optimizations based on .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Introduced in PTX ISA version 2.

pragma “nounroll”. Directives Table 138.pragma directive strings is implementation-specific and has no impact on PTX semantics. 2010 165 .entry foo . .pragma “nounroll”. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Performance-Tuning Directives: . at entry-scope. Supported on all target architectures.pragma directive may occur at module-scope. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma list-of-strings . or statement-level directives to the PTX backend compiler. Introduced in PTX ISA version 2.Chapter 10. The interpretation of .0. Pass module-scoped. The . entry-scoped.pragma Syntax Description Pass directives to PTX backend compiler. { … } January 24. . or at statementlevel.pragma .

2.section .. 0x63613031. @@DWARF dwarf-string dwarf-string may have one of the .4byte .x code.loc The .debug_pubnames.section . 0x00. replaced by .264-1] .section directive. @progbits .4. 0x00. Supported on all target architectures..byte byte-list // comma-separated hexadecimal byte values . 0x02. 0x00. The @@DWARF syntax is deprecated as of PTX version 2. 0x00.byte 0x2b.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x00 166 January 24. Table 139. 0x00 . 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. “”.byte 0x00.0 but is supported for legacy PTX version 1. Deprecated as of PTX 2.file .232-1] . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .0. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .0 and replaces the @@DWARF syntax.0 10. 0x5f736f63 .quad int64-list // comma-separated hexadecimal integers in range [0. 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0. 0x00000364. 0x736d6172 . 2010 .4byte 0x6e69616d.4byte label .PTX ISA Version 2. Introduced in PTX ISA version 1. 0x6150736f.4byte 0x000006b5.debug_info . 0x61395a5f.section directive is new in PTX ISA verison 2.

Supported on all target architectures.b8 0x2b. .. Debugging Directives: . 0x00.loc line_number January 24. 0x00 0x61395a5f.section . replaces @@DWARF syntax.section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x6e69616d.0.debug_pubnames { .. 0x00.b32 .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b64 int64-list // comma-separated list of integers in range [0.debug_info . 0x00. 2010 167 .b32 label .264-1] .loc .file .b8 0x00. Supported on all target architectures.0. Source file information. Debugging Directives: . 0x63613031.232-1] .b8 byte-list // comma-separated list of integers in range [0. . } 0x02.255] . 0x00.Chapter 10.file filename Table 142. .. . 0x00000364. 0x00.b32 int32-list // comma-separated list of integers in range [0.b32 0x000006b5.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x5f736f63 0x6150736f.0.section . Directives Table 140. Supported on all target architectures. Debugging Directives: . . Source file location. 0x736d6172 0x00 Table 141. 0x00. . .section Syntax PTX section definition.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

global .0 10. // foo is defined in another module Table 144.visible identifier Declares identifier to be externally visible.extern . Introduced in PTX ISA version 1.b32 foo.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern identifier Declares identifier to be defined externally. Supported on all target architectures.extern .extern . .PTX ISA Version 2. .0. . 2010 . Linking Directives: .visible Table 143. Linking Directives . Introduced in PTX ISA version 1.b32 foo.global .6.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.0. . Linking Directives: . // foo will be externally visible 168 January 24.visible .visible . Supported on all target architectures.

3 PTX ISA 1.0 PTX ISA 1.5 PTX ISA 2.2 CUDA 2.1 CUDA 2. and the remaining sections provide a record of changes in previous releases.3 driver r190 CUDA 3. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0.4 PTX ISA 1. 2010 169 .0 CUDA 2.0 driver r195 PTX ISA Version PTX ISA 1.1 PTX ISA 1.1 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.2 PTX ISA 1.0 January 24.Chapter 11. CUDA Release CUDA 1.0 CUDA 1. The release history is as follows.

x code and sm_1x targets.sat modifiers.f32 and mad.f32 require a rounding modifier for sm_20 targets.0 11.PTX ISA Version 2.f32 instruction also supports . The mad. New Features 11. 2010 . The goal is to achieve IEEE 754 compliance wherever possible. and sqrt with IEEE 754 compliant rounding have been added. Single-precision add. and mul now support . A single-precision fused multiply-add (fma) instruction has been added.1.rp rounding modifiers for sm_20 targets.1. The changes from PTX ISA 1. The . rcp. The mad. Changes in Version 2.1.ftz modifier may be used to enforce backward compatibility with sm_1x.f32 for sm_20 targets.0 for sm_20 targets. while maximizing backward compatibility with legacy PTX 1. When code compiled for sm_1x is executed on sm_20 devices.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.1. These are indicated by the use of a rounding modifier and require sm_20. Instructions testp and copysign have been added.rm and .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.1. The fma. sub.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rn. • • • • • 170 January 24. fma.f32 maps to fma.f32.1. Floating-Point Extensions This section describes the floating-point changes in PTX 2. Both fma.ftz and . Single.and double-precision div. mad.0 11.f32 requires sm_20.

maxnctapersm directive was deprecated and replaced with . brev. Instructions {atom.ballot.f32 have been implemented. Surface instructions support additional . Instructions prefetch and prefetchu have also been added. has been added. and shared addresses to generic address and vice-versa has been added.clamp modifiers.pred have been added.u32 and bar. membar. prefetch.zero.1.1.lt.sys. Video instructions (includes prmt) have been added.arrive instruction has been added. 2010 171 . isspacep. and sust. The bar instruction has been extended as follows: • • • A bar. vote. New instructions A “load uniform” instruction. local.red. atom.red. January 24. prefetchu.shared have been extended to handle 64-bit data types for sm_20 targets. st. has been added.add. New special registers %nsmid.gt} have been added. st. e. %lanemask_{eq. has been added. A “vote ballot” instruction. Instruction sust now supports formatted surface stores. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Release Notes 11. cvta.ge. has been added. A “find leading non-sign bit” instruction.1. has been added. bfe and bfi.b32.1.clamp and . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. have been added.g. Bit field extract and insert instructions. A new directive. 11. ldu. for prefetching to specified level of memory hierarchy.{and. clz.Chapter 11. Other new features Instructions ld. has been added. popc. The .le. bfind. .section. and red now support generic addressing.or}. Instructions bar. %clock64. Cache operations have been added to instructions ld. . suld. ldu.minnctapersm to better match its behavior and usage. A “bit reversal” instruction. Instruction cvta for converting global.red}. A “population count” instruction. bar now supports optional thread count and register operands. A “count leading zeros” instruction.popc.red}. has been added. A system-level membar instruction. Instructions {atom.2.3.

172 January 24. 11. stack-based ABI is unimplemented.target sm_1x.5. Formatted surface store with .3.u32.s32. {atom. cvt. call suld.{u32. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.1. the correct number is sixteen.p.2.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.1.p sust. The underlying. Support for variadic functions and alloca are unimplemented.f32 type is unimplemented.5 and later.red}.4 and earlier. Semantic Changes and Clarifications The errata in cvt. . Formatted surface load is unimplemented.f32. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.version is 1. or .PTX ISA Version 2. if . See individual instruction descriptions for details.4 or earlier. In PTX version 1. To maintain compatibility with legacy PTX code.0 11. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.ftz for PTX ISA versions 1.s32.max} are not implemented.f32} atom. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.ftz (and cvt for .{min. has been fixed. Instruction bra. where . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. 2010 .

Table 145.pragma “nounroll”. . including loops preceding the . disables unrolling of0 the loop for which the current block is the loop header. Note that in order to have the desired effect at statement level. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.0.pragma “nounroll”. Ignored for sm_1x targets. . L1_body: … L1_continue: bra L1_head. The “nounroll” pragma is allowed at module.entry foo (…) .pragma.pragma “nounroll”. Supported only for sm_20 targets. … @p bra L1_end. L1_end: … } // do not unroll this loop January 24. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.Appendix A. Descriptions of .pragma strings defined by ptxas. disables unrolling for all loops in the entry function body. and statement levels. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. entry-function. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. 2010 173 .func bar (…) { … L1_head: . { … } // do not unroll any loop in this function .pragma Strings This section describes the .

PTX ISA Version 2. 2010 .0 174 January 24.

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