NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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...............................................6.4........ Types........................................................ 37 Array Declarations ............................................................. 46 6.....................6.................... Types ................4.......................... 6......... 29 Global State Space ....................... 5......................................................................... 5.......................................... 5........5............................................1.......... 41 Destination Operands ................... 33 Restricted Use of Sub-Word Sizes ................. 27 5...............................4........................................... 41 Source Operands.........................................................1....1...4........1................6... Arrays...1...... Chapter 6............2.....................5.............................................. 5.......... 42 Addresses as Operands ............... 5....................... 25 Chapter 5............. 49 ii January 24..............................8................................................. 38 Alignment .................. 43 Labels and Function Names as Operands ............................. 5................ Operand Costs ........................................2.................................................. Function declarations and definitions ....................................................... 28 Special Register State Space .7.4..... and Surface Types ............................................1....................... 5.............................. 39 5..... 6......... 5...................3....................................................................................4.................. 27 Register State Space .2..............4........ 33 Fundamental Types .................................... 34 Variables .......5..1........ 6.............................................. 5............................PTX ISA Version 2. 32 5.............................................1....................................................................5........ 28 Constant State Space ............................................................1.................................................. Texture.............................................5.............................................. 5.. 41 Using Addresses.......1............................5.................4........ 37 Variable Declarations ....... 32 Texture State Space (deprecated) .............. 39 Parameterized Variable Names ........................................................ 5............................... 6....................... 37 Vectors .................................. and Variables .................................................................................. State Spaces..............................................................................6.4...... 44 Rounding Modifiers .........................1..................2.2................................... 2010 .............................. 29 Parameter State Space ...4........... 6.............1............. 42 Arrays as Operands .............. 47 Chapter 7.......................................................................... 5................ 30 Shared State Space............................. Type Conversion.......................................................... 41 6...........4............... and Vectors ............4.................................................. 49 7............3.....2................................2................................................................2........................................... 43 Vectors as Operands ..................................................................... 6..... Summary of Constant Expression Evaluation Rules ................................................................... 6....3............. Instruction Operands..................1..............1........................................................1............... 5.................................... Operand Type Information ........................ 5............................................ 5....4................................. 5....0 4....3...... 29 Local State Space ......... 6........... State Spaces ........................2.........................................................3............... Abstracting the ABI ...1.................4.........................4.................... 38 Initializers ..... 44 Scalar Conversions ............. 6...... 33 5............ 43 6...................................................... Sampler...............

................................................................................................................... 62 Semantics .......................... 52 Variadic functions ................................ 60 8......... 108 Texture and Surface Instructions ... 8. Release Notes ....................................3......................... Changes from PTX 1............................................. 81 Comparison and Selection Instructions .............1..................................1...................... PTX Version and Target Directives ..................................1................1..............3............. 162 Debugging Directives ............................. 122 Control Flow Instructions ..8................... 53 Alloca ......................................................................7..........0 .........7....................... 8.................................................................................................3..................................7... 8....2............................... 10...7................................... 8............... 55 PTX Instructions .........................4........................7........ 56 Comparisons ................. 7..7...........4....... 7.................7................................... 8...................................................................................................... 62 8............................................................................................... 8.......... 149 Chapter 10...... 62 Machine-Specific Semantics of 16-bit Code ................. Directives ... 100 Logic and Shift Instructions ..................4....... 8.......................2................... Changes in Version 2.3.............. 8............................ 54 Chapter 8......................................................................2....................2............................................................ 10............................7................................................................................................ 166 Linking Directives ..........................1....................... 170 New Features ................................................................. 160 Performance-Tuning Directives ................3..........3..................1.......... 59 Operand Size Exceeding Instruction-Type Size ...................... 11....................... 2010 iii ......... 147 8.............. Type Information for Instructions and Operands ..... 10. 8....................... 169 11.................... 58 8............................1..... 10........................................ 8.......................1...................5..................... 55 8..................................... 168 Chapter 11.........................1...7........7............................................................................... 157 Specifying Kernel Entry Points and Functions .................. 8..........................7..............1........ 8................................................. 140 Miscellaneous Instructions....................................................... Format and Semantics of Instruction Descriptions ............... Divergence of Threads in Control Constructs ........................................... 63 Floating-Point Instructions .................... Instruction Set ... Special Registers ......................x ....................................10..................................................................... Instructions ................. 11.........7................6............... 104 Data Movement and Conversion Instructions ...4.................2.. 8. 157 10........ 57 Manipulating Predicates ............7............6...... 170 Semantic Changes and Clarifications ... 8.6......... 172 Unimplemented Features Remaining .................................................................. 172 January 24.............. 63 Integer Arithmetic Instructions .......................................................3.............. 129 Parallel Synchronization and Communication Instructions .................... 8................... 55 Predicated Execution .........................................................1.................................2...........................1..................................5.....6.............................. 11...........................................1..9..................................... Chapter 9.. 132 Video Instructions ........................... 8.............

..PTX ISA Version 2....... 2010 .......0 Appendix A.................pragma Strings............... 173 iv January 24............. Descriptions of .......

............. Table 18....... 71 January 24.................. Table 19............................................................................ Table 25............................. Table 10. 66 Integer Arithmetic Instructions: subc .......................................... 27 Properties of State Spaces .................... Table 21................................................................................................ 2010 v .................. Table 12....................... 69 Integer Arithmetic Instructions: mad24 ........... Table 20................................................................................... 20 Operator Precedence ........ PTX Directives ............ Table 11............................................ Table 6.......... 58 Type Checking Rules ....................................... Table 7............................................................. Table 9........................................ 23 Constant Expression Evaluation Rules .............................. Table 16. 64 Integer Arithmetic Instructions: add..............................................................................................cc ........................................................................... Table 3.............................. Table 4.. Table 27....................................... 46 Cost Estimates for Accessing State-Spaces ..................... and Bit-Size Types ................................. Table 31. Table 8.............................................. 35 Opaque Type Fields in Independent Texture Mode ...................................................................................................... 28 Fundamental Type Specifiers ...........................................cc ............................................................................................ Table 30.... 47 Operators for Signed Integer.............................................................................................................................................. 25 State Spaces .... 59 Relaxed Type-checking Rules for Source Operands ....... 66 Integer Arithmetic Instructions: mul .. 46 Integer Rounding Modifiers ....................................... 35 Convert Instruction Precision and Format ................... 58 Floating-Point Comparison Operators Testing for NaN ............................... Table 14................. Table 22.................. 57 Floating-Point Comparison Operators ............................ Table 15.......................... Table 2.............................. 19 Predefined Identifiers ..................................... Table 17........................ Unsigned Integer. 64 Integer Arithmetic Instructions: sub ............................... 65 Integer Arithmetic Instructions: sub..................... 57 Floating-Point Comparison Operators Accepting NaN .... Table 26...................................... Table 32................................... 33 Opaque Type Fields in Unified Texture Mode ...................................................................................... 65 Integer Arithmetic Instructions: addc ....................................... Table 23.......... 61 Integer Arithmetic Instructions: add .......................List of Tables Table 1......................................................................... 60 Relaxed Type-checking Rules for Destination Operands..... Table 29................................. Table 24.......................................................... 67 Integer Arithmetic Instructions: mad ................. Table 28..................................................................... Table 5....... 68 Integer Arithmetic Instructions: mul24 ...... Table 13. 70 Integer Arithmetic Instructions: sad ................... 45 Floating-Point Rounding Modifiers .......................................................... 18 Reserved Instruction Keywords ........

......................... 74 Integer Arithmetic Instructions: bfind .......... 72 Integer Arithmetic Instructions: min ..................................................................................... 92 Floating-Point Instructions: rcp .......... Table 37................................................ Table 54.......... 103 Comparison and Selection Instructions: slct ...............0 Table 33............... 73 Integer Arithmetic Instructions: max .. 84 Floating-Point Instructions: sub .............................................................................................................................. Table 61.................................................... Table 69.................................................................................................... Table 40................ Table 60............................................................................... 94 Floating-Point Instructions: rsqrt ............. 87 Floating-Point Instructions: mad ...................... Table 34.... 71 Integer Arithmetic Instructions: abs ...... Table 38................. 97 Floating-Point Instructions: lg2 .............................................................. Table 64.......... Table 63............. Table 39............ 75 Integer Arithmetic Instructions: brev ....................................................................................................................................................................... Table 55. Table 35.... 86 Floating-Point Instructions: fma .. Table 51........ Table 43...................................... Table 44................................................. Table 41.................................................................. 103 vi January 24................................................... 85 Floating-Point Instructions: mul .. 101 Comparison and Selection Instructions: setp ................... Table 56...................... 96 Floating-Point Instructions: cos ....... 74 Integer Arithmetic Instructions: clz .................................. 72 Integer Arithmetic Instructions: neg ................. 99 Comparison and Selection Instructions: set ...... 76 Integer Arithmetic Instructions: bfe .............................. 83 Floating-Point Instructions: copysign ................ 102 Comparison and Selection Instructions: selp . 71 Integer Arithmetic Instructions: rem ....................... Table 53............................................................ Table 47........................................................... Table 59............................................................................................................ 73 Integer Arithmetic Instructions: popc ................................................................................ Table 58.................................................................................... 95 Floating-Point Instructions: sin ....................................................................................................................... 93 Floating-Point Instructions: sqrt ........................................................................................................................................................................ 78 Integer Arithmetic Instructions: prmt .................................................................................. 82 Floating-Point Instructions: testp ............... Table 67..... 2010 . Table 48.... 83 Floating-Point Instructions: add ................................................... 79 Summary of Floating-Point Instructions ......................................................................... 92 Floating-Point Instructions: max ............... Integer Arithmetic Instructions: div ......... 90 Floating-Point Instructions: abs ........................................ Table 66.................... Table 62....................................................................................... Table 42........... Table 68.... 91 Floating-Point Instructions: min ............... 98 Floating-Point Instructions: ex2 ............................. Table 57......................... Table 52............................PTX ISA Version 2.......... Table 45................................. Table 65........................................................... 91 Floating-Point Instructions: neg ......................................... Table 36............................ 77 Integer Arithmetic Instructions: bfi ........................................................... 88 Floating-Point Instructions: div ............. Table 49.................... Table 46.................... Table 50......................

.......................... 126 Texture and Surface Instructions: sured............................................................................ 119 Data Movement and Conversion Instructions: cvt .......................... vmax .......................................... 131 Control Flow Instructions: exit ............ 116 Data Movement and Conversion Instructions: prefetch................................................................ 130 Control Flow Instructions: call ........................ Table 104...................... Table 72.......... Table 84.......................... vshr ............................ Table 98............ 123 Texture and Surface Instructions: txq ................... vsub................................. Table 90............................. 119 Data Movement and Conversion Instructions: cvta .............................. Table 71........ 105 Logic and Shift Instructions: xor .............................................. 107 Logic and Shift Instructions: shr ....... 120 Texture and Surface Instructions: tex . Table 100.................................................. Table 80............ Table 86...... 124 Texture and Surface Instructions: suld .............. 135 Parallel Synchronization and Communication Instructions: red .................................................................... Table 106. 129 Control Flow Instructions: @ .. 128 Control Flow Instructions: { } ................................................................. 131 Parallel Synchronization and Communication Instructions: bar ....................................... Table 97........ vabsdiff......................................... 129 Control Flow Instructions: bra ...... Table 88............................ Table 92................................................... Table 83........ 106 Logic and Shift Instructions: shl ....................................................... Table 103.............................................. Table 75................. 127 Texture and Surface Instructions: suq ....................................... Table 74.............. Table 93.............................................. Table 94......... Table 81............................... 137 Parallel Synchronization and Communication Instructions: vote .. 109 Cache Operators for Memory Store Instructions ...... Table 73......................... 106 Logic and Shift Instructions: cnot ...... Table 99.............................. Table 85........................................ 112 Data Movement and Conversion Instructions: ld .............. 133 Parallel Synchronization and Communication Instructions: membar ...................... Table 79.. Table 77.. 115 Data Movement and Conversion Instructions: st .................................. 125 Texture and Surface Instructions: sust ........................ Table 105........................... 110 Data Movement and Conversion Instructions: mov ... 105 Logic and Shift Instructions: or .................................. Table 95....................... Table 102.................Table 70......... vmin................. Table 89............. Table 96............. 113 Data Movement and Conversion Instructions: ldu ....... Table 76. 139 Video Instructions: vadd.............................................................. Table 91.................................................................................................................... 142 Video Instructions: vshl... 130 Control Flow Instructions: ret .......................................... 143 January 24...................................... 107 Cache Operators for Memory Load Instructions ....................... Table 78.............................. Table 87.................................................................................. 118 Data Movement and Conversion Instructions: isspacep ......................................... Logic and Shift Instructions: and ................ 2010 vii ......................................................................................... Table 101......... prefetchu ....................................... 106 Logic and Shift Instructions: not ........................ Table 82....... 134 Parallel Synchronization and Communication Instructions: atom ............... 111 Data Movement and Conversion Instructions: mov .........................

...............file ... %pm1.......................func ............................... Table 126......................... 144 Video Instructions: vset... 147 Special Registers: %tid ... 166 Debugging Directives: ................ 154 Special Registers: %lanemask_lt ............. 151 Special Registers: %ctaid .... 164 Performance-Tuning Directives: ............................. Table 121...section . 154 Special Registers: %lanemask_ge ...extern............. Table 130... Table 116......................0 Table 107............................... 146 Miscellaneous Instructions: trap ............................................................. Table 142.............................................PTX ISA Version 2............................. Table 123.....entry...................... 151 Special Registers: %warpid ................ 150 Special Registers: %ntid ........ Table 114........................................................................................................................................................................................... 165 Debugging Directives: @@DWARF ....................................... 163 Performance-Tuning Directives: ....... Table 119.. 167 Debugging Directives: ................. 164 Performance-Tuning Directives: ....... 157 PTX File Directives: ..........target ..... 153 Special Registers: %lanemask_eq ................. 150 Special Registers: %laneid .................................. 160 Kernel and Function Directives: . Table 117............ 151 Special Registers: %nwarpid .............. Table 133.. Table 132.................. Table 108.............. Table 136..........version.................................................................. 158 Kernel and Function Directives: ........................... Table 141........... 167 Linking Directives: ........................................................................................................................ 2010 ........... Table 137........................ Table 120..................................................................................................................................... Table 143................................................................................................ 153 Special Registers: %nsmid ..................... Table 140................... 154 Special Registers: %lanemask_le ...... 152 Special Registers: %nctaid . 161 Performance-Tuning Directives: .. Table 134.. 156 Special Registers: %pm0........... 163 Performance-Tuning Directives: ...........................maxnreg ................................................................................. Table 118... 155 Special Registers: %clock .............................. 168 viii January 24....................... Table 125...... 147 Miscellaneous Instructions: pmevent....................................................................................................... Table 129............................................... 152 Special Registers: %smid .............................. Table 109........ Table 115..... Table 135.................................................pragma ...................................................... Table 131................................................................................. 167 Debugging Directives: ............................................................................... 156 PTX File Directives: ................................................................................ Table 110......... Table 111................................................................ Table 112.......................................... Table 138................................. 156 Special Registers: %clock64 ..............maxnctapersm (deprecated) ........................ Table 128...................... %pm3 .................................... 147 Miscellaneous Instructions: brkpt .......................................................................................................................... %pm2......... Table 139........................ Table 127............ 153 Special Registers: %gridid ....... Table 122............................... Table 124................................ Table 113....................................................... 155 Special Registers: %lanemask_gt ...loc .............minnctapersm ................maxntid ........................................................................ Video Instructions: vmad .....................

........Table 144...................................... Linking Directives: ............................................. 2010 ix .................. 173 January 24................................. Table 145........ 168 Pragma Strings: “nounroll” ........visible.............

2010 .0 x January 24.PTX ISA Version 2.

Similarly. and pattern recognition can map image blocks and pixels to parallel processing threads. 1.1.2. In fact. 2010 1 . the memory access latency can be hidden with calculations instead of big data caches. which are optimized for and translated to native target-architecture instructions. high-definition 3D graphics. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. the programmable GPU has evolved into a highly parallel. there is a lower requirement for sophisticated flow control. Data-parallel processing maps data elements to parallel processing threads.Chapter 1. and because it is executed on many data elements and has high arithmetic intensity. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. stereo vision. January 24. 1. image and media processing applications such as post-processing of rendered images. Because the same program is executed for each data element. PTX exposes the GPU as a data-parallel computing device. from general signal processing or physics simulation to computational finance or computational biology. Introduction This document describes PTX. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. PTX defines a virtual machine and ISA for general purpose parallel thread execution. video encoding and decoding. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. PTX programs are translated at install time to the target hardware instruction set. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. image scaling. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. many-core processor with tremendous computational horsepower and very high memory bandwidth. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). multithreaded.

Legacy PTX 1. fma. Provide a common source-level ISA for optimizing code generators and translators. performance kernels.0 is in improved support for the IEEE 754 floating-point standard. Single-precision add. The changes from PTX ISA 1. Provide a machine-independent ISA for C/C++ and other compilers to target.rn. A “flush-to-zero” (. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. A single-precision fused multiply-add (fma) instruction has been added.rp rounding modifiers for sm_20 targets.3. including integer. and video instructions.1.0 is a superset of PTX 1.3. 1.f32 require a rounding modifier for sm_20 targets. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. barrier. 1. PTX 2. The mad.PTX ISA Version 2. Provide a code distribution ISA for application and middleware developers. Achieve performance in compiled applications comparable to native GPU performance. atomic. Facilitate hand-coding of libraries.f32 requires sm_20.ftz) modifier may be used to enforce backward compatibility with sm_1x. PTX ISA Version 2. surface.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.0 are improved support for IEEE 754 floating-point operations. Both fma.sat modifiers.0 PTX ISA Version 2. Most of the new features require a sm_20 target.rm and .0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. memory.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.f32 and mad.f32. The main areas of change in PTX 2. The fma. and all PTX 1.x code will continue to run on sm_1x targets as well.ftz and . and mul now support . and architecture tests.f32 instruction also supports .0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. and the introduction of many new instructions. which map PTX to specific target machines. • • • 2 January 24. Improved Floating-Point Support A main area of change in PTX 2.x features are supported on the new sm_20 target.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 for sm_20 targets. mad. When code compiled for sm_1x is executed on sm_20 devices.f32 maps to fma. Instructions marked with .x. sub. addition of generic addressing to facilitate the use of general-purpose pointers. 2010 . reduction. The mad.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.

See Section 7 for details of the function definition and call syntax needed to abstract the ABI.4. suld. January 24. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. 2010 3 . local. These are indicated by the use of a rounding modifier and require sm_20. isspacep. so recursion is not yet supported. and Application Binary Interface (ABI). Surface Instructions • • Instruction sust now supports formatted surface stores. Support for an Application Binary Interface Rather than expose details of a particular calling convention. allowing memory instructions to access these spaces without needing to specify the state space.Chapter 1. Generic addressing unifies the global. .3. stack-based ABI. NOTE: The current version of PTX does not implement the underlying. Instruction cvta for converting global. these changes bring PTX 2. and vice versa. rcp. and directives are introduced in PTX 2. 1. and red now support generic addressing.0 closer to full compliance with the IEEE 754 standard.clamp and . • Taken as a whole. special registers. cvta. an address that is the same across all threads in a warp. stack layout. e.e.2.zero.3. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. and shared addresses to generic address and vice-versa has been added. Instructions prefetch and prefetchu have been added.3. Cache operations have been added to instructions ld. 1.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. i. st. ldu. prefetch. PTX 2. instructions ld. 1.g. Instructions testp and copysign have been added. New Instructions The following new instructions. prefetchu. local.3. and sqrt with IEEE 754 compliant rounding have been added. local. for prefetching to specified level of memory hierarchy.0. In PTX 2.. A new cvta instruction has been added to convert global. Generic Addressing Another major change is the addition of generic addressing. and shared addresses to generic addresses. and sust. Introduction • Single. st. and shared state spaces.0. Surface instructions support additional clamp modifiers.and double-precision div. atom.

PTX ISA Version 2. %clock64. Other Extensions • • • Video instructions (includes prmt) have been added.le.sys. vote. bfi bit field extract and insert popc clz Atomic.u32 and bar.gt} have been added.ge. .arrive instruction has been added.red.lt. membar.ballot. %lanemask_{eq. has been added.f32 have been added. Barrier Instructions • • A system-level membar instruction.red.shared have been extended to handle 64-bit data types for sm_20 targets. bar now supports an optional thread count and register operands. A new directive.b32.section. 2010 .red}.red}. New special registers %nsmid. 4 January 24.popc. has been added. and Vote Instructions • • • New atomic and reduction instructions {atom. Reduction. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.{and.or}. Instructions {atom.add. A “vote ballot” instruction. A bar. Instructions bar.pred have been added.

Chapter 5 describes state spaces.0. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 9 lists special registers. Chapter 6 describes instruction operands. and variable declarations. Chapter 7 describes the function and call syntax. 2010 5 . Chapter 3 gives an overview of the PTX virtual machine model. types. Chapter 10 lists the assembly directives supported in PTX.Chapter 1. Chapter 4 describes the basic syntax of the PTX language. Chapter 11 provides release notes for PTX Version 2. January 24.4. Introduction 1. calling convention. Chapter 8 describes the instruction set.

2010 .PTX ISA Version 2.0 6 January 24.

is an array of threads that execute a kernel concurrently or in parallel. or 3D shape specified by a three-element vector ntid (with elements ntid. 2D. 2D.2. work. The vector ntid specifies the number of threads in each CTA dimension. A cooperative thread array. 2. but independently on different data.z). assign specific input and output positions. 2010 7 . Programming Model 2. compute-intensive portions of applications running on the host are off-loaded onto the device. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. and select work to perform.2. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. data-parallel. and tid. a portion of an application that is executed many times.1.x. or CTA.x. Each CTA has a 1D. tid. and results across the threads of the CTA. The thread identifier is a three-element vector tid. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. can be isolated into a kernel function that is executed on the GPU as many different threads.y. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Threads within a CTA can communicate with each other. compute addresses. and ntid. Each CTA thread uses its thread identifier to determine its assigned role. ntid. or host: In other words.1. (with elements tid. More precisely. one can specify synchronization points where threads wait until all threads in the CTA have arrived. Programs use a data parallel decomposition to partition inputs. To that effect. 2. or 3D CTA.z) that specifies the thread’s position within a 1D. It operates as a coprocessor to the main CPU. To coordinate the communication of the threads within the CTA.Chapter 2. January 24.y. Each thread has a unique thread identifier within the CTA. Cooperative thread arrays (CTAs) implement CUDA thread blocks.

A warp is a maximal subset of threads from a single CTA.2. 2. %ctaid. a warp has 32 threads. such that the threads execute the same instructions at the same time. However. CTAs that execute the same kernel can be batched together into a grid of CTAs.0 Threads within a CTA execute in SIMT (single-instruction. 2D . %ntid. Each grid also has a unique temporal grid identifier (gridid). so PTX includes a run-time immediate constant. Threads within a warp are sequentially numbered. or sequentially. 8 January 24. Some applications may be able to maximize performance with knowledge of the warp size. multiple-thread) fashion in groups called warps. so that the total number of threads that can be launched in a single kernel invocation is very large. This comes at the expense of reduced thread communication and synchronization. 2010 . Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). which may be used in any instruction where an immediate operand is allowed. The warp size is a machine-dependent constant. The host issues a succession of kernel invocations to the device. Threads may read and use these values through predefined. WARP_SZ. or 3D shape specified by the parameter nctaid. read-only special registers %tid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Typically.2. depending on the platform. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs.PTX ISA Version 2. and %gridid. because threads in different CTAs cannot communicate and synchronize with each other. Multiple CTAs may execute concurrently and in parallel. Each grid of CTAs has a 1D. %nctaid.

Chapter 2. 2) Thread (3. 1) Thread (3. 1) Thread (2. 1) Thread (1. Thread Batching January 24. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) Thread (3. 1) Thread (0. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) CTA (2. 0) Thread (2. 2) Thread (2. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (4. 0) CTA (2. 0) Thread (1. 2) Thread (4. 0) CTA (0. 0) CTA (1. 0) Thread (0. 1) Thread (0. A grid is a set of CTAs that execute independently. 2) Thread (1. 1) CTA (1. 2010 9 . 1) Thread (4. Figure 1.

referred to as host memory and device memory. and texture memory spaces are optimized for different memory usages. as well as data filtering. The device memory may be mapped and read or written by the host. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. respectively. all threads have access to the same global memory. for some specific data formats. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Finally. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Both the host and the device maintain their own local memory. The global. constant. Each thread has a private local memory. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. 10 January 24.3.PTX ISA Version 2. and texture memory spaces are persistent across kernel launches by the same application.0 2. constant. The global. or. for more efficient transfer. Texture memory also offers different addressing modes. 2010 .

0) Block (1. 1) Block (0. 2010 11 .Chapter 2. 0) Block (2. 2) Block (1. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (1. 1) Grid 1 Global memory Block (0. 1) Block (2. 1) Block (1. Memory Hierarchy January 24. 0) Block (0. 2) Figure 2. 0) Block (1.

PTX ISA Version 2.0 12 January 24. 2010 .

manages.1. As thread blocks terminate. To manage hundreds of threads running several different programs. multiple-thread).) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. the threads converge back to the same execution path. 2010 13 . a multithreaded instruction unit. At every instruction issue time. It implements a single-instruction barrier synchronization. A multiprocessor consists of multiple Scalar Processor (SP) cores. The multiprocessor SIMT unit creates. the multiprocessor employs a new architecture we call SIMT (single-instruction. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image.Chapter 3. so full efficiency is realized when all threads of a warp agree on their execution path. Branch divergence occurs only within a warp. A warp executes one common instruction at a time. The threads of a thread block execute concurrently on one multiprocessor. a voxel in a volume. The way a block is split into warps is always the same. schedules. for example. new blocks are launched on the vacated multiprocessors. manages. and executes threads in groups of parallel threads called warps. and when all paths complete. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. the warp serially executes each branch path taken. allowing. The multiprocessor maps each thread to one scalar processor core. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. (This term originates from weaving. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. January 24. disabling threads that are not on that path. If threads of a warp diverge via a data-dependent conditional branch. increasing thread IDs with the first warp containing thread 0. and executes concurrent threads in hardware with zero scheduling overhead. each warp contains threads of consecutive. and on-chip shared memory. it splits them into warps that get scheduled by the SIMT unit. different warps execute independently regardless of whether they are executing common or disjointed code paths. When a host program invokes a kernel grid. Parallel Thread Execution Machine Model 3. the first parallel thread technology. The multiprocessor creates. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). a cell in a grid-based computation). and each scalar thread executes independently with its own instruction address and register state. When a multiprocessor is given one or more thread blocks to execute.

modifies. require the software to coalesce loads into vectors and manage divergence manually. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. 14 January 24. scalar threads.PTX ISA Version 2. the programmer can essentially ignore the SIMT behavior. In practice. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering.0 SIMT architecture is akin to SIMD (Single Instruction. but one of the writes is guaranteed to succeed. the kernel will fail to launch. SIMT enables programmers to write thread-level parallel code for independent. Vector architectures. which is a read-only region of device memory. write to that location occurs and they are all serialized. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. As illustrated by Figure 3. If an atomic instruction executed by a warp reads. each read. as well as data-parallel code for coordinated threads. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. and writes to the same location in global memory for more than one of the threads of the warp. however. on the other hand. A multiprocessor can execute as many as eight thread blocks concurrently. modify. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. In contrast with SIMD vector machines. For the purposes of correctness. which is a read-only region of device memory. but the order in which they occur is undefined. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. 2010 . Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. the number of serialized writes that occur to that location and the order in which they occur is undefined. whereas SIMT instructions specify the execution and branching behavior of a single thread. If there are not enough registers or shared memory available per multiprocessor to process at least one block. • The local and global memory spaces are read-write regions of device memory and are not cached. A key difference is that SIMD vector organizations expose the SIMD width to the software.

Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 . Hardware Model January 24. Figure 3.

PTX ISA Version 2. 2010 .0 16 January 24.

Chapter 4. Lines are separated by the newline character (‘\n’). whitespace is ignored except for its use in separating tokens in the language. Comments Comments in PTX follow C/C++ syntax. Comments in PTX are treated as whitespace.2. Syntax PTX programs are a collection of text source files. followed by a . Lines beginning with # are preprocessor directives. Each PTX file must begin with a . Source Format Source files are ASCII text. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #define.target directive specifying the target architecture assumed. #ifdef. All whitespace characters are equivalent. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. Pseudo-operations specify symbol and addressing management.version directive specifying the PTX language version. PTX is case sensitive and uses lowercase for keywords. 4. #if. See Section 9 for a more information on these directives. #endif. The C preprocessor cpp may be used to process PTX source files. and using // to begin a comment that extends to the end of the current line. 4.1. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #line. January 24. The following are common preprocessor directives: #include. #else. using non-nested /* and */ for comments that may span multiple lines. 2010 17 .

The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.minnctapersm .3. followed by source operands.3.2. . Table 1.x.version .3.section . r1. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. address expressions.reg .5. array[r1].1.pragma .global start: .f32 r2. Operands may be register variables. 0.shared . or label names.sreg .extern . Instruction keywords are listed in Table 2.param . %tid.b32 r1.visible 4.entry . Statements A PTX statement is either a directive or an instruction. All instruction keywords are reserved tokens in PTX. and is written as @p.PTX ISA Version 2.b32 add. Directive Statements Directive keywords begin with a dot. Statements begin with an optional label and end with a semicolon. r2. constant expressions. mov.b32 r1. r2.loc . Instructions have an optional guard predicate which controls conditional execution. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. .0 4. 2.maxnreg . so no conflict is possible with user-defined identifiers. The guard predicate may be optionally negated.global . The destination operand is first.maxnctapersm . where p is a predicate register.target .file PTX Directives .func . 2010 . written as @!p.reg .tex . and terminated with a semicolon. The guard predicate follows the optional label and precedes the opcode.maxntid . Examples: .local .b32 r1.global. r2.align . shl.const . 18 January 24. ld.f32 array[N].

Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2. 2010 19 .

Many high-level languages such as C and C++ follow similar rules for identifier names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. …. underscore.4.0 4. %pm3 WARP_SZ 20 January 24. PTX allows the percentage sign as the first character of an identifier. between user-defined variable names and compiler-generated names. dollar. listed in Table 3. or dollar characters.PTX ISA Version 2. e. digits. 2010 . or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Table 3. digits. or percentage character followed by one or more letters.g. or they start with an underscore. PTX predefines one constant and a small number of special registers that begin with the percentage sign. except that the percentage sign is not allowed. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. underscore. The percentage sign can be used to avoid name conflicts.

5.u64. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. floating-point. integer constants are allowed and are interpreted as in C.s64 or .2. every integer constant has type . Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. i.u64).1. The syntax follows that of C. Unlike C and C++. 4.s64 or the unsigned suffix is specified. there is no suffix letter to specify size..e. Syntax 4. zero values are FALSE and non-zero values are TRUE.. in which case the literal is unsigned (. When used in an instruction or data initialization. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. 4. or binary notation.Chapter 4. For predicate-type data and instructions. To specify IEEE 754 single-precision floating point values. i. Constants PTX supports integer and floating-point constants and constant expressions. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.e. Type checking rules remain the same for integer. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. 2010 21 . where the behavior of the operation depends on the operand types. octal. the constant begins with 0d or 0D followed by 16 hex digits.s64) unless the value cannot be fully represented in .5. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Integer literals may be written in decimal. each integer constant is converted to the appropriate size based on the data or instruction type at its use.5. 0[fF]{hexdigit}{8} // single-precision floating point January 24. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Floating-point literals may be written with an optional decimal point and an optional signed exponent. hexadecimal. These constants may be used in data initialization and as operands to instructions. To specify IEEE 754 doubleprecision floating point values. the constant begins with 0f or 0F followed by 8 hex digits. literals are always represented in 64-bit double-precision format. and bit-size types. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

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s64 .s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . Syntax 4.u64) (.u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 use usual conversions .f64 use usual conversions .u64 1st unchanged.u64.f64 use usual conversions . 2010 25 .u64 same as 1st operand .u64 .s64 .s64 .f64 same as source .s64) + .6.u64 .s64.u64 .f64 converted type .s64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. .Chapter 4. Table 5. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 : .s64 . 2nd is .u64 .u64 .f64 integer integer integer integer integer int ?. or .s64 .s64 .f64 converted type constant literal + ! ~ Cast Binary (.u64 .f64 integer .5.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 integer .

2010 .PTX ISA Version 2.0 26 January 24.

State Spaces A state space is a storage area with particular characteristics. Name State Spaces Description Registers. The characteristics of a state space include its size. . access rights. Addressable memory shared between threads in 1 CTA. and Variables While the specific resources available in a given target GPU will vary. and these resources are abstracted in PTX through state spaces and data types. pre-defined. platform-specific. 2010 27 . Global texture memory (deprecated). 5. and level of sharing between threads. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Kernel parameters.const .Chapter 5. Shared. Local memory.param . All variables reside in some state space. fast.tex January 24. Special registers.reg . Global memory. access speed.local . shared by all threads. defined per-thread.shared . State Spaces. defined per-grid. Table 6. the kinds of resources will be common across platforms.global . Read-only. private to each thread.1. and properties of state spaces are shown in Table 5. read-only memory. addressability.sreg . The list of state spaces is shown in Table 4. or Function or local parameters. Types.

scalar registers have a width of 8-.reg . When the limit is exceeded.local . platform-specific registers. and thread parameters. 1 Accessible only via the ld. or as elements of vector tuples. floating point.param (used in functions) . Registers may be typed (signed integer. such as grid. predicate) or untyped.1.1. i. it is not possible to refer to the address of a register. or 128-bits. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. and cvt instructions. 16-. and performance monitoring registers.1. Registers may have alignment boundaries required by multi-word loads and stores.param instructions. 32-.sreg . register variables will be spilled to memory.PTX ISA Version 2.shared .sreg) state space holds predefined.2. aside from predicate registers which are 1-bit. Register State Space Registers (.local state space. CTA.param and st. The most common use of 8-bit registers is with ld. causing changes in performance.global . unsigned integer. 5. 2010 . st. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Registers differ from the other state spaces in that they are not fully addressable. and will vary from platform to platform. the parameter is then located on the stack frame and its address is in the .0 Table 7. clock counters.. The number of registers is limited. 3 Accessible only via the tex instruction. or 64-bits. Special Register State Space The special register (. 2 Accessible via ld. Register size is restricted.tex Restricted Yes No3 5.param instruction. Device function input parameters may have their address taken via mov.reg state space) are fast storage locations. and vector registers have a width of 16-. Address may be taken via mov instruction. 64-. All special registers are predefined. 28 January 24. 32-.param (as input to kernel) .e. For each architecture. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).const .

For example. By convention. This pointer can then be used to access the entire 64KB constant bank.b32 const_buffer[]. st. The constant memory is organized into fixed size banks. b = b – 1. Global State Space The global (.extern . Constant State Space The constant (. each pointing to the start address of the specified constant bank. Types.const[2] . there are eleven 64KB banks. The size is limited. 2010 29 . Local State Space The local state space (. In implementations that support a stack. Threads wait at the barrier until all threads in the CTA have arrived. If another thread sees the variable b change.1.global. initialized by the host. an incomplete array in bank 2 is accessed as follows: . The remaining banks may be used to implement “incomplete” constant arrays (in C.b32 %r1. Consider the case where one thread executes the following two assignments: a = a + 1.Chapter 5. Threads must be able to do their work without waiting for other threads to do theirs. State Spaces. For any thread in a context. the bank number must be provided in the state space of the load instruction. results in const_buffer pointing to the start of constant bank two.global. all addresses are in global memory are shared. and atom. It is typically standard memory with cache.global to access global variables. To access data in contant banks 1 through 10.sync instruction.const[2]. Multiple incomplete array variables declared in the same bank become aliases. as it must be allocated on a perthread basis. Global memory is not sequentially consistent. This reiterates the kind of parallelism available in machines that run PTX.b32 const_buffer[].const) state space is a read-only memory. the declaration . and Variables 5. where the size is not known at compile time. Sequential consistency is provided by the bar.const[bank] modifier. It is the mechanism by which different CTAs and different grids can communicate.3.global) state space is memory that is accessible by all threads in a context. Banks are specified using the .local and st. // load second word 5.1. Module-scoped local memory variables are stored at fixed addresses. If no bank number is given. ld. [const_buffer+4]. bank zero is used for all statically-sized constant variables.local) is private memory for each thread to keep its own data. the stack is in local memory. where bank ranges from 0 to 10. 5. All memory writes prior to the bar. the store operation updating a may still be in flight. For the current devices. bank zero is used. as in lock-free and wait-free style programming. for example).5. For example.local to access local variables. whereas local memory variables declared January 24.sync instruction are guaranteed to be visible to any reads after the barrier instruction.4. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.extern .const[2] . Use ld. Use ld.1.

reg . Note that PTX ISA versions 1. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.b8 buffer[64] ) { . Example: .PTX ISA Version 2.reg . Values passed from the host to the kernel are accessed through these parameter variables using ld.f64 %d. (2a) to declare formal input and return parameters for device functions called from within kernel execution. all local memory variables are stored at fixed addresses and recursive function calls are not supported.1.param state space and is accessed using ld.param instructions.reg .u32 %ptr. %n. The kernel parameter variables are shared across all CTAs within a grid.u32 %n.u32 %n. 5.b32 len ) { . read-only variables declared in the .b32 N. Similarly.6.x supports only kernel function parameters in . 5. PTX code should make no assumptions about the relative locations or ordering of .0 within a function or kernel body are allocated on the stack.param state space.f64 %d. 2010 . in some implementations kernel parameters reside in global memory.1. In implementations that do not support a stack.6. Therefore. The resulting address is in the .entry bar ( . . [%ptr].param space. For example. . per-kernel versus per-thread).param . ld. These parameters are addressable.align 8 . len. ld.param .param. No access protection is provided between parameter and global space in this case. The address of a kernel parameter may be moved into a register using the mov instruction.u32 %n.u32 %ptr. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. [buffer].param. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. device function parameters were previously restricted to the register state space.param .entry foo ( .0 and requires target architecture sm_20.param space variables. ld. mov. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).1.param instructions. typically for passing large structures by value to a function.param. [N]. … Example: .param) state space is used (1) to pass input arguments from the host to the kernel. The use of parameter state space for device function parameters is new to PTX ISA version 2. Note: The location of parameter space is implementation specific. … 30 January 24. Parameter State Space The parameter (.

Aside from passing structures by value.s32 [mystruct+8]. . … } // code snippet from the caller // struct { double d.f64 %d.param. In this case. Example: // pass object of type struct { double d. int y.param space is also required whenever a formal parameter has its address taken within the called function.param formal parameter having the same size and alignment as the passed argument. .reg . and Variables 5. Types.local and st. . … See the section on function call syntax for more details. dbl.param byte array variable that represents a flattened C structure or union.s32 x.2.0 extends the use of parameter space to device function parameters. a byte array in parameter space is used.reg . call foo.f64 [mystruct+0]. such as C structures larger than 8 bytes. mystruct). State Spaces.param . Note that the parameter will be copied to the stack if necessary. . .f64 dbl. ld.reg . This will be passed by value to a callee. January 24. Function input parameters may be read via ld. st.6. it is illegal to write to an input parameter or read from a return parameter. ld.param.align 8 .s32 %y.b8 mystruct. … st.1. It is not possible to use mov to get the address of a return parameter or a locally-scoped . passed to foo … .param. .param .s32 %y. [buffer]. the caller will declare a locally-scoped . and so the address will be in the . x. The most common use is for passing objects by value that do not fit within a PTX register. int y. is flattened. Device Function Parameters PTX ISA version 2.func foo ( . (4. }.reg .param and function return parameters may be written using st. } mystruct.param.local instructions. [buffer+8]. which declares a .Chapter 5. Typically. the address of a function input parameter may be moved into a register using the mov instruction.param.local state space and is accessed via ld.reg .b8 buffer[12] ) { .f64 %d.param space variable. In PTX.b32 N.align 8 . 2010 31 .

u32 .tex .shared and st.tex . The texture name must be of type .tex . For example.u32 . and programs should instead reference texture memory through variables of type .7.u64. tex_f.texref type and Section 8. is equivalent to . See Section 5.tex) state space is global memory accessed via the texture instruction.texref. The . where all threads read from the same address.8. and variables declared in the . One example is broadcast. Use ld.7.tex . tex_c. Multiple names may be bound to the same physical texture identifier. Texture memory is read-only. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). Physical texture resources are allocated on a per-module granularity.u32 tex_a.tex . The . Example: .tex directive is retained for backward compatibility.1.u32 tex_a. A texture’s base address is assumed to be aligned to a 16-byte boundary. 32 January 24.texref variables in the .3 for the description of the .6 for its use in texture instructions.shared) state space is a per-CTA region of memory for threads in a CTA to share data.PTX ISA Version 2. Shared State Space The shared (. An error is generated if the maximum number of physical resources is exceeded. and . An address in shared memory can be read and written by any thread in a CTA.global .0 5. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. 2010 .u32 or . tex_d.tex state space are equivalent to module-scoped . It is shared by all threads in a context.global state space. tex_d.1.u32 . 5. Shared memory typically has some optimizations to support the sharing.tex variables are required to be defined in the global scope.tex directive will bind the named texture memory variable to a hardware texture identifier. Another is sequential access from sequential threads. where texture identifiers are allocated sequentially beginning with zero.shared to access shared variables. Texture State Space (deprecated) The texture (. a legacy PTX definitions such as .texref tex_a.

s16. 2010 33 . State Spaces.s64 . all variables (aside from predicates) could be declared using only bit-size types. The same typesize specifiers are used for both variable definitions and for typing instructions.2. and Variables 5. Two fundamental types are compatible if they have the same basic type and are the same size. All floating-point instructions operate only on .u8. .f32 and .pred Most instructions have one or more type specifiers.u64 .s32. and converted using regular-width registers. and instructions operate on these types.s8. .f64 . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. st. Operand types and sizes are checked against instruction types for compatibility. . .1. Restricted Use of Sub-Word Sizes The . needed to fully specify instruction behavior.f32 and .2.2.Chapter 5.b16. .f16 floating-point type is allowed only in conversions to and from .u16. The following table lists the fundamental type specifiers for each basic type: Table 8. ld. A fundamental type specifies both a basic type and a size. and .u8. so their names are intentionally short. Register variables are always of a fundamental type. Signed and unsigned integer types are compatible if they have the same size.b8 instruction types are restricted to ld. .f64 types. . . but typed variables enhance program readability and allow for better operand type checking. Fundamental Types In PTX. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .u32. and cvt instructions. so that narrow values may be loaded. The . For convenience. or converted to other types and sizes.f16. st. 5. . the fundamental types reflect the native data types supported by the target architectures. stored.b64 . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. . Types. . In principle.s8. The bitsize type is compatible with any fundamental type having the same size.f64 types. For example. .2. January 24.b8. stored.b32.f32. Types 5.

store. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. and .e. Sampler.surfref. allowing them to be defined separately and combined at the site of usage in the program. opaque_var.PTX ISA Version 2. The following tables list the named members of each type for unified and independent texture modes.{u32. texture and sampler information is accessed through a single . samplers. i. Creating pointers to opaque variables using mov.u64} reg. For working with textures and samplers. field ordering.texref handle.3. These types have named fields similar to structures. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. The three built-in types are ..samplerref.texref. .texref type that describe sampler properties are ignored. texture and sampler information each have their own handle. and Surface Types PTX includes built-in “opaque” types for defining texture. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. passed as a parameter to functions. Retrieving the value of a named member via query instructions (txq. 34 January 24. and query instructions. accessing the pointer with ld and st instructions. 2010 . and de-referenced by texture and surface load. hence the term “opaque”. In the unified mode. suq). PTX has two modes of operation. or performing pointer arithmetic will result in undefined results.samplerref variables. or surfaces via texture and surface load/store instructions (tex. but the pointer cannot otherwise be treated as an address. Texture. the resulting pointer may be stored to and loaded from memory. In independent mode the fields of the .0 5. suld. base address. Referencing textures. since these properties are defined by . sampler. sust. sured). but all information about layout. and overall size is hidden to a PTX program. In the independent mode. and surface descriptor variables.

Types. linear wrap.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_border 0. mirror. clamp_ogl. Member width height depth Opaque Type Fields in Unified Texture Mode .texref values . clamp_ogl. clamp_to_edge. linear wrap. clamp_to_border N/A N/A N/A N/A N/A . and Variables Table 9. clamp_to_edge.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.texref values in elements in elements in elements 0. mirror.samplerref values N/A N/A N/A N/A nearest. 1 nearest.Chapter 5. 1 ignored ignored ignored ignored . Member width height depth Opaque Type Fields in Independent Texture Mode . State Spaces. 2010 35 .

Example: .global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. 36 January 24.samplerref my_sampler_name. As kernel parameters. .global state space. the types may be initialized using a list of static expressions assigning values to the named members. these variables must be in the . 2010 . When declared at module scope. At module scope.global .global .surfref my_surface_name. Example: .texref my_texture_name. these variables are declared in the . .global .global .param state space.PTX ISA Version 2. . filter_mode = nearest }.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.texref tex1.

global . Variable Declarations All storage for data is specified with variable declarations.0.v3 }. 2010 37 .u16 uv.v4 . 1. Predicate variables may only be declared in the register state space.Chapter 5. vector variables are aligned to a multiple of their overall size (vector length times base-type size). an optional array size. 5.4. In addition to fundamental types.v1.f32 V.u8 bg[4] = {0. .v4.f32 v0.v2 or .4. and Variables 5. Every variable must reside in one of the state spaces enumerated in the previous section. A variable declaration names the space in which the variable resides. January 24. // a length-4 vector of bytes By default. . Vectors must be based on a fundamental type.reg . . a variable declaration describes both the variable’s type and its state space. . for example. .reg . Three-element vectors may be handled by using a . Variables In PTX. This is a common case for three-dimensional grids.global . // a length-4 vector of floats .struct float4 { . textures. 5.v4 vector. Examples: . PTX supports types for simple aggregate objects such as vectors and arrays.u32 loc.pred p.global .v4 .shared . r.v2. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . its name.global .f32 bias[] = {-1.reg . q. an optional initializer. and they may reside in the register space.const .v4.v2 . . State Spaces. Types.v4 . // typedef . 0}. Vectors Limited-length vector types are supported.1. 0. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.global .s32 i. etc.f32 accel.f64 is not allowed. . and an optional fixed address for the variable.struct float4 coord.4. Examples: .b8 v. Vectors cannot exceed 128-bits in length. // a length-2 vector of unsigned ints .0}. 0. its type and size. where the fourth element provides padding.2.

05. Examples: .. . or is left empty. The size of the array specifies how many elements should be reserved. . To declare an array. variable initialization is supported only for constant and global state spaces. 38 January 24.local .1..05.u16 kernel[19][19]. Variables that hold addresses of variables or instructions should be of type .u8 mailbox[128].global . 0}. . For the kernel declaration above. Array Declarations Array declarations are provided to allow the programmer to reserve space.pred.3.0. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. -1}. 2010 . 5.1}.0.05}. {1. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). 19*19 (361) halfwords are reserved (722 bytes). where the variable name is followed by an equals sign and the initial value or values for the variable.4. 0}. {0. The size of the dimension is either a constant expression.shared .{.s32 n = 10. .0.0. Variable names appearing in initializers represent the address of the variable. {0. 1} }. this can be used to statically initialize a pointer to a variable.0}}.{..PTX ISA Version 2.global .s32 offset[][] = { {-1. Here are some examples: . // address of rgba into ptr Currently. Similarly. Initializers are allowed for all types except . this can be used to initialize a jump table to be used with indirect branches or calls.4.4.0}.1. {0.f16 and .f32 blur_kernel[][] = {{.. label names appearing in initializers represent the address of the next instruction following the label..u64.b32 ptr = rgba. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.05}}.global . .u32 or . being determined by an array initializer.0}.1. {0.global .1. A scalar takes a single value..v4 .u8 rgba[3] = {{1.4.1.global .0 5.

4.. nor are initializers permitted..0. The default alignment for scalar and array variables is to a multiple of the base-type size. Rather than require explicit declaration of every name.6.align 4 . %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. State Spaces. Alignment is specified using an optional . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.b8 bar[8] = {0. %r1. and Variables 5.2.align byte-count specifier immediately following the state-space specifier. say one hundred.. For arrays. %r99.reg . …. named %r0. 2010 39 . alignment specifies the address alignment for the starting address of the entire array. . Elements are bytes.0. Parameterized Variable Names Since PTX supports virtual registers.const . // declare %r0. Array variables cannot be declared this way. Examples: // allocate array at 4-byte aligned address. 5.b32 %r<100>.b32 variables. and may be preceded by an alignment specifier. Types.0. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.0.0}. The variable will be aligned to an address which is an integer multiple of byte-count.4. For example. %r1.0. These 100 register variables can be declared as follows: . The default alignment for vector variables is to a multiple of the overall vector size. January 24.5. it is quite common for a compiler frontend to generate a large number of register names. . not for individual elements.Chapter 5. of . Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. suppose a program uses a large number.

2010 .PTX ISA Version 2.0 40 January 24.

The result operand is a scalar or vector variable in the register state space. and cvt instructions copy data from one location to another. mov. s. Most instructions have an optional predicate guard that controls conditional execution. Instructions ld and st move data from/to addressable state spaces to/from registers. The cvt (convert) instruction takes a variety of operand types and sizes. January 24. The mov instruction copies data between registers. st. The bit-size type is compatible with every type having the same size.2. Source Operands The source operands are denoted in the instruction descriptions by the names a.1. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Each operand type must be compatible with the type determined by the instruction template and instruction type.Chapter 6. and c. the sizes of the operands must be consistent. The ld. 2010 41 . r. q. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. PTX describes a load-store machine. For most operations. Integer types of a common size are compatible with each other. There is no automatic conversion between types. Predicate operands are denoted by the names p. . 6. as its job is to convert from nearly any data type to any other data type (and size). and a few instructions have additional predicate source operands. so operands for ALU instructions must all be in variables declared in the . 6. Operand Type Information All operands in instructions have a known type from their declarations. Instruction Operands 6. b.3.reg register state space.

global . . . 6.reg .reg .u32 42 January 24.shared. The mov instruction can be used to move the address of a variable into a pointer. The syntax is similar to that used in many assembly languages.0 6.f32 ld. W. The address is an offset in the state space in which the variable is declared.gloal.b32 p.v4 .reg .[x].s32 mov. and Vectors Using scalar variables as operands is straightforward.u16 r0. Address expressions include variable names. address register plus byte offset. r0. Arrays. [tbl+12].reg . Load and store operations move data between registers and locations in addressable state spaces.PTX ISA Version 2.1. there is no support for C-style pointer arithmetic.s32 tbl[256].const . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. ld. Examples include pointer arithmetic and pointer comparisons. All addresses and address computations are byte-based. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.const. . q. Here are a few examples: .f32 V. . address registers. [V]. 2010 . arrays.u16 x.v4. . . and immediate address expressions which evaluate at compile-time to a constant address.v4 . p.f32 W. The interesting capabilities begin with addresses.4.shared . tbl.4.u16 ld. and vectors. Using Addresses.s32 q.

z V. and the identifier becomes an address constant in the space where the array is declared. Vector loads and stores can be used to implement wide loads and stores.g V. [addr+offset].u32 s. V2. January 24.f32 ld.x V. st.d}.c. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. 2010 43 .z and . it must be written as an address calculation prior to use. Arrays as Operands Arrays of all types can be declared.f32 {a.d}. A brace-enclosed list is used for pattern matching to pull apart vectors.b V. Vectors as Operands Vector operands are supported by a limited subset of instructions.r. .w. mov.f32 a.b. Examples are ld. and tex. which include mov. If more complicated indexing is desired. Rd}.4.3. V. mov. where the offset is a constant expression that is either added or subtracted from a register variable.Chapter 6. say {Ra. Here are examples: ld.global. Vectors may also be passed as arguments to called functions.2. ld. as well as the typical color fields . and in move instructions to get the address of the label or function into a register.u32 s. or a simple “register with constant offset” expression. d.4. . a[1].x. Rc. . Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. or by indexing into the array using square-bracket notation.y. b. [addr+offset2].r V.v4. Array elements can be accessed using an explicitly calculated byte address. The registers in the load/store operations can be a vector. a register variable.global.y V.f32 V.u32 {a.v4 . // move address of a[1] into s 6. Instruction Operands 6. Elements in a brace-enclosed vector.v4.global.v2.global. which may improve memory performance. The size of the array is a constant in the program. a[N-1].g. c. .c.b. Vector elements can be extracted from the vector with the suffixes . The expression within square brackets is either a constant integer.4. a[0]. .reg . for use in an indirect branch or call.reg .u32 s. .a.a 6.4.b and . Rb.w = = = = V. or a braceenclosed list of similarly typed scalars. ld.

Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. logic. and ~131. 6.PTX ISA Version 2.5.5. except for operations where changing the size and/or type is part of the definition of the instruction.u16 instruction is given a u16 source operand and s32 as a destination operand.000 for f16).0 6. the u16 is zero-extended to s32.s32. 2010 . Type Conversion All operands to all arithmetic. For example. and data movement instruction must be of the same type and size. 44 January 24. Operands of different sizes or types must be converted prior to the operation. if a cvt.1.

January 24. s2f = signed-to-float.u32 targeting a 32-bit register will first chop to 16-bits. u2f = unsigned-to-float. 2010 45 . f2s = float-to-signed. The type of extension (sign or zero) is based on the destination format. f2f = float-to-float.Chapter 6. then sign-extend to 32-bits. Notes 1 If the destination register is wider than the destination format. chop = keep only low bits that fit. the result is extended to the destination register width after chopping.s16. zext = zero-extend. f2u = float-to-unsigned. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. For example. Instruction Operands Table 11. cvt.

PTX ISA Version 2. Rounding Modifiers Conversion instructions may specify a rounding modifier. In PTX. Modifier . The following tables summarize the rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.0 6.rmi .rzi . Table 12. Modifier .rm . there are four integer rounding modifiers and four floating-point rounding modifiers.rni .rpi Integer Rounding Modifiers Description round to nearest integer.5. choosing even integer if source is equidistant between two integers. 2010 .2.rn .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rz .

Registers are fastest. Another way to hide latency is to issue the load instructions as early as possible. Instruction Operands 6. first access is high Notes January 24. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. 2010 47 .6. Operand Costs Operands from different state spaces affect the speed of an operation. Table 11 gives estimates of the costs of using different kinds of memory. while global memory is slowest. The register in a store operation is available much more quickly. Much of the delay to memory can be hidden in a number of ways. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.Chapter 6. Table 14. as execution is not blocked until the desired result is used in a subsequent (in time) instruction.

PTX ISA Version 2. 2010 .0 48 January 24.

Abstracting the ABI Rather than expose details of a particular calling convention. and Application Binary Interface (ABI). stack layout. so recursion is not yet supported. A function definition specifies both the interface and the body of the function. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. the function name. } … call foo. Execution of the ret instruction within foo transfers control to the instruction following the call. January 24. and memory allocated on the stack (“alloca”). 7. The simplest function has no parameters or return values. execution of the call instruction transfers control to foo. support for variadic functions (“varargs”). implicitly saving the return address. and is represented in PTX as follows: . or prototype. Scalar and vector base-type input and return parameters may be represented simply as register variables. we describe the features of PTX needed to achieve this hiding of the ABI. A function must be declared or defined prior to being called. At the call. arguments may be register variables or constants. functions are declared and defined using the .func directive. A function declaration specifies an optional list of return parameters. and return values may be placed directly into register variables. NOTE: The current version of PTX does not implement the underlying. together these specify the function’s interface. stack-based ABI. function calls.func foo { … ret. In this section. parameter passing. Function declarations and definitions In PTX. and an optional list of input parameters. … Here. 2010 49 .1. These include syntax for function definitions. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations.Chapter 7.

}.param .b8 c1. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param. (%r1. 50 January 24. For example. c3. . // scalar args in .b8 [py+ 8]. %rd.4). ret.s32 out) bar (. note that . %inc.param space call (%out). ld.param space variables are used in two ways.param. py). st.c3. [y+11]. ld. passed by value to a function: struct { double dbl. 2010 .reg . } { .param. bumpptr.reg space.b8 [py+10].param.param. Second.func (.param state space is used to pass the structure by value: . … st.u32 %res) inc_ptr ( .reg .align 8 y[12]) { .b32 c1.PTX ISA Version 2. . consider the following C structure.reg .param.c1. In PTX. ld.f1.c2.b64 [py+ 0]. %rc2. char c[4].b8 .u32 %ptr.func (.b8 [py+ 9].c4. (%x.s32 x.reg . ld. this structure will be flattened into a byte array. } … call (%r1). a . [y+0]. … ld.u32 %res.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. [y+9].reg .f64 field are aligned. %rc2. %rc1.reg .b8 c3.u32 %inc ) { add.align 8 py[12]. st. The . c4. … In this example. st. a .b8 c4.param.f64 f1.b8 [py+11].f64 f1. c2. Since memory accesses are required to be aligned to a multiple of the access size. [y+10]. [y+8].b8 .param space memory. %rc1.param.param . byte array in .param variable y is used in function definition bar to represent a formal parameter. %ptr. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . . First.param.b8 c2.reg . st. inc_ptr. … … // computation using x.0 Example: .param.

A .reg variables. In the case of .param variables or . For a caller. Supporting the . In the case of . In the case of .param space byte array with matching type. and alignment. • • • Input and return parameters may be .reg space variable with matching type and size.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param or . .param space formal parameters that are byte arrays. or a constant that can be represented in the type of the formal parameter. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. all st.reg state space in this way provides legacy support.param argument must be declared within the local scope of the caller. 4..param state space is used to receive parameter values and/or pass return values back to the caller. 8. the corresponding argument may be either a .param and ld. Abstracting the ABI The following is a conceptual way to think about the . or constants.param arguments. Note that the choice of . For a caller.reg or . or a constant that can be represented in the type of the formal parameter.reg space variable of matching type and size.param memory must be aligned to a multiple of 1. 2. Typically. The . • • • For a callee. Parameters in . and alignment of parameters.param byte array is used to collect together fields of a structure being passed by value.reg variables. • The .reg state space can be used to receive and return base-type scalar and vector values.param or .param instructions used for argument passing must be contained in the basic block with the call instruction. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. For .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. 2010 51 . January 24.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. The .g. For a callee.reg space formal parameters. • • Arguments may be . This enables backend optimization and ensures that the . The following restrictions apply to parameter passing.param variables. or 16 bytes.Chapter 7. size. • The . a . the corresponding argument may be either a . size. the argument must also be a .param space formal parameters that are base-type scalar or vector variables.param state space use in device functions.

PTX 2.1.reg or .param byte array should be used to return objects that do not fit into a register. 2010 .x.0. and . formal parameters may be in either .param state space.reg state space. 52 January 24.0 continues to support multiple return registers for sm_1x targets. Objects such as C structures were flattened and passed or returned using multiple registers. In PTX ISA version 2.x In PTX ISA version 1.param space parameters support arrays. Changes from PTX 1.0 restricts functions to a single return value. PTX 1.PTX ISA Version 2. and there was no support for array parameters.0 7. For sm_2x targets.x supports multiple return values for this purpose. formal parameters were restricted to . and a .1. PTX 2.

reg . ret. To support functions with a variable number of arguments.u32 ap.reg . 0x8000000.func %va_end (. In both cases. %va_end is called to free the variable argument list handle. 4. This handle is then passed to the %va_arg and %va_arg64 built-in functions. the size may be 1. 8. val. For %va_arg.func (.s32 result. variadic functions are declared with an ellipsis at the end of the input parameter list.u32 align) . (ap. and end access to a list of variable arguments. N.reg .b32 result. .func baz ( . 2010 53 . (2. maxN. … ) . 4. %r2.b32 val) %va_arg (. or 8 bytes. (ap). // default to MININT mov. the alignment may be 1. . .reg .2.reg .u32 ptr) %va_start . … %va_start returns Loop: @p Done: January 24. %s1. for %va_arg64. iteratively access.. call (ap). maxN.u32 sz. %va_arg. ctr.reg .u32 N. 2.u32.reg .func okay ( … ) Built-in functions are provided to initialize. result.reg . Abstracting the ABI 7.reg . following zero or more fixed parameters: .func ( . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . bra Done.reg . 4). PTX provides a high-level mechanism similar to the one provided by the stdarg. (3. . 4.reg . Once all arguments have been processed. In PTX. mov.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. %va_start.h headers in C.u32 ptr. along with the size and alignment of the next data value to be accessed.Chapter 7. .reg .u32 b. setp.pred p. 0.u32 a. 2.u32 sz.h and varargs. bra Loop. %s2).u32 ptr. or 4 bytes. or 16 bytes. … call (%max). %r1.s32 result ) maxN ( .s32 val.func (. %r3).. .func (.reg . Variadic functions NOTE: The current version of PTX does not support variadic functions. ) { . max.reg .reg . ctr. . call %va_end.b64 val) %va_arg64 (.ge p. call (val). 2. The function prototypes are defined as follows: .b32 ctr.u32 align) . } … call (%max). the size may be 1.reg .reg . .

54 January 24.local and st.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. If a particular alignment is required.reg .reg . a function simply calls the built-in function %alloca.u32 ptr ) %alloca ( .3. defined as follows: .0 7. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. The array is then accessed with ld. To allocate memory.func ( .local instructions. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. 2010 . Alloca NOTE: The current version of PTX does not support alloca.PTX ISA Version 2.

lt p|q. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.s32. followed by some examples that attempt to show several possible instantiations of the instruction. For some instructions the destination operand is optional. the D operand is the destination operand. For instructions that create a result value. 8. In addition to the name and the format of the instruction.Chapter 8. setp. b. The setp instruction writes two destination registers. a. // p = (a < b). Instruction Set 8. B. q = !(a < b). We use a ‘|’ symbol to separate multiple destination registers. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. PTX Instructions PTX instructions generally have from zero to four operands. A. opcode D. C. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. while A. 2010 55 . and C are the source operands. January 24.1. the semantics are described. B. opcode A. A. B. opcode D.2. opcode D.

lt. n. consider the high-level code if (i < n) j = j + 1. Predicated Execution In PTX.s32 p.s32 p. To implement the above example as a true conditional branch. As an example.pred p. add.s32 j. where p is a predicate variable. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. branch over 56 January 24. Instructions without a guard predicate are executed unconditionally. Predicates are most commonly set as the result of a comparison performed by the setp instruction. 1.reg . … // compare i to n // if false. add 1 to j To get a conditional branch or conditional function call. 2010 .0 8. predicate registers are virtual and have . n. 1.lt. q.3. i. j.PTX ISA Version 2. add.s32 j.pred as the type specifier. i. So. the following PTX instruction sequence might be used: @!p L1: setp. This can be written in PTX as @p setp. predicate registers can be declared as . j. use a predicate to control the execution of the branch or call instructions. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. optionally negated. // p = (i < n) // if i < n. bra L1.

Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Instruction Set 8. and ge (greater-than-or-equal). gt (greater-than). Unsigned Integer.Chapter 8. lo (lower). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. lt (less-than). le (less-than-or-equal).3. and bitsize types. hi (higher).1. le. gt. The unsigned comparisons are eq. 2010 57 . ne. ne.1. The bit-size comparisons are eq and ne. The following table shows the operators for signed integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).2. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. ge. the result is false.1. ne (not-equal). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. ls (lower-or-same). unsigned integer. Comparisons 8. Table 16.3.3. If either operand is NaN. ordering comparisons are not defined for bit-size types. Table 15.1. lt. and hs (higher-or-same).

and nan returns true if either operand is NaN. // convert predicate to 32-bit value 58 January 24.0. and no direct way to load or store predicate register values.u32 %r1.0 To aid comparison operations in the presence of NaN values. If both operands are numeric values (not NaN).1.PTX ISA Version 2. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.%p. xor. neu. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.2. then these comparisons have the same result as their ordered counterparts. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. and mov. Table 17.3. for example: selp. geu. There is no direct conversion between predicates and integer values. However. num returns true if both operands are numeric values (not NaN). unordered versions are included: equ. ltu. Table 18. gtu. 2010 . If either operand is NaN. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. not. two operators num (numeric) and nan (isNaN) are provided. then the result of these comparisons is true. setp can be used to generate a predicate from an integer. leu. or.

e.reg . a.fX ok inv inv ok Instruction Type . add. cvt. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. For example. For example: .u16 d. b. different sizes).sX ok ok ok inv . • The following table summarizes these type checking rules. they must match exactly. a.u16 a.Chapter 8. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. most notably the data conversion instruction cvt.f32. b.reg . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. It requires separate type-size modifiers for the result and source. and this information must be specified as a suffix to the opcode. and integer operands are silently cast to the instruction type if needed. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. float. 2010 59 . Example: .4.bX . the add instruction requires type and size information to properly perform the addition operation (signed.bX . . i. Instruction Set 8.fX ok ok ok ok January 24. Type Checking Rules Operand Type .u16 d. Table 19. a.uX .reg . unsigned.sX ..u16 d. Signed and unsigned integer types agree provided they have the same size. Floating-point types agree only if they have the same size.uX ok ok ok inv .f32 d. For example. and these are placed in the same order as the operands. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.

8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. stored. 60 January 24. When used with a floating-point instruction type.4.0 8. The data is truncated to the instruction-type size and interpreted according to the instruction type. floating-point instruction types still require that the operand type-size matches exactly.1. Table 20. the cvt instruction does not support . The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. 2010 . Source register size must be of equal or greater size than the instruction-type size. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. “-“ = allowed.bX instruction types. the data will be truncated. the size must match exactly. When used with a narrower bit-size type. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. For example. so those rows are invalid for cvt. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. The following table summarizes the relaxed type-checking rules for source operands. Floating-point source registers can only be used with bit-size or floating-point instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. and converted using regular-width registers. for example. inv = invalid. 4.PTX ISA Version 2. Notes 3. ld. so that narrow values may be loaded. st. 1. stored. or converted to other types and sizes. parse error. Bit-size source registers may be used with any appropriately-sized instruction type. 2. no conversion needed. Note that some combinations may still be invalid for a particular instruction. Operand Size Exceeding Instruction-Type Size For convenience. When a source operand has a size that exceeds the instruction-type size. unless the operand is of bit-size type.

otherwise. the size must match exactly. Destination register size must be of equal or greater size than the instruction-type size. Bit-size destination registers may be used with any appropriately-sized instruction type. Notes 3. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the data is zeroextended. If the corresponding instruction type is signed integer. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. parse error. the data will be zero-extended. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. 2. The data is sign-extended to the destination register width for signed integer instruction types. the data is sign-extended. 1. When used with a narrower bit-size instruction type. zext = zero-extend. January 24. Instruction Set When a destination operand has a size that exceeds the instruction-type size. inv = Invalid.Chapter 8. When used with a floatingpoint instruction type. “-“ = Allowed but no conversion needed. 2010 61 . The data is signextended to the destination register width for signed integer instruction types. The following table summarizes the relaxed type-checking rules for destination operands.or sign-extended to the size of the destination register. the destination data is zero. 4. and is zero-extended to the destination register width otherwise. Table 21.

5. the optimizing code generator automatically determines points of re-convergence.uni suffix. The semantics are described using C. this is not desirable. and for many applications the difference in execution is preferable to limiting performance. by a right-shift instruction. a compiler or code author targeting PTX can ignore the issue of divergent threads. for example. If all of the threads act in unison and follow a single control flow path. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. conditional function call. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. until C is not expressive enough. If threads execute down different control flow paths. the threads are called divergent. the threads are called uniform. and 16-bit computations are “promoted” to 32-bit computations. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. These extra precision bits can become visible at the application level. using the . since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 62 January 24.1.0 8. A compiler or programmer may chose to enforce portable. 16-bit registers in PTX are mapped to 32-bit physical registers.6. At the PTX language level. so it is important to have divergent threads re-converge as soon as possible. For divergent control flow. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. 8. 2010 . for many performance-critical applications. Therefore.PTX ISA Version 2. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. When executing on a 32-bit data path. or conditional return. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine.6. until they come to a conditional control construct such as a conditional branch. 8. Both situations occur often in programs. However. the semantics of 16-bit instructions in PTX is machine-specific. at least in appearance. Divergence of Threads in Control Constructs Threads in a CTA execute together. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs.

Instruction Set 8. In the following descriptions. the optional guard predicate is omitted from the syntax.cc.7. 2010 63 .1.Chapter 8. 8. Instructions All PTX instructions may be predicated.cc.7. The Integer arithmetic instructions are: add sub add. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. addc sub. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.

2010 .u32. Introduced in PTX ISA version 1.0. sub. Description Semantics Notes Performs addition and writes the resulting value into a destination register. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. add Syntax Integer Arithmetic Instructions: add Add two values.MAXINT (no overflow) for the size of the operation. Saturation modifier: .s64 }. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.MAXINT (no overflow) for the size of the operation.s32 d. .c.z.s32 c. .s32 d.u64.s32 c.u16.sat}.0.1.sat. @p add. . Applies only to . . b.u32 x. Supported on all target architectures.s32 .PTX ISA Version 2. Introduced in PTX ISA version 1. // .type add{. d = a + b.s32 type. .s16.y..type = { . b. d. sub.type sub{. // .s16. Supported on all target architectures.s32 . . a.sat limits result to MININT.u16. add. d.s64 }.type = { . d = a – b.s32 type. . b. Saturation modifier: .. add. Applies only to .u64. a. PTX ISA Notes Target ISA Notes Examples 64 January 24.sat}. PTX ISA Notes Target ISA Notes Examples Table 23.a. . a.s32.sat applies only to . .sat limits result to MININT. a.s32. b.u32.sat applies only to .0 Table 22.b. .

x4. d = a + b + CC.cc specified.y1. a.y4. . Instruction Set Instructions add. x3. add.cc.cc.Chapter 8. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. Supported on all target architectures. b. x2.type = { .z3. if . x3. addc{. Behavior is the same for unsigned and signed integers.z3.b32 x1. .cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.z2.b32 addc.s32 }. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.CF) holding carry-in/carry-out or borrowin/borrow-out.y1.cc.s32 }. 2010 65 .cc.y3.b32 addc.type d.b32 addc.type = {. @p @p @p @p add. .cc. Table 24. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. x2.cc. These instructions support extended-precision integer addition and subtraction. Introduced in PTX ISA version 1.2.z4. Introduced in PTX ISA version 1.y2.u32. Supported on all target architectures. No other instructions access the condition code. carry-out written to CC. sub. Behavior is the same for unsigned and signed integers.z2.type d.cc Add two values with carry-out.cc. @p @p @p @p add.b32 x1. addc.cc}.cc. clearing.CF No integer rounding modifiers.y3. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.CF.z1.2. b.z4.cc.b32 addc. add. a.CF No integer rounding modifiers. No saturation.cc Syntax Integer Arithmetic Instructions: add.y2.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.u32. carry-out written to CC. d = a + b. x4.z1.b32 addc. or testing the condition code. No saturation. and there is no support for setting.y4. .b32 addc.

cc.cc Subract one value from another. x3.cc}. b.y2. No saturation.b32 subc. x4.s32 }.b32 subc.cc.b32 subc.u32. a.cc specified.b32 subc.b32 x1. if .z3. sub. d = a .y1.cc.b32 x1. No saturation. .cc. . subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. withborrow-in and optional borrow-out. Supported on all target architectures.cc. 2010 . Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.b32 subc.y3. sub. with borrow-out. x4. . x2.z2.cc. Introduced in PTX ISA version 1.type = {.cc.CF No integer rounding modifiers.CF). x3. borrow-out written to CC.y4. @p @p @p @p sub.z4.cc.y4.u32.b32 subc.y2. Introduced in PTX ISA version 1.s32 }.CF No integer rounding modifiers.z1.type d.z1.z2. Behavior is the same for unsigned and signed integers. subc{.cc.(b + CC.y3.type d.PTX ISA Version 2. Supported on all target architectures. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.0 Table 26.z4.type = { . x2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. borrow-out written to CC.z3.3. a. d = a – b.3. b. Behavior is the same for unsigned and signed integers. @p @p @p @p sub.y1. .cc Syntax Integer Arithmetic Instructions: sub. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.

u64.fys. mul.lo is specified. save only the low 16 bits // 32*32 bits.0>. .s64 }.. d = t<n-1.type d.u16. .type = { . t = a * b.x..s16. b.wide is specified. If .s32. // 16*16 bits yields 32 bits // 16*16 bits. Supported on all target architectures.lo variant Notes The type of the operation represents the types of the a and b operands. .0.wide.hi variant // for .n>. // for . Description Semantics Compute the product of two values. . then d is twice as wide as a and b to receive the full result of the multiplication.fys. 2010 67 .hi.fxs. a.wide // for . Instruction Set Table 28. then d is the same size as a and b. .wide.Chapter 8.. creates 64 bit result January 24.wide}. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. d = t.y.u32.hi or . mul.s16 fa.s16 fa.lo. d = t<2n-1.fxs.s32 z. If . n = bitwidth of type. and either the upper or lower half of the result is written to the destination register. The .wide suffix is supported only for 16. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo.and 32-bit integer types. mul. .. mul{.

lo.lo. and then writes the resulting value into a destination register.a.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.sat limits result to MININT.and 32-bit integer types.0> + c.0 Table 29.u16. 68 January 24. 2010 .s16.hi or . If .lo variant Notes The type of the operation represents the types of the a and b operands.type mad. c. .s32. The .PTX ISA Version 2. Description Semantics Multiplies two values and adds a third. . and either the upper or lower half of the result is written to the destination register.hi.u64. a. mad{.s32 d.u32. then d and c are twice as wide as a and b to receive the result of the multiplication.type = { .wide}. Saturation modifier: . If .s32 r. . . Supported on all target architectures. t n d d d = = = = = a * b.lo. a.r. t<n-1... Applies only to . mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.s32 type in .. @p mad. b. mad. // for . bitwidth of type.b. then d and c are the same size as a and b.c.hi variant // for .hi. c. . b.s32 d.n> + c. d.wide suffix is supported only for 16.s64 }..MAXINT (no overflow) for the size of the operation.wide is specified.p.q.. t + c. t<2n-1.sat.hi mode.lo is specified. .wide // for .

. Instruction Set Table 30.0. t = a * b. d = t<31. i. d = t<47. mul24.16>.e.0>. // low 32-bits of 24x24-bit signed multiply.hi may be less efficient on machines without hardware support for 24-bit multiply. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.. 48bits.. b. a.. All operands are of the same type and size. and return either the high or low 32-bits of the 48-bit result. Supported on all target architectures. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. mul24. mul24{.hi variant // for .lo.lo}.Chapter 8.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. // for .u32.a. January 24. .hi. 2010 69 .b.type = { .type d.s32 d. mul24.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.s32 }. mul24.

70 January 24. mad24. d = t<47. Supported on all target architectures. d.0 Table 31. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.u32. Return either the high or low 32-bits of the 48-bit result.type = { ..lo}. Saturation modifier: . a.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. 48bits. . a.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.hi mode. mad24.. mad24{. t = a * b.0> + c.hi may be less efficient on machines without hardware support for 24-bit multiply.. and add a third.hi. 32-bit value to either the high or low 32-bits of the 48-bit result. i. // for .b.s32 }.lo. mad24. ..sat. mad24. 2010 .type mad24.a.s32 d.16> + c. Description Compute the product of two 24-bit integer values held in 32-bit source registers.s32 type in . All operands are of the same type and size.MAXINT (no overflow). d = t<31.sat limits result of 32-bit signed addition to MININT.s32 d. b. Applies only to .PTX ISA Version 2. // low 32-bits of 24x24-bit signed multiply.hi variant // for .hi. b.c.0. c. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.e. c.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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clz.b64 d. a. inclusively.type d. X. a.b64 type. // cnt is . 2010 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. popc requires sm_20 or later.u32 PTX ISA Notes Target ISA Notes Examples Table 40. if (. d = 0.b64 d. For . a = a >> 1.0.type == .b32. popc. mask = 0x8000000000000000. mask = 0x80000000. } while (d < max && (a&mask == 0) ) { d++. d = 0. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.u32 Semantics 74 January 24.b32) { max = 32. .b32 popc.b32.0 Table 39. .PTX ISA Version 2. .type d. cnt. For . while (a != 0) { if (a&0x1) d++.b32 type.b32 clz. } else { max = 64.type = { .b64 }. inclusively. cnt. the number of leading zeros is between 0 and 32.0. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. } Introduced in PTX ISA version 2.b64 }. clz requires sm_20 or later. . // cnt is . clz.type = { . popc. a. popc Syntax Integer Arithmetic Instructions: popc Population count. the number of leading zeros is between 0 and 64. a = a << 1. a. X.

Operand a has the instruction type. a. If . } } if (.type d. i>=0.s64 }.u32 || .shiftamt. Description Find the bit position of the most significant non-sign bit in a and place the result in d. Semantics msb = (. For signed integers.s32) ? 31 : 63. // cnt is . . bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. For unsigned integers. bfind. bfind returns 0xFFFFFFFF if no non-sign bit is found.s32.s64 cnt. d = -1.d.u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Instruction Set Table 41.u64. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind requires sm_20 or later. break. .u32 d.shiftamt && d != -1) { d = msb . and operand d has type . bfind returns the bit position of the most significant “1”. X. a. bfind. bfind.type bfind.Chapter 8. d.u32. .shiftamt.type = { . for (i=msb. .u32 January 24.0. 2010 75 .type==. a. i--) { if (a & (1<<i)) { d = i.shiftamt is specified.type==. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.

b32.PTX ISA Version 2. i<=msb. 76 January 24. 2010 .b32 d. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. a.type d. msb = (. for (i=0.type = { . brev requires sm_20 or later. Description Semantics Perform bitwise reversal of input.0 Table 42. brev. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i++) { d[i] = a[msb-i].type==.0.b32) ? 31 : 63.b64 }. a. brev. . .

i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.type==. The destination d is padded with the sign bit of the extracted field. Semantics msb = (. Description Extract bit field from a and place the zero or sign-extended result in d.u32 || .len.start. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. bfe requires sm_20 or later.msb)]. bfe. else sbit = a[min(pos+len-1.u32. i<=msb. .s32) ? 31 : 63.u64. c. If the start position is beyond the msb of the input. 2010 77 . otherwise If the bit field length is zero. January 24. and source c gives the bit field length in bits.a. Source b gives the bit field starting bit position.s32. the destination d is filled with the replicated sign bit of the extracted field. the result is zero. . for (i=0. pos = b.s64 }. and operands b and c are type .type==.type = { . . . b. The sign bit of the extracted field is defined as: .s32.Chapter 8.u64 || len==0) sbit = 0. a.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.0. Instruction Set Table 43. if (. Operands a and d have the same type as the instruction type.type==.u64: .u32.b32 d. .u32 || . d = 0.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.type d. len = c. bfe. .

bfi requires sm_20 or later. and f have the same type as the instruction type. d. . for (i=0.0 Table 44. b. the result is b.type==. Description Align and insert a bit field from a into b.type = { . bfi. bfi.a. a. the result is b. Source c gives the starting bit position for the insertion.b32 d.start. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.b32) ? 31 : 63.b32. c. pos = c.b. Operands a. b. f = b. Semantics msb = (.len. If the bit field length is zero. i<len && pos+i<=msb. i++) { f[pos+i] = a[i].b64 }.u32. .PTX ISA Version 2. and operands c and d are type . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. len = d. and place the result in f. 78 January 24. and source d gives the bit field length in bits. If the start position is beyond the msb of the input.type f. 2010 .

The bytes in the two source registers are numbered from 0 to 7: {b.b1 source select c[7:4] d.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.rc8. For each byte in the target register. . . .b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. b4}. as a 16b permute code. and reassemble them into a 32-bit destination register. b6. The msb defines if the byte value should be copied.mode} d. b1. {b3. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.b3 source select c[15:12] d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. b.f4e. 2010 79 . the four 4-bit values fully specify an arbitrary byte permute. b0}}. Description Pick four arbitrary bytes from two 32-bit registers. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b32{. the permute control consists of four 4-bit selection values. msb=1 means replicate the sign. b2. prmt. c.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b4e. a} = {{b7. . Note that the sign extension is only performed as part of generic form. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. Thus.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.Chapter 8. a 4-bit selection value is defined.ecl.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. . Instruction Set Table 45. . a. b5.mode = { . msb=0 means copy the literal value.b2 source select c[11:8] d.rc16 }. In the generic form (no mode specified).ecr. default mode index d.

tmp64 ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r4. ctl[3] = (c >> 12) & 0xf. 2010 .f4e r1. ctl[1]. ctl[1] = (c >> 4) & 0xf. tmp[15:08] = ReadByte( mode. r2.PTX ISA Version 2. tmp64 ).0. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[0].b32. tmp64 ). prmt. prmt requires sm_20 or later.b32 prmt.0 Semantics tmp64 = (b<<32) | a. ctl[2] = (c >> 8) & 0xf. tmp[31:24] = ReadByte( mode. r1. r3. tmp64 ). r3. } tmp[07:00] = ReadByte( mode. r2. ctl[2]. r4. tmp[23:16] = ReadByte( mode. 80 January 24. ctl[3]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.

Chapter 8.7. 2010 81 .2.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8.f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.

neg.f64 rsqrt.0.ftz .ex2}.sat Notes If no rounding modifier is specified.f64 {abs.f64 and fma.mul}.f32 {div.max}. 82 January 24.f64 mad.approx.rcp.fma}.sqrt}. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.target sm_1x No rounding modifier.rz .approx.rn and instructions may be folded into a multiply-add.rnd.min.f32 {div.target sm_20 . 2010 .f32 {div. The optional .rnd.f32 {mad.approx. NaN payloads are supported for double-precision instructions.cos.mul}.neg. default is .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f64 {sin.approx.0]. . {mad.f32 .rcp.f32 {abs. Double-precision instructions support subnormal inputs and results. No rounding modifier. Note that future implementations may support NaN payloads for single-precision instructions.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. and mad support saturation of results to the range [0.f64 div.rp .rnd.f64 are the same.rnd. default is . 1.sqrt}. mul.min.f32 are the same.rm .rnd.sqrt}.rnd. .rn and instructions may be folded into a multiply-add. with NaNs being flushed to positive zero. sub.PTX ISA Version 2.0 The following table summarizes floating-point instructions in PTX.rcp.max}.sub. If no rounding modifier is specified. Table 46.lg2.full.f32 rsqrt.f32 {add. Single-precision add.rn .32 and fma.target sm_20 mad.sub. {add.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. but single-precision instructions return an unspecified NaN. Instruction Summary of Floating-Point Instructions . so PTX programs should not rely on the specific single-precision NaNs being generated.fma}.

p.Chapter 8. testp Syntax Floating-Point Instructions: testp Test floating-point property.op. true if the input is a subnormal number (not NaN. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. Introduced in PTX ISA version 2. y. testp. copysign. not infinity). copysign requires sm_20 or later. A.infinite.number. Table 48.subnormal }. .op p. z.notanumber.0. f0. 2010 83 . .pred = { . and return the result as d. . X. .f32 copysign.0. a.finite. C. copysign.f32.type d.normal. Instruction Set Table 47.type . // result is . .f64 x. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f64 }. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.infinite. B.f64 isnan. a.f64 }.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.infinite testp. .finite testp.notanumber testp. .normal testp. January 24. . b.notanumber. testp.f32 testp. . testp. not infinity) As a special case.type = { .type = { . testp requires sm_20 or later.f32.number testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. positive and negative zero are considered normal numbers.

f64 d. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Saturation modifier: .rnd}.rn.f32 flushes subnormal inputs and results to sign-preserving zero. Rounding modifiers (default is .f32 clamps the result to [0.rz.0].f2.ftz.0.f32 flushes subnormal inputs and results to sign-preserving zero.rnd}{.rm.rn.f64.f32 f1. .sat}. add. add.ftz.PTX ISA Version 2. add. subnormal numbers are supported. 1. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers have the following target requirements: .f32 add{. a.rm. sm_1x: add. requires sm_20 Examples @p add.f64 supports subnormal numbers.rz.sat. add. add.0.rz mantissa LSB rounds towards zero . Description Semantics Notes Performs addition and writes the resulting value into a destination register. . . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.ftz}{. NaN results are flushed to +0. .rp }.rnd = { . a.rn): . In particular.f3. .rz available for all targets . d = a + b.0 Table 49.rm mantissa LSB rounds towards negative infinity .rp for add. b. 84 January 24.f64 requires sm_13 or later.0f. add{. d.f32.rn mantissa LSB rounds to nearest even . add Syntax Floating-Point Instructions: add Add two values. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 supported on all target architectures. b. requires sm_13 for add. 2010 .

0f. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. b.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .sat}.f3.Chapter 8.rn mantissa LSB rounds to nearest even . . d. d = a . requires sm_13 for sub. Saturation modifier: sub. b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. . 1. sub. 2010 85 . . subnormal numbers are supported.rn.f32 supported on all target architectures.rz.rnd}.ftz}{. a.rm.rnd = { .f32 c.b.b. Rounding modifiers have the following target requirements: . NaN results are flushed to +0.rnd}{. sub.rm mantissa LSB rounds towards negative infinity .ftz. Instruction Set Table 50.0.rn. In particular.0.rm.rz available for all targets .f32. sub. sub{.f64 requires sm_13 or later.ftz. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.sat.rn): .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.a. sub.f64 supports subnormal numbers.f32 f1.rp for sub. January 24. sub Syntax Floating-Point Instructions: sub Subtract one value from another. a.f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples sub. sm_1x: sub. sub.rp }. Rounding modifiers (default is . .rn.0].f64.rz mantissa LSB rounds towards zero .f32 sub{.f32 clamps the result to [0.f2.

requires sm_20 Examples mul.f64 supports subnormal numbers.f32 circumf. For floating-point multiplication. mul. .f32 mul{. .rn mantissa LSB rounds to nearest even .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 supported on all target architectures. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Rounding modifiers (default is . . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. Description Semantics Notes Compute the product of two values.0].0 Table 51. sm_1x: mul.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.rn): .rnd}{. mul. 1. subnormal numbers are supported. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32. d = a * b.rn. mul.rnd}.ftz.f64.rp }. Rounding modifiers have the following target requirements: . In particular.rm mantissa LSB rounds towards negative infinity .f32 flushes subnormal inputs and results to sign-preserving zero.0. requires sm_13 for mul. b.rn. . Saturation modifier: mul.rnd = { .f32 clamps the result to [0. b. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.sat}.rp for mul.radius.0.rz mantissa LSB rounds towards zero .ftz.pi // a single-precision multiply 86 January 24. all operands must be the same size.0f. 2010 . NaN results are flushed to +0. mul Syntax Floating-Point Instructions: mul Multiply two values. .ftz}{.rz.rm.f64 d. a. d.sat. mul. a.rz available for all targets .PTX ISA Version 2. mul{.rm. .

c.f64 computes the product of a and b to infinite precision and then adds c to this product.rn mantissa LSB rounds to nearest even .rz. fma.rnd{.f32 requires sm_20 or later. fma. .f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to single precision using the rounding mode specified by .z. Saturation: fma.ftz.b. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.ftz. fma. d. fma.rp }. again in infinite precision.f64 w.rn. .f32 computes the product of a and b to infinite precision and then adds c to this product.f64 is the same as mad. PTX ISA Notes Target ISA Notes Examples January 24. d.rm.rz mantissa LSB rounds towards zero . fma. sm_1x: fma. The resulting value is then rounded to double precision using the rounding mode specified by . fma. c.sat. b.rnd.f64.x.f32 introduced in PTX ISA version 2.sat}.4.f64 introduced in PTX ISA version 1. a. fma Syntax Floating-Point Instructions: fma Fused multiply-add.0. fma. 1. NaN results are flushed to +0.rn.f64 supports subnormal numbers.f32 fma.rnd. a.rnd = { .rn. d = a*b + c.a. fma.f32 is unimplemented in sm_1x. . fma. Instruction Set Table 52.y. .f32 fma. again in infinite precision. Rounding modifiers (no default): .rm mantissa LSB rounds towards negative infinity .f32 clamps the result to [0. 2010 87 .f64 d.Chapter 8.ftz}{. @p fma. b. subnormal numbers are supported.0].0f.rnd.c.0.f64 requires sm_13 or later. fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.

the treatment of subnormal inputs and output follows IEEE 754 standard.f64 is the same as fma. For . The exception for mad. again in infinite precision.f32.{f32.target sm_1x d. c. b. The resulting value is then rounded to double precision using the rounding mode specified by .f32 flushes subnormal inputs and results to sign-preserving zero. mad. . again in infinite precision.rnd. .rz.{f32. mad. b.rp }.f64 computes the product of a and b to infinite precision and then adds c to this product.rnd{. When JIT-compiled for SM 2. Rounding modifiers (no default): .rn mantissa LSB rounds to nearest even . The resulting value is then rounded to single precision using the rounding mode specified by . mad.0. mad. For . subnormal numbers are supported.f64. a.rnd.rn.sat}. d = a*b + c. Saturation modifier: mad.f32 mad. In this case.f64}. Note that this is different from computing the product with mul.f64 supports subnormal numbers. but the exponent is preserved.0 devices.f32 computes the product of a and b at double precision. mad. sm_1x: mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0.rnd.target sm_13 and later .f32 computes the product of a and b to infinite precision and then adds c to this product. . c. 88 January 24. Unlike mad. and then writes the resulting value into a destination register.sat}. NaN results are flushed to +0. mad.0f.rnd. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. again in infinite precision.rn. b.f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { . a. 1. The resulting value is then rounded to double precision using the rounding mode specified by .f32).rz mantissa LSB rounds towards zero .PTX ISA Version 2.target sm_1x: mad.target sm_20 d.ftz.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz}{. Description Semantics Notes Multiplies two values and adds a third.f32 mad.rm.f32 clamps the result to [0. where the mantissa can be rounded and the exponent will be clamped.f64 d.e.0]. mad. // . fma.f32 is implemented as a fused multiply-add (i. mad{.sat. mad. 2010 . mad.target sm_20: mad.rm mantissa LSB rounds towards negative infinity . c. a.f32 is when c = +/-0.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. // .0 Table 53..ftz}{.f32 is identical to the result computed using separate mul and add instructions.ftz. // . and then the mantissa is truncated to 23 bits.f64} is the same as fma.

mad.f32 supported on all target architectures.Chapter 8..4 and later.f64. a rounding modifier is required for mad.0. In PTX ISA versions 1.rp for mad.0 and later.a..f64.f32 d.rm.rm.c.f64 instructions having no rounding modifier will map to mad.f32...rn. requires sm_20 Examples @p mad.rz. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rn.rn.f32 for sm_20 targets. requires sm_13 .b. In PTX ISA versions 2.f64 requires sm_13 or later. Target ISA Notes mad.rz.. a rounding modifier is required for mad.. January 24. Legacy mad.rp for mad. 2010 89 . Rounding modifiers have the following target requirements: .f64.

a. computed as d = a * (1/b).0 Table 54.f32 supported on all target architectures.rm.rm mantissa LSB rounds towards negative infinity .14159.3. .4. a. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .rnd.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. approximate single-precision divides: div.ftz}. d.rnd{. // // // // fast.f32 implements a fast approximation to divide. 2010 .rm.rnd.ftz. Subnormal inputs and results are flushed to sign-preserving zero. .approx{. PTX ISA Notes div. approximate division by zero creates a value of infinity (with same sign as a).approx.full. div.f32 div.f32 div. y.0 through 1. d. div. For b in [2-126.approx.approx.f64 requires sm_13 or later.f64.f32.4 and later. full-range approximation that scales operands to achieve better accuracy. The maximum ulp error is 2 across the full range of inputs. b.f64 diam.full.ftz.3. Examples 90 January 24. b.f32 div. div. 2126].full{.full.ftz. and rounding introduced in PTX ISA version 1. z.f32 requires sm_20 or later. Description Semantics Notes Divides a by b. one of .f32 flushes subnormal inputs and results to sign-preserving zero.circum. div.approx.f32 and div. b.rn. div. or .ftz}.rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.rp }.f64 defaults to div. but is not fully IEEE 754 compliant and does not support rounding modifiers. the maximum ulp error is 2. d = a / b. stores result in d. d.full.f32 defaults to div. div Syntax Floating-Point Instructions: div Divide one value by another. Target ISA Notes div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f64 introduced in PTX ISA version 1. div. Fast. . Explicit modifiers .rp}. zd.f32 implements a relatively fast.rn.f64 requires sm_20 or later.{rz.full.rn. . div. For PTX ISA version 1.f32 div. For PTX ISA versions 1. xd. div. x.ftz}.f32 and div.0. div.f64 d.ftz.rnd = { . . b.rz. . a.f64 supports subnormal numbers. sm_1x: div.f32 div.rz mantissa LSB rounds towards zero .approx.approx. Fast. a. and div.rnd is required.ftz.rn.PTX ISA Version 2. yd.

subnormal numbers are supported.Chapter 8.ftz. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Table 56. Negate the sign of a and store the result in d. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. a.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: abs. Subnormal numbers: sm_20: By default. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. January 24. abs. neg. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f64 d. neg. d. Take the absolute value of a and store the result in d.ftz. Instruction Set Table 55. d. neg. Subnormal numbers: sm_20: By default.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.f32 neg. abs.f32 x. a. neg.f64 requires sm_13 or later. neg{.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. NaN inputs yield an unspecified NaN.0. sm_1x: neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 abs. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz}.f0. NaN inputs yield an unspecified NaN. d = -a. 2010 91 .f32 flushes subnormal inputs and results to sign-preserving zero. abs{.f32 supported on all target architectures. abs. abs.f0. subnormal numbers are supported.ftz.f64 requires sm_13 or later.f64 d.f64 supports subnormal numbers.0.f64 supports subnormal numbers. a. a. abs.f32 supported on all target architectures. d = |a|.

max. b.0.f32 flushes subnormal inputs and results to sign-preserving zero. min.f64 supports subnormal numbers.b.f64 d.ftz.ftz. a. Table 58. min.f64 requires sm_13 or later. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. 2010 . a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d d d d = = = = NaN.c. max{.ftz}. (a < b) ? a : b.c. max. a. b.ftz}. Store the maximum of a and b in d. a.x. b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a.PTX ISA Version 2. d.b.f32 flushes subnormal inputs and results to sign-preserving zero. min. 92 January 24.f64 d. subnormal numbers are supported. a. b. b.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 f0.ftz.f2. max. sm_1x: min.f32 min.f32 min.z. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 z. d.f32 max.f64 requires sm_13 or later. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. Store the minimum of a and b in d. min. min{.0 Table 57.f32 max.f32 supported on all target architectures. a. @p min. max. max. (a > b) ? a : b.f32 supported on all target architectures. subnormal numbers are supported. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d d d d = = = = NaN. a.f1.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: max.0. b.

f64 defaults to rcp. a.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.approx{.f32 rcp. For PTX ISA version 1. . subnormal numbers are supported. General rounding modifiers were added in PTX ISA version 2.f64 d. d = 1 / a.ftz. 2010 93 . Instruction Set Table 59. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rp}.rn. a. The maximum absolute error is 2-23. PTX ISA Notes rcp.rm.rnd.rn. rcp. rcp.f32 supported on all target architectures.approx.rz mantissa LSB rounds towards zero .f32 and rcp.approx. rcp.rn.rp }.0. one of . rcp.rnd is required.f64 ri. .rz.0 through 1.f32 defaults to rcp.ftz}. d. For PTX ISA versions 1.rnd{.approx.rn.rm.ftz}.rnd = { .Chapter 8.approx.ftz.f64. d.ftz were introduced in PTX ISA version 1.rn. xi. sm_1x: rcp.f32.x. rcp.f64 requires sm_13 or later.0 over the range 1.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 rcp.4. xi.ftz.x. Examples January 24.f32 flushes subnormal inputs and results to sign-preserving zero.f64 introduced in PTX ISA version 1. // fast.0.f32 implements a fast approximation to reciprocal.approx or . rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.r. . rcp.rn mantissa LSB rounds to nearest even .0 +0.4 and later.0 -Inf -Inf +Inf +Inf +0.f64 and explicit modifiers .ftz.f32 rcp.f32 rcp. rcp.f64 requires sm_20 or later. rcp.approx and .0 +subnormal +Inf NaN Result -0.f32 requires sm_20 or later. Target ISA Notes rcp.rnd. rcp.f64 supports subnormal numbers.3. Input -Inf -subnormal -0.0-2. Description Semantics Notes Compute 1/a.{rz. store result in d. and rcp.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn. a.0.

f32 requires sm_20 or later. sqrt. sqrt.f32 is TBD. Target ISA Notes sqrt. store in d.f64 and explicit modifiers . // fast.rn.ftz. sqrt.approx and .rm.f64 requires sm_13 or later.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . sqrt.f64 requires sm_20 or later.rnd = { .f64 supports subnormal numbers.0.x. 2010 . sqrt.approx. sm_1x: sqrt.f32 sqrt.{rz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to square root. one of .ftz}. Description Semantics Notes Compute sqrt(a).approx{. PTX ISA Notes sqrt. . sqrt. and sqrt.rz.0 +subnormal +Inf NaN Result NaN NaN -0.rz mantissa LSB rounds towards zero .rp }.3.rnd.4. // IEEE 754 compliant rounding d.f32.0 -0.f32 sqrt.rnd. .rn.approx.0 +0.f64 r.f32 sqrt.f32 sqrt. a. Examples 94 January 24. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.ftz}.rp}. a.rn. General rounding modifiers were added in PTX ISA version 2.ftz.ftz were introduced in PTX ISA version 1.x. .approx.f32 supported on all target architectures.rm.0 +0.PTX ISA Version 2. // IEEE 754 compliant rounding .rn. For PTX ISA versions 1.x.f64 introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. approximate square root d. Input -Inf -normal -subnormal -0.f64 defaults to sqrt. r. sqrt.rnd{.rn.ftz.rn mantissa LSB rounds to nearest even .approx.f32 defaults to sqrt.0 +0.f64 d.approx or . d = sqrt(a). sqrt. sqrt.ftz.4 and later. subnormal numbers are supported.approx.rm mantissa LSB rounds towards negative infinity .f64. sqrt.f32 and sqrt.rn. r.0 Table 60. a.rnd is required.0 through 1. The maximum absolute error for sqrt. For PTX ISA version 1.0.

0-4. Target ISA Notes Examples rsqrt.4 and later.f32 flushes subnormal inputs and results to sign-preserving zero. ISR. rsqrt. rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f32 defaults to rsqrt. and rsqrt. rsqrt.f32 and rsqrt.0. a.4.ftz}.approx.f64.f32. Note that rsqrt.approx implements an approximation to the reciprocal square root.3.f64 is emulated in software and are relatively slow. a.approx. Subnormal numbers: sm_20: By default.0 NaN The maximum absolute error for rsqrt. Explicit modifiers .f32 supported on all target architectures. For PTX ISA version 1. January 24.approx.approx and . rsqrt. For PTX ISA versions 1.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.approx. rsqrt.approx. Input -Inf -normal -subnormal -0.f64 requires sm_13 or later. d. x.0 through 1.ftz. sm_1x: rsqrt.f64 isr.4 over the range 1. the .ftz were introduced in PTX ISA version 1.f32 rsqrt.approx. X. d = 1/sqrt(a).f64 d.f64 is TBD.f32 is 2-22.0. The maximum absolute error for rsqrt. PTX ISA Notes rsqrt. Compute 1/sqrt(a). rsqrt. Instruction Set Table 61.ftz.f64 were introduced in PTX ISA version 1. 2010 95 . subnormal numbers are supported.approx{. store the result in d. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.Chapter 8.0 +0.ftz.approx modifier is required. rsqrt.f64 defaults to rsqrt.f32 rsqrt.

9 in quadrant 00. Input -Inf -subnormal -0.ftz.4 and later. sin.PTX ISA Version 2. the . 96 January 24.approx.3. sin. d = sin(a).f32 defaults to sin.0 -0. Explicit modifiers . a.0 +0. 2010 .f32 implements a fast approximation to sine. a.ftz.ftz.4.0 NaN NaN The maximum absolute error is 2-20. sin. Subnormal numbers: sm_20: By default. Target ISA Notes Examples Supported on all target architectures. Find the sine of the angle a (in radians). For PTX ISA version 1.f32 d.0 +0.f32 sa. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. subnormal numbers are supported.0 +0.approx.0 Table 62. sm_1x: Subnormal inputs and results to sign-preserving zero.f32. PTX ISA Notes sin.f32 introduced in PTX ISA version 1. For PTX ISA versions 1.0 +subnormal +Inf NaN Result NaN -0.0 through 1.ftz introduced in PTX ISA version 1.approx and .0.approx{. sin.approx. sin.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.approx modifier is required.

ftz.4 and later. subnormal numbers are supported.approx and .ftz introduced in PTX ISA version 1. For PTX ISA versions 1. Instruction Set Table 63. cos. cos.0 +1. Explicit modifiers .approx modifier is required.Chapter 8.f32 defaults to cos. cos.f32 ca. the .0. For PTX ISA version 1. a. Subnormal numbers: sm_20: By default.ftz. cos.0 +1.approx.0 NaN NaN The maximum absolute error is 2-20.0 +1. cos.f32.f32 flushes subnormal inputs and results to sign-preserving zero. a.ftz}. 2010 97 .f32 implements a fast approximation to cosine.0 +subnormal +Inf NaN Result NaN +1. Input -Inf -subnormal -0.approx. Target ISA Notes Examples Supported on all target architectures.f32 d.approx{. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +0. d = cos(a).f32 introduced in PTX ISA version 1.4.0 through 1. Find the cosine of the angle a (in radians). January 24.ftz.approx.3. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. PTX ISA Notes cos.9 in quadrant 00.

lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. lg2.0 +0.f32.f32 introduced in PTX ISA version 1. the .approx. lg2. sm_1x: Subnormal inputs and results to sign-preserving zero.approx{. 98 January 24. lg2. lg2. 2010 .ftz}. lg2. a. Input -Inf -subnormal -0.4 and later.PTX ISA Version 2. For PTX ISA version 1.6 for mantissa.approx and .ftz.approx. For PTX ISA versions 1.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.0 through 1.3. a.4.ftz introduced in PTX ISA version 1.f32 la.f32 defaults to lg2. Explicit modifiers .f32 Determine the log2 of a.approx modifier is required.approx. PTX ISA Notes lg2. subnormal numbers are supported. d = log(a) / log(2).0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. The maximum absolute error is 2-22.f32 implements a fast approximation to log2(a).0 Table 64.0. Target ISA Notes Examples Supported on all target architectures. Subnormal numbers: sm_20: By default.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

n. p = BoolOp(t. Semantics t = (a CmpOp b) ? 1 : 0.s16. q = BoolOp(!t. If both operands are numeric values (not NaN).i. neu.u32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. ls.lt. gt. Applies to all numeric types. . then these comparisons have the same result as their ordered counterparts. a. This result is written to the first destination operand.f32 flushes subnormal inputs to sign-preserving zero.u32 p|q. The destinations p and q must be .and. and hs for lower. The signed and unsigned comparison operators are eq. higher. b.0.s32 setp. p[|q].pred variables. and nan returns true if either operand is NaN. loweror-same.b64.eq.b16. . then the result of these comparisons is true. and higher-or-same may be used instead of lt.s64. gt. {!}c.s32. The untyped.PTX ISA Version 2.r. le. gt. respectively.dtype.B) is one of: and. setp. nan The Boolean operator BoolOp(A. the comparison operators lo.type setp. . p. hs equ. lo. bit-size comparisons are eq and ne. c). p[|q]. The comparison operator is a suffix on the instruction. . Description Compares two values and combines the result with another predicate value by applying a Boolean operator. Integer Notes Floating Point Notes The ordered comparisons are eq. To aid comparison operations in the presence of NaN values. 2010 . or.b32. b. num returns true if both operands are numeric values (not NaN). 102 January 24. .f64 }.dtype.f32. .type . lt. hi.CmpOp{. and (optionally) combine this result with a predicate value by applying a Boolean operator. setp. le. a. setp. le. leu.a. A related value computed using the complement of the compare result is written to the second destination operand. ltu.CmpOp. ge. If either operand is NaN. neu. the result is false.u64. geu. If either operand is NaN. gtu.type = { . xor. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. gt.0 Table 67.BoolOp{.b. . ne.dtype. ge. For unsigned values.f32 comparisons.u16. . sm_1x: setp.f64 source type requires sm_13 or later.f32 flushes subnormal inputs to sign-preserving zero. ne. lt. geu. hi. Subnormal numbers: sm_20: By default. unordered versions are included: equ. ge. ge. leu. ls. lt. @q setp. ltu. le.ftz.ftz applies only to . subnormal numbers are supported.ftz}. c). setp with . Modifier . . and can be one of: eq. ne. . gtu.ftz}.f64 supports subnormal numbers. num.

.u16. . B.ftz}.f32.b16.ftz. c. b otherwise. sm_1x: slct.s32. subnormal numbers are supported.0.f32 flushes subnormal values of operand c to sign-preserving zero. Semantics Floating Point Notes January 24.s32 x.dtype. Operands d.Chapter 8.b32. . d = (c >= 0) ? a : b. d = (c == 1) ? a : b.s64. otherwise b is stored in d. . slct.b64. . a.f32 A.f64 }. based on the value of the predicate source operand. . and operand a is selected.t.ftz applies only to . c. selp Syntax Comparison and Selection Instructions: selp Select between source operands. The selected input is copied to the output without modification. val.s16. a is stored in d.s32 slct{.p. 2010 103 . Modifier . . Introduced in PTX ISA version 1. a. . slct. If c ≥ 0. . b. C.f32 comparisons.f32.u64.b16.u32. Table 69. Operands d.dtype. slct. .f64 }. a.r. a. . Description Conditional selection. and b are treated as a bitsize type of the same width as the first instruction type. f0. .f32 d.f32 comparisons.0. If operand c is NaN.u64. .b64. . @q selp.u32.f64 requires sm_13 or later. . negative zero equals zero. .u64.f64 requires sm_13 or later. slct. . slct Syntax Comparison and Selection Instructions: slct Select one source operand. c. the comparison is unordered and operand b is selected.f32 flushes subnormal values of operand c to sign-preserving zero.b32. d. b.f32 r0. . and operand a is selected.u16. Operand c is a predicate. based on the sign of the third operand.s64. and b must be of the same type. . slct. . Subnormal numbers: sm_20: By default. y. .dtype.xp. selp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. a is stored in d. . a.dtype.s32 selp. Instruction Set Table 68.ftz. For .dtype = { . selp. b.s16. operand c must match the second instruction type.g.u32. If c is True. fval.x.type = { . z.s32.type d.

4. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. 2010 .7. and not also operate on predicates.0 8. This permits bit-wise operations on floating point values without having to define a union to access the bits. performing bit-wise operations on operands of any type. Instructions and. xor.PTX ISA Version 2. provided the operands are of the same size. or.

. . or. and.q.fpvalue.pred. and Syntax Logic and Shift Instructions: and Bitwise AND. d = a | b. The size of the operands must match. . Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type d. Introduced in PTX ISA version 1. a.b64 }.0. Introduced in PTX ISA version 1.0x80000000. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b32 and. a. or.0.b16. 2010 105 .b32. Allowed types include predicate registers.b16.q. but not necessarily the type. Supported on all target architectures. or Syntax Logic and Shift Instructions: or Bitwise OR.type = { . . b.pred p.type = { . d = a & b. Supported on all target architectures. January 24.r. .Chapter 8. b. . sign.pred. but not necessarily the type.r. Table 71.b32 x. .type d.b64 }. The size of the operands must match. Instruction Set Table 70.0x00010001 or.b32. and.b32 mask mask.

Allowed types include predicates.b32 xor. .0. xor.b16. but not necessarily the type. a.b32.b32 d. a. xor.b32 mask.PTX ISA Version 2. Supported on all target architectures.type = { .q.mask. Supported on all target architectures. Supported on all target architectures. not. but not necessarily the type. Table 74. not Syntax Logic and Shift Instructions: not Bitwise negation.b16.type d. d = a ^ b.q.type d. . . .type = { . d. b. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Introduced in PTX ISA version 1. d = ~a.a.b64 }. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. cnot. . Table 73. .0 Table 72. Introduced in PTX ISA version 1. not. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b32.b16.x. d = (a==0) ? 1 : 0. Introduced in PTX ISA version 1. cnot. but not necessarily the type.b16 d. . .pred.0.b32.b64 }. The size of the operands must match.r.0. one’s complement. .pred.type d.0x0001.b64 }. The size of the operands must match. 2010 . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. 106 January 24. Allowed types include predicate registers.pred p. not. a. . The size of the operands must match.type = { .

s32 shr.type d. The sizes of the destination and first source operand must match. The b operand must be a 32-bit value. but not necessarily the type. b. .b16. The b operand must be a 32-bit value.2.0.b16 c. PTX ISA Notes Target ISA Notes Examples January 24. .a.2.b16.type = { .s32. Shift amounts greater than the register width N are clamped to N. .0. shl. Introduced in PTX ISA version 1.u16. .a. zero-fill on right.u32. Supported on all target architectures. .type d. Supported on all target architectures. but not necessarily the type. k. shr. shr. Signed shifts fill with the sign bit.j. . The sizes of the destination and first source operand must match.i. d = a >> b. Shift amounts greater than the register width N are clamped to N. . regardless of the instruction type. regardless of the instruction type. shr Syntax Logic and Shift Instructions: shr Shift bits right. Bit-size types are included for symmetry with SHL.s16.u16 shr. i. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. PTX ISA Notes Target ISA Notes Examples Table 76. b. a. . a.b64. shl. unsigned and untyped shifts fill with 0.b32 q.1. 2010 107 . sign or zero fill on left.b64 }.Chapter 8.u64.type = { . Instruction Set Table 75.b32. . .i.b32. .s64 }. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. . shl Syntax Logic and Shift Instructions: shl Shift bits left. Introduced in PTX ISA version 1. d = a << b.

The isspacep instruction is provided to query whether a generic address falls within a particular state space window. local. st. or shared state spaces. and sust support optional cache operations.5. 2010 . mov. possibly converting it from one format to another. Instructions ld. Data Movement and Conversion Instructions These instructions copy data from place to place. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.PTX ISA Version 2. suld. and from state space to state space. prefetchu isspacep cvta cvt 108 January 24.7. and st operate on both scalar and vector types.0 8. The cvta instruction converts addresses between generic and global. ldu. ld.

lu Last use.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. As a result of this request. evict-first.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.lu operation.ca. Operator . When ld. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. . Instruction Set 8.0 introduces optional cache operators on load and store instructions. bypassing the L1 cache. when applied to a local address. the cache operators have the following definitions and behavior. Table 77.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.cv to a frame buffer DRAM address is the same as ld. .lu instruction performs a load cached streaming operation (ld. The cache operators require a target architecture of sm_20 or later. .5.7. fetch again). The compiler / programmer may use ld. Global data is coherent at the L2 level.lu load last use operation. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.Chapter 8. but multiple L1 caches are not coherent for global data. and a second thread loads that address via a second L1 cache with ld. likely to be accessed again.ca. and cache only in the L2 cache. invalidates (discards) the local L1 line following the load.ca loads cached in L1. Cache Operators PTX 2. For sm_20 and later. if the line is fully covered.cg Cache at global level (cache in L2 and below. A ld.cs is applied to a Local window address. The default load instruction cache operation is ld.cg to cache loads only globally. not L1). .cv Cache as volatile (consider cached system memory lines stale. any existing cache lines that match the requested address in L1 will be evicted. it performs the ld. January 24. If one thread stores to global memory via one L1 cache.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The ld. rather than the data stored by the first thread. to allow the thread program to poll a SysMem location written by the CPU. likely to be accessed once.cs Cache streaming. The ld. Use ld. 2010 109 . The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cs) on global addresses. The ld.cs.1. The ld. the second thread may get stale L1 cache data.

. 110 January 24.cg is the same as st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.wt store write-through operation applied to a global System Memory address writes through the L2 cache. and cache only in the L2 cache. but st.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. However. regardless of the cache operation. In sm_20.wb. Addresses not in System Memory use normal write-back. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. and discard any L1 lines that match. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. 2010 . The default store instruction cache operation is st. . Data stored to local per-thread memory is cached in L1 and L2 with with write-back. The st. If one thread stores to global memory. Future GPUs may have globally-coherent L1 caches. The st. and a second thread in a different SM later loads from that address via a different L1 cache with ld. bypassing its L1 cache. rather than get the data from L2 or memory stored by the first thread. and marks local L1 lines evict-first.cg to local memory uses the L1 cache. st.ca loads.cg to cache global store data only globally.wt. bypassing the L1 cache.wt Cache write-through (to system memory). Operator . likely to be accessed once.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. the second thread may get a hit on stale L1 cache data.ca.cg Cache at global level (cache in L2 and below. in which case st. Global stores bypass L1.wb for global data. which writes back cache lines of coherent cache levels with normal eviction policy.PTX ISA Version 2. to allow a CPU program to poll a SysMem location written by the GPU with st.cs Cache streaming. .wb could write-back global store data from L1.0 Table 78. not L1). Use st.

s32. special register. u. alternately. d = sreg. . local.f32. within the variable’s declared state space Notes Although only predicate and bit-size types are required. d = &label.type mov.s16. .type mov. Semantics d = a..type d. Note that if the address of a device function parameter is moved to a register. Instruction Set Table 79. . d = &avar. d. . sreg.b32.u64. local.v. or function name.f64 }.b64. // get address of variable // get address of label or function . .f32 mov. // address is non-generic. the address of the variable in its state space) into the destination register. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.global. label. . the parameter will be copied onto the stack and the address will be in the local state space.f64 requires sm_13 or later.type = { .s64. or shared state space may be taken directly using the cvta instruction. . or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.shared state spaces. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. 2010 111 . Write register d with the value of a.u32 mov. variable in an addressable memory space. The generic address of a variable in global. Operand a may be a register.u16.0. d. .e. myFunc..e. i. mov. Description . mov places the non-generic address of the variable (i.type mov. A[5].u32 mov.Chapter 8. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.1. label.0. ptr. d. addr. and . mov. Take the non-generic address of a variable in global. immediate. a. A.const. ptr.b16. k.pred.u16 mov. mov.a. local. .f32 mov. or shared state space. Introduced in PTX ISA version 1. . . For variables declared in .u32. the generic address of a variable declared in global. .local.u32 d. avar.

w } = { a[0.w have type .b32. .31] } // unpack 8-bit elements from .b64 mov.b32 %r1.b64 }.y.x | (a. d.31].31] } // unpack 16-bit elements from .y } = { a[0. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.b32 { d.23]. // // // // a..x.x..a}. a[16.y << 16) | (a.y << 32) // pack two 8-bit elements into . a[16.b32 mov.b.b16 // pack four 8-bit elements into .type = { .y.PTX ISA Version 2.w}.b16. 2010 . mov.15].63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.z.y.x | (a.31]. a[32.w } = { a[0.7].7].0.47]. Description Write scalar register d with the packed value of vector register a.b64 { d.0 Table 80.x. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.u8 // unpack 32-bit elements from ..b64 112 January 24.type d.b16 { d...u32 x.z. d.%r1.x.b}. a[48. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). a[8. a[32.b64 // pack two 32-bit elements into .b32 mov. .15]..x | (a. or write vector register d with the unpacked values from scalar register a.w << 24) d = a..z.y } = { a[0. a[16..hi}.{a. d.b32 { d.u16 %x is a double.{x. d.b8 r.15].y } = { a[0.x | (a.y. d.b have type .b64 { d.z. d. . For bit-size types.y << 8) | (a..63] } // unpack 16-bit elements from . a[8.g.b32 // pack two 16-bit elements into .b.15] } // unpack 8-bit elements from . a[24...b32 // pack four 16-bit elements into . mov.x | (a. {lo.y << 8) d = a.z << 32) | (a. Semantics d = a.hi are .. %x. %r1.x.w << 48) d = a.g. a.a have type . {r.y << 16) d = a. d..z << 16) | (a. lo. d. d. Supported on all target architectures..

PTX ISA Notes January 24. .ss}{.e.ca. . This may be used. .reg state space. Addresses are zero-extended to the specified width as needed. d.param.b16.Chapter 8. . .global and . an address maps to the corresponding location in local or shared memory. and truncated if the register width exceeds the state space address width for the target architecture.s64. .volatile introduced in PTX ISA version 1.s32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Generic addressing and cache operations introduced in PTX ISA 2. [a].cop = { .f64 using cvt. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.0.local.s8.type . Instruction Set Table 81. Generic addressing may be used with ld. an integer or bit-size type register reg containing a byte address. [a]. ld introduced in PTX ISA version 1. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.volatile may be used with . Cache operations are not permitted with ld. *(immAddr).type ld.shared }. Within these windows. .u16. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.v2. and is zeroextended to the destination register width for unsigned and bit-size types.volatile{.ss = { .global. [a].type d.type ld{.u32.. The address must be naturally aligned to a multiple of the access size.u64. perform the load using generic addressing. .f16 data may be loaded using ld. i.u8. .type = { . and then converted to . ld. . d. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b64. The address size may be either 32-bit or 64-bit.ss}. If an address is not properly aligned.1. *a.0. . or [immAddr] an immediate absolute byte address (unsigned.cv }. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .b32.cop}. In generic addressing. for example.ss}. A destination register wider than the specified type may be used.b16.e. . d. .lu. 32-bit). .ss}{. ld{.f64 }. 2010 113 .v4 }.volatile. The . . The value loaded is sign-extended to the destination register width for signed integers. [a].s16. .vec. .f32. the resulting behavior is undefined.cg. . an address maps to global memory unless it falls within the local memory window or the shared memory window. Description Load register variable d from the location specified by the source address operand a in specified state space. ld.vec.volatile{. or the instruction may fault.cop}. to enforce sequential consistency between threads accessing shared memory. 32-bit).const space suffix may have an optional bank number to indicate constant banks other than bank zero. .vec = { .const. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. Semantics d d d d = = = = a.f32 or . i. If no state space is given. *(a+immOff). .shared spaces to inhibit optimization of references to volatile memory.cs. . . .volatile. .b8. .

Q.b32 ld.f16 d.const.b64 ld.[fs].f32.global. // load .global.b32 ld.[p+-8].v4.%r.[a]. %r.[p+4]. 2010 .[240].b16 cvt. d.const[4]. ld.f32 ld.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. // negative offset %r.s32 ld.b32 ld. // immediate address %r.0 Target ISA Notes ld. // access incomplete array x.local.PTX ISA Version 2.[buffer+64].[p].local. x.f64 requires sm_13 or later.shared. Generic addressing requires sm_20 or later. Cache operations require sm_20 or later.

and is zeroextended to the destination register width for unsigned and bit-size types.0.ss = { .v2. .vec = { .b32 d.reg state space. If no state space is given. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. . *(a+immOff). The address must be naturally aligned to a multiple of the access size. The addressable operand a is one of: [avar] the name of an addressable variable var.b16. . Instruction Set Table 82.u64.s16. an address maps to global memory unless it falls within the local memory window or the shared memory window. or [immAddr] an immediate absolute byte address (unsigned. ldu.s64. // load from address // vec load from address . or the instruction may fault. If an address is not properly aligned. . . 32-bit). . In generic addressing. d. The value loaded is sign-extended to the destination register width for signed integers.v4 }.e.global. the access may proceed by silently masking off low-order address bits to achieve proper rounding. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. A destination register wider than the specified type may be used.u16.ss}.[a].f32 Q.e.f64 }. i. the resulting behavior is undefined. *a. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The address size may be either 32-bit or 64-bit.v4.type d.. 2010 115 .b16. .vec.f64 requires sm_13 or later. . only generic addresses that map to global memory are legal. perform the load using generic addressing. [areg] a register reg containing a byte address. For ldu.ss}. PTX ISA Notes Target ISA Notes Examples January 24.u8. Introduced in PTX ISA version 2. ldu.s32. *(immAddr). A register containing an address may be declared as a bit-size type or integer type.b64. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. where the address is guaranteed to be the same across all threads in the warp. . 32-bit).global.f32 or .b32.b8. .f16 data may be loaded using ldu.global. Semantics d d d d = = = = a.type = { . ldu.[p+4].global }. . Addresses are zero-extended to the specified width as needed.f32. The data at the specified address must be read-only. ldu{. Within these windows.f64 using cvt. . an address maps to the corresponding location in local or shared memory. and then converted to . . ldu.f32 d. // state space . [a]. .s8. [a]. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.u32.Chapter 8. i.type ldu{. and truncated if the register width exceeds the state space address width for the target architecture.[p]. .

s16. .0.e. to enforce sequential consistency between threads accessing shared memory.type . Cache operations are not permitted with st. b. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.PTX ISA Version 2.cop .vec . Generic addressing requires sm_20 or later.b32. [a].global and . . the resulting behavior is undefined.u64..f64 requires sm_13 or later.volatile may be used with .u8.vec.ss . st.1. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. st introduced in PTX ISA version 1.f16 data resulting from a cvt instruction may be stored using st.volatile{. If an address is not properly aligned.cg.s64.ss}{. an address maps to the corresponding location in local or shared memory. . *(d+immOffset) = a. b. b. . This may be used.b16. an integer or bit-size type register reg containing a byte address. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.volatile introduced in PTX ISA version 1. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. *(immAddr) = a. { .type st{. b. Semantics d = a. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. 32-bit).v4 }. The address size may be either 32-bit or 64-bit. Cache operations require sm_20 or later.wb. A source register wider than the specified type may be used. { . .global.vec. . or [immAddr] an immediate absolute byte address (unsigned.shared }. or the instruction may fault.local.ss}. . . an address maps to global memory unless it falls within the local memory window or the shared memory window.b64. 32-bit). perform the store using generic addressing.wt }. . PTX ISA Notes Target ISA Notes 116 January 24.u32.volatile.f64 }.reg state space. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.cop}. .s32.type st. st.shared spaces to inhibit optimization of references to volatile memory. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. i. [a]. Generic addressing and cache operations introduced in PTX ISA 2. [a]. .b16.u16. for example.type [a]. .ss}. If no state space is given.cop}.cs.v2. st{.volatile. The lower n bits corresponding to the instruction-type width are stored to memory.0 Table 83.e. . and truncated if the register width exceeds the state space address width for the target architecture. The address must be naturally aligned to a multiple of the access size.ss}{. { . . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . . st.type = = = = {. . i.b8. . Within these windows. 2010 . In generic addressing.0.f32. . *d = a. Addresses are zero-extended to the specified width as needed. . Generic addressing may be used with st.s8.volatile{.

a. [p].b32 st.%r.local.s32 cvt. [q+4].r7.f16.v4.b16 [a].local. [q+-8]. // negative offset [100].b.f32 st.global.Chapter 8.local. [fs].%r.Q.s32 st.f32 st. 2010 117 . // %r is 32-bit register // store lower 16 bits January 24.a. // immediate address %r.global. Instruction Set Examples st.b32 st.

Addresses are zero-extended to the specified width as needed.global. in specified state space. . 118 January 24. prefetch and prefetchu require sm_20 or later.PTX ISA Version 2. . // prefetch to data cache // prefetch to uniform cache . The addressable operand a is one of: [var] [reg] the name of an addressable variable var.L2 }. prefetchu. Within these windows. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. an address maps to global memory unless it falls within the local memory window or the shared memory window. and no operation occurs if the address maps to a local or shared memory location. the prefetch uses generic addressing. In generic addressing. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.space = { . If no state space is given. or [immAddr] an immediate absolute byte address (unsigned. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.L1 [addr]. A prefetch into the uniform cache requires a generic address.0 Table 84. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.0. and truncated if the register width exceeds the state space address width for the target architecture. a register reg containing a byte address.level prefetchu. The address size may be either 32-bit or 64-bit.L1 [a]. i. [a]. prefetch{.e.global. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.level = { .L1 [ptr]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.L1. 32-bit). 2010 . 32-bit). A prefetch to a shared memory location performs no operation.local }.space}. . prefetch. an address maps to the corresponding location in local or shared memory.

lptr. isspacep requires sm_20 or later.shared }.space = { .u64.local. or shared state space to generic. p.u32.u64. or vice-versa.0. .u64 or cvt. local. cvta.global.global.space = { . Use cvt.u64 }.to.size cvta.local isspacep.pred . 2010 119 .shared isglbl.0. A program may use isspacep to guard against such incorrect behavior. cvta requires sm_20 or later. isshrd. isspacep.u32 or .to.space. sptr. cvta. . a. the generic address of the variable may be taken using cvta. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or shared address cvta. Description Convert a global.size .u32 to truncate or zero-extend addresses. islcl. p.genptr. gptr. Instruction Set Table 85. The source address operand must be a register of type .lptr.u32 p. Introduced in PTX ISA version 2.space p.Chapter 8.local.local. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. or shared state space. or shared state space.size p. The destination register must be of type .global. a. January 24. // local.pred. For variables declared in global. local. or vice-versa. .u32 p. local.space. a. local. The source and destination addresses must be the same size. or shared address. Take the generic address of a variable declared in global.u32. . local.global isspacep. // convert to generic address // get generic address of var // convert generic address to global.size = { .shared }. // get generic address of svar cvta. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. // result is . or shared address to a generic address. isspacep. svar.shared. When converting a generic address into a global. cvta.u32 gptr. PTX ISA Notes Target ISA Notes Examples Table 86. . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.space. var.

MAXINT for the size of the operation.ftz.ftz.f16.f32.atype = { .f64 }.rpi }. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32. .f32.f32 float-tofloat conversions with integer rounding.rmi.u32.sat}.u64. . .dtype.dtype = .f32 float-to-integer conversions and cvt.f32 float-to-integer conversions and cvt..rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. the .dtype. . The optional . The compiler will preserve this behavior for legacy PTX code. a.frnd = { .atype d.s8. i. subnormal numbers are supported. cvt{.rni round to nearest integer.s64.u8. Integer rounding is illegal in all other instances. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. d = convert(a). .ftz}{. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. subnormal inputs are flushed to signpreserving zero. // integer rounding // fp rounding . .ftz. . i. .f32 float-tofloat conversions with integer rounding.PTX ISA Version 2. subnormal inputs are flushed to signpreserving zero.rm. .ftz}{.0 Table 87.rn. .rzi round to nearest integer in the direction of zero . . the result is clamped to the destination range by default.rz.frnd}{. .rzi.4 and earlier.rni. For cvt.sat}. choosing even integer if source is equidistant between two integers.irnd}{.e.ftz.dtype.rp }. 2010 .sat limits the result to MININT. Description Semantics Integer Notes Convert between different types and sizes. Note that saturation applies to both signed and unsigned integer types. .e. .sat modifier is illegal in cases where saturation is not possible based on the source and destination types. Integer rounding is required for float-to-integer conversions. Integer rounding modifiers: . . d..atype cvt{.dtype. a.sat is redundant.s16.ftz modifier may be specified in these cases for clarity. . . Note: In PTX ISA versions 1.s32. sm_1x: For cvt. .rmi round to nearest integer in direction of negative infinity . .irnd = { . Saturation modifier: .u16. and for same-size float-tofloat conversions where the value is rounded to an integer. . For float-to-integer conversions. 120 January 24.sat For integer destination types. .

ftz behavior for sm_1x targets January 24.f16. Subnormal numbers: sm_20: By default. subnormal numbers are supported.rn mantissa LSB rounds to nearest even .4 or earlier. and for integer-to-float conversions. and . // round to nearest int.4 and earlier. and cvt.f32.s32 f.f64 requires sm_13 or later.y.f32 instructions. Floating-point rounding is illegal in all other instances.y.f32. Floating-point rounding modifiers: . 2010 121 .r.rm mantissa LSB rounds towards negative infinity .Chapter 8.s32.i. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. result is fp cvt. Introduced in PTX ISA version 1. Applies to .sat For floating-point destination types. The compiler will preserve this behavior for legacy PTX code. cvt to or from . Saturation modifier: . Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. The operands must be of the same size. if the PTX .f32.sat limits the result to the range [0. The result is an integral value.ftz modifier may be specified in these cases for clarity. // note . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f64.f32 x.0].f16. The optional . stored in floating-point format. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.rni. .f64 j.0. cvt.f32 x.version is 1. Note: In PTX ISA versions 1. Modifier . NaN results are flushed to positive zero.f32. // float-to-int saturates by default cvt.f32.0.f16. 1.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).rz mantissa LSB rounds towards zero . cvt.f64 types. Specifically. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. cvt.f32.f32.

PTX has two modes of operation. mul.width. samplers. but the number of samplers is greatly restricted to 16. .height. with the restriction that they correspond 1-to-1 with the 128 possible textures. .b32 r5. and surface descriptors: • • • Static initialization of texture. = nearest width height tsamp1. Texturing modes For working with textures and samplers.u32 r5. texture and sampler information each have their own handle. and surface descriptors. . [tex1]. sampler.target options ‘texmode_unified’ and ‘texmode_independent’. allowing them to be defined separately and combined at the site of usage in the program. r1. 2010 . and surface descriptors. If no texturing mode is declared. r4. and surface descriptors. r5. r5. sampler. add. and surfaces. 122 January 24.samplerref tsamp1 = { addr_mode_0 filter_mode }.u32 r5. the file is assumed to use unified mode.f32 r3. [tex1].texref tex1 ) { txq.f2}].f32 r1. Example: calculate an element’s power contribution as element’s power/total number of elements.r3. [tex1.7. // get tex1’s txq.param .r2.entry compute_power ( .b32 r6. add. texture and sampler information is accessed through a single .global .0 8. add.f32 r1. r3.2d. cvt. PTX supports the following operations on texture.r4}. Ability to query fields within texture.target texmode_independent . div.6. sampler.v4. Module-scope and per-entry scope definitions of texture. r2. r6. The advantage of unified mode is that it allows 128 samplers. The advantage of independent mode is that textures and samplers can be mixed and matched.texref handle. {f1.f32. r3. sampler. Texture and Surface Instructions This section describes PTX instructions for accessing textures. r1. A PTX module may declare only one texturing mode. r1. In the independent mode. In the unified mode.PTX ISA Version 2.. The texturing mode is selected using .. } = clamp_to_border.f32 {r1. // get tex1’s tex. r5.f32.f32 r1.

the sampler behavior is a property of the named texture. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. //Example of unified mode texturing tex. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.s32. . i. // Example of independent mode texturing tex.f3. where the fourth element is ignored. // explicit sampler . c].s32. [tex_a. [tex_a.r2.Chapter 8.dtype. b.btype tex.f32 }.f2. If no sampler is specified.s32. If an address is not properly aligned.dtype = { . Description Texture lookup using a texture coordinate vector.geom = { .v4 coordinate vectors are allowed for any geometry.geom.s32 {r1. The instruction always returns a four-element vector of 32-bit values.3d }.f32 {r1. {f1}]. the resulting behavior is undefined. and is a four-element vector for 3d textures.f4}]. tex txq suld sust sured suq Table 88. d. or the instruction may fault. An optional texture sampler b may be specified. the square brackets are not required and .f32 }.u32. Notes For compatibility with prior versions of PTX. . 2010 123 .v4. . .dtype. [a. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. is a two-element vector for 2d textures.v4.3d. c]. Operand c is a scalar or singleton tuple for 1d textures. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. with the extra elements being ignored.btype = { . {f1. .v4.s32.r2.r4}. . .r3.1d. tex. Supported on all target architectures. Unified mode texturing introduced in PTX ISA version 1. A texture base address is assumed to be aligned to a 16-byte address.geom.r3.. sampler_x. [a.2d.0. PTX ISA Notes Target ISA Notes Examples January 24.r4}. Instruction Set These instructions provide access to texture and surface memory. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.1d.btype d.e.v4.5.

// unified mode // independent mode 124 January 24.width . addr_mode_2 }. .5. txq. Operand a is a .addr_mode_0 . Supported on all target architectures. sampler attributes are also accessed via a texref argument. txq.addr_mode_0.0 Table 89.depth . // texture attributes // sampler attributes .normalized_coords }.depth. d.tquery. [tex_A].tquery = { .filter_mode . In unified mode.PTX ISA Version 2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 %r1. . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.height.width.squery. .addr_mode_0. Description Query an attribute of a texture or sampler.filter_mode. Query: . [a].samplerref variable.texref or . txq.addr_mode_1 .b32 %r1.width. [a]. [tex_A].squery = { . . [smpl_B].b32 txq.height . mirror.b32 %r1.b32 d. clamp_ogl. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.filter_mode. addr_mode_1.normalized_coords .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). txq. and in independent mode sampler attributes are accessed via a separate samplerref argument. Integer from enum { nearest. . 2010 . linear } Integer from enum { wrap. clamp_to_edge.

. suld.e.ca. and the size of the data transfer matches the size of destination operand d.s32. // cache operation none.trap . // unformatted d.clamp . .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.p. is a two-element vector for 2d surfaces. [surf_B.b64. .v2.f32.2d. 2010 125 . // for suld.b. b].w}].trap {r1.cv }. sm_1x targets support only the .dtype .trap clamping modifier.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.p requires sm_20 or later.u32. .3d. . Target ISA Notes Examples January 24.f32. suld. then .trap suld.y. // for suld. if the surface format contains SINT data. . suld.f4}. b]. .b32.Chapter 8. [a. suld.0. or .b. and cache operations introduced in PTX ISA version 2.v4 }.p.zero }.clamp = = = = = = { { { { { { d. Operand b is a scalar or singleton tuple for 1d surfaces. i. .geom{.dtype . suld. A surface base address is assumed to be aligned to a 16-byte address.3d }.b. G. suld.5. Cache operations require sm_20 or later.u32. the surface sample elements are converted to . B. and is a four-element vector for 3d surfaces.p is currently unimplemented.s32. If an address is not properly aligned. . [a. suld.clamp field specifies how to handle out-of-bounds addresses: . Coordinate elements are of type . .cop .r2}.s32. Description Load from surface memory using a surface coordinate vector.s32 is returned. .v2.cg.b64 }.surfref variable. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . .clamp suld. {f1. The . the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp .b performs an unformatted load of binary data. .geom{.z.s32. . {x}].1d. .clamp.f3. {x. SNORM.u32 is returned. size and type conversion is performed as needed to convert from the surface sample format to the destination type.. the resulting behavior is undefined.trap.cop}.b32. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.v4.1d.p .b supported on all target architectures. . if the surface format contains UINT data. If the destination type is .b32.trap introduced in PTX ISA version 1. Destination vector elements corresponding to components that do not appear in the surface format are not written.geom . suld. suld.u32.cs.f32 }.dtype.b8 . additional clamp modifiers.cop}. where the fourth element is ignored.f32 is returned. or FLOAT data. If the destination base type is . and A components of the surface format. Instruction Set Table 90. or .p. [surf_A. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.vec .3d requires sm_20 or later.vec. . // formatted . then . then .b16. or the instruction may fault.f32 based on the surface format as follows: If the surface format contains UNORM. The lowest dimension coordinate represents a sample offset rather than a byte offset. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b . Operand a is a .f2.dtype.v4. .

If the source type is .clamp = = = = = = { { { { { { [a.z. .3d.wt }.f32. .p Description Store to surface memory using a surface coordinate vector. sust. [surf_B. A surface base address is assumed to be aligned to a 16-byte address. .clamp . .v4 }.zero }.f32} are currently unimplemented. sust. G. .clamp. sust.3d requires sm_20 or later. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32. .b // for sust. sust. {r1. 2010 .. These elements are written to the corresponding surface sample components. where the fourth element is ignored. if the surface format contains UINT data. The .ctype.surfref variable.trap introduced in PTX ISA version 1. {x. sust.0 Table 91. if the surface format contains SINT data. . The source vector elements are interpreted left-to-right as R.clamp . {x}]. .p. Coordinate elements are of type .cop}. .trap clamping modifier.clamp field specifies how to handle out-of-bounds addresses: .p. and cache operations introduced in PTX ISA version 2.w}]. .f32. i.v2.trap [surf_A. Surface sample components that do not occur in the source vector will be written with an unpredictable value.y. size and type conversions are performed as needed between the surface sample format and the destination type.2d. The size of the data transfer matches the size of source operand c. b].b32. and A surface components.s32.b.cop .v4. b]. .f2.vec .f32 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. If the source base type is .b64.u32 is assumed. sust. additional clamp modifiers.b32. c.p requires sm_20 or later.b32.p. .s32 is assumed. c.wb. sm_1x targets support only the .5. Operand b is a scalar or singleton tuple for 1d surfaces.r2}.geom{. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. // for sust. // unformatted // formatted .1d.b. then . If an address is not properly aligned. the resulting behavior is undefined. .vec.trap. .b16.b supported on all target architectures. . [a.clamp sust.f3.u32. Target ISA Notes Examples 126 January 24.cg. .ctype .s32. or FLOAT data. and is a four-element vector for 3d surfaces. . sust Syntax Texture and Surface Instructions: sust Store to surface memory.u32.geom{.{u32. .ctype .geom . or .f32 is assumed.0. then .p.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.v2.b64 }.1d. is a two-element vector for 2d surfaces. {f1. or the instruction may fault.PTX ISA Version 2.ctype.s32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.p performs a formatted store of a vector of 32-bit data values to a surface sample.cs.e. Operand a is a . sust. The lowest dimension coordinate represents a sample offset rather than a byte offset.b8 .cop}.f4}. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.3d }. . sust.trap sust.vec. none. SNORM. Cache operations require sm_20 or later. Source elements that do not occur in the surface sample are ignored.b. sust. B. . The source data is then converted from this type to the surface sample format. then .b performs an unformatted store of binary data.trap .

. sured. Operand a is a .u32 and . 2010 127 .y}]. {x. .u32. .or }. The .b32.clamp [a. // sample addressing .clamp [a. and is a four-element vector for 3d surfaces.c. .op.u32. The instruction type is restricted to .s32 types..and. January 24. . r1.b32 }.s32.b32.trap sured.add. .geom = { . .surfref variable.0.trap .min. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b32. .s32 is assumed. Coordinate elements are of type .u32.s32 or .s32. Operations add applies to .2d.c. and .add.max. . .geom. If an address is not properly aligned.u32 is assumed. .u32 based on the surface sample format as follows: if the surface format contains UINT data.b32 type. the resulting behavior is undefined. min and max apply to . is a two-element vector for 2d surfaces.3d }. or the instruction may fault. where the fourth element is ignored.Chapter 8. .u64.clamp . or . and the data is interpreted as . .ctype.op = { .e. // for sured. r1.ctype. sured. .min.clamp = { .clamp. operations and and or apply to .p performs a reduction on sample-addressed 32-bit data.b.p. [surf_B. sured. then .b performs an unformatted reduction on .u64 data. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. sured.op.s32 types. The lowest dimension coordinate represents a sample offset rather than a byte offset.b . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Operand b is a scalar or singleton tuple for 1d surfaces.u64.1d.1d.geom. {x}]. // for sured. i.clamp field specifies how to handle out-of-bounds addresses: .b]. Instruction Set Table 92. then .trap. sured requires sm_20 or later. the access may proceed by silently masking off low-order address bits to achieve proper rounding. // byte addressing sured.p . .b.b32 }.ctype = { . . Reduction to surface memory using a surface coordinate vector.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. A surface base address is assumed to be aligned to a 16-byte address. if the surface format contains SINT data.u32.2d.s32.p.ctype = { . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b].trap [surf_A.zero }.

suq. Supported on all target architectures.PTX ISA Version 2.height. [a].0 Table 93.height .width .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. [surf_A].query.depth }.b32 %r1.5.width. . 2010 . suq. . Operand a is a . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.surfref variable. 128 January 24.b32 d. .query = { .width. Query: . Description Query an attribute of a surface.

0.f32 @!p div. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.s32 a.0. Execute an instruction or instruction block for threads that have the guard predicate true. mov.a.b. Threads with a false guard predicate do nothing. @{!}p instruction. Instruction Set 8. setp.s32 d. used primarily for defining a function body.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. ratio.7. Introduced in PTX ISA version 1. } PTX ISA Notes Target ISA Notes Examples Table 95.0. { add.7.eq. Supported on all target architectures.x.f32 @q bra L23.Chapter 8. Supported on all target architectures. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.c. 2010 129 . {} Syntax Description Control Flow Instructions: { } Instruction grouping. { instructionList } The curly braces create a group of instructions.y. p. If {!}p then instruction Introduced in PTX ISA version 1.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Chapter 8.0. All threads in the warp are stalled until the barrier completes. Execution in this case is unpredictable.red delays the executing threads (similar to bar.sync) until the barrier count is met. the final value is written to the destination register in all threads waiting at the barrier.and.and).cta. threads within a CTA that wish to communicate via memory can store to memory. {!}c.sync 0. Operand b specifies the number of threads participating in the barrier. a{.sync with an immediate barrier number is supported for sm_1x targets.arrive a{.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. it is as if all the threads in the warp have executed the bar instruction. bar. In conditionally executed code. the waiting threads are restarted without delay. all-threads-true (.popc).{arrive.sync bar. and bar. a{.arrive. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).red are population-count (. all threads in the CTA participate in the barrier. if any thread in a warp executes a bar instruction.red} require sm_20 or later. January 24. p. If no thread count is specified. .op.arrive using the same active barrier. Note that a non-zero thread count is required for bar.op = { . The result of .or }.u32 bar. the optional thread count must be a multiple of the warp size. When a barrier completes.. while .red} introduced in PTX . b.red also guarantee memory ordering among threads identical to membar. Once the barrier count is reached.red performs a predicate reduction across the threads participating in the barrier. and any-thread-true (.0. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. thread count. and then safely read values stored by other threads prior to the barrier. Each CTA instance has sixteen barriers numbered 0.version 2. bar. 2010 133 . The barrier instructions signal the arrival of the executing threads at the named barrier.15. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.sync and bar.popc is the number of threads with a true predicate. Register operands. Operands a. the bar. b}. and d have type . thread count.or).pred .sync without a thread count introduced in PTX ISA 1.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Thus. d.red instruction.u32.red should not be intermixed with bar. Instruction Set Table 100. Since barriers are executed on a per-warp basis. operands p and c are predicates.{arrive. PTX ISA Notes Target ISA Notes Examples bar. execute a bar.red.red performs a reduction operation across threads. bar. {!}c. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. Register operands. Only bar.popc. b}. and bar. b}. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. bar.and and . Description Performs barrier synchronization and communication within a CTA. bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). bar. bar. In addition to signaling its arrival at the barrier. The reduction operations for bar.arrive does not cause any waiting by the executing threads. bar.red. b. Barriers are executed on a per-warp basis as if all the threads in a warp are active. and the barrier is reinitialized so that it can be immediately reused. it simply marks a thread's arrival at the barrier. a.sync or bar.sync or bar. bar. Thus.sync and bar.

.level.g.{cta.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.sys Waits until all prior memory requests have been performed with respect to all clients. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. by st.cta. . A memory read (e. level describes the scope of other clients for which membar is an ordering event.gl} introduced in PTX . PTX ISA Notes Target ISA Notes Examples membar. membar.cta.sys requires sm_20 or later. red or atom) has been performed when the value written has become visible to other clients at the specified level.level = { . membar.sys }.0.gl.sys will typically have much longer latency than membar.sys. when the previous value can no longer be read. For communication between threads in different CTAs or even different SMs.4.cta. membar. this is the appropriate level of membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. membar. or system memory level. .0 Table 101. 134 January 24.version 2. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.gl} supported on all target architectures.{cta. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar. membar.gl.gl will typically have a longer latency than membar.sys introduced in PTX .version 1. including thoses communicating via PCI-E such as system and peer-to-peer memory. membar. A memory write (e. membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. 2010 .PTX ISA Version 2.gl. that is. membar. and memory reads by this thread can no longer be affected by other thread writes. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar. membar. global.cta Waits until all prior memory writes are visible to other threads in the same CTA.g. membar.

perform the memory accesses using generic addressing. . atom{. b.s32. A register containing an address may be declared as a bit-size type or integer type.space}.or.u64.inc. and exch (exchange).exch. cas (compare-and-swap).u64 .s32.f32 Atomically loads the original value at location a into destination register d. . d. . and truncated if the register width exceeds the state space address width for the target architecture. . [a]. If no state space is given. a de-referenced register areg containing a byte address.min. .op = { . The bit-size operations are and. inc. .. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. an address maps to global memory unless it falls within the local memory window or the shared memory window. The integer operations are add.add. Addresses are zero-extended to the specified width as needed.space = { . .b]. .space}. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. 2010 135 . overwriting the original value.b32. .shared }. .f32. or the instruction may fault. and stores the result of the specified operation at location a. . . The floating-point add. . e.f32 }.op.e.b32. or by using atom. b. Instruction Set Table 102.and. accesses to local memory are illegal.type d. atom. min. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.type = { .u32. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. For atom.dec. The address must be naturally aligned to a multiple of the access size. . Operand a specifies a location in the specified state space.g. .xor. and max. or. If an address is not properly aligned.s32. In generic addressing. min. c.b64 .Chapter 8. i. an address maps to the corresponding location in local or shared memory.op. .u32.exch to store to locations accessed by other atomic operations. dec. The address size may be either 32-bit or 64-bit.global.cas.max }. min. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Description // // // // // . xor. The floating-point operations are add.add. the access may proceed by silently masking off low-order address bits to achieve proper rounding.e.u32. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b64.type atom{. max. or [immAddr] an immediate absolute byte address. by inserting barriers between normal stores and atomic operations to a common address. the resulting behavior is undefined. . .. . The inc and dec operations return a result in the range [0. Within these windows. [a].u32 only . 32-bit operations. performs a reduction operation with operand b and the value in location a. i. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. . January 24.b32 only . and max operations are single-precision. . .

0.f32.add.{add. Introduced in PTX ISA version 1.[x+4]. : r-1. 2010 . atom.global. atom.b32 d.PTX ISA Version 2.global.[a]. b.my_new_val. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.{min. Use of generic addressing requires sm_20 or later.shared. d.1.f32 requires sm_20 or later.exch} requires sm_12 or later.add. atom. s) = s.cas. *a = (operation == cas) ? : } where inc(r. : r. s) = (r > s) ? s exch(r.cas. d.f32 atom.[p]. c) operation(*a. atom.shared requires sm_12 or later. Release Notes Examples @p 136 January 24. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.0.t) = (r == s) ? t operation(*a.s.my_val.max} are unimplemented. b). 64-bit atom. s) = (r >= s) ? 0 dec(r.max. atom.0 Semantics atomic { d = *a.global requires sm_11 or later.shared operations require sm_20 or later. cas(r. : r+1. 64-bit atom.s32 atom.

dec. If an address is not properly aligned. .g.u32.add.space}.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. .b32. .and. 2010 137 . dec(r. and max operations are single-precision. or [immAddr] an immediate absolute byte address. . and max. an address maps to the corresponding location in local or shared memory.min. min. s) = (r >= s) ? 0 : r+1. inc.f32 }. Within these windows.space = { . where inc(r.add. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. min. For red. Instruction Set Table 103. Addresses are zero-extended to the specified width as needed. The address must be naturally aligned to a multiple of the access size. b).s32.u32. . The floating-point add. . or by using atom. and xor. .e.inc.s32.s32. Semantics *a = operation(*a.u64 . . 32-bit operations. and stores the result of the specified operation at location a. . red{.type = { . Operand a specifies a location in the specified state space. s) = (r > s) ? s : r-1. ...b64. by inserting barriers between normal stores and reduction operations to a common address. b.op = { .or. and truncated if the register width exceeds the state space address width for the target architecture. .op.shared }. red. . max. Description // // // // . or. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. The address size may be either 32-bit or 64-bit. . .xor. accesses to local memory are illegal. In generic addressing. the resulting behavior is undefined. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.type [a]. A register containing an address may be declared as a bit-size type or integer type.max }.global. an address maps to global memory unless it falls within the local memory window or the shared memory window. perform the memory accesses using generic addressing. overwriting the original value. .u32 only .dec. min. a de-referenced register areg containing a byte address. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. The floating-point operations are add.b]. . or the instruction may fault.exch to store to locations accessed by other reduction operations.f32 Performs a reduction operation with operand b and the value in location a. . January 24. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. If no state space is given.b32 only . The integer operations are add. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The inc and dec operations return a result in the range [0.u64. Notes Operand a must reside in either the global or shared state space.f32. . i.e. e. i. .Chapter 8.u32. The bit-size operations are and.

add requires sm_12 or later.max.max} are unimplemented.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. red.and.b32 [a].add.{min.0.shared operations require sm_20 or later.add.global requires sm_11 or later red. 2010 .shared requires sm_12 or later. 64-bit red.PTX ISA Version 2.1.global. Release Notes Examples @p 138 January 24. red.my_val.global. Use of generic addressing requires sm_20 or later.f32 red. [p].s32 red.shared. red. 64-bit red.f32 requires sm_20 or later.f32.2. [x+4]. red.

pred vote. returns bitmask .uni. // get ‘ballot’ across warp January 24.uni True if source predicate has the same value in all active threads in warp. {!}a. In the ‘ballot’ form.b32 requires sm_20 or later.all True if source predicate is True for all active threads in warp. vote. vote.mode = { .2. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.none. . r1.p. 2010 139 . vote. Negating the source predicate also computes . vote requires sm_12 or later. .pred vote.all. p. {!}a. . vote.Chapter 8.q.b32 p.any. .any True if source predicate is True for some active thread in warp.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. The reduction modes are: .mode.ballot.all. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.pred d. Instruction Set Table 104. The destination predicate value is the same across all threads in the warp. where the bit position corresponds to the thread’s lane id. // ‘ballot’ form.ballot.uni. not across an entire CTA. Note that vote applies to threads in a single warp. Negate the source predicate to compute . Description Performs a reduction of the source predicate across threads in a warp.not_all.ballot.b32 d. vote.ballot.q.uni }. Negate the source predicate to compute .

bsel}. .PTX ISA Version 2.dsel = . .sat}. .sat} d. b{.btype = { .atype = . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.s34 intermediate result.btype{.s32 }.btype{.extended internally to . perform a scalar arithmetic operation to produce a signed 34-bit result.h1 }.b2.s33 values.bsel = { .dtype. . The general format of video instructions is as follows: // 32-bit scalar operation.h0.atype. a{.sat} d. Using the atype/btype and asel/bsel specifiers. vop. the input values are extracted and signor zero. The type of each operand (. 4. 2010 .bsel}. .asel}. atype.atype.asel}. half-word. 140 January 24. optionally clamp the result to the range of the destination type.bsel}.u32.dtype.s32) is specified in the instruction type. Video Instructions All video instructions operate on 32-bit register operands.secop = { . 3. . extract and sign. 2. b{. with optional secondary operation vop.asel = . // 32-bit scalar operation. The source and destination operands are all 32-bit registers. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). .b3. c. and btype are valid.b0. The primary operation is then performed to produce an .dsel. The sign of the intermediate result depends on dtype. with optional data merge vop. a{. taking into account the subword destination size in the case of optional data merging.min. all combinations of dtype. or word values from its source operands. . . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.or zero-extend byte.7. to produce signed 33-bit input values.0 8.max }.b1.u32 or .secop d. c.btype{. a{.dtype.add.atype.asel}.dtype = . b{.9. . . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.

. } } . The sign of the c operand is based on dtype. .s33 tmp. U16_MAX. tmp.s33 optMerge( Modifier dsel. S8_MIN ). .b2.s33 tmp. c). Instruction Set . tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp.h0. default: return tmp. Bool sign. . . c).b0: return ((tmp & 0xff) case . c). 2010 141 . c). U16_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. January 24. . switch ( dsel ) { case . S32_MIN ). tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.b0. .b2: return ((tmp & 0xff) << 16) case . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). as shown in the following pseudocode.s33 c) { switch ( secop ) { . c).b1. U8_MAX.add: return tmp + c. Modifier dsel ) { if ( !sat ) return tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case .Chapter 8. . U32_MAX. S16_MAX. The lower 32-bits are then written to the destination operand.s34 tmp. Bool sat. .s33 c ) switch ( dsel ) { case . S16_MIN ). U8_MIN ). S32_MAX.max return MAX(tmp.s33 optSaturate( .min: return MIN(tmp. .b1: return ((tmp & 0xff) << 8) case .h1: return ((tmp & 0xffff) << 16) case .h0: return ((tmp & 0xffff) case . . c).s33 optSecOp(Modifier secop. c). tmp. U32_MIN ). S8_MAX.

. .sat} d.b1. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.h0. r1.dsel .btype{.s32.sat vmin.dtype. // 32-bit scalar operation. r3.s32.PTX ISA Version 2. tb ).s32. vsub vabsdiff vmin.btype{.u32.asel = . vmin. dsel ).add r1. vmin. tmp = MIN( ta.vop .atype. vadd.s32. taking into account destination type and merge operations tmp = optSaturate( tmp. vmax vadd.s32. r2. Integer byte/half-word/word minimum / maximum. { .s32. b{.btype{. c ).op2 d.bsel}. . vsub.h1.dsel.s32. r1. with optional data merge vop.sat vabsdiff. r3. tb ). vabsdiff.b2.bsel = { . vmin. with optional secondary operation vop. // optional merge with c operand 142 January 24. c.b0. vabsdiff. . tmp = | ta – tb |.s32. . c ). . vsub. a{. and optional secondary arithmetic operation or subword data merge.min. sat. isSigned(dtype). c. a{. r2. // 32-bit scalar operation. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r2. tmp.dtype . tmp.s32.atype. // optional secondary operation d = optMerge( dsel. . atype.0 Table 105.max }.btype = { . vmax }.asel}.asel}.op2 Description = = = = { vadd.atype. d = optSecondaryOp( op2.b0. vmax require sm_20 or later. r1.bsel}. c.b2. . vadd.dtype. b{.add.h0.sat} d. vmax Syntax Integer byte/half-word/word addition / subtraction. . r3. bsel ). tmp = ta – tb.asel}.dtype.u32.h1 }. .s32. . r3.h1.or zero-extend based on source operand type ta = partSelectSignExtend( a. Video Instructions: vadd.u32.b0.sat}. 2010 .b3.sat.bsel}. Integer byte/half-word/word absolute value of difference. // extract byte/half-word/word and sign. Perform scalar arithmetic operation with optional saturate. tmp = MAX( ta. b{. r2. vabsdiff. btype. tb = partSelectSignExtend( b.0.atype = . vop. c. vsub. a{.s32 }.h0. asel ).sat vsub. Semantics // saturate.

. and optional secondary arithmetic operation or subword data merge. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat}{.u32{. and optional secondary arithmetic operation or subword data merge.u32{.u32. // default is . b{. .atype.dtype . January 24.bsel}.mode . vshr Syntax Integer byte/half-word/word left / right shift. c ). a{.b3. c. // optional secondary operation d = optMerge( dsel.atype = { .op2 d. { .u32{. vshl. vop. if ( mode == .dsel . Semantics // extract byte/half-word/word and sign.bsel = { .dtype.wrap }. asel ). atype. Video Instructions: vshl. vshr vshl. r1. r3. a{.vop .clamp . c ).asel}. tb = partSelectSignExtend( b. r3.clamp.b1. vshr require sm_20 or later. . isSigned(dtype).u32. vshr }.0. a{. .u32 vshr. { . switch ( vop ) { case vshl: tmp = ta << tb. with optional secondary operation vop. r2. 2010 143 .asel = . .clamp && tb > 32 ) tb = 32. r2. vshr: Shift a right by unsigned amount in b with optional saturate.dtype.s32 }. . with optional data merge vop.sat}{.h1 }.dsel.Chapter 8. bsel ). Signed shift fills with the sign bit. case vshr: tmp = ta >> tb.mode} d. . unsigned shift fills with zero.h1.u32.asel}.atype. // 32-bit scalar operation.or zero-extend based on source operand type ta = partSelectSignExtend( a. } // saturate. tmp. dsel ).bsel}.u32.b2. if ( mode == . vshl: Shift a left by unsigned amount in b with optional saturate. . Instruction Set Table 106.wrap ) tb = tb & 0x1f.op2 Description = = = = = { vshl. Left shift fills with zero. sat.max }. b{.dtype. vshl. . d = optSecondaryOp( op2.atype. .bsel}.min.wrap r1. .sat}{.s32.h0.mode} d.mode}. // 32-bit scalar operation. tmp. taking into account destination type and merge operations tmp = optSaturate( tmp.b0. .u32.add. b{.asel}.u32. c.

U32 // intermediate unsigned.0 Table 107. internally this is represented as negation of the product (a*b). The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (U32 * U32) .atype = . this result is sign-extended if the final result is signed.atype. 144 January 24.sat}{. final signed (S32 * S32) .dtype. “plus one” mode. Source operands may not be negated in . .sat}{.btype = { . the intermediate result is signed. {-}c. {-}b{. a{.bsel = { .s32 }.PTX ISA Version 2.b3. otherwise.po mode. final signed (S32 * U32) + S32 // intermediate signed.shr7..b1. That is. .asel}. final signed -(S32 * U32) + S32 // intermediate signed.atype. and the operand negates. which is used in computing averages. 2010 . . . . final signed (U32 * S32) . Although PTX syntax allows separate negation of the a and b operands.po{. . {-}a{. and scaling.scale} d. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. . Depending on the sign of the a and b operands. vmad.dtype.u32. The “plus one” mode (. PTX allows negation of either (a*b) or c. final signed -(U32 * S32) + S32 // intermediate signed. Input c has the same sign as the intermediate result. final signed (U32 * S32) + S32 // intermediate signed.scale = { .scale} d.S32 // intermediate signed.dtype = .h0. final signed The intermediate result is optionally scaled via right-shift.bsel}. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.b0.S32 // intermediate signed.bsel}. final unsigned -(U32 * U32) + S32 // intermediate signed.S32 // intermediate signed. b{. The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed -(S32 * S32) + S32 // intermediate signed. c. The source operands support optional negation with some restrictions. // 32-bit scalar operation vmad. .shr15 }.btype. final signed (S32 * U32) .btype{.b2. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.po) computes (a*b) + c + 1. .asel}. final signed (S32 * S32) + S32 // intermediate signed.h1 }. . Description Calculate (a*b) + c. (a*b) is negated if and only if exactly one of a or b is negated. and zero-extended otherwise.asel = . with optional operand negates.

po ) { lsb = 1.h0.h0.negate. Instruction Set Semantics // extract byte/half-word/word and sign. vmad requires sm_20 or later. else result = CLAMP(result.sat vmad.u32. bsel ). r2. tmp = tmp + c128 + lsb. U32_MIN). U32_MAX. btype. -r3. } if ( . lsb = 1. S32_MAX. } else if ( a. January 24. r2.shr15 r0. atype. S32_MIN).Chapter 8. r1.s32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. asel ). vmad. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 0. signedFinal = isSigned(atype) || isSigned(btype) || (a. tb = partSelectSignExtend( b.shr7: result = (tmp >> 7) & 0xffffffffffffffff.0.negate ) { tmp = ~tmp.u32. switch( scale ) { case . tmp[127:0] = ta * tb.negate ^ b. case . 2010 145 .negate ^ b. r0.u32.sat ) { if (signedFinal) result = CLAMP(result.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32. r3.negate) || c. lsb = 1. r1.shr15: result = (tmp >> 15) & 0xffffffffffffffff. } else if ( c. if ( .negate ) { c = ~c.u32.

tmp = compare( ta.max }. .asel}.bsel}. atype. . { . . with optional data merge vset. .u32.0. r3.dsel.bsel = { . r2.u32. with optional secondary arithmetic operation or subword data merge. .ge }.atype.op2 Description = = = = .b0.add. r1. . 2010 .le. a{. The intermediate result of the comparison is always unsigned.s32.b3.u32. . . tb = partSelectSignExtend( b.or zero-extend based on source operand type ta = partSelectSignExtend( a.btype = { . c. r2.dsel . { . tmp.asel}.h0.ne r1. vset requires sm_20 or later.b2.ne. bsel ).cmp . vset.asel}.cmp d. // optional secondary operation d = optMerge( dsel.lt vset.u32. .lt. // 32-bit scalar operation.atype.btype.op2 d. Compare input values using specified comparison. a{.btype. cmp ) ? 1 : 0.h1. and therefore the c operand and final result are also unsigned.gt. c ).0 Table 108. b{. r3.btype. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. 146 January 24. with optional secondary operation vset. .s32 }. Semantics // extract byte/half-word/word and sign. .min. a{.eq. b{. btype. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . c.atype.cmp d.b1. b{. . vset. .bsel}.PTX ISA Version 2.h1 }. d = optSecondaryOp( op2. // 32-bit scalar operation. tb. asel ).asel = . tmp.atype .cmp. .bsel}. c ).

there are sixteen performance monitor events.0. Instruction Set 8.7. @p pmevent 1.Chapter 8. pmevent a. trap. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. January 24.10. brkpt. trap Abort execution and generate an interrupt to the host CPU. The relationship between events and counters is programmed via API calls from the host. brkpt. brkpt requires sm_11 or later. 2010 147 . Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. numbered 0 through 15. Supported on all target architectures.4. Triggers one of a fixed number of performance monitor events. Supported on all target architectures. Notes PTX ISA Notes Target ISA Notes Examples Currently. with index specified by immediate operand a. Table 110. Introduced in PTX ISA version 1. pmevent 7. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. trap. Introduced in PTX ISA version 1. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. brkpt Suspends execution Introduced in PTX ISA version 1.0. Table 111.

2010 .PTX ISA Version 2.0 148 January 24.

read-only variables. Special Registers PTX includes a number of predefined. %pm3 January 24. …. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_le.Chapter 9. %lanemask_gt %clock. %lanemask_ge. which are visible as special registers and accessed through mov or cvt instructions. %clock64 %pm0. 2010 149 . %lanemask_lt.

Redefined as . %ntid.%ntid.z.sreg . The number of threads in each dimension are specified by the predefined special register %ntid.u16 %rh.%tid.%h1. the %tid value in unused dimensions is 0.u16 %r2. The %tid special register contains a 1D. mov.x.u32 %tid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. %ntid.y * %ntid.u32 %ntid.u32 %h2. .0. Redefined as . The total number of threads in a CTA is (%ntid. mad.u32 type in PTX 2. read-only.0. // zero-extend tid.y.v4 .%h2.u32.z.0.x < %ntid. CTA dimensions are non-zero.x code accessing 16-bit component of %tid mov. cvt.z PTX ISA Notes Introduced in PTX ISA version 1. .z to %r2 Table 113.x.z == 1 in 1D CTAs. .y.x.z < %ntid.z == 0 in 2D CTAs.0 Table 112. // legacy PTX 1. 2D.z).sreg .z == 0 in 1D CTAs.u32 %ntid.y == %ntid.x to %rh Target ISA Notes Examples // legacy PTX 1. %tid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.z.u32 %tid.v4. // compute unified thread id for 2D CTA mov. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. mov. mov.%tid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. It is guaranteed that: 0 <= %tid.u32 %r1.x 0 <= %tid.%r0.x. %ntid. %tid component values range from 0 through %ntid–1 in each CTA dimension.sreg .%tid.sreg . // CTA shape vector // CTA dimensions A predefined. per-thread special register initialized with the thread identifier within the CTA.PTX ISA Version 2. Supported on all target architectures. %tid.x.0.y. or 3D vector to match the CTA shape.%tid.x.y < %ntid. The fourth element is unused and always returns zero. // thread id vector // thread id components A predefined. PTX ISA Notes Introduced in PTX ISA version 1.u32 %r0.x * %ntid. %tid.u16 %rh.%ntid.x.u32 type in PTX 2.u32 %r0. the fourth element is unused and always returns zero.y 0 <= %tid.%tid.y == %tid. Supported on all target architectures. 2010 . read-only special register initialized with the number of thread ids in each CTA dimension. .x code Target ISA Notes Examples 150 January 24.u32 %h1.z == 1 in 2D CTAs. Every thread in the CTA has a unique %tid. mov. %ntid. // move tid.v4. %tid.v4 .

%warpid. read-only special register that returns the thread’s warp identifier.u32 %r. but its value may change during execution. Special Registers Table 114. Introduced in PTX ISA version 1. Introduced in PTX ISA version 2.Chapter 9. Table 115. PTX ISA Notes Target ISA Notes Examples Table 116.g. A predefined. . The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. January 24. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.3. %nwarpid requires sm_20 or later.u32 %warpid.sreg . Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. .u32 %laneid. . %laneid. A predefined. e. mov.0. Note that %warpid is volatile and returns the location of a thread at the moment when read.sreg . mov.sreg . The warp identifier will be the same for all threads within a single warp. due to rescheduling of threads following preemption. For this reason. 2010 151 .3. mov. read-only special register that returns the maximum number of warp identifiers. %nwarpid. A predefined. The lane identifier ranges from zero to WARP_SZ-1. Supported on all target architectures. read-only special register that returns the thread’s lane within the warp.u32 %r.u32 %nwarpid. Introduced in PTX ISA version 1.u32 %r. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Supported on all target architectures.

%nctaid.sreg .0.sreg .z.{x.sreg .v4 .x. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u32 type in PTX 2.%nctaid.x.x < %nctaid. or 3D vector. Redefined as . . read-only special register initialized with the CTA identifier within the CTA grid. The %nctaid special register contains a 3D grid shape vector. %rh. Supported on all target architectures. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.0. depending on the shape and rank of the CTA grid.x.536 PTX ISA Notes Introduced in PTX ISA version 1. 2D.0 Table 117.z PTX ISA Notes Introduced in PTX ISA version 1.v4.y.y.x code Target ISA Notes Examples Table 118. Redefined as . Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u16 %r0.%nctaid.%ctaid. .x.z. %rh. mov.u16 %r0.y 0 <= %ctaid.z < %nctaid.y. The %ctaid special register contains a 1D. // legacy PTX 1.0.0.z} < 65.sreg . // legacy PTX 1.x. // CTA id vector // CTA id components A predefined.v4.PTX ISA Version 2.%nctaid.y < %nctaid. %ctaid. The fourth element is unused and always returns zero.u32 mov.%ctaid.u32 type in PTX 2. Each vector element value is >= 0 and < 65535. It is guaranteed that: 0 <= %ctaid. mov.u32 %nctaid.u32 %ctaid.x 0 <= %ctaid. It is guaranteed that: 1 <= %nctaid. with each element having a value of at least 1.x code Target ISA Notes Examples 152 January 24. read-only special register initialized with the number of CTAs in each grid dimension.v4 . The fourth element is unused and always returns zero. .u32 %nctaid . 2010 . Supported on all target architectures.y. // Grid shape vector // Grid dimensions A predefined. %ctaid.u32 %ctaid.u32 mov. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.

repeated launches of programs may occur. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. During execution. %nsmid requires sm_20 or later. Note that %smid is volatile and returns the location of a thread at the moment when read. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Supported on all target architectures. The SM identifier numbering is not guaranteed to be contiguous. e. A predefined. PTX ISA Notes Target ISA Notes Examples January 24. mov.u32 %smid. Notes PTX ISA Notes Target ISA Notes Examples Table 120. A predefined. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.u32 %nsmid.Chapter 9. The SM identifier numbering is not guaranteed to be contiguous. Supported on all target architectures. where each launch starts a grid-of-CTAs. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Introduced in PTX ISA version 2. Introduced in PTX ISA version 1.u32 %r. Introduced in PTX ISA version 1. due to rescheduling of threads following preemption.u32 %r. %smid. but its value may change during execution.sreg . This variable provides the temporal grid launch number for this context.sreg . . 2010 153 . PTX ISA Notes Target ISA Notes Examples Table 121.u32 %gridid. read-only special register initialized with the per-grid temporal grid identifier. so %nsmid may be larger than the physical number of SMs in the device.g.u32 %r. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. read-only special register that returns the maximum number of SM identifiers. mov. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. // initialized at grid launch A predefined.0. mov.3. %nsmid. Special Registers Table 119.sreg . The SM identifier ranges from 0 to %nsmid-1. %gridid. .0. .

Table 124. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_eq. %lanemask_le requires sm_20 or later. Introduced in PTX ISA version 2. 2010 .u32 %r.u32 %r. .sreg . A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.0.0. mov. 154 January 24.u32 %lanemask_eq. %lanemask_lt.PTX ISA Version 2. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . Introduced in PTX ISA version 2. %lanemask_le. A predefined.0 Table 122.sreg . Table 123.u32 %r. . Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_lt. A predefined.0.u32 %lanemask_le. mov. %lanemask_lt requires sm_20 or later.sreg . mov. Introduced in PTX ISA version 2. %lanemask_eq requires sm_20 or later.

Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.Chapter 9.0. . Special Registers Table 125.u32 %lanemask_gt. A predefined. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2.u32 %r.sreg . %lanemask_ge. %lanemask_ge requires sm_20 or later. 2010 155 . January 24. mov.u32 %lanemask_ge.0. A predefined. %lanemask_gt requires sm_20 or later. %lanemask_gt. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. . read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. Table 126. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg .u32 %r.

%pm1.PTX ISA Version 2. . mov. Special registers %pm0.sreg . Table 129.u32 r1.sreg . Table 128. mov.u32 r1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm2. %pm1.u64 r1. and %pm3 are unsigned 32-bit read-only performance monitor counters. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.%pm0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Supported on all target architectures. .sreg . %pm2. Supported on all target architectures. read-only 32-bit unsigned cycle counter. 2010 . read-only 64-bit unsigned cycle counter.u64 %clock64.0.%clock.u32 %clock.0 Table 127. 156 January 24. %pm1.%clock64. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.3. %clock64 requires sm_20 or later. Introduced in PTX ISA version 2. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Introduced in PTX ISA version 1. Their behavior is currently undefined. Special Registers: %pm0. mov.u32 %pm0.0. . Introduced in PTX ISA version 1. %pm2. %pm3 %pm0. The lower 32-bits of %clock64 are identical to %clock. …. %pm3.

version . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX File Directives: .version .version major.version 1. 2010 157 . .1.version directives are allowed provided they match the original . and the target architecture for which the code was generated.0. Each ptx file must begin with a . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.Chapter 10.version 2.4 January 24. Duplicate .version Syntax Description Semantics PTX version number. Directives 10.minor // major. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directive. .0 . minor are integers Specifies the PTX language version number. . Supported on all target architectures. Increments to the major number indicate incompatible changes to PTX.version directive.target Table 130.

Therefore.texref and . generations of SM architectures follow an “onion layer” model. PTX File Directives: . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. but subsequent .texref descriptor.f64 instructions used. Adds double-precision support. 64-bit {atom. sm_12. and an error is generated if an unsupported feature is used. texture and sampler information is referenced with independent . map_f64_to_f32 }.f32.f64 instructions used.target directive specifies a single target architecture.texmode_unified) .target directives can be used to change the set of target features allowed during parsing. with only half being used by instructions converted from .target Syntax Architecture and Platform target. sm_11. vote instructions. PTX code generated for a given target can be run on later generation devices. sm_10.shared.target directive containing a target architecture and optional platform options. Adds {atom. brkpt instructions. Requires map_f64_to_f32 if any . The following table summarizes the features in PTX that vary according to target architecture.texmode_unified .red}. texmode_unified. Supported on all target architectures. Texturing mode: (default is .5. including expanded rounding modifiers.f64 to . sm_13.0 Table 131. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.version directive. where each generation adds new features and retains all features of previous generations. Adds {atom.PTX ISA Version 2. Requires map_f64_to_f32 if any .target . A . immediately followed by a .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Requires map_f64_to_f32 if any . Description Specifies the set of features in the target architecture for which the current ptx code was generated.global. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.0.red}. PTX features are checked against the specified target architecture. Texturing mode introduced in PTX ISA version 1. 158 January 24. Note that . Target sm_20 Description Baseline feature set for sm_20 architecture.texmode_independent texture and sampler information is bound together and accessed via a single . texmode_independent. 2010 .f64 instructions used. The texturing mode is specified for an entire module and cannot be changed within the module. Disallows use of map_f64_to_f32. In general.samplerref descriptors. A program with multiple . .red}.global. Each PTX file must begin with a .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 storage remains as 64-bits.

Directives Examples . 2010 159 .target sm_13 // supports double-precision . texmode_independent January 24.target sm_10 // baseline target architecture .Chapter 10.target sm_20.

opaque .texref.param instructions.3. .param .param.param. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. Parameters are passed via .entry cta_fft .b32 %r3.entry kernel-name kernel-body Defines a kernel entry point name. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. and body for the kernel function. In addition to normal parameters. PTX ISA Notes For PTX ISA version 1. . with optional parameters.entry Syntax Description Kernel entry point and body.PTX ISA Version 2.0 through 1. . . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. etc. ld. 160 January 24. For PTX ISA versions 1. and .2. parameter variables are declared in the kernel parameter list.samplerref. Supported on all target architectures. 2010 . Parameters may be referenced by name within the kernel body and loaded into registers using ld.param. parameters.param space memory and are listed within an optional parenthesized parameter list.4.5 and later.entry . The shape and size of the CTA executing the kernel are available in special registers. e.entry filter ( . store.b32 x. . ld.b32 %r<99>. Kernel and Function Directives: . %ntid. ld. and query instructions and cannot be accessed via ld. %nctaid. parameter variables are declared in the kernel body.func Table 132.entry kernel-name ( param-list ) kernel-body .param { .surfref variables may be passed as parameters. [z]. … } .b32 %r1.0 10. These parameters can only be referenced by name within texture and surface load.g.b32 z ) Target ISA Notes Examples [x]. the kernel dimensions and properties are established and made available via special registers.reg .4 and later.param . .b32 y. [y].0 through 1.entry . At kernel launch. Semantics Specify the entry point for a kernel program.param instructions.b32 %r2.

Semantics The PTX syntax hides all details of the underlying calling convention and ABI.func Syntax Function definition.func . Release Notes For PTX ISA version 1. Variadic functions are represented using ellipsis following the last fixed argument.2 for a description of variadic functions.func (ret-param) fname (param-list) function-body Defines a function. parameters must be in the register state space. Kernel and Function Directives: . Variadic functions are currently unimplemented.0 with target sm_20 allows parameters in the . A .Chapter 10. foo.func definition with no body provides a function prototype. and supports recursion. 2010 161 . including input and return parameters and optional function body.param space are accessed using ld. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.b32 localVar. (val0.b32 rval.b32 rval) foo (.func fname function-body . Supported on all target architectures. val1). PTX ISA 2. there is no stack. Parameter passing is call-by-value.b32 N.0 with target sm_20 supports at most one return value.func fname (param-list) function-body . other code. Parameters in .x code.param and st. . } … call (fooval). The parameter lists define locally-scoped variables in the function body. mov. PTX 2. which may use a combination of registers and stack locations to pass parameters. if any.reg .f64 dbl) { . implements an ABI with stack. … use N. Directives Table 133. ret.param state space. dbl.reg .func (.reg . .param instructions in the body. Parameters in register state space may be referenced directly within instructions in the function body. … Description // return value in fooval January 24. The implementation of parameter passing is left to the optimizing translator. Parameters must be base types in either the register or parameter state space. and recursion is illegal. .reg . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.result.

to throttle the resource requirements (e.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. at entry-scope.pragma directives may appear at module (file) scope. the . for example.maxntid.g. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. the .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxnreg. The directives take precedence over any module-level constraints passed to the optimizing backend.maxntid and . The . .maxnctapersm (deprecated) . . The interpretation of . registers) to increase total thread count and provide a greater opportunity to hide memory latency.3.maxnreg . Note that .minnctapersm directives may be applied per-entry and must appear between an .maxntid directive specifies the maximum number of threads in a thread block (CTA). or as statements within a kernel or device function body. and the strings have no semantics within the PTX virtual machine model.0 10.pragma The . Performance-Tuning Directives To provide a mechanism for low-level performance tuning.pragma directive is supported for passing information to the PTX backend. These can be used. and the . PTX supports the following directives.entry directive and its body. which pass information to the backend optimizing compiler.maxntid . and .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. A general . 162 January 24.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).minnctapersm .PTX ISA Version 2. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. Currently. 2010 . The directive passes a list of strings to the backend.

3. . for example. .maxntid 16.16.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. 2D.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxnreg . nz Declare the maximum number of threads in the thread block (CTA). The maximum number of threads is the product of the maximum extent in each dimension.entry foo .Chapter 10.maxctapersm. Performance-Tuning Directives: . The compiler guarantees that this limit will not be exceeded.maxntid nx. Exceeding any of these limits results in a runtime error or kernel launch failure. .maxntid Syntax Maximum number of threads in thread block (CTA).entry foo . the backend may be able to compile to fewer registers.3. Supported on all target architectures. Supported on all target architectures.maxntid and .maxntid nx. ny.entry bar . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxnreg n Declare the maximum number of registers per thread in a CTA. The actual number of registers used may be less.maxntid 256 .maxntid nx . Performance-Tuning Directives: . Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Directives Table 134. ny .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. or 3D CTA. 2010 163 .maxntid . . or the maximum number of registers may be further constrained by .

. Introduced in PTX ISA version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Performance-Tuning Directives: . For this reason.0.maxntid 256 .minnctapersm 4 { … } 164 January 24. Supported on all target architectures. . Deprecated in PTX ISA version 2.0. Supported on all target architectures.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0 Table 136.maxnctapersm (deprecated) .minnctapersm . .maxntid and . .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. However.maxntid to be specified as well.entry foo .maxnctapersm generally need .maxnctapersm.minnctapersm in PTX ISA version 2.PTX ISA Version 2. Optimizations based on .minnctapersm generally need .0 as a replacement for .3. if the number of registers used by the backend is sufficiently lower than this bound. . Optimizations based on . Introduced in PTX ISA version 1.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. The optimizing backend compiler uses .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Performance-Tuning Directives: .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. 2010 .maxnctapersm has been renamed to .maxntid to be specified as well. additional CTAs may be mapped to a single multiprocessor.maxntid 256 .entry foo .

pragma Syntax Description Pass directives to PTX backend compiler.pragma “nounroll”. The interpretation of .pragma . or statement-level directives to the PTX backend compiler.0. . Directives Table 138. 2010 165 . entry-scoped. Performance-Tuning Directives: . { … } January 24.pragma list-of-strings . or at statementlevel. Introduced in PTX ISA version 2. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma directive may occur at module-scope. Pass module-scoped. The . .pragma directive strings is implementation-specific and has no impact on PTX semantics. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Supported on all target architectures.Chapter 10. at entry-scope.entry foo .pragma “nounroll”.

@@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x6150736f. 0x61395a5f.loc The .PTX ISA Version 2.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00.4byte 0x000006b5. 2010 . 0x02.section . 0x5f736f63 .section directive. 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0.debug_pubnames. 0x00.4.4byte . The @@DWARF syntax is deprecated as of PTX version 2.file .2. 0x00000364.byte byte-list // comma-separated hexadecimal byte values . Supported on all target architectures. Deprecated as of PTX 2..232-1] .byte 0x2b. 0x00.4byte label .0.section .byte 0x00. Table 139. @@DWARF dwarf-string dwarf-string may have one of the .quad int64-list // comma-separated hexadecimal integers in range [0.0 10. “”.0 and replaces the @@DWARF syntax.section directive is new in PTX ISA verison 2. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.debug_info . 0x00 166 January 24. 0x00.4byte 0x6e69616d. 0x00 .0 but is supported for legacy PTX version 1.264-1] .. @progbits . 0x736d6172 . 0x63613031.x code. replaced by . Introduced in PTX ISA version 1.

Supported on all target architectures.b32 label .b32 int32-list // comma-separated list of integers in range [0.b8 0x00.section . 0x00. Supported on all target architectures.section Syntax PTX section definition. Debugging Directives: .b8 0x2b. .loc line_number January 24. .Chapter 10.section section_name { dwarf-lines } dwarf-lines have the following formats: . } 0x02. 0x00. 0x00 0x61395a5f. Source file location. 0x736d6172 0x00 Table 141.0. .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Debugging Directives: .file . 0x00. . .b8 byte-list // comma-separated list of integers in range [0.b32 . 0x00. Source file information.b32 0x6e69616d.0.file filename Table 142. Supported on all target architectures.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x63613031.232-1] .debug_info ..b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b64 int64-list // comma-separated list of integers in range [0. 0x00..debug_pubnames { .264-1] . Debugging Directives: . . 0x00.0.loc .255] . 0x5f736f63 0x6150736f. 0x00000364. Directives Table 140.section . 2010 167 . .. replaces @@DWARF syntax.b32 0x000006b5.

global .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.global . .visible identifier Declares identifier to be externally visible.extern .6. .extern . Introduced in PTX ISA version 1. .extern identifier Declares identifier to be defined externally.0 10.PTX ISA Version 2. // foo is defined in another module Table 144. Supported on all target architectures.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern . . Introduced in PTX ISA version 1.visible Table 143.visible . Linking Directives: .b32 foo. Linking Directives: .0. 2010 .visible . Supported on all target architectures. // foo will be externally visible 168 January 24.0.b32 foo. Linking Directives .

0 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation. and the remaining sections provide a record of changes in previous releases.2 CUDA 2.5 PTX ISA 2.0 driver r195 PTX ISA Version PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 CUDA 2. The release history is as follows. 2010 169 .0 January 24.4 PTX ISA 1.3 driver r190 CUDA 3.2 PTX ISA 1.3 PTX ISA 1.1 CUDA 2. CUDA Release CUDA 1.1 PTX ISA 1.1 CUDA 2.0.Chapter 11.0 CUDA 1.

rcp. and mul now support . and sqrt with IEEE 754 compliant rounding have been added. 2010 .PTX ISA Version 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices. The mad.f32 maps to fma.1.f32 require a rounding modifier for sm_20 targets. New Features 11. These are indicated by the use of a rounding modifier and require sm_20.ftz modifier may be used to enforce backward compatibility with sm_1x. The . A single-precision fused multiply-add (fma) instruction has been added.rm and . The goal is to achieve IEEE 754 compliance wherever possible.1.1. Instructions testp and copysign have been added. mad. sub.1.f32 instruction also supports .f32 requires sm_20. Changes in Version 2.rn.rp rounding modifiers for sm_20 targets.1.0 for sm_20 targets. • • • • • 170 January 24. fma.0 11. while maximizing backward compatibility with legacy PTX 1. Both fma. The changes from PTX ISA 1.f32 and mad. Single-precision add.sat modifiers. The fma.f32 for sm_20 targets. Floating-Point Extensions This section describes the floating-point changes in PTX 2.and double-precision div. The mad.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32.x code and sm_1x targets. Single.ftz and .0 11.1.

cvta.section.3. local.u32 and bar.clamp and . A “find leading non-sign bit” instruction. A “vote ballot” instruction.1. prefetch. suld.clamp modifiers.maxnctapersm directive was deprecated and replaced with . has been added. Instruction cvta for converting global. membar.pred have been added.popc. and sust. popc. ldu. Cache operations have been added to instructions ld. A “bit reversal” instruction. A “count leading zeros” instruction. and shared addresses to generic address and vice-versa has been added. e.{and.or}. st. prefetchu. Instructions {atom. Video instructions (includes prmt) have been added. Instructions prefetch and prefetchu have also been added.red}. %clock64. has been added. . has been added.shared have been extended to handle 64-bit data types for sm_20 targets. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. The . bar now supports optional thread count and register operands. clz. Bit field extract and insert instructions. Release Notes 11.sys.1. has been added. vote. .le.f32 have been implemented. A “population count” instruction. has been added. Instruction sust now supports formatted surface stores. and red now support generic addressing. isspacep. atom. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A new directive. January 24.lt. have been added.minnctapersm to better match its behavior and usage. New instructions A “load uniform” instruction. A system-level membar instruction.arrive instruction has been added.b32. Instructions {atom. The bar instruction has been extended as follows: • • • A bar. ldu.add. %lanemask_{eq. New special registers %nsmid. Other new features Instructions ld.1.1. 11. Instructions bar.gt} have been added.2.red}. brev.zero. has been added. Surface instructions support additional . st.g. bfe and bfi.Chapter 11. has been added.ballot. bfind. 2010 171 . for prefetching to specified level of memory hierarchy.ge.red.red.

u32. The underlying.target sm_1x. stack-based ABI is unimplemented.5 and later. cvt.4 and earlier.PTX ISA Version 2.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. .f32} atom. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.4 or earlier.5. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. the correct number is sixteen. Semantic Changes and Clarifications The errata in cvt. Instruction bra.{min.3.s32.{u32.version is 1. Formatted surface load is unimplemented. where . In PTX version 1.f32.0 11. 11. Support for variadic functions and alloca are unimplemented.1. 2010 . if .max} are not implemented.p.f32 type is unimplemented.ftz (and cvt for . Formatted surface store with . or .1.red}. has been fixed. 172 January 24.p sust. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. See individual instruction descriptions for details.s32. {atom. To maintain compatibility with legacy PTX code.2. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.ftz for PTX ISA versions 1. call suld. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.

2010 173 . Ignored for sm_1x targets. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Note that in order to have the desired effect at statement level. . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. L1_end: … } // do not unroll this loop January 24.func bar (…) { … L1_head: . Supported only for sm_20 targets. and statement levels. Descriptions of .pragma “nounroll”.entry foo (…) .pragma. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. … @p bra L1_end. L1_body: … L1_continue: bra L1_head. Table 145. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. { … } // do not unroll any loop in this function . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma “nounroll”. disables unrolling for all loops in the entry function body. entry-function.0.Appendix A. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.pragma Strings This section describes the . disables unrolling of0 the loop for which the current block is the loop header. . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma “nounroll”. including loops preceding the .pragma strings defined by ptxas. The “nounroll” pragma is allowed at module.

PTX ISA Version 2. 2010 .0 174 January 24.

However. DRAWINGS. CUDA. No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation. All rights reserved.Notice ALL NVIDIA DESIGN SPECIFICATIONS. Other company and product names may be trademarks of the respective companies with which they are associated. STATUTORY. Specifications mentioned in this publication are subject to change without notice. Trademarks NVIDIA. the NVIDIA logo. This publication supersedes and replaces all information previously supplied. EXPRESSED. NVIDIA Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation. LISTS. MERCHANTABILITY. OR OTHERWISE WITH RESPECT TO THE MATERIALS. DIAGNOSTICS. REFERENCE BOARDS. and Tesla are trademarks or registered trademarks of NVIDIA Corporation in the United States and other countries. NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use. Copyright © 2010 NVIDIA Corporation. AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT.” NVIDIA MAKES NO WARRANTIES. AND FITNESS FOR A PARTICULAR PURPOSE. . Information furnished is believed to be accurate and reliable. AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY. “MATERIALS”) ARE BEING PROVIDED “AS IS. IMPLIED. FILES.

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