NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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..2.......................................................................................4.............................. 43 6................................. 2010 ............ 6.............. 37 Array Declarations ........ 33 Fundamental Types ..................................1.........................4............................. 5.................................. 6......4...4............................... 5......6..................... 41 Source Operands. 43 Vectors as Operands ...............................1........ 5............ 42 Arrays as Operands ............................... 29 Local State Space .........................................4............. 5.................................................... 44 Scalar Conversions ....................... 42 Addresses as Operands ...................5..............................1......4.... 33 5.................. 5.. and Vectors ........................ Sampler...............4.. 28 Constant State Space ........6....... 43 Labels and Function Names as Operands ...............................................................................1....5...... 49 ii January 24..................3....................................................1............... Chapter 6.......................................................... 49 7.. 6... 27 5............ 38 Alignment ............................1................................................... 6........... 5.......................... 41 Destination Operands .................4.......................... and Variables .......................6.........1............ Types ..........................................................................4........... 6....... Instruction Operands............................. 41 Using Addresses.......5...........................................4............................ 5...........1......2........... 5.....0 4............ 25 Chapter 5.................4.......................................... 6........1............................. 37 Vectors ..........................1...................................................... 34 Variables .................................................. Texture..................1............... 28 Special Register State Space ...................1..........5.............................................................................4......................... Types.................................... 5.................................1............................................................................. 33 Restricted Use of Sub-Word Sizes ....................................................................................................................................... 44 Rounding Modifiers ...........................5............................................ 5.. 46 6................... Operand Type Information ..... 39 5................ Abstracting the ABI ........... 29 Parameter State Space ...........................................................8..... 38 Initializers .......................2.........................4............ Function declarations and definitions .....1...................................................................................5......................................................................PTX ISA Version 2....... 27 Register State Space ..................3........... 32 Texture State Space (deprecated) ..2...........................2..............................................3........4...................................3............. 41 6...... State Spaces ............. 29 Global State Space ...............................................2.......... 6...........................6............................................... 47 Chapter 7...............................................................................................1............... 5.......3.... 32 5.......1............4......................................... 5.........................................2.....................................2................. 30 Shared State Space................. State Spaces....7........ 5...................................................... 5.................. Operand Costs .......2................ 6............... 5...... Arrays....................................... and Surface Types ........ Type Conversion................................................................................................. 6.............. 39 Parameterized Variable Names .................................... 37 Variable Declarations ............. Summary of Constant Expression Evaluation Rules .............................. 5........................

. Divergence of Threads in Control Constructs ..................7..................................... 55 PTX Instructions .1........................................6..............1..............7.............................................................................1..... 55 Predicated Execution .................................................1..........7................................................3................... 8....... 8... 8.............................. 52 Variadic functions ................ 10.......................4.......... 172 Unimplemented Features Remaining .. 169 11................... 8.... Release Notes .............................. PTX Version and Target Directives ............... 8......................................... 8......... 8..............................1........................................................ 168 Chapter 11........................................................ 57 Manipulating Predicates .... 62 8............................... 56 Comparisons .. 8...................... 11........ 157 Specifying Kernel Entry Points and Functions ...................................... 11....................................1....................................1................. Changes from PTX 1................................2...........2...........................................................2.8..................................................... 157 10......................................... 63 Floating-Point Instructions .......................................... 54 Chapter 8...3.................6.........2.............. 58 8......................7.......... 162 Debugging Directives .............................. 7... 8........................... 147 8.......................................................................................3............. 60 8........................ Instruction Set ......... Special Registers ..................9................................ 149 Chapter 10......................... 59 Operand Size Exceeding Instruction-Type Size ..... 172 January 24........................ 132 Video Instructions .........................................................2......... 10......... 63 Integer Arithmetic Instructions ..7.....7............................................2......................4.................... Instructions .6............................................................................................................................7.10..................................................... 8...........................1................................ 170 Semantic Changes and Clarifications ......................... Format and Semantics of Instruction Descriptions ...................................... 166 Linking Directives .. 8..........................6......................................................7......................7............................................ 8......1......................... 10...................................................5................ 7.......................................4..7....1............. Directives .................................... Changes in Version 2.. 160 Performance-Tuning Directives ................ 108 Texture and Surface Instructions .... 100 Logic and Shift Instructions ... 140 Miscellaneous Instructions............ Type Information for Instructions and Operands ............................ 81 Comparison and Selection Instructions ......................0 .. 8...................7............................... 104 Data Movement and Conversion Instructions ................ 55 8. 122 Control Flow Instructions ................................................7...................................7. 129 Parallel Synchronization and Communication Instructions ........................................... 62 Machine-Specific Semantics of 16-bit Code ......................................................... 8...............1....................5.............................................................................................x ....................3............ 8................ 8......................3............................. 2010 iii .4................... 170 New Features .........3.......... 53 Alloca ......................................................... Chapter 9..................1.......................3.............................................................. 62 Semantics ...... 10............1........ 11...........................................................................

. Descriptions of ................pragma Strings........................PTX ISA Version 2.. 2010 ......0 Appendix A......... 173 iv January 24..........

.. Unsigned Integer..................... 2010 v ....... 47 Operators for Signed Integer.. PTX Directives ....................................... 66 Integer Arithmetic Instructions: subc ......................................... 33 Opaque Type Fields in Unified Texture Mode ............................................................. 65 Integer Arithmetic Instructions: sub................ Table 28.............................. Table 14................................. 61 Integer Arithmetic Instructions: add .............................................................. Table 21......... 68 Integer Arithmetic Instructions: mul24 .......... Table 22............................................................................ 46 Integer Rounding Modifiers .................... Table 30............. 23 Constant Expression Evaluation Rules .. 58 Type Checking Rules ................................................................................................... 27 Properties of State Spaces .................... Table 31.. 70 Integer Arithmetic Instructions: sad ....................... 35 Convert Instruction Precision and Format ....... Table 4............. Table 3........................ Table 17..................... 19 Predefined Identifiers ........................................cc ......... 18 Reserved Instruction Keywords ......................................................................... 64 Integer Arithmetic Instructions: add...... Table 6.......................... Table 18.................................. Table 23......................................................................................... Table 8.................. 46 Cost Estimates for Accessing State-Spaces ......... 67 Integer Arithmetic Instructions: mad ........................................................ 69 Integer Arithmetic Instructions: mad24 ................. Table 5............................. 35 Opaque Type Fields in Independent Texture Mode ............ Table 24............................ 65 Integer Arithmetic Instructions: addc ............................................... 57 Floating-Point Comparison Operators . 71 January 24........................... 57 Floating-Point Comparison Operators Accepting NaN ........ 60 Relaxed Type-checking Rules for Destination Operands....................... 66 Integer Arithmetic Instructions: mul ............................................................................................................................... and Bit-Size Types ................................................. 45 Floating-Point Rounding Modifiers .................................... 28 Fundamental Type Specifiers ......................................................... 25 State Spaces .......... 20 Operator Precedence ..................cc ............................................. Table 10................................................. Table 29.......... Table 25...............................List of Tables Table 1..................................................................................... Table 27... Table 26......................................... Table 19...................... Table 12........................................................................................................ Table 2................................................................ 64 Integer Arithmetic Instructions: sub ............................................................. Table 16............................... Table 15................ Table 9. Table 32.................................. Table 11.................................................................................................................. Table 13.............................. Table 20................ 59 Relaxed Type-checking Rules for Source Operands . Table 7............. 58 Floating-Point Comparison Operators Testing for NaN .........................................................

.. 93 Floating-Point Instructions: sqrt ................. 96 Floating-Point Instructions: cos .................. 92 Floating-Point Instructions: max ................................................... 79 Summary of Floating-Point Instructions ................... Table 39.............. Table 38................................ 75 Integer Arithmetic Instructions: brev ................................... Table 68................................................................... 85 Floating-Point Instructions: mul .............................. 73 Integer Arithmetic Instructions: popc ........................ 90 Floating-Point Instructions: abs ......................................................... Table 63.............................................................. Table 44...... Table 65.................... 2010 ........................... Table 35....... Table 64............................................................................................................................ 83 Floating-Point Instructions: copysign ........................................... Table 46............. 99 Comparison and Selection Instructions: set ....................................................... 91 Floating-Point Instructions: min ...... Table 66................. Table 37........ Table 41............................. Table 61............... Table 67.......................... Integer Arithmetic Instructions: div .. 71 Integer Arithmetic Instructions: rem ........................... Table 52.... Table 49...... Table 58................................................................... 74 Integer Arithmetic Instructions: bfind ......... 78 Integer Arithmetic Instructions: prmt ................................................... 102 Comparison and Selection Instructions: selp ..............0 Table 33.................................... Table 69.. Table 43................ 83 Floating-Point Instructions: add ........................ Table 48.................................... Table 50............................. Table 34......................................................................................... 92 Floating-Point Instructions: rcp ...................................................................................................... 91 Floating-Point Instructions: neg ..................................................................... 84 Floating-Point Instructions: sub .......................................................... Table 62........................... 76 Integer Arithmetic Instructions: bfe ....... 101 Comparison and Selection Instructions: setp ................................................... Table 60...... 88 Floating-Point Instructions: div ..................................... Table 56................................................... 72 Integer Arithmetic Instructions: neg .................................................................... Table 53............... Table 59.............................................. 86 Floating-Point Instructions: fma ...... 95 Floating-Point Instructions: sin .................................................. 103 Comparison and Selection Instructions: slct .............................. Table 47............................ Table 57.......................................................................... 74 Integer Arithmetic Instructions: clz ......................................................................................................... 94 Floating-Point Instructions: rsqrt ............. 71 Integer Arithmetic Instructions: abs ......................... Table 54.................................................................................... 77 Integer Arithmetic Instructions: bfi ..................... Table 55............................... 82 Floating-Point Instructions: testp ................... Table 42........................................................ 98 Floating-Point Instructions: ex2 .........PTX ISA Version 2............................................................................................................................................... 87 Floating-Point Instructions: mad ................................................................................................................................... 73 Integer Arithmetic Instructions: max . 103 vi January 24........................................................................ Table 40................... Table 36...... 72 Integer Arithmetic Instructions: min ................ 97 Floating-Point Instructions: lg2 ..................................................... Table 45................................... Table 51............

....... Table 86..................... 110 Data Movement and Conversion Instructions: mov ...................... 131 Parallel Synchronization and Communication Instructions: bar ........ 139 Video Instructions: vadd.... 135 Parallel Synchronization and Communication Instructions: red ............. 107 Logic and Shift Instructions: shr ....................... 113 Data Movement and Conversion Instructions: ldu ......................................................... vmin........................................................ 106 Logic and Shift Instructions: cnot ................................ Table 74.............................. Table 92.... 129 Control Flow Instructions: @ ......... Table 85................. Table 81.................................. Logic and Shift Instructions: and ............................................... 137 Parallel Synchronization and Communication Instructions: vote ....................................................... Table 106................................................................................................ Table 95....................................... Table 72... 106 Logic and Shift Instructions: shl .......... Table 84.................................................................................................................................. Table 96........................ vsub........ Table 83.............................. 105 Logic and Shift Instructions: xor ................................................... Table 87...... 123 Texture and Surface Instructions: txq ................... 143 January 24.......................... Table 77............. 131 Control Flow Instructions: exit ... Table 73.......................... 134 Parallel Synchronization and Communication Instructions: atom ........................................... Table 79. Table 76................................... Table 93..... 118 Data Movement and Conversion Instructions: isspacep ............................................. 130 Control Flow Instructions: call ............................. Table 102.......... vshr . Table 103..................................Table 70............................................................................... 142 Video Instructions: vshl..................... 116 Data Movement and Conversion Instructions: prefetch....... 127 Texture and Surface Instructions: suq ........... 130 Control Flow Instructions: ret ................................................... vmax ....................................... 126 Texture and Surface Instructions: sured............. prefetchu ................... Table 91....................................................................... Table 90. 2010 vii .......................... Table 88...................................... 115 Data Movement and Conversion Instructions: st ........................... Table 98....................... 119 Data Movement and Conversion Instructions: cvta .. Table 101............................................... Table 89.................. 112 Data Movement and Conversion Instructions: ld ...................................... 109 Cache Operators for Memory Store Instructions ................... 124 Texture and Surface Instructions: suld .................... vabsdiff......... 107 Cache Operators for Memory Load Instructions ..................... Table 99.. 106 Logic and Shift Instructions: not .... Table 78.................. 133 Parallel Synchronization and Communication Instructions: membar .................... Table 97................................................................. Table 80...................... Table 100.... Table 94............................................................ 129 Control Flow Instructions: bra ................................................... Table 104..... Table 75.................................... Table 71......... Table 105.......................... 125 Texture and Surface Instructions: sust ........... 128 Control Flow Instructions: { } ............................ 105 Logic and Shift Instructions: or ............................... 111 Data Movement and Conversion Instructions: mov ......................... Table 82............. 119 Data Movement and Conversion Instructions: cvt ................. 120 Texture and Surface Instructions: tex ........................................................

...... Table 109................... 167 Debugging Directives: ............................................................ Table 133..................... Table 115................... Table 140................ Table 112................ 147 Miscellaneous Instructions: pmevent...................... %pm1................... Table 117. 150 Special Registers: %laneid ......................loc .................. 163 Performance-Tuning Directives: ...................................................................... Table 111......................................................... 144 Video Instructions: vset................ Table 129....................... 158 Kernel and Function Directives: .....entry................................... Table 138........................................................... Table 123.......................... Table 141........ Table 131............................. Table 116.................... Table 126...................................................... Table 113............. Table 124.........maxntid ........................... Table 136..................... 161 Performance-Tuning Directives: ................. Table 120......... 151 Special Registers: %warpid ...................................................... Table 125.................. Table 121............... 146 Miscellaneous Instructions: trap .............. Table 130.......................................................................... 157 PTX File Directives: .................................................................................. Table 128............ Table 110.................................................................... 167 Debugging Directives: ......... Table 142........................ 147 Miscellaneous Instructions: brkpt .................................................func ....................................................................... 153 Special Registers: %nsmid ....... Table 127................... Table 134..................................... 2010 ..................... 156 Special Registers: %clock64 ....... Table 137................................................................... 164 Performance-Tuning Directives: .......................................... 152 Special Registers: %nctaid .................................maxnreg ................................. 164 Performance-Tuning Directives: ......... 150 Special Registers: %ntid .............. Table 135...................... 155 Special Registers: %clock .....0 Table 107........ 154 Special Registers: %lanemask_lt ............................. 151 Special Registers: %ctaid .......................................... Table 139.................................................................... 153 Special Registers: %lanemask_eq ........ 154 Special Registers: %lanemask_ge ........ Table 108....... 152 Special Registers: %smid ...................................minnctapersm ...........PTX ISA Version 2...................................................................................file .........................pragma ........ 163 Performance-Tuning Directives: ................................ 156 PTX File Directives: ....................................................................... 155 Special Registers: %lanemask_gt ......................................................................... Table 114.....................extern....................maxnctapersm (deprecated) .................... 166 Debugging Directives: ..............version....section ...... Table 118.................................................................................... 154 Special Registers: %lanemask_le .............. %pm3 ................................................................................................................................................................................................................... 151 Special Registers: %nwarpid ... %pm2.....................target .............. Table 119...... 168 viii January 24........................ 165 Debugging Directives: @@DWARF ...... 156 Special Registers: %pm0.......................................................... 167 Linking Directives: ......... Table 143...... 147 Special Registers: %tid ..... 153 Special Registers: %gridid ........ 160 Kernel and Function Directives: .......... Table 132...................................................................... Video Instructions: vmad ............................................... Table 122........

.....................visible................. 168 Pragma Strings: “nounroll” ........ 2010 ix ............................ Table 145. 173 January 24........................Table 144.......................................... Linking Directives: ..............................

2010 .PTX ISA Version 2.0 x January 24.

video encoding and decoding. PTX programs are translated at install time to the target hardware instruction set. which are optimized for and translated to native target-architecture instructions. Similarly. image and media processing applications such as post-processing of rendered images. PTX exposes the GPU as a data-parallel computing device.1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. from general signal processing or physics simulation to computational finance or computational biology. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. many-core processor with tremendous computational horsepower and very high memory bandwidth. 1.Chapter 1. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Introduction This document describes PTX. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. Because the same program is executed for each data element. multithreaded. and because it is executed on many data elements and has high arithmetic intensity. the memory access latency can be hidden with calculations instead of big data caches.2. In fact. there is a lower requirement for sophisticated flow control. January 24. 1. 2010 1 . The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Data-parallel processing maps data elements to parallel processing threads. stereo vision. the programmable GPU has evolved into a highly parallel. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. image scaling. high-definition 3D graphics. PTX defines a virtual machine and ISA for general purpose parallel thread execution. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. and pattern recognition can map image blocks and pixels to parallel processing threads.

3. A single-precision fused multiply-add (fma) instruction has been added.f32 and mad.x features are supported on the new sm_20 target. addition of generic addressing to facilitate the use of general-purpose pointers. which map PTX to specific target machines. fma. PTX 2. PTX ISA Version 2. mad.ftz and . • • • 2 January 24. and all PTX 1. Improved Floating-Point Support A main area of change in PTX 2. A “flush-to-zero” (.f32 requires sm_20. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. The mad. Provide a common source-level ISA for optimizing code generators and translators. Both fma.0 are improved support for IEEE 754 floating-point operations.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. sub. 1. and architecture tests. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.0 PTX ISA Version 2.0 is in improved support for the IEEE 754 floating-point standard. 2010 .f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.3.f32 maps to fma. Facilitate hand-coding of libraries.PTX ISA Version 2.rp rounding modifiers for sm_20 targets. Provide a machine-independent ISA for C/C++ and other compilers to target. performance kernels. barrier.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. When code compiled for sm_1x is executed on sm_20 devices. and video instructions. and the introduction of many new instructions. atomic.sat modifiers. The fma.x code will continue to run on sm_1x targets as well. Most of the new features require a sm_20 target. The main areas of change in PTX 2. Instructions marked with .1. Provide a code distribution ISA for application and middleware developers.f32 require a rounding modifier for sm_20 targets.ftz) modifier may be used to enforce backward compatibility with sm_1x. including integer.rn. Single-precision add.f32 for sm_20 targets. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.x. 1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. memory.f32 instruction also supports . Achieve performance in compiled applications comparable to native GPU performance.f32.rm and .ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. surface.0 is a superset of PTX 1. The changes from PTX ISA 1. reduction. Legacy PTX 1. and mul now support . The mad.

. prefetch. instructions ld. 1. and Application Binary Interface (ABI). • Taken as a whole. isspacep.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. In PTX 2.0.0. allowing memory instructions to access these spaces without needing to specify the state space.3. cvta. so recursion is not yet supported.Chapter 1. These are indicated by the use of a rounding modifier and require sm_20. and shared state spaces. local.e. 1.3. January 24. local. and sqrt with IEEE 754 compliant rounding have been added. stack layout. e. Generic addressing unifies the global. Introduction • Single.0 closer to full compliance with the IEEE 754 standard. st. Support for an Application Binary Interface Rather than expose details of a particular calling convention. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. st.2. 1. Surface instructions support additional clamp modifiers. special registers. suld. an address that is the same across all threads in a warp. ldu. and shared addresses to generic addresses. and sust. Surface Instructions • • Instruction sust now supports formatted surface stores. NOTE: The current version of PTX does not implement the underlying. . and red now support generic addressing. Instructions testp and copysign have been added. Instruction cvta for converting global. PTX 2. prefetchu.3. i. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. rcp. and shared addresses to generic address and vice-versa has been added. and directives are introduced in PTX 2. See Section 7 for details of the function definition and call syntax needed to abstract the ABI.and double-precision div.g. Instructions prefetch and prefetchu have been added. stack-based ABI. New Instructions The following new instructions. and vice versa.3. atom.4. these changes bring PTX 2. Generic Addressing Another major change is the addition of generic addressing.clamp and . A new cvta instruction has been added to convert global. Cache operations have been added to instructions ld. 2010 3 . local.zero. for prefetching to specified level of memory hierarchy.

add.red}.{and.ballot.section. and Vote Instructions • • • New atomic and reduction instructions {atom.red.popc. 4 January 24.f32 have been added.le. . New special registers %nsmid. Barrier Instructions • • A system-level membar instruction. Reduction.shared have been extended to handle 64-bit data types for sm_20 targets. vote.ge.b32.or}. Instructions bar. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A “vote ballot” instruction.pred have been added.red. Other Extensions • • • Video instructions (includes prmt) have been added.sys.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.arrive instruction has been added. membar. %lanemask_{eq. has been added. 2010 .red}. %clock64. A new directive. bar now supports an optional thread count and register operands.gt} have been added. A bar.PTX ISA Version 2. has been added. Instructions {atom.u32 and bar.lt. bfi bit field extract and insert popc clz Atomic.

Chapter 3 gives an overview of the PTX virtual machine model. Chapter 7 describes the function and call syntax. and variable declarations. Chapter 4 describes the basic syntax of the PTX language. 2010 5 . Chapter 11 provides release notes for PTX Version 2.4. Chapter 8 describes the instruction set.Chapter 1. Introduction 1. Chapter 9 lists special registers. Chapter 5 describes state spaces. January 24. calling convention. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 10 lists the assembly directives supported in PTX. types. Chapter 6 describes instruction operands.0. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.

2010 .PTX ISA Version 2.0 6 January 24.

January 24.z) that specifies the thread’s position within a 1D. To coordinate the communication of the threads within the CTA. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. More precisely. a portion of an application that is executed many times. 2D.x. is an array of threads that execute a kernel concurrently or in parallel. can be isolated into a kernel function that is executed on the GPU as many different threads.2. Programs use a data parallel decomposition to partition inputs. data-parallel. or CTA. and tid. compute addresses. The thread identifier is a three-element vector tid. 2D. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Each CTA has a 1D. ntid. Each thread has a unique thread identifier within the CTA. or 3D shape specified by a three-element vector ntid (with elements ntid. or 3D CTA. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. but independently on different data. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2. Threads within a CTA can communicate with each other. It operates as a coprocessor to the main CPU. or host: In other words. (with elements tid. assign specific input and output positions. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.y.1. and results across the threads of the CTA. 2. To that effect.z). The vector ntid specifies the number of threads in each CTA dimension. work. Programming Model 2. A cooperative thread array. and ntid.Chapter 2. tid.2. Each CTA thread uses its thread identifier to determine its assigned role.1. and select work to perform. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. compute-intensive portions of applications running on the host are off-loaded onto the device.y. Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2010 7 .x.

Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 2010 . Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs.2. This comes at the expense of reduced thread communication and synchronization. read-only special registers %tid. WARP_SZ. The host issues a succession of kernel invocations to the device. which may be used in any instruction where an immediate operand is allowed. CTAs that execute the same kernel can be batched together into a grid of CTAs. and %gridid. depending on the platform.2. Each grid of CTAs has a 1D. Threads may read and use these values through predefined. 2D . a warp has 32 threads. Multiple CTAs may execute concurrently and in parallel. or 3D shape specified by the parameter nctaid. However. Threads within a warp are sequentially numbered. so PTX includes a run-time immediate constant. multiple-thread) fashion in groups called warps.PTX ISA Version 2. 2. The warp size is a machine-dependent constant. %ctaid. Some applications may be able to maximize performance with knowledge of the warp size. because threads in different CTAs cannot communicate and synchronize with each other. Typically. 8 January 24.0 Threads within a CTA execute in SIMT (single-instruction. or sequentially. A warp is a maximal subset of threads from a single CTA. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). so that the total number of threads that can be launched in a single kernel invocation is very large. %nctaid. %ntid. Each grid also has a unique temporal grid identifier (gridid). such that the threads execute the same instructions at the same time.

0) Thread (3. 0) Thread (2. 1) Thread (1. 2) Thread (1. 2010 9 . 0) CTA (0. Figure 1. 0) CTA (2. A grid is a set of CTAs that execute independently.Chapter 2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (4. 1) Thread (2. 1) CTA (2. 1) Thread (0. 0) Thread (1. 2) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (4. 1) Thread (0. 2) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (4. 1) CTA (1. Thread Batching January 24. 0) Thread (0. 0) CTA (1. 1) Thread (3.

0 2. 2010 . The device memory may be mapped and read or written by the host. as well as data filtering. or. Each thread has a private local memory.PTX ISA Version 2.3. The global. Finally. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant. respectively. referred to as host memory and device memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. for more efficient transfer. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Both the host and the device maintain their own local memory. and texture memory spaces are persistent across kernel launches by the same application. all threads have access to the same global memory. Texture memory also offers different addressing modes. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. for some specific data formats. and texture memory spaces are optimized for different memory usages. constant. The global. 10 January 24.

Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (0. 2) Block (1. 1) Block (0. 1) Block (1. 2) Figure 2. Memory Hierarchy January 24. 1) Block (1. 2010 11 . 0) Block (2. 1) Grid 1 Global memory Block (0. 0) Block (1. 0) Block (1. 1) Block (2.Chapter 2. 0) Block (0.

PTX ISA Version 2.0 12 January 24. 2010 .

The multiprocessor SIMT unit creates. each warp contains threads of consecutive. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. (This term originates from weaving. January 24. disabling threads that are not on that path. and on-chip shared memory. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). and executes threads in groups of parallel threads called warps. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. Parallel Thread Execution Machine Model 3. To manage hundreds of threads running several different programs. new blocks are launched on the vacated multiprocessors. The multiprocessor maps each thread to one scalar processor core. the first parallel thread technology. for example. different warps execute independently regardless of whether they are executing common or disjointed code paths. increasing thread IDs with the first warp containing thread 0. a cell in a grid-based computation). manages. A multiprocessor consists of multiple Scalar Processor (SP) cores. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. schedules. a voxel in a volume. the warp serially executes each branch path taken. When a multiprocessor is given one or more thread blocks to execute. a multithreaded instruction unit. The threads of a thread block execute concurrently on one multiprocessor. the multiprocessor employs a new architecture we call SIMT (single-instruction. At every instruction issue time. A warp executes one common instruction at a time. As thread blocks terminate.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. and executes concurrent threads in hardware with zero scheduling overhead. so full efficiency is realized when all threads of a warp agree on their execution path. allowing. it splits them into warps that get scheduled by the SIMT unit.1. When a host program invokes a kernel grid. Branch divergence occurs only within a warp. manages. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. The multiprocessor creates. 2010 13 . It implements a single-instruction barrier synchronization. If threads of a warp diverge via a data-dependent conditional branch. and each scalar thread executes independently with its own instruction address and register state. The way a block is split into warps is always the same. multiple-thread). the threads converge back to the same execution path.Chapter 3. and when all paths complete.

In practice. modifies. scalar threads. write to that location occurs and they are all serialized. on the other hand. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. which is a read-only region of device memory. For the purposes of correctness. the kernel will fail to launch. and writes to the same location in global memory for more than one of the threads of the warp. the programmer can essentially ignore the SIMT behavior. • The local and global memory spaces are read-write regions of device memory and are not cached. but the order in which they occur is undefined. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. If an atomic instruction executed by a warp reads. SIMT enables programmers to write thread-level parallel code for independent. modify. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. which is a read-only region of device memory. A multiprocessor can execute as many as eight thread blocks concurrently. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A key difference is that SIMD vector organizations expose the SIMD width to the software. Vector architectures. 2010 . If there are not enough registers or shared memory available per multiprocessor to process at least one block. In contrast with SIMD vector machines. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. but one of the writes is guaranteed to succeed. 14 January 24. however. as well as data-parallel code for coordinated threads. each read. the number of serialized writes that occur to that location and the order in which they occur is undefined. require the software to coalesce loads into vectors and manage divergence manually.PTX ISA Version 2. whereas SIMT instructions specify the execution and branching behavior of a single thread. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge.0 SIMT architecture is akin to SIMD (Single Instruction. As illustrated by Figure 3.

Chapter 3. 2010 15 . Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Figure 3. Hardware Model January 24.

PTX ISA Version 2. 2010 .0 16 January 24.

Pseudo-operations specify symbol and addressing management. 4. #ifdef.version directive specifying the PTX language version. Each PTX file must begin with a . #else. Lines are separated by the newline character (‘\n’). Comments in PTX are treated as whitespace. The following are common preprocessor directives: #include. #line. 4. followed by a . whitespace is ignored except for its use in separating tokens in the language. All whitespace characters are equivalent. #define. See Section 9 for a more information on these directives. 2010 17 . using non-nested /* and */ for comments that may span multiple lines. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #if. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.2. Syntax PTX programs are a collection of text source files. #endif.target directive specifying the target architecture assumed. Lines beginning with # are preprocessor directives. Comments Comments in PTX follow C/C++ syntax. January 24. Source Format Source files are ASCII text.Chapter 4. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. The C preprocessor cpp may be used to process PTX source files. PTX is case sensitive and uses lowercase for keywords. and using // to begin a comment that extends to the end of the current line.1.

maxntid .global.3.func . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.x. Statements A PTX statement is either a directive or an instruction.minnctapersm . All instruction keywords are reserved tokens in PTX. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. Instruction keywords are listed in Table 2. The guard predicate may be optionally negated.1.entry .shared .maxnreg .pragma . 2.maxnctapersm .visible 4.f32 r2.const .tex . r2.b32 r1. written as @!p.global . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. The guard predicate follows the optional label and precedes the opcode.f32 array[N]. Operands may be register variables.version . The destination operand is first.5. shl. Instructions have an optional guard predicate which controls conditional execution. mov.reg .3.b32 r1.loc . . followed by source operands. constant expressions. 2010 . or label names. Table 1.param . so no conflict is possible with user-defined identifiers.b32 r1. r2.extern . address expressions.local . and is written as @p. 0. r1. Directive Statements Directive keywords begin with a dot.align .0 4.section . %tid.PTX ISA Version 2. where p is a predicate register.3. array[r1]. Examples: .reg . r2. ld. Statements begin with an optional label and end with a semicolon.sreg . .b32 add. 18 January 24. and terminated with a semicolon.target .global start: .file PTX Directives .2.

Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2. 2010 19 .

…. Many high-level languages such as C and C++ follow similar rules for identifier names. digits. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or dollar characters.g. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.4. listed in Table 3. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. %pm3 WARP_SZ 20 January 24. or percentage character followed by one or more letters. 2010 . underscore.0 4. between user-defined variable names and compiler-generated names. digits. Table 3. or they start with an underscore. dollar. The percentage sign can be used to avoid name conflicts.PTX ISA Version 2. e. PTX allows the percentage sign as the first character of an identifier. except that the percentage sign is not allowed.

Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. Type checking rules remain the same for integer. floating-point. 4.u64). and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. each integer constant is converted to the appropriate size based on the data or instruction type at its use. To specify IEEE 754 single-precision floating point values.s64 or the unsigned suffix is specified. When used in an instruction or data initialization. Unlike C and C++. integer constants are allowed and are interpreted as in C.2. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. or binary notation.5. 4. Syntax 4. every integer constant has type . To specify IEEE 754 doubleprecision floating point values. The syntax follows that of C.Chapter 4.e. Constants PTX supports integer and floating-point constants and constant expressions. and bit-size types. 2010 21 . Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. i. 0[fF]{hexdigit}{8} // single-precision floating point January 24. i. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. the constant begins with 0d or 0D followed by 16 hex digits. the constant begins with 0f or 0F followed by 8 hex digits.e. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Floating-point literals may be written with an optional decimal point and an optional signed exponent.1. there is no suffix letter to specify size. where the behavior of the operation depends on the operand types. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.u64. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.. octal. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.. literals are always represented in 64-bit double-precision format. Integer literals may be written in decimal. zero values are FALSE and non-zero values are TRUE. These constants may be used in data initialization and as operands to instructions. the sm_1x and sm_20 targets have a WARP_SZ value of 32.5.s64 or . hexadecimal.s64) unless the value cannot be fully represented in . For predicate-type data and instructions. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.5. in which case the literal is unsigned (. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64 .5.u64 .s64) + .u64. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 integer .f64 : . or .s64 . Table 5.f64 converted type .u64 . .s64.f64 converted type constant literal + ! ~ Cast Binary (.s64 .f64 use usual conversions . 2nd is .u64 .f64 use usual conversions .u64 .f64 same as source . 2010 25 .s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 integer .f64 integer integer integer integer integer int ?.u64) (.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. Syntax 4.f64 use usual conversions .s64 .s64 .s64 .6.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .s64 .Chapter 4.u64 .u64 1st unchanged.u64 same as 1st operand .

2010 .0 26 January 24.PTX ISA Version 2.

5.param . and level of sharing between threads.reg . The characteristics of a state space include its size. Global memory. addressability. and Variables While the specific resources available in a given target GPU will vary. 2010 27 . Addressable memory shared between threads in 1 CTA. Table 6.global . Name State Spaces Description Registers. and these resources are abstracted in PTX through state spaces and data types. access rights.local . defined per-grid. shared by all threads. Types. Local memory. State Spaces A state space is a storage area with particular characteristics. All variables reside in some state space. Read-only. The list of state spaces is shown in Table 4.const . Shared. private to each thread. defined per-thread. and properties of state spaces are shown in Table 5. Special registers. Kernel parameters. . read-only memory. access speed. State Spaces. platform-specific. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. the kinds of resources will be common across platforms. or Function or local parameters. Global texture memory (deprecated). fast. pre-defined.shared .tex January 24.sreg .1.Chapter 5.

64-. 3 Accessible only via the tex instruction. Address may be taken via mov instruction. 2010 .const . or 128-bits. the parameter is then located on the stack frame and its address is in the .local state space. 28 January 24.0 Table 7. 5.e. such as grid. Register State Space Registers (. i.reg state space) are fast storage locations. floating point. or as elements of vector tuples. Registers differ from the other state spaces in that they are not fully addressable. Register size is restricted. The most common use of 8-bit registers is with ld.global . 16-. clock counters. 32-. Registers may be typed (signed integer.1. When the limit is exceeded. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).2.param (used in functions) .param and st. 32-.1.local .param (as input to kernel) . unsigned integer. Device function input parameters may have their address taken via mov. platform-specific registers. causing changes in performance. Special Register State Space The special register (. and vector registers have a width of 16-. 1 Accessible only via the ld.param instructions.shared .PTX ISA Version 2.param instruction. CTA. and thread parameters.sreg) state space holds predefined. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . register variables will be spilled to memory. For each architecture. All special registers are predefined. Registers may have alignment boundaries required by multi-word loads and stores.reg .tex Restricted Yes No3 5.sreg . or 64-bits. it is not possible to refer to the address of a register. 2 Accessible via ld. aside from predicate registers which are 1-bit. The number of registers is limited. predicate) or untyped. and cvt instructions..1. and will vary from platform to platform. st. and performance monitoring registers. scalar registers have a width of 8-. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.

This pointer can then be used to access the entire 64KB constant bank. initialized by the host. If another thread sees the variable b change. for example). Types. 2010 29 . the bank number must be provided in the state space of the load instruction. Module-scoped local memory variables are stored at fixed addresses. It is the mechanism by which different CTAs and different grids can communicate.global) state space is memory that is accessible by all threads in a context.1. For the current devices. 5. For example. In implementations that support a stack.const) state space is a read-only memory. For any thread in a context. and Variables 5. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.const[2] . Banks are specified using the . Sequential consistency is provided by the bar. Constant State Space The constant (. there are eleven 64KB banks.global.sync instruction are guaranteed to be visible to any reads after the barrier instruction. By convention. the store operation updating a may still be in flight. To access data in contant banks 1 through 10. For example.global. Local State Space The local state space (. It is typically standard memory with cache.1.local) is private memory for each thread to keep its own data. If no bank number is given.const[2].b32 const_buffer[]. each pointing to the start address of the specified constant bank. The remaining banks may be used to implement “incomplete” constant arrays (in C. ld.extern . b = b – 1.const[bank] modifier. bank zero is used. State Spaces.b32 const_buffer[]. an incomplete array in bank 2 is accessed as follows: . Threads wait at the barrier until all threads in the CTA have arrived. Global State Space The global (.4. The size is limited. Use ld. // load second word 5.local to access local variables. This reiterates the kind of parallelism available in machines that run PTX. where bank ranges from 0 to 10. the declaration . as it must be allocated on a perthread basis.local and st. Use ld. All memory writes prior to the bar. bank zero is used for all statically-sized constant variables. where the size is not known at compile time. whereas local memory variables declared January 24. Global memory is not sequentially consistent.global to access global variables.b32 %r1. st.const[2] . the stack is in local memory.3.sync instruction.1. Multiple incomplete array variables declared in the same bank become aliases.5. [const_buffer+4]. Threads must be able to do their work without waiting for other threads to do theirs. results in const_buffer pointing to the start of constant bank two. all addresses are in global memory are shared. as in lock-free and wait-free style programming. and atom. Consider the case where one thread executes the following two assignments: a = a + 1.Chapter 5.extern . The constant memory is organized into fixed size banks.

[%ptr]. [N]. ld.param state space and is accessed using ld.reg .u32 %ptr.param) state space is used (1) to pass input arguments from the host to the kernel.param . and (2b) to declare locally-scoped byte array variables that serve as function call arguments. Example: .b8 buffer[64] ) { . … Example: .f64 %d. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. mov.1.1. The resulting address is in the .PTX ISA Version 2. 2010 . The kernel parameter variables are shared across all CTAs within a grid. Therefore.param state space. … 30 January 24.param instructions.entry foo ( . 5. Similarly.x supports only kernel function parameters in . PTX code should make no assumptions about the relative locations or ordering of .param . For example. [buffer].entry bar ( . device function parameters were previously restricted to the register state space. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.6.param. 5.reg . ld.param space variables. in some implementations kernel parameters reside in global memory. len. ld. Values passed from the host to the kernel are accessed through these parameter variables using ld. typically for passing large structures by value to a function. %n.param instructions.align 8 .b32 len ) { .0 within a function or kernel body are allocated on the stack. No access protection is provided between parameter and global space in this case.reg .param.param space. (2a) to declare formal input and return parameters for device functions called from within kernel execution. These parameters are addressable. per-kernel versus per-thread).1.u32 %n.0 and requires target architecture sm_20.f64 %d. .b32 N. The address of a kernel parameter may be moved into a register using the mov instruction. Note that PTX ISA versions 1.param. The use of parameter state space for device function parameters is new to PTX ISA version 2. .param . In implementations that do not support a stack. Parameter State Space The parameter (. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Note: The location of parameter space is implementation specific. read-only variables declared in the .6.u32 %n. all local memory variables are stored at fixed addresses and recursive function calls are not supported.u32 %n.u32 %ptr.

a byte array in parameter space is used. the address of a function input parameter may be moved into a register using the mov instruction. .param formal parameter having the same size and alignment as the passed argument. [buffer+8]. x. int y. is flattened. Example: // pass object of type struct { double d.1.b32 N.b8 mystruct. Note that the parameter will be copied to the stack if necessary. call foo. st.s32 [mystruct+8].b8 buffer[12] ) { .param .param and function return parameters may be written using st.align 8 . January 24.f64 [mystruct+0]. passed to foo … .local and st. int y. The most common use is for passing objects by value that do not fit within a PTX register. This will be passed by value to a callee.reg .2.param . mystruct). Function input parameters may be read via ld. .func foo ( . Typically.f64 %d. the caller will declare a locally-scoped . .align 8 .reg . In PTX. dbl.param.0 extends the use of parameter space to device function parameters.param.s32 x.param space variable.f64 dbl. Aside from passing structures by value. ld.s32 %y. … } // code snippet from the caller // struct { double d. State Spaces.f64 %d. It is not possible to use mov to get the address of a return parameter or a locally-scoped . .reg .param. which declares a .param space is also required whenever a formal parameter has its address taken within the called function. it is illegal to write to an input parameter or read from a return parameter. In this case. .param. and so the address will be in the . such as C structures larger than 8 bytes.reg .6. (4.local state space and is accessed via ld.reg .param byte array variable that represents a flattened C structure or union. and Variables 5. 2010 31 . .s32 %y.local instructions. }.Chapter 5. Types. Device Function Parameters PTX ISA version 2. } mystruct. [buffer]. ld. … st. … See the section on function call syntax for more details.param.

tex directive is retained for backward compatibility.texref type and Section 8. Example: . where texture identifiers are allocated sequentially beginning with zero.tex state space are equivalent to module-scoped . The . Use ld. It is shared by all threads in a context. An error is generated if the maximum number of physical resources is exceeded.u32 or . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).texref tex_a.texref variables in the .global . Texture memory is read-only.u32 .texref.tex directive will bind the named texture memory variable to a hardware texture identifier.tex) state space is global memory accessed via the texture instruction.3 for the description of the . See Section 5. tex_d. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Physical texture resources are allocated on a per-module granularity.6 for its use in texture instructions. tex_f. One example is broadcast.shared to access shared variables. The . A texture’s base address is assumed to be aligned to a 16-byte boundary.tex variables are required to be defined in the global scope. tex_c.7.tex . For example.u32 . Multiple names may be bound to the same physical texture identifier. 32 January 24.8.global state space.7.u32 .tex . tex_d.1. 2010 .0 5.u32 tex_a.tex . Shared State Space The shared (.u32 tex_a. is equivalent to . Texture State Space (deprecated) The texture (. and programs should instead reference texture memory through variables of type . where all threads read from the same address. Another is sequential access from sequential threads. The texture name must be of type .shared) state space is a per-CTA region of memory for threads in a CTA to share data. An address in shared memory can be read and written by any thread in a CTA. 5.PTX ISA Version 2.shared and st.1. Shared memory typically has some optimizations to support the sharing. and variables declared in the .tex . a legacy PTX definitions such as .tex . and .u64.

f32. and instructions operate on these types. ld. The following table lists the fundamental type specifiers for each basic type: Table 8. . Two fundamental types are compatible if they have the same basic type and are the same size. 5.1. so their names are intentionally short.f64 types.s64 .s16. .f16. the fundamental types reflect the native data types supported by the target architectures. Restricted Use of Sub-Word Sizes The . A fundamental type specifies both a basic type and a size.s8.2. and Variables 5. or converted to other types and sizes. all variables (aside from predicates) could be declared using only bit-size types. stored.2.2. Operand types and sizes are checked against instruction types for compatibility. and .b64 .u64 . . and converted using regular-width registers. st.f16 floating-point type is allowed only in conversions to and from . . .Chapter 5. . Types. so that narrow values may be loaded. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.b32.f32 and . but typed variables enhance program readability and allow for better operand type checking. . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.f64 . The .2. State Spaces.s8.u32.b8. Fundamental Types In PTX. In principle. All floating-point instructions operate only on .b16. st.f32 and .s32. . .u8. Register variables are always of a fundamental type. .f64 types. For convenience. January 24. 2010 33 .u16.u8. For example. Signed and unsigned integer types are compatible if they have the same size. The same typesize specifiers are used for both variable definitions and for typing instructions. needed to fully specify instruction behavior. and cvt instructions.b8 instruction types are restricted to ld.pred Most instructions have one or more type specifiers. . Types 5. The bitsize type is compatible with any fundamental type having the same size. stored. . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .

since these properties are defined by . Referencing textures. In independent mode the fields of the .texref handle. allowing them to be defined separately and combined at the site of usage in the program. The following tables list the named members of each type for unified and independent texture modes. i. accessing the pointer with ld and st instructions. texture and sampler information each have their own handle. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. and query instructions.{u32. opaque_var.samplerref variables. In the unified mode. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. The three built-in types are . the resulting pointer may be stored to and loaded from memory. and surface descriptor variables. 34 January 24. In the independent mode.e.u64} reg. samplers. Retrieving the value of a named member via query instructions (txq. These types have named fields similar to structures. and Surface Types PTX includes built-in “opaque” types for defining texture.3. base address. suld.texref. store. sured). field ordering. For working with textures and samplers. and . PTX has two modes of operation. . and overall size is hidden to a PTX program. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. passed as a parameter to functions. or surfaces via texture and surface load/store instructions (tex. suq).samplerref.0 5. 2010 .PTX ISA Version 2. Texture. Sampler. or performing pointer arithmetic will result in undefined results.texref type that describe sampler properties are ignored. sampler.surfref. but all information about layout. hence the term “opaque”. sust.. but the pointer cannot otherwise be treated as an address. texture and sampler information is accessed through a single . and de-referenced by texture and surface load. Creating pointers to opaque variables using mov.

samplerref values N/A N/A N/A N/A nearest.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. and Variables Table 9. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_ogl. linear wrap. Types. clamp_to_edge. mirror. Member width height depth Opaque Type Fields in Independent Texture Mode . clamp_to_border N/A N/A N/A N/A N/A . 1 ignored ignored ignored ignored .Chapter 5. 1 nearest. State Spaces. linear wrap. clamp_to_border 0.texref values in elements in elements in elements 0. clamp_to_edge. clamp_ogl.texref values . 2010 35 . mirror.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.

Example: . the types may be initialized using a list of static expressions assigning values to the named members.global state space. 36 January 24.global .PTX ISA Version 2.texref tex1. .global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. these variables are declared in the . . When declared at module scope.surfref my_surface_name. As kernel parameters. 2010 .samplerref my_sampler_name. .texref my_texture_name. At module scope. Example: . these variables must be in the .param state space.global . filter_mode = nearest }.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global .global .

Variables In PTX.global . // a length-4 vector of floats . q.struct float4 coord. State Spaces.f32 V.shared .global . Three-element vectors may be handled by using a .v2 or . etc.s32 i. Vectors must be based on a fundamental type.reg . 2010 37 . an optional array size. . .4.0.global . 1.v2. Every variable must reside in one of the state spaces enumerated in the previous section. 5. January 24. This is a common case for three-dimensional grids.v3 }. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.2.v4 . 0. In addition to fundamental types.0}.reg .const . .v4 vector.4. Vectors Limited-length vector types are supported.u32 loc.f32 v0. . .v4 . 5. r. and they may reside in the register space. 0.Chapter 5. Examples: .f32 accel.global .v1.v4. . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .u8 bg[4] = {0. // a length-4 vector of bytes By default. // typedef .u16 uv.f64 is not allowed. 0}. its type and size. for example.v2 . // a length-2 vector of unsigned ints . Examples: .4.struct float4 { .reg .v4. Predicate variables may only be declared in the register state space. and Variables 5.pred p.1.global . .v4 . an optional initializer. textures. PTX supports types for simple aggregate objects such as vectors and arrays.f32 bias[] = {-1. Vectors cannot exceed 128-bits in length. a variable declaration describes both the variable’s type and its state space.b8 v. Types. and an optional fixed address for the variable. its name. where the fourth element provides padding. vector variables are aligned to a multiple of their overall size (vector length times base-type size). A variable declaration names the space in which the variable resides. Variable Declarations All storage for data is specified with variable declarations.

b32 ptr = rgba. 2010 . 19*19 (361) halfwords are reserved (722 bytes).PTX ISA Version 2.4. 0}. .f32 blur_kernel[][] = {{. .05}}. To declare an array. . {1.f16 and . label names appearing in initializers represent the address of the next instruction following the label. A scalar takes a single value. being determined by an array initializer.0. this can be used to initialize a jump table to be used with indirect branches or calls.global .v4 . this can be used to statically initialize a pointer to a variable. // address of rgba into ptr Currently.. 1} }. Variable names appearing in initializers represent the address of the variable. Initializers are allowed for all types except . {0.u8 mailbox[128]. The size of the array specifies how many elements should be reserved.global .0}.0. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).0.05}...global .0}.1.1.0 5.1.0. {0.u64.4.u16 kernel[19][19]. {0. variable initialization is supported only for constant and global state spaces.{. . Variables that hold addresses of variables or instructions should be of type ..s32 n = 10.1.1}.shared .3.05. Examples: .{. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.local . The size of the dimension is either a constant expression. 5...4.u8 rgba[3] = {{1. {0.1. Array Declarations Array declarations are provided to allow the programmer to reserve space. .u32 or . For the kernel declaration above. -1}.05. or is left empty.s32 offset[][] = { {-1.pred. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. Here are some examples: . 0}.4. where the variable name is followed by an equals sign and the initial value or values for the variable. 38 January 24.global . Similarly.global .0}}.

named %r0. Rather than require explicit declaration of every name. and Variables 5. …. For example. say one hundred. // declare %r0.0. 5.0. The default alignment for scalar and array variables is to a multiple of the base-type size. of .0. The default alignment for vector variables is to a multiple of the overall vector size.4..Chapter 5. Types. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.reg . Array variables cannot be declared this way. %r1.0}.. .6. Elements are bytes.. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.b8 bar[8] = {0. suppose a program uses a large number. State Spaces. Alignment is specified using an optional . Examples: // allocate array at 4-byte aligned address. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. alignment specifies the address alignment for the starting address of the entire array. and may be preceded by an alignment specifier. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. The variable will be aligned to an address which is an integer multiple of byte-count.4. %r1.b32 variables. not for individual elements.align 4 . These 100 register variables can be declared as follows: .0. nor are initializers permitted.0. .2. January 24.5. 2010 39 .align byte-count specifier immediately following the state-space specifier. it is quite common for a compiler frontend to generate a large number of register names. For arrays. %r99.b32 %r<100>.const . Parameterized Variable Names Since PTX supports virtual registers.

2010 .0 40 January 24.PTX ISA Version 2.

For most operations. 6. Operand Type Information All operands in instructions have a known type from their declarations.2. q.reg register state space. Most instructions have an optional predicate guard that controls conditional execution. Each operand type must be compatible with the type determined by the instruction template and instruction type.1. b. January 24. and a few instructions have additional predicate source operands. The result operand is a scalar or vector variable in the register state space. The ld. Integer types of a common size are compatible with each other. Instruction Operands 6. Source Operands The source operands are denoted in the instruction descriptions by the names a. as its job is to convert from nearly any data type to any other data type (and size). and c. s. The mov instruction copies data between registers. so operands for ALU instructions must all be in variables declared in the . Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.3. The bit-size type is compatible with every type having the same size. PTX describes a load-store machine. 6. Predicate operands are denoted by the names p. st. There is no automatic conversion between types. The cvt (convert) instruction takes a variety of operand types and sizes.Chapter 6. r. 2010 41 . mov. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. the sizes of the operands must be consistent. Instructions ld and st move data from/to addressable state spaces to/from registers. and cvt instructions copy data from one location to another. .

shared . . The interesting capabilities begin with addresses. . q. p.gloal.u32 42 January 24.reg . 6.global .const. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.[x].1.b32 p. arrays.reg . and Vectors Using scalar variables as operands is straightforward. Examples include pointer arithmetic and pointer comparisons.v4. r0. Here are a few examples: .u16 x. The syntax is similar to that used in many assembly languages.shared. Using Addresses.reg . Load and store operations move data between registers and locations in addressable state spaces. address registers. [tbl+12]. All addresses and address computations are byte-based.const . and immediate address expressions which evaluate at compile-time to a constant address. tbl. .u16 r0. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.f32 W.4. Address expressions include variable names.f32 V. there is no support for C-style pointer arithmetic.s32 q.s32 mov.v4 .4. The address is an offset in the state space in which the variable is declared. Arrays. .f32 ld.v4 .u16 ld. W.PTX ISA Version 2. and vectors.reg . 2010 . .s32 tbl[256]. address register plus byte offset. . ld.0 6. [V]. The mov instruction can be used to move the address of a variable into a pointer.

it must be written as an address calculation prior to use. .v4. .reg . where the offset is a constant expression that is either added or subtracted from a register variable.b. mov. and tex.global.4.u32 s.global.3. // move address of a[1] into s 6. and the identifier becomes an address constant in the space where the array is declared. or by indexing into the array using square-bracket notation. The registers in the load/store operations can be a vector. a[N-1]. If more complicated indexing is desired. Rb. Vectors may also be passed as arguments to called functions. January 24.z and . Array elements can be accessed using an explicitly calculated byte address.b and . say {Ra.z V.Chapter 6.y. Arrays as Operands Arrays of all types can be declared.4. Examples are ld.y V. mov.reg . Elements in a brace-enclosed vector.2. . a[0].c. Rd}.w.r.global.u32 {a. c. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. Vector loads and stores can be used to implement wide loads and stores. st. The expression within square brackets is either a constant integer. Here are examples: ld. [addr+offset2].v4.g.d}. and in move instructions to get the address of the label or function into a register.x.c.a 6. or a simple “register with constant offset” expression. .x V.u32 s.w = = = = V.f32 ld.f32 a. V2.r V. The size of the array is a constant in the program. as well as the typical color fields .f32 V. ld. A brace-enclosed list is used for pattern matching to pull apart vectors. ld. a register variable. . . a[1]. Instruction Operands 6.f32 {a. Vector elements can be extracted from the vector with the suffixes . correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. 2010 43 .g V. which may improve memory performance.u32 s.b V.global. for use in an indirect branch or call.v4 .b.4. which include mov.4. [addr+offset]. Vectors as Operands Vector operands are supported by a limited subset of instructions. b. V.a. d.v2.d}. Rc. or a braceenclosed list of similarly typed scalars.

5. 6. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.0 6. except for operations where changing the size and/or type is part of the definition of the instruction. logic. if a cvt. For example.1. and data movement instruction must be of the same type and size. 44 January 24.u16 instruction is given a u16 source operand and s32 as a destination operand.PTX ISA Version 2.5. Type Conversion All operands to all arithmetic. the u16 is zero-extended to s32. 2010 . Operands of different sizes or types must be converted prior to the operation.000 for f16). and ~131. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.s32.

u32 targeting a 32-bit register will first chop to 16-bits. For example.s16. The type of extension (sign or zero) is based on the destination format. f2u = float-to-unsigned. zext = zero-extend. f2f = float-to-float. Notes 1 If the destination register is wider than the destination format. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. January 24.Chapter 6. u2f = unsigned-to-float. the result is extended to the destination register width after chopping. Instruction Operands Table 11. cvt. chop = keep only low bits that fit. s2f = signed-to-float. f2s = float-to-signed. then sign-extend to 32-bits. 2010 45 .

Modifier .rni . Rounding Modifiers Conversion instructions may specify a rounding modifier.PTX ISA Version 2. there are four integer rounding modifiers and four floating-point rounding modifiers. Table 12. In PTX.0 6. The following tables summarize the rounding modifiers.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. choosing even integer if source is equidistant between two integers. Modifier .rz . 2010 .rzi . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rn .rm .2.rpi Integer Rounding Modifiers Description round to nearest integer.rmi .5.

2010 47 . Registers are fastest. The register in a store operation is available much more quickly. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Table 11 gives estimates of the costs of using different kinds of memory.6. while global memory is slowest. first access is high Notes January 24.Chapter 6. Instruction Operands 6. Much of the delay to memory can be hidden in a number of ways. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Operand Costs Operands from different state spaces affect the speed of an operation. Another way to hide latency is to issue the load instructions as early as possible. Table 14.

0 48 January 24. 2010 .PTX ISA Version 2.

arguments may be register variables or constants. A function declaration specifies an optional list of return parameters. 2010 49 . together these specify the function’s interface. Execution of the ret instruction within foo transfers control to the instruction following the call. and memory allocated on the stack (“alloca”). At the call. or prototype. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. Function declarations and definitions In PTX. and Application Binary Interface (ABI). stack-based ABI. so recursion is not yet supported. The simplest function has no parameters or return values.func directive. … Here. and is represented in PTX as follows: . and return values may be placed directly into register variables. function calls. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters.1. A function must be declared or defined prior to being called. implicitly saving the return address. Scalar and vector base-type input and return parameters may be represented simply as register variables. These include syntax for function definitions. support for variadic functions (“varargs”). A function definition specifies both the interface and the body of the function. execution of the call instruction transfers control to foo. In this section. functions are declared and defined using the . } … call foo. stack layout. NOTE: The current version of PTX does not implement the underlying. and an optional list of input parameters. parameter passing. the function name.func foo { … ret. Abstracting the ABI Rather than expose details of a particular calling convention. January 24.Chapter 7. 7. we describe the features of PTX needed to achieve this hiding of the ABI.

. .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.param .param. ld. byte array in . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . %ptr. .b8 [py+ 9]. (%x. … st. … ld.param.param.reg .f1.0 Example: .c3.b8 [py+ 8].b8 [py+10].s32 out) bar (. For example. ret. c4.param.param.reg .u32 %res) inc_ptr ( .f64 field are aligned.param space call (%out). … In this example.f64 f1. } { . char c[4].c2.c4.param.b64 [py+ 0]. %rc1.reg .func (.b8 c1. [y+11].b32 c1. this structure will be flattened into a byte array.b8 . note that . st. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . c2. %inc. py).func (. passed by value to a function: struct { double dbl.param space memory. %rc2.4).b8 c3. st.reg .reg .u32 %inc ) { add. [y+0]. First.param. Second. }. inc_ptr.c1.s32 x. %rc2.param variable y is used in function definition bar to represent a formal parameter.reg .f64 f1. ld. 50 January 24. consider the following C structure.b8 .u32 %res. st. // scalar args in .b8 c2. ld.param state space is used to pass the structure by value: .param. … … // computation using x.PTX ISA Version 2. In PTX.align 8 y[12]) { . a . [y+8]. ld.reg space. The . } … call (%r1). Since memory accesses are required to be aligned to a multiple of the access size. (%r1.b8 [py+11].align 8 py[12]. [y+9]. c3. bumpptr.param space variables are used in two ways.param. %rd.param. [y+10]. st.u32 %ptr. %rc1.param . a .reg . 2010 .b8 c4.

In the case of . • • • For a callee. The . .g. or a constant that can be represented in the type of the formal parameter. In the case of .reg space formal parameters. For a caller. a .reg space variable with matching type and size.param state space is used to receive parameter values and/or pass return values back to the caller. the corresponding argument may be either a . • The . size.reg state space in this way provides legacy support. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.param space byte array with matching type. or a constant that can be represented in the type of the formal parameter. A . the corresponding argument may be either a . 2010 51 .param instructions used for argument passing must be contained in the basic block with the call instruction.reg or .Chapter 7.param arguments. 8. Supporting the . For a callee. or 16 bytes. The .param or .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. 4. Note that the choice of . 2. or constants. size. The following restrictions apply to parameter passing.param variables or ..reg variables.param variables. For a caller. • The .param argument must be declared within the local scope of the caller.param byte array is used to collect together fields of a structure being passed by value. Parameters in .param space formal parameters that are byte arrays. and alignment. Abstracting the ABI The following is a conceptual way to think about the . all st.param and ld.param space formal parameters that are base-type scalar or vector variables.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. • • Arguments may be . Typically.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. January 24. the argument must also be a . In the case of .reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. This enables backend optimization and ensures that the .param state space use in device functions.reg space variable of matching type and size.param memory must be aligned to a multiple of 1.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.reg state space can be used to receive and return base-type scalar and vector values. • • • Input and return parameters may be . For .param or . and alignment of parameters.

1.x supports multiple return values for this purpose.reg or .x In PTX ISA version 1.0 continues to support multiple return registers for sm_1x targets. and . and there was no support for array parameters.param state space.0 restricts functions to a single return value. For sm_2x targets. Changes from PTX 1.PTX ISA Version 2. and a .0. PTX 2.reg state space. PTX 2.x. 52 January 24.0 7.param byte array should be used to return objects that do not fit into a register. formal parameters may be in either . In PTX ISA version 2. 2010 .1. formal parameters were restricted to .param space parameters support arrays. PTX 1. Objects such as C structures were flattened and passed or returned using multiple registers.

reg . 4). 2010 53 . or 8 bytes. … %va_start returns Loop: @p Done: January 24. %va_start.pred p.s32 result. Once all arguments have been processed.reg . … call (%max). maxN.ge p.b32 val) %va_arg (..reg .reg . (3. Variadic functions NOTE: The current version of PTX does not support variadic functions. iteratively access.u32 ptr) %va_start .u32 ap. the size may be 1. The function prototypes are defined as follows: .Chapter 7. . 2.func baz ( . and end access to a list of variable arguments. .u32 ptr.reg .reg . maxN. 4. max. This handle is then passed to the %va_arg and %va_arg64 built-in functions. 8. %va_arg. 2. %r3). For %va_arg.. for %va_arg64.reg . result.u32 sz.u32. (ap). To support functions with a variable number of arguments. %va_end is called to free the variable argument list handle. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . N. 4. following zero or more fixed parameters: . call (val).reg .b64 val) %va_arg64 (.func (.reg . or 16 bytes.b32 result.func (. // default to MININT mov. the size may be 1.2.h and varargs. bra Done. the alignment may be 1.reg . PTX provides a high-level mechanism similar to the one provided by the stdarg. %r2. } … call (%max). 2.reg .reg .b32 ctr. .reg .func ( . %r1.u32 b.func okay ( … ) Built-in functions are provided to initialize.u32 sz. Abstracting the ABI 7. 4.u32 align) . .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. ) { .func (.s32 val.h headers in C.u32 N. val. (2. ctr.func %va_end (. (ap. or 4 bytes. along with the size and alignment of the next data value to be accessed. variadic functions are declared with an ellipsis at the end of the input parameter list.reg .u32 ptr. . .reg . .u32 a. . In both cases. ctr. bra Loop.reg .reg . call (ap). ret. 0.u32 align) . … ) . %s2). setp.s32 result ) maxN ( . mov. 0x8000000. call %va_end. In PTX. %s1.

u32 ptr ) %alloca ( . If a particular alignment is required. 2010 .reg . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.0 7.func ( .local and st.PTX ISA Version 2. Alloca NOTE: The current version of PTX does not support alloca. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. To allocate memory. defined as follows: .3. The array is then accessed with ld. a function simply calls the built-in function %alloca.reg . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.local instructions. 54 January 24.

Chapter 8. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode.s32. opcode D. a. setp. opcode A. B. opcode D. A. For some instructions the destination operand is optional. B. B. January 24. C. The setp instruction writes two destination registers. For instructions that create a result value.lt p|q. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. // p = (a < b). followed by some examples that attempt to show several possible instantiations of the instruction. q = !(a < b). Format and Semantics of Instruction Descriptions This section describes each PTX instruction. while A. Instruction Set 8. the semantics are described. 8. We use a ‘|’ symbol to separate multiple destination registers. the D operand is the destination operand. 2010 55 . opcode D. A. and C are the source operands.2. In addition to the name and the format of the instruction.1. PTX Instructions PTX instructions generally have from zero to four operands. A. b.

i.pred p. Predicates are most commonly set as the result of a comparison performed by the setp instruction. To implement the above example as a true conditional branch. q. i. j.s32 j.reg . predicate registers are virtual and have . consider the high-level code if (i < n) j = j + 1. branch over 56 January 24.0 8.s32 j. the following PTX instruction sequence might be used: @!p L1: setp. n. … // compare i to n // if false. add 1 to j To get a conditional branch or conditional function call. // p = (i < n) // if i < n. add.pred as the type specifier.s32 p. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. Predicated Execution In PTX.PTX ISA Version 2.lt. where p is a predicate variable. n.3. Instructions without a guard predicate are executed unconditionally. 1. predicate registers can be declared as . As an example. bra L1.s32 p.lt. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. j. use a predicate to control the execution of the branch or call instructions. This can be written in PTX as @p setp. So. 1. 2010 . optionally negated. add.

1. ne. le (less-than-or-equal). Unsigned Integer. the result is false.3.3. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ls (lower-or-same). If either operand is NaN. and ge (greater-than-or-equal). Instruction Set 8. The bit-size comparisons are eq and ne. gt (greater-than). 2010 57 . and bitsize types. lt.3.Chapter 8. lt (less-than). and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Comparisons 8. Table 16. The unsigned comparisons are eq.1. hi (higher). le. ne. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. and hs (higher-or-same).1. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).2. ge. gt.1. unsigned integer. ordering comparisons are not defined for bit-size types. Table 15. lo (lower). The following table shows the operators for signed integer. ne (not-equal). Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.

1. then these comparisons have the same result as their ordered counterparts. and nan returns true if either operand is NaN. two operators num (numeric) and nan (isNaN) are provided. or. Table 17.u32 %r1. There is no direct conversion between predicates and integer values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. ltu. not. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. xor. neu.0.%p.0 To aid comparison operations in the presence of NaN values. and no direct way to load or store predicate register values. If both operands are numeric values (not NaN). gtu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. num returns true if both operands are numeric values (not NaN). setp can be used to generate a predicate from an integer. Table 18. unordered versions are included: equ. then the result of these comparisons is true.2. // convert predicate to 32-bit value 58 January 24. for example: selp.3.PTX ISA Version 2. and mov. If either operand is NaN. 2010 . Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. However. leu. geu.

u16 d. and this information must be specified as a suffix to the opcode. Type Checking Rules Operand Type . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. a. and integer operands are silently cast to the instruction type if needed. i.f32.fX ok inv inv ok Instruction Type .bX . Table 19.. 2010 59 .Chapter 8.sX .u16 d.bX . most notably the data conversion instruction cvt. a. add. For example. • The following table summarizes these type checking rules.reg . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.f32 d.4.fX ok ok ok ok January 24. unsigned. cvt.u16 d. and these are placed in the same order as the operands. . Floating-point types agree only if they have the same size.u16 a.e. float. Instruction Set 8. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. they must match exactly. different sizes). Example: . the add instruction requires type and size information to properly perform the addition operation (signed. It requires separate type-size modifiers for the result and source. For example.uX . b. For example: .sX ok ok ok inv . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.uX ok ok ok inv . a.reg . Signed and unsigned integer types agree provided they have the same size.reg . b.

the size must match exactly. Source register size must be of equal or greater size than the instruction-type size. stored. the data will be truncated. Operand Size Exceeding Instruction-Type Size For convenience. When used with a floating-point instruction type. 1. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.PTX ISA Version 2. When used with a narrower bit-size type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. ld. the cvt instruction does not support . The following table summarizes the relaxed type-checking rules for source operands. 60 January 24. parse error. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. stored. Note that some combinations may still be invalid for a particular instruction. 2. 2010 . so that narrow values may be loaded.0 8. Table 20. The data is truncated to the instruction-type size and interpreted according to the instruction type. inv = invalid. so those rows are invalid for cvt.4. Floating-point source registers can only be used with bit-size or floating-point instruction types.bX instruction types. unless the operand is of bit-size type. no conversion needed. st. Notes 3. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. floating-point instruction types still require that the operand type-size matches exactly.1. 4. “-“ = allowed. and converted using regular-width registers. Bit-size source registers may be used with any appropriately-sized instruction type. When a source operand has a size that exceeds the instruction-type size. for example. or converted to other types and sizes. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. For example. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize.

inv = Invalid.or sign-extended to the size of the destination register. Bit-size destination registers may be used with any appropriately-sized instruction type. The data is sign-extended to the destination register width for signed integer instruction types. 4. Floating-point destination registers can only be used with bit-size or floating-point instruction types. When used with a narrower bit-size instruction type. January 24. The following table summarizes the relaxed type-checking rules for destination operands. Destination register size must be of equal or greater size than the instruction-type size. If the corresponding instruction type is signed integer. the data will be zero-extended.Chapter 8. the data is sign-extended. the data is zeroextended. Notes 3. 2. otherwise. parse error. When used with a floatingpoint instruction type. Table 21. The data is signextended to the destination register width for signed integer instruction types. Instruction Set When a destination operand has a size that exceeds the instruction-type size. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. 1. the destination data is zero. and is zero-extended to the destination register width otherwise. “-“ = Allowed but no conversion needed. the size must match exactly. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. 2010 61 . zext = zero-extend.

2010 .6. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. the semantics of 16-bit instructions in PTX is machine-specific. When executing on a 32-bit data path. Both situations occur often in programs. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.0 8.1. or conditional return.uni suffix. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. Divergence of Threads in Control Constructs Threads in a CTA execute together. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. The semantics are described using C. for example. For divergent control flow. the threads are called uniform. until they come to a conditional control construct such as a conditional branch. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. for many performance-critical applications. at least in appearance. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. If threads execute down different control flow paths. At the PTX language level. 8. These extra precision bits can become visible at the application level. using the . by a right-shift instruction. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path.6. 16-bit registers in PTX are mapped to 32-bit physical registers. and for many applications the difference in execution is preferable to limiting performance. until C is not expressive enough. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine.5. If all of the threads act in unison and follow a single control flow path. Therefore. conditional function call. the optimizing code generator automatically determines points of re-convergence. and 16-bit computations are “promoted” to 32-bit computations. However. 62 January 24. so it is important to have divergent threads re-converge as soon as possible. A compiler or programmer may chose to enforce portable. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. this is not desirable. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. a compiler or code author targeting PTX can ignore the issue of divergent threads. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. 8.PTX ISA Version 2. the threads are called divergent.

2010 63 .1.7.Chapter 8.cc.7. Instructions All PTX instructions may be predicated. In the following descriptions. addc sub. Instruction Set 8. the optional guard predicate is omitted from the syntax.cc. The Integer arithmetic instructions are: add sub add. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. 8.

MAXINT (no overflow) for the size of the operation. b.s64 }. @p add. . PTX ISA Notes Target ISA Notes Examples Table 23.. .type add{. add.sat applies only to . a.s32 .s32 d.u16. a.u64.z. . sub.s32 c. a.0 Table 22. b. .0.u32 x.type = { .s32 d. d = a + b.s64 }. .c. a. .type sub{. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add. d. .u64.type = { . . b.sat}. // . Introduced in PTX ISA version 1.s32. Supported on all target architectures.u16. d = a – b. b.s32 .s32 type.s32..sat}. Saturation modifier: . Applies only to . . d. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.s16.sat limits result to MININT.y. 2010 .s32 c.0.u32.sat.MAXINT (no overflow) for the size of the operation.s16.a.1. Introduced in PTX ISA version 1. // . sub. Supported on all target architectures. Saturation modifier: . add Syntax Integer Arithmetic Instructions: add Add two values.b.sat applies only to . Applies only to .s32 type.sat limits result to MININT.u32. PTX ISA Notes Target ISA Notes Examples 64 January 24.PTX ISA Version 2. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.

addc.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. d = a + b.y1.CF No integer rounding modifiers. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.u32.b32 addc. a.z3.z1. 2010 65 . d = a + b + CC.b32 addc. sub.CF.z1. add. x2.u32. and there is no support for setting.z4. if .s32 }. x2.z2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. x4.z3.y4.cc. Supported on all target architectures. .s32 }.y4.y3.cc. a. carry-out written to CC. Instruction Set Instructions add.y1.cc. x3. or testing the condition code.type = {. Behavior is the same for unsigned and signed integers.cc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. Introduced in PTX ISA version 1. No other instructions access the condition code. b.b32 x1.cc.cc}. Behavior is the same for unsigned and signed integers. No saturation. These instructions support extended-precision integer addition and subtraction. .cc.y2. .z4.cc Add two values with carry-out.Chapter 8.b32 addc.b32 x1. add.y3.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. carry-out written to CC.y2. @p @p @p @p add.CF) holding carry-in/carry-out or borrowin/borrow-out.CF No integer rounding modifiers.b32 addc.type d.2. .cc. clearing.type = { . Introduced in PTX ISA version 1.cc. x4.2. @p @p @p @p add.type d.b32 addc.cc Syntax Integer Arithmetic Instructions: add. No saturation. Supported on all target architectures. b.cc. x3. Table 24.z2.cc specified. addc{.b32 addc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.

cc.cc. @p @p @p @p sub.z2. x4. Introduced in PTX ISA version 1. . x3.CF).y2.b32 x1.y1.s32 }. sub.3. Behavior is the same for unsigned and signed integers.y3. x2.0 Table 26.cc Subract one value from another. if .cc. x2. .z1. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.cc.z3.cc Syntax Integer Arithmetic Instructions: sub.cc.b32 subc.y2. with borrow-out.z2. a.y3.type = { .z1.z4.z3.b32 subc.u32. b.3.(b + CC.cc. No saturation. a. d = a – b. Introduced in PTX ISA version 1. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. d = a .CF No integer rounding modifiers.z4. Supported on all target architectures.b32 x1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.type = {.cc}.cc.b32 subc.PTX ISA Version 2. No saturation.CF No integer rounding modifiers.cc.u32. x3.type d. borrow-out written to CC.cc.s32 }. . Supported on all target architectures. @p @p @p @p sub. withborrow-in and optional borrow-out.b32 subc. sub.cc specified. . 2010 .b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y4. b. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.y4.b32 subc. Behavior is the same for unsigned and signed integers. borrow-out written to CC. x4. subc{.y1.type d.

u32. mul.s32 z.wide is specified.0. and either the upper or lower half of the result is written to the destination register.fxs.x..y. d = t<n-1. If .hi variant // for .lo. // for . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul.fys.hi.s16 fa. b. . then d is the same size as a and b. If .lo variant Notes The type of the operation represents the types of the a and b operands.hi or .0>. 2010 67 . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.type d. creates 64 bit result January 24. save only the low 16 bits // 32*32 bits.fxs. d = t.Chapter 8..s32. . .wide suffix is supported only for 16.s16. The .s16 fa. mul{.s64 }. d = t<2n-1.wide. . Instruction Set Table 28. // 16*16 bits yields 32 bits // 16*16 bits. . mul.lo is specified.fys.u64... . a.lo.wide.and 32-bit integer types. Supported on all target architectures. then d is twice as wide as a and b to receive the full result of the multiplication. Description Semantics Compute the product of two values.wide}.wide // for . t = a * b.u16. n = bitwidth of type.type = { .n>.

lo is specified.. bitwidth of type. mad{.PTX ISA Version 2.lo variant Notes The type of the operation represents the types of the a and b operands.lo. d.and 32-bit integer types.wide is specified.0 Table 29.p.r. If . c. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. t n d d d = = = = = a * b.u16. The ..0.b.u32.hi or .hi. . Description Semantics Multiplies two values and adds a third.s64 }.. . then d and c are twice as wide as a and b to receive the result of the multiplication.wide // for .s32 r. . t + c.hi variant // for . then d and c are the same size as a and b. .a. and then writes the resulting value into a destination register.lo. @p mad.s32 type in .MAXINT (no overflow) for the size of the operation. b. c.wide suffix is supported only for 16. t<n-1. t<2n-1. Applies only to . 68 January 24. and either the upper or lower half of the result is written to the destination register.wide}.sat limits result to MININT. mad.u64.hi.hi mode.type = { . . .0> + c. a. a.s32 d. Saturation modifier: . If .lo..q.sat. b.c..s32 d. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. Supported on all target architectures. 2010 .type mad.n> + c.s16.s32. // for .

u32. b. t = a * b.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.b. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.hi variant // for .e. mul24.0. 48bits. // for . .lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. Supported on all target architectures. d = t<47. // low 32-bits of 24x24-bit signed multiply.hi may be less efficient on machines without hardware support for 24-bit multiply.type d.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.0>.type = { . mul24. and return either the high or low 32-bits of the 48-bit result. mul24. .lo}. All operands are of the same type and size. 2010 69 .. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24. i. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. a.Chapter 8.s32 }.lo.s32 d.. Instruction Set Table 30.16>. January 24. mul24{.a..hi. d = t<31.

type mad24.s32 type in . . Applies only to .s32 }.hi mode.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.16> + c.hi. mad24.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.. All operands are of the same type and size.s32 d. and add a third.0 Table 31.MAXINT (no overflow). 48bits. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.sat. // low 32-bits of 24x24-bit signed multiply. c. 2010 . Description Compute the product of two 24-bit integer values held in 32-bit source registers.e. b.u32.s32 d.hi variant // for .c. 70 January 24.type = { .hi may be less efficient on machines without hardware support for 24-bit multiply.hi. a.b.0> + c. d = t<47..lo}.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. b. d. Supported on all target architectures.PTX ISA Version 2.sat limits result of 32-bit signed addition to MININT. mad24.lo. .a. 32-bit value to either the high or low 32-bits of the 48-bit result. d = t<31. t = a * b. a. Return either the high or low 32-bits of the 48-bit result. Saturation modifier: . i.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.0. // for .. mad24. mad24{. c. mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b32. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. clz. popc.b32 popc.u32 PTX ISA Notes Target ISA Notes Examples Table 40.b64 type.b32) { max = 32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz. d = 0. X. cnt. the number of leading zeros is between 0 and 32.type d.type = { . the number of leading zeros is between 0 and 64. .type = { . . . Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. popc. a = a << 1. } while (d < max && (a&mask == 0) ) { d++. a. a.PTX ISA Version 2. popc Syntax Integer Arithmetic Instructions: popc Population count. inclusively.0. a. popc requires sm_20 or later. 2010 .b64 }.b64 }.type d. clz requires sm_20 or later. // cnt is . } else { max = 64.b32 type. For .0. if (. a = a >> 1. . // cnt is .b32 clz.0 Table 39.b64 d. while (a != 0) { if (a&0x1) d++. cnt. X. a.b64 d. d = 0. mask = 0x8000000000000000.type == . clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. inclusively. For .u32 Semantics 74 January 24.b32. mask = 0x80000000. } Introduced in PTX ISA version 2.

u32. If . .u32 January 24. bfind.0. Instruction Set Table 41.s32) ? 31 : 63.s64 cnt.u64.type==. X. d.s32. For unsigned integers.u32 d.type = { .u32 || . d = -1. 2010 75 . Description Find the bit position of the most significant non-sign bit in a and place the result in d.shiftamt is specified. i--) { if (a & (1<<i)) { d = i. Semantics msb = (.Chapter 8. i>=0.shiftamt.type==.s64 }. bfind.u32. For signed integers.shiftamt.type d. // cnt is .d. . and operand d has type . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind requires sm_20 or later. a. for (i=msb. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type bfind. bfind. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. a. break. a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Operand a has the instruction type. . } } if (. bfind returns the bit position of the most significant “1”.shiftamt && d != -1) { d = msb . . bfind returns 0xFFFFFFFF if no non-sign bit is found.

a. .type = { . Description Semantics Perform bitwise reversal of input. i<=msb. msb = (. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. brev.0. 76 January 24.b32.b32) ? 31 : 63. for (i=0.0 Table 42.type==. .PTX ISA Version 2.type d. brev.b64 }. 2010 . a. i++) { d[i] = a[msb-i]. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. brev requires sm_20 or later.b32 d.

Instruction Set Table 43.s32. Operands a and d have the same type as the instruction type.msb)].u32 || . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.type==.s32) ? 31 : 63.u64: .u64. d = 0.u32 || . bfe.type==. . The destination d is padded with the sign bit of the extracted field.Chapter 8. and operands b and c are type . 2010 77 . bfe requires sm_20 or later.u32. bfe. c.u32. i<=msb. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. else sbit = a[min(pos+len-1.type==. Description Extract bit field from a and place the zero or sign-extended result in d. The sign bit of the extracted field is defined as: . .u64 || len==0) sbit = 0. pos = b. if (.type==. the result is zero.a. and source c gives the bit field length in bits. Source b gives the bit field starting bit position.0. .type d. .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. b. . for (i=0. If the start position is beyond the msb of the input.b32 d. Semantics msb = (. len = c.len.type = { .s32. a. otherwise If the bit field length is zero.u32. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.s64 }. the destination d is filled with the replicated sign bit of the extracted field. January 24.start.

and operands c and d are type . i++) { f[pos+i] = a[i].len. b.b32) ? 31 : 63. f = b. the result is b. 78 January 24. bfi.b64 }.b32 d.a. bfi. Description Align and insert a bit field from a into b. Source c gives the starting bit position for the insertion.0.u32. Operands a.b32. and f have the same type as the instruction type. d.type==.0 Table 44. If the bit field length is zero. for (i=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { . a. b. the result is b.start. . bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. and source d gives the bit field length in bits. If the start position is beyond the msb of the input. Semantics msb = (. len = d. i<len && pos+i<=msb. c.type f. 2010 .PTX ISA Version 2. and place the result in f. .b. bfi requires sm_20 or later. pos = c.

rc16 }. b0}}. Note that the sign extension is only performed as part of generic form. msb=1 means replicate the sign. . .b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.ecl. In the generic form (no mode specified). . prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. and reassemble them into a 32-bit destination register.mode = { .b1 source select c[7:4] d. as a 16b permute code. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. b6.Chapter 8. prmt. a} = {{b7. b1. For each byte in the target register.f4e.b3 source select c[15:12] d. . b. Description Pick four arbitrary bytes from two 32-bit registers. msb=0 means copy the literal value. Thus. default mode index d. a. {b3. b2.rc8. b4}. c. the permute control consists of four 4-bit selection values.b2 source select c[11:8] d.b32{. The msb defines if the byte value should be copied.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.ecr. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. The bytes in the two source registers are numbered from 0 to 7: {b.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. .mode} d. 2010 79 .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. . the four 4-bit values fully specify an arbitrary byte permute. Instruction Set Table 45. b5. a 4-bit selection value is defined.b4e.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.

tmp[15:08] = ReadByte( mode. r2. ctl[3] = (c >> 12) & 0xf. ctl[1]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r3.f4e r1. ctl[3]. tmp64 ).0. } tmp[07:00] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp[23:16] = ReadByte( mode. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r1. r4. ctl[1] = (c >> 4) & 0xf. r3. tmp[31:24] = ReadByte( mode.0 Semantics tmp64 = (b<<32) | a.b32 prmt. prmt requires sm_20 or later. prmt. 2010 . ctl[0]. r2. 80 January 24. r4. tmp64 ). tmp64 ). ctl[2]. tmp64 ). ctl[2] = (c >> 8) & 0xf.PTX ISA Version 2.b32.

7.2. 2010 81 .f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on .Chapter 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Instruction Set 8.f32 and .

ex2}. mul.f32 . default is .rn and instructions may be folded into a multiply-add.rcp.sub. Double-precision instructions support subnormal inputs and results.f32 {add.0 The following table summarizes floating-point instructions in PTX.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. 1.f64 {abs.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 rsqrt.rn and instructions may be folded into a multiply-add. sub. and mad support saturation of results to the range [0.f32 are the same.target sm_20 mad.rnd.fma}.PTX ISA Version 2. default is .approx.sqrt}. but single-precision instructions return an unspecified NaN.ftz .mul}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.max}.0.f32 {div.neg.approx. .lg2. Table 46. NaN payloads are supported for double-precision instructions.rm .rz .fma}.cos.min.rnd.rn .f64 {sin. The optional . 2010 . with NaNs being flushed to positive zero.rcp.f64 mad.f64 are the same.approx. Note that future implementations may support NaN payloads for single-precision instructions.max}.sqrt}.rp .sqrt}. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f64 div.target sm_1x No rounding modifier.f64 rsqrt.f32 {abs. No rounding modifier.f64 and fma.rnd.sub.min.32 and fma. If no rounding modifier is specified.sat Notes If no rounding modifier is specified. so PTX programs should not rely on the specific single-precision NaNs being generated.mul}.rnd. {add.f32 {div.target sm_20 . 82 January 24. Instruction Summary of Floating-Point Instructions . . {mad.f32 {mad.full.f32 {div.rnd.0].neg. Single-precision add.approx.rnd.rcp.

y. . . testp Syntax Floating-Point Instructions: testp Test floating-point property.infinite.f32. not infinity). X. .number.pred = { . testp. 2010 83 . z.number testp.f32. Introduced in PTX ISA version 2. positive and negative zero are considered normal numbers. . . . and return the result as d. a. . . b. copysign.notanumber testp.normal.infinite testp.type = { . Instruction Set Table 47. . not infinity) As a special case. a. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. copysign requires sm_20 or later. C.f64 isnan. f0. // result is . Table 48. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.op p.notanumber. testp. p. A.infinite.type d. copysign.f32 testp.Chapter 8. January 24.f64 }. true if the input is a subnormal number (not NaN.type .f64 x.subnormal }. testp requires sm_20 or later.type = { .f64 }. B. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.normal testp. testp.finite testp.op.notanumber. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.f32 copysign.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.0.0.finite.

.rz. Rounding modifiers have the following target requirements: . .rz available for all targets .sat. 1.f32 supported on all target architectures.sat}.f64.f64 d.f32. .rnd}. . .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. add{. subnormal numbers are supported.0. add. a.ftz}{.rn.f32 clamps the result to [0.f2. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. NaN results are flushed to +0. requires sm_20 Examples @p add. d = a + b.rn. b. add.rp for add.rnd = { .rp }. 84 January 24. add. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 flushes subnormal inputs and results to sign-preserving zero. . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64 requires sm_13 or later. b. sm_1x: add. Rounding modifiers (default is . add.f32 add{. requires sm_13 for add. 2010 .f64 supports subnormal numbers.rn): .rm.0].0. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm mantissa LSB rounds towards negative infinity .PTX ISA Version 2. add Syntax Floating-Point Instructions: add Add two values.0 Table 49.f3.ftz. In particular. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rz.rz mantissa LSB rounds towards zero .ftz.f32 flushes subnormal inputs and results to sign-preserving zero.rm.rn mantissa LSB rounds to nearest even . Saturation modifier: . a.rnd}{. d. add.f32 f1.0f.

Saturation modifier: sub. January 24. . 1.sat}.a.b. sub{.f32 f1. sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn mantissa LSB rounds to nearest even .ftz. requires sm_20 Examples sub.ftz.f32 c.f32 clamps the result to [0. sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rm. a.rn.f32 sub{. . sub.f32. .rz mantissa LSB rounds towards zero .ftz}{. Instruction Set Table 50. 2010 85 .0].f32 flushes subnormal inputs and results to sign-preserving zero.f3.rnd}{.0.rm. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.Chapter 8.f64.f64 requires sm_13 or later.rp for sub.rz available for all targets .rp }. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. d = a .rm mantissa LSB rounds towards negative infinity .rz.b. b. requires sm_13 for sub.f32 supported on all target architectures.f2.rnd = { .rn.sat. . a. sub Syntax Floating-Point Instructions: sub Subtract one value from another. sub.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. NaN results are flushed to +0.0. In particular.0f. Rounding modifiers have the following target requirements: . .rnd}. Rounding modifiers (default is . d. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub. sm_1x: sub.rn.rn): .f64 d. . subnormal numbers are supported.

rn.rp for mul.ftz. .rm.pi // a single-precision multiply 86 January 24. . mul.f64 requires sm_13 or later. Saturation modifier: mul. Rounding modifiers have the following target requirements: . . requires sm_20 Examples mul.rm mantissa LSB rounds towards negative infinity . 2010 .sat}.rnd}. .f32 flushes subnormal inputs and results to sign-preserving zero.f64.rz.f32 supported on all target architectures.0]. all operands must be the same size. 1. mul{.f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. subnormal numbers are supported. sm_1x: mul.rnd = { . In particular. d.0 Table 51.radius.f64 d.rn mantissa LSB rounds to nearest even .f32 clamps the result to [0. Description Semantics Notes Compute the product of two values. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rnd}{. a.rp }. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .f32 mul{.rn): . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. mul. mul.PTX ISA Version 2.0.ftz}{. NaN results are flushed to +0.f32 circumf.0f. d = a * b.rn. Rounding modifiers (default is . mul Syntax Floating-Point Instructions: mul Multiply two values. a. b.sat. . For floating-point multiplication.rz mantissa LSB rounds towards zero .ftz. requires sm_13 for mul.f32 flushes subnormal inputs and results to sign-preserving zero. b.f64 supports subnormal numbers.rz available for all targets .0. mul.rm. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.

sat}. a. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rnd.ftz}{.f32 flushes subnormal inputs and results to sign-preserving zero.a. PTX ISA Notes Target ISA Notes Examples January 24.rp }.rnd{. @p fma.f32 requires sm_20 or later.f64 supports subnormal numbers.0. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma. fma.rnd = { . d = a*b + c. b.c.x.rm mantissa LSB rounds towards negative infinity . sm_1x: fma. 1.f32 fma.rm. b.f32 introduced in PTX ISA version 2. again in infinite precision. NaN results are flushed to +0.rn. fma. c. fma.rn.ftz.f64 introduced in PTX ISA version 1.0. The resulting value is then rounded to double precision using the rounding mode specified by .f64.f32 fma. .f64 d.rn.4. 2010 87 . Rounding modifiers (no default): .y.rn mantissa LSB rounds to nearest even .Chapter 8. again in infinite precision. Saturation: fma. fma. fma. c.ftz.b. fma. d. . d. Instruction Set Table 52.f32 clamps the result to [0.f64 requires sm_13 or later.f32 is unimplemented in sm_1x.0].0f.rz.rz mantissa LSB rounds towards zero .rnd.z. fma. . The resulting value is then rounded to single precision using the rounding mode specified by .f64 is the same as mad. .f32 computes the product of a and b to infinite precision and then adds c to this product.rnd. a. fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. subnormal numbers are supported.f64 computes the product of a and b to infinite precision and then adds c to this product. fma.sat.f64 w.

rz mantissa LSB rounds towards zero . Note that this is different from computing the product with mul.rnd{. // . again in infinite precision.target sm_20 d.rnd.f32 flushes subnormal inputs and results to sign-preserving zero.f32 mad. In this case. where the mantissa can be rounded and the exponent will be clamped. The resulting value is then rounded to double precision using the rounding mode specified by . // .f32.0. again in infinite precision.sat. For . a.e. and then the mantissa is truncated to 23 bits.f32 computes the product of a and b to infinite precision and then adds c to this product. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. NaN results are flushed to +0.f64 supports subnormal numbers. but the exponent is preserved.rz.f32 flushes subnormal inputs and results to sign-preserving zero.rnd.f32 is implemented as a fused multiply-add (i. mad. mad.rn.ftz.f64. sm_1x: mad.target sm_1x d. Saturation modifier: mad.rnd.target sm_20: mad.rnd = { .f32).rnd. For . mad. 1.f64 computes the product of a and b to infinite precision and then adds c to this product.f64} is the same as fma. Unlike mad.0f. The resulting value is then rounded to single precision using the rounding mode specified by . . the treatment of subnormal inputs and output follows IEEE 754 standard. c. mad.f64}.ftz.f64 d. mad. mad.PTX ISA Version 2.f32 is when c = +/-0. subnormal numbers are supported.target sm_1x: mad. mad. 88 January 24.rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity . fma. Description Semantics Notes Multiplies two values and adds a third. . 2010 . c. mad{.rp }. and then writes the resulting value into a destination register. b.f64 is the same as fma. The resulting value is then rounded to double precision using the rounding mode specified by ..rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.{f32.sat}. The exception for mad. c.ftz}{. mad.0].f64 computes the product of a and b to infinite precision and then adds c to this product. a. d = a*b + c. a. . // .0 devices. Rounding modifiers (no default): .rm.{f32. When JIT-compiled for SM 2.f32 computes the product of a and b at double precision.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.0 Table 53. b. mad. b.f32 mad.f32 is identical to the result computed using separate mul and add instructions.ftz}{.rn.f32 clamps the result to [0. again in infinite precision.0.target sm_13 and later .sat}.

Legacy mad.b.f32 d.rm..0. 2010 89 .f32 for sm_20 targets.. mad.rn.0 and later.rn.Chapter 8. requires sm_20 Examples @p mad.f64 instructions having no rounding modifier will map to mad. a rounding modifier is required for mad.f64 requires sm_13 or later.rm.rz.. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.c.. a rounding modifier is required for mad. Rounding modifiers have the following target requirements: .rp for mad.f64.f64.. requires sm_13 .. In PTX ISA versions 1.f32.rz.4 and later. Target ISA Notes mad. January 24.a.f32 supported on all target architectures. In PTX ISA versions 2.rp for mad.f64.rn.

approx. z. div. Fast.full. full-range approximation that scales operands to achieve better accuracy.full.f32 div. or .rn mantissa LSB rounds to nearest even . . xd.f64 defaults to div. div. y. The maximum ulp error is 2 across the full range of inputs.rm.approx.circum. sm_1x: div. a. Subnormal inputs and results are flushed to sign-preserving zero.rn. div. x. Target ISA Notes div.f32 flushes subnormal inputs and results to sign-preserving zero. . For PTX ISA version 1.full.14159.ftz. and rounding introduced in PTX ISA version 1.f32 div.f64 introduced in PTX ISA version 1. For PTX ISA versions 1. d = a / b.ftz}.f32 defaults to div. d.approx.0 through 1.3. the maximum ulp error is 2. div.f32 flushes subnormal inputs and results to sign-preserving zero.rm. b. a. b.full. but is not fully IEEE 754 compliant and does not support rounding modifiers. zd. 2010 .f32 and div.rnd is required.PTX ISA Version 2.4.f64 diam. Fast.rnd = { .f64 d. Examples 90 January 24.rn.f32 requires sm_20 or later. Explicit modifiers . . div.f32.ftz.f32 and div.f64 requires sm_13 or later.f32 div.rnd.approx. div. div.rn.rp}.rp }. b.full{.3. div Syntax Floating-Point Instructions: div Divide one value by another.f32 div.ftz}. .rnd.f32 div. one of .f64. a.0 Table 54.full. div.ftz.f32 supported on all target architectures. subnormal numbers are supported.rz mantissa LSB rounds towards zero .approx. yd. .f32 implements a relatively fast.{rz. a.f64 requires sm_20 or later.4 and later. 2126]. approximate division by zero creates a value of infinity (with same sign as a).ftz.f32 implements a fast approximation to divide. computed as d = a * (1/b).ftz. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.approx. approximate single-precision divides: div.rnd{. and div. Description Semantics Notes Divides a by b. b.f64 supports subnormal numbers.rz. .rm mantissa LSB rounds towards negative infinity . PTX ISA Notes div. stores result in d. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . For b in [2-126.ftz}. div. // // // // fast.approx{. d.0.

Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. subnormal numbers are supported. abs{.0.f64 supports subnormal numbers. d.f32 supported on all target architectures.f64 d. NaN inputs yield an unspecified NaN.ftz. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. sm_1x: neg. d = -a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.f64 d. Table 56.Chapter 8.f0.f32 flushes subnormal inputs and results to sign-preserving zero. neg.ftz.ftz}. abs. neg. Instruction Set Table 55. a. January 24.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. neg. neg.ftz}. abs.ftz. NaN inputs yield an unspecified NaN. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Subnormal numbers: sm_20: By default.f32 supported on all target architectures. neg{. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. abs. 2010 91 .f32 flushes subnormal inputs and results to sign-preserving zero. abs. sm_1x: abs.f0. a.0.f32 x.f64 requires sm_13 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Take the absolute value of a and store the result in d. neg. a. d.f32 abs. Subnormal numbers: sm_20: By default. d = |a|.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero. abs.f32 neg.ftz. subnormal numbers are supported. Negate the sign of a and store the result in d.

ftz.0. b. max.f32 supported on all target architectures. b.f2. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.ftz.f32 min. sm_1x: min.f32 max. 92 January 24.f64 f0. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.b. max.c. a. sm_1x: max.f64 supports subnormal numbers. min. max.z. subnormal numbers are supported.f64 supports subnormal numbers. a. (a < b) ? a : b.0 Table 57. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.ftz.b.f32 supported on all target architectures. b.f32 min. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.0. Store the maximum of a and b in d.f64 d. min. a. min{.f64 d. b. b. b. a. min.f32 max. subnormal numbers are supported. d.f64 requires sm_13 or later. max{. d. Store the minimum of a and b in d. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.x.ftz}. min.f64 requires sm_13 or later. a.PTX ISA Version 2.c.f64 z. @p min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d d d d = = = = NaN. (a > b) ? a : b.ftz}. a. max. max.f32 flushes subnormal inputs and results to sign-preserving zero.f1. Table 58.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. a. d d d d = = = = NaN.

rn mantissa LSB rounds to nearest even .approx.approx.f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.approx or . Input -Inf -subnormal -0. xi. .approx and .f32 rcp.ftz were introduced in PTX ISA version 1.0. d. The maximum absolute error is 2-23.f32 defaults to rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f32 flushes subnormal inputs and results to sign-preserving zero.ftz.4 and later.rnd{. rcp. xi.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.rn.f64 ri. Description Semantics Notes Compute 1/a.f64.3.rnd = { . rcp. subnormal numbers are supported. rcp.rp}. rcp.rm mantissa LSB rounds towards negative infinity . and rcp.f32 implements a fast approximation to reciprocal.0 through 1.rm.rn.f64 requires sm_20 or later. For PTX ISA versions 1. d = 1 / a.0.r. PTX ISA Notes rcp.f32 requires sm_20 or later.rz mantissa LSB rounds towards zero .f64 d.rnd. rcp. Target ISA Notes rcp.ftz}. rcp.0.ftz}.rn.rn. . sm_1x: rcp.ftz.0 +0. 2010 93 .rnd is required. Examples January 24. one of .x.rz.f64 and explicit modifiers .0 over the range 1. rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. a.0 +subnormal +Inf NaN Result -0.f32 and rcp. a. // fast.rn. a.rnd.0 -Inf -Inf +Inf +Inf +0. Instruction Set Table 59. store result in d.approx.{rz.f32.f32 supported on all target architectures. d.ftz.ftz.Chapter 8.f64 introduced in PTX ISA version 1. . rcp.f32 rcp.approx.rn.f64 defaults to rcp.f32 rcp.0-2. rcp.approx{.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rp }.x.rm. General rounding modifiers were added in PTX ISA version 2.f32 rcp.f64 requires sm_13 or later.4. rcp.

sqrt.f64 introduced in PTX ISA version 1.f64 defaults to sqrt.f64 requires sm_20 or later.0 +0.rp }.rnd is required. sqrt.4 and later. a. // IEEE 754 compliant rounding d. sqrt.rm mantissa LSB rounds towards negative infinity .rn.0.approx.rnd. approximate square root d. r.rn.rnd{.f32 defaults to sqrt.rnd = { .f64 requires sm_13 or later. PTX ISA Notes sqrt.f64 and explicit modifiers .0 +0. r.f32 and sqrt.f32 is TBD.f64.rn.rn mantissa LSB rounds to nearest even .f32 sqrt.0 Table 60.rn. General rounding modifiers were added in PTX ISA version 2.3. sqrt. Input -Inf -normal -subnormal -0.approx.ftz. subnormal numbers are supported. .rn.0. and sqrt.ftz.f32 sqrt.f32 sqrt.rnd.0 +subnormal +Inf NaN Result NaN NaN -0.rn.ftz were introduced in PTX ISA version 1.f64 supports subnormal numbers.ftz. Description Semantics Notes Compute sqrt(a). Target ISA Notes sqrt.x. store in d.approx{. d = sqrt(a). 2010 .0 -0. sqrt.approx or .f64 d. For PTX ISA versions 1.approx.approx. Examples 94 January 24.f64 r. . For PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.rm.approx.rz mantissa LSB rounds towards zero . // fast. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.ftz. sqrt. // IEEE 754 compliant rounding .f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1.{rz.0 +0. The maximum absolute error for sqrt.x. a.4.rm. sqrt.f32.rz. sqrt.f32 supported on all target architectures.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. one of .PTX ISA Version 2. sm_1x: sqrt.rp}.f32 requires sm_20 or later.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .ftz}. .f32 sqrt.x. sqrt. sqrt.f32 implements a fast approximation to square root.approx and .ftz}. a.

ftz were introduced in PTX ISA version 1.f64 defaults to rsqrt.f64 is TBD. January 24. the .f32 is 2-22.f64 is emulated in software and are relatively slow.approx. sm_1x: rsqrt.4 and later. rsqrt. Note that rsqrt.f32 rsqrt. rsqrt. rsqrt. The maximum absolute error for rsqrt.approx{. Input -Inf -normal -subnormal -0.approx.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. and rsqrt. rsqrt.f64 were introduced in PTX ISA version 1. d.4. x. a.0 through 1. store the result in d.3.f64. rsqrt. Explicit modifiers .f64 requires sm_13 or later. 2010 95 . rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. a. For PTX ISA version 1. d = 1/sqrt(a). For PTX ISA versions 1.Chapter 8.f32 defaults to rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt. Target ISA Notes Examples rsqrt.0 +0.approx.f64 supports subnormal numbers. PTX ISA Notes rsqrt.ftz}.4 over the range 1.f32.ftz.f64 isr. ISR.0.approx implements an approximation to the reciprocal square root.0 NaN The maximum absolute error for rsqrt.f32 and rsqrt. subnormal numbers are supported.0-4. Compute 1/sqrt(a). Instruction Set Table 61.approx.approx. Subnormal numbers: sm_20: By default. X.ftz.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f32 rsqrt.approx modifier is required.approx and .approx.f32 supported on all target architectures.0.ftz.

Find the sine of the angle a (in radians). a.4 and later.f32 d. Input -Inf -subnormal -0.0 through 1. PTX ISA Notes sin. Target ISA Notes Examples Supported on all target architectures.ftz.0 +0.ftz introduced in PTX ISA version 1.PTX ISA Version 2.f32 introduced in PTX ISA version 1. sin.ftz}. a. sm_1x: Subnormal inputs and results to sign-preserving zero. sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.f32. Explicit modifiers .4.approx.0 +0. sin.f32 sa.f32 flushes subnormal inputs and results to sign-preserving zero.f32 defaults to sin. sin.ftz.approx.0 +0.0 Table 62.0.approx{.f32 implements a fast approximation to sine. sin. For PTX ISA versions 1. subnormal numbers are supported. d = sin(a). For PTX ISA version 1.9 in quadrant 00. 96 January 24.3.approx. 2010 .0 +subnormal +Inf NaN Result NaN -0. the .ftz.0 -0.0 NaN NaN The maximum absolute error is 2-20.approx modifier is required. Subnormal numbers: sm_20: By default.approx and .

January 24. a. cos.0 NaN NaN The maximum absolute error is 2-20. Input -Inf -subnormal -0. Explicit modifiers . Subnormal numbers: sm_20: By default.0 +1.0 through 1. Instruction Set Table 63. Target ISA Notes Examples Supported on all target architectures.approx.Chapter 8.0. cos.ftz}.9 in quadrant 00.f32 flushes subnormal inputs and results to sign-preserving zero.0 +1.3. cos. a.4 and later.f32 d. PTX ISA Notes cos. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz.approx and .f32.approx. Find the cosine of the angle a (in radians).f32 defaults to cos. the .approx{.ftz. subnormal numbers are supported. For PTX ISA version 1.ftz introduced in PTX ISA version 1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. cos.0 +subnormal +Inf NaN Result NaN +1. For PTX ISA versions 1. 2010 97 .0 +1. cos.approx modifier is required.ftz.f32 implements a fast approximation to cosine.4.f32 introduced in PTX ISA version 1.approx.f32 ca.0 +0. d = cos(a).

4.approx modifier is required.approx{.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.0.0 through 1. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +0.ftz. Subnormal numbers: sm_20: By default.PTX ISA Version 2.ftz introduced in PTX ISA version 1. the .approx.6 for mantissa.approx.f32. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.f32 defaults to lg2. 2010 .ftz. subnormal numbers are supported. PTX ISA Notes lg2. lg2. lg2.ftz.4 and later. 98 January 24. For PTX ISA versions 1.approx and . lg2.f32 implements a fast approximation to log2(a).ftz}. Input -Inf -subnormal -0.3. lg2. a. For PTX ISA version 1. Explicit modifiers . The maximum absolute error is 2-22. d = log(a) / log(2).f32 la. Target ISA Notes Examples Supported on all target architectures.approx.f32 Determine the log2 of a.f32 flushes subnormal inputs and results to sign-preserving zero. a. lg2.f32 introduced in PTX ISA version 1.0 Table 64.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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ftz}.eq. a. ge. lt. .r.i.b. @q setp. and higher-or-same may be used instead of lt.0 Table 67. unordered versions are included: equ. Semantics t = (a CmpOp b) ? 1 : 0. then these comparisons have the same result as their ordered counterparts. If both operands are numeric values (not NaN). respectively. Applies to all numeric types. leu. gtu. lt. p[|q]. neu.dtype. geu. and can be one of: eq. gt. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. hi. setp.ftz. lo.ftz}. The signed and unsigned comparison operators are eq.s64.type = { .s32.u32 p|q.pred variables. a. p[|q]. geu.b16. ls. The untyped. ltu.dtype.B) is one of: and. setp. le. Subnormal numbers: sm_20: By default. setp with . Integer Notes Floating Point Notes The ordered comparisons are eq. The comparison operator is a suffix on the instruction. hs equ.s32 setp. and (optionally) combine this result with a predicate value by applying a Boolean operator.ftz applies only to .u16. subnormal numbers are supported. {!}c.b32.n. the result is false. This result is written to the first destination operand.f64 supports subnormal numbers. q = BoolOp(!t. b. lt.BoolOp{. le.f32 flushes subnormal inputs to sign-preserving zero.and. ls. or. b.type setp. . . num. To aid comparison operations in the presence of NaN values. setp.f64 }. p.f32. ge. ltu. xor.CmpOp. If either operand is NaN. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. c). gt. Modifier .f32 comparisons. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. hi. leu. ne. If either operand is NaN. For unsigned values.f32 flushes subnormal inputs to sign-preserving zero. higher.PTX ISA Version 2.a. 2010 . The destinations p and q must be . num returns true if both operands are numeric values (not NaN).0. c). ge. loweror-same. 102 January 24. . . le. bit-size comparisons are eq and ne. . neu. . . . nan The Boolean operator BoolOp(A.dtype. and nan returns true if either operand is NaN. p = BoolOp(t. ne. gt. then the result of these comparisons is true. A related value computed using the complement of the compare result is written to the second destination operand. le.f64 source type requires sm_13 or later. the comparison operators lo.CmpOp{. gt. . sm_1x: setp.s16. and hs for lower. gtu. ne.u32.lt.type .u64. ge.b64.

negative zero equals zero. slct.dtype.u64.s32 slct{.0.u16.f64 requires sm_13 or later. c.s64. selp Syntax Comparison and Selection Instructions: selp Select between source operands.t. . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. If operand c is NaN. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . d = (c == 1) ? a : b. slct. .f32 comparisons.f32 flushes subnormal values of operand c to sign-preserving zero. B. . slct. c.r. and operand a is selected. . d. Operands d. 2010 103 .ftz.s16. slct.ftz applies only to .ftz.s32.s16.f32 d. otherwise b is stored in d. Instruction Set Table 68. .s32. . a.b16.dtype. @q selp. The selected input is copied to the output without modification.b64. C. . . based on the value of the predicate source operand. fval. slct Syntax Comparison and Selection Instructions: slct Select one source operand.dtype = { .type = { . Semantics Floating Point Notes January 24. For . . and b are treated as a bitsize type of the same width as the first instruction type. . selp. Subnormal numbers: sm_20: By default. the comparison is unordered and operand b is selected. . z. Table 69. b. Introduced in PTX ISA version 1. sm_1x: slct.f32 r0.ftz}.u64.f32 A. Description Conditional selection. val. .0.xp.u32. a is stored in d. Modifier . d = (c >= 0) ? a : b.s32 x.f64 }. operand c must match the second instruction type. If c ≥ 0.s32 selp. a.f64 }. and operand a is selected.s64. . based on the sign of the third operand.f32. a. . b otherwise.f32 flushes subnormal values of operand c to sign-preserving zero.f64 requires sm_13 or later. subnormal numbers are supported. slct. . selp. . .u16. .g.b32.dtype.f32 comparisons. b. . and b must be of the same type.p. c.u32. f0. a.u64. a.f32. . a is stored in d.Chapter 8. Operand c is a predicate.b16.b64. If c is True.b32.x.type d. b. Operands d.u32.dtype. y. .

2010 . performing bit-wise operations on operands of any type.7. xor.PTX ISA Version 2. provided the operands are of the same size. and not also operate on predicates. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. or.4. This permits bit-wise operations on floating point values without having to define a union to access the bits. Instructions and.0 8. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.

Introduced in PTX ISA version 1. and Syntax Logic and Shift Instructions: and Bitwise AND.b64 }.type d. Allowed types include predicate registers.b32. Supported on all target architectures. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.q. Instruction Set Table 70. and.b32 and.0. The size of the operands must match.pred.b32.type d. The size of the operands must match.fpvalue.0x80000000.b16. Table 71.b32 x. . b. sign. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.pred.pred p. Allowed types include predicate registers.Chapter 8.type = { . .0. Introduced in PTX ISA version 1.b32 mask mask.0x00010001 or. . or Syntax Logic and Shift Instructions: or Bitwise OR.b64 }.b16. a. . . 2010 105 . but not necessarily the type. . or. d = a & b. and.r. a.r.type = { . January 24. . or. b. Supported on all target architectures.q. d = a | b. but not necessarily the type.

but not necessarily the type. . not.q. Introduced in PTX ISA version 1. d. Table 73.b16.type = { . .b16 d.pred p. 2010 .a. . The size of the operands must match.b32.b32. Allowed types include predicates.b32 mask. xor. a.0 Table 72. . but not necessarily the type. xor. not Syntax Logic and Shift Instructions: not Bitwise negation. d = ~a. 106 January 24.x.PTX ISA Version 2. Introduced in PTX ISA version 1. . . .r. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.type d.0. not. Supported on all target architectures. a.0x0001.type d.b16. one’s complement.0.type = { .b32 d. .pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. cnot.b64 }. d = a ^ b.b64 }. . a.0. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.pred. d = (a==0) ? 1 : 0. not. Introduced in PTX ISA version 1.b64 }.type = { .mask. Table 74.b16. but not necessarily the type. Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b32. .q. Supported on all target architectures. The size of the operands must match. Allowed types include predicate registers. b.b32 xor. The size of the operands must match.type d. cnot.

s64 }. k.i.type d. . unsigned and untyped shifts fill with 0. PTX ISA Notes Target ISA Notes Examples Table 76.type = { .s32. a.u16 shr. PTX ISA Notes Target ISA Notes Examples January 24. The b operand must be a 32-bit value. . Supported on all target architectures.j. regardless of the instruction type. shr Syntax Logic and Shift Instructions: shr Shift bits right.b16. i.a.a. The b operand must be a 32-bit value.b64. . The sizes of the destination and first source operand must match. Introduced in PTX ISA version 1.s32 shr. zero-fill on right.2. d = a << b. Instruction Set Table 75. but not necessarily the type.b16 c. shr. shl. Introduced in PTX ISA version 1.b16. . Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.u64. .b32. but not necessarily the type.1. . Supported on all target architectures. shl Syntax Logic and Shift Instructions: shl Shift bits left. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. . shl.type d.i.u32. b. The sizes of the destination and first source operand must match.2. .Chapter 8. . shr. .s16. Signed shifts fill with the sign bit. sign or zero fill on left. 2010 107 .b32. Shift amounts greater than the register width N are clamped to N. b. d = a >> b.b32 q.type = { . a. Bit-size types are included for symmetry with SHL. Shift amounts greater than the register width N are clamped to N.b64 }. .0.0. .u16. regardless of the instruction type.

The isspacep instruction is provided to query whether a generic address falls within a particular state space window.5.7. Data Movement and Conversion Instructions These instructions copy data from place to place. possibly converting it from one format to another. st. Instructions ld. and st operate on both scalar and vector types. ld. ldu. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. or shared state spaces. and from state space to state space. and sust support optional cache operations. prefetchu isspacep cvta cvt 108 January 24. 2010 . The cvta instruction converts addresses between generic and global. mov. local.PTX ISA Version 2. suld.0 8.

cv Cache as volatile (consider cached system memory lines stale.7. evict-first. invalidates (discards) the local L1 line following the load.ca loads cached in L1.lu operation. The ld. but multiple L1 caches are not coherent for global data. and a second thread loads that address via a second L1 cache with ld. When ld. Cache Operators PTX 2. As a result of this request.lu Last use.lu instruction performs a load cached streaming operation (ld. The ld. Table 77. the cache operators have the following definitions and behavior. not L1). Global data is coherent at the L2 level.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. it performs the ld. . Use ld. and cache only in the L2 cache. likely to be accessed again.1. If one thread stores to global memory via one L1 cache. The ld. .cg to cache loads only globally. A ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. The compiler / programmer may use ld.Chapter 8.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. Instruction Set 8. For sm_20 and later. if the line is fully covered.cs. fetch again). 2010 109 . rather than the data stored by the first thread. any existing cache lines that match the requested address in L1 will be evicted. The default load instruction cache operation is ld. January 24. The cache operators require a target architecture of sm_20 or later.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. likely to be accessed once. Operator .ca. The ld.cg Cache at global level (cache in L2 and below. to allow the thread program to poll a SysMem location written by the CPU.cs Cache streaming.5. when applied to a local address. . which allocates cache lines in all levels (L1 and L2) with normal eviction policy.cv to a frame buffer DRAM address is the same as ld.lu load last use operation. bypassing the L1 cache. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. .0 introduces optional cache operators on load and store instructions.cs) on global addresses.cs is applied to a Local window address. the second thread may get stale L1 cache data.ca.

and a second thread in a different SM later loads from that address via a different L1 cache with ld. The default store instruction cache operation is st.cg to local memory uses the L1 cache. bypassing its L1 cache.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.wt store write-through operation applied to a global System Memory address writes through the L2 cache. the second thread may get a hit on stale L1 cache data.cg Cache at global level (cache in L2 and below. rather than get the data from L2 or memory stored by the first thread.cs Cache streaming.0 Table 78. and marks local L1 lines evict-first. Future GPUs may have globally-coherent L1 caches.wt Cache write-through (to system memory). The st.cg is the same as st. which writes back cache lines of coherent cache levels with normal eviction policy.PTX ISA Version 2.wb.ca loads. However. not L1). The driver must invalidate global L1 cache lines between dependent grids of thread arrays. In sm_20. st. Global stores bypass L1.wb could write-back global store data from L1. The st. . . bypassing the L1 cache.ca.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. regardless of the cache operation. likely to be accessed once.wt. to allow a CPU program to poll a SysMem location written by the GPU with st. and discard any L1 lines that match. If one thread stores to global memory.cg to cache global store data only globally. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. Operator . Addresses not in System Memory use normal write-back. 110 January 24. and cache only in the L2 cache. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. 2010 . in which case st. Use st. .wb for global data. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. but st.

and . Introduced in PTX ISA version 1. . Operand a may be a register. . Description .type mov.type = { . // address is non-generic. mov places the non-generic address of the variable (i.b64. 2010 111 .f32.e. .type mov. label.b16.s64.u16 mov.b32. The generic address of a variable in global. alternately. sreg. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. // get address of variable // get address of label or function .u16.const.v. d = &avar. mov.f64 }. d.global. the generic address of a variable declared in global. Instruction Set Table 79.a. immediate. local. d = &label.f32 mov. u. A. or function name.s32.f32 mov.1. variable in an addressable memory space..u32 d. local. For variables declared in .pred.0. . local. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. . A[5]. .Chapter 8.f64 requires sm_13 or later.u32 mov.local. or shared state space may be taken directly using the cvta instruction. a.e. d. Note that if the address of a device function parameter is moved to a register. or shared state space. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. . the address of the variable in its state space) into the destination register. special register. Semantics d = a. avar. Write register d with the value of a.0. k.s16.. d.u64. within the variable’s declared state space Notes Although only predicate and bit-size types are required.u32 mov. addr. i. ptr.type mov. the parameter will be copied onto the stack and the address will be in the local state space. mov. . label. d = sreg. mov.u32. myFunc. . .type d. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.shared state spaces. . Take the non-generic address of a variable in global. . ptr.

type d.y << 8) d = a. .b64 // pack two 32-bit elements into .b32 // pack two 16-bit elements into .PTX ISA Version 2. %x..y } = { a[0.g. a[24.x | (a. a[32. a[16.31] } // unpack 8-bit elements from . Description Write scalar register d with the packed value of vector register a.y.y } = { a[0.31].b16.b32.15]. lo.b}.31]. or write vector register d with the unpacked values from scalar register a.z.7].u32 x.0 Table 80.b16 { d. For bit-size types. 2010 . d.{a..b32 // pack four 16-bit elements into .w have type ..b.x | (a.hi are . a[8. {r.b8 r.x.. d.{x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).z.y..b have type . // // // // a.15].type = { .y } = { a[0. a[8. d. d.y << 16) | (a...b32 { d.b.x | (a. a[48.b64 { d. a[32.x | (a.a}.63] } // unpack 16-bit elements from .w}.y << 32) // pack two 8-bit elements into . .b64 { d.x | (a.47]. a.g.15] } // unpack 8-bit elements from .b64 mov.31] } // unpack 16-bit elements from .w << 48) d = a.. {lo.%r1. .x. a[16.u8 // unpack 32-bit elements from .y << 8) | (a.z. %r1. mov. mov. d.15].w } = { a[0.b64 112 January 24.y. d.7]. Supported on all target architectures.x..z << 16) | (a. d.x.z << 32) | (a.b32 mov..b16 // pack four 8-bit elements into .23].a have type . Semantics d = a.b32 mov. a[16..b32 { d..w << 24) d = a. d. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. d.u16 %x is a double.x.0.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.w } = { a[0.hi}.b32 %r1..b64 }.z.y.y << 16) d = a..

ld introduced in PTX ISA version 1. [a].f64 using cvt. .ss}{.cs. This may be used. and is zeroextended to the destination register width for unsigned and bit-size types. Addresses are zero-extended to the specified width as needed. .type ld{.e. d. . ld{. d. .cop = { .Chapter 8.const space suffix may have an optional bank number to indicate constant banks other than bank zero.volatile. Generic addressing may be used with ld. an address maps to the corresponding location in local or shared memory. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.ss}. Semantics d d d d = = = = a. The address size may be either 32-bit or 64-bit.b8. [a].type d.global and . an address maps to global memory unless it falls within the local memory window or the shared memory window. . . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. or the instruction may fault. the resulting behavior is undefined. Generic addressing and cache operations introduced in PTX ISA 2.shared }. 32-bit). .b64.. A destination register wider than the specified type may be used. In generic addressing.reg state space.f32. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.ss}{.volatile{. . perform the load using generic addressing. . Description Load register variable d from the location specified by the source address operand a in specified state space. If an address is not properly aligned.s8. to enforce sequential consistency between threads accessing shared memory. If no state space is given.v2.v4 }.volatile may be used with .s16.cg. *a.lu. Within these windows.f16 data may be loaded using ld.vec. for example. i.vec = { . .local. .volatile introduced in PTX ISA version 1. .f32 or .1.b32.s64.0. PTX ISA Notes January 24. the access may proceed by silently masking off low-order address bits to achieve proper rounding. 32-bit).type . an integer or bit-size type register reg containing a byte address. .u32. .e. or [immAddr] an immediate absolute byte address (unsigned.f64 }. . 2010 113 .u16.volatile{.ca.u8.type = { . . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type ld. . [a].ss}.cv }.volatile.b16. .b16. The value loaded is sign-extended to the destination register width for signed integers. ld.param.cop}. [a]. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.u64. . . The address must be naturally aligned to a multiple of the access size. The .cop}.s32. Cache operations are not permitted with ld. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . i. *(immAddr). ld.vec.global. .ss = { . and truncated if the register width exceeds the state space address width for the target architecture.0. *(a+immOff). and then converted to . d.shared spaces to inhibit optimization of references to volatile memory. Instruction Set Table 81.const. . .

b16 cvt. %r. 2010 .b32 ld.[p+4]. Generic addressing requires sm_20 or later. // negative offset %r.shared.[a].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.const. Cache operations require sm_20 or later.[buffer+64].local.[fs].v4.PTX ISA Version 2.0 Target ISA Notes ld.local.%r.global.const[4].[p].f64 requires sm_13 or later.[p+-8].s32 ld. // immediate address %r.b32 ld.f16 d.b64 ld.global. ld.b32 ld. // access incomplete array x. // load . x.[240]. d.f32 ld.f32. Q.

f32 Q.. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .b16. Addresses are zero-extended to the specified width as needed. .[p+4].u64. ldu{. d.v4. i.vec.vec = { .type = { .f32 or .Chapter 8. // load from address // vec load from address .type ldu{.s8.ss = { .global. *(immAddr).v2. If an address is not properly aligned.b16. The address size may be either 32-bit or 64-bit. Within these windows. [areg] a register reg containing a byte address. or the instruction may fault. A register containing an address may be declared as a bit-size type or integer type.f32 d. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. ldu.s32. . ldu. 32-bit). Semantics d d d d = = = = a. .0. 32-bit). .s64.ss}. 2010 115 . only generic addresses that map to global memory are legal. ldu.s16. .b64. The address must be naturally aligned to a multiple of the access size.b32. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.f16 data may be loaded using ldu. If no state space is given. The value loaded is sign-extended to the destination register width for signed integers. . . the resulting behavior is undefined. or [immAddr] an immediate absolute byte address (unsigned. and is zeroextended to the destination register width for unsigned and bit-size types.f64 using cvt.u32. For ldu. . i. Instruction Set Table 82.b32 d. Introduced in PTX ISA version 2. an address maps to global memory unless it falls within the local memory window or the shared memory window. In generic addressing. . [a]. // state space .ss}. [a]. . The data at the specified address must be read-only. .[p]. The addressable operand a is one of: [avar] the name of an addressable variable var. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .u8.v4 }.f64 }. and truncated if the register width exceeds the state space address width for the target architecture.b8. where the address is guaranteed to be the same across all threads in the warp.global }. ldu.[a]. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. and then converted to . perform the load using generic addressing.global.f32. PTX ISA Notes Target ISA Notes Examples January 24.type d. .e.u16. .reg state space. *(a+immOff). an address maps to the corresponding location in local or shared memory. *a. the access may proceed by silently masking off low-order address bits to achieve proper rounding.global. . A destination register wider than the specified type may be used.e.f64 requires sm_13 or later.

. Cache operations require sm_20 or later. i. Cache operations are not permitted with st. st{.b64. b. 32-bit). Generic addressing requires sm_20 or later. an address maps to global memory unless it falls within the local memory window or the shared memory window. [a].0. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.v2. or [immAddr] an immediate absolute byte address (unsigned.cg. Within these windows.shared }. . an address maps to the corresponding location in local or shared memory. . . If an address is not properly aligned.b8. 2010 .0 Table 83. The address size may be either 32-bit or 64-bit. The address must be naturally aligned to a multiple of the access size. perform the store using generic addressing. the access may proceed by silently masking off low-order address bits to achieve proper rounding. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .cop .u32.b16. 32-bit).volatile may be used with . Generic addressing and cache operations introduced in PTX ISA 2.reg state space. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. and truncated if the register width exceeds the state space address width for the target architecture.s64.wb.. PTX ISA Notes Target ISA Notes 116 January 24.s16. . . for example. .volatile.wt }.shared spaces to inhibit optimization of references to volatile memory. A source register wider than the specified type may be used. *(d+immOffset) = a. b.volatile{.u8.b16.local.ss}.f64 requires sm_13 or later. .f32.volatile{.type st.ss .0. { .type st{. This may be used. Addresses are zero-extended to the specified width as needed. *(immAddr) = a. . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. In generic addressing. .v4 }.cop}. to enforce sequential consistency between threads accessing shared memory.PTX ISA Version 2. .s32. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.type [a]. st introduced in PTX ISA version 1.volatile introduced in PTX ISA version 1. st.type = = = = {. b. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.global.cop}. .f16 data resulting from a cvt instruction may be stored using st.ss}{. { . i. Generic addressing may be used with st. . . . an integer or bit-size type register reg containing a byte address. [a].u16.1. .u64.ss}{. st. .f64 }.type . { .cs.s8. st. . The lower n bits corresponding to the instruction-type width are stored to memory.global and . If no state space is given.vec . [a]. *d = a.vec.e. or the instruction may fault. the resulting behavior is undefined. .ss}. b.vec. .volatile.b32.e. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Semantics d = a.

b.global.f32 st.v4. [p]. 2010 117 . Instruction Set Examples st.Q. // %r is 32-bit register // store lower 16 bits January 24.%r. [q+4].a. // immediate address %r.b32 st.a.b16 [a].%r.f32 st.r7.f16. [fs].local. [q+-8]. // negative offset [100].Chapter 8.b32 st.s32 st.s32 cvt.local.local.global.

2010 . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. // prefetch to data cache // prefetch to uniform cache . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. an address maps to global memory unless it falls within the local memory window or the shared memory window. an address maps to the corresponding location in local or shared memory. 32-bit).local }.space}. prefetch. prefetch{.global. prefetch and prefetchu require sm_20 or later. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . .L1. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch into the uniform cache requires a generic address.PTX ISA Version 2. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. the prefetch uses generic addressing. 32-bit). i. prefetchu. a register reg containing a byte address.global. 118 January 24. The address size may be either 32-bit or 64-bit.L1 [addr].L2 }. In generic addressing. and no operation occurs if the address maps to a local or shared memory location.0.level prefetchu.space = { . or [immAddr] an immediate absolute byte address (unsigned. in specified state space. and truncated if the register width exceeds the state space address width for the target architecture. [a].e. Addresses are zero-extended to the specified width as needed.L1 [ptr].0 Table 84. If no state space is given. Within these windows. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. A prefetch to a shared memory location performs no operation.L1 [a]. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.level = { .

Chapter 8.u64 or cvt.size = { .global isspacep.space. PTX ISA Notes Target ISA Notes Examples Table 86.pred . or vice-versa. or shared state space.size p. Description Convert a global.size .u64. or shared state space. The source and destination addresses must be the same size. Introduced in PTX ISA version 2.local. The source address operand must be a register of type . For variables declared in global.genptr.global.local isspacep. local.shared. or shared address. or vice-versa. . // local. or shared address cvta. sptr. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. . cvta.to. . gptr.space p. var.u32 or .shared }. . the generic address of the variable may be taken using cvta.u32 p.space = { . // get generic address of svar cvta. cvta requires sm_20 or later. A program may use isspacep to guard against such incorrect behavior. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. // result is . // convert to generic address // get generic address of var // convert generic address to global.pred. local.shared }.0. p.space.u32.global.local.space.to. cvta.size cvta. lptr. When converting a generic address into a global.u64. local. Instruction Set Table 85.0. isshrd.u32. Use cvt.u32 gptr. a. local.lptr.local. p. local. islcl. isspacep. a. January 24.space = { . . a.u64 }. cvta. . isspacep requires sm_20 or later.shared isglbl. The destination register must be of type . svar. 2010 119 . the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32 p. or shared address to a generic address. Take the generic address of a variable declared in global. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. or shared state space to generic.u32 to truncate or zero-extend addresses.global. isspacep. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

d. .frnd = { . sm_1x: For cvt.ftz}{.s32.sat is redundant.f32.. a. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.s64. 120 January 24.f32 float-to-integer conversions and cvt.4 and earlier. .f32 float-tofloat conversions with integer rounding.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.rp }.irnd}{.f16. Saturation modifier: .ftz. For float-to-integer conversions.rni.u64. . . . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.dtype.frnd}{. . . Description Semantics Integer Notes Convert between different types and sizes. 2010 .rm.rni round to nearest integer.atype d.s8. subnormal inputs are flushed to signpreserving zero. subnormal numbers are supported.. .rmi. subnormal inputs are flushed to signpreserving zero.rzi. and for same-size float-tofloat conversions where the value is rounded to an integer.irnd = { . Integer rounding modifiers: .u16.sat}. Note: In PTX ISA versions 1. . the result is clamped to the destination range by default. .rn.ftz. . the . i. The compiler will preserve this behavior for legacy PTX code. a.sat For integer destination types.sat}.ftz}{.f32.dtype.MAXINT for the size of the operation. Integer rounding is required for float-to-integer conversions.u8. .f32. d = convert(a).f32 float-tofloat conversions with integer rounding.ftz modifier may be specified in these cases for clarity.dtype. The optional .dtype = .rz. . .s16. cvt{. .atype cvt{. Note that saturation applies to both signed and unsigned integer types. choosing even integer if source is equidistant between two integers. i.PTX ISA Version 2. .ftz.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. // integer rounding // fp rounding .e. .e.rzi round to nearest integer in the direction of zero .0 Table 87. Integer rounding is illegal in all other instances. .rmi round to nearest integer in direction of negative infinity .sat limits the result to MININT.ftz.atype = { . . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.f32 float-to-integer conversions and cvt.f64 }. . .dtype.rpi }.u32. For cvt.

Subnormal numbers: sm_20: By default. and cvt. and for integer-to-float conversions. if the PTX . Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.version is 1. .f64.y.i. result is fp cvt.rz mantissa LSB rounds towards zero . NaN results are flushed to positive zero.f32. The compiler will preserve this behavior for legacy PTX code.0. cvt to or from . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.rm mantissa LSB rounds towards negative infinity . and . Saturation modifier: . The result is an integral value.s32 f.r. // round to nearest int.4 or earlier. // float-to-int saturates by default cvt. stored in floating-point format.sat limits the result to the range [0.f32. Floating-point rounding is illegal in all other instances.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. Modifier . The optional . cvt.f32.y.f32.f64 j. 2010 121 . cvt.f32.f32 x.Chapter 8.rni.ftz behavior for sm_1x targets January 24. Floating-point rounding modifiers: .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).sat For floating-point destination types.0].rn mantissa LSB rounds to nearest even .f32 x. Note: In PTX ISA versions 1. Specifically. .ftz modifier may be specified in these cases for clarity.f16.f64 requires sm_13 or later. 1.f64 types.f16.f16.f32 instructions.s32.4 and earlier.0.f32. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . subnormal numbers are supported. cvt. Introduced in PTX ISA version 1. The operands must be of the same size. // note .f32. Applies to .

The advantage of unified mode is that it allows 128 samplers.b32 r5. div.7. texture and sampler information is accessed through a single . r2. [tex1. r1.f32 {r1.target texmode_independent . add.r4}.f32 r1. sampler. and surfaces. The advantage of independent mode is that textures and samplers can be mixed and matched. the file is assumed to use unified mode. allowing them to be defined separately and combined at the site of usage in the program.entry compute_power ( . and surface descriptors..f32. r5. Ability to query fields within texture. In the independent mode. = nearest width height tsamp1. A PTX module may declare only one texturing mode.. In the unified mode. r5. sampler. sampler.f32 r3. mul. 2010 .height.2d.b32 r6.samplerref tsamp1 = { addr_mode_0 filter_mode }.v4. r3. add. PTX has two modes of operation. Texture and Surface Instructions This section describes PTX instructions for accessing textures. If no texturing mode is declared.6.texref handle. with the restriction that they correspond 1-to-1 with the 128 possible textures. and surface descriptors. .texref tex1 ) { txq. add. . The texturing mode is selected using .f2}]. Texturing modes For working with textures and samplers. and surface descriptors.param . r5.global . and surface descriptors: • • • Static initialization of texture.r2. 122 January 24. cvt. // get tex1’s tex.PTX ISA Version 2.u32 r5. r6. {f1. sampler.target options ‘texmode_unified’ and ‘texmode_independent’. r4. r1. // get tex1’s txq. Module-scope and per-entry scope definitions of texture. r3. [tex1]. PTX supports the following operations on texture. r1.f32 r1.f32.0 8. [tex1]. } = clamp_to_border.u32 r5. texture and sampler information each have their own handle. samplers.f32 r1. Example: calculate an element’s power contribution as element’s power/total number of elements. .width. but the number of samplers is greatly restricted to 16.r3.

r4}. c].. If no sampler is specified. sampler_x.v4 coordinate vectors are allowed for any geometry. Instruction Set These instructions provide access to texture and surface memory. .r3. with the extra elements being ignored. [a.5.v4. Description Texture lookup using a texture coordinate vector. tex txq suld sust sured suq Table 88. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.v4. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.3d. A texture base address is assumed to be aligned to a 16-byte address. Unified mode texturing introduced in PTX ISA version 1. c]. .1d. the resulting behavior is undefined. is a two-element vector for 2d textures. {f1}]. [a.f2. the square brackets are not required and .s32. If an address is not properly aligned.btype d.dtype. d.v4.dtype = { . . i.r2. {f1. . . An optional texture sampler b may be specified. .3d }.Chapter 8. [tex_a. // Example of independent mode texturing tex.e.geom.f3. or the instruction may fault. the sampler behavior is a property of the named texture.r4}.s32 {r1.btype = { .f32 {r1.s32. Operand c is a scalar or singleton tuple for 1d textures. PTX ISA Notes Target ISA Notes Examples January 24. b. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.s32.v4.btype tex.f4}]. The instruction always returns a four-element vector of 32-bit values. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. the access may proceed by silently masking off low-order address bits to achieve proper rounding.dtype. 2010 123 . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.0. .u32.r2.f32 }.geom.r3. where the fourth element is ignored. tex. //Example of unified mode texturing tex. Notes For compatibility with prior versions of PTX. [tex_a.1d. and is a four-element vector for 3d textures.geom = { .2d. // explicit sampler . Supported on all target architectures.f32 }.s32.

addr_mode_0 .5. d. linear } Integer from enum { wrap.addr_mode_1 . mirror.normalized_coords . Description Query an attribute of a texture or sampler. [a].width . clamp_to_edge.width. txq.height. 2010 .width.squery.0 Table 89. txq. .depth . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. . [tex_A]. // texture attributes // sampler attributes .filter_mode. . Query: .filter_mode . // unified mode // independent mode 124 January 24.depth.addr_mode_0.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).b32 %r1. [tex_A]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.tquery.height . In unified mode. clamp_ogl.PTX ISA Version 2. addr_mode_1. sampler attributes are also accessed via a texref argument.b32 %r1.addr_mode_0. and in independent mode sampler attributes are accessed via a separate samplerref argument.b32 txq. [a]. Supported on all target architectures. .squery = { .b32 %r1. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. txq.samplerref variable. . Integer from enum { nearest.filter_mode.b32 d.tquery = { . [smpl_B]. txq.texref or . Operand a is a .normalized_coords }. addr_mode_2 }.

The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. . and A components of the surface format.w}]. Description Load from surface memory using a surface coordinate vector. [a.geom{. suld.trap introduced in PTX ISA version 1.v2. suld. .clamp field specifies how to handle out-of-bounds addresses: . or FLOAT data.trap.v4.surfref variable.p .cop}. then .z.f2.3d requires sm_20 or later. // for suld.b. the surface sample elements are converted to .b. If an address is not properly aligned.u32. // formatted . 2010 125 .b32. . suld.Chapter 8. .b .f32.v4 }.p is currently unimplemented. suld.b32. [a.1d. additional clamp modifiers.cop .s32 is returned.zero }. . then . size and type conversion is performed as needed to convert from the surface sample format to the destination type. sm_1x targets support only the .b32. .b64 }. b].u32. and the size of the data transfer matches the size of destination operand d.dtype . B.u32.b64. b].b16.f32 is returned.b. . if the surface format contains UINT data. .p.ca.trap clamping modifier. // for suld. A surface base address is assumed to be aligned to a 16-byte address. .y.. G.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. and is a four-element vector for 3d surfaces. . // cache operation none. if the surface format contains SINT data.v2. Destination vector elements corresponding to components that do not appear in the surface format are not written. or the instruction may fault. SNORM.f32.1d. [surf_A. {x}]. or . the access may proceed by silently masking off low-order address bits to achieve proper rounding. suld.cs. or .clamp . .dtype.p. . .f32 based on the surface format as follows: If the surface format contains UNORM. Target ISA Notes Examples January 24.s32. .clamp = = = = = = { { { { { { d.3d }. the resulting behavior is undefined. suld.f4}. Instruction Set Table 90.r2}.f32 }.geom{. . .dtype .s32.b8 .b performs an unformatted load of binary data. The .s32.e. suld. suld Syntax Texture and Surface Instructions: suld Load from surface memory. Operand b is a scalar or singleton tuple for 1d surfaces.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. and cache operations introduced in PTX ISA version 2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32.2d.0.cg. . suld.vec .cop}. where the fourth element is ignored. Operand a is a . Cache operations require sm_20 or later.f3.vec.dtype.v4.trap suld.clamp. .u32 is returned.geom . then . {f1. // unformatted d.trap . If the destination type is . Coordinate elements are of type . The lowest dimension coordinate represents a sample offset rather than a byte offset.p. . [surf_B. {x. If the destination base type is . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap {r1.p requires sm_20 or later.5. i.3d. is a two-element vector for 2d surfaces.b supported on all target architectures.clamp suld.clamp . suld.cv }.

These elements are written to the corresponding surface sample components.. then . or FLOAT data.{u32.b supported on all target architectures. c.s32.1d. The .geom{. sust. i.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.cop}. {x. B. If the source base type is . Surface sample components that do not occur in the source vector will be written with an unpredictable value.cop .s32.f32} are currently unimplemented.b16.cg.ctype.u32 is assumed. . Source elements that do not occur in the surface sample are ignored.geom{. sust. {x}].e.0. G.geom . . or the instruction may fault.w}]. The source data is then converted from this type to the surface sample format. where the fourth element is ignored.trap clamping modifier.v4.3d. Coordinate elements are of type . additional clamp modifiers.vec . . if the surface format contains SINT data.p.wb. size and type conversions are performed as needed between the surface sample format and the destination type.v4 }. sust.0 Table 91. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.r2}.5.b // for sust. and is a four-element vector for 3d surfaces.s32. [a. .b.b. .f2. . sust.f32 is assumed. the resulting behavior is undefined.3d }. sust.v2. .p.p. and A surface components.clamp .b performs an unformatted store of binary data. sust. Target ISA Notes Examples 126 January 24. If an address is not properly aligned. .clamp.v2. . The size of the data transfer matches the size of source operand c. then .ctype.b64 }. sust. . A surface base address is assumed to be aligned to a 16-byte address.vec. sust.p. . Cache operations require sm_20 or later.f32.cop}.f32. b]. sust.f3.1d.surfref variable. b]. The lowest dimension coordinate represents a sample offset rather than a byte offset. 2010 . sust Syntax Texture and Surface Instructions: sust Store to surface memory.zero }. . // unformatted // formatted .PTX ISA Version 2. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Operand a is a .s32 is assumed.b8 . . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.clamp = = = = = = { { { { { { [a.trap sust.ctype . or .clamp field specifies how to handle out-of-bounds addresses: . Operand b is a scalar or singleton tuple for 1d surfaces.2d. and cache operations introduced in PTX ISA version 2. if the surface format contains UINT data. c. .trap. SNORM.u32.wt }.s32. // for sust.p performs a formatted store of a vector of 32-bit data values to a surface sample.f4}. . The source vector elements are interpreted left-to-right as R.3d requires sm_20 or later. . {f1. sm_1x targets support only the . is a two-element vector for 2d surfaces.vec.clamp sust.b.z.p Description Store to surface memory using a surface coordinate vector.b64.f32 }. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b32.cs.y.trap [surf_A.u32.b32.trap . .p requires sm_20 or later.trap introduced in PTX ISA version 1. then . . none.clamp . .b32.ctype . [surf_B. . {r1. If the source type is .

{x.b .clamp . .geom.y}].and.b. then . sured requires sm_20 or later. r1. if the surface format contains SINT data.u32 based on the surface sample format as follows: if the surface format contains UINT data. then .s32 types. is a two-element vector for 2d surfaces. January 24.u64. where the fourth element is ignored.add. .1d.p. .b32. Reduction to surface memory using a surface coordinate vector.geom. // for sured. and the data is interpreted as . The instruction type is restricted to . .b32. min and max apply to .zero }. The . // sample addressing .min. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. {x}].ctype = { . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.ctype.s32 is assumed.trap .u32 is assumed.1d. or .u32.add. and . .u32.2d. The lowest dimension coordinate represents a sample offset rather than a byte offset. .p.trap [surf_A.ctype = { .u64 data.u32.op.s32 types.or }.s32. . .s32.c. [surf_B. A surface base address is assumed to be aligned to a 16-byte address.b]. .p .op.min.b]. // for sured.b32 type.clamp [a.e.2d. .p performs a reduction on sample-addressed 32-bit data.surfref variable.u32.u32 and .trap. 2010 127 .clamp [a.u64.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If an address is not properly aligned.0. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .clamp. .max.trap sured. operations and and or apply to .s32 or . the resulting behavior is undefined. or the instruction may fault. and is a four-element vector for 3d surfaces. i.b performs an unformatted reduction on .b32 }. .b. // byte addressing sured.b32 }..Chapter 8. .3d }. . Operand a is a . sured. Coordinate elements are of type .ctype.s32. Operand b is a scalar or singleton tuple for 1d surfaces. sured. sured.clamp field specifies how to handle out-of-bounds addresses: . the access may proceed by silently masking off low-order address bits to achieve proper rounding. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. r1. Instruction Set Table 92. sured.clamp = { .c. Operations add applies to .op = { .geom = { .b32. .

depth }.5.b32 d. suq.height .width.query = { . Description Query an attribute of a surface. . [a]. 128 January 24. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. . Operand a is a .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.height.width .query.surfref variable.width. [surf_A].b32 %r1. 2010 . Supported on all target architectures. Query: .0 Table 93. suq.PTX ISA Version 2. .

ratio.7.f32 @!p div. Introduced in PTX ISA version 1.7. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. setp. Supported on all target architectures. 2010 129 .c.x.0.y. Supported on all target architectures. p. Execute an instruction or instruction block for threads that have the guard predicate true. {} Syntax Description Control Flow Instructions: { } Instruction grouping.a. } PTX ISA Notes Target ISA Notes Examples Table 95.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. used primarily for defining a function body.f32 @q bra L23. Instruction Set 8.Chapter 8. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. If {!}p then instruction Introduced in PTX ISA version 1. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. { instructionList } The curly braces create a group of instructions.eq. Threads with a false guard predicate do nothing.0.b.s32 a. mov. { add.s32 d.0. @{!}p instruction.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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0. All threads in the warp are stalled until the barrier completes.arrive.and). and any-thread-true (. bar.red delays the executing threads (similar to bar. thread count. a{. bar.{arrive. b.or).and and . In conditionally executed code. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. a.popc). Execution in this case is unpredictable. Once the barrier count is reached. operands p and c are predicates.arrive using the same active barrier.. and then safely read values stored by other threads prior to the barrier.red also guarantee memory ordering among threads identical to membar.popc is the number of threads with a true predicate.red. it is as if all the threads in the warp have executed the bar instruction. and d have type . bar.sync or bar. b}. Instruction Set Table 100. Thus.op = { . Register operands. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. and bar. threads within a CTA that wish to communicate via memory can store to memory. if any thread in a warp executes a bar instruction. January 24.version 2. Barriers are executed on a per-warp basis as if all the threads in a warp are active. 2010 133 . b}. thread count.and. and bar. PTX ISA Notes Target ISA Notes Examples bar. it simply marks a thread's arrival at the barrier. b}. bar. Note that a non-zero thread count is required for bar.sync and bar.sync and bar. p.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. In addition to signaling its arrival at the barrier. Operands a. bar.sync bar.{arrive. .popc.sync 0.red} introduced in PTX .arrive a{. all threads in the CTA participate in the barrier.red instruction.red performs a reduction operation across threads. Description Performs barrier synchronization and communication within a CTA. Register operands.cta. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). while . Operand b specifies the number of threads participating in the barrier. {!}c.red} require sm_20 or later. the waiting threads are restarted without delay. and the barrier is reinitialized so that it can be immediately reused. If no thread count is specified.15.op.u32 bar.red should not be intermixed with bar. d. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.red performs a predicate reduction across the threads participating in the barrier.or }. Only bar. The reduction operations for bar. the bar.arrive does not cause any waiting by the executing threads. When a barrier completes. all-threads-true (.sync or bar.0.sync) until the barrier count is met.Chapter 8. bar. Each CTA instance has sixteen barriers numbered 0. {!}c. The barrier instructions signal the arrival of the executing threads at the named barrier. bar.u32. execute a bar. The result of .red are population-count (.red. the optional thread count must be a multiple of the warp size. bar. Thus.sync with an immediate barrier number is supported for sm_1x targets. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. b. the final value is written to the destination register in all threads waiting at the barrier.sync without a thread count introduced in PTX ISA 1. bar. Since barriers are executed on a per-warp basis. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).pred . a{.

gl will typically have a longer latency than membar. by st.level = { . A memory write (e. .gl} supported on all target architectures.cta. this is the appropriate level of membar. and memory reads by this thread can no longer be affected by other thread writes.sys }.4. membar. membar. membar. . Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar.g. PTX ISA Notes Target ISA Notes Examples membar.sys introduced in PTX . membar.level.0. that is.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.{cta.gl.version 1. membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. 134 January 24.cta. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.PTX ISA Version 2.cta. membar.sys. membar.cta Waits until all prior memory writes are visible to other threads in the same CTA. level describes the scope of other clients for which membar is an ordering event.{cta. global. membar. A memory read (e.gl.gl} introduced in PTX .gl. or system memory level.sys Waits until all prior memory requests have been performed with respect to all clients. 2010 . red or atom) has been performed when the value written has become visible to other clients at the specified level.0 Table 101. For communication between threads in different CTAs or even different SMs. including thoses communicating via PCI-E such as system and peer-to-peer memory. membar. when the previous value can no longer be read.version 2. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.sys will typically have much longer latency than membar.sys requires sm_20 or later. membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. . membar.g.

. 32-bit operations.inc.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and exch (exchange).f32. d. and truncated if the register width exceeds the state space address width for the target architecture. . . i. Operand a specifies a location in the specified state space. .b64. . or the instruction may fault.b].space}.e. a de-referenced register areg containing a byte address. Instruction Set Table 102. The integer operations are add.b32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . cas (compare-and-swap).shared }.s32. . by inserting barriers between normal stores and atomic operations to a common address. an address maps to the corresponding location in local or shared memory.min. . atom{. .s32. b. If no state space is given.exch to store to locations accessed by other atomic operations. min. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. 2010 135 . accesses to local memory are illegal..or.op.type = { .g. min. . The inc and dec operations return a result in the range [0. xor. performs a reduction operation with operand b and the value in location a.add. . overwriting the original value. perform the memory accesses using generic addressing. or [immAddr] an immediate absolute byte address. A register containing an address may be declared as a bit-size type or integer type. . [a]. . or. e. The address must be naturally aligned to a multiple of the access size.xor. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.u32. .global. or by using atom. Addresses are zero-extended to the specified width as needed.b32 only . . . For atom. b. The bit-size operations are and. The floating-point operations are add.add. dec. and max operations are single-precision.s32.f32 Atomically loads the original value at location a into destination register d.space}.Chapter 8. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. January 24. .b32.e. In generic addressing.. If an address is not properly aligned.u32 only . .and. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and stores the result of the specified operation at location a.max }. [a].f32 }. . min.exch. Within these windows.u32.op. The floating-point add.u32.dec. .u64. inc. .type d. Description // // // // // .space = { . and max. c. . an address maps to global memory unless it falls within the local memory window or the shared memory window. i.u64 . max.type atom{.cas. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.op = { .b64 . . The address size may be either 32-bit or 64-bit. atom.

atom. s) = (r >= s) ? 0 dec(r. b.s32 atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. 2010 . 64-bit atom.s.f32.add.1. : r. atom.0.my_new_val.cas.shared requires sm_12 or later. d.max.b32 d.f32 requires sm_20 or later.t) = (r == s) ? t operation(*a.my_val. : r-1.PTX ISA Version 2. b).[x+4].f32 atom.exch} requires sm_12 or later.global. atom.global requires sm_11 or later. c) operation(*a.cas. Introduced in PTX ISA version 1. atom. Use of generic addressing requires sm_20 or later. 64-bit atom.[p].shared. s) = (r > s) ? s exch(r. atom. s) = s.0.{add.max} are unimplemented. : r+1. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.add. *a = (operation == cas) ? : } where inc(r.{min.[a]. Release Notes Examples @p 136 January 24.0 Semantics atomic { d = *a.shared operations require sm_20 or later. d. cas(r.global.

. a de-referenced register areg containing a byte address.add. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32.type [a].space}.or. max. and max. dec. red.max }.u32 only .op. . b). perform the memory accesses using generic addressing. .global. If an address is not properly aligned.f32 }. red{. the resulting behavior is undefined. The floating-point add. Within these windows. .dec. . Addresses are zero-extended to the specified width as needed. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u64 .u32. Description // // // // .b32 only . If no state space is given.add.u32. . For red. where inc(r. . e. The floating-point operations are add.b32.space = { . an address maps to the corresponding location in local or shared memory.shared }. 2010 137 .f32. or [immAddr] an immediate absolute byte address.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.xor. or. or the instruction may fault. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.min.u64.u32. inc. min. . .g. an address maps to global memory unless it falls within the local memory window or the shared memory window. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. . and xor.. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. b.. min. .b]. Semantics *a = operation(*a.Chapter 8. . i. Operand a specifies a location in the specified state space. .s32. i. . by inserting barriers between normal stores and reduction operations to a common address. overwriting the original value. dec(r.exch to store to locations accessed by other reduction operations. The bit-size operations are and. In generic addressing. Instruction Set Table 103. s) = (r >= s) ? 0 : r+1. . and truncated if the register width exceeds the state space address width for the target architecture. . and stores the result of the specified operation at location a. s) = (r > s) ? s : r-1.s32. Notes Operand a must reside in either the global or shared state space. A register containing an address may be declared as a bit-size type or integer type. January 24. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The integer operations are add. and max operations are single-precision. The address must be naturally aligned to a multiple of the access size.inc. . . The address size may be either 32-bit or 64-bit. 32-bit operations.type = { .and. .e. or by using atom. The inc and dec operations return a result in the range [0. min. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.b64. accesses to local memory are illegal. .e.f32 Performs a reduction operation with operand b and the value in location a.op = { .

[p].shared operations require sm_20 or later. red.b32 [a]. red.global.shared.shared requires sm_12 or later.f32.PTX ISA Version 2.global. red. [x+4].s32 red.global requires sm_11 or later red.2. red.max} are unimplemented.max.and.add.my_val. 64-bit red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.1.add requires sm_12 or later. Release Notes Examples @p 138 January 24.add.0.{min.f32 requires sm_20 or later.f32 red. 2010 . Use of generic addressing requires sm_20 or later. 64-bit red.

vote. Instruction Set Table 104.any.ballot. .uni. vote. Negate the source predicate to compute . vote requires sm_12 or later. The reduction modes are: .b32 p.uni. . Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. returns bitmask .none. not across an entire CTA.p. where the bit position corresponds to the thread’s lane id.all True if source predicate is True for all active threads in warp.not_all.pred vote.ballot.pred d. Negating the source predicate also computes .b32 requires sm_20 or later. The destination predicate value is the same across all threads in the warp. 2010 139 . . p.mode. // ‘ballot’ form.q. Negate the source predicate to compute .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.2. . r1.all.ballot. In the ‘ballot’ form. Note that vote applies to threads in a single warp.Chapter 8.any True if source predicate is True for some active thread in warp.q.all.b32 d. // get ‘ballot’ across warp January 24.mode = { .uni }. vote. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. vote. {!}a.pred vote. Description Performs a reduction of the source predicate across threads in a warp.ballot. vote.uni True if source predicate has the same value in all active threads in warp. {!}a.

asel}. optionally clamp the result to the range of the destination type.b2.btype{. to produce signed 33-bit input values. half-word. The sign of the intermediate result depends on dtype. Video Instructions All video instructions operate on 32-bit register operands.7.atype.dsel. b{.h1 }.b3. .bsel = { . 2. atype.btype{. 3.u32. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. 2010 .add.9. // 32-bit scalar operation. b{. 140 January 24.h0.s32 }.dtype. The type of each operand (. c. The primary operation is then performed to produce an . 4. all combinations of dtype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. a{.atype.dtype. the input values are extracted and signor zero. c. a{.atype = .sat} d.bsel}. . . with optional secondary operation vop. . .secop = { . Using the atype/btype and asel/bsel specifiers.asel}.u32 or .dsel = .dtype.btype = { .b1.s34 intermediate result. extract and sign. perform a scalar arithmetic operation to produce a signed 34-bit result. vop. . .btype{.sat} d.min. The general format of video instructions is as follows: // 32-bit scalar operation.sat}.extended internally to . with optional data merge vop.s33 values.or zero-extend byte. b{. or word values from its source operands.s32) is specified in the instruction type. and btype are valid.asel}.bsel}.bsel}.atype.0 8. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.max }. . a{.asel = .PTX ISA Version 2. . The source and destination operands are all 32-bit registers.secop d. taking into account the subword destination size in the case of optional data merging. .b0. .dtype = . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).

S8_MAX. . tmp. . . Bool sat. .s33 c) { switch ( secop ) { . U16_MIN ). switch ( dsel ) { case .Chapter 8. Modifier dsel ) { if ( !sat ) return tmp. . c). U16_MAX.s33 optSecOp(Modifier secop. S32_MIN ).h1: return ((tmp & 0xffff) << 16) case . S8_MIN ).h0: return ((tmp & 0xffff) case . The sign of the c operand is based on dtype.b1. c).b2: return ((tmp & 0xff) << 16) case . c). . tmp.s33 tmp.b2. . .b0: return ((tmp & 0xff) case . . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). S16_MAX.b0.b3: if ( sign ) return CLAMP( else return CLAMP( case . c).min: return MIN(tmp. tmp.b3: return ((tmp & 0xff) << 24) default: return tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. The lower 32-bits are then written to the destination operand. default: return tmp.s33 optSaturate( . S16_MIN ). c). . Instruction Set .s33 optMerge( Modifier dsel. S32_MAX.b1: return ((tmp & 0xff) << 8) case .h0.s33 c ) switch ( dsel ) { case .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.add: return tmp + c. U32_MAX. } } . tmp. c). U8_MAX. 2010 141 . Bool sign. U8_MIN ).s33 tmp.max return MAX(tmp. tmp. c). as shown in the following pseudocode. .s34 tmp. January 24. U32_MIN ).

. tb ).dsel. Integer byte/half-word/word minimum / maximum.h0.b3.h0.asel = .sat} d.dtype. Semantics // saturate. // 32-bit scalar operation. tb = partSelectSignExtend( b. . dsel ). { . r3. c. isSigned(dtype). . Video Instructions: vadd. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.h0. d = optSecondaryOp( op2. . vabsdiff.s32. tmp = MAX( ta. vsub.s32.bsel}. // 32-bit scalar operation. btype. vadd. r2. . .s32.btype = { .op2 d.atype. a{.dtype .h1. vsub. r3.b0.add r1. r2.sat vmin.bsel = { .b0. tmp = | ta – tb |.s32.0.atype.bsel}. c.u32. r2.s32. vmin.vop .op2 Description = = = = { vadd.s32. r3.sat vsub. r1. . vmax }.btype{. vmax require sm_20 or later. bsel ).min.b2.h1. vop.or zero-extend based on source operand type ta = partSelectSignExtend( a. .sat. tb ). tmp. vmax Syntax Integer byte/half-word/word addition / subtraction. r3. c ). tmp = MIN( ta. a{. c ).asel}.0 Table 105. c. . atype. vabsdiff. tmp = ta – tb.PTX ISA Version 2.add.sat} d. asel ).b0.dtype. Perform scalar arithmetic operation with optional saturate. // optional secondary operation d = optMerge( dsel. . with optional secondary operation vop. vmin.b2.s32. // optional merge with c operand 142 January 24.s32 }.h1 }. b{. a{.sat vabsdiff. vsub vabsdiff vmin. 2010 .dsel .bsel}. sat. . tmp. r2. vadd. Integer byte/half-word/word absolute value of difference. c.btype{.u32. vmax vadd. vabsdiff.asel}. b{.atype. and optional secondary arithmetic operation or subword data merge.b1. taking into account destination type and merge operations tmp = optSaturate( tmp. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. // extract byte/half-word/word and sign.s32.s32.max }. b{.asel}. vsub.atype = . with optional data merge vop. vmin.s32.dtype.btype{.sat}. r1. r1.u32.

clamp .atype = { . Left shift fills with zero.atype.mode}. c ).min.wrap }.Chapter 8. Video Instructions: vshl. b{. d = optSecondaryOp( op2. r3. vshr vshl.vop . b{. dsel ).sat}{. c.bsel}. isSigned(dtype).u32.mode . vshr Syntax Integer byte/half-word/word left / right shift. vshr require sm_20 or later. January 24. . r2. r2.u32.u32.u32{.dtype. vshr }. 2010 143 . .b0. if ( mode == .b1. vshr: Shift a right by unsigned amount in b with optional saturate. . // 32-bit scalar operation.b3. a{. } // saturate. and optional secondary arithmetic operation or subword data merge. sat.bsel}. asel ).asel}.dtype.dsel .h1.dsel. Signed shift fills with the sign bit.asel}. { . with optional data merge vop. taking into account destination type and merge operations tmp = optSaturate( tmp. unsigned shift fills with zero.op2 Description = = = = = { vshl.add.max }. with optional secondary operation vop.u32. r3. . c ). // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.bsel}. vshl: Shift a left by unsigned amount in b with optional saturate. a{. atype.atype.u32.0. switch ( vop ) { case vshl: tmp = ta << tb.asel}. . r1. if ( mode == .u32{.s32 }.mode} d. a{. c.s32.dtype.wrap r1.dtype .h0.u32. case vshr: tmp = ta >> tb.wrap ) tb = tb & 0x1f.mode} d.atype. { . . tb = partSelectSignExtend( b. vshl.h1 }. vshl. tmp. . bsel ).sat}{.u32 vshr. Semantics // extract byte/half-word/word and sign. // default is . .sat}{.clamp && tb > 32 ) tb = 32.or zero-extend based on source operand type ta = partSelectSignExtend( a.op2 d. b{.asel = .bsel = { . // optional secondary operation d = optMerge( dsel.clamp. . and optional secondary arithmetic operation or subword data merge. // 32-bit scalar operation. .b2. vop. Instruction Set Table 106. . . tmp.u32{.

final signed (S32 * S32) + S32 // intermediate signed. final signed (U32 * S32) .u32.b0. {-}a{.S32 // intermediate signed. Source operands may not be negated in . final signed (S32 * S32) . Depending on the sign of the a and b operands. 2010 . otherwise. The final result is unsigned if the intermediate result is unsigned and c is not negated. {-}c. .atype = . and the operand negates.scale = { .btype. final unsigned -(U32 * U32) + S32 // intermediate signed.atype. That is. Description Calculate (a*b) + c. which is used in computing averages. . final signed (U32 * S32) + S32 // intermediate signed.dtype.po) computes (a*b) + c + 1. . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. (a*b) is negated if and only if exactly one of a or b is negated.bsel = { .shr15 }. c.S32 // intermediate signed.asel}. final signed -(S32 * U32) + S32 // intermediate signed.btype = { .po{.dtype = . vmad.0 Table 107. Input c has the same sign as the intermediate result. internally this is represented as negation of the product (a*b). . final signed The intermediate result is optionally scaled via right-shift. final signed -(S32 * S32) + S32 // intermediate signed.PTX ISA Version 2.asel}..U32 // intermediate unsigned. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. . .b2. final signed -(U32 * S32) + S32 // intermediate signed.po mode. PTX allows negation of either (a*b) or c. a{. final signed (U32 * U32) . . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.h0. with optional operand negates. this result is sign-extended if the final result is signed. the intermediate result is signed. Although PTX syntax allows separate negation of the a and b operands. final signed (S32 * U32) + S32 // intermediate signed.shr7.scale} d. // 32-bit scalar operation vmad. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.bsel}. “plus one” mode. The source operands support optional negation with some restrictions.b3. .bsel}.btype{.h1 }.asel = .dtype.atype.sat}{. final signed (S32 * U32) . . The “plus one” mode (.S32 // intermediate signed.b1. . and scaling. b{. {-}b{.scale} d.s32 }.sat}{. and zero-extended otherwise. 144 January 24.

-r3. r1. tb = partSelectSignExtend( b.po ) { lsb = 1.h0. S32_MAX. lsb = 1. U32_MIN).u32.negate) || c. } else if ( a.negate ^ b.Chapter 8. signedFinal = isSigned(atype) || isSigned(btype) || (a.negate ^ b. r1.negate ) { c = ~c. asel ). lsb = 1.u32.sat ) { if (signedFinal) result = CLAMP(result.0. atype.u32. r3.shr15: result = (tmp >> 15) & 0xffffffffffffffff. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 145 .sat vmad. r0. } if ( . lsb = 0.negate ) { tmp = ~tmp. if ( . January 24. btype. case . vmad requires sm_20 or later. r2.s32.or zero-extend based on source operand type ta = partSelectSignExtend( a. switch( scale ) { case .s32. } else if ( c. tmp[127:0] = ta * tb.shr7: result = (tmp >> 7) & 0xffffffffffffffff. vmad. bsel ). Instruction Set Semantics // extract byte/half-word/word and sign. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). U32_MAX.negate.u32.shr15 r0.h0. S32_MIN). else result = CLAMP(result. r2. tmp = tmp + c128 + lsb.

u32. r1.btype = { .lt. vset. r2.atype.op2 d. . asel ). b{.b2.asel = . . atype. . b{. . b{.0 Table 108.cmp . r3. tmp.atype. . Compare input values using specified comparison.op2 Description = = = = .u32. .asel}.min. d = optSecondaryOp( op2. c ). .s32.btype. tb = partSelectSignExtend( b.asel}. .eq.bsel}.bsel}. .lt vset. tmp.le.u32.max }. Semantics // extract byte/half-word/word and sign. a{.PTX ISA Version 2. c.bsel}.s32 }. .atype. c ). // 32-bit scalar operation. btype. 2010 . cmp ) ? 1 : 0.cmp d. .or zero-extend based on source operand type ta = partSelectSignExtend( a.ge }.bsel = { .h0.dsel. { .btype. with optional data merge vset. vset. The intermediate result of the comparison is always unsigned.b3. a{. tmp = compare( ta. 146 January 24. { . with optional secondary arithmetic operation or subword data merge.btype. .ne r1.dsel .cmp d. . tb. with optional secondary operation vset. bsel ). r2.0.asel}. r3.atype .gt. // 32-bit scalar operation.h1.h1 }. . a{. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.ne.b1. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and therefore the c operand and final result are also unsigned.add.cmp.b0. . c.u32. vset requires sm_20 or later. // optional secondary operation d = optMerge( dsel.

January 24. there are sixteen performance monitor events.0. Notes PTX ISA Notes Target ISA Notes Examples Currently. trap. brkpt requires sm_11 or later. @p pmevent 1. Supported on all target architectures. Introduced in PTX ISA version 1.Chapter 8.10. Table 110.4.0. brkpt. 2010 147 . Triggers one of a fixed number of performance monitor events. brkpt Suspends execution Introduced in PTX ISA version 1. pmevent a. Introduced in PTX ISA version 1. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters.7. trap Abort execution and generate an interrupt to the host CPU. trap. Supported on all target architectures. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. The relationship between events and counters is programmed via API calls from the host. pmevent 7. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. numbered 0 through 15. with index specified by immediate operand a. Instruction Set 8. brkpt. Table 111.

2010 .PTX ISA Version 2.0 148 January 24.

Chapter 9. 2010 149 . %lanemask_le. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %clock64 %pm0. %lanemask_lt. %pm3 January 24. …. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_gt %clock. read-only variables. %lanemask_ge. Special Registers PTX includes a number of predefined.

y < %ntid. Redefined as . mov.u32 %r0.x. It is guaranteed that: 0 <= %tid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.sreg .z == 1 in 2D CTAs. 2010 . The %tid special register contains a 1D.x.z < %ntid.z.y. Redefined as .y.x code accessing 16-bit component of %tid mov.y == %tid.%ntid.v4.z == 0 in 1D CTAs.%tid. cvt.%tid.u16 %rh.x.%h2.x. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.v4 .0. Supported on all target architectures.x < %ntid. The total number of threads in a CTA is (%ntid. %tid.u16 %rh.z == 1 in 1D CTAs. read-only.sreg .u32 type in PTX 2. or 3D vector to match the CTA shape. %ntid.0. .y 0 <= %tid.x. mad.%h1. %ntid.u32 %tid.z.y == %ntid.u32 %h2.%ntid. %ntid.0. The fourth element is unused and always returns zero.v4.sreg .u16 %r2.x. .u32 %ntid.x. // legacy PTX 1. // thread id vector // thread id components A predefined. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. . the fourth element is unused and always returns zero. %tid.z to %r2 Table 113. %tid component values range from 0 through %ntid–1 in each CTA dimension. CTA dimensions are non-zero.z. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.u32 %ntid.z == 0 in 2D CTAs.x to %rh Target ISA Notes Examples // legacy PTX 1. . %tid.u32.y * %ntid. per-thread special register initialized with the thread identifier within the CTA. mov. the %tid value in unused dimensions is 0. 2D.x 0 <= %tid. mov.0.z).u32 %h1.sreg .u32 type in PTX 2. mov.u32 %tid.PTX ISA Version 2. Every thread in the CTA has a unique %tid.%tid. %tid. // move tid.y. PTX ISA Notes Introduced in PTX ISA version 1.x code Target ISA Notes Examples 150 January 24.%tid. Supported on all target architectures.%tid.u32 %r0. // zero-extend tid.v4 .z PTX ISA Notes Introduced in PTX ISA version 1.u32 %r1. The number of threads in each dimension are specified by the predefined special register %ntid. read-only special register initialized with the number of thread ids in each CTA dimension. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. // compute unified thread id for 2D CTA mov.0 Table 112. // CTA shape vector // CTA dimensions A predefined. %ntid.x * %ntid.%r0.

read-only special register that returns the maximum number of warp identifiers. Note that %warpid is volatile and returns the location of a thread at the moment when read. read-only special register that returns the thread’s lane within the warp. Supported on all target architectures. A predefined. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.u32 %r. mov. due to rescheduling of threads following preemption. Introduced in PTX ISA version 2.sreg . %warpid. but its value may change during execution. Table 115. e.0. The lane identifier ranges from zero to WARP_SZ-1.sreg .u32 %r. For this reason. mov.u32 %laneid. Introduced in PTX ISA version 1.Chapter 9. .u32 %r.sreg . PTX ISA Notes Target ISA Notes Examples Table 116. mov. Supported on all target architectures. read-only special register that returns the thread’s warp identifier. A predefined. . Introduced in PTX ISA version 1. %nwarpid. %laneid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %warpid.3. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.g. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. . The warp identifier will be the same for all threads within a single warp. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.3. A predefined. Special Registers Table 114. 2010 151 .u32 %nwarpid. %nwarpid requires sm_20 or later. January 24.

mov.v4.y 0 <= %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.y < %nctaid.u32 %nctaid.y.0 Table 117.u16 %r0.y.{x. read-only special register initialized with the number of CTAs in each grid dimension. . It is guaranteed that: 0 <= %ctaid.u32 mov. It is guaranteed that: 1 <= %nctaid.sreg .sreg .sreg .x < %nctaid. with each element having a value of at least 1.x. The %ctaid special register contains a 1D.x code Target ISA Notes Examples 152 January 24. %ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.%ctaid.%nctaid. Each vector element value is >= 0 and < 65535.u32 mov.0. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.%ctaid. 2010 . The fourth element is unused and always returns zero.%nctaid.x 0 <= %ctaid. Supported on all target architectures.x.x.536 PTX ISA Notes Introduced in PTX ISA version 1.u32 %ctaid. Redefined as .z PTX ISA Notes Introduced in PTX ISA version 1.u32 type in PTX 2. %rh. . Redefined as .v4 . // Grid shape vector // Grid dimensions A predefined.0.%nctaid. depending on the shape and rank of the CTA grid. 2D.0.PTX ISA Version 2.v4. The fourth element is unused and always returns zero.x.%nctaid. .u32 %nctaid . %ctaid.0.u32 %ctaid.x code Target ISA Notes Examples Table 118. // CTA id vector // CTA id components A predefined. // legacy PTX 1.x.y.v4 . The %nctaid special register contains a 3D grid shape vector. %rh.z < %nctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.z} < 65.z.u16 %r0.sreg .u32 type in PTX 2. read-only special register initialized with the CTA identifier within the CTA grid. // legacy PTX 1.y. or 3D vector.z. Supported on all target architectures. mov.

Supported on all target architectures. During execution.g. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. e. but its value may change during execution. repeated launches of programs may occur.u32 %r. .0. 2010 153 . The SM identifier numbering is not guaranteed to be contiguous.u32 %smid. mov. The SM identifier numbering is not guaranteed to be contiguous. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. read-only special register that returns the maximum number of SM identifiers. mov. so %nsmid may be larger than the physical number of SMs in the device. A predefined.u32 %gridid. where each launch starts a grid-of-CTAs. mov.0. %smid. PTX ISA Notes Target ISA Notes Examples Table 121.Chapter 9. Introduced in PTX ISA version 2. %nsmid requires sm_20 or later. %gridid. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Special Registers Table 119. Notes PTX ISA Notes Target ISA Notes Examples Table 120. This variable provides the temporal grid launch number for this context.sreg .u32 %r. Note that %smid is volatile and returns the location of a thread at the moment when read. A predefined.sreg . . read-only special register initialized with the per-grid temporal grid identifier. due to rescheduling of threads following preemption. Supported on all target architectures.u32 %r. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.3. // initialized at grid launch A predefined. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. The SM identifier ranges from 0 to %nsmid-1.u32 %nsmid.sreg . PTX ISA Notes Target ISA Notes Examples January 24. %nsmid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. . %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.

A predefined. %lanemask_eq requires sm_20 or later. Introduced in PTX ISA version 2. mov. Introduced in PTX ISA version 2. 154 January 24.0 Table 122.0. A predefined.sreg . Table 124. . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. Table 123.sreg .PTX ISA Version 2.0.u32 %lanemask_le. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. mov. %lanemask_lt requires sm_20 or later.u32 %lanemask_eq.u32 %r. mov. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. 2010 .u32 %r. . %lanemask_lt. %lanemask_eq. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. . A predefined.u32 %lanemask_lt. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg . Introduced in PTX ISA version 2. %lanemask_le.u32 %r.0. %lanemask_le requires sm_20 or later.

%lanemask_ge.sreg .u32 %lanemask_ge. %lanemask_gt. %lanemask_gt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.0. A predefined.u32 %lanemask_gt. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Introduced in PTX ISA version 2.Chapter 9.u32 %r. 2010 155 . %lanemask_ge requires sm_20 or later. Special Registers Table 125. mov.u32 %r. Table 126. . Introduced in PTX ISA version 2. mov.sreg .0. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. . A predefined. January 24.

. read-only 64-bit unsigned cycle counter.0 Table 127. .%pm0. Supported on all target architectures. Table 128. mov. Special Registers: %pm0. %pm3 %pm0.u32 %clock. Their behavior is currently undefined. and %pm3 are unsigned 32-bit read-only performance monitor counters.sreg . mov.u32 r1.0. %pm3. %pm2.u32 %pm0.PTX ISA Version 2. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Special registers %pm0.%clock. mov. %pm2.sreg .sreg . %pm2. read-only 32-bit unsigned cycle counter. 2010 .0. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.u64 r1. The lower 32-bits of %clock64 are identical to %clock. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Introduced in PTX ISA version 2. %pm1. 156 January 24. %clock64 requires sm_20 or later.u32 r1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u64 %clock64. Supported on all target architectures. %pm1.3.%clock64. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. . %pm1. …. Table 129.

.minor // major. .target Table 130.4 January 24.0 .version 2. and the target architecture for which the code was generated.Chapter 10.1. Increments to the major number indicate incompatible changes to PTX.version .0. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Directives 10. Supported on all target architectures. Each ptx file must begin with a .version . .version 1.version major. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directive.version Syntax Description Semantics PTX version number. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 157 .version directive. minor are integers Specifies the PTX language version number. PTX File Directives: .version directives are allowed provided they match the original . Duplicate .

Supported on all target architectures. PTX features are checked against the specified target architecture. In general. immediately followed by a . where each generation adds new features and retains all features of previous generations. texmode_unified. 158 January 24.f64 to .samplerref descriptors. Texturing mode introduced in PTX ISA version 1. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. 64-bit {atom.shared.version directive.target directive specifies a single target architecture. Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_13. and an error is generated if an unsupported feature is used.target Syntax Architecture and Platform target. Adds double-precision support. A . A program with multiple .0 Table 131. Texturing mode: (default is . vote instructions.red}. Requires map_f64_to_f32 if any . 2010 .texref descriptor. Target sm_20 Description Baseline feature set for sm_20 architecture. with only half being used by instructions converted from .texref and .red}.PTX ISA Version 2.f64 instructions used. The texturing mode is specified for an entire module and cannot be changed within the module. The following table summarizes the features in PTX that vary according to target architecture. including expanded rounding modifiers. PTX File Directives: . but subsequent . sm_11.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.red}.texmode_unified . Requires map_f64_to_f32 if any .0. .target .f32. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Adds {atom. Therefore. map_f64_to_f32 }. Disallows use of map_f64_to_f32.texmode_unified) .global. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. brkpt instructions.5. Adds {atom. Requires map_f64_to_f32 if any . Each PTX file must begin with a . texture and sampler information is referenced with independent .f64 storage remains as 64-bits. PTX code generated for a given target can be run on later generation devices. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Introduced in PTX ISA version 1. sm_12. sm_10.target directive containing a target architecture and optional platform options.target directives can be used to change the set of target features allowed during parsing.global. texmode_independent.f64 instructions used. generations of SM architectures follow an “onion layer” model. Note that .f64 instructions used.texmode_independent texture and sampler information is bound together and accessed via a single .

Directives Examples .Chapter 10.target sm_10 // baseline target architecture . 2010 159 . texmode_independent January 24.target sm_13 // supports double-precision .target sm_20.

b32 %r<99>. … } . [z]. For PTX ISA versions 1.param .texref. parameter variables are declared in the kernel parameter list. with optional parameters. PTX ISA Notes For PTX ISA version 1.0 through 1.reg . [y]. Supported on all target architectures.param. etc. .3.surfref variables may be passed as parameters.param . ld. the kernel dimensions and properties are established and made available via special registers. and body for the kernel function.entry cta_fft . These parameters can only be referenced by name within texture and surface load.entry kernel-name ( param-list ) kernel-body . and query instructions and cannot be accessed via ld.b32 %r2. parameter variables are declared in the kernel body. store. ld.5 and later. In addition to normal parameters.entry .param instructions. At kernel launch. %ntid. parameters.entry filter ( .g.entry kernel-name kernel-body Defines a kernel entry point name. Parameters are passed via .entry . The shape and size of the CTA executing the kernel are available in special registers.samplerref. .b32 %r3.4 and later. .param { . and .param instructions.0 10.4. e. ld. 160 January 24. Kernel and Function Directives: .param.0 through 1. 2010 .param.b32 x.b32 %r1.param space memory and are listed within an optional parenthesized parameter list. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.2. Semantics Specify the entry point for a kernel program. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. %nctaid. Parameters may be referenced by name within the kernel body and loaded into registers using ld. . .entry Syntax Description Kernel entry point and body. .b32 y. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.PTX ISA Version 2.func Table 132. opaque .b32 z ) Target ISA Notes Examples [x].

Parameters must be base types in either the register or parameter state space. PTX ISA 2.func . and supports recursion. ret.reg .0 with target sm_20 supports at most one return value. . and recursion is illegal. Variadic functions are represented using ellipsis following the last fixed argument. if any. Directives Table 133. . including input and return parameters and optional function body. val1). parameters must be in the register state space. which may use a combination of registers and stack locations to pass parameters.func fname (param-list) function-body . there is no stack.2 for a description of variadic functions. mov.param space are accessed using ld. Variadic functions are currently unimplemented.reg . (val0.func Syntax Function definition.b32 rval) foo (. PTX 2. foo.b32 rval. Parameter passing is call-by-value.f64 dbl) { . Parameters in .func definition with no body provides a function prototype.reg .param instructions in the body.b32 N. The parameter lists define locally-scoped variables in the function body. … use N.b32 localVar. … Description // return value in fooval January 24. Parameters in register state space may be referenced directly within instructions in the function body.func fname function-body . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Kernel and Function Directives: .0.Chapter 10.reg .result.0 with target sm_20 allows parameters in the . Release Notes For PTX ISA version 1. } … call (fooval).param and st. . A .func (. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. implements an ABI with stack. Supported on all target architectures. dbl. other code.param state space.func (ret-param) fname (param-list) function-body Defines a function. The implementation of parameter passing is left to the optimizing translator.x code. 2010 161 .

to throttle the resource requirements (e.3. PTX supports the following directives.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.minnctapersm directives may be applied per-entry and must appear between an .g. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.0 10.PTX ISA Version 2.maxnreg .maxntid and .maxnctapersm (deprecated) .maxnreg. . and the strings have no semantics within the PTX virtual machine model. the . which pass information to the backend optimizing compiler. and the . 2010 . The .entry directive and its body. .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.maxntid. The interpretation of . These can be used. and . A general . at entry-scope.maxntid directive specifies the maximum number of threads in a thread block (CTA). The directive passes a list of strings to the backend.pragma directive is supported for passing information to the PTX backend. Note that .pragma directives may appear at module (file) scope.pragma The . Currently. The directives take precedence over any module-level constraints passed to the optimizing backend. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.maxntid .minnctapersm .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). registers) to increase total thread count and provide a greater opportunity to hide memory latency. or as statements within a kernel or device function body. 162 January 24. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. the . for example.

maxntid .Chapter 10.maxntid 16. The actual number of registers used may be less. This maximum is specified by giving the maximum extent of each dimention of the 1D. nz Declare the maximum number of threads in the thread block (CTA). Performance-Tuning Directives: . 2010 163 . The compiler guarantees that this limit will not be exceeded.3. the backend may be able to compile to fewer registers.entry bar .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. Introduced in PTX ISA version 1.maxntid nx . Performance-Tuning Directives: . or 3D CTA.maxnreg n Declare the maximum number of registers per thread in a CTA. ny. for example.entry foo . Exceeding any of these limits results in a runtime error or kernel launch failure. . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. The maximum number of threads is the product of the maximum extent in each dimension.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxntid nx. 2D. Directives Table 134. .maxnreg .16. Supported on all target architectures.maxctapersm. or the maximum number of registers may be further constrained by .maxntid nx.3.entry foo . ny .maxntid 256 . . Introduced in PTX ISA version 1.maxntid and . . Supported on all target architectures.

additional CTAs may be mapped to a single multiprocessor. .maxntid to be specified as well.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0. For this reason.entry foo . Optimizations based on .maxnctapersm (deprecated) . Optimizations based on . . . Introduced in PTX ISA version 1.maxntid 256 .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxntid and .maxntid 256 .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Supported on all target architectures. Deprecated in PTX ISA version 2. However.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.entry foo . Introduced in PTX ISA version 2.minnctapersm in PTX ISA version 2.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm generally need .maxnctapersm.3. 2010 . Performance-Tuning Directives: .maxnctapersm has been renamed to . .PTX ISA Version 2.0 as a replacement for .maxntid to be specified as well. The optimizing backend compiler uses . .0 Table 136. Performance-Tuning Directives: .0.maxnctapersm generally need . if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm 4 { … } 164 January 24.minnctapersm . Supported on all target architectures.

// disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . entry-scoped.pragma “nounroll”. The .pragma directive strings is implementation-specific and has no impact on PTX semantics. or at statementlevel.pragma Syntax Description Pass directives to PTX backend compiler. Introduced in PTX ISA version 2. Pass module-scoped.pragma list-of-strings . .pragma directive may occur at module-scope. The interpretation of .entry foo . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma . Supported on all target architectures. Directives Table 138. { … } January 24. 2010 165 .Chapter 10. . at entry-scope.0. Performance-Tuning Directives: . or statement-level directives to the PTX backend compiler.pragma “nounroll”.

@@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .section .quad int64-list // comma-separated hexadecimal integers in range [0.section directive is new in PTX ISA verison 2. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . Table 139.4byte label .byte 0x2b.. The @@DWARF syntax is deprecated as of PTX version 2.section directive.file . 0x00000364.x code.loc The . replaced by . 0x00. 0x00.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. “”.4byte 0x000006b5.section . Supported on all target architectures. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.4. 2010 . 0x61395a5f. 0x63613031. 0x6150736f.debug_pubnames. Introduced in PTX ISA version 1.264-1] . 0x00 . 0x00.0 but is supported for legacy PTX version 1.byte 0x00.byte byte-list // comma-separated hexadecimal byte values . @@DWARF dwarf-string dwarf-string may have one of the . 0x5f736f63 . 0x02.4byte .0 10.232-1] . 0x736d6172 . 0x00. @progbits . 0x00.PTX ISA Version 2.debug_info ..0.2. 0x00 166 January 24.4byte int32-list // comma-separated hexadecimal integers in range [0.0 and replaces the @@DWARF syntax. Deprecated as of PTX 2.4byte 0x6e69616d.

loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Source file location.264-1] .0.section Syntax PTX section definition. 0x5f736f63 0x6150736f.255] .b32 0x000006b5. .232-1] .section .. Supported on all target architectures. Supported on all target architectures. . } 0x02. 0x00000364.b32 int32-list // comma-separated list of integers in range [0. 0x00. 0x00. .Chapter 10.0.file filename Table 142. . . Source file information.0. 2010 167 ..section .b8 byte-list // comma-separated list of integers in range [0.b32 .file .loc . Debugging Directives: . 0x00.debug_info . 0x00 0x61395a5f. 0x736d6172 0x00 Table 141.b64 int64-list // comma-separated list of integers in range [0.b32 0x6e69616d.b8 0x2b.loc line_number January 24. replaces @@DWARF syntax. Supported on all target architectures. .b32 label .debug_pubnames { . 0x63613031.. . Debugging Directives: .b8 0x00. 0x00. 0x00. Debugging Directives: . Directives Table 140. 0x00.section section_name { dwarf-lines } dwarf-lines have the following formats: .

Linking Directives: .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.visible . . Linking Directives: . Introduced in PTX ISA version 1.6. Linking Directives .extern . .extern identifier Declares identifier to be defined externally. // foo will be externally visible 168 January 24.extern . .extern . Introduced in PTX ISA version 1.PTX ISA Version 2.0.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Supported on all target architectures.0. . // foo is defined in another module Table 144. 2010 .b32 foo.visible identifier Declares identifier to be externally visible.b32 foo.visible Table 143.global . Supported on all target architectures.visible .global .0 10.

1 CUDA 2.3 driver r190 CUDA 3.0. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 2.5 PTX ISA 2.1 CUDA 2. 2010 169 .0 driver r195 PTX ISA Version PTX ISA 1. CUDA Release CUDA 1.1 PTX ISA 1.Chapter 11.0 January 24.2 PTX ISA 1. and the remaining sections provide a record of changes in previous releases. The release history is as follows.2 CUDA 2.0 CUDA 1.4 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 PTX ISA 1.3 PTX ISA 1.

f32 for sm_20 targets. The goal is to achieve IEEE 754 compliance wherever possible. Single. When code compiled for sm_1x is executed on sm_20 devices. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.x code and sm_1x targets.ftz modifier may be used to enforce backward compatibility with sm_1x. mad.0 11.rm and .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. 2010 .1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. rcp. Changes in Version 2. The mad.f32.1. The fma.1.1.and double-precision div.PTX ISA Version 2. The . Both fma. Single-precision add.1. and mul now support .1.f32 and mad. sub. while maximizing backward compatibility with legacy PTX 1.rn.f32 instruction also supports .f32 maps to fma. These are indicated by the use of a rounding modifier and require sm_20.f32 require a rounding modifier for sm_20 targets. Floating-Point Extensions This section describes the floating-point changes in PTX 2.ftz and .rp rounding modifiers for sm_20 targets. Instructions testp and copysign have been added. and sqrt with IEEE 754 compliant rounding have been added. New Features 11. fma.f32 requires sm_20. A single-precision fused multiply-add (fma) instruction has been added. • • • • • 170 January 24.sat modifiers.0 11.0 for sm_20 targets. The mad. The changes from PTX ISA 1.

{and. bar now supports optional thread count and register operands. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. has been added. has been added. vote. and shared addresses to generic address and vice-versa has been added.pred have been added. st. has been added.red}. %clock64.shared have been extended to handle 64-bit data types for sm_20 targets. A “count leading zeros” instruction.2. Release Notes 11. 11.add. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. for prefetching to specified level of memory hierarchy.ge.zero. January 24.gt} have been added. and red now support generic addressing.f32 have been implemented. New instructions A “load uniform” instruction.b32. A “population count” instruction. ldu. A system-level membar instruction. e. A “bit reversal” instruction.red.section. st. has been added.or}.1. atom. .ballot.minnctapersm to better match its behavior and usage. suld. Bit field extract and insert instructions. clz.lt. local.red. Surface instructions support additional .1. A new directive. The . bfe and bfi. A “find leading non-sign bit” instruction. New special registers %nsmid. Instructions {atom. Other new features Instructions ld.arrive instruction has been added. has been added. popc. Cache operations have been added to instructions ld. Instruction cvta for converting global. isspacep. membar. prefetch. bfind. A “vote ballot” instruction. 2010 171 . Instructions prefetch and prefetchu have also been added. has been added. Instructions {atom.Chapter 11. cvta.clamp and .popc. brev.3.1.u32 and bar. %lanemask_{eq. Video instructions (includes prmt) have been added. and sust. have been added.sys. ldu.maxnctapersm directive was deprecated and replaced with .1. Instructions bar.clamp modifiers. prefetchu. The bar instruction has been extended as follows: • • • A bar. Instruction sust now supports formatted surface stores.g. . has been added.le.red}.

4 and earlier. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.version is 1.f32 type is unimplemented.0 11.ftz (and cvt for .2. See individual instruction descriptions for details. call suld.s32.4 or earlier.3. where .u32.ftz for PTX ISA versions 1. {atom. The underlying. Formatted surface load is unimplemented.red}. has been fixed. cvt.PTX ISA Version 2.max} are not implemented. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. stack-based ABI is unimplemented. the correct number is sixteen. or . To maintain compatibility with legacy PTX code. 11. .1. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.f32} atom.5.s32. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.{min.{u32.5 and later.f32. if .target sm_1x. Instruction bra. In PTX version 1.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. Support for variadic functions and alloca are unimplemented. 2010 . 172 January 24.p sust.p. Semantic Changes and Clarifications The errata in cvt.1. Formatted surface store with .

… @p bra L1_end. entry-function.func bar (…) { … L1_head: . . Descriptions of .pragma “nounroll”. The “nounroll” pragma is allowed at module.pragma “nounroll”. and statement levels. { … } // do not unroll any loop in this function .pragma. disables unrolling for all loops in the entry function body. Ignored for sm_1x targets. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. L1_body: … L1_continue: bra L1_head. disables unrolling of0 the loop for which the current block is the loop header. L1_end: … } // do not unroll this loop January 24. . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Table 145. Supported only for sm_20 targets.pragma strings defined by ptxas.0.pragma Strings This section describes the . Note that in order to have the desired effect at statement level. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.pragma “nounroll”.entry foo (…) . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. including loops preceding the . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.Appendix A. 2010 173 .

PTX ISA Version 2. 2010 .0 174 January 24.

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