NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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...........1.................................7...................................................................... Abstracting the ABI ............................ 6..1..... 41 Source Operands..................2.................................2................1.................. 6.2... 29 Global State Space .....2...............1........................................ 38 Alignment ................. 5.........................1.........1... 5..........4.....................PTX ISA Version 2.... 34 Variables .. 6........................1.2............................. 5..................................................... 46 6............ 49 7....................... 30 Shared State Space...............................................3......................................................................................... 6.....2............................................. Types...................................................................4................... 2010 ... 27 Register State Space ..........6........................................................................................ 27 5...................................... Chapter 6......1..... 5..................5..... 32 Texture State Space (deprecated) ............ 44 Rounding Modifiers ... 44 Scalar Conversions ..5.......................... 6..1............................................ 37 Array Declarations .......................................................4............................. 5.6. State Spaces............................................................ State Spaces .......................................... Types .............................1................................. 28 Constant State Space ........2....................................0 4.........................................................................4................................................ Summary of Constant Expression Evaluation Rules ............. 5..................................................3......1..8.... 49 ii January 24............................................................4.................... 5.. 29 Local State Space .........................4....... 33 5......................................................... 6...2............................................ 37 Vectors ...........................5......................................................6..................................................................1.. Operand Type Information ............................. 28 Special Register State Space ...................... 39 Parameterized Variable Names .................. 33 Fundamental Types ....................4..... 5................................................................ 43 Vectors as Operands ......... Function declarations and definitions ... 47 Chapter 7...............4........................................................ and Vectors ........3............................. 25 Chapter 5..................................................... Type Conversion.................................................. 5......................... 5.............. 42 Arrays as Operands .1..... Texture............5.................................4.......... 5....4............................... 38 Initializers ...........................................4...... 6............5........... 5.......... 5........ 6....4..................5.4............................................................................................................................................. 41 6............................... 43 6........... and Surface Types ... Operand Costs ............................................................................6... 29 Parameter State Space .................. 33 Restricted Use of Sub-Word Sizes ....... 39 5......................... 5.......... 43 Labels and Function Names as Operands .......................... 42 Addresses as Operands ...............................................................1..................................................1.............................................. 6.......................... 41 Using Addresses...3.......... and Variables .................................................................................. 41 Destination Operands ............... Arrays................................................. Instruction Operands....................4...................................................................................................... Sampler. 5................3.............................. 5................1.................. 37 Variable Declarations ...... 32 5...........2...4.........................

................................................... 55 PTX Instructions .........................2..............5....... 104 Data Movement and Conversion Instructions ................ Changes from PTX 1...... 8.....................................................................................................4.6.......................0 ......7....................................................................... 10................ Chapter 9..................... 62 Machine-Specific Semantics of 16-bit Code ................................ 8.............. 169 11..................................................................2......................... 60 8....................... 8..........2.................. 55 8....... PTX Version and Target Directives .................x ............................................................................1.............................. 168 Chapter 11...................................................................3........................................ 8................................................... 62 8............................................. 132 Video Instructions ............................................................. Format and Semantics of Instruction Descriptions ............................................9................................................................. 122 Control Flow Instructions . 8...............7.........3... Instruction Set .... 53 Alloca ............1....... 54 Chapter 8...................... Special Registers ................................... 160 Performance-Tuning Directives .......................7................ 170 New Features ... Divergence of Threads in Control Constructs .................................. 8........ 63 Integer Arithmetic Instructions ..3........ 8.......... 57 Manipulating Predicates .........................1........................7............ 8.........................7.......................7......... 129 Parallel Synchronization and Communication Instructions ....................................... 8............... 11.....................1... 100 Logic and Shift Instructions ......................................7.1....2............................ 7. Type Information for Instructions and Operands ..1.......................................................6....................................................... 172 Unimplemented Features Remaining .... 166 Linking Directives ............................................... 8............................ 8.............................................................. Instructions .................................. 56 Comparisons .7...................... 172 January 24. 108 Texture and Surface Instructions ...................................................... Changes in Version 2....................... 8................ 58 8......... 162 Debugging Directives ............3.....................1..................................... 11............. 8.......................................... 2010 iii .7. 10....... 140 Miscellaneous Instructions...............................................................................1.................................................. 63 Floating-Point Instructions .............................................................................. 170 Semantic Changes and Clarifications .......10....................................3... 7...........................1................................3..7......................................... 8..............6.....1..............8............ 157 10...................................... 59 Operand Size Exceeding Instruction-Type Size ........ 55 Predicated Execution .....................2....7................. 8.......... 8...............4....... Directives ............................7........5........................................... 52 Variadic functions ......................................................... 10.......4.. 157 Specifying Kernel Entry Points and Functions .... 11..7..1......2.........................4.............................................................................................................................................3.......6............................................. 149 Chapter 10... 81 Comparison and Selection Instructions .. 147 8........................................................................................................................................................1........ Release Notes ... 62 Semantics ............... 10..1.......

...........0 Appendix A.......... 2010 ..... 173 iv January 24..pragma Strings..........................PTX ISA Version 2............ Descriptions of ..

. Table 27....... Table 6.............................................. Table 14............................................. Table 9......... 68 Integer Arithmetic Instructions: mul24 ..... 18 Reserved Instruction Keywords ..................... Table 17............................................... 28 Fundamental Type Specifiers ................................................................................... Table 19........... 27 Properties of State Spaces ..... 61 Integer Arithmetic Instructions: add .... 35 Convert Instruction Precision and Format ............. 47 Operators for Signed Integer................................................................ 23 Constant Expression Evaluation Rules ..... Table 11.................... Table 21............................. Table 13.................. 70 Integer Arithmetic Instructions: sad ..................................................................... 59 Relaxed Type-checking Rules for Source Operands ....... 57 Floating-Point Comparison Operators Accepting NaN .................................................. Table 22.................................................... Table 8... 20 Operator Precedence .. 19 Predefined Identifiers .................................................................. 65 Integer Arithmetic Instructions: sub............................................. 66 Integer Arithmetic Instructions: subc .................. Table 18... Table 25.................................................................. 46 Integer Rounding Modifiers .. Table 4................. 2010 v .......................... Table 26.. 35 Opaque Type Fields in Independent Texture Mode .........cc ............ Table 15................................ Table 12.................................................................................... Table 32........ 45 Floating-Point Rounding Modifiers .............................................................................. Table 31.. Table 2...... Table 24......................... 65 Integer Arithmetic Instructions: addc ........................................................................ Table 23.................... 60 Relaxed Type-checking Rules for Destination Operands................................. 64 Integer Arithmetic Instructions: sub ............................................ Table 7.......................................... 67 Integer Arithmetic Instructions: mad .................................................................... Table 29........................................................................................................................................................................................................... 46 Cost Estimates for Accessing State-Spaces ......................... Table 16...................................... Table 3..................................... 64 Integer Arithmetic Instructions: add........ 71 January 24.............................................................................. 25 State Spaces .......... 33 Opaque Type Fields in Unified Texture Mode ............cc .......................................................... 58 Type Checking Rules ................................................... Table 10......................................................................... and Bit-Size Types .. Table 20..........................................List of Tables Table 1....... 69 Integer Arithmetic Instructions: mad24 ........................................ Table 5.................................................................................... Unsigned Integer............ PTX Directives ................. Table 28....................................... 58 Floating-Point Comparison Operators Testing for NaN ........................ 57 Floating-Point Comparison Operators ................................................................. 66 Integer Arithmetic Instructions: mul ....... Table 30..

.............. 73 Integer Arithmetic Instructions: popc ................................................................... 86 Floating-Point Instructions: fma ........ 74 Integer Arithmetic Instructions: bfind ............................... Table 62...... 93 Floating-Point Instructions: sqrt ...... 75 Integer Arithmetic Instructions: brev ..................................................................... 85 Floating-Point Instructions: mul .... Table 47............. 87 Floating-Point Instructions: mad .................................... Table 34................... 94 Floating-Point Instructions: rsqrt ............................... Table 42....................................... 91 Floating-Point Instructions: min . Table 52.............PTX ISA Version 2............................................................. 72 Integer Arithmetic Instructions: min ...............................................................................................................................................................................................................................0 Table 33..................... 2010 ...... Table 63. Table 56. Table 48.................................. 74 Integer Arithmetic Instructions: clz ........................... Table 51................................................................................... Table 57................ Table 67.............................................................................................................................. Table 39...................................................................... 95 Floating-Point Instructions: sin ............................................................................................................ Table 53. 101 Comparison and Selection Instructions: setp ............................................ 84 Floating-Point Instructions: sub ........................ 99 Comparison and Selection Instructions: set ............... Table 68........................................ Table 38.......................................................................... 96 Floating-Point Instructions: cos .................................... 76 Integer Arithmetic Instructions: bfe ............................................................................................... Table 64.... 90 Floating-Point Instructions: abs .................................................................................................................................................................... 73 Integer Arithmetic Instructions: max . 83 Floating-Point Instructions: add .. Table 40...................... Integer Arithmetic Instructions: div .................... Table 61......................... 91 Floating-Point Instructions: neg ................................... 78 Integer Arithmetic Instructions: prmt ...................... Table 65............................... 103 vi January 24.. Table 60.............. Table 49.............. 102 Comparison and Selection Instructions: selp ........................................ 72 Integer Arithmetic Instructions: neg .............. Table 41................................................. Table 35... 92 Floating-Point Instructions: rcp ... 98 Floating-Point Instructions: ex2 ..................................................... 82 Floating-Point Instructions: testp .................... Table 37................................................................................................... Table 45............................................................ Table 59..... Table 44...................... Table 58...................................... 88 Floating-Point Instructions: div .... 92 Floating-Point Instructions: max . Table 69.... Table 54....................... Table 46.......................................... 83 Floating-Point Instructions: copysign .... Table 66......... Table 43.. Table 55................... 71 Integer Arithmetic Instructions: rem ........................................... 71 Integer Arithmetic Instructions: abs ............................. Table 50.................................................. 77 Integer Arithmetic Instructions: bfi .......................................................... 79 Summary of Floating-Point Instructions ................................................. Table 36................................................. 97 Floating-Point Instructions: lg2 ................................................................................................................................................... 103 Comparison and Selection Instructions: slct ......................................................

.............. 113 Data Movement and Conversion Instructions: ldu ..................... vsub............................................................. 125 Texture and Surface Instructions: sust ......................................................................... Table 91........................................................... 110 Data Movement and Conversion Instructions: mov ..... Table 101..........Table 70.............. 126 Texture and Surface Instructions: sured............................. Table 102............................................................................................ Table 105.... 139 Video Instructions: vadd.. vabsdiff........................................................................................................................................................................................ 130 Control Flow Instructions: call ............ Logic and Shift Instructions: and ............................ Table 72................. 128 Control Flow Instructions: { } ...................... Table 87... Table 73.. Table 76.............. 105 Logic and Shift Instructions: or ........................... Table 99.................... 131 Parallel Synchronization and Communication Instructions: bar ................ Table 75..................... Table 97.......................... Table 74................ Table 94.................................................................... Table 88.................................................... 2010 vii . Table 82....... 118 Data Movement and Conversion Instructions: isspacep ............................................... 131 Control Flow Instructions: exit ..................... 123 Texture and Surface Instructions: txq ................................................... 119 Data Movement and Conversion Instructions: cvt ......... 129 Control Flow Instructions: @ ........................................................... Table 80...................................... Table 81.... prefetchu .............. Table 96........ Table 98..................... Table 71.... 137 Parallel Synchronization and Communication Instructions: vote ............................. vshr ..... 111 Data Movement and Conversion Instructions: mov ......................... 106 Logic and Shift Instructions: not .................................................................... Table 92............. 116 Data Movement and Conversion Instructions: prefetch............ Table 78................................. Table 103............................................................... 130 Control Flow Instructions: ret . 107 Cache Operators for Memory Load Instructions ................................ 112 Data Movement and Conversion Instructions: ld .............................................. 124 Texture and Surface Instructions: suld .................................... 106 Logic and Shift Instructions: shl ...... Table 100............................................................ vmax .......... Table 83........ vmin........ 129 Control Flow Instructions: bra ..... Table 77................. 106 Logic and Shift Instructions: cnot . 134 Parallel Synchronization and Communication Instructions: atom .... 143 January 24................................................................ 119 Data Movement and Conversion Instructions: cvta ............................................ 142 Video Instructions: vshl.............. 135 Parallel Synchronization and Communication Instructions: red ... Table 90...................... Table 104...... Table 106............................................... 107 Logic and Shift Instructions: shr .................................................................. Table 79.......... Table 84.................................. 127 Texture and Surface Instructions: suq ....... Table 85.... Table 86................................. Table 93........ 120 Texture and Surface Instructions: tex ... Table 89......................................... 105 Logic and Shift Instructions: xor .................... 133 Parallel Synchronization and Communication Instructions: membar ................ 109 Cache Operators for Memory Store Instructions ........................................................... 115 Data Movement and Conversion Instructions: st ............... Table 95...................................

....... Table 117.............................. 152 Special Registers: %smid ........... Table 111....... Table 127........................................... Table 134................. 163 Performance-Tuning Directives: ......................... 147 Miscellaneous Instructions: pmevent................................................ 151 Special Registers: %warpid ........................................... 164 Performance-Tuning Directives: ................................................................................................. 161 Performance-Tuning Directives: .................pragma ................................................................. Table 132..................... 160 Kernel and Function Directives: ..........................................entry................................................................ Table 121..... 146 Miscellaneous Instructions: trap ........................................ Table 125........ Table 123............................................................. Table 137............ Table 113............................. 147 Miscellaneous Instructions: brkpt ........... Table 126...............................................................................................file ............... 156 Special Registers: %pm0......................................................................................................................... %pm2............................. Table 143.................................................func ................................................... Table 108. %pm1.................................. Table 130........... 155 Special Registers: %lanemask_gt .............. Table 139............................................ Table 118.......................................................... 166 Debugging Directives: .....................0 Table 107............ Table 114................................... Table 116.......................................................PTX ISA Version 2......................... 151 Special Registers: %ctaid .................................. 154 Special Registers: %lanemask_lt .............. 150 Special Registers: %laneid .............. Table 119..... Table 109........................................................................ Table 122......................................maxntid ....................target ........................... 155 Special Registers: %clock ...........................................maxnctapersm (deprecated) ......................... 165 Debugging Directives: @@DWARF .............. 157 PTX File Directives: .............................................................. Table 110... 156 Special Registers: %clock64 ............................................................................extern...... 168 viii January 24.........................minnctapersm .... Table 120.......... 154 Special Registers: %lanemask_ge ........... Table 133. 153 Special Registers: %lanemask_eq .. Table 112...... Table 142..... 153 Special Registers: %gridid ..... 154 Special Registers: %lanemask_le ........................... 150 Special Registers: %ntid ..................................... Table 141................................ 167 Linking Directives: .................................................................... 158 Kernel and Function Directives: ........ Table 115...................... 156 PTX File Directives: ..... Table 124.............................. 163 Performance-Tuning Directives: ................. Table 138.............................. 2010 ....................................................................... 152 Special Registers: %nctaid ............... 153 Special Registers: %nsmid . %pm3 . 144 Video Instructions: vset....version.............. Table 131... Table 129.................................................................................... 147 Special Registers: %tid ........section ...........maxnreg .......... Table 128... Table 136............................................... Table 140............... 167 Debugging Directives: ...................................................................................................................... 164 Performance-Tuning Directives: ............ Video Instructions: vmad ........ 151 Special Registers: %nwarpid ........................................................... 167 Debugging Directives: ........................... Table 135...............loc ...........................................

.................................................... 173 January 24......................... 2010 ix ..........Table 144.. Table 145........visible....................................... 168 Pragma Strings: “nounroll” ........ Linking Directives: ...........................

PTX ISA Version 2. 2010 .0 x January 24.

Chapter 1. many-core processor with tremendous computational horsepower and very high memory bandwidth. there is a lower requirement for sophisticated flow control. from general signal processing or physics simulation to computational finance or computational biology. image and media processing applications such as post-processing of rendered images. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. PTX exposes the GPU as a data-parallel computing device. video encoding and decoding. 1. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Introduction This document describes PTX. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. the memory access latency can be hidden with calculations instead of big data caches. and because it is executed on many data elements and has high arithmetic intensity. January 24. 2010 1 .1. high-definition 3D graphics. Data-parallel processing maps data elements to parallel processing threads. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Because the same program is executed for each data element. stereo vision. image scaling. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. In fact. the programmable GPU has evolved into a highly parallel. 1. and pattern recognition can map image blocks and pixels to parallel processing threads. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing.2. PTX defines a virtual machine and ISA for general purpose parallel thread execution. which are optimized for and translated to native target-architecture instructions. PTX programs are translated at install time to the target hardware instruction set. multithreaded. Similarly. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time.

ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.x code will continue to run on sm_1x targets as well. A “flush-to-zero” (.f32 maps to fma. and video instructions. Instructions marked with .PTX ISA Version 2. memory. Provide a common source-level ISA for optimizing code generators and translators. The main areas of change in PTX 2.x features are supported on the new sm_20 target.ftz and . A single-precision fused multiply-add (fma) instruction has been added.rn. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.rp rounding modifiers for sm_20 targets. Most of the new features require a sm_20 target. sub. Achieve performance in compiled applications comparable to native GPU performance. addition of generic addressing to facilitate the use of general-purpose pointers. 2010 . Legacy PTX 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.1. 1. and mul now support . extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. PTX 2. Provide a machine-independent ISA for C/C++ and other compilers to target. 1. Provide a code distribution ISA for application and middleware developers. fma. Both fma. surface. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. atomic. Facilitate hand-coding of libraries.ftz) modifier may be used to enforce backward compatibility with sm_1x. • • • 2 January 24.f32 requires sm_20.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 and mad. The mad. and the introduction of many new instructions. and architecture tests. barrier.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 for sm_20 targets.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 is a superset of PTX 1. and all PTX 1. Single-precision add. which map PTX to specific target machines. performance kernels.3.f32 instruction also supports .sat modifiers.0 is in improved support for the IEEE 754 floating-point standard.f32 require a rounding modifier for sm_20 targets.0 PTX ISA Version 2.0 are improved support for IEEE 754 floating-point operations. mad.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Improved Floating-Point Support A main area of change in PTX 2.3.x. reduction. When code compiled for sm_1x is executed on sm_20 devices. The mad. The fma. The changes from PTX ISA 1.f32. PTX ISA Version 2.rm and . including integer.

0 provides a slightly higher-level abstraction and supports multiple ABI implementations. 1. NOTE: The current version of PTX does not implement the underlying. cvta. special registers.clamp and . Introduction • Single. allowing memory instructions to access these spaces without needing to specify the state space.Chapter 1.and double-precision div..0 closer to full compliance with the IEEE 754 standard. local. and directives are introduced in PTX 2. rcp. New Instructions The following new instructions. 1. stack layout. and red now support generic addressing.2. . ldu. Generic Addressing Another major change is the addition of generic addressing. These are indicated by the use of a rounding modifier and require sm_20. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. A new cvta instruction has been added to convert global. Instructions prefetch and prefetchu have been added. and shared addresses to generic addresses. and shared addresses to generic address and vice-versa has been added. prefetch. and sust.4. and shared state spaces.e. January 24. for prefetching to specified level of memory hierarchy.g. and sqrt with IEEE 754 compliant rounding have been added. 2010 3 . local.3. and vice versa.3. Generic addressing unifies the global.0. Instruction cvta for converting global. atom. an address that is the same across all threads in a warp. Surface Instructions • • Instruction sust now supports formatted surface stores. 1. st. Cache operations have been added to instructions ld. stack-based ABI. i. these changes bring PTX 2.zero. suld. local. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.3. Instructions testp and copysign have been added. e. so recursion is not yet supported. Support for an Application Binary Interface Rather than expose details of a particular calling convention. prefetchu. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. instructions ld. Surface instructions support additional clamp modifiers. and Application Binary Interface (ABI).0. st. isspacep. PTX 2.3. In PTX 2. • Taken as a whole.

%lanemask_{eq. bar now supports an optional thread count and register operands.gt} have been added. A new directive. vote. A “vote ballot” instruction. 4 January 24. membar. Other Extensions • • • Video instructions (includes prmt) have been added.add.section.sys. Barrier Instructions • • A system-level membar instruction.b32. has been added. 2010 .u32 and bar.PTX ISA Version 2. %clock64.red}.f32 have been added. Reduction.red.popc.ballot. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Instructions {atom. . and Vote Instructions • • • New atomic and reduction instructions {atom.{and. New special registers %nsmid. Instructions bar.or}. A bar.arrive instruction has been added. has been added.red}.shared have been extended to handle 64-bit data types for sm_20 targets.lt.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.pred have been added.le.ge.red. bfi bit field extract and insert popc clz Atomic.

calling convention. Chapter 8 describes the instruction set. Chapter 7 describes the function and call syntax. Introduction 1. Chapter 6 describes instruction operands.0. January 24. Chapter 3 gives an overview of the PTX virtual machine model. and PTX support for abstracting the Application Binary Interface (ABI).Chapter 1. types. and variable declarations. 2010 5 . Chapter 11 provides release notes for PTX Version 2. Chapter 4 describes the basic syntax of the PTX language. Chapter 10 lists the assembly directives supported in PTX. Chapter 5 describes state spaces. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 9 lists special registers.4.

0 6 January 24. 2010 .PTX ISA Version 2.

and ntid.Chapter 2. a portion of an application that is executed many times.z) that specifies the thread’s position within a 1D. To coordinate the communication of the threads within the CTA. January 24. Programming Model 2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. or CTA. ntid. work. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Each CTA thread uses its thread identifier to determine its assigned role. 2. but independently on different data. or 3D CTA. one can specify synchronization points where threads wait until all threads in the CTA have arrived.1. Programs use a data parallel decomposition to partition inputs. Cooperative thread arrays (CTAs) implement CUDA thread blocks. Each thread has a unique thread identifier within the CTA.x. To that effect. The thread identifier is a three-element vector tid. compute-intensive portions of applications running on the host are off-loaded onto the device.1. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. or 3D shape specified by a three-element vector ntid (with elements ntid. (with elements tid.y.2. can be isolated into a kernel function that is executed on the GPU as many different threads. It operates as a coprocessor to the main CPU. The vector ntid specifies the number of threads in each CTA dimension. or host: In other words. is an array of threads that execute a kernel concurrently or in parallel. 2D.y. 2D. and select work to perform. assign specific input and output positions. 2010 7 . compute addresses.z).x. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. A cooperative thread array. Each CTA has a 1D. data-parallel. More precisely. 2. Threads within a CTA can communicate with each other. tid. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. and tid. and results across the threads of the CTA.2.

multiple-thread) fashion in groups called warps. or sequentially. 2. so that the total number of threads that can be launched in a single kernel invocation is very large. However. Multiple CTAs may execute concurrently and in parallel. 2D . Threads may read and use these values through predefined. The host issues a succession of kernel invocations to the device. read-only special registers %tid. The warp size is a machine-dependent constant. because threads in different CTAs cannot communicate and synchronize with each other. This comes at the expense of reduced thread communication and synchronization.2. A warp is a maximal subset of threads from a single CTA. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs.PTX ISA Version 2.0 Threads within a CTA execute in SIMT (single-instruction. Each grid of CTAs has a 1D. or 3D shape specified by the parameter nctaid. which may be used in any instruction where an immediate operand is allowed. %nctaid. Some applications may be able to maximize performance with knowledge of the warp size. a warp has 32 threads. %ctaid. Threads within a warp are sequentially numbered. so PTX includes a run-time immediate constant. depending on the platform. 2010 . CTAs that execute the same kernel can be batched together into a grid of CTAs. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). 8 January 24.2. and %gridid. such that the threads execute the same instructions at the same time. Each grid also has a unique temporal grid identifier (gridid). %ntid. WARP_SZ. Typically. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain.

1) Thread (4. A grid is a set of CTAs that execute independently. 1) Thread (0. 0) Thread (3. Thread Batching January 24. 2) Thread (1. 2) Thread (3. 1) Thread (2. Figure 1. 0) CTA (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (2. 1) Thread (3.Chapter 2. 2) Thread (4. 0) CTA (2. 0) Thread (0. 1) CTA (2. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (4. 1) Thread (1. 0) CTA (1. 1) CTA (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2010 9 . 0) Thread (2. 1) Thread (0. 0) Thread (1.

Texture memory also offers different addressing modes. The global.0 2. and texture memory spaces are optimized for different memory usages. all threads have access to the same global memory. The global. The device memory may be mapped and read or written by the host. and texture memory spaces are persistent across kernel launches by the same application. as well as data filtering. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. respectively. Finally.PTX ISA Version 2. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. for some specific data formats. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. constant. constant. for more efficient transfer. 10 January 24.3. referred to as host memory and device memory. or. 2010 . Both the host and the device maintain their own local memory. Each thread has a private local memory.

0) Block (1. 0) Block (0. 1) Block (2. 2) Figure 2. Memory Hierarchy January 24.Chapter 2. 0) Block (0. 1) Block (0. 0) Block (2. 1) Block (1. 0) Block (1. 1) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Block (1. 2010 11 . 1) Grid 1 Global memory Block (0.

2010 .PTX ISA Version 2.0 12 January 24.

When a multiprocessor is given one or more thread blocks to execute.Chapter 3. Parallel Thread Execution Machine Model 3. The multiprocessor SIMT unit creates. multiple-thread). schedules. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. Branch divergence occurs only within a warp. a voxel in a volume. different warps execute independently regardless of whether they are executing common or disjointed code paths.1. the multiprocessor employs a new architecture we call SIMT (single-instruction. 2010 13 . and executes threads in groups of parallel threads called warps. When a host program invokes a kernel grid. January 24. the warp serially executes each branch path taken. allowing. The multiprocessor creates. (This term originates from weaving. for example. a multithreaded instruction unit. and executes concurrent threads in hardware with zero scheduling overhead. disabling threads that are not on that path. increasing thread IDs with the first warp containing thread 0. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. manages. and when all paths complete. so full efficiency is realized when all threads of a warp agree on their execution path.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. the first parallel thread technology. The way a block is split into warps is always the same. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). As thread blocks terminate. new blocks are launched on the vacated multiprocessors. It implements a single-instruction barrier synchronization. A multiprocessor consists of multiple Scalar Processor (SP) cores. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. To manage hundreds of threads running several different programs. At every instruction issue time. the threads converge back to the same execution path. and on-chip shared memory. A warp executes one common instruction at a time. each warp contains threads of consecutive. If threads of a warp diverge via a data-dependent conditional branch. The multiprocessor maps each thread to one scalar processor core. it splits them into warps that get scheduled by the SIMT unit. manages. The threads of a thread block execute concurrently on one multiprocessor. and each scalar thread executes independently with its own instruction address and register state. a cell in a grid-based computation).

SIMT enables programmers to write thread-level parallel code for independent. each read. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. If there are not enough registers or shared memory available per multiprocessor to process at least one block. the kernel will fail to launch. whereas SIMT instructions specify the execution and branching behavior of a single thread. A multiprocessor can execute as many as eight thread blocks concurrently. write to that location occurs and they are all serialized. For the purposes of correctness. • The local and global memory spaces are read-write regions of device memory and are not cached. 14 January 24. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. 2010 . which is a read-only region of device memory. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. A key difference is that SIMD vector organizations expose the SIMD width to the software. require the software to coalesce loads into vectors and manage divergence manually. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. modify.PTX ISA Version 2. however. the number of serialized writes that occur to that location and the order in which they occur is undefined. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. but the order in which they occur is undefined. the programmer can essentially ignore the SIMT behavior. and writes to the same location in global memory for more than one of the threads of the warp. If an atomic instruction executed by a warp reads. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. As illustrated by Figure 3. modifies. scalar threads.0 SIMT architecture is akin to SIMD (Single Instruction. which is a read-only region of device memory. on the other hand. Vector architectures. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. In practice. as well as data-parallel code for coordinated threads. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. but one of the writes is guaranteed to succeed. In contrast with SIMD vector machines.

Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3. Figure 3. 2010 15 .

2010 .PTX ISA Version 2.0 16 January 24.

The following are common preprocessor directives: #include.1. #line.version directive specifying the PTX language version. Source Format Source files are ASCII text. Pseudo-operations specify symbol and addressing management. #else. using non-nested /* and */ for comments that may span multiple lines. Lines beginning with # are preprocessor directives. Lines are separated by the newline character (‘\n’). The C preprocessor cpp may be used to process PTX source files. January 24. All whitespace characters are equivalent. Syntax PTX programs are a collection of text source files. #define. #ifdef.2. 4. followed by a . #if.Chapter 4. #endif. 2010 17 . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. 4. PTX is case sensitive and uses lowercase for keywords. Each PTX file must begin with a . and using // to begin a comment that extends to the end of the current line. See Section 9 for a more information on these directives. whitespace is ignored except for its use in separating tokens in the language.target directive specifying the target architecture assumed. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Comments in PTX are treated as whitespace. Comments Comments in PTX follow C/C++ syntax.

maxntid .tex . . r1. 2010 .maxnctapersm .b32 add. ld. All instruction keywords are reserved tokens in PTX. Instruction keywords are listed in Table 2. The destination operand is first. Table 1.PTX ISA Version 2.align . and is written as @p.shared . shl. 2.global .pragma .3.target . Statements A PTX statement is either a directive or an instruction. %tid. r2.b32 r1.reg . mov.minnctapersm . where p is a predicate register.f32 array[N]. 18 January 24. written as @!p. The guard predicate may be optionally negated.const .b32 r1.section .0 4.f32 r2. Examples: .version .file PTX Directives . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.param . r2. 0.2.x. Directive Statements Directive keywords begin with a dot. Instructions have an optional guard predicate which controls conditional execution. The guard predicate follows the optional label and precedes the opcode.3. array[r1]. constant expressions. Statements begin with an optional label and end with a semicolon.local .global.reg .entry . address expressions. r2. or label names.b32 r1. Operands may be register variables. .sreg . followed by source operands. and terminated with a semicolon.1.5.func .extern .3.loc .visible 4.maxnreg . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.global start: . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. so no conflict is possible with user-defined identifiers.

Syntax Table 2.Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

except that the percentage sign is not allowed. or dollar characters. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. between user-defined variable names and compiler-generated names. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.4. Many high-level languages such as C and C++ follow similar rules for identifier names. %pm3 WARP_SZ 20 January 24. 2010 . PTX predefines one constant and a small number of special registers that begin with the percentage sign. listed in Table 3. The percentage sign can be used to avoid name conflicts. Table 3. dollar. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. or percentage character followed by one or more letters. digits. underscore. or they start with an underscore.0 4.PTX ISA Version 2. underscore. e. digits.g. PTX allows the percentage sign as the first character of an identifier. ….

4. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. where the behavior of the operation depends on the operand types. literals are always represented in 64-bit double-precision format. 2010 21 . For predicate-type data and instructions. the constant begins with 0d or 0D followed by 16 hex digits. and bit-size types. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.u64). Unlike C and C++. The syntax follows that of C. Floating-point literals may be written with an optional decimal point and an optional signed exponent.s64 or the unsigned suffix is specified. each integer constant is converted to the appropriate size based on the data or instruction type at its use. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. in which case the literal is unsigned (.5. there is no suffix letter to specify size. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. 0[fF]{hexdigit}{8} // single-precision floating point January 24.s64) unless the value cannot be fully represented in .2. integer constants are allowed and are interpreted as in C. These constants may be used in data initialization and as operands to instructions.. Syntax 4.u64. To specify IEEE 754 doubleprecision floating point values.5. Integer literals may be written in decimal. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. or binary notation. Type checking rules remain the same for integer. i.1. octal. To specify IEEE 754 single-precision floating point values. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. 4. Constants PTX supports integer and floating-point constants and constant expressions.s64 or .5. floating-point. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. i.Chapter 4. When used in an instruction or data initialization. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. the sm_1x and sm_20 targets have a WARP_SZ value of 32. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. hexadecimal.. every integer constant has type . zero values are FALSE and non-zero values are TRUE.e.e. the constant begins with 0f or 0F followed by 8 hex digits.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64 .f64 integer .s64 . Syntax 4.s64 .u64 1st unchanged.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64.s64 .f64 use usual conversions .f64 same as source .s64 . 2nd is .f64 converted type .f64 converted type constant literal + ! ~ Cast Binary (. Table 5. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 use usual conversions .s64) + .u64 .u64) (.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 same as 1st operand .f64 use usual conversions .u64 . .u64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table. or .6.u64 .s64.s64 .f64 integer .f64 integer integer integer integer integer int ?.s64 .Chapter 4.f64 : .s64 .u64 . 2010 25 .5.s64 .

PTX ISA Version 2. 2010 .0 26 January 24.

defined per-grid. the kinds of resources will be common across platforms.param . All variables reside in some state space. Global texture memory (deprecated). and Variables While the specific resources available in a given target GPU will vary. State Spaces.shared .const .reg . Kernel parameters. Special registers. and properties of state spaces are shown in Table 5. addressability. Types. 5. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. 2010 27 . The list of state spaces is shown in Table 4. The characteristics of a state space include its size. Global memory.Chapter 5. Addressable memory shared between threads in 1 CTA. fast. Read-only. or Function or local parameters. platform-specific. private to each thread. read-only memory. Name State Spaces Description Registers. pre-defined. shared by all threads. Local memory.1. and level of sharing between threads.sreg . Table 6. Shared.tex January 24. defined per-thread. State Spaces A state space is a storage area with particular characteristics. access rights. and these resources are abstracted in PTX through state spaces and data types.local . access speed. .global .

local state space. register variables will be spilled to memory.sreg . 32-. 32-. and thread parameters.e. Registers may be typed (signed integer. or 64-bits. floating point.global . clock counters.reg .param (as input to kernel) . 1 Accessible only via the ld. Device function input parameters may have their address taken via mov.tex Restricted Yes No3 5. Registers may have alignment boundaries required by multi-word loads and stores. or 128-bits.2. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). and vector registers have a width of 16-.shared . 28 January 24. Register size is restricted. For each architecture. scalar registers have a width of 8-. 16-. st. 64-.param (used in functions) ..PTX ISA Version 2.sreg) state space holds predefined.1. 3 Accessible only via the tex instruction.param instructions. and performance monitoring registers. or as elements of vector tuples. The number of registers is limited.0 Table 7. causing changes in performance. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. platform-specific registers.param and st. 5. it is not possible to refer to the address of a register.const . and will vary from platform to platform. The most common use of 8-bit registers is with ld. Registers differ from the other state spaces in that they are not fully addressable. i. aside from predicate registers which are 1-bit.param instruction. predicate) or untyped. such as grid.reg state space) are fast storage locations.1. 2010 . Register State Space Registers (. 2 Accessible via ld. the parameter is then located on the stack frame and its address is in the .local . Special Register State Space The special register (. When the limit is exceeded.1. Address may be taken via mov instruction. All special registers are predefined. CTA. unsigned integer. and cvt instructions. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .

and atom. If another thread sees the variable b change.global. the store operation updating a may still be in flight.const[2]. bank zero is used. Global memory is not sequentially consistent. an incomplete array in bank 2 is accessed as follows: . Banks are specified using the . Local State Space The local state space (.1.b32 const_buffer[].1. If no bank number is given. For example.extern .Chapter 5. ld. all addresses are in global memory are shared. State Spaces. [const_buffer+4].global to access global variables. as it must be allocated on a perthread basis. 5.local to access local variables.local) is private memory for each thread to keep its own data. Module-scoped local memory variables are stored at fixed addresses. // load second word 5.const[2] . Use ld.global) state space is memory that is accessible by all threads in a context. bank zero is used for all statically-sized constant variables. initialized by the host. each pointing to the start address of the specified constant bank. Multiple incomplete array variables declared in the same bank become aliases. and Variables 5. Use ld. the stack is in local memory. For example.sync instruction are guaranteed to be visible to any reads after the barrier instruction.5. 2010 29 . the bank number must be provided in the state space of the load instruction.const[bank] modifier. This reiterates the kind of parallelism available in machines that run PTX.local and st.sync instruction. Threads wait at the barrier until all threads in the CTA have arrived. For the current devices. Types.b32 const_buffer[]. By convention. All memory writes prior to the bar.const) state space is a read-only memory. For any thread in a context.global. b = b – 1. To access data in contant banks 1 through 10. The remaining banks may be used to implement “incomplete” constant arrays (in C.const[2] . This pointer can then be used to access the entire 64KB constant bank.3. Global State Space The global (. The size is limited.b32 %r1. where bank ranges from 0 to 10. as in lock-free and wait-free style programming.1.extern .4. there are eleven 64KB banks. where the size is not known at compile time. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. results in const_buffer pointing to the start of constant bank two. Consider the case where one thread executes the following two assignments: a = a + 1. st. Constant State Space The constant (. Threads must be able to do their work without waiting for other threads to do theirs. whereas local memory variables declared January 24. It is the mechanism by which different CTAs and different grids can communicate. In implementations that support a stack. Sequential consistency is provided by the bar. It is typically standard memory with cache. for example). the declaration . The constant memory is organized into fixed size banks.

Example: . No access protection is provided between parameter and global space in this case. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).param .0 within a function or kernel body are allocated on the stack.u32 %ptr. The resulting address is in the . 5. typically for passing large structures by value to a function. Parameter State Space The parameter (. The use of parameter state space for device function parameters is new to PTX ISA version 2.param state space.reg .param .param. .f64 %d. … Example: . ld. ld.6. read-only variables declared in the . The address of a kernel parameter may be moved into a register using the mov instruction. 2010 . 5. Note that PTX ISA versions 1.u32 %n.f64 %d. The kernel parameter variables are shared across all CTAs within a grid. device function parameters were previously restricted to the register state space. len.entry foo ( . [buffer]. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.reg .param .1. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. … 30 January 24. [%ptr]. Therefore. Similarly.param instructions. [N].param) state space is used (1) to pass input arguments from the host to the kernel.x supports only kernel function parameters in . These parameters are addressable.b32 N. in some implementations kernel parameters reside in global memory. %n. Values passed from the host to the kernel are accessed through these parameter variables using ld.reg .align 8 . PTX code should make no assumptions about the relative locations or ordering of . .u32 %n.b32 len ) { .b8 buffer[64] ) { .u32 %n. Note: The location of parameter space is implementation specific.1.PTX ISA Version 2. mov. all local memory variables are stored at fixed addresses and recursive function calls are not supported. ld.param.1. (2a) to declare formal input and return parameters for device functions called from within kernel execution.u32 %ptr.0 and requires target architecture sm_20.param space. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param space variables.6. For example.param instructions. per-kernel versus per-thread).entry bar ( .param.param state space and is accessed using ld. In implementations that do not support a stack.

x.b32 N. such as C structures larger than 8 bytes. . Typically.f64 [mystruct+0].align 8 . [buffer+8].s32 %y. . and Variables 5. It is not possible to use mov to get the address of a return parameter or a locally-scoped . ld. passed to foo … . call foo. In PTX. is flattened.2.reg . . (4.1.param.b8 mystruct. .param. … } // code snippet from the caller // struct { double d. }.reg .local instructions.6. January 24.param.Chapter 5.param byte array variable that represents a flattened C structure or union.align 8 . State Spaces. a byte array in parameter space is used.s32 [mystruct+8]. … st. Function input parameters may be read via ld. the address of a function input parameter may be moved into a register using the mov instruction. In this case.reg .f64 dbl.reg .reg . This will be passed by value to a callee. The most common use is for passing objects by value that do not fit within a PTX register.param.b8 buffer[12] ) { .param. Note that the parameter will be copied to the stack if necessary.func foo ( .local and st. dbl. } mystruct.param . and so the address will be in the . mystruct). [buffer].s32 x.f64 %d. int y.param and function return parameters may be written using st.param . 2010 31 . st.param space is also required whenever a formal parameter has its address taken within the called function.param space variable. … See the section on function call syntax for more details. Aside from passing structures by value. Example: // pass object of type struct { double d. which declares a .s32 %y. the caller will declare a locally-scoped . .param formal parameter having the same size and alignment as the passed argument. Types.0 extends the use of parameter space to device function parameters. int y. Device Function Parameters PTX ISA version 2.f64 %d. it is illegal to write to an input parameter or read from a return parameter. . ld.local state space and is accessed via ld.

The .shared to access shared variables. Texture State Space (deprecated) The texture (.texref tex_a. and . and variables declared in the .shared and st.tex .texref variables in the . Physical texture resources are allocated on a per-module granularity. tex_f.global state space. The texture name must be of type . 5. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Shared memory typically has some optimizations to support the sharing.texref. tex_d. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).6 for its use in texture instructions.tex . One example is broadcast.u32 . It is shared by all threads in a context.tex . See Section 5.tex variables are required to be defined in the global scope. The . Shared State Space The shared (.u32 .global . a legacy PTX definitions such as . For example.tex directive will bind the named texture memory variable to a hardware texture identifier. Texture memory is read-only. is equivalent to . Example: .tex) state space is global memory accessed via the texture instruction.3 for the description of the . where all threads read from the same address.7. An address in shared memory can be read and written by any thread in a CTA. tex_c.u32 tex_a.u32 . and programs should instead reference texture memory through variables of type .PTX ISA Version 2.tex . Use ld.shared) state space is a per-CTA region of memory for threads in a CTA to share data. tex_d.8. Multiple names may be bound to the same physical texture identifier. 2010 .u64.tex state space are equivalent to module-scoped .7.0 5.u32 tex_a.u32 or .1. where texture identifiers are allocated sequentially beginning with zero. Another is sequential access from sequential threads.1.tex directive is retained for backward compatibility. An error is generated if the maximum number of physical resources is exceeded. 32 January 24.texref type and Section 8.tex . A texture’s base address is assumed to be aligned to a 16-byte boundary.

2. or converted to other types and sizes. The .f16. stored. A fundamental type specifies both a basic type and a size. and converted using regular-width registers. so that narrow values may be loaded. The bitsize type is compatible with any fundamental type having the same size. but typed variables enhance program readability and allow for better operand type checking.1. .s32.2. 5. Two fundamental types are compatible if they have the same basic type and are the same size. .f32.u8. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.Chapter 5. The same typesize specifiers are used for both variable definitions and for typing instructions. . and Variables 5. st. In principle. .u8.b64 .f32 and . and instructions operate on these types. the fundamental types reflect the native data types supported by the target architectures. Types 5. and cvt instructions. For example.f16 floating-point type is allowed only in conversions to and from . .s16. .u32. . 2010 33 . stored. . For convenience.b16. Fundamental Types In PTX.b32.pred Most instructions have one or more type specifiers. and . .2.f64 types.s8. . Register variables are always of a fundamental type. .s64 . January 24. The following table lists the fundamental type specifiers for each basic type: Table 8. Signed and unsigned integer types are compatible if they have the same size. . State Spaces.f32 and . Operand types and sizes are checked against instruction types for compatibility. so their names are intentionally short. Restricted Use of Sub-Word Sizes The . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.f64 . all variables (aside from predicates) could be declared using only bit-size types.f64 types. ld.2.s8.b8 instruction types are restricted to ld.b8. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .u16.u64 . st. Types. All floating-point instructions operate only on . needed to fully specify instruction behavior.

field ordering. and query instructions. suld. base address. sampler. or surfaces via texture and surface load/store instructions (tex. For working with textures and samplers. since these properties are defined by . These types have named fields similar to structures.PTX ISA Version 2. hence the term “opaque”. Creating pointers to opaque variables using mov.0 5. i. PTX has two modes of operation. Retrieving the value of a named member via query instructions (txq. suq).samplerref variables. but the pointer cannot otherwise be treated as an address. and Surface Types PTX includes built-in “opaque” types for defining texture. In the unified mode.texref handle.samplerref. and surface descriptor variables.u64} reg. 34 January 24. allowing them to be defined separately and combined at the site of usage in the program. and overall size is hidden to a PTX program. In independent mode the fields of the . texture and sampler information each have their own handle.e. The three built-in types are . Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. the resulting pointer may be stored to and loaded from memory. or performing pointer arithmetic will result in undefined results.. In the independent mode. Sampler. but all information about layout. samplers. texture and sampler information is accessed through a single .3. and . Texture. accessing the pointer with ld and st instructions. 2010 . and de-referenced by texture and surface load.surfref.texref type that describe sampler properties are ignored. sust. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.{u32. passed as a parameter to functions. store. sured).texref. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. Referencing textures. The following tables list the named members of each type for unified and independent texture modes. . opaque_var.

and Variables Table 9. clamp_to_border N/A N/A N/A N/A N/A . 1 ignored ignored ignored ignored . 2010 35 .Chapter 5. Member width height depth Opaque Type Fields in Independent Texture Mode . Types. clamp_to_edge. clamp_to_edge. State Spaces.texref values . clamp_to_border 0. Member width height depth Opaque Type Fields in Unified Texture Mode . mirror.texref values in elements in elements in elements 0. clamp_ogl. 1 nearest.samplerref values N/A N/A N/A N/A nearest. linear wrap. linear wrap. mirror.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_ogl.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.

filter_mode = nearest }. .texref tex1.global . these variables must be in the . .surfref my_surface_name. these variables are declared in the . At module scope.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. Example: . Example: . When declared at module scope. the types may be initialized using a list of static expressions assigning values to the named members.global . 2010 .texref my_texture_name. As kernel parameters. .global state space.global .param state space.global .global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.PTX ISA Version 2. 36 January 24.samplerref my_sampler_name.

r. . PTX supports types for simple aggregate objects such as vectors and arrays.v4. .v4 . State Spaces.global . its name. 5. This is a common case for three-dimensional grids. Every variable must reside in one of the state spaces enumerated in the previous section. // typedef . and Variables 5. Examples: .global . Variable Declarations All storage for data is specified with variable declarations. vector variables are aligned to a multiple of their overall size (vector length times base-type size). // a length-2 vector of unsigned ints .u8 bg[4] = {0.struct float4 { . 0. // a length-4 vector of floats . In addition to fundamental types. Three-element vectors may be handled by using a .f64 is not allowed.pred p.v1. 1.f32 v0. etc.b8 v.f32 bias[] = {-1.global . 2010 37 .reg .0. its type and size. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . January 24.v2 .s32 i. and they may reside in the register space. .struct float4 coord. . Variables In PTX.shared . and an optional fixed address for the variable.v4 vector. 0. an optional initializer.4.2. A variable declaration names the space in which the variable resides. Vectors must be based on a fundamental type. 0}. Examples: .v3 }.u16 uv.f32 V. q.Chapter 5.0}. // a length-4 vector of bytes By default. 5. .global .v4.1.v4 . Vectors Limited-length vector types are supported.4. Types.reg .global . where the fourth element provides padding. for example.f32 accel.v2 or . to enable vector load and store instructions which require addresses aligned to a multiple of the access size. a variable declaration describes both the variable’s type and its state space. Vectors cannot exceed 128-bits in length.reg .u32 loc. textures.v4 . Predicate variables may only be declared in the register state space.4. . an optional array size.const . .v2.

this can be used to initialize a jump table to be used with indirect branches or calls.u64. variable initialization is supported only for constant and global state spaces.0. .4.4.u8 rgba[3] = {{1. {0. 19*19 (361) halfwords are reserved (722 bytes). . Array Declarations Array declarations are provided to allow the programmer to reserve space. Initializers are allowed for all types except . {1.0 5.4.. being determined by an array initializer.u32 or . this can be used to statically initialize a pointer to a variable.u16 kernel[19][19].shared .{. To declare an array. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).1}..s32 n = 10.. -1}.f16 and .0}.f32 blur_kernel[][] = {{. or is left empty.. For the kernel declaration above.b32 ptr = rgba. 38 January 24. 0}. The size of the array specifies how many elements should be reserved.1. // address of rgba into ptr Currently.05..global .05}}. . Initializers Declared variables may specify an initial value using a syntax similar to C/C++.s32 offset[][] = { {-1.4. A scalar takes a single value.pred. Examples: .0}.PTX ISA Version 2. The size of the dimension is either a constant expression.0}}.0.v4 .05. label names appearing in initializers represent the address of the next instruction following the label.global .1. {0. 2010 .0. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. . where the variable name is followed by an equals sign and the initial value or values for the variable..{. 1} }.global .u8 mailbox[128]. Here are some examples: . 0}.global . {0.1. Variables that hold addresses of variables or instructions should be of type .local .global . . {0.05}. Similarly.1.3. Variable names appearing in initializers represent the address of the variable.1. 5.0.

%r1. alignment specifies the address alignment for the starting address of the entire array. // declare %r0.b32 variables.4. Array variables cannot be declared this way. 5. it is quite common for a compiler frontend to generate a large number of register names. The default alignment for scalar and array variables is to a multiple of the base-type size. State Spaces.0. suppose a program uses a large number. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. Elements are bytes. Types.align byte-count specifier immediately following the state-space specifier. For example.b8 bar[8] = {0.. not for individual elements.0.0. %r99. .0}. nor are initializers permitted. January 24. Alignment is specified using an optional . Rather than require explicit declaration of every name. and Variables 5.2. These 100 register variables can be declared as follows: . …. and may be preceded by an alignment specifier. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Examples: // allocate array at 4-byte aligned address. The variable will be aligned to an address which is an integer multiple of byte-count. %r1.b32 %r<100>.6. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. .0.Chapter 5. 2010 39 .align 4 . The default alignment for vector variables is to a multiple of the overall vector size. named %r0.0. of . For arrays. say one hundred..5.4..const .reg . Parameterized Variable Names Since PTX supports virtual registers.

PTX ISA Version 2.0 40 January 24. 2010 .

mov.Chapter 6. The mov instruction copies data between registers. Instruction Operands 6. and cvt instructions copy data from one location to another. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.2. s. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Source Operands The source operands are denoted in the instruction descriptions by the names a. Operand Type Information All operands in instructions have a known type from their declarations. st. so operands for ALU instructions must all be in variables declared in the . r. 2010 41 . Integer types of a common size are compatible with each other. The ld.1. Each operand type must be compatible with the type determined by the instruction template and instruction type. January 24. For most operations. There is no automatic conversion between types. The bit-size type is compatible with every type having the same size.reg register state space. q.3. PTX describes a load-store machine. Most instructions have an optional predicate guard that controls conditional execution. Instructions ld and st move data from/to addressable state spaces to/from registers. Predicate operands are denoted by the names p. The cvt (convert) instruction takes a variety of operand types and sizes. b. The result operand is a scalar or vector variable in the register state space. and c. 6. 6. and a few instructions have additional predicate source operands. as its job is to convert from nearly any data type to any other data type (and size). the sizes of the operands must be consistent. .

0 6.4. . arrays.1.f32 ld. Using Addresses. and Vectors Using scalar variables as operands is straightforward. there is no support for C-style pointer arithmetic.[x]. r0. . .v4. and vectors.f32 V. W. q.s32 q. 6. The mov instruction can be used to move the address of a variable into a pointer. address register plus byte offset. .s32 mov.shared.const.u32 42 January 24.v4 .reg .u16 r0.s32 tbl[256].const .f32 W. All addresses and address computations are byte-based.PTX ISA Version 2.4.reg .v4 .shared . Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.u16 x. 2010 . [tbl+12]. The syntax is similar to that used in many assembly languages. . p.gloal. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. . tbl. and immediate address expressions which evaluate at compile-time to a constant address. ld. Here are a few examples: . The address is an offset in the state space in which the variable is declared. address registers. Load and store operations move data between registers and locations in addressable state spaces. Address expressions include variable names. Examples include pointer arithmetic and pointer comparisons. [V].b32 p.reg .reg . Arrays. The interesting capabilities begin with addresses.u16 ld.global .

Rb. where the offset is a constant expression that is either added or subtracted from a register variable.z V. . . Array elements can be accessed using an explicitly calculated byte address. mov. [addr+offset2].Chapter 6. V.u32 {a.u32 s. V2.c.2.4. .v4. mov.g V. a[N-1].global. The size of the array is a constant in the program.global. and tex.f32 a.b V.v2. or a simple “register with constant offset” expression. st.3. ld. it must be written as an address calculation prior to use. which may improve memory performance.v4 .w = = = = V.f32 {a.z and .b. or by indexing into the array using square-bracket notation. [addr+offset].d}. // move address of a[1] into s 6.g. say {Ra.y V.global. A brace-enclosed list is used for pattern matching to pull apart vectors.4.a.a 6. a[0]. . Vector elements can be extracted from the vector with the suffixes .r.x V. ld.4. .x. and the identifier becomes an address constant in the space where the array is declared. and in move instructions to get the address of the label or function into a register.y. or a braceenclosed list of similarly typed scalars. Vectors may also be passed as arguments to called functions. Examples are ld. January 24. Here are examples: ld. which include mov.w.f32 V.global.reg . Vector loads and stores can be used to implement wide loads and stores. b. .d}.f32 ld. 2010 43 . The registers in the load/store operations can be a vector.b. Vectors as Operands Vector operands are supported by a limited subset of instructions. Rc. Elements in a brace-enclosed vector.4. Arrays as Operands Arrays of all types can be declared.reg .r V. The expression within square brackets is either a constant integer.b and . as well as the typical color fields . for use in an indirect branch or call. If more complicated indexing is desired.v4. Instruction Operands 6. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.c. d. a register variable. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. Rd}. c.u32 s. a[1].u32 s.

Type Conversion All operands to all arithmetic. if a cvt. except for operations where changing the size and/or type is part of the definition of the instruction. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. and data movement instruction must be of the same type and size.1. 2010 .s32. logic. 44 January 24. Operands of different sizes or types must be converted prior to the operation.5.0 6.5. the u16 is zero-extended to s32.PTX ISA Version 2. and ~131. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.u16 instruction is given a u16 source operand and s32 as a destination operand. For example.000 for f16). 6.

f2s = float-to-signed. Instruction Operands Table 11.s16. f2u = float-to-unsigned. u2f = unsigned-to-float. The type of extension (sign or zero) is based on the destination format.u32 targeting a 32-bit register will first chop to 16-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. s2f = signed-to-float. chop = keep only low bits that fit. then sign-extend to 32-bits. For example. January 24. f2f = float-to-float. zext = zero-extend. the result is extended to the destination register width after chopping. cvt. 2010 45 .Chapter 6. Notes 1 If the destination register is wider than the destination format.

rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.2.rpi Integer Rounding Modifiers Description round to nearest integer.5.rni . Modifier .rzi .rn . choosing even integer if source is equidistant between two integers.rz . 2010 . Table 12.rm .rmi . Modifier . there are four integer rounding modifiers and four floating-point rounding modifiers.PTX ISA Version 2. In PTX. Rounding Modifiers Conversion instructions may specify a rounding modifier.0 6. The following tables summarize the rounding modifiers.

Table 14.Chapter 6. first access is high Notes January 24.6. Operand Costs Operands from different state spaces affect the speed of an operation. Registers are fastest. 2010 47 . Much of the delay to memory can be hidden in a number of ways. while global memory is slowest. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Another way to hide latency is to issue the load instructions as early as possible. The register in a store operation is available much more quickly. Instruction Operands 6. Table 11 gives estimates of the costs of using different kinds of memory. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.

2010 .0 48 January 24.PTX ISA Version 2.

1. January 24. and is represented in PTX as follows: . Scalar and vector base-type input and return parameters may be represented simply as register variables. These include syntax for function definitions. and return values may be placed directly into register variables. parameter passing.Chapter 7. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and an optional list of input parameters. or prototype. … Here. A function must be declared or defined prior to being called. Abstracting the ABI Rather than expose details of a particular calling convention. and memory allocated on the stack (“alloca”). arguments may be register variables or constants. stack layout. support for variadic functions (“varargs”). 2010 49 . functions are declared and defined using the . A function declaration specifies an optional list of return parameters. The simplest function has no parameters or return values. At the call. A function definition specifies both the interface and the body of the function. Function declarations and definitions In PTX. NOTE: The current version of PTX does not implement the underlying. Execution of the ret instruction within foo transfers control to the instruction following the call. } … call foo.func directive. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. stack-based ABI. and Application Binary Interface (ABI).func foo { … ret. 7. together these specify the function’s interface. function calls. implicitly saving the return address. the function name. so recursion is not yet supported. execution of the call instruction transfers control to foo. we describe the features of PTX needed to achieve this hiding of the ABI. In this section.

consider the following C structure. . [y+10]. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . ld. [y+8]. } … call (%r1). [y+0]. inc_ptr. ld.param.param.b8 c1.param space call (%out).b8 [py+ 8].func (.f64 f1.reg . %ptr. st.param.f1.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.u32 %res) inc_ptr ( . note that . … … // computation using x.b8 [py+11].func (.param state space is used to pass the structure by value: . In PTX. .align 8 y[12]) { .b64 [py+ 0]. %rd.align 8 py[12]. … st.u32 %ptr.b8 .b8 [py+10]. } { .PTX ISA Version 2.s32 out) bar (. First. 2010 . … In this example. 50 January 24.b32 c1.c4.param. bumpptr. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .u32 %res.param. … ld. c4. For example. }. this structure will be flattened into a byte array. %inc.b8 c2.reg . ld. %rc1. The .0 Example: .param .b8 [py+ 9].f64 field are aligned. (%r1. // scalar args in . [y+11]. [y+9].param variable y is used in function definition bar to represent a formal parameter.u32 %inc ) { add. st. py).b8 c4. %rc2. (%x.param space variables are used in two ways.param. st.c3.reg .param.reg space.param. a . c2. a . st.f64 f1.param.reg .c1. %rc2.param space memory. %rc1.reg .reg .reg . ret.param .b8 c3.b8 .s32 x. passed by value to a function: struct { double dbl.c2.param.4). Since memory accesses are required to be aligned to a multiple of the access size. . char c[4]. c3. byte array in . ld. Second.

8. Typically. 2010 51 . • • Arguments may be .param byte array is used to collect together fields of a structure being passed by value. The . January 24.param and ld. and alignment.param state space is used to receive parameter values and/or pass return values back to the caller. all st. The . A . Note that the choice of .param argument must be declared within the local scope of the caller. .reg space formal parameters.param space byte array with matching type.reg or . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param memory must be aligned to a multiple of 1. This enables backend optimization and ensures that the .param instructions used for argument passing must be contained in the basic block with the call instruction. In the case of . or a constant that can be represented in the type of the formal parameter. For .reg variables. Supporting the .param or .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. • The . • • • Input and return parameters may be . 4.reg space variable of matching type and size. In the case of . the argument must also be a . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. a . • The . Abstracting the ABI The following is a conceptual way to think about the .g.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. or 16 bytes. or constants.reg variables. Parameters in .param or .reg state space in this way provides legacy support.. 2. or a constant that can be represented in the type of the formal parameter. For a callee.reg space variable with matching type and size. The following restrictions apply to parameter passing.Chapter 7.param variables.param space formal parameters that are base-type scalar or vector variables. For a caller.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. and alignment of parameters. size.param arguments.param variables or . the corresponding argument may be either a . size. In the case of .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. the corresponding argument may be either a .reg state space can be used to receive and return base-type scalar and vector values. For a caller.param space formal parameters that are byte arrays. • • • For a callee.param state space use in device functions.

formal parameters may be in either . Objects such as C structures were flattened and passed or returned using multiple registers.reg or . PTX 1.x In PTX ISA version 1.param state space.1. Changes from PTX 1.0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays. PTX 2. and . PTX 2. and there was no support for array parameters. 52 January 24.reg state space.0.param byte array should be used to return objects that do not fit into a register. and a . formal parameters were restricted to . In PTX ISA version 2. 2010 . For sm_2x targets.x supports multiple return values for this purpose.0 7.0 restricts functions to a single return value.PTX ISA Version 2.1.x.

%va_end is called to free the variable argument list handle. Abstracting the ABI 7. call (val).b32 val) %va_arg (.u32 a.func ( .b32 ctr. 8.h and varargs. variadic functions are declared with an ellipsis at the end of the input parameter list. The function prototypes are defined as follows: . ctr. For %va_arg. call %va_end. . %va_arg. … call (%max). 2. the size may be 1..reg .reg . .func (. maxN.pred p. . %r2.b32 result.func okay ( … ) Built-in functions are provided to initialize. ) { . or 16 bytes.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . In PTX.u32 sz.reg . ctr. or 8 bytes.b64 val) %va_arg64 (. or 4 bytes. 4. This handle is then passed to the %va_arg and %va_arg64 built-in functions. mov.reg .s32 val. Once all arguments have been processed.reg . bra Loop.reg . %s2).u32 N. %r1.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg . (2. 4.func (. . the alignment may be 1.2. bra Done.reg .u32 align) .u32 sz. 0.u32.u32 ptr) %va_start .func baz ( . (3. max.s32 result.func (. maxN.reg . 2. along with the size and alignment of the next data value to be accessed. (ap. … %va_start returns Loop: @p Done: January 24.reg .reg . 0x8000000. call (ap). . .func %va_end (. result.u32 align) . 4). (ap). ret. %r3).u32 ptr. %s1. iteratively access.Chapter 7. and end access to a list of variable arguments.u32 b. . // default to MININT mov.u32 ap. 2.reg . PTX provides a high-level mechanism similar to the one provided by the stdarg. 2010 53 . 4.reg . following zero or more fixed parameters: ..h headers in C.ge p. for %va_arg64. val. %va_start. To support functions with a variable number of arguments. In both cases.reg . setp. } … call (%max).s32 result ) maxN ( . . … ) . N. the size may be 1.u32 ptr.reg .

reg . To allocate memory.func ( . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.3. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. 54 January 24. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.PTX ISA Version 2. If a particular alignment is required. defined as follows: .local instructions. Alloca NOTE: The current version of PTX does not support alloca. The array is then accessed with ld. a function simply calls the built-in function %alloca.u32 ptr ) %alloca ( .0 7.local and st.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.reg . 2010 .

s32. 2010 55 . For instructions that create a result value. // p = (a < b). The setp instruction writes two destination registers. the semantics are described. B. B.lt p|q.1. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. opcode A. PTX Instructions PTX instructions generally have from zero to four operands. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. opcode D. Instruction Set 8. A. a. q = !(a < b).2. We use a ‘|’ symbol to separate multiple destination registers. B. A. and C are the source operands. setp. In addition to the name and the format of the instruction. opcode D. the D operand is the destination operand. 8. opcode D.Chapter 8. b. C. January 24. For some instructions the destination operand is optional. A. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. while A. followed by some examples that attempt to show several possible instantiations of the instruction.

s32 p. This can be written in PTX as @p setp.s32 j. Predicated Execution In PTX. optionally negated. the following PTX instruction sequence might be used: @!p L1: setp.pred p.pred as the type specifier.lt. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.lt. branch over 56 January 24. use a predicate to control the execution of the branch or call instructions.0 8. To implement the above example as a true conditional branch. add 1 to j To get a conditional branch or conditional function call.3. 2010 . where p is a predicate variable. predicate registers can be declared as . Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 p.reg . add. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. 1. … // compare i to n // if false. q. j.s32 j. i.PTX ISA Version 2. 1. As an example. predicate registers are virtual and have . j. consider the high-level code if (i < n) j = j + 1. add. So. n. i. Instructions without a guard predicate are executed unconditionally. // p = (i < n) // if i < n. n. bra L1.

2010 57 . Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Table 16. le.2.1. ordering comparisons are not defined for bit-size types. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. lt (less-than).1. and hs (higher-or-same).1. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. Instruction Set 8. lo (lower). and ge (greater-than-or-equal). If either operand is NaN. Unsigned Integer. Comparisons 8.1. ne (not-equal). hi (higher). Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Table 15. ls (lower-or-same).3. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. and bitsize types. gt (greater-than).3. ge. The unsigned comparisons are eq. ne. unsigned integer. The bit-size comparisons are eq and ne. lt. le (less-than-or-equal).Chapter 8. The following table shows the operators for signed integer. gt. the result is false.3. ne.

Table 17.0 To aid comparison operations in the presence of NaN values. or.2. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. and no direct way to load or store predicate register values. for example: selp.1.%p. neu. and nan returns true if either operand is NaN.0. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. setp can be used to generate a predicate from an integer. two operators num (numeric) and nan (isNaN) are provided.3. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. If either operand is NaN. However. There is no direct conversion between predicates and integer values. // convert predicate to 32-bit value 58 January 24. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. If both operands are numeric values (not NaN). xor.PTX ISA Version 2. then these comparisons have the same result as their ordered counterparts. Table 18. num returns true if both operands are numeric values (not NaN). ltu.u32 %r1. gtu. unordered versions are included: equ. geu. leu. then the result of these comparisons is true. not. and mov. 2010 .

float. 2010 59 .bX .uX ok ok ok inv . i.sX ok ok ok inv . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.u16 a. the add instruction requires type and size information to properly perform the addition operation (signed. they must match exactly. • The following table summarizes these type checking rules. a. most notably the data conversion instruction cvt. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. It requires separate type-size modifiers for the result and source. and this information must be specified as a suffix to the opcode.u16 d.f32 d. Example: . unsigned..Chapter 8.reg . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 d. Table 19. Floating-point types agree only if they have the same size.sX . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.f32. and these are placed in the same order as the operands.reg .fX ok inv inv ok Instruction Type .bX . For example. For example: . cvt.e. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. and integer operands are silently cast to the instruction type if needed.4. add. a.reg . Type Checking Rules Operand Type . b. b.fX ok ok ok ok January 24. Instruction Set 8. For example. different sizes).u16 d. .uX . Signed and unsigned integer types agree provided they have the same size. a.

no conversion needed. the cvt instruction does not support . Source register size must be of equal or greater size than the instruction-type size. Notes 3.1. 60 January 24. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type.4. Bit-size source registers may be used with any appropriately-sized instruction type. The following table summarizes the relaxed type-checking rules for source operands. so that narrow values may be loaded. ld. Note that some combinations may still be invalid for a particular instruction. the data will be truncated. Operand Size Exceeding Instruction-Type Size For convenience. so those rows are invalid for cvt. stored. Table 20.PTX ISA Version 2. and converted using regular-width registers. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. stored. 1. or converted to other types and sizes. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. 4. “-“ = allowed. Floating-point source registers can only be used with bit-size or floating-point instruction types. unless the operand is of bit-size type. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. for example. When used with a narrower bit-size type. inv = invalid. 2. the size must match exactly. The data is truncated to the instruction-type size and interpreted according to the instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. st. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.bX instruction types. parse error. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. For example. When a source operand has a size that exceeds the instruction-type size. When used with a floating-point instruction type.0 8. 2010 . floating-point instruction types still require that the operand type-size matches exactly.

The data is sign-extended to the destination register width for signed integer instruction types.or sign-extended to the size of the destination register. 1. zext = zero-extend. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. the data is sign-extended.Chapter 8. the data will be zero-extended. the data is zeroextended. otherwise. “-“ = Allowed but no conversion needed. Table 21. The following table summarizes the relaxed type-checking rules for destination operands. the destination data is zero. Destination register size must be of equal or greater size than the instruction-type size. When used with a narrower bit-size instruction type. 2010 61 . the size must match exactly. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. January 24. inv = Invalid. 4. Bit-size destination registers may be used with any appropriately-sized instruction type. If the corresponding instruction type is signed integer. When used with a floatingpoint instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. parse error. and is zero-extended to the destination register width otherwise. 2. Instruction Set When a destination operand has a size that exceeds the instruction-type size. The data is signextended to the destination register width for signed integer instruction types. Notes 3.

Therefore. Both situations occur often in programs. The semantics are described using C.6. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.0 8.1.6. If all of the threads act in unison and follow a single control flow path.uni suffix. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. so it is important to have divergent threads re-converge as soon as possible. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. the threads are called divergent. by a right-shift instruction. using the . When executing on a 32-bit data path. 16-bit registers in PTX are mapped to 32-bit physical registers. until they come to a conditional control construct such as a conditional branch. 8. this is not desirable.5. at least in appearance. and 16-bit computations are “promoted” to 32-bit computations. At the PTX language level. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. conditional function call. the optimizing code generator automatically determines points of re-convergence. However. until C is not expressive enough. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. a compiler or code author targeting PTX can ignore the issue of divergent threads. If threads execute down different control flow paths.PTX ISA Version 2. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. Divergence of Threads in Control Constructs Threads in a CTA execute together. for example. These extra precision bits can become visible at the application level. and for many applications the difference in execution is preferable to limiting performance. or conditional return. 8. for many performance-critical applications. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. the semantics of 16-bit instructions in PTX is machine-specific. A compiler or programmer may chose to enforce portable. the threads are called uniform. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 2010 . For divergent control flow. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. 62 January 24.

cc.7.cc.Chapter 8. addc sub. In the following descriptions. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.1. Instruction Set 8. the optional guard predicate is omitted from the syntax. The Integer arithmetic instructions are: add sub add. Instructions All PTX instructions may be predicated. 8.7. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 2010 63 .

.u64.0 Table 22.type = { .u32. // .s16. . b.z. sub.u32. Supported on all target architectures.sat applies only to . d.s32.sat}. @p add. Applies only to .0. b.s32 c.c.0.u32 x.u16.u64. sub. . // . b. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add Syntax Integer Arithmetic Instructions: add Add two values.s32 type.b.sat}.s32 ..type = { . a.MAXINT (no overflow) for the size of the operation. Introduced in PTX ISA version 1. add. a.s32 d.sat limits result to MININT. Saturation modifier: .PTX ISA Version 2. d. PTX ISA Notes Target ISA Notes Examples Table 23. 2010 ..s32. Introduced in PTX ISA version 1. b. PTX ISA Notes Target ISA Notes Examples 64 January 24. . . a.a. Applies only to .u16.sat limits result to MININT. .type add{.type sub{. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. .MAXINT (no overflow) for the size of the operation. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.sat.sat applies only to . add. . d = a + b.s32 d. .s32 c.y.s32 type. d = a – b. a.s64 }.s64 }.s32 .1. Saturation modifier: . . Supported on all target architectures.s16.

Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc}.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.y4. x3. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. if . . Introduced in PTX ISA version 1. or testing the condition code.cc.b32 addc. sub.y1.2.y2.type = { . b.y4. Behavior is the same for unsigned and signed integers. clearing. .b32 x1.z2. x4. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. addc{. and there is no support for setting.z1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Table 24. . Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. add.cc. addc.type = {.cc.CF No integer rounding modifiers. Instruction Set Instructions add.b32 addc.Chapter 8.cc.cc Syntax Integer Arithmetic Instructions: add.cc.cc specified. x2. @p @p @p @p add.z4. No other instructions access the condition code.z3. add.y3.z3.y2.type d. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc Add two values with carry-out.cc. 2010 65 .CF. d = a + b. carry-out written to CC.2.cc. a. Supported on all target architectures.s32 }.CF No integer rounding modifiers.u32. x2.cc.b32 addc. a.b32 x1.b32 addc.u32.y3.z2. No saturation. b. Supported on all target architectures.cc. carry-out written to CC. Introduced in PTX ISA version 1. x4.CF) holding carry-in/carry-out or borrowin/borrow-out.b32 addc.y1. @p @p @p @p add. No saturation.s32 }.cc.z4. These instructions support extended-precision integer addition and subtraction. . d = a + b + CC. x3.b32 addc. Behavior is the same for unsigned and signed integers.z1.type d.

cc.b32 x1.u32.cc. Behavior is the same for unsigned and signed integers.b32 x1.3.CF No integer rounding modifiers.z3.0 Table 26. b.s32 }.cc specified. borrow-out written to CC. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. borrow-out written to CC.CF).u32. @p @p @p @p sub.b32 subc. x3. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. Introduced in PTX ISA version 1.y3.cc Subract one value from another. with borrow-out.z4.z3.cc.y2. d = a . withborrow-in and optional borrow-out.type = {. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. x2.y2.3. sub. if . . subc{.y1.CF No integer rounding modifiers. Supported on all target architectures.b32 subc. x4.z1. x4.cc. No saturation.cc. . x3.cc Syntax Integer Arithmetic Instructions: sub. a.b32 subc. Behavior is the same for unsigned and signed integers.type = { .cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc.b32 subc.b32 subc. @p @p @p @p sub.b32 subc. Supported on all target architectures. No saturation. Introduced in PTX ISA version 1.cc. 2010 .type d. .y1.PTX ISA Version 2.s32 }.cc.z4.(b + CC.cc}.y4. sub. a.z2.y3. . d = a – b.z1. x2.z2.type d.y4. b. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.

x. a.hi variant // for . mul Syntax Integer Arithmetic Instructions: mul Multiply two values. d = t<n-1.lo variant Notes The type of the operation represents the types of the a and b operands.u16.type = { . Instruction Set Table 28.lo.wide // for .wide}. creates 64 bit result January 24. mul.s16.s64 }.type d. n = bitwidth of type. and either the upper or lower half of the result is written to the destination register.0>. mul{. b. If .hi.wide.s16 fa. d = t<2n-1.hi or .lo. . mul.Chapter 8..s32. Description Semantics Compute the product of two values. The ..s32 z.u32.and 32-bit integer types.y.fys.fxs. . save only the low 16 bits // 32*32 bits. then d is the same size as a and b. If .u64. Supported on all target architectures.wide is specified.fxs.. d = t. . mul. t = a * b. // 16*16 bits yields 32 bits // 16*16 bits. .0..wide.wide suffix is supported only for 16. .fys. // for .n>. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . then d is twice as wide as a and b to receive the full result of the multiplication. 2010 67 .lo is specified.s16 fa.

. and either the upper or lower half of the result is written to the destination register..s32 d. . // for .hi. mad. . 2010 . c. c. then d and c are twice as wide as a and b to receive the result of the multiplication.hi or .. The .wide suffix is supported only for 16.s64 }.u16. Applies only to .n> + c. Supported on all target architectures.r.lo variant Notes The type of the operation represents the types of the a and b operands. . Description Semantics Multiplies two values and adds a third. b.c. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 68 January 24.and 32-bit integer types. then d and c are the same size as a and b.q.lo.a. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.type mad.wide // for . bitwidth of type.lo.0 Table 29.u64. d.sat.wide}.wide is specified. t<2n-1..lo is specified. t n d d d = = = = = a * b.0. and then writes the resulting value into a destination register. .0> + c. b.lo. a.p.s16. a. If . If . mad{. @p mad.s32 d. ..u32..sat limits result to MININT.hi variant // for .type = { .s32 r.b.s32 type in .hi.MAXINT (no overflow) for the size of the operation. Saturation modifier: .PTX ISA Version 2.s32.hi mode. t<n-1. t + c.

Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. January 24..type = { .hi. mul24.s32 }. mul24. a. mul24.u32.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24. // low 32-bits of 24x24-bit signed multiply.type d. d = t<47. i. b.0>. Supported on all target architectures.16>.. . mul24{.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. 48bits.hi variant // for .lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. Instruction Set Table 30.b.a. and return either the high or low 32-bits of the 48-bit result.Chapter 8.. t = a * b.hi may be less efficient on machines without hardware support for 24-bit multiply. d = t<31. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .s32 d. All operands are of the same type and size.lo.0.e. 2010 69 . // for . mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.lo}.

hi mode. d. Return either the high or low 32-bits of the 48-bit result. mad24. t = a * b. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. mad24.type mad24.hi may be less efficient on machines without hardware support for 24-bit multiply..lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.16> + c. and add a third. // low 32-bits of 24x24-bit signed multiply. mad24. .hi..s32 d. d = t<47.lo}. // for .. c. 48bits.PTX ISA Version 2. All operands are of the same type and size. i.u32.0> + c. a. Description Compute the product of two 24-bit integer values held in 32-bit source registers.b. Applies only to ..a.0. 32-bit value to either the high or low 32-bits of the 48-bit result. mad24.sat.s32 type in . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type = { . Supported on all target architectures.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. 2010 .hi.0 Table 31. . Saturation modifier: . 70 January 24.lo. d = t<31.s32 }.c.s32 d.MAXINT (no overflow).sat limits result of 32-bit signed addition to MININT.hi variant // for . mad24{.e.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. c. b. a. b.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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type d. } else { max = 64.u32 PTX ISA Notes Target ISA Notes Examples Table 40. } Introduced in PTX ISA version 2. cnt. inclusively. .u32 Semantics 74 January 24. // cnt is . For . d = 0. cnt.b32. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. a.b32 clz. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. d = 0. a. X.b64 }. clz requires sm_20 or later. . the number of leading zeros is between 0 and 64. a = a >> 1. a.0.b64 d.0 Table 39. For . while (a != 0) { if (a&0x1) d++. the number of leading zeros is between 0 and 32.b32 type. popc requires sm_20 or later. mask = 0x80000000.type = { .0. popc Syntax Integer Arithmetic Instructions: popc Population count. a. clz.b64 d.b64 type. X. } while (d < max && (a&mask == 0) ) { d++. popc.b32 popc. .b64 }.b32) { max = 32.type == .type d.b32.type = { . mask = 0x8000000000000000. inclusively.PTX ISA Version 2. if (. a = a << 1. popc. . // cnt is . 2010 . clz.

type==.u32 January 24.s32) ? 31 : 63. a.u32. Instruction Set Table 41. bfind.u32 d.shiftamt.shiftamt && d != -1) { d = msb . If . bfind returns the bit position of the most significant “1”.s32.type bfind. Description Find the bit position of the most significant non-sign bit in a and place the result in d. For unsigned integers. break.type = { . a. bfind requires sm_20 or later.d.u32.Chapter 8. bfind returns 0xFFFFFFFF if no non-sign bit is found. For signed integers.type d. a. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. and operand d has type .u64.0. Operand a has the instruction type. Semantics msb = (. . } } if (. 2010 75 . bfind. // cnt is .shiftamt is specified. d. X. .s64 cnt.u32 || .s64 }.type==. i>=0. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shiftamt. bfind. d = -1. . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. i--) { if (a & (1<<i)) { d = i. for (i=msb.

brev. brev requires sm_20 or later. brev.type d.type==.type = { . . a. msb = (. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. 2010 . Description Semantics Perform bitwise reversal of input.PTX ISA Version 2. i++) { d[i] = a[msb-i].b32) ? 31 : 63.0. a. 76 January 24. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 42.b32. i<=msb.b64 }. . for (i=0.b32 d.

. Source b gives the bit field starting bit position. If the start position is beyond the msb of the input.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.u32.s64 }. else sbit = a[min(pos+len-1. a.u64: .u32 || . Description Extract bit field from a and place the zero or sign-extended result in d. len = c.0.type==. Operands a and d have the same type as the instruction type. bfe requires sm_20 or later. the result is zero. Semantics msb = (.s32.u32.start.Chapter 8.u64.u32 || . bfe. bfe. The destination d is padded with the sign bit of the extracted field. the destination d is filled with the replicated sign bit of the extracted field. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. January 24.type==. .msb)]. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. b.type==.b32 d.type==. c. if (. Instruction Set Table 43.type d. . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u64 || len==0) sbit = 0. otherwise If the bit field length is zero. d = 0. and operands b and c are type . .a.s32) ? 31 : 63. for (i=0.u32.type = { . and source c gives the bit field length in bits. 2010 77 . i<=msb.s32.len. The sign bit of the extracted field is defined as: . . pos = b.

b. bfi.PTX ISA Version 2. and f have the same type as the instruction type. Description Align and insert a bit field from a into b. for (i=0. and source d gives the bit field length in bits. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.type = { . Semantics msb = (. len = d. and place the result in f. If the bit field length is zero. .len. c.b. bfi. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 44. a.b32) ? 31 : 63. f = b. the result is b. d. 78 January 24. i<len && pos+i<=msb.b32 d. i++) { f[pos+i] = a[i]. 2010 .type f.a. If the start position is beyond the msb of the input. . and operands c and d are type . Source c gives the starting bit position for the insertion. the result is b.start. b.0. Operands a.b32.b64 }.u32.type==. pos = c. bfi requires sm_20 or later.

ecr. c.rc16 }. msb=1 means replicate the sign.Chapter 8.mode} d.b32{. default mode index d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. a} = {{b7. msb=0 means copy the literal value. b4}. as a 16b permute code.mode = { . The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.rc8. Instruction Set Table 45. . .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. the four 4-bit values fully specify an arbitrary byte permute. b0}}. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. b. Note that the sign extension is only performed as part of generic form. .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. the permute control consists of four 4-bit selection values.b2 source select c[11:8] d.f4e. In the generic form (no mode specified). prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. a. Thus. b6.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. {b3. . . For each byte in the target register. b5. Description Pick four arbitrary bytes from two 32-bit registers. 2010 79 . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b3 source select c[15:12] d.b1 source select c[7:4] d. The msb defines if the byte value should be copied. and reassemble them into a 32-bit destination register.ecl.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b4e. b1. The bytes in the two source registers are numbered from 0 to 7: {b. prmt. a 4-bit selection value is defined. . b2.

} else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp[23:16] = ReadByte( mode. r3. tmp64 ). 80 January 24. ctl[0]. prmt.f4e r1.0. r4.b32 prmt. tmp[15:08] = ReadByte( mode. ctl[2]. ctl[2] = (c >> 8) & 0xf. ctl[3]. ctl[1] = (c >> 4) & 0xf. r3. tmp64 ). 2010 . tmp64 ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r1. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r4. tmp64 ). tmp[31:24] = ReadByte( mode. ctl[1]. r2.PTX ISA Version 2.b32. ctl[3] = (c >> 12) & 0xf. } tmp[07:00] = ReadByte( mode. prmt requires sm_20 or later. r2.0 Semantics tmp64 = (b<<32) | a.

2. Instruction Set 8.Chapter 8.7.f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on .

default is .f32 rsqrt. 2010 .rnd.PTX ISA Version 2. . Note that future implementations may support NaN payloads for single-precision instructions.0.0 The following table summarizes floating-point instructions in PTX.approx. .rcp.lg2. If no rounding modifier is specified.mul}.target sm_20 mad.rm . No rounding modifier.f32 . NaN payloads are supported for double-precision instructions.f32 {abs.fma}.f64 and fma.rnd.full. 82 January 24.f64 {abs.rz .f64 are the same.min.rp .target sm_1x No rounding modifier.f32 are the same.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.target sm_20 .rnd.f64 rsqrt.max}. 1. so PTX programs should not rely on the specific single-precision NaNs being generated.f32 {div. and mad support saturation of results to the range [0. Single-precision add.rn and instructions may be folded into a multiply-add.f64 {sin.rnd.sat Notes If no rounding modifier is specified.ftz .sub.rnd.neg.rnd.sqrt}.f32 {add. Table 46.max}.rn and instructions may be folded into a multiply-add.f32 {div.32 and fma. but single-precision instructions return an unspecified NaN.min.ex2}. default is . {mad.fma}.f64 div.0].rcp. Double-precision instructions support subnormal inputs and results. mul.approx.sqrt}.f32 {div.sub.f64 mad.rn .f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. The optional .sqrt}.cos. {add.approx. sub.rcp.mul}. Instruction Summary of Floating-Point Instructions . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.approx.neg. with NaNs being flushed to positive zero.f32 {mad.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

notanumber. . f0.0. and return the result as d.infinite testp.finite. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. testp.normal testp.infinite. .type = { . y. X.Chapter 8. testp.infinite. January 24.type d. .notanumber.op. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.pred = { . a. Instruction Set Table 47.f32 testp. z.type = { . testp. b. not infinity).number.0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . B. . copysign.f32 copysign. . . Introduced in PTX ISA version 2. not infinity) As a special case. p.notanumber testp.number testp. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. copysign requires sm_20 or later.subnormal }. C.f64 }. . true if the input is a subnormal number (not NaN.f64 }. 2010 83 .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.finite testp. // result is . positive and negative zero are considered normal numbers.op p.f64 isnan. testp Syntax Floating-Point Instructions: testp Test floating-point property. Table 48. .f32.f64 x. testp requires sm_20 or later.type .f32. copysign.normal. a. A.

rn mantissa LSB rounds to nearest even . add. add.rz available for all targets . add.ftz.f32 f1. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rp }. add.rm. .rn): .rnd}. add Syntax Floating-Point Instructions: add Add two values. b.ftz.rnd}{.f32 add{.rm. subnormal numbers are supported.f32 clamps the result to [0.f32.f3. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. add. b.sat. NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 49.rz mantissa LSB rounds towards zero . requires sm_20 Examples @p add. .sat}.rnd = { .rm mantissa LSB rounds towards negative infinity .f32 flushes subnormal inputs and results to sign-preserving zero.0f.rz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. d. Rounding modifiers (default is . . 84 January 24. .f64 supports subnormal numbers.rz.f64 d.f2.ftz}{. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. . . 1. add{.f64 requires sm_13 or later. Rounding modifiers have the following target requirements: .0. Description Semantics Notes Performs addition and writes the resulting value into a destination register. a.PTX ISA Version 2. Saturation modifier: . sm_1x: add.rn.0.rp for add. d = a + b. In particular.0].f32 supported on all target architectures. a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 2010 .rn.f64. requires sm_13 for add.

sm_1x: sub.f2.f64 d.f64 requires sm_13 or later.0.f32 clamps the result to [0.rp }.f32 flushes subnormal inputs and results to sign-preserving zero. b. sub.rm.rnd = { . a. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rz. subnormal numbers are supported.sat}. sub Syntax Floating-Point Instructions: sub Subtract one value from another. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 flushes subnormal inputs and results to sign-preserving zero. sub. 2010 85 . 1. .rn): . d.ftz}{.rnd}.f32. sub.0].0. In particular.rm. requires sm_20 Examples sub. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 sub{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.b. sub.f64. NaN results are flushed to +0.rn. Instruction Set Table 50.a. d = a .rn. requires sm_13 for sub.sat.rm mantissa LSB rounds towards negative infinity .ftz.rp for sub. .rz available for all targets .Chapter 8.f32 f1.f32 supported on all target architectures.rn. a. b. .ftz.b.f3.f64 supports subnormal numbers.rn mantissa LSB rounds to nearest even .rnd}{. Saturation modifier: sub. January 24. Rounding modifiers have the following target requirements: . Rounding modifiers (default is . sub{.0f. sub.f32 c.rz mantissa LSB rounds towards zero . .

NaN results are flushed to +0.pi // a single-precision multiply 86 January 24.0.rn mantissa LSB rounds to nearest even .f64 supports subnormal numbers.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.0. . Saturation modifier: mul.f32 circumf.rz mantissa LSB rounds towards zero . subnormal numbers are supported. mul. a. . Rounding modifiers (default is . For floating-point multiplication. 1.f32.0].ftz. Rounding modifiers have the following target requirements: . mul. b.rm. b.rn. requires sm_20 Examples mul.rz available for all targets .f32 flushes subnormal inputs and results to sign-preserving zero.rn. d.0f.rp }. Description Semantics Notes Compute the product of two values. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 mul{.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later. mul{. In particular.rm.rnd}. mul Syntax Floating-Point Instructions: mul Multiply two values. a.rp for mul.f64 d.rnd = { . A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz}{. d = a * b.f64.0 Table 51. mul.f32 clamps the result to [0. . .sat. 2010 .rnd}{.rn): . mul.rz.PTX ISA Version 2.radius. . sm_1x: mul. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.sat}. requires sm_13 for mul.f32 supported on all target architectures. .ftz. all operands must be the same size.

sat. c.Chapter 8.rm mantissa LSB rounds towards negative infinity .f32 clamps the result to [0. The resulting value is then rounded to single precision using the rounding mode specified by . b. fma. 1. The resulting value is then rounded to double precision using the rounding mode specified by .ftz}{. .0].f32 is unimplemented in sm_1x. Rounding modifiers (no default): .rnd = { . fma. a.f64 computes the product of a and b to infinite precision and then adds c to this product.rnd.f64 requires sm_13 or later.rn. Instruction Set Table 52.f32 computes the product of a and b to infinite precision and then adds c to this product. 2010 87 .0f. Saturation: fma. b. .f64 is the same as mad. fma.rz.f32 introduced in PTX ISA version 2. @p fma.x.rn mantissa LSB rounds to nearest even . PTX ISA Notes Target ISA Notes Examples January 24. fma. again in infinite precision. sm_1x: fma.f64 supports subnormal numbers. c. again in infinite precision. a.rnd. fma.rz mantissa LSB rounds towards zero . fma. subnormal numbers are supported. fma. d = a*b + c.4.f32 fma.rnd{.rnd.f32 fma.rp }.rm. .rn.f64 w. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f64. fma.y.z.c. NaN results are flushed to +0.rn.f32 requires sm_20 or later. .0. fma.f32 flushes subnormal inputs and results to sign-preserving zero.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.b. fma. d. d.f64 introduced in PTX ISA version 1.sat}.a.ftz.0.f64 d.ftz. fma Syntax Floating-Point Instructions: fma Fused multiply-add.

and then writes the resulting value into a destination register. 1.0].f64 computes the product of a and b to infinite precision and then adds c to this product.f64. mad.f32 is identical to the result computed using separate mul and add instructions. 88 January 24.rz. . Unlike mad.f32 is when c = +/-0.target sm_20: mad. mad. Description Semantics Notes Multiplies two values and adds a third. a.sat}. .target sm_13 and later . When JIT-compiled for SM 2.{f32. mad. d = a*b + c.f64 computes the product of a and b to infinite precision and then adds c to this product. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. 2010 .target sm_20 d. In this case.rnd. subnormal numbers are supported.rnd. mad.rnd.rz mantissa LSB rounds towards zero .f32 is implemented as a fused multiply-add (i.sat}. again in infinite precision.0 devices. For .ftz.rn.{f32. mad.0f. // . a.f32 mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. where the mantissa can be rounded and the exponent will be clamped.f32 flushes subnormal inputs and results to sign-preserving zero. For . b. c. The resulting value is then rounded to single precision using the rounding mode specified by .PTX ISA Version 2.rn mantissa LSB rounds to nearest even .f32 clamps the result to [0. again in infinite precision. // .f32 flushes subnormal inputs and results to sign-preserving zero.e.f64 is the same as fma.rn.f32 computes the product of a and b to infinite precision and then adds c to this product.rm mantissa LSB rounds towards negative infinity . NaN results are flushed to +0.rnd{. The resulting value is then rounded to double precision using the rounding mode specified by . The resulting value is then rounded to double precision using the rounding mode specified by .sat.0 Table 53. a.f32 mad. again in infinite precision.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0. Rounding modifiers (no default): .rnd. Saturation modifier: mad. sm_1x: mad. mad..f64}.f32 computes the product of a and b at double precision. fma.rnd = { .ftz.rp }. b.0. // .f64} is the same as fma.f32. mad.rm. mad{.ftz}{. the treatment of subnormal inputs and output follows IEEE 754 standard. but the exponent is preserved. and then the mantissa is truncated to 23 bits.target sm_1x d.f32).ftz}{. mad. .f64 d. c.target sm_1x: mad. b. mad. Note that this is different from computing the product with mul. The exception for mad. c.f64 supports subnormal numbers.

rm..c.rn. In PTX ISA versions 1..rm.rn.f32 d.rn. Target ISA Notes mad... In PTX ISA versions 2. 2010 89 . requires sm_20 Examples @p mad.f64 requires sm_13 or later.f64. requires sm_13 . mad.0.a. Legacy mad..f64.f32. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.b.0 and later. a rounding modifier is required for mad.f32 supported on all target architectures.f64 instructions having no rounding modifier will map to mad. a rounding modifier is required for mad.rz.f32 for sm_20 targets..rz. January 24.Chapter 8. Rounding modifiers have the following target requirements: .4 and later.rp for mad.rp for mad.f64.

f32 flushes subnormal inputs and results to sign-preserving zero.rp }.full. div.full.ftz.rp}.f32 and div.full. Fast. and div. PTX ISA Notes div.rnd is required. .rn. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . one of . a.4 and later. div. computed as d = a * (1/b).rn.ftz}. div Syntax Floating-Point Instructions: div Divide one value by another. a. yd.f64. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . Examples 90 January 24.f64 d.rnd.3.ftz}. the maximum ulp error is 2.ftz. d.approx.f32 supported on all target architectures. div. y.f64 diam.f64 introduced in PTX ISA version 1. .approx{.rm mantissa LSB rounds towards negative infinity . d.ftz}.f32 defaults to div.rn. subnormal numbers are supported. .ftz.approx. b.f32 and div.rm.f64 supports subnormal numbers. b.rz.full{.0 through 1. // // // // fast.3. div.0. div.circum.rm.PTX ISA Version 2.14159. The maximum ulp error is 2 across the full range of inputs.rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.f64 requires sm_13 or later.ftz. div.0 Table 54. zd. x. approximate division by zero creates a value of infinity (with same sign as a). sm_1x: div.f32 div. 2010 . .full.rnd = { . full-range approximation that scales operands to achieve better accuracy. div.rn mantissa LSB rounds to nearest even .ftz.full.f32 div. b.rnd. div.f64 defaults to div.f32 div. div.f32 implements a relatively fast. a. d. or . d = a / b. Fast.4. and rounding introduced in PTX ISA version 1.approx.f32 requires sm_20 or later. . b.approx.f32.approx.f32 div.f32 div. 2126].rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. For b in [2-126.rnd{. . z. Description Semantics Notes Divides a by b. a. Explicit modifiers .f32 implements a fast approximation to divide. For PTX ISA versions 1. Target ISA Notes div.rn. approximate single-precision divides: div.approx. xd. stores result in d. but is not fully IEEE 754 compliant and does not support rounding modifiers.f64 requires sm_20 or later. Subnormal inputs and results are flushed to sign-preserving zero.{rz.

NaN inputs yield an unspecified NaN. 2010 91 .f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. Take the absolute value of a and store the result in d.f32 neg.Chapter 8. subnormal numbers are supported. Instruction Set Table 55. neg.ftz.ftz}. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Negate the sign of a and store the result in d.f32 supported on all target architectures.f64 requires sm_13 or later.0. a. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. abs. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. d = -a.f64 supports subnormal numbers.ftz.f0.0.f32 x. d = |a|. Table 56.f0. Subnormal numbers: sm_20: By default. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d. a.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later.f64 supports subnormal numbers.ftz.f64 d.ftz. neg. sm_1x: abs. neg. neg. NaN inputs yield an unspecified NaN. abs{. a. abs.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: neg. abs. abs.f32 flushes subnormal inputs and results to sign-preserving zero. neg{.ftz}.f32 supported on all target architectures. Subnormal numbers: sm_20: By default.f32 x. neg. January 24. d.

f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. Store the minimum of a and b in d.ftz}. max.ftz.f64 f0.f64 d. a. a.0. (a < b) ? a : b.f1. max. min. b.c. min.f64 z. Table 58. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. max. 2010 .z. Store the maximum of a and b in d. b. a.f64 supports subnormal numbers. min.f32 max. sm_1x: max.f2. d d d d = = = = NaN. a.0.f32 supported on all target architectures. a. min.f64 requires sm_13 or later.ftz. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 min.x. subnormal numbers are supported. d.f32 max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.b. d d d d = = = = NaN. a. max{.b. b.ftz}.f64 d. (a > b) ? a : b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.PTX ISA Version 2. 92 January 24.c. min{. sm_1x: min. b.f32 min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.ftz. a. @p min. b. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.0 Table 57. d. max. b.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. max. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f64 supports subnormal numbers.ftz.

For PTX ISA versions 1. rcp. xi.f64 introduced in PTX ISA version 1. d. sm_1x: rcp. .0 through 1. // fast.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . a.approx{.ftz.f32 requires sm_20 or later.f32.f32 supported on all target architectures.0 +subnormal +Inf NaN Result -0.ftz.rn mantissa LSB rounds to nearest even .f64 ri. store result in d.rm. 2010 93 .ftz. rcp.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.0 over the range 1. rcp. . xi.rnd.4.f32 and rcp. The maximum absolute error is 2-23.f32 rcp. a.f64 and explicit modifiers . rcp.ftz}. PTX ISA Notes rcp.{rz. d = 1 / a.rn. rcp.x. d.0-2. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f64.0.f64 requires sm_13 or later.rnd.rnd = { . Description Semantics Notes Compute 1/a. .rm mantissa LSB rounds towards negative infinity .approx.3. rcp.f32 rcp. rcp.rn.rp}.approx and .rz.rnd is required.approx.approx or .rnd{.f64 d. General rounding modifiers were added in PTX ISA version 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.x. For PTX ISA version 1.f64 requires sm_20 or later.f32 rcp. Target ISA Notes rcp.rn.rm.ftz were introduced in PTX ISA version 1. and rcp.rp }.rn.0 +0.f32 defaults to rcp. rcp. rcp. Input -Inf -subnormal -0. a. Instruction Set Table 59. Examples January 24.rz mantissa LSB rounds towards zero .approx.rn.rn. rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .0.f64 supports subnormal numbers.0.ftz.4 and later.approx. one of .f32 rcp.f64 defaults to rcp.f32 implements a fast approximation to reciprocal.0 -Inf -Inf +Inf +Inf +0.r.

f32 implements a fast approximation to square root.approx.f32 flushes subnormal inputs and results to sign-preserving zero.approx. The maximum absolute error for sqrt.f32 sqrt.0 +0.rz mantissa LSB rounds towards zero . approximate square root d.4 and later.f64 requires sm_20 or later.x.rp}. store in d.ftz. a.0 -0. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. one of . sqrt. // IEEE 754 compliant rounding . . sqrt. sqrt.rn.0. PTX ISA Notes sqrt.f64 and explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero.f32 and sqrt.rp }.0. Description Semantics Notes Compute sqrt(a). a. subnormal numbers are supported.rnd is required. Examples 94 January 24.f64. r. // fast.ftz}. General rounding modifiers were added in PTX ISA version 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 defaults to sqrt.f32 requires sm_20 or later. r. sqrt.0 +0.x.approx. sqrt.ftz.f64 introduced in PTX ISA version 1. a.f64 supports subnormal numbers. . 2010 .PTX ISA Version 2.approx.rz.f32 sqrt.rnd = { .{rz.f32 defaults to sqrt.ftz}. sm_1x: sqrt. For PTX ISA version 1.rn. d = sqrt(a).rn.f32 supported on all target architectures.f64 r.approx or .0 through 1.f32 sqrt.approx{.rn.0 +0. sqrt.0 Table 60. // IEEE 754 compliant rounding d.3.rn.approx and .ftz.approx.rn mantissa LSB rounds to nearest even . sqrt.rm.rn.f32 is TBD.f64 requires sm_13 or later.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .4. .rnd.rnd.ftz were introduced in PTX ISA version 1.f64 d.rm mantissa LSB rounds towards negative infinity .rm. sqrt.x. and sqrt.rnd{. sqrt.0 +subnormal +Inf NaN Result NaN NaN -0.f32 sqrt. sqrt. Target ISA Notes sqrt. For PTX ISA versions 1.f32. Input -Inf -normal -subnormal -0.ftz.

Target ISA Notes Examples rsqrt. store the result in d.f32.f64 defaults to rsqrt. Subnormal numbers: sm_20: By default. Input -Inf -normal -subnormal -0.f64 requires sm_13 or later.0 through 1.f32 is 2-22. rsqrt.approx.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.4 and later.ftz. Explicit modifiers .4. and rsqrt. X.f64 isr.approx{. x. Instruction Set Table 61. d = 1/sqrt(a). 2010 95 .f64 is emulated in software and are relatively slow.f32 flushes subnormal inputs and results to sign-preserving zero. a. Note that rsqrt. For PTX ISA version 1.ftz}.0.f64 were introduced in PTX ISA version 1.f32 rsqrt. sm_1x: rsqrt.4 over the range 1. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes rsqrt.ftz.approx.approx.0 NaN The maximum absolute error for rsqrt.3. For PTX ISA versions 1.approx implements an approximation to the reciprocal square root.f32 defaults to rsqrt.f64 d. d.f64 supports subnormal numbers. The maximum absolute error for rsqrt.ftz were introduced in PTX ISA version 1. a.f32 and rsqrt. rsqrt. ISR.f64.ftz.0 +0.f32 rsqrt.f64 is TBD. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f32 supported on all target architectures.0. Compute 1/sqrt(a). rsqrt.Chapter 8.approx. rsqrt. rsqrt. January 24.approx modifier is required. the .approx.approx and . rsqrt.0-4.approx. subnormal numbers are supported.

sin.f32 introduced in PTX ISA version 1.0 +0. Find the sine of the angle a (in radians).ftz.f32 flushes subnormal inputs and results to sign-preserving zero. d = sin(a).0 +0.0.ftz introduced in PTX ISA version 1.f32 sa. 96 January 24.0 Table 62. PTX ISA Notes sin.ftz. Subnormal numbers: sm_20: By default. For PTX ISA versions 1.3.0 -0.0 through 1.approx. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx. Explicit modifiers .f32 d.9 in quadrant 00. sin. sin. subnormal numbers are supported.f32 defaults to sin.f32. sin.approx modifier is required.PTX ISA Version 2.approx.approx{. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to sine. a. sin.approx and . Input -Inf -subnormal -0. Target ISA Notes Examples Supported on all target architectures.0 +subnormal +Inf NaN Result NaN -0.ftz. For PTX ISA version 1. 2010 . the .ftz}.4 and later.0 +0.4. a.0 NaN NaN The maximum absolute error is 2-20.

0 +subnormal +Inf NaN Result NaN +1. subnormal numbers are supported. a. cos.9 in quadrant 00.ftz introduced in PTX ISA version 1. For PTX ISA version 1.ftz. For PTX ISA versions 1. d = cos(a).approx. Instruction Set Table 63.f32 flushes subnormal inputs and results to sign-preserving zero.0 +1.f32 defaults to cos.ftz. Subnormal numbers: sm_20: By default. 2010 97 .0 through 1.0 +1.4 and later. cos.Chapter 8.ftz.4.f32 implements a fast approximation to cosine. PTX ISA Notes cos. the . sm_1x: Subnormal inputs and results to sign-preserving zero.0 NaN NaN The maximum absolute error is 2-20.f32 ca.ftz}.0 +0.approx. Find the cosine of the angle a (in radians). Explicit modifiers .0 +1. cos. January 24.f32 introduced in PTX ISA version 1. cos. cos.f32.approx modifier is required.f32 d.approx{.3.approx.0. Target ISA Notes Examples Supported on all target architectures.approx and . a. Input -Inf -subnormal -0. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.

approx and .0 +0.ftz. 98 January 24. Target ISA Notes Examples Supported on all target architectures.4. lg2.f32 la.f32 implements a fast approximation to log2(a).approx.0 Table 64.ftz}. lg2.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.PTX ISA Version 2.ftz.f32 introduced in PTX ISA version 1.6 for mantissa. a.f32 defaults to lg2. PTX ISA Notes lg2.ftz introduced in PTX ISA version 1. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. For PTX ISA versions 1. a.approx.f32 flushes subnormal inputs and results to sign-preserving zero.approx{.0 through 1. For PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero. d = log(a) / log(2).approx modifier is required.0. Subnormal numbers: sm_20: By default. lg2.4 and later. the .ftz. subnormal numbers are supported.approx.3.f32 Determine the log2 of a. Explicit modifiers .f32. lg2. The maximum absolute error is 2-22. 2010 . lg2. Input -Inf -subnormal -0.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

. or. Semantics t = (a CmpOp b) ? 1 : 0.b32. . the result is false. @q setp. Subnormal numbers: sm_20: By default.0 Table 67. .u64. ls. ge.u32 p|q.a. lt. ge. and higher-or-same may be used instead of lt. gt. hi. xor. num.dtype.dtype.b64. respectively. q = BoolOp(!t.eq. Applies to all numeric types.n. If either operand is NaN. ge. geu.CmpOp{.s16.f32.s64.f64 source type requires sm_13 or later. . ne. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. . subnormal numbers are supported. setp with . ltu. ne. then these comparisons have the same result as their ordered counterparts.type setp.PTX ISA Version 2. ne.f32 flushes subnormal inputs to sign-preserving zero. gtu. a.B) is one of: and.0.pred variables. ge. If both operands are numeric values (not NaN). This result is written to the first destination operand. The destinations p and q must be . lt. 2010 . hs equ.ftz. loweror-same.b. gtu. The comparison operator is a suffix on the instruction. The untyped. le. neu. unordered versions are included: equ. c). Modifier . Integer Notes Floating Point Notes The ordered comparisons are eq.f64 }. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.b16. gt. then the result of these comparisons is true. p[|q]. hi. le. setp. p[|q].i. and hs for lower.f32 flushes subnormal inputs to sign-preserving zero.ftz}.r. lt.u32. setp. bit-size comparisons are eq and ne. b. gt. . le. and can be one of: eq. ls.s32. ltu. b. The signed and unsigned comparison operators are eq. If either operand is NaN. gt. . the comparison operators lo. a. sm_1x: setp.f64 supports subnormal numbers. and nan returns true if either operand is NaN. nan The Boolean operator BoolOp(A.f32 comparisons. num returns true if both operands are numeric values (not NaN). 102 January 24.u16. For unsigned values. c). geu.type = { .CmpOp. setp. {!}c. lo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. A related value computed using the complement of the compare result is written to the second destination operand. leu. neu.dtype.s32 setp. To aid comparison operations in the presence of NaN values. . le. p = BoolOp(t. and (optionally) combine this result with a predicate value by applying a Boolean operator. p.BoolOp{.and.ftz applies only to .type . . . higher. leu.ftz}.lt.

.u32. . sm_1x: slct.f64 }.s16. . . Operands d. operand c must match the second instruction type.u16. y.b32. selp Syntax Comparison and Selection Instructions: selp Select between source operands. selp. Subnormal numbers: sm_20: By default.f32 comparisons. If operand c is NaN. and operand a is selected.type d.u32. slct. c. b. a. .dtype = { .f64 requires sm_13 or later. slct. Operands d. based on the sign of the third operand.u64. .dtype. f0. d = (c == 1) ? a : b. If c is True. and b are treated as a bitsize type of the same width as the first instruction type.g. a is stored in d. @q selp. .s32. subnormal numbers are supported. based on the value of the predicate source operand. fval.b32. c. c. . The selected input is copied to the output without modification. .f32 A.f32 comparisons.x.0. . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.f64 }. slct.s32 x. Instruction Set Table 68. slct.dtype.f32 flushes subnormal values of operand c to sign-preserving zero. Introduced in PTX ISA version 1. and operand a is selected. val.s64. Semantics Floating Point Notes January 24. a.f64 requires sm_13 or later.u16. slct Syntax Comparison and Selection Instructions: slct Select one source operand. a.dtype.f32.r. otherwise b is stored in d.u64.f32. For . and b must be of the same type.u32. d.ftz}. .u64.f32 r0. a. 2010 103 . slct. a. selp. C.b16.dtype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b64. . d = (c >= 0) ? a : b.b64.p.s32. .xp.s16.Chapter 8. b otherwise. the comparison is unordered and operand b is selected. . .ftz applies only to .ftz. If c ≥ 0. b. z. Operand c is a predicate.b16. B. .s32 slct{. . . a is stored in d.0.f32 flushes subnormal values of operand c to sign-preserving zero. . . b.f32 d. Description Conditional selection.s32 selp.s64. .ftz. .type = { .t. Table 69. Modifier . negative zero equals zero.

provided the operands are of the same size.0 8. or.7. xor. and not also operate on predicates.4. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. Instructions and. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. This permits bit-wise operations on floating point values without having to define a union to access the bits.PTX ISA Version 2. performing bit-wise operations on operands of any type.

Chapter 8. sign.pred.0x00010001 or. Introduced in PTX ISA version 1. . . Allowed types include predicate registers.fpvalue. or. The size of the operands must match. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type = { . and Syntax Logic and Shift Instructions: and Bitwise AND.b32. The size of the operands must match. Table 71. b.b32 mask mask. Instruction Set Table 70.b32 and.q. or.type d. .b32 x. but not necessarily the type. a.type = { . d = a | b.q. 2010 105 .r. d = a & b. .pred. Supported on all target architectures. b. or Syntax Logic and Shift Instructions: or Bitwise OR. Allowed types include predicate registers.pred p. and. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.0. and. .0x80000000. Supported on all target architectures. a.b32.0. January 24.type d. .r.b64 }. but not necessarily the type.b64 }. . .b16.b16.

but not necessarily the type. The size of the operands must match.b64 }. Introduced in PTX ISA version 1.pred p.q. not.0. Table 73. xor. .type d. but not necessarily the type.b16.type = { .0.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.q. d.b32 mask. one’s complement.type = { . . b. . a.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. . Table 74. Introduced in PTX ISA version 1.type d. Supported on all target architectures. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b32 xor.type = { .mask. cnot. Supported on all target architectures. a. .0 Table 72.PTX ISA Version 2. not Syntax Logic and Shift Instructions: not Bitwise negation. cnot.b32.type d.pred.a. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b16.r. d = a ^ b. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. .b16 d. but not necessarily the type.pred. not. The size of the operands must match.b32 d. .b32. not. xor. .0. The size of the operands must match. Supported on all target architectures. Allowed types include predicates.x.b16. . . d = ~a.b64 }. Introduced in PTX ISA version 1. d = (a==0) ? 1 : 0.0x0001. a. Allowed types include predicate registers. 2010 . 106 January 24.

.u16 shr.a.2. Introduced in PTX ISA version 1.2. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples Table 76. The sizes of the destination and first source operand must match. shr. shr.0. shl.1. .u64.a.b64 }. unsigned and untyped shifts fill with 0.b16 c. . Shift amounts greater than the register width N are clamped to N. PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1.i. shl.u32.type d.0. a. zero-fill on right.s64 }. Signed shifts fill with the sign bit. 2010 107 .s16. The sizes of the destination and first source operand must match.b32. Instruction Set Table 75. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.s32.s32 shr. regardless of the instruction type. . but not necessarily the type. shl Syntax Logic and Shift Instructions: shl Shift bits left. but not necessarily the type. Supported on all target architectures.b32. b. d = a >> b. sign or zero fill on left. The b operand must be a 32-bit value. i. b.Chapter 8. .b16. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.u16. . regardless of the instruction type. a. . k.type = { .type d. . Bit-size types are included for symmetry with SHL. . .i. . Shift amounts greater than the register width N are clamped to N. shr Syntax Logic and Shift Instructions: shr Shift bits right. . The b operand must be a 32-bit value.b16.b32 q.type = { . d = a << b.b64.j.

7. 2010 . ld. Data Movement and Conversion Instructions These instructions copy data from place to place.0 8. suld.PTX ISA Version 2. local. The cvta instruction converts addresses between generic and global. mov. and sust support optional cache operations. prefetchu isspacep cvta cvt 108 January 24. and from state space to state space. or shared state spaces. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. possibly converting it from one format to another. and st operate on both scalar and vector types. ldu. Instructions ld.5. st.

cs.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.7.cg Cache at global level (cache in L2 and below. The default load instruction cache operation is ld. The ld. The compiler / programmer may use ld.lu load last use operation. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cs is applied to a Local window address. bypassing the L1 cache.lu Last use. . when applied to a local address.ca. but multiple L1 caches are not coherent for global data. rather than the data stored by the first thread. . if the line is fully covered. the second thread may get stale L1 cache data. and a second thread loads that address via a second L1 cache with ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cs) on global addresses. the cache operators have the following definitions and behavior. and cache only in the L2 cache. invalidates (discards) the local L1 line following the load. For sm_20 and later. Operator . The ld.lu operation. Global data is coherent at the L2 level.0 introduces optional cache operators on load and store instructions. .cg to cache loads only globally.cv Cache as volatile (consider cached system memory lines stale. fetch again).lu instruction performs a load cached streaming operation (ld. Use ld. any existing cache lines that match the requested address in L1 will be evicted. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. The ld. Cache Operators PTX 2. As a result of this request.cs Cache streaming. evict-first. January 24. it performs the ld. A ld.cv to a frame buffer DRAM address is the same as ld. likely to be accessed once.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The cache operators require a target architecture of sm_20 or later.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.5.Chapter 8. If one thread stores to global memory via one L1 cache. The ld.ca. likely to be accessed again.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. to allow the thread program to poll a SysMem location written by the CPU. Table 77.1. When ld. 2010 109 . not L1). Instruction Set 8. .ca loads cached in L1.

the second thread may get a hit on stale L1 cache data. which writes back cache lines of coherent cache levels with normal eviction policy. to allow a CPU program to poll a SysMem location written by the GPU with st. not L1).wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. The default store instruction cache operation is st. 110 January 24. Addresses not in System Memory use normal write-back.0 Table 78. 2010 . and cache only in the L2 cache.wb could write-back global store data from L1.cg to local memory uses the L1 cache. regardless of the cache operation. The st. . The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wb.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. .ca loads. and marks local L1 lines evict-first. The st. in which case st. rather than get the data from L2 or memory stored by the first thread. . and a second thread in a different SM later loads from that address via a different L1 cache with ld. bypassing the L1 cache.PTX ISA Version 2.wb for global data. Use st.cs Cache streaming. likely to be accessed once. st. but st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wt Cache write-through (to system memory). However.cg to cache global store data only globally. and discard any L1 lines that match. bypassing its L1 cache. Global stores bypass L1. Future GPUs may have globally-coherent L1 caches.cg Cache at global level (cache in L2 and below.ca.cg is the same as st.wt. In sm_20.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Operator . If one thread stores to global memory. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.

a. . the parameter will be copied onto the stack and the address will be in the local state space. 2010 111 . the address of the variable in its state space) into the destination register. . Introduced in PTX ISA version 1. Description . immediate.b32. . . mov. k. d = sreg. . ..type = { . local.e. Operand a may be a register.u16. mov places the non-generic address of the variable (i. local. d. d. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. . the generic address of a variable declared in global. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.const. d = &avar.f64 }.v.b64.u16 mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.e. A.s32. mov. d = &label. ptr. and . Instruction Set Table 79.u64.type mov. Note that if the address of a device function parameter is moved to a register.0. mov. . sreg.u32 mov. A[5]. local. or shared state space.u32 d.f64 requires sm_13 or later.a. Semantics d = a. Take the non-generic address of a variable in global. addr. within the variable’s declared state space Notes Although only predicate and bit-size types are required. alternately. The generic address of a variable in global. special register.f32 mov. or function name.local.f32 mov. For variables declared in .f32. .0. or shared state space may be taken directly using the cvta instruction. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. .type mov.s16. label. u..1.s64. variable in an addressable memory space.Chapter 8. label. // get address of variable // get address of label or function . .type d. ptr.global.pred.b16.shared state spaces. // address is non-generic. avar. Write register d with the value of a.type mov. i. myFunc. d.u32 mov. .u32.

For bit-size types.x.a have type . {r.x.b64 { d.63] } // unpack 16-bit elements from . 2010 .x.x | (a. lo.y.b32 // pack four 16-bit elements into .x.y..b have type .x | (a. or write vector register d with the unpacked values from scalar register a.w } = { a[0.y << 8) d = a. a[16.. a[16.0 Table 80.31].z. Semantics d = a.a}. // // // // a. %r1.y.z. d.b32 { d.15].type = { .x | (a.{a.u8 // unpack 32-bit elements from .w << 48) d = a..type d.15].PTX ISA Version 2..b64 { d.hi}. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.y. {lo.47]. a.b16.u32 x.7].y << 32) // pack two 8-bit elements into .b8 r. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). ..b32 { d.b32.w << 24) d = a..{x.15].u16 %x is a double. d. a[8.z.z << 16) | (a.y } = { a[0.b64 // pack two 32-bit elements into . %x.b. a[32.b32 mov.z << 32) | (a.w}.w have type ..%r1. .z....g.7]. Supported on all target architectures. d. a[32.b16 // pack four 8-bit elements into . Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b. d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 %r1. a[8.y } = { a[0... a[16. a[48.31] } // unpack 8-bit elements from ..b}. mov.g.x | (a.w } = { a[0.y << 16) d = a.y << 8) | (a. . a[24.b64 mov. d. mov. d.hi are . d.y << 16) | (a.b64 }..b32 // pack two 16-bit elements into . Description Write scalar register d with the packed value of vector register a.b64 112 January 24.b16 { d.31] } // unpack 16-bit elements from .15] } // unpack 8-bit elements from .y } = { a[0.b32 mov.0. d.x.31]. d.23].x | (a.

. and then converted to . In generic addressing. .ss = { .const.local. . .volatile may be used with . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. .lu. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. the access may proceed by silently masking off low-order address bits to achieve proper rounding.v4 }. 32-bit). Instruction Set Table 81.vec.ss}.v2. The address size may be either 32-bit or 64-bit. The address must be naturally aligned to a multiple of the access size.f32. The . the resulting behavior is undefined. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. Addresses are zero-extended to the specified width as needed.ss}{.volatile.cs. ld.volatile{.type ld{. ld.vec = { . . . If an address is not properly aligned. [a]. ld{. . Within these windows.cv }. an integer or bit-size type register reg containing a byte address. d.f64 }. .cop}.const space suffix may have an optional bank number to indicate constant banks other than bank zero. The value loaded is sign-extended to the destination register width for signed integers.type = { . PTX ISA Notes January 24. .ca.type d. . .b8. . d. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.shared }. or [immAddr] an immediate absolute byte address (unsigned.param.e.ss}{.type ld.b32.u64. Generic addressing and cache operations introduced in PTX ISA 2.u32.volatile introduced in PTX ISA version 1. and is zeroextended to the destination register width for unsigned and bit-size types. or the instruction may fault. i. Semantics d d d d = = = = a. . Cache operations are not permitted with ld.cop}.u8. . A destination register wider than the specified type may be used.cg..volatile{.global.global and .b16. .vec. . . .shared spaces to inhibit optimization of references to volatile memory.ss}.0.s8. an address maps to global memory unless it falls within the local memory window or the shared memory window. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . .type .0. 2010 113 . *a. to enforce sequential consistency between threads accessing shared memory. ld introduced in PTX ISA version 1. *(a+immOff). for example.reg state space. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.e.s16.f64 using cvt.f16 data may be loaded using ld.u16. [a]. [a]. This may be used.1. . *(immAddr).s32. Generic addressing may be used with ld.f32 or .b16. . .cop = { . an address maps to the corresponding location in local or shared memory.s64. Description Load register variable d from the location specified by the source address operand a in specified state space. 32-bit). d. [a].volatile. i. If no state space is given. and truncated if the register width exceeds the state space address width for the target architecture. .Chapter 8.b64. perform the load using generic addressing.

b64 ld.[fs].[a].f32 ld. // load . Generic addressing requires sm_20 or later.0 Target ISA Notes ld. 2010 .s32 ld.shared.[240].[p+-8]. x. Q.v4. ld.b32 ld.local. // access incomplete array x.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.b32 ld. Cache operations require sm_20 or later. %r.f32. // immediate address %r.%r.[p+4].f64 requires sm_13 or later.f16 d. // negative offset %r.b32 ld.global. d.global.const[4].const.local.b16 cvt.[buffer+64].[p].PTX ISA Version 2.

b32. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. Semantics d d d d = = = = a. The data at the specified address must be read-only.f64 using cvt. *(immAddr). i.f32. . . The address must be naturally aligned to a multiple of the access size.b64. .type d.s16.s64. . Instruction Set Table 82. . ldu. ldu. . 32-bit). d. The addressable operand a is one of: [avar] the name of an addressable variable var. .s8.u64. .Chapter 8. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. ldu. ldu{. . Introduced in PTX ISA version 2. [a].vec = { .s32. // state space . and is zeroextended to the destination register width for unsigned and bit-size types. If no state space is given. 2010 115 . [a].ss = { . In generic addressing. The value loaded is sign-extended to the destination register width for signed integers.f16 data may be loaded using ldu. . . only generic addresses that map to global memory are legal. . *(a+immOff).v4.f64 }.ss}.global.f64 requires sm_13 or later.e.u32.v2. A register containing an address may be declared as a bit-size type or integer type. ldu.. and then converted to . and truncated if the register width exceeds the state space address width for the target architecture.[p]. *a.global }.b8. .[p+4]. i. perform the load using generic addressing.type = { .e.u8.b32 d. where the address is guaranteed to be the same across all threads in the warp.type ldu{.b16.u16. [areg] a register reg containing a byte address.reg state space. // load from address // vec load from address . For ldu. Addresses are zero-extended to the specified width as needed.[a]. The address size may be either 32-bit or 64-bit.f32 d. an address maps to the corresponding location in local or shared memory. Within these windows. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.global.f32 or . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. the resulting behavior is undefined. 32-bit). A destination register wider than the specified type may be used.ss}.v4 }.b16. or [immAddr] an immediate absolute byte address (unsigned. an address maps to global memory unless it falls within the local memory window or the shared memory window. If an address is not properly aligned. or the instruction may fault.f32 Q.vec.0. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . PTX ISA Notes Target ISA Notes Examples January 24.global.

Generic addressing requires sm_20 or later. an integer or bit-size type register reg containing a byte address. The address size may be either 32-bit or 64-bit.type st. the access may proceed by silently masking off low-order address bits to achieve proper rounding. { . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.cs. .global.vec. st. { .u32. an address maps to the corresponding location in local or shared memory.shared spaces to inhibit optimization of references to volatile memory. [a]. .volatile. Generic addressing may be used with st. or [immAddr] an immediate absolute byte address (unsigned. an address maps to global memory unless it falls within the local memory window or the shared memory window.b16.b16.cg.f64 requires sm_13 or later. *(d+immOffset) = a. 2010 .type st{.e.reg state space. { . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. [a].type = = = = {. . b. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.s8. the resulting behavior is undefined.ss}.v4 }. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .volatile introduced in PTX ISA version 1. Cache operations require sm_20 or later.type [a].. .e.cop}. to enforce sequential consistency between threads accessing shared memory.ss}{. If an address is not properly aligned. st introduced in PTX ISA version 1. The lower n bits corresponding to the instruction-type width are stored to memory.volatile{.f64 }. . Addresses are zero-extended to the specified width as needed. Semantics d = a.s64. The address must be naturally aligned to a multiple of the access size.volatile. .local. .ss}.wb. . . In generic addressing.vec .PTX ISA Version 2. .0.cop .ss . . Cache operations are not permitted with st.0 Table 83.cop}. 32-bit). .shared }. *d = a. st. b. . perform the store using generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. PTX ISA Notes Target ISA Notes 116 January 24. b. . .f16 data resulting from a cvt instruction may be stored using st.volatile may be used with . If no state space is given.0. *(immAddr) = a. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. .global and .vec.b8.wt }. st.s32. [a]. i. or the instruction may fault.v2.b64. This may be used.f32. 32-bit). A source register wider than the specified type may be used. i. st{.u64.u16.u8. and truncated if the register width exceeds the state space address width for the target architecture. . Within these windows.volatile{.ss}{. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. b.b32. for example. . Generic addressing and cache operations introduced in PTX ISA 2.1.s16. .type . .

global. 2010 117 .%r. [q+4].r7.b16 [a].v4.s32 st.local.local. [q+-8].global. // immediate address %r.f32 st.f16.%r.s32 cvt.a. [p].b.a. [fs].b32 st.Q. // negative offset [100].f32 st.b32 st.local.Chapter 8. // %r is 32-bit register // store lower 16 bits January 24. Instruction Set Examples st.

level prefetchu.L1 [a]. in specified state space. prefetch. prefetch and prefetchu require sm_20 or later. an address maps to global memory unless it falls within the local memory window or the shared memory window. .L1.PTX ISA Version 2. A prefetch to a shared memory location performs no operation.space = { . Addresses are zero-extended to the specified width as needed.level = { . The address size may be either 32-bit or 64-bit. // prefetch to data cache // prefetch to uniform cache .global. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. 32-bit). If no state space is given.space}. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.local }. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. 2010 . and no operation occurs if the address maps to a local or shared memory location. the prefetch uses generic addressing. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.L2 }.0 Table 84. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 32-bit). an address maps to the corresponding location in local or shared memory.0. prefetchu. In generic addressing. or [immAddr] an immediate absolute byte address (unsigned. i. a register reg containing a byte address. [a]. 118 January 24. A prefetch into the uniform cache requires a generic address. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.e. Within these windows. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. .L1 [addr]. prefetch{. . and truncated if the register width exceeds the state space address width for the target architecture.L1 [ptr].

lptr. local. cvta. svar. // result is . . .space.0.local. January 24.size = { . p. a. Instruction Set Table 85.shared }.size .u64. var. Introduced in PTX ISA version 2. cvta. sptr. isspacep. islcl. 2010 119 . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. or shared state space.pred.0.u64.shared. isspacep requires sm_20 or later. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32. Take the generic address of a variable declared in global. // get generic address of svar cvta. A program may use isspacep to guard against such incorrect behavior.to. The source address operand must be a register of type . a.u32 or .lptr. . p. isspacep. local. When converting a generic address into a global.global. For variables declared in global.space = { . Use cvt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.global isspacep. or shared state space. or shared address to a generic address. // convert to generic address // get generic address of var // convert generic address to global. or vice-versa. the generic address of the variable may be taken using cvta.genptr. Description Convert a global.global.local. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.space = { . . .u32. isshrd. local.shared }.u32 p. local.local isspacep.global.to.size p.pred . a. or shared state space to generic. or shared address.space p.space. . or shared address cvta.u64 or cvt.u32 to truncate or zero-extend addresses. gptr.size cvta.space.shared isglbl.u32 p. PTX ISA Notes Target ISA Notes Examples Table 86. The source and destination addresses must be the same size.u64 }. // local. The destination register must be of type . cvta.u32 gptr. or vice-versa. cvta requires sm_20 or later. local.local.Chapter 8.

s8.e. a. .irnd = { .ftz modifier may be specified in these cases for clarity.dtype. For float-to-integer conversions.f32 float-tofloat conversions with integer rounding.f32.dtype.atype d. d = convert(a).s32. . . subnormal inputs are flushed to signpreserving zero. .f32. cvt{.frnd = { .ftz.0 Table 87. . the . sm_1x: For cvt.f32 float-to-integer conversions and cvt.u8. For cvt.rni round to nearest integer.rni. // integer rounding // fp rounding .sat}. . 120 January 24. Note that saturation applies to both signed and unsigned integer types.s64. . the result is clamped to the destination range by default.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.f16. Integer rounding is required for float-to-integer conversions. .u32.rm.ftz}{.sat For integer destination types. .rn. .rmi. i. Saturation modifier: . subnormal inputs are flushed to signpreserving zero. .rzi.ftz.MAXINT for the size of the operation. .dtype = .e.s16.atype cvt{.sat limits the result to MININT.ftz. Note: In PTX ISA versions 1.PTX ISA Version 2.sat is redundant. Description Semantics Integer Notes Convert between different types and sizes.rzi round to nearest integer in the direction of zero . .dtype.dtype. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. .rmi round to nearest integer in direction of negative infinity ..ftz.irnd}{.f64 }.rz. .rp }.ftz}{.f32 float-to-integer conversions and cvt. 2010 .. . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. and for same-size float-tofloat conversions where the value is rounded to an integer. . Integer rounding modifiers: . i. . a.u64.4 and earlier.rpi }.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. subnormal numbers are supported. Integer rounding is illegal in all other instances. The compiler will preserve this behavior for legacy PTX code.u16.f32. .atype = { .frnd}{. . choosing even integer if source is equidistant between two integers.f32 float-tofloat conversions with integer rounding.sat}. d. . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. The optional .

f16. Floating-point rounding is illegal in all other instances. cvt to or from .0]. if the PTX . // note . cvt.f64 types. The optional . The operands must be of the same size. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.rni.rz mantissa LSB rounds towards zero .f32 x.0. cvt.rn mantissa LSB rounds to nearest even . Saturation modifier: . .f16. . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. Introduced in PTX ISA version 1.f64.f32 x. NaN results are flushed to positive zero. cvt.f32. // float-to-int saturates by default cvt. Subnormal numbers: sm_20: By default. subnormal numbers are supported. The result is an integral value.Chapter 8.ftz modifier may be specified in these cases for clarity.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.y.f64 requires sm_13 or later.y.f32. and for integer-to-float conversions.r.sat limits the result to the range [0.rm mantissa LSB rounds towards negative infinity .f32.version is 1.f32.4 and earlier. Applies to . Modifier . stored in floating-point format. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. and . Specifically. Floating-point rounding modifiers: . result is fp cvt. Note: In PTX ISA versions 1.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). // round to nearest int.f64 j.f32. The compiler will preserve this behavior for legacy PTX code. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .s32. 2010 121 .4 or earlier.i.sat For floating-point destination types.ftz behavior for sm_1x targets January 24.f32. and cvt.0.f32. 1.f32 instructions.f16.s32 f.

sampler.samplerref tsamp1 = { addr_mode_0 filter_mode }. texture and sampler information each have their own handle.6.u32 r5.f32 r3. add.entry compute_power ( . but the number of samplers is greatly restricted to 16. and surfaces.r2.f32 r1. // get tex1’s tex.u32 r5. add. [tex1].f2}].global . The texturing mode is selected using .f32.param . .texref handle.b32 r6. 2010 .target options ‘texmode_unified’ and ‘texmode_independent’. mul. and surface descriptors. texture and sampler information is accessed through a single . r1.. . = nearest width height tsamp1.PTX ISA Version 2.r3. In the independent mode.f32 r1. The advantage of independent mode is that textures and samplers can be mixed and matched.r4}. Ability to query fields within texture. [tex1]. the file is assumed to use unified mode. r3. sampler. In the unified mode. r1. r2.0 8. PTX supports the following operations on texture.v4. // get tex1’s txq. allowing them to be defined separately and combined at the site of usage in the program. cvt. r5.f32. {f1. add. If no texturing mode is declared. Texture and Surface Instructions This section describes PTX instructions for accessing textures.height. Module-scope and per-entry scope definitions of texture.texref tex1 ) { txq. with the restriction that they correspond 1-to-1 with the 128 possible textures. 122 January 24.b32 r5.f32 {r1. samplers.2d. The advantage of unified mode is that it allows 128 samplers. sampler. r6. r5. sampler. A PTX module may declare only one texturing mode. } = clamp_to_border. and surface descriptors: • • • Static initialization of texture. and surface descriptors..7.width. r3. and surface descriptors. div. [tex1. Texturing modes For working with textures and samplers. r4. .f32 r1. r5.target texmode_independent . r1. PTX has two modes of operation. Example: calculate an element’s power contribution as element’s power/total number of elements.

Supported on all target architectures. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.f2. where the fourth element is ignored. sampler_x. Instruction Set These instructions provide access to texture and surface memory.1d. Unified mode texturing introduced in PTX ISA version 1.f32 }. If no sampler is specified.r2. or the instruction may fault. {f1. is a two-element vector for 2d textures.v4 coordinate vectors are allowed for any geometry. Operand c is a scalar or singleton tuple for 1d textures. //Example of unified mode texturing tex.dtype.s32. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.0.v4.dtype.geom. Notes For compatibility with prior versions of PTX.3d. [tex_a. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. .btype d. {f1}]. If an address is not properly aligned.r3. tex txq suld sust sured suq Table 88. // Example of independent mode texturing tex. .s32. i. tex.f32 {r1. b.r4}.f32 }. [a. the square brackets are not required and .btype tex.2d. c]. the sampler behavior is a property of the named texture.r2. with the extra elements being ignored.s32.f3.Chapter 8.geom = { .. 2010 123 . . // explicit sampler . . Description Texture lookup using a texture coordinate vector.geom. PTX ISA Notes Target ISA Notes Examples January 24. c].v4.e.5. .s32.3d }. d.r3.s32 {r1. and is a four-element vector for 3d textures.btype = { . The instruction always returns a four-element vector of 32-bit values. the resulting behavior is undefined.f4}].1d. [a. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. An optional texture sampler b may be specified.dtype = { . [tex_a.r4}.u32. . A texture base address is assumed to be aligned to a 16-byte address.v4.v4. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.

mirror. .addr_mode_0. Integer from enum { nearest. txq.PTX ISA Version 2.squery. txq.height .normalized_coords }. [a].5.filter_mode. clamp_ogl.depth .b32 %r1. .filter_mode .b32 txq. addr_mode_2 }. Supported on all target architectures. . [tex_A].0 Table 89. clamp_to_edge.width. sampler attributes are also accessed via a texref argument. // texture attributes // sampler attributes . Query: . d. .tquery = { . 2010 .filter_mode.width.addr_mode_1 . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. linear } Integer from enum { wrap. and in independent mode sampler attributes are accessed via a separate samplerref argument. Operand a is a . [a].b32 %r1.tquery. txq.width .addr_mode_0 . // unified mode // independent mode 124 January 24. [smpl_B]. .b32 d.squery = { .normalized_coords . addr_mode_1. [tex_A].samplerref variable. txq.texref or . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.height.b32 %r1.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). Description Query an attribute of a texture or sampler.depth. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.addr_mode_0. In unified mode.

suld.cop}.b. . and the size of the data transfer matches the size of destination operand d. Destination vector elements corresponding to components that do not appear in the surface format are not written. additional clamp modifiers. {x}].vec. suld. if the surface format contains UINT data. . Operand b is a scalar or singleton tuple for 1d surfaces. B.y. suld.u32.e. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b32.p. or the instruction may fault. Operand a is a .cop .trap . . .3d requires sm_20 or later. then . A surface base address is assumed to be aligned to a 16-byte address. // formatted .cop}. i. or . Cache operations require sm_20 or later.trap clamping modifier.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. [a. The . If an address is not properly aligned. and is a four-element vector for 3d surfaces. . and cache operations introduced in PTX ISA version 2.p is currently unimplemented.cs.f32 is returned.f32. [surf_A. .f32.p.2d. .v4.Chapter 8.v2.r2}. .b . b]. .trap. . .b.b8 . sm_1x targets support only the . Target ISA Notes Examples January 24. the resulting behavior is undefined.clamp . [a. if the surface format contains SINT data.3d.f2.clamp = = = = = = { { { { { { d.b64.cg. is a two-element vector for 2d surfaces. // unformatted d. size and type conversion is performed as needed to convert from the surface sample format to the destination type. .s32.s32. // for suld.3d }.dtype. . .u32. 2010 125 .1d.vec .. // for suld.f3.b64 }.s32. suld. suld.p.1d.geom{. and A components of the surface format. or . .5.b performs an unformatted load of binary data. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. . suld. then . [surf_B. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.zero }.v4. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp suld. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. b]. SNORM. or FLOAT data.f32 based on the surface format as follows: If the surface format contains UNORM.surfref variable. Instruction Set Table 90. G.dtype.geom . where the fourth element is ignored.clamp field specifies how to handle out-of-bounds addresses: .0.p .cv }.clamp .u32 is returned. then .f4}.trap suld. . Coordinate elements are of type . {f1. suld.f32 }.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. The lowest dimension coordinate represents a sample offset rather than a byte offset.b32. suld. // cache operation none.trap introduced in PTX ISA version 1.b32.z.v2. .v4 }.b supported on all target architectures. the surface sample elements are converted to . suld.geom{.u32. . Description Load from surface memory using a surface coordinate vector.dtype .ca.s32.trap {r1.dtype .p requires sm_20 or later.b16.w}]. If the destination base type is . If the destination type is .b.clamp. {x.s32 is returned.

clamp.b. Operand b is a scalar or singleton tuple for 1d surfaces.trap introduced in PTX ISA version 1.wt }.b. sust. is a two-element vector for 2d surfaces. size and type conversions are performed as needed between the surface sample format and the destination type. sust. sust.v4. sust.u32.5. .0.v4 }.trap.v2.clamp . .clamp sust.p. .geom{.vec. and cache operations introduced in PTX ISA version 2.trap sust. i.3d.b performs an unformatted store of binary data. .f3. The source vector elements are interpreted left-to-right as R.cs.s32.b16.ctype.cop}.cop}. . sust. If an address is not properly aligned. where the fourth element is ignored. [surf_B. b]. if the surface format contains SINT data. . then .f2.f32} are currently unimplemented.b32. // unformatted // formatted .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. . . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. .s32 is assumed.z. {f1.b. Source elements that do not occur in the surface sample are ignored.u32 is assumed.b8 . G. if the surface format contains UINT data. If the source base type is . the resulting behavior is undefined. .s32. The size of the data transfer matches the size of source operand c.surfref variable.y. . then . B..3d requires sm_20 or later. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.p.cop .geom{.1d. c.f32 is assumed.u32.w}].s32.2d. sm_1x targets support only the .clamp = = = = = = { { { { { { [a.trap clamping modifier. Operand a is a . or FLOAT data.wb. .clamp field specifies how to handle out-of-bounds addresses: .b64 }. {r1.vec.r2}. [a.f4}. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.v2. and A surface components. A surface base address is assumed to be aligned to a 16-byte address.p requires sm_20 or later. . sust.b64.e.p. Surface sample components that do not occur in the source vector will be written with an unpredictable value. 2010 .ctype .p Description Store to surface memory using a surface coordinate vector.cg. and is a four-element vector for 3d surfaces.b supported on all target architectures. // for sust.zero }. If the source type is . .b32. Coordinate elements are of type . .trap [surf_A. {x}]. .geom . The lowest dimension coordinate represents a sample offset rather than a byte offset. sust.b32. {x. Cache operations require sm_20 or later. Target ISA Notes Examples 126 January 24. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.ctype. sust.b // for sust. SNORM.3d }.s32. sust Syntax Texture and Surface Instructions: sust Store to surface memory. . or .{u32.p.PTX ISA Version 2. or the instruction may fault. . The .clamp .1d.ctype .f32. additional clamp modifiers. These elements are written to the corresponding surface sample components. . c. none.vec . b].f32 }.0 Table 91. sust. The source data is then converted from this type to the surface sample format.trap . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32.p performs a formatted store of a vector of 32-bit data values to a surface sample. then .

y}]. where the fourth element is ignored.0. If an address is not properly aligned. .and. The lowest dimension coordinate represents a sample offset rather than a byte offset. The .op.trap [surf_A. is a two-element vector for 2d surfaces.ctype = { .clamp [a.b.1d. // byte addressing sured.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Reduction to surface memory using a surface coordinate vector. // for sured.u32 is assumed.s32 types.s32.u64.Chapter 8.p .b32. Operand a is a . .u32. . {x}]..zero }.op = { .b32 }. if the surface format contains SINT data.trap .b .1d. Instruction Set Table 92.ctype.p performs a reduction on sample-addressed 32-bit data. // for sured. .op.p.s32 is assumed.min.u64 data. . sured. . January 24. The instruction type is restricted to . and the data is interpreted as . . r1. i.max. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b32 }.s32 or .u32 based on the surface sample format as follows: if the surface format contains UINT data. operations and and or apply to . or .s32 types. . min and max apply to .b32. .u64. . {x.s32.b]. Coordinate elements are of type .surfref variable.trap sured.geom. then . .ctype = { .u32. Operations add applies to .c.2d.b].2d.s32.c. and is a four-element vector for 3d surfaces.clamp. Operand b is a scalar or singleton tuple for 1d surfaces.add.b32 type.geom. or the instruction may fault. sured.geom = { . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.b.ctype.u32 and .clamp . .p. . A surface base address is assumed to be aligned to a 16-byte address. sured requires sm_20 or later.min.or }.add.u32. the resulting behavior is undefined. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. sured. [surf_B.b32. // sample addressing . 2010 127 .b performs an unformatted reduction on . .trap.clamp [a.clamp = { .e. r1. sured.3d }.u32. and . . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.clamp field specifies how to handle out-of-bounds addresses: . then .

[a].0 Table 93. Supported on all target architectures. 2010 .width. Operand a is a . .query.b32 %r1.surfref variable. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.width.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.query = { .height.width . Description Query an attribute of a surface.b32 d.PTX ISA Version 2.depth }. 128 January 24. .5. suq. [surf_A]. suq. . Query: .height .

eq. mov. } PTX ISA Notes Target ISA Notes Examples Table 95. Instruction Set 8.0. {} Syntax Description Control Flow Instructions: { } Instruction grouping. { add.7. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. If {!}p then instruction Introduced in PTX ISA version 1. 2010 129 .y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.a.y. p. Introduced in PTX ISA version 1. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.c.7.b.f32 @q bra L23.x. Supported on all target architectures.f32 @!p div.0. ratio. @{!}p instruction.s32 d. Supported on all target architectures.Chapter 8.0. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. { instructionList } The curly braces create a group of instructions. Execute an instruction or instruction block for threads that have the guard predicate true. used primarily for defining a function body.s32 a. setp. Threads with a false guard predicate do nothing.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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arrive a{. bar. If no thread count is specified.pred . Register operands. a{.red performs a predicate reduction across the threads participating in the barrier. In conditionally executed code.sync and bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. threads within a CTA that wish to communicate via memory can store to memory. b}. {!}c.0. Operands a. a. Register operands. if any thread in a warp executes a bar instruction. 2010 133 .red delays the executing threads (similar to bar. bar. Thus.. the final value is written to the destination register in all threads waiting at the barrier. b. Description Performs barrier synchronization and communication within a CTA. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. bar.red performs a reduction operation across threads. b}.red. the optional thread count must be a multiple of the warp size.arrive using the same active barrier. all-threads-true (. Note that a non-zero thread count is required for bar. b. bar. Execution in this case is unpredictable.{arrive. The barrier instructions signal the arrival of the executing threads at the named barrier. Only bar. bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. The reduction operations for bar.15. the waiting threads are restarted without delay.{arrive. PTX ISA Notes Target ISA Notes Examples bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. and bar.red are population-count (. while . it is as if all the threads in the warp have executed the bar instruction. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). operands p and c are predicates.red instruction. and the barrier is reinitialized so that it can be immediately reused. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).and). The result of .popc is the number of threads with a true predicate. it simply marks a thread's arrival at the barrier. and then safely read values stored by other threads prior to the barrier.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.0. When a barrier completes. bar.or).or }. . Thus.red} introduced in PTX .sync or bar.Chapter 8.sync bar.op = { .sync) until the barrier count is met. thread count. all threads in the CTA participate in the barrier.red should not be intermixed with bar.cta.red} require sm_20 or later.and and . p. bar. {!}c.sync and bar. execute a bar.sync with an immediate barrier number is supported for sm_1x targets.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.sync without a thread count introduced in PTX ISA 1.arrive does not cause any waiting by the executing threads. and d have type . bar. b}. thread count.sync or bar.popc). bar. and bar. a{.op.and.red also guarantee memory ordering among threads identical to membar. January 24. Instruction Set Table 100.sync 0. Once the barrier count is reached.version 2.popc. and any-thread-true (. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. In addition to signaling its arrival at the barrier.u32. Each CTA instance has sixteen barriers numbered 0. Operand b specifies the number of threads participating in the barrier.u32 bar. Since barriers are executed on a per-warp basis. d. All threads in the warp are stalled until the barrier completes.arrive. the bar.red.

gl} introduced in PTX .version 2. level describes the scope of other clients for which membar is an ordering event. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. For communication between threads in different CTAs or even different SMs.level. membar. A memory read (e. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar.PTX ISA Version 2.g. . this is the appropriate level of membar.sys Waits until all prior memory requests have been performed with respect to all clients.0. membar.version 1. .sys will typically have much longer latency than membar.0 Table 101. PTX ISA Notes Target ISA Notes Examples membar.sys. or system memory level. that is. by st.gl. A memory write (e.sys introduced in PTX . membar. membar. 134 January 24. global. membar.gl.sys requires sm_20 or later. membar.g. membar. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. red or atom) has been performed when the value written has become visible to other clients at the specified level.level = { .{cta.cta. membar. .sys }.{cta. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. and memory reads by this thread can no longer be affected by other thread writes.gl. including thoses communicating via PCI-E such as system and peer-to-peer memory.gl will typically have a longer latency than membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. 2010 .cta. when the previous value can no longer be read.gl} supported on all target architectures. membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.4.cta Waits until all prior memory writes are visible to other threads in the same CTA.cta. membar.

max }.f32 }.inc. In generic addressing. 2010 135 .s32. . . d.b64.and. min. or the instruction may fault.space}.type = { . The inc and dec operations return a result in the range [0. The floating-point operations are add. an address maps to global memory unless it falls within the local memory window or the shared memory window. overwriting the original value. .b32. .add. . [a]. .op.b]. performs a reduction operation with operand b and the value in location a.cas.u64. max. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. . and exch (exchange). .type atom{. Within these windows. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. or [immAddr] an immediate absolute byte address. Description // // // // // . . The address size may be either 32-bit or 64-bit. and stores the result of the specified operation at location a. and max operations are single-precision. inc. .b64 .g.e.f32. . and truncated if the register width exceeds the state space address width for the target architecture. The floating-point add. the resulting behavior is undefined.f32 Atomically loads the original value at location a into destination register d. . .global.dec. atom.type d. The bit-size operations are and.exch to store to locations accessed by other atomic operations.. . b. For atom. Operand a specifies a location in the specified state space. b.. an address maps to the corresponding location in local or shared memory. [a].u32 only . atom{.b32.s32. cas (compare-and-swap). .b32 only .op = { .space}. perform the memory accesses using generic addressing.s32. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.add. e. . 32-bit operations. A register containing an address may be declared as a bit-size type or integer type. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . .min. min. . If an address is not properly aligned.op. dec. . . or.space = { . and max. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Instruction Set Table 102. c.e. or by using atom.exch.u32.xor. If no state space is given.shared }.or. accesses to local memory are illegal. . i. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The integer operations are add. January 24. min. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .u32. Addresses are zero-extended to the specified width as needed. a de-referenced register areg containing a byte address. . xor.Chapter 8. The address must be naturally aligned to a multiple of the access size. i.u64 . by inserting barriers between normal stores and atomic operations to a common address.u32.

add. atom.0 Semantics atomic { d = *a.{min.max} are unimplemented.cas. b.add. 64-bit atom. atom. d.b32 d. s) = (r >= s) ? 0 dec(r.shared requires sm_12 or later. Release Notes Examples @p 136 January 24.global requires sm_11 or later. *a = (operation == cas) ? : } where inc(r.[a].0. d. atom.cas. s) = (r > s) ? s exch(r.s32 atom. : r+1. cas(r. Use of generic addressing requires sm_20 or later.my_val.s.exch} requires sm_12 or later.global. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. c) operation(*a.global.f32 atom.f32 requires sm_20 or later.max.[p]. s) = s.t) = (r == s) ? t operation(*a.my_new_val.shared.f32.{add. atom.[x+4]. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. : r.shared operations require sm_20 or later. 2010 . : r-1.0. b).PTX ISA Version 2. 64-bit atom. atom.1.

u64.. . a de-referenced register areg containing a byte address.. and truncated if the register width exceeds the state space address width for the target architecture. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. and max.b64. .dec.f32 Performs a reduction operation with operand b and the value in location a. Addresses are zero-extended to the specified width as needed. an address maps to the corresponding location in local or shared memory. min. The bit-size operations are and.inc.shared }.s32.type [a].e. and stores the result of the specified operation at location a.add. .u32. e. In generic addressing. perform the memory accesses using generic addressing.type = { . . 2010 137 .e.space = { . Semantics *a = operation(*a. If no state space is given.max }. January 24. Within these windows. . Operand a specifies a location in the specified state space. . . inc. an address maps to global memory unless it falls within the local memory window or the shared memory window.and. A register containing an address may be declared as a bit-size type or integer type.xor. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. red.g. s) = (r > s) ? s : r-1. The address size may be either 32-bit or 64-bit. where inc(r. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. dec(r. . .min. . or the instruction may fault. i. overwriting the original value.u32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. s) = (r >= s) ? 0 : r+1.u32 only . . If an address is not properly aligned. .f32. The floating-point operations are add. and xor. and max operations are single-precision.Chapter 8. max. .exch to store to locations accessed by other reduction operations.op.add. For red. Instruction Set Table 103. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. red{.b32 only .u64 .u32. .global. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .op = { .f32 }.b32. The floating-point add. Description // // // // . b. accesses to local memory are illegal. or. dec. The inc and dec operations return a result in the range [0. b). min. or by using atom.b]. . . Notes Operand a must reside in either the global or shared state space. i.or. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. . the resulting behavior is undefined. . or [immAddr] an immediate absolute byte address. The integer operations are add.space}.s32. . The address must be naturally aligned to a multiple of the access size. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. . 32-bit operations.s32. by inserting barriers between normal stores and reduction operations to a common address. min.

red. [x+4].max.0.add.f32 requires sm_20 or later.f32.f32 red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 64-bit red.2.and. red. red.shared requires sm_12 or later.max} are unimplemented.s32 red.add.{min.global. Use of generic addressing requires sm_20 or later.PTX ISA Version 2. red. [p].shared. 64-bit red.global requires sm_11 or later red.global.add requires sm_12 or later.my_val. 2010 .shared operations require sm_20 or later. Release Notes Examples @p 138 January 24.b32 [a].1.

uni }. r1. In the ‘ballot’ form. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.mode = { .mode.uni.all. . Negating the source predicate also computes . not across an entire CTA. vote. // get ‘ballot’ across warp January 24.pred vote.ballot. Note that vote applies to threads in a single warp.q. 2010 139 . vote. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.any.uni.ballot.ballot. The reduction modes are: . returns bitmask . vote requires sm_12 or later. Description Performs a reduction of the source predicate across threads in a warp.any True if source predicate is True for some active thread in warp.pred vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. . vote.none.2. {!}a.ballot. p. vote.pred d. .uni True if source predicate has the same value in all active threads in warp.b32 p. Negate the source predicate to compute . Negate the source predicate to compute . where the bit position corresponds to the thread’s lane id.Chapter 8.b32 d.b32 requires sm_20 or later.q.all. The destination predicate value is the same across all threads in the warp. Instruction Set Table 104. vote. . {!}a.all True if source predicate is True for all active threads in warp.not_all.p. // ‘ballot’ form.

sat} d. optionally clamp the result to the range of the destination type.9.dtype.dsel. c. perform a scalar arithmetic operation to produce a signed 34-bit result.max }.dsel = .atype. to produce signed 33-bit input values. The source and destination operands are all 32-bit registers. The primary operation is then performed to produce an .asel}.0 8. . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. vop. .b0.s33 values. . b{.asel}. Using the atype/btype and asel/bsel specifiers.atype. atype.btype{. a{. .h0. the input values are extracted and signor zero. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). . . a{.secop = { .s34 intermediate result. 140 January 24. with optional data merge vop.dtype = . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.dtype. taking into account the subword destination size in the case of optional data merging.asel}.secop d.bsel}. The sign of the intermediate result depends on dtype. The general format of video instructions is as follows: // 32-bit scalar operation. . 3.b2.atype. b{.bsel}. 4. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. half-word.h1 }.asel = .u32 or . extract and sign.sat}.atype = .add. 2010 . a{.s32) is specified in the instruction type.dtype.u32. Video Instructions All video instructions operate on 32-bit register operands.bsel = { . // 32-bit scalar operation.or zero-extend byte. b{.btype{.PTX ISA Version 2. and btype are valid.extended internally to . .bsel}.s32 }. The type of each operand (. . c.btype{.b1. .b3.7.min. or word values from its source operands. all combinations of dtype. with optional secondary operation vop. .sat} d. 2.btype = { .

The sign of the c operand is based on dtype. tmp. The lower 32-bits are then written to the destination operand.b2: return ((tmp & 0xff) << 16) case .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.s33 c ) switch ( dsel ) { case .s33 optSecOp(Modifier secop. c). S16_MAX. U8_MAX. default: return tmp.s33 optSaturate( .h1: return ((tmp & 0xffff) << 16) case . Instruction Set . 2010 141 . c). . S32_MAX. switch ( dsel ) { case . January 24.b0: return ((tmp & 0xff) case .s33 tmp.add: return tmp + c. .s33 tmp. c). . U8_MIN ). c).s33 optMerge( Modifier dsel.h0. c). .h0: return ((tmp & 0xffff) case . tmp.min: return MIN(tmp. c).s33 c) { switch ( secop ) { . tmp. S16_MIN ).b1. tmp.b2. . . U32_MIN ). S8_MAX. U16_MIN ). c).Chapter 8. U16_MAX. as shown in the following pseudocode. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).max return MAX(tmp. . . S8_MIN ). } } . Bool sat. S32_MIN ). Modifier dsel ) { if ( !sat ) return tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case .b3: return ((tmp & 0xff) << 24) default: return tmp. tmp. Bool sign. .b0. U32_MAX.b1: return ((tmp & 0xff) << 8) case . . .s34 tmp.

atype.b1. asel ).sat vabsdiff. vop.h0. r2.sat vsub. r2. isSigned(dtype). c.b0. a{. tmp = MIN( ta.h1. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.atype. r2. vabsdiff.s32. Video Instructions: vadd. . tb ). vmax require sm_20 or later.btype = { . vmax vadd.bsel}.sat vmin.b3. with optional data merge vop.dtype.s32. vsub.h0.0.0 Table 105. // optional merge with c operand 142 January 24. with optional secondary operation vop. tmp. vmin. bsel ). Perform scalar arithmetic operation with optional saturate. r3.btype{. Integer byte/half-word/word minimum / maximum.btype{. . . taking into account destination type and merge operations tmp = optSaturate( tmp. d = optSecondaryOp( op2.sat} d. . .op2 d. c. c ).s32. b{. r3.vop .add. r3.s32. vmax Syntax Integer byte/half-word/word addition / subtraction.s32.dtype .or zero-extend based on source operand type ta = partSelectSignExtend( a. .atype. vabsdiff.b2.h1 }. c. dsel ).dtype. b{. .min.atype = . r1. // 32-bit scalar operation. tmp = MAX( ta. vsub.s32. .b2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.add r1.btype{. { . tmp = | ta – tb |. vabsdiff. vadd. vsub. vsub vabsdiff vmin. tmp = ta – tb.s32.s32 }. // extract byte/half-word/word and sign. tmp.bsel}.sat.s32. c. b{. .sat}.atype. vmax }.u32.sat} d. .asel}.b0.max }. // optional secondary operation d = optMerge( dsel. tb ). 2010 . a{.u32. c ). and optional secondary arithmetic operation or subword data merge.h0. r3. sat. tb = partSelectSignExtend( b. vmin.op2 Description = = = = { vadd. vadd.bsel}. a{. Integer byte/half-word/word absolute value of difference.b0. r1.asel}.PTX ISA Version 2. btype. vmin.dtype.bsel = { .s32. .u32.s32.asel = . // 32-bit scalar operation.dsel .asel}. r2. r1.dsel.h1. Semantics // saturate.

sat}{. case vshr: tmp = ta >> tb. { . tb = partSelectSignExtend( b.asel = . Left shift fills with zero.atype = { . asel ). // 32-bit scalar operation.mode} d. b{. 2010 143 . vshl.vop . and optional secondary arithmetic operation or subword data merge. Signed shift fills with the sign bit.clamp . with optional secondary operation vop.atype.u32.sat}{. tmp. c.u32{.bsel}. vop. atype. vshr }. . { . dsel ). bsel ). a{.u32.u32. Video Instructions: vshl.bsel}.atype.dtype . isSigned(dtype). sat. . b{. . . . and optional secondary arithmetic operation or subword data merge.h0. tmp.bsel = { .atype.dsel . c ). Instruction Set Table 106.b0.add. vshr Syntax Integer byte/half-word/word left / right shift.op2 Description = = = = = { vshl.u32. // default is .max }. . switch ( vop ) { case vshl: tmp = ta << tb. . r2.dtype.mode .wrap r1. c.op2 d.asel}. c ). .u32.wrap }.dtype. with optional data merge vop.mode} d. } // saturate.u32 vshr. r1.h1. taking into account destination type and merge operations tmp = optSaturate( tmp. .s32.u32.b1. vshr require sm_20 or later. // optional secondary operation d = optMerge( dsel. vshl.asel}.asel}. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .b2. d = optSecondaryOp( op2. unsigned shift fills with zero.0.Chapter 8.u32{.h1 }.sat}{.s32 }.dsel.wrap ) tb = tb & 0x1f. r2. r3.mode}.b3. if ( mode == .u32{. vshr: Shift a right by unsigned amount in b with optional saturate.dtype. January 24. // 32-bit scalar operation. .clamp && tb > 32 ) tb = 32.min.clamp. b{. if ( mode == . a{. Semantics // extract byte/half-word/word and sign. . vshr vshl.bsel}. vshl: Shift a left by unsigned amount in b with optional saturate. a{.or zero-extend based on source operand type ta = partSelectSignExtend( a. r3.

with optional operand negates. internally this is represented as negation of the product (a*b).atype.h1 }. Source operands may not be negated in . this result is sign-extended if the final result is signed.S32 // intermediate signed.scale} d.PTX ISA Version 2.scale} d. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. which is used in computing averages. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.asel}.b3. vmad. Although PTX syntax allows separate negation of the a and b operands.dtype.btype{. (a*b) is negated if and only if exactly one of a or b is negated.sat}{.u32. “plus one” mode. .bsel}.dtype = .shr7.btype.bsel}. . Description Calculate (a*b) + c. 144 January 24. .po) computes (a*b) + c + 1.asel}. . {-}b{. final signed (S32 * U32) . 2010 .atype. {-}c..btype = { .b1. The final result is unsigned if the intermediate result is unsigned and c is not negated.h0. .shr15 }. a{. final signed -(S32 * U32) + S32 // intermediate signed.bsel = { . final signed (S32 * S32) + S32 // intermediate signed. That is.0 Table 107. final signed -(U32 * S32) + S32 // intermediate signed. . final signed (S32 * S32) . // 32-bit scalar operation vmad. b{. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. final signed The intermediate result is optionally scaled via right-shift. final signed (U32 * S32) .atype = .po mode.U32 // intermediate unsigned. final signed (U32 * U32) . . . Depending on the sign of the a and b operands. final unsigned -(U32 * U32) + S32 // intermediate signed.S32 // intermediate signed. c.po{. final signed (S32 * U32) + S32 // intermediate signed.S32 // intermediate signed. and the operand negates. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. The source operands support optional negation with some restrictions. and scaling. the intermediate result is signed.b0.b2.asel = .dtype. The “plus one” mode (. {-}a{. and zero-extended otherwise. PTX allows negation of either (a*b) or c.s32 }.sat}{. . otherwise.scale = { . final signed (U32 * S32) + S32 // intermediate signed. . Input c has the same sign as the intermediate result. final signed -(S32 * S32) + S32 // intermediate signed.

if ( .sat vmad. S32_MIN).sat ) { if (signedFinal) result = CLAMP(result. } else if ( a.negate) || c.shr7: result = (tmp >> 7) & 0xffffffffffffffff. tmp = tmp + c128 + lsb. vmad requires sm_20 or later. Instruction Set Semantics // extract byte/half-word/word and sign.0.h0. } if ( .or zero-extend based on source operand type ta = partSelectSignExtend( a.s32. bsel ).negate ) { c = ~c. case . } else if ( c.u32.negate. tmp[127:0] = ta * tb. r1.u32. r1.shr15 r0. lsb = 0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Chapter 8. r2. lsb = 1. -r3. r3.negate ^ b. U32_MAX. btype.h0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.s32. S32_MAX.po ) { lsb = 1. January 24. asel ). U32_MIN).u32. atype. vmad. else result = CLAMP(result. r2.negate ) { tmp = ~tmp. switch( scale ) { case . signedFinal = isSigned(atype) || isSigned(btype) || (a. lsb = 1.u32. 2010 145 . } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). r0.negate ^ b. tb = partSelectSignExtend( b.

u32.u32. b{. btype.bsel = { . . a{.cmp d. atype.h1.asel}.h0.eq.atype. tb.h1 }. 146 January 24.b0. r2.u32. c ). vset. The intermediate result of the comparison is always unsigned.add.s32.asel}.btype.lt. a{. tmp. tmp = compare( ta.b1.asel = .bsel}. . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. .atype . c. asel ). .asel}. b{.bsel}. . . tmp.le.op2 d. bsel ). tb = partSelectSignExtend( b. // 32-bit scalar operation.atype.bsel}. r3.ne r1. with optional secondary operation vset. Compare input values using specified comparison.or zero-extend based on source operand type ta = partSelectSignExtend( a.atype. Semantics // extract byte/half-word/word and sign. . .u32.gt.min. r3. .cmp. { .b2.cmp d. with optional secondary arithmetic operation or subword data merge. // optional secondary operation d = optMerge( dsel.ge }. c. . with optional data merge vset. . .dsel . and therefore the c operand and final result are also unsigned.0. 2010 .b3.s32 }.lt vset. .0 Table 108. a{. .PTX ISA Version 2.dsel. r2.btype. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.cmp . vset requires sm_20 or later. vset. // 32-bit scalar operation. . cmp ) ? 1 : 0.op2 Description = = = = .max }. b{. d = optSecondaryOp( op2.btype. r1.btype = { .ne. { . c ).

brkpt requires sm_11 or later. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Notes PTX ISA Notes Target ISA Notes Examples Currently. Supported on all target architectures. numbered 0 through 15. brkpt Suspends execution Introduced in PTX ISA version 1. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. @p pmevent 1. with index specified by immediate operand a. 2010 147 . January 24. brkpt. Supported on all target architectures. trap. pmevent 7. there are sixteen performance monitor events. Introduced in PTX ISA version 1.0.4. Instruction Set 8.7.10. trap.0. Table 111. Table 110. pmevent a. Introduced in PTX ISA version 1. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Triggers one of a fixed number of performance monitor events. The relationship between events and counters is programmed via API calls from the host. brkpt.Chapter 8. trap Abort execution and generate an interrupt to the host CPU.

PTX ISA Version 2. 2010 .0 148 January 24.

which are visible as special registers and accessed through mov or cvt instructions. read-only variables. %pm3 January 24. %lanemask_le. %lanemask_gt %clock.Chapter 9. %clock64 %pm0. 2010 149 . %lanemask_lt. %lanemask_ge. Special Registers PTX includes a number of predefined. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. ….

per-thread special register initialized with the thread identifier within the CTA.x * %ntid.0.u32 type in PTX 2.z to %r2 Table 113. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. // CTA shape vector // CTA dimensions A predefined.u32 %ntid.u32 %tid. read-only. // move tid. cvt. Every thread in the CTA has a unique %tid. the %tid value in unused dimensions is 0.%ntid. . %tid component values range from 0 through %ntid–1 in each CTA dimension.z).y 0 <= %tid. Redefined as .x. The total number of threads in a CTA is (%ntid.0 Table 112. It is guaranteed that: 0 <= %tid.x.v4 .%tid.u32 %r0.0. read-only special register initialized with the number of thread ids in each CTA dimension. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.x. The number of threads in each dimension are specified by the predefined special register %ntid. .z == 0 in 1D CTAs.y < %ntid.x < %ntid.u32 %ntid.sreg .v4.u32 %r1. PTX ISA Notes Introduced in PTX ISA version 1. %tid. . mov.%h2.u32 %r0.0.z == 1 in 2D CTAs.u16 %rh. %ntid.y.z. mov.%h1.z == 0 in 2D CTAs.sreg .x 0 <= %tid.z PTX ISA Notes Introduced in PTX ISA version 1. %tid.v4.x. or 3D vector to match the CTA shape.v4 .0.z < %ntid. // compute unified thread id for 2D CTA mov.u32.u32 %h2. // zero-extend tid. CTA dimensions are non-zero. %ntid.u32 %h1.%r0.y * %ntid. %ntid.%tid. Supported on all target architectures.x code accessing 16-bit component of %tid mov. The fourth element is unused and always returns zero.y == %tid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. Redefined as . mov.y == %ntid. %ntid. the fourth element is unused and always returns zero. 2010 .%tid.y.PTX ISA Version 2.y. .x code Target ISA Notes Examples 150 January 24. %tid.u32 type in PTX 2.x.x to %rh Target ISA Notes Examples // legacy PTX 1.%ntid.sreg .sreg .z. // legacy PTX 1.u32 %tid.z. mad. The %tid special register contains a 1D. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.z == 1 in 1D CTAs.x. mov. 2D. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.u16 %rh. %tid. // thread id vector // thread id components A predefined.%tid. Supported on all target architectures.%tid.x.u16 %r2.

Special Registers Table 114. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. .3.3. A predefined. The lane identifier ranges from zero to WARP_SZ-1.0. mov. Introduced in PTX ISA version 2. PTX ISA Notes Target ISA Notes Examples Table 116. read-only special register that returns the thread’s warp identifier. January 24. %laneid. %nwarpid requires sm_20 or later.u32 %nwarpid. A predefined.g. but its value may change during execution. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov. Introduced in PTX ISA version 1. Note that %warpid is volatile and returns the location of a thread at the moment when read.u32 %r.u32 %laneid. . A predefined. read-only special register that returns the thread’s lane within the warp.u32 %r.u32 %warpid. %warpid.Chapter 9. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %nwarpid. e. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. read-only special register that returns the maximum number of warp identifiers. due to rescheduling of threads following preemption. For this reason.sreg . mov.sreg . Supported on all target architectures. . Introduced in PTX ISA version 1. 2010 151 .sreg . The warp identifier will be the same for all threads within a single warp.u32 %r. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Supported on all target architectures. Table 115.

The %ctaid special register contains a 1D.u32 mov.z.u32 mov. .x.v4.x 0 <= %ctaid. depending on the shape and rank of the CTA grid.u32 type in PTX 2.u32 %nctaid.u32 %ctaid.0. Supported on all target architectures. 2010 .%nctaid.z PTX ISA Notes Introduced in PTX ISA version 1.u16 %r0.y < %nctaid.0 Table 117.%ctaid.sreg .v4 . 2D.{x.x code Target ISA Notes Examples 152 January 24.u32 %nctaid .v4 .z.%nctaid. The fourth element is unused and always returns zero.x. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u16 %r0. The %nctaid special register contains a 3D grid shape vector. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.x code Target ISA Notes Examples Table 118.v4.y. read-only special register initialized with the number of CTAs in each grid dimension.PTX ISA Version 2.u32 type in PTX 2. mov.sreg . mov. // legacy PTX 1. .0.z} < 65.0.%nctaid. // legacy PTX 1. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. %ctaid.x.0.x < %nctaid. Redefined as .%nctaid.u32 %ctaid. Each vector element value is >= 0 and < 65535.sreg .z < %nctaid.x. or 3D vector. %rh.x. // CTA id vector // CTA id components A predefined. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. // Grid shape vector // Grid dimensions A predefined. %ctaid.sreg .%ctaid. It is guaranteed that: 1 <= %nctaid. Supported on all target architectures. %rh. with each element having a value of at least 1.y 0 <= %ctaid. The fourth element is unused and always returns zero. Redefined as .y.536 PTX ISA Notes Introduced in PTX ISA version 1. It is guaranteed that: 0 <= %ctaid.y. read-only special register initialized with the CTA identifier within the CTA grid.y. .

u32 %r. mov. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.3. .Chapter 9. PTX ISA Notes Target ISA Notes Examples Table 121. %nsmid requires sm_20 or later. Supported on all target architectures. %smid.0.sreg . The SM identifier numbering is not guaranteed to be contiguous. %gridid.u32 %smid. repeated launches of programs may occur. Notes PTX ISA Notes Target ISA Notes Examples Table 120. read-only special register initialized with the per-grid temporal grid identifier. but its value may change during execution. Note that %smid is volatile and returns the location of a thread at the moment when read. due to rescheduling of threads following preemption. . The SM identifier numbering is not guaranteed to be contiguous.sreg . Introduced in PTX ISA version 1. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. A predefined.u32 %r. Supported on all target architectures.0.u32 %nsmid. read-only special register that returns the maximum number of SM identifiers. mov. Introduced in PTX ISA version 2. where each launch starts a grid-of-CTAs. so %nsmid may be larger than the physical number of SMs in the device. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. PTX ISA Notes Target ISA Notes Examples January 24. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. e. This variable provides the temporal grid launch number for this context. Introduced in PTX ISA version 1. . %nsmid. // initialized at grid launch A predefined. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Special Registers Table 119. A predefined.g. The SM identifier ranges from 0 to %nsmid-1.u32 %gridid. 2010 153 . During execution.sreg . mov.u32 %r.

mov. 154 January 24. .0.u32 %lanemask_le.PTX ISA Version 2.0 Table 122.u32 %r. %lanemask_lt. %lanemask_le requires sm_20 or later. %lanemask_eq requires sm_20 or later.sreg . Introduced in PTX ISA version 2.u32 %lanemask_lt. Table 124. 2010 . A predefined.sreg .u32 %lanemask_eq.u32 %r. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.0. mov.sreg . Table 123. %lanemask_le. A predefined. Introduced in PTX ISA version 2. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_eq. . A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.0. mov. Introduced in PTX ISA version 2. . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %r. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.

u32 %r. %lanemask_gt.sreg .u32 %lanemask_ge. Introduced in PTX ISA version 2.Chapter 9. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %lanemask_gt. .u32 %r. %lanemask_gt requires sm_20 or later.0. January 24. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. A predefined.0. mov. Introduced in PTX ISA version 2. Special Registers Table 125. %lanemask_ge requires sm_20 or later. Table 126. %lanemask_ge. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. . A predefined.sreg . mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. 2010 155 .

read-only 64-bit unsigned cycle counter. Special registers %pm0.sreg . Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. mov. Introduced in PTX ISA version 1. %pm2. Special Registers: %pm0. %pm2. Table 129.u32 r1. 2010 .0 Table 127. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Table 128.3.PTX ISA Version 2. %pm1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %clock64 requires sm_20 or later. Supported on all target architectures.u32 r1.u64 r1. . . read-only 32-bit unsigned cycle counter. Introduced in PTX ISA version 1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm2. 156 January 24.sreg .u64 %clock64. and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm1. Introduced in PTX ISA version 2.%clock64. %pm1.0. %pm3 %pm0.sreg . mov. ….u32 %pm0.%clock. %pm3. mov. Their behavior is currently undefined. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. .0.%pm0. Supported on all target architectures.u32 %clock. The lower 32-bits of %clock64 are identical to %clock.

0.0 .version . Increments to the major number indicate incompatible changes to PTX.version directives are allowed provided they match the original . Duplicate . minor are integers Specifies the PTX language version number. 2010 157 .target Table 130.1. Directives 10. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.4 January 24.version directive. . PTX File Directives: . Each ptx file must begin with a . . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.Chapter 10. .version major. Supported on all target architectures.version .version Syntax Description Semantics PTX version number.version 1.minor // major.version directive. and the target architecture for which the code was generated. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version 2.

f64 instructions used. Supported on all target architectures. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Note that . Requires map_f64_to_f32 if any . vote instructions. sm_13.global. A program with multiple . In general. The texturing mode is specified for an entire module and cannot be changed within the module. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. 64-bit {atom. Therefore. but subsequent . PTX File Directives: . including expanded rounding modifiers. The following table summarizes the features in PTX that vary according to target architecture. Adds double-precision support.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.texmode_unified .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.PTX ISA Version 2.samplerref descriptors.f64 instructions used. where each generation adds new features and retains all features of previous generations. Description Specifies the set of features in the target architecture for which the current ptx code was generated.target Syntax Architecture and Platform target. with only half being used by instructions converted from . and an error is generated if an unsupported feature is used. PTX features are checked against the specified target architecture.f32. Disallows use of map_f64_to_f32.f64 to . texmode_unified. sm_11. Texturing mode introduced in PTX ISA version 1. Target sm_20 Description Baseline feature set for sm_20 architecture.target directive specifies a single target architecture. Requires map_f64_to_f32 if any .target .target directive containing a target architecture and optional platform options. A . Adds {atom. 2010 .f64 instructions used.target directives can be used to change the set of target features allowed during parsing. 158 January 24.f64 storage remains as 64-bits.red}.version directive.0 Table 131. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.texmode_unified) .texmode_independent texture and sampler information is bound together and accessed via a single . PTX code generated for a given target can be run on later generation devices. Requires map_f64_to_f32 if any . Texturing mode: (default is .red}.shared. map_f64_to_f32 }. . Adds {atom. texmode_independent. generations of SM architectures follow an “onion layer” model.0. texture and sampler information is referenced with independent .5.texref descriptor. Introduced in PTX ISA version 1. Each PTX file must begin with a .texref and . brkpt instructions. sm_10.global.red}. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. sm_12. immediately followed by a .

target sm_20. 2010 159 .target sm_13 // supports double-precision . Directives Examples . texmode_independent January 24.target sm_10 // baseline target architecture .Chapter 10.

Parameters are passed via .0 10. parameter variables are declared in the kernel body.entry filter ( . ld.param instructions.entry kernel-name ( param-list ) kernel-body . PTX ISA Notes For PTX ISA version 1. %ntid.param.4. .samplerref. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. and . e. At kernel launch.b32 %r2. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. %nctaid. the kernel dimensions and properties are established and made available via special registers.0 through 1. . 160 January 24. For PTX ISA versions 1.param space memory and are listed within an optional parenthesized parameter list. … } .4 and later. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Semantics Specify the entry point for a kernel program.b32 %r<99>. These parameters can only be referenced by name within texture and surface load. Kernel and Function Directives: . parameter variables are declared in the kernel parameter list.g. opaque . parameters. store.param instructions.func Table 132. Parameters may be referenced by name within the kernel body and loaded into registers using ld.param.param.entry Syntax Description Kernel entry point and body.param { . .PTX ISA Version 2.param . .reg . The shape and size of the CTA executing the kernel are available in special registers.b32 %r3.param .b32 y. and query instructions and cannot be accessed via ld.5 and later. ld.b32 %r1.0 through 1. [z]. . 2010 . and body for the kernel function.surfref variables may be passed as parameters. Supported on all target architectures.texref. with optional parameters.b32 z ) Target ISA Notes Examples [x]. ld. etc. [y].entry kernel-name kernel-body Defines a kernel entry point name. .2.b32 x.entry cta_fft . In addition to normal parameters.entry .3.entry .

. Supported on all target architectures.func . ret. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. val1).param space are accessed using ld.func (ret-param) fname (param-list) function-body Defines a function.reg . 2010 161 .func Syntax Function definition.b32 N. . and recursion is illegal.Chapter 10. including input and return parameters and optional function body.param state space.0 with target sm_20 supports at most one return value. Parameters in . … Description // return value in fooval January 24. there is no stack. foo.param instructions in the body.0.param and st. implements an ABI with stack.reg . Parameters in register state space may be referenced directly within instructions in the function body. PTX 2.reg . other code. and supports recursion. … use N. parameters must be in the register state space.0 with target sm_20 allows parameters in the .x code. (val0. Variadic functions are currently unimplemented.2 for a description of variadic functions. which may use a combination of registers and stack locations to pass parameters. dbl. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.b32 rval.func fname function-body . Directives Table 133. .func (.b32 rval) foo (. Parameter passing is call-by-value. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.result.reg . The parameter lists define locally-scoped variables in the function body. PTX ISA 2. Release Notes For PTX ISA version 1. Parameters must be base types in either the register or parameter state space.func definition with no body provides a function prototype. A . Kernel and Function Directives: .f64 dbl) { . Variadic functions are represented using ellipsis following the last fixed argument. } … call (fooval). The implementation of parameter passing is left to the optimizing translator. mov.func fname (param-list) function-body . if any.b32 localVar.

g.pragma The . . and .maxntid and . the . 162 January 24.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. the . or as statements within a kernel or device function body.maxnreg . registers) to increase total thread count and provide a greater opportunity to hide memory latency. at entry-scope. The directive passes a list of strings to the backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. Note that . which pass information to the backend optimizing compiler. . and the .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.maxntid.minnctapersm . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. The .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.3.minnctapersm directives may be applied per-entry and must appear between an . A general .maxntid directive specifies the maximum number of threads in a thread block (CTA). and the strings have no semantics within the PTX virtual machine model. The interpretation of .maxnctapersm (deprecated) .PTX ISA Version 2. for example. 2010 . Currently. PTX supports the following directives. These can be used.pragma directives may appear at module (file) scope. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.entry directive and its body. The directives take precedence over any module-level constraints passed to the optimizing backend.0 10.maxntid . to throttle the resource requirements (e.maxnreg.pragma directive is supported for passing information to the PTX backend.

Directives Table 134. for example.maxnreg n Declare the maximum number of registers per thread in a CTA. The actual number of registers used may be less. ny . 2010 163 .entry bar . The maximum number of threads is the product of the maximum extent in each dimension. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid 16.16.maxntid 256 . ny.entry foo . Performance-Tuning Directives: . nz Declare the maximum number of threads in the thread block (CTA).3. The compiler guarantees that this limit will not be exceeded.maxntid nx . .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.Chapter 10. Introduced in PTX ISA version 1. .maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. . .maxntid nx.maxntid . or the maximum number of registers may be further constrained by . or 3D CTA. Supported on all target architectures.maxctapersm.maxntid nx. Introduced in PTX ISA version 1.entry foo . This maximum is specified by giving the maximum extent of each dimention of the 1D. Performance-Tuning Directives: .maxntid and . Supported on all target architectures.3. Exceeding any of these limits results in a runtime error or kernel launch failure. 2D.maxnreg . the backend may be able to compile to fewer registers.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.

entry foo .minnctapersm .0 Table 136.entry foo . . Supported on all target architectures.0. Optimizations based on . For this reason.minnctapersm 4 { … } 164 January 24.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm generally need .maxntid 256 . The optimizing backend compiler uses . Deprecated in PTX ISA version 2.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm (deprecated) . .0. However.maxntid and .maxnctapersm has been renamed to .minnctapersm in PTX ISA version 2. Introduced in PTX ISA version 2. additional CTAs may be mapped to a single multiprocessor.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).PTX ISA Version 2.maxnctapersm.maxntid to be specified as well.3. Supported on all target architectures. . Performance-Tuning Directives: . if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxnctapersm generally need . Performance-Tuning Directives: . .maxntid 256 . Introduced in PTX ISA version 1.maxntid to be specified as well. 2010 .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Optimizations based on . .0 as a replacement for .

pragma Syntax Description Pass directives to PTX backend compiler.Chapter 10.pragma directive strings is implementation-specific and has no impact on PTX semantics.0.pragma list-of-strings . .pragma directive may occur at module-scope. { … } January 24.entry foo . Pass module-scoped. Introduced in PTX ISA version 2. or statement-level directives to the PTX backend compiler. at entry-scope. or at statementlevel. The interpretation of .pragma . entry-scoped. Directives Table 138. The . Performance-Tuning Directives: . 2010 165 . Supported on all target architectures. .pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma “nounroll”.

0x02. 0x00. The @@DWARF syntax is deprecated as of PTX version 2.byte 0x00. 0x5f736f63 .byte byte-list // comma-separated hexadecimal byte values . 0x00.loc The .264-1] .section directive is new in PTX ISA verison 2.4byte 0x000006b5.0 10. 0x00 .2. 0x00.section directive.debug_info .4byte label .section . 0x736d6172 . Table 139. 2010 .4byte 0x6e69616d.4byte .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser..232-1] . @@DWARF dwarf-string dwarf-string may have one of the .4byte int32-list // comma-separated hexadecimal integers in range [0. replaced by . 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x63613031. “”.quad int64-list // comma-separated hexadecimal integers in range [0.0 and replaces the @@DWARF syntax. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .. 0x00.0. Supported on all target architectures.x code. @progbits . 0x00000364.debug_pubnames. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . Introduced in PTX ISA version 1. 0x61395a5f.0 but is supported for legacy PTX version 1. 0x00 166 January 24.4.byte 0x2b.section . 0x6150736f. Deprecated as of PTX 2.PTX ISA Version 2. 0x00.file .

0x5f736f63 0x6150736f.b32 .. } 0x02.debug_pubnames { .264-1] . 0x63613031.b8 0x00.0. .b32 0x000006b5. 0x00. Supported on all target architectures. Source file information.section .b32 label .loc . . replaces @@DWARF syntax. 0x00.232-1] .b8 0x2b.file .255] . Supported on all target architectures. . Debugging Directives: . 0x736d6172 0x00 Table 141. . 2010 167 ..b32 int32-list // comma-separated list of integers in range [0.section Syntax PTX section definition.loc line_number January 24.b8 byte-list // comma-separated list of integers in range [0. Debugging Directives: . Source file location. Debugging Directives: .debug_info .0. 0x00 0x61395a5f. 0x00.0. . 0x00.file filename Table 142.b64 int64-list // comma-separated list of integers in range [0. 0x00000364. . .Chapter 10.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.section section_name { dwarf-lines } dwarf-lines have the following formats: ..file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x00.section .b32 0x6e69616d. Directives Table 140. 0x00.

Supported on all target architectures.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern .0. Linking Directives .extern .visible .0 10. Introduced in PTX ISA version 1.6.0.extern identifier Declares identifier to be defined externally. Linking Directives: .visible Table 143.b32 foo. Introduced in PTX ISA version 1.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern . 2010 .visible .b32 foo.global .PTX ISA Version 2. // foo will be externally visible 168 January 24. Supported on all target architectures. // foo is defined in another module Table 144.visible identifier Declares identifier to be externally visible. . .global . Linking Directives: . . .

The release history is as follows.2 CUDA 2.0.3 driver r190 CUDA 3.5 PTX ISA 2.0 CUDA 2. and the remaining sections provide a record of changes in previous releases.3 PTX ISA 1.1 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.0 PTX ISA 1.4 PTX ISA 1.1 CUDA 2.Chapter 11.1 CUDA 2.0 CUDA 1. 2010 169 . CUDA Release CUDA 1.0 January 24.2 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.

x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The mad. and mul now support .f32 requires sm_20. The changes from PTX ISA 1.f32 maps to fma.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. while maximizing backward compatibility with legacy PTX 1. The . New Features 11. • • • • • 170 January 24.1. rcp.f32.ftz and .rn. The fma.x code and sm_1x targets. sub. A single-precision fused multiply-add (fma) instruction has been added. Floating-Point Extensions This section describes the floating-point changes in PTX 2. These are indicated by the use of a rounding modifier and require sm_20. Single-precision add. Instructions testp and copysign have been added.1. mad.0 11. 2010 . The mad.sat modifiers.1.PTX ISA Version 2.and double-precision div. and sqrt with IEEE 754 compliant rounding have been added.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. fma.1.rm and . Single.rp rounding modifiers for sm_20 targets.f32 require a rounding modifier for sm_20 targets.f32 and mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Both fma.1.0 for sm_20 targets.1.0 11. The goal is to achieve IEEE 754 compliance wherever possible.ftz modifier may be used to enforce backward compatibility with sm_1x.f32 instruction also supports .f32 for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices. Changes in Version 2.

has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. isspacep. st. ldu. 2010 171 . prefetch. %clock64. New special registers %nsmid. brev. Bit field extract and insert instructions. suld. local. have been added. bfind. vote. and shared addresses to generic address and vice-versa has been added. A “population count” instruction. A “find leading non-sign bit” instruction. Surface instructions support additional .ge. membar. and sust. Instruction cvta for converting global. .gt} have been added.1.sys. The bar instruction has been extended as follows: • • • A bar. st. New instructions A “load uniform” instruction. A “count leading zeros” instruction.b32.zero. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. The . prefetchu. Release Notes 11. ldu. A “bit reversal” instruction.section. Cache operations have been added to instructions ld.clamp modifiers. atom. Instructions bar.1. .1. and red now support generic addressing. for prefetching to specified level of memory hierarchy. Video instructions (includes prmt) have been added.or}. Other new features Instructions ld. Instructions {atom. 11. %lanemask_{eq.u32 and bar. Instruction sust now supports formatted surface stores. January 24.clamp and . Instructions {atom.3.red}.g. clz. has been added.{and. A new directive. popc.arrive instruction has been added.Chapter 11.red. A system-level membar instruction.red}. A “vote ballot” instruction.2.red.popc.maxnctapersm directive was deprecated and replaced with .lt. Instructions prefetch and prefetchu have also been added. has been added. cvta.shared have been extended to handle 64-bit data types for sm_20 targets.1.ballot.pred have been added. bar now supports optional thread count and register operands. e.minnctapersm to better match its behavior and usage. has been added. has been added.add. has been added.f32 have been implemented. has been added.le. bfe and bfi. has been added.

In PTX version 1. stack-based ABI is unimplemented. 2010 .5 and later. where .s32.3. See individual instruction descriptions for details.p sust.f32.p.4 and earlier. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.4 or earlier. the correct number is sixteen. Formatted surface load is unimplemented. or .5.max} are not implemented.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. Support for variadic functions and alloca are unimplemented. 11.f32} atom.f32 type is unimplemented.s32. cvt. Instruction bra.u32.{u32. To maintain compatibility with legacy PTX code.2. 172 January 24.target sm_1x. The underlying. has been fixed. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. Semantic Changes and Clarifications The errata in cvt.0 11.1. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. Formatted surface store with .red}.PTX ISA Version 2.version is 1. {atom.ftz for PTX ISA versions 1. if .ftz (and cvt for . .1. call suld.{min.

pragma “nounroll”. L1_body: … L1_continue: bra L1_head. Table 145.0.pragma Strings This section describes the . L1_end: … } // do not unroll this loop January 24.pragma “nounroll”. disables unrolling for all loops in the entry function body. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma strings defined by ptxas. entry-function. Descriptions of . including loops preceding the .pragma “nounroll”. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. .entry foo (…) . Ignored for sm_1x targets. The “nounroll” pragma is allowed at module. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Appendix A. and statement levels. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma. … @p bra L1_end. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.func bar (…) { … L1_head: . Note that in order to have the desired effect at statement level. disables unrolling of0 the loop for which the current block is the loop header. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. { … } // do not unroll any loop in this function . Supported only for sm_20 targets. . 2010 173 .

2010 .PTX ISA Version 2.0 174 January 24.

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