NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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......................................................... 44 Scalar Conversions ............... State Spaces .................................4...............................................................................................5... 29 Parameter State Space . 6.... 33 Restricted Use of Sub-Word Sizes ....................................................................................... 49 ii January 24.... 29 Local State Space .....................................4......... 5....................................... 32 Texture State Space (deprecated) .............2.................................................. 38 Initializers .. 5............................8...................... 5.................................................................................. 42 Arrays as Operands ...... 6.7...................... 43 Labels and Function Names as Operands .................................. 5............ 41 6................................................................................................................. 34 Variables ........................................2........................ 49 7.................................................................................................................. Sampler....................................1...........1...... 39 5.......PTX ISA Version 2.......... 27 Register State Space ......... 37 Array Declarations ... 5...3.........................1............................................................................................................3.... 37 Variable Declarations ....4................................................... 6............ 5.3.......................1....... 5.............. 5...4........ Operand Costs .......................1........5... Type Conversion................4........................... 5............ 5........ 2010 ......................................4.... 43 Vectors as Operands ........4.....2.5..................................................................5............4............ Instruction Operands............... 39 Parameterized Variable Names .........1...................1....... 6.2....................................... 32 5........ 29 Global State Space ........3...............................1.6..............2. 5.............................4.. Summary of Constant Expression Evaluation Rules .. 6.................. Types................ 5.................. 42 Addresses as Operands ....................................................................... 30 Shared State Space..................5......... Types ....................................4..6.............1............................6................... and Surface Types ........................................ and Vectors ........4.......................................... 43 6.5...... 6................ 5................................................... 41 Using Addresses...................................... Abstracting the ABI . 5............................................................................................................................. 27 5.... 41 Source Operands..............................................................0 4..............3.......................................2....... 44 Rounding Modifiers ....1................... 33 5.....................................................................6...........1........................................ Texture....1......... State Spaces.............2.......................................... Function declarations and definitions ................................................................................................................................................................................................. 41 Destination Operands ..................4. 6...............................4........ Arrays........ 47 Chapter 7............................................. Chapter 6.....................4............ 28 Special Register State Space ............... 46 6.................................. and Variables .................2.......................................................................4........... 6........................ 5... 38 Alignment ................1.............1............1.............................. 33 Fundamental Types ................................................. 25 Chapter 5..................................... Operand Type Information ......................................................2.... 37 Vectors ......................................................... 5.............. 28 Constant State Space ..................... 6.....................................1....

. PTX Version and Target Directives ................................. 11..............................3........................................................... 8. 8. 157 10............. 8..................... 8...7....3.............. 104 Data Movement and Conversion Instructions ....... 2010 iii .....4.........3............... 168 Chapter 11........ 10......... Changes in Version 2....................1.2............................................... 62 8...................................................... 169 11.........................................7...... 172 January 24......................................2................ 11........ 55 Predicated Execution ..........9........................................ Directives .1..........................................................................................................................................................................4.................... 8.......8................................. 172 Unimplemented Features Remaining ..............................................................................7...............7.........................................................0 ..................... 60 8................................. 8.........................................................7............................................. 53 Alloca ...............................1..................................... 56 Comparisons ...........7......................6...... 63 Floating-Point Instructions .....................6.................................................. Release Notes ........................................... Special Registers ..7.... 8.... 162 Debugging Directives .3... 8..................... 132 Video Instructions ..5.......................................................................................... Instruction Set ................... 11.................................. 62 Machine-Specific Semantics of 16-bit Code ....................2......... 149 Chapter 10......... 147 8..3......................................................... 170 New Features ..................... 81 Comparison and Selection Instructions ...... 8....... 63 Integer Arithmetic Instructions ......................... 8...... 100 Logic and Shift Instructions ..........1.1.......................... 10................. 7.......2.........6....... 8..1............ Divergence of Threads in Control Constructs ...................................................................4..1..........7.............................................2.................... Chapter 9........4....1...2............. 157 Specifying Kernel Entry Points and Functions ..........1............. Changes from PTX 1.........................x ............. 62 Semantics .... 8................ 166 Linking Directives ............................................6...................................................................... 54 Chapter 8......... 7........................................................ 55 PTX Instructions ................7............................................................................................................1...1.......................... 58 8..... 10................. 122 Control Flow Instructions .......................................................1..................................................................................................... 8.10......... 59 Operand Size Exceeding Instruction-Type Size ..5......................3...................................................................1..........................7..................................................................... 8................................................................................. 129 Parallel Synchronization and Communication Instructions ............................ 10............................... 170 Semantic Changes and Clarifications ............................ 57 Manipulating Predicates ... 160 Performance-Tuning Directives ............ Type Information for Instructions and Operands ................ 108 Texture and Surface Instructions ...........7......7..... 52 Variadic functions .........7........................................ Format and Semantics of Instruction Descriptions ..............................................3..................................................................................... 140 Miscellaneous Instructions.......... 55 8.............. 8...... 8.................. Instructions ....................................................

........0 Appendix A........PTX ISA Version 2.. 173 iv January 24.................... Descriptions of ...............pragma Strings..... 2010 ..........

............................ 2010 v .... 68 Integer Arithmetic Instructions: mul24 . 23 Constant Expression Evaluation Rules ..... 64 Integer Arithmetic Instructions: sub ............................................... Table 5............. Table 30..... 57 Floating-Point Comparison Operators Accepting NaN .. Table 4............................................................................................................................................................................... 47 Operators for Signed Integer... Table 2..................... 46 Integer Rounding Modifiers ................... 46 Cost Estimates for Accessing State-Spaces ....................................................................................................... Table 29.... Table 7. 58 Type Checking Rules ................................................................................... Table 10.......List of Tables Table 1.. Table 18........................... 25 State Spaces ............................................................. 35 Convert Instruction Precision and Format .......................................................................... 33 Opaque Type Fields in Unified Texture Mode .. Table 11............ Table 24............... 65 Integer Arithmetic Instructions: sub........................................... 66 Integer Arithmetic Instructions: mul .................................................................. 65 Integer Arithmetic Instructions: addc ..................................................... and Bit-Size Types ................................ 45 Floating-Point Rounding Modifiers ............................... 60 Relaxed Type-checking Rules for Destination Operands........................................................... Unsigned Integer......................... 61 Integer Arithmetic Instructions: add ................................ 57 Floating-Point Comparison Operators ..............................................................cc .......................... Table 31.......... Table 9..................... Table 19........................................................ 64 Integer Arithmetic Instructions: add........................................... Table 16............... Table 3................ Table 21....... Table 15........... Table 8..................... Table 28........................................................ Table 32............................. 28 Fundamental Type Specifiers ...... 19 Predefined Identifiers ......... 67 Integer Arithmetic Instructions: mad .. 66 Integer Arithmetic Instructions: subc ......................................... Table 20......................................................... Table 27........ 35 Opaque Type Fields in Independent Texture Mode ........... Table 6... 70 Integer Arithmetic Instructions: sad .......................................... 18 Reserved Instruction Keywords ..................................................................................................................................................................................... Table 17...................... 69 Integer Arithmetic Instructions: mad24 ............ 20 Operator Precedence ............ Table 26.. 27 Properties of State Spaces ........ Table 13........................................................... Table 23.................................... Table 14.............................. 58 Floating-Point Comparison Operators Testing for NaN ............. Table 12....................................................................................... Table 22................................................................ Table 25.................................................................... PTX Directives ...........................................cc ............................................ 71 January 24................... 59 Relaxed Type-checking Rules for Source Operands .......................

........ Table 55......... Table 54....... 103 Comparison and Selection Instructions: slct ........... 74 Integer Arithmetic Instructions: clz .................................. Table 42........... Table 47............... 97 Floating-Point Instructions: lg2 ............................................................... Table 41............................................ Table 61............................. 83 Floating-Point Instructions: add . 73 Integer Arithmetic Instructions: max .......................................... Table 45... 85 Floating-Point Instructions: mul ......... 71 Integer Arithmetic Instructions: abs ........................ 91 Floating-Point Instructions: min ......... Table 60.................. Table 66......... 86 Floating-Point Instructions: fma ................................ 79 Summary of Floating-Point Instructions ............... Integer Arithmetic Instructions: div .... 98 Floating-Point Instructions: ex2 ................................................................... 88 Floating-Point Instructions: div ......................................................................................................................................................... Table 50......................................................................................... Table 43................................... 82 Floating-Point Instructions: testp ....................................................................... Table 34....................................................... Table 40................ Table 58..................................................PTX ISA Version 2.................................................................................................................................................................. 83 Floating-Point Instructions: copysign .............................. 2010 ................... Table 49.......................................... Table 63.............................. Table 59.................................................................................... Table 36........ Table 35......... Table 46.................................................. 87 Floating-Point Instructions: mad .......................... Table 65............................................................................................... 91 Floating-Point Instructions: neg ... Table 39........... 76 Integer Arithmetic Instructions: bfe ................................................................................................................... Table 68........................................................... 103 vi January 24................. Table 44.............. 90 Floating-Point Instructions: abs ....... Table 67......................................... Table 64......................................................................................................... 78 Integer Arithmetic Instructions: prmt ...................................................................... 96 Floating-Point Instructions: cos . 71 Integer Arithmetic Instructions: rem .............. 95 Floating-Point Instructions: sin .................. Table 37.................................................................................... 99 Comparison and Selection Instructions: set .......... 72 Integer Arithmetic Instructions: min ................................................... Table 48............. Table 57... 74 Integer Arithmetic Instructions: bfind ................ 92 Floating-Point Instructions: rcp ..... 102 Comparison and Selection Instructions: selp .................... 75 Integer Arithmetic Instructions: brev ................. 77 Integer Arithmetic Instructions: bfi ......................... 73 Integer Arithmetic Instructions: popc ............................................. 92 Floating-Point Instructions: max .... 93 Floating-Point Instructions: sqrt ............................................ 101 Comparison and Selection Instructions: setp ...... 84 Floating-Point Instructions: sub .............................. Table 52............................................................................................................................................. Table 53.................................................................... 94 Floating-Point Instructions: rsqrt ........ Table 69..................... 72 Integer Arithmetic Instructions: neg ................................. Table 38.......................................... Table 56...............................................0 Table 33........................................................................ Table 62.................. Table 51..........................

............................................................................. Table 85....................... Table 77.............. Table 102.. 123 Texture and Surface Instructions: txq . 107 Logic and Shift Instructions: shr . 109 Cache Operators for Memory Store Instructions ............ 110 Data Movement and Conversion Instructions: mov ............... 112 Data Movement and Conversion Instructions: ld .......... 134 Parallel Synchronization and Communication Instructions: atom .............................................................. Table 78........................................................ Table 75................................................................................. Table 84..................... 143 January 24....................................................... Table 76..................... prefetchu . 129 Control Flow Instructions: bra .......................... 126 Texture and Surface Instructions: sured................... Table 74................... Table 86........... 131 Parallel Synchronization and Communication Instructions: bar ............... Table 90......................................................................... 135 Parallel Synchronization and Communication Instructions: red .................... 120 Texture and Surface Instructions: tex ......... 105 Logic and Shift Instructions: or ......................... Table 88............ vsub.. 119 Data Movement and Conversion Instructions: cvta .. Table 72......................... Table 97......... 119 Data Movement and Conversion Instructions: cvt .......... Table 106.... 107 Cache Operators for Memory Load Instructions .................... Table 99....................................................... Table 73........................................................... 2010 vii ........................................... Table 103...................................... 106 Logic and Shift Instructions: not ..................... Table 87....................................... 111 Data Movement and Conversion Instructions: mov . 137 Parallel Synchronization and Communication Instructions: vote ............ 105 Logic and Shift Instructions: xor ......... 131 Control Flow Instructions: exit ............. 115 Data Movement and Conversion Instructions: st ........................... 142 Video Instructions: vshl.............. 118 Data Movement and Conversion Instructions: isspacep ................. 127 Texture and Surface Instructions: suq ....... vshr ... Table 71.......................................... 129 Control Flow Instructions: @ ... vmin....................................... Table 81........... Table 105.......... Table 89........................... 133 Parallel Synchronization and Communication Instructions: membar ........................ Table 79.............................................. 139 Video Instructions: vadd..........................Table 70........ Table 96......... Table 91....... 130 Control Flow Instructions: ret ... 130 Control Flow Instructions: call ....................................... 106 Logic and Shift Instructions: shl .................................................................... Table 95........... Table 80......................................................... Table 98.............................................................. Logic and Shift Instructions: and ......................................................... 113 Data Movement and Conversion Instructions: ldu .......... Table 94................................................. 125 Texture and Surface Instructions: sust ............................ vmax ....... vabsdiff.................................................................................................. Table 104.......... 106 Logic and Shift Instructions: cnot . 124 Texture and Surface Instructions: suld ...... 128 Control Flow Instructions: { } .... 116 Data Movement and Conversion Instructions: prefetch..................................................................................... Table 100....................................................................... Table 83.................................................................................... Table 82.................................................... Table 93..... Table 101.................................. Table 92.........................

....................func ............. 154 Special Registers: %lanemask_ge ........................................... Table 121....... Table 133................................. Table 122.. Table 137................ 161 Performance-Tuning Directives: ........ 154 Special Registers: %lanemask_le .............. 155 Special Registers: %lanemask_gt ..... 153 Special Registers: %lanemask_eq ....................................................... 147 Miscellaneous Instructions: pmevent............. Table 116.......... 165 Debugging Directives: @@DWARF ......................................................entry.......... Table 130..................................................................................... Table 138...................... 163 Performance-Tuning Directives: ............................................ 147 Miscellaneous Instructions: brkpt .............................................................................. 156 PTX File Directives: ......... 167 Debugging Directives: .... Table 115............................................................................................................... 164 Performance-Tuning Directives: .................................... Table 111................... Table 114....version...........pragma ....................................0 Table 107..... Table 120................................................................loc ....................................................... Table 141..... Table 140...................... Table 113....................................... 151 Special Registers: %nwarpid ..................................... Table 129... 151 Special Registers: %warpid ..... 151 Special Registers: %ctaid . 152 Special Registers: %nctaid ... 153 Special Registers: %gridid ........................... Table 109............... 152 Special Registers: %smid .............................................................................target .............................................................................................................minnctapersm ... 2010 .............. Table 131....................................................PTX ISA Version 2........ 158 Kernel and Function Directives: .......................... %pm2............................................ Table 125............ 167 Linking Directives: ... Table 135.......................extern..................................................................maxnctapersm (deprecated) ................................... 150 Special Registers: %laneid ....................................... Table 126........ Table 134.......................... Video Instructions: vmad ................................................ Table 139......... Table 136...........................................................................................................................maxnreg ................section ...... 154 Special Registers: %lanemask_lt .............. 146 Miscellaneous Instructions: trap ... 166 Debugging Directives: ..................................maxntid ......file ......................... 163 Performance-Tuning Directives: ................ Table 110........ 164 Performance-Tuning Directives: .................... Table 124.... Table 118........................................... %pm3 . Table 123....................................................... Table 127.................................................................................... 150 Special Registers: %ntid ............................ 156 Special Registers: %pm0........ 157 PTX File Directives: ............................................ Table 108.................................... Table 128............................. %pm1....... 147 Special Registers: %tid ........................ 153 Special Registers: %nsmid ................ 155 Special Registers: %clock ...................... Table 119............................. 160 Kernel and Function Directives: ....... 156 Special Registers: %clock64 ........................................................................................................................ 144 Video Instructions: vset.......................................................... Table 112.................................................. 168 viii January 24......... 167 Debugging Directives: ................. Table 117.. Table 142................................................. Table 143............. Table 132.....................................................................

............................................ Table 145....Table 144...................... 168 Pragma Strings: “nounroll” ...................................... 173 January 24........... 2010 ix .... Linking Directives: .....................visible...........................

PTX ISA Version 2. 2010 .0 x January 24.

and because it is executed on many data elements and has high arithmetic intensity. PTX exposes the GPU as a data-parallel computing device. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. video encoding and decoding. January 24. Introduction This document describes PTX. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). from general signal processing or physics simulation to computational finance or computational biology. the programmable GPU has evolved into a highly parallel. many-core processor with tremendous computational horsepower and very high memory bandwidth. PTX defines a virtual machine and ISA for general purpose parallel thread execution. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. image and media processing applications such as post-processing of rendered images. 1.2. In fact. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. 2010 1 . stereo vision. the memory access latency can be hidden with calculations instead of big data caches. PTX programs are translated at install time to the target hardware instruction set. which are optimized for and translated to native target-architecture instructions. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. image scaling. high-definition 3D graphics. multithreaded.1. and pattern recognition can map image blocks and pixels to parallel processing threads. Similarly. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Because the same program is executed for each data element. there is a lower requirement for sophisticated flow control. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.Chapter 1. Data-parallel processing maps data elements to parallel processing threads. 1.

and video instructions. Provide a code distribution ISA for application and middleware developers.f32 instruction also supports . The mad. Achieve performance in compiled applications comparable to native GPU performance.x. Single-precision add. fma. 1. Most of the new features require a sm_20 target. The changes from PTX ISA 1. Provide a common source-level ISA for optimizing code generators and translators. A “flush-to-zero” (.f32 for sm_20 targets. Provide a machine-independent ISA for C/C++ and other compilers to target. 1. and mul now support . Improved Floating-Point Support A main area of change in PTX 2. performance kernels. atomic. and all PTX 1.x code will continue to run on sm_1x targets as well.f32 and mad. Instructions marked with .1. When code compiled for sm_1x is executed on sm_20 devices. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.f32.ftz) modifier may be used to enforce backward compatibility with sm_1x.PTX ISA Version 2.0 PTX ISA Version 2.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. PTX ISA Version 2.3.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.rp rounding modifiers for sm_20 targets. including integer.ftz and . PTX 2.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.f32 requires sm_20.f32 maps to fma. Both fma.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.3.f32 require a rounding modifier for sm_20 targets.0 are improved support for IEEE 754 floating-point operations. addition of generic addressing to facilitate the use of general-purpose pointers. and the introduction of many new instructions. The main areas of change in PTX 2. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rn. surface. A single-precision fused multiply-add (fma) instruction has been added. and architecture tests. reduction. Facilitate hand-coding of libraries. barrier. 2010 . mad. Legacy PTX 1.rm and . extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.0 is in improved support for the IEEE 754 floating-point standard. The fma. sub.sat modifiers. which map PTX to specific target machines.x features are supported on the new sm_20 target. memory.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. • • • 2 January 24.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The mad.0 is a superset of PTX 1.

Generic Addressing Another major change is the addition of generic addressing. stack-based ABI. 1. Surface Instructions • • Instruction sust now supports formatted surface stores. Support for an Application Binary Interface Rather than expose details of a particular calling convention. ldu. NOTE: The current version of PTX does not implement the underlying. i. Instruction cvta for converting global.3. prefetch. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. In PTX 2. suld. for prefetching to specified level of memory hierarchy. st. st.clamp and . Instructions prefetch and prefetchu have been added. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Introduction • Single.zero.4. 2010 3 .e. and vice versa. and directives are introduced in PTX 2. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.2. these changes bring PTX 2.0. January 24. PTX 2. special registers. .g. Surface instructions support additional clamp modifiers. and sust. stack layout.3.0 closer to full compliance with the IEEE 754 standard. so recursion is not yet supported.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. and red now support generic addressing. Instructions testp and copysign have been added. allowing memory instructions to access these spaces without needing to specify the state space. e. local.. New Instructions The following new instructions. Cache operations have been added to instructions ld.3. rcp. 1. isspacep. and Application Binary Interface (ABI).3. prefetchu.0. and sqrt with IEEE 754 compliant rounding have been added. and shared state spaces. an address that is the same across all threads in a warp. local. and shared addresses to generic addresses. local. Generic addressing unifies the global. These are indicated by the use of a rounding modifier and require sm_20. atom. • Taken as a whole.Chapter 1. instructions ld. A new cvta instruction has been added to convert global.and double-precision div. 1. and shared addresses to generic address and vice-versa has been added. cvta.

red}.shared have been extended to handle 64-bit data types for sm_20 targets. Other Extensions • • • Video instructions (includes prmt) have been added. Reduction.red}. 2010 .f32 have been added. A bar. bfi bit field extract and insert popc clz Atomic. membar. %clock64. New special registers %nsmid. vote.le.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.b32.section. 4 January 24.pred have been added.gt} have been added.arrive instruction has been added. bar now supports an optional thread count and register operands. .ballot. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added. A “vote ballot” instruction.PTX ISA Version 2. has been added. Instructions bar.sys.ge. A new directive.u32 and bar.lt.or}. Instructions {atom.red. and Vote Instructions • • • New atomic and reduction instructions {atom.add.{and.popc. Barrier Instructions • • A system-level membar instruction.red. %lanemask_{eq.

2010 5 . calling convention. Chapter 9 lists special registers. Chapter 7 describes the function and call syntax. January 24. Chapter 6 describes instruction operands. Chapter 11 provides release notes for PTX Version 2. Chapter 8 describes the instruction set. types. Chapter 4 describes the basic syntax of the PTX language. Introduction 1.Chapter 1.4. Chapter 10 lists the assembly directives supported in PTX. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 5 describes state spaces.0. Chapter 3 gives an overview of the PTX virtual machine model. and variable declarations.

PTX ISA Version 2. 2010 .0 6 January 24.

Chapter 2. More precisely. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. It operates as a coprocessor to the main CPU. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.1. The thread identifier is a three-element vector tid. Each CTA thread uses its thread identifier to determine its assigned role. assign specific input and output positions. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. or 3D shape specified by a three-element vector ntid (with elements ntid. is an array of threads that execute a kernel concurrently or in parallel. A cooperative thread array.y.z) that specifies the thread’s position within a 1D.2. 2.x. (with elements tid.1.z). January 24. Cooperative thread arrays (CTAs) implement CUDA thread blocks. tid. work. 2.y. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. 2D. 2D. To that effect. or 3D CTA.x. and ntid.2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Programming Model 2. compute addresses. Programs use a data parallel decomposition to partition inputs. ntid. Threads within a CTA can communicate with each other. data-parallel. or host: In other words. or CTA. and tid. Each CTA has a 1D. and results across the threads of the CTA. The vector ntid specifies the number of threads in each CTA dimension. a portion of an application that is executed many times. To coordinate the communication of the threads within the CTA. compute-intensive portions of applications running on the host are off-loaded onto the device. can be isolated into a kernel function that is executed on the GPU as many different threads. Each thread has a unique thread identifier within the CTA. and select work to perform. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2010 7 . but independently on different data.

0 Threads within a CTA execute in SIMT (single-instruction. 2010 . A warp is a maximal subset of threads from a single CTA. Multiple CTAs may execute concurrently and in parallel. The host issues a succession of kernel invocations to the device. CTAs that execute the same kernel can be batched together into a grid of CTAs. Each grid also has a unique temporal grid identifier (gridid). a warp has 32 threads. multiple-thread) fashion in groups called warps. 2. WARP_SZ.PTX ISA Version 2. %ntid. Typically. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Threads may read and use these values through predefined. This comes at the expense of reduced thread communication and synchronization. 8 January 24. Some applications may be able to maximize performance with knowledge of the warp size. Each grid of CTAs has a 1D. read-only special registers %tid. and %gridid.2. Threads within a warp are sequentially numbered. or sequentially. so that the total number of threads that can be launched in a single kernel invocation is very large. or 3D shape specified by the parameter nctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs.2. %ctaid. The warp size is a machine-dependent constant. so PTX includes a run-time immediate constant. However. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. %nctaid. which may be used in any instruction where an immediate operand is allowed. such that the threads execute the same instructions at the same time. because threads in different CTAs cannot communicate and synchronize with each other. 2D . depending on the platform.

1) CTA (1. 0) Thread (0. 1) CTA (2.Chapter 2. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (3. 2) Thread (4. 1) Thread (4. Thread Batching January 24. 1) Thread (0. 0) Thread (4. 1) Thread (2. 2) Thread (2. 0) Thread (2. 2010 9 . 1) Thread (3. 0) CTA (0. 1) Thread (1. 2) Thread (1. 0) CTA (1. 0) CTA (2. 1) Thread (0. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) Thread (3. 0) Thread (1. A grid is a set of CTAs that execute independently. Figure 1.

Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. constant. 2010 . constant. The device memory may be mapped and read or written by the host. and texture memory spaces are persistent across kernel launches by the same application. Texture memory also offers different addressing modes. The global. as well as data filtering. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.PTX ISA Version 2. Both the host and the device maintain their own local memory. or.3. all threads have access to the same global memory. and texture memory spaces are optimized for different memory usages.0 2. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Each thread has a private local memory. for some specific data formats. Finally. for more efficient transfer. The global. referred to as host memory and device memory. 10 January 24. respectively.

Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Grid 1 Global memory Block (0. 0) Block (1. 2) Figure 2. 0) Block (0. 0) Block (2. 1) Block (1. 2010 11 . 1) Block (2. Memory Hierarchy January 24. 1) Block (0. 0) Block (0. 2) Block (1. 0) Block (1. 1) Block (1.Chapter 2.

PTX ISA Version 2.0 12 January 24. 2010 .

At every instruction issue time. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. The multiprocessor creates. When a host program invokes a kernel grid. It implements a single-instruction barrier synchronization. a cell in a grid-based computation). and executes threads in groups of parallel threads called warps. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). When a multiprocessor is given one or more thread blocks to execute. (This term originates from weaving. for example. January 24. and executes concurrent threads in hardware with zero scheduling overhead. and when all paths complete. To manage hundreds of threads running several different programs. A warp executes one common instruction at a time. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. If threads of a warp diverge via a data-dependent conditional branch.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. allowing.1. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. so full efficiency is realized when all threads of a warp agree on their execution path. The way a block is split into warps is always the same. Parallel Thread Execution Machine Model 3. The multiprocessor maps each thread to one scalar processor core. the multiprocessor employs a new architecture we call SIMT (single-instruction. the threads converge back to the same execution path.Chapter 3. the warp serially executes each branch path taken. it splits them into warps that get scheduled by the SIMT unit. manages. disabling threads that are not on that path. multiple-thread). and each scalar thread executes independently with its own instruction address and register state. and on-chip shared memory. a voxel in a volume. each warp contains threads of consecutive. A multiprocessor consists of multiple Scalar Processor (SP) cores. The threads of a thread block execute concurrently on one multiprocessor. increasing thread IDs with the first warp containing thread 0. a multithreaded instruction unit. schedules. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. As thread blocks terminate. the first parallel thread technology. different warps execute independently regardless of whether they are executing common or disjointed code paths. Branch divergence occurs only within a warp. 2010 13 . manages. The multiprocessor SIMT unit creates. new blocks are launched on the vacated multiprocessors.

SIMT enables programmers to write thread-level parallel code for independent. on the other hand. modify. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. but the order in which they occur is undefined. which is a read-only region of device memory. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. In practice. modifies. A key difference is that SIMD vector organizations expose the SIMD width to the software. and writes to the same location in global memory for more than one of the threads of the warp.PTX ISA Version 2. In contrast with SIMD vector machines. but one of the writes is guaranteed to succeed. the programmer can essentially ignore the SIMT behavior. • The local and global memory spaces are read-write regions of device memory and are not cached. 14 January 24. which is a read-only region of device memory. the kernel will fail to launch. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A multiprocessor can execute as many as eight thread blocks concurrently. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. As illustrated by Figure 3. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. write to that location occurs and they are all serialized. the number of serialized writes that occur to that location and the order in which they occur is undefined. For the purposes of correctness. as well as data-parallel code for coordinated threads. each read. require the software to coalesce loads into vectors and manage divergence manually. however. If an atomic instruction executed by a warp reads. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. scalar threads. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. whereas SIMT instructions specify the execution and branching behavior of a single thread. If there are not enough registers or shared memory available per multiprocessor to process at least one block. 2010 . Vector architectures.0 SIMT architecture is akin to SIMD (Single Instruction.

Chapter 3. Hardware Model January 24. Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 .

0 16 January 24.PTX ISA Version 2. 2010 .

PTX is case sensitive and uses lowercase for keywords. 4. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #ifdef.target directive specifying the target architecture assumed. Lines are separated by the newline character (‘\n’).1. #line. Each PTX file must begin with a . The C preprocessor cpp may be used to process PTX source files. #if. January 24. Comments Comments in PTX follow C/C++ syntax. using non-nested /* and */ for comments that may span multiple lines. Syntax PTX programs are a collection of text source files. 2010 17 . #define. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Source Format Source files are ASCII text.2. Pseudo-operations specify symbol and addressing management.version directive specifying the PTX language version.Chapter 4. followed by a . All whitespace characters are equivalent. and using // to begin a comment that extends to the end of the current line. 4. #else. See Section 9 for a more information on these directives. The following are common preprocessor directives: #include. Comments in PTX are treated as whitespace. #endif. whitespace is ignored except for its use in separating tokens in the language. Lines beginning with # are preprocessor directives. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.

mov. %tid.version . r2. .section .local .extern . 2010 .f32 array[N]. constant expressions.2. where p is a predicate register. or label names.file PTX Directives . r1. The guard predicate follows the optional label and precedes the opcode. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.pragma . followed by source operands. and terminated with a semicolon.target . The guard predicate may be optionally negated. All instruction keywords are reserved tokens in PTX.b32 add. The destination operand is first. ld. Table 1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.3.1.PTX ISA Version 2.shared .x. Statements A PTX statement is either a directive or an instruction. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. Directive Statements Directive keywords begin with a dot. 0. r2.b32 r1.sreg . address expressions.maxnreg . 2.visible 4. array[r1].3.b32 r1.entry .tex .3.5. .loc .maxnctapersm . Instructions have an optional guard predicate which controls conditional execution. r2.minnctapersm .b32 r1. and is written as @p.const . written as @!p.reg .0 4. Instruction keywords are listed in Table 2.global start: .global . 18 January 24. shl. Examples: . Operands may be register variables.align .param .func .f32 r2. so no conflict is possible with user-defined identifiers. Statements begin with an optional label and end with a semicolon.maxntid .global.reg .

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .Chapter 4. Syntax Table 2.

Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. e. or they start with an underscore. PTX allows the percentage sign as the first character of an identifier.PTX ISA Version 2. digits.g. Table 3. between user-defined variable names and compiler-generated names. or percentage character followed by one or more letters. except that the percentage sign is not allowed. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. or dollar characters. %pm3 WARP_SZ 20 January 24. 2010 . %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. dollar. PTX predefines one constant and a small number of special registers that begin with the percentage sign.0 4. underscore. underscore. Many high-level languages such as C and C++ follow similar rules for identifier names. The percentage sign can be used to avoid name conflicts.4. …. listed in Table 3. digits.

The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.e. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. To specify IEEE 754 single-precision floating point values.e.2. octal. and bit-size types. 4. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.u64). 4. Unlike C and C++.5. i. Syntax 4. When used in an instruction or data initialization.. Constants PTX supports integer and floating-point constants and constant expressions. zero values are FALSE and non-zero values are TRUE. Floating-point literals may be written with an optional decimal point and an optional signed exponent. where the behavior of the operation depends on the operand types. 2010 21 . literals are always represented in 64-bit double-precision format. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. To specify IEEE 754 doubleprecision floating point values.Chapter 4.5. integer constants are allowed and are interpreted as in C. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. i. the sm_1x and sm_20 targets have a WARP_SZ value of 32.s64) unless the value cannot be fully represented in .. every integer constant has type . Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.1. Type checking rules remain the same for integer. there is no suffix letter to specify size. hexadecimal. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. These constants may be used in data initialization and as operands to instructions. the constant begins with 0f or 0F followed by 8 hex digits. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. For predicate-type data and instructions. floating-point. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.s64 or the unsigned suffix is specified. 0[fF]{hexdigit}{8} // single-precision floating point January 24.u64. Integer literals may be written in decimal. in which case the literal is unsigned (. each integer constant is converted to the appropriate size based on the data or instruction type at its use. The syntax follows that of C.5. the constant begins with 0d or 0D followed by 16 hex digits.s64 or . or binary notation.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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2nd is .u64.f64 use usual conversions . or .u64 .f64 use usual conversions .f64 same as source . Syntax 4.f64 converted type . . Table 5.u64 .f64 integer .s64 .u64 1st unchanged.u64 .f64 use usual conversions .f64 integer integer integer integer integer int ?.s64) + .5.f64 converted type constant literal + ! ~ Cast Binary (.u64 same as 1st operand .f64 integer . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . 2010 25 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .s64 .s64.f64 : .s64 .Chapter 4.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .s64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .6.u64 .s64 .u64 .u64) (.s64 .

PTX ISA Version 2.0 26 January 24. 2010 .

reg . platform-specific. access speed. access rights. Global memory. defined per-grid. 2010 27 . State Spaces A state space is a storage area with particular characteristics.sreg .tex January 24. 5. and properties of state spaces are shown in Table 5.local . private to each thread. Addressable memory shared between threads in 1 CTA. the kinds of resources will be common across platforms. or Function or local parameters. fast. Global texture memory (deprecated). State Spaces. and level of sharing between threads. defined per-thread. Read-only. The characteristics of a state space include its size.const . and Variables While the specific resources available in a given target GPU will vary. Special registers. and these resources are abstracted in PTX through state spaces and data types. Shared. read-only memory. The list of state spaces is shown in Table 4. Kernel parameters.shared . Table 6. Local memory.Chapter 5.global . All variables reside in some state space. pre-defined. . Name State Spaces Description Registers.1.param . The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. addressability. Types. shared by all threads.

28 January 24.param (used in functions) . clock counters.const . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). it is not possible to refer to the address of a register.PTX ISA Version 2. the parameter is then located on the stack frame and its address is in the .1.param and st. Register size is restricted.1.reg state space) are fast storage locations.local . Special Register State Space The special register (. 2010 .local state space.2. unsigned integer. and thread parameters. 1 Accessible only via the ld. 3 Accessible only via the tex instruction. or 64-bits. register variables will be spilled to memory. Registers may be typed (signed integer. and will vary from platform to platform. or 128-bits. 32-. When the limit is exceeded. floating point. st. 64-.param instructions. Device function input parameters may have their address taken via mov.e. and performance monitoring registers. such as grid. and cvt instructions.0 Table 7.param instruction.sreg) state space holds predefined. platform-specific registers. scalar registers have a width of 8-.reg .tex Restricted Yes No3 5. 32-.1. The most common use of 8-bit registers is with ld.param (as input to kernel) . CTA. Registers may have alignment boundaries required by multi-word loads and stores. 2 Accessible via ld.global . For each architecture. predicate) or untyped. Registers differ from the other state spaces in that they are not fully addressable. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Register State Space Registers (. causing changes in performance. 5. 16-. All special registers are predefined. Address may be taken via mov instruction. The number of registers is limited.shared . aside from predicate registers which are 1-bit. and vector registers have a width of 16-. i. or as elements of vector tuples.sreg ..

This pointer can then be used to access the entire 64KB constant bank.sync instruction are guaranteed to be visible to any reads after the barrier instruction. In implementations that support a stack. the store operation updating a may still be in flight. Local State Space The local state space (. If no bank number is given. Threads must be able to do their work without waiting for other threads to do theirs. Consider the case where one thread executes the following two assignments: a = a + 1. The size is limited.global.1. For example. where bank ranges from 0 to 10. It is the mechanism by which different CTAs and different grids can communicate.sync instruction. ld. Global State Space The global (. Multiple incomplete array variables declared in the same bank become aliases. bank zero is used for all statically-sized constant variables.extern . the stack is in local memory. and atom.4. whereas local memory variables declared January 24.const[bank] modifier.local and st.const[2] .1. the declaration . all addresses are in global memory are shared.3. results in const_buffer pointing to the start of constant bank two. initialized by the host.1. and Variables 5. [const_buffer+4]. For the current devices.local to access local variables. as in lock-free and wait-free style programming.local) is private memory for each thread to keep its own data. where the size is not known at compile time.b32 %r1. for example). Global memory is not sequentially consistent. By convention.global. To access data in contant banks 1 through 10. For any thread in a context. Sequential consistency is provided by the bar. Types. an incomplete array in bank 2 is accessed as follows: . there are eleven 64KB banks.const) state space is a read-only memory. Use ld. This reiterates the kind of parallelism available in machines that run PTX. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. The constant memory is organized into fixed size banks.global) state space is memory that is accessible by all threads in a context. State Spaces. st.extern . The remaining banks may be used to implement “incomplete” constant arrays (in C. Threads wait at the barrier until all threads in the CTA have arrived. as it must be allocated on a perthread basis. Use ld.5.Chapter 5. the bank number must be provided in the state space of the load instruction. bank zero is used. For example. 5.b32 const_buffer[].const[2] .global to access global variables. Constant State Space The constant (. // load second word 5.b32 const_buffer[].const[2]. Banks are specified using the . each pointing to the start address of the specified constant bank. If another thread sees the variable b change. 2010 29 . It is typically standard memory with cache. All memory writes prior to the bar. Module-scoped local memory variables are stored at fixed addresses. b = b – 1.

param . . Parameter State Space The parameter (.param space variables.reg . [%ptr].param) state space is used (1) to pass input arguments from the host to the kernel. (2a) to declare formal input and return parameters for device functions called from within kernel execution. The address of a kernel parameter may be moved into a register using the mov instruction.param. The use of parameter state space for device function parameters is new to PTX ISA version 2.param .0 and requires target architecture sm_20. len. No access protection is provided between parameter and global space in this case.0 within a function or kernel body are allocated on the stack. Therefore. These parameters are addressable. PTX code should make no assumptions about the relative locations or ordering of . Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).f64 %d.u32 %n.param state space.u32 %ptr.1. %n.u32 %ptr. per-kernel versus per-thread).param . in some implementations kernel parameters reside in global memory. Values passed from the host to the kernel are accessed through these parameter variables using ld. mov.entry foo ( . In implementations that do not support a stack.6. ld.param. … Example: .param state space and is accessed using ld. … 30 January 24.param space.f64 %d.PTX ISA Version 2.b8 buffer[64] ) { . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. ld. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. The kernel parameter variables are shared across all CTAs within a grid. The resulting address is in the .align 8 .1. 2010 .reg . all local memory variables are stored at fixed addresses and recursive function calls are not supported. 5. ld. device function parameters were previously restricted to the register state space.x supports only kernel function parameters in . Note that PTX ISA versions 1. typically for passing large structures by value to a function. read-only variables declared in the . [N].reg .6.entry bar ( .b32 N. Similarly.b32 len ) { . For example. .u32 %n.param instructions.u32 %n.1. Note: The location of parameter space is implementation specific. [buffer].param instructions. Example: . 5.

dbl. the caller will declare a locally-scoped . … } // code snippet from the caller // struct { double d. passed to foo … . Aside from passing structures by value.func foo ( . Note that the parameter will be copied to the stack if necessary.param byte array variable that represents a flattened C structure or union.param.param. st.param space variable.param space is also required whenever a formal parameter has its address taken within the called function. and so the address will be in the . }.6.Chapter 5. mystruct). Types.f64 dbl.reg . Typically.reg . } mystruct. it is illegal to write to an input parameter or read from a return parameter. It is not possible to use mov to get the address of a return parameter or a locally-scoped .reg . (4. January 24.0 extends the use of parameter space to device function parameters. which declares a .b8 mystruct.reg .param. Function input parameters may be read via ld.local instructions. This will be passed by value to a callee. In PTX.s32 %y. such as C structures larger than 8 bytes.align 8 .s32 %y.f64 %d. The most common use is for passing objects by value that do not fit within a PTX register.param .1. . In this case.local state space and is accessed via ld. int y.align 8 . .reg .param and function return parameters may be written using st.param. and Variables 5. [buffer+8]. ld.2.param. . x. 2010 31 .param . is flattened. ld. . call foo. the address of a function input parameter may be moved into a register using the mov instruction.b32 N. … st. a byte array in parameter space is used. . … See the section on function call syntax for more details.b8 buffer[12] ) { .s32 [mystruct+8].local and st. Device Function Parameters PTX ISA version 2. int y.param formal parameter having the same size and alignment as the passed argument.s32 x.f64 %d. . [buffer].f64 [mystruct+0]. State Spaces. Example: // pass object of type struct { double d.

tex variables are required to be defined in the global scope. See Section 5. The texture name must be of type .shared to access shared variables. tex_f.tex . It is shared by all threads in a context. Shared memory typically has some optimizations to support the sharing.6 for its use in texture instructions.texref. An address in shared memory can be read and written by any thread in a CTA. tex_c. Another is sequential access from sequential threads. Shared State Space The shared (. and . is equivalent to .u32 tex_a.u32 or . and variables declared in the . The . 5.7.7.texref variables in the .global state space. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex state space are equivalent to module-scoped .u32 .tex .1. For example. An error is generated if the maximum number of physical resources is exceeded.u32 tex_a.u32 .u32 .tex) state space is global memory accessed via the texture instruction.1. a legacy PTX definitions such as . and programs should instead reference texture memory through variables of type .tex .8. where all threads read from the same address.texref tex_a.texref type and Section 8.tex directive is retained for backward compatibility. A texture’s base address is assumed to be aligned to a 16-byte boundary.global .tex . where texture identifiers are allocated sequentially beginning with zero. tex_d.shared) state space is a per-CTA region of memory for threads in a CTA to share data. One example is broadcast. 2010 . tex_d.u64. Texture State Space (deprecated) The texture (.tex . Multiple names may be bound to the same physical texture identifier. Use ld.shared and st. The . Texture memory is read-only.tex directive will bind the named texture memory variable to a hardware texture identifier.0 5. Example: . 32 January 24.3 for the description of the . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.PTX ISA Version 2. Physical texture resources are allocated on a per-module granularity.

f32 and . stored.s32. . so that narrow values may be loaded. Types. 5.s8. Signed and unsigned integer types are compatible if they have the same size.pred Most instructions have one or more type specifiers. .b16. Restricted Use of Sub-Word Sizes The .b64 .2. . and .s16. . All floating-point instructions operate only on . .f32 and .u8. the fundamental types reflect the native data types supported by the target architectures.s64 . but typed variables enhance program readability and allow for better operand type checking. st. .u64 . all variables (aside from predicates) could be declared using only bit-size types. Operand types and sizes are checked against instruction types for compatibility. The bitsize type is compatible with any fundamental type having the same size. and cvt instructions. The same typesize specifiers are used for both variable definitions and for typing instructions.u16. For example.b32. .Chapter 5. st.2. . 2010 33 . Types 5. The .1. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. .b8 instruction types are restricted to ld.b8. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . so their names are intentionally short. and Variables 5.f16 floating-point type is allowed only in conversions to and from . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.2.f16. A fundamental type specifies both a basic type and a size.s8. ld. Two fundamental types are compatible if they have the same basic type and are the same size.f32. and converted using regular-width registers. . Register variables are always of a fundamental type. Fundamental Types In PTX. The following table lists the fundamental type specifiers for each basic type: Table 8. State Spaces.2. .u32.u8. In principle.f64 types. and instructions operate on these types. needed to fully specify instruction behavior. For convenience.f64 . stored.f64 types. . or converted to other types and sizes. January 24.

since these properties are defined by . For working with textures and samplers. sust. the resulting pointer may be stored to and loaded from memory. texture and sampler information each have their own handle. but the pointer cannot otherwise be treated as an address.3. and query instructions.texref type that describe sampler properties are ignored. and overall size is hidden to a PTX program. In the independent mode. In independent mode the fields of the . and . The following tables list the named members of each type for unified and independent texture modes.samplerref. base address.surfref. PTX has two modes of operation. but all information about layout. and surface descriptor variables. and de-referenced by texture and surface load. 2010 .PTX ISA Version 2.samplerref variables. samplers. The three built-in types are . Texture. suq).texref.{u32. i.e. Sampler. hence the term “opaque”. passed as a parameter to functions. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. 34 January 24. accessing the pointer with ld and st instructions.texref handle. opaque_var. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. store. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. allowing them to be defined separately and combined at the site of usage in the program. These types have named fields similar to structures.0 5. Retrieving the value of a named member via query instructions (txq. Referencing textures. sured). or surfaces via texture and surface load/store instructions (tex. and Surface Types PTX includes built-in “opaque” types for defining texture.. field ordering. In the unified mode. . or performing pointer arithmetic will result in undefined results.u64} reg. suld. sampler. Creating pointers to opaque variables using mov. texture and sampler information is accessed through a single .

clamp_ogl. clamp_to_border 0. State Spaces.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.texref values in elements in elements in elements 0. Types.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.Chapter 5. 2010 35 .texref values . 1 nearest. linear wrap. clamp_to_edge. 1 ignored ignored ignored ignored . clamp_to_edge. clamp_ogl. clamp_to_border N/A N/A N/A N/A N/A .samplerref values N/A N/A N/A N/A nearest. mirror. mirror. Member width height depth Opaque Type Fields in Unified Texture Mode . linear wrap. Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9.

these variables are declared in the .global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.surfref my_surface_name. . Example: .global .global . these variables must be in the . filter_mode = nearest }.global state space. As kernel parameters. At module scope.samplerref my_sampler_name.texref tex1.texref my_texture_name. Example: .param state space. 36 January 24.PTX ISA Version 2. the types may be initialized using a list of static expressions assigning values to the named members. .global . 2010 .global . When declared at module scope.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. .

global . 0.0}. vector variables are aligned to a multiple of their overall size (vector length times base-type size).v4 . 5. Examples: . and Variables 5.v4 . Vectors cannot exceed 128-bits in length.reg . .b8 v.s32 i. 0. . Types. Variable Declarations All storage for data is specified with variable declarations. where the fourth element provides padding.v2. . // a length-2 vector of unsigned ints .u32 loc. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . etc. q.f32 bias[] = {-1. . an optional initializer. PTX supports types for simple aggregate objects such as vectors and arrays.f64 is not allowed. Every variable must reside in one of the state spaces enumerated in the previous section. Vectors must be based on a fundamental type.reg . Examples: . and they may reside in the register space.f32 V. 0}. and an optional fixed address for the variable.reg .v4. This is a common case for three-dimensional grids. In addition to fundamental types.global .Chapter 5.0.4.1.4.struct float4 { .v3 }. Three-element vectors may be handled by using a .2. . // typedef . 1.f32 v0.u8 bg[4] = {0. January 24.f32 accel.global .shared . Predicate variables may only be declared in the register state space.struct float4 coord.const . State Spaces. .v4 vector. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. A variable declaration names the space in which the variable resides. its type and size.v4. .v2 or . Variables In PTX.global . // a length-4 vector of floats . an optional array size. r.v2 . 5. // a length-4 vector of bytes By default.pred p.global . textures. Vectors Limited-length vector types are supported.v4 . its name. 2010 37 .u16 uv. a variable declaration describes both the variable’s type and its state space.4. for example.v1.

PTX ISA Version 2.05.global . . {0.b32 ptr = rgba.u8 rgba[3] = {{1.f16 and . Examples: . . Here are some examples: .shared .s32 offset[][] = { {-1.0.u8 mailbox[128].u16 kernel[19][19].0.05.3.u64. To declare an array.global . Array Declarations Array declarations are provided to allow the programmer to reserve space.global . {0. The size of the dimension is either a constant expression.1. Initializers are allowed for all types except .0.1. // address of rgba into ptr Currently. 19*19 (361) halfwords are reserved (722 bytes)..05}.1. A scalar takes a single value. Variables that hold addresses of variables or instructions should be of type .f32 blur_kernel[][] = {{.s32 n = 10. or is left empty.global .global . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).4.4.. 38 January 24.. where the variable name is followed by an equals sign and the initial value or values for the variable. variable initialization is supported only for constant and global state spaces.. .0. 0}. 5. this can be used to initialize a jump table to be used with indirect branches or calls.u32 or .4. .1. {0.05}}.v4 .1}. 0}. .0}. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.0 5. this can be used to statically initialize a pointer to a variable..{. {0. The size of the array specifies how many elements should be reserved. -1}.local . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. being determined by an array initializer. 2010 .pred.. 1} }. For the kernel declaration above. label names appearing in initializers represent the address of the next instruction following the label. Similarly.{.0}.1. {1. Variable names appearing in initializers represent the address of the variable.4.0}}.

0. Elements are bytes. Types. Examples: // allocate array at 4-byte aligned address..0. // declare %r0.align byte-count specifier immediately following the state-space specifier. 2010 39 . not for individual elements. Array variables cannot be declared this way. %r99. The default alignment for vector variables is to a multiple of the overall vector size. . State Spaces. %r1.b8 bar[8] = {0. and may be preceded by an alignment specifier.b32 variables. and Variables 5.0... The variable will be aligned to an address which is an integer multiple of byte-count.4. say one hundred.const .4.Chapter 5. nor are initializers permitted. .align 4 .2. The default alignment for scalar and array variables is to a multiple of the base-type size. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. …. suppose a program uses a large number. January 24. These 100 register variables can be declared as follows: . Alignment is specified using an optional . Parameterized Variable Names Since PTX supports virtual registers. %r1. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.0}. For example. alignment specifies the address alignment for the starting address of the entire array. 5.6. named %r0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. it is quite common for a compiler frontend to generate a large number of register names. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.b32 %r<100>. For arrays.0.5. Rather than require explicit declaration of every name. of .0.reg .

0 40 January 24. 2010 .PTX ISA Version 2.

6. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. and c. 2010 41 . The result operand is a scalar or vector variable in the register state space. Each operand type must be compatible with the type determined by the instruction template and instruction type. PTX describes a load-store machine. Most instructions have an optional predicate guard that controls conditional execution. The bit-size type is compatible with every type having the same size. . Instructions ld and st move data from/to addressable state spaces to/from registers. the sizes of the operands must be consistent. Source Operands The source operands are denoted in the instruction descriptions by the names a. q. 6. Integer types of a common size are compatible with each other. January 24. mov.3. s. Predicate operands are denoted by the names p. There is no automatic conversion between types. For most operations. so operands for ALU instructions must all be in variables declared in the .1. and cvt instructions copy data from one location to another. r. Operand Type Information All operands in instructions have a known type from their declarations.Chapter 6. The ld. and a few instructions have additional predicate source operands.reg register state space. as its job is to convert from nearly any data type to any other data type (and size).2. Instruction Operands 6. b. The mov instruction copies data between registers. st. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. The cvt (convert) instruction takes a variety of operand types and sizes.

Here are a few examples: . The interesting capabilities begin with addresses.u16 x. [tbl+12]. . address register plus byte offset.f32 ld. there is no support for C-style pointer arithmetic. Load and store operations move data between registers and locations in addressable state spaces.s32 tbl[256].reg .s32 mov. Examples include pointer arithmetic and pointer comparisons.f32 V.1. and Vectors Using scalar variables as operands is straightforward.4. [V]. r0.[x].const. .f32 W.gloal. . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.u16 ld. q. The syntax is similar to that used in many assembly languages.s32 q.reg . and immediate address expressions which evaluate at compile-time to a constant address.u16 r0. .v4. p.reg .4. .global .reg .PTX ISA Version 2. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. and vectors.const . address registers. . Address expressions include variable names. Using Addresses. All addresses and address computations are byte-based.b32 p. tbl. W. The mov instruction can be used to move the address of a variable into a pointer.shared . Arrays. The address is an offset in the state space in which the variable is declared.0 6.shared.u32 42 January 24. 2010 . 6. ld.v4 .v4 . arrays.

Examples are ld.v4 . a register variable. or a braceenclosed list of similarly typed scalars. . .reg .y V.x V. .u32 s.v4. Here are examples: ld. Instruction Operands 6. d. The registers in the load/store operations can be a vector.4.global.w.f32 {a. . Rd}. Vectors may also be passed as arguments to called functions.reg . a[0]. V2.global. a[1]. which may improve memory performance. A brace-enclosed list is used for pattern matching to pull apart vectors.f32 ld.a 6.2. The size of the array is a constant in the program. Rc. a[N-1]. Vector loads and stores can be used to implement wide loads and stores.global. Arrays as Operands Arrays of all types can be declared. where the offset is a constant expression that is either added or subtracted from a register variable.b and .global.4. The expression within square brackets is either a constant integer. it must be written as an address calculation prior to use. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.g V. c. January 24.v2. b. Vector elements can be extracted from the vector with the suffixes .b V.x. which include mov. and the identifier becomes an address constant in the space where the array is declared. mov. or a simple “register with constant offset” expression.f32 V. as well as the typical color fields .u32 {a.c. Rb.a. say {Ra. // move address of a[1] into s 6. and in move instructions to get the address of the label or function into a register. st.z and .z V.b. V.v4.4. Elements in a brace-enclosed vector.Chapter 6.f32 a. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. and tex. mov.4.d}.3.d}. ld.b. Vectors as Operands Vector operands are supported by a limited subset of instructions.g. ld.r. [addr+offset2]. If more complicated indexing is desired. .r V.w = = = = V. for use in an indirect branch or call.c. [addr+offset]. or by indexing into the array using square-bracket notation. 2010 43 . Array elements can be accessed using an explicitly calculated byte address.u32 s. .y.u32 s.

Operands of different sizes or types must be converted prior to the operation. logic. For example.1.s32. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 2010 .5.u16 instruction is given a u16 source operand and s32 as a destination operand.PTX ISA Version 2. 44 January 24. except for operations where changing the size and/or type is part of the definition of the instruction.0 6.5. if a cvt.000 for f16). and data movement instruction must be of the same type and size. Type Conversion All operands to all arithmetic. the u16 is zero-extended to s32. 6. and ~131.

cvt. For example. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.s16. January 24. s2f = signed-to-float. Instruction Operands Table 11. f2s = float-to-signed. 2010 45 . the result is extended to the destination register width after chopping. zext = zero-extend. u2f = unsigned-to-float. f2u = float-to-unsigned. f2f = float-to-float. then sign-extend to 32-bits. chop = keep only low bits that fit. Notes 1 If the destination register is wider than the destination format.Chapter 6.u32 targeting a 32-bit register will first chop to 16-bits. The type of extension (sign or zero) is based on the destination format.

rz . The following tables summarize the rounding modifiers. choosing even integer if source is equidistant between two integers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rm .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.2. Rounding Modifiers Conversion instructions may specify a rounding modifier. 2010 . Modifier . In PTX.5. there are four integer rounding modifiers and four floating-point rounding modifiers.rzi .rmi .0 6. Table 12. Modifier .rn .rpi Integer Rounding Modifiers Description round to nearest integer.rni .PTX ISA Version 2.

while global memory is slowest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Table 14. Another way to hide latency is to issue the load instructions as early as possible. Registers are fastest. Operand Costs Operands from different state spaces affect the speed of an operation. Much of the delay to memory can be hidden in a number of ways. The register in a store operation is available much more quickly. Instruction Operands 6. 2010 47 . Table 11 gives estimates of the costs of using different kinds of memory. first access is high Notes January 24.Chapter 6.6.

0 48 January 24.PTX ISA Version 2. 2010 .

These include syntax for function definitions. At the call. and an optional list of input parameters. The simplest function has no parameters or return values. 2010 49 . or prototype. function calls. and is represented in PTX as follows: . so recursion is not yet supported. January 24. NOTE: The current version of PTX does not implement the underlying. Execution of the ret instruction within foo transfers control to the instruction following the call. implicitly saving the return address. stack-based ABI. and Application Binary Interface (ABI). In this section. A function must be declared or defined prior to being called. 7. support for variadic functions (“varargs”).func foo { … ret. and return values may be placed directly into register variables. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. together these specify the function’s interface.1. execution of the call instruction transfers control to foo. Function declarations and definitions In PTX. arguments may be register variables or constants. Scalar and vector base-type input and return parameters may be represented simply as register variables. A function declaration specifies an optional list of return parameters.Chapter 7. } … call foo. and memory allocated on the stack (“alloca”). functions are declared and defined using the . … Here. A function definition specifies both the interface and the body of the function. parameter passing. Abstracting the ABI Rather than expose details of a particular calling convention. we describe the features of PTX needed to achieve this hiding of the ABI.func directive. the function name. stack layout. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations.

ld.c2. %rd.b8 [py+ 9]. . The .param.param space call (%out). [y+10]. // scalar args in .param .u32 %ptr. ld. %ptr.func (. char c[4].param space memory. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . .PTX ISA Version 2. this structure will be flattened into a byte array. ret.u32 %res.align 8 py[12]. … In this example.b8 c3.param.param.param state space is used to pass the structure by value: . Since memory accesses are required to be aligned to a multiple of the access size.reg space. … ld. inc_ptr.b8 c1.param.f64 f1.0 Example: .s32 x. } { . py).param.reg . st. c2. For example. (%r1. In PTX.b8 .b8 [py+ 8].b64 [py+ 0]. Second.align 8 y[12]) { .param.u32 %inc ) { add.u32 %res) inc_ptr ( . consider the following C structure.c3. ld. %rc1. st. note that . st. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. a . byte array in . %rc1.c1. [y+11].reg . %inc.param . }.f1. a .param. %rc2. [y+8]. } … call (%r1). … … // computation using x. … st.reg .b8 .b8 c2.f64 field are aligned.reg .param.s32 out) bar (.reg .c4.reg . %rc2. passed by value to a function: struct { double dbl. 2010 . First.f64 f1.b32 c1. [y+0].param.param.b8 [py+10].param variable y is used in function definition bar to represent a formal parameter. [y+9]. ld. c3.b8 [py+11].4). c4. st.b8 c4.func (.reg .param space variables are used in two ways. (%x. bumpptr. 50 January 24.

Supporting the .param or . • • • For a callee.param variables.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param and ld.Chapter 7. and alignment. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param state space is used to receive parameter values and/or pass return values back to the caller.reg variables.reg variables.param argument must be declared within the local scope of the caller. the argument must also be a .param state space is used to set values that will passed to a called function and/or to receive return values from a called function.g. or a constant that can be represented in the type of the formal parameter. The . • The . Parameters in . • • • Input and return parameters may be . or a constant that can be represented in the type of the formal parameter.param space formal parameters that are byte arrays. The . .reg space variable with matching type and size. The following restrictions apply to parameter passing.param memory must be aligned to a multiple of 1.param or . a . or constants. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. Typically. all st. and alignment of parameters. For a caller.reg state space in this way provides legacy support. the corresponding argument may be either a .param variables or .reg state space can be used to receive and return base-type scalar and vector values.reg space formal parameters. 2. size. size. For .reg space variable of matching type and size.. This enables backend optimization and ensures that the . 2010 51 . Note that the choice of . • The . In the case of . 4. For a callee. the corresponding argument may be either a . • • Arguments may be .param arguments.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param space byte array with matching type. January 24.param space formal parameters that are base-type scalar or vector variables.param instructions used for argument passing must be contained in the basic block with the call instruction. Abstracting the ABI The following is a conceptual way to think about the . In the case of . A . For a caller. or 16 bytes. In the case of .param state space use in device functions.reg or .param byte array is used to collect together fields of a structure being passed by value.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. 8.

0 continues to support multiple return registers for sm_1x targets. formal parameters were restricted to . Objects such as C structures were flattened and passed or returned using multiple registers. Changes from PTX 1.0 7.param space parameters support arrays.reg or . 52 January 24. and a . and there was no support for array parameters. In PTX ISA version 2. PTX 2.PTX ISA Version 2.0.param state space. PTX 1. formal parameters may be in either .1. For sm_2x targets.param byte array should be used to return objects that do not fit into a register. and .1.x supports multiple return values for this purpose.reg state space.x.0 restricts functions to a single return value.x In PTX ISA version 1. 2010 . PTX 2.

In PTX. Variadic functions NOTE: The current version of PTX does not support variadic functions. the alignment may be 1.reg .b64 val) %va_arg64 (. ctr.reg . 2.reg . (ap). This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg . // default to MININT mov. . iteratively access. setp. call (val).reg . 0x8000000.u32 a.func ( .reg . the size may be 1.func %va_end (. The function prototypes are defined as follows: . or 16 bytes. … ) . Abstracting the ABI 7. %va_start. In both cases.reg . maxN. %va_end is called to free the variable argument list handle.func okay ( … ) Built-in functions are provided to initialize.2. %s2). .u32 ptr.u32 N.reg .pred p. maxN. . %s1. ctr. . %r1.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . 4). … %va_start returns Loop: @p Done: January 24. (ap.u32 ptr.u32 align) . following zero or more fixed parameters: .reg . call %va_end. call (ap).Chapter 7..reg .u32 sz.reg .h headers in C.reg . N. . 8.reg .s32 result ) maxN ( ..b32 val) %va_arg (. bra Loop.func (. 2.ge p. 4. . … call (%max).u32 b.s32 result. For %va_arg.reg . ) { .func baz ( . 4.func (. 2.reg . . (2. mov.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. To support functions with a variable number of arguments.u32. along with the size and alignment of the next data value to be accessed. or 4 bytes.u32 ap.u32 sz. val. %va_arg.u32 ptr) %va_start .reg . or 8 bytes. and end access to a list of variable arguments. variadic functions are declared with an ellipsis at the end of the input parameter list. max. 0. PTX provides a high-level mechanism similar to the one provided by the stdarg.s32 val. %r3). 4.b32 ctr. Once all arguments have been processed. bra Done. ret. 2010 53 . .u32 align) . the size may be 1. } … call (%max).b32 result. (3. for %va_arg64. result.func (. %r2.h and varargs.

PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( .reg . defined as follows: . 2010 .u32 ptr ) %alloca ( .reg . If a particular alignment is required.local instructions.3. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.PTX ISA Version 2. The array is then accessed with ld. Alloca NOTE: The current version of PTX does not support alloca. a function simply calls the built-in function %alloca.0 7. 54 January 24.local and st. To allocate memory.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.

In addition to the name and the format of the instruction.2. the D operand is the destination operand. opcode D. For some instructions the destination operand is optional. A. the semantics are described. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.s32. a.lt p|q. January 24. // p = (a < b). Instruction Set 8. 2010 55 .Chapter 8. 8. A. followed by some examples that attempt to show several possible instantiations of the instruction. For instructions that create a result value. We use a ‘|’ symbol to separate multiple destination registers. opcode A. C. b. opcode D.1. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. B. PTX Instructions PTX instructions generally have from zero to four operands. The setp instruction writes two destination registers. B. and C are the source operands. B. A. while A. setp. q = !(a < b).

1. consider the high-level code if (i < n) j = j + 1. predicate registers can be declared as .s32 p.lt. i.s32 j. branch over 56 January 24. add.PTX ISA Version 2. 1. i.pred p.reg . j. To implement the above example as a true conditional branch. j. n. use a predicate to control the execution of the branch or call instructions. As an example. Instructions without a guard predicate are executed unconditionally. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. 2010 . So. Predicates are most commonly set as the result of a comparison performed by the setp instruction. … // compare i to n // if false. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. the following PTX instruction sequence might be used: @!p L1: setp.lt. // p = (i < n) // if i < n. q. n.s32 j.s32 p. Predicated Execution In PTX. add 1 to j To get a conditional branch or conditional function call.0 8. This can be written in PTX as @p setp.3. add. where p is a predicate variable. predicate registers are virtual and have . bra L1. optionally negated.pred as the type specifier.

ne (not-equal).1. lt.1. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. The bit-size comparisons are eq and ne. If either operand is NaN. Instruction Set 8. ne.Chapter 8. The following table shows the operators for signed integer. and ge (greater-than-or-equal). Table 15. gt (greater-than). le. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. and bitsize types.3.3. Table 16. ge. le (less-than-or-equal). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ordering comparisons are not defined for bit-size types.2. 2010 57 . The unsigned comparisons are eq. ls (lower-or-same). ne. gt. Unsigned Integer. lo (lower). lt (less-than). the result is false.1. unsigned integer. hi (higher). and hs (higher-or-same). Comparisons 8. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.1.3.

leu. then these comparisons have the same result as their ordered counterparts. 2010 . Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.0. setp can be used to generate a predicate from an integer. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. ltu. and no direct way to load or store predicate register values. gtu. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. unordered versions are included: equ. However. then the result of these comparisons is true.0 To aid comparison operations in the presence of NaN values.u32 %r1. for example: selp. If either operand is NaN. or. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. geu.3. If both operands are numeric values (not NaN). num returns true if both operands are numeric values (not NaN).2. two operators num (numeric) and nan (isNaN) are provided. Table 18.1. neu. xor. // convert predicate to 32-bit value 58 January 24. Table 17. not.%p.PTX ISA Version 2. and nan returns true if either operand is NaN. and mov. There is no direct conversion between predicates and integer values.

It requires separate type-size modifiers for the result and source. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. unsigned. . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. different sizes). For example. and integer operands are silently cast to the instruction type if needed. most notably the data conversion instruction cvt. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.sX ok ok ok inv .u16 d. and this information must be specified as a suffix to the opcode. float.reg ..sX .bX . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. i. For example. the add instruction requires type and size information to properly perform the addition operation (signed. b. For example: .4. 2010 59 . cvt. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.uX . Signed and unsigned integer types agree provided they have the same size.fX ok ok ok ok January 24.reg . and these are placed in the same order as the operands. Floating-point types agree only if they have the same size. • The following table summarizes these type checking rules.u16 d. Instruction Set 8. Example: . a.reg .u16 a.e.Chapter 8.bX .u16 d. b.f32 d. a. Type Checking Rules Operand Type . they must match exactly. add. a. Table 19.f32.uX ok ok ok inv .fX ok inv inv ok Instruction Type .

Source register size must be of equal or greater size than the instruction-type size. the size must match exactly. For example. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. Bit-size source registers may be used with any appropriately-sized instruction type. 1. so that narrow values may be loaded. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. 4. for example. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. The data is truncated to the instruction-type size and interpreted according to the instruction type. When a source operand has a size that exceeds the instruction-type size.0 8. Floating-point source registers can only be used with bit-size or floating-point instruction types. Notes 3. inv = invalid. The following table summarizes the relaxed type-checking rules for source operands. or converted to other types and sizes. unless the operand is of bit-size type. ld. 60 January 24. 2. and converted using regular-width registers. the cvt instruction does not support .1. the data will be truncated. When used with a floating-point instruction type. st. 2010 . floating-point instruction types still require that the operand type-size matches exactly.4. “-“ = allowed. Table 20. so those rows are invalid for cvt. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. no conversion needed. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Operand Size Exceeding Instruction-Type Size For convenience. Note that some combinations may still be invalid for a particular instruction. parse error. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. When used with a narrower bit-size type. stored. stored.PTX ISA Version 2. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.bX instruction types.

If the corresponding instruction type is signed integer. Floating-point destination registers can only be used with bit-size or floating-point instruction types.or sign-extended to the size of the destination register. the destination data is zero. The following table summarizes the relaxed type-checking rules for destination operands. January 24. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. parse error. 2. Bit-size destination registers may be used with any appropriately-sized instruction type. 2010 61 . the size must match exactly. the data will be zero-extended. the data is zeroextended. 1. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. zext = zero-extend. “-“ = Allowed but no conversion needed. The data is signextended to the destination register width for signed integer instruction types. When used with a floatingpoint instruction type. Table 21. When used with a narrower bit-size instruction type. 4. otherwise. Notes 3. and is zero-extended to the destination register width otherwise. The data is sign-extended to the destination register width for signed integer instruction types. Instruction Set When a destination operand has a size that exceeds the instruction-type size. inv = Invalid. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type.Chapter 8. Destination register size must be of equal or greater size than the instruction-type size. the data is sign-extended.

This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. a compiler or code author targeting PTX can ignore the issue of divergent threads. the semantics of 16-bit instructions in PTX is machine-specific.1. Therefore. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. Both situations occur often in programs. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. this is not desirable. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. However. 8. the optimizing code generator automatically determines points of re-convergence. 2010 . The semantics are described using C.6. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.6. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. conditional function call. for many performance-critical applications. 62 January 24. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. so it is important to have divergent threads re-converge as soon as possible. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. These extra precision bits can become visible at the application level. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. until they come to a conditional control construct such as a conditional branch. When executing on a 32-bit data path. For divergent control flow. at least in appearance.uni suffix. or conditional return. using the . Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. At the PTX language level. 8. If threads execute down different control flow paths. Divergence of Threads in Control Constructs Threads in a CTA execute together. and 16-bit computations are “promoted” to 32-bit computations.PTX ISA Version 2. until C is not expressive enough. and for many applications the difference in execution is preferable to limiting performance. If all of the threads act in unison and follow a single control flow path. A compiler or programmer may chose to enforce portable. for example. the threads are called divergent. 16-bit registers in PTX are mapped to 32-bit physical registers.5. by a right-shift instruction.0 8. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. the threads are called uniform.

subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. The Integer arithmetic instructions are: add sub add. 2010 63 .1.7. 8. In the following descriptions. Instruction Set 8.Chapter 8. Instructions All PTX instructions may be predicated. addc sub.cc. the optional guard predicate is omitted from the syntax.cc.

s32 c. Saturation modifier: . // . d = a – b.MAXINT (no overflow) for the size of the operation.sat applies only to . Introduced in PTX ISA version 1. // .MAXINT (no overflow) for the size of the operation.sat}.u64. . sub.s64 }. b. b.type add{.sat limits result to MININT. d = a + b.type sub{. a. PTX ISA Notes Target ISA Notes Examples Table 23.0 Table 22.PTX ISA Version 2. b. d.u32. .0. .a.s16.s32 . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. @p add. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.sat limits result to MININT.u32 x. . .sat}. .s32 . sub.u16.. Introduced in PTX ISA version 1.u64. PTX ISA Notes Target ISA Notes Examples 64 January 24. a.u32.z. .0.1. Supported on all target architectures.c. add.s32.sat. Supported on all target architectures.s32 d.s16. 2010 . a. .u16. Applies only to . Applies only to . d. Saturation modifier: .type = { .b.s32 type.s64 }. a. .s32. add Syntax Integer Arithmetic Instructions: add Add two values. b.s32 c.s32 d.s32 type..type = { .y. add.sat applies only to . Description Semantics Notes Performs addition and writes the resulting value into a destination register.

b. d = a + b. add.z2. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. Supported on all target architectures. These instructions support extended-precision integer addition and subtraction. No other instructions access the condition code. add.y3. Instruction Set Instructions add.cc Add two values with carry-out. . Table 24.z1.CF) holding carry-in/carry-out or borrowin/borrow-out. d = a + b + CC. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.type d.CF No integer rounding modifiers. No saturation. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc.cc. sub. a.y1. x4. x2.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.b32 addc. .Chapter 8.2.z4.s32 }. No saturation. b. .z3.s32 }.b32 addc.b32 x1. clearing. a.b32 addc. and there is no support for setting.type d. @p @p @p @p add.u32.cc.CF. Behavior is the same for unsigned and signed integers. x2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.b32 addc.z3.cc.y2. 2010 65 .cc specified.y3.z1.2. if .type = {. x4. carry-out written to CC.cc. .b32 addc. addc. Behavior is the same for unsigned and signed integers.cc}.CF No integer rounding modifiers.b32 x1.cc Syntax Integer Arithmetic Instructions: add. carry-out written to CC. @p @p @p @p add. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.cc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y2.z4.cc. Introduced in PTX ISA version 1.cc. x3. Introduced in PTX ISA version 1.y4. or testing the condition code.type = { .b32 addc. x3. Supported on all target architectures.cc.u32.y4. addc{.z2.y1.cc.

Supported on all target architectures. sub.y1. d = a – b.b32 subc.CF No integer rounding modifiers.type = {. x2.u32. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.z1. x3. x4.b32 subc.y3. b. subc{.cc.cc Syntax Integer Arithmetic Instructions: sub. . // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.s32 }. Introduced in PTX ISA version 1. a.cc Subract one value from another. with borrow-out. d = a .z1. x2. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. .(b + CC. No saturation.cc. .cc.cc.y3. .y2.z2.z3.PTX ISA Version 2.3.b32 subc. b.type = { . x3.z4. Behavior is the same for unsigned and signed integers.u32.b32 subc.cc. Behavior is the same for unsigned and signed integers.z3. 2010 .s32 }.b32 subc. x4.cc specified. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.y1. borrow-out written to CC. Supported on all target architectures.z4.0 Table 26.z2.cc.type d.3. borrow-out written to CC.cc. withborrow-in and optional borrow-out. @p @p @p @p sub. No saturation. @p @p @p @p sub.CF No integer rounding modifiers.CF).type d.y4.y2.cc}.b32 x1.b32 subc.y4. if .b32 x1.cc. Introduced in PTX ISA version 1. a.cc. sub.

. ..Chapter 8. Description Semantics Compute the product of two values..type = { . d = t<2n-1.x.fxs. .lo.type d. Supported on all target architectures. .hi.fys.wide // for .u32.. d = t.lo.s32 z.s32. mul{.wide}. and either the upper or lower half of the result is written to the destination register. .and 32-bit integer types.s64 }. . d = t<n-1. a. then d is the same size as a and b. mul. mul. 2010 67 . The .y.u64.wide. n = bitwidth of type.u16.s16 fa.hi variant // for .lo is specified.n>. If . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.wide is specified.s16 fa. save only the low 16 bits // 32*32 bits.fxs.0>. t = a * b. // 16*16 bits yields 32 bits // 16*16 bits. If .s16. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide. Instruction Set Table 28. mul.lo variant Notes The type of the operation represents the types of the a and b operands.fys.0. // for .wide suffix is supported only for 16. creates 64 bit result January 24. then d is twice as wide as a and b to receive the full result of the multiplication. b.hi or . .

hi variant // for . b.lo. 2010 . t<n-1. If . t<2n-1. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.type = { .u64.hi or .sat.lo. .q. . a. .lo variant Notes The type of the operation represents the types of the a and b operands. . .hi mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide suffix is supported only for 16. d.lo is specified.s32 r. c. mad.type mad. mad{. a. // for .r. Saturation modifier: .s32 d.sat limits result to MININT.a. Supported on all target architectures.MAXINT (no overflow) for the size of the operation.PTX ISA Version 2.hi.s16.s32 type in ..s64 }.n> + c. and then writes the resulting value into a destination register.lo.0> + c. t n d d d = = = = = a * b.s32 d.0.c. . t + c.b.0 Table 29.hi. Applies only to ..p.wide}.and 32-bit integer types.wide // for . then d and c are the same size as a and b. Description Semantics Multiplies two values and adds a third. If . then d and c are twice as wide as a and b to receive the result of the multiplication.s32. b.u32. c.wide is specified..u16. 68 January 24. and either the upper or lower half of the result is written to the destination register. @p mad. bitwidth of type. The ...

s32 d.u32. // low 32-bits of 24x24-bit signed multiply.. . a. Instruction Set Table 30. 2010 69 . .s32 }. mul24. mul24. b. mul24. // for .hi variant // for .type = { . All operands are of the same type and size.b. d = t<47.lo}.0>. January 24.0.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.hi.16>. t = a * b.Chapter 8.a.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. and return either the high or low 32-bits of the 48-bit result.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.lo. Supported on all target architectures. mul24{. 48bits. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. d = t<31. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type d. mul24.hi may be less efficient on machines without hardware support for 24-bit multiply.e.. i.

a.16> + c. b. b.. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. t = a * b. mad24. Description Compute the product of two 24-bit integer values held in 32-bit source registers. All operands are of the same type and size.s32 }. mad24. .0> + c.type = { . 48bits. d = t<47. .. mad24.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. Applies only to . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type mad24. Saturation modifier: . 32-bit value to either the high or low 32-bits of the 48-bit result. Return either the high or low 32-bits of the 48-bit result.c.sat limits result of 32-bit signed addition to MININT. mad24{.s32 d.a. // for .hi may be less efficient on machines without hardware support for 24-bit multiply.s32 d.MAXINT (no overflow).s32 type in .e. d.lo}.sat. Supported on all target architectures.0. 2010 .lo. i.hi variant // for .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. a. mad24.. 70 January 24.0 Table 31.u32. and add a third. // low 32-bits of 24x24-bit signed multiply.b.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. c.PTX ISA Version 2.hi mode. c.hi.hi. d = t<31..

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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a. clz. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. popc.b64 }. For . d = 0.b32) { max = 32. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.PTX ISA Version 2. mask = 0x8000000000000000.b64 d. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. . d = 0.0 Table 39.b32. inclusively. 2010 . . a = a >> 1. the number of leading zeros is between 0 and 64.0. a. // cnt is . cnt.b32.type = { . popc Syntax Integer Arithmetic Instructions: popc Population count.type = { .b64 }. . cnt.0. } while (d < max && (a&mask == 0) ) { d++.u32 PTX ISA Notes Target ISA Notes Examples Table 40. // cnt is . clz requires sm_20 or later.type d.b64 d.type d. .b32 clz. X. popc.b32 type. a.u32 Semantics 74 January 24. the number of leading zeros is between 0 and 32.b64 type. } Introduced in PTX ISA version 2. For . a = a << 1.b32 popc. while (a != 0) { if (a&0x1) d++. X. mask = 0x80000000. } else { max = 64. clz. popc requires sm_20 or later. if (.type == . Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. inclusively. a.

bfind. a. .type==. bfind.0.u32 d. For signed integers. Operand a has the instruction type. For unsigned integers.s64 }.s32) ? 31 : 63. d. 2010 75 . i--) { if (a & (1<<i)) { d = i. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. and operand d has type .shiftamt. . Instruction Set Table 41.shiftamt is specified.u64.shiftamt && d != -1) { d = msb . .Chapter 8.u32. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.s64 cnt. bfind requires sm_20 or later. a. If . d = -1.d.type bfind. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shiftamt.type==.type d. } } if (. // cnt is . for (i=msb. a.s32.u32 January 24. X. bfind returns 0xFFFFFFFF if no non-sign bit is found.u32 || . break. Semantics msb = (. Description Find the bit position of the most significant non-sign bit in a and place the result in d. . bfind.type = { . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. i>=0. bfind returns the bit position of the most significant “1”.u32.

i<=msb.PTX ISA Version 2. 76 January 24.0 Table 42.type==. for (i=0. brev.b32) ? 31 : 63. a.type d.b32 d. brev.b64 }. .b32. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. Description Semantics Perform bitwise reversal of input. a. brev requires sm_20 or later. . 2010 . msb = (. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { . i++) { d[i] = a[msb-i].0.

2010 77 . b.type d. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. .u32. bfe. len = c.s32.u32.u32.type==.start. . i<=msb. . Operands a and d have the same type as the instruction type.s32) ? 31 : 63. and source c gives the bit field length in bits.s32. d = 0.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If the start position is beyond the msb of the input.type==.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. The sign bit of the extracted field is defined as: .u64: .u32 || .type==. .u64. Semantics msb = (.u64 || len==0) sbit = 0. Source b gives the bit field starting bit position.len. bfe. Instruction Set Table 43. January 24.0. c. pos = b.s64 }.msb)]. else sbit = a[min(pos+len-1. otherwise If the bit field length is zero. Description Extract bit field from a and place the zero or sign-extended result in d. if (. for (i=0.a. .Chapter 8. the result is zero.u32 || . bfe requires sm_20 or later.type = { . bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. the destination d is filled with the replicated sign bit of the extracted field. . a. and operands b and c are type .b32 d. The destination d is padded with the sign bit of the extracted field.

b.type==.0 Table 44.start. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i<len && pos+i<=msb.b64 }.b. len = d. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. and operands c and d are type .0. b.type f. 2010 .PTX ISA Version 2. f = b. . and place the result in f. Source c gives the starting bit position for the insertion. a.len. bfi. d. Semantics msb = (. for (i=0. If the bit field length is zero. the result is b. and source d gives the bit field length in bits.u32. 78 January 24. c. .b32.type = { . and f have the same type as the instruction type. Description Align and insert a bit field from a into b. i++) { f[pos+i] = a[i].b32 d. pos = c. bfi. bfi requires sm_20 or later. If the start position is beyond the msb of the input. the result is b.a. Operands a.b32) ? 31 : 63.

b4e. default mode index d. b2.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. c.f4e.b2 source select c[11:8] d.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. the four 4-bit values fully specify an arbitrary byte permute. Description Pick four arbitrary bytes from two 32-bit registers. . The bytes in the two source registers are numbered from 0 to 7: {b. In the generic form (no mode specified). .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. b1. msb=1 means replicate the sign. a. b4}.ecl. Note that the sign extension is only performed as part of generic form. The msb defines if the byte value should be copied.b32{. b0}}.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.rc8. . and reassemble them into a 32-bit destination register.mode = { . msb=0 means copy the literal value.b1 source select c[7:4] d. prmt.rc16 }. {b3.ecr. b6. 2010 79 . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).mode} d. For each byte in the target register. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b. a} = {{b7. the permute control consists of four 4-bit selection values. . Thus. . . as a 16b permute code. Instruction Set Table 45.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.Chapter 8. b5.b3 source select c[15:12] d. a 4-bit selection value is defined.

b32. r2.b32 prmt. tmp[31:24] = ReadByte( mode. prmt requires sm_20 or later. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[2] = (c >> 8) & 0xf. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r3. 80 January 24. ctl[2].f4e r1. r2. tmp[15:08] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp64 ). ctl[0]. 2010 . tmp[23:16] = ReadByte( mode. tmp64 ). tmp64 ).PTX ISA Version 2. r4. r3. ctl[3].0. ctl[1] = (c >> 4) & 0xf. tmp64 ). prmt. ctl[1]. ctl[3] = (c >> 12) & 0xf. r4. } tmp[07:00] = ReadByte( mode. r1.0 Semantics tmp64 = (b<<32) | a.

f64 register operands and constant immediate values.f32 and . Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on .2.7.Chapter 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .

sqrt}. but single-precision instructions return an unspecified NaN.0. If no rounding modifier is specified.f64 rsqrt.fma}. and mad support saturation of results to the range [0. The optional .rm .f32 {abs. 2010 .rnd.mul}. NaN payloads are supported for double-precision instructions. with NaNs being flushed to positive zero.f32 rsqrt.f64 {sin. 82 January 24.rcp. .target sm_1x No rounding modifier.rn .0].sqrt}. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. 1.f32 . Instruction Summary of Floating-Point Instructions .f64 div.f32 {div.approx. Single-precision add. sub.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.target sm_20 .approx.target sm_20 mad.32 and fma.f32 are the same.f64 and fma.rnd.rn and instructions may be folded into a multiply-add.max}.full.rz .ftz .neg. default is .neg.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.0 The following table summarizes floating-point instructions in PTX.max}.rcp.rnd. {mad.cos.rnd.sqrt}.f32 {add. Note that future implementations may support NaN payloads for single-precision instructions. Double-precision instructions support subnormal inputs and results.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.fma}.rn and instructions may be folded into a multiply-add.f32 {mad. {add.rnd. mul.mul}. so PTX programs should not rely on the specific single-precision NaNs being generated.rnd.ex2}.PTX ISA Version 2.approx.f64 are the same. Table 46.f64 mad. .f64 {abs.f32 {div.sub.sat Notes If no rounding modifier is specified.min.min.rcp.approx. No rounding modifier.lg2.rp . default is .f32 {div.sub.

0. f0.op p.f64 }.type = { . positive and negative zero are considered normal numbers. C.f32.type . .f32 copysign. 2010 83 . Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.f64 }. copysign. copysign requires sm_20 or later. a. . . Introduced in PTX ISA version 2.op. A. . . .infinite.f64 x. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.normal. copysign. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. testp. Table 48.notanumber testp. testp Syntax Floating-Point Instructions: testp Test floating-point property.normal testp. and return the result as d.finite.notanumber. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f64 isnan.subnormal }.infinite testp. testp.pred = { .notanumber. testp.type = { .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.number. . Instruction Set Table 47. b. January 24. true if the input is a subnormal number (not NaN. z.0. . B.number testp.f32.Chapter 8. X.finite testp. not infinity) As a special case. testp requires sm_20 or later. y.infinite. a. . not infinity).type d. p. // result is .f32 testp.

0.rnd}{.sat. b. sm_1x: add.f32 clamps the result to [0. NaN results are flushed to +0.rn): .rz mantissa LSB rounds towards zero . Rounding modifiers (default is . 1. 2010 .f32. .0.rm mantissa LSB rounds towards negative infinity . add. Saturation modifier: . . requires sm_20 Examples @p add. .f64.f32 supported on all target architectures. a. requires sm_13 for add.rz. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. .rp for add. add{.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 49.f32 flushes subnormal inputs and results to sign-preserving zero.f2. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f64 requires sm_13 or later. add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b.rn. add. .rz available for all targets . An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f3. a. add.rm.0f.ftz.rp }.rnd = { . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. In particular.f64 supports subnormal numbers.rn mantissa LSB rounds to nearest even .f32 add{.0].rn.f32 f1.sat}.ftz. d.rz. subnormal numbers are supported.rnd}. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. Rounding modifiers have the following target requirements: . 84 January 24.PTX ISA Version 2.rm.f64 d. .ftz}{. add Syntax Floating-Point Instructions: add Add two values. d = a + b. add.

subnormal numbers are supported. January 24.a.Chapter 8.f64 supports subnormal numbers. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64 requires sm_13 or later.f64 d.sat.f2.f32 flushes subnormal inputs and results to sign-preserving zero. sub.sat}.ftz. requires sm_20 Examples sub. .rz available for all targets .f32 sub{.rm. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm mantissa LSB rounds towards negative infinity .b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f3. sm_1x: sub.rn. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. .b.rn. Instruction Set Table 50.0. sub. Rounding modifiers have the following target requirements: .rz.f32 clamps the result to [0.f32. requires sm_13 for sub.rn.f32 supported on all target architectures.rp }.rz mantissa LSB rounds towards zero .rnd = { .rnd}. 2010 85 .0f. sub Syntax Floating-Point Instructions: sub Subtract one value from another. .rn): .ftz}{. Rounding modifiers (default is .f32 f1. d. Saturation modifier: sub. 1. a. b. sub. .0].f64.rnd}{. sub.rp for sub. In particular.0. .rm. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f32 c. sub{. sub. d = a . .ftz.rn mantissa LSB rounds to nearest even . a. NaN results are flushed to +0. b.f32 flushes subnormal inputs and results to sign-preserving zero.

b.rn.rn): . Description Semantics Notes Compute the product of two values. mul. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rn mantissa LSB rounds to nearest even .rz available for all targets .radius.rnd}{.sat. a. .pi // a single-precision multiply 86 January 24. Rounding modifiers have the following target requirements: .rp }.0f. requires sm_13 for mul. d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32.rnd}.f32 flushes subnormal inputs and results to sign-preserving zero. 1. .f64. d = a * b. all operands must be the same size. b. Rounding modifiers (default is . a.ftz.PTX ISA Version 2.rz.0 Table 51. mul{. .f64 requires sm_13 or later.sat}.rm.rn.f32 clamps the result to [0.ftz.rp for mul.f32 mul{. In particular. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rm mantissa LSB rounds towards negative infinity . mul. . Saturation modifier: mul.0].f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0.f32 circumf. sm_1x: mul. For floating-point multiplication.0. .ftz}{.f64 supports subnormal numbers. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64 d.f32 supported on all target architectures. . 2010 .rm. mul. mul.rnd = { . NaN results are flushed to +0. mul Syntax Floating-Point Instructions: mul Multiply two values. subnormal numbers are supported.rz mantissa LSB rounds towards zero .

f32 clamps the result to [0. The resulting value is then rounded to double precision using the rounding mode specified by . fma. c.f64 d.b.rn.rnd = { . The resulting value is then rounded to single precision using the rounding mode specified by .f32 flushes subnormal inputs and results to sign-preserving zero. fma. 1.f32 is unimplemented in sm_1x.f32 computes the product of a and b to infinite precision and then adds c to this product.ftz. . Instruction Set Table 52.f64 computes the product of a and b to infinite precision and then adds c to this product.f64 supports subnormal numbers. Rounding modifiers (no default): . d = a*b + c.f32 requires sm_20 or later.Chapter 8.0f.sat}. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add. b. a.rnd.rnd{. fma.rnd. fma.f64. Saturation: fma. @p fma. a. d.rp }.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat. PTX ISA Notes Target ISA Notes Examples January 24. fma. again in infinite precision. fma.4.0. again in infinite precision.f64 introduced in PTX ISA version 1.rn. c.x. subnormal numbers are supported. fma. sm_1x: fma.f32 fma.ftz.z.f32 introduced in PTX ISA version 2. fma. b.c. NaN results are flushed to +0. 2010 87 .f64 requires sm_13 or later.rn. .0].a.rz.f32 fma.0. fma. .rm mantissa LSB rounds towards negative infinity .f64 is the same as mad.rz mantissa LSB rounds towards zero .f64 w.rn mantissa LSB rounds to nearest even .rm. .y. d.ftz}{.rnd. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.

sat}.rm mantissa LSB rounds towards negative infinity .f64} is the same as fma. mad. mad. the treatment of subnormal inputs and output follows IEEE 754 standard. again in infinite precision.PTX ISA Version 2. Rounding modifiers (no default): .0].0 Table 53.ftz.f32 computes the product of a and b at double precision.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. . fma. where the mantissa can be rounded and the exponent will be clamped.rnd. In this case. and then the mantissa is truncated to 23 bits.f32 is implemented as a fused multiply-add (i.e.f32 is when c = +/-0.f32 clamps the result to [0.rn. c.target sm_1x d.{f32.ftz}{.rm. NaN results are flushed to +0. // .f64 is the same as fma.f32.0.f32 mad. The resulting value is then rounded to double precision using the rounding mode specified by . 2010 .f64 computes the product of a and b to infinite precision and then adds c to this product.sat. When JIT-compiled for SM 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat}. mad. again in infinite precision. . again in infinite precision. For . d = a*b + c.rnd. a. and then writes the resulting value into a destination register. sm_1x: mad.ftz}{.rnd. mad.f64 supports subnormal numbers.target sm_20 d.0f.rnd. mad. a. b.{f32.f32). The resulting value is then rounded to double precision using the rounding mode specified by . b. mad.target sm_1x: mad.ftz. Description Semantics Notes Multiplies two values and adds a third. subnormal numbers are supported. // . mad. The resulting value is then rounded to single precision using the rounding mode specified by . The exception for mad. Unlike mad. but the exponent is preserved.rnd{. Saturation modifier: mad.f32 mad.target sm_20: mad. 1..rp }.0. . // . mad.0 devices.rnd = { .target sm_13 and later .f32 flushes subnormal inputs and results to sign-preserving zero. mad{. For .rz. c. 88 January 24.rn.f64}. b. c.f64.rz mantissa LSB rounds towards zero . a. mad.f32 is identical to the result computed using separate mul and add instructions.f64 d.rn mantissa LSB rounds to nearest even .f64 computes the product of a and b to infinite precision and then adds c to this product. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. Note that this is different from computing the product with mul.f32 flushes subnormal inputs and results to sign-preserving zero.f32 computes the product of a and b to infinite precision and then adds c to this product.

c.rm. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. a rounding modifier is required for mad.rn. Target ISA Notes mad.f32. mad..rp for mad.rn.rz. a rounding modifier is required for mad.b. requires sm_20 Examples @p mad.0.0 and later.. 2010 89 . Rounding modifiers have the following target requirements: .f32 supported on all target architectures. requires sm_13 . January 24.f32 d.rz.f64 requires sm_13 or later.f64..rm.. Legacy mad. In PTX ISA versions 1.f64.4 and later. In PTX ISA versions 2..f64.rp for mad.rn.f32 for sm_20 targets.a.Chapter 8.f64 instructions having no rounding modifier will map to mad..

ftz.ftz.full. div.3. a.0 through 1. div. full-range approximation that scales operands to achieve better accuracy. div.f32 div. d = a / b. div.approx.rm.ftz}. . 2126].approx{.ftz.rnd is required. Explicit modifiers .rn. x. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .PTX ISA Version 2.f64 diam. a. div.f64 supports subnormal numbers.rnd. Examples 90 January 24.ftz}. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . computed as d = a * (1/b).approx. For PTX ISA versions 1. b. but is not fully IEEE 754 compliant and does not support rounding modifiers. .3. For b in [2-126. div Syntax Floating-Point Instructions: div Divide one value by another.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 .rnd.rnd = { .ftz.f32 and div.approx.full. one of .full. b.rn.f64 requires sm_20 or later. approximate single-precision divides: div. d.full.ftz}. y.f64.rn.circum. z. stores result in d. a. . and div.approx.4 and later.f32 div. The maximum ulp error is 2 across the full range of inputs.rp }. zd.4.f32.rn mantissa LSB rounds to nearest even . or .f32 requires sm_20 or later. and rounding introduced in PTX ISA version 1.rnd{. div.rp}.f64 introduced in PTX ISA version 1.{rz.rz.f32 implements a fast approximation to divide. // // // // fast. sm_1x: div.f64 d. div. . the maximum ulp error is 2. b.14159.full. .ftz. yd.f32 and div. b. PTX ISA Notes div.f32 div.approx.f64 defaults to div. For PTX ISA version 1. div. d.rz mantissa LSB rounds towards zero . subnormal numbers are supported. . xd.approx.rm mantissa LSB rounds towards negative infinity .rn. Subnormal inputs and results are flushed to sign-preserving zero. Fast.f32 div. Target ISA Notes div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. d.f32 flushes subnormal inputs and results to sign-preserving zero.f32 defaults to div. Fast.f32 supported on all target architectures.rm. div. approximate division by zero creates a value of infinity (with same sign as a).f64 requires sm_13 or later.full{.f32 div.f32 implements a relatively fast.0 Table 54. Description Semantics Notes Divides a by b. a.0.

Chapter 8. neg{. Table 56. Subnormal numbers: sm_20: By default. d.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. a. sm_1x: neg.f32 x. a. NaN inputs yield an unspecified NaN. subnormal numbers are supported. Subnormal numbers: sm_20: By default. Instruction Set Table 55. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. d. Negate the sign of a and store the result in d.f64 requires sm_13 or later.f64 supports subnormal numbers. 2010 91 . a.f32 supported on all target architectures. subnormal numbers are supported.f32 supported on all target architectures.f0.ftz}.f32 neg. Take the absolute value of a and store the result in d. abs.ftz. a.f0.ftz. abs{. neg. d = -a.ftz. neg.f32 x. abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs.f64 supports subnormal numbers.f32 abs.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: abs. neg. January 24. neg. neg.f64 requires sm_13 or later. abs.f32 flushes subnormal inputs and results to sign-preserving zero.0.ftz}. d = |a|. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.0. NaN inputs yield an unspecified NaN.

ftz.f64 z.f64 d. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. subnormal numbers are supported.c. sm_1x: max.f32 flushes subnormal inputs and results to sign-preserving zero. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. (a < b) ? a : b. Table 58. 2010 .f1.ftz}. @p min.b.f64 requires sm_13 or later. b.f64 requires sm_13 or later. max. a.f64 d. a. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. d. b.z. d.ftz.f64 supports subnormal numbers.f64 supports subnormal numbers.0 Table 57. 92 January 24. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. min.f32 supported on all target architectures. (a > b) ? a : b. d d d d = = = = NaN. b.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. b.f32 max.f32 flushes subnormal inputs and results to sign-preserving zero.f32 min. a. min.0. a. max{.PTX ISA Version 2.ftz. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. b. max.f2. min. min{.b. a.c.f32 supported on all target architectures. a. d d d d = = = = NaN. subnormal numbers are supported.0. max. sm_1x: min. Store the maximum of a and b in d.f64 f0.f32 min. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 max. b. max.x.ftz. max. min. Store the minimum of a and b in d.

f64 and explicit modifiers . rcp.rn. rcp.ftz}.x.f32 rcp.f64 defaults to rcp.approx or . rcp. xi.rm.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.rn. d.rnd{.ftz.0.f32 rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rp }.rn.0 over the range 1.f32 rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 requires sm_13 or later. Target ISA Notes rcp. d = 1 / a.ftz. General rounding modifiers were added in PTX ISA version 2. d. . Instruction Set Table 59.approx and .approx.0 -Inf -Inf +Inf +Inf +0.rm.r.f32 supported on all target architectures.approx{.rn mantissa LSB rounds to nearest even . The maximum absolute error is 2-23. a. PTX ISA Notes rcp.f64 introduced in PTX ISA version 1.ftz were introduced in PTX ISA version 1. store result in d.f32 defaults to rcp. For PTX ISA version 1.0 +0. rcp.approx.0.rn.f32 rcp.f64 d.ftz.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .0 +subnormal +Inf NaN Result -0.approx. // fast. xi.approx.rz. rcp. a.3. .rp}. For PTX ISA versions 1.4. 2010 93 . a.x. rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 requires sm_20 or later.0-2.ftz.rz mantissa LSB rounds towards zero .f64 ri.rn.rnd.f32 flushes subnormal inputs and results to sign-preserving zero. Examples January 24. sm_1x: rcp. one of . Input -Inf -subnormal -0.0.rnd. .f32.f32 and rcp.rn.f64.0 through 1. subnormal numbers are supported.f32 requires sm_20 or later. and rcp.4 and later. Description Semantics Notes Compute 1/a.rnd = { .{rz. rcp.ftz}.rm mantissa LSB rounds towards negative infinity .f64 supports subnormal numbers. rcp.rnd is required.f32 implements a fast approximation to reciprocal. rcp.

f32 sqrt.ftz. sqrt. PTX ISA Notes sqrt.rn.f32 sqrt.f32 sqrt.rn. Target ISA Notes sqrt.f64.f32 defaults to sqrt. Examples 94 January 24. sqrt. Description Semantics Notes Compute sqrt(a).4 and later.rnd.approx or . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.0. d = sqrt(a).approx.0 Table 60.x.0. r.rp }.approx{.x. sqrt.rnd is required.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .PTX ISA Version 2. sqrt.0 -0.rm mantissa LSB rounds towards negative infinity .f64 introduced in PTX ISA version 1.f32 sqrt.3. General rounding modifiers were added in PTX ISA version 2.approx. For PTX ISA versions 1.f64 defaults to sqrt.f64 requires sm_13 or later.{rz. approximate square root d.rn.x.rz. // IEEE 754 compliant rounding d.f32 requires sm_20 or later.rm.ftz}. a.approx.approx. // fast.approx. sqrt.rn. 2010 .4. Input -Inf -normal -subnormal -0. // IEEE 754 compliant rounding .ftz. The maximum absolute error for sqrt. sm_1x: sqrt.0 +0. r. a.f32 and sqrt. sqrt.f64 supports subnormal numbers. . one of .f32 flushes subnormal inputs and results to sign-preserving zero. store in d.f32 is TBD. .approx and .rnd.f64 and explicit modifiers .f64 r.rn. and sqrt. For PTX ISA version 1.rn.f32 implements a fast approximation to square root.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd = { .rnd{.rp}. .f64 d.0 through 1. sqrt.f64 requires sm_20 or later.rn mantissa LSB rounds to nearest even .0 +0. sqrt.ftz were introduced in PTX ISA version 1. sqrt.f32 supported on all target architectures. a.f32. subnormal numbers are supported.0 +subnormal +Inf NaN Result NaN NaN -0.0 +0.ftz.ftz}.ftz. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.rm.rz mantissa LSB rounds towards zero .

f32 supported on all target architectures. Compute 1/sqrt(a). 2010 95 . PTX ISA Notes rsqrt.approx.f64 is emulated in software and are relatively slow.f64 were introduced in PTX ISA version 1. Target ISA Notes Examples rsqrt. x. d.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt.4.ftz.f32.0.approx.4 over the range 1.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt.0 NaN The maximum absolute error for rsqrt.Chapter 8. For PTX ISA version 1. d = 1/sqrt(a).f64 requires sm_13 or later.approx. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 through 1. rsqrt. Input -Inf -normal -subnormal -0. Subnormal numbers: sm_20: By default.approx{.approx.f64 isr. store the result in d. January 24.approx. and rsqrt.f32 defaults to rsqrt.approx. For PTX ISA versions 1.ftz were introduced in PTX ISA version 1.f32 is 2-22. the .3. Note that rsqrt.4 and later.f64 supports subnormal numbers.f64 defaults to rsqrt.f32 and rsqrt.0.ftz}.approx and . a.f32 rsqrt. a. rsqrt.f64 is TBD.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. ISR.0 +0.0-4.f64 d. The maximum absolute error for rsqrt. rsqrt.approx modifier is required. subnormal numbers are supported.f64. X. Explicit modifiers . Instruction Set Table 61.approx implements an approximation to the reciprocal square root.f32 rsqrt. rsqrt. rsqrt. sm_1x: rsqrt.ftz.

ftz. sin.approx{.f32. a.f32 defaults to sin. d = sin(a). For PTX ISA versions 1.4 and later. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.0 +subnormal +Inf NaN Result NaN -0.ftz. subnormal numbers are supported.0.9 in quadrant 00.approx.0 NaN NaN The maximum absolute error is 2-20.0 +0. sm_1x: Subnormal inputs and results to sign-preserving zero. sin.ftz}.f32 d.approx modifier is required. 2010 .f32 introduced in PTX ISA version 1.0 +0.4. Input -Inf -subnormal -0.0 through 1. For PTX ISA version 1. sin. the .0 Table 62. a.f32 sa. Explicit modifiers .approx and .3.0 -0. Target ISA Notes Examples Supported on all target architectures.approx. sin. Find the sine of the angle a (in radians).ftz introduced in PTX ISA version 1.f32 implements a fast approximation to sine.0 +0.f32 flushes subnormal inputs and results to sign-preserving zero.approx. PTX ISA Notes sin. sin. Subnormal numbers: sm_20: By default.PTX ISA Version 2. 96 January 24.ftz.

f32 ca.approx.approx. cos. Explicit modifiers . For PTX ISA versions 1.3. d = cos(a).0 through 1. Subnormal numbers: sm_20: By default. cos. Input -Inf -subnormal -0.ftz introduced in PTX ISA version 1. Find the cosine of the angle a (in radians). Target ISA Notes Examples Supported on all target architectures.0 NaN NaN The maximum absolute error is 2-20.0 +1.0 +0.ftz.f32 introduced in PTX ISA version 1.4 and later. PTX ISA Notes cos. subnormal numbers are supported. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.Chapter 8.f32 defaults to cos. a.ftz.0.approx{. the . For PTX ISA version 1.0 +1.f32 implements a fast approximation to cosine. January 24.ftz}. 2010 97 . cos.9 in quadrant 00.f32 flushes subnormal inputs and results to sign-preserving zero.f32. cos.f32 d.0 +subnormal +Inf NaN Result NaN +1. Instruction Set Table 63. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz. a.approx.approx and .approx modifier is required.4. cos.0 +1.

a.0 Table 64.4 and later. lg2. sm_1x: Subnormal inputs and results to sign-preserving zero.0.approx modifier is required. lg2.approx. Input -Inf -subnormal -0. Explicit modifiers . lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. subnormal numbers are supported.approx and .ftz introduced in PTX ISA version 1.approx. For PTX ISA versions 1.PTX ISA Version 2. d = log(a) / log(2).f32 la. lg2.ftz.3.0 +0.approx{. The maximum absolute error is 2-22.ftz.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.f32 defaults to lg2. Target ISA Notes Examples Supported on all target architectures. a.6 for mantissa.4.f32 Determine the log2 of a. 2010 . For PTX ISA version 1.ftz. 98 January 24.approx. the . PTX ISA Notes lg2. lg2.0 through 1.f32 implements a fast approximation to log2(a).ftz}. lg2.f32 introduced in PTX ISA version 1.f32.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

i. nan The Boolean operator BoolOp(A. . The signed and unsigned comparison operators are eq.s32. p[|q]. .BoolOp{. Subnormal numbers: sm_20: By default.b. setp. xor. {!}c. hi.0. To aid comparison operations in the presence of NaN values. b.r. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. and can be one of: eq. p[|q]. For unsigned values. le.b16.f64 supports subnormal numbers. a. lo. ge. . gtu.PTX ISA Version 2. ltu. If both operands are numeric values (not NaN). subnormal numbers are supported. ge. q = BoolOp(!t. gt. and higher-or-same may be used instead of lt.type setp.b32. le.f32 flushes subnormal inputs to sign-preserving zero. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. p. .lt. ltu.u32. neu. This result is written to the first destination operand. le.f32 comparisons. . the comparison operators lo.n.CmpOp. gt.s32 setp. ls. higher. loweror-same. ls.eq. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. ne. hi. . ne.ftz}. hs equ. .f64 }. Integer Notes Floating Point Notes The ordered comparisons are eq. 102 January 24. sm_1x: setp. .dtype.pred variables.ftz}.u64.ftz applies only to . setp with . gt. the result is false. The comparison operator is a suffix on the instruction. ge. Modifier . and (optionally) combine this result with a predicate value by applying a Boolean operator. p = BoolOp(t.ftz. 2010 . Applies to all numeric types. leu.type . neu. geu. and hs for lower. then these comparisons have the same result as their ordered counterparts.type = { . lt.b64.f32 flushes subnormal inputs to sign-preserving zero. .s64. bit-size comparisons are eq and ne.dtype. gt. Semantics t = (a CmpOp b) ? 1 : 0. setp.and.0 Table 67. or. a. If either operand is NaN.a.f64 source type requires sm_13 or later. lt.f32. respectively. A related value computed using the complement of the compare result is written to the second destination operand.u32 p|q.CmpOp{. num. gtu. ge. The destinations p and q must be .B) is one of: and. If either operand is NaN.s16. The untyped. setp. c). .u16. b. leu. c). le. geu. @q setp. and nan returns true if either operand is NaN. ne. lt. then the result of these comparisons is true.dtype. num returns true if both operands are numeric values (not NaN). unordered versions are included: equ.

.g.type = { . .u16. The selected input is copied to the output without modification. .f32 flushes subnormal values of operand c to sign-preserving zero. a. slct. based on the value of the predicate source operand. Introduced in PTX ISA version 1. a.u64. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.s16. Semantics Floating Point Notes January 24. otherwise b is stored in d. . . slct.r.u64. operand c must match the second instruction type. subnormal numbers are supported.f32 comparisons. d. . and operand a is selected. sm_1x: slct. d = (c == 1) ? a : b.b32.dtype.b16. slct. c. slct.f64 requires sm_13 or later.x. b otherwise. If operand c is NaN.t.dtype. Description Conditional selection. Modifier . B. a is stored in d. and operand a is selected. c.u32. d = (c >= 0) ? a : b.u64. based on the sign of the third operand. selp. 2010 103 .dtype = { . . Operands d.s32 slct{. . Subnormal numbers: sm_20: By default. C. For .f64 }.u32. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. selp Syntax Comparison and Selection Instructions: selp Select between source operands. .f64 }.s32. and b must be of the same type. the comparison is unordered and operand b is selected.0. .p.0. @q selp. a. Operand c is a predicate. If c is True.b16. .b64.s16. b. .u32.f32 flushes subnormal values of operand c to sign-preserving zero. . selp. Instruction Set Table 68. and b are treated as a bitsize type of the same width as the first instruction type. . f0. . y.dtype. Operands d. If c ≥ 0.xp.type d. b.s32 x. . a is stored in d.s64. a.ftz.ftz}. negative zero equals zero.s32 selp. Table 69.f32 d. . c. z.b64.s32. slct.Chapter 8.ftz. val.f32 A.f32. .ftz applies only to .f32. slct Syntax Comparison and Selection Instructions: slct Select one source operand.f64 requires sm_13 or later.u16.b32.dtype.f32 comparisons. . . fval. b.f32 r0.s64. . .

xor. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. and not also operate on predicates. performing bit-wise operations on operands of any type. 2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.7. This permits bit-wise operations on floating point values without having to define a union to access the bits. provided the operands are of the same size. Instructions and.0 8. or.PTX ISA Version 2.4.

and.q.type = { .fpvalue. sign. .b32.b32. d = a & b.b64 }.b32 x. Supported on all target architectures. Allowed types include predicate registers.pred p. Introduced in PTX ISA version 1.b32 mask mask. or.pred. The size of the operands must match. a.Chapter 8. a. d = a | b.type d.0. Allowed types include predicate registers.pred. Introduced in PTX ISA version 1. .b64 }.0. but not necessarily the type.0x80000000. but not necessarily the type.type = { . 2010 105 . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.r. . and.r. .b16. and Syntax Logic and Shift Instructions: and Bitwise AND. b. January 24. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. b. Supported on all target architectures.0x00010001 or. or Syntax Logic and Shift Instructions: or Bitwise OR. or. . Instruction Set Table 70. .b16.type d. .b32 and. The size of the operands must match. . Table 71.q.

Table 74.0.x. . .q.0. not Syntax Logic and Shift Instructions: not Bitwise negation.b32 d.b64 }. not.r. a.type = { .b32.0x0001.pred p. .PTX ISA Version 2.b32 xor.b16. but not necessarily the type. d = (a==0) ? 1 : 0. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b16 d. Introduced in PTX ISA version 1.type = { . The size of the operands must match. . .q. xor.b32. not. Supported on all target architectures.type d. .a. . The size of the operands must match. .0.0 Table 72. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Allowed types include predicates. a. Allowed types include predicate registers.type d.mask. . cnot. d = ~a.pred. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b64 }. but not necessarily the type. Supported on all target architectures. b.pred. 106 January 24. a. cnot. 2010 . . The size of the operands must match. Supported on all target architectures. xor. not.b32.type d. .type = { .b64 }.b32 mask.b16. Table 73. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b16. d = a ^ b. one’s complement. but not necessarily the type.

u32. a.b16.2. shl. regardless of the instruction type. shl. . unsigned and untyped shifts fill with 0. .b16. The b operand must be a 32-bit value.type d.b32. . shr.type d.b64 }.j. k. Supported on all target architectures. i. b. Signed shifts fill with the sign bit.a. but not necessarily the type. .type = { .s32. The sizes of the destination and first source operand must match. a. shr Syntax Logic and Shift Instructions: shr Shift bits right.b64. . Supported on all target architectures.type = { .1.b32. PTX ISA Notes Target ISA Notes Examples January 24. The sizes of the destination and first source operand must match. d = a >> b.i. .b32 q.s32 shr.Chapter 8.u16 shr. sign or zero fill on left. Instruction Set Table 75. shl Syntax Logic and Shift Instructions: shl Shift bits left.0.b16 c.u64. PTX ISA Notes Target ISA Notes Examples Table 76. . 2010 107 . Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. d = a << b. b. zero-fill on right. . .u16. Introduced in PTX ISA version 1. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. regardless of the instruction type. Introduced in PTX ISA version 1. . shr.s64 }. but not necessarily the type. Shift amounts greater than the register width N are clamped to N. The b operand must be a 32-bit value.s16. .a. Shift amounts greater than the register width N are clamped to N.0. Bit-size types are included for symmetry with SHL.i.2. .

The cvta instruction converts addresses between generic and global. Instructions ld. possibly converting it from one format to another.7. and sust support optional cache operations. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and from state space to state space. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. or shared state spaces. ldu. st. prefetchu isspacep cvta cvt 108 January 24. Data Movement and Conversion Instructions These instructions copy data from place to place. ld. and st operate on both scalar and vector types.5. local.PTX ISA Version 2. suld.0 8. mov. 2010 .

Chapter 8. Global data is coherent at the L2 level. likely to be accessed again. evict-first. and cache only in the L2 cache.cs Cache streaming.5. A ld. but multiple L1 caches are not coherent for global data. likely to be accessed once. when applied to a local address. Cache Operators PTX 2. January 24. bypassing the L1 cache.7.lu load last use operation. the cache operators have the following definitions and behavior. not L1). The compiler / programmer may use ld.0 introduces optional cache operators on load and store instructions.lu Last use.cs) on global addresses. The ld.lu instruction performs a load cached streaming operation (ld. fetch again). which allocates cache lines in all levels (L1 and L2) with normal eviction policy.cv to a frame buffer DRAM address is the same as ld. . Use ld. If one thread stores to global memory via one L1 cache. the second thread may get stale L1 cache data.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cg to cache loads only globally. The cache operators require a target architecture of sm_20 or later.cv Cache as volatile (consider cached system memory lines stale. Operator . Instruction Set 8. 2010 109 . Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.lu operation. any existing cache lines that match the requested address in L1 will be evicted. and a second thread loads that address via a second L1 cache with ld. Table 77. rather than the data stored by the first thread.cs is applied to a Local window address. When ld. if the line is fully covered. to allow the thread program to poll a SysMem location written by the CPU.ca loads cached in L1. it performs the ld. The ld. . For sm_20 and later. .cg Cache at global level (cache in L2 and below.ca. As a result of this request. invalidates (discards) the local L1 line following the load. The ld. The default load instruction cache operation is ld. The ld.cs.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.1. .cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.ca.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.

cg is the same as st. 110 January 24. likely to be accessed once.PTX ISA Version 2.cg to local memory uses the L1 cache. The default store instruction cache operation is st. Use st. bypassing its L1 cache. and cache only in the L2 cache. bypassing the L1 cache.0 Table 78. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. The st. to allow a CPU program to poll a SysMem location written by the GPU with st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. If one thread stores to global memory. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. but st.cg Cache at global level (cache in L2 and below.wb could write-back global store data from L1. Global stores bypass L1. rather than get the data from L2 or memory stored by the first thread.ca. which writes back cache lines of coherent cache levels with normal eviction policy. Operator . and discard any L1 lines that match. Future GPUs may have globally-coherent L1 caches. The st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. Addresses not in System Memory use normal write-back.wb for global data. regardless of the cache operation. and a second thread in a different SM later loads from that address via a different L1 cache with ld.wt store write-through operation applied to a global System Memory address writes through the L2 cache. the second thread may get a hit on stale L1 cache data. and marks local L1 lines evict-first. in which case st. In sm_20. However.wt. st. not L1). 2010 .cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.cg to cache global store data only globally.wb. .ca loads.cs Cache streaming.wt Cache write-through (to system memory). .

Semantics d = a.f64 requires sm_13 or later. A[5].u64. . . k.type mov.1.u32.b16. Introduced in PTX ISA version 1. the parameter will be copied onto the stack and the address will be in the local state space. ptr. .f64 }.e. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. or function name..f32.e. For variables declared in .f32 mov. mov places the non-generic address of the variable (i. Description . or shared state space. d. myFunc. avar. i. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. d = &label. addr.type mov. Take the non-generic address of a variable in global.Chapter 8. Write register d with the value of a.shared state spaces.s32. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. mov.u32 d. 2010 111 . local.global.local. local. alternately. Operand a may be a register. Instruction Set Table 79.const.f32 mov. local. mov. u. // get address of variable // get address of label or function .pred. the generic address of a variable declared in global.v. d = &avar. label.s64.b64. d. immediate. . . the address of the variable in its state space) into the destination register. mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.0. within the variable’s declared state space Notes Although only predicate and bit-size types are required. label. or shared state space may be taken directly using the cvta instruction. sreg. d = sreg.u32 mov. . A. .type mov.a. . ptr. and . special register. The generic address of a variable in global. Note that if the address of a device function parameter is moved to a register.u16.b32..s16. variable in an addressable memory space. a. .u16 mov. // address is non-generic.type = { .0. . . d. .type d.u32 mov.

%r1.type d.u16 %x is a double. {lo.b64 // pack two 32-bit elements into .b8 r. d.b64 }.x. d. .b. or write vector register d with the unpacked values from scalar register a.y.7].x | (a.hi are .b64 { d. a[48.b64 { d.b32 %r1... 2010 .w}..w have type . Both the overall size of the vector and the size of the scalar must match the size of the instruction type.w << 48) d = a.w } = { a[0. d. lo.x.. d. %r1.b64 112 January 24.u32 x.31] } // unpack 16-bit elements from . mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.y << 16) d = a..w } = { a[0.x | (a.31] } // unpack 8-bit elements from ..15].z.y } = { a[0.63] } // unpack 16-bit elements from .b32 // pack four 16-bit elements into .type = { .b.hi}.x..x.7].. d. d. Supported on all target architectures. d.z.x | (a. a[32..z << 32) | (a. mov. {r.b32 mov. Description Write scalar register d with the packed value of vector register a. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).z << 16) | (a..b16 // pack four 8-bit elements into . a.b32 mov.31]. a[24..g.23]. a[32.a}. Semantics d = a. a[16.PTX ISA Version 2.x.0.b32.{x.z.. %x.b16.0 Table 80.b}. . a[8.{a.y << 16) | (a.w << 24) d = a.a have type . mov. For bit-size types.y << 8) | (a.b32 { d.x | (a..31].b have type . .y.15].y. a[16.b32 // pack two 16-bit elements into . a[16.b16 { d.y << 32) // pack two 8-bit elements into .15] } // unpack 8-bit elements from .u8 // unpack 32-bit elements from .b64 mov.y << 8) d = a.z.b32 { d. d.g. // // // // a.. a[8.47].y. d.y } = { a[0.15].x | (a.y } = { a[0.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

Generic addressing may be used with ld. and truncated if the register width exceeds the state space address width for the target architecture. ld{. [a].ss}{. the access may proceed by silently masking off low-order address bits to achieve proper rounding.volatile{. . . perform the load using generic addressing.vec. . *(a+immOff). an address maps to global memory unless it falls within the local memory window or the shared memory window.ss}{.s16. d.cv }. Description Load register variable d from the location specified by the source address operand a in specified state space. . i. . Generic addressing and cache operations introduced in PTX ISA 2. i.volatile. .b16.f64 using cvt. [a]. . an integer or bit-size type register reg containing a byte address.const space suffix may have an optional bank number to indicate constant banks other than bank zero. .0.0. . 32-bit).v2.type ld. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type ld{.type = { . ld.volatile{.f32 or . Semantics d d d d = = = = a.global and .type d. This may be used.local.shared }. The address size may be either 32-bit or 64-bit. 32-bit). *(immAddr). . *a. and then converted to . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.b8. . . .Chapter 8. d. the resulting behavior is undefined. [a]. or [immAddr] an immediate absolute byte address (unsigned. ..ca.cop}.vec.b32.volatile.type . In generic addressing.e.cop}. to enforce sequential consistency between threads accessing shared memory.volatile may be used with .s64.b16.e. If no state space is given. . . .cop = { . 2010 113 .f16 data may be loaded using ld. The value loaded is sign-extended to the destination register width for signed integers.lu. ld introduced in PTX ISA version 1.ss}.cs.cg. and is zeroextended to the destination register width for unsigned and bit-size types. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. . . an address maps to the corresponding location in local or shared memory. Instruction Set Table 81.b64.u32.ss = { . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .volatile introduced in PTX ISA version 1. ld. or the instruction may fault. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . A destination register wider than the specified type may be used.u16.param. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. Within these windows.s8. . .const.s32. PTX ISA Notes January 24. Addresses are zero-extended to the specified width as needed. . The address must be naturally aligned to a multiple of the access size.f64 }.shared spaces to inhibit optimization of references to volatile memory.vec = { .1.u8. . If an address is not properly aligned. Cache operations are not permitted with ld.v4 }. [a]. The .global. .u64.f32. for example. d.ss}.reg state space.

// access incomplete array x. d.f32.f32 ld.[fs].shared. %r. ld.s32 ld.0 Target ISA Notes ld.local.[240].f16 d.local.global.global. // negative offset %r.const.b32 ld. Cache operations require sm_20 or later. // immediate address %r.[p+4].v4.[p+-8].b16 cvt. // load .PTX ISA Version 2.b32 ld.b32 ld. Generic addressing requires sm_20 or later. 2010 .const[4].[p].[buffer+64].%r.f64 requires sm_13 or later. x.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. Q.b64 ld.[a].

e. [a].f32 or .f16 data may be loaded using ldu.global }. . 2010 115 . For ldu. i. only generic addresses that map to global memory are legal.ss}.v4. [areg] a register reg containing a byte address. A destination register wider than the specified type may be used. The address size may be either 32-bit or 64-bit. ldu.s64. or the instruction may fault. or [immAddr] an immediate absolute byte address (unsigned. an address maps to global memory unless it falls within the local memory window or the shared memory window. and truncated if the register width exceeds the state space address width for the target architecture. If an address is not properly aligned. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. ..b32.f64 }. *(immAddr). A register containing an address may be declared as a bit-size type or integer type. i. The data at the specified address must be read-only. .ss}.u8. . *a. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . // load from address // vec load from address . . If no state space is given.global. ldu. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . ldu{. ldu.[p].f32. [a].v4 }. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. PTX ISA Notes Target ISA Notes Examples January 24. The value loaded is sign-extended to the destination register width for signed integers.Chapter 8. Within these windows. The addressable operand a is one of: [avar] the name of an addressable variable var. and then converted to . d.e. The address must be naturally aligned to a multiple of the access size.vec = { . .b32 d.s32.vec.[a]. the resulting behavior is undefined. Addresses are zero-extended to the specified width as needed.[p+4]. Introduced in PTX ISA version 2.reg state space.v2.global. ldu.f64 requires sm_13 or later. . .u32.type d. 32-bit).b64. 32-bit). ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. and is zeroextended to the destination register width for unsigned and bit-size types. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . .s8.b8. Instruction Set Table 82.f32 d.u64.b16.type = { . . . .f32 Q.u16. Semantics d d d d = = = = a.global.ss = { .type ldu{.b16.f64 using cvt. perform the load using generic addressing. // state space . *(a+immOff). where the address is guaranteed to be the same across all threads in the warp.0. . an address maps to the corresponding location in local or shared memory. In generic addressing.s16.

The lower n bits corresponding to the instruction-type width are stored to memory. The address must be naturally aligned to a multiple of the access size. In generic addressing.ss . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. b.b8. . . an address maps to global memory unless it falls within the local memory window or the shared memory window.0 Table 83. PTX ISA Notes Target ISA Notes 116 January 24.e.s32. and truncated if the register width exceeds the state space address width for the target architecture. Within these windows. .cop}. .b32.b16. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.cop . *(immAddr) = a.type . Addresses are zero-extended to the specified width as needed. 32-bit).v4 }. the resulting behavior is undefined.type [a]. [a]. Semantics d = a. . . .0. .b64.global..ss}.s16. . The address size may be either 32-bit or 64-bit.ss}{.global and .1. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. or the instruction may fault. . 2010 .shared }.f64 requires sm_13 or later.e.ss}. Generic addressing requires sm_20 or later. . perform the store using generic addressing. .cg.type st. Generic addressing may be used with st. *d = a. b.shared spaces to inhibit optimization of references to volatile memory. to enforce sequential consistency between threads accessing shared memory. .volatile. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. *(d+immOffset) = a. an integer or bit-size type register reg containing a byte address.s64. an address maps to the corresponding location in local or shared memory. st{.cs. .u8.volatile{. . .wt }. [a]. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st. 32-bit). This may be used.f16 data resulting from a cvt instruction may be stored using st. i.0.v2.vec.volatile{. the access may proceed by silently masking off low-order address bits to achieve proper rounding.vec . Cache operations are not permitted with st.ss}{. . st. st. .f32.wb.u16.u64. If no state space is given. Cache operations require sm_20 or later.PTX ISA Version 2. . { .type st{. A source register wider than the specified type may be used. b.u32. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.local.volatile may be used with . { . Generic addressing and cache operations introduced in PTX ISA 2.f64 }.volatile introduced in PTX ISA version 1.s8.vec. .cop}. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. If an address is not properly aligned. for example. st introduced in PTX ISA version 1.b16. or [immAddr] an immediate absolute byte address (unsigned.volatile. b. [a].type = = = = {. { . i.reg state space.

r7.b32 st. [q+-8].f16.a.local.Chapter 8.f32 st.Q.b32 st.global. Instruction Set Examples st.%r. [p].a.v4.global.local.b16 [a].local.s32 cvt.s32 st.b. // negative offset [100]. // %r is 32-bit register // store lower 16 bits January 24. 2010 117 . [fs].f32 st. [q+4].%r. // immediate address %r.

. Within these windows. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. in specified state space. or [immAddr] an immediate absolute byte address (unsigned. A prefetch to a shared memory location performs no operation.L2 }. In generic addressing. .space = { . .global.e.local }. a register reg containing a byte address.space}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. 32-bit).level prefetchu. and truncated if the register width exceeds the state space address width for the target architecture.global.L1 [addr]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. A prefetch into the uniform cache requires a generic address. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. 2010 . The address size may be either 32-bit or 64-bit. an address maps to the corresponding location in local or shared memory. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. an address maps to global memory unless it falls within the local memory window or the shared memory window. prefetchu. If no state space is given.0 Table 84. prefetch.PTX ISA Version 2. [a].L1 [ptr]. // prefetch to data cache // prefetch to uniform cache . Addresses are zero-extended to the specified width as needed. prefetch{. and no operation occurs if the address maps to a local or shared memory location.L1 [a]. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. the prefetch uses generic addressing. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. i. 32-bit).level = { . 118 January 24.0.L1. prefetch and prefetchu require sm_20 or later.

space = { .shared. gptr.shared isglbl.genptr. cvta. or vice-versa. or shared state space to generic. local. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. or shared address. svar.pred . When converting a generic address into a global. // get generic address of svar cvta.Chapter 8.u32 gptr.u64 }. isshrd. January 24.local isspacep. Instruction Set Table 85.size p. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The destination register must be of type . local. cvta.local. a. or shared address to a generic address.local.size cvta. the generic address of the variable may be taken using cvta. var.space = { . a.0.local. // convert to generic address // get generic address of var // convert generic address to global. A program may use isspacep to guard against such incorrect behavior. // local. local. The source address operand must be a register of type .global.space. or shared state space.u64 or cvt. or shared state space.u64. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. isspacep. local. The source and destination addresses must be the same size.global.0.u64. cvta requires sm_20 or later.pred. a. local. . islcl.u32 p. or vice-versa.shared }.space p. // result is . or shared address cvta.u32.global. Use cvt. p. lptr.u32 to truncate or zero-extend addresses.shared }. Description Convert a global. . isspacep requires sm_20 or later. sptr. . cvta. p.u32 p.size .u32.u32 or . isspacep.space.global isspacep.to. . .lptr. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.to. Introduced in PTX ISA version 2. 2010 119 .size = { . Take the generic address of a variable declared in global.space. PTX ISA Notes Target ISA Notes Examples Table 86. . For variables declared in global.

sat For integer destination types. For float-to-integer conversions. .u16.u32. and for same-size float-tofloat conversions where the value is rounded to an integer. The compiler will preserve this behavior for legacy PTX code. sm_1x: For cvt.ftz. .dtype = . . the . .ftz.dtype.e. Integer rounding is illegal in all other instances. subnormal inputs are flushed to signpreserving zero.sat}. d.f32. 2010 . choosing even integer if source is equidistant between two integers. Integer rounding modifiers: . The optional . Saturation modifier: .u8. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.dtype.rzi.s8.rp }.f32. i.f32 float-to-integer conversions and cvt.. .rni round to nearest integer.rpi }.ftz modifier may be specified in these cases for clarity.4 and earlier.rzi round to nearest integer in the direction of zero . a.dtype. .rn.rz.f32 float-to-integer conversions and cvt.f32 float-tofloat conversions with integer rounding. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.s16..f32.0 Table 87. .atype = { . .ftz}{. // integer rounding // fp rounding . d = convert(a). .sat is redundant. . . subnormal numbers are supported. .rmi round to nearest integer in direction of negative infinity . Note that saturation applies to both signed and unsigned integer types. Description Semantics Integer Notes Convert between different types and sizes.ftz.u64. . a. .atype cvt{. . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.frnd}{. . cvt{.ftz}{.f32 float-tofloat conversions with integer rounding.sat}.f16.atype d. Note: In PTX ISA versions 1.irnd}{. .s64.dtype.MAXINT for the size of the operation. .ftz.s32. 120 January 24.e. For cvt.rmi.f64 }.frnd = { .rm.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. . subnormal inputs are flushed to signpreserving zero. the result is clamped to the destination range by default. Integer rounding is required for float-to-integer conversions. .sat limits the result to MININT.rni. . i.irnd = { .PTX ISA Version 2.

and .f32.f32 x. cvt. Floating-point rounding modifiers: . . Specifically.f16.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).y.f16. stored in floating-point format.0].f32.version is 1. and cvt.f32.sat limits the result to the range [0. The operands must be of the same size. Floating-point rounding is illegal in all other instances.4 or earlier.sat For floating-point destination types. 2010 121 .4 and earlier.ftz modifier may be specified in these cases for clarity. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f32. .rni.ftz behavior for sm_1x targets January 24. if the PTX . NaN results are flushed to positive zero.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. cvt.r.s32.f64 j. Applies to .f32 x.0.Chapter 8. // float-to-int saturates by default cvt.rz mantissa LSB rounds towards zero .s32 f.f64 types. // note .f32. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. // round to nearest int.f32 instructions. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.rm mantissa LSB rounds towards negative infinity . and for integer-to-float conversions. cvt to or from . Modifier . Introduced in PTX ISA version 1. result is fp cvt. cvt. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.y. Saturation modifier: . 1.rn mantissa LSB rounds to nearest even .0.f32. Note: In PTX ISA versions 1. The result is an integral value. The optional .f32. subnormal numbers are supported. Subnormal numbers: sm_20: By default.f16. The compiler will preserve this behavior for legacy PTX code.f64 requires sm_13 or later.i.f64.

and surface descriptors.. If no texturing mode is declared. In the unified mode. Texturing modes For working with textures and samplers. The advantage of unified mode is that it allows 128 samplers. Example: calculate an element’s power contribution as element’s power/total number of elements.width. The texturing mode is selected using . allowing them to be defined separately and combined at the site of usage in the program. 122 January 24.6. div. r3.f2}]. r5. texture and sampler information is accessed through a single .texref tex1 ) { txq.target options ‘texmode_unified’ and ‘texmode_independent’.f32 r1. r4.param . r2. // get tex1’s tex. PTX has two modes of operation. but the number of samplers is greatly restricted to 16.b32 r6.b32 r5. The advantage of independent mode is that textures and samplers can be mixed and matched. r1. sampler. r1.u32 r5. . r6.target texmode_independent . . sampler. [tex1]. Ability to query fields within texture. . r3. PTX supports the following operations on texture. and surface descriptors: • • • Static initialization of texture. {f1.f32 {r1.samplerref tsamp1 = { addr_mode_0 filter_mode }. add.height. sampler.f32 r1. 2010 .0 8.7.2d.global . sampler.PTX ISA Version 2. with the restriction that they correspond 1-to-1 with the 128 possible textures. the file is assumed to use unified mode. and surfaces.v4. [tex1.r4}. A PTX module may declare only one texturing mode. = nearest width height tsamp1.f32 r3.u32 r5.r2.entry compute_power ( . r1. texture and sampler information each have their own handle. and surface descriptors.r3. r5..f32. add. Module-scope and per-entry scope definitions of texture. } = clamp_to_border.f32. mul.f32 r1. In the independent mode. Texture and Surface Instructions This section describes PTX instructions for accessing textures. and surface descriptors.texref handle. samplers. r5. cvt. add. [tex1]. // get tex1’s txq.

If an address is not properly aligned.r4}. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Description Texture lookup using a texture coordinate vector. // explicit sampler .r3.s32. or the instruction may fault.e.1d. .geom = { .btype d. The instruction always returns a four-element vector of 32-bit values. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f4}].f32 {r1.dtype = { .f32 }.0.2d.v4 coordinate vectors are allowed for any geometry. //Example of unified mode texturing tex.r2.u32.v4.v4. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.5. d.geom.s32. tex txq suld sust sured suq Table 88. tex. [tex_a. If no sampler is specified.btype tex.btype = { . Instruction Set These instructions provide access to texture and surface memory. {f1}]. Operand c is a scalar or singleton tuple for 1d textures. where the fourth element is ignored. sampler_x. . 2010 123 . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.Chapter 8. .dtype.r3. .dtype. // Example of independent mode texturing tex. PTX ISA Notes Target ISA Notes Examples January 24. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.v4. Supported on all target architectures. Notes For compatibility with prior versions of PTX.geom. . .f3.s32. and is a four-element vector for 3d textures.1d. with the extra elements being ignored.s32 {r1. is a two-element vector for 2d textures. An optional texture sampler b may be specified. c]. .3d. {f1.f2.v4. c].3d }. the square brackets are not required and . A texture base address is assumed to be aligned to a 16-byte address.s32.f32 }. [a. b..r4}. the resulting behavior is undefined. i. [a. Unified mode texturing introduced in PTX ISA version 1. [tex_a. the sampler behavior is a property of the named texture.r2.

. // texture attributes // sampler attributes . txq.b32 %r1.b32 %r1.width.normalized_coords }.samplerref variable.filter_mode. .width .b32 %r1. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.PTX ISA Version 2.tquery. .addr_mode_0.addr_mode_0 .width. Operand a is a .addr_mode_1 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. addr_mode_1.height . clamp_to_edge. // unified mode // independent mode 124 January 24. mirror. [a]. txq. sampler attributes are also accessed via a texref argument. d. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.addr_mode_0.height. Supported on all target architectures.depth . Query: . Integer from enum { nearest. [a].filter_mode. [smpl_B]. linear } Integer from enum { wrap.depth.b32 txq. 2010 . [tex_A]. Description Query an attribute of a texture or sampler.5. [tex_A]. txq.0 Table 89. txq.tquery = { .squery. addr_mode_2 }.b32 d.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). and in independent mode sampler attributes are accessed via a separate samplerref argument.squery = { .texref or . . In unified mode.normalized_coords . . clamp_ogl.filter_mode .

then .geom{. Operand a is a .3d requires sm_20 or later.v4 }. The . .f2. If the destination type is .trap .2d. suld Syntax Texture and Surface Instructions: suld Load from surface memory. .0.s32. or .3d }. 2010 125 .f32 }. suld.f32 based on the surface format as follows: If the surface format contains UNORM.dtype .clamp . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.b16. then . .vec .f4}.b32.y.clamp suld. // for suld.s32. and A components of the surface format. .clamp field specifies how to handle out-of-bounds addresses: .dtype.clamp. size and type conversion is performed as needed to convert from the surface sample format to the destination type.r2}. and is a four-element vector for 3d surfaces.p is currently unimplemented.b64.b32.p.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. Description Load from surface memory using a surface coordinate vector.b. . SNORM.cop}. Target ISA Notes Examples January 24. // for suld. // cache operation none. suld. . suld. .f32 is returned. suld.b64 }. If an address is not properly aligned.clamp = = = = = = { { { { { { d. suld.b8 . . Cache operations require sm_20 or later. {x}].trap {r1.5.geom . or FLOAT data.cg.s32.f32.v2. .b.trap introduced in PTX ISA version 1. . the resulting behavior is undefined. // formatted . {x. B. i. the surface sample elements are converted to . {f1. or .cop}. and the size of the data transfer matches the size of destination operand d. .cs. [surf_A.dtype .1d. The lowest dimension coordinate represents a sample offset rather than a byte offset. . suld.ca.zero }. and cache operations introduced in PTX ISA version 2.trap clamping modifier.b .p. Instruction Set Table 90.u32.s32.p requires sm_20 or later. is a two-element vector for 2d surfaces.trap suld. A surface base address is assumed to be aligned to a 16-byte address. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. G. . additional clamp modifiers.1d. If the destination base type is .u32 is returned.e.f32. Operand b is a scalar or singleton tuple for 1d surfaces. .p . then . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . .v4.surfref variable. or the instruction may fault.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.v2. suld.dtype.u32.p.cv }.Chapter 8.v4.vec. .geom{.3d.b32.cop . . [a. if the surface format contains UINT data.f3.clamp . // unformatted d. [surf_B. suld. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Coordinate elements are of type ..b performs an unformatted load of binary data.b.b supported on all target architectures.z. suld.u32. where the fourth element is ignored. b]. [a. if the surface format contains SINT data.w}]. Destination vector elements corresponding to components that do not appear in the surface format are not written. b].trap. sm_1x targets support only the .s32 is returned.

and A surface components.PTX ISA Version 2. then .cop}. If the source base type is . SNORM.f3. sust Syntax Texture and Surface Instructions: sust Store to surface memory.v4 }. sust. These elements are written to the corresponding surface sample components. sust.u32..p requires sm_20 or later.trap . Operand a is a .p.f32.v2. .trap [surf_A.cop}.v4.u32 is assumed.p.0.b32. . if the surface format contains SINT data. and is a four-element vector for 3d surfaces.r2}.geom . where the fourth element is ignored. The source data is then converted from this type to the surface sample format. sust.trap clamping modifier. . b]. The size of the data transfer matches the size of source operand c. sust. .trap.s32.3d requires sm_20 or later.f32} are currently unimplemented. {x}]. // unformatted // formatted . . Source elements that do not occur in the surface sample are ignored. .3d }.vec .zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.3d.1d.u32.2d.s32 is assumed. Operand b is a scalar or singleton tuple for 1d surfaces.cs. If the source type is .b. Coordinate elements are of type .e. A surface base address is assumed to be aligned to a 16-byte address.f32 is assumed.b performs an unformatted store of binary data. if the surface format contains UINT data. sust.z. The .clamp = = = = = = { { { { { { [a.b64 }. Target ISA Notes Examples 126 January 24. sust. The source vector elements are interpreted left-to-right as R.trap introduced in PTX ISA version 1. The lowest dimension coordinate represents a sample offset rather than a byte offset. the resulting behavior is undefined.cg. then . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.vec. B.p Description Store to surface memory using a surface coordinate vector.b64. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32.p.b // for sust. .w}]. . . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. . size and type conversions are performed as needed between the surface sample format and the destination type. [surf_B. .v2.b. i. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.clamp sust. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.s32.ctype.clamp .s32.vec. c. . sm_1x targets support only the . Cache operations require sm_20 or later. sust. or .ctype .b8 . .b32.y. sust.f2.wb. {x.cop . .ctype .{u32.clamp field specifies how to handle out-of-bounds addresses: .f4}. . additional clamp modifiers. Surface sample components that do not occur in the source vector will be written with an unpredictable value. . then . or the instruction may fault.1d.geom{. sust. [a.b supported on all target architectures. and cache operations introduced in PTX ISA version 2. {f1.b.f32.wt }. 2010 .surfref variable.geom{. . is a two-element vector for 2d surfaces.zero }. G.b32.ctype.clamp .trap sust. none. // for sust.f32 }.0 Table 91.5. {r1.p. If an address is not properly aligned. .p performs a formatted store of a vector of 32-bit data values to a surface sample. b].clamp. . . or FLOAT data. c.b16.

.clamp [a. operations and and or apply to . Reduction to surface memory using a surface coordinate vector. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.p performs a reduction on sample-addressed 32-bit data.b32 }.ctype = { .or }.trap sured. or .op = { . // for sured.u32. // sample addressing .p. the access may proceed by silently masking off low-order address bits to achieve proper rounding.ctype = { . .b. i. The . and is a four-element vector for 3d surfaces. r1.s32 is assumed.max.s32 or . the resulting behavior is undefined. Instruction Set Table 92.zero }.u32 is assumed.geom = { . // byte addressing sured.b .u32. and the data is interpreted as .b].b32 }.min. Operand a is a .trap. or the instruction may fault. is a two-element vector for 2d surfaces.2d. sured requires sm_20 or later.2d. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.s32. If an address is not properly aligned.add.b. .3d }. and .and. sured. .s32 types. .op.geom. . . then . sured.b performs an unformatted reduction on . The instruction type is restricted to .b32. if the surface format contains SINT data.Chapter 8. . .trap . . 2010 127 .e.c.add.s32 types. .u32. .s32. [surf_B.op. A surface base address is assumed to be aligned to a 16-byte address. then .geom.clamp .clamp = { . Operations add applies to .min.ctype. The lowest dimension coordinate represents a sample offset rather than a byte offset. // for sured. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b32 type.. sured. January 24.u64 data.clamp.clamp [a.u32 based on the surface sample format as follows: if the surface format contains UINT data.b32. sured.surfref variable.s32.clamp field specifies how to handle out-of-bounds addresses: . .p. where the fourth element is ignored.1d. r1.b32.u32 and .1d.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. Coordinate elements are of type .u64.y}].ctype. .p . . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.0.b]. {x. {x}]. . Operand b is a scalar or singleton tuple for 1d surfaces. min and max apply to .c.u64.trap [surf_A.

. 2010 .depth }.surfref variable.width.5.height. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.PTX ISA Version 2. .query = { . [a]. 128 January 24.b32 %r1. [surf_A].query. suq. .b32 d.width.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Supported on all target architectures.0 Table 93. suq. Description Query an attribute of a surface.width .height . Query: . Operand a is a .

y. Introduced in PTX ISA version 1. Threads with a false guard predicate do nothing. Execute an instruction or instruction block for threads that have the guard predicate true. If {!}p then instruction Introduced in PTX ISA version 1.a. p. } PTX ISA Notes Target ISA Notes Examples Table 95.f32 @!p div. 2010 129 . The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.b.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.s32 d.7.0. ratio. {} Syntax Description Control Flow Instructions: { } Instruction grouping. Instruction Set 8. Supported on all target architectures.f32 @q bra L23.eq. { add. @{!}p instruction.c. { instructionList } The curly braces create a group of instructions. Supported on all target architectures. used primarily for defining a function body. mov.7.x.0. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.Chapter 8.0. setp.s32 a.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

January 24, 2010

131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Operand b specifies the number of threads participating in the barrier.u32. bar. Note that a non-zero thread count is required for bar. a{. and then safely read values stored by other threads prior to the barrier.sync) until the barrier count is met.Chapter 8. and bar.sync or bar.red. Thus. p.red instruction. bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. it simply marks a thread's arrival at the barrier. Register operands. Once the barrier count is reached.{arrive.0. bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.red} require sm_20 or later.sync 0.sync without a thread count introduced in PTX ISA 1.15. the optional thread count must be a multiple of the warp size.popc).sync or bar.red delays the executing threads (similar to bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. Instruction Set Table 100. {!}c. the waiting threads are restarted without delay. 2010 133 . In addition to signaling its arrival at the barrier. If no thread count is specified. operands p and c are predicates. Register operands.red performs a predicate reduction across the threads participating in the barrier. if any thread in a warp executes a bar instruction. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.or }. The result of . bar. Operands a.arrive.version 2. and the barrier is reinitialized so that it can be immediately reused.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).popc.arrive a{. Since barriers are executed on a per-warp basis.u32 bar.sync and bar. Execution in this case is unpredictable. bar. the final value is written to the destination register in all threads waiting at the barrier. the bar. while . b}.red also guarantee memory ordering among threads identical to membar.. a{.red performs a reduction operation across threads. b}. January 24. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.popc is the number of threads with a true predicate.0. .sync with an immediate barrier number is supported for sm_1x targets.op = { . execute a bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.and and .red should not be intermixed with bar.pred . Only bar. bar. b. PTX ISA Notes Target ISA Notes Examples bar. threads within a CTA that wish to communicate via memory can store to memory. thread count. a.or). d. bar.sync and bar. Thus. All threads in the warp are stalled until the barrier completes.{arrive. {!}c. Description Performs barrier synchronization and communication within a CTA. all-threads-true (. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).sync bar.red} introduced in PTX .and.red are population-count (. all threads in the CTA participate in the barrier. bar. and any-thread-true (. and d have type . and bar.cta.op. Each CTA instance has sixteen barriers numbered 0. b. thread count. The reduction operations for bar.arrive does not cause any waiting by the executing threads. In conditionally executed code. When a barrier completes.and). bar.arrive using the same active barrier. The barrier instructions signal the arrival of the executing threads at the named barrier. it is as if all the threads in the warp have executed the bar instruction. b}.red.

gl} introduced in PTX . membar.gl} supported on all target architectures. A memory write (e.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. global. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. 134 January 24.0. membar.{cta.cta. membar.g.PTX ISA Version 2.0 Table 101.sys introduced in PTX . membar. .g.sys. membar. membar. membar. 2010 . Waits until prior memory reads have been performed with respect to other threads in the CTA. membar. membar.sys requires sm_20 or later.level = { .sys will typically have much longer latency than membar. membar.cta. A memory read (e. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.sys }. this is the appropriate level of membar. when the previous value can no longer be read. level describes the scope of other clients for which membar is an ordering event. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. or system memory level.gl. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar.sys Waits until all prior memory requests have been performed with respect to all clients. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. including thoses communicating via PCI-E such as system and peer-to-peer memory. PTX ISA Notes Target ISA Notes Examples membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.gl. .version 1.cta Waits until all prior memory writes are visible to other threads in the same CTA.4. by st.level.cta.version 2.gl.{cta. .gl will typically have a longer latency than membar. that is. and memory reads by this thread can no longer be affected by other thread writes. For communication between threads in different CTAs or even different SMs.

and exch (exchange).xor. i.b64. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.exch to store to locations accessed by other atomic operations. b. The integer operations are add.Chapter 8. and truncated if the register width exceeds the state space address width for the target architecture.g. . . or. The address size may be either 32-bit or 64-bit.add. cas (compare-and-swap).f32.u32.u32 only . .cas.type = { .shared }.space}. min.op. . If no state space is given.u64.. The inc and dec operations return a result in the range [0.max }.dec. Within these windows.type atom{. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. and stores the result of the specified operation at location a.min.exch.space}.b]. and max operations are single-precision. . the resulting behavior is undefined. a de-referenced register areg containing a byte address. .. dec. by inserting barriers between normal stores and atomic operations to a common address. xor.u32.s32. accesses to local memory are illegal. perform the memory accesses using generic addressing.and. Addresses are zero-extended to the specified width as needed. d. . . The bit-size operations are and. If an address is not properly aligned. Description // // // // // . The floating-point operations are add.global. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. [a]. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. min. .u64 . . . or the instruction may fault.add.b32 only . . 32-bit operations. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . .u32. overwriting the original value. For atom.f32 Atomically loads the original value at location a into destination register d. The floating-point add. b.s32. . .type d.or. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 102.space = { . performs a reduction operation with operand b and the value in location a. inc. .b32. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32. max. i. min.e. c.e. and max. or [immAddr] an immediate absolute byte address.op. Operand a specifies a location in the specified state space. . . 2010 135 .f32 }. A register containing an address may be declared as a bit-size type or integer type.s32. or by using atom.inc. [a].op = { . . The address must be naturally aligned to a multiple of the access size. atom.b64 . an address maps to the corresponding location in local or shared memory. e. January 24. an address maps to global memory unless it falls within the local memory window or the shared memory window. atom{. . In generic addressing.

cas. b. Introduced in PTX ISA version 1. 2010 .shared.s32 atom.s.max} are unimplemented.{min.cas. : r-1. cas(r. 64-bit atom. atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. c) operation(*a. b).global.global requires sm_11 or later.0.shared requires sm_12 or later.b32 d.0. atom.f32 requires sm_20 or later. atom.[a].[x+4]. *a = (operation == cas) ? : } where inc(r.{add. Release Notes Examples @p 136 January 24. Use of generic addressing requires sm_20 or later. d. s) = s. atom.my_new_val.exch} requires sm_12 or later. 64-bit atom.add. s) = (r >= s) ? 0 dec(r.1.t) = (r == s) ? t operation(*a. s) = (r > s) ? s exch(r.shared operations require sm_20 or later.0 Semantics atomic { d = *a.global. d.max.PTX ISA Version 2. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. atom.[p]. : r.add.f32 atom.f32.my_val. : r+1.

exch to store to locations accessed by other reduction operations.and.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. inc. In generic addressing. A register containing an address may be declared as a bit-size type or integer type. and truncated if the register width exceeds the state space address width for the target architecture. January 24.e.b32.space}. .u32. .type [a]. the access may proceed by silently masking off low-order address bits to achieve proper rounding.shared }. Semantics *a = operation(*a. accesses to local memory are illegal.op.f32. perform the memory accesses using generic addressing.inc. For red.f32 }. . i. . min. red{. Description // // // // .s32. . . s) = (r > s) ? s : r-1.add. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. dec.global.Chapter 8. the resulting behavior is undefined. s) = (r >= s) ? 0 : r+1. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. dec(r. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory..min. min. b. Operand a specifies a location in the specified state space. or. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. max.. . The integer operations are add.type = { . by inserting barriers between normal stores and reduction operations to a common address.u32.b].b64. Instruction Set Table 103.e. an address maps to the corresponding location in local or shared memory. i. 32-bit operations. and stores the result of the specified operation at location a. . . The address size may be either 32-bit or 64-bit. overwriting the original value.u32 only . and xor.f32 Performs a reduction operation with operand b and the value in location a.xor. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Within these windows.space = { .s32.max }. . . . a de-referenced register areg containing a byte address.u32. . and max operations are single-precision. . an address maps to global memory unless it falls within the local memory window or the shared memory window. e. .add. min. The floating-point operations are add. . If no state space is given. or by using atom. The address must be naturally aligned to a multiple of the access size. The floating-point add. . 2010 137 . and max. The bit-size operations are and. red. . .b32 only . If an address is not properly aligned. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Notes Operand a must reside in either the global or shared state space.dec. or the instruction may fault.u64 .or. The inc and dec operations return a result in the range [0. Addresses are zero-extended to the specified width as needed.s32. where inc(r.u64.g.op = { . or [immAddr] an immediate absolute byte address. . b).

add.shared operations require sm_20 or later. [x+4].0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.{min.shared requires sm_12 or later.PTX ISA Version 2.b32 [a].1.0. red.add. 64-bit red.2. red.and.my_val.f32 red.s32 red. red. [p]. 64-bit red.shared.max.global.global. Release Notes Examples @p 138 January 24.f32.max} are unimplemented. red. 2010 . Use of generic addressing requires sm_20 or later.f32 requires sm_20 or later.add requires sm_12 or later.global requires sm_11 or later red.

ballot. The reduction modes are: .none. vote.q. returns bitmask .any. {!}a.b32 p.b32 requires sm_20 or later. Note that vote applies to threads in a single warp.all. vote. . Negating the source predicate also computes .mode.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. where the bit position corresponds to the thread’s lane id. p. Negate the source predicate to compute .pred vote. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. Description Performs a reduction of the source predicate across threads in a warp.pred d.not_all. In the ‘ballot’ form.2. The destination predicate value is the same across all threads in the warp. Instruction Set Table 104. // get ‘ballot’ across warp January 24.uni.uni True if source predicate has the same value in all active threads in warp. r1. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. .uni.p.all.Chapter 8. // ‘ballot’ form. .ballot. not across an entire CTA. Negate the source predicate to compute .all True if source predicate is True for all active threads in warp. vote.any True if source predicate is True for some active thread in warp. vote. {!}a. .uni }.ballot. vote requires sm_12 or later.ballot. 2010 139 .pred vote.q.mode = { . vote.b32 d.

The primary operation is then performed to produce an . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.btype{. b{.b0. . half-word. 140 January 24. The source and destination operands are all 32-bit registers. or word values from its source operands.or zero-extend byte.bsel}. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. to produce signed 33-bit input values.s32 }.s34 intermediate result.dtype.dtype.dsel = .dtype = . and btype are valid. 4. .sat} d. .atype.atype = . 2.bsel}.atype.btype{. . perform a scalar arithmetic operation to produce a signed 34-bit result. c. . the input values are extracted and signor zero.s32) is specified in the instruction type. .h0. The type of each operand (.max }. // 32-bit scalar operation.9.add. . optionally clamp the result to the range of the destination type. . . atype.extended internally to .min. The general format of video instructions is as follows: // 32-bit scalar operation.asel}. . The sign of the intermediate result depends on dtype. 2010 .asel = . all combinations of dtype.bsel = { .asel}. 3.secop = { . vop.b2.dsel.h1 }. extract and sign. b{.atype.0 8. c.bsel}.btype{.7.sat} d. .PTX ISA Version 2. taking into account the subword destination size in the case of optional data merging.dtype. with optional data merge vop. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.s33 values.sat}. with optional secondary operation vop. a{.secop d. a{. Using the atype/btype and asel/bsel specifiers.b1. a{.u32.b3. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).u32 or .asel}. b{. Video Instructions All video instructions operate on 32-bit register operands.btype = { .

s33 optSecOp(Modifier secop. c). . The sign of the c operand is based on dtype. c). . . Bool sign. switch ( dsel ) { case .s33 tmp. . U32_MIN ). . tmp. tmp.b0. tmp. U16_MIN ). c).h0: return ((tmp & 0xffff) case . as shown in the following pseudocode. . U16_MAX. tmp. 2010 141 . . . Modifier dsel ) { if ( !sat ) return tmp. S16_MIN ). Instruction Set . Bool sat. U32_MAX. January 24. c).Chapter 8. U8_MIN ).b1: return ((tmp & 0xff) << 8) case .h1: return ((tmp & 0xffff) << 16) case .b0: return ((tmp & 0xff) case . c). c). tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).s33 optMerge( Modifier dsel. S32_MAX. S16_MAX. . .h0. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. } } .add: return tmp + c. c). . The lower 32-bits are then written to the destination operand.s34 tmp.min: return MIN(tmp. S32_MIN ). U8_MAX.s33 c ) switch ( dsel ) { case . default: return tmp. S8_MIN ).b2: return ((tmp & 0xff) << 16) case .b3: return ((tmp & 0xff) << 24) default: return tmp.s33 c) { switch ( secop ) { .s33 tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.b2.s33 optSaturate( .max return MAX(tmp. S8_MAX.b3: if ( sign ) return CLAMP( else return CLAMP( case .b1.

u32. c.s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vmax vadd.dtype.sat} d. r1. r3.vop .add r1. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.u32. Integer byte/half-word/word absolute value of difference. c ).h1 }. a{.op2 Description = = = = { vadd. vsub.atype.asel}. tb ).sat vsub.s32.bsel}.h1. vsub vabsdiff vmin. vmin. sat.s32 }.add.dtype.PTX ISA Version 2.b0. // optional merge with c operand 142 January 24. // extract byte/half-word/word and sign. { . . . bsel ). Video Instructions: vadd.s32. with optional secondary operation vop.btype{.s32.asel = . tmp = | ta – tb |. r3.h0. tb ). // 32-bit scalar operation. btype.bsel}. b{. vadd.btype = { . vabsdiff. with optional data merge vop. vabsdiff. dsel ). vop.u32.s32. a{.op2 d. r3. .sat} d.asel}. // optional secondary operation d = optMerge( dsel. vmin. r2.btype{. 2010 . Perform scalar arithmetic operation with optional saturate. . atype. .sat. vmax require sm_20 or later. // 32-bit scalar operation. c. r3. asel ). .asel}.dsel .dtype.max }.atype = .sat}. r2. taking into account destination type and merge operations tmp = optSaturate( tmp.dtype . r2. vabsdiff. a{. b{. .s32. .atype. vmin. c. c.h1.0. . r1. .b1.bsel}. Semantics // saturate.b2.or zero-extend based on source operand type ta = partSelectSignExtend( a. vmax }.b2. tb = partSelectSignExtend( b. vsub.sat vabsdiff. d = optSecondaryOp( op2. vmax Syntax Integer byte/half-word/word addition / subtraction.s32.h0.sat vmin.b0.atype.btype{. c ). tmp. isSigned(dtype). Integer byte/half-word/word minimum / maximum. tmp = MAX( ta.dsel.s32. .min. and optional secondary arithmetic operation or subword data merge. r2. tmp = MIN( ta.b0. vadd. b{. r1.s32.0 Table 105.s32. vsub.b3. tmp = ta – tb. tmp.bsel = { .h0.

vshr vshl. b{. . Instruction Set Table 106. and optional secondary arithmetic operation or subword data merge.u32. if ( mode == .wrap ) tb = tb & 0x1f. switch ( vop ) { case vshl: tmp = ta << tb. } // saturate. tb = partSelectSignExtend( b. vshr require sm_20 or later. . Left shift fills with zero.asel}. .sat}{.bsel}.dsel .or zero-extend based on source operand type ta = partSelectSignExtend( a. vshr Syntax Integer byte/half-word/word left / right shift.sat}{. case vshr: tmp = ta >> tb.dtype.s32 }. vshl.mode} d.u32{. r3. dsel ).asel}.u32.u32. and optional secondary arithmetic operation or subword data merge.u32. a{.min. asel ).u32.u32. vshr: Shift a right by unsigned amount in b with optional saturate. . .h0. atype. vshl.dtype.clamp. r2. . r3.dtype .wrap r1. c. with optional data merge vop.atype. a{. r1. bsel ). Video Instructions: vshl. vshr }. tmp. c ).bsel}.atype.u32{.max }. tmp.asel = . . isSigned(dtype). vshl: Shift a left by unsigned amount in b with optional saturate.b1.mode} d.atype. . // optional secondary operation d = optMerge( dsel. b{.bsel}. .0.atype = { . if ( mode == . d = optSecondaryOp( op2.Chapter 8. sat.wrap }. unsigned shift fills with zero. a{. with optional secondary operation vop. vop.clamp && tb > 32 ) tb = 32. Semantics // extract byte/half-word/word and sign. { . { . taking into account destination type and merge operations tmp = optSaturate( tmp.dsel.s32.op2 Description = = = = = { vshl. . // 32-bit scalar operation.add.mode . c. January 24.mode}. c ). r2.asel}.dtype.u32{.bsel = { .h1 }. // 32-bit scalar operation.b0. // default is .vop .sat}{.u32 vshr.h1.b3. .b2.clamp . Signed shift fills with the sign bit. .op2 d. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 143 . b{.

final signed (S32 * S32) . . . final signed (S32 * U32) + S32 // intermediate signed. which is used in computing averages. b{. final signed The intermediate result is optionally scaled via right-shift. {-}a{. Description Calculate (a*b) + c.scale} d. a{. That is. {-}b{. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. Input c has the same sign as the intermediate result. and zero-extended otherwise. . The “plus one” mode (.atype. final signed (U32 * U32) .h1 }.S32 // intermediate signed.b3.atype. the intermediate result is signed.po mode. final signed (U32 * S32) . .S32 // intermediate signed.scale} d.b1. and the operand negates.u32.asel = . .shr15 }. The source operands support optional negation with some restrictions. // 32-bit scalar operation vmad. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. final signed -(S32 * U32) + S32 // intermediate signed. “plus one” mode. .U32 // intermediate unsigned.b0. .dtype = . final signed -(S32 * S32) + S32 // intermediate signed.btype{.bsel}. and scaling.dtype. vmad. PTX allows negation of either (a*b) or c. final signed (S32 * S32) + S32 // intermediate signed. {-}c. 2010 . . with optional operand negates. . final signed (S32 * U32) .b2.0 Table 107.dtype.bsel}. 144 January 24. The final result is unsigned if the intermediate result is unsigned and c is not negated.sat}{.sat}{. final unsigned -(U32 * U32) + S32 // intermediate signed.h0.shr7.scale = { .asel}.asel}. c.bsel = { .po) computes (a*b) + c + 1. final signed -(U32 * S32) + S32 // intermediate signed. this result is sign-extended if the final result is signed. Depending on the sign of the a and b operands.btype = { . otherwise.s32 }. final signed (U32 * S32) + S32 // intermediate signed. Source operands may not be negated in . .S32 // intermediate signed. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.atype = ..PTX ISA Version 2. Although PTX syntax allows separate negation of the a and b operands. internally this is represented as negation of the product (a*b). The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.btype.po{. (a*b) is negated if and only if exactly one of a or b is negated.

-r3. S32_MAX.s32. atype.shr7: result = (tmp >> 7) & 0xffffffffffffffff. } if ( . r2. January 24. } else if ( c.negate ) { tmp = ~tmp.negate) || c.u32. r3.shr15: result = (tmp >> 15) & 0xffffffffffffffff. r1. 2010 145 .negate ^ b.or zero-extend based on source operand type ta = partSelectSignExtend( a. else result = CLAMP(result.shr15 r0. Instruction Set Semantics // extract byte/half-word/word and sign.negate ^ b. r0. U32_MIN).h0. lsb = 1. case .po ) { lsb = 1. S32_MIN).u32.sat ) { if (signedFinal) result = CLAMP(result.Chapter 8. } else if ( a.sat vmad. vmad.s32. switch( scale ) { case .negate ) { c = ~c. btype. U32_MAX. r2. tmp = tmp + c128 + lsb.0. bsel ). asel ).negate.u32. tmp[127:0] = ta * tb. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vmad requires sm_20 or later.h0.u32. signedFinal = isSigned(atype) || isSigned(btype) || (a. tb = partSelectSignExtend( b. r1. lsb = 1. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 0. if ( .

r2. with optional secondary arithmetic operation or subword data merge.0 Table 108. a{.b3. .cmp d.bsel}. vset.u32.btype. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. c ).u32. b{. r2. .atype.0. Semantics // extract byte/half-word/word and sign. r3. // optional secondary operation d = optMerge( dsel. bsel ).bsel}. .b1.s32 }.or zero-extend based on source operand type ta = partSelectSignExtend( a. The intermediate result of the comparison is always unsigned. asel ). tb = partSelectSignExtend( b.op2 d. 2010 . { . . .op2 Description = = = = . with optional secondary operation vset. r3.ne. with optional data merge vset.dsel . .btype. a{. . cmp ) ? 1 : 0. atype. and therefore the c operand and final result are also unsigned. .h1. vset requires sm_20 or later. tmp = compare( ta. b{.dsel. Compare input values using specified comparison.atype. tb. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c ).asel}.s32.ge }. a{.u32. r1. . // 32-bit scalar operation. tmp.asel = . .asel}.le. . { .cmp.asel}.eq.PTX ISA Version 2. .atype .u32.bsel = { .bsel}.h0. 146 January 24. .lt vset.ne r1.btype = { . btype.atype.b2. . d = optSecondaryOp( op2. c. c.b0.cmp . // 32-bit scalar operation.add.min. vset.lt. tmp. b{.max }.cmp d.gt.h1 }.btype.

there are sixteen performance monitor events. pmevent 7. January 24.0. Triggers one of a fixed number of performance monitor events. brkpt Suspends execution Introduced in PTX ISA version 1. brkpt requires sm_11 or later. Notes PTX ISA Notes Target ISA Notes Examples Currently. Supported on all target architectures. The relationship between events and counters is programmed via API calls from the host. Table 110.10. Table 111. trap. brkpt. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. with index specified by immediate operand a. Instruction Set 8.7. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. 2010 147 . Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.4. brkpt. Supported on all target architectures.0.Chapter 8. Introduced in PTX ISA version 1. trap Abort execution and generate an interrupt to the host CPU. pmevent a. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. @p pmevent 1. numbered 0 through 15. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Introduced in PTX ISA version 1. trap.

2010 .PTX ISA Version 2.0 148 January 24.

Chapter 9. 2010 149 . %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. which are visible as special registers and accessed through mov or cvt instructions. read-only variables. %lanemask_lt. %clock64 %pm0. …. %lanemask_gt %clock. Special Registers PTX includes a number of predefined. %lanemask_le. %pm3 January 24.

Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.v4.u32 type in PTX 2.%tid. // legacy PTX 1.z == 1 in 1D CTAs. per-thread special register initialized with the thread identifier within the CTA.%h2.z == 0 in 2D CTAs.%ntid.x.x. // move tid.sreg .u32 %r1.y == %tid. mov.%r0. %tid. read-only. // compute unified thread id for 2D CTA mov.y * %ntid.x * %ntid. The total number of threads in a CTA is (%ntid. or 3D vector to match the CTA shape.x.u16 %r2.y. Redefined as .u16 %rh.%tid. %tid.%h1.v4 . the %tid value in unused dimensions is 0.x code accessing 16-bit component of %tid mov.%tid.x. // CTA shape vector // CTA dimensions A predefined.sreg .u32 %ntid. .sreg .PTX ISA Version 2.x < %ntid.x. .%tid.u32 %r0. The fourth element is unused and always returns zero. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.0.u32 %r0.%tid. mov.u32 %ntid.z.y < %ntid.u32 type in PTX 2.y. . cvt. PTX ISA Notes Introduced in PTX ISA version 1. Redefined as . The %tid special register contains a 1D.x 0 <= %tid.0. 2010 . // zero-extend tid.u32 %h2.z.v4. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u32 %tid.x code Target ISA Notes Examples 150 January 24.z == 0 in 1D CTAs.y 0 <= %tid. The number of threads in each dimension are specified by the predefined special register %ntid. mad. %tid. CTA dimensions are non-zero.u16 %rh. %ntid. // thread id vector // thread id components A predefined.y == %ntid. mov. . the fourth element is unused and always returns zero. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.0 Table 112.0. mov. Supported on all target architectures. %ntid. Supported on all target architectures.x.%ntid.y.x.z to %r2 Table 113. Every thread in the CTA has a unique %tid. It is guaranteed that: 0 <= %tid. 2D.0.u32.z == 1 in 2D CTAs. %tid.z < %ntid. %tid component values range from 0 through %ntid–1 in each CTA dimension.u32 %tid. %ntid.v4 .z). read-only special register initialized with the number of thread ids in each CTA dimension.sreg .x to %rh Target ISA Notes Examples // legacy PTX 1. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.z PTX ISA Notes Introduced in PTX ISA version 1.z.u32 %h1. %ntid.

Table 115. Supported on all target architectures. The lane identifier ranges from zero to WARP_SZ-1. read-only special register that returns the thread’s lane within the warp. A predefined. read-only special register that returns the maximum number of warp identifiers. %warpid. e. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.u32 %nwarpid. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.g. Note that %warpid is volatile and returns the location of a thread at the moment when read. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Introduced in PTX ISA version 1. %laneid. read-only special register that returns the thread’s warp identifier.u32 %r. 2010 151 . A predefined. %nwarpid. but its value may change during execution. mov.u32 %r. Introduced in PTX ISA version 2. PTX ISA Notes Target ISA Notes Examples Table 116. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. . mov. mov. Supported on all target architectures.sreg . .u32 %laneid.sreg . Special Registers Table 114.0.sreg . For this reason. %nwarpid requires sm_20 or later.Chapter 9. Introduced in PTX ISA version 1. January 24.u32 %warpid.3.3. The warp identifier will be the same for all threads within a single warp.u32 %r. due to rescheduling of threads following preemption. . A predefined. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.

y < %nctaid. mov. Redefined as .x. // legacy PTX 1. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. read-only special register initialized with the number of CTAs in each grid dimension.u32 %nctaid. The %ctaid special register contains a 1D.y.sreg . or 3D vector.u32 type in PTX 2.536 PTX ISA Notes Introduced in PTX ISA version 1. . with each element having a value of at least 1.{x.v4. %rh.z.x. %ctaid.x. depending on the shape and rank of the CTA grid.v4 . .u32 %nctaid .u32 %ctaid. %rh.x code Target ISA Notes Examples Table 118.x 0 <= %ctaid.v4.0.u32 mov. Each vector element value is >= 0 and < 65535.z} < 65.x code Target ISA Notes Examples 152 January 24.u32 mov.%nctaid. Supported on all target architectures. The %nctaid special register contains a 3D grid shape vector. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. // CTA id vector // CTA id components A predefined.0 Table 117.sreg .y. It is guaranteed that: 1 <= %nctaid. . %ctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. read-only special register initialized with the CTA identifier within the CTA grid.0.y. // Grid shape vector // Grid dimensions A predefined.%nctaid.sreg .%ctaid.v4 . 2D. The fourth element is unused and always returns zero.z < %nctaid. It is guaranteed that: 0 <= %ctaid.u16 %r0.x < %nctaid.z.PTX ISA Version 2. Redefined as .%nctaid.%ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.%nctaid.u16 %r0.u32 %ctaid.u32 type in PTX 2.y 0 <= %ctaid. The fourth element is unused and always returns zero. 2010 . Supported on all target architectures.x.0.y.0. mov.sreg .x. // legacy PTX 1.z PTX ISA Notes Introduced in PTX ISA version 1.

0. Introduced in PTX ISA version 2.Chapter 9. 2010 153 . Supported on all target architectures. During execution. read-only special register initialized with the per-grid temporal grid identifier.0.g.sreg . . mov. due to rescheduling of threads following preemption. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. but its value may change during execution. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Note that %smid is volatile and returns the location of a thread at the moment when read.u32 %gridid. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.u32 %r. . Introduced in PTX ISA version 1. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. e.sreg . so %nsmid may be larger than the physical number of SMs in the device. PTX ISA Notes Target ISA Notes Examples January 24. // initialized at grid launch A predefined. PTX ISA Notes Target ISA Notes Examples Table 121. read-only special register that returns the maximum number of SM identifiers. %smid. The SM identifier numbering is not guaranteed to be contiguous. %gridid. The SM identifier ranges from 0 to %nsmid-1. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. mov. %nsmid requires sm_20 or later. . Special Registers Table 119. This variable provides the temporal grid launch number for this context.u32 %nsmid. Introduced in PTX ISA version 1. Supported on all target architectures. mov. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.u32 %r.u32 %r.sreg . The SM identifier numbering is not guaranteed to be contiguous. A predefined. repeated launches of programs may occur. Notes PTX ISA Notes Target ISA Notes Examples Table 120.3. A predefined. where each launch starts a grid-of-CTAs.u32 %smid. %nsmid.

%lanemask_eq requires sm_20 or later. 154 January 24.0.u32 %lanemask_eq.u32 %r.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %r.0.0. mov. %lanemask_lt. Introduced in PTX ISA version 2.u32 %r. Table 123.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.u32 %lanemask_lt. 2010 . Introduced in PTX ISA version 2. . Table 124.0 Table 122. Introduced in PTX ISA version 2. A predefined.u32 %lanemask_le. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined. . A predefined. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg . %lanemask_le requires sm_20 or later. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_le. %lanemask_eq.PTX ISA Version 2. mov. . mov.

0.u32 %lanemask_gt. %lanemask_ge. %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg . A predefined. mov. %lanemask_ge requires sm_20 or later. . January 24.u32 %r. Introduced in PTX ISA version 2.sreg .u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. 2010 155 . mov. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.0.Chapter 9. . A predefined.u32 %lanemask_ge. Table 126. Introduced in PTX ISA version 2. Special Registers Table 125. %lanemask_gt requires sm_20 or later.

%pm2. .u64 %clock64. mov. .%clock.u32 %clock. %pm1. Special Registers: %pm0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.sreg . . %pm3. %pm2.%pm0.3. Special registers %pm0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. read-only 64-bit unsigned cycle counter.u32 r1. %pm1. Table 129. Introduced in PTX ISA version 2.u32 %pm0.sreg .0.PTX ISA Version 2. and %pm3 are unsigned 32-bit read-only performance monitor counters. Introduced in PTX ISA version 1. Table 128.0.0 Table 127. 2010 . read-only 32-bit unsigned cycle counter. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. mov. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. …. The lower 32-bits of %clock64 are identical to %clock. Introduced in PTX ISA version 1.sreg . %pm1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm3 %pm0. Supported on all target architectures. 156 January 24. Their behavior is currently undefined. mov.u64 r1.%clock64.u32 r1. %pm2. Supported on all target architectures. %clock64 requires sm_20 or later.

version 2. Each ptx file must begin with a . .target Table 130. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version .0. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. PTX File Directives: .version 1. 2010 157 . Duplicate . and the target architecture for which the code was generated. Supported on all target architectures.1.minor // major.version major.version .version directive. Directives 10.Chapter 10.0 . . Increments to the major number indicate incompatible changes to PTX. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.version Syntax Description Semantics PTX version number. .version directives are allowed provided they match the original .4 January 24. minor are integers Specifies the PTX language version number.version directive.

immediately followed by a .0 Table 131.0.red}. map_f64_to_f32 }.samplerref descriptors.target Syntax Architecture and Platform target. 2010 . 64-bit {atom. Texturing mode introduced in PTX ISA version 1. sm_10. Disallows use of map_f64_to_f32. Requires map_f64_to_f32 if any .texmode_unified) .texmode_independent texture and sampler information is bound together and accessed via a single .global. A .f64 storage remains as 64-bits. Each PTX file must begin with a . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. In general. but subsequent . Adds {atom. texmode_unified. PTX code generated for a given target can be run on later generation devices. Requires map_f64_to_f32 if any .f64 to .f64 instructions used.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. including expanded rounding modifiers. sm_12. PTX features are checked against the specified target architecture. brkpt instructions. sm_13. PTX File Directives: . 158 January 24. Supported on all target architectures.target directive specifies a single target architecture. Requires map_f64_to_f32 if any . sm_11.texmode_unified .version directive. The texturing mode is specified for an entire module and cannot be changed within the module. texture and sampler information is referenced with independent . Therefore. with only half being used by instructions converted from .f64 instructions used. A program with multiple .f32. Target sm_20 Description Baseline feature set for sm_20 architecture. Texturing mode: (default is .texref and .texref descriptor. generations of SM architectures follow an “onion layer” model.5. .global. Description Specifies the set of features in the target architecture for which the current ptx code was generated. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. The following table summarizes the features in PTX that vary according to target architecture. vote instructions.shared.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.target directive containing a target architecture and optional platform options. Introduced in PTX ISA version 1.red}. Note that .PTX ISA Version 2.target .target directives can be used to change the set of target features allowed during parsing. Adds double-precision support.red}.f64 instructions used. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. texmode_independent. and an error is generated if an unsupported feature is used. Adds {atom. where each generation adds new features and retains all features of previous generations.

texmode_independent January 24.Chapter 10.target sm_13 // supports double-precision .target sm_20.target sm_10 // baseline target architecture . Directives Examples . 2010 159 .

2.PTX ISA Version 2. .g.param . .entry filter ( . parameters.reg . opaque . . 160 January 24.0 10.b32 %r1.samplerref.b32 z ) Target ISA Notes Examples [x]. In addition to normal parameters. PTX ISA Notes For PTX ISA version 1.func Table 132. For PTX ISA versions 1.b32 %r<99>.entry .b32 %r3. . Parameters may be referenced by name within the kernel body and loaded into registers using ld.4 and later. ld. Supported on all target architectures. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. ld. parameter variables are declared in the kernel body. parameter variables are declared in the kernel parameter list.param.0 through 1.param space memory and are listed within an optional parenthesized parameter list. and .b32 x.texref. %nctaid.entry kernel-name ( param-list ) kernel-body . e. Semantics Specify the entry point for a kernel program.0 through 1. … } . and body for the kernel function.param. These parameters can only be referenced by name within texture and surface load. [y]. the kernel dimensions and properties are established and made available via special registers. etc.entry Syntax Description Kernel entry point and body.5 and later.entry . ld.b32 %r2. with optional parameters.surfref variables may be passed as parameters. . [z]. 2010 .3. Parameters are passed via . store.entry cta_fft . . and query instructions and cannot be accessed via ld. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.b32 y.entry kernel-name kernel-body Defines a kernel entry point name.param instructions.param . The shape and size of the CTA executing the kernel are available in special registers. At kernel launch. Kernel and Function Directives: .4. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. %ntid.param instructions.param.param { .

Parameters must be base types in either the register or parameter state space.reg .f64 dbl) { .func (. Release Notes For PTX ISA version 1. } … call (fooval).b32 rval) foo (.Chapter 10. . PTX ISA 2.b32 localVar. (val0.0 with target sm_20 supports at most one return value. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . other code. PTX 2. foo. mov.result.param state space.func . dbl. if any. ret.reg .func (ret-param) fname (param-list) function-body Defines a function. Supported on all target architectures. The parameter lists define locally-scoped variables in the function body. there is no stack. val1). which may use a combination of registers and stack locations to pass parameters.0 with target sm_20 allows parameters in the .x code. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.b32 N. Variadic functions are represented using ellipsis following the last fixed argument. .0.param and st. parameters must be in the register state space.func fname (param-list) function-body .b32 rval. implements an ABI with stack. and supports recursion.reg . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. … use N. 2010 161 . Parameters in .func definition with no body provides a function prototype. Parameters in register state space may be referenced directly within instructions in the function body. A .reg .func fname function-body .param instructions in the body. Directives Table 133. including input and return parameters and optional function body.2 for a description of variadic functions.param space are accessed using ld. Variadic functions are currently unimplemented. Parameter passing is call-by-value.func Syntax Function definition. … Description // return value in fooval January 24. The implementation of parameter passing is left to the optimizing translator. Kernel and Function Directives: . and recursion is illegal.

Performance-Tuning Directives To provide a mechanism for low-level performance tuning. The directive passes a list of strings to the backend.maxntid.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.g.pragma directive is supported for passing information to the PTX backend. The directives take precedence over any module-level constraints passed to the optimizing backend.maxnreg .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. 2010 . The . the . registers) to increase total thread count and provide a greater opportunity to hide memory latency.maxnreg.minnctapersm directives may be applied per-entry and must appear between an .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). . A general .maxntid .3. and . The interpretation of . and the strings have no semantics within the PTX virtual machine model. . for example.PTX ISA Version 2.pragma The .pragma directives may appear at module (file) scope.maxntid and . and the . to throttle the resource requirements (e. Note that .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. 162 January 24.0 10.minnctapersm .maxntid directive specifies the maximum number of threads in a thread block (CTA).entry directive and its body. These can be used. or as statements within a kernel or device function body. at entry-scope. which pass information to the backend optimizing compiler. the .maxnctapersm (deprecated) . Currently. PTX supports the following directives. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.

Performance-Tuning Directives: . . 2010 163 .3. Exceeding any of these limits results in a runtime error or kernel launch failure. Performance-Tuning Directives: .entry foo . .maxntid 16. or 3D CTA.maxntid nx. The actual number of registers used may be less. the backend may be able to compile to fewer registers.maxntid nx.maxnreg . .maxntid 256 .maxnreg n Declare the maximum number of registers per thread in a CTA.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Supported on all target architectures. The maximum number of threads is the product of the maximum extent in each dimension. Directives Table 134. The compiler guarantees that this limit will not be exceeded.maxctapersm.3.16. This maximum is specified by giving the maximum extent of each dimention of the 1D.Chapter 10.maxntid Syntax Maximum number of threads in thread block (CTA). ny . Introduced in PTX ISA version 1.maxntid nx . nz Declare the maximum number of threads in the thread block (CTA).maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid and . . Introduced in PTX ISA version 1.maxntid .entry foo . for example. 2D. Supported on all target architectures. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.entry bar . ny.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. or the maximum number of registers may be further constrained by .

minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. However.maxntid and . Performance-Tuning Directives: .0 as a replacement for .maxntid 256 .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.0.maxnctapersm. Introduced in PTX ISA version 1.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. For this reason. 2010 .0.maxnctapersm (deprecated) .PTX ISA Version 2. Introduced in PTX ISA version 2. The optimizing backend compiler uses .maxntid to be specified as well.maxntid to be specified as well. Supported on all target architectures.minnctapersm in PTX ISA version 2.0 Table 136. if the number of registers used by the backend is sufficiently lower than this bound.entry foo .maxnctapersm has been renamed to .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.minnctapersm generally need . Optimizations based on . Deprecated in PTX ISA version 2.minnctapersm 4 { … } 164 January 24. Optimizations based on . . Performance-Tuning Directives: . .entry foo .maxnctapersm generally need . additional CTAs may be mapped to a single multiprocessor.maxntid 256 .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Supported on all target architectures. . .3. .minnctapersm .

pragma list-of-strings . Supported on all target architectures. { … } January 24.pragma . Introduced in PTX ISA version 2. Performance-Tuning Directives: . .0.entry foo .pragma directive strings is implementation-specific and has no impact on PTX semantics. Directives Table 138. entry-scoped. The interpretation of . 2010 165 .pragma Syntax Description Pass directives to PTX backend compiler. The . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . at entry-scope. Pass module-scoped.pragma “nounroll”. or statement-level directives to the PTX backend compiler. or at statementlevel.Chapter 10.pragma directive may occur at module-scope. . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma “nounroll”.

0x00 . “”. 0x00. The @@DWARF syntax is deprecated as of PTX version 2. 0x736d6172 . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .4byte label .2.section directive is new in PTX ISA verison 2.x code.section . 0x00.debug_pubnames. Deprecated as of PTX 2.0 but is supported for legacy PTX version 1. 0x5f736f63 . 0x02. 2010 .byte byte-list // comma-separated hexadecimal byte values . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .file .debug_info .. replaced by .quad int64-list // comma-separated hexadecimal integers in range [0.264-1] . 0x63613031.section directive. 0x61395a5f.232-1] . 0x00. @progbits .4.4byte . 0x00.4byte 0x6e69616d. 0x00000364. 0x00 166 January 24.PTX ISA Version 2. Table 139.. 0x6150736f.section .0.byte 0x2b. Supported on all target architectures. Introduced in PTX ISA version 1.4byte 0x000006b5. @@DWARF dwarf-string dwarf-string may have one of the . 0x00.loc The .4byte int32-list // comma-separated hexadecimal integers in range [0.byte 0x00.0 and replaces the @@DWARF syntax.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.0 10. 0x00.

. 0x00. 0x736d6172 0x00 Table 141. . 0x00.264-1] . } 0x02. . Directives Table 140. 0x00.section .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.debug_pubnames { . replaces @@DWARF syntax.file .0. 0x00..file filename Table 142.0.Chapter 10. 0x5f736f63 0x6150736f.b8 byte-list // comma-separated list of integers in range [0. 2010 167 .b32 . 0x00. Debugging Directives: . 0x00000364.232-1] . Debugging Directives: .section section_name { dwarf-lines } dwarf-lines have the following formats: .section Syntax PTX section definition. Source file location. 0x00 0x61395a5f.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 int32-list // comma-separated list of integers in range [0. 0x63613031.b8 0x2b. Source file information.b32 label . .debug_info . Supported on all target architectures.b32 0x000006b5. . .0. Supported on all target architectures..section . .loc .b8 0x00.b64 int64-list // comma-separated list of integers in range [0.b32 0x6e69616d. Debugging Directives: .loc line_number January 24.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures. .255] . 0x00.

visible Table 143. . Introduced in PTX ISA version 1.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Linking Directives: . Introduced in PTX ISA version 1.0 10. . 2010 .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.visible . .visible identifier Declares identifier to be externally visible.global .0.b32 foo.extern identifier Declares identifier to be defined externally.0.extern .extern .b32 foo. Linking Directives .visible . .PTX ISA Version 2.global . Supported on all target architectures.extern .6. Linking Directives: . // foo will be externally visible 168 January 24. // foo is defined in another module Table 144. Supported on all target architectures.

0 driver r195 PTX ISA Version PTX ISA 1.4 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.5 PTX ISA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 CUDA 1. The release history is as follows. CUDA Release CUDA 1.2 PTX ISA 1. 2010 169 .3 driver r190 CUDA 3.1 PTX ISA 1.0. and the remaining sections provide a record of changes in previous releases.3 PTX ISA 1.1 CUDA 2.0 PTX ISA 1.0 January 24.0 CUDA 2.2 CUDA 2.Chapter 11.1 CUDA 2.

sat modifiers. New Features 11.0 for sm_20 targets. The goal is to achieve IEEE 754 compliance wherever possible.and double-precision div.ftz and .f32 maps to fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2. The mad.0 11. The fma.1.x code and sm_1x targets.f32 and mad. rcp. Single-precision add.1.PTX ISA Version 2.rp rounding modifiers for sm_20 targets. • • • • • 170 January 24.f32 for sm_20 targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.ftz modifier may be used to enforce backward compatibility with sm_1x.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. mad. sub. The .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. These are indicated by the use of a rounding modifier and require sm_20.1. and sqrt with IEEE 754 compliant rounding have been added.0 11. Both fma. The mad.f32 requires sm_20. Changes in Version 2. Instructions testp and copysign have been added.1.f32.1. When code compiled for sm_1x is executed on sm_20 devices. The changes from PTX ISA 1. and mul now support .1.rn. Single. while maximizing backward compatibility with legacy PTX 1. fma.f32 require a rounding modifier for sm_20 targets. 2010 . A single-precision fused multiply-add (fma) instruction has been added. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rm and .f32 instruction also supports .

ldu. Other new features Instructions ld. and sust. prefetch. brev.add. 11.3.or}. has been added. atom. vote. January 24.red}. Release Notes 11.zero. . prefetchu. has been added.{and.Chapter 11. has been added. A new directive.gt} have been added.u32 and bar. %clock64.pred have been added.1. . The . A “find leading non-sign bit” instruction. %lanemask_{eq. has been added. Instructions {atom. Bit field extract and insert instructions.2. suld.le.section.popc.g. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. and shared addresses to generic address and vice-versa has been added. local. A “vote ballot” instruction. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.f32 have been implemented. popc. A “count leading zeros” instruction. Cache operations have been added to instructions ld. st.ballot. Instructions bar. A system-level membar instruction. Instruction cvta for converting global.arrive instruction has been added. has been added. cvta. The bar instruction has been extended as follows: • • • A bar.minnctapersm to better match its behavior and usage. bar now supports optional thread count and register operands.b32. New special registers %nsmid.shared have been extended to handle 64-bit data types for sm_20 targets. Instruction sust now supports formatted surface stores. Surface instructions support additional . ldu. bfind. for prefetching to specified level of memory hierarchy. bfe and bfi. st.red. has been added.1. isspacep. e.sys.1. have been added. clz.maxnctapersm directive was deprecated and replaced with .ge. Video instructions (includes prmt) have been added.clamp modifiers.1.red. A “population count” instruction.red}. membar. Instructions prefetch and prefetchu have also been added.clamp and . New instructions A “load uniform” instruction. A “bit reversal” instruction.lt. has been added. Instructions {atom. 2010 171 . and red now support generic addressing.

In PTX version 1. Formatted surface store with .4 or earlier.{u32. call suld. Instruction bra.2. Semantic Changes and Clarifications The errata in cvt. 2010 . where . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.target sm_1x. The underlying.s32.max} are not implemented.red}. Formatted surface load is unimplemented.1. if .{min.1. 172 January 24. Support for variadic functions and alloca are unimplemented.p sust.s32. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. To maintain compatibility with legacy PTX code. See individual instruction descriptions for details.3.5.PTX ISA Version 2.f32} atom.p. has been fixed.0 11.5 and later. the correct number is sixteen.u32. {atom.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. cvt.f32 type is unimplemented. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.version is 1. 11. stack-based ABI is unimplemented.f32. .ftz for PTX ISA versions 1.ftz (and cvt for . or .4 and earlier.

disables unrolling for all loops in the entry function body. The “nounroll” pragma is allowed at module. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. { … } // do not unroll any loop in this function .pragma Strings This section describes the . including loops preceding the .pragma “nounroll”. . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. disables unrolling of0 the loop for which the current block is the loop header. Supported only for sm_20 targets. and statement levels. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.pragma “nounroll”. … @p bra L1_end. Descriptions of .pragma. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma strings defined by ptxas.entry foo (…) . . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.pragma “nounroll”. L1_end: … } // do not unroll this loop January 24. 2010 173 . L1_body: … L1_continue: bra L1_head.0. Note that in order to have the desired effect at statement level.func bar (…) { … L1_head: . Table 145.Appendix A. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. entry-function. Ignored for sm_1x targets.

2010 .0 174 January 24.PTX ISA Version 2.

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