NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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..... Types .............. 6...............6.......................... 6......................4.................................................................................. 43 Labels and Function Names as Operands ..2..................1................................... 37 Variable Declarations ......................................................4........... 5............... 37 Vectors ................ 49 ii January 24............................... 6.1.............................4...3.................. 5....................................................................6..1..................................................................................1.......................3.........4....1..6.................................................................................... 27 5...................7...................................................... 33 Restricted Use of Sub-Word Sizes ..................... Sampler.............................. Chapter 6.................................................................................... 5........................................... 42 Addresses as Operands ..................................................................................................... State Spaces...................................... 5..... 41 Source Operands.........3....8. Operand Type Information .............................................. 33 5...............4.........................................................1..... 34 Variables .........................5........... 5..................... 2010 ............................................................... 29 Parameter State Space ............ 38 Initializers ............................................................... Abstracting the ABI .........PTX ISA Version 2........1.................5......... Types...................... 47 Chapter 7.............................. 38 Alignment ..............................................4.................. 5.............................................................. 6............................... Summary of Constant Expression Evaluation Rules .......................... 33 Fundamental Types ...2....4................. 29 Global State Space .....4............................................ 43 Vectors as Operands ....................2...........................6................. 5................................... State Spaces .. Arrays..5.... and Variables ........... 42 Arrays as Operands .........1....................2...........2........... 28 Constant State Space ...................................2........ 6.......................4................... 44 Scalar Conversions ............ Operand Costs .................. 28 Special Register State Space ........................4.......................................................1..3........................ 6............................................ 39 Parameterized Variable Names ........................................5........................ 41 Destination Operands ................... 5.......................................................2..............0 4.......................... 5.......... 27 Register State Space ................ 5... Type Conversion.................... 5............3.....................4................................................. 5. 6........4...............4................................................................................................................. 5........5..... Texture........... and Vectors .....................4............... 39 5................... 5.................... 6.............1...........2... 25 Chapter 5..................5..................... 43 6.......... 5...... 5..........................................................................1.............................................1............................................................................................. 41 Using Addresses...................................... and Surface Types ......................................... Function declarations and definitions ... 46 6......1...................................................................................... Instruction Operands.............................4...................... 44 Rounding Modifiers ..1........ 37 Array Declarations .................... 41 6................. 32 Texture State Space (deprecated) .. 30 Shared State Space...........................................1.............2.................................... 49 7.... 6............................... 29 Local State Space ..1... 32 5...................................................................

................................................ Special Registers ....3.................................3........ 169 11............................. 104 Data Movement and Conversion Instructions .. Instruction Set ..7................................7.....7............. 132 Video Instructions .. 172 Unimplemented Features Remaining ...1...................... 55 PTX Instructions ........................3.......................................... 129 Parallel Synchronization and Communication Instructions ........................ 55 Predicated Execution ............................1...x .... 52 Variadic functions ....................... 8. 58 8........................................................................ 162 Debugging Directives .........1.............. 56 Comparisons ....5.........................................................................................................................7...4.......6......................9....................................................................7...... 8.........1.......... 63 Integer Arithmetic Instructions ............ 122 Control Flow Instructions ........................................... 8............. 157 Specifying Kernel Entry Points and Functions .......... 8................... 57 Manipulating Predicates ................................................... 55 8........... PTX Version and Target Directives .................................................................... 10....... Changes in Version 2.........................1...........................................................0 .................................. Divergence of Threads in Control Constructs ................................... Type Information for Instructions and Operands ..................................................................... 8.............4.7.........................7....... 8...................................1................................... 60 8..........7........... 160 Performance-Tuning Directives .............................. 8.............. 7.......... 10......................... 100 Logic and Shift Instructions . 7...............................................7........ 10............1........2................................................................... 140 Miscellaneous Instructions...4..........................2.............6................. Changes from PTX 1.................3........................................... 59 Operand Size Exceeding Instruction-Type Size ................6....2..................... 11...................................... 8...... 8.. 11............................ 147 8.............. 149 Chapter 10........................5............................. 63 Floating-Point Instructions ...7...................................................... 8........................ 8.............................1........................ 157 10.............. 62 Machine-Specific Semantics of 16-bit Code .....................4..................................................................................................................................2. 170 New Features .................................................... 53 Alloca ......................1.................. 8......1.................3.................................................. 54 Chapter 8................ 62 Semantics ...................................... 168 Chapter 11...7............................3.....7.................... Release Notes ......................... Chapter 9............ 8........................................... 108 Texture and Surface Instructions ... 81 Comparison and Selection Instructions .....................................................................3.......................................................... 2010 iii .............................. 8....................................................................................10...........6.........1............ 10.......1................. 62 8............... 172 January 24.............................................. 170 Semantic Changes and Clarifications ........................... 8................................ Format and Semantics of Instruction Descriptions .......... Instructions .................. 11............................ Directives ...........................................7...... 8...... 166 Linking Directives .........................................................2.......1............................2..............................................8............................

........0 Appendix A.PTX ISA Version 2....... Descriptions of ..................... 2010 ..........pragma Strings.................... 173 iv January 24.

.. 58 Type Checking Rules ............ Table 9................... 66 Integer Arithmetic Instructions: mul ............ Table 17. Table 26............................. Table 10............................................... 20 Operator Precedence ....................... 59 Relaxed Type-checking Rules for Source Operands .. Table 6............................................................................................................................ Table 11.. Table 18.......... Table 2............. 58 Floating-Point Comparison Operators Testing for NaN ........................................... Table 12................................................................ Table 3.................... 67 Integer Arithmetic Instructions: mad ..................................... Table 23. 25 State Spaces .............. Table 4.................... 45 Floating-Point Rounding Modifiers .......................... 2010 v .................................... 57 Floating-Point Comparison Operators .....................................List of Tables Table 1............... 28 Fundamental Type Specifiers .................. Table 13.............................................. 66 Integer Arithmetic Instructions: subc . Table 22........... Table 28............................ PTX Directives ............... 60 Relaxed Type-checking Rules for Destination Operands.............................. Table 32..... 61 Integer Arithmetic Instructions: add ............................................................. Table 14.............. 64 Integer Arithmetic Instructions: sub ....................................................................... 57 Floating-Point Comparison Operators Accepting NaN . 47 Operators for Signed Integer. Table 15.................................... Table 30............................................... 18 Reserved Instruction Keywords ......... 68 Integer Arithmetic Instructions: mul24 .... 35 Convert Instruction Precision and Format .... 23 Constant Expression Evaluation Rules ............................ Table 5............................. Table 20..........................................................................................................................................................................................cc ......................................................... 70 Integer Arithmetic Instructions: sad ...........................cc ........ 46 Cost Estimates for Accessing State-Spaces ................................................................. Table 25. 65 Integer Arithmetic Instructions: sub............ 19 Predefined Identifiers .......................... 65 Integer Arithmetic Instructions: addc .................................................................................. Table 24.............. 35 Opaque Type Fields in Independent Texture Mode ........ 27 Properties of State Spaces .. Unsigned Integer...................................................................................................... Table 27... Table 31.. 69 Integer Arithmetic Instructions: mad24 .................................................................... Table 19......................... Table 21................ 64 Integer Arithmetic Instructions: add....................................................................................................... 46 Integer Rounding Modifiers ........................... 33 Opaque Type Fields in Unified Texture Mode ................................... 71 January 24........................... Table 29....................................................................................... Table 8............................................................................... Table 7......................................... Table 16............................ and Bit-Size Types ...................................................................................................................................

.. 90 Floating-Point Instructions: abs .................................................................. 77 Integer Arithmetic Instructions: bfi .................................. 82 Floating-Point Instructions: testp ........................ Table 41............................ Table 37.......................................... Table 66..... Table 42............................... 84 Floating-Point Instructions: sub ................ Table 55....................................................................... 102 Comparison and Selection Instructions: selp ...................................... 86 Floating-Point Instructions: fma .................................................................... 103 Comparison and Selection Instructions: slct ............... 79 Summary of Floating-Point Instructions ......... 78 Integer Arithmetic Instructions: prmt ............................ Table 60................................................. Table 50............................................ Table 43................................................................ 97 Floating-Point Instructions: lg2 .......................... 74 Integer Arithmetic Instructions: bfind .......................... Table 51....... Table 36............................ 93 Floating-Point Instructions: sqrt .................................................................................... Table 38.......... 75 Integer Arithmetic Instructions: brev ............................ Table 49...................................PTX ISA Version 2.................. 72 Integer Arithmetic Instructions: neg ............................................................................. 95 Floating-Point Instructions: sin ........................................ 76 Integer Arithmetic Instructions: bfe ............................. Table 61................ 72 Integer Arithmetic Instructions: min ............ 87 Floating-Point Instructions: mad ............................... Table 48.................. Table 64.................... Table 47...................................... 74 Integer Arithmetic Instructions: clz .......... 83 Floating-Point Instructions: add ....... 99 Comparison and Selection Instructions: set ...................................................................... Table 54........................................... 73 Integer Arithmetic Instructions: max .............................. 92 Floating-Point Instructions: max ......................... Table 62.... Table 35... 71 Integer Arithmetic Instructions: rem .................. Table 39........................................................................................ Table 68................................................................ Table 53...................................................................... Table 59............................................................................ Table 69...... Table 67................................................................................. Integer Arithmetic Instructions: div .................... 103 vi January 24................................................................................. 96 Floating-Point Instructions: cos ................................................. 94 Floating-Point Instructions: rsqrt ......... 71 Integer Arithmetic Instructions: abs ......................................... 92 Floating-Point Instructions: rcp ........................................................... 91 Floating-Point Instructions: min .............................................................................................................. 91 Floating-Point Instructions: neg ....... Table 45....................... 73 Integer Arithmetic Instructions: popc .......................... Table 44.................................................. Table 52....................................................................... 88 Floating-Point Instructions: div ....... 98 Floating-Point Instructions: ex2 .......... Table 57........................................... Table 63................ Table 65................................................. Table 46................................................ 85 Floating-Point Instructions: mul ................ 83 Floating-Point Instructions: copysign .............. 101 Comparison and Selection Instructions: setp .......... Table 56............ Table 40.............................................................................. Table 58......................................................................... 2010 .................................. Table 34..........................0 Table 33..........................................................

........................................... 105 Logic and Shift Instructions: xor .......... 125 Texture and Surface Instructions: sust .................................................................................. Table 95......................................... 139 Video Instructions: vadd..... 124 Texture and Surface Instructions: suld .............. 113 Data Movement and Conversion Instructions: ldu ....................................... Table 105..... Table 73. Table 104.............................................. Table 83........ Table 84.. 135 Parallel Synchronization and Communication Instructions: red .......................................... 133 Parallel Synchronization and Communication Instructions: membar ......................................... 2010 vii .................... Table 76.............. 131 Control Flow Instructions: exit ........................................Table 70.......... Table 101.......... Table 93.. 143 January 24... vsub................... 120 Texture and Surface Instructions: tex ............... 106 Logic and Shift Instructions: not ................. Table 90........................................ 116 Data Movement and Conversion Instructions: prefetch... Table 86.......... Table 88.................................................... 131 Parallel Synchronization and Communication Instructions: bar .................................. Table 80.............. Table 97........................................................................................ Table 75............................... Table 74................................... vshr ..... 128 Control Flow Instructions: { } ................. Table 72.................................... Table 87.......... Table 99................................................. 126 Texture and Surface Instructions: sured................................... 129 Control Flow Instructions: @ ................. 109 Cache Operators for Memory Store Instructions ..................... Table 102............................ 129 Control Flow Instructions: bra ....................... prefetchu ................................ vmax ................... Table 96.... Table 78.......... Table 89........................ Table 103......... 134 Parallel Synchronization and Communication Instructions: atom ................................ 115 Data Movement and Conversion Instructions: st .................. 106 Logic and Shift Instructions: shl ................................................................................................ 127 Texture and Surface Instructions: suq ........................................................................................................................ 130 Control Flow Instructions: ret ............... 106 Logic and Shift Instructions: cnot .......... vmin....................... 142 Video Instructions: vshl... Table 82................................... 111 Data Movement and Conversion Instructions: mov ................................. Table 98............. Table 81......................................................... 110 Data Movement and Conversion Instructions: mov ......... Table 94.................. 112 Data Movement and Conversion Instructions: ld ..... Table 85............................................ Table 106................ 119 Data Movement and Conversion Instructions: cvta ..... 119 Data Movement and Conversion Instructions: cvt ................................ Logic and Shift Instructions: and ............. 130 Control Flow Instructions: call ........ 123 Texture and Surface Instructions: txq .................... Table 100..... vabsdiff......... Table 92... 107 Cache Operators for Memory Load Instructions .................... 105 Logic and Shift Instructions: or ........ Table 77................................... 107 Logic and Shift Instructions: shr ........................................ Table 91........................................................................................................................ Table 71.................................... Table 79........................................................................ 137 Parallel Synchronization and Communication Instructions: vote .............. 118 Data Movement and Conversion Instructions: isspacep ...................................................................

..............minnctapersm ..entry.......................... 2010 ...... 167 Debugging Directives: ................................................................... Table 142................................. Table 112.............................. 160 Kernel and Function Directives: .................................................. 150 Special Registers: %ntid ............................. Table 124............................................................................ 156 Special Registers: %clock64 .......................................... Table 117.................. Table 138............................................... Table 116.............................file .................................. Table 127..... 150 Special Registers: %laneid ................... 154 Special Registers: %lanemask_lt ....................................... 152 Special Registers: %smid .......................... Table 141....................... 155 Special Registers: %clock ................................................... 153 Special Registers: %gridid ....................................... Table 114............... Table 140...................................................... 147 Special Registers: %tid ..................................................... 165 Debugging Directives: @@DWARF .................. Table 111.................................... 163 Performance-Tuning Directives: .................................func .... 144 Video Instructions: vset........maxnreg ............ 166 Debugging Directives: ..................................................... Table 113....................................... 164 Performance-Tuning Directives: ............................................................pragma ......................................... Video Instructions: vmad ............... %pm2....................... Table 132.................................. Table 122................ %pm3 .............................................loc ................. 156 PTX File Directives: ......target ......................................... Table 110.............................extern..section ...................... 158 Kernel and Function Directives: ............ 154 Special Registers: %lanemask_ge .............................................. 153 Special Registers: %lanemask_eq ........... Table 137............. 156 Special Registers: %pm0.............. 157 PTX File Directives: . Table 123.......................................................... Table 121............................ 151 Special Registers: %warpid ...................................................................................................................... Table 109............................... 154 Special Registers: %lanemask_le ................. 167 Linking Directives: ........................................................................... 168 viii January 24... Table 118.............................................maxnctapersm (deprecated) ........... 151 Special Registers: %ctaid ........................................................................... Table 126............. 147 Miscellaneous Instructions: brkpt .......................... 163 Performance-Tuning Directives: ................................. Table 133.........................................................maxntid ............................... %pm1.......... 167 Debugging Directives: ................................................................. 147 Miscellaneous Instructions: pmevent........... Table 108...................... Table 125................................. Table 128............................. Table 134.................version. Table 135............................................ Table 143............. Table 130......................PTX ISA Version 2... Table 136................................. Table 119................................... 152 Special Registers: %nctaid ....... 161 Performance-Tuning Directives: ................................................ Table 131.......... Table 120......... Table 139.......................................................... 151 Special Registers: %nwarpid ... 146 Miscellaneous Instructions: trap ............... 153 Special Registers: %nsmid . Table 115..........................................0 Table 107........... 164 Performance-Tuning Directives: ........................ Table 129......................................................... 155 Special Registers: %lanemask_gt ..................

................................... Table 145.................. 173 January 24.... Linking Directives: .................... 2010 ix ....................Table 144..................... 168 Pragma Strings: “nounroll” ....................................................visible.

PTX ISA Version 2.0 x January 24. 2010 .

which are optimized for and translated to native target-architecture instructions.2. PTX programs are translated at install time to the target hardware instruction set. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. 2010 1 . a low-level parallel thread execution virtual machine and instruction set architecture (ISA). PTX exposes the GPU as a data-parallel computing device. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. Introduction This document describes PTX. Because the same program is executed for each data element. multithreaded. In fact.1. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. the programmable GPU has evolved into a highly parallel. stereo vision. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. PTX defines a virtual machine and ISA for general purpose parallel thread execution. image scaling. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. many-core processor with tremendous computational horsepower and very high memory bandwidth. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. and pattern recognition can map image blocks and pixels to parallel processing threads. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Similarly. Data-parallel processing maps data elements to parallel processing threads. 1. the memory access latency can be hidden with calculations instead of big data caches. there is a lower requirement for sophisticated flow control. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. 1. video encoding and decoding. January 24. and because it is executed on many data elements and has high arithmetic intensity.Chapter 1. image and media processing applications such as post-processing of rendered images. high-definition 3D graphics. from general signal processing or physics simulation to computational finance or computational biology. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.

rp rounding modifiers for sm_20 targets. and the introduction of many new instructions. Achieve performance in compiled applications comparable to native GPU performance.ftz) modifier may be used to enforce backward compatibility with sm_1x.0 are improved support for IEEE 754 floating-point operations. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. surface.f32. When code compiled for sm_1x is executed on sm_20 devices.1. atomic. Most of the new features require a sm_20 target. which map PTX to specific target machines.f32 and mad. PTX ISA Version 2.0 is a superset of PTX 1.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Provide a code distribution ISA for application and middleware developers. Improved Floating-Point Support A main area of change in PTX 2.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Legacy PTX 1. including integer.rn.sat modifiers.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. sub. The changes from PTX ISA 1. and architecture tests. • • • 2 January 24. 2010 .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. and all PTX 1. addition of generic addressing to facilitate the use of general-purpose pointers.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.PTX ISA Version 2. PTX 2. memory. A “flush-to-zero” (.3.x features are supported on the new sm_20 target. and mul now support .ftz and .0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.f32 require a rounding modifier for sm_20 targets.f32 maps to fma. 1.f32 instruction also supports . The mad.f32 for sm_20 targets.3. The mad. reduction. Provide a machine-independent ISA for C/C++ and other compilers to target. mad. Single-precision add.f32 requires sm_20. 1.x code will continue to run on sm_1x targets as well. The main areas of change in PTX 2. Instructions marked with . and video instructions. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. fma. The fma. barrier.0 is in improved support for the IEEE 754 floating-point standard. Both fma.0 PTX ISA Version 2. Facilitate hand-coding of libraries.x. A single-precision fused multiply-add (fma) instruction has been added. Provide a common source-level ISA for optimizing code generators and translators. performance kernels.rm and .

stack-based ABI. Support for an Application Binary Interface Rather than expose details of a particular calling convention.0 closer to full compliance with the IEEE 754 standard. and Application Binary Interface (ABI). ldu.Chapter 1.e.3..clamp and .g. January 24.zero. so recursion is not yet supported. A new cvta instruction has been added to convert global. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Introduction • Single. e. rcp. and vice versa. Surface Instructions • • Instruction sust now supports formatted surface stores. special registers. and shared state spaces. an address that is the same across all threads in a warp. 1. stack layout. Surface instructions support additional clamp modifiers. prefetchu.3. In PTX 2.3. isspacep. and shared addresses to generic address and vice-versa has been added. instructions ld. and sqrt with IEEE 754 compliant rounding have been added. atom. Generic addressing unifies the global.3. local.4. 1. NOTE: The current version of PTX does not implement the underlying. Generic Addressing Another major change is the addition of generic addressing. allowing memory instructions to access these spaces without needing to specify the state space. local. .0 provides a slightly higher-level abstraction and supports multiple ABI implementations. PTX 2. 2010 3 . and sust. st. and directives are introduced in PTX 2. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. • Taken as a whole.2. i. Instructions testp and copysign have been added.0. 1. Instructions prefetch and prefetchu have been added.and double-precision div. These are indicated by the use of a rounding modifier and require sm_20. local. prefetch. Instruction cvta for converting global. Cache operations have been added to instructions ld. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. for prefetching to specified level of memory hierarchy. New Instructions The following new instructions. st. these changes bring PTX 2. and shared addresses to generic addresses. and red now support generic addressing.0. suld. cvta.

bar now supports an optional thread count and register operands.{and.popc.lt. %lanemask_{eq.PTX ISA Version 2. Instructions bar. A new directive. Reduction.pred have been added.ge. 4 January 24.red. and Vote Instructions • • • New atomic and reduction instructions {atom.b32.shared have been extended to handle 64-bit data types for sm_20 targets.section. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A “vote ballot” instruction. membar. 2010 . Instructions {atom. New special registers %nsmid. has been added.arrive instruction has been added.red}.u32 and bar.ballot. A bar.red}.sys.red.add. Other Extensions • • • Video instructions (includes prmt) have been added. %clock64.f32 have been added.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. has been added. .gt} have been added.le. Barrier Instructions • • A system-level membar instruction. bfi bit field extract and insert popc clz Atomic.or}. vote.

Chapter 5 describes state spaces. 2010 5 . calling convention. Chapter 7 describes the function and call syntax. January 24. Chapter 4 describes the basic syntax of the PTX language. Introduction 1. Chapter 9 lists special registers. and variable declarations. Chapter 11 provides release notes for PTX Version 2.Chapter 1.4. Chapter 3 gives an overview of the PTX virtual machine model. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. types.0. Chapter 6 describes instruction operands. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 10 lists the assembly directives supported in PTX. Chapter 8 describes the instruction set.

0 6 January 24.PTX ISA Version 2. 2010 .

y. It operates as a coprocessor to the main CPU. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. 2D. 2. Each CTA has a 1D.Chapter 2. and select work to perform. Programs use a data parallel decomposition to partition inputs. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Cooperative thread arrays (CTAs) implement CUDA thread blocks.x. Programming Model 2. a portion of an application that is executed many times. or CTA.2. Each CTA thread uses its thread identifier to determine its assigned role. is an array of threads that execute a kernel concurrently or in parallel.2. or host: In other words. data-parallel. and tid. The vector ntid specifies the number of threads in each CTA dimension. but independently on different data. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.z) that specifies the thread’s position within a 1D.x.y. can be isolated into a kernel function that is executed on the GPU as many different threads. tid. or 3D CTA. compute addresses. 2. 2D. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Each thread has a unique thread identifier within the CTA. To coordinate the communication of the threads within the CTA. January 24. Threads within a CTA can communicate with each other. A cooperative thread array. (with elements tid. The thread identifier is a three-element vector tid. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. 2010 7 . work.z).1. and ntid. and results across the threads of the CTA. To that effect. or 3D shape specified by a three-element vector ntid (with elements ntid. ntid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. assign specific input and output positions. compute-intensive portions of applications running on the host are off-loaded onto the device. More precisely.1.

However. %ctaid. The host issues a succession of kernel invocations to the device. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). a warp has 32 threads. Typically. Threads within a warp are sequentially numbered. Each grid of CTAs has a 1D.0 Threads within a CTA execute in SIMT (single-instruction. or 3D shape specified by the parameter nctaid. depending on the platform. WARP_SZ. Some applications may be able to maximize performance with knowledge of the warp size. CTAs that execute the same kernel can be batched together into a grid of CTAs. %nctaid.2. The warp size is a machine-dependent constant. so PTX includes a run-time immediate constant. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Threads may read and use these values through predefined. Multiple CTAs may execute concurrently and in parallel. such that the threads execute the same instructions at the same time. multiple-thread) fashion in groups called warps. 8 January 24. or sequentially. A warp is a maximal subset of threads from a single CTA. because threads in different CTAs cannot communicate and synchronize with each other. read-only special registers %tid. and %gridid. 2. This comes at the expense of reduced thread communication and synchronization. 2D . Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. %ntid.2. so that the total number of threads that can be launched in a single kernel invocation is very large. 2010 . which may be used in any instruction where an immediate operand is allowed. Each grid also has a unique temporal grid identifier (gridid).PTX ISA Version 2.

2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) CTA (2. 0) Thread (3. 0) Thread (1. 1) Thread (0. 1) Thread (4. 0) Thread (4. 1) CTA (1. 0) Thread (0. 0) CTA (1. Figure 1. Thread Batching January 24. 1) Thread (0.Chapter 2. 0) Thread (2. 0) CTA (0. 2010 9 . 2) Thread (1. 1) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. A grid is a set of CTAs that execute independently. 1) Thread (1. 2) Thread (2. 1) Grid 2 Kernel 2 CTA (1. 1) CTA (2. 1) Thread (3. 2) Thread (4. 2) Thread (3.

Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Both the host and the device maintain their own local memory. referred to as host memory and device memory. as well as data filtering. 10 January 24. 2010 .0 2.PTX ISA Version 2. The device memory may be mapped and read or written by the host. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. Texture memory also offers different addressing modes. or.3. respectively. Each thread has a private local memory. Finally. The global. all threads have access to the same global memory. constant. for some specific data formats. and texture memory spaces are persistent across kernel launches by the same application. and texture memory spaces are optimized for different memory usages. constant. for more efficient transfer. The global. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.

2) Figure 2. 0) Block (1. 1) Block (1. 1) Block (2. 1) Block (0. 1) Grid 1 Global memory Block (0. 2) Block (1. 2010 11 . 1) Block (1. 0) Block (0. 0) Block (0. 0) Block (1. 0) Block (2.Chapter 2. Memory Hierarchy January 24. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0.

2010 .PTX ISA Version 2.0 12 January 24.

the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. Parallel Thread Execution Machine Model 3. a voxel in a volume. and on-chip shared memory. The multiprocessor creates. schedules. the threads converge back to the same execution path. Branch divergence occurs only within a warp. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. it splits them into warps that get scheduled by the SIMT unit. manages. multiple-thread). new blocks are launched on the vacated multiprocessors. allowing. a multithreaded instruction unit. (This term originates from weaving. If threads of a warp diverge via a data-dependent conditional branch. and executes concurrent threads in hardware with zero scheduling overhead. The multiprocessor SIMT unit creates.Chapter 3.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. different warps execute independently regardless of whether they are executing common or disjointed code paths. At every instruction issue time. It implements a single-instruction barrier synchronization. the first parallel thread technology. When a host program invokes a kernel grid. disabling threads that are not on that path. and executes threads in groups of parallel threads called warps. A warp executes one common instruction at a time. When a multiprocessor is given one or more thread blocks to execute. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. manages. January 24. The multiprocessor maps each thread to one scalar processor core. so full efficiency is realized when all threads of a warp agree on their execution path. The threads of a thread block execute concurrently on one multiprocessor. increasing thread IDs with the first warp containing thread 0. the warp serially executes each branch path taken. The way a block is split into warps is always the same. a cell in a grid-based computation). each warp contains threads of consecutive. As thread blocks terminate.1. 2010 13 . A multiprocessor consists of multiple Scalar Processor (SP) cores. the multiprocessor employs a new architecture we call SIMT (single-instruction. To manage hundreds of threads running several different programs. and when all paths complete. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). and each scalar thread executes independently with its own instruction address and register state. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. for example.

scalar threads. and writes to the same location in global memory for more than one of the threads of the warp. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. but the order in which they occur is undefined. write to that location occurs and they are all serialized. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. whereas SIMT instructions specify the execution and branching behavior of a single thread. require the software to coalesce loads into vectors and manage divergence manually. on the other hand. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. 2010 . the kernel will fail to launch. For the purposes of correctness. each read. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. but one of the writes is guaranteed to succeed. If an atomic instruction executed by a warp reads. A multiprocessor can execute as many as eight thread blocks concurrently. as well as data-parallel code for coordinated threads. which is a read-only region of device memory. 14 January 24. SIMT enables programmers to write thread-level parallel code for independent. modify. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor.PTX ISA Version 2. In contrast with SIMD vector machines. however. • The local and global memory spaces are read-write regions of device memory and are not cached.0 SIMT architecture is akin to SIMD (Single Instruction. Vector architectures. In practice. As illustrated by Figure 3. A key difference is that SIMD vector organizations expose the SIMD width to the software. which is a read-only region of device memory. the number of serialized writes that occur to that location and the order in which they occur is undefined. the programmer can essentially ignore the SIMT behavior. modifies. If there are not enough registers or shared memory available per multiprocessor to process at least one block. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance.

Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 . Figure 3. Hardware Model January 24.

PTX ISA Version 2.0 16 January 24. 2010 .

#else. Each PTX file must begin with a . The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.Chapter 4. Lines beginning with # are preprocessor directives. The following are common preprocessor directives: #include. 2010 17 . #define.2. 4. followed by a . whitespace is ignored except for its use in separating tokens in the language. Source Format Source files are ASCII text. #if. Comments in PTX are treated as whitespace. Comments Comments in PTX follow C/C++ syntax. 4. January 24. Pseudo-operations specify symbol and addressing management. #endif. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. The C preprocessor cpp may be used to process PTX source files. and using // to begin a comment that extends to the end of the current line. Syntax PTX programs are a collection of text source files. #line. PTX is case sensitive and uses lowercase for keywords. using non-nested /* and */ for comments that may span multiple lines. #ifdef. All whitespace characters are equivalent.target directive specifying the target architecture assumed. Lines are separated by the newline character (‘\n’).version directive specifying the PTX language version. See Section 9 for a more information on these directives.1.

0. 18 January 24.b32 add. r2.version . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. and is written as @p.global . All instruction keywords are reserved tokens in PTX. array[r1].minnctapersm . where p is a predicate register.0 4.b32 r1. . Instruction keywords are listed in Table 2.maxnreg .pragma .maxntid .maxnctapersm . ld.global start: .5. Instructions have an optional guard predicate which controls conditional execution. The destination operand is first. 2.b32 r1. followed by source operands.2.align .3. Directive Statements Directive keywords begin with a dot.shared .loc . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. written as @!p.section .visible 4. . Table 1. Statements A PTX statement is either a directive or an instruction.1.local .global. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. r1. and terminated with a semicolon.file PTX Directives .reg . or label names. constant expressions.b32 r1. r2. Examples: .extern .reg . shl. so no conflict is possible with user-defined identifiers.f32 array[N]. mov.param .func .const .sreg . %tid.f32 r2.3. address expressions.tex . Operands may be register variables.target . Statements begin with an optional label and end with a semicolon. 2010 . r2.x. The guard predicate may be optionally negated.3.entry .PTX ISA Version 2. The guard predicate follows the optional label and precedes the opcode.

Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.

PTX ISA Version 2. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.g. underscore. except that the percentage sign is not allowed.4. digits. listed in Table 3. 2010 . %pm3 WARP_SZ 20 January 24. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. dollar. Table 3. digits. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.0 4. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. The percentage sign can be used to avoid name conflicts. PTX allows the percentage sign as the first character of an identifier. or percentage character followed by one or more letters. or dollar characters. between user-defined variable names and compiler-generated names. Many high-level languages such as C and C++ follow similar rules for identifier names. …. or they start with an underscore. e.

2. or binary notation. there is no suffix letter to specify size.e.5. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.u64). Integer literals may be written in decimal. and bit-size types.1.e. the constant begins with 0d or 0D followed by 16 hex digits. i. hexadecimal.u64. floating-point. octal. When used in an instruction or data initialization. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. 4.s64 or the unsigned suffix is specified. The syntax follows that of C. 4. To specify IEEE 754 single-precision floating point values.. To specify IEEE 754 doubleprecision floating point values. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. integer constants are allowed and are interpreted as in C.5. i. Unlike C and C++. in which case the literal is unsigned (. the constant begins with 0f or 0F followed by 8 hex digits. Syntax 4. zero values are FALSE and non-zero values are TRUE. Type checking rules remain the same for integer. 0[fF]{hexdigit}{8} // single-precision floating point January 24. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.s64 or . each integer constant is converted to the appropriate size based on the data or instruction type at its use. the sm_1x and sm_20 targets have a WARP_SZ value of 32. For predicate-type data and instructions.. 2010 21 .5. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Constants PTX supports integer and floating-point constants and constant expressions. every integer constant has type . These constants may be used in data initialization and as operands to instructions. literals are always represented in 64-bit double-precision format. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. where the behavior of the operation depends on the operand types. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic.s64) unless the value cannot be fully represented in .Chapter 4. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. Floating-point literals may be written with an optional decimal point and an optional signed exponent.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

January 24, 2010

Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .u64 .6.u64 .u64) (.s64 .f64 : . 2010 25 .s64 .s64 .Chapter 4. .s64 . 2nd is .f64 use usual conversions . or .s64) + .5.s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 integer integer integer integer integer int ?. Table 5.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 .s64 .u64 .u64. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .u64 .s64 .f64 integer .f64 use usual conversions .f64 converted type .f64 use usual conversions .f64 converted type constant literal + ! ~ Cast Binary (. Syntax 4.u64 same as 1st operand .s64.f64 same as source .f64 integer .u64 1st unchanged.u64 .

PTX ISA Version 2. 2010 .0 26 January 24.

const . Name State Spaces Description Registers. Global memory. 5. pre-defined. Read-only. defined per-grid. The list of state spaces is shown in Table 4. and Variables While the specific resources available in a given target GPU will vary. Global texture memory (deprecated). or Function or local parameters. and level of sharing between threads. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. read-only memory. . private to each thread.shared . All variables reside in some state space. access speed.local .reg . fast. Kernel parameters. shared by all threads. Table 6.1. State Spaces.Chapter 5. access rights. 2010 27 . State Spaces A state space is a storage area with particular characteristics. Local memory. addressability. Special registers.sreg . platform-specific. and these resources are abstracted in PTX through state spaces and data types.tex January 24.param . Types.global . the kinds of resources will be common across platforms. Addressable memory shared between threads in 1 CTA. The characteristics of a state space include its size. and properties of state spaces are shown in Table 5. defined per-thread. Shared.

.PTX ISA Version 2. 32-. 3 Accessible only via the tex instruction.reg . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. and performance monitoring registers.sreg . 5. and will vary from platform to platform. aside from predicate registers which are 1-bit. 32-. 64-. Address may be taken via mov instruction. Registers may be typed (signed integer. causing changes in performance. floating point. or 64-bits. it is not possible to refer to the address of a register.2. 16-. and thread parameters. st. The most common use of 8-bit registers is with ld. Register size is restricted. unsigned integer. platform-specific registers. CTA. and vector registers have a width of 16-.reg state space) are fast storage locations. clock counters. Registers may have alignment boundaries required by multi-word loads and stores. scalar registers have a width of 8-.param (used in functions) . Registers differ from the other state spaces in that they are not fully addressable. All special registers are predefined. predicate) or untyped.param instruction.local . Special Register State Space The special register (.1. register variables will be spilled to memory. Register State Space Registers (.0 Table 7. For each architecture. 2010 . and cvt instructions. or as elements of vector tuples. The number of registers is limited.e.sreg) state space holds predefined. 1 Accessible only via the ld.param and st.1. i.const . When the limit is exceeded.param (as input to kernel) .shared . via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Device function input parameters may have their address taken via mov. or 128-bits.global . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). such as grid.tex Restricted Yes No3 5.1.local state space. the parameter is then located on the stack frame and its address is in the . 2 Accessible via ld. 28 January 24.param instructions.

const[bank] modifier.b32 const_buffer[]. Constant State Space The constant (.Chapter 5. the store operation updating a may still be in flight. the declaration .1. Global memory is not sequentially consistent. [const_buffer+4]. an incomplete array in bank 2 is accessed as follows: . // load second word 5. All memory writes prior to the bar. The remaining banks may be used to implement “incomplete” constant arrays (in C. where bank ranges from 0 to 10. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. The constant memory is organized into fixed size banks. For example. results in const_buffer pointing to the start of constant bank two. the stack is in local memory. and atom.4.extern .5.global) state space is memory that is accessible by all threads in a context. Use ld. bank zero is used. 5.extern .1.3. Threads must be able to do their work without waiting for other threads to do theirs.local and st. For example. This reiterates the kind of parallelism available in machines that run PTX. It is the mechanism by which different CTAs and different grids can communicate. b = b – 1. Threads wait at the barrier until all threads in the CTA have arrived.1. Multiple incomplete array variables declared in the same bank become aliases.sync instruction are guaranteed to be visible to any reads after the barrier instruction. whereas local memory variables declared January 24.global to access global variables.const[2] . initialized by the host. all addresses are in global memory are shared. as it must be allocated on a perthread basis. It is typically standard memory with cache. If another thread sees the variable b change. bank zero is used for all statically-sized constant variables.global. In implementations that support a stack. each pointing to the start address of the specified constant bank. Types. This pointer can then be used to access the entire 64KB constant bank. Use ld. as in lock-free and wait-free style programming. Banks are specified using the .b32 const_buffer[]. ld. for example). the bank number must be provided in the state space of the load instruction.const) state space is a read-only memory. 2010 29 . Local State Space The local state space (. To access data in contant banks 1 through 10.local to access local variables. Global State Space The global (.local) is private memory for each thread to keep its own data. Module-scoped local memory variables are stored at fixed addresses. Sequential consistency is provided by the bar.sync instruction.global. State Spaces. For any thread in a context. Consider the case where one thread executes the following two assignments: a = a + 1. where the size is not known at compile time. st. If no bank number is given. and Variables 5. there are eleven 64KB banks. By convention.b32 %r1. For the current devices.const[2]. The size is limited.const[2] .

u32 %n.entry foo ( .u32 %n. typically for passing large structures by value to a function.6. mov. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. For example.PTX ISA Version 2.1.b32 N. 2010 .reg . The kernel parameter variables are shared across all CTAs within a grid.b32 len ) { . ld. The resulting address is in the .f64 %d.param. %n.param space variables.param space. ld. These parameters are addressable. PTX code should make no assumptions about the relative locations or ordering of . The use of parameter state space for device function parameters is new to PTX ISA version 2.f64 %d. ld. Note: The location of parameter space is implementation specific.param instructions.0 within a function or kernel body are allocated on the stack.param.param . Example: . Parameter State Space The parameter (.param instructions. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.u32 %ptr. len. … Example: .align 8 . Similarly. all local memory variables are stored at fixed addresses and recursive function calls are not supported. … 30 January 24.reg . In implementations that do not support a stack.entry bar ( .param) state space is used (1) to pass input arguments from the host to the kernel. Note that PTX ISA versions 1. Therefore.param state space and is accessed using ld. in some implementations kernel parameters reside in global memory. .param state space.u32 %ptr. [buffer].param .0 and requires target architecture sm_20.u32 %n.b8 buffer[64] ) { . 5.reg . The address of a kernel parameter may be moved into a register using the mov instruction.6. [N]. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. per-kernel versus per-thread). Values passed from the host to the kernel are accessed through these parameter variables using ld. device function parameters were previously restricted to the register state space. (2a) to declare formal input and return parameters for device functions called from within kernel execution. .param. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). read-only variables declared in the .x supports only kernel function parameters in . No access protection is provided between parameter and global space in this case. 5.param . [%ptr].1.1.

.param. Example: // pass object of type struct { double d. st. The most common use is for passing objects by value that do not fit within a PTX register. dbl.f64 [mystruct+0].reg . int y. and Variables 5. . . State Spaces.f64 %d. call foo. and so the address will be in the . x. … } // code snippet from the caller // struct { double d.6. Function input parameters may be read via ld. Note that the parameter will be copied to the stack if necessary. }. the caller will declare a locally-scoped .b8 buffer[12] ) { .s32 %y.s32 x.2. is flattened.reg . … See the section on function call syntax for more details. mystruct). [buffer+8]. int y.f64 dbl. In this case. Device Function Parameters PTX ISA version 2.local and st. … st.align 8 . ld. which declares a .param and function return parameters may be written using st.reg . . In PTX. (4.align 8 .f64 %d.param. it is illegal to write to an input parameter or read from a return parameter.param byte array variable that represents a flattened C structure or union. Types.func foo ( . .param space variable. It is not possible to use mov to get the address of a return parameter or a locally-scoped .param.b32 N. } mystruct.0 extends the use of parameter space to device function parameters.param formal parameter having the same size and alignment as the passed argument. . January 24. ld.reg .param. Typically. Aside from passing structures by value. passed to foo … . a byte array in parameter space is used.reg .local state space and is accessed via ld. This will be passed by value to a callee.1.b8 mystruct.s32 [mystruct+8]. such as C structures larger than 8 bytes.param .param.Chapter 5.param space is also required whenever a formal parameter has its address taken within the called function.s32 %y.local instructions. [buffer].param . 2010 31 . the address of a function input parameter may be moved into a register using the mov instruction.

Use ld.PTX ISA Version 2. tex_f.u32 tex_a. 2010 .7.tex .u32 . and programs should instead reference texture memory through variables of type .u32 .texref variables in the .u32 . Multiple names may be bound to the same physical texture identifier.8. Shared memory typically has some optimizations to support the sharing. is equivalent to . tex_d. An address in shared memory can be read and written by any thread in a CTA. where all threads read from the same address.texref tex_a.tex . tex_c.3 for the description of the .u32 tex_a.1.tex . One example is broadcast. The texture name must be of type .texref.tex variables are required to be defined in the global scope. See Section 5. Texture memory is read-only. Physical texture resources are allocated on a per-module granularity.tex directive is retained for backward compatibility. For example.tex) state space is global memory accessed via the texture instruction.texref type and Section 8. and .tex . a legacy PTX definitions such as .1.u32 or . where texture identifiers are allocated sequentially beginning with zero. tex_d.6 for its use in texture instructions. and variables declared in the . The . An error is generated if the maximum number of physical resources is exceeded.shared to access shared variables.tex directive will bind the named texture memory variable to a hardware texture identifier.tex .global . Another is sequential access from sequential threads.global state space. Texture State Space (deprecated) The texture (. A texture’s base address is assumed to be aligned to a 16-byte boundary. 32 January 24.7.u64.tex state space are equivalent to module-scoped .shared) state space is a per-CTA region of memory for threads in a CTA to share data. Shared State Space The shared (. 5. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).0 5.shared and st. The . It is shared by all threads in a context. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Example: .

.2. stored.f64 .f32 and .s32.b8 instruction types are restricted to ld.u8. and .u8. Types 5. .f32 and . and converted using regular-width registers. all variables (aside from predicates) could be declared using only bit-size types.pred Most instructions have one or more type specifiers.1.2. . Operand types and sizes are checked against instruction types for compatibility. January 24. The same typesize specifiers are used for both variable definitions and for typing instructions. State Spaces.f32. 2010 33 . In principle. . . . Register variables are always of a fundamental type. . The bitsize type is compatible with any fundamental type having the same size. .b64 .2.2. For convenience. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. the fundamental types reflect the native data types supported by the target architectures. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . and Variables 5.f16. but typed variables enhance program readability and allow for better operand type checking. Signed and unsigned integer types are compatible if they have the same size. .f16 floating-point type is allowed only in conversions to and from . so that narrow values may be loaded. . and instructions operate on these types. All floating-point instructions operate only on .u16. The following table lists the fundamental type specifiers for each basic type: Table 8.u32.Chapter 5. Fundamental Types In PTX. . 5. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. and cvt instructions. For example.f64 types. Two fundamental types are compatible if they have the same basic type and are the same size.f64 types. so their names are intentionally short. ld.b16. The .s8.s8.b32. needed to fully specify instruction behavior.s16.b8. or converted to other types and sizes. Types. st. A fundamental type specifies both a basic type and a size.s64 . Restricted Use of Sub-Word Sizes The . . stored.u64 . st.

accessing the pointer with ld and st instructions. For working with textures and samplers. 34 January 24.e.texref type that describe sampler properties are ignored.PTX ISA Version 2. and . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. suq).3. texture and sampler information is accessed through a single . and query instructions. In independent mode the fields of the .texref. Texture. base address. or surfaces via texture and surface load/store instructions (tex. In the unified mode. Creating pointers to opaque variables using mov.texref handle. and surface descriptor variables. PTX has two modes of operation. The following tables list the named members of each type for unified and independent texture modes. sured). store. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.surfref. i.u64} reg. but the pointer cannot otherwise be treated as an address. opaque_var. allowing them to be defined separately and combined at the site of usage in the program. Sampler.{u32. Referencing textures. sust. Retrieving the value of a named member via query instructions (txq. the resulting pointer may be stored to and loaded from memory.0 5. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. or performing pointer arithmetic will result in undefined results. but all information about layout. since these properties are defined by . hence the term “opaque”. and de-referenced by texture and surface load. samplers. .samplerref variables.. sampler. and Surface Types PTX includes built-in “opaque” types for defining texture.samplerref. The three built-in types are . and overall size is hidden to a PTX program. In the independent mode. These types have named fields similar to structures. field ordering. texture and sampler information each have their own handle. suld. passed as a parameter to functions. 2010 .

texref values in elements in elements in elements 0. clamp_to_border N/A N/A N/A N/A N/A . 1 ignored ignored ignored ignored . clamp_to_edge. and Variables Table 9. 1 nearest. clamp_ogl.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_ogl. mirror.samplerref values N/A N/A N/A N/A nearest. mirror. linear wrap. State Spaces. clamp_to_edge. 2010 35 . linear wrap. Member width height depth Opaque Type Fields in Independent Texture Mode .texref values . clamp_to_border 0.Chapter 5. Types. Member width height depth Opaque Type Fields in Unified Texture Mode .

. .param state space.global . . 36 January 24. When declared at module scope. Example: . As kernel parameters.texref tex1.global .global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists.texref my_texture_name.global state space. these variables are declared in the .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global .surfref my_surface_name.PTX ISA Version 2. 2010 . the types may be initialized using a list of static expressions assigning values to the named members. Example: .samplerref my_sampler_name. At module scope.global . filter_mode = nearest }. these variables must be in the .

its type and size. Variables In PTX. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.shared .v2.s32 i.v4 vector. Predicate variables may only be declared in the register state space. In addition to fundamental types. q.v4. vector variables are aligned to a multiple of their overall size (vector length times base-type size).f64 is not allowed. Types. 0. Examples: . an optional initializer. Vectors must be based on a fundamental type.v1. where the fourth element provides padding.4.u16 uv. // a length-4 vector of bytes By default.f32 bias[] = {-1.b8 v. .global .global . . // a length-2 vector of unsigned ints .u8 bg[4] = {0. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .0}.0. Vectors Limited-length vector types are supported.struct float4 coord.f32 v0. State Spaces.reg . . 5. PTX supports types for simple aggregate objects such as vectors and arrays.v4 .global .global . textures.f32 accel.v4. 1. .v3 }.pred p.f32 V. A variable declaration names the space in which the variable resides. and an optional fixed address for the variable. .reg .v2 . for example.Chapter 5. // typedef . 2010 37 . . its name.global .u32 loc. a variable declaration describes both the variable’s type and its state space. .4. 5. Variable Declarations All storage for data is specified with variable declarations.const . an optional array size. January 24. Three-element vectors may be handled by using a .4. // a length-4 vector of floats . Every variable must reside in one of the state spaces enumerated in the previous section. etc. Examples: . Vectors cannot exceed 128-bits in length. and Variables 5. This is a common case for three-dimensional grids.v2 or .reg .1. and they may reside in the register space. r. 0}.v4 .v4 .struct float4 { . 0.2.

label names appearing in initializers represent the address of the next instruction following the label.. . Similarly. 0}. 2010 .4. {0. 5. . For the kernel declaration above.05}.1.. or is left empty. Variable names appearing in initializers represent the address of the variable. being determined by an array initializer.shared . . {0. 1} }.u8 rgba[3] = {{1.s32 n = 10.1. 0}. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. 19*19 (361) halfwords are reserved (722 bytes).3.4.u16 kernel[19][19].0.0.local .u8 mailbox[128]. . {0.{. Array Declarations Array declarations are provided to allow the programmer to reserve space.global .b32 ptr = rgba. where the variable name is followed by an equals sign and the initial value or values for the variable. 38 January 24.1}. Here are some examples: .05}}.global .u64.u32 or .v4 .0.0}}.05..PTX ISA Version 2. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.1. this can be used to initialize a jump table to be used with indirect branches or calls.0}. The size of the dimension is either a constant expression. Variables that hold addresses of variables or instructions should be of type .1.s32 offset[][] = { {-1. .0.global . {1. variable initialization is supported only for constant and global state spaces.global .. // address of rgba into ptr Currently.4. A scalar takes a single value.{. -1}.05.0 5. Examples: .0}.f32 blur_kernel[][] = {{.1..global . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).4.pred.f16 and . Initializers are allowed for all types except . The size of the array specifies how many elements should be reserved.. {0. To declare an array. this can be used to statically initialize a pointer to a variable.

These 100 register variables can be declared as follows: . %r1. . %r99. Types. Examples: // allocate array at 4-byte aligned address. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.align 4 .0.const . it is quite common for a compiler frontend to generate a large number of register names. %r1..4. The variable will be aligned to an address which is an integer multiple of byte-count. Elements are bytes.. and Variables 5. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. nor are initializers permitted. not for individual elements. named %r0.0}. Array variables cannot be declared this way.0. Alignment is specified using an optional . ….5. .b32 %r<100>. 2010 39 .0.0.Chapter 5.2.b32 variables. of . // declare %r0. and may be preceded by an alignment specifier. say one hundred.4..6. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.b8 bar[8] = {0. Rather than require explicit declaration of every name. suppose a program uses a large number.align byte-count specifier immediately following the state-space specifier. January 24. For example. The default alignment for scalar and array variables is to a multiple of the base-type size.0. State Spaces.reg . 5. Parameterized Variable Names Since PTX supports virtual registers. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. alignment specifies the address alignment for the starting address of the entire array. The default alignment for vector variables is to a multiple of the overall vector size. For arrays.

PTX ISA Version 2.0 40 January 24. 2010 .

Instructions ld and st move data from/to addressable state spaces to/from registers.2. as its job is to convert from nearly any data type to any other data type (and size). The bit-size type is compatible with every type having the same size. The result operand is a scalar or vector variable in the register state space. b. 2010 41 . Integer types of a common size are compatible with each other.reg register state space. q. s. r. and c. The cvt (convert) instruction takes a variety of operand types and sizes. Instruction Operands 6.Chapter 6. Most instructions have an optional predicate guard that controls conditional execution. so operands for ALU instructions must all be in variables declared in the .3. January 24. . mov. the sizes of the operands must be consistent. and a few instructions have additional predicate source operands.1. Source Operands The source operands are denoted in the instruction descriptions by the names a. 6. st. Each operand type must be compatible with the type determined by the instruction template and instruction type. 6. There is no automatic conversion between types. The ld. For most operations. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The mov instruction copies data between registers. and cvt instructions copy data from one location to another. Operand Type Information All operands in instructions have a known type from their declarations. PTX describes a load-store machine. Predicate operands are denoted by the names p.

u32 42 January 24. The mov instruction can be used to move the address of a variable into a pointer.4.global .const . . All addresses and address computations are byte-based. address register plus byte offset. and Vectors Using scalar variables as operands is straightforward. q. Address expressions include variable names.reg .const.u16 x. there is no support for C-style pointer arithmetic. address registers. [V]. The interesting capabilities begin with addresses.f32 ld.gloal. The address is an offset in the state space in which the variable is declared. .s32 mov. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. p.s32 q. Examples include pointer arithmetic and pointer comparisons. 6. The syntax is similar to that used in many assembly languages.0 6.v4 . arrays.shared.[x]. tbl. Load and store operations move data between registers and locations in addressable state spaces. . .shared .u16 r0. .reg . and immediate address expressions which evaluate at compile-time to a constant address. Arrays.PTX ISA Version 2.b32 p. ld.4. Here are a few examples: . .s32 tbl[256].u16 ld.f32 V. r0. [tbl+12]. 2010 .f32 W.1. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. W.reg . Using Addresses.v4.v4 . and vectors.reg .

b.2. and tex. .a 6. Examples are ld.b and .g. d. If more complicated indexing is desired.c. for use in an indirect branch or call. ld. The expression within square brackets is either a constant integer.4. Rd}.3. January 24. Elements in a brace-enclosed vector.u32 s. Instruction Operands 6.global. a register variable.a. . a[1]. V2. Rb.b. Here are examples: ld.v2. . V.reg .c.f32 {a.v4.Chapter 6.4. [addr+offset]. Rc. where the offset is a constant expression that is either added or subtracted from a register variable. c.f32 ld. . a[N-1]. which may improve memory performance. or a braceenclosed list of similarly typed scalars. // move address of a[1] into s 6. mov. Vector loads and stores can be used to implement wide loads and stores. say {Ra.y V.x. ld.x V. it must be written as an address calculation prior to use. a[0]. The registers in the load/store operations can be a vector.z V. Array elements can be accessed using an explicitly calculated byte address.reg . 2010 43 .y. and the identifier becomes an address constant in the space where the array is declared. . as well as the typical color fields . Vectors may also be passed as arguments to called functions. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.r. or by indexing into the array using square-bracket notation.v4. st.4. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Vectors as Operands Vector operands are supported by a limited subset of instructions. b.4. which include mov.r V.f32 V.f32 a. Arrays as Operands Arrays of all types can be declared.u32 s.b V.w. The size of the array is a constant in the program.u32 s. Vector elements can be extracted from the vector with the suffixes . [addr+offset2].d}.z and .d}. and in move instructions to get the address of the label or function into a register.u32 {a.global.w = = = = V. or a simple “register with constant offset” expression. .global.v4 . mov.g V.global. A brace-enclosed list is used for pattern matching to pull apart vectors.

u16 instruction is given a u16 source operand and s32 as a destination operand. Type Conversion All operands to all arithmetic. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. Operands of different sizes or types must be converted prior to the operation. and ~131. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. For example. if a cvt.000 for f16).5. 2010 . the u16 is zero-extended to s32.s32. 44 January 24. and data movement instruction must be of the same type and size. except for operations where changing the size and/or type is part of the definition of the instruction.0 6.PTX ISA Version 2. 6.1. logic.5.

2010 45 . Instruction Operands Table 11. For example. Notes 1 If the destination register is wider than the destination format. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. the result is extended to the destination register width after chopping. f2s = float-to-signed. then sign-extend to 32-bits. cvt. January 24. u2f = unsigned-to-float.Chapter 6.s16. f2u = float-to-unsigned. The type of extension (sign or zero) is based on the destination format. f2f = float-to-float. chop = keep only low bits that fit.u32 targeting a 32-bit register will first chop to 16-bits. zext = zero-extend. s2f = signed-to-float.

Modifier . choosing even integer if source is equidistant between two integers. there are four integer rounding modifiers and four floating-point rounding modifiers.rmi . In PTX.rzi .rz .0 6. Modifier .rni .rn . The following tables summarize the rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.2.rpi Integer Rounding Modifiers Description round to nearest integer.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. Rounding Modifiers Conversion instructions may specify a rounding modifier.rm .PTX ISA Version 2. Table 12.5. 2010 .

Another way to hide latency is to issue the load instructions as early as possible. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Instruction Operands 6. first access is high Notes January 24. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Registers are fastest. 2010 47 . while global memory is slowest. Table 11 gives estimates of the costs of using different kinds of memory. Much of the delay to memory can be hidden in a number of ways. Operand Costs Operands from different state spaces affect the speed of an operation. Table 14. The register in a store operation is available much more quickly. as execution is not blocked until the desired result is used in a subsequent (in time) instruction.6.Chapter 6.

0 48 January 24.PTX ISA Version 2. 2010 .

or prototype.func foo { … ret. arguments may be register variables or constants. Abstracting the ABI Rather than expose details of a particular calling convention.func directive. Function declarations and definitions In PTX. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and an optional list of input parameters. Execution of the ret instruction within foo transfers control to the instruction following the call.Chapter 7. support for variadic functions (“varargs”). execution of the call instruction transfers control to foo. 2010 49 . and is represented in PTX as follows: . and return values may be placed directly into register variables. and memory allocated on the stack (“alloca”). The simplest function has no parameters or return values. NOTE: The current version of PTX does not implement the underlying.1. } … call foo. and Application Binary Interface (ABI). together these specify the function’s interface. stack layout. we describe the features of PTX needed to achieve this hiding of the ABI. so recursion is not yet supported. In this section. the function name. At the call. implicitly saving the return address. function calls. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Scalar and vector base-type input and return parameters may be represented simply as register variables. These include syntax for function definitions. A function declaration specifies an optional list of return parameters. 7. A function definition specifies both the interface and the body of the function. functions are declared and defined using the . … Here. parameter passing. stack-based ABI. January 24. A function must be declared or defined prior to being called.

.b32 c1. this structure will be flattened into a byte array.u32 %ptr.f64 field are aligned. [y+0]. ld. // scalar args in .param variable y is used in function definition bar to represent a formal parameter. [y+10].b8 c2. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .param space memory. passed by value to a function: struct { double dbl. st.c1.reg . inc_ptr. } { .func (.c3.align 8 py[12]. %ptr.param state space is used to pass the structure by value: .align 8 y[12]) { . In PTX.param.reg . ld. … st. 2010 . [y+8]. %inc.param . %rc1.b8 [py+ 8]. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .c4.b8 .0 Example: .u32 %res) inc_ptr ( . a . ld.param. c3.b8 c1. st. st.param. py).param. … ld.reg . char c[4]. … … // computation using x.param.b8 c4. %rc2. [y+11]. (%r1.f1. c4. Since memory accesses are required to be aligned to a multiple of the access size. %rd.reg . a . For example.b8 [py+11].s32 x.PTX ISA Version 2.4).param space call (%out).f64 f1.param . bumpptr. st.param. c2.reg space.reg . [y+9]. . }. Second.c2.func (. … In this example. note that .b64 [py+ 0]. } … call (%r1).f64 f1.reg . 50 January 24. byte array in .b8 [py+ 9].b8 c3. ld.s32 out) bar (.b8 . %rc2. . ret.param.param space variables are used in two ways.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.u32 %res.param. (%x. First.param. %rc1.param. consider the following C structure.b8 [py+10].reg .u32 %inc ) { add. The .

or constants. size. Supporting the .param memory must be aligned to a multiple of 1. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. 4. In the case of .Chapter 7.param or . or a constant that can be represented in the type of the formal parameter.param variables.. • • Arguments may be . . January 24.reg state space can be used to receive and return base-type scalar and vector values.param state space use in device functions.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. The . or 16 bytes. For a caller.reg state space in this way provides legacy support. or a constant that can be represented in the type of the formal parameter. a . Typically. size.param state space is used to receive parameter values and/or pass return values back to the caller.reg or .param or . The following restrictions apply to parameter passing.param space formal parameters that are base-type scalar or vector variables. A . 2.param space formal parameters that are byte arrays.g. For . all st.param byte array is used to collect together fields of a structure being passed by value. • • • Input and return parameters may be .param space byte array with matching type. For a caller.param arguments.reg space formal parameters. • The . The . In the case of . the corresponding argument may be either a . Parameters in .param state space is used to set values that will passed to a called function and/or to receive return values from a called function.param argument must be declared within the local scope of the caller. 2010 51 . This enables backend optimization and ensures that the . 8.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. the argument must also be a .param and ld.reg variables. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param instructions used for argument passing must be contained in the basic block with the call instruction. In the case of . the corresponding argument may be either a .reg space variable with matching type and size.reg variables. and alignment of parameters. Note that the choice of . • The .reg space variable of matching type and size.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variables or . For a callee. • • • For a callee. and alignment. Abstracting the ABI The following is a conceptual way to think about the .

x In PTX ISA version 1.reg state space. 2010 . PTX 2.1.x.param byte array should be used to return objects that do not fit into a register. PTX 2. PTX 1. In PTX ISA version 2.0 restricts functions to a single return value. 52 January 24. formal parameters may be in either .PTX ISA Version 2.reg or .0 7. and .x supports multiple return values for this purpose.1. Objects such as C structures were flattened and passed or returned using multiple registers. Changes from PTX 1. and there was no support for array parameters.0. formal parameters were restricted to .param state space.param space parameters support arrays. For sm_2x targets. and a .0 continues to support multiple return registers for sm_1x targets.

. bra Loop. for %va_arg64.reg .u32 align) .func ( . … %va_start returns Loop: @p Done: January 24.. ) { . … ) . the size may be 1. or 8 bytes.u32 ap.reg .func (. 2.reg . call (ap). %s2).u32 ptr. Once all arguments have been processed.func (. %va_start.s32 val.Chapter 7.reg . To support functions with a variable number of arguments. (2. setp. In PTX. ctr. and end access to a list of variable arguments.u32 align) .reg .u32 sz. . ctr.reg . 0x8000000.s32 result ) maxN ( . the alignment may be 1. val. iteratively access.u32 ptr. N. PTX provides a high-level mechanism similar to the one provided by the stdarg. (3.pred p. or 16 bytes. Variadic functions NOTE: The current version of PTX does not support variadic functions. call (val). call %va_end. maxN. 4.u32 N.u32 sz. %r3).reg . %r1.b32 ctr. variadic functions are declared with an ellipsis at the end of the input parameter list. // default to MININT mov. For %va_arg.reg . %r2. or 4 bytes. 8. . 0.u32. 2. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . 4..u32 a. .s32 result. result.b32 val) %va_arg (.b32 result. . 2010 53 .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. following zero or more fixed parameters: .func %va_end (.reg . (ap. 2.reg . .reg . (ap). ret.reg . %va_end is called to free the variable argument list handle. mov.ge p. .reg .reg . 4. %va_arg.u32 b.h headers in C. 4). In both cases.reg .reg . . This handle is then passed to the %va_arg and %va_arg64 built-in functions.b64 val) %va_arg64 (. } … call (%max). Abstracting the ABI 7.func okay ( … ) Built-in functions are provided to initialize.h and varargs. the size may be 1.u32 ptr) %va_start . … call (%max).func baz ( . along with the size and alignment of the next data value to be accessed. bra Done. The function prototypes are defined as follows: .reg . maxN. %s1.2.func (. max.

2010 . To allocate memory.0 7.3.local instructions. 54 January 24. a function simply calls the built-in function %alloca. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. Alloca NOTE: The current version of PTX does not support alloca. The array is then accessed with ld.reg .local and st.PTX ISA Version 2.u32 ptr ) %alloca ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.func ( . defined as follows: .reg . If a particular alignment is required. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.

The setp instruction writes two destination registers.2. setp. opcode D. opcode A. // p = (a < b). For some instructions the destination operand is optional. 8. q = !(a < b). January 24. 2010 55 . PTX Instructions PTX instructions generally have from zero to four operands. C. We use a ‘|’ symbol to separate multiple destination registers. while A. B. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. In addition to the name and the format of the instruction. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. Instruction Set 8. the D operand is the destination operand. A.Chapter 8. the semantics are described. followed by some examples that attempt to show several possible instantiations of the instruction.1. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. B.lt p|q. B.s32. b. and C are the source operands. opcode D. For instructions that create a result value. a. A. opcode D.

reg . The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.lt. As an example.PTX ISA Version 2. Predicated Execution In PTX.s32 p.pred p. use a predicate to control the execution of the branch or call instructions. q. Predicates are most commonly set as the result of a comparison performed by the setp instruction. 2010 .s32 j. j.0 8.pred as the type specifier. So. i. 1. To implement the above example as a true conditional branch. i. predicate registers can be declared as . add. where p is a predicate variable. optionally negated. the following PTX instruction sequence might be used: @!p L1: setp. … // compare i to n // if false. 1.s32 j. predicate registers are virtual and have . Instructions without a guard predicate are executed unconditionally. branch over 56 January 24. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. n. bra L1. This can be written in PTX as @p setp.s32 p.3. j.lt. // p = (i < n) // if i < n. consider the high-level code if (i < n) j = j + 1. add. add 1 to j To get a conditional branch or conditional function call. n.

1. Unsigned Integer. lt. 2010 57 . Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ne (not-equal). ordering comparisons are not defined for bit-size types. Table 16.3. Table 15. gt. ge. and hs (higher-or-same).1. and ge (greater-than-or-equal). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.Chapter 8. gt (greater-than). ls (lower-or-same). the result is false. If either operand is NaN. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).3. ne. Instruction Set 8.1.1. The following table shows the operators for signed integer. lt (less-than).3. le. Comparisons 8. ne.2. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. The unsigned comparisons are eq. unsigned integer. lo (lower). The bit-size comparisons are eq and ne. hi (higher). and bitsize types. le (less-than-or-equal).

leu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. or. 2010 .u32 %r1. ltu. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. not.3. for example: selp. xor.0 To aid comparison operations in the presence of NaN values. gtu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. setp can be used to generate a predicate from an integer. neu.%p. However. geu. and mov. // convert predicate to 32-bit value 58 January 24. num returns true if both operands are numeric values (not NaN).1. If both operands are numeric values (not NaN). then the result of these comparisons is true. Table 17. two operators num (numeric) and nan (isNaN) are provided.2. Table 18. If either operand is NaN.0. then these comparisons have the same result as their ordered counterparts. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. and nan returns true if either operand is NaN. and no direct way to load or store predicate register values.PTX ISA Version 2. unordered versions are included: equ. There is no direct conversion between predicates and integer values.

e. Type Checking Rules Operand Type . most notably the data conversion instruction cvt. and this information must be specified as a suffix to the opcode.uX . It requires separate type-size modifiers for the result and source. the add instruction requires type and size information to properly perform the addition operation (signed. float. i.4.u16 d. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. For example: . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.f32. Floating-point types agree only if they have the same size.Chapter 8. different sizes).uX ok ok ok inv . unsigned. and integer operands are silently cast to the instruction type if needed. 2010 59 . . a.u16 a.sX ok ok ok inv .u16 d. b. they must match exactly. For example.reg . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. b. For example. Example: . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.sX .bX .u16 d.. and these are placed in the same order as the operands.f32 d.reg . a. a.reg .fX ok ok ok ok January 24. Instruction Set 8. add. cvt.fX ok inv inv ok Instruction Type . Table 19. • The following table summarizes these type checking rules. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.bX . Signed and unsigned integer types agree provided they have the same size.

60 January 24. ld. 2010 .bX instruction types. unless the operand is of bit-size type. inv = invalid. 1. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type.1. parse error. so those rows are invalid for cvt. stored. for example. 2. Bit-size source registers may be used with any appropriately-sized instruction type. Floating-point source registers can only be used with bit-size or floating-point instruction types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. or converted to other types and sizes. floating-point instruction types still require that the operand type-size matches exactly. so that narrow values may be loaded. 4. The data is truncated to the instruction-type size and interpreted according to the instruction type. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. st. “-“ = allowed.0 8. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. When used with a narrower bit-size type. the data will be truncated. The following table summarizes the relaxed type-checking rules for source operands.4. stored. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. the size must match exactly. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Note that some combinations may still be invalid for a particular instruction. Operand Size Exceeding Instruction-Type Size For convenience. For example. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. the cvt instruction does not support . Source register size must be of equal or greater size than the instruction-type size.PTX ISA Version 2. When used with a floating-point instruction type. and converted using regular-width registers. Table 20. When a source operand has a size that exceeds the instruction-type size. Notes 3. no conversion needed.

2010 61 . When used with a narrower bit-size instruction type. 2. the data is sign-extended. The data is signextended to the destination register width for signed integer instruction types. the data is zeroextended. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. parse error. 4.Chapter 8. January 24. Destination register size must be of equal or greater size than the instruction-type size. “-“ = Allowed but no conversion needed. zext = zero-extend. Table 21. inv = Invalid. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. the data will be zero-extended. Floating-point destination registers can only be used with bit-size or floating-point instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. The following table summarizes the relaxed type-checking rules for destination operands. Notes 3. When used with a floatingpoint instruction type. the size must match exactly. Bit-size destination registers may be used with any appropriately-sized instruction type. the destination data is zero. 1.or sign-extended to the size of the destination register. If the corresponding instruction type is signed integer. The data is sign-extended to the destination register width for signed integer instruction types. Instruction Set When a destination operand has a size that exceeds the instruction-type size. otherwise. and is zero-extended to the destination register width otherwise.

so it is important to have divergent threads re-converge as soon as possible. These extra precision bits can become visible at the application level. 62 January 24. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. or conditional return. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 8.5. the semantics of 16-bit instructions in PTX is machine-specific. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.1. Both situations occur often in programs. The semantics are described using C. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. the optimizing code generator automatically determines points of re-convergence. by a right-shift instruction. If all of the threads act in unison and follow a single control flow path. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. the threads are called divergent. If threads execute down different control flow paths. For divergent control flow. using the . At the PTX language level. Therefore.0 8. When executing on a 32-bit data path. Divergence of Threads in Control Constructs Threads in a CTA execute together. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. until C is not expressive enough. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. 2010 . 16-bit registers in PTX are mapped to 32-bit physical registers. 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. the threads are called uniform. a compiler or code author targeting PTX can ignore the issue of divergent threads. However. until they come to a conditional control construct such as a conditional branch.6. for example.uni suffix.6. and for many applications the difference in execution is preferable to limiting performance. conditional function call. this is not desirable.PTX ISA Version 2. and 16-bit computations are “promoted” to 32-bit computations. for many performance-critical applications. A compiler or programmer may chose to enforce portable. at least in appearance.

cc.7. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.1.7. the optional guard predicate is omitted from the syntax. Instructions All PTX instructions may be predicated. In the following descriptions. addc sub. 8.Chapter 8.cc. 2010 63 . The Integer arithmetic instructions are: add sub add. Instruction Set 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.

u32.sat applies only to .sat limits result to MININT.MAXINT (no overflow) for the size of the operation.u32 x.s32 type. a.s64 }. // . PTX ISA Notes Target ISA Notes Examples 64 January 24.sat limits result to MININT.u32. add.s32 d. . add.sat applies only to .s32 type.b.PTX ISA Version 2.1. a.s32 c.. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.sat}. Applies only to . . Applies only to . Introduced in PTX ISA version 1.type add{. // . add Syntax Integer Arithmetic Instructions: add Add two values.u16.s32 .type = { .s16. d = a – b. . a. @p add. .type sub{.s16. d. . b.type = { . d = a + b.y.u16. . Saturation modifier: . PTX ISA Notes Target ISA Notes Examples Table 23. .c.a. b. sub. Saturation modifier: . Introduced in PTX ISA version 1.u64.s32 .sat.MAXINT (no overflow) for the size of the operation. sub. Supported on all target architectures.z. d. 2010 .0.0 Table 22. . Supported on all target architectures. .u64.s64 }. . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.sat}. b. b.0.. Description Semantics Notes Performs addition and writes the resulting value into a destination register. a.s32.s32 d.s32.s32 c.

z1.cc.y4. Supported on all target architectures. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc.y2.CF) holding carry-in/carry-out or borrowin/borrow-out. @p @p @p @p add. x4. a. These instructions support extended-precision integer addition and subtraction.b32 addc.b32 x1.type d.cc specified.z4.cc.z4. and there is no support for setting. .s32 }.y1. x4.cc.y2. carry-out written to CC.type d. 2010 65 . The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.2.Chapter 8. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc.CF. x3. .u32.cc. x3.b32 addc. clearing. d = a + b + CC. Behavior is the same for unsigned and signed integers.b32 addc. if .cc}. x2.b32 addc. b. Instruction Set Instructions add. b.cc. carry-out written to CC. x2.cc. addc.s32 }. No saturation.z2. No other instructions access the condition code. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.CF No integer rounding modifiers.y1.z3.y3. add. or testing the condition code. Behavior is the same for unsigned and signed integers.cc.2.b32 x1. Introduced in PTX ISA version 1.y4.b32 addc.z3.cc. d = a + b.z2. Table 24.cc Add two values with carry-out.y3. .cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.type = {.CF No integer rounding modifiers. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. .z1.b32 addc. No saturation. Introduced in PTX ISA version 1. add. Supported on all target architectures. sub.type = { . a. @p @p @p @p add.u32. addc{.cc Syntax Integer Arithmetic Instructions: add. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.

sub.CF No integer rounding modifiers. subc{.cc.y2. sub.b32 subc. Introduced in PTX ISA version 1.z2. d = a – b. 2010 .u32.PTX ISA Version 2. with borrow-out.b32 subc. borrow-out written to CC.y4. Supported on all target architectures.0 Table 26. x2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. Introduced in PTX ISA version 1. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.(b + CC.b32 subc.type = {.y3. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. x2. . withborrow-in and optional borrow-out. x3. Supported on all target architectures. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. Behavior is the same for unsigned and signed integers.cc.b32 subc.s32 }. d = a .b32 subc.b32 x1.cc.y3.z3. b.type = { .b32 subc. .y1. No saturation.cc.z2. x4.s32 }.cc.cc. a.cc. .z1.u32. if . x4.cc Syntax Integer Arithmetic Instructions: sub. @p @p @p @p sub.z3.type d.cc}.z4.z4. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. b.y4.z1.cc Subract one value from another.3. @p @p @p @p sub.cc.y1.3. a. borrow-out written to CC. x3.y2. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers.b32 x1.CF).cc.cc specified. . No saturation.type d.

n = bitwidth of type.wide is specified.x.fys.. then d is twice as wide as a and b to receive the full result of the multiplication.s64 }.y. mul.. // for . t = a * b.wide // for . .u64. .wide.u32.fxs. then d is the same size as a and b.s32. d = t. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. 2010 67 .lo.wide suffix is supported only for 16. Supported on all target architectures.and 32-bit integer types.wide.wide}.s16. mul.u16. . creates 64 bit result January 24. If .n>. If .0>. and either the upper or lower half of the result is written to the destination register.hi or .s16 fa. d = t<2n-1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Instruction Set Table 28. . mul{. .type = { . a.0. The .hi variant // for .s32 z.lo. . // 16*16 bits yields 32 bits // 16*16 bits..lo is specified. mul.fys. d = t<n-1.fxs.Chapter 8.hi. b.lo variant Notes The type of the operation represents the types of the a and b operands. save only the low 16 bits // 32*32 bits.. Description Semantics Compute the product of two values.s16 fa.type d.

and then writes the resulting value into a destination register.sat.s64 }.lo. Applies only to . b..u32..hi. and either the upper or lower half of the result is written to the destination register. a. 68 January 24. Supported on all target architectures.wide is specified. . Saturation modifier: .wide // for .sat limits result to MININT.s32 type in . c.lo variant Notes The type of the operation represents the types of the a and b operands.type mad.0> + c. mad.hi variant // for . bitwidth of type.hi mode.0. . . .PTX ISA Version 2. d.lo is specified. If .hi or .type = { .MAXINT (no overflow) for the size of the operation. .. // for . then d and c are twice as wide as a and b to receive the result of the multiplication.and 32-bit integer types. c.s32 r. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. t n d d d = = = = = a * b.wide}.u16. then d and c are the same size as a and b. t<2n-1.s32 d. t<n-1.b.c.a..0 Table 29. mad{.hi.u64..wide suffix is supported only for 16.p.lo.s16. If . t + c. The .s32. a.q.s32 d. 2010 .r. b.lo. @p mad. Description Semantics Multiplies two values and adds a third. .n> + c.

mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. d = t<31.s32 }. mul24.a.e. .. January 24. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. mul24. 2010 69 . mul24{.0>. All operands are of the same type and size. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type = { . Supported on all target architectures. mul24.s32 d.lo. i.hi.lo}.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result..u32.type d.Chapter 8. // for . t = a * b.b. // low 32-bits of 24x24-bit signed multiply. and return either the high or low 32-bits of the 48-bit result.0..hi may be less efficient on machines without hardware support for 24-bit multiply. b. 48bits. .lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.hi variant // for .lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.16>. Instruction Set Table 30. d = t<47. a. mul24.

// for .sat limits result of 32-bit signed addition to MININT.u32. d = t<47.16> + c. d.. Description Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d. // low 32-bits of 24x24-bit signed multiply.type = { .MAXINT (no overflow).lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.. mad24{.lo.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.. c.e.hi may be less efficient on machines without hardware support for 24-bit multiply.hi. All operands are of the same type and size. Saturation modifier: . mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.. 32-bit value to either the high or low 32-bits of the 48-bit result. a.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.s32 }. .sat. mad24. 48bits.0.s32 d. c.hi variant // for .hi.0> + c.hi mode. b.s32 type in . Return either the high or low 32-bits of the 48-bit result. mad24. and add a third.lo}. d = t<31. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. i. . mad24. Applies only to .a. 2010 .0 Table 31. 70 January 24. mad24.b.type mad24.c. t = a * b. b.PTX ISA Version 2. a. Supported on all target architectures.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b32) { max = 32. a = a << 1. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.type = { .b32 popc. the number of leading zeros is between 0 and 32. popc. a.type = { . inclusively. } while (d < max && (a&mask == 0) ) { d++.b64 }. . a. d = 0. 2010 . if (.0. a. cnt. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.b32. clz requires sm_20 or later.b64 }.PTX ISA Version 2.type d. .b64 d. For . X.type == .0 Table 39. mask = 0x8000000000000000. } else { max = 64.u32 PTX ISA Notes Target ISA Notes Examples Table 40. d = 0. popc Syntax Integer Arithmetic Instructions: popc Population count. // cnt is . a = a >> 1. inclusively.b64 d. For .type d.0. the number of leading zeros is between 0 and 64.b32. X. cnt.b64 type. clz.b32 clz.u32 Semantics 74 January 24. a. // cnt is . mask = 0x80000000. } Introduced in PTX ISA version 2. . .b32 type. while (a != 0) { if (a&0x1) d++. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. popc. clz. popc requires sm_20 or later.

d. // cnt is . bfind requires sm_20 or later. X.s32.s64 cnt. d = -1. . i--) { if (a & (1<<i)) { d = i. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. Operand a has the instruction type.shiftamt. break.Chapter 8. i>=0.u32. a. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.s64 }. for (i=msb.u64. For unsigned integers. and operand d has type . For signed integers. } } if (. Semantics msb = (. bfind returns 0xFFFFFFFF if no non-sign bit is found. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfind.shiftamt.u32 January 24.d. a.shiftamt && d != -1) { d = msb . 2010 75 . bfind returns the bit position of the most significant “1”. bfind. a.0.type==.u32 || .shiftamt is specified. .type d. .u32.type bfind. Instruction Set Table 41. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. If .type==.type = { . .s32) ? 31 : 63. bfind. Description Find the bit position of the most significant non-sign bit in a and place the result in d.u32 d.

} PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i<=msb. Description Semantics Perform bitwise reversal of input.0 Table 42.b32 d. .type = { . i++) { d[i] = a[msb-i]. 76 January 24.type==. 2010 . brev requires sm_20 or later.0. a. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.type d. brev. for (i=0.b64 }.b32) ? 31 : 63. brev.b32. . msb = (. a.PTX ISA Version 2.

s64 }.s32.u32. else sbit = a[min(pos+len-1. otherwise If the bit field length is zero. and operands b and c are type . i<=msb.s32) ? 31 : 63.type==.type==.u32. Operands a and d have the same type as the instruction type.0.type = { . and source c gives the bit field length in bits. . bfe requires sm_20 or later.Chapter 8.u64. Instruction Set Table 43. pos = b. d = 0.type d.type==. Source b gives the bit field starting bit position.start. . bfe. . the destination d is filled with the replicated sign bit of the extracted field. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . if (. . a. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. b. for (i=0.u64 || len==0) sbit = 0. If the start position is beyond the msb of the input.u32 || . .u64: .msb)]. The sign bit of the extracted field is defined as: .type==. Semantics msb = (. len = c. c. the result is zero.u32. bfe.b32 d.s32.a. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. 2010 77 .len. January 24. Description Extract bit field from a and place the zero or sign-extended result in d. The destination d is padded with the sign bit of the extracted field.u32 || .

and f have the same type as the instruction type. and place the result in f. and operands c and d are type . for (i=0. the result is b. c. len = d. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfi requires sm_20 or later. b.b32 d.PTX ISA Version 2.0 Table 44.u32.0. Source c gives the starting bit position for the insertion. 2010 .b32) ? 31 : 63.type = { . the result is b.type f. bfi. a. Semantics msb = (.b.b32. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. Operands a. and source d gives the bit field length in bits. i++) { f[pos+i] = a[i].start. If the start position is beyond the msb of the input. .a.type==. Description Align and insert a bit field from a into b. If the bit field length is zero.len. i<len && pos+i<=msb. bfi. 78 January 24. f = b. b. d. pos = c.b64 }.

The bytes in the two source registers are numbered from 0 to 7: {b. and reassemble them into a 32-bit destination register.b2 source select c[11:8] d. The msb defines if the byte value should be copied.Chapter 8. . b0}}.b4e. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). prmt. .rc8. msb=1 means replicate the sign. the permute control consists of four 4-bit selection values.mode} d. b4}. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. Description Pick four arbitrary bytes from two 32-bit registers.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. msb=0 means copy the literal value. {b3.ecl.b32{. a} = {{b7.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. . b. b6. Thus. Note that the sign extension is only performed as part of generic form. . . 2010 79 . . as a 16b permute code.rc16 }. the four 4-bit values fully specify an arbitrary byte permute. b5. Instruction Set Table 45.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. b1. In the generic form (no mode specified). prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. c. a.mode = { .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b1 source select c[7:4] d. b2.ecr. default mode index d.f4e.b3 source select c[15:12] d. a 4-bit selection value is defined. For each byte in the target register.

0 Semantics tmp64 = (b<<32) | a. tmp[31:24] = ReadByte( mode. r3. tmp[23:16] = ReadByte( mode. 80 January 24. r1. tmp64 ). // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[1] = (c >> 4) & 0xf. ctl[1]. r4. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp64 ). tmp[15:08] = ReadByte( mode.b32. ctl[3]. ctl[0].b32 prmt. } tmp[07:00] = ReadByte( mode.0. tmp64 ).f4e r1. r2. prmt. ctl[2]. ctl[2] = (c >> 8) & 0xf.PTX ISA Version 2. r2. r3. tmp64 ). 2010 . prmt requires sm_20 or later. ctl[3] = (c >> 12) & 0xf. r4. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3.

The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f32 and . 2010 81 .f64 register operands and constant immediate values. Instruction Set 8.2.7. Floating-Point Instructions Floating-point instructions operate on .Chapter 8.

sqrt}. NaN payloads are supported for double-precision instructions. Double-precision instructions support subnormal inputs and results.target sm_1x No rounding modifier.f64 and fma.approx.f32 {div.sat Notes If no rounding modifier is specified. .rcp.f32 {mad.f64 div.full.neg. Instruction Summary of Floating-Point Instructions .rnd. The optional .0 The following table summarizes floating-point instructions in PTX.min.rn and instructions may be folded into a multiply-add.lg2.rnd.f32 {add.mul}.rnd. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. 2010 .rp .rcp.rz .mul}.sqrt}.rn .f32 rsqrt.f32 {abs.PTX ISA Version 2. default is .max}.rm . 82 January 24. so PTX programs should not rely on the specific single-precision NaNs being generated.rcp. If no rounding modifier is specified.ex2}. with NaNs being flushed to positive zero.min.0.f64 rsqrt. .32 and fma. sub.0].f64 {sin.cos. {add.target sm_20 .ftz .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.approx.f32 {div.target sm_20 mad. Single-precision add.f64 mad.sqrt}.rnd.rnd. Note that future implementations may support NaN payloads for single-precision instructions. default is . and mad support saturation of results to the range [0.f64 {abs. mul.f64 are the same. No rounding modifier.neg.sub.rnd.max}.approx. {mad.f32 {div.sub.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. Table 46.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.rn and instructions may be folded into a multiply-add.f32 .fma}.approx. but single-precision instructions return an unspecified NaN.f32 are the same.fma}. 1.

normal. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . a. a. C. z. 2010 83 . .f32. true if the input is a subnormal number (not NaN. positive and negative zero are considered normal numbers.f64 isnan. .notanumber. . .infinite. b.type d. .notanumber.f64 x. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.type = { .f64 }. p.f32 copysign. // result is . testp.0. not infinity). not infinity) As a special case.type = { . B. Introduced in PTX ISA version 2.finite. .infinite. y.0.f32 testp.f64 }.pred = { . January 24. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.op p. Table 48.infinite testp.op. A.finite testp. testp Syntax Floating-Point Instructions: testp Test floating-point property.f32. X. .normal testp. testp. testp requires sm_20 or later. copysign.number. f0. . and return the result as d. copysign requires sm_20 or later.type .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.Chapter 8. testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. Instruction Set Table 47. copysign.notanumber testp.number testp.subnormal }.

f64 supports subnormal numbers. 1. add Syntax Floating-Point Instructions: add Add two values.rz. add{. Description Semantics Notes Performs addition and writes the resulting value into a destination register.rm mantissa LSB rounds towards negative infinity .f32.rm.0].rn mantissa LSB rounds to nearest even . add.rz.ftz.rnd = { .f32 supported on all target architectures. . .f32 f1.ftz. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. requires sm_13 for add.rn. NaN results are flushed to +0. d. add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b. Rounding modifiers (default is .ftz}{. sm_1x: add. subnormal numbers are supported.sat. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 flushes subnormal inputs and results to sign-preserving zero. . add. .f64 d.0.f32 clamps the result to [0.f3. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero. . d = a + b.0 Table 49.rm.rnd}{. 2010 . a.rn.f32 add{.sat}.f64.0. requires sm_20 Examples @p add.f64 requires sm_13 or later. add. a. 84 January 24.rnd}.f2. Rounding modifiers have the following target requirements: . add. Saturation modifier: .rn): .PTX ISA Version 2. In particular.0f. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. .rz available for all targets .rp for add. b.rp }.

f32 supported on all target architectures. Instruction Set Table 50. Rounding modifiers have the following target requirements: .f64 d. .f3.rn mantissa LSB rounds to nearest even .b. NaN results are flushed to +0.rnd}{. subnormal numbers are supported. d.rp for sub. b.rz available for all targets . .ftz}{. sub.sat. In particular.f32 f1. sub{.f64. d = a . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0]. requires sm_20 Examples sub.f32 sub{. sub. sub.rp }. .rz. sub.ftz.rm. a.0.a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sub Syntax Floating-Point Instructions: sub Subtract one value from another. 2010 85 . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.b. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64 requires sm_13 or later. Rounding modifiers (default is . .0.rn. .rn.f32 clamps the result to [0.rn): . sm_1x: sub. requires sm_13 for sub.rz mantissa LSB rounds towards zero .f32 c.f32.rm mantissa LSB rounds towards negative infinity .f2.ftz. Saturation modifier: sub.rn. .Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. 1.f64 supports subnormal numbers.rnd = { . sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. a.rm.rnd}. January 24.0f.sat}. b.

. b.f32 flushes subnormal inputs and results to sign-preserving zero. In particular.f32 clamps the result to [0.rp for mul.rz.f32 mul{.sat}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 d. 2010 . requires sm_20 Examples mul.f32 circumf.0. .f64 requires sm_13 or later.f32. d = a * b. Rounding modifiers (default is .rz mantissa LSB rounds towards zero . requires sm_13 for mul. mul Syntax Floating-Point Instructions: mul Multiply two values.rm.rm.pi // a single-precision multiply 86 January 24. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.0].rnd}. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm mantissa LSB rounds towards negative infinity .0. Rounding modifiers have the following target requirements: .rn): . For floating-point multiplication. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. b.rnd = { . mul.0 Table 51. a. mul.f64 supports subnormal numbers. a. mul.f32 flushes subnormal inputs and results to sign-preserving zero. Description Semantics Notes Compute the product of two values. mul{.rz available for all targets . sm_1x: mul.f64. d. all operands must be the same size. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. . Saturation modifier: mul.ftz. mul.0f.sat.rn.PTX ISA Version 2. .rp }.ftz. subnormal numbers are supported.rn.rn mantissa LSB rounds to nearest even . . NaN results are flushed to +0.ftz}{. 1. .radius.f32 supported on all target architectures.rnd}{.

Saturation: fma.f32 fma.rn.rnd. subnormal numbers are supported. . c. fma.4.ftz}{.rnd. 2010 87 .f32 introduced in PTX ISA version 2. Rounding modifiers (no default): . Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. d = a*b + c. fma Syntax Floating-Point Instructions: fma Fused multiply-add.rnd.rm.Chapter 8.rz. fma.0].0. c. fma.y.c. d. @p fma.rn mantissa LSB rounds to nearest even .f64 requires sm_13 or later.x. a.ftz.b. .f64. The resulting value is then rounded to double precision using the rounding mode specified by . a.sat.f64 w.ftz.rn. b. Instruction Set Table 52.f32 clamps the result to [0. b.f32 is unimplemented in sm_1x. fma.rnd{.f64 is the same as mad.f64 supports subnormal numbers. .f64 introduced in PTX ISA version 1. .z.f32 fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp }.rm mantissa LSB rounds towards negative infinity . d.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples January 24.a.f32 computes the product of a and b to infinite precision and then adds c to this product. NaN results are flushed to +0.f64 d.sat}. again in infinite precision. fma. fma. fma. sm_1x: fma.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 requires sm_20 or later.rnd = { .0.0f. 1. fma. fma. again in infinite precision.rn. The resulting value is then rounded to single precision using the rounding mode specified by . fma.rz mantissa LSB rounds towards zero .

// .rn mantissa LSB rounds to nearest even .0 Table 53.f32 mad. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.rm.f32. a. Rounding modifiers (no default): .target sm_13 and later .rn.ftz}{. again in infinite precision.f64 computes the product of a and b to infinite precision and then adds c to this product.rm mantissa LSB rounds towards negative infinity . where the mantissa can be rounded and the exponent will be clamped. .f32 computes the product of a and b at double precision. For . but the exponent is preserved.rnd. and then the mantissa is truncated to 23 bits. mad.rnd. For .ftz}{.{f32. // .0. mad. NaN results are flushed to +0. sm_1x: mad.PTX ISA Version 2.f64 computes the product of a and b to infinite precision and then adds c to this product.0f.target sm_1x d.f32 flushes subnormal inputs and results to sign-preserving zero.e.0. mad.rn. . mad. . mad. mad{..sat}. b. Unlike mad. mad.f64. Note that this is different from computing the product with mul.ftz.f64}. b.f64 d.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.rnd.f32 clamps the result to [0.rnd. Saturation modifier: mad.f32 mad. mad. again in infinite precision. and then writes the resulting value into a destination register. 1. fma. 2010 .ftz.rz.target sm_20: mad.target sm_1x: mad. In this case. c. The resulting value is then rounded to double precision using the rounding mode specified by .sat. When JIT-compiled for SM 2.rnd = { . mad.f32 is identical to the result computed using separate mul and add instructions.{f32.f32).target sm_20 d. // . The exception for mad.f64 is the same as fma. The resulting value is then rounded to double precision using the rounding mode specified by . b. d = a*b + c. subnormal numbers are supported.f32 is implemented as a fused multiply-add (i. a. c. mad. The resulting value is then rounded to single precision using the rounding mode specified by .f64} is the same as fma. Description Semantics Notes Multiplies two values and adds a third.rz mantissa LSB rounds towards zero .rp }. c. a.f32 is when c = +/-0.0 devices.sat}.f64 supports subnormal numbers.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. again in infinite precision. 88 January 24.0].f32 computes the product of a and b to infinite precision and then adds c to this product.rnd{. the treatment of subnormal inputs and output follows IEEE 754 standard.

f32 for sm_20 targets.f64.rp for mad. Legacy mad.f32 supported on all target architectures. In PTX ISA versions 1..rn.c.f64 requires sm_13 or later.f64. Rounding modifiers have the following target requirements: .rn.f64 instructions having no rounding modifier will map to mad.rn.0.rz..f32 d. requires sm_20 Examples @p mad. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.0 and later. a rounding modifier is required for mad.f32.a.rm.. mad.Chapter 8..b.rm. In PTX ISA versions 2. a rounding modifier is required for mad..rz. January 24.4 and later.rp for mad. Target ISA Notes mad. 2010 89 ..f64. requires sm_13 .

ftz.ftz}.ftz. Target ISA Notes div.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. stores result in d.full. approximate division by zero creates a value of infinity (with same sign as a).f32 and div. full-range approximation that scales operands to achieve better accuracy.f32 implements a relatively fast. b. div.f32 div.f32. div. a.ftz. Description Semantics Notes Divides a by b. Fast. .ftz}. . d. a. d. a. d = a / b.f32 div. one of .3.rnd{.0 through 1. For PTX ISA versions 1. Examples 90 January 24.ftz}.full. subnormal numbers are supported. but is not fully IEEE 754 compliant and does not support rounding modifiers.rz.full.{rz. yd. The maximum ulp error is 2 across the full range of inputs.f32 and div. x.full.rp }. Explicit modifiers .ftz. div.circum. or . // // // // fast. 2126]. div.approx. and rounding introduced in PTX ISA version 1.approx.f64 d.f64 introduced in PTX ISA version 1. sm_1x: div. b.rz mantissa LSB rounds towards zero .f64 supports subnormal numbers.f32 implements a fast approximation to divide.full. b.f32 defaults to div. .f64 requires sm_20 or later. div Syntax Floating-Point Instructions: div Divide one value by another. the maximum ulp error is 2. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 flushes subnormal inputs and results to sign-preserving zero. a.f64 diam.4. z.f32 flushes subnormal inputs and results to sign-preserving zero.rm.rm. div. . div.PTX ISA Version 2.full{.0 Table 54.rnd.0. 2010 .rp}. b.rn. computed as d = a * (1/b).approx.rm mantissa LSB rounds towards negative infinity .rnd is required.ftz.f64 requires sm_13 or later.f64 defaults to div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . PTX ISA Notes div.rnd = { . For PTX ISA version 1. approximate single-precision divides: div. .rn.f32 div.approx.approx{.f64.f32 requires sm_20 or later.rn.approx.f32 supported on all target architectures.3.14159.rnd.rn mantissa LSB rounds to nearest even . div. zd. d.f32 div. and div.4 and later. Subnormal inputs and results are flushed to sign-preserving zero. . Fast. div. div.approx. y. For b in [2-126.rn.f32 div. xd.

0.f32 flushes subnormal inputs and results to sign-preserving zero. Negate the sign of a and store the result in d.f32 flushes subnormal inputs and results to sign-preserving zero. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f64 requires sm_13 or later. abs. neg. sm_1x: abs. neg{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. January 24.f64 d.0.f64 supports subnormal numbers. d = -a. subnormal numbers are supported. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs.ftz.Chapter 8.f32 supported on all target architectures. neg. Table 56.f64 d. 2010 91 . a. NaN inputs yield an unspecified NaN. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f32 x. a. Instruction Set Table 55.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 neg.f32 abs. abs{. sm_1x: neg. Subnormal numbers: sm_20: By default.ftz}. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Take the absolute value of a and store the result in d. abs. abs. abs.f32 supported on all target architectures.ftz. a.f0. NaN inputs yield an unspecified NaN.ftz.f64 supports subnormal numbers. d. Subnormal numbers: sm_20: By default.f0. d.f32 x. neg.ftz}. neg. neg.f64 requires sm_13 or later. subnormal numbers are supported. d = |a|.

min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 d. (a < b) ? a : b.PTX ISA Version 2.f1. sm_1x: max. max{. b.ftz}.f32 supported on all target architectures.f64 requires sm_13 or later. Store the maximum of a and b in d.f32 max.b.0. subnormal numbers are supported. max. d. a.f64 z.x.ftz}.c. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 supports subnormal numbers. b. b.f64 f0. @p min.f32 min.b.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. 2010 . d.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. a. a.f32 max.f32 supported on all target architectures. Store the minimum of a and b in d. Table 58. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.ftz. b. min. a. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. min. min.f32 flushes subnormal inputs and results to sign-preserving zero. max. d d d d = = = = NaN. min. max.f64 requires sm_13 or later. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 min.c. max.f64 supports subnormal numbers.f64 d. sm_1x: min.z. subnormal numbers are supported. a.0 Table 57. (a > b) ? a : b. min{.0. a. b. max. d d d d = = = = NaN. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b.f2.ftz. 92 January 24.

0.rz mantissa LSB rounds towards zero .approx. a.f32 and rcp. store result in d.f64 requires sm_13 or later. rcp.rp}. xi. rcp.approx.rm mantissa LSB rounds towards negative infinity .rnd. rcp. rcp.4.approx or . rcp. .rnd.rp }.rnd{.0-2.f32 rcp.f64 defaults to rcp.rn.f32 defaults to rcp. . subnormal numbers are supported.f32 rcp. 2010 93 .f32 flushes subnormal inputs and results to sign-preserving zero.rn.rn mantissa LSB rounds to nearest even .4 and later.f32 rcp. Input -Inf -subnormal -0.0 +0. rcp. xi.approx.rn. Instruction Set Table 59. and rcp.0 +subnormal +Inf NaN Result -0.f64 introduced in PTX ISA version 1.rm.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . sm_1x: rcp. For PTX ISA versions 1.ftz}.f64. a.f32 requires sm_20 or later.ftz.0 over the range 1. .0 -Inf -Inf +Inf +Inf +0. General rounding modifiers were added in PTX ISA version 2.rnd is required. d.f32 flushes subnormal inputs and results to sign-preserving zero. one of . rcp.ftz. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.ftz.f64 requires sm_20 or later. d = 1 / a.3.f64 d. Examples January 24.approx{. d.0.rn. Target ISA Notes rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.r. rcp. rcp.{rz.approx.ftz}.f64 and explicit modifiers .rnd = { .ftz were introduced in PTX ISA version 1.Chapter 8.x. The maximum absolute error is 2-23.f32 implements a fast approximation to reciprocal.f32 rcp. For PTX ISA version 1.f64 ri. a. Description Semantics Notes Compute 1/a.rz.f64 supports subnormal numbers.x.approx and .f32.ftz.0 through 1.rn. // fast.rm.rn. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . PTX ISA Notes rcp.f32 supported on all target architectures. rcp.0.

f64 and explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. r.0. . The maximum absolute error for sqrt.approx and . sqrt. .f64.rz mantissa LSB rounds towards zero .f64 r.f32 and sqrt. 2010 .0 +0.4 and later.f64 requires sm_13 or later.ftz}.0 +0.rp}.x.0 +0.ftz.0 +subnormal +Inf NaN Result NaN NaN -0.ftz}. For PTX ISA version 1.x.approx.rnd. and sqrt. Examples 94 January 24.rnd{.rm.rm mantissa LSB rounds towards negative infinity . d = sqrt(a). sqrt.0 through 1.f64 requires sm_20 or later.3.f32 is TBD.f32 defaults to sqrt. // IEEE 754 compliant rounding d. sqrt.f32 requires sm_20 or later.rnd is required.rn. one of .approx{.f32 sqrt. a.f32 supported on all target architectures.rz. Description Semantics Notes Compute sqrt(a). store in d.f64 defaults to sqrt.ftz.ftz were introduced in PTX ISA version 1.0 -0. a.rn. For PTX ISA versions 1.4.f64 introduced in PTX ISA version 1.PTX ISA Version 2.ftz.approx or . sqrt.0. sqrt.rnd = { . sqrt.approx.rnd. sm_1x: sqrt.approx.f32 sqrt. // IEEE 754 compliant rounding .x. . r.rn. Target ISA Notes sqrt.f32 implements a fast approximation to square root.f32 sqrt. // fast. sqrt.f32 sqrt. sqrt.rn mantissa LSB rounds to nearest even . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. subnormal numbers are supported.0 Table 60. sqrt.approx.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx.rn.f64 supports subnormal numbers.ftz. sqrt.{rz. approximate square root d.rm.f64 d.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn.f32 flushes subnormal inputs and results to sign-preserving zero. a. Input -Inf -normal -subnormal -0. PTX ISA Notes sqrt. General rounding modifiers were added in PTX ISA version 2.rp }.rn.f32.

For PTX ISA version 1.f64 isr.0 through 1.ftz}. ISR.f32 flushes subnormal inputs and results to sign-preserving zero.approx.approx implements an approximation to the reciprocal square root.f32 and rsqrt. 2010 95 .approx.4 and later.ftz were introduced in PTX ISA version 1.0.Chapter 8.f64 defaults to rsqrt.ftz.ftz. Compute 1/sqrt(a).f64 supports subnormal numbers. the .f32 rsqrt.f32.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. Instruction Set Table 61.approx.0 +0. rsqrt. subnormal numbers are supported.f64 d.f32 supported on all target architectures. store the result in d. X.3.approx. Explicit modifiers .f32 defaults to rsqrt. For PTX ISA versions 1.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. rsqrt. rsqrt.4 over the range 1. d.f64 is TBD. The maximum absolute error for rsqrt.0 NaN The maximum absolute error for rsqrt.approx and .approx{.f64 is emulated in software and are relatively slow.f64 were introduced in PTX ISA version 1. rsqrt.0-4. a.f32 rsqrt.f32 is 2-22. sm_1x: rsqrt. x.ftz. rsqrt. Input -Inf -normal -subnormal -0.4. rsqrt.f64 requires sm_13 or later. Target ISA Notes Examples rsqrt. d = 1/sqrt(a). January 24.approx. a. Note that rsqrt. and rsqrt. PTX ISA Notes rsqrt. rsqrt.0.approx modifier is required.approx.f64. Subnormal numbers: sm_20: By default.

ftz. Explicit modifiers .approx modifier is required.f32 d.PTX ISA Version 2.4 and later. d = sin(a).approx.ftz}. PTX ISA Notes sin.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1.ftz.ftz introduced in PTX ISA version 1. sin. 2010 . Subnormal numbers: sm_20: By default. a. sin.approx and .0 +0.9 in quadrant 00. a.0 Table 62. Find the sine of the angle a (in radians).ftz. the .f32 implements a fast approximation to sine. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. For PTX ISA versions 1.0 NaN NaN The maximum absolute error is 2-20.approx.approx.f32 sa. sin. Input -Inf -subnormal -0.approx{.0 -0.4.0.0 +0.f32 introduced in PTX ISA version 1.f32 defaults to sin. sin.0 +subnormal +Inf NaN Result NaN -0.f32. Target ISA Notes Examples Supported on all target architectures.0 +0. subnormal numbers are supported. 96 January 24. For PTX ISA version 1. sin. sm_1x: Subnormal inputs and results to sign-preserving zero.3.

cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. cos. Input -Inf -subnormal -0.f32 ca. cos.ftz.0 through 1.0 +1.f32 implements a fast approximation to cosine.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes cos. sm_1x: Subnormal inputs and results to sign-preserving zero.0.9 in quadrant 00. a. For PTX ISA versions 1.0 +1. For PTX ISA version 1. January 24. Subnormal numbers: sm_20: By default.Chapter 8. cos. cos.4 and later.ftz}.f32. d = cos(a). Instruction Set Table 63.0 +subnormal +Inf NaN Result NaN +1. the .0 +1. subnormal numbers are supported.4.approx{.approx and . cos.f32 d.approx. a.ftz introduced in PTX ISA version 1. 2010 97 .approx.0 +0.f32 introduced in PTX ISA version 1.approx.3.ftz.0 NaN NaN The maximum absolute error is 2-20. Target ISA Notes Examples Supported on all target architectures. Find the cosine of the angle a (in radians). Explicit modifiers .ftz.approx modifier is required.f32 defaults to cos.

0. d = log(a) / log(2).3.ftz. lg2.f32 flushes subnormal inputs and results to sign-preserving zero.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.6 for mantissa.ftz}. For PTX ISA versions 1.approx{.ftz. lg2.4. 98 January 24.PTX ISA Version 2.4 and later.ftz introduced in PTX ISA version 1. a. Input -Inf -subnormal -0.f32.approx. lg2. lg2. sm_1x: Subnormal inputs and results to sign-preserving zero. a.approx.approx modifier is required.0 +0.f32 defaults to lg2. lg2. Explicit modifiers .0 through 1. subnormal numbers are supported. For PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures.approx. Subnormal numbers: sm_20: By default.f32 la.0 Table 64.f32 Determine the log2 of a.approx and .f32 implements a fast approximation to log2(a). PTX ISA Notes lg2. 2010 . the .ftz.f32 introduced in PTX ISA version 1. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. The maximum absolute error is 2-22.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

January 24, 2010

Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

f32 flushes subnormal inputs to sign-preserving zero. b.f32 flushes subnormal inputs to sign-preserving zero. gt.dtype. a.s16.0.BoolOp{.u32 p|q. .dtype. ge. p[|q]. and higher-or-same may be used instead of lt. and (optionally) combine this result with a predicate value by applying a Boolean operator. or. . .pred variables. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. . Applies to all numeric types.f64 source type requires sm_13 or later. The destinations p and q must be .0 Table 67.a.CmpOp{. and nan returns true if either operand is NaN. If both operands are numeric values (not NaN). p = BoolOp(t.type .u16.type = { . le. . nan The Boolean operator BoolOp(A. The comparison operator is a suffix on the instruction. then the result of these comparisons is true.PTX ISA Version 2. then these comparisons have the same result as their ordered counterparts.f32. This result is written to the first destination operand. If either operand is NaN.ftz applies only to .b. lo. geu.f64 supports subnormal numbers. lt. q = BoolOp(!t.ftz}. Subnormal numbers: sm_20: By default.lt.eq. gt. and hs for lower. higher. respectively. A related value computed using the complement of the compare result is written to the second destination operand. . For unsigned values. . b. geu.i. hi. lt. gtu. c). ge.f64 }. .b32. sm_1x: setp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. leu. unordered versions are included: equ. and can be one of: eq.b16. setp.u64. num returns true if both operands are numeric values (not NaN).s32. ge. bit-size comparisons are eq and ne.b64. . loweror-same. leu. ls. gtu. le. The signed and unsigned comparison operators are eq.r.type setp.ftz. le. gt. ne. le. .n. subnormal numbers are supported. To aid comparison operations in the presence of NaN values. 2010 . setp.dtype.B) is one of: and. ne. Semantics t = (a CmpOp b) ? 1 : 0. @q setp. ltu. Modifier . hs equ. neu. ge. Integer Notes Floating Point Notes The ordered comparisons are eq. setp with .ftz}.CmpOp. lt. ne. {!}c. setp. hi. The untyped. ltu. ls. gt. 102 January 24.s32 setp.f32 comparisons. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. num. If either operand is NaN.and.u32. p[|q]. c). p. the comparison operators lo. the result is false. xor. neu. a.s64.

u32.s16.s32 slct{. a is stored in d. based on the value of the predicate source operand.f64 requires sm_13 or later.f32 flushes subnormal values of operand c to sign-preserving zero. . .b16. If c ≥ 0. Operands d. Operand c is a predicate. For . the comparison is unordered and operand b is selected. C. d = (c >= 0) ? a : b.xp. . c.type d. The selected input is copied to the output without modification.u64. Table 69.g.dtype.ftz. b.f32. b.s64.f32 A. . b.u16. subnormal numbers are supported. and operand a is selected. . slct. . a. slct. b otherwise. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 r0.p.b16.t. z. 2010 103 .ftz}. slct.u16.s64.s32.s32.f32 d.f32. Description Conditional selection.f64 requires sm_13 or later.x.f64 }. . . . . Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.u32.b64. selp Syntax Comparison and Selection Instructions: selp Select between source operands. and operand a is selected.u32. Instruction Set Table 68. . and b must be of the same type. negative zero equals zero. slct Syntax Comparison and Selection Instructions: slct Select one source operand. val. y. a. selp. a.type = { . Semantics Floating Point Notes January 24. .s32 selp. If operand c is NaN. and b are treated as a bitsize type of the same width as the first instruction type. selp.dtype. .f32 comparisons.f32 comparisons. slct. . fval. . . a is stored in d.s16.b32. Introduced in PTX ISA version 1.dtype.b64. B. a. If c is True.ftz applies only to . c.dtype = { .b32. f0.ftz. based on the sign of the third operand. . a.r. . . c. Modifier . Operands d. d = (c == 1) ? a : b.s32 x.f64 }.u64. operand c must match the second instruction type.Chapter 8. . . @q selp.0. . d. sm_1x: slct.f32 flushes subnormal values of operand c to sign-preserving zero.dtype. otherwise b is stored in d. slct.0.u64. Subnormal numbers: sm_20: By default.

7.PTX ISA Version 2. 2010 . and not also operate on predicates. provided the operands are of the same size. xor. performing bit-wise operations on operands of any type. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. Instructions and. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.4. or.0 8. This permits bit-wise operations on floating point values without having to define a union to access the bits.

b16. Introduced in PTX ISA version 1. Supported on all target architectures. or.b32 x. .b32 mask mask. Instruction Set Table 70. and Syntax Logic and Shift Instructions: and Bitwise AND. January 24. but not necessarily the type.q.type d.pred.pred p. The size of the operands must match.r. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.type d.b32 and. 2010 105 . .r. Allowed types include predicate registers. but not necessarily the type. b.fpvalue. d = a | b.0. . . a.b16. a.0x00010001 or.b32. . b. Table 71. sign.Chapter 8.q. Introduced in PTX ISA version 1.0.type = { . The size of the operands must match. and.b64 }.0x80000000.type = { . and.pred.b64 }. or Syntax Logic and Shift Instructions: or Bitwise OR. d = a & b. or. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.b32. . . Allowed types include predicate registers. . Supported on all target architectures.

0. not.b16. cnot. Allowed types include predicate registers.b32 d. a. but not necessarily the type.mask.b32 mask. xor.q.pred.b16. . but not necessarily the type.b32. xor.type = { . a. The size of the operands must match. not. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. Table 74. Allowed types include predicates. a. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). not Syntax Logic and Shift Instructions: not Bitwise negation. d = a ^ b.b64 }.type = { . .b32 xor. .pred. d. b.type d.0.b16. . cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.0 Table 72.pred p.x. . d = (a==0) ? 1 : 0. The size of the operands must match.type d. Introduced in PTX ISA version 1. Supported on all target architectures.a.type d. . d = ~a.b64 }. Table 73. but not necessarily the type.b32.b64 }. Supported on all target architectures. cnot. . Supported on all target architectures.b16 d. 106 January 24.PTX ISA Version 2.type = { . .r. . Introduced in PTX ISA version 1. . one’s complement. The size of the operands must match.0x0001.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.q. Introduced in PTX ISA version 1. .0. not. 2010 .

s64 }.u64. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.u16. i. sign or zero fill on left. Shift amounts greater than the register width N are clamped to N. Introduced in PTX ISA version 1. 2010 107 . .1. Instruction Set Table 75. shl Syntax Logic and Shift Instructions: shl Shift bits left. .type d. The sizes of the destination and first source operand must match.a. The b operand must be a 32-bit value. k. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples January 24. zero-fill on right. Supported on all target architectures.i.b64. but not necessarily the type. . regardless of the instruction type.b32. a.b16. .s16. shr. Introduced in PTX ISA version 1. Bit-size types are included for symmetry with SHL. shl. shr.b16.type = { . .b64 }. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.i. The sizes of the destination and first source operand must match.0. . regardless of the instruction type.2.u16 shr. . shr Syntax Logic and Shift Instructions: shr Shift bits right. but not necessarily the type.type = { .b32 q.s32. Signed shifts fill with the sign bit. PTX ISA Notes Target ISA Notes Examples Table 76. shl. . b.b16 c. Shift amounts greater than the register width N are clamped to N. . . b. a.0. unsigned and untyped shifts fill with 0.a. . .type d.Chapter 8.u32.2. d = a >> b. d = a << b.b32. The b operand must be a 32-bit value.j.s32 shr.

and from state space to state space. local. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. possibly converting it from one format to another. suld. Data Movement and Conversion Instructions These instructions copy data from place to place. ld. ldu. prefetchu isspacep cvta cvt 108 January 24. 2010 . Instructions ld. st. The cvta instruction converts addresses between generic and global.5.PTX ISA Version 2.0 8. mov.7. and sust support optional cache operations. and st operate on both scalar and vector types. or shared state spaces. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.

evict-first.7. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.cg Cache at global level (cache in L2 and below. and a second thread loads that address via a second L1 cache with ld. likely to be accessed once.Chapter 8.cs. when applied to a local address. The ld.cs) on global addresses.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.cg to cache loads only globally. to allow the thread program to poll a SysMem location written by the CPU. Global data is coherent at the L2 level.lu instruction performs a load cached streaming operation (ld. any existing cache lines that match the requested address in L1 will be evicted. When ld. not L1).ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The ld. invalidates (discards) the local L1 line following the load. . If one thread stores to global memory via one L1 cache. Operator . The ld. .cs is applied to a Local window address. if the line is fully covered. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. but multiple L1 caches are not coherent for global data. bypassing the L1 cache. likely to be accessed again.5.lu load last use operation. January 24. The default load instruction cache operation is ld. Instruction Set 8. the second thread may get stale L1 cache data. 2010 109 .lu operation. . Table 77. The cache operators require a target architecture of sm_20 or later. As a result of this request.0 introduces optional cache operators on load and store instructions.1.ca. it performs the ld.ca. fetch again). The compiler / programmer may use ld. The ld.cv to a frame buffer DRAM address is the same as ld. A ld. rather than the data stored by the first thread.cv Cache as volatile (consider cached system memory lines stale.lu Last use. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Use ld. and cache only in the L2 cache. For sm_20 and later.ca loads cached in L1.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Cache Operators PTX 2. . the cache operators have the following definitions and behavior.cs Cache streaming.

The st.cg Cache at global level (cache in L2 and below. bypassing its L1 cache.cs Cache streaming. the second thread may get a hit on stale L1 cache data.wb for global data. . .wt store write-through operation applied to a global System Memory address writes through the L2 cache. regardless of the cache operation. and marks local L1 lines evict-first. However.wt. The default store instruction cache operation is st. and a second thread in a different SM later loads from that address via a different L1 cache with ld. bypassing the L1 cache. The st. Global stores bypass L1.wt Cache write-through (to system memory).ca loads.0 Table 78. and discard any L1 lines that match. 2010 .PTX ISA Version 2. but st.cg to cache global store data only globally. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. In sm_20. likely to be accessed once. Addresses not in System Memory use normal write-back. 110 January 24. Future GPUs may have globally-coherent L1 caches.cg to local memory uses the L1 cache. and cache only in the L2 cache.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.ca. in which case st. to allow a CPU program to poll a SysMem location written by the GPU with st. which writes back cache lines of coherent cache levels with normal eviction policy. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. Operator . If one thread stores to global memory.wb.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. rather than get the data from L2 or memory stored by the first thread. st.cg is the same as st. Use st. not L1).wb could write-back global store data from L1.

.b32. d.. d = sreg.u16 mov. . the generic address of a variable declared in global. Description . local. avar. . .u32 mov.u64.const.shared state spaces. a.f32 mov.u32 d. ptr.f64 }. Instruction Set Table 79.type = { .b64. immediate.f32 mov. label. . alternately.0. sreg. .s16. addr. Write register d with the value of a. The generic address of a variable in global.e. ptr. or function name. the parameter will be copied onto the stack and the address will be in the local state space. k. mov.pred. .v.f32. 2010 111 . . Operand a may be a register. and . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.e. Take the non-generic address of a variable in global.global. d. local.u16. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. For variables declared in . special register. local.s64. .1. label. d = &avar.Chapter 8. mov places the non-generic address of the variable (i.type mov. or shared state space.u32. mov.f64 requires sm_13 or later. or shared state space may be taken directly using the cvta instruction. Semantics d = a. Introduced in PTX ISA version 1. d. A[5]. the address of the variable in its state space) into the destination register. A.s32.type mov.b16.0. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. d = &label. // address is non-generic.. . within the variable’s declared state space Notes Although only predicate and bit-size types are required.u32 mov.a. variable in an addressable memory space.local. i. mov.type mov. myFunc. // get address of variable // get address of label or function . . u. Note that if the address of a device function parameter is moved to a register.type d. .

23].b}.g.15]. Description Write scalar register d with the packed value of vector register a. d.w}.z. .b64 // pack two 32-bit elements into .47]. d.y } = { a[0. {r. d.a}.y << 8) | (a. a[24.b32. {lo.y << 32) // pack two 8-bit elements into . a[16. . Supported on all target architectures.b64 { d.x | (a. mov.w } = { a[0.z << 16) | (a.x.w << 48) d = a. %r1.u16 %x is a double.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d.y << 16) d = a.15] } // unpack 8-bit elements from .x. a..x | (a.31].type = { . a[48. or write vector register d with the unpacked values from scalar register a.b32 { d.w } = { a[0..b16 // pack four 8-bit elements into .x.. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector..b64 112 January 24.y << 8) d = a. // // // // a. a[8.. 2010 .b16 { d.%r1. d.z..b32 // pack two 16-bit elements into . lo.b32 mov.7]..z << 32) | (a.g..b16.y..0.b have type .b32 // pack four 16-bit elements into . d.31] } // unpack 8-bit elements from . d.a have type ..y } = { a[0.y << 16) | (a. a[32. . mov.31]..0 Table 80. a[8.b64 }. For bit-size types. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.hi are ..y } = { a[0. a[16.x.b32 { d. a[16. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack)..x | (a.hi}. d.{a.. a[32. %x.15].b64 { d.PTX ISA Version 2.b32 %r1.b8 r.z.x | (a.b.63] } // unpack 16-bit elements from .w have type .b32 mov.y.type d.z.x.y.{x.u32 x.b.u8 // unpack 32-bit elements from . d.y.x | (a.b64 mov.15]. Semantics d = a.7].31] } // unpack 16-bit elements from .w << 24) d = a.

. .volatile{.type .const space suffix may have an optional bank number to indicate constant banks other than bank zero.param. or the instruction may fault. .vec. . ld{.f32 or . Description Load register variable d from the location specified by the source address operand a in specified state space.f32. . .type ld{. . to enforce sequential consistency between threads accessing shared memory. . . Generic addressing and cache operations introduced in PTX ISA 2. or [immAddr] an immediate absolute byte address (unsigned.lu. Generic addressing may be used with ld.u16.f64 }.type = { .vec. PTX ISA Notes January 24. In generic addressing.cop}. ld.volatile.global. . the resulting behavior is undefined.e. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.volatile{. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.f16 data may be loaded using ld. If an address is not properly aligned. This may be used.v4 }. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. an address maps to global memory unless it falls within the local memory window or the shared memory window. perform the load using generic addressing.v2. 32-bit). [a].reg state space. . ld introduced in PTX ISA version 1.b16. 32-bit).e.cg. d.cs. . .vec = { . Cache operations are not permitted with ld.ss}.. Semantics d d d d = = = = a. [a]. ld.Chapter 8. . .f64 using cvt. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. an address maps to the corresponding location in local or shared memory. .local.ss}.1. If no state space is given.const. The . [a].s64.b16. for example.volatile. *(a+immOff). *(immAddr).s8. . The value loaded is sign-extended to the destination register width for signed integers.shared spaces to inhibit optimization of references to volatile memory. .volatile introduced in PTX ISA version 1.ca. A destination register wider than the specified type may be used.s16. .ss}{. d. an integer or bit-size type register reg containing a byte address.s32. i.volatile may be used with .cop = { .global and . i. [a].ss}{.shared }. Within these windows. .b8.0. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.cv }. d.b64. and is zeroextended to the destination register width for unsigned and bit-size types. and then converted to . .0.type ld. . 2010 113 .u8. and truncated if the register width exceeds the state space address width for the target architecture. . .u64.ss = { . The address must be naturally aligned to a multiple of the access size. *a. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . .type d. The address size may be either 32-bit or 64-bit.cop}.u32. Addresses are zero-extended to the specified width as needed. Instruction Set Table 81.b32.

const. // access incomplete array x. Generic addressing requires sm_20 or later.f32 ld.b32 ld.%r.s32 ld.[buffer+64].const[4]. Cache operations require sm_20 or later.[a].b32 ld.[p+4]. %r.[p+-8]. // negative offset %r.f16 d. d. // immediate address %r. 2010 .global.local. Q.b32 ld.f32.[240].v4.global.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.0 Target ISA Notes ld.shared.[p].b16 cvt.[fs]. ld. // load .PTX ISA Version 2.b64 ld. x.f64 requires sm_13 or later.local.

*a. ldu{. Instruction Set Table 82.b16. The address must be naturally aligned to a multiple of the access size. . For ldu. The data at the specified address must be read-only.s32. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 32-bit).b8. ldu. i. i. an address maps to the corresponding location in local or shared memory.v2.ss}.type ldu{.f32 or .global.f64 requires sm_13 or later.[p]. . . and then converted to .e. If no state space is given. . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. an address maps to global memory unless it falls within the local memory window or the shared memory window. . .global. .v4.u32. and is zeroextended to the destination register width for unsigned and bit-size types. *(a+immOff).f32 d.global. ldu.s64.b32. only generic addresses that map to global memory are legal. . [a]. . .reg state space.vec. Introduced in PTX ISA version 2. Semantics d d d d = = = = a. . [a]. .u8. the access may proceed by silently masking off low-order address bits to achieve proper rounding. perform the load using generic addressing.0. d.type = { . The addressable operand a is one of: [avar] the name of an addressable variable var. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. *(immAddr). // state space .global }.u16. The address size may be either 32-bit or 64-bit. Within these windows.ss = { .ss}. The value loaded is sign-extended to the destination register width for signed integers. or [immAddr] an immediate absolute byte address (unsigned. where the address is guaranteed to be the same across all threads in the warp. ldu..b32 d. 2010 115 . // load from address // vec load from address . ldu. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .vec = { .f16 data may be loaded using ldu.v4 }. In generic addressing.u64. . the resulting behavior is undefined.b64.s8. [areg] a register reg containing a byte address.[p+4]. and truncated if the register width exceeds the state space address width for the target architecture. .s16. or the instruction may fault.type d. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.f32.f64 using cvt. A register containing an address may be declared as a bit-size type or integer type. If an address is not properly aligned.f32 Q.e. Addresses are zero-extended to the specified width as needed.b16.f64 }. .[a]. PTX ISA Notes Target ISA Notes Examples January 24.Chapter 8. A destination register wider than the specified type may be used. 32-bit).

The address must be naturally aligned to a multiple of the access size. .volatile.s8.ss}.volatile may be used with . ..b16.s16. st. . to enforce sequential consistency between threads accessing shared memory.u64. PTX ISA Notes Target ISA Notes 116 January 24.shared spaces to inhibit optimization of references to volatile memory. the resulting behavior is undefined.cop . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st introduced in PTX ISA version 1.b64.cop}. *d = a.ss}{.wb.volatile{. { . [a]. Generic addressing requires sm_20 or later. Within these windows.0 Table 83. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.shared }.type .ss}{.cop}. or [immAddr] an immediate absolute byte address (unsigned. perform the store using generic addressing. .volatile. an address maps to the corresponding location in local or shared memory.cs.b8. Generic addressing and cache operations introduced in PTX ISA 2. .0.f32.vec.f16 data resulting from a cvt instruction may be stored using st. b.0. b.global and . A source register wider than the specified type may be used. The address size may be either 32-bit or 64-bit. i.vec . st.wt }.e. .s32.volatile{. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. an address maps to global memory unless it falls within the local memory window or the shared memory window.reg state space.global. Generic addressing may be used with st.local. If no state space is given.cg.1.v4 }. [a]. 2010 .type [a].s64.type = = = = {. Addresses are zero-extended to the specified width as needed. This may be used. { .f64 }. *(d+immOffset) = a. Semantics d = a.u16. 32-bit). b.volatile introduced in PTX ISA version 1. st. . Cache operations are not permitted with st. . i.b32.PTX ISA Version 2. . . { .u32. . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. .ss .e. In generic addressing.b16. .f64 requires sm_13 or later.vec. If an address is not properly aligned.type st{.ss}. and truncated if the register width exceeds the state space address width for the target architecture. Cache operations require sm_20 or later.v2. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. b. [a]. 32-bit). The addressable operand a is one of: [var] [reg] the name of an addressable variable var. st{. *(immAddr) = a. . . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. for example. .u8. or the instruction may fault. . .type st. . an integer or bit-size type register reg containing a byte address. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The lower n bits corresponding to the instruction-type width are stored to memory. .

b32 st.local. [q+4].f32 st. [fs].b.s32 st.local.global.a.f32 st. // negative offset [100].local.f16.r7.global.Chapter 8.%r. // %r is 32-bit register // store lower 16 bits January 24.Q.b16 [a]. // immediate address %r.b32 st. [q+-8]. [p].a. Instruction Set Examples st.%r. 2010 117 .s32 cvt.v4.

The addressable operand a is one of: [var] [reg] the name of an addressable variable var.L1 [addr]. prefetch. an address maps to the corresponding location in local or shared memory. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. i.0. the prefetch uses generic addressing. prefetchu. Within these windows. A prefetch to a shared memory location performs no operation.0 Table 84. A prefetch into the uniform cache requires a generic address.space = { . In generic addressing. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.L1 [ptr]. [a]. 2010 . prefetch{. an address maps to global memory unless it falls within the local memory window or the shared memory window. .e.global. If no state space is given. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 32-bit). 118 January 24. a register reg containing a byte address. and truncated if the register width exceeds the state space address width for the target architecture. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.PTX ISA Version 2. Addresses are zero-extended to the specified width as needed. in specified state space. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. .level prefetchu.L2 }. . or [immAddr] an immediate absolute byte address (unsigned.L1.level = { . prefetch and prefetchu require sm_20 or later. The address size may be either 32-bit or 64-bit. 32-bit).global.L1 [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // prefetch to data cache // prefetch to uniform cache .space}.local }. and no operation occurs if the address maps to a local or shared memory location. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 gptr.shared }.local.0.local.u64 or cvt.global. a. or shared address cvta.lptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.u32 p. cvta. var. or shared state space. cvta.u32 to truncate or zero-extend addresses. isspacep.u32. p. When converting a generic address into a global. local. gptr. .pred . For variables declared in global. isspacep. January 24. // convert to generic address // get generic address of var // convert generic address to global.global. PTX ISA Notes Target ISA Notes Examples Table 86. local. or shared state space to generic.u64. a. .global isspacep.space = { . lptr.pred.size cvta. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32.space = { .size = { .u32 or . cvta. Description Convert a global. The destination register must be of type . local. Instruction Set Table 85.genptr. Take the generic address of a variable declared in global. . local.size p.global. svar.0. isshrd. a. // get generic address of svar cvta.space.shared isglbl. The source address operand must be a register of type . p. or shared state space. cvta requires sm_20 or later. 2010 119 .space p. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. The source and destination addresses must be the same size.local isspacep. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. local. Introduced in PTX ISA version 2.u32 p. .size . // local.Chapter 8.to. islcl.space. sptr. isspacep requires sm_20 or later.shared. or vice-versa. . or shared address.to. or shared address to a generic address. A program may use isspacep to guard against such incorrect behavior.u64.shared }.space. // result is . or vice-versa.u64 }. the generic address of the variable may be taken using cvta. .local. Use cvt.

0 Table 87. Integer rounding modifiers: . i..ftz}{.f32.u32. Note: In PTX ISA versions 1. The optional . Integer rounding is illegal in all other instances. sm_1x: For cvt.ftz. Description Semantics Integer Notes Convert between different types and sizes. .s16.ftz modifier may be specified in these cases for clarity. .ftz.rp }.rni.rm.ftz}{.f32 float-tofloat conversions with integer rounding. For cvt.irnd}{.sat For integer destination types. .e.sat limits the result to MININT.u16. .f32. The compiler will preserve this behavior for legacy PTX code. and for same-size float-tofloat conversions where the value is rounded to an integer.rn. . Note that saturation applies to both signed and unsigned integer types. d = convert(a).atype = { . .f32 float-to-integer conversions and cvt. .u8. . 120 January 24. . the result is clamped to the destination range by default.sat}.rzi round to nearest integer in the direction of zero .f32. . . .frnd}{.rmi. choosing even integer if source is equidistant between two integers.s8.rz.f64 }.f32 float-tofloat conversions with integer rounding.ftz. the . Saturation modifier: . . For float-to-integer conversions.rni round to nearest integer.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. . subnormal numbers are supported.4 and earlier.u64.dtype.dtype. 2010 . a.dtype. .sat is redundant. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.s64. .dtype = .sat}. .irnd = { .rmi round to nearest integer in direction of negative infinity .atype cvt{.rzi. // integer rounding // fp rounding . a.MAXINT for the size of the operation.PTX ISA Version 2.frnd = { .ftz. d.f16. . . subnormal inputs are flushed to signpreserving zero. .dtype.atype d. Integer rounding is required for float-to-integer conversions.f32 float-to-integer conversions and cvt. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.. subnormal inputs are flushed to signpreserving zero.e. cvt{.rpi }.s32. .sat modifier is illegal in cases where saturation is not possible based on the source and destination types. i.

Applies to . and cvt.0. .f32 instructions.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.r. Note: In PTX ISA versions 1.f32.0].f32.i.ftz behavior for sm_1x targets January 24.f32. stored in floating-point format.rm mantissa LSB rounds towards negative infinity .f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. cvt to or from .f64.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.4 and earlier.f32.rn mantissa LSB rounds to nearest even .f16. Introduced in PTX ISA version 1. cvt.f64 types. cvt. Subnormal numbers: sm_20: By default. The result is an integral value.sat limits the result to the range [0. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . // float-to-int saturates by default cvt. // round to nearest int.s32 f. The compiler will preserve this behavior for legacy PTX code. 1.f32.s32.rni. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f64 j. subnormal numbers are supported.version is 1.f32.0. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. Saturation modifier: . The operands must be of the same size. NaN results are flushed to positive zero.f16.f16.f64 requires sm_13 or later.rz mantissa LSB rounds towards zero . // note . 2010 121 .y.ftz modifier may be specified in these cases for clarity.f32 x.f32 x. Specifically. The optional . . Modifier . and . result is fp cvt.Chapter 8.y. cvt.4 or earlier. if the PTX . Floating-point rounding is illegal in all other instances. Floating-point rounding modifiers: . and for integer-to-float conversions.sat For floating-point destination types.

f32 r1. [tex1.param . add.r4}. div.r2.r3. 122 January 24.u32 r5. = nearest width height tsamp1.f32.entry compute_power ( .v4. add. The advantage of independent mode is that textures and samplers can be mixed and matched.f32. .texref handle.width.6. If no texturing mode is declared. cvt. . r1.texref tex1 ) { txq.f32 r1. r3. A PTX module may declare only one texturing mode.. r5.global . {f1.PTX ISA Version 2.height. r1. sampler. Example: calculate an element’s power contribution as element’s power/total number of elements. allowing them to be defined separately and combined at the site of usage in the program. In the unified mode. [tex1]. // get tex1’s tex. sampler. r5. but the number of samplers is greatly restricted to 16. r1.f32 r1.u32 r5. add. . Ability to query fields within texture.f2}]. and surface descriptors.target texmode_independent . PTX supports the following operations on texture.0 8. Module-scope and per-entry scope definitions of texture. and surface descriptors. r3. texture and sampler information is accessed through a single . r6.. samplers. PTX has two modes of operation. and surface descriptors. The texturing mode is selected using . r2.f32 r3. 2010 .target options ‘texmode_unified’ and ‘texmode_independent’. mul. r4. The advantage of unified mode is that it allows 128 samplers. texture and sampler information each have their own handle. Texturing modes For working with textures and samplers. sampler. with the restriction that they correspond 1-to-1 with the 128 possible textures.7.2d. // get tex1’s txq. } = clamp_to_border.samplerref tsamp1 = { addr_mode_0 filter_mode }. the file is assumed to use unified mode. r5. and surfaces. and surface descriptors: • • • Static initialization of texture.f32 {r1. [tex1]. In the independent mode.b32 r5. Texture and Surface Instructions This section describes PTX instructions for accessing textures.b32 r6. sampler.

btype tex.2d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.1d.v4.1d. Description Texture lookup using a texture coordinate vector.f3. // explicit sampler .3d. the square brackets are not required and . . where the fourth element is ignored.f32 }.geom = { . [tex_a.u32.5.r2. // Example of independent mode texturing tex.dtype = { .Chapter 8.geom.r2. Unified mode texturing introduced in PTX ISA version 1.geom. with the extra elements being ignored. sampler_x. [tex_a. Operand c is a scalar or singleton tuple for 1d textures. d. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. b.r4}. //Example of unified mode texturing tex. 2010 123 . Instruction Set These instructions provide access to texture and surface memory. An optional texture sampler b may be specified.v4.0. .e. Supported on all target architectures. A texture base address is assumed to be aligned to a 16-byte address.dtype.s32.f32 }.btype = { . the sampler behavior is a property of the named texture. the resulting behavior is undefined. If an address is not properly aligned.btype d.s32. tex. . If no sampler is specified.v4.f32 {r1. [a.r3.s32. . . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. c].f2. c].f4}].s32 {r1. Notes For compatibility with prior versions of PTX.r3. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.r4}.3d }. or the instruction may fault. [a.dtype. the access may proceed by silently masking off low-order address bits to achieve proper rounding.. and is a four-element vector for 3d textures. PTX ISA Notes Target ISA Notes Examples January 24.s32. The instruction always returns a four-element vector of 32-bit values. tex txq suld sust sured suq Table 88. {f1. i. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. . is a two-element vector for 2d textures. {f1}].v4.v4 coordinate vectors are allowed for any geometry. .

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. clamp_to_edge.filter_mode.normalized_coords . addr_mode_2 }.squery = { .addr_mode_0. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. txq. . linear } Integer from enum { wrap. [tex_A]. d.squery.height . 2010 .width. .PTX ISA Version 2.normalized_coords }.b32 txq.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).b32 %r1.depth. Supported on all target architectures. [a]. [tex_A]. clamp_ogl. mirror. Query: .filter_mode . // texture attributes // sampler attributes .5.tquery = { .tquery. txq. txq. sampler attributes are also accessed via a texref argument.addr_mode_0.width . In unified mode. Operand a is a . and in independent mode sampler attributes are accessed via a separate samplerref argument. // unified mode // independent mode 124 January 24. [smpl_B].samplerref variable.depth .b32 d. . .addr_mode_0 .0 Table 89. Description Query an attribute of a texture or sampler. Integer from enum { nearest.b32 %r1.b32 %r1.width. addr_mode_1. [a].height.filter_mode. txq. .texref or .addr_mode_1 .

// cache operation none.geom . .geom{. If the destination type is . {f1. [a. Instruction Set Table 90.b performs an unformatted load of binary data.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. .geom{.s32.b.surfref variable. .f32.1d. i. suld. . suld.trap introduced in PTX ISA version 1. .cop . . where the fourth element is ignored.w}].p requires sm_20 or later.u32 is returned. G. or the instruction may fault.b .3d }.f32 }. suld. or . suld.Chapter 8.s32. The lowest dimension coordinate represents a sample offset rather than a byte offset. if the surface format contains UINT data.clamp = = = = = = { { { { { { d.3d requires sm_20 or later.b. {x}].trap . the access may proceed by silently masking off low-order address bits to achieve proper rounding. additional clamp modifiers. SNORM. size and type conversion is performed as needed to convert from the surface sample format to the destination type.zero }. the surface sample elements are converted to .v2.f4}.vec. Coordinate elements are of type .s32.trap. . b]. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. B. . . Operand a is a .dtype.u32. Destination vector elements corresponding to components that do not appear in the surface format are not written. suld. . .cop}. .r2}. or FLOAT data. [surf_A. suld. suld. If the destination base type is . .s32. If an address is not properly aligned.z.. .3d. Target ISA Notes Examples January 24. or .clamp field specifies how to handle out-of-bounds addresses: .1d.b8 . .f32 is returned. and is a four-element vector for 3d surfaces.clamp.cg.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.p .v2. suld.dtype.cv }. Cache operations require sm_20 or later. suld. [surf_B. then .e.dtype .p.u32. .trap {r1.v4 }. [a.b64 }.0. if the surface format contains SINT data.clamp suld. 2010 125 . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. // for suld. Operand b is a scalar or singleton tuple for 1d surfaces. .u32.clamp . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b32.b64.vec .clamp . {x. The .p.b32.f3. then .2d.b16. // formatted .cs.f32.v4.dtype .v4. A surface base address is assumed to be aligned to a 16-byte address.5. // for suld.b. sm_1x targets support only the .ca.p is currently unimplemented. . b].trap suld.y.p.f32 based on the surface format as follows: If the surface format contains UNORM. is a two-element vector for 2d surfaces. then .trap clamping modifier. the resulting behavior is undefined.b supported on all target architectures. and A components of the surface format. .f2. Description Load from surface memory using a surface coordinate vector. // unformatted d. suld Syntax Texture and Surface Instructions: suld Load from surface memory. and cache operations introduced in PTX ISA version 2. and the size of the data transfer matches the size of destination operand d.b32.s32 is returned.cop}.

u32 is assumed.trap .cop}. . {f1.geom . // for sust. then . sust.y.b.clamp .b16.b32.3d requires sm_20 or later. Operand a is a . Operand b is a scalar or singleton tuple for 1d surfaces.zero }.f32 }. . .b. .u32. .b // for sust. G.wb. The size of the data transfer matches the size of source operand c. .clamp sust. c. or the instruction may fault. .clamp . .v2. if the surface format contains SINT data. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. b]. . is a two-element vector for 2d surfaces. and cache operations introduced in PTX ISA version 2. The source vector elements are interpreted left-to-right as R. B. c.f3.p.p requires sm_20 or later.b32.p. {x. . sust.s32. [surf_B.b32. Coordinate elements are of type .trap. If an address is not properly aligned. . . sust.2d. . .geom{.clamp field specifies how to handle out-of-bounds addresses: . A surface base address is assumed to be aligned to a 16-byte address. If the source base type is .f32. .wt }.z.b64 }.f32} are currently unimplemented.cg.vec . Target ISA Notes Examples 126 January 24. sust. // unformatted // formatted .5. sust.p.clamp = = = = = = { { { { { { [a.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.0 Table 91.b supported on all target architectures..f2.1d. sust. sust.b.v4. .s32.p Description Store to surface memory using a surface coordinate vector. {r1. or . i.s32. then . sm_1x targets support only the . where the fourth element is ignored. . and is a four-element vector for 3d surfaces.0.trap clamping modifier.surfref variable.p performs a formatted store of a vector of 32-bit data values to a surface sample.f32 is assumed.s32. or FLOAT data.trap [surf_A. size and type conversions are performed as needed between the surface sample format and the destination type. 2010 .e. b].r2}.f4}.cs. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. and A surface components.clamp. if the surface format contains UINT data.1d.vec.v4 }.b8 . the resulting behavior is undefined. . sust.cop . If the source type is . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. [a. SNORM.f32. Surface sample components that do not occur in the source vector will be written with an unpredictable value. sust Syntax Texture and Surface Instructions: sust Store to surface memory.vec.u32.cop}.ctype .geom{.b performs an unformatted store of binary data. The source data is then converted from this type to the surface sample format. {x}]. Source elements that do not occur in the surface sample are ignored. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.{u32.s32 is assumed.3d. Cache operations require sm_20 or later.ctype. none.ctype .trap introduced in PTX ISA version 1. sust.trap sust. These elements are written to the corresponding surface sample components. . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. The .3d }.v2.p. The lowest dimension coordinate represents a sample offset rather than a byte offset.ctype. then .w}].b64.PTX ISA Version 2. additional clamp modifiers.

u32.s32.surfref variable. . and . Operand b is a scalar or singleton tuple for 1d surfaces.ctype = { . // sample addressing .p.op.b32 }. . where the fourth element is ignored.s32 is assumed.u32.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // for sured.max. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.add. is a two-element vector for 2d surfaces. Instruction Set Table 92.op = { . sured. sured. . // byte addressing sured.b . The instruction type is restricted to . . {x. Coordinate elements are of type . .min. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32 types.s32 or .ctype.p. {x}].min.3d }. . .y}]. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.1d.b].s32.2d.u64.0. sured. or the instruction may fault.u32 is assumed.b32 }.. or . A surface base address is assumed to be aligned to a 16-byte address.u64 data.b.b32.b32. sured.add. Reduction to surface memory using a surface coordinate vector.u32 and . sured requires sm_20 or later. Operand a is a . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b. then . operations and and or apply to . January 24. // for sured.s32.2d.b]. 2010 127 .b32.trap . . The lowest dimension coordinate represents a sample offset rather than a byte offset. and the data is interpreted as .s32 types.c.ctype. and is a four-element vector for 3d surfaces.Chapter 8. if the surface format contains SINT data.geom.zero }.b performs an unformatted reduction on .clamp .1d. min and max apply to .clamp. the resulting behavior is undefined.p performs a reduction on sample-addressed 32-bit data.b32 type.p .and. Operations add applies to . .trap. the access may proceed by silently masking off low-order address bits to achieve proper rounding. r1.ctype = { . . .trap [surf_A.geom = { . If an address is not properly aligned. then . r1.clamp = { .u32. . .u32. i. . The .trap sured.clamp [a.geom.u32 based on the surface sample format as follows: if the surface format contains UINT data. [surf_B.c.or }. .u64.clamp field specifies how to handle out-of-bounds addresses: .op. .e.clamp [a.

128 January 24. . [a].b32 d.surfref variable.width.height .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. . Query: . Supported on all target architectures. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.0 Table 93.depth }. Description Query an attribute of a surface. Operand a is a .width . suq.height. .5. 2010 .PTX ISA Version 2.b32 %r1. suq. [surf_A].query.width.query = { .

{ instructionList } The curly braces create a group of instructions. Execute an instruction or instruction block for threads that have the guard predicate true.y. Supported on all target architectures. Introduced in PTX ISA version 1. } PTX ISA Notes Target ISA Notes Examples Table 95. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Supported on all target architectures. Threads with a false guard predicate do nothing. used primarily for defining a function body. p. { add.7.Chapter 8. {} Syntax Description Control Flow Instructions: { } Instruction grouping. If {!}p then instruction Introduced in PTX ISA version 1. mov.s32 d.7.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Instruction Set 8.f32 @q bra L23. ratio. setp. 2010 129 .0.eq. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.x.s32 a.b.0. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.0. @{!}p instruction.f32 @!p div.c.a.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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popc. Since barriers are executed on a per-warp basis.15. {!}c. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. bar. Register operands. bar. Instruction Set Table 100. bar. Each CTA instance has sixteen barriers numbered 0.op = { . the optional thread count must be a multiple of the warp size. Execution in this case is unpredictable.pred . In conditionally executed code.arrive using the same active barrier.red delays the executing threads (similar to bar. Only bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). The barrier instructions signal the arrival of the executing threads at the named barrier.or }. Thus. the final value is written to the destination register in all threads waiting at the barrier.sync) until the barrier count is met. threads within a CTA that wish to communicate via memory can store to memory. January 24. Thus. The result of . d. thread count. it is as if all the threads in the warp have executed the bar instruction.and.sync 0.sync or bar. and bar. a. while . all threads in the CTA participate in the barrier. The reduction operations for bar. all-threads-true (.op. Once the barrier count is reached.sync and bar. and bar.0.{arrive. bar. thread count. Barriers are executed on a per-warp basis as if all the threads in a warp are active. bar. If no thread count is specified.. execute a bar. In addition to signaling its arrival at the barrier. b}. a{.or). {!}c.popc).and).sync and bar.popc is the number of threads with a true predicate.0.sync bar.red instruction. the waiting threads are restarted without delay.Chapter 8. it simply marks a thread's arrival at the barrier. and any-thread-true (.red} introduced in PTX . .arrive. Description Performs barrier synchronization and communication within a CTA.u32.red performs a predicate reduction across the threads participating in the barrier. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.u32 bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).{arrive. All threads in the warp are stalled until the barrier completes. a{.red.red performs a reduction operation across threads.sync without a thread count introduced in PTX ISA 1. the bar. bar.sync with an immediate barrier number is supported for sm_1x targets.red. Operand b specifies the number of threads participating in the barrier. and d have type . b}.red also guarantee memory ordering among threads identical to membar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. 2010 133 . Note that a non-zero thread count is required for bar.red} require sm_20 or later. if any thread in a warp executes a bar instruction. and then safely read values stored by other threads prior to the barrier. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. b.arrive a{. PTX ISA Notes Target ISA Notes Examples bar. bar. Register operands.and and . Operands a.red should not be intermixed with bar.sync or bar.arrive does not cause any waiting by the executing threads. b.version 2. operands p and c are predicates.red are population-count (. p. and the barrier is reinitialized so that it can be immediately reused.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. When a barrier completes. bar. b}.cta.

when the previous value can no longer be read. membar.sys Waits until all prior memory requests have been performed with respect to all clients. membar.gl} supported on all target architectures. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. . membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.sys will typically have much longer latency than membar.gl. For communication between threads in different CTAs or even different SMs. and memory reads by this thread can no longer be affected by other thread writes. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. level describes the scope of other clients for which membar is an ordering event.g.4.sys requires sm_20 or later.sys introduced in PTX . 2010 . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. Waits until prior memory reads have been performed with respect to other threads in the CTA. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar.level = { . membar. by st.sys }.0 Table 101.gl will typically have a longer latency than membar.{cta.0. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. red or atom) has been performed when the value written has become visible to other clients at the specified level. global. . that is.sys. this is the appropriate level of membar. membar. PTX ISA Notes Target ISA Notes Examples membar.gl. including thoses communicating via PCI-E such as system and peer-to-peer memory.{cta.gl. membar. 134 January 24.version 1.gl} introduced in PTX . membar. .level. A memory read (e.cta. membar.cta. membar.PTX ISA Version 2. or system memory level.version 2.cta Waits until all prior memory writes are visible to other threads in the same CTA. membar. A memory write (e.g.cta. membar.

u32. min. inc.s32.space}. . The inc and dec operations return a result in the range [0. Description // // // // // .e.op. atom.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.b64. min.min. and exch (exchange). Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. dec. the resulting behavior is undefined.u64 .add. or. an address maps to the corresponding location in local or shared memory.s32.f32.g. . i. accesses to local memory are illegal. c. The integer operations are add. . . an address maps to global memory unless it falls within the local memory window or the shared memory window. . The floating-point operations are add. and max operations are single-precision. . and max.u32. .space}. .exch to store to locations accessed by other atomic operations.f32 }. and stores the result of the specified operation at location a.global. or the instruction may fault. . atom{. . . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.b64 . . A register containing an address may be declared as a bit-size type or integer type. 2010 135 . . ..inc.u64.dec. [a].space = { . 32-bit operations. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. Within these windows.type atom{.max }.b]. Instruction Set Table 102.u32. a de-referenced register areg containing a byte address. b. or by using atom. by inserting barriers between normal stores and atomic operations to a common address.b32.s32.cas. .u32 only .shared }. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .e. If no state space is given. January 24. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. max.or.type = { . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. [a]. or [immAddr] an immediate absolute byte address. xor. Addresses are zero-extended to the specified width as needed.. The address size may be either 32-bit or 64-bit.b32 only . The bit-size operations are and.and.b32.exch. min.op = { . d. .xor. Operand a specifies a location in the specified state space. overwriting the original value. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.type d. The address must be naturally aligned to a multiple of the access size. . and truncated if the register width exceeds the state space address width for the target architecture. In generic addressing. b. perform the memory accesses using generic addressing. The floating-point add.Chapter 8. cas (compare-and-swap).op. If an address is not properly aligned. . e. . performs a reduction operation with operand b and the value in location a. For atom.add. . .f32 Atomically loads the original value at location a into destination register d. i.

shared.[x+4]. cas(r. b. atom.[a].cas.0 Semantics atomic { d = *a. 64-bit atom. atom.PTX ISA Version 2.0.shared operations require sm_20 or later.s32 atom. c) operation(*a.f32 atom.global. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. s) = s.max} are unimplemented. s) = (r >= s) ? 0 dec(r. atom.add. Use of generic addressing requires sm_20 or later.s.[p].f32.global. atom. : r-1.cas.exch} requires sm_12 or later.add. : r.my_val.f32 requires sm_20 or later.shared requires sm_12 or later. : r+1.t) = (r == s) ? t operation(*a. b). d.{min.{add.my_new_val.max. 64-bit atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.global requires sm_11 or later. Release Notes Examples @p 136 January 24. d. atom. Introduced in PTX ISA version 1. 2010 .b32 d. s) = (r > s) ? s exch(r.1. *a = (operation == cas) ? : } where inc(r.0.

op. If an address is not properly aligned. The bit-size operations are and. and xor.u64 . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.Chapter 8.min. an address maps to global memory unless it falls within the local memory window or the shared memory window. The floating-point add. min.inc. In generic addressing.. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.dec. dec(r.b64. b.op = { . Operand a specifies a location in the specified state space.b32. . a de-referenced register areg containing a byte address. If no state space is given.type [a]. or [immAddr] an immediate absolute byte address.global. . The floating-point operations are add. . b). or by using atom.f32. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.max }. perform the memory accesses using generic addressing.u32.exch to store to locations accessed by other reduction operations. . The inc and dec operations return a result in the range [0. the access may proceed by silently masking off low-order address bits to achieve proper rounding. min. and stores the result of the specified operation at location a. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. or the instruction may fault. Instruction Set Table 103. Description // // // // .space}.b32 only . the resulting behavior is undefined.s32. The address must be naturally aligned to a multiple of the access size.g. and max operations are single-precision. .and. Notes Operand a must reside in either the global or shared state space.xor. 32-bit operations. .e.f32 }.f32 Performs a reduction operation with operand b and the value in location a. or. max.. overwriting the original value. . A register containing an address may be declared as a bit-size type or integer type. and max. 2010 137 . .or.add. dec. . and truncated if the register width exceeds the state space address width for the target architecture. i.add.space = { .u32. The address size may be either 32-bit or 64-bit.shared }. by inserting barriers between normal stores and reduction operations to a common address. Within these windows. . . Addresses are zero-extended to the specified width as needed. .u64. accesses to local memory are illegal.b]. an address maps to the corresponding location in local or shared memory. red. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. i. Semantics *a = operation(*a. min. .u32. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. . .e. s) = (r >= s) ? 0 : r+1. For red.s32. s) = (r > s) ? s : r-1. . .u32 only . January 24. where inc(r. e. .s32.type = { . The integer operations are add. inc. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. red{. .

{min.max. 64-bit red.global. red.shared. 64-bit red.max} are unimplemented.global. red.add.and.0. red. Use of generic addressing requires sm_20 or later.b32 [a]. red. Release Notes Examples @p 138 January 24.shared requires sm_12 or later.PTX ISA Version 2.my_val.global requires sm_11 or later red. 2010 . [x+4].1.f32.2.add.f32 red.f32 requires sm_20 or later.s32 red.add requires sm_12 or later.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.shared operations require sm_20 or later. [p].

uni. Negate the source predicate to compute .ballot. . .b32 p. 2010 139 .p. The destination predicate value is the same across all threads in the warp.pred vote.uni.b32 d. returns bitmask .all. // ‘ballot’ form.2.all True if source predicate is True for all active threads in warp.uni }. . vote. Negating the source predicate also computes .uni True if source predicate has the same value in all active threads in warp. // get ‘ballot’ across warp January 24.mode. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.none. vote.ballot. vote requires sm_12 or later.ballot.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.not_all.all. Description Performs a reduction of the source predicate across threads in a warp.any True if source predicate is True for some active thread in warp. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. Note that vote applies to threads in a single warp. Instruction Set Table 104.b32 requires sm_20 or later.pred vote. {!}a.mode = { .q.Chapter 8. p.any. where the bit position corresponds to the thread’s lane id.ballot.pred d. vote. vote. The reduction modes are: . Negate the source predicate to compute . vote. In the ‘ballot’ form.q. . r1. {!}a. not across an entire CTA.

vop. The source and destination operands are all 32-bit registers. atype.min.asel}.btype = { . .dtype = .dsel. c.btype{. b{.atype. .bsel = { .asel}.7. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. b{.9. The type of each operand (.h1 }.bsel}.PTX ISA Version 2. 2010 .bsel}. .b3. b{. optionally clamp the result to the range of the destination type.u32.s32) is specified in the instruction type.atype = . The sign of the intermediate result depends on dtype. .btype{. to produce signed 33-bit input values. The primary operation is then performed to produce an .sat} d.atype.b1. .s34 intermediate result.max }.extended internally to . with optional secondary operation vop. 4. the input values are extracted and signor zero.b0. . . extract and sign.dtype. half-word.0 8.bsel}.secop d. Video Instructions All video instructions operate on 32-bit register operands.h0. .add. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. .asel}.s32 }.dtype.dsel = . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. a{. with optional data merge vop. all combinations of dtype. 140 January 24. // 32-bit scalar operation.asel = . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). . and btype are valid. 3. or word values from its source operands.b2.secop = { . The general format of video instructions is as follows: // 32-bit scalar operation. perform a scalar arithmetic operation to produce a signed 34-bit result. Using the atype/btype and asel/bsel specifiers. a{. taking into account the subword destination size in the case of optional data merging. c.sat} d.dtype.atype.sat}.btype{.or zero-extend byte.u32 or . . 2. a{.s33 values.

c). c).min: return MIN(tmp. tmp.h1: return ((tmp & 0xffff) << 16) case .s33 c ) switch ( dsel ) { case . . tmp.s33 tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). S16_MAX. tmp.add: return tmp + c.b3: if ( sign ) return CLAMP( else return CLAMP( case .s33 optSaturate( . c).h0. S8_MIN ). S32_MIN ). c). c).s33 optSecOp(Modifier secop.max return MAX(tmp. S32_MAX. U16_MAX. U8_MAX. . S16_MIN ). tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. Modifier dsel ) { if ( !sat ) return tmp.Chapter 8. Bool sign. .b2: return ((tmp & 0xff) << 16) case .s33 tmp. . U16_MIN ). U32_MAX. Instruction Set .b0. U8_MIN ). U32_MIN ).b2. . tmp. switch ( dsel ) { case . default: return tmp. The sign of the c operand is based on dtype.s33 optMerge( Modifier dsel.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. S8_MAX. . January 24. . .b0: return ((tmp & 0xff) case .b1: return ((tmp & 0xff) << 8) case . as shown in the following pseudocode. . .s34 tmp. 2010 141 .s33 c) { switch ( secop ) { . . c).b3: return ((tmp & 0xff) << 24) default: return tmp. c).b1. } } .h0: return ((tmp & 0xffff) case . The lower 32-bits are then written to the destination operand. Bool sat.

dsel .0 Table 105. isSigned(dtype). vmax }.max }. r3. bsel ). r2.bsel = { .op2 Description = = = = { vadd. b{. c.dsel. vmax vadd. tb ). r1. a{.b3.btype{.min. tb ). Video Instructions: vadd. sat. with optional data merge vop.s32. vmax Syntax Integer byte/half-word/word addition / subtraction.sat} d. . .b0. 2010 . tmp.dtype . .sat vmin. tmp. tb = partSelectSignExtend( b.asel}. // optional secondary operation d = optMerge( dsel.sat vabsdiff. vabsdiff.h1 }. d = optSecondaryOp( op2. // optional merge with c operand 142 January 24. c. . vmin. vadd.s32.h1. vsub vabsdiff vmin. c. vmin. r3. r3.b1. r2. Integer byte/half-word/word absolute value of difference.0. atype.bsel}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.btype{. vsub.sat. and optional secondary arithmetic operation or subword data merge. with optional secondary operation vop. r1. dsel ). // 32-bit scalar operation. . .or zero-extend based on source operand type ta = partSelectSignExtend( a.asel}. taking into account destination type and merge operations tmp = optSaturate( tmp.asel = . b{.btype{. vmax require sm_20 or later.dtype. vsub. c.s32.s32.s32. r3. tmp = MIN( ta.sat}. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.atype.u32. tmp = ta – tb.sat vsub.asel}.s32. c ). Semantics // saturate.b0. { . asel ). Perform scalar arithmetic operation with optional saturate.bsel}.atype = . . . c ). . r2.bsel}.h1.sat} d. b{. vadd. Integer byte/half-word/word minimum / maximum.PTX ISA Version 2. // 32-bit scalar operation. a{. r1.s32. r2.s32.b2. vmin.b2.btype = { .atype. // extract byte/half-word/word and sign. vabsdiff. tmp = MAX( ta. a{.dtype.dtype.op2 d.s32 }.s32. vop.s32. .u32.b0.atype.h0. vabsdiff.add r1. .vop . tmp = | ta – tb |.u32.h0. vsub.h0. btype.add.

b{.dsel .u32.dtype. unsigned shift fills with zero.dsel. } // saturate.s32 }.mode} d. and optional secondary arithmetic operation or subword data merge. vshr Syntax Integer byte/half-word/word left / right shift. Instruction Set Table 106. . . { . Left shift fills with zero. // 32-bit scalar operation.bsel = { . a{.u32 vshr. .clamp . .atype = { . sat.b2.0.dtype. b{. Video Instructions: vshl.s32. tb = partSelectSignExtend( b. vshr vshl. r3.dtype.b1. r3. r1. and optional secondary arithmetic operation or subword data merge. Semantics // extract byte/half-word/word and sign. Signed shift fills with the sign bit. a{. .asel}. vshr require sm_20 or later.b0. r2. bsel ).u32{. case vshr: tmp = ta >> tb.u32.asel = .Chapter 8. // 32-bit scalar operation. // default is .or zero-extend based on source operand type ta = partSelectSignExtend( a.atype.op2 Description = = = = = { vshl. if ( mode == . 2010 143 . if ( mode == . taking into account destination type and merge operations tmp = optSaturate( tmp. . vshl: Shift a left by unsigned amount in b with optional saturate. b{.wrap ) tb = tb & 0x1f. c.atype. .h1 }.mode}. vshl.mode} d.add. dsel ).max }. { .dtype .op2 d.h1.bsel}. d = optSecondaryOp( op2. with optional data merge vop. switch ( vop ) { case vshl: tmp = ta << tb. c ). isSigned(dtype).clamp && tb > 32 ) tb = 32.u32. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.bsel}. .sat}{. tmp. with optional secondary operation vop. vshl.b3.u32. vshr }. .wrap r1.sat}{.u32. a{.u32{.sat}{. c. vshr: Shift a right by unsigned amount in b with optional saturate. atype.min.h0.u32{.asel}. vop.clamp.atype.asel}. tmp.u32. . January 24. c ).vop . . .mode . // optional secondary operation d = optMerge( dsel.bsel}.wrap }. asel ). r2.

sat}{. final signed (S32 * S32) + S32 // intermediate signed. final signed (S32 * U32) + S32 // intermediate signed.asel = .b1. final signed (U32 * U32) .dtype = . final signed (S32 * S32) .asel}. final signed (U32 * S32) + S32 // intermediate signed.PTX ISA Version 2. and the operand negates. otherwise. The source operands support optional negation with some restrictions. final signed (S32 * U32) . final signed -(U32 * S32) + S32 // intermediate signed. {-}a{. final signed (U32 * S32) .sat}{.po mode. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final unsigned -(U32 * U32) + S32 // intermediate signed. and zero-extended otherwise. .scale} d. PTX allows negation of either (a*b) or c.po{.btype = { .asel}. {-}b{.atype = .u32.S32 // intermediate signed. (a*b) is negated if and only if exactly one of a or b is negated. . “plus one” mode. // 32-bit scalar operation vmad. The final result is unsigned if the intermediate result is unsigned and c is not negated.atype.S32 // intermediate signed. .shr15 }.U32 // intermediate unsigned.0 Table 107.b0.btype{. internally this is represented as negation of the product (a*b). . That is. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.bsel}. with optional operand negates.h0. . c. . . a{. final signed -(S32 * U32) + S32 // intermediate signed.bsel = { . Input c has the same sign as the intermediate result. b{.bsel}.po) computes (a*b) + c + 1. Depending on the sign of the a and b operands. Description Calculate (a*b) + c.dtype. . the intermediate result is signed.. final signed -(S32 * S32) + S32 // intermediate signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. The “plus one” mode (.s32 }.btype.shr7.scale = { . 2010 . .b2. . final signed The intermediate result is optionally scaled via right-shift. Although PTX syntax allows separate negation of the a and b operands.b3. {-}c. Source operands may not be negated in .scale} d.atype. 144 January 24.dtype. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.S32 // intermediate signed. and scaling. which is used in computing averages. this result is sign-extended if the final result is signed. vmad.h1 }.

negate. -r3. } else if ( c. tmp[127:0] = ta * tb. r3.sat ) { if (signedFinal) result = CLAMP(result. } else if ( a. tmp = tmp + c128 + lsb.sat vmad.po ) { lsb = 1. Instruction Set Semantics // extract byte/half-word/word and sign.s32. signedFinal = isSigned(atype) || isSigned(btype) || (a.u32. lsb = 0. switch( scale ) { case .s32.shr7: result = (tmp >> 7) & 0xffffffffffffffff.0.negate ) { c = ~c. S32_MIN).shr15 r0. 2010 145 . vmad requires sm_20 or later. r2. U32_MAX.negate ^ b. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). U32_MIN). bsel ). asel ). tb = partSelectSignExtend( b.u32.negate ) { tmp = ~tmp. S32_MAX.u32.negate) || c. lsb = 1. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shr15: result = (tmp >> 15) & 0xffffffffffffffff. else result = CLAMP(result. r2. r1. r0.negate ^ b.or zero-extend based on source operand type ta = partSelectSignExtend( a. r1. lsb = 1. January 24. vmad. atype.h0. btype. } if ( .Chapter 8.u32. case . if ( .h0.

atype.max }. b{. .bsel = { .op2 d. { .btype.cmp .bsel}. c. // optional secondary operation d = optMerge( dsel. b{. .cmp d.min.eq.b3.asel}. Compare input values using specified comparison.asel}. asel ). vset requires sm_20 or later.dsel.bsel}. cmp ) ? 1 : 0.PTX ISA Version 2. d = optSecondaryOp( op2.lt vset. r3. .atype .b2. . . c. .h0. r2. c ). . c ). r3. vset. a{. Semantics // extract byte/half-word/word and sign.0. .or zero-extend based on source operand type ta = partSelectSignExtend( a. . tmp.atype.op2 Description = = = = .cmp. btype.le.gt.asel}. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.h1.u32.dsel .add. vset.atype. a{. tmp.s32 }.s32.ge }. . The intermediate result of the comparison is always unsigned. b{. a{. bsel ). . . tmp = compare( ta.btype = { . and therefore the c operand and final result are also unsigned.b0.lt.bsel}. . tb.atype. r1.asel = .ne r1.b1. { .h1 }. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. // 32-bit scalar operation.cmp d.u32. with optional data merge vset.btype. r2.btype.0 Table 108. 2010 . .u32. with optional secondary operation vset. with optional secondary arithmetic operation or subword data merge. // 32-bit scalar operation. 146 January 24. tb = partSelectSignExtend( b.u32.ne.

Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.4. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. brkpt Suspends execution Introduced in PTX ISA version 1. pmevent a. Introduced in PTX ISA version 1.7. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.0. numbered 0 through 15. brkpt requires sm_11 or later. trap.10. trap Abort execution and generate an interrupt to the host CPU. brkpt. Instruction Set 8. Table 110. 2010 147 . pmevent 7. with index specified by immediate operand a. @p pmevent 1. Triggers one of a fixed number of performance monitor events.0. January 24. Table 111. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. brkpt. Supported on all target architectures. there are sixteen performance monitor events. Supported on all target architectures.Chapter 8. trap. The relationship between events and counters is programmed via API calls from the host.

PTX ISA Version 2.0 148 January 24. 2010 .

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %clock64 %pm0. %pm3 January 24. %lanemask_ge. %lanemask_le.Chapter 9. …. read-only variables. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_lt. %lanemask_gt %clock. Special Registers PTX includes a number of predefined. 2010 149 .

sreg .x * %ntid. // zero-extend tid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u32 %r1. %tid.v4 .sreg . .%tid.x.%ntid.%tid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. Redefined as . 2D. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.%h1. mad.x code Target ISA Notes Examples 150 January 24.z. . Supported on all target architectures.y * %ntid.x < %ntid. The %tid special register contains a 1D.z == 0 in 2D CTAs.y.u32 %h1.sreg .z == 1 in 2D CTAs. the fourth element is unused and always returns zero.PTX ISA Version 2.u16 %rh. Redefined as .0. mov.u32 %h2.y == %tid. %ntid.x to %rh Target ISA Notes Examples // legacy PTX 1.0. // compute unified thread id for 2D CTA mov.v4. the %tid value in unused dimensions is 0.0. mov. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.y.x 0 <= %tid. The fourth element is unused and always returns zero. mov.z PTX ISA Notes Introduced in PTX ISA version 1. read-only special register initialized with the number of thread ids in each CTA dimension. // move tid.z.v4 . read-only. or 3D vector to match the CTA shape. 2010 . CTA dimensions are non-zero. mov.u16 %r2.z.y.u32 type in PTX 2.sreg . Every thread in the CTA has a unique %tid. . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. %ntid.y < %ntid. The number of threads in each dimension are specified by the predefined special register %ntid.u32 type in PTX 2.0.u16 %rh.z < %ntid.z to %r2 Table 113.%r0. %ntid.x.u32 %tid.%h2.x.0 Table 112. .u32 %r0.x code accessing 16-bit component of %tid mov.%tid. // CTA shape vector // CTA dimensions A predefined.v4.z == 1 in 1D CTAs.y == %ntid. %tid.z). // thread id vector // thread id components A predefined. Supported on all target architectures. %tid component values range from 0 through %ntid–1 in each CTA dimension.x.%ntid.u32 %tid.z == 0 in 1D CTAs. cvt. per-thread special register initialized with the thread identifier within the CTA. PTX ISA Notes Introduced in PTX ISA version 1.y 0 <= %tid. // legacy PTX 1.x.u32 %r0.x. The total number of threads in a CTA is (%ntid.u32 %ntid.x.%tid. %ntid. It is guaranteed that: 0 <= %tid. %tid. %tid.%tid.u32 %ntid.u32.

A predefined.3. Introduced in PTX ISA version 1. The warp identifier will be the same for all threads within a single warp. e.u32 %r. PTX ISA Notes Target ISA Notes Examples Table 116. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.u32 %nwarpid. %laneid. mov. For this reason.sreg . %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Note that %warpid is volatile and returns the location of a thread at the moment when read. A predefined.u32 %r.sreg . 2010 151 . read-only special register that returns the thread’s lane within the warp. A predefined. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. due to rescheduling of threads following preemption. Supported on all target architectures. .0. Introduced in PTX ISA version 2. Special Registers Table 114.sreg . read-only special register that returns the thread’s warp identifier. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. but its value may change during execution. January 24.u32 %r.g. Introduced in PTX ISA version 1. Supported on all target architectures.Chapter 9. . . mov. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %warpid. The lane identifier ranges from zero to WARP_SZ-1. read-only special register that returns the maximum number of warp identifiers. %warpid. %nwarpid. Table 115. mov.3. %nwarpid requires sm_20 or later.u32 %laneid. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.

Each vector element value is >= 0 and < 65535.z < %nctaid. The %nctaid special register contains a 3D grid shape vector.u32 %nctaid .0. with each element having a value of at least 1.PTX ISA Version 2.0.%nctaid. %ctaid.v4.%nctaid.%ctaid.y 0 <= %ctaid.z PTX ISA Notes Introduced in PTX ISA version 1.%nctaid.v4 .sreg . Supported on all target architectures.sreg .{x.y.u32 type in PTX 2. .u32 %nctaid.536 PTX ISA Notes Introduced in PTX ISA version 1. The fourth element is unused and always returns zero. mov. Supported on all target architectures. // CTA id vector // CTA id components A predefined.u32 %ctaid.u32 mov.z. // legacy PTX 1.u16 %r0.x. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. %ctaid.u32 type in PTX 2.x 0 <= %ctaid.x < %nctaid. read-only special register initialized with the CTA identifier within the CTA grid.u32 %ctaid. depending on the shape and rank of the CTA grid. It is guaranteed that: 0 <= %ctaid. .v4 . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.0. // Grid shape vector // Grid dimensions A predefined.0. Redefined as . Redefined as .sreg . // legacy PTX 1. The fourth element is unused and always returns zero.0 Table 117. %rh.y.y.%ctaid. or 3D vector.y < %nctaid. The %ctaid special register contains a 1D.%nctaid.z. read-only special register initialized with the number of CTAs in each grid dimension.v4.y.x code Target ISA Notes Examples 152 January 24. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.x.x.u32 mov. 2D. %rh.x. .u16 %r0. It is guaranteed that: 1 <= %nctaid.x code Target ISA Notes Examples Table 118.x. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. mov. 2010 .sreg .z} < 65.

A predefined. %nsmid. mov.u32 %smid. read-only special register initialized with the per-grid temporal grid identifier. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.3. Note that %smid is volatile and returns the location of a thread at the moment when read. The SM identifier numbering is not guaranteed to be contiguous.u32 %gridid. .0. Special Registers Table 119.u32 %nsmid. . A predefined. due to rescheduling of threads following preemption. PTX ISA Notes Target ISA Notes Examples Table 121. During execution. e. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. The SM identifier numbering is not guaranteed to be contiguous.u32 %r. Introduced in PTX ISA version 1. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. PTX ISA Notes Target ISA Notes Examples January 24.sreg .0.Chapter 9. This variable provides the temporal grid launch number for this context. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.u32 %r. 2010 153 . mov. so %nsmid may be larger than the physical number of SMs in the device. repeated launches of programs may occur. read-only special register that returns the maximum number of SM identifiers. // initialized at grid launch A predefined. Introduced in PTX ISA version 2. but its value may change during execution.sreg . where each launch starts a grid-of-CTAs. %smid. . %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov. Supported on all target architectures.sreg . The SM identifier ranges from 0 to %nsmid-1. Supported on all target architectures. Introduced in PTX ISA version 1. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Notes PTX ISA Notes Target ISA Notes Examples Table 120.g.u32 %r. %nsmid requires sm_20 or later. %gridid.

mov. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg .0. %lanemask_eq.u32 %lanemask_le. %lanemask_eq requires sm_20 or later. Introduced in PTX ISA version 2. Table 124. %lanemask_le requires sm_20 or later.u32 %lanemask_eq. mov. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. %lanemask_le. Introduced in PTX ISA version 2. .u32 %r. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. 154 January 24. mov. A predefined.PTX ISA Version 2.u32 %r. %lanemask_lt.sreg . 2010 .0 Table 122. A predefined. A predefined.u32 %r. . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. . %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Table 123.0.0.sreg .u32 %lanemask_lt.

A predefined. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Table 126. mov. Introduced in PTX ISA version 2.0. 2010 155 . A predefined. .u32 %lanemask_gt.u32 %r.Chapter 9.0.sreg . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %lanemask_ge. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. Introduced in PTX ISA version 2.u32 %r. %lanemask_gt requires sm_20 or later. %lanemask_gt. January 24.sreg . Special Registers Table 125. %lanemask_ge. . %lanemask_ge requires sm_20 or later.

u64 %clock64. 156 January 24. mov.3. Their behavior is currently undefined. 2010 .u32 %pm0. read-only 64-bit unsigned cycle counter.sreg . Supported on all target architectures. …. %pm1. %pm2. mov. and %pm3 are unsigned 32-bit read-only performance monitor counters. Special Registers: %pm0.PTX ISA Version 2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.%pm0.u64 r1. mov. .sreg . Introduced in PTX ISA version 1.u32 r1.0 Table 127. %pm2.u32 r1. %pm1. Supported on all target architectures. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. The lower 32-bits of %clock64 are identical to %clock. %pm3. Special registers %pm0. read-only 32-bit unsigned cycle counter.sreg . %pm2. .%clock. Table 128. . Introduced in PTX ISA version 1.u32 %clock. Introduced in PTX ISA version 2.%clock64. %pm1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.0. %pm3 %pm0. %clock64 requires sm_20 or later. Table 129.0. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.

target Table 130.0.Chapter 10. minor are integers Specifies the PTX language version number.version 1. Duplicate .version directives are allowed provided they match the original .4 January 24. .version . .minor // major. Each ptx file must begin with a . Supported on all target architectures.version directive. PTX File Directives: . 2010 157 .version major. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.0 . Directives 10.version 2. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version .version directive.version Syntax Description Semantics PTX version number.1. and the target architecture for which the code was generated. . Increments to the major number indicate incompatible changes to PTX.

immediately followed by a .f64 to .f64 storage remains as 64-bits. . but subsequent . Target sm_20 Description Baseline feature set for sm_20 architecture.texmode_unified) . Each PTX file must begin with a . Adds {atom.texref and .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.global. In general. sm_13.PTX ISA Version 2. sm_11. brkpt instructions. 2010 . where each generation adds new features and retains all features of previous generations. generations of SM architectures follow an “onion layer” model. 158 January 24.texmode_unified . texture and sampler information is referenced with independent .0. PTX File Directives: . Texturing mode introduced in PTX ISA version 1. texmode_independent. Therefore. Introduced in PTX ISA version 1. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Requires map_f64_to_f32 if any .red}. A program with multiple .target directive specifies a single target architecture. including expanded rounding modifiers.f64 instructions used.target Syntax Architecture and Platform target. Adds double-precision support.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Disallows use of map_f64_to_f32. Supported on all target architectures.global. A . Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_10. 64-bit {atom.red}. and an error is generated if an unsupported feature is used.target directive containing a target architecture and optional platform options.version directive.5.texref descriptor.f64 instructions used.shared. Texturing mode: (default is .0 Table 131. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.texmode_independent texture and sampler information is bound together and accessed via a single .samplerref descriptors. Adds {atom. PTX features are checked against the specified target architecture.red}.target directives can be used to change the set of target features allowed during parsing. with only half being used by instructions converted from . texmode_unified.target . sm_12. The following table summarizes the features in PTX that vary according to target architecture. Requires map_f64_to_f32 if any . PTX code generated for a given target can be run on later generation devices.f64 instructions used. The texturing mode is specified for an entire module and cannot be changed within the module. Note that . map_f64_to_f32 }. Requires map_f64_to_f32 if any .f32. vote instructions.

Chapter 10.target sm_20.target sm_13 // supports double-precision . 2010 159 . Directives Examples .target sm_10 // baseline target architecture . texmode_independent January 24.

5 and later.param . etc. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.param instructions. Semantics Specify the entry point for a kernel program. parameter variables are declared in the kernel body.PTX ISA Version 2. Parameters may be referenced by name within the kernel body and loaded into registers using ld. parameters. ld. These parameters can only be referenced by name within texture and surface load. opaque .param.param instructions.entry Syntax Description Kernel entry point and body. and .param. 2010 .b32 %r3.entry . PTX ISA Notes For PTX ISA version 1. ld. The shape and size of the CTA executing the kernel are available in special registers. Supported on all target architectures. Kernel and Function Directives: .g.param space memory and are listed within an optional parenthesized parameter list. 160 January 24. … } .samplerref.reg .b32 %r1.b32 %r<99>.param.0 10.2. %nctaid. In addition to normal parameters. and body for the kernel function.entry filter ( .b32 y.0 through 1. . . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.4.4 and later.entry kernel-name kernel-body Defines a kernel entry point name. [y]. with optional parameters. At kernel launch. Parameters are passed via .func Table 132.surfref variables may be passed as parameters. and query instructions and cannot be accessed via ld. store. For PTX ISA versions 1.3.entry cta_fft .entry kernel-name ( param-list ) kernel-body . parameter variables are declared in the kernel parameter list.entry . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. e.b32 %r2.param { . . %ntid.b32 z ) Target ISA Notes Examples [x].b32 x. .param . . ld. the kernel dimensions and properties are established and made available via special registers.texref. [z].0 through 1. .

Semantics The PTX syntax hides all details of the underlying calling convention and ABI.func definition with no body provides a function prototype.param instructions in the body. .func (.func (ret-param) fname (param-list) function-body Defines a function.reg .2 for a description of variadic functions. Variadic functions are represented using ellipsis following the last fixed argument.Chapter 10. parameters must be in the register state space. which may use a combination of registers and stack locations to pass parameters.b32 rval) foo (.0 with target sm_20 allows parameters in the . PTX ISA 2. val1). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 dbl) { . including input and return parameters and optional function body. PTX 2.reg . … use N. .result.x code. there is no stack.func Syntax Function definition. Parameters must be base types in either the register or parameter state space. mov. The parameter lists define locally-scoped variables in the function body. Parameter passing is call-by-value. Parameters in . Directives Table 133.func . foo.0.0 with target sm_20 supports at most one return value. (val0. if any.func fname (param-list) function-body . and recursion is illegal.param state space. } … call (fooval). other code. dbl. 2010 161 . Kernel and Function Directives: .reg .param and st. implements an ABI with stack.param space are accessed using ld. Supported on all target architectures. The implementation of parameter passing is left to the optimizing translator.b32 N. and supports recursion. … Description // return value in fooval January 24. Variadic functions are currently unimplemented.reg .b32 rval.b32 localVar. Release Notes For PTX ISA version 1. A .func fname function-body . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. . ret. Parameters in register state space may be referenced directly within instructions in the function body.

pragma directives may appear at module (file) scope. The directives take precedence over any module-level constraints passed to the optimizing backend.0 10.g.minnctapersm directives may be applied per-entry and must appear between an . the . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. 162 January 24.maxntid and .minnctapersm . at entry-scope. These can be used. and the strings have no semantics within the PTX virtual machine model. or as statements within a kernel or device function body. A general .maxntid.3. .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. to throttle the resource requirements (e. for example. registers) to increase total thread count and provide a greater opportunity to hide memory latency.maxnreg.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.pragma The .maxntid directive specifies the maximum number of threads in a thread block (CTA). The directive passes a list of strings to the backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. the .PTX ISA Version 2. The .entry directive and its body.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). PTX supports the following directives. . The interpretation of .maxnreg .maxnctapersm (deprecated) . Currently. 2010 . Note that . and the . and . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxntid . which pass information to the backend optimizing compiler.pragma directive is supported for passing information to the PTX backend.

4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. or 3D CTA. Performance-Tuning Directives: . .maxntid 16.maxntid . 2D. The actual number of registers used may be less.Chapter 10. Performance-Tuning Directives: . 2010 163 . the backend may be able to compile to fewer registers. Directives Table 134.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. ny.3. . for example. ny .maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid and .entry bar .maxntid Syntax Maximum number of threads in thread block (CTA). Exceeding any of these limits results in a runtime error or kernel launch failure. The compiler guarantees that this limit will not be exceeded.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. Supported on all target architectures. Introduced in PTX ISA version 1. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxctapersm.16. .3. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. nz Declare the maximum number of threads in the thread block (CTA).maxntid nx. Supported on all target architectures.maxnreg .maxntid 256 .maxntid nx .entry foo .maxntid nx. or the maximum number of registers may be further constrained by . . Introduced in PTX ISA version 1. The maximum number of threads is the product of the maximum extent in each dimension.entry foo .

entry foo . .maxnctapersm (deprecated) . Optimizations based on .maxntid 256 .entry foo . Optimizations based on . . .minnctapersm in PTX ISA version 2. additional CTAs may be mapped to a single multiprocessor.0 Table 136. .maxntid and . Performance-Tuning Directives: .maxntid to be specified as well.minnctapersm 4 { … } 164 January 24.3. Introduced in PTX ISA version 1.maxntid to be specified as well. .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Performance-Tuning Directives: .minnctapersm generally need . if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxntid 256 .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm. Supported on all target architectures.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Introduced in PTX ISA version 2.maxnctapersm generally need . The optimizing backend compiler uses .minnctapersm .0.0.PTX ISA Version 2. For this reason. Deprecated in PTX ISA version 2.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. Supported on all target architectures.maxnctapersm has been renamed to . 2010 .0 as a replacement for . However.

Performance-Tuning Directives: . 2010 165 .pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas.0. { … } January 24. Introduced in PTX ISA version 2. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . or statement-level directives to the PTX backend compiler.pragma list-of-strings . or at statementlevel. entry-scoped.entry foo . Directives Table 138.pragma . at entry-scope. Supported on all target architectures.pragma Syntax Description Pass directives to PTX backend compiler. .pragma “nounroll”. The .Chapter 10.pragma directive may occur at module-scope. The interpretation of . . Pass module-scoped.

section .byte 0x2b.loc The .byte 0x00. Deprecated as of PTX 2.232-1] .section . 0x02. 0x00. 0x61395a5f. 0x00 .0 and replaces the @@DWARF syntax.0. @@DWARF dwarf-string dwarf-string may have one of the . 0x00.2.section directive is new in PTX ISA verison 2.quad int64-list // comma-separated hexadecimal integers in range [0. Introduced in PTX ISA version 1. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. “”. 0x5f736f63 . Table 139.4byte .. 0x00. The @@DWARF syntax is deprecated as of PTX version 2.4byte label . Supported on all target architectures. 0x00 166 January 24.byte byte-list // comma-separated hexadecimal byte values . replaced by .section directive.0 but is supported for legacy PTX version 1. 0x736d6172 .4.4byte 0x6e69616d.4byte int32-list // comma-separated hexadecimal integers in range [0. @progbits .4byte 0x000006b5. 0x63613031. 2010 .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x00.file .264-1] . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .x code..0 10.PTX ISA Version 2. 0x00000364. 0x00.debug_info . 0x6150736f.debug_pubnames. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x00.

} 0x02. . 0x00 0x61395a5f.b8 0x00.section section_name { dwarf-lines } dwarf-lines have the following formats: . 0x00. . 0x00. Supported on all target architectures.b8 byte-list // comma-separated list of integers in range [0. .255] . . Debugging Directives: . . 2010 167 .debug_pubnames { .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Source file location.0. . 0x00000364.b32 . 0x00.section .debug_info .section Syntax PTX section definition.b32 0x000006b5.b32 label .b32 0x6e69616d.section . 0x00. 0x00..0.b32 int32-list // comma-separated list of integers in range [0. 0x736d6172 0x00 Table 141. Supported on all target architectures. 0x63613031. 0x00.file .Chapter 10. Debugging Directives: . Directives Table 140.264-1] ..loc line_number January 24.0.loc .232-1] .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b64 int64-list // comma-separated list of integers in range [0.. Source file information. .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x5f736f63 0x6150736f. Supported on all target architectures. replaces @@DWARF syntax.b8 0x2b.file filename Table 142. Debugging Directives: .

extern identifier Declares identifier to be defined externally. Introduced in PTX ISA version 1. Supported on all target architectures.global . Linking Directives: .extern .global .extern . Introduced in PTX ISA version 1.PTX ISA Version 2.0. Linking Directives: .b32 foo.0 10.0.b32 foo. .visible .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible . .visible Table 143.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures. 2010 .visible identifier Declares identifier to be externally visible. .extern . // foo will be externally visible 168 January 24.6. Linking Directives . // foo is defined in another module Table 144. .

1 CUDA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.4 PTX ISA 1.3 driver r190 CUDA 3.1 CUDA 2. 2010 169 .1 PTX ISA 1.5 PTX ISA 2. The release history is as follows.0 PTX ISA 1. CUDA Release CUDA 1.0 CUDA 2. and the remaining sections provide a record of changes in previous releases.3 PTX ISA 1.0 January 24.Chapter 11.0 driver r195 PTX ISA Version PTX ISA 1.2 PTX ISA 1.2 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.0.0 CUDA 1.

0 for sm_20 targets.0 11. The fma.ftz and . Both fma.1.1. Changes in Version 2. The mad. 2010 .f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. • • • • • 170 January 24. and sqrt with IEEE 754 compliant rounding have been added. fma.f32 for sm_20 targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. The goal is to achieve IEEE 754 compliance wherever possible. A single-precision fused multiply-add (fma) instruction has been added. and mul now support .ftz modifier may be used to enforce backward compatibility with sm_1x.rm and .f32 require a rounding modifier for sm_20 targets. mad.f32 requires sm_20.1. rcp. while maximizing backward compatibility with legacy PTX 1.f32. The mad.1.f32 instruction also supports . sub. Instructions testp and copysign have been added. Floating-Point Extensions This section describes the floating-point changes in PTX 2.rn.PTX ISA Version 2.1. New Features 11. When code compiled for sm_1x is executed on sm_20 devices.rp rounding modifiers for sm_20 targets. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The changes from PTX ISA 1.f32 maps to fma. Single. Single-precision add.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.0 11.sat modifiers.and double-precision div. These are indicated by the use of a rounding modifier and require sm_20. The .f32 and mad.1.x code and sm_1x targets.

ballot. have been added. A new directive.red}. Instruction sust now supports formatted surface stores. .1.section.gt} have been added. bar now supports optional thread count and register operands.red}. Instructions {atom. st. %lanemask_{eq. vote. bfind.popc.maxnctapersm directive was deprecated and replaced with . Video instructions (includes prmt) have been added.lt.clamp modifiers. Instructions {atom. bfe and bfi. membar. for prefetching to specified level of memory hierarchy. prefetchu.g. Cache operations have been added to instructions ld. A “find leading non-sign bit” instruction.red.shared have been extended to handle 64-bit data types for sm_20 targets.ge. e.1. has been added. has been added. has been added.1. has been added. A “vote ballot” instruction. and sust.zero. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. New instructions A “load uniform” instruction.Chapter 11. has been added. %clock64. ldu. New special registers %nsmid. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.{and. atom.3. A system-level membar instruction. cvta.sys. The bar instruction has been extended as follows: • • • A bar. . Bit field extract and insert instructions. Other new features Instructions ld. Instruction cvta for converting global. The . A “bit reversal” instruction. 11.u32 and bar. A “population count” instruction.1. isspacep. Surface instructions support additional . prefetch.red.clamp and . 2010 171 . Release Notes 11.minnctapersm to better match its behavior and usage. local.pred have been added.le. Instructions prefetch and prefetchu have also been added. st.b32. Instructions bar.add. brev. A “count leading zeros” instruction. January 24. suld.arrive instruction has been added. has been added. popc. clz.2. has been added. and red now support generic addressing. ldu.f32 have been implemented.or}. and shared addresses to generic address and vice-versa has been added.

f32} atom.p.4 and earlier.target sm_1x.2. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. Instruction bra. call suld.s32. {atom.PTX ISA Version 2.5 and later. Formatted surface load is unimplemented. has been fixed.u32. if .p sust.f32 type is unimplemented. .ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. In PTX version 1. or .s32.red}.4 or earlier.0 11. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. Support for variadic functions and alloca are unimplemented. cvt. the correct number is sixteen. 11.{min. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.1.ftz for PTX ISA versions 1. 172 January 24. Formatted surface store with .max} are not implemented. See individual instruction descriptions for details.f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. 2010 . stack-based ABI is unimplemented. The underlying.version is 1. To maintain compatibility with legacy PTX code. where .1.5.ftz (and cvt for . Semantic Changes and Clarifications The errata in cvt.{u32.3.

pragma strings defined by ptxas. Descriptions of . . including loops preceding the .pragma Strings This section describes the . Note that in order to have the desired effect at statement level.func bar (…) { … L1_head: . … @p bra L1_end. disables unrolling of0 the loop for which the current block is the loop header. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. disables unrolling for all loops in the entry function body.0. 2010 173 . Ignored for sm_1x targets. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. .Appendix A.pragma “nounroll”. L1_body: … L1_continue: bra L1_head.pragma “nounroll”. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Table 145.pragma. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.entry foo (…) .pragma “nounroll”. { … } // do not unroll any loop in this function . entry-function. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. The “nounroll” pragma is allowed at module. Supported only for sm_20 targets. and statement levels. L1_end: … } // do not unroll this loop January 24. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.

2010 .0 174 January 24.PTX ISA Version 2.

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