NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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............4......4..........................................................1.....5....4......................................................1............................. 27 Register State Space .............................................. 30 Shared State Space.........1.... 5..........................PTX ISA Version 2.........................4........6....................8................. 25 Chapter 5.................... 5...........6............4..........................................................................................2.............................................5.. 5..7.. 28 Constant State Space .............. 33 5............................................ 5....................6...................................... State Spaces.......................... 33 Fundamental Types ......................................4............ 5...... Chapter 6.................... 41 Source Operands.................................... 6...................2.....................4......................... 39 Parameterized Variable Names .......... 2010 .............................1..........................................................2................................... 6............ 39 5........... and Vectors .......0 4.... 49 7................ 6..............2.......................1...............3...................... 37 Vectors ........................................................................................................ Sampler........................... 5............ 29 Local State Space ........... 5................................................................................1.............. 42 Arrays as Operands .............. and Surface Types ..................................... 41 Destination Operands ............................................5....................................................... Type Conversion.........................................1....................................1...............2........................ 29 Global State Space .... 5...................................... 41 Using Addresses............................................... 43 6... 43 Labels and Function Names as Operands ....4...........................................................2.............................................. Arrays................................................................. 44 Rounding Modifiers ........... 32 Texture State Space (deprecated) ...................1. Instruction Operands...................... 5...........5.............4........................................... 41 6....................................................... Operand Type Information .........5.......... 44 Scalar Conversions .................................... 5................... 6................................... 5.. 5................................4............................................................6............ 43 Vectors as Operands ..................................................... Operand Costs .........................1.......... 37 Variable Declarations ............................... 6..3..................2... 33 Restricted Use of Sub-Word Sizes ....1......... and Variables .............................................................. Types .......................................................4.................. 42 Addresses as Operands ..................... 37 Array Declarations .....4............................................................4.........1... 27 5....4.................. 28 Special Register State Space ..............................3.. 47 Chapter 7............. 5...................................1........................... 5..............................1..................................1..3.................................................. 34 Variables ........................... 5.................... 46 6........ Abstracting the ABI ......... 6............................................................................... State Spaces ........................................... 6..........3........................... 38 Alignment ......2............... 29 Parameter State Space .....................2......................... 49 ii January 24...................................5.............1...................... Function declarations and definitions ..................... 6... Texture................. 6................................ 38 Initializers .................................................................4....................... Summary of Constant Expression Evaluation Rules ............................. Types........ 32 5.................................... 5...............

.....4.................... 62 Machine-Specific Semantics of 16-bit Code .........................7................................. 60 8.............................................................................................................................................. 58 8............................................... 8...............7...............5........... 57 Manipulating Predicates ...... 55 Predicated Execution ....................................... 8..........................4......10.........................6............................................................. 166 Linking Directives . Instructions ........................................ Divergence of Threads in Control Constructs ......7............. 8..........6............................ 10................................................ 62 Semantics .......................................1.................... PTX Version and Target Directives .................1........ 8............................................. 8..........................x ................................ 53 Alloca ...................................................... 2010 iii ..... 129 Parallel Synchronization and Communication Instructions ........... Changes in Version 2.......... 157 Specifying Kernel Entry Points and Functions ................... 7................................................2....................................2.............................2....7............... 8.............. 132 Video Instructions .................................................................. 8.................7...................................................... Format and Semantics of Instruction Descriptions ........................................... 170 New Features ........... 8. 55 PTX Instructions .............................................. 172 Unimplemented Features Remaining ................................... 81 Comparison and Selection Instructions .................6... Changes from PTX 1................ 160 Performance-Tuning Directives ......1.............................. 10..............3.............................3..................................4........1.....................................7..........................................................................2..3.7....................... 104 Data Movement and Conversion Instructions .............. 100 Logic and Shift Instructions ...........5............................................... 172 January 24..........................................................3...................................... 11.................................................................................................................................7. 10... 63 Floating-Point Instructions ..1...................................................... 10.............1............3...1.... 8............................2...............................................................2............................................................... 8... 8................................................................ 8................................................ 149 Chapter 10.. 147 8.... 162 Debugging Directives ..................................9.......... 8.......1. 11............ Type Information for Instructions and Operands ................... 169 11... 170 Semantic Changes and Clarifications ... 168 Chapter 11.7..............4........ 11. 59 Operand Size Exceeding Instruction-Type Size .......7............. Directives ..................................................................... 8.... Special Registers ......... 54 Chapter 8...3................. Instruction Set ...................7..........................0 .................................................................................................1...................... 62 8.......8..6...........................3..... Release Notes .............................1................................... 108 Texture and Surface Instructions ................... 55 8........ 63 Integer Arithmetic Instructions ....................... 140 Miscellaneous Instructions.................1.......... 56 Comparisons .............. 8...................... 52 Variadic functions .. Chapter 9...... 7.......... 122 Control Flow Instructions ..................................... 157 10..............................7..................................................................................1............ 8.........................................7..........................1.................

.0 Appendix A............................ 2010 ....PTX ISA Version 2.................... Descriptions of .. 173 iv January 24.pragma Strings............

.......................................... Table 22.................. 65 Integer Arithmetic Instructions: sub.... 45 Floating-Point Rounding Modifiers ................................... Table 9........................... Table 19.................................................................................... Table 28.................. Table 18.........................List of Tables Table 1............ Table 17.................. 33 Opaque Type Fields in Unified Texture Mode ......... 46 Cost Estimates for Accessing State-Spaces .................... Table 27.... 18 Reserved Instruction Keywords ........................ Table 20......... 64 Integer Arithmetic Instructions: add........................................... 69 Integer Arithmetic Instructions: mad24 ... 46 Integer Rounding Modifiers .................... 58 Type Checking Rules .............. 20 Operator Precedence .......................................... Table 2......................................................................................................................................................................................................................... Table 10.. Table 7... 60 Relaxed Type-checking Rules for Destination Operands.. 68 Integer Arithmetic Instructions: mul24 ........... Table 4....................... Table 13.................................................................... Table 15..........cc ................................................. Table 14........ Table 8..................................................................................... 57 Floating-Point Comparison Operators Accepting NaN ............................................... 65 Integer Arithmetic Instructions: addc ........ 66 Integer Arithmetic Instructions: mul ... Table 3.... Table 32.......................cc ............................................................... 57 Floating-Point Comparison Operators ................. 25 State Spaces ...................................... 28 Fundamental Type Specifiers ..... 47 Operators for Signed Integer............... 2010 v .... 58 Floating-Point Comparison Operators Testing for NaN ................................. 35 Opaque Type Fields in Independent Texture Mode . 64 Integer Arithmetic Instructions: sub ..................................... Table 12...... Table 24............................................. Table 5................................................. 70 Integer Arithmetic Instructions: sad ........................................................ 19 Predefined Identifiers ......................................................................... Table 25.......................................................................... Table 6............ 27 Properties of State Spaces ............................................................................... PTX Directives ........ Table 30.............................................. Unsigned Integer....................................... Table 26.............. Table 29.................. 35 Convert Instruction Precision and Format ...................................................... 71 January 24................................................................... Table 11................................ 23 Constant Expression Evaluation Rules ................................................................... Table 21................................................ 59 Relaxed Type-checking Rules for Source Operands ...... Table 31...................... Table 23.............................................................. 66 Integer Arithmetic Instructions: subc ........................................................................................ Table 16........ 61 Integer Arithmetic Instructions: add ........................................................... 67 Integer Arithmetic Instructions: mad ................................ and Bit-Size Types ...................

................................................................................................................................................................................................................. 84 Floating-Point Instructions: sub ................................... 92 Floating-Point Instructions: max ..................................................................................................................... 82 Floating-Point Instructions: testp ..................................................................................... Table 67............................ Table 49.............................................. 93 Floating-Point Instructions: sqrt .............................................................. 83 Floating-Point Instructions: add ....................... Table 40...... 94 Floating-Point Instructions: rsqrt ...................................... Table 61.................... Table 62.............................................................. Table 48........................................................ Table 35............ 99 Comparison and Selection Instructions: set ............................................. 87 Floating-Point Instructions: mad .................. 2010 .................... 98 Floating-Point Instructions: ex2 ............ Table 60.................................... Table 68.................................................... Table 64...................................... Table 59..................... Table 43.............. Table 69... 73 Integer Arithmetic Instructions: popc ..................0 Table 33........................................................ 78 Integer Arithmetic Instructions: prmt ............................................................ 86 Floating-Point Instructions: fma ........................ 72 Integer Arithmetic Instructions: neg ........................................ Table 46.................... 102 Comparison and Selection Instructions: selp .............. 103 vi January 24.............................................................. Table 57.............. Table 38..... Table 41...............PTX ISA Version 2.... Table 34. 74 Integer Arithmetic Instructions: bfind ... Table 56................. Table 54........................................................................................................... 95 Floating-Point Instructions: sin ...................................... 72 Integer Arithmetic Instructions: min ............................................................................................................................................... 79 Summary of Floating-Point Instructions ........................ Table 45............................................................................................. 88 Floating-Point Instructions: div ...... 103 Comparison and Selection Instructions: slct .......................... Table 42..................................... 76 Integer Arithmetic Instructions: bfe .......................... Table 51......................... 97 Floating-Point Instructions: lg2 ................................................. 83 Floating-Point Instructions: copysign ................................................................................................... Table 58........................ Table 36...... Table 44....... Table 50.................................. 90 Floating-Point Instructions: abs ........................ Table 63...................... Table 39................................................................. 92 Floating-Point Instructions: rcp ............ 91 Floating-Point Instructions: min ................ Table 53........................ Table 65......................................... 77 Integer Arithmetic Instructions: bfi .......... 96 Floating-Point Instructions: cos ............................................................ 91 Floating-Point Instructions: neg ................... 71 Integer Arithmetic Instructions: rem ...................................... Table 47.................. Table 52...................................................... 71 Integer Arithmetic Instructions: abs ................................ 75 Integer Arithmetic Instructions: brev ............ Integer Arithmetic Instructions: div ............. 73 Integer Arithmetic Instructions: max ........... 74 Integer Arithmetic Instructions: clz ........................................... Table 66................... 101 Comparison and Selection Instructions: setp .................................. Table 37............... 85 Floating-Point Instructions: mul .......................... Table 55.................................................

......................................... Table 91..................................................... Table 103.............................................................................................................................. Table 72..... Table 94...... Table 102........................................... 111 Data Movement and Conversion Instructions: mov ................................. 116 Data Movement and Conversion Instructions: prefetch........................................................ 119 Data Movement and Conversion Instructions: cvt ............................... 135 Parallel Synchronization and Communication Instructions: red ............. 105 Logic and Shift Instructions: or ....... 131 Parallel Synchronization and Communication Instructions: bar ........ 143 January 24... 119 Data Movement and Conversion Instructions: cvta ..................................................... Table 76........................................................ Table 97.............................................. 106 Logic and Shift Instructions: shl ................................... Table 75............ Table 96....................................... 107 Logic and Shift Instructions: shr ....... 139 Video Instructions: vadd... Table 77.......................................... 106 Logic and Shift Instructions: cnot .................... 106 Logic and Shift Instructions: not .. 2010 vii .................... Table 82.... Table 79............................ Table 95.................................. vmin.............. Table 93......... Table 87................................................... 130 Control Flow Instructions: ret .............. 107 Cache Operators for Memory Load Instructions ................................................ 118 Data Movement and Conversion Instructions: isspacep ...... vabsdiff...................................... Table 85. Table 78...................... Table 100.... Table 92........................... Table 84................................ 128 Control Flow Instructions: { } ................. 130 Control Flow Instructions: call ........... 112 Data Movement and Conversion Instructions: ld .......................................................... 137 Parallel Synchronization and Communication Instructions: vote ............... 133 Parallel Synchronization and Communication Instructions: membar ................ 123 Texture and Surface Instructions: txq ........................................................................................................................... Table 83... 126 Texture and Surface Instructions: sured.......Table 70............. 129 Control Flow Instructions: bra .......... Table 88..................... 113 Data Movement and Conversion Instructions: ldu .... Table 104............... Table 71........ 115 Data Movement and Conversion Instructions: st ..................................... 109 Cache Operators for Memory Store Instructions .... Table 98................................................................. Table 81................ vsub..... 110 Data Movement and Conversion Instructions: mov .............................................................................................. 124 Texture and Surface Instructions: suld .............. Table 90.............................. 125 Texture and Surface Instructions: sust ........................ 142 Video Instructions: vshl................................................................ Table 86................................................................................................ 129 Control Flow Instructions: @ .................................................................... Table 73................................................ vshr .................. prefetchu ................. Table 105......... Table 106. Table 80... vmax .. 105 Logic and Shift Instructions: xor ..................... 127 Texture and Surface Instructions: suq ................... Table 74............................................... 120 Texture and Surface Instructions: tex .... 134 Parallel Synchronization and Communication Instructions: atom ................................ Logic and Shift Instructions: and ........... Table 89........ Table 101.......................... 131 Control Flow Instructions: exit ... Table 99..............................

................................................. 150 Special Registers: %ntid .......................................... %pm3 ........................................................... Table 121........................................................................... Table 122................... Table 143.......................................... Table 125............................................. 152 Special Registers: %smid ..........loc ................. Table 130......................... 161 Performance-Tuning Directives: .................................................................... 167 Linking Directives: ............................................................................................................................version............... 147 Miscellaneous Instructions: brkpt .................................................................. Table 131............................................... Table 111................ 153 Special Registers: %lanemask_eq ............ 151 Special Registers: %warpid ....PTX ISA Version 2...................... 164 Performance-Tuning Directives: .......................................... Table 115............. Table 117.. Table 132...... 152 Special Registers: %nctaid .......... %pm1........... 153 Special Registers: %nsmid ........................ Table 123........................................................ 163 Performance-Tuning Directives: ..... 157 PTX File Directives: ...................................................................target ...... Table 141............................................................extern....................... Table 138.maxntid ............................... Table 136............maxnreg ........... 167 Debugging Directives: .......... Table 116. 146 Miscellaneous Instructions: trap .................. 144 Video Instructions: vset.................................................................................................. Table 119................................................................ Table 109.................................................. 163 Performance-Tuning Directives: .............................pragma ....file ....... 156 PTX File Directives: .................... Table 140........................ 156 Special Registers: %pm0................................. 155 Special Registers: %clock .. Table 110.. Table 113... 167 Debugging Directives: .............. Table 129................................................. 165 Debugging Directives: @@DWARF ............................................ 153 Special Registers: %gridid ............................................ Table 133. Table 142... Video Instructions: vmad ............section ....................................................................................................... Table 124..................... 150 Special Registers: %laneid .... 151 Special Registers: %nwarpid .......... Table 126...... Table 114................... 156 Special Registers: %clock64 ........ 147 Miscellaneous Instructions: pmevent................................................................................................. 2010 ........... Table 137..minnctapersm ............. Table 108... 155 Special Registers: %lanemask_gt .......... Table 134.............................func ....................................................................... Table 127................. Table 120....... 154 Special Registers: %lanemask_lt .................................. 164 Performance-Tuning Directives: .........maxnctapersm (deprecated) ......................... Table 118................................... 151 Special Registers: %ctaid ................................................. 166 Debugging Directives: .... 154 Special Registers: %lanemask_ge ............................................entry............................................................................... Table 128....... %pm2........0 Table 107.................................... Table 139........... 168 viii January 24...... 147 Special Registers: %tid ..... 154 Special Registers: %lanemask_le .................... 160 Kernel and Function Directives: .... Table 112............................................................................................................................................................................. 158 Kernel and Function Directives: ................................................ Table 135...........................................

.........Table 144............... Table 145.......... Linking Directives: ...................... 173 January 24.............visible.................................................. 168 Pragma Strings: “nounroll” .......................................... 2010 ix ..........

2010 .0 x January 24.PTX ISA Version 2.

Many applications that process large data sets can use a data-parallel programming model to speed up the computations. from general signal processing or physics simulation to computational finance or computational biology. stereo vision. video encoding and decoding. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. PTX exposes the GPU as a data-parallel computing device. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Data-parallel processing maps data elements to parallel processing threads. image and media processing applications such as post-processing of rendered images. PTX programs are translated at install time to the target hardware instruction set. In fact. Introduction This document describes PTX. the memory access latency can be hidden with calculations instead of big data caches. Similarly. January 24. a low-level parallel thread execution virtual machine and instruction set architecture (ISA).2. many-core processor with tremendous computational horsepower and very high memory bandwidth.1. and because it is executed on many data elements and has high arithmetic intensity. which are optimized for and translated to native target-architecture instructions. high-definition 3D graphics. and pattern recognition can map image blocks and pixels to parallel processing threads.Chapter 1. image scaling. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. the programmable GPU has evolved into a highly parallel. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. 1. 1. multithreaded. 2010 1 . there is a lower requirement for sophisticated flow control. Because the same program is executed for each data element. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. PTX defines a virtual machine and ISA for general purpose parallel thread execution.

fma.f32 instruction also supports .sat modifiers.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Achieve performance in compiled applications comparable to native GPU performance.0 is a superset of PTX 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.rm and . and mul now support .ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.f32.3.0 is in improved support for the IEEE 754 floating-point standard. Provide a common source-level ISA for optimizing code generators and translators. reduction.1.f32 require a rounding modifier for sm_20 targets. The changes from PTX ISA 1. mad.rp rounding modifiers for sm_20 targets. and architecture tests.f32 and mad.ftz and . A single-precision fused multiply-add (fma) instruction has been added. The mad. When code compiled for sm_1x is executed on sm_20 devices.rn. Both fma. PTX 2. memory.x features are supported on the new sm_20 target.3. Legacy PTX 1. The mad. Instructions marked with . and the introduction of many new instructions. Provide a code distribution ISA for application and middleware developers. • • • 2 January 24. 1. Single-precision add.PTX ISA Version 2. Most of the new features require a sm_20 target. 2010 . The fma.0 PTX ISA Version 2.0 are improved support for IEEE 754 floating-point operations.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. Facilitate hand-coding of libraries. PTX ISA Version 2. sub.f32 requires sm_20. performance kernels.f32 for sm_20 targets.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. and video instructions. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Provide a machine-independent ISA for C/C++ and other compilers to target. surface. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. including integer.x. which map PTX to specific target machines. atomic.f32 maps to fma. 1.ftz) modifier may be used to enforce backward compatibility with sm_1x. barrier. and all PTX 1. A “flush-to-zero” (. Improved Floating-Point Support A main area of change in PTX 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. addition of generic addressing to facilitate the use of general-purpose pointers. The main areas of change in PTX 2.x code will continue to run on sm_1x targets as well.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.

1. e. and directives are introduced in PTX 2. NOTE: The current version of PTX does not implement the underlying. i. Instruction cvta for converting global.2. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. New Instructions The following new instructions. prefetch. local. these changes bring PTX 2. In PTX 2. A new cvta instruction has been added to convert global. Support for an Application Binary Interface Rather than expose details of a particular calling convention.3.clamp and . cvta. local.g. Generic Addressing Another major change is the addition of generic addressing. and sust. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. local. prefetchu. January 24. and shared addresses to generic addresses.e.. . stack layout. atom. and shared state spaces. and Application Binary Interface (ABI). Cache operations have been added to instructions ld. • Taken as a whole. Introduction • Single. for prefetching to specified level of memory hierarchy. Instructions testp and copysign have been added. Instructions prefetch and prefetchu have been added.and double-precision div. PTX 2. and red now support generic addressing. st. an address that is the same across all threads in a warp. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. ldu.3. stack-based ABI.3. isspacep. These are indicated by the use of a rounding modifier and require sm_20.0 closer to full compliance with the IEEE 754 standard.Chapter 1.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Generic addressing unifies the global. suld. and sqrt with IEEE 754 compliant rounding have been added. st. special registers.0. instructions ld.3. 1. and shared addresses to generic address and vice-versa has been added. and vice versa. Surface instructions support additional clamp modifiers. Surface Instructions • • Instruction sust now supports formatted surface stores.zero. 1. so recursion is not yet supported. allowing memory instructions to access these spaces without needing to specify the state space.0. rcp. 2010 3 .4.

bfi bit field extract and insert popc clz Atomic.b32. Barrier Instructions • • A system-level membar instruction. Instructions bar.PTX ISA Version 2. %clock64.pred have been added.red.or}.ge.gt} have been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. New special registers %nsmid. %lanemask_{eq.shared have been extended to handle 64-bit data types for sm_20 targets.f32 have been added.ballot.red. 4 January 24.{and. Reduction. A “vote ballot” instruction.le. has been added. has been added. membar. 2010 . Instructions {atom.arrive instruction has been added.red}. . and Vote Instructions • • • New atomic and reduction instructions {atom. A bar. Other Extensions • • • Video instructions (includes prmt) have been added.add.red}. vote.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.u32 and bar.section.lt.popc. A new directive.sys. bar now supports an optional thread count and register operands.

2010 5 . Chapter 11 provides release notes for PTX Version 2. types. Introduction 1. calling convention. Chapter 9 lists special registers. and variable declarations. Chapter 5 describes state spaces. Chapter 3 gives an overview of the PTX virtual machine model.Chapter 1.4. Chapter 4 describes the basic syntax of the PTX language.0. Chapter 6 describes instruction operands. Chapter 7 describes the function and call syntax. Chapter 8 describes the instruction set. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 10 lists the assembly directives supported in PTX. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. January 24.

2010 .PTX ISA Version 2.0 6 January 24.

2D. 2. or 3D CTA.z) that specifies the thread’s position within a 1D. tid. compute-intensive portions of applications running on the host are off-loaded onto the device.Chapter 2. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. 2D. and select work to perform. Cooperative thread arrays (CTAs) implement CUDA thread blocks. assign specific input and output positions. Each CTA has a 1D. or 3D shape specified by a three-element vector ntid (with elements ntid. a portion of an application that is executed many times. Threads within a CTA can communicate with each other. ntid.x. Programming Model 2.1. A cooperative thread array. compute addresses.2. 2. To that effect. 2010 7 . The vector ntid specifies the number of threads in each CTA dimension. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.1. and ntid. but independently on different data.y. More precisely.y.x. data-parallel. and results across the threads of the CTA. work. To coordinate the communication of the threads within the CTA. The thread identifier is a three-element vector tid. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. January 24. Programs use a data parallel decomposition to partition inputs. and tid. It operates as a coprocessor to the main CPU. one can specify synchronization points where threads wait until all threads in the CTA have arrived. Each CTA thread uses its thread identifier to determine its assigned role. Each thread has a unique thread identifier within the CTA. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.2. or host: In other words. (with elements tid. is an array of threads that execute a kernel concurrently or in parallel. or CTA.z). can be isolated into a kernel function that is executed on the GPU as many different threads.

a warp has 32 threads. However. Typically. A warp is a maximal subset of threads from a single CTA. or sequentially. and %gridid. because threads in different CTAs cannot communicate and synchronize with each other.PTX ISA Version 2. Threads within a warp are sequentially numbered. WARP_SZ. The warp size is a machine-dependent constant.2. Each grid of CTAs has a 1D. Threads may read and use these values through predefined. %ntid.0 Threads within a CTA execute in SIMT (single-instruction. 2D . so that the total number of threads that can be launched in a single kernel invocation is very large. depending on the platform. or 3D shape specified by the parameter nctaid. This comes at the expense of reduced thread communication and synchronization. so PTX includes a run-time immediate constant. which may be used in any instruction where an immediate operand is allowed. Some applications may be able to maximize performance with knowledge of the warp size. multiple-thread) fashion in groups called warps. The host issues a succession of kernel invocations to the device. %nctaid. Each grid also has a unique temporal grid identifier (gridid). 2.2. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). %ctaid. Multiple CTAs may execute concurrently and in parallel. such that the threads execute the same instructions at the same time. CTAs that execute the same kernel can be batched together into a grid of CTAs. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. 2010 . 8 January 24. read-only special registers %tid.

2) Thread (1. 1) Thread (0. 2) Thread (2. 1) CTA (1. 2010 9 . 1) Thread (1.Chapter 2. Thread Batching January 24. 0) Thread (3. 0) Thread (4. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) CTA (2. 0) CTA (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. A grid is a set of CTAs that execute independently. 2) Thread (4. Figure 1. 1) CTA (2. 0) Thread (1. 1) Thread (2. 1) Thread (3. 0) CTA (0. 0) Thread (0. 0) Thread (2. 2) Thread (3. 1) Thread (0. 1) Thread (4. 1) Grid 2 Kernel 2 CTA (1.

and texture memory spaces are optimized for different memory usages. for more efficient transfer. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant. or. Both the host and the device maintain their own local memory. The device memory may be mapped and read or written by the host. The global. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Finally. 10 January 24.PTX ISA Version 2. as well as data filtering. referred to as host memory and device memory. The global. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. respectively. 2010 . constant.3. Texture memory also offers different addressing modes.0 2. for some specific data formats. and texture memory spaces are persistent across kernel launches by the same application. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Each thread has a private local memory. all threads have access to the same global memory.

2) Figure 2. 1) Block (1.Chapter 2. Memory Hierarchy January 24. 1) Block (1. 2) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (1. 1) Grid 1 Global memory Block (0. 0) Block (0. 2010 11 . 0) Block (2. 1) Block (2. 0) Block (0. 1) Block (0. 0) Block (1.

0 12 January 24. 2010 .PTX ISA Version 2.

so full efficiency is realized when all threads of a warp agree on their execution path. it splits them into warps that get scheduled by the SIMT unit. a voxel in a volume. Parallel Thread Execution Machine Model 3. new blocks are launched on the vacated multiprocessors. 2010 13 . (This term originates from weaving. If threads of a warp diverge via a data-dependent conditional branch. different warps execute independently regardless of whether they are executing common or disjointed code paths.1. manages. The way a block is split into warps is always the same. a multithreaded instruction unit. At every instruction issue time. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. A warp executes one common instruction at a time. and when all paths complete. the threads converge back to the same execution path. To manage hundreds of threads running several different programs. It implements a single-instruction barrier synchronization. schedules. and on-chip shared memory. The multiprocessor SIMT unit creates. The multiprocessor creates. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). When a host program invokes a kernel grid. the multiprocessor employs a new architecture we call SIMT (single-instruction. The threads of a thread block execute concurrently on one multiprocessor. As thread blocks terminate. the warp serially executes each branch path taken. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. Branch divergence occurs only within a warp. a cell in a grid-based computation). a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and executes concurrent threads in hardware with zero scheduling overhead. each warp contains threads of consecutive. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. manages. When a multiprocessor is given one or more thread blocks to execute.Chapter 3. The multiprocessor maps each thread to one scalar processor core. multiple-thread). and each scalar thread executes independently with its own instruction address and register state.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. A multiprocessor consists of multiple Scalar Processor (SP) cores. the first parallel thread technology. increasing thread IDs with the first warp containing thread 0. and executes threads in groups of parallel threads called warps. January 24. disabling threads that are not on that path. for example. allowing.

each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. If there are not enough registers or shared memory available per multiprocessor to process at least one block. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. which is a read-only region of device memory. but the order in which they occur is undefined. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. write to that location occurs and they are all serialized. SIMT enables programmers to write thread-level parallel code for independent. If an atomic instruction executed by a warp reads. • The local and global memory spaces are read-write regions of device memory and are not cached. whereas SIMT instructions specify the execution and branching behavior of a single thread. as well as data-parallel code for coordinated threads. but one of the writes is guaranteed to succeed. modifies. the programmer can essentially ignore the SIMT behavior. Vector architectures. the kernel will fail to launch. 2010 . each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A multiprocessor can execute as many as eight thread blocks concurrently. the number of serialized writes that occur to that location and the order in which they occur is undefined. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. on the other hand. require the software to coalesce loads into vectors and manage divergence manually. As illustrated by Figure 3. 14 January 24. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. and writes to the same location in global memory for more than one of the threads of the warp. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. scalar threads. For the purposes of correctness. each read. which is a read-only region of device memory. In contrast with SIMD vector machines. modify. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. In practice. A key difference is that SIMD vector organizations expose the SIMD width to the software. however.PTX ISA Version 2.0 SIMT architecture is akin to SIMD (Single Instruction.

Chapter 3. Figure 3. 2010 15 . Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

0 16 January 24.PTX ISA Version 2. 2010 .

target directive specifying the target architecture assumed. and using // to begin a comment that extends to the end of the current line. Syntax PTX programs are a collection of text source files. whitespace is ignored except for its use in separating tokens in the language. #ifdef.2. The following are common preprocessor directives: #include. See Section 9 for a more information on these directives. 4. Each PTX file must begin with a . Comments in PTX are treated as whitespace. 2010 17 . #if. Pseudo-operations specify symbol and addressing management. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor.Chapter 4. followed by a . 4. Lines are separated by the newline character (‘\n’). Source Format Source files are ASCII text.1. #endif. using non-nested /* and */ for comments that may span multiple lines. PTX is case sensitive and uses lowercase for keywords. #line. Lines beginning with # are preprocessor directives. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #else. Comments Comments in PTX follow C/C++ syntax. #define. All whitespace characters are equivalent. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. January 24.version directive specifying the PTX language version. The C preprocessor cpp may be used to process PTX source files.

reg .entry .pragma .section . r2.tex .global . followed by source operands. Instruction keywords are listed in Table 2.align . The guard predicate follows the optional label and precedes the opcode. 0.global start: . Statements begin with an optional label and end with a semicolon.1.f32 r2. r2. r1.loc . Table 1. r2.PTX ISA Version 2. Instructions have an optional guard predicate which controls conditional execution. 18 January 24. so no conflict is possible with user-defined identifiers.sreg .3.b32 add.5.shared .target . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.minnctapersm . array[r1].func . shl. All instruction keywords are reserved tokens in PTX. .2. Operands may be register variables. or label names.version . where p is a predicate register.maxnreg . 2. address expressions.0 4. The destination operand is first.reg . Directive Statements Directive keywords begin with a dot. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.global.extern .x. 2010 .maxntid .local . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.b32 r1. and is written as @p.3. and terminated with a semicolon. %tid. Statements A PTX statement is either a directive or an instruction.file PTX Directives .param .3.visible 4. . mov.b32 r1.const .maxnctapersm .f32 array[N]. Examples: . ld. written as @!p. constant expressions.b32 r1. The guard predicate may be optionally negated.

2010 19 . Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4.

or dollar characters. listed in Table 3. digits. dollar. Many high-level languages such as C and C++ follow similar rules for identifier names. between user-defined variable names and compiler-generated names.g.4. 2010 . PTX allows the percentage sign as the first character of an identifier. or they start with an underscore. …. e. digits. except that the percentage sign is not allowed. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. Table 3. %pm3 WARP_SZ 20 January 24.0 4. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. or percentage character followed by one or more letters.PTX ISA Version 2. underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. The percentage sign can be used to avoid name conflicts. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.

. i. there is no suffix letter to specify size.5.5. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.e. 4. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.5. When used in an instruction or data initialization. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Constants PTX supports integer and floating-point constants and constant expressions.Chapter 4. Integer literals may be written in decimal.. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.s64 or . and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. 4.1.u64. or binary notation. the constant begins with 0f or 0F followed by 8 hex digits. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. floating-point. i. in which case the literal is unsigned (. 2010 21 . integer constants are allowed and are interpreted as in C. and bit-size types. Unlike C and C++. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. where the behavior of the operation depends on the operand types. To specify IEEE 754 single-precision floating point values. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.u64). the sm_1x and sm_20 targets have a WARP_SZ value of 32.s64 or the unsigned suffix is specified. octal. For predicate-type data and instructions. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. the constant begins with 0d or 0D followed by 16 hex digits.2. These constants may be used in data initialization and as operands to instructions. zero values are FALSE and non-zero values are TRUE. Syntax 4. each integer constant is converted to the appropriate size based on the data or instruction type at its use. literals are always represented in 64-bit double-precision format. Type checking rules remain the same for integer. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. every integer constant has type .s64) unless the value cannot be fully represented in . To specify IEEE 754 doubleprecision floating point values. The syntax follows that of C.e. 0[fF]{hexdigit}{8} // single-precision floating point January 24. hexadecimal. Floating-point literals may be written with an optional decimal point and an optional signed exponent.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

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2nd is .s64 .s64 .u64 1st unchanged.u64 .u64) (.f64 : .u64 .u64 same as 1st operand .f64 integer .f64 same as source .s64) + .f64 use usual conversions .f64 use usual conversions .s64 .u64 .s64 .f64 integer .s64 . or .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64.s64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. 2010 25 .Chapter 4.s64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 converted type constant literal + ! ~ Cast Binary (.f64 converted type .u64 .u64 . Syntax 4. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .6.s64 .f64 integer integer integer integer integer int ?.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64. .f64 use usual conversions .u64 . Table 5.5.

2010 .PTX ISA Version 2.0 26 January 24.

reg . the kinds of resources will be common across platforms. Table 6.tex January 24. defined per-thread.param . Name State Spaces Description Registers. shared by all threads. Addressable memory shared between threads in 1 CTA.global . Read-only. Global texture memory (deprecated). pre-defined. . addressability. Special registers. Shared.shared . and level of sharing between threads. Local memory. State Spaces A state space is a storage area with particular characteristics. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. The list of state spaces is shown in Table 4.Chapter 5. 5. platform-specific. access speed. and properties of state spaces are shown in Table 5. The characteristics of a state space include its size.sreg . 2010 27 . defined per-grid. Kernel parameters. or Function or local parameters. read-only memory. access rights. fast.local .const . private to each thread.1. State Spaces. and Variables While the specific resources available in a given target GPU will vary. Types. Global memory. and these resources are abstracted in PTX through state spaces and data types. All variables reside in some state space.

When the limit is exceeded.tex Restricted Yes No3 5. clock counters. it is not possible to refer to the address of a register.param (used in functions) .e. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 16-. causing changes in performance. Special Register State Space The special register (. Registers may be typed (signed integer. Device function input parameters may have their address taken via mov. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. For each architecture. 1 Accessible only via the ld. 5.reg . and performance monitoring registers. Address may be taken via mov instruction.0 Table 7.global . and thread parameters. Register State Space Registers (.param and st. predicate) or untyped.param instructions.sreg . scalar registers have a width of 8-.shared . 3 Accessible only via the tex instruction. register variables will be spilled to memory. or 128-bits.reg state space) are fast storage locations.1. The number of registers is limited. The most common use of 8-bit registers is with ld. such as grid. i. Registers may have alignment boundaries required by multi-word loads and stores.1. the parameter is then located on the stack frame and its address is in the .sreg) state space holds predefined. 32-. floating point. or as elements of vector tuples.. and cvt instructions. and vector registers have a width of 16-. 2 Accessible via ld. CTA. 28 January 24. All special registers are predefined. or 64-bits. Register size is restricted.PTX ISA Version 2. Registers differ from the other state spaces in that they are not fully addressable. st. and will vary from platform to platform.local state space. aside from predicate registers which are 1-bit. 64-.const .local . 32-. platform-specific registers. unsigned integer.1. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).param (as input to kernel) . 2010 .2.param instruction.

All memory writes prior to the bar. 5. Types. State Spaces. [const_buffer+4]. This reiterates the kind of parallelism available in machines that run PTX.local and st.3. It is the mechanism by which different CTAs and different grids can communicate.const[2] .b32 %r1. If no bank number is given.4.const) state space is a read-only memory. there are eleven 64KB banks. // load second word 5.extern . Use ld. Global memory is not sequentially consistent. where bank ranges from 0 to 10.global. 2010 29 .1. results in const_buffer pointing to the start of constant bank two.5.global. For example. This pointer can then be used to access the entire 64KB constant bank.const[2]. and atom.global to access global variables. bank zero is used.sync instruction are guaranteed to be visible to any reads after the barrier instruction. as it must be allocated on a perthread basis. Sequential consistency is provided by the bar. Global State Space The global (. To access data in contant banks 1 through 10. st. For example.1. initialized by the host. Threads wait at the barrier until all threads in the CTA have arrived. Module-scoped local memory variables are stored at fixed addresses.b32 const_buffer[]. Use ld. The remaining banks may be used to implement “incomplete” constant arrays (in C. The constant memory is organized into fixed size banks.Chapter 5. where the size is not known at compile time. for example). whereas local memory variables declared January 24. If another thread sees the variable b change. Local State Space The local state space (. the stack is in local memory.local) is private memory for each thread to keep its own data. and Variables 5. each pointing to the start address of the specified constant bank. the store operation updating a may still be in flight.b32 const_buffer[].const[2] . ld. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. as in lock-free and wait-free style programming.local to access local variables. the bank number must be provided in the state space of the load instruction. The size is limited. the declaration .const[bank] modifier.sync instruction. By convention.1. all addresses are in global memory are shared. In implementations that support a stack. bank zero is used for all statically-sized constant variables. an incomplete array in bank 2 is accessed as follows: . For the current devices.extern . Threads must be able to do their work without waiting for other threads to do theirs. Banks are specified using the . Constant State Space The constant (. b = b – 1. It is typically standard memory with cache. For any thread in a context. Consider the case where one thread executes the following two assignments: a = a + 1. Multiple incomplete array variables declared in the same bank become aliases.global) state space is memory that is accessible by all threads in a context.

The use of parameter state space for device function parameters is new to PTX ISA version 2. PTX code should make no assumptions about the relative locations or ordering of . all local memory variables are stored at fixed addresses and recursive function calls are not supported. … 30 January 24.u32 %ptr.1. ld. These parameters are addressable.0 and requires target architecture sm_20.param instructions.u32 %n. ld.param state space and is accessed using ld. Therefore.f64 %d. 5.u32 %n. len. in some implementations kernel parameters reside in global memory.reg . (2a) to declare formal input and return parameters for device functions called from within kernel execution. . The resulting address is in the . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).b8 buffer[64] ) { .6.reg .reg .align 8 .param .entry foo ( . No access protection is provided between parameter and global space in this case.PTX ISA Version 2. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.param space variables.param . … Example: . [buffer].u32 %n. per-kernel versus per-thread).0 within a function or kernel body are allocated on the stack.param instructions. Example: .param.param. device function parameters were previously restricted to the register state space.param. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.b32 N. Values passed from the host to the kernel are accessed through these parameter variables using ld. Note: The location of parameter space is implementation specific. [N].param . 2010 .6.1. 5. In implementations that do not support a stack. The address of a kernel parameter may be moved into a register using the mov instruction. Note that PTX ISA versions 1. The kernel parameter variables are shared across all CTAs within a grid. read-only variables declared in the .f64 %d. %n.param space. mov. For example. [%ptr].entry bar ( .x supports only kernel function parameters in .1. typically for passing large structures by value to a function. ld. .param) state space is used (1) to pass input arguments from the host to the kernel.u32 %ptr. Parameter State Space The parameter (. Similarly.param state space.b32 len ) { . and (2b) to declare locally-scoped byte array variables that serve as function call arguments.

1. . Types. Aside from passing structures by value. In this case. Device Function Parameters PTX ISA version 2.param byte array variable that represents a flattened C structure or union. x.f64 %d. (4.func foo ( . } mystruct.param space variable. This will be passed by value to a callee.param.b8 buffer[12] ) { . int y.b8 mystruct.param formal parameter having the same size and alignment as the passed argument. and Variables 5. It is not possible to use mov to get the address of a return parameter or a locally-scoped .local instructions.local and st.align 8 .s32 [mystruct+8].6.s32 %y.local state space and is accessed via ld. The most common use is for passing objects by value that do not fit within a PTX register. [buffer]. which declares a . the address of a function input parameter may be moved into a register using the mov instruction. State Spaces.reg . In PTX.reg . dbl. ld. call foo.param. ld. … See the section on function call syntax for more details. }.param. it is illegal to write to an input parameter or read from a return parameter.param .param. st.Chapter 5.0 extends the use of parameter space to device function parameters.param. such as C structures larger than 8 bytes.reg . 2010 31 . a byte array in parameter space is used. . mystruct).2.f64 dbl.param and function return parameters may be written using st. Typically. int y. .b32 N. the caller will declare a locally-scoped .s32 %y. Example: // pass object of type struct { double d. passed to foo … .reg . and so the address will be in the .param .f64 %d. January 24.f64 [mystruct+0]. Note that the parameter will be copied to the stack if necessary. [buffer+8]. … st. .align 8 . is flattened. … } // code snippet from the caller // struct { double d.s32 x. . .reg .param space is also required whenever a formal parameter has its address taken within the called function. Function input parameters may be read via ld.

where texture identifiers are allocated sequentially beginning with zero.tex .tex . Example: .tex .8. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).texref.PTX ISA Version 2. and variables declared in the .tex .global state space. Shared State Space The shared (. Physical texture resources are allocated on a per-module granularity. See Section 5.u64. tex_c.global .7. tex_f.shared to access shared variables.texref tex_a. For example.tex directive will bind the named texture memory variable to a hardware texture identifier.u32 or . tex_d. Shared memory typically has some optimizations to support the sharing.texref variables in the . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.0 5. a legacy PTX definitions such as .tex) state space is global memory accessed via the texture instruction.3 for the description of the . is equivalent to .shared) state space is a per-CTA region of memory for threads in a CTA to share data.7. Multiple names may be bound to the same physical texture identifier. One example is broadcast. 32 January 24. Use ld. The .u32 tex_a. and programs should instead reference texture memory through variables of type . Texture State Space (deprecated) The texture (. The .1.tex variables are required to be defined in the global scope. tex_d.tex directive is retained for backward compatibility. where all threads read from the same address.6 for its use in texture instructions. 5.1.tex .u32 tex_a. A texture’s base address is assumed to be aligned to a 16-byte boundary. An address in shared memory can be read and written by any thread in a CTA. 2010 .u32 .u32 . Texture memory is read-only. It is shared by all threads in a context.texref type and Section 8. Another is sequential access from sequential threads. An error is generated if the maximum number of physical resources is exceeded. and .tex state space are equivalent to module-scoped .u32 .shared and st. The texture name must be of type .

s16. For example. 5. but typed variables enhance program readability and allow for better operand type checking. and . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. and converted using regular-width registers. 2010 33 . stored. . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.u8.2.f32 and . Types 5.f16.u64 .u8.b16. Register variables are always of a fundamental type. The bitsize type is compatible with any fundamental type having the same size. the fundamental types reflect the native data types supported by the target architectures. or converted to other types and sizes. For convenience.b8 instruction types are restricted to ld. Operand types and sizes are checked against instruction types for compatibility.f16 floating-point type is allowed only in conversions to and from . so their names are intentionally short. Signed and unsigned integer types are compatible if they have the same size. and cvt instructions. ld. so that narrow values may be loaded.b64 . . and instructions operate on these types.b8. and Variables 5.1. Types. State Spaces. .2. needed to fully specify instruction behavior. stored.pred Most instructions have one or more type specifiers. Restricted Use of Sub-Word Sizes The . In principle. . The .u32. .s32.Chapter 5. all variables (aside from predicates) could be declared using only bit-size types.u16. Two fundamental types are compatible if they have the same basic type and are the same size.f64 types.f64 types. .f32 and .b32. st. . .s8. The same typesize specifiers are used for both variable definitions and for typing instructions. . .f32. . .f64 . All floating-point instructions operate only on .2. January 24. The following table lists the fundamental type specifiers for each basic type: Table 8.s64 . st. Fundamental Types In PTX. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .2. A fundamental type specifies both a basic type and a size.s8.

field ordering. and query instructions. base address. Retrieving the value of a named member via query instructions (txq. In the unified mode. samplers. and Surface Types PTX includes built-in “opaque” types for defining texture. The three built-in types are . For working with textures and samplers. accessing the pointer with ld and st instructions. In the independent mode. suq). opaque_var. since these properties are defined by . texture and sampler information each have their own handle. sust.e.samplerref variables. the resulting pointer may be stored to and loaded from memory. 34 January 24. but all information about layout. sampler. Referencing textures. store. Sampler. In independent mode the fields of the . passed as a parameter to functions. allowing them to be defined separately and combined at the site of usage in the program. and surface descriptor variables. The following tables list the named members of each type for unified and independent texture modes.texref type that describe sampler properties are ignored. and . Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. These types have named fields similar to structures..PTX ISA Version 2. texture and sampler information is accessed through a single . sured).texref. 2010 . and de-referenced by texture and surface load. i. or surfaces via texture and surface load/store instructions (tex. Creating pointers to opaque variables using mov.u64} reg.0 5.samplerref.surfref. and overall size is hidden to a PTX program. or performing pointer arithmetic will result in undefined results.3. Texture. but the pointer cannot otherwise be treated as an address.{u32. suld. hence the term “opaque”. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. .texref handle. PTX has two modes of operation.

texref values in elements in elements in elements 0. 1 nearest. clamp_to_border N/A N/A N/A N/A N/A . clamp_to_edge.samplerref values N/A N/A N/A N/A nearest. 1 ignored ignored ignored ignored . clamp_to_border 0. Types. clamp_to_edge. linear wrap. linear wrap.Chapter 5.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode . 2010 35 .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. State Spaces. Member width height depth Opaque Type Fields in Unified Texture Mode . mirror. mirror. and Variables Table 9.texref values . clamp_ogl.

global state space. 2010 .global .param state space.global .samplerref my_sampler_name. . these variables are declared in the . .texref my_texture_name.global . filter_mode = nearest }. Example: . When declared at module scope.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.PTX ISA Version 2.texref tex1.samplerref tsamp1 = { addr_mode_0 = clamp_to_border. these variables must be in the . . 36 January 24. At module scope. As kernel parameters.global . the types may be initialized using a list of static expressions assigning values to the named members.global .surfref my_surface_name. Example: .

global .v3 }.v1.f64 is not allowed.global . A variable declaration names the space in which the variable resides. textures. .v2 . an optional initializer. its name. Vectors cannot exceed 128-bits in length.v4 vector. . . // a length-2 vector of unsigned ints .0. vector variables are aligned to a multiple of their overall size (vector length times base-type size).struct float4 coord. Vectors Limited-length vector types are supported. 0.const . for example. PTX supports types for simple aggregate objects such as vectors and arrays. Vectors must be based on a fundamental type.4.u32 loc.0}.reg . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . 2010 37 . Variables In PTX. // a length-4 vector of floats . Variable Declarations All storage for data is specified with variable declarations.reg . a variable declaration describes both the variable’s type and its state space.v2. // typedef . etc.s32 i.f32 v0.4. where the fourth element provides padding.f32 bias[] = {-1. r.Chapter 5.u16 uv.f32 V. Predicate variables may only be declared in the register state space. 5.reg .4.v4. . and an optional fixed address for the variable. an optional array size. .u8 bg[4] = {0. Every variable must reside in one of the state spaces enumerated in the previous section. State Spaces. its type and size. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.global . q.global .b8 v.global . 5. and Variables 5. . .v4 . 1. Three-element vectors may be handled by using a . Examples: .1. 0}. Types. // a length-4 vector of bytes By default.f32 accel. Examples: . and they may reside in the register space.v2 or .v4.pred p.shared .v4 . In addition to fundamental types.v4 . 0.2. This is a common case for three-dimensional grids. January 24.struct float4 { .

global . this can be used to initialize a jump table to be used with indirect branches or calls.05}.s32 n = 10. {0. Initializers are allowed for all types except . .1. Here are some examples: . {0. // address of rgba into ptr Currently.s32 offset[][] = { {-1.0}.. 5..f32 blur_kernel[][] = {{.0..05}}. {1. {0.u32 or . -1}.1. Variables that hold addresses of variables or instructions should be of type . {0. this can be used to statically initialize a pointer to a variable.pred. 0}. . Initializers Declared variables may specify an initial value using a syntax similar to C/C++.4.u8 rgba[3] = {{1. The size of the dimension is either a constant expression.f16 and .. or is left empty.05. label names appearing in initializers represent the address of the next instruction following the label.0}.05.u64.PTX ISA Version 2. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.{. For the kernel declaration above.shared . 1} }. Examples: . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). variable initialization is supported only for constant and global state spaces.0.4.4.{.1.u16 kernel[19][19].3. . Variable names appearing in initializers represent the address of the variable.global .4.global . A scalar takes a single value.global .0}}. 0}. . where the variable name is followed by an equals sign and the initial value or values for the variable.0. 2010 ..local . Similarly..u8 mailbox[128].1}.0 5. To declare an array.1.v4 . being determined by an array initializer. Array Declarations Array declarations are provided to allow the programmer to reserve space. 38 January 24. . The size of the array specifies how many elements should be reserved.0.b32 ptr = rgba. 19*19 (361) halfwords are reserved (722 bytes).global .1.

Parameterized Variable Names Since PTX supports virtual registers.4.5.4.0..Chapter 5. Alignment is specified using an optional . nor are initializers permitted.0. State Spaces. %r1. These 100 register variables can be declared as follows: .0. %r1.b32 variables. The variable will be aligned to an address which is an integer multiple of byte-count. alignment specifies the address alignment for the starting address of the entire array. Elements are bytes. Rather than require explicit declaration of every name. it is quite common for a compiler frontend to generate a large number of register names. For arrays. not for individual elements. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. 5. .b32 %r<100>.0}. Types. named %r0.const . …. // declare %r0. ..b8 bar[8] = {0. %r99..2.reg . Examples: // allocate array at 4-byte aligned address. The default alignment for scalar and array variables is to a multiple of the base-type size. and may be preceded by an alignment specifier. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.align 4 . suppose a program uses a large number. January 24.0. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Array variables cannot be declared this way. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. and Variables 5. The default alignment for vector variables is to a multiple of the overall vector size. of .align byte-count specifier immediately following the state-space specifier. say one hundred. For example. 2010 39 .0.6.

0 40 January 24.PTX ISA Version 2. 2010 .

r. Integer types of a common size are compatible with each other. Source Operands The source operands are denoted in the instruction descriptions by the names a. Operand Type Information All operands in instructions have a known type from their declarations. There is no automatic conversion between types. q. mov. 6.reg register state space. The result operand is a scalar or vector variable in the register state space. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. and cvt instructions copy data from one location to another. Each operand type must be compatible with the type determined by the instruction template and instruction type. Instructions ld and st move data from/to addressable state spaces to/from registers.Chapter 6. Predicate operands are denoted by the names p.1. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Most instructions have an optional predicate guard that controls conditional execution. so operands for ALU instructions must all be in variables declared in the . the sizes of the operands must be consistent. st. b. and a few instructions have additional predicate source operands. The mov instruction copies data between registers. 2010 41 . s. January 24. .3.2. The ld. as its job is to convert from nearly any data type to any other data type (and size). For most operations. PTX describes a load-store machine. 6. The bit-size type is compatible with every type having the same size. and c. The cvt (convert) instruction takes a variety of operand types and sizes. Instruction Operands 6.

reg . Examples include pointer arithmetic and pointer comparisons. Address expressions include variable names. r0. The interesting capabilities begin with addresses.u16 ld. The syntax is similar to that used in many assembly languages.v4.f32 V. and immediate address expressions which evaluate at compile-time to a constant address. and Vectors Using scalar variables as operands is straightforward. there is no support for C-style pointer arithmetic. Arrays.u16 r0. 2010 . p.reg . 6. .b32 p. .shared . . Here are a few examples: .f32 W.reg .s32 tbl[256]. address registers. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. Using Addresses.s32 mov. ld. [tbl+12].v4 .[x].1.const . and vectors.0 6. [V].f32 ld.v4 . .shared. tbl. address register plus byte offset. The address is an offset in the state space in which the variable is declared. q.u16 x.u32 42 January 24.4.s32 q. W. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. The mov instruction can be used to move the address of a variable into a pointer. All addresses and address computations are byte-based. .global . arrays.4.reg . Load and store operations move data between registers and locations in addressable state spaces. .PTX ISA Version 2.const.gloal.

f32 {a. [addr+offset2].a. The size of the array is a constant in the program. a[N-1]. mov.u32 {a.v4. which may improve memory performance. d. If more complicated indexing is desired. Here are examples: ld. . 2010 43 .z V. .f32 V. a[1]. b.Chapter 6.4. and in move instructions to get the address of the label or function into a register. say {Ra.f32 a.global. Rd}. or a braceenclosed list of similarly typed scalars. Rb. for use in an indirect branch or call.reg . or a simple “register with constant offset” expression.3. Rc.global.d}. Instruction Operands 6. . which include mov.c.x. mov. January 24.v4 .u32 s.g V.y.c.g.v2.global. a register variable. V.v4. c.4. [addr+offset]. or by indexing into the array using square-bracket notation.reg .4. Array elements can be accessed using an explicitly calculated byte address.a 6. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. V2.y V. Vector elements can be extracted from the vector with the suffixes . Vectors may also be passed as arguments to called functions. . as well as the typical color fields .b V. Vector loads and stores can be used to implement wide loads and stores. // move address of a[1] into s 6. .b. Arrays as Operands Arrays of all types can be declared. and tex.d}. The registers in the load/store operations can be a vector.u32 s.r V. Examples are ld. ld. Vectors as Operands Vector operands are supported by a limited subset of instructions. a[0]. Elements in a brace-enclosed vector. ld. where the offset is a constant expression that is either added or subtracted from a register variable.4.w = = = = V. st. . and the identifier becomes an address constant in the space where the array is declared.x V. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.w.global.z and . The expression within square brackets is either a constant integer.u32 s.b. it must be written as an address calculation prior to use.f32 ld.b and . A brace-enclosed list is used for pattern matching to pull apart vectors.2.r.

1. except for operations where changing the size and/or type is part of the definition of the instruction.5. and ~131. the u16 is zero-extended to s32. 2010 . 6. logic. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. 44 January 24.000 for f16). Operands of different sizes or types must be converted prior to the operation.PTX ISA Version 2. For example.0 6.s32.u16 instruction is given a u16 source operand and s32 as a destination operand. Type Conversion All operands to all arithmetic. if a cvt. and data movement instruction must be of the same type and size. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.5.

For example. chop = keep only low bits that fit. u2f = unsigned-to-float. cvt.s16. s2f = signed-to-float. The type of extension (sign or zero) is based on the destination format. then sign-extend to 32-bits.Chapter 6. zext = zero-extend. Notes 1 If the destination register is wider than the destination format. the result is extended to the destination register width after chopping. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. January 24. 2010 45 . f2f = float-to-float.u32 targeting a 32-bit register will first chop to 16-bits. f2u = float-to-unsigned. f2s = float-to-signed. Instruction Operands Table 11.

PTX ISA Version 2.2.rn . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. Rounding Modifiers Conversion instructions may specify a rounding modifier.rzi .rz . there are four integer rounding modifiers and four floating-point rounding modifiers. In PTX.rni . Modifier .0 6.rmi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rm . 2010 . choosing even integer if source is equidistant between two integers.rpi Integer Rounding Modifiers Description round to nearest integer. The following tables summarize the rounding modifiers. Table 12. Modifier .5.

while global memory is slowest. Table 11 gives estimates of the costs of using different kinds of memory.6. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. first access is high Notes January 24.Chapter 6. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Operand Costs Operands from different state spaces affect the speed of an operation. Table 14. The register in a store operation is available much more quickly. Instruction Operands 6. Much of the delay to memory can be hidden in a number of ways. Another way to hide latency is to issue the load instructions as early as possible. Registers are fastest. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. 2010 47 .

0 48 January 24.PTX ISA Version 2. 2010 .

A function declaration specifies an optional list of return parameters. Function declarations and definitions In PTX. the function name. together these specify the function’s interface. so recursion is not yet supported. support for variadic functions (“varargs”). Execution of the ret instruction within foo transfers control to the instruction following the call. execution of the call instruction transfers control to foo. Scalar and vector base-type input and return parameters may be represented simply as register variables. and an optional list of input parameters. functions are declared and defined using the . parameter passing. function calls. The simplest function has no parameters or return values. A function must be declared or defined prior to being called. At the call. January 24. } … call foo.1.Chapter 7. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and memory allocated on the stack (“alloca”). A function definition specifies both the interface and the body of the function. and is represented in PTX as follows: .func foo { … ret. stack layout. implicitly saving the return address. … Here.func directive. 7. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. stack-based ABI. and return values may be placed directly into register variables. we describe the features of PTX needed to achieve this hiding of the ABI. NOTE: The current version of PTX does not implement the underlying. and Application Binary Interface (ABI). These include syntax for function definitions. or prototype. In this section. arguments may be register variables or constants. Abstracting the ABI Rather than expose details of a particular calling convention. 2010 49 .

[y+9].param.param variable y is used in function definition bar to represent a formal parameter.b8 c4.param. Since memory accesses are required to be aligned to a multiple of the access size.c2. this structure will be flattened into a byte array.f64 f1. inc_ptr. ld.b8 [py+10].f64 f1. For example.b8 [py+ 8]. st. First.b8 c3.u32 %res) inc_ptr ( .s32 x.param space variables are used in two ways.b8 [py+ 9].s32 out) bar (. . }.reg .0 Example: .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. st. st. … … // computation using x. py).param. %inc.func (.align 8 py[12].param.reg .param space call (%out). [y+0]. char c[4].param.param. In PTX. %rc1. consider the following C structure.4). } { . . ld.param space memory. . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .reg . %rc2.PTX ISA Version 2.param .param. passed by value to a function: struct { double dbl.b8 . %ptr.f64 field are aligned. (%r1. … In this example.u32 %ptr.u32 %res. [y+11].reg .b8 [py+11]. byte array in .b8 . note that .u32 %inc ) { add. The . 50 January 24. a .param .c4. (%x.align 8 y[12]) { . %rc2.reg .param state space is used to pass the structure by value: . Second. a .param.f1. … st. st.param. %rd.reg space. bumpptr.b64 [py+ 0]. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . … ld.b32 c1.c3. [y+10].param.b8 c1. } … call (%r1). 2010 .reg . ret.c1. // scalar args in . c4. [y+8].b8 c2. c3.func (. c2. ld. %rc1. ld.reg .

reg space formal parameters.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The .g.param space formal parameters that are base-type scalar or vector variables. 8. In the case of . This enables backend optimization and ensures that the .param arguments. • • • Input and return parameters may be .reg state space can be used to receive and return base-type scalar and vector values. the argument must also be a . The following restrictions apply to parameter passing.reg variables. In the case of . Note that the choice of .param and ld. For a caller.param or . or 16 bytes.. • The . or a constant that can be represented in the type of the formal parameter. a .param argument must be declared within the local scope of the caller.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param state space is used to receive parameter values and/or pass return values back to the caller. For .param variables. • • • For a callee. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.param space byte array with matching type.param variables or . 2010 51 .param state space use in device functions.param space formal parameters that are byte arrays.param or . 4. the corresponding argument may be either a .reg space variable with matching type and size. For a callee. • The . Typically.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param byte array is used to collect together fields of a structure being passed by value. For a caller. size. the corresponding argument may be either a . or a constant that can be represented in the type of the formal parameter. The .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.reg or . In the case of . Abstracting the ABI The following is a conceptual way to think about the . January 24.reg space variable of matching type and size. A . Parameters in .reg state space in this way provides legacy support. size.param instructions used for argument passing must be contained in the basic block with the call instruction. or constants.reg variables. and alignment of parameters. 2.param memory must be aligned to a multiple of 1. and alignment. . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. • • Arguments may be . Supporting the . all st.Chapter 7.

param state space.x.0.x supports multiple return values for this purpose.1.0 continues to support multiple return registers for sm_1x targets. formal parameters may be in either .PTX ISA Version 2.reg or . 2010 . For sm_2x targets.param space parameters support arrays.param byte array should be used to return objects that do not fit into a register. formal parameters were restricted to .reg state space. PTX 1. Objects such as C structures were flattened and passed or returned using multiple registers. and there was no support for array parameters. and .0 7. 52 January 24.1. In PTX ISA version 2.0 restricts functions to a single return value. Changes from PTX 1. PTX 2. PTX 2.x In PTX ISA version 1. and a .

. %r1. 4..u32 ptr.reg .u32 ptr. call (val).reg . %r2. ctr. In both cases. 4.b32 val) %va_arg (.func (. . call %va_end. %s2).reg .u32 ap. %s1. N. For %va_arg. along with the size and alignment of the next data value to be accessed.u32 sz.u32 ptr) %va_start .h and varargs. or 8 bytes. Abstracting the ABI 7.b64 val) %va_arg64 (. This handle is then passed to the %va_arg and %va_arg64 built-in functions. … %va_start returns Loop: @p Done: January 24.func ( . the size may be 1. } … call (%max). To support functions with a variable number of arguments.reg .reg . following zero or more fixed parameters: . maxN.ge p.h headers in C.reg . for %va_arg64. . call (ap). 2.u32.b32 result. . (ap. the size may be 1. or 16 bytes. %r3).reg .u32 align) . and end access to a list of variable arguments.u32 N. iteratively access. … call (%max).func baz ( . or 4 bytes.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. 2010 53 . 4). maxN.reg . ret. 2. (ap).func okay ( … ) Built-in functions are provided to initialize.b32 ctr.reg .u32 sz. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . mov. %va_start.2. In PTX. .func (. 2. PTX provides a high-level mechanism similar to the one provided by the stdarg.s32 val. %va_end is called to free the variable argument list handle. Once all arguments have been processed. 0.. bra Done.func %va_end (.reg .Chapter 7. the alignment may be 1. .func (.u32 b. 4. ) { .reg . (3. .s32 result.reg . 0x8000000.reg . %va_arg. The function prototypes are defined as follows: . Variadic functions NOTE: The current version of PTX does not support variadic functions.u32 align) . // default to MININT mov.u32 a. . ctr. bra Loop.reg .reg . (2.pred p. … ) .reg . 8. variadic functions are declared with an ellipsis at the end of the input parameter list.s32 result ) maxN ( .reg . result. setp. val. max.

func ( .3. Alloca NOTE: The current version of PTX does not support alloca.reg . 54 January 24. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.PTX ISA Version 2.local instructions. a function simply calls the built-in function %alloca. The array is then accessed with ld.local and st. To allocate memory. If a particular alignment is required.u32 ptr ) %alloca ( .0 7. defined as follows: . 2010 .reg .

B. setp. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. B.2. a. We use a ‘|’ symbol to separate multiple destination registers. opcode A. opcode D.s32. B.1. A. opcode D. C. In addition to the name and the format of the instruction. // p = (a < b). A. the semantics are described. 2010 55 . January 24. For some instructions the destination operand is optional. For instructions that create a result value. while A. opcode D. Instruction Set 8. followed by some examples that attempt to show several possible instantiations of the instruction. 8.Chapter 8. PTX Instructions PTX instructions generally have from zero to four operands. and C are the source operands. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. the D operand is the destination operand. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. The setp instruction writes two destination registers.lt p|q. q = !(a < b). b.

… // compare i to n // if false. add.s32 p.lt. use a predicate to control the execution of the branch or call instructions.3. Predicates are most commonly set as the result of a comparison performed by the setp instruction. the following PTX instruction sequence might be used: @!p L1: setp. where p is a predicate variable. consider the high-level code if (i < n) j = j + 1. predicate registers can be declared as . r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. n.s32 p. i.0 8. This can be written in PTX as @p setp. n.pred as the type specifier. // p = (i < n) // if i < n. i.s32 j. branch over 56 January 24.PTX ISA Version 2. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.reg . add. 2010 . j. To implement the above example as a true conditional branch.pred p. j. bra L1. predicate registers are virtual and have .lt. As an example. add 1 to j To get a conditional branch or conditional function call. optionally negated. Instructions without a guard predicate are executed unconditionally. Predicated Execution In PTX.s32 j. 1. q. So. 1.

le (less-than-or-equal). and hs (higher-or-same).1.3. 2010 57 .1.1. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. lo (lower). ls (lower-or-same).Chapter 8. The following table shows the operators for signed integer. ne (not-equal). Table 15.3. ne. gt (greater-than). Comparisons 8. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. unsigned integer. le. hi (higher).2. ge. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. ordering comparisons are not defined for bit-size types. lt (less-than). Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Unsigned Integer. and bitsize types. and ge (greater-than-or-equal). Instruction Set 8. lt. The bit-size comparisons are eq and ne.1. gt.3. Table 16. ne. the result is false. If either operand is NaN. The unsigned comparisons are eq.

two operators num (numeric) and nan (isNaN) are provided. geu. and no direct way to load or store predicate register values. then the result of these comparisons is true. setp can be used to generate a predicate from an integer. However.3. for example: selp. num returns true if both operands are numeric values (not NaN). ltu. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. gtu.%p. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.1. If both operands are numeric values (not NaN). or. Table 18.0. unordered versions are included: equ.u32 %r1. leu. not.2. If either operand is NaN. // convert predicate to 32-bit value 58 January 24. There is no direct conversion between predicates and integer values.0 To aid comparison operations in the presence of NaN values.PTX ISA Version 2. then these comparisons have the same result as their ordered counterparts. xor. Table 17. and nan returns true if either operand is NaN. 2010 . Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. neu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. and mov.

For example.bX .e.uX . a.u16 d.bX .4.reg .reg . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. For example: . 2010 59 . b. Example: . a. Type Checking Rules Operand Type . they must match exactly. unsigned. For example.f32 d. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Floating-point types agree only if they have the same size. the add instruction requires type and size information to properly perform the addition operation (signed. float.reg . and this information must be specified as a suffix to the opcode. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. most notably the data conversion instruction cvt. • The following table summarizes these type checking rules.uX ok ok ok inv .fX ok inv inv ok Instruction Type . and these are placed in the same order as the operands.u16 d. It requires separate type-size modifiers for the result and source. . and integer operands are silently cast to the instruction type if needed. a. b. Signed and unsigned integer types agree provided they have the same size.sX ok ok ok inv . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. different sizes).fX ok ok ok ok January 24.sX . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.. i.Chapter 8. cvt.f32. Table 19. add.u16 d. Instruction Set 8.u16 a.

unless the operand is of bit-size type. Note that some combinations may still be invalid for a particular instruction. Bit-size source registers may be used with any appropriately-sized instruction type. 1. Source register size must be of equal or greater size than the instruction-type size. stored. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. 60 January 24. st. “-“ = allowed. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.4.bX instruction types. the size must match exactly. parse error. 2010 . ld. so those rows are invalid for cvt. 4. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. For example.0 8. inv = invalid. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 2.PTX ISA Version 2. Operand Size Exceeding Instruction-Type Size For convenience. stored. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. The data is truncated to the instruction-type size and interpreted according to the instruction type. and converted using regular-width registers. Notes 3. When used with a floating-point instruction type. Floating-point source registers can only be used with bit-size or floating-point instruction types. the data will be truncated. the cvt instruction does not support . or converted to other types and sizes. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. so that narrow values may be loaded. no conversion needed. The following table summarizes the relaxed type-checking rules for source operands. When used with a narrower bit-size type. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. for example.1. floating-point instruction types still require that the operand type-size matches exactly. Table 20. When a source operand has a size that exceeds the instruction-type size.

When used with a floatingpoint instruction type. 2. 1. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types.or sign-extended to the size of the destination register. zext = zero-extend. the data will be zero-extended. 2010 61 . Notes 3. Bit-size destination registers may be used with any appropriately-sized instruction type. Table 21. the size must match exactly. and is zero-extended to the destination register width otherwise. otherwise. “-“ = Allowed but no conversion needed. Destination register size must be of equal or greater size than the instruction-type size. The data is signextended to the destination register width for signed integer instruction types. the data is sign-extended. When used with a narrower bit-size instruction type. The data is sign-extended to the destination register width for signed integer instruction types. The following table summarizes the relaxed type-checking rules for destination operands. If the corresponding instruction type is signed integer. parse error. Instruction Set When a destination operand has a size that exceeds the instruction-type size. the destination data is zero. the data is zeroextended. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Floating-point destination registers can only be used with bit-size or floating-point instruction types.Chapter 8. inv = Invalid. 4. January 24.

Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. 16-bit registers in PTX are mapped to 32-bit physical registers. for example. 8. the semantics of 16-bit instructions in PTX is machine-specific. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. this is not desirable. so it is important to have divergent threads re-converge as soon as possible. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. At the PTX language level. a compiler or code author targeting PTX can ignore the issue of divergent threads. When executing on a 32-bit data path. For divergent control flow. for many performance-critical applications. Both situations occur often in programs. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.PTX ISA Version 2.6. the optimizing code generator automatically determines points of re-convergence. Divergence of Threads in Control Constructs Threads in a CTA execute together. A compiler or programmer may chose to enforce portable. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. These extra precision bits can become visible at the application level. and 16-bit computations are “promoted” to 32-bit computations. using the . 2010 . at least in appearance. 62 January 24. If all of the threads act in unison and follow a single control flow path.1. However. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. Therefore. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code.5. conditional function call. and for many applications the difference in execution is preferable to limiting performance. until C is not expressive enough. If threads execute down different control flow paths.0 8. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. or conditional return. until they come to a conditional control construct such as a conditional branch. 8.6. the threads are called uniform. the threads are called divergent. The semantics are described using C. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. by a right-shift instruction.uni suffix.

Instructions All PTX instructions may be predicated.7.Chapter 8. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. The Integer arithmetic instructions are: add sub add.1. the optional guard predicate is omitted from the syntax.cc. 2010 63 . 8.7. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. addc sub.cc. Instruction Set 8. In the following descriptions.

PTX ISA Notes Target ISA Notes Examples 64 January 24.. Introduced in PTX ISA version 1.u16.1. b.sat limits result to MININT.s32 .b.s32 type. .s16.0 Table 22. b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0.u16.sat. Saturation modifier: .c. .sat limits result to MININT.s32.u64. // .PTX ISA Version 2. d = a – b.u32 x. PTX ISA Notes Target ISA Notes Examples Table 23. Applies only to .type sub{. d. Saturation modifier: .u32. a.a. d.s32. Supported on all target architectures. . a. 2010 . sub.type = { .z.s32 .MAXINT (no overflow) for the size of the operation.sat applies only to .s64 }.s32 c. sub.sat}. . Introduced in PTX ISA version 1. a.sat applies only to . .u32. Description Semantics Notes Performs addition and writes the resulting value into a destination register. b. @p add. b.type = { . . d = a + b.s32 type.. add.s32 d.MAXINT (no overflow) for the size of the operation. . Applies only to . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. // . .y. . Supported on all target architectures. add.s16.0.s32 c.sat}. add Syntax Integer Arithmetic Instructions: add Add two values. a.s32 d.u64. .s64 }.type add{.

Supported on all target architectures. x3.type = { . addc{. add.CF.cc. Instruction Set Instructions add.y2. .cc.2. Behavior is the same for unsigned and signed integers.y1.cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. b. . x2. and there is no support for setting. x2.y4.z3.z1.b32 x1.b32 addc.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. clearing. addc.cc. sub. No other instructions access the condition code.z4.cc.b32 addc.type d.s32 }.z1. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.y1.b32 addc. . x4. b. .type d. @p @p @p @p add. Supported on all target architectures. No saturation.y3.b32 x1. These instructions support extended-precision integer addition and subtraction. add.s32 }. Table 24. a.z3.cc. carry-out written to CC.cc.z4.CF No integer rounding modifiers.2.y2. d = a + b + CC.cc. a.y3.type = {.b32 addc.b32 addc.z2. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.cc specified. x3.cc.cc Syntax Integer Arithmetic Instructions: add.cc Add two values with carry-out. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. @p @p @p @p add.z2.CF No integer rounding modifiers. No saturation. x4. if .y4. Behavior is the same for unsigned and signed integers. or testing the condition code. Introduced in PTX ISA version 1. carry-out written to CC. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1.Chapter 8.cc}. d = a + b. 2010 65 .CF) holding carry-in/carry-out or borrowin/borrow-out. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.u32.cc.b32 addc.u32.

cc. x2.z4. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.CF No integer rounding modifiers. Supported on all target architectures.b32 subc.y3. @p @p @p @p sub. 2010 .z3.type d.cc.z2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.y1. sub.s32 }.b32 subc.type = { . No saturation.b32 x1.cc.0 Table 26. .cc specified. with borrow-out. sub. a.u32. x3.u32.cc. @p @p @p @p sub. x2. Behavior is the same for unsigned and signed integers. x4. b.type d. x3.b32 subc.cc Subract one value from another.z1.s32 }.y2. d = a .y4.cc Syntax Integer Arithmetic Instructions: sub. a. if .b32 subc.PTX ISA Version 2.b32 subc.3. Introduced in PTX ISA version 1. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.type = {. . b. x4.y1.cc}.b32 subc. d = a – b.y3.3. Behavior is the same for unsigned and signed integers.CF). borrow-out written to CC.z3.cc. subc{.z4.cc.cc. .cc.y4. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. borrow-out written to CC.cc.z1.b32 x1. No saturation. . withborrow-in and optional borrow-out. Introduced in PTX ISA version 1.y2.CF No integer rounding modifiers. Supported on all target architectures.z2. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.(b + CC.

type d. t = a * b. // for . and either the upper or lower half of the result is written to the destination register.wide is specified.fys. Supported on all target architectures.lo is specified.0>.s64 }. .wide.u16. mul.s16 fa.lo. . d = t<2n-1.y.0.. creates 64 bit result January 24. .fxs.hi variant // for . d = t.. mul.wide suffix is supported only for 16.hi or .wide}.n>. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . If . Description Semantics Compute the product of two values.. 2010 67 .u64.s16.wide.s32 z..hi. // 16*16 bits yields 32 bits // 16*16 bits.lo variant Notes The type of the operation represents the types of the a and b operands. b. d = t<n-1.lo. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. a. then d is the same size as a and b. then d is twice as wide as a and b to receive the full result of the multiplication.s32. If .type = { .s16 fa.fys. n = bitwidth of type.Chapter 8. The . mul.x.fxs. Instruction Set Table 28.and 32-bit integer types. save only the low 16 bits // 32*32 bits. .u32. mul{.wide // for . .

wide}.. If .u64.0> + c.s32 d.sat limits result to MININT. t<2n-1.0. a. .hi mode. Description Semantics Multiplies two values and adds a third.c. t<n-1.type = { ..u16.hi or . c.lo is specified.b.s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . b.lo.s32 r.lo variant Notes The type of the operation represents the types of the a and b operands..and 32-bit integer types. @p mad. c.lo.wide is specified. then d and c are twice as wide as a and b to receive the result of the multiplication.type mad. bitwidth of type. b. mad{. 2010 .0 Table 29.hi. and either the upper or lower half of the result is written to the destination register.r. Applies only to .MAXINT (no overflow) for the size of the operation. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. If .s16. d.wide suffix is supported only for 16.lo.sat. Saturation modifier: . The . .s32 type in . a.a.PTX ISA Version 2.hi.s64 }. . // for .wide // for . 68 January 24. and then writes the resulting value into a destination register.n> + c. then d and c are the same size as a and b. .. Supported on all target architectures.hi variant // for .. t + c. mad.u32.q. t n d d d = = = = = a * b.s32 d. .p.

hi may be less efficient on machines without hardware support for 24-bit multiply.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24{. // for .lo.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. Supported on all target architectures..type d. mul24.hi variant // for . .b. mul24.Chapter 8.a. t = a * b. Instruction Set Table 30. // low 32-bits of 24x24-bit signed multiply.e. b. 2010 69 ..hi.u32.s32 }. mul24. a.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. i. 48bits.s32 d. mul24. January 24.16>. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. All operands are of the same type and size. .lo}.0. d = t<31.0>. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. and return either the high or low 32-bits of the 48-bit result. d = t<47.type = { ..

Applies only to . d = t<47. mad24{. b.0 Table 31.sat limits result of 32-bit signed addition to MININT..c. // low 32-bits of 24x24-bit signed multiply.s32 }. mad24. c. t = a * b. mad24. mad24.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.e.s32 d. a. Return either the high or low 32-bits of the 48-bit result.sat. // for .0> + c.u32.hi may be less efficient on machines without hardware support for 24-bit multiply. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. . mad24. Supported on all target architectures.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. 2010 .s32 d.hi mode.. Saturation modifier: .lo}.16> + c. All operands are of the same type and size. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and add a third. . a.hi.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. 32-bit value to either the high or low 32-bits of the 48-bit result.s32 type in . i.MAXINT (no overflow). 48bits..a. c.b.type = { .hi.lo.. Description Compute the product of two 24-bit integer values held in 32-bit source registers. b.0. d = t<31.type mad24. d.hi variant // for .PTX ISA Version 2. 70 January 24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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u32 PTX ISA Notes Target ISA Notes Examples Table 40. a. . X.b64 }. mask = 0x80000000. X.PTX ISA Version 2.0 Table 39. clz requires sm_20 or later.b64 type. the number of leading zeros is between 0 and 64.0. clz.type = { . } else { max = 64.b64 d.b64 d. popc requires sm_20 or later.u32 Semantics 74 January 24. d = 0. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.type d. cnt.b32 clz. a = a << 1. popc. . . } Introduced in PTX ISA version 2. inclusively. d = 0. 2010 .0. cnt. a. popc Syntax Integer Arithmetic Instructions: popc Population count. // cnt is .b32.b32. For .b64 }.b32 popc. . mask = 0x8000000000000000. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.type = { . the number of leading zeros is between 0 and 32. } while (d < max && (a&mask == 0) ) { d++.type d. popc. inclusively.b32) { max = 32. a = a >> 1. a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz. if (. // cnt is . For . a.b32 type. while (a != 0) { if (a&0x1) d++.type == .

type==.Chapter 8. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. bfind.shiftamt.s32) ? 31 : 63.s64 cnt. // cnt is .type = { . break. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. and operand d has type . For unsigned integers.d.0. i>=0. Instruction Set Table 41. bfind requires sm_20 or later. d = -1. bfind. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.type==.shiftamt && d != -1) { d = msb . i--) { if (a & (1<<i)) { d = i. For signed integers. } } if (.shiftamt is specified. bfind returns 0xFFFFFFFF if no non-sign bit is found. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .type bfind. . a. d.u32 || . .u32 d. 2010 75 . X.s64 }.type d. a. bfind returns the bit position of the most significant “1”. Description Find the bit position of the most significant non-sign bit in a and place the result in d.u32.u32 January 24. Operand a has the instruction type. bfind.u64.u32.shiftamt. for (i=msb. . If .s32. a. Semantics msb = (.

i++) { d[i] = a[msb-i].type = { . .0. .PTX ISA Version 2. i<=msb. brev requires sm_20 or later. a. for (i=0. brev. a.b32) ? 31 : 63. msb = (. 76 January 24.b64 }.type d. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.b32. Description Semantics Perform bitwise reversal of input. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==.0 Table 42. brev. 2010 .b32 d.

u32. else sbit = a[min(pos+len-1. Operands a and d have the same type as the instruction type. Semantics msb = (.u32 || . . The sign bit of the extracted field is defined as: . Instruction Set Table 43. bfe.s32) ? 31 : 63. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. d = 0.u32. .u32.u32 || .msb)].type = { . bfe. c. 2010 77 . i<=msb. Description Extract bit field from a and place the zero or sign-extended result in d. pos = b.s64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==.start. b. . . len = c. and source c gives the bit field length in bits. for (i=0.s32. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.b32 d. and operands b and c are type .s32. . if (. If the start position is beyond the msb of the input.u64 || len==0) sbit = 0.0.a.type d.type==. Source b gives the bit field starting bit position.u64.u64: .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.Chapter 8. a. otherwise If the bit field length is zero. bfe requires sm_20 or later. January 24.len. The destination d is padded with the sign bit of the extracted field.type==. . the destination d is filled with the replicated sign bit of the extracted field.type==. the result is zero.

b64 }. bfi requires sm_20 or later. b. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. If the bit field length is zero. len = d. bfi. c.0 Table 44. 78 January 24. Semantics msb = (. .b. and operands c and d are type . and place the result in f. and source d gives the bit field length in bits. Description Align and insert a bit field from a into b. and f have the same type as the instruction type. 2010 .b32 d.PTX ISA Version 2.type = { . f = b. i<len && pos+i<=msb. i++) { f[pos+i] = a[i].0. Source c gives the starting bit position for the insertion. pos = c.type f.start.b32. for (i=0. b. the result is b.b32) ? 31 : 63.u32.len. d. . the result is b. bfi. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Operands a. If the start position is beyond the msb of the input.type==.a. a.

default mode index d.f4e. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. 2010 79 .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. and reassemble them into a 32-bit destination register. a 4-bit selection value is defined. the permute control consists of four 4-bit selection values. {b3. b2.b3 source select c[15:12] d. . b5.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. b1.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. Note that the sign extension is only performed as part of generic form. b4}. a} = {{b7. Thus. Instruction Set Table 45. .b2 source select c[11:8] d. . The bytes in the two source registers are numbered from 0 to 7: {b.mode} d. as a 16b permute code. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. Description Pick four arbitrary bytes from two 32-bit registers. msb=1 means replicate the sign. In the generic form (no mode specified).b4e. the four 4-bit values fully specify an arbitrary byte permute.ecr.mode = { .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b1 source select c[7:4] d. . .b32{. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). . a. b. The msb defines if the byte value should be copied. msb=0 means copy the literal value. b6.ecl.Chapter 8.rc16 }.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. prmt. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.rc8. For each byte in the target register. b0}}. c.

tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[1] = (c >> 4) & 0xf. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. r4. ctl[0]. prmt requires sm_20 or later. r2. ctl[2] = (c >> 8) & 0xf.f4e r1. r3. tmp64 ). tmp[31:24] = ReadByte( mode. ctl[3]. 2010 .b32 prmt. r4. 80 January 24.0. tmp[15:08] = ReadByte( mode.0 Semantics tmp64 = (b<<32) | a. ctl[2]. r1. ctl[1]. tmp64 ). tmp64 ). prmt. r2. r3.PTX ISA Version 2. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. } tmp[07:00] = ReadByte( mode. ctl[3] = (c >> 12) & 0xf. tmp[23:16] = ReadByte( mode.

2.f32 and . Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.f64 register operands and constant immediate values.Chapter 8. 2010 81 .7.

f32 {abs.neg.cos.rnd.sqrt}.sqrt}.fma}.target sm_20 mad.f32 {mad. Instruction Summary of Floating-Point Instructions .rz .approx.sub. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.rp .f64 are the same.rn and instructions may be folded into a multiply-add. No rounding modifier.f64 {sin.0. default is . but single-precision instructions return an unspecified NaN. sub.sqrt}.rnd.f32 rsqrt.rnd.max}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. The optional .f32 {div.lg2.f64 and fma.sat Notes If no rounding modifier is specified.rn and instructions may be folded into a multiply-add.f64 div. so PTX programs should not rely on the specific single-precision NaNs being generated.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {add.approx.max}.0].sub.f64 rsqrt. 82 January 24. Table 46.min.f64 {abs.rm .f32 {div.rcp. 2010 .f32 are the same.target sm_20 .approx.mul}.ftz .PTX ISA Version 2. If no rounding modifier is specified.neg.0 The following table summarizes floating-point instructions in PTX.fma}.f64 mad.target sm_1x No rounding modifier.rcp.rn . with NaNs being flushed to positive zero.approx.rcp.32 and fma. . mul.f32 {div.ex2}. and mad support saturation of results to the range [0. 1. Note that future implementations may support NaN payloads for single-precision instructions. NaN payloads are supported for double-precision instructions.full. default is .rnd. {add. {mad.f32 . Double-precision instructions support subnormal inputs and results.mul}.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. Single-precision add.rnd.min.rnd. .

copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.pred = { . Table 48.op. testp.type . . true if the input is a subnormal number (not NaN. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. . .number.finite testp. .normal. C.notanumber.op p.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . copysign requires sm_20 or later. f0. positive and negative zero are considered normal numbers.notanumber. testp requires sm_20 or later. testp Syntax Floating-Point Instructions: testp Test floating-point property. . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. copysign. January 24. A.f64 }. Introduced in PTX ISA version 2. . // result is . testp.f64 isnan.subnormal }. a.0. b. Instruction Set Table 47. .f32 testp. 2010 83 . X. z.f64 }.f32 copysign. testp.f32. not infinity) As a special case.infinite testp. not infinity). .notanumber testp.finite.f32. p. and return the result as d.number testp. B. y.type d.0.Chapter 8.infinite.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.infinite.f64 x. copysign. a.normal testp.type = { .

.sat.rm. add.ftz.f64 requires sm_13 or later. requires sm_13 for add. requires sm_20 Examples @p add.f64 supports subnormal numbers. 1. b.f32 clamps the result to [0.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: add. a.f64 d.rm mantissa LSB rounds towards negative infinity .rn. subnormal numbers are supported. d. . . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.sat}. add. 2010 .rnd = { .0. Rounding modifiers have the following target requirements: .0. NaN results are flushed to +0.f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 f1.f32 flushes subnormal inputs and results to sign-preserving zero.rn mantissa LSB rounds to nearest even . 84 January 24.0 Table 49. .f3.0f.rm. . add.rz mantissa LSB rounds towards zero .rn.rn): . Rounding modifiers (default is .ftz.rz available for all targets . b. In particular.f2. add{. . add.rp for add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rp }. add. a. add Syntax Floating-Point Instructions: add Add two values.rz.0].f64.f32 add{.rz.PTX ISA Version 2. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. d = a + b.rnd}.ftz}{. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 supported on all target architectures. Saturation modifier: .rnd}{. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.

f32 flushes subnormal inputs and results to sign-preserving zero.rnd}.f32. a. sm_1x: sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero .0f.rp for sub. 2010 85 . . . d = a . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rp }.f64.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.0.rn. Saturation modifier: sub. 1. NaN results are flushed to +0. sub.sat.rn. b.rm.rn): . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.0].rz available for all targets .rn mantissa LSB rounds to nearest even .f32 f1. sub Syntax Floating-Point Instructions: sub Subtract one value from another. . .ftz.rnd = { . January 24. subnormal numbers are supported. sub{. d.sat}.f2.f64 supports subnormal numbers.rm.Chapter 8.ftz}{.a. Rounding modifiers have the following target requirements: .0.b.f32 clamps the result to [0. sub.rn. . Rounding modifiers (default is .f32 sub{. requires sm_20 Examples sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f3. a.f32 c. sub.f64 requires sm_13 or later.rm mantissa LSB rounds towards negative infinity .rz.ftz.b. sub. Instruction Set Table 50.f32 supported on all target architectures. b. . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. In particular.rnd}{. requires sm_13 for sub.

mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. d = a * b. 1.f64 supports subnormal numbers. Description Semantics Notes Compute the product of two values. all operands must be the same size. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rn): . NaN results are flushed to +0.sat}.rp }.0 Table 51. requires sm_20 Examples mul.rz.rz available for all targets . . mul. .rnd = { . Rounding modifiers have the following target requirements: .radius. a.0f. mul. . mul Syntax Floating-Point Instructions: mul Multiply two values. d. 2010 .f64 d.f32 circumf. .f32 clamps the result to [0.0].rnd}.rp for mul.f32 supported on all target architectures. For floating-point multiplication. mul. b. In particular.rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: mul.f32 mul{.rm mantissa LSB rounds towards negative infinity . requires sm_13 for mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm. a.rn.rm.f32 flushes subnormal inputs and results to sign-preserving zero.pi // a single-precision multiply 86 January 24. .sat. Saturation modifier: mul.rnd}{. subnormal numbers are supported. Rounding modifiers (default is . b.0.0.ftz}{. .f32.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64. mul.PTX ISA Version 2.rz mantissa LSB rounds towards zero .ftz.f64 requires sm_13 or later. mul{. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.ftz.

fma.rz.f32 fma.f64 requires sm_13 or later.0. c.rnd. The resulting value is then rounded to double precision using the rounding mode specified by .f64 computes the product of a and b to infinite precision and then adds c to this product.rn. d.f64 is the same as mad. sm_1x: fma.f32 requires sm_20 or later.f32 computes the product of a and b to infinite precision and then adds c to this product. c. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. a. @p fma.f32 fma.y.ftz. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma. subnormal numbers are supported.f64 w.f64 d. PTX ISA Notes Target ISA Notes Examples January 24.sat}. again in infinite precision.rp }. Instruction Set Table 52. fma. fma. The resulting value is then rounded to single precision using the rounding mode specified by .rn mantissa LSB rounds to nearest even . b.4.rn.f32 is unimplemented in sm_1x. Rounding modifiers (no default): .rnd{. d.rm.rm mantissa LSB rounds towards negative infinity . d = a*b + c.rnd.ftz}{. fma. . fma.rnd.f64 introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero . fma. fma.x. fma.0].sat. NaN results are flushed to +0.f64 supports subnormal numbers. .0f.f64. a.rn.ftz. fma.b. again in infinite precision.c.Chapter 8.a.f32 introduced in PTX ISA version 2. . Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.z. .rnd = { . Saturation: fma.f32 clamps the result to [0.f32 flushes subnormal inputs and results to sign-preserving zero. b.0. 2010 87 .

the treatment of subnormal inputs and output follows IEEE 754 standard. b. again in infinite precision.rn.f64}. In this case. mad.rnd.f32).f32 is implemented as a fused multiply-add (i. // . 88 January 24.f32.rp }.{f32.f32 mad.rnd. The resulting value is then rounded to single precision using the rounding mode specified by . again in infinite precision. Note that this is different from computing the product with mul.rnd. .rnd = { .rnd. mad{. where the mantissa can be rounded and the exponent will be clamped. // .f64 d. Rounding modifiers (no default): .target sm_20 d. mad. . b.rz mantissa LSB rounds towards zero .rnd{.0.sat.rn. a. mad.0. Description Semantics Notes Multiplies two values and adds a third.f32 is when c = +/-0.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 computes the product of a and b at double precision. a.f32 clamps the result to [0. When JIT-compiled for SM 2. d = a*b + c. but the exponent is preserved.target sm_13 and later .f64 supports subnormal numbers. 1.0]. The resulting value is then rounded to double precision using the rounding mode specified by .rm mantissa LSB rounds towards negative infinity . mad. mad. c. mad.target sm_1x d.f64. a.0 Table 53.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. . c. and then writes the resulting value into a destination register. mad. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero.f64} is the same as fma. mad. For .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0f.target sm_20: mad.PTX ISA Version 2.ftz}{. b.f32 mad. again in infinite precision. The exception for mad.ftz}{.rm.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz. fma. NaN results are flushed to +0..f64 is the same as fma. 2010 .sat}. and then the mantissa is truncated to 23 bits. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.e.{f32.target sm_1x: mad. Saturation modifier: mad.rn mantissa LSB rounds to nearest even . c.sat}. // . The resulting value is then rounded to double precision using the rounding mode specified by . sm_1x: mad.f32 flushes subnormal inputs and results to sign-preserving zero. Unlike mad.rz. mad.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 is identical to the result computed using separate mul and add instructions.0 devices.ftz. For .

. In PTX ISA versions 1.4 and later. Legacy mad.f32 for sm_20 targets.rn.rm.c. mad.f64 instructions having no rounding modifier will map to mad. requires sm_20 Examples @p mad. Target ISA Notes mad..Chapter 8.rn.b..rn.rz.0 and later. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.. Rounding modifiers have the following target requirements: .rp for mad.f64 requires sm_13 or later.f64. In PTX ISA versions 2.rm.f32 supported on all target architectures.rp for mad.f64.0. requires sm_13 .rz.f64. January 24. 2010 89 .f32.a..f32 d. a rounding modifier is required for mad.. a rounding modifier is required for mad.

div.rnd{.rnd.14159. 2010 .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. div. y. . .4 and later.rn.f32.approx. b. div.f32 div.f32 and div. d.approx{.f64. full-range approximation that scales operands to achieve better accuracy.rm mantissa LSB rounds towards negative infinity . a.f64 defaults to div.ftz}.rnd. The maximum ulp error is 2 across the full range of inputs. b.rp }. div Syntax Floating-Point Instructions: div Divide one value by another. Fast.ftz.rnd = { . Examples 90 January 24. a.f32 div.rz.rn mantissa LSB rounds to nearest even . .f64 requires sm_20 or later.f32 div. zd. d. z.full. Description Semantics Notes Divides a by b. d = a / b. div. div.f32 div.ftz}. or . one of . div. .full.rn.ftz. For PTX ISA version 1.approx. d.4. div.ftz}. the maximum ulp error is 2. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .3. subnormal numbers are supported. sm_1x: div. Explicit modifiers .f32 implements a fast approximation to divide. approximate single-precision divides: div. but is not fully IEEE 754 compliant and does not support rounding modifiers. stores result in d. . yd. computed as d = a * (1/b).f64 requires sm_13 or later.f32 defaults to div.circum.{rz. Fast. b. // // // // fast.full. and rounding introduced in PTX ISA version 1. and div. b. div. xd.full.rz mantissa LSB rounds towards zero . a.approx.approx.rm.rnd is required.f32 div.rp}.ftz.f64 supports subnormal numbers. 2126]. a. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 implements a relatively fast.f32 flushes subnormal inputs and results to sign-preserving zero. For b in [2-126. PTX ISA Notes div.rm.approx. For PTX ISA versions 1. Subnormal inputs and results are flushed to sign-preserving zero.3.f64 diam.0 Table 54.rn. Target ISA Notes div. approximate division by zero creates a value of infinity (with same sign as a).0 through 1.approx.ftz.f32 supported on all target architectures.f64 introduced in PTX ISA version 1. div.0. .full.PTX ISA Version 2.rn.f32 requires sm_20 or later.full{. x.f32 and div.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.

neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. subnormal numbers are supported.ftz. neg. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f64 requires sm_13 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs.ftz. sm_1x: neg.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 55.Chapter 8. d = |a|. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Table 56. neg.f32 x.f32 supported on all target architectures. NaN inputs yield an unspecified NaN.0. NaN inputs yield an unspecified NaN. d = -a. d.f32 neg.f32 x. neg. abs.f64 d. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 supports subnormal numbers.f0. January 24. a. a. Subnormal numbers: sm_20: By default. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. neg. subnormal numbers are supported. a.f32 supported on all target architectures.0. neg. abs{.f32 flushes subnormal inputs and results to sign-preserving zero. abs.f64 requires sm_13 or later. neg{. Negate the sign of a and store the result in d.f32 flushes subnormal inputs and results to sign-preserving zero. Take the absolute value of a and store the result in d.f64 supports subnormal numbers.ftz.f32 abs.ftz}. abs.ftz}. sm_1x: abs.f64 d.f0. 2010 91 .

max.f64 requires sm_13 or later. b. b.0. d d d d = = = = NaN.c.f64 requires sm_13 or later.f64 z. max. b.ftz}.f2.f32 flushes subnormal inputs and results to sign-preserving zero.f64 f0.f32 max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.c.f32 min.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.f32 max. d. min. max.f64 d. a. subnormal numbers are supported. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. min. Store the minimum of a and b in d. (a < b) ? a : b.f32 supported on all target architectures.0 Table 57.f32 supported on all target architectures.ftz. a. a. min.ftz. Table 58. d.PTX ISA Version 2. b.z.f32 flushes subnormal inputs and results to sign-preserving zero. 92 January 24.f64 supports subnormal numbers.f32 min.f64 supports subnormal numbers. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.ftz.ftz}.b. sm_1x: min. max. Store the maximum of a and b in d.f1. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b. 2010 . sm_1x: max. max. @p min. a. a.f32 flushes subnormal inputs and results to sign-preserving zero. a. min{. min. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. a. max{.f64 d. b. d d d d = = = = NaN. b. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.ftz. (a > b) ? a : b.x.0.

rn.f32 flushes subnormal inputs and results to sign-preserving zero.f32 rcp.f64 introduced in PTX ISA version 1.0 through 1.rm.0 over the range 1.f32 defaults to rcp. rcp.approx. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f32 rcp.0 +subnormal +Inf NaN Result -0.f32 supported on all target architectures.ftz}.4. Description Semantics Notes Compute 1/a.f64 defaults to rcp.4 and later.{rz. .ftz}.f32 requires sm_20 or later.rnd.f64 requires sm_13 or later.ftz.approx or .rnd{. . Examples January 24.Chapter 8.approx and . rcp.0-2. xi.approx{.f64 and explicit modifiers .f64.ftz.rn.approx.f64 ri. General rounding modifiers were added in PTX ISA version 2.f64 supports subnormal numbers.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 rcp. subnormal numbers are supported.0 +0. The maximum absolute error is 2-23. xi. For PTX ISA version 1. PTX ISA Notes rcp.3.rn mantissa LSB rounds to nearest even . Instruction Set Table 59. rcp.rn. a. and rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. d.f32 rcp.rn.ftz.rn. .x.f64 requires sm_20 or later. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . For PTX ISA versions 1.rm mantissa LSB rounds towards negative infinity .approx. Input -Inf -subnormal -0.x. // fast. rcp. a.f32 and rcp. d = 1 / a.f32.rp}. sm_1x: rcp. d.0. one of .ftz were introduced in PTX ISA version 1. rcp. 2010 93 .f64 d.r. Target ISA Notes rcp. store result in d.rz.f32 flushes subnormal inputs and results to sign-preserving zero.rnd.approx.0. rcp.rz mantissa LSB rounds towards zero .rp }. rcp. rcp.f32 implements a fast approximation to reciprocal.rnd is required.rm.rnd = { .0. rcp. a. rcp.0 -Inf -Inf +Inf +Inf +0.rn.

approx and .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. // fast. PTX ISA Notes sqrt. Description Semantics Notes Compute sqrt(a). a.ftz. sqrt.approx or . sqrt.f64 introduced in PTX ISA version 1. store in d. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. . Input -Inf -normal -subnormal -0.ftz}.rp }. and sqrt.4 and later.0 Table 60. Examples 94 January 24. .0 +0.f64 r.rnd{. // IEEE 754 compliant rounding d. r.approx.f32 defaults to sqrt.rn.rm mantissa LSB rounds towards negative infinity .f32 flushes subnormal inputs and results to sign-preserving zero.0. d = sqrt(a).f32 and sqrt. sm_1x: sqrt.rz. sqrt.rn. .f32 sqrt. a. approximate square root d. // IEEE 754 compliant rounding .rnd = { .ftz.f32 supported on all target architectures. r. For PTX ISA version 1.0 +0.f32 implements a fast approximation to square root.rn.ftz.rm. 2010 .rn.0 +0.ftz were introduced in PTX ISA version 1.3.rn.ftz}.rn.{rz.approx.x.f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA versions 1.f32 sqrt.f64 requires sm_20 or later.f64 and explicit modifiers . subnormal numbers are supported.f32 sqrt.approx.rz mantissa LSB rounds towards zero .0 through 1. sqrt.f64 supports subnormal numbers.x.rn mantissa LSB rounds to nearest even . a.approx{.rnd is required. sqrt.approx.f64.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .4. sqrt.f32.rm.f32 requires sm_20 or later.x. The maximum absolute error for sqrt. sqrt.f32 sqrt. sqrt. Target ISA Notes sqrt.rnd.rnd.0 +subnormal +Inf NaN Result NaN NaN -0.PTX ISA Version 2. one of .f64 requires sm_13 or later.f64 defaults to sqrt.f64 d. sqrt.0 -0.rp}.f32 is TBD. sqrt.0.approx.ftz. General rounding modifiers were added in PTX ISA version 2.

ISR.3. store the result in d.0. 2010 95 . Subnormal numbers: sm_20: By default.ftz}.f32 defaults to rsqrt.approx.4 over the range 1.0-4.approx{. rsqrt.approx implements an approximation to the reciprocal square root. a.f64 is TBD. January 24.ftz were introduced in PTX ISA version 1.f64 defaults to rsqrt. subnormal numbers are supported.f64 requires sm_13 or later. Explicit modifiers . d. For PTX ISA versions 1.f32 rsqrt. x. rsqrt.approx.approx.f32 flushes subnormal inputs and results to sign-preserving zero.approx modifier is required. the .0 +0.f32 flushes subnormal inputs and results to sign-preserving zero.f64 is emulated in software and are relatively slow. Target ISA Notes Examples rsqrt. d = 1/sqrt(a). Input -Inf -normal -subnormal -0.f64 isr. Instruction Set Table 61. PTX ISA Notes rsqrt. a.ftz.4.approx. For PTX ISA version 1.Chapter 8. and rsqrt.0.f32.f32 rsqrt.0 through 1.f32 is 2-22. rsqrt. X.f64 d.ftz.f64.0 NaN The maximum absolute error for rsqrt. The maximum absolute error for rsqrt. rsqrt. Note that rsqrt.f32 and rsqrt. sm_1x: rsqrt. rsqrt. Compute 1/sqrt(a).approx and .f32 supported on all target architectures.ftz.4 and later.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt. rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f64 supports subnormal numbers.approx.approx.f64 were introduced in PTX ISA version 1.

PTX ISA Notes sin. sm_1x: Subnormal inputs and results to sign-preserving zero. Target ISA Notes Examples Supported on all target architectures.0 +0.ftz introduced in PTX ISA version 1. sin. a.f32 defaults to sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx and . sin.approx.f32 sa.0 through 1.0 -0.0. sin.f32 flushes subnormal inputs and results to sign-preserving zero. Find the sine of the angle a (in radians).4 and later. For PTX ISA versions 1. the . For PTX ISA version 1.PTX ISA Version 2. Explicit modifiers .approx.4.f32. sin. 2010 . sin.ftz}.f32 d.ftz. d = sin(a).0 NaN NaN The maximum absolute error is 2-20.0 +0. a. Input -Inf -subnormal -0.approx{.approx.f32 introduced in PTX ISA version 1.0 Table 62. Subnormal numbers: sm_20: By default.approx modifier is required.ftz.0 +subnormal +Inf NaN Result NaN -0. subnormal numbers are supported.0 +0. 96 January 24.3.f32 implements a fast approximation to sine.ftz.9 in quadrant 00.

f32. Instruction Set Table 63.approx{. cos. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. subnormal numbers are supported.approx modifier is required.9 in quadrant 00. cos. Input -Inf -subnormal -0.0 +subnormal +Inf NaN Result NaN +1. Find the cosine of the angle a (in radians).3. Explicit modifiers .0 NaN NaN The maximum absolute error is 2-20. PTX ISA Notes cos. For PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.4 and later. cos. d = cos(a).ftz. a.f32 introduced in PTX ISA version 1.f32 defaults to cos.f32 ca. the .ftz.0 +1.0.approx. cos.Chapter 8. a.f32 implements a fast approximation to cosine. For PTX ISA versions 1.approx and .approx.ftz introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default. January 24.ftz}.0 through 1.0 +1.f32 d. sm_1x: Subnormal inputs and results to sign-preserving zero.4. 2010 97 . cos. Target ISA Notes Examples Supported on all target architectures.0 +0.ftz.approx.0 +1.

0 +0.approx{.approx.0 through 1.approx.6 for mantissa. lg2.f32 defaults to lg2. lg2. For PTX ISA version 1.f32 la. Subnormal numbers: sm_20: By default.3.f32 Determine the log2 of a.approx modifier is required. lg2. the .f32.ftz}.approx and .0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. PTX ISA Notes lg2. Explicit modifiers . lg2.f32 introduced in PTX ISA version 1. The maximum absolute error is 2-22. a.0 Table 64. d = log(a) / log(2).4.f32 implements a fast approximation to log2(a).ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 . a.0.ftz.4 and later. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.approx. subnormal numbers are supported. Target ISA Notes Examples Supported on all target architectures.ftz introduced in PTX ISA version 1. lg2.ftz. For PTX ISA versions 1. 98 January 24.PTX ISA Version 2. Input -Inf -subnormal -0.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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. leu.B) is one of: and. leu. neu. bit-size comparisons are eq and ne. geu.u32 p|q.ftz}. ne. 102 January 24. . If either operand is NaN. @q setp. subnormal numbers are supported. setp with . If both operands are numeric values (not NaN). higher. or. . setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. nan The Boolean operator BoolOp(A. . setp.lt. then the result of these comparisons is true.f64 }. . setp. 2010 . respectively. a. gt. ls.f64 source type requires sm_13 or later.s32. If either operand is NaN. the comparison operators lo. . and hs for lower. le. a. p[|q]. le. unordered versions are included: equ. .u16. ge. Modifier . hi. Semantics t = (a CmpOp b) ? 1 : 0.0 Table 67.f32. . .PTX ISA Version 2. The signed and unsigned comparison operators are eq. lt. lt.pred variables.s32 setp. Integer Notes Floating Point Notes The ordered comparisons are eq.type . p. ltu. neu. c).type = { . ls. . gt.0. {!}c. sm_1x: setp.ftz}. A related value computed using the complement of the compare result is written to the second destination operand. setp. q = BoolOp(!t. hs equ. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.f32 flushes subnormal inputs to sign-preserving zero. The comparison operator is a suffix on the instruction.dtype. loweror-same.s64.ftz applies only to . This result is written to the first destination operand.b32. and (optionally) combine this result with a predicate value by applying a Boolean operator.BoolOp{.CmpOp{. gtu. ne. and can be one of: eq. To aid comparison operations in the presence of NaN values. gt. and higher-or-same may be used instead of lt.b.ftz. and nan returns true if either operand is NaN. num. ltu. Applies to all numeric types. lo. The destinations p and q must be . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. gtu. ge.s16. For unsigned values.b16.CmpOp.eq.a.n. Subnormal numbers: sm_20: By default. then these comparisons have the same result as their ordered counterparts.r. xor.f64 supports subnormal numbers.i. gt.u64. ge. ne.f32 flushes subnormal inputs to sign-preserving zero. ge. p = BoolOp(t.b64. The untyped. le. the result is false.type setp. c). b.and.dtype. hi. geu. b. lt.u32.dtype. p[|q]. le.f32 comparisons. num returns true if both operands are numeric values (not NaN).

a.b32. the comparison is unordered and operand b is selected. . The selected input is copied to the output without modification.ftz. d. .u64. . . and b must be of the same type. slct Syntax Comparison and Selection Instructions: slct Select one source operand. . y. slct. . f0.ftz applies only to .Chapter 8. If operand c is NaN.b64. Subnormal numbers: sm_20: By default.f32 flushes subnormal values of operand c to sign-preserving zero.s32. . a.f64 }. negative zero equals zero. Operand c is a predicate.dtype = { .f64 }. B. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.r.ftz}. . .s64.s64. b.b32. Introduced in PTX ISA version 1. operand c must match the second instruction type. selp. c.f64 requires sm_13 or later.t.s32 x.u64. . slct.u64.dtype. c. .type = { .0. C.dtype.ftz. subnormal numbers are supported. d = (c >= 0) ? a : b. Instruction Set Table 68. .b16. fval. a is stored in d. . b otherwise. Semantics Floating Point Notes January 24. For .xp.f64 requires sm_13 or later.u32. Description Conditional selection. 2010 103 . and b are treated as a bitsize type of the same width as the first instruction type.f32 comparisons.0.f32 r0. and operand a is selected.p. Table 69.dtype. .f32 d. a. based on the value of the predicate source operand.f32. sm_1x: slct. b. based on the sign of the third operand. . slct.s32 slct{. . . Modifier .s16. @q selp.f32.s32 selp.g. and operand a is selected. If c is True.f32 A. d = (c == 1) ? a : b. selp Syntax Comparison and Selection Instructions: selp Select between source operands. . z.b64. selp.s16. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. slct. c.f32 flushes subnormal values of operand c to sign-preserving zero.s32.dtype.x.b16.u32. b. . Operands d.type d. a. Operands d.f32 comparisons. . val. a. a is stored in d.u32. otherwise b is stored in d.u16.u16. . slct. If c ≥ 0.

or. Instructions and. This permits bit-wise operations on floating point values without having to define a union to access the bits. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.PTX ISA Version 2. and not also operate on predicates.0 8. performing bit-wise operations on operands of any type. 2010 . provided the operands are of the same size.4.7. xor.

Introduced in PTX ISA version 1.type d.r.b16. d = a & b.b64 }.b64 }.0x00010001 or.q. a. . Instruction Set Table 70.b32. . Supported on all target architectures.b16. but not necessarily the type.fpvalue.q.type d. January 24.Chapter 8. Table 71. but not necessarily the type. or Syntax Logic and Shift Instructions: or Bitwise OR. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.r. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. .pred. sign. and Syntax Logic and Shift Instructions: and Bitwise AND. .b32 and. or.pred p. Allowed types include predicate registers.b32 mask mask.0. Allowed types include predicate registers. Supported on all target architectures. 2010 105 . d = a | b.pred. . or.b32. Introduced in PTX ISA version 1. . a.0.0x80000000. . and. . The size of the operands must match.type = { .type = { . The size of the operands must match.b32 x. b. and. b.

Table 73.b32 d. Allowed types include predicate registers.PTX ISA Version 2.0.type = { .r. d = ~a. one’s complement. . Table 74. . . The size of the operands must match.pred. Allowed types include predicates. xor. xor. d = a ^ b. . .0 Table 72. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.pred p.q.type d. Introduced in PTX ISA version 1.b16.b16. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b32. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b32 xor.b16. cnot. Introduced in PTX ISA version 1. a. not. but not necessarily the type. 2010 . 106 January 24.b64 }. b. Introduced in PTX ISA version 1.x. cnot.b64 }. .type d. Supported on all target architectures. not. d.b32. a. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. .type d. not Syntax Logic and Shift Instructions: not Bitwise negation.b32.pred.mask. d = (a==0) ? 1 : 0.b16 d.0x0001.b32 mask.0.0. Supported on all target architectures. Supported on all target architectures.type = { . but not necessarily the type.type = { .q. . a. not. The size of the operands must match. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.a.b64 }. . The size of the operands must match. .

Shift amounts greater than the register width N are clamped to N.s32. The b operand must be a 32-bit value. shr Syntax Logic and Shift Instructions: shr Shift bits right. Signed shifts fill with the sign bit. regardless of the instruction type. . but not necessarily the type. .u16.s32 shr.b32.b16.b32 q. b. a. i. but not necessarily the type.0.b64 }.i.b16. . Shift amounts greater than the register width N are clamped to N. The sizes of the destination and first source operand must match. Supported on all target architectures. .a. . Bit-size types are included for symmetry with SHL. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. .u16 shr. . Supported on all target architectures. d = a << b. shr. 2010 107 . PTX ISA Notes Target ISA Notes Examples Table 76.a.u64.s64 }. PTX ISA Notes Target ISA Notes Examples January 24. shl Syntax Logic and Shift Instructions: shl Shift bits left. k.type = { . sign or zero fill on left. zero-fill on right. shl. The b operand must be a 32-bit value. shr.i. b. regardless of the instruction type. .s16.0. The sizes of the destination and first source operand must match.2.1. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.b16 c.2.j.b32. Introduced in PTX ISA version 1. a. .type = { . . shl. . Introduced in PTX ISA version 1. d = a >> b.u32.Chapter 8.type d.type d. unsigned and untyped shifts fill with 0. Instruction Set Table 75.b64. .

mov. st. 2010 . The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. ld. possibly converting it from one format to another. or shared state spaces. Instructions ld. ldu.PTX ISA Version 2. and sust support optional cache operations. The cvta instruction converts addresses between generic and global.0 8. and from state space to state space. prefetchu isspacep cvta cvt 108 January 24. suld.7. Data Movement and Conversion Instructions These instructions copy data from place to place. and st operate on both scalar and vector types. local. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.5.

As a result of this request. to allow the thread program to poll a SysMem location written by the CPU. and cache only in the L2 cache. the cache operators have the following definitions and behavior. bypassing the L1 cache. Use ld. . not L1).lu operation. The cache operators require a target architecture of sm_20 or later. A ld. The ld. rather than the data stored by the first thread.ca loads cached in L1.ca.1. invalidates (discards) the local L1 line following the load. The compiler / programmer may use ld. and a second thread loads that address via a second L1 cache with ld. Global data is coherent at the L2 level.lu load last use operation. Table 77. if the line is fully covered.lu instruction performs a load cached streaming operation (ld.cs. evict-first. when applied to a local address. The default load instruction cache operation is ld. likely to be accessed once.cs) on global addresses. For sm_20 and later. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.5.lu Last use.cg Cache at global level (cache in L2 and below. The ld.cs is applied to a Local window address.0 introduces optional cache operators on load and store instructions. the second thread may get stale L1 cache data. When ld.cv Cache as volatile (consider cached system memory lines stale. . which allocates cache lines in all levels (L1 and L2) with normal eviction policy. If one thread stores to global memory via one L1 cache. 2010 109 .Chapter 8. . The driver must invalidate global L1 cache lines between dependent grids of parallel threads. Instruction Set 8.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. any existing cache lines that match the requested address in L1 will be evicted. Cache Operators PTX 2. fetch again).7.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. it performs the ld.cv to a frame buffer DRAM address is the same as ld. January 24. Operator .cg to cache loads only globally. . The ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. but multiple L1 caches are not coherent for global data.ca.cs Cache streaming. likely to be accessed again. The ld.

2010 .cg is the same as st. .ca loads. The st.cg to cache global store data only globally. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wt Cache write-through (to system memory).wb could write-back global store data from L1. Global stores bypass L1.wb. and discard any L1 lines that match. which writes back cache lines of coherent cache levels with normal eviction policy. but st. in which case st. likely to be accessed once.wb for global data.cs Cache streaming. The default store instruction cache operation is st. .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. If one thread stores to global memory. In sm_20.wt store write-through operation applied to a global System Memory address writes through the L2 cache. The st. Future GPUs may have globally-coherent L1 caches. Addresses not in System Memory use normal write-back. st. and a second thread in a different SM later loads from that address via a different L1 cache with ld. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.PTX ISA Version 2. to allow a CPU program to poll a SysMem location written by the GPU with st. bypassing its L1 cache. Operator . and marks local L1 lines evict-first. .cg Cache at global level (cache in L2 and below. 110 January 24.0 Table 78. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.ca.wt. rather than get the data from L2 or memory stored by the first thread. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. Use st.cg to local memory uses the L1 cache. bypassing the L1 cache. regardless of the cache operation. However. not L1). and cache only in the L2 cache.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. the second thread may get a hit on stale L1 cache data.

the address of the variable in its state space) into the destination register. sreg.type = { .u32 mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.1. k.b16. avar.f32 mov. local. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. label. . mov places the non-generic address of the variable (i. the generic address of a variable declared in global. A[5]. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. or shared state space may be taken directly using the cvta instruction. addr.const. . myFunc.Chapter 8. local.b64. u. Write register d with the value of a.0. local.s64.f32 mov. label. // address is non-generic. ptr. Semantics d = a.e. The generic address of a variable in global.type mov.f32.v. .u64.a. . d. Take the non-generic address of a variable in global. A. the parameter will be copied onto the stack and the address will be in the local state space. . ptr.f64 }. Introduced in PTX ISA version 1.u32. immediate.s32. mov.0. // get address of variable // get address of label or function . i. or function name. d.b32. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. Description .pred.s16. d = sreg... 2010 111 .u32 mov. Note that if the address of a device function parameter is moved to a register. mov.u16 mov.shared state spaces. d = &label. Operand a may be a register.f64 requires sm_13 or later. within the variable’s declared state space Notes Although only predicate and bit-size types are required.u32 d. . For variables declared in . and . alternately.type d. Instruction Set Table 79. or shared state space.type mov. special register. mov. variable in an addressable memory space.e.global. .type mov. . d = &avar. .local. . d. a.u16. . .

.31] } // unpack 8-bit elements from .7].y. 2010 . or write vector register d with the unpacked values from scalar register a.b16.y.w}.y << 16) d = a. Semantics d = a. . {r.x.31]. mov.7].w << 48) d = a.y << 16) | (a.b32 %r1. d.w have type .g.y << 8) d = a.. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b}. a[8. a[24.23]. a[16.b32 { d.%r1. a[32.z.b16 // pack four 8-bit elements into .x | (a.z << 32) | (a. a[8. a[32.. d.x | (a. .u32 x.31] } // unpack 16-bit elements from .. d.b64 { d.{a.y } = { a[0.y.{x.b32 // pack four 16-bit elements into .b32 mov.. a[16.x. a[16.a}.b64 // pack two 32-bit elements into . For bit-size types.b64 mov.g.hi are .47].w } = { a[0.x | (a.31]. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.b32 { d.b have type .z.15]. d.b64 112 January 24.63] } // unpack 16-bit elements from .type d.y << 8) | (a. %r1.b8 r.type = { .b64 { d.15].x.w } = { a[0.w << 24) d = a. %x..z. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).PTX ISA Version 2. a[48. mov.b64 }.u16 %x is a double. d.b16 { d. d. {lo.. a. d.a have type .15].. // // // // a.0 Table 80. Supported on all target architectures..hi}.b32... .x | (a.b32 // pack two 16-bit elements into ..z << 16) | (a.15] } // unpack 8-bit elements from .b32 mov.y } = { a[0.z.b.y } = { a[0.x | (a.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. lo.u8 // unpack 32-bit elements from ..x.y << 32) // pack two 8-bit elements into .y.0.b.. d. Description Write scalar register d with the packed value of vector register a. d.x.

d.s32.s16.0.s64.cg. . or [immAddr] an immediate absolute byte address (unsigned. Cache operations are not permitted with ld.volatile{.vec.v2.cop}. .f64 using cvt.ss}. . .volatile introduced in PTX ISA version 1.e. The . for example. Addresses are zero-extended to the specified width as needed. .type ld.cs. an integer or bit-size type register reg containing a byte address.type .type d. .lu.param. .cop = { . The value loaded is sign-extended to the destination register width for signed integers. ld introduced in PTX ISA version 1. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.e. . i. perform the load using generic addressing.s8.f32 or . [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. an address maps to global memory unless it falls within the local memory window or the shared memory window. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.f64 }.type ld{.f32. i.u64.v4 }.ss}{. . d. A destination register wider than the specified type may be used.vec.volatile{. Generic addressing may be used with ld.shared }.const.Chapter 8. and truncated if the register width exceeds the state space address width for the target architecture. In generic addressing.volatile. If no state space is given.volatile..ss}. ld. to enforce sequential consistency between threads accessing shared memory.const space suffix may have an optional bank number to indicate constant banks other than bank zero. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.volatile may be used with . . 32-bit).u8.b64.b16.global. . . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. 2010 113 . . The address size may be either 32-bit or 64-bit. [a]. and then converted to . Generic addressing and cache operations introduced in PTX ISA 2. . Description Load register variable d from the location specified by the source address operand a in specified state space. *(immAddr).f16 data may be loaded using ld. [a].cop}. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .b16.local. . ld. *a. .vec = { . This may be used.reg state space. 32-bit). . and is zeroextended to the destination register width for unsigned and bit-size types. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. d.shared spaces to inhibit optimization of references to volatile memory.ss = { . . . . Within these windows.1. ld{. .b8.cv }. [a].ca. the resulting behavior is undefined. or the instruction may fault.b32. Semantics d d d d = = = = a.0. Instruction Set Table 81.ss}{. If an address is not properly aligned. .u32. an address maps to the corresponding location in local or shared memory.u16. . PTX ISA Notes January 24. . .global and . *(a+immOff).type = { . The address must be naturally aligned to a multiple of the access size.

[p+-8]. Generic addressing requires sm_20 or later.b32 ld.global.[p]. // negative offset %r.v4. d.%r. Cache operations require sm_20 or later. // load .f64 requires sm_13 or later.local. ld.b64 ld.b16 cvt. %r.0 Target ISA Notes ld.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. // immediate address %r.b32 ld.f32.f32 ld.b32 ld.PTX ISA Version 2.[p+4]. 2010 .global.const[4].[a].shared.local.f16 d.[240].[fs]. x. Q. // access incomplete array x.s32 ld.const.[buffer+64].

[p+4]. [areg] a register reg containing a byte address. and truncated if the register width exceeds the state space address width for the target architecture. only generic addresses that map to global memory are legal.s16.f64 using cvt.Chapter 8. 2010 115 . Within these windows.vec = { . For ldu. ldu{.f32 d. the access may proceed by silently masking off low-order address bits to achieve proper rounding. 32-bit). *(a+immOff). If no state space is given. .u16.global. [a].global. A destination register wider than the specified type may be used.ss = { .. *(immAddr). ldu.ss}. perform the load using generic addressing. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.b64. // load from address // vec load from address .v2.f64 }.[a]. or [immAddr] an immediate absolute byte address (unsigned.f32 or .b16. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. The data at the specified address must be read-only.type = { . .f32. or the instruction may fault.global }.type ldu{.b32 d. and then converted to . the resulting behavior is undefined.global. .f16 data may be loaded using ldu. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .type d. .s8.b32.b8. i. The address must be naturally aligned to a multiple of the access size.reg state space. where the address is guaranteed to be the same across all threads in the warp.u64. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 2. 32-bit).u32. ldu. an address maps to global memory unless it falls within the local memory window or the shared memory window.f64 requires sm_13 or later. [a]. .f32 Q.s32. The value loaded is sign-extended to the destination register width for signed integers.v4 }.s64.[p]. d. . Semantics d d d d = = = = a.e. .v4. Instruction Set Table 82. The addressable operand a is one of: [avar] the name of an addressable variable var.u8. If an address is not properly aligned. . A register containing an address may be declared as a bit-size type or integer type. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b16. . . . ldu. i. Addresses are zero-extended to the specified width as needed. The address size may be either 32-bit or 64-bit.e.vec. . . .ss}. In generic addressing. *a. and is zeroextended to the destination register width for unsigned and bit-size types. ldu. an address maps to the corresponding location in local or shared memory. . . // state space .0.

32-bit). b. { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. .s64. *(d+immOffset) = a. an integer or bit-size type register reg containing a byte address.b32.vec . The address must be naturally aligned to a multiple of the access size.ss}. .local.volatile{. st{. PTX ISA Notes Target ISA Notes 116 January 24. . . perform the store using generic addressing. an address maps to the corresponding location in local or shared memory.v4 }.e. Generic addressing requires sm_20 or later. 32-bit).s16. Semantics d = a.type [a].ss}{. .u8. The address size may be either 32-bit or 64-bit. st. .volatile introduced in PTX ISA version 1.vec. .f16 data resulting from a cvt instruction may be stored using st. . Generic addressing and cache operations introduced in PTX ISA 2. st.PTX ISA Version 2. In generic addressing.s8. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. st introduced in PTX ISA version 1.global and .u16. *d = a.volatile may be used with .ss .cg.type st.f64 requires sm_13 or later. .cop}.wt }. to enforce sequential consistency between threads accessing shared memory..e. { .f32.volatile{. .vec. [a]. b.1. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .cop}.u32. Generic addressing may be used with st. Cache operations require sm_20 or later.b16. A source register wider than the specified type may be used.0. i.reg state space.cop .ss}{. . an address maps to global memory unless it falls within the local memory window or the shared memory window.b16. . This may be used. . The addressable operand a is one of: [var] [reg] the name of an addressable variable var. 2010 . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. *(immAddr) = a.s32. If no state space is given. . { . The lower n bits corresponding to the instruction-type width are stored to memory. b.shared }.wb.global.u64. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.cs. and truncated if the register width exceeds the state space address width for the target architecture. .volatile. b.b8.type st{.type = = = = {.b64. st. .0 Table 83. [a]. . If an address is not properly aligned. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or [immAddr] an immediate absolute byte address (unsigned.type .volatile. or the instruction may fault. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.ss}. Addresses are zero-extended to the specified width as needed.f64 }. Within these windows. [a]. for example. .v2. the resulting behavior is undefined. .shared spaces to inhibit optimization of references to volatile memory. i.0. Cache operations are not permitted with st. .

local. // immediate address %r.%r.local.b32 st.Q.r7.f32 st. Instruction Set Examples st.b32 st. [p].b. [fs].local. 2010 117 .a.f16. [q+4].v4.f32 st.global.b16 [a].Chapter 8. // negative offset [100].a. // %r is 32-bit register // store lower 16 bits January 24.s32 st. [q+-8].%r.s32 cvt.global.

32-bit). // prefetch to data cache // prefetch to uniform cache . an address maps to the corresponding location in local or shared memory. If no state space is given. in specified state space. .space}. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. A prefetch into the uniform cache requires a generic address. [a].0.local }. prefetch and prefetchu require sm_20 or later.global.L1 [ptr]. .PTX ISA Version 2.0 Table 84. prefetch. The address size may be either 32-bit or 64-bit.global. and no operation occurs if the address maps to a local or shared memory location.L1 [addr]. 118 January 24. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. . a register reg containing a byte address.e. prefetch{. i. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. the prefetch uses generic addressing. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. an address maps to global memory unless it falls within the local memory window or the shared memory window. Within these windows. prefetchu. A prefetch to a shared memory location performs no operation. Addresses are zero-extended to the specified width as needed.space = { .L1.L2 }. and truncated if the register width exceeds the state space address width for the target architecture. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.level prefetchu. 32-bit). or [immAddr] an immediate absolute byte address (unsigned.level = { . In generic addressing.L1 [a]. 2010 .

u32.u32 gptr. .global.size = { .local.space = { . sptr. local.u64. PTX ISA Notes Target ISA Notes Examples Table 86.u64 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. When converting a generic address into a global. 2010 119 . . p. or shared state space to generic. or shared address. The source and destination addresses must be the same size. lptr. isspacep requires sm_20 or later. a.local. .global.0.u64.size cvta. or vice-versa. local. // convert to generic address // get generic address of var // convert generic address to global. isspacep. Instruction Set Table 85. or vice-versa.lptr. . a.pred . or shared address to a generic address.u64 or cvt.shared isglbl.shared }. For variables declared in global.local isspacep.Chapter 8.genptr. Use cvt. .global.space. Introduced in PTX ISA version 2. Take the generic address of a variable declared in global. gptr. cvta requires sm_20 or later. var. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. The destination register must be of type . or shared state space.to. a.u32 p. cvta. January 24.u32 to truncate or zero-extend addresses. isspacep. p. cvta. cvta.pred. local. // result is .global isspacep.size p. or shared address cvta.shared.space p.u32 or . svar. local.space.shared }. The source address operand must be a register of type . . or shared state space.space. // local. the generic address of the variable may be taken using cvta. local. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. islcl.to. isshrd. // get generic address of svar cvta. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. A program may use isspacep to guard against such incorrect behavior. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.local.u32 p.size .u32. Description Convert a global.space = { .

irnd}{.MAXINT for the size of the operation. Saturation modifier: .ftz}{.rzi. cvt{. .ftz.s16.frnd}{.rmi. i. .dtype.s8.f32.atype d.s32.PTX ISA Version 2.f32. sm_1x: For cvt..atype = { .f16. 2010 .sat}. Integer rounding is illegal in all other instances.f64 }.rmi round to nearest integer in direction of negative infinity .rni round to nearest integer. and for same-size float-tofloat conversions where the value is rounded to an integer. .rp }. .atype cvt{. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32 float-to-integer conversions and cvt.ftz modifier may be specified in these cases for clarity.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.dtype = .rn.ftz}{.s64.sat For integer destination types.f32 float-tofloat conversions with integer rounding. Note: In PTX ISA versions 1.f32 float-tofloat conversions with integer rounding. . .sat limits the result to MININT. ..f32 float-to-integer conversions and cvt. Integer rounding is required for float-to-integer conversions. The compiler will preserve this behavior for legacy PTX code.f32.rzi round to nearest integer in the direction of zero .irnd = { . Note that saturation applies to both signed and unsigned integer types. .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.rm.u16. the . .u64.rpi }.rz. .ftz. d.u8. . Description Semantics Integer Notes Convert between different types and sizes.u32. choosing even integer if source is equidistant between two integers.sat}.ftz. For cvt. . .e. Integer rounding modifiers: . . . the result is clamped to the destination range by default. a.e.dtype. i. The optional .dtype. . a. . . subnormal inputs are flushed to signpreserving zero. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. subnormal inputs are flushed to signpreserving zero.dtype.4 and earlier. 120 January 24.ftz.frnd = { . subnormal numbers are supported. . // integer rounding // fp rounding .sat is redundant. For float-to-integer conversions. . .0 Table 87.rni. d = convert(a).

single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.ftz modifier may be specified in these cases for clarity.f32 x. // note .f32 instructions.f32. Note: In PTX ISA versions 1.sat limits the result to the range [0. if the PTX .s32. subnormal numbers are supported.4 and earlier. and .y.f32 x.f64 types. The optional . Subnormal numbers: sm_20: By default. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. stored in floating-point format. Specifically.version is 1. . The compiler will preserve this behavior for legacy PTX code.rni.f16.ftz behavior for sm_1x targets January 24.f16.y. Modifier .f32. cvt.f32.f64 requires sm_13 or later.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). .0.0.rn mantissa LSB rounds to nearest even . 1.rz mantissa LSB rounds towards zero . result is fp cvt.f64. cvt.r. cvt to or from . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. and for integer-to-float conversions.f32.f64 j.f32. cvt. Floating-point rounding modifiers: . and cvt. // float-to-int saturates by default cvt.f32. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . // round to nearest int. Floating-point rounding is illegal in all other instances.i. NaN results are flushed to positive zero. The operands must be of the same size.s32 f.rm mantissa LSB rounds towards negative infinity .f32. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f16. Introduced in PTX ISA version 1.sat For floating-point destination types.Chapter 8. 2010 121 .0]. Applies to .4 or earlier.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. The result is an integral value. Saturation modifier: .

samplers. {f1.f32. and surface descriptors: • • • Static initialization of texture.. r1. texture and sampler information each have their own handle. sampler. add. r4. Texture and Surface Instructions This section describes PTX instructions for accessing textures.entry compute_power ( .u32 r5. and surface descriptors.v4.target texmode_independent . r5.. allowing them to be defined separately and combined at the site of usage in the program. A PTX module may declare only one texturing mode. and surface descriptors.f2}]. In the independent mode.r2.b32 r5. In the unified mode.f32 r1. . . // get tex1’s tex.PTX ISA Version 2. and surfaces. .target options ‘texmode_unified’ and ‘texmode_independent’. r6. [tex1].6. The texturing mode is selected using . r1. 122 January 24. div.texref tex1 ) { txq.global . Ability to query fields within texture. The advantage of unified mode is that it allows 128 samplers. r1. add. sampler. Example: calculate an element’s power contribution as element’s power/total number of elements.2d.param . Module-scope and per-entry scope definitions of texture. sampler. [tex1.f32 r1.u32 r5. r5. r2. r3.0 8.f32 r3. } = clamp_to_border. with the restriction that they correspond 1-to-1 with the 128 possible textures.7.f32 {r1. 2010 .r4}. The advantage of independent mode is that textures and samplers can be mixed and matched. PTX has two modes of operation. If no texturing mode is declared. but the number of samplers is greatly restricted to 16. r5. PTX supports the following operations on texture. add. sampler. = nearest width height tsamp1.height. and surface descriptors. [tex1].f32. the file is assumed to use unified mode.samplerref tsamp1 = { addr_mode_0 filter_mode }.b32 r6.texref handle.width. mul. cvt. texture and sampler information is accessed through a single .f32 r1. // get tex1’s txq. r3.r3. Texturing modes For working with textures and samplers.

An optional texture sampler b may be specified. where the fourth element is ignored.5.2d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. {f1. tex.r2. tex txq suld sust sured suq Table 88. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a. .f4}]. If an address is not properly aligned. is a two-element vector for 2d textures. d.f2.s32. // Example of independent mode texturing tex.1d. Unified mode texturing introduced in PTX ISA version 1.geom = { .geom. The instruction always returns a four-element vector of 32-bit values.f32 }. b. Notes For compatibility with prior versions of PTX.r4}. with the extra elements being ignored.v4 coordinate vectors are allowed for any geometry. .dtype = { . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. [tex_a.f32 {r1. .btype tex.f3. i. c]. [tex_a.e. c]. [a. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. . Supported on all target architectures. 2010 123 .r3.dtype. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. // explicit sampler . the square brackets are not required and . and is a four-element vector for 3d textures.s32.r3. Instruction Set These instructions provide access to texture and surface memory. . PTX ISA Notes Target ISA Notes Examples January 24. A texture base address is assumed to be aligned to a 16-byte address.3d. //Example of unified mode texturing tex. .r4}.v4.v4. .v4.3d }. the sampler behavior is a property of the named texture.1d.s32 {r1.s32.Chapter 8.s32. the resulting behavior is undefined.u32.f32 }.btype d.geom.btype = { . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. If no sampler is specified.dtype. sampler_x. Description Texture lookup using a texture coordinate vector.0..r2. Operand c is a scalar or singleton tuple for 1d textures. or the instruction may fault.v4. {f1}].

b32 %r1.squery = { .width . clamp_to_edge. txq. addr_mode_2 }. and in independent mode sampler attributes are accessed via a separate samplerref argument. txq.filter_mode. mirror.0 Table 89. d.addr_mode_1 .b32 txq. linear } Integer from enum { wrap. addr_mode_1. // unified mode // independent mode 124 January 24. [tex_A].width.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [smpl_B].filter_mode .PTX ISA Version 2.texref or . Supported on all target architectures.addr_mode_0.height . Operand a is a .5. Description Query an attribute of a texture or sampler.filter_mode.depth . txq.b32 %r1. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // texture attributes // sampler attributes . [a]. txq.normalized_coords }. 2010 .squery. . In unified mode.b32 d. Integer from enum { nearest. . .height.tquery. Query: .b32 %r1. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.addr_mode_0 .depth.tquery = { .addr_mode_0.samplerref variable. .normalized_coords . . clamp_ogl. [tex_A]. sampler attributes are also accessed via a texref argument.width. [a].

u32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.clamp .trap.dtype .dtype. and cache operations introduced in PTX ISA version 2. . suld. or . The . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. . suld Syntax Texture and Surface Instructions: suld Load from surface memory.cop . and is a four-element vector for 3d surfaces. [a.zero }. The lowest dimension coordinate represents a sample offset rather than a byte offset.p .p. {x}]. .v2. Instruction Set Table 90. .2d. .clamp .e.f3. and A components of the surface format. the resulting behavior is undefined.v4 }. or .b16.f2. . is a two-element vector for 2d surfaces. or the instruction may fault.geom{. 2010 125 .u32 is returned.cop}. Coordinate elements are of type . . // unformatted d.geom .b.v4.b32. the surface sample elements are converted to . suld. If the destination base type is . i.ca. b].r2}.1d.v2.dtype. additional clamp modifiers.b64 }.clamp. b]. suld. // for suld.s32 is returned. // for suld. {f1. suld.b .vec . . then .f32 is returned. where the fourth element is ignored.b64..s32. . if the surface format contains UINT data. .s32. suld. . [surf_B. .s32.trap .3d requires sm_20 or later.cop}. suld. . {x.z. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32.f4}. If an address is not properly aligned. Target ISA Notes Examples January 24. Operand b is a scalar or singleton tuple for 1d surfaces.3d. then .b8 . [a. then . suld.v4. [surf_A.s32. Operand a is a . .b32.p.cg. Cache operations require sm_20 or later.u32. and the size of the data transfer matches the size of destination operand d. // cache operation none.vec.clamp = = = = = = { { { { { { d.cv }. suld.trap clamping modifier.w}]. B.surfref variable.y.cs. sm_1x targets support only the .u32. or FLOAT data.p requires sm_20 or later. size and type conversion is performed as needed to convert from the surface sample format to the destination type. If the destination type is . .clamp field specifies how to handle out-of-bounds addresses: .trap suld.f32 based on the surface format as follows: If the surface format contains UNORM.dtype .p.trap introduced in PTX ISA version 1. G.b performs an unformatted load of binary data.0. SNORM.b supported on all target architectures. .p is currently unimplemented. .b.clamp suld.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. Destination vector elements corresponding to components that do not appear in the surface format are not written.1d.f32.3d }. if the surface format contains SINT data.f32. . suld.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.b. . // formatted .5. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap {r1. A surface base address is assumed to be aligned to a 16-byte address.geom{.f32 }. Description Load from surface memory using a surface coordinate vector.Chapter 8.

2d.wb.geom{.s32.{u32. // unformatted // formatted .wt }. The lowest dimension coordinate represents a sample offset rather than a byte offset. sust Syntax Texture and Surface Instructions: sust Store to surface memory. .3d. [a. . or the instruction may fault. sust.vec. and A surface components.w}].clamp = = = = = = { { { { { { [a.p.f3. . .clamp . the resulting behavior is undefined. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.clamp .b // for sust. . and cache operations introduced in PTX ISA version 2.s32 is assumed.3d requires sm_20 or later.trap. .ctype . [surf_B.trap clamping modifier. Surface sample components that do not occur in the source vector will be written with an unpredictable value.0 Table 91.cop . If the source type is . If an address is not properly aligned. . .clamp field specifies how to handle out-of-bounds addresses: . Operand a is a . or . sust. {x}]. Cache operations require sm_20 or later. c. the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom .b.b. sm_1x targets support only the . c. Coordinate elements are of type . . G. is a two-element vector for 2d surfaces.s32. .cop}. .p. sust.vec.zero }. The source vector elements are interpreted left-to-right as R.5.b performs an unformatted store of binary data.y.u32. .ctype.3d }.geom{..s32. .PTX ISA Version 2.f32 }.b32. sust.p requires sm_20 or later.f32.v4 }. . .f32 is assumed. Operand b is a scalar or singleton tuple for 1d surfaces. .ctype .cop}. {f1. then .b8 .b supported on all target architectures.u32 is assumed.trap sust. The source data is then converted from this type to the surface sample format. A surface base address is assumed to be aligned to a 16-byte address. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. .z. size and type conversions are performed as needed between the surface sample format and the destination type.clamp. sust.trap [surf_A. B.p performs a formatted store of a vector of 32-bit data values to a surface sample.e. .trap introduced in PTX ISA version 1. {x. If the source base type is .u32.f2.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.b32.p Description Store to surface memory using a surface coordinate vector.b32. then . These elements are written to the corresponding surface sample components.p.r2}.clamp sust. none. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. {r1. if the surface format contains UINT data.b16.v2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. sust. 2010 .b. sust.cg. or FLOAT data. if the surface format contains SINT data. SNORM.v2.f32.p. additional clamp modifiers.b64. then . .v4. // for sust. sust.1d. Target ISA Notes Examples 126 January 24.1d. i.cs.vec .s32. and is a four-element vector for 3d surfaces.b64 }. where the fourth element is ignored. sust. The size of the data transfer matches the size of source operand c.f32} are currently unimplemented. . The .ctype. Source elements that do not occur in the surface sample are ignored.f4}. b].trap .0. b].surfref variable.

then . operations and and or apply to . If an address is not properly aligned.op. min and max apply to .s32.add.op. . {x. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.geom = { . and is a four-element vector for 3d surfaces. i.c.ctype = { . then . sured.b. The .u32. Reduction to surface memory using a surface coordinate vector. Operand a is a .u64. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. .b32 }.y}].u32.max.s32 is assumed. .b performs an unformatted reduction on .clamp. .0.p.u32.s32 types. the resulting behavior is undefined.u32 and . . The instruction type is restricted to .p .ctype = { .min.u32.u32 based on the surface sample format as follows: if the surface format contains UINT data. sured requires sm_20 or later.b .clamp field specifies how to handle out-of-bounds addresses: . is a two-element vector for 2d surfaces.b32 }.u32 is assumed..s32 types.p performs a reduction on sample-addressed 32-bit data. . sured. . r1. .e. A surface base address is assumed to be aligned to a 16-byte address.surfref variable. Operations add applies to . The lowest dimension coordinate represents a sample offset rather than a byte offset. // sample addressing .Chapter 8. January 24. sured. // for sured. Instruction Set Table 92.clamp . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Operand b is a scalar or singleton tuple for 1d surfaces. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. where the fourth element is ignored. and the data is interpreted as . 2010 127 .or }.add. or . // for sured.trap sured.b32.zero }.u64.trap.trap [surf_A.s32.b.and.1d. .trap .clamp = { .op = { . // byte addressing sured.b32. and .2d.clamp [a. if the surface format contains SINT data.geom.b]. . .min.b].ctype. . . r1.c. Coordinate elements are of type .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. sured.s32. .ctype.1d. .2d. [surf_B. . {x}]. or the instruction may fault.geom.u64 data.s32 or . the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32.3d }.b32 type.clamp [a.p.

128 January 24.PTX ISA Version 2.query = { .surfref variable.b32 %r1. [surf_A].width .5. . Query: .depth }. Operand a is a . .width. 2010 . Description Query an attribute of a surface.height .width.height.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq.0 Table 93. . suq. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.b32 d. Supported on all target architectures.query. [a].

c. p.x.f32 @!p div. 2010 129 .y.0. ratio. { instructionList } The curly braces create a group of instructions.0.7. {} Syntax Description Control Flow Instructions: { } Instruction grouping. } PTX ISA Notes Target ISA Notes Examples Table 95.7.eq. setp.f32 @q bra L23. mov. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. Threads with a false guard predicate do nothing. Supported on all target architectures. If {!}p then instruction Introduced in PTX ISA version 1.s32 a. Execute an instruction or instruction block for threads that have the guard predicate true. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.s32 d. Instruction Set 8.a. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.b. Introduced in PTX ISA version 1. used primarily for defining a function body.0. @{!}p instruction.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. { add.Chapter 8. Supported on all target architectures.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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u32 bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).u32. all threads in the CTA participate in the barrier. and d have type . {!}c. Once the barrier count is reached. operands p and c are predicates. Instruction Set Table 100.or }.red delays the executing threads (similar to bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.Chapter 8. 2010 133 . When a barrier completes. it is as if all the threads in the warp have executed the bar instruction.version 2. and bar.sync) until the barrier count is met.sync and bar.red should not be intermixed with bar.sync and bar.or). and the barrier is reinitialized so that it can be immediately reused. The reduction operations for bar. thread count. bar. the waiting threads are restarted without delay. bar. Since barriers are executed on a per-warp basis. a.popc.sync without a thread count introduced in PTX ISA 1.op = { . Barriers are executed on a per-warp basis as if all the threads in a warp are active. Register operands. p. If no thread count is specified. Operands a.and. In addition to signaling its arrival at the barrier.red also guarantee memory ordering among threads identical to membar.arrive a{. In conditionally executed code.sync bar. bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. and then safely read values stored by other threads prior to the barrier. Thus. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.and and . and any-thread-true (. . while . Operand b specifies the number of threads participating in the barrier. Description Performs barrier synchronization and communication within a CTA. thread count. a{. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). bar.red} require sm_20 or later.sync with an immediate barrier number is supported for sm_1x targets.sync or bar. a{.sync or bar.{arrive.arrive. bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.popc). b. b}. The result of . the final value is written to the destination register in all threads waiting at the barrier. b. all-threads-true (.red performs a predicate reduction across the threads participating in the barrier. execute a bar. the optional thread count must be a multiple of the warp size.and). January 24. Each CTA instance has sixteen barriers numbered 0. Register operands.red. b}.red are population-count (. bar.red.15.popc is the number of threads with a true predicate.red performs a reduction operation across threads. bar. The barrier instructions signal the arrival of the executing threads at the named barrier.pred .0. bar. the bar..arrive using the same active barrier. Thus. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. All threads in the warp are stalled until the barrier completes. b}. {!}c. if any thread in a warp executes a bar instruction. Note that a non-zero thread count is required for bar. Only bar. PTX ISA Notes Target ISA Notes Examples bar.red instruction.0. threads within a CTA that wish to communicate via memory can store to memory.arrive does not cause any waiting by the executing threads.sync 0.{arrive. and bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. bar.op. Execution in this case is unpredictable. d.cta.red} introduced in PTX . it simply marks a thread's arrival at the barrier.

membar. 2010 . Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.sys }.PTX ISA Version 2. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys Waits until all prior memory requests have been performed with respect to all clients.0. membar.gl.cta. membar. membar. by st.level. when the previous value can no longer be read. this is the appropriate level of membar.gl.0 Table 101. PTX ISA Notes Target ISA Notes Examples membar.cta. membar. For communication between threads in different CTAs or even different SMs.version 1. level describes the scope of other clients for which membar is an ordering event. membar. membar.sys.gl} introduced in PTX .sys will typically have much longer latency than membar. membar. global.cta Waits until all prior memory writes are visible to other threads in the same CTA. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. or system memory level.level = { . membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. including thoses communicating via PCI-E such as system and peer-to-peer memory.g.gl will typically have a longer latency than membar. . 134 January 24.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. . membar.cta. and memory reads by this thread can no longer be affected by other thread writes.g.version 2. .{cta.sys requires sm_20 or later.4.gl} supported on all target architectures. that is.{cta.sys introduced in PTX . membar. A memory read (e. membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. red or atom) has been performed when the value written has become visible to other clients at the specified level. A memory write (e.gl.

If an address is not properly aligned. The address must be naturally aligned to a multiple of the access size.b]. Operand a specifies a location in the specified state space.xor. .min. . performs a reduction operation with operand b and the value in location a. a de-referenced register areg containing a byte address.op. . by inserting barriers between normal stores and atomic operations to a common address.type = { .space}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b64 .b32 only . Addresses are zero-extended to the specified width as needed. atom{. an address maps to global memory unless it falls within the local memory window or the shared memory window.dec.or.Chapter 8.op = { . and stores the result of the specified operation at location a. min. min.space = { . The integer operations are add. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.inc.space}. The bit-size operations are and. and truncated if the register width exceeds the state space address width for the target architecture.u32. . January 24.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and max operations are single-precision. . .add. max.exch to store to locations accessed by other atomic operations. The floating-point add.f32 Atomically loads the original value at location a into destination register d. . ..cas. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. or by using atom. or. b. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . Within these windows. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. The address size may be either 32-bit or 64-bit. perform the memory accesses using generic addressing.u64 . an address maps to the corresponding location in local or shared memory. dec. the resulting behavior is undefined. In generic addressing. . .type atom{. . .type d. e. xor. overwriting the original value. 32-bit operations. or the instruction may fault. . .b32.f32.s32. . .s32.max }. For atom.u32. [a].u32.f32 }. 2010 135 .and. The floating-point operations are add.shared }. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.u32 only . The inc and dec operations return a result in the range [0. .add. and max.op.global. min. i. A register containing an address may be declared as a bit-size type or integer type.e. Description // // // // // . If no state space is given. .u64. Instruction Set Table 102. cas (compare-and-swap). b. and exch (exchange).b32. atom. .exch.s32.. d. c. or [immAddr] an immediate absolute byte address. [a].e. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. accesses to local memory are illegal. . i. inc.b64.g.

[x+4]. 2010 . Introduced in PTX ISA version 1.0. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.{min. s) = s. cas(r.my_val.cas. atom.global requires sm_11 or later. s) = (r > s) ? s exch(r.s32 atom.1.shared requires sm_12 or later. : r. 64-bit atom. s) = (r >= s) ? 0 dec(r.[p]. atom. 64-bit atom.0.add. Release Notes Examples @p 136 January 24. d.b32 d. : r-1.t) = (r == s) ? t operation(*a. atom.my_new_val.shared. atom.shared operations require sm_20 or later.max} are unimplemented. b. c) operation(*a.[a].global. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.cas.{add.s.max. *a = (operation == cas) ? : } where inc(r. b). d.PTX ISA Version 2. Use of generic addressing requires sm_20 or later.exch} requires sm_12 or later.add.f32 atom.global. atom.f32 requires sm_20 or later. : r+1.f32.0 Semantics atomic { d = *a.

min. .max }.e. The integer operations are add. Within these windows. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f32 Performs a reduction operation with operand b and the value in location a. . .b64. .b32 only . e.inc.b32. i. b. The address size may be either 32-bit or 64-bit. and truncated if the register width exceeds the state space address width for the target architecture. overwriting the original value. January 24.e. the access may proceed by silently masking off low-order address bits to achieve proper rounding.global. Semantics *a = operation(*a. The floating-point operations are add. . .xor. 2010 137 .. The floating-point add. and stores the result of the specified operation at location a. or by using atom. 32-bit operations.space = { . The bit-size operations are and.u32 only . . . A register containing an address may be declared as a bit-size type or integer type. accesses to local memory are illegal. If no state space is given. . The inc and dec operations return a result in the range [0. dec(r. red{.op. dec.s32. the resulting behavior is undefined. where inc(r. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset..f32.b].f32 }. .shared }. min. an address maps to global memory unless it falls within the local memory window or the shared memory window. In generic addressing.exch to store to locations accessed by other reduction operations. and max operations are single-precision.u64. b). Notes Operand a must reside in either the global or shared state space. . .s32. min. . . . min.type [a]. and max. and xor. i.op = { . max.g. .u32.s32. or the instruction may fault. by inserting barriers between normal stores and reduction operations to a common address.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.dec.add. Instruction Set Table 103. or [immAddr] an immediate absolute byte address. For red. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. red. The address must be naturally aligned to a multiple of the access size. .add. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. s) = (r >= s) ? 0 : r+1.Chapter 8. Addresses are zero-extended to the specified width as needed.type = { . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. or.and.space}.or. . s) = (r > s) ? s : r-1. If an address is not properly aligned. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. . . perform the memory accesses using generic addressing. an address maps to the corresponding location in local or shared memory.u64 .u32. Operand a specifies a location in the specified state space. Description // // // // . inc. a de-referenced register areg containing a byte address.u32.

red. Use of generic addressing requires sm_20 or later. [p].my_val.f32 red.and. 64-bit red.f32.PTX ISA Version 2. 2010 .global.global.add.max} are unimplemented.shared.f32 requires sm_20 or later. 64-bit red.add.shared operations require sm_20 or later. red.max.shared requires sm_12 or later.0. red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. red.global requires sm_11 or later red.b32 [a].s32 red. [x+4].1.add requires sm_12 or later.2. Release Notes Examples @p 138 January 24.{min.

uni. returns bitmask .2.b32 requires sm_20 or later. vote requires sm_12 or later.all. p. not across an entire CTA.ballot.b32 d. vote.ballot.p. .q.pred vote.pred vote.uni }. Negate the source predicate to compute . Negating the source predicate also computes . In the ‘ballot’ form.ballot. Note that vote applies to threads in a single warp. 2010 139 . vote.uni. The reduction modes are: .all.any. // get ‘ballot’ across warp January 24.all True if source predicate is True for all active threads in warp. r1. . Description Performs a reduction of the source predicate across threads in a warp. .pred d. {!}a.uni True if source predicate has the same value in all active threads in warp.not_all.Chapter 8. {!}a.b32 p. vote. where the bit position corresponds to the thread’s lane id.any True if source predicate is True for some active thread in warp. Instruction Set Table 104. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. // ‘ballot’ form. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.none. vote.mode = { .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.mode.ballot. The destination predicate value is the same across all threads in the warp. . vote. Negate the source predicate to compute .q.

vop. 3.b2.btype{.bsel = { .asel = .atype = . The type of each operand (.atype. all combinations of dtype. .asel}. .u32 or .0 8.min. c. the input values are extracted and signor zero.bsel}.extended internally to .or zero-extend byte.bsel}. . perform a scalar arithmetic operation to produce a signed 34-bit result. Video Instructions All video instructions operate on 32-bit register operands. .h0.s33 values.9.asel}.PTX ISA Version 2.btype{.sat} d. 4.add. b{. a{.s34 intermediate result. c. a{.s32 }.asel}. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. taking into account the subword destination size in the case of optional data merging. 2010 .secop d. 140 January 24. b{. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. Using the atype/btype and asel/bsel specifiers. . 2.dtype = . extract and sign.btype = { . with optional secondary operation vop.u32. . . .max }.sat} d.secop = { .bsel}. The sign of the intermediate result depends on dtype.atype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. . a{.b3. optionally clamp the result to the range of the destination type. The source and destination operands are all 32-bit registers.atype. .b0. The general format of video instructions is as follows: // 32-bit scalar operation. and btype are valid. with optional data merge vop. to produce signed 33-bit input values.sat}. b{. // 32-bit scalar operation.s32) is specified in the instruction type.b1. The primary operation is then performed to produce an .btype{.h1 }.dtype. or word values from its source operands. half-word.dsel = .dsel.dtype.7. . atype.dtype.

b2. as shown in the following pseudocode.max return MAX(tmp. . Instruction Set . S32_MAX. c). U32_MIN ). } } . U16_MAX. . c). .h0. c). . U8_MAX.h0: return ((tmp & 0xffff) case . Modifier dsel ) { if ( !sat ) return tmp.b1.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.s33 tmp. U8_MIN ). U16_MIN ). January 24. S32_MIN ). c).b0.s33 optSecOp(Modifier secop. c). tmp.add: return tmp + c.b1: return ((tmp & 0xff) << 8) case . .min: return MIN(tmp.s33 optMerge( Modifier dsel. . tmp. 2010 141 . The sign of the c operand is based on dtype. S8_MIN ). . Bool sat. S16_MAX. c).b3: return ((tmp & 0xff) << 24) default: return tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).b3: if ( sign ) return CLAMP( else return CLAMP( case . S8_MAX. tmp. tmp.s33 tmp.s33 c) { switch ( secop ) { .Chapter 8. default: return tmp. U32_MAX. S16_MIN ). .s33 c ) switch ( dsel ) { case . .b0: return ((tmp & 0xff) case . Bool sign. .s33 optSaturate( . tmp.b2: return ((tmp & 0xff) << 16) case .s34 tmp. . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.h1: return ((tmp & 0xffff) << 16) case . c). switch ( dsel ) { case . The lower 32-bits are then written to the destination operand.

s32. tmp.bsel}. r2. vabsdiff.dtype . vabsdiff. 2010 .sat} d.0 Table 105. tmp.asel}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r2. .add r1.0.b1. taking into account destination type and merge operations tmp = optSaturate( tmp.bsel = { . tmp = ta – tb. .b2. . // optional secondary operation d = optMerge( dsel. r3.s32. r1. a{.u32. asel ). atype.s32. vsub.dtype. b{. vmin. r3.bsel}. vmin. tb = partSelectSignExtend( b. Perform scalar arithmetic operation with optional saturate.sat vsub.h0.sat} d. bsel ).h1 }.u32. b{. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.btype = { . vadd. vmax }. . dsel ).asel}. vsub vabsdiff vmin. r1. .op2 d.btype{.PTX ISA Version 2. r2.dtype.dtype.asel = . tmp = MAX( ta.vop . c.or zero-extend based on source operand type ta = partSelectSignExtend( a.b0.min. // optional merge with c operand 142 January 24. . d = optSecondaryOp( op2.op2 Description = = = = { vadd.dsel. vsub.atype. r3.sat vabsdiff.sat vmin. Integer byte/half-word/word minimum / maximum. vmax vadd. Semantics // saturate. vmin. .btype{.bsel}. { . r1. Video Instructions: vadd. a{.s32. . Integer byte/half-word/word absolute value of difference. and optional secondary arithmetic operation or subword data merge.h1.s32. tb ). c ). tb ). sat.b2. c.add.b0. vabsdiff. . vmax require sm_20 or later.h0. btype.s32.u32. vop.sat. . a{.btype{.s32.h0. // 32-bit scalar operation.sat}.atype = .s32. // 32-bit scalar operation.atype. vadd. r2.asel}. // extract byte/half-word/word and sign.h1. with optional secondary operation vop.max }. c.s32 }.atype.b3. vsub. r3. isSigned(dtype). b{. vmax Syntax Integer byte/half-word/word addition / subtraction. tmp = | ta – tb |. tmp = MIN( ta. c. . with optional data merge vop.s32. c ).dsel .s32.b0.

sat. unsigned shift fills with zero. r1. b{.asel = . . 2010 143 . b{.clamp && tb > 32 ) tb = 32. r2.s32 }.h1 }. Semantics // extract byte/half-word/word and sign.asel}.dtype . . vop.sat}{.atype. atype.Chapter 8.vop . . c.s32. r2.dtype.u32{. vshr require sm_20 or later. tb = partSelectSignExtend( b. dsel ). a{.clamp.atype. with optional data merge vop. .sat}{.bsel}. // 32-bit scalar operation.bsel = { . c ). { .b3. .u32 vshr. b{.u32. . c ).atype = { . .u32.asel}. r3. { . tmp. c. . } // saturate. tmp. asel ). // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vshl: Shift a left by unsigned amount in b with optional saturate.u32{. vshl.0.asel}. Video Instructions: vshl.atype. // default is .sat}{. vshr Syntax Integer byte/half-word/word left / right shift.mode}.wrap r1. vshl.op2 Description = = = = = { vshl.bsel}.dsel .dsel. a{.dtype.h0.u32. and optional secondary arithmetic operation or subword data merge. if ( mode == .max }. d = optSecondaryOp( op2. with optional secondary operation vop. // optional secondary operation d = optMerge( dsel. and optional secondary arithmetic operation or subword data merge.b0.min.wrap ) tb = tb & 0x1f. .u32. vshr: Shift a right by unsigned amount in b with optional saturate. r3. .u32.mode} d. case vshr: tmp = ta >> tb. vshr }.b1.h1. // 32-bit scalar operation. Left shift fills with zero. a{.wrap }.bsel}.add.clamp . if ( mode == . vshr vshl.mode .b2. switch ( vop ) { case vshl: tmp = ta << tb. .u32{.op2 d.or zero-extend based on source operand type ta = partSelectSignExtend( a. . bsel ). Signed shift fills with the sign bit. taking into account destination type and merge operations tmp = optSaturate( tmp.dtype.mode} d. Instruction Set Table 106. isSigned(dtype). January 24.u32.

.asel}.sat}{. . .po mode.atype = . .PTX ISA Version 2. “plus one” mode.btype = { .scale} d.0 Table 107. . .po{. and scaling.b1. otherwise. final unsigned -(U32 * U32) + S32 // intermediate signed. PTX allows negation of either (a*b) or c.asel}. which is used in computing averages.shr7. . vmad.b3. and the operand negates. Description Calculate (a*b) + c.S32 // intermediate signed.dtype. Source operands may not be negated in . 144 January 24. . The source operands support optional negation with some restrictions. {-}b{. final signed (S32 * S32) .sat}{.shr15 }.U32 // intermediate unsigned. with optional operand negates. final signed (S32 * S32) + S32 // intermediate signed.s32 }. final signed (U32 * U32) . . 2010 . Depending on the sign of the a and b operands. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.u32.S32 // intermediate signed. // 32-bit scalar operation vmad.atype. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. {-}c. this result is sign-extended if the final result is signed. . final signed -(U32 * S32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift.asel = .atype.po) computes (a*b) + c + 1.h1 }.dtype = . c. final signed (U32 * S32) . The “plus one” mode (. The final result is unsigned if the intermediate result is unsigned and c is not negated. Although PTX syntax allows separate negation of the a and b operands. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (U32 * S32) + S32 // intermediate signed. {-}a{. the intermediate result is signed. final signed -(S32 * U32) + S32 // intermediate signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. (a*b) is negated if and only if exactly one of a or b is negated. internally this is represented as negation of the product (a*b). Input c has the same sign as the intermediate result..bsel}.scale} d. final signed (S32 * U32) + S32 // intermediate signed. final signed (S32 * U32) .h0. b{.b2.btype.scale = { . final signed -(S32 * S32) + S32 // intermediate signed.b0.dtype. a{.S32 // intermediate signed. and zero-extended otherwise.btype{. That is.bsel}.bsel = { .

tb = partSelectSignExtend( b.negate ) { tmp = ~tmp. U32_MAX. r2. lsb = 1.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a.shr15 r0. } else if ( c. } else if ( a. if ( .h0.u32. r0.sat ) { if (signedFinal) result = CLAMP(result. S32_MAX. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 145 . case . signedFinal = isSigned(atype) || isSigned(btype) || (a.Chapter 8.u32. U32_MIN).shr7: result = (tmp >> 7) & 0xffffffffffffffff.po ) { lsb = 1. lsb = 1.u32. btype. vmad. tmp = tmp + c128 + lsb.negate. tmp[127:0] = ta * tb. January 24. switch( scale ) { case .s32. r3. } if ( . r1.0. S32_MIN). asel ).shr15: result = (tmp >> 15) & 0xffffffffffffffff. else result = CLAMP(result. r1. vmad requires sm_20 or later. Instruction Set Semantics // extract byte/half-word/word and sign.sat vmad. bsel ). atype.negate ^ b. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 0. r2.h0.s32.negate ^ b.negate) || c.negate ) { c = ~c. -r3.

r2.lt vset.h0.0 Table 108. . .bsel}.add. vset. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r2.max }. .cmp d. and therefore the c operand and final result are also unsigned.btype. .ge }. d = optSecondaryOp( op2. 2010 .asel = .btype = { .asel}.min. r3.ne r1. . tmp. 146 January 24. .lt. a{. with optional secondary operation vset. vset. tmp = compare( ta.dsel.s32 }. atype.btype.eq.le. b{.bsel}.dsel . asel ). Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. r3.gt. b{. c.op2 Description = = = = . .atype.bsel}.u32. btype. with optional data merge vset. tb = partSelectSignExtend( b.atype.cmp . . vset requires sm_20 or later. with optional secondary arithmetic operation or subword data merge. { . a{. Semantics // extract byte/half-word/word and sign.h1.b2.s32. tmp.atype . . // 32-bit scalar operation.asel}. b{. bsel ). . tb. c ). c.PTX ISA Version 2. .b0.h1 }.bsel = { . cmp ) ? 1 : 0. a{. // 32-bit scalar operation. r1. // optional secondary operation d = optMerge( dsel.cmp d.ne. c ).btype.cmp.u32.asel}. Compare input values using specified comparison. .0. .u32. { .or zero-extend based on source operand type ta = partSelectSignExtend( a.b3. .atype.op2 d. The intermediate result of the comparison is always unsigned.u32.b1.

0. pmevent a. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.Chapter 8. Instruction Set 8. Notes PTX ISA Notes Target ISA Notes Examples Currently. Introduced in PTX ISA version 1. Triggers one of a fixed number of performance monitor events. Supported on all target architectures. brkpt. @p pmevent 1. there are sixteen performance monitor events. trap Abort execution and generate an interrupt to the host CPU. January 24.10. trap. trap. with index specified by immediate operand a. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Table 111. numbered 0 through 15. Table 110. pmevent 7. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Introduced in PTX ISA version 1.0. The relationship between events and counters is programmed via API calls from the host.7. brkpt requires sm_11 or later.4. 2010 147 . brkpt Suspends execution Introduced in PTX ISA version 1. brkpt. Supported on all target architectures. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters.

PTX ISA Version 2.0 148 January 24. 2010 .

which are visible as special registers and accessed through mov or cvt instructions. %lanemask_lt. …. Special Registers PTX includes a number of predefined. %lanemask_le. 2010 149 . %clock64 %pm0. %lanemask_gt %clock. read-only variables. %lanemask_ge. %pm3 January 24.Chapter 9. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq.

2D. or 3D vector to match the CTA shape.u32.u32 %r0. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.%tid.u32 %ntid. %tid. the fourth element is unused and always returns zero.z.x code accessing 16-bit component of %tid mov.%tid.u16 %rh.x to %rh Target ISA Notes Examples // legacy PTX 1. 2010 .%tid.u16 %rh. It is guaranteed that: 0 <= %tid. // legacy PTX 1.x. read-only. per-thread special register initialized with the thread identifier within the CTA.PTX ISA Version 2.u32 %h2. %tid component values range from 0 through %ntid–1 in each CTA dimension. mov.x < %ntid. The %tid special register contains a 1D.y * %ntid.u16 %r2. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.y.0.0. mov.%h2.y < %ntid.y == %ntid. The number of threads in each dimension are specified by the predefined special register %ntid.z. PTX ISA Notes Introduced in PTX ISA version 1.%tid.x 0 <= %tid.%h1.y 0 <= %tid. // compute unified thread id for 2D CTA mov. Redefined as .v4 . mov. %ntid.u32 %ntid. read-only special register initialized with the number of thread ids in each CTA dimension. .x.v4. mad. Redefined as . %tid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.%ntid. CTA dimensions are non-zero.z == 0 in 1D CTAs.y == %tid.u32 type in PTX 2.z. // zero-extend tid.x.x code Target ISA Notes Examples 150 January 24.z == 1 in 2D CTAs. %ntid.u32 %tid.z).z == 0 in 2D CTAs.sreg . The total number of threads in a CTA is (%ntid.v4 .x.0.u32 %tid.%r0.x * %ntid.u32 type in PTX 2.0 Table 112.x.u32 %r0.%tid. mov.x.u32 %h1. // thread id vector // thread id components A predefined. Supported on all target architectures.sreg .y. // CTA shape vector // CTA dimensions A predefined.v4.z < %ntid.sreg . The fourth element is unused and always returns zero.sreg . %tid. the %tid value in unused dimensions is 0. %tid. . .u32 %r1.z == 1 in 1D CTAs. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.%ntid.0. cvt. %ntid. // move tid. Every thread in the CTA has a unique %tid.y. Supported on all target architectures.z PTX ISA Notes Introduced in PTX ISA version 1.z to %r2 Table 113. . %ntid.x.

Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %warpid. mov. Introduced in PTX ISA version 1. 2010 151 . Introduced in PTX ISA version 1.u32 %warpid. A predefined. e.sreg .Chapter 9. Table 115. mov. read-only special register that returns the thread’s warp identifier. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. but its value may change during execution. %laneid.sreg .sreg .u32 %r. read-only special register that returns the maximum number of warp identifiers.u32 %nwarpid. Supported on all target architectures. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. The lane identifier ranges from zero to WARP_SZ-1. The warp identifier will be the same for all threads within a single warp.u32 %r. Note that %warpid is volatile and returns the location of a thread at the moment when read. A predefined. A predefined. . %nwarpid. Special Registers Table 114.g. due to rescheduling of threads following preemption. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. Introduced in PTX ISA version 2. For this reason.3. .u32 %laneid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. .u32 %r. Supported on all target architectures. %nwarpid requires sm_20 or later. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. January 24. read-only special register that returns the thread’s lane within the warp.3.0. mov. PTX ISA Notes Target ISA Notes Examples Table 116.

The %ctaid special register contains a 1D.u16 %r0.x code Target ISA Notes Examples Table 118. .x.0. Redefined as .%nctaid.sreg . mov.z} < 65.536 PTX ISA Notes Introduced in PTX ISA version 1.u32 %nctaid.v4. Supported on all target architectures.0.{x. The fourth element is unused and always returns zero.%nctaid. depending on the shape and rank of the CTA grid.0 Table 117.u32 type in PTX 2.0.%ctaid.v4 . The %nctaid special register contains a 3D grid shape vector.x code Target ISA Notes Examples 152 January 24. %ctaid. Redefined as .u32 %ctaid.x < %nctaid. .u32 %nctaid .0.%nctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.y.u16 %r0. 2D. with each element having a value of at least 1.z.sreg .y. %ctaid.PTX ISA Version 2.z < %nctaid.y 0 <= %ctaid.y < %nctaid. read-only special register initialized with the number of CTAs in each grid dimension.u32 mov.sreg . // legacy PTX 1. The fourth element is unused and always returns zero. // CTA id vector // CTA id components A predefined.y. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.sreg .v4. Each vector element value is >= 0 and < 65535.x. // Grid shape vector // Grid dimensions A predefined. %rh. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. It is guaranteed that: 1 <= %nctaid. .%nctaid. 2010 .z.x. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. %rh. Supported on all target architectures.x 0 <= %ctaid.x. read-only special register initialized with the CTA identifier within the CTA grid.%ctaid.u32 mov.u32 type in PTX 2. // legacy PTX 1.z PTX ISA Notes Introduced in PTX ISA version 1. or 3D vector. It is guaranteed that: 0 <= %ctaid.x. mov.v4 .y.u32 %ctaid.

%nsmid requires sm_20 or later.sreg . Introduced in PTX ISA version 2.u32 %r. e. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. This variable provides the temporal grid launch number for this context.g. The SM identifier ranges from 0 to %nsmid-1. repeated launches of programs may occur. read-only special register that returns the maximum number of SM identifiers. The SM identifier numbering is not guaranteed to be contiguous. The SM identifier numbering is not guaranteed to be contiguous. mov.u32 %nsmid.sreg . due to rescheduling of threads following preemption.3.Chapter 9. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Introduced in PTX ISA version 1. A predefined. // initialized at grid launch A predefined.u32 %smid. Note that %smid is volatile and returns the location of a thread at the moment when read. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. but its value may change during execution.u32 %r. PTX ISA Notes Target ISA Notes Examples January 24.0. %smid.0. . Supported on all target architectures. %gridid. 2010 153 . Special Registers Table 119. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Supported on all target architectures. so %nsmid may be larger than the physical number of SMs in the device. . mov. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Introduced in PTX ISA version 1.u32 %gridid. %nsmid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. .sreg . mov. where each launch starts a grid-of-CTAs. PTX ISA Notes Target ISA Notes Examples Table 121.u32 %r. read-only special register initialized with the per-grid temporal grid identifier. During execution. A predefined. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.

mov. Introduced in PTX ISA version 2. mov. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %r.u32 %lanemask_le.sreg . Table 124. . Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %r. %lanemask_le.0.u32 %r.u32 %lanemask_lt.0. mov. . A predefined. Table 123. %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later. 2010 . %lanemask_eq. A predefined.u32 %lanemask_eq. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. .sreg . %lanemask_lt.sreg . A predefined. %lanemask_le requires sm_20 or later.0 Table 122. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.0. 154 January 24. Introduced in PTX ISA version 2.PTX ISA Version 2.

sreg .u32 %lanemask_gt. Introduced in PTX ISA version 2. A predefined. 2010 155 . %lanemask_ge requires sm_20 or later. Introduced in PTX ISA version 2.u32 %lanemask_ge. %lanemask_ge. . read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt requires sm_20 or later. Special Registers Table 125. Table 126. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. %lanemask_gt. A predefined.0.Chapter 9. January 24.sreg . Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. mov. . mov.0.

0 Table 127. mov. %pm3. Table 128. %pm2.u64 r1. Introduced in PTX ISA version 1. Supported on all target architectures. 156 January 24. %clock64 requires sm_20 or later.%pm0. read-only 64-bit unsigned cycle counter.u32 %pm0. Supported on all target architectures. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. mov. %pm1. …. Special registers %pm0.sreg . and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm1. %pm2. mov. Their behavior is currently undefined. %pm3 %pm0. . Introduced in PTX ISA version 2. Introduced in PTX ISA version 1.%clock. %pm1.u64 %clock64. %pm2. The lower 32-bits of %clock64 are identical to %clock. .sreg . 2010 .u32 %clock.%clock64.PTX ISA Version 2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.0. .0.u32 r1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.sreg .3.u32 r1. Special Registers: %pm0. read-only 32-bit unsigned cycle counter. Table 129.

version directive. and the target architecture for which the code was generated.version major. 2010 157 . .target Table 130. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version directive.4 January 24. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.version Syntax Description Semantics PTX version number. . Increments to the major number indicate incompatible changes to PTX. Duplicate .version .0.version directives are allowed provided they match the original . Supported on all target architectures.version 2.Chapter 10.version . Directives 10. .version 1. minor are integers Specifies the PTX language version number. Each ptx file must begin with a . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.minor // major.0 . PTX File Directives: .1.

This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. brkpt instructions.f64 to .5. immediately followed by a .red}. Texturing mode: (default is .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.f64 instructions used. In general.red}.f64 instructions used. Adds {atom.PTX ISA Version 2.0. Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_12. sm_11.target directive specifies a single target architecture.target directives can be used to change the set of target features allowed during parsing. 64-bit {atom.global. Requires map_f64_to_f32 if any .version directive.0 Table 131. including expanded rounding modifiers.global. map_f64_to_f32 }. Therefore. sm_10. Supported on all target architectures.f64 storage remains as 64-bits. Adds {atom. Introduced in PTX ISA version 1. but subsequent . Adds double-precision support. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. where each generation adds new features and retains all features of previous generations. texture and sampler information is referenced with independent . PTX code generated for a given target can be run on later generation devices. sm_13.target . The following table summarizes the features in PTX that vary according to target architecture. . 158 January 24.texref and . A .target directive containing a target architecture and optional platform options. A program with multiple .red}.f64 instructions used. Requires map_f64_to_f32 if any . with only half being used by instructions converted from . Each PTX file must begin with a . vote instructions. texmode_independent. and an error is generated if an unsupported feature is used. The texturing mode is specified for an entire module and cannot be changed within the module.texref descriptor. PTX File Directives: .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Texturing mode introduced in PTX ISA version 1. Target sm_20 Description Baseline feature set for sm_20 architecture. generations of SM architectures follow an “onion layer” model. texmode_unified.shared. Note that .texmode_independent texture and sampler information is bound together and accessed via a single . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Disallows use of map_f64_to_f32.texmode_unified) .texmode_unified .target Syntax Architecture and Platform target.f32.samplerref descriptors. Requires map_f64_to_f32 if any . 2010 . PTX features are checked against the specified target architecture.

target sm_13 // supports double-precision . Directives Examples .Chapter 10. texmode_independent January 24. 2010 159 .target sm_20.target sm_10 // baseline target architecture .

entry filter ( .entry .entry .b32 %r2. .param.surfref variables may be passed as parameters. with optional parameters. e. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.b32 %r1. Kernel and Function Directives: . [y].entry kernel-name kernel-body Defines a kernel entry point name.entry Syntax Description Kernel entry point and body.samplerref. etc.0 through 1.param.0 through 1.param instructions. %nctaid. parameter variables are declared in the kernel parameter list.2. and query instructions and cannot be accessed via ld.4 and later. %ntid.param space memory and are listed within an optional parenthesized parameter list.5 and later. Supported on all target architectures. and body for the kernel function. 2010 .PTX ISA Version 2.param instructions. opaque .b32 %r3.b32 x.g. [z]. ld. . parameter variables are declared in the kernel body. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. … } . PTX ISA Notes For PTX ISA version 1.reg . 160 January 24.0 10. The shape and size of the CTA executing the kernel are available in special registers.texref. At kernel launch. These parameters can only be referenced by name within texture and surface load. ld. . Parameters are passed via . the kernel dimensions and properties are established and made available via special registers. .param .entry cta_fft .param. parameters. ld. In addition to normal parameters. store. and . . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. .4. Semantics Specify the entry point for a kernel program. Parameters may be referenced by name within the kernel body and loaded into registers using ld.entry kernel-name ( param-list ) kernel-body .b32 y.param { .param .b32 z ) Target ISA Notes Examples [x].b32 %r<99>.func Table 132. For PTX ISA versions 1.3.

func fname function-body . The parameter lists define locally-scoped variables in the function body.0 with target sm_20 allows parameters in the .b32 rval) foo (.reg . other code. Parameter passing is call-by-value. (val0.reg . foo.func (. there is no stack. parameters must be in the register state space.func fname (param-list) function-body . .func . Directives Table 133.0 with target sm_20 supports at most one return value. Parameters in . Release Notes For PTX ISA version 1.0.x code.param state space. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.func Syntax Function definition.reg .func (ret-param) fname (param-list) function-body Defines a function. ret. } … call (fooval).b32 rval.param and st. dbl. val1). and supports recursion.result.param space are accessed using ld. Parameters in register state space may be referenced directly within instructions in the function body. mov. Parameters must be base types in either the register or parameter state space. … Description // return value in fooval January 24.2 for a description of variadic functions. Variadic functions are represented using ellipsis following the last fixed argument.b32 localVar.param instructions in the body. including input and return parameters and optional function body.reg . Variadic functions are currently unimplemented.func definition with no body provides a function prototype. implements an ABI with stack.b32 N. if any. . 2010 161 . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Supported on all target architectures. PTX ISA 2. . which may use a combination of registers and stack locations to pass parameters. The implementation of parameter passing is left to the optimizing translator. A . PTX 2. … use N.Chapter 10.f64 dbl) { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Kernel and Function Directives: . and recursion is illegal.

maxnreg directive specifies the maximum number of registers to be allocated to a single thread.maxntid. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. PTX supports the following directives. These can be used. The . .PTX ISA Version 2.maxnreg. and . which pass information to the backend optimizing compiler.minnctapersm . 2010 . The interpretation of . The directive passes a list of strings to the backend.maxntid .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. for example.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.g.entry directive and its body. to throttle the resource requirements (e. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.3. A general .maxnreg .maxnctapersm (deprecated) . registers) to increase total thread count and provide a greater opportunity to hide memory latency. and the . the . 162 January 24. .maxntid and . at entry-scope. the . Currently.pragma directives may appear at module (file) scope.pragma directive is supported for passing information to the PTX backend. Note that . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.minnctapersm directives may be applied per-entry and must appear between an . The directives take precedence over any module-level constraints passed to the optimizing backend.pragma The . and the strings have no semantics within the PTX virtual machine model.maxntid directive specifies the maximum number of threads in a thread block (CTA).minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).0 10. or as statements within a kernel or device function body.

The compiler guarantees that this limit will not be exceeded. Introduced in PTX ISA version 1.entry foo . nz Declare the maximum number of threads in the thread block (CTA). ny. or 3D CTA. This maximum is specified by giving the maximum extent of each dimention of the 1D. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. ny . Supported on all target architectures. Supported on all target architectures.maxntid and . . The actual number of registers used may be less.maxntid 256 .maxntid nx.maxntid . or the maximum number of registers may be further constrained by . The maximum number of threads is the product of the maximum extent in each dimension. .3. Performance-Tuning Directives: .maxntid nx . 2D. 2010 163 .entry bar .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxnreg .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. .maxntid Syntax Maximum number of threads in thread block (CTA).Chapter 10.entry foo . for example.3.maxnreg n Declare the maximum number of registers per thread in a CTA. Directives Table 134. Introduced in PTX ISA version 1. . Performance-Tuning Directives: .16.maxntid 16.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid nx. Exceeding any of these limits results in a runtime error or kernel launch failure. the backend may be able to compile to fewer registers.maxctapersm.

.entry foo . .minnctapersm generally need .maxnctapersm (deprecated) .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. However.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Supported on all target architectures. Optimizations based on .maxnctapersm has been renamed to .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. 2010 . Introduced in PTX ISA version 2.maxnctapersm generally need . The optimizing backend compiler uses .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm in PTX ISA version 2.0 Table 136.0 as a replacement for .entry foo . .0. Supported on all target architectures.maxnctapersm.3.maxntid and . Performance-Tuning Directives: .0.maxntid to be specified as well. For this reason. Introduced in PTX ISA version 1. .PTX ISA Version 2.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm 4 { … } 164 January 24. . Deprecated in PTX ISA version 2.minnctapersm .maxntid 256 . Optimizations based on . additional CTAs may be mapped to a single multiprocessor. if the number of registers used by the backend is sufficiently lower than this bound.maxntid to be specified as well.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxntid 256 . Performance-Tuning Directives: .

2010 165 . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . The . { … } January 24. Performance-Tuning Directives: . at entry-scope. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma Syntax Description Pass directives to PTX backend compiler. . or statement-level directives to the PTX backend compiler.pragma “nounroll”. Directives Table 138. Introduced in PTX ISA version 2.pragma directive strings is implementation-specific and has no impact on PTX semantics. entry-scoped.pragma directive may occur at module-scope.Chapter 10.pragma . or at statementlevel. . Supported on all target architectures.0.pragma “nounroll”. The interpretation of . Pass module-scoped.entry foo .pragma list-of-strings .

replaced by .debug_info .2.file .232-1] .byte byte-list // comma-separated hexadecimal byte values . 0x00.0.quad int64-list // comma-separated hexadecimal integers in range [0. Deprecated as of PTX 2. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0. Introduced in PTX ISA version 1.PTX ISA Version 2.0 10.byte 0x2b.264-1] . 0x00. The @@DWARF syntax is deprecated as of PTX version 2.4byte 0x6e69616d.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. @@DWARF dwarf-string dwarf-string may have one of the . Supported on all target architectures. 0x00 .0 and replaces the @@DWARF syntax. 0x5f736f63 . 0x63613031.4byte label . 0x00. 0x00.4.byte 0x00. 0x00 166 January 24..debug_pubnames. Table 139.x code. 0x61395a5f. @progbits .loc The .section directive is new in PTX ISA verison 2. 2010 . “”. 0x6150736f.0 but is supported for legacy PTX version 1. 0x02. 0x00000364. 0x736d6172 .section .section directive. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .4byte 0x000006b5. 0x00..section .4byte .

replaces @@DWARF syntax.. 0x00. Source file information.section section_name { dwarf-lines } dwarf-lines have the following formats: .section Syntax PTX section definition. . 0x00.. Directives Table 140.loc line_number January 24.. . Debugging Directives: .232-1] . 0x00. 0x00 0x61395a5f.b64 int64-list // comma-separated list of integers in range [0.section . . 0x00.b32 0x000006b5.0.debug_pubnames { . Supported on all target architectures.b32 label .loc .b32 int32-list // comma-separated list of integers in range [0. Source file location. .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.255] . .b32 .0. .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00. Supported on all target architectures. 0x5f736f63 0x6150736f. . 0x63613031.b32 0x6e69616d.file filename Table 142. Debugging Directives: .b8 byte-list // comma-separated list of integers in range [0.264-1] . 0x736d6172 0x00 Table 141.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.debug_info . } 0x02.0. Supported on all target architectures. 0x00.file .b8 0x2b.Chapter 10.b8 0x00. 2010 167 . 0x00000364. Debugging Directives: .section .

extern .b32 foo. Linking Directives . // foo is defined in another module Table 144.visible identifier Declares identifier to be externally visible.PTX ISA Version 2.0. Introduced in PTX ISA version 1. Supported on all target architectures. 2010 .extern .visible Table 143. Supported on all target architectures.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.global . Linking Directives: .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. .6.visible .extern identifier Declares identifier to be defined externally. . Introduced in PTX ISA version 1.b32 foo.extern . .global . Linking Directives: . // foo will be externally visible 168 January 24. .visible .0.0 10.

Release Notes This section describes the history of change in the PTX ISA and implementation.0 PTX ISA 1.2 PTX ISA 1. The release history is as follows. The first section describes ISA and implementation changes in the current release of PTX ISA 2.3 driver r190 CUDA 3.4 PTX ISA 1.0.2 CUDA 2. CUDA Release CUDA 1.1 PTX ISA 1.1 CUDA 2.0 CUDA 1.1 CUDA 2.0 January 24. and the remaining sections provide a record of changes in previous releases.0 driver r195 PTX ISA Version PTX ISA 1.Chapter 11.3 PTX ISA 1.0 CUDA 2.5 PTX ISA 2. 2010 169 .

mad.0 11. 2010 . The fma. The mad.f32 requires sm_20.PTX ISA Version 2. Floating-Point Extensions This section describes the floating-point changes in PTX 2.1.0 for sm_20 targets.1.1.f32 instruction also supports .rp rounding modifiers for sm_20 targets.f32 and mad. sub.rn.0 11. The mad.f32 maps to fma. and sqrt with IEEE 754 compliant rounding have been added. The .f32.sat modifiers. The goal is to achieve IEEE 754 compliance wherever possible.ftz and . fma.ftz modifier may be used to enforce backward compatibility with sm_1x. Changes in Version 2. Both fma. The changes from PTX ISA 1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.1. Single-precision add.x code and sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added.f32 for sm_20 targets.and double-precision div. rcp.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. New Features 11.1. Single. Instructions testp and copysign have been added. When code compiled for sm_1x is executed on sm_20 devices.1. and mul now support .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. These are indicated by the use of a rounding modifier and require sm_20. • • • • • 170 January 24.f32 require a rounding modifier for sm_20 targets.rm and . while maximizing backward compatibility with legacy PTX 1.

has been added. has been added.arrive instruction has been added.minnctapersm to better match its behavior and usage.red}. Instruction sust now supports formatted surface stores. and red now support generic addressing. local.red. Instruction cvta for converting global. has been added. Cache operations have been added to instructions ld. A system-level membar instruction. 11.ballot. Release Notes 11. Bit field extract and insert instructions.{and. New instructions A “load uniform” instruction. e.2. bfe and bfi. suld. New special registers %nsmid. A “population count” instruction.le.section.u32 and bar. bar now supports optional thread count and register operands.b32. cvta. ldu. popc. has been added. Other new features Instructions ld. ldu. Instructions {atom.or}. Video instructions (includes prmt) have been added. st. Instructions {atom. Instructions prefetch and prefetchu have also been added. A new directive. membar. has been added. for prefetching to specified level of memory hierarchy. A “count leading zeros” instruction.lt. prefetch. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. prefetchu.ge. Surface instructions support additional . . The .gt} have been added. has been added.1.g.red}. A “vote ballot” instruction. st.red. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.1. A “bit reversal” instruction.add. and sust. Instructions bar.1. %clock64. clz. atom. has been added. have been added. and shared addresses to generic address and vice-versa has been added.Chapter 11.1. 2010 171 .popc. isspacep. brev. .pred have been added.f32 have been implemented.maxnctapersm directive was deprecated and replaced with . bfind.clamp modifiers.shared have been extended to handle 64-bit data types for sm_20 targets. January 24. vote.zero.3.sys. A “find leading non-sign bit” instruction.clamp and . %lanemask_{eq. The bar instruction has been extended as follows: • • • A bar.

if .s32. Formatted surface load is unimplemented.PTX ISA Version 2. 2010 .version is 1. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.4 and earlier.target sm_1x. Instruction bra.2.ftz (and cvt for .5 and later.1. The underlying.u32. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. Formatted surface store with . {atom. To maintain compatibility with legacy PTX code.max} are not implemented.p sust. the correct number is sixteen. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. 172 January 24.4 or earlier.f32.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.s32.{u32.5. Support for variadic functions and alloca are unimplemented. or . In PTX version 1. stack-based ABI is unimplemented. cvt. has been fixed.f32 type is unimplemented.ftz for PTX ISA versions 1. 11.f32} atom. See individual instruction descriptions for details.0 11.{min.3.p.red}. . where . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. call suld.1. Semantic Changes and Clarifications The errata in cvt. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.

Table 145.pragma “nounroll”. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma “nounroll”.entry foo (…) . Supported only for sm_20 targets.pragma strings defined by ptxas. L1_end: … } // do not unroll this loop January 24. … @p bra L1_end. . disables unrolling of0 the loop for which the current block is the loop header.Appendix A. Note that in order to have the desired effect at statement level.pragma “nounroll”. entry-function. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. { … } // do not unroll any loop in this function . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. The “nounroll” pragma is allowed at module. 2010 173 .0.func bar (…) { … L1_head: . including loops preceding the . and statement levels. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. Descriptions of . Ignored for sm_1x targets. . L1_body: … L1_continue: bra L1_head. disables unrolling for all loops in the entry function body.pragma Strings This section describes the .

PTX ISA Version 2.0 174 January 24. 2010 .

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