NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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................................ 44 Rounding Modifiers .....................4........ Types............................................... and Variables .................. 29 Local State Space .............................1..................4................ 39 Parameterized Variable Names ............................ 5.............................2..................................................................... Chapter 6........................... 6.......... 32 5.............. 5......................................... and Surface Types .................................. 33 5.............................................................................................................................................................. 6.............. 28 Special Register State Space ...................................................................... 5........ 6..................................... 5.........................................................................................................................1...... 5.......6......................3..................... 41 Using Addresses..........2........................ 34 Variables ...... 5.........4.........1..... 27 Register State Space .......................... 49 ii January 24... 41 6.......... 42 Addresses as Operands ................................................................... Arrays.............................................1....................... 37 Variable Declarations .......................3........... Instruction Operands......................................... 37 Array Declarations ............................PTX ISA Version 2............5.......................................................................................5.................................. 27 5.................................... 32 Texture State Space (deprecated) ....... Sampler...........5........................................................ 5.........................4.........4............... 29 Global State Space ...... Texture........1......................4............................................................2.......................4................................................1...7................ 47 Chapter 7.6........ 43 6.................2............0 4................................................................... 43 Vectors as Operands .................1.... 49 7...................................................... 42 Arrays as Operands ................. 33 Fundamental Types ................................. 6... State Spaces ....................... 5........... Abstracting the ABI ................1....................... 37 Vectors ....... 5. Function declarations and definitions ....4....................................1.............................................6......................1..1................ 28 Constant State Space ... 43 Labels and Function Names as Operands ..................5..........5............... 6.. Operand Type Information .........................1...........................4....... 39 5.......... 5................................... 5...1........................ 44 Scalar Conversions ..2............. 41 Source Operands...................2.......................1...4.......4...4.................................................................................8....... Operand Costs ..... State Spaces......................................... 6..... 5............................6............................................3.......................4......... 29 Parameter State Space ....... 2010 ............................... 38 Initializers ........................ 6.................. 6.............................................................................................. and Vectors ........2................... 5..................................................................................... 38 Alignment ................... Types ......................1.............4.............. 5..... Summary of Constant Expression Evaluation Rules .......................................................1.......... 25 Chapter 5........................................................... 5...................................4...........................................................................................3......... 41 Destination Operands ..............................5.....................................2.......................... 5...... 46 6........2..................... Type Conversion................. 33 Restricted Use of Sub-Word Sizes .. 6.......................3............................ 30 Shared State Space........................

...............2.......................7............................................... Changes in Version 2........................6............ 8...1................................................. Chapter 9.........................................................................................................................................................................................................................................................................5................................... 129 Parallel Synchronization and Communication Instructions .................. Instructions ...............................1............ 8......... 60 8..... 147 8..............................2.. 162 Debugging Directives ............ 55 PTX Instructions ...... 100 Logic and Shift Instructions ............................. 8.........3............................................................................................................7....................................3............................................................. 170 New Features .......................4.....1.................................4.................................4...6............................6......................................................................................................... 56 Comparisons .............. Type Information for Instructions and Operands .... 10........................................................................ 8.1..................... 2010 iii ............................ 8................. 62 8..............................9...4. 10................... 149 Chapter 10....2............ 8............. 8........ 55 8..1... 157 Specifying Kernel Entry Points and Functions ...................... 58 8.......... Changes from PTX 1.....0 ...............................6... 62 Machine-Specific Semantics of 16-bit Code ...... 55 Predicated Execution ... Divergence of Threads in Control Constructs ............................ 59 Operand Size Exceeding Instruction-Type Size .............. 132 Video Instructions ........................................................... 166 Linking Directives ... 62 Semantics .......... Format and Semantics of Instruction Descriptions .............................. 122 Control Flow Instructions ......... 8........... 104 Data Movement and Conversion Instructions ....................................... 7...... 140 Miscellaneous Instructions...............................................1................................... 11.. 81 Comparison and Selection Instructions ............... 10...................................... 8................................................................1.......................................... Release Notes .8........................7......... 11.........................3................ 8....................... 172 January 24....................................... 108 Texture and Surface Instructions ........................................... Special Registers .. 63 Integer Arithmetic Instructions .......7...... Directives ....................................7.........................2............................ 157 10...............................7..................................................................... 160 Performance-Tuning Directives ......... 170 Semantic Changes and Clarifications ....... 57 Manipulating Predicates ....7........... 10............ 169 11...................................... 172 Unimplemented Features Remaining .......7............. 168 Chapter 11......................1..... 52 Variadic functions ................3........................................................................ 8.............1.................... 53 Alloca ...............1................. 8...........................................................10............... 8........................................7...........................................1........................2................... 54 Chapter 8....... 63 Floating-Point Instructions ...................................2.7... PTX Version and Target Directives ................. 11.........................7............................................................. 7......................3..................5................................x ...................3............. 8............... 8....7... Instruction Set .....................7............1....................................................................1..........................................3................. 8..........

...PTX ISA Version 2............pragma Strings....... Descriptions of .........................0 Appendix A........ 173 iv January 24...... 2010 .......

.................. 59 Relaxed Type-checking Rules for Source Operands ............ Table 5....... Table 27......................................... 65 Integer Arithmetic Instructions: addc ..................................... Table 2.................... 35 Opaque Type Fields in Independent Texture Mode ...... 70 Integer Arithmetic Instructions: sad ... 58 Floating-Point Comparison Operators Testing for NaN .............. 66 Integer Arithmetic Instructions: mul ................................................................................ Table 24.................................... Table 15............ Table 25........... 33 Opaque Type Fields in Unified Texture Mode ........................................... 27 Properties of State Spaces ................................. Table 23........................ Table 20............................... 64 Integer Arithmetic Instructions: sub ......................................... Table 8.............................................. 61 Integer Arithmetic Instructions: add .............................. Table 26........................................................................................... Table 6...................................... 35 Convert Instruction Precision and Format .....cc ... 20 Operator Precedence .................................. Table 18............................................... 18 Reserved Instruction Keywords ........ 69 Integer Arithmetic Instructions: mad24 ......................................................................... Table 22........... Table 12............................ Table 17................... 66 Integer Arithmetic Instructions: subc ........................ and Bit-Size Types ............................. Table 30....List of Tables Table 1.................. Table 13.............................................. Table 11....... 25 State Spaces .................................... Table 10................................................. Table 19...................................................................................................................................................................................................... 71 January 24.............. 67 Integer Arithmetic Instructions: mad ............... Table 14.................................. Table 9......................................................................... Table 3................................................. 58 Type Checking Rules ............................................... 47 Operators for Signed Integer.......................... 2010 v ................................................................. PTX Directives .......................................................................... Table 21.................. Table 16................ Table 7..... 57 Floating-Point Comparison Operators ............ Table 32................... 45 Floating-Point Rounding Modifiers ..................................................... 23 Constant Expression Evaluation Rules . 64 Integer Arithmetic Instructions: add.......................................................... Unsigned Integer........... 46 Integer Rounding Modifiers ............................. Table 29........................... 60 Relaxed Type-checking Rules for Destination Operands...................... 57 Floating-Point Comparison Operators Accepting NaN ............................... Table 28.. Table 31............ 68 Integer Arithmetic Instructions: mul24 ............... 19 Predefined Identifiers ...................................... 28 Fundamental Type Specifiers .................................................................. 46 Cost Estimates for Accessing State-Spaces ....................... 65 Integer Arithmetic Instructions: sub..........cc ............................................................. Table 4...........................................................................................

.... 90 Floating-Point Instructions: abs ........................... 85 Floating-Point Instructions: mul ................................... Integer Arithmetic Instructions: div ....................................................................0 Table 33............................................ Table 34.................................... 95 Floating-Point Instructions: sin ......................... 92 Floating-Point Instructions: rcp .................. 72 Integer Arithmetic Instructions: neg .......... Table 35.............................. Table 62............................... Table 69........................... Table 40............................. Table 55..... 74 Integer Arithmetic Instructions: bfind .............. Table 57................................................ Table 63.................... Table 56................................................................................................................................................................................................ 102 Comparison and Selection Instructions: selp .................................. 72 Integer Arithmetic Instructions: min .. 76 Integer Arithmetic Instructions: bfe ......................................... Table 42. Table 43....................................................... 91 Floating-Point Instructions: min ........................ 93 Floating-Point Instructions: sqrt .................................................................................................... 78 Integer Arithmetic Instructions: prmt .......... Table 53.......................... Table 58............ 74 Integer Arithmetic Instructions: clz ............... Table 47....... Table 65............................... Table 64............................................................................................................. Table 46.................................................... Table 61............................................................ Table 36................................................ 88 Floating-Point Instructions: div ...........................PTX ISA Version 2..................... 99 Comparison and Selection Instructions: set ........................................ Table 39.......................................................... Table 59....................... 84 Floating-Point Instructions: sub .................................... Table 54................................ 96 Floating-Point Instructions: cos ..................... 91 Floating-Point Instructions: neg .............. 83 Floating-Point Instructions: copysign ............ Table 51................................................. 94 Floating-Point Instructions: rsqrt ................... 2010 .......................... Table 49.................................................................... 73 Integer Arithmetic Instructions: max ........................... 103 vi January 24....................................................................................................................................................... 97 Floating-Point Instructions: lg2 ......................................... Table 66.......................................... 71 Integer Arithmetic Instructions: abs ...................... 77 Integer Arithmetic Instructions: bfi .................................................................... Table 50......................................................................................... Table 68.............. 82 Floating-Point Instructions: testp .... 98 Floating-Point Instructions: ex2 ............................ Table 60............................. 71 Integer Arithmetic Instructions: rem ... Table 48........ 73 Integer Arithmetic Instructions: popc .............................. 87 Floating-Point Instructions: mad ............................. 86 Floating-Point Instructions: fma ................................ Table 52.. Table 37....................... Table 41................................................................................................................... Table 67....... 79 Summary of Floating-Point Instructions ............................. 103 Comparison and Selection Instructions: slct ........................................ 92 Floating-Point Instructions: max ......... Table 44........................................................................... Table 45..................... 83 Floating-Point Instructions: add ................. 75 Integer Arithmetic Instructions: brev ......... Table 38................................................... 101 Comparison and Selection Instructions: setp .............................................................

.......................... 137 Parallel Synchronization and Communication Instructions: vote .................... 106 Logic and Shift Instructions: cnot .... Table 89.................................. Table 102..... Table 100................................. Table 104............. 128 Control Flow Instructions: { } .................................... 112 Data Movement and Conversion Instructions: ld .................................... Table 98....................... 120 Texture and Surface Instructions: tex ............................................................................ Table 106.................................................................................... Table 101............ Logic and Shift Instructions: and .............................................. 131 Parallel Synchronization and Communication Instructions: bar . 135 Parallel Synchronization and Communication Instructions: red ................................................... 134 Parallel Synchronization and Communication Instructions: atom ...................................... 105 Logic and Shift Instructions: or ..................................... 131 Control Flow Instructions: exit .............................................. Table 78....................... Table 81... 119 Data Movement and Conversion Instructions: cvta .............. Table 90......................................................................................................................................................................... 106 Logic and Shift Instructions: not ..................... Table 99..................................................... Table 85....... Table 74.................. 105 Logic and Shift Instructions: xor ... Table 71......................... vsub. Table 96..... 139 Video Instructions: vadd.......... Table 94.................. Table 79................... 129 Control Flow Instructions: @ . Table 91................... Table 88..... Table 82...... 118 Data Movement and Conversion Instructions: isspacep ... Table 73.................... Table 95................. vmax ........ 109 Cache Operators for Memory Store Instructions .................................................................................. Table 92............................................. Table 72...Table 70.. Table 83.......................................... Table 105....................................... 123 Texture and Surface Instructions: txq ................................... 116 Data Movement and Conversion Instructions: prefetch............................................................ Table 93.......... Table 97........ Table 86............. prefetchu .......... 111 Data Movement and Conversion Instructions: mov ......... 119 Data Movement and Conversion Instructions: cvt ....... Table 76... Table 80......... 143 January 24..................... 110 Data Movement and Conversion Instructions: mov ........................... Table 84.............. 106 Logic and Shift Instructions: shl .. 2010 vii ....................... vmin.. 129 Control Flow Instructions: bra ............................................................................................................ Table 77......................... 130 Control Flow Instructions: call .. 125 Texture and Surface Instructions: sust .................................................................................... 133 Parallel Synchronization and Communication Instructions: membar ...... 130 Control Flow Instructions: ret ........... 115 Data Movement and Conversion Instructions: st ..... 142 Video Instructions: vshl............................................... 107 Logic and Shift Instructions: shr ..................................... Table 87........................... 107 Cache Operators for Memory Load Instructions ............................ 124 Texture and Surface Instructions: suld ........ vshr ..................................................... vabsdiff.................................. 126 Texture and Surface Instructions: sured. Table 75......... Table 103................................. 113 Data Movement and Conversion Instructions: ldu ............................................................................ 127 Texture and Surface Instructions: suq ................................................................................

............................... Table 112......................... Table 110................ Table 123.................. Table 139.......................................... Table 127........................ 150 Special Registers: %laneid ................................func ......... 154 Special Registers: %lanemask_lt ..................... Table 113....version.............................. 147 Miscellaneous Instructions: pmevent........................... 160 Kernel and Function Directives: ......... Table 142............. 144 Video Instructions: vset....................................................... %pm1.................minnctapersm ................................................. 147 Special Registers: %tid ......................... Table 126.......................................... Table 119.................................... 157 PTX File Directives: ................................ 151 Special Registers: %ctaid .................................................................................. Table 130............................................................................ 164 Performance-Tuning Directives: .. Table 141. Table 125....................PTX ISA Version 2.............................................................................................................................. Table 121...............0 Table 107...........................target ........ 168 viii January 24.................................................... Table 108........................................ 153 Special Registers: %nsmid ....................... 161 Performance-Tuning Directives: ...... Table 111................... Table 122. 164 Performance-Tuning Directives: ..........pragma .............................................. Table 131.... Table 135....... Table 116....... Table 132................................ 153 Special Registers: %lanemask_eq ........entry......... 152 Special Registers: %smid .................maxntid ...... Table 115...................................................................................................................................................................................................................................... 155 Special Registers: %lanemask_gt .......... 155 Special Registers: %clock ..............................................................................................................................maxnreg ............ 147 Miscellaneous Instructions: brkpt ........... 154 Special Registers: %lanemask_ge ................................................................................... 151 Special Registers: %nwarpid ........................................................... %pm3 .................................... Table 137.................................. Table 129................maxnctapersm (deprecated) ................................................. 152 Special Registers: %nctaid ............... 166 Debugging Directives: ............................... Table 120...................................................................................... Table 117.................. Table 136..file .. Table 134........... Table 128........ Table 143..... %pm2............................................. Table 109. 151 Special Registers: %warpid ..................... Table 133.................... 165 Debugging Directives: @@DWARF .... 156 Special Registers: %clock64 .......................... 150 Special Registers: %ntid .section ................................. 163 Performance-Tuning Directives: ................................................................................. Table 124.................................. 167 Debugging Directives: ... 146 Miscellaneous Instructions: trap ........ 158 Kernel and Function Directives: ....................................................... 156 PTX File Directives: .............. 156 Special Registers: %pm0................loc ..... 153 Special Registers: %gridid ...... 167 Debugging Directives: ................. 154 Special Registers: %lanemask_le .............. 167 Linking Directives: .......................................................................... 2010 ...................... 163 Performance-Tuning Directives: ................. Table 140....... Video Instructions: vmad ......... Table 118................................................extern.......................................................... Table 114......................... Table 138...............................

............. 173 January 24..Table 144......... Table 145.........................................visible............... Linking Directives: .................................... 2010 ix ................................................. 168 Pragma Strings: “nounroll” ......

2010 .0 x January 24.PTX ISA Version 2.

video encoding and decoding. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Introduction This document describes PTX. image scaling. Because the same program is executed for each data element. 2010 1 . Similarly. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. stereo vision. 1. the memory access latency can be hidden with calculations instead of big data caches. image and media processing applications such as post-processing of rendered images. January 24. Data-parallel processing maps data elements to parallel processing threads. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. PTX defines a virtual machine and ISA for general purpose parallel thread execution. 1. multithreaded. high-definition 3D graphics. PTX exposes the GPU as a data-parallel computing device. there is a lower requirement for sophisticated flow control. In fact. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. PTX programs are translated at install time to the target hardware instruction set. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. the programmable GPU has evolved into a highly parallel.1. from general signal processing or physics simulation to computational finance or computational biology. and because it is executed on many data elements and has high arithmetic intensity. and pattern recognition can map image blocks and pixels to parallel processing threads.Chapter 1.2. which are optimized for and translated to native target-architecture instructions. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations.

f32 require a rounding modifier for sm_20 targets. Achieve performance in compiled applications comparable to native GPU performance. and mul now support .rp rounding modifiers for sm_20 targets. 1. Instructions marked with . including integer. PTX 2. Provide a common source-level ISA for optimizing code generators and translators. fma. and all PTX 1. PTX ISA Version 2. 1. Most of the new features require a sm_20 target. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.f32 maps to fma.x.3. barrier. addition of generic addressing to facilitate the use of general-purpose pointers. Single-precision add.1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. The fma. Provide a machine-independent ISA for C/C++ and other compilers to target.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.f32 and mad. and video instructions. The main areas of change in PTX 2. sub.0 is in improved support for the IEEE 754 floating-point standard.PTX ISA Version 2. and the introduction of many new instructions.rm and . Facilitate hand-coding of libraries.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.ftz) modifier may be used to enforce backward compatibility with sm_1x. Improved Floating-Point Support A main area of change in PTX 2. Provide a code distribution ISA for application and middleware developers.f32. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.0 PTX ISA Version 2.0 is a superset of PTX 1. surface.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x features are supported on the new sm_20 target.f32 requires sm_20. which map PTX to specific target machines. The mad. When code compiled for sm_1x is executed on sm_20 devices.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. 2010 . atomic. • • • 2 January 24.3. A single-precision fused multiply-add (fma) instruction has been added. performance kernels.x code will continue to run on sm_1x targets as well. and architecture tests. A “flush-to-zero” (.0 are improved support for IEEE 754 floating-point operations.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. mad.sat modifiers.f32 for sm_20 targets.ftz and . reduction.rn. The mad. memory. Both fma.f32 instruction also supports . Legacy PTX 1. The changes from PTX ISA 1.

suld. stack-based ABI.3. New Instructions The following new instructions. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. Generic Addressing Another major change is the addition of generic addressing. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. local. atom. Instructions testp and copysign have been added. and shared addresses to generic address and vice-versa has been added. 1.Chapter 1. 2010 3 . e. prefetch. and shared state spaces.. prefetchu. NOTE: The current version of PTX does not implement the underlying. Introduction • Single.4. rcp. stack layout.0. Support for an Application Binary Interface Rather than expose details of a particular calling convention. local.3.zero. st.2. Instructions prefetch and prefetchu have been added. an address that is the same across all threads in a warp. A new cvta instruction has been added to convert global. . Cache operations have been added to instructions ld. local. special registers. cvta. ldu. instructions ld. January 24.3.0. These are indicated by the use of a rounding modifier and require sm_20.3.g. Surface instructions support additional clamp modifiers. Generic addressing unifies the global. these changes bring PTX 2. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.clamp and . and shared addresses to generic addresses. Instruction cvta for converting global. for prefetching to specified level of memory hierarchy. and vice versa. i. allowing memory instructions to access these spaces without needing to specify the state space. • Taken as a whole. and red now support generic addressing. and directives are introduced in PTX 2. 1. st. PTX 2. isspacep. 1.0 closer to full compliance with the IEEE 754 standard. so recursion is not yet supported. and sqrt with IEEE 754 compliant rounding have been added. Surface Instructions • • Instruction sust now supports formatted surface stores. and Application Binary Interface (ABI). and sust. In PTX 2.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.e.and double-precision div.

.section.add. membar.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.PTX ISA Version 2. %lanemask_{eq. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.le. 4 January 24. bfi bit field extract and insert popc clz Atomic.shared have been extended to handle 64-bit data types for sm_20 targets.red}.red.ballot. 2010 . vote. bar now supports an optional thread count and register operands.ge.gt} have been added.popc. A “vote ballot” instruction.or}. %clock64.arrive instruction has been added. New special registers %nsmid. Barrier Instructions • • A system-level membar instruction.sys. has been added. Reduction.u32 and bar. Other Extensions • • • Video instructions (includes prmt) have been added.b32.pred have been added.red. A bar. Instructions bar.red}.lt. and Vote Instructions • • • New atomic and reduction instructions {atom. has been added. Instructions {atom.{and.f32 have been added. A new directive.

0. Chapter 7 describes the function and call syntax. and variable declarations. Chapter 3 gives an overview of the PTX virtual machine model. 2010 5 . Chapter 8 describes the instruction set. Chapter 11 provides release notes for PTX Version 2.Chapter 1. Introduction 1. January 24. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 4 describes the basic syntax of the PTX language. Chapter 6 describes instruction operands. calling convention.4. Chapter 9 lists special registers. types. Chapter 10 lists the assembly directives supported in PTX. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 5 describes state spaces.

PTX ISA Version 2. 2010 .0 6 January 24.

and results across the threads of the CTA. ntid.z) that specifies the thread’s position within a 1D. January 24. or 3D CTA.z). or host: In other words. The vector ntid specifies the number of threads in each CTA dimension. 2. and ntid.x.1. a portion of an application that is executed many times. To that effect.1. To coordinate the communication of the threads within the CTA. A cooperative thread array. work. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. 2D. 2. data-parallel. Programs use a data parallel decomposition to partition inputs.y. or CTA. Programming Model 2. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Each thread has a unique thread identifier within the CTA. compute addresses. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. More precisely. and tid.2.2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.x.Chapter 2. It operates as a coprocessor to the main CPU. is an array of threads that execute a kernel concurrently or in parallel. assign specific input and output positions. Each CTA thread uses its thread identifier to determine its assigned role. Cooperative thread arrays (CTAs) implement CUDA thread blocks. can be isolated into a kernel function that is executed on the GPU as many different threads. The thread identifier is a three-element vector tid. or 3D shape specified by a three-element vector ntid (with elements ntid. tid. Each CTA has a 1D.y. compute-intensive portions of applications running on the host are off-loaded onto the device. 2010 7 . (with elements tid. but independently on different data. Threads within a CTA can communicate with each other. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. 2D. one can specify synchronization points where threads wait until all threads in the CTA have arrived. and select work to perform.

depending on the platform. This comes at the expense of reduced thread communication and synchronization. The warp size is a machine-dependent constant. a warp has 32 threads.PTX ISA Version 2. 8 January 24. Each grid also has a unique temporal grid identifier (gridid). A warp is a maximal subset of threads from a single CTA. CTAs that execute the same kernel can be batched together into a grid of CTAs. read-only special registers %tid.2. The host issues a succession of kernel invocations to the device. Typically. %nctaid.0 Threads within a CTA execute in SIMT (single-instruction. or 3D shape specified by the parameter nctaid. so that the total number of threads that can be launched in a single kernel invocation is very large. because threads in different CTAs cannot communicate and synchronize with each other. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 2D . and %gridid. %ntid. Threads may read and use these values through predefined. WARP_SZ. Each grid of CTAs has a 1D. Some applications may be able to maximize performance with knowledge of the warp size. Multiple CTAs may execute concurrently and in parallel. Threads within a warp are sequentially numbered. %ctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. However. which may be used in any instruction where an immediate operand is allowed. 2010 . so PTX includes a run-time immediate constant. 2. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1).2. such that the threads execute the same instructions at the same time. multiple-thread) fashion in groups called warps. or sequentially.

2010 9 . 1) Thread (3. 1) CTA (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. A grid is a set of CTAs that execute independently. 2) Thread (1. 0) Thread (3. Thread Batching January 24. 1) Thread (4. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (0. 0) CTA (0. 1) Thread (1. 1) Grid 2 Kernel 2 CTA (1. Figure 1. 0) Thread (2. 2) Thread (3. 1) CTA (1. 1) Thread (0. 1) Thread (2. 0) Thread (1. 0) CTA (1. 2) Thread (2. 0) Thread (4. 0) CTA (2. 0) Thread (0. 2) Thread (4.Chapter 2.

or. The device memory may be mapped and read or written by the host. 2010 . Each thread has a private local memory.PTX ISA Version 2.3. Finally. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Texture memory also offers different addressing modes.0 2. constant. Both the host and the device maintain their own local memory. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant. respectively. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. for some specific data formats. referred to as host memory and device memory. The global. all threads have access to the same global memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. 10 January 24. as well as data filtering. The global. and texture memory spaces are persistent across kernel launches by the same application. and texture memory spaces are optimized for different memory usages. for more efficient transfer.

Memory Hierarchy January 24. 0) Block (2. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (2. 2) Block (1. 2) Figure 2. 1) Block (1. 1) Block (0. 1) Grid 1 Global memory Block (0. 0) Block (1.Chapter 2. 1) Block (1. 0) Block (0. 0) Block (1. 2010 11 .

PTX ISA Version 2.0 12 January 24. 2010 .

disabling threads that are not on that path. and executes threads in groups of parallel threads called warps. a cell in a grid-based computation). At every instruction issue time. If threads of a warp diverge via a data-dependent conditional branch. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). A multiprocessor consists of multiple Scalar Processor (SP) cores. a multithreaded instruction unit. Parallel Thread Execution Machine Model 3. the threads converge back to the same execution path. and each scalar thread executes independently with its own instruction address and register state. allowing. A warp executes one common instruction at a time. As thread blocks terminate. It implements a single-instruction barrier synchronization. To manage hundreds of threads running several different programs. schedules. the multiprocessor employs a new architecture we call SIMT (single-instruction. multiple-thread). manages. January 24. it splits them into warps that get scheduled by the SIMT unit. so full efficiency is realized when all threads of a warp agree on their execution path. The threads of a thread block execute concurrently on one multiprocessor. each warp contains threads of consecutive. different warps execute independently regardless of whether they are executing common or disjointed code paths. (This term originates from weaving. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. The multiprocessor SIMT unit creates. The multiprocessor creates. When a host program invokes a kernel grid. a voxel in a volume. and executes concurrent threads in hardware with zero scheduling overhead. increasing thread IDs with the first warp containing thread 0. Branch divergence occurs only within a warp. The multiprocessor maps each thread to one scalar processor core. 2010 13 . the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. for example. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently.Chapter 3. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. the first parallel thread technology. and on-chip shared memory. manages.1. When a multiprocessor is given one or more thread blocks to execute. and when all paths complete. new blocks are launched on the vacated multiprocessors. the warp serially executes each branch path taken. The way a block is split into warps is always the same.

• The local and global memory spaces are read-write regions of device memory and are not cached. In practice. 2010 . In contrast with SIMD vector machines. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. SIMT enables programmers to write thread-level parallel code for independent. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. A multiprocessor can execute as many as eight thread blocks concurrently. 14 January 24. modifies. which is a read-only region of device memory. For the purposes of correctness.0 SIMT architecture is akin to SIMD (Single Instruction. Vector architectures. A key difference is that SIMD vector organizations expose the SIMD width to the software. however. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. If there are not enough registers or shared memory available per multiprocessor to process at least one block. As illustrated by Figure 3. whereas SIMT instructions specify the execution and branching behavior of a single thread. the number of serialized writes that occur to that location and the order in which they occur is undefined. on the other hand. the kernel will fail to launch. Multiple Data) vector organizations in that a single instruction controls multiple processing elements.PTX ISA Version 2. scalar threads. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each read. and writes to the same location in global memory for more than one of the threads of the warp. modify. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. as well as data-parallel code for coordinated threads. If an atomic instruction executed by a warp reads. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. the programmer can essentially ignore the SIMT behavior. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. which is a read-only region of device memory. write to that location occurs and they are all serialized. require the software to coalesce loads into vectors and manage divergence manually. but one of the writes is guaranteed to succeed. but the order in which they occur is undefined.

Hardware Model January 24. 2010 15 .Chapter 3. Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

PTX ISA Version 2. 2010 .0 16 January 24.

Comments in PTX are treated as whitespace. Syntax PTX programs are a collection of text source files. Source Format Source files are ASCII text. PTX is case sensitive and uses lowercase for keywords. The C preprocessor cpp may be used to process PTX source files.target directive specifying the target architecture assumed.Chapter 4. 2010 17 . #if. 4. Lines beginning with # are preprocessor directives. #define. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. using non-nested /* and */ for comments that may span multiple lines. whitespace is ignored except for its use in separating tokens in the language.2. Pseudo-operations specify symbol and addressing management. Each PTX file must begin with a . and using // to begin a comment that extends to the end of the current line. #endif. #line. #ifdef.1. Comments Comments in PTX follow C/C++ syntax. All whitespace characters are equivalent.version directive specifying the PTX language version. #else. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. followed by a . See Section 9 for a more information on these directives. January 24. Lines are separated by the newline character (‘\n’). 4. The following are common preprocessor directives: #include.

1.3.entry .maxnctapersm . .param .b32 add. and terminated with a semicolon. shl. The destination operand is first. Instructions have an optional guard predicate which controls conditional execution.minnctapersm . The guard predicate may be optionally negated. Table 1. mov. r2.global. 2010 .sreg .shared .section .3. where p is a predicate register.loc .PTX ISA Version 2. followed by source operands.2.maxntid .reg . array[r1]. 0.f32 array[N]. All instruction keywords are reserved tokens in PTX.0 4.global .b32 r1. 18 January 24.visible 4. r2. r1. and is written as @p. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.b32 r1.func .align . or label names. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.maxnreg . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.f32 r2.3. 2.5.tex . Directive Statements Directive keywords begin with a dot.const .extern . constant expressions. Statements begin with an optional label and end with a semicolon. Statements A PTX statement is either a directive or an instruction. Examples: . written as @!p.reg . . Instruction keywords are listed in Table 2. The guard predicate follows the optional label and precedes the opcode. so no conflict is possible with user-defined identifiers. address expressions.b32 r1. r2. Operands may be register variables.x.file PTX Directives .global start: .pragma .local . %tid. ld.target .version .

Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.

0 4. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. underscore. The percentage sign can be used to avoid name conflicts. underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. listed in Table 3. dollar.g. %pm3 WARP_SZ 20 January 24. or they start with an underscore. except that the percentage sign is not allowed. …. Many high-level languages such as C and C++ follow similar rules for identifier names.PTX ISA Version 2. e. 2010 . Table 3. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. digits. digits. or dollar characters. PTX predefines one constant and a small number of special registers that begin with the percentage sign. or percentage character followed by one or more letters. between user-defined variable names and compiler-generated names. PTX allows the percentage sign as the first character of an identifier.4.

e. floating-point. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.e. i. 4.1. 2010 21 . Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. the constant begins with 0f or 0F followed by 8 hex digits. or binary notation. every integer constant has type . literals are always represented in 64-bit double-precision format.u64.5. the sm_1x and sm_20 targets have a WARP_SZ value of 32. For predicate-type data and instructions. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. and bit-size types. 4. integer constants are allowed and are interpreted as in C. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.2. To specify IEEE 754 single-precision floating point values. Unlike C and C++.s64 or the unsigned suffix is specified. i. Constants PTX supports integer and floating-point constants and constant expressions. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Floating-point literals may be written with an optional decimal point and an optional signed exponent. The syntax follows that of C.s64) unless the value cannot be fully represented in . Type checking rules remain the same for integer. in which case the literal is unsigned (. where the behavior of the operation depends on the operand types. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic.. Syntax 4.5. each integer constant is converted to the appropriate size based on the data or instruction type at its use. the constant begins with 0d or 0D followed by 16 hex digits.u64).s64 or . octal. there is no suffix letter to specify size. hexadecimal. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Integer literals may be written in decimal. To specify IEEE 754 doubleprecision floating point values.. zero values are FALSE and non-zero values are TRUE.5. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. When used in an instruction or data initialization.Chapter 4. These constants may be used in data initialization and as operands to instructions.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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s64 . 2nd is .u64) (.u64 same as 1st operand . Syntax 4.u64 .u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 .s64 . or .f64 integer .s64 . 2010 25 .f64 converted type constant literal + ! ~ Cast Binary (.u64.s64 .u64 .f64 use usual conversions . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 . .f64 converted type .u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 : .u64 .Chapter 4.f64 use usual conversions .s64 .f64 use usual conversions .s64.u64 .f64 same as source .s64) + . Table 5.s64 .u64 .f64 integer .5.f64 integer integer integer integer integer int ?.u64 1st unchanged.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.6.

PTX ISA Version 2.0 26 January 24. 2010 .

All variables reside in some state space. pre-defined. and level of sharing between threads.local .reg . 2010 27 . Shared.Chapter 5. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Special registers. Global texture memory (deprecated). access rights. The characteristics of a state space include its size. and properties of state spaces are shown in Table 5. Types. 5.const . State Spaces A state space is a storage area with particular characteristics. State Spaces. shared by all threads. read-only memory. Name State Spaces Description Registers. the kinds of resources will be common across platforms. The list of state spaces is shown in Table 4. Table 6. defined per-thread.shared . Addressable memory shared between threads in 1 CTA. and these resources are abstracted in PTX through state spaces and data types.1. private to each thread. . Read-only. fast. Global memory.tex January 24. or Function or local parameters.param .sreg . addressability. defined per-grid. and Variables While the specific resources available in a given target GPU will vary. access speed. Kernel parameters.global . Local memory. platform-specific.

16-. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.1. For each architecture. the parameter is then located on the stack frame and its address is in the .global .local state space.param and st. Device function input parameters may have their address taken via mov. Registers may be typed (signed integer. The most common use of 8-bit registers is with ld.sreg) state space holds predefined. 2010 .tex Restricted Yes No3 5. 2 Accessible via ld. i.0 Table 7. CTA. and performance monitoring registers. and will vary from platform to platform. Registers differ from the other state spaces in that they are not fully addressable. register variables will be spilled to memory.reg . 32-. and thread parameters. 64-. st. The number of registers is limited. 1 Accessible only via the ld. 32-.local . Registers may have alignment boundaries required by multi-word loads and stores.reg state space) are fast storage locations. or 128-bits. such as grid. causing changes in performance. All special registers are predefined. it is not possible to refer to the address of a register. Register State Space Registers (. 3 Accessible only via the tex instruction.e. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). scalar registers have a width of 8-.param instruction. 5.shared .. and cvt instructions. Special Register State Space The special register (. platform-specific registers.PTX ISA Version 2. or 64-bits. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . unsigned integer. When the limit is exceeded. floating point. predicate) or untyped.2. Address may be taken via mov instruction. or as elements of vector tuples.1. clock counters. 28 January 24.1.param (as input to kernel) . Register size is restricted.param (used in functions) .sreg .param instructions. and vector registers have a width of 16-.const . aside from predicate registers which are 1-bit.

where the size is not known at compile time. Use ld. If another thread sees the variable b change. For the current devices. the stack is in local memory. In implementations that support a stack. If no bank number is given. // load second word 5. 5. This reiterates the kind of parallelism available in machines that run PTX.const) state space is a read-only memory.const[bank] modifier.global.global) state space is memory that is accessible by all threads in a context.global. Banks are specified using the . Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.1. State Spaces. The size is limited. each pointing to the start address of the specified constant bank.b32 const_buffer[]. 2010 29 . For any thread in a context. st. Sequential consistency is provided by the bar. The constant memory is organized into fixed size banks. Global State Space The global (. an incomplete array in bank 2 is accessed as follows: .extern . where bank ranges from 0 to 10. [const_buffer+4]. It is the mechanism by which different CTAs and different grids can communicate. Threads wait at the barrier until all threads in the CTA have arrived.4. To access data in contant banks 1 through 10. the declaration .local and st. there are eleven 64KB banks.sync instruction are guaranteed to be visible to any reads after the barrier instruction.5. Local State Space The local state space (. all addresses are in global memory are shared. initialized by the host. Types.b32 %r1.global to access global variables. the store operation updating a may still be in flight.Chapter 5.1. ld. For example. This pointer can then be used to access the entire 64KB constant bank. Constant State Space The constant (. and Variables 5. the bank number must be provided in the state space of the load instruction. The remaining banks may be used to implement “incomplete” constant arrays (in C. whereas local memory variables declared January 24.3.const[2] .const[2] . and atom. results in const_buffer pointing to the start of constant bank two.local to access local variables. Consider the case where one thread executes the following two assignments: a = a + 1. b = b – 1. Module-scoped local memory variables are stored at fixed addresses. Threads must be able to do their work without waiting for other threads to do theirs. as it must be allocated on a perthread basis. Multiple incomplete array variables declared in the same bank become aliases. bank zero is used. Global memory is not sequentially consistent.local) is private memory for each thread to keep its own data. bank zero is used for all statically-sized constant variables. By convention.const[2]. for example). It is typically standard memory with cache.1.sync instruction. as in lock-free and wait-free style programming.b32 const_buffer[]. All memory writes prior to the bar.extern . Use ld. For example.

param state space and is accessed using ld.u32 %n.0 and requires target architecture sm_20.6. In implementations that do not support a stack. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.u32 %ptr. Note: The location of parameter space is implementation specific.0 within a function or kernel body are allocated on the stack. device function parameters were previously restricted to the register state space. . . PTX code should make no assumptions about the relative locations or ordering of . %n.param space variables.b32 N. all local memory variables are stored at fixed addresses and recursive function calls are not supported. Therefore. Similarly. The use of parameter state space for device function parameters is new to PTX ISA version 2. For example. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.f64 %d. in some implementations kernel parameters reside in global memory.u32 %n. read-only variables declared in the .u32 %n. … 30 January 24. ld. No access protection is provided between parameter and global space in this case. … Example: .reg . [%ptr]. The resulting address is in the .reg .param .param. typically for passing large structures by value to a function.1.f64 %d. 2010 . len.param. ld.1. ld.param state space. (2a) to declare formal input and return parameters for device functions called from within kernel execution.1.reg .param. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Kernel Function Parameters Each kernel function definition includes an optional list of parameters.align 8 . [buffer].b8 buffer[64] ) { . [N]. 5.param .entry foo ( .PTX ISA Version 2. Note that PTX ISA versions 1. 5.param instructions. Values passed from the host to the kernel are accessed through these parameter variables using ld. Parameter State Space The parameter (.param space. The address of a kernel parameter may be moved into a register using the mov instruction. Example: . per-kernel versus per-thread).u32 %ptr.param instructions.6. These parameters are addressable.x supports only kernel function parameters in . The kernel parameter variables are shared across all CTAs within a grid.param .param) state space is used (1) to pass input arguments from the host to the kernel. mov.entry bar ( .b32 len ) { .

param. … See the section on function call syntax for more details.6.s32 [mystruct+8].0 extends the use of parameter space to device function parameters. 2010 31 .f64 %d. x. [buffer]. passed to foo … . ld.param space is also required whenever a formal parameter has its address taken within the called function. and so the address will be in the . … } // code snippet from the caller // struct { double d.s32 x. int y. and Variables 5.f64 [mystruct+0].param and function return parameters may be written using st. . Example: // pass object of type struct { double d.local state space and is accessed via ld. mystruct). [buffer+8].param space variable.param byte array variable that represents a flattened C structure or union.2.param. This will be passed by value to a callee.align 8 .Chapter 5. it is illegal to write to an input parameter or read from a return parameter. call foo. dbl.local and st. In this case.reg . Aside from passing structures by value.param.param. the caller will declare a locally-scoped . Types. } mystruct.reg . the address of a function input parameter may be moved into a register using the mov instruction. }.f64 %d. int y.s32 %y.param formal parameter having the same size and alignment as the passed argument.reg . Device Function Parameters PTX ISA version 2. (4.1. st.align 8 . which declares a .f64 dbl. The most common use is for passing objects by value that do not fit within a PTX register. . . … st. In PTX. such as C structures larger than 8 bytes. is flattened. State Spaces. .func foo ( .reg .reg .b8 mystruct. . Typically.b32 N.param . ld. .b8 buffer[12] ) { . Function input parameters may be read via ld.param. January 24.param .local instructions. Note that the parameter will be copied to the stack if necessary. a byte array in parameter space is used. It is not possible to use mov to get the address of a return parameter or a locally-scoped .s32 %y.

Another is sequential access from sequential threads. a legacy PTX definitions such as .u64. Shared State Space The shared (. See Section 5. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). An address in shared memory can be read and written by any thread in a CTA.texref tex_a. 2010 . Texture memory is read-only.tex directive is retained for backward compatibility.global state space.u32 . Shared memory typically has some optimizations to support the sharing.tex variables are required to be defined in the global scope. One example is broadcast.0 5. where all threads read from the same address.PTX ISA Version 2.global .1. Example: . tex_d. Use ld. 32 January 24. An error is generated if the maximum number of physical resources is exceeded. and .u32 .u32 tex_a. where texture identifiers are allocated sequentially beginning with zero. The . tex_d. tex_f. 5.tex . A texture’s base address is assumed to be aligned to a 16-byte boundary.shared to access shared variables. For example. It is shared by all threads in a context.tex .tex state space are equivalent to module-scoped . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.u32 tex_a.tex .tex . Multiple names may be bound to the same physical texture identifier. is equivalent to . Physical texture resources are allocated on a per-module granularity. The texture name must be of type . tex_c.1.tex .u32 .8.7. and variables declared in the .shared and st. Texture State Space (deprecated) The texture (.6 for its use in texture instructions.3 for the description of the .texref variables in the . The .7. and programs should instead reference texture memory through variables of type .shared) state space is a per-CTA region of memory for threads in a CTA to share data.texref.tex directive will bind the named texture memory variable to a hardware texture identifier.tex) state space is global memory accessed via the texture instruction.texref type and Section 8.u32 or .

For example. . and Variables 5. . 2010 33 .s16. Types 5. st.b16. . all variables (aside from predicates) could be declared using only bit-size types. For convenience.f64 types.2. The .u64 . The bitsize type is compatible with any fundamental type having the same size.b64 .u8. January 24. The same typesize specifiers are used for both variable definitions and for typing instructions.f64 types. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. so that narrow values may be loaded. or converted to other types and sizes. The following table lists the fundamental type specifiers for each basic type: Table 8. State Spaces. . and . so their names are intentionally short. .f32 and . Register variables are always of a fundamental type. All floating-point instructions operate only on . Two fundamental types are compatible if they have the same basic type and are the same size. ld.f32 and .f16. A fundamental type specifies both a basic type and a size.2. and instructions operate on these types.u32. Restricted Use of Sub-Word Sizes The . .s32.2.u16. In principle. stored.u8.2. Operand types and sizes are checked against instruction types for compatibility. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . . .b32.s64 .b8.f32. the fundamental types reflect the native data types supported by the target architectures. st. Signed and unsigned integer types are compatible if they have the same size.f64 . stored. needed to fully specify instruction behavior. and cvt instructions.pred Most instructions have one or more type specifiers. and converted using regular-width registers. Types. Fundamental Types In PTX.f16 floating-point type is allowed only in conversions to and from .Chapter 5. . 5.s8.s8. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. . but typed variables enhance program readability and allow for better operand type checking.1. .b8 instruction types are restricted to ld.

and surface descriptor variables. and query instructions. passed as a parameter to functions.0 5. sust. sured). sampler.3.. since these properties are defined by . the resulting pointer may be stored to and loaded from memory. 34 January 24. Referencing textures.samplerref variables. and .{u32.texref. . but the pointer cannot otherwise be treated as an address. In the independent mode. accessing the pointer with ld and st instructions. texture and sampler information each have their own handle. Retrieving the value of a named member via query instructions (txq. suld. or surfaces via texture and surface load/store instructions (tex. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. field ordering. The following tables list the named members of each type for unified and independent texture modes. 2010 . The three built-in types are .u64} reg. texture and sampler information is accessed through a single . i. In the unified mode. hence the term “opaque”. Sampler. For working with textures and samplers. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. store.e. or performing pointer arithmetic will result in undefined results. suq). and Surface Types PTX includes built-in “opaque” types for defining texture. Creating pointers to opaque variables using mov. and overall size is hidden to a PTX program.PTX ISA Version 2. allowing them to be defined separately and combined at the site of usage in the program. In independent mode the fields of the .texref handle. but all information about layout. samplers. and de-referenced by texture and surface load. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists.texref type that describe sampler properties are ignored. These types have named fields similar to structures.samplerref.surfref. base address. PTX has two modes of operation. Texture. opaque_var.

mirror. Member width height depth Opaque Type Fields in Unified Texture Mode .samplerref values N/A N/A N/A N/A nearest. 2010 35 . mirror. clamp_ogl.Chapter 5.texref values . 1 nearest.texref values in elements in elements in elements 0. clamp_to_edge. Member width height depth Opaque Type Fields in Independent Texture Mode .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge. clamp_ogl. clamp_to_border N/A N/A N/A N/A N/A .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. linear wrap. linear wrap. and Variables Table 9. Types. State Spaces. 1 ignored ignored ignored ignored . clamp_to_border 0.

When declared at module scope. .PTX ISA Version 2. these variables are declared in the .global state space.param state space.texref my_texture_name. Example: . 36 January 24.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.surfref my_surface_name. .samplerref my_sampler_name. these variables must be in the . the types may be initialized using a list of static expressions assigning values to the named members. At module scope.texref tex1. filter_mode = nearest }. .global .global .global . As kernel parameters.global . Example: .global . 2010 .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.

Three-element vectors may be handled by using a . This is a common case for three-dimensional grids. . // a length-4 vector of floats .u16 uv.4. 2010 37 . 0.f32 bias[] = {-1. 1. 0. its type and size. vector variables are aligned to a multiple of their overall size (vector length times base-type size). . // a length-4 vector of bytes By default.f32 v0.s32 i. Variable Declarations All storage for data is specified with variable declarations.pred p.global .Chapter 5.4.v4. // typedef .global . State Spaces.4. its name.f32 accel. where the fourth element provides padding.v4 .v4 vector. r. an optional initializer. 0}.0}. and they may reside in the register space. Variables In PTX. Examples: .global . A variable declaration names the space in which the variable resides.v4 .reg .b8 v. Vectors must be based on a fundamental type.struct float4 { . Predicate variables may only be declared in the register state space.shared .const . q. 5.struct float4 coord. Types.global . .0.v3 }. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. and an optional fixed address for the variable. // a length-2 vector of unsigned ints .reg . .f64 is not allowed. etc.reg . January 24. . Every variable must reside in one of the state spaces enumerated in the previous section. .2.v2 or .u8 bg[4] = {0. an optional array size.v2 . Examples: . 5. textures. for example. PTX supports types for simple aggregate objects such as vectors and arrays.u32 loc. .1.global . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .v4 . a variable declaration describes both the variable’s type and its state space. Vectors cannot exceed 128-bits in length. In addition to fundamental types.f32 V. and Variables 5.v1.v4. Vectors Limited-length vector types are supported.v2.

1.global . . {0. . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. variable initialization is supported only for constant and global state spaces..0 5. ..shared .{. Array Declarations Array declarations are provided to allow the programmer to reserve space.global . Similarly.3. this can be used to initialize a jump table to be used with indirect branches or calls. .s32 n = 10.0.. 5. The size of the dimension is either a constant expression.{.s32 offset[][] = { {-1..pred.u32 or . Examples: . Variable names appearing in initializers represent the address of the variable. this can be used to statically initialize a pointer to a variable.4.0}}. The size of the array specifies how many elements should be reserved. For the kernel declaration above.0. 19*19 (361) halfwords are reserved (722 bytes).global . {0.u8 mailbox[128]. .1}. -1}.05. // address of rgba into ptr Currently.v4 .global . To declare an array.u8 rgba[3] = {{1.1.u64..global . where the variable name is followed by an equals sign and the initial value or values for the variable. Variables that hold addresses of variables or instructions should be of type .1.1.0}. being determined by an array initializer. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). 1} }. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. or is left empty..u16 kernel[19][19].1. Initializers are allowed for all types except .f16 and .local .PTX ISA Version 2. 2010 . {1.05}}.4.4.4. label names appearing in initializers represent the address of the next instruction following the label. {0. 0}.0.05.0. 0}. 38 January 24. Here are some examples: . A scalar takes a single value.0}. {0.b32 ptr = rgba.05}.f32 blur_kernel[][] = {{.

5.2. and may be preceded by an alignment specifier. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. 2010 39 .0.. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.reg . …. January 24.b32 %r<100>.6. Parameterized Variable Names Since PTX supports virtual registers. The default alignment for vector variables is to a multiple of the overall vector size. These 100 register variables can be declared as follows: . not for individual elements. Elements are bytes. . The variable will be aligned to an address which is an integer multiple of byte-count.align 4 . For arrays. The default alignment for scalar and array variables is to a multiple of the base-type size. of . PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.0. nor are initializers permitted. named %r0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.const . Types. Alignment is specified using an optional .0.Chapter 5. Array variables cannot be declared this way. For example. it is quite common for a compiler frontend to generate a large number of register names. and Variables 5. suppose a program uses a large number. %r1.4.0. Examples: // allocate array at 4-byte aligned address.0}. State Spaces.b32 variables. // declare %r0.4. %r99. alignment specifies the address alignment for the starting address of the entire array. %r1..b8 bar[8] = {0. 5.0. . say one hundred. Rather than require explicit declaration of every name.align byte-count specifier immediately following the state-space specifier..

PTX ISA Version 2.0 40 January 24. 2010 .

2010 41 . Instruction Operands 6. January 24. Instructions ld and st move data from/to addressable state spaces to/from registers. The mov instruction copies data between registers. and c. . Integer types of a common size are compatible with each other.2. 6. q.1.3. The bit-size type is compatible with every type having the same size. Predicate operands are denoted by the names p. The result operand is a scalar or vector variable in the register state space. st. s.reg register state space. the sizes of the operands must be consistent. b. Most instructions have an optional predicate guard that controls conditional execution. Source Operands The source operands are denoted in the instruction descriptions by the names a. so operands for ALU instructions must all be in variables declared in the . PTX describes a load-store machine. The cvt (convert) instruction takes a variety of operand types and sizes. as its job is to convert from nearly any data type to any other data type (and size). The ld.Chapter 6. Each operand type must be compatible with the type determined by the instruction template and instruction type. and cvt instructions copy data from one location to another. Operand Type Information All operands in instructions have a known type from their declarations. and a few instructions have additional predicate source operands. For most operations. mov. 6. r. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. There is no automatic conversion between types.

reg . there is no support for C-style pointer arithmetic.reg .4.global .f32 V.4. tbl.s32 mov. r0. Examples include pointer arithmetic and pointer comparisons.f32 W. 2010 . . and Vectors Using scalar variables as operands is straightforward. Address expressions include variable names. The mov instruction can be used to move the address of a variable into a pointer.v4 . .s32 q. Load and store operations move data between registers and locations in addressable state spaces.reg .u16 ld. The syntax is similar to that used in many assembly languages. address registers. address register plus byte offset.u32 42 January 24.v4 . . Here are a few examples: . Arrays. 6. W.shared . Using Addresses.0 6.PTX ISA Version 2.const . and vectors. ld.1. The interesting capabilities begin with addresses.reg . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.f32 ld.u16 x.s32 tbl[256].b32 p. arrays. .gloal. p. and immediate address expressions which evaluate at compile-time to a constant address. [tbl+12]. The address is an offset in the state space in which the variable is declared. [V].v4.[x].const. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.u16 r0. . All addresses and address computations are byte-based.shared. . q.

y V. .u32 s.g. a[N-1].d}.reg . say {Ra.y.b and . V2. Vectors as Operands Vector operands are supported by a limited subset of instructions.a 6.3.u32 s.w = = = = V. // move address of a[1] into s 6.global. V. and the identifier becomes an address constant in the space where the array is declared.v2.u32 s. or by indexing into the array using square-bracket notation. .4.d}. The registers in the load/store operations can be a vector.x. mov.v4. where the offset is a constant expression that is either added or subtracted from a register variable. The expression within square brackets is either a constant integer.z V. Rc.4. a register variable. as well as the typical color fields . Rd}.global. Arrays as Operands Arrays of all types can be declared.r V. Array elements can be accessed using an explicitly calculated byte address.4.v4. A brace-enclosed list is used for pattern matching to pull apart vectors.f32 {a.w.global. The size of the array is a constant in the program. b.global.c.z and .4. . which may improve memory performance. Vector loads and stores can be used to implement wide loads and stores. Instruction Operands 6.reg .u32 {a. . or a braceenclosed list of similarly typed scalars.f32 a.2.b. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. for use in an indirect branch or call. which include mov. a[0]. Examples are ld. [addr+offset].Chapter 6. c. January 24. . or a simple “register with constant offset” expression. Vector elements can be extracted from the vector with the suffixes .v4 . st. Here are examples: ld.b V.f32 ld. it must be written as an address calculation prior to use.c. ld. mov. If more complicated indexing is desired. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.a.b. Elements in a brace-enclosed vector. Vectors may also be passed as arguments to called functions. [addr+offset2]. 2010 43 . d. ld. . and in move instructions to get the address of the label or function into a register.f32 V.r.x V.g V. and tex. Rb. a[1].

if a cvt. and ~131. logic.5. Type Conversion All operands to all arithmetic. Operands of different sizes or types must be converted prior to the operation.s32.0 6.5. 6.000 for f16). Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. except for operations where changing the size and/or type is part of the definition of the instruction. 2010 . 44 January 24. and data movement instruction must be of the same type and size.1. For example.u16 instruction is given a u16 source operand and s32 as a destination operand. the u16 is zero-extended to s32.PTX ISA Version 2.

s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. January 24.s16.u32 targeting a 32-bit register will first chop to 16-bits. f2u = float-to-unsigned.Chapter 6. s2f = signed-to-float. Instruction Operands Table 11. zext = zero-extend. For example. f2f = float-to-float. then sign-extend to 32-bits. 2010 45 . u2f = unsigned-to-float. Notes 1 If the destination register is wider than the destination format. f2s = float-to-signed. chop = keep only low bits that fit. The type of extension (sign or zero) is based on the destination format. the result is extended to the destination register width after chopping. cvt.

rm .rpi Integer Rounding Modifiers Description round to nearest integer. Modifier .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rmi .rz . The following tables summarize the rounding modifiers.rzi . Rounding Modifiers Conversion instructions may specify a rounding modifier.rn . Table 12. Modifier . 2010 . there are four integer rounding modifiers and four floating-point rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.PTX ISA Version 2. In PTX.rni .0 6. choosing even integer if source is equidistant between two integers.2.5.

Table 11 gives estimates of the costs of using different kinds of memory.6. first access is high Notes January 24. The register in a store operation is available much more quickly. while global memory is slowest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Much of the delay to memory can be hidden in a number of ways. Operand Costs Operands from different state spaces affect the speed of an operation.Chapter 6. Table 14. Registers are fastest. Another way to hide latency is to issue the load instructions as early as possible. 2010 47 . Instruction Operands 6. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution.

PTX ISA Version 2.0 48 January 24. 2010 .

stack-based ABI. These include syntax for function definitions. At the call. NOTE: The current version of PTX does not implement the underlying.func foo { … ret. together these specify the function’s interface. and is represented in PTX as follows: . execution of the call instruction transfers control to foo. Abstracting the ABI Rather than expose details of a particular calling convention. The simplest function has no parameters or return values. } … call foo. arguments may be register variables or constants. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. so recursion is not yet supported. parameter passing. A function definition specifies both the interface and the body of the function. the function name. support for variadic functions (“varargs”). … Here. we describe the features of PTX needed to achieve this hiding of the ABI. implicitly saving the return address. 7. stack layout. and Application Binary Interface (ABI). and return values may be placed directly into register variables. Function declarations and definitions In PTX. and an optional list of input parameters. 2010 49 . The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Scalar and vector base-type input and return parameters may be represented simply as register variables. January 24.Chapter 7. and memory allocated on the stack (“alloca”).func directive. A function declaration specifies an optional list of return parameters. function calls. A function must be declared or defined prior to being called. functions are declared and defined using the . Execution of the ret instruction within foo transfers control to the instruction following the call. In this section. or prototype.1.

c2. }. py). passed by value to a function: struct { double dbl. %rd.b8 [py+ 9].s32 out) bar (.b8 [py+10].u32 %ptr.param. c4. … ld. . [y+10]. ld.func (.reg . ld.param. } … call (%r1).param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 c2. Since memory accesses are required to be aligned to a multiple of the access size.u32 %res.b8 .param .b64 [py+ 0].f64 field are aligned.4).param state space is used to pass the structure by value: . [y+9].func (.param variable y is used in function definition bar to represent a formal parameter. ld. st.b8 c3. [y+0].param .u32 %inc ) { add. } { . 2010 . . %rc2.align 8 y[12]) { . a . %rc1. consider the following C structure. (%r1.c4. … In this example.reg .reg .b8 c1. 50 January 24.0 Example: . char c[4].param space call (%out).param. st.f64 f1. For example. st. inc_ptr. . %inc. %rc2.param. (%x. ret.c1.reg .f64 f1. [y+11].param. bumpptr.c3.param.u32 %res) inc_ptr ( .param.b8 . %ptr. [y+8].reg . c3. ld. … st.b8 [py+ 8]. Second. st. In PTX.b32 c1. note that . First.reg .param. // scalar args in .reg space. byte array in .s32 x.param.reg . %rc1.f1.align 8 py[12].PTX ISA Version 2. c2. … … // computation using x.param space variables are used in two ways. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param.b8 c4. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . a .param space memory. The .b8 [py+11]. this structure will be flattened into a byte array.

2010 51 .param space formal parameters that are byte arrays. Parameters in . Note that the choice of . In the case of . The following restrictions apply to parameter passing. the corresponding argument may be either a .param or . Abstracting the ABI The following is a conceptual way to think about the . • • Arguments may be .param or .param variables or .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.reg space formal parameters.param memory must be aligned to a multiple of 1.reg space variable of matching type and size. 4. • The . In the case of . or 16 bytes.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. size. Supporting the . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. and alignment of parameters. size.param and ld.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param arguments. a .reg or . For . The . or a constant that can be represented in the type of the formal parameter. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. or constants.param byte array is used to collect together fields of a structure being passed by value.param argument must be declared within the local scope of the caller.g. • • • For a callee. The . For a callee.reg variables. This enables backend optimization and ensures that the . or a constant that can be represented in the type of the formal parameter.reg state space can be used to receive and return base-type scalar and vector values. January 24.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.. Typically. the argument must also be a .param state space is used to receive parameter values and/or pass return values back to the caller. • The .param variables.reg space variable with matching type and size. .reg variables. • • • Input and return parameters may be .reg state space in this way provides legacy support.Chapter 7. all st.param state space use in device functions. and alignment. For a caller. In the case of . A . 8.param space formal parameters that are base-type scalar or vector variables. the corresponding argument may be either a . 2.param space byte array with matching type. For a caller.param instructions used for argument passing must be contained in the basic block with the call instruction.

0 continues to support multiple return registers for sm_1x targets.x. PTX 1. formal parameters were restricted to .reg state space. Objects such as C structures were flattened and passed or returned using multiple registers. formal parameters may be in either . and .1. and a .1. In PTX ISA version 2.reg or . For sm_2x targets. 2010 .param state space.0 restricts functions to a single return value. PTX 2. and there was no support for array parameters.0.PTX ISA Version 2. Changes from PTX 1.x In PTX ISA version 1.0 7.param byte array should be used to return objects that do not fit into a register. 52 January 24.param space parameters support arrays.x supports multiple return values for this purpose. PTX 2.

Chapter 7. the size may be 1. In PTX.u32 b. .reg . mov.u32 ptr. ret. %va_arg. This handle is then passed to the %va_arg and %va_arg64 built-in functions. call %va_end. 2010 53 . . ctr. } … call (%max).u32 ap.func (.func (. setp. (ap. for %va_arg64.func %va_end (. Abstracting the ABI 7. (2. along with the size and alignment of the next data value to be accessed. call (ap).reg .u32 align) . 4. Variadic functions NOTE: The current version of PTX does not support variadic functions.u32 sz. following zero or more fixed parameters: .reg . The function prototypes are defined as follows: . 2. . 8. . For %va_arg.func baz ( .reg .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. or 8 bytes.2.u32 N. %r2.func (.b32 result. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . or 16 bytes. call (val). (ap).. … %va_start returns Loop: @p Done: January 24. or 4 bytes. In both cases. 0x8000000. (3.h and varargs. PTX provides a high-level mechanism similar to the one provided by the stdarg. bra Loop. 2.reg .s32 result ) maxN ( . and end access to a list of variable arguments. %r3). %s2).func okay ( … ) Built-in functions are provided to initialize.b32 ctr. N. the alignment may be 1.ge p.func ( .reg . maxN. 2. iteratively access. val. bra Done.reg .reg .reg . %va_end is called to free the variable argument list handle.h headers in C. 0. .s32 result. variadic functions are declared with an ellipsis at the end of the input parameter list. %va_start.reg . %s1.s32 val. ) { . … call (%max).reg .reg .u32 align) .u32 sz.reg . .reg .u32. .u32 a. … ) . Once all arguments have been processed.u32 ptr.reg . .pred p. ctr. the size may be 1.reg .b32 val) %va_arg (. 4. // default to MININT mov. To support functions with a variable number of arguments. 4.reg . result..u32 ptr) %va_start . 4). %r1. max. maxN.b64 val) %va_arg64 (.

54 January 24.func ( . Alloca NOTE: The current version of PTX does not support alloca.0 7. defined as follows: .PTX ISA Version 2.local instructions. 2010 . The array is then accessed with ld. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. a function simply calls the built-in function %alloca.reg .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.local and st.reg . If a particular alignment is required. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.u32 ptr ) %alloca ( .3. To allocate memory.

a. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. opcode D.2.s32. A. followed by some examples that attempt to show several possible instantiations of the instruction. opcode D. opcode D. A. b. the semantics are described. opcode A. PTX Instructions PTX instructions generally have from zero to four operands. In addition to the name and the format of the instruction. B. setp. We use a ‘|’ symbol to separate multiple destination registers. // p = (a < b). B. For instructions that create a result value. and C are the source operands. The setp instruction writes two destination registers.lt p|q.Chapter 8. C. the D operand is the destination operand. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. q = !(a < b). January 24. For some instructions the destination operand is optional. Instruction Set 8. B. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. 8.1. while A. 2010 55 .

predicate registers are virtual and have .reg .s32 p. predicate registers can be declared as . Instructions without a guard predicate are executed unconditionally. j.s32 p. j.PTX ISA Version 2.lt. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. As an example. So. Predicates are most commonly set as the result of a comparison performed by the setp instruction. where p is a predicate variable. n. i. 1. optionally negated. consider the high-level code if (i < n) j = j + 1. bra L1. the following PTX instruction sequence might be used: @!p L1: setp. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.3. // p = (i < n) // if i < n. Predicated Execution In PTX.s32 j.pred p. add 1 to j To get a conditional branch or conditional function call. q.pred as the type specifier. use a predicate to control the execution of the branch or call instructions. branch over 56 January 24. add. 1. n. add. … // compare i to n // if false. To implement the above example as a true conditional branch.s32 j.0 8. i. This can be written in PTX as @p setp. 2010 .lt.

unsigned integer. lt (less-than). le (less-than-or-equal). The following table shows the operators for signed integer. Comparisons 8. The bit-size comparisons are eq and ne. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). ordering comparisons are not defined for bit-size types.Chapter 8. If either operand is NaN.3. hi (higher). Table 15. lo (lower).1. ls (lower-or-same). ge. le. Unsigned Integer. ne (not-equal).1.1. ne. ne. Table 16. and bitsize types. gt. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.3. and ge (greater-than-or-equal). the result is false.1. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. 2010 57 .3. gt (greater-than). lt. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. The unsigned comparisons are eq.2. Instruction Set 8. and hs (higher-or-same).

PTX ISA Version 2. geu. unordered versions are included: equ. gtu.0 To aid comparison operations in the presence of NaN values. Table 17. num returns true if both operands are numeric values (not NaN). ltu. or. 2010 .2. leu. two operators num (numeric) and nan (isNaN) are provided. and no direct way to load or store predicate register values.1. and nan returns true if either operand is NaN. Table 18. setp can be used to generate a predicate from an integer. not.u32 %r1. and mov. // convert predicate to 32-bit value 58 January 24.0. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. If either operand is NaN. If both operands are numeric values (not NaN). then these comparisons have the same result as their ordered counterparts. then the result of these comparisons is true.3. xor. neu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. There is no direct conversion between predicates and integer values. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. for example: selp. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.%p. However.

most notably the data conversion instruction cvt. cvt.u16 d. It requires separate type-size modifiers for the result and source.uX ok ok ok inv .sX ok ok ok inv . different sizes).fX ok ok ok ok January 24. a. Example: . For example.e.Chapter 8.reg . add. i. a. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 d. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. Type Checking Rules Operand Type . Floating-point types agree only if they have the same size. b.reg . they must match exactly..bX . and integer operands are silently cast to the instruction type if needed. b. Table 19. the add instruction requires type and size information to properly perform the addition operation (signed.sX . • The following table summarizes these type checking rules. unsigned. Instruction Set 8. For example. and these are placed in the same order as the operands.uX . and this information must be specified as a suffix to the opcode.u16 a.4.fX ok inv inv ok Instruction Type .f32. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. a. . 2010 59 .bX .u16 d. For example: .reg .f32 d. float. Signed and unsigned integer types agree provided they have the same size.

When used with a floating-point instruction type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. stored.0 8. 4. the cvt instruction does not support . parse error. for example. stored. no conversion needed. Floating-point source registers can only be used with bit-size or floating-point instruction types.bX instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. The following table summarizes the relaxed type-checking rules for source operands. Notes 3. The data is truncated to the instruction-type size and interpreted according to the instruction type. Source register size must be of equal or greater size than the instruction-type size. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. For example. unless the operand is of bit-size type.4. st. ld. 60 January 24. floating-point instruction types still require that the operand type-size matches exactly. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. the data will be truncated. Operand Size Exceeding Instruction-Type Size For convenience. inv = invalid. or converted to other types and sizes.1. 1. and converted using regular-width registers. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. so that narrow values may be loaded. Bit-size source registers may be used with any appropriately-sized instruction type. “-“ = allowed. When used with a narrower bit-size type. so those rows are invalid for cvt. 2. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. When a source operand has a size that exceeds the instruction-type size. 2010 . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. the size must match exactly. Table 20. Note that some combinations may still be invalid for a particular instruction.PTX ISA Version 2.

parse error. The data is signextended to the destination register width for signed integer instruction types. Notes 3. Instruction Set When a destination operand has a size that exceeds the instruction-type size. inv = Invalid. The following table summarizes the relaxed type-checking rules for destination operands. the data is sign-extended. the destination data is zero. 1. 2. Floating-point destination registers can only be used with bit-size or floating-point instruction types. and is zero-extended to the destination register width otherwise. When used with a narrower bit-size instruction type. Destination register size must be of equal or greater size than the instruction-type size. When used with a floatingpoint instruction type. the data is zeroextended.Chapter 8. zext = zero-extend. Table 21. otherwise. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. 2010 61 . Bit-size destination registers may be used with any appropriately-sized instruction type. “-“ = Allowed but no conversion needed. the data will be zero-extended. January 24. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. The data is sign-extended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer.or sign-extended to the size of the destination register. the size must match exactly. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. 4.

16-bit registers in PTX are mapped to 32-bit physical registers. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. so it is important to have divergent threads re-converge as soon as possible. The semantics are described using C. If all of the threads act in unison and follow a single control flow path. for many performance-critical applications. For divergent control flow. the optimizing code generator automatically determines points of re-convergence. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. If threads execute down different control flow paths.6. 62 January 24. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. this is not desirable. or conditional return. When executing on a 32-bit data path. and for many applications the difference in execution is preferable to limiting performance.1. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. These extra precision bits can become visible at the application level. 8. Divergence of Threads in Control Constructs Threads in a CTA execute together. 2010 . machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. a compiler or code author targeting PTX can ignore the issue of divergent threads. using the .6. at least in appearance. the threads are called uniform. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.uni suffix. However. and 16-bit computations are “promoted” to 32-bit computations. Therefore. At the PTX language level. until they come to a conditional control construct such as a conditional branch. the threads are called divergent. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. the semantics of 16-bit instructions in PTX is machine-specific. by a right-shift instruction. conditional function call. for example. Both situations occur often in programs. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path.0 8.PTX ISA Version 2. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.5. until C is not expressive enough. A compiler or programmer may chose to enforce portable. 8. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers.

Chapter 8. addc sub.1. Instruction Set 8.cc. the optional guard predicate is omitted from the syntax. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.7.cc. 8. 2010 63 . In the following descriptions. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instructions All PTX instructions may be predicated.7. The Integer arithmetic instructions are: add sub add.

u16.s32 .sat limits result to MININT.MAXINT (no overflow) for the size of the operation. Saturation modifier: .sat applies only to .sat applies only to . . b. add.0 Table 22.sat}. d = a + b.u64.u32. // . a. PTX ISA Notes Target ISA Notes Examples Table 23. .s32 type.s32 d.s32 type. d. . . b. a.sat}.PTX ISA Version 2.u64.z. sub.MAXINT (no overflow) for the size of the operation.s64 }. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.u32 x.0..s32 d.s16. Description Semantics Notes Performs addition and writes the resulting value into a destination register. a. d = a – b. a. Supported on all target architectures. Introduced in PTX ISA version 1.sat. . Supported on all target architectures.0.u16.u32.b.type sub{. Applies only to .type = { . Applies only to .s32 c.type = { . b.s16. .type add{. Introduced in PTX ISA version 1.1. Saturation modifier: . add Syntax Integer Arithmetic Instructions: add Add two values. @p add..c. d.s32 c.s32.s32 . .a.y. .s32. b.sat limits result to MININT. PTX ISA Notes Target ISA Notes Examples 64 January 24. add. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. sub.s64 }. // . 2010 . . .

Instruction Set Instructions add.b32 x1.CF No integer rounding modifiers. sub. No saturation. x3. a.b32 addc. Table 24. These instructions support extended-precision integer addition and subtraction. . Supported on all target architectures.s32 }.cc Add two values with carry-out.b32 x1.s32 }. x4.z3. .cc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. x2.CF No integer rounding modifiers.z4. clearing. Supported on all target architectures.cc Syntax Integer Arithmetic Instructions: add. carry-out written to CC. add.cc.y1.cc. and there is no support for setting.u32.cc. d = a + b + CC.cc.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. add. addc. Behavior is the same for unsigned and signed integers. x4.z2.CF.b32 addc. @p @p @p @p add.z3.y3. carry-out written to CC.z1.b32 addc. d = a + b.cc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.type = {. Behavior is the same for unsigned and signed integers.y4. or testing the condition code.cc. .y4. if . 2010 65 .2. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.CF) holding carry-in/carry-out or borrowin/borrow-out.cc.u32. No other instructions access the condition code.y2.b32 addc.y1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1. x3.y3. addc{.type d. Introduced in PTX ISA version 1.cc specified.cc.2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.b32 addc.cc. a.cc}.type d.Chapter 8.z4. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. x2. No saturation. b.z1.b32 addc. . b.y2.z2. @p @p @p @p add.type = { .

b32 subc. .cc.cc specified.CF No integer rounding modifiers. x4.s32 }. Introduced in PTX ISA version 1.type d.y1.PTX ISA Version 2. x3. Behavior is the same for unsigned and signed integers. sub.0 Table 26. Behavior is the same for unsigned and signed integers.b32 subc.u32. x2. borrow-out written to CC.b32 x1.type = {. .cc. x2.3.y1.b32 subc. d = a .s32 }.z1.y4.b32 x1.cc}. Introduced in PTX ISA version 1.y4.z2. . Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. No saturation. subc{. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. b. a.CF No integer rounding modifiers.cc.3.cc. d = a – b.(b + CC. .y2.u32. x4.y3.type = { .cc.z4. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. @p @p @p @p sub. 2010 .b32 subc. with borrow-out. x3.b32 subc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Supported on all target architectures.cc Syntax Integer Arithmetic Instructions: sub. b.cc.y2.b32 subc.z2. a. Supported on all target architectures.z1. if . withborrow-in and optional borrow-out. borrow-out written to CC.cc Subract one value from another.y3.type d.cc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.z4. sub.z3.z3. @p @p @p @p sub.cc.cc.CF). No saturation.

0>.s64 }.x.and 32-bit integer types.lo.fxs. .n>.s32.. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.fxs. . mul.. mul. .wide is specified. If .type = { .lo is specified. creates 64 bit result January 24.wide suffix is supported only for 16.wide // for .wide. Instruction Set Table 28. d = t<2n-1.lo variant Notes The type of the operation represents the types of the a and b operands. then d is the same size as a and b.s16 fa. n = bitwidth of type.fys. The ..s32 z. . t = a * b. d = t<n-1.fys. If .s16 fa.s16.lo.type d.wide.. b.u16. a.hi variant // for .u32. 2010 67 .0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // for .y. .hi. mul.hi or .Chapter 8. save only the low 16 bits // 32*32 bits. Supported on all target architectures. and either the upper or lower half of the result is written to the destination register.wide}. . Description Semantics Compute the product of two values. mul{. // 16*16 bits yields 32 bits // 16*16 bits. then d is twice as wide as a and b to receive the full result of the multiplication. d = t.u64.

t<n-1. .r. t<2n-1. bitwidth of type. If .PTX ISA Version 2.and 32-bit integer types.hi.s32 d. The . mad.lo is specified.wide suffix is supported only for 16. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.0> + c.a.s32.hi or .. // for .s16.wide is specified.n> + c.MAXINT (no overflow) for the size of the operation.b.s32 d. then d and c are the same size as a and b..c. b. and either the upper or lower half of the result is written to the destination register. Supported on all target architectures. @p mad. . t + c..s32 r. 68 January 24. .s64 }. If . . d.lo. a. . mad{. Saturation modifier: .wide}.p.q.lo.sat..hi variant // for .lo. . Description Semantics Multiplies two values and adds a third.type mad. then d and c are twice as wide as a and b to receive the result of the multiplication.hi..u16.u32.0 Table 29. 2010 .sat limits result to MININT.s32 type in . Applies only to . a.u64.type = { .wide // for . t n d d d = = = = = a * b. b.0. c. and then writes the resulting value into a destination register. c.lo variant Notes The type of the operation represents the types of the a and b operands.hi mode.

b.hi.Chapter 8. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type d. d = t<47. 2010 69 .. b.lo. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24. All operands are of the same type and size. d = t<31.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. 48bits.0. // low 32-bits of 24x24-bit signed multiply.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.lo}... mul24.e. mul24{. mul24.a.hi may be less efficient on machines without hardware support for 24-bit multiply.type = { . // for . and return either the high or low 32-bits of the 48-bit result. .lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.s32 d.0>. t = a * b. . January 24.hi variant // for . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.16>.s32 }.u32. Supported on all target architectures. mul24. Instruction Set Table 30. i. a.

0 Table 31. mad24.s32 type in .lo}. .hi.MAXINT (no overflow). and add a third.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. 2010 .u32.hi variant // for . All operands are of the same type and size. mad24. 48bits. Applies only to . 32-bit value to either the high or low 32-bits of the 48-bit result. Supported on all target architectures. b.lo.PTX ISA Version 2.s32 d.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. a.e.a. // for . d = t<47. t = a * b..c.s32 }. mad24.type = { .s32 d. 70 January 24. b. // low 32-bits of 24x24-bit signed multiply.0. c. d. d = t<31. mad24{.type mad24.b.. Saturation modifier: .16> + c. a.sat.hi..sat limits result of 32-bit signed addition to MININT.hi may be less efficient on machines without hardware support for 24-bit multiply..hi mode. .lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. Description Compute the product of two 24-bit integer values held in 32-bit source registers. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. c. Return either the high or low 32-bits of the 48-bit result. i. mad24.0> + c. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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} PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz. popc Syntax Integer Arithmetic Instructions: popc Population count. popc.0. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. while (a != 0) { if (a&0x1) d++. the number of leading zeros is between 0 and 64. mask = 0x8000000000000000.type == .u32 PTX ISA Notes Target ISA Notes Examples Table 40. a = a << 1. } else { max = 64.type = { . For . d = 0. if (. d = 0.type = { . a. cnt.b64 }. For . inclusively.b64 d. } while (d < max && (a&mask == 0) ) { d++. inclusively. mask = 0x80000000.b32 popc.0.0 Table 39. a.b32 type. } Introduced in PTX ISA version 2.b32) { max = 32. a.b32. X. X.b64 d. cnt.PTX ISA Version 2. . . 2010 . clz. // cnt is . a = a >> 1.b32 clz. a. popc requires sm_20 or later. popc. . Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. clz requires sm_20 or later. .u32 Semantics 74 January 24.b32.b64 }.type d.b64 type. // cnt is . clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. the number of leading zeros is between 0 and 32.type d.

for (i=msb. bfind.type bfind. X.u32.type==. i>=0.u32 d. For signed integers.s32.u32 January 24. bfind returns 0xFFFFFFFF if no non-sign bit is found. bfind. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. bfind returns the bit position of the most significant “1”.d. Instruction Set Table 41. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. and operand d has type . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shiftamt && d != -1) { d = msb .s32) ? 31 : 63. a.shiftamt is specified. Operand a has the instruction type. a. .shiftamt.s64 cnt. break. .u32. bfind requires sm_20 or later. For unsigned integers.type = { .0. 2010 75 .s64 }. Description Find the bit position of the most significant non-sign bit in a and place the result in d. . // cnt is . a. If . d = -1.u64.Chapter 8. . Semantics msb = (. } } if (. bfind.shiftamt.type==.type d. i--) { if (a & (1<<i)) { d = i. d.u32 || .

} PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i<=msb.b32. a. brev. .b32) ? 31 : 63. for (i=0. brev requires sm_20 or later.type==.type d. msb = (. Description Semantics Perform bitwise reversal of input.PTX ISA Version 2.b32 d. a. 2010 .type = { .0. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. i++) { d[i] = a[msb-i]. . 76 January 24. brev.0 Table 42.b64 }.

u64 || len==0) sbit = 0. pos = b.u32 || .msb)].type==. and operands b and c are type . Semantics msb = (. bfe. If the start position is beyond the msb of the input. .u32 || . The destination d is padded with the sign bit of the extracted field. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.0. if (. . 2010 77 . January 24. d = 0. otherwise If the bit field length is zero. The sign bit of the extracted field is defined as: . .u32. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. Source b gives the bit field starting bit position.u64. Operands a and d have the same type as the instruction type. i<=msb. the destination d is filled with the replicated sign bit of the extracted field. Description Extract bit field from a and place the zero or sign-extended result in d.u32.type d. len = c. the result is zero. and source c gives the bit field length in bits.type==. for (i=0. else sbit = a[min(pos+len-1.a.s32.s32.b32 d.type==.type==.s64 }.start.Chapter 8.s32) ? 31 : 63. . a. bfe requires sm_20 or later. .len. c.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.type = { . bfe. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. b. Instruction Set Table 43.u32. .u64: .

type = { .u32. If the bit field length is zero. f = b. Operands a. d.b32) ? 31 : 63. the result is b. pos = c. i<len && pos+i<=msb. and operands c and d are type . . the result is b.type==. i++) { f[pos+i] = a[i]. b.b32 d. 78 January 24. Semantics msb = (. bfi.type f.len. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Description Align and insert a bit field from a into b.b32. and source d gives the bit field length in bits. Source c gives the starting bit position for the insertion.start. bfi. bfi requires sm_20 or later. c. .0 Table 44. len = d.b64 }.0.b. a. and f have the same type as the instruction type.PTX ISA Version 2. b. for (i=0. If the start position is beyond the msb of the input. and place the result in f. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.a. 2010 .

b2 source select c[11:8] d.mode} d. {b3. For each byte in the target register. b5. prmt. msb=0 means copy the literal value. Instruction Set Table 45. In the generic form (no mode specified). The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. . a.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. The msb defines if the byte value should be copied. Thus. as a 16b permute code. Description Pick four arbitrary bytes from two 32-bit registers.b32{. Note that the sign extension is only performed as part of generic form. and reassemble them into a 32-bit destination register. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.mode = { .ecr.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. b6. b1. c.rc16 }. the permute control consists of four 4-bit selection values. 2010 79 . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.f4e.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. msb=1 means replicate the sign.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b3 source select c[15:12] d. . b2. b. a} = {{b7. . b4}.ecl. . a 4-bit selection value is defined. The bytes in the two source registers are numbered from 0 to 7: {b. default mode index d.Chapter 8. .b4e. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). b0}}. the four 4-bit values fully specify an arbitrary byte permute.b1 source select c[7:4] d. .rc8.

tmp64 ). ctl[1] = (c >> 4) & 0xf. tmp[15:08] = ReadByte( mode. } tmp[07:00] = ReadByte( mode. r3. r4.0 Semantics tmp64 = (b<<32) | a.b32 prmt.b32. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[3] = (c >> 12) & 0xf. ctl[2]. prmt requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r1. ctl[1]. tmp[31:24] = ReadByte( mode.f4e r1. r2. tmp64 ). r3.PTX ISA Version 2.0. 80 January 24. ctl[3]. tmp[23:16] = ReadByte( mode. prmt. r4. ctl[2] = (c >> 8) & 0xf. 2010 . tmp64 ). ctl[0]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r2.

2010 81 .2. Instruction Set 8.f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.Chapter 8.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on .7.

sub. so PTX programs should not rely on the specific single-precision NaNs being generated.approx.sub.full.rp .sqrt}.rnd.f64 {abs. If no rounding modifier is specified.neg.rm .max}.approx.f32 rsqrt. Note that future implementations may support NaN payloads for single-precision instructions.rcp.approx.ftz .f64 mad.rnd. Single-precision add.rz .sqrt}.rcp.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. . Instruction Summary of Floating-Point Instructions .cos.fma}. The optional .max}.f64 rsqrt.rnd. Double-precision instructions support subnormal inputs and results.ex2}.f64 {sin. {mad.PTX ISA Version 2. 1.f64 div.f32 . and mad support saturation of results to the range [0. Table 46. sub.f32 {abs.f32 are the same.f32 {div.lg2. 82 January 24. with NaNs being flushed to positive zero.f64 are the same. but single-precision instructions return an unspecified NaN.rn and instructions may be folded into a multiply-add. No rounding modifier.f64 and fma. mul.rnd.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 {div.sat Notes If no rounding modifier is specified.rn .0 The following table summarizes floating-point instructions in PTX.mul}.f32 {mad.rcp.0].32 and fma. default is .target sm_20 mad.target sm_20 .approx.rnd.0. . 2010 .target sm_1x No rounding modifier. default is .f32 {add.neg. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.mul}.f32 {div.sqrt}.rn and instructions may be folded into a multiply-add.fma}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. NaN payloads are supported for double-precision instructions.rnd.min.min. {add.

. f0. X. a.finite.f32.f32. B.f64 x.op.type = { . a.number testp. Instruction Set Table 47.notanumber. testp.pred = { . true if the input is a subnormal number (not NaN.infinite.0.infinite testp. Introduced in PTX ISA version 2. // result is . not infinity) As a special case. 2010 83 .normal testp.f64 isnan. Table 48.op p. copysign.f32 testp. . testp Syntax Floating-Point Instructions: testp Test floating-point property. y. testp requires sm_20 or later. testp. January 24. not infinity). b. .finite testp. copysign. A. and return the result as d.type . copysign requires sm_20 or later. .notanumber. . Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.subnormal }. . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. p. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f64 }. . C.f32 copysign.type d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .f64 }. positive and negative zero are considered normal numbers.Chapter 8.normal. .notanumber testp.type = { .infinite.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.number. testp.0. z.

rn mantissa LSB rounds to nearest even .0. .0f.f32. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures.rm. d. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.sat}. add. a. . . . add.rn. In particular.f32 add{.rnd}{.PTX ISA Version 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. add. 2010 . NaN results are flushed to +0.f64 d.rz. b. d = a + b.rp }.ftz}{. sm_1x: add.rnd}. b.rnd = { .rz mantissa LSB rounds towards zero . .rz available for all targets . subnormal numbers are supported. requires sm_20 Examples @p add.0 Table 49.sat.f2.rm. requires sm_13 for add.f64 requires sm_13 or later. 84 January 24.f64 supports subnormal numbers.f3. . add{. a.0. Rounding modifiers have the following target requirements: . Rounding modifiers (default is .rn.f32 flushes subnormal inputs and results to sign-preserving zero. 1. add Syntax Floating-Point Instructions: add Add two values.f32 clamps the result to [0.ftz. add. Saturation modifier: . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rp for add.ftz.f32 f1.f64.rz.0]. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add.rm mantissa LSB rounds towards negative infinity .rn): . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.

sub.f32 sub{. 1.rn.f32 clamps the result to [0.rn. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 flushes subnormal inputs and results to sign-preserving zero. sub. In particular.sat.f3.f64.f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples sub. sm_1x: sub.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Saturation modifier: sub.ftz.Chapter 8.f64 d. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sub Syntax Floating-Point Instructions: sub Subtract one value from another. d = a .f64 supports subnormal numbers. Rounding modifiers have the following target requirements: . d. 2010 85 .rp }. .rz. January 24.rz available for all targets . a. . sub. sub.ftz. b.f32. subnormal numbers are supported. b.rp for sub. sub{.rn): . . Instruction Set Table 50.0. Rounding modifiers (default is .rn. a. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.b.0]. .f32 f1. .sat}.rm. sub. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.ftz}{.rn mantissa LSB rounds to nearest even . requires sm_13 for sub. NaN results are flushed to +0.f32 c.f32 supported on all target architectures. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 requires sm_13 or later.b.f2.rnd}.0.rnd = { .rz mantissa LSB rounds towards zero .rnd}{.a. .0f.rm.

d = a * b.rnd = { . . Rounding modifiers (default is .ftz.f32 supported on all target architectures. .sat. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.0f. . all operands must be the same size. sm_1x: mul.rn.rm. 1.f64.f32 flushes subnormal inputs and results to sign-preserving zero.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm. subnormal numbers are supported.sat}.pi // a single-precision multiply 86 January 24.rz available for all targets . a. Rounding modifiers have the following target requirements: . mul Syntax Floating-Point Instructions: mul Multiply two values. requires sm_13 for mul. b. .0. Saturation modifier: mul.PTX ISA Version 2. Description Semantics Notes Compute the product of two values.rm mantissa LSB rounds towards negative infinity .rn): .rnd}{.f32 clamps the result to [0.f64 d.f32. In particular.f64 supports subnormal numbers.rnd}.rn mantissa LSB rounds to nearest even . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. mul{. mul.radius.f32 mul{.rp }.ftz.ftz}{. 2010 . a.0 Table 51. .f32 flushes subnormal inputs and results to sign-preserving zero. For floating-point multiplication.rz mantissa LSB rounds towards zero .rp for mul. mul. mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0.rn.0].rz. requires sm_20 Examples mul.f64 requires sm_13 or later.f32 circumf. . d. mul. NaN results are flushed to +0. b. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.

f64 introduced in PTX ISA version 1.f64 requires sm_13 or later.0f.f32 computes the product of a and b to infinite precision and then adds c to this product. d.ftz}{.ftz.a. again in infinite precision. 2010 87 . fma.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. .sat}.0.z. PTX ISA Notes Target ISA Notes Examples January 24.rnd = { .b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64.f64 w.f32 clamps the result to [0.rp }. fma Syntax Floating-Point Instructions: fma Fused multiply-add.sat. a. fma. @p fma. fma. b.0. Instruction Set Table 52. fma.rnd.rm.f32 requires sm_20 or later. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rn.ftz.f32 fma. Saturation: fma. d.rnd. . d = a*b + c. b.rz. The resulting value is then rounded to double precision using the rounding mode specified by .f32 is unimplemented in sm_1x. NaN results are flushed to +0.rn.c.f64 supports subnormal numbers. The resulting value is then rounded to single precision using the rounding mode specified by . 1.y.rn.rn mantissa LSB rounds to nearest even . c. fma.rnd. Rounding modifiers (no default): .0].Chapter 8. c. sm_1x: fma. fma. fma. .f64 d. fma.f32 fma.4.rnd{. fma.x.rz mantissa LSB rounds towards zero .f64 is the same as mad. .rm mantissa LSB rounds towards negative infinity . again in infinite precision.f64 computes the product of a and b to infinite precision and then adds c to this product. fma. a.f32 introduced in PTX ISA version 2.

b.e. Note that this is different from computing the product with mul.rn. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f32 flushes subnormal inputs and results to sign-preserving zero..f64 computes the product of a and b to infinite precision and then adds c to this product.target sm_1x: mad.rp }.ftz}{. For . 1. When JIT-compiled for SM 2.rnd.target sm_1x d. Description Semantics Notes Multiplies two values and adds a third. mad.0.target sm_20 d.ftz}{. c. For .rnd{.rm.rnd. d = a*b + c. . NaN results are flushed to +0.f64 d.target sm_13 and later . 2010 .0]. sm_1x: mad. b. mad. // . mad{.sat}. fma. again in infinite precision. c.f32. mad.f32 mad. mad. The resulting value is then rounded to single precision using the rounding mode specified by . again in infinite precision. b.f32 is when c = +/-0.f64. mad.{f32. .f64}.f64} is the same as fma.0f. The exception for mad.f32 computes the product of a and b at double precision.f32). again in infinite precision. // . but the exponent is preserved. The resulting value is then rounded to double precision using the rounding mode specified by .rnd.f32 flushes subnormal inputs and results to sign-preserving zero. . a.{f32.f32 is implemented as a fused multiply-add (i. // . Saturation modifier: mad.rnd = { .rm mantissa LSB rounds towards negative infinity .f32 mad. Rounding modifiers (no default): . mad. subnormal numbers are supported.sat}.0.rnd.f64 computes the product of a and b to infinite precision and then adds c to this product.sat.ftz.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.0 devices.rz.rz mantissa LSB rounds towards zero . Unlike mad. the treatment of subnormal inputs and output follows IEEE 754 standard.f32 clamps the result to [0.target sm_20: mad.f64 is the same as fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. mad.f64 supports subnormal numbers.PTX ISA Version 2.rn mantissa LSB rounds to nearest even .f32 computes the product of a and b to infinite precision and then adds c to this product. and then the mantissa is truncated to 23 bits.rn.f32 is identical to the result computed using separate mul and add instructions. mad. In this case. a. The resulting value is then rounded to double precision using the rounding mode specified by . a.ftz. and then writes the resulting value into a destination register. where the mantissa can be rounded and the exponent will be clamped. 88 January 24. mad.0 Table 53. c.

4 and later..f64.f64..Chapter 8.rm.f32 d.f64 requires sm_13 or later.f32 for sm_20 targets. Legacy mad. mad..f64 instructions having no rounding modifier will map to mad.rz.f32. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.f32 supported on all target architectures. January 24..rn..rn. requires sm_13 .rn.rp for mad.f64. In PTX ISA versions 2.c.0 and later.a. In PTX ISA versions 1. requires sm_20 Examples @p mad.0.rp for mad. Rounding modifiers have the following target requirements: .. Target ISA Notes mad.rm. 2010 89 . a rounding modifier is required for mad.b. a rounding modifier is required for mad.rz.

full. For b in [2-126.rz mantissa LSB rounds towards zero .approx. but is not fully IEEE 754 compliant and does not support rounding modifiers.rnd is required. Description Semantics Notes Divides a by b. div.3. z. a.rnd.rm. approximate division by zero creates a value of infinity (with same sign as a).f32 implements a fast approximation to divide. x.full. approximate single-precision divides: div.f32 flushes subnormal inputs and results to sign-preserving zero.full. subnormal numbers are supported. 2010 .rp}. For PTX ISA versions 1.f64 defaults to div.rn. The maximum ulp error is 2 across the full range of inputs. yd. .rn. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . PTX ISA Notes div.f32 supported on all target architectures. stores result in d. div. d.f64 supports subnormal numbers.ftz. div Syntax Floating-Point Instructions: div Divide one value by another. Fast.f32 implements a relatively fast. zd. one of .f32 div. .rnd{.approx.rn mantissa LSB rounds to nearest even . // // // // fast. div.ftz}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd = { .4. b. a.rm mantissa LSB rounds towards negative infinity . or .14159.3. d. a. Target ISA Notes div.f32 and div.{rz. sm_1x: div. div.PTX ISA Version 2.0.f32. Fast. a. 2126].ftz.f32 and div.4 and later. d. Examples 90 January 24. For PTX ISA version 1.0 Table 54.ftz.0 through 1. .circum.ftz}.f32 div.ftz}.f32 div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .approx.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.rn. b. full-range approximation that scales operands to achieve better accuracy. and div. div. b. computed as d = a * (1/b). div.rn. . Explicit modifiers . .full{. b.approx{. div.f64 requires sm_20 or later. xd. the maximum ulp error is 2.f32 requires sm_20 or later.f64 requires sm_13 or later.f64 introduced in PTX ISA version 1.rp }.approx. and rounding introduced in PTX ISA version 1.rz. Subnormal inputs and results are flushed to sign-preserving zero.full. div.ftz.full.approx.f32 defaults to div. y.f64 diam.rm.ftz.approx. .f32 div.f64.f32 div.rnd. d = a / b. div.

ftz. neg.f64 d. neg. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f32 x. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs{. Instruction Set Table 55. a. abs.f32 flushes subnormal inputs and results to sign-preserving zero. d. abs. subnormal numbers are supported. Take the absolute value of a and store the result in d.ftz.f0.0. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. NaN inputs yield an unspecified NaN. abs. neg{.f64 requires sm_13 or later. d. 2010 91 . a. subnormal numbers are supported.Chapter 8.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. Negate the sign of a and store the result in d. neg.f32 supported on all target architectures. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 x. abs. sm_1x: neg.ftz. neg.ftz. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. January 24.f64 requires sm_13 or later.f32 abs. sm_1x: abs. NaN inputs yield an unspecified NaN. a. neg.f32 flushes subnormal inputs and results to sign-preserving zero.f32 neg. Subnormal numbers: sm_20: By default.f0.ftz}. Table 56. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs. d = |a|.0. d = -a.f64 supports subnormal numbers.f32 supported on all target architectures. Subnormal numbers: sm_20: By default.

b. d.f64 z. max. min. 2010 . a. max.f64 supports subnormal numbers.f64 d. d d d d = = = = NaN.f64 requires sm_13 or later. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 supported on all target architectures.f64 f0. min{.0 Table 57. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.f32 max. max.f64 d. max{. 92 January 24.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. a.b. b.ftz.x. subnormal numbers are supported.c. d d d d = = = = NaN. (a > b) ? a : b. min. d.ftz}. a. b. sm_1x: max. b. b.f32 flushes subnormal inputs and results to sign-preserving zero. Table 58. Store the minimum of a and b in d. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later. max.0.z.f64 supports subnormal numbers.f2. a.ftz. Store the maximum of a and b in d.f32 max.f1. a. min.f32 flushes subnormal inputs and results to sign-preserving zero.f32 min.c.ftz. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. @p min. (a < b) ? a : b.0.PTX ISA Version 2.f32 supported on all target architectures.f32 min. a. a. a. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.b. subnormal numbers are supported. min. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. max. sm_1x: min.

For PTX ISA version 1.approx and . subnormal numbers are supported. one of .rn. and rcp.rz mantissa LSB rounds towards zero .f64 d.rm.rn.f32 supported on all target architectures. Target ISA Notes rcp.f32 flushes subnormal inputs and results to sign-preserving zero. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.3.0 +subnormal +Inf NaN Result -0.rnd is required.0.f64 requires sm_20 or later.approx.rm mantissa LSB rounds towards negative infinity . a. The maximum absolute error is 2-23.rn.f64 supports subnormal numbers. Input -Inf -subnormal -0. Instruction Set Table 59.0. . rcp.0-2. store result in d.approx.x. rcp.approx.0 through 1.rn. d.{rz. .f32 implements a fast approximation to reciprocal.f64 requires sm_13 or later.rn mantissa LSB rounds to nearest even .r.f32 rcp.approx or .f64 and explicit modifiers . rcp.ftz.f32 rcp.rm. sm_1x: rcp. a.0 over the range 1.f64 defaults to rcp.ftz}. rcp.ftz.f32 and rcp.rp}.0 -Inf -Inf +Inf +Inf +0.ftz were introduced in PTX ISA version 1.f32 requires sm_20 or later.f64 ri. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. General rounding modifiers were added in PTX ISA version 2.rn.f32 flushes subnormal inputs and results to sign-preserving zero.4.rnd = { .rnd.rn.Chapter 8.f32 rcp.f64. xi.approx{. For PTX ISA versions 1. rcp. Description Semantics Notes Compute 1/a.f32 defaults to rcp.0 +0.approx.0. rcp. a. Examples January 24. 2010 93 .x.4 and later.f64 introduced in PTX ISA version 1. . PTX ISA Notes rcp.rnd{.ftz.rnd. rcp. rcp.ftz}. d = 1 / a.rp }. rcp.ftz. xi.f32 rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . d. // fast.f32.rz. rcp.

approx or .rp }. sqrt.0.f32 sqrt.f64 d.f64 supports subnormal numbers.f32 sqrt.ftz.approx.rn.rz mantissa LSB rounds towards zero .rn. subnormal numbers are supported.rn.x. // IEEE 754 compliant rounding d.rn. a. and sqrt. r. . sqrt. sqrt.rz. Input -Inf -normal -subnormal -0.{rz. a. Examples 94 January 24.rp}.approx and .f32 flushes subnormal inputs and results to sign-preserving zero.rm mantissa LSB rounds towards negative infinity .0 Table 60.rn.0 +0.0.f32.f64 defaults to sqrt. The maximum absolute error for sqrt. For PTX ISA version 1.f32 is TBD.ftz.rn mantissa LSB rounds to nearest even .0 through 1.f64 introduced in PTX ISA version 1.rnd.rm.ftz.f64 r. sqrt. d = sqrt(a).3.f64 requires sm_20 or later.rnd{.f32 sqrt.f32 defaults to sqrt. .rnd = { .0 -0. sqrt.rnd is required. Description Semantics Notes Compute sqrt(a).ftz}.ftz were introduced in PTX ISA version 1.0 +0. PTX ISA Notes sqrt.x.f32 implements a fast approximation to square root.f32 supported on all target architectures. sqrt.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . approximate square root d.x.approx.f64. General rounding modifiers were added in PTX ISA version 2. 2010 . .ftz.approx. one of . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. sm_1x: sqrt.f32 requires sm_20 or later. sqrt. sqrt.approx.f32 and sqrt.4 and later.0 +subnormal +Inf NaN Result NaN NaN -0.rn.4.approx.rm. // fast. For PTX ISA versions 1.0 +0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sqrt. a. Target ISA Notes sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt. r.f64 and explicit modifiers . store in d.rnd.approx{.f64 requires sm_13 or later.ftz}. // IEEE 754 compliant rounding .PTX ISA Version 2.f32 sqrt.

d.f64 isr. For PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.0 NaN The maximum absolute error for rsqrt.approx implements an approximation to the reciprocal square root.f32 defaults to rsqrt. The maximum absolute error for rsqrt.f64 requires sm_13 or later.4 over the range 1. Explicit modifiers .approx. rsqrt.f32 rsqrt. For PTX ISA versions 1.approx and . Input -Inf -normal -subnormal -0.approx{.f32 rsqrt.approx. Instruction Set Table 61.0 +0.f64 supports subnormal numbers. and rsqrt. X.f32. January 24. rsqrt. rsqrt. rsqrt. 2010 95 .0.ftz were introduced in PTX ISA version 1.0 through 1.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. x. rsqrt.f64 defaults to rsqrt.4. rsqrt.4 and later. subnormal numbers are supported. PTX ISA Notes rsqrt. ISR.ftz.f64 were introduced in PTX ISA version 1. Target ISA Notes Examples rsqrt. a. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f32 and rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. d = 1/sqrt(a).f32 is 2-22.0.approx.f64.Chapter 8.f64 d.approx.f64 is emulated in software and are relatively slow.approx modifier is required. the .f64 is TBD. Note that rsqrt.ftz. Compute 1/sqrt(a).3.0-4.ftz.f32 supported on all target architectures.approx. a. Subnormal numbers: sm_20: By default. rsqrt. sm_1x: rsqrt. store the result in d.approx.

0 NaN NaN The maximum absolute error is 2-20.f32 d. For PTX ISA versions 1. sin. Find the sine of the angle a (in radians).ftz}.0 +0. Subnormal numbers: sm_20: By default.0. For PTX ISA version 1. a. 96 January 24.approx. sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. sm_1x: Subnormal inputs and results to sign-preserving zero.approx{.f32 implements a fast approximation to sine.9 in quadrant 00.ftz.approx and .f32 flushes subnormal inputs and results to sign-preserving zero.0 +0.0 -0. subnormal numbers are supported.0 through 1.approx modifier is required.approx.0 +subnormal +Inf NaN Result NaN -0.0 +0.ftz.ftz introduced in PTX ISA version 1.f32 sa. 2010 . a.f32 introduced in PTX ISA version 1.f32. sin. Input -Inf -subnormal -0. Explicit modifiers . the .ftz.approx.4. PTX ISA Notes sin.f32 defaults to sin.3. sin.4 and later. Target ISA Notes Examples Supported on all target architectures. d = sin(a).0 Table 62.PTX ISA Version 2. sin.

Input -Inf -subnormal -0.f32.Chapter 8.0 +subnormal +Inf NaN Result NaN +1. PTX ISA Notes cos.0 through 1. cos. Subnormal numbers: sm_20: By default. cos.approx{.0 +1. Instruction Set Table 63.approx.f32 implements a fast approximation to cosine. January 24.0 +0.ftz. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero.ftz. cos. cos. For PTX ISA versions 1. a.approx modifier is required.0. Target ISA Notes Examples Supported on all target architectures. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.9 in quadrant 00.f32 introduced in PTX ISA version 1.approx. subnormal numbers are supported. For PTX ISA version 1.0 +1. cos.0 +1. a.0 NaN NaN The maximum absolute error is 2-20. d = cos(a). 2010 97 .ftz.f32 defaults to cos.ftz introduced in PTX ISA version 1.ftz}.4. the .3.f32 d.f32 ca.4 and later. Find the cosine of the angle a (in radians).approx and . sm_1x: Subnormal inputs and results to sign-preserving zero.approx.

approx and . lg2.approx. Subnormal numbers: sm_20: By default.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. For PTX ISA versions 1.f32 introduced in PTX ISA version 1.approx. lg2.approx modifier is required. Target ISA Notes Examples Supported on all target architectures. lg2.approx{. subnormal numbers are supported. lg2. the .3.ftz introduced in PTX ISA version 1.4.0.ftz}. a. 98 January 24. Input -Inf -subnormal -0. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to log2(a).f32 defaults to lg2. The maximum absolute error is 2-22. d = log(a) / log(2).6 for mantissa.f32 Determine the log2 of a. For PTX ISA version 1. PTX ISA Notes lg2.0 through 1.0 +0.approx. lg2.4 and later.ftz.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 64. Explicit modifiers . a.ftz.ftz.f32. 2010 .f32 la.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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c). .0. num returns true if both operands are numeric values (not NaN). p. hi.pred variables. p[|q].ftz. .f64 source type requires sm_13 or later.type = { . geu. gt. . le.b. and can be one of: eq. ltu. sm_1x: setp.lt.dtype. nan The Boolean operator BoolOp(A. @q setp. 2010 . A related value computed using the complement of the compare result is written to the second destination operand. ge.PTX ISA Version 2.r. leu.s32 setp.f64 supports subnormal numbers.u32. then the result of these comparisons is true. lt. lt. or.0 Table 67.ftz applies only to . a.u16.f64 }. higher. hs equ.f32. . the comparison operators lo. . The destinations p and q must be . ls. . setp. lo.CmpOp. q = BoolOp(!t. If either operand is NaN.f32 flushes subnormal inputs to sign-preserving zero. gt. .s16. . p[|q]. setp with . c). and nan returns true if either operand is NaN. ge. bit-size comparisons are eq and ne. . This result is written to the first destination operand.type . gt. loweror-same. .f32 comparisons.b64. ls. leu. hi.CmpOp{.eq. and higher-or-same may be used instead of lt. ge. ltu. ne. unordered versions are included: equ. ge. lt.s32. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. Modifier .b16. The comparison operator is a suffix on the instruction. setp. the result is false. Applies to all numeric types. If both operands are numeric values (not NaN).a. and (optionally) combine this result with a predicate value by applying a Boolean operator. neu. gtu. le. The untyped. b. le. gt. To aid comparison operations in the presence of NaN values. ne. For unsigned values. xor. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. p = BoolOp(t.and. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.type setp.n. then these comparisons have the same result as their ordered counterparts. 102 January 24. num. subnormal numbers are supported. and hs for lower.BoolOp{.u32 p|q.dtype. ne. {!}c. If either operand is NaN.dtype. The signed and unsigned comparison operators are eq.b32.u64. Integer Notes Floating Point Notes The ordered comparisons are eq. Subnormal numbers: sm_20: By default. geu. setp. b.i. le.ftz}. respectively.s64.ftz}.B) is one of: and. gtu. neu. Semantics t = (a CmpOp b) ? 1 : 0.f32 flushes subnormal inputs to sign-preserving zero.

If c is True. a. . based on the sign of the third operand.u16. a. Operands d. . . . and b are treated as a bitsize type of the same width as the first instruction type. c. C.ftz}. and operand a is selected. d. . slct.f64 requires sm_13 or later. . . b.type = { . Modifier . fval.f32 r0. . slct. .b16. . selp.b32.s16. selp Syntax Comparison and Selection Instructions: selp Select between source operands. slct Syntax Comparison and Selection Instructions: slct Select one source operand.s16. Operands d.ftz.b32. subnormal numbers are supported.dtype. negative zero equals zero. Description Conditional selection.u64. . a. @q selp.u64. b otherwise.dtype. a.xp. Semantics Floating Point Notes January 24. slct.s32.r.ftz.type d.f32.0. sm_1x: slct. d = (c == 1) ? a : b.dtype = { . The selected input is copied to the output without modification.u32. c.s32 selp. .s32 slct{.g. 2010 103 . a.f32.f32 d.p. and operand a is selected. a is stored in d. val. . .0.u64. Introduced in PTX ISA version 1.t.f32 comparisons.f64 requires sm_13 or later.f64 }.u32.s64. . . . .x. If operand c is NaN.b16.f32 flushes subnormal values of operand c to sign-preserving zero. Subnormal numbers: sm_20: By default. d = (c >= 0) ? a : b. otherwise b is stored in d.f32 flushes subnormal values of operand c to sign-preserving zero. selp. . and b must be of the same type.f64 }. b. .ftz applies only to . B.Chapter 8.s32 x. based on the value of the predicate source operand. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. slct. c. Table 69. .b64. f0.f32 A.s32.dtype.u32. y. b. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.dtype. slct. Instruction Set Table 68.u16. operand c must match the second instruction type. z. the comparison is unordered and operand b is selected.b64. If c ≥ 0. a is stored in d. . For . Operand c is a predicate.f32 comparisons.s64.

7. This permits bit-wise operations on floating point values without having to define a union to access the bits. performing bit-wise operations on operands of any type.0 8.PTX ISA Version 2. Instructions and. 2010 . and not also operate on predicates. provided the operands are of the same size. or. xor. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.4. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.

Introduced in PTX ISA version 1.q. but not necessarily the type.b32.fpvalue.b32 x. The size of the operands must match. or. Instruction Set Table 70.0. Supported on all target architectures. d = a & b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.pred. but not necessarily the type. and. .b64 }.type = { . d = a | b. a. January 24. 2010 105 . or Syntax Logic and Shift Instructions: or Bitwise OR.type d. or.0. b.0x80000000. .b32 and. . sign.q.b32 mask mask. Introduced in PTX ISA version 1. a.Chapter 8. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type d.r. .r.b64 }. Allowed types include predicate registers. and Syntax Logic and Shift Instructions: and Bitwise AND. b.pred p. Table 71.b16.type = { . . Allowed types include predicate registers. . and.0x00010001 or. . Supported on all target architectures. The size of the operands must match.b16. .b32.pred.

xor.b16. .type d. The size of the operands must match. d = a ^ b.type d. d = ~a.b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. 106 January 24.a.0. a.pred p. one’s complement. . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.type = { .b16.mask. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. Supported on all target architectures. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. but not necessarily the type. not Syntax Logic and Shift Instructions: not Bitwise negation. a. . d.q.type = { .b32 d. Introduced in PTX ISA version 1. 2010 .type = { . but not necessarily the type. b. . Allowed types include predicates. . Allowed types include predicate registers. Supported on all target architectures.b32.b16. Table 73. . The size of the operands must match. d = (a==0) ? 1 : 0.type d.b64 }.q.x. . not.b32 xor. . Introduced in PTX ISA version 1.b16 d. Introduced in PTX ISA version 1. but not necessarily the type. . not.r. xor.0.b32 mask.b32.0. Table 74. cnot.0x0001. Supported on all target architectures.pred. The size of the operands must match.b64 }.PTX ISA Version 2. a. . cnot.pred.0 Table 72.b32. not.

Instruction Set Table 75.u16 shr. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. but not necessarily the type.1.s64 }.b32. unsigned and untyped shifts fill with 0. k. The b operand must be a 32-bit value. . Signed shifts fill with the sign bit. shr.b16. The sizes of the destination and first source operand must match.s32 shr. shl Syntax Logic and Shift Instructions: shl Shift bits left. Introduced in PTX ISA version 1.b32 q. .i. Supported on all target architectures. The sizes of the destination and first source operand must match. .type d.a.u32. . a.b16.b32. regardless of the instruction type.type = { .s32. Supported on all target architectures.b64 }. zero-fill on right. The b operand must be a 32-bit value. b. Introduced in PTX ISA version 1.a. PTX ISA Notes Target ISA Notes Examples Table 76. .type d.2. . . shl.j.0.type = { . regardless of the instruction type. . PTX ISA Notes Target ISA Notes Examples January 24.u64. . shr.0. . but not necessarily the type.2. shl. b.u16.b64. 2010 107 . Shift amounts greater than the register width N are clamped to N. .i. Shift amounts greater than the register width N are clamped to N.s16. a. d = a << b. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.Chapter 8.b16 c. Bit-size types are included for symmetry with SHL. i. d = a >> b. shr Syntax Logic and Shift Instructions: shr Shift bits right. . sign or zero fill on left.

2010 . st. or shared state spaces. ldu. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. Data Movement and Conversion Instructions These instructions copy data from place to place.5. Instructions ld. ld.0 8. and from state space to state space. suld. and st operate on both scalar and vector types. and sust support optional cache operations. local. prefetchu isspacep cvta cvt 108 January 24. The cvta instruction converts addresses between generic and global.7. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. possibly converting it from one format to another.PTX ISA Version 2. mov.

rather than the data stored by the first thread. if the line is fully covered.1. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. The ld. any existing cache lines that match the requested address in L1 will be evicted. and a second thread loads that address via a second L1 cache with ld. The compiler / programmer may use ld.cs is applied to a Local window address.cg to cache loads only globally. .lu Last use. likely to be accessed again.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. A ld.cs. Global data is coherent at the L2 level. when applied to a local address.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. to allow the thread program to poll a SysMem location written by the CPU. but multiple L1 caches are not coherent for global data.Chapter 8. the second thread may get stale L1 cache data.0 introduces optional cache operators on load and store instructions. bypassing the L1 cache.7. and cache only in the L2 cache. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. The default load instruction cache operation is ld. Cache Operators PTX 2.ca. invalidates (discards) the local L1 line following the load.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. not L1).ca loads cached in L1. The ld. Table 77. The cache operators require a target architecture of sm_20 or later. 2010 109 .cs Cache streaming. .lu instruction performs a load cached streaming operation (ld.cg Cache at global level (cache in L2 and below. The ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. Use ld.cv Cache as volatile (consider cached system memory lines stale. When ld. .lu load last use operation. evict-first. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. it performs the ld.cv to a frame buffer DRAM address is the same as ld. . For sm_20 and later. the cache operators have the following definitions and behavior. January 24. If one thread stores to global memory via one L1 cache.cs) on global addresses. Operator .lu operation. Instruction Set 8. As a result of this request.5. likely to be accessed once.ca. fetch again). The ld.

cg to cache global store data only globally. and a second thread in a different SM later loads from that address via a different L1 cache with ld.wb could write-back global store data from L1.wt. Addresses not in System Memory use normal write-back.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. If one thread stores to global memory. likely to be accessed once. The st.PTX ISA Version 2.0 Table 78. 110 January 24. st.cg is the same as st. . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wt Cache write-through (to system memory). In sm_20. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. and marks local L1 lines evict-first. 2010 .wb. which writes back cache lines of coherent cache levels with normal eviction policy. Future GPUs may have globally-coherent L1 caches. to allow a CPU program to poll a SysMem location written by the GPU with st. and discard any L1 lines that match. regardless of the cache operation.cg Cache at global level (cache in L2 and below. the second thread may get a hit on stale L1 cache data. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. in which case st. . Global stores bypass L1. .cs Cache streaming.ca. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. Use st.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. not L1). The st. bypassing its L1 cache. Operator .ca loads. and cache only in the L2 cache. rather than get the data from L2 or memory stored by the first thread.wt store write-through operation applied to a global System Memory address writes through the L2 cache. bypassing the L1 cache.cg to local memory uses the L1 cache. but st. The default store instruction cache operation is st.wb for global data. However.

u64.const.type mov. label.b16. u.s16. k.type mov. d. A[5]. the address of the variable in its state space) into the destination register. i. A. ptr. mov places the non-generic address of the variable (i.s32. // get address of variable // get address of label or function .0. variable in an addressable memory space. sreg.local. addr. Introduced in PTX ISA version 1. . Write register d with the value of a. . 2010 111 . .type mov.. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.a.shared state spaces.b64. alternately. immediate. .f64 }. . myFunc.u32 mov. or shared state space may be taken directly using the cvta instruction. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.u32.f32. local. d = &avar.u16. Take the non-generic address of a variable in global. d = &label. the generic address of a variable declared in global.e.e.type d.f32 mov. . .f64 requires sm_13 or later.u32 mov.v. avar. Operand a may be a register. local.u32 d. mov.s64.f32 mov. d. local. Note that if the address of a device function parameter is moved to a register. or function name. label.b32. The generic address of a variable in global.1. .global. . For variables declared in . Instruction Set Table 79. d = sreg. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. // address is non-generic. mov. mov.pred. ptr.type = { .. .Chapter 8. special register. the parameter will be copied onto the stack and the address will be in the local state space. Semantics d = a. Description . and .0. . within the variable’s declared state space Notes Although only predicate and bit-size types are required. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. or shared state space. . a.u16 mov. d.

y.b32 // pack two 16-bit elements into . mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b32.b64 // pack two 32-bit elements into .. a[16.b16 // pack four 8-bit elements into .63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b64 mov.31]. // // // // a.b have type .b64 112 January 24.7].x. Description Write scalar register d with the packed value of vector register a.y } = { a[0. a[32. a[8.z << 16) | (a.w}.b64 }.b32 mov..0..x | (a.{a.15]. d. a[16.a have type . %r1.y } = { a[0.y. d. a[32.y << 8) d = a... a.b64 { d.. d.PTX ISA Version 2..y } = { a[0.b16 { d.a}.hi}..{x.. 2010 . or write vector register d with the unpacked values from scalar register a.b. a[48.b32 // pack four 16-bit elements into .w << 48) d = a. mov.b32 %r1.63] } // unpack 16-bit elements from . d.u16 %x is a double.b32 { d.u32 x. . For bit-size types. {r...y.z.b32 { d. %x.z << 32) | (a. Supported on all target architectures.w } = { a[0.y.z.z. d.g..x | (a. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.23].hi are . a[16.x.w } = { a[0.z.x.u8 // unpack 32-bit elements from .31] } // unpack 8-bit elements from .7].x. {lo.%r1..y << 16) | (a.x.15] } // unpack 8-bit elements from .w << 24) d = a.x | (a.31].. mov.b16.b8 r.y << 16) d = a.0 Table 80. d.type = { . lo. .b}.47].15].g.x | (a. d. Semantics d = a.y << 8) | (a.15].31] } // unpack 16-bit elements from .b.w have type . a[8. d.type d.x | (a.b32 mov. .b64 { d. a[24. d. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.y << 32) // pack two 8-bit elements into .

b8.vec = { . . i.volatile may be used with .b16.ss}.type = { .global and . 32-bit).lu. If an address is not properly aligned.ss}.0. d. d.f32.ss}{. The address size may be either 32-bit or 64-bit.u16. *(immAddr).0. . .const.cop = { .u64. ld introduced in PTX ISA version 1. . . ld{. Generic addressing may be used with ld. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.cv }. and then converted to . . . . . .b16. an integer or bit-size type register reg containing a byte address.cop}.e.type d. In generic addressing.type ld.shared spaces to inhibit optimization of references to volatile memory. Addresses are zero-extended to the specified width as needed. . . Generic addressing and cache operations introduced in PTX ISA 2. or [immAddr] an immediate absolute byte address (unsigned. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. [a].cop}.v2. Within these windows. 32-bit). [a]. ld.type . Semantics d d d d = = = = a.s8.f64 }. [a]. *a.u32. and truncated if the register width exceeds the state space address width for the target architecture.e.param.volatile.b32. an address maps to the corresponding location in local or shared memory.global.1.vec. .f64 using cvt.Chapter 8. to enforce sequential consistency between threads accessing shared memory. for example.reg state space.type ld{. the access may proceed by silently masking off low-order address bits to achieve proper rounding. perform the load using generic addressing. If no state space is given. 2010 113 .v4 }. and is zeroextended to the destination register width for unsigned and bit-size types. .volatile. i.cs.s16. .ca. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. *(a+immOff).volatile introduced in PTX ISA version 1. Instruction Set Table 81. The address must be naturally aligned to a multiple of the access size. .ss = { .ss}{.s64. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. d. The .volatile{. an address maps to global memory unless it falls within the local memory window or the shared memory window. .local. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . .b64. or the instruction may fault.vec. PTX ISA Notes January 24.cg.u8. A destination register wider than the specified type may be used. .f32 or .. This may be used.shared }. . Description Load register variable d from the location specified by the source address operand a in specified state space. [a].s32. the resulting behavior is undefined. ld. .const space suffix may have an optional bank number to indicate constant banks other than bank zero. .f16 data may be loaded using ld.volatile{. Cache operations are not permitted with ld. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . The value loaded is sign-extended to the destination register width for signed integers.

%r.b16 cvt. // access incomplete array x. // load .[p+4].s32 ld.[p].shared.[240]. d.b64 ld. 2010 .0 Target ISA Notes ld.const[4].f32 ld. Cache operations require sm_20 or later.b32 ld. ld.local.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.local. Generic addressing requires sm_20 or later.f32. x.f16 d.v4. // immediate address %r.[a].[buffer+64]. // negative offset %r.[p+-8].global.b32 ld.const. Q.f64 requires sm_13 or later.b32 ld.PTX ISA Version 2.%r.global.[fs].

b16. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. *(a+immOff).b32.ss}. an address maps to global memory unless it falls within the local memory window or the shared memory window. 2010 115 .ss}. . .e.f16 data may be loaded using ldu. [a].[p+4]. .b64.global }. .u64. A destination register wider than the specified type may be used. . In generic addressing. i. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. only generic addresses that map to global memory are legal.f32 d. and is zeroextended to the destination register width for unsigned and bit-size types.[a].v2.f32 or . For ldu.type ldu{. or the instruction may fault. .v4. .vec. PTX ISA Notes Target ISA Notes Examples January 24. The address must be naturally aligned to a multiple of the access size. . . // load from address // vec load from address .Chapter 8.global.u32.b32 d. If an address is not properly aligned. The addressable operand a is one of: [avar] the name of an addressable variable var.f64 requires sm_13 or later.f64 using cvt. 32-bit). *a. ldu.e. ldu. [a].0. *(immAddr). ldu{.s32. // state space . or [immAddr] an immediate absolute byte address (unsigned.s16.s8. 32-bit).u16. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and then converted to . ldu. . an address maps to the corresponding location in local or shared memory.type = { .ss = { . perform the load using generic addressing.type d. . .f32 Q. [areg] a register reg containing a byte address.f64 }. Introduced in PTX ISA version 2. Semantics d d d d = = = = a. Addresses are zero-extended to the specified width as needed. i. The address size may be either 32-bit or 64-bit. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Instruction Set Table 82.u8. Within these windows. . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. A register containing an address may be declared as a bit-size type or integer type. The data at the specified address must be read-only. the resulting behavior is undefined. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .b16..s64.global. The value loaded is sign-extended to the destination register width for signed integers.f32. d.vec = { . .v4 }.[p].global. where the address is guaranteed to be the same across all threads in the warp. . If no state space is given. .b8.reg state space. and truncated if the register width exceeds the state space address width for the target architecture. ldu.

*d = a. and truncated if the register width exceeds the state space address width for the target architecture.shared spaces to inhibit optimization of references to volatile memory.type . . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.v4 }. { . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.u16. i. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. an address maps to the corresponding location in local or shared memory. b. st. b. . for example.global. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.f16 data resulting from a cvt instruction may be stored using st. . Generic addressing may be used with st.PTX ISA Version 2. This may be used. Generic addressing requires sm_20 or later. .volatile may be used with .vec. The address size may be either 32-bit or 64-bit. Cache operations are not permitted with st.type [a].local. Within these windows. A source register wider than the specified type may be used. { .wb.v2. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.type st{. The lower n bits corresponding to the instruction-type width are stored to memory.s8.b64. an address maps to global memory unless it falls within the local memory window or the shared memory window.1. [a]. If no state space is given. . st{. 32-bit).volatile{.ss}{.shared }.ss}. b. { . PTX ISA Notes Target ISA Notes 116 January 24. .cop}. . .b32.. .s64.0.s32. 2010 .cg.vec .0 Table 83. the resulting behavior is undefined. Semantics d = a. Cache operations require sm_20 or later. .b16. b. . If an address is not properly aligned.s16.type st. *(immAddr) = a. 32-bit). .reg state space.f64 }. perform the store using generic addressing. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st introduced in PTX ISA version 1. .volatile introduced in PTX ISA version 1.volatile.0. .volatile.ss}{.ss}. Addresses are zero-extended to the specified width as needed. [a]. to enforce sequential consistency between threads accessing shared memory. .f64 requires sm_13 or later. an integer or bit-size type register reg containing a byte address.e. .e.cs. [a]. The address must be naturally aligned to a multiple of the access size. st.cop . . In generic addressing.u8.u64.u32. or the instruction may fault.b8.f32.cop}.vec.global and .volatile{. *(d+immOffset) = a. st. or [immAddr] an immediate absolute byte address (unsigned.ss .type = = = = {. i. . Generic addressing and cache operations introduced in PTX ISA 2.wt }.b16.

[fs].Q. [p]. 2010 117 .Chapter 8.f32 st.%r. // %r is 32-bit register // store lower 16 bits January 24.local.local.b. Instruction Set Examples st.b32 st.global. // negative offset [100].r7.%r.global. // immediate address %r.b16 [a]. [q+4].f32 st.s32 st.a. [q+-8].v4.local.a.s32 cvt.f16.b32 st.

global.L2 }. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. an address maps to the corresponding location in local or shared memory.L1.space = { .L1 [ptr]. prefetchu. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // prefetch to data cache // prefetch to uniform cache . prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The address size may be either 32-bit or 64-bit. 32-bit). A prefetch into the uniform cache requires a generic address. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.L1 [addr].0 Table 84. the prefetch uses generic addressing.PTX ISA Version 2.L1 [a].local }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. an address maps to global memory unless it falls within the local memory window or the shared memory window.level = { . In generic addressing. 32-bit). 2010 . prefetch. prefetch{. prefetch and prefetchu require sm_20 or later. i. . and no operation occurs if the address maps to a local or shared memory location. 118 January 24.level prefetchu.0. . . Within these windows.e. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. [a]. a register reg containing a byte address.global. and truncated if the register width exceeds the state space address width for the target architecture. Addresses are zero-extended to the specified width as needed. A prefetch to a shared memory location performs no operation. in specified state space. If no state space is given.space}. or [immAddr] an immediate absolute byte address (unsigned.

u32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shared }. // convert to generic address // get generic address of var // convert generic address to global. or shared state space.space = { . isshrd.size cvta. the generic address of the variable may be taken using cvta. . svar.space = { . a.size .u64. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.lptr.genptr.u64.shared. January 24.global isspacep.u32 or .to. .local. a. cvta. cvta. local.u32 to truncate or zero-extend addresses. Take the generic address of a variable declared in global. .space p.u32 gptr. or shared state space to generic. p.shared }. // result is . or shared address.global.space. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. p.size p. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. 2010 119 . When converting a generic address into a global. isspacep. isspacep requires sm_20 or later. For variables declared in global.global. lptr. Instruction Set Table 85.Chapter 8. The source address operand must be a register of type .shared isglbl.u64 }.space. gptr. PTX ISA Notes Target ISA Notes Examples Table 86. or shared state space.0. or vice-versa. local.u32 p.u32. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. .local. Introduced in PTX ISA version 2.local. or shared address to a generic address. The source and destination addresses must be the same size. isspacep. // local.global.to.space. . or vice-versa. islcl. A program may use isspacep to guard against such incorrect behavior. cvta requires sm_20 or later. local. a.local isspacep.pred . or shared address cvta.size = { .u64 or cvt. var.pred.u32 p. The destination register must be of type . local. local. . Use cvt.0. sptr. Description Convert a global. cvta. // get generic address of svar cvta.

i. .frnd}{. . Note: In PTX ISA versions 1.ftz. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits..s64.f32 float-to-integer conversions and cvt.f32 float-to-integer conversions and cvt. .f32 float-tofloat conversions with integer rounding. a.irnd = { .PTX ISA Version 2. subnormal numbers are supported.f32. .f16.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.sat limits the result to MININT. . . . . .MAXINT for the size of the operation. . d. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.sat For integer destination types.dtype.4 and earlier. Note that saturation applies to both signed and unsigned integer types.e.u8. The optional .s32. . cvt{.rmi. // integer rounding // fp rounding .rni.f32 float-tofloat conversions with integer rounding.rpi }. . Integer rounding modifiers: . . .rni round to nearest integer.f64 }. .u32.irnd}{. Saturation modifier: .frnd = { .0 Table 87. subnormal inputs are flushed to signpreserving zero. . sm_1x: For cvt. .f32.ftz.ftz}{.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.sat is redundant. Integer rounding is required for float-to-integer conversions. For float-to-integer conversions. choosing even integer if source is equidistant between two integers. 2010 .rn. a.ftz.rm.atype cvt{. 120 January 24.e.rzi.f32.atype d. For cvt.rp }.ftz modifier may be specified in these cases for clarity. the result is clamped to the destination range by default. Integer rounding is illegal in all other instances. . i.rmi round to nearest integer in direction of negative infinity .dtype = .dtype.sat}.u16.ftz. The compiler will preserve this behavior for legacy PTX code. the .dtype.ftz}{. and for same-size float-tofloat conversions where the value is rounded to an integer.s16. . d = convert(a).dtype.sat}. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. subnormal inputs are flushed to signpreserving zero. . . Description Semantics Integer Notes Convert between different types and sizes.u64..atype = { .s8.rz.rzi round to nearest integer in the direction of zero .

f32.f16. 1.f32.sat limits the result to the range [0. and for integer-to-float conversions.f64 types. if the PTX . Subnormal numbers: sm_20: By default. and . cvt.y.4 or earlier. result is fp cvt.f32. // float-to-int saturates by default cvt. 2010 121 . // round to nearest int.f32.f16. The optional . cvt.f16. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f32 instructions. The compiler will preserve this behavior for legacy PTX code.ftz modifier may be specified in these cases for clarity. and cvt.version is 1.f32.rni. subnormal numbers are supported. Specifically.f64. cvt to or from .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).s32.Chapter 8.0].ftz behavior for sm_1x targets January 24. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .s32 f. // note . stored in floating-point format.rz mantissa LSB rounds towards zero .0.f64 requires sm_13 or later. Applies to . cvt. Saturation modifier: .f64 j.0.f32 x. Floating-point rounding is illegal in all other instances. Introduced in PTX ISA version 1. The operands must be of the same size.f32.rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity .r. . Floating-point rounding modifiers: .f32. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f32 x. Note: In PTX ISA versions 1. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.y. . NaN results are flushed to positive zero.i.sat For floating-point destination types. Modifier . The result is an integral value.4 and earlier.

// get tex1’s txq. . r1. In the independent mode.7. and surfaces. cvt.entry compute_power ( . sampler.height. PTX supports the following operations on texture. = nearest width height tsamp1. r3. Module-scope and per-entry scope definitions of texture.. r4. // get tex1’s tex.r3.f32 r3.u32 r5. In the unified mode.f32 r1. div. sampler.f32 r1.0 8.f32 {r1.PTX ISA Version 2. r6.u32 r5. the file is assumed to use unified mode. A PTX module may declare only one texturing mode.v4.texref tex1 ) { txq.b32 r6. samplers.target options ‘texmode_unified’ and ‘texmode_independent’. and surface descriptors. r3. sampler. add. 122 January 24. with the restriction that they correspond 1-to-1 with the 128 possible textures.param . If no texturing mode is declared. The advantage of independent mode is that textures and samplers can be mixed and matched. add. [tex1.texref handle. PTX has two modes of operation. r1. r1. {f1. r5.f2}]. sampler. [tex1]. add. and surface descriptors. r5.2d.target texmode_independent .f32. . r2. allowing them to be defined separately and combined at the site of usage in the program.6. but the number of samplers is greatly restricted to 16. } = clamp_to_border. mul. . Ability to query fields within texture.f32 r1. texture and sampler information each have their own handle. The advantage of unified mode is that it allows 128 samplers. Example: calculate an element’s power contribution as element’s power/total number of elements. texture and sampler information is accessed through a single . The texturing mode is selected using .f32.width.r2. [tex1]. and surface descriptors. r5.r4}. Texturing modes For working with textures and samplers. Texture and Surface Instructions This section describes PTX instructions for accessing textures. 2010 .global .samplerref tsamp1 = { addr_mode_0 filter_mode }.. and surface descriptors: • • • Static initialization of texture.b32 r5.

f2. [a. If an address is not properly aligned.f3.s32. Notes For compatibility with prior versions of PTX. d. is a two-element vector for 2d textures.s32. . [tex_a.1d.dtype. tex. A texture base address is assumed to be aligned to a 16-byte address.v4. b.f32 {r1.r3. {f1. or the instruction may fault..s32.f32 }. Unified mode texturing introduced in PTX ISA version 1. // Example of independent mode texturing tex. Instruction Set These instructions provide access to texture and surface memory.0. An optional texture sampler b may be specified.e.f32 }. . c]. //Example of unified mode texturing tex. c].s32 {r1. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.v4 coordinate vectors are allowed for any geometry. tex txq suld sust sured suq Table 88. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32. The instruction always returns a four-element vector of 32-bit values. Description Texture lookup using a texture coordinate vector.3d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.geom. PTX ISA Notes Target ISA Notes Examples January 24.btype = { .v4. Operand c is a scalar or singleton tuple for 1d textures.r4}.geom = { . and is a four-element vector for 3d textures. the resulting behavior is undefined.v4.geom.dtype. .r4}.btype d. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.v4.r2.2d. Supported on all target architectures. {f1}].1d.Chapter 8.f4}]. the square brackets are not required and . .dtype = { .r2. [tex_a. the sampler behavior is a property of the named texture. If no sampler is specified.5.btype tex. . . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.3d }. 2010 123 . . [a. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. i.r3. where the fourth element is ignored. with the extra elements being ignored.u32. sampler_x. // explicit sampler .

addr_mode_0.texref or .tquery. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. txq. addr_mode_2 }. [tex_A]. . // texture attributes // sampler attributes . mirror.filter_mode . [tex_A]. txq.PTX ISA Version 2. In unified mode. d. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. Operand a is a . [smpl_B].b32 %r1.width.squery.addr_mode_1 .depth . addr_mode_1. [a].normalized_coords .depth.addr_mode_0. txq. 2010 .b32 d.tquery = { .5.normalized_coords }. [a]. sampler attributes are also accessed via a texref argument.samplerref variable. Integer from enum { nearest.b32 %r1.width. .squery = { . txq.height . . linear } Integer from enum { wrap.filter_mode.0 Table 89. // unified mode // independent mode 124 January 24.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).addr_mode_0 . Supported on all target architectures. clamp_to_edge. and in independent mode sampler attributes are accessed via a separate samplerref argument.height. clamp_ogl. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. Description Query an attribute of a texture or sampler.width .b32 %r1. Query: . .filter_mode.b32 txq.

trap {r1.s32 is returned.b . .s32. {x}].z. // cache operation none.f32 is returned.dtype . suld. suld. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32 is returned.cv }. [surf_A. // for suld. . If the destination type is . the resulting behavior is undefined.f32 }. Target ISA Notes Examples January 24.b. {f1.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.trap . . If the destination base type is .ca. .f2.b8 .r2}. and A components of the surface format. then .geom .s32. The .v2. and is a four-element vector for 3d surfaces. i.v4. then .b16.Chapter 8.0. Coordinate elements are of type . suld. the surface sample elements are converted to .cop . Instruction Set Table 90. .b supported on all target architectures. SNORM. suld Syntax Texture and Surface Instructions: suld Load from surface memory.vec . or FLOAT data.cop}. .b performs an unformatted load of binary data.clamp suld.geom{.p .geom{. .p requires sm_20 or later. sm_1x targets support only the .f32 based on the surface format as follows: If the surface format contains UNORM.clamp . A surface base address is assumed to be aligned to a 16-byte address. .b.w}].cop}. . {x.clamp.clamp = = = = = = { { { { { { d.v4 }. additional clamp modifiers.clamp . [a. is a two-element vector for 2d surfaces. suld.s32. where the fourth element is ignored.f3.v2. G. suld.3d }. . suld. If an address is not properly aligned.vec.trap suld. The lowest dimension coordinate represents a sample offset rather than a byte offset.p is currently unimplemented.5..b32.trap introduced in PTX ISA version 1.b64. 2010 125 . . b]. // formatted . suld. Operand a is a .dtype . if the surface format contains SINT data. .cg.zero }. [a. // for suld. suld. size and type conversion is performed as needed to convert from the surface sample format to the destination type.e.trap.b64 }.3d.clamp field specifies how to handle out-of-bounds addresses: . if the surface format contains UINT data.surfref variable.u32.1d.cs.dtype. // unformatted d.p.b.f4}. .y. B. then . Description Load from surface memory using a surface coordinate vector. . [surf_B. . . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.s32. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. b]. and cache operations introduced in PTX ISA version 2.v4.u32.dtype. . or .p. Operand b is a scalar or singleton tuple for 1d surfaces.f32.1d.f32.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. or . or the instruction may fault. Cache operations require sm_20 or later. Destination vector elements corresponding to components that do not appear in the surface format are not written.b32.b32.trap clamping modifier. the access may proceed by silently masking off low-order address bits to achieve proper rounding.3d requires sm_20 or later.p.u32. and the size of the data transfer matches the size of destination operand d.2d. . suld. .

additional clamp modifiers. the resulting behavior is undefined. sust. or . The source data is then converted from this type to the surface sample format.v2. size and type conversions are performed as needed between the surface sample format and the destination type. then .wt }.trap . If the source base type is . Surface sample components that do not occur in the source vector will be written with an unpredictable value.p.p requires sm_20 or later. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. if the surface format contains UINT data. b]. . .f32. and is a four-element vector for 3d surfaces. .v2.f32 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .cop .f4}.u32 is assumed.1d. 2010 . . sust. then . The . The size of the data transfer matches the size of source operand c.trap clamping modifier.f32 is assumed.geom .cop}.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.y.b // for sust. Operand a is a .trap sust. . . Operand b is a scalar or singleton tuple for 1d surfaces.5.u32. . or the instruction may fault.zero }.clamp = = = = = = { { { { { { [a.r2}.{u32.0. A surface base address is assumed to be aligned to a 16-byte address.cop}. sust. {x. .ctype.s32.v4 }.f2.trap [surf_A. G. . . sm_1x targets support only the . [surf_B.geom{.3d requires sm_20 or later.b. b]. sust. . {x}]. B.geom{. then .v4. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.PTX ISA Version 2. sust. . sust.e. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.vec. sust.s32. . Target ISA Notes Examples 126 January 24.f32} are currently unimplemented.vec .w}]. The source vector elements are interpreted left-to-right as R.clamp . // for sust.b32. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. and A surface components.ctype. .surfref variable. . if the surface format contains SINT data.trap.b.b performs an unformatted store of binary data. // unformatted // formatted .wb. [a. sust Syntax Texture and Surface Instructions: sust Store to surface memory.clamp . none.s32.1d.trap introduced in PTX ISA version 1.clamp sust. c. .2d.f32. Source elements that do not occur in the surface sample are ignored. {f1. . Cache operations require sm_20 or later.b.3d }.b64 }. where the fourth element is ignored.ctype .p performs a formatted store of a vector of 32-bit data values to a surface sample. . The lowest dimension coordinate represents a sample offset rather than a byte offset.b32.b64. These elements are written to the corresponding surface sample components.z.p. and cache operations introduced in PTX ISA version 2.p.cs. or FLOAT data. SNORM. i.p.f3.cg. sust. sust. Coordinate elements are of type .b16. If the source type is ..clamp.b8 .clamp field specifies how to handle out-of-bounds addresses: . If an address is not properly aligned. is a two-element vector for 2d surfaces.p Description Store to surface memory using a surface coordinate vector.b supported on all target architectures.u32.s32. c.s32 is assumed. {r1.0 Table 91.3d.vec.b32.ctype .

p performs a reduction on sample-addressed 32-bit data.clamp. January 24.trap sured. i.u32. Operand b is a scalar or singleton tuple for 1d surfaces.surfref variable. .s32.3d }.min. . Coordinate elements are of type .b32 type. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. Instruction Set Table 92.b . then .u64 data.p .e. // byte addressing sured. 2010 127 .u32. sured. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. and is a four-element vector for 3d surfaces.zero }.p. r1. Operand a is a .u32. . [surf_B.u32. sured.u64. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32 is assumed.trap.2d.ctype = { .u32 based on the surface sample format as follows: if the surface format contains UINT data.1d. // for sured.max. and the data is interpreted as . . .clamp . operations and and or apply to .op = { .clamp = { .0.b.min.and.u32 and . the resulting behavior is undefined. .u64.b32 }.geom = { . where the fourth element is ignored.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // for sured. A surface base address is assumed to be aligned to a 16-byte address.b32.ctype.or }. The lowest dimension coordinate represents a sample offset rather than a byte offset.Chapter 8.s32 types. and . The instruction type is restricted to .c.clamp [a. {x}]..geom.s32.geom.y}].s32.b32. if the surface format contains SINT data. . then .trap .u32 is assumed. sured requires sm_20 or later. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. .c. If an address is not properly aligned.b performs an unformatted reduction on . . .b32 }. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .p. Operations add applies to . or the instruction may fault. min and max apply to .s32 types.clamp [a.op.op. . . . . // sample addressing .ctype.b.b32. The .ctype = { . r1.b]. or . sured. sured.trap [surf_A.s32 or . Reduction to surface memory using a surface coordinate vector.add.b]. . is a two-element vector for 2d surfaces.clamp field specifies how to handle out-of-bounds addresses: .2d. {x.add.1d.

128 January 24.b32 %r1. . Description Query an attribute of a surface.depth }. Supported on all target architectures. .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.b32 d.height. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. suq.query = { .width.width.height .0 Table 93.PTX ISA Version 2.query.surfref variable. suq. [a]. Operand a is a .5. 2010 . .width . [surf_A]. Query: .

s32 a. { add. ratio.b.a.y. Supported on all target architectures. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. {} Syntax Description Control Flow Instructions: { } Instruction grouping. Instruction Set 8. @{!}p instruction.c.s32 d.0.f32 @q bra L23. Threads with a false guard predicate do nothing.0.7.7.f32 @!p div. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. If {!}p then instruction Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Supported on all target architectures. p. setp. mov.x. 2010 129 . { instructionList } The curly braces create a group of instructions. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Table 95.0.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Execute an instruction or instruction block for threads that have the guard predicate true.eq. used primarily for defining a function body.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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red.{arrive. The barrier instructions signal the arrival of the executing threads at the named barrier.red should not be intermixed with bar.red also guarantee memory ordering among threads identical to membar. Register operands.sync and bar. and the barrier is reinitialized so that it can be immediately reused. Each CTA instance has sixteen barriers numbered 0.sync with an immediate barrier number is supported for sm_1x targets. In addition to signaling its arrival at the barrier.u32 bar.red performs a reduction operation across threads.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. b}.0.cta.popc is the number of threads with a true predicate.0. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.popc). Thus. 2010 133 . d. p. Thus. the bar. bar.sync bar.red} require sm_20 or later. the optional thread count must be a multiple of the warp size. thread count.sync or bar.sync without a thread count introduced in PTX ISA 1.Chapter 8.and and . if any thread in a warp executes a bar instruction. In conditionally executed code. Description Performs barrier synchronization and communication within a CTA. The reduction operations for bar.sync) until the barrier count is met. Register operands. Instruction Set Table 100. all threads in the CTA participate in the barrier. bar.red are population-count (. and bar. PTX ISA Notes Target ISA Notes Examples bar.{arrive. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). it is as if all the threads in the warp have executed the bar instruction.red delays the executing threads (similar to bar. the final value is written to the destination register in all threads waiting at the barrier. Operand b specifies the number of threads participating in the barrier. and d have type . bar.arrive a{. bar. bar. January 24. bar. threads within a CTA that wish to communicate via memory can store to memory. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). b.arrive does not cause any waiting by the executing threads. The result of . All threads in the warp are stalled until the barrier completes. and then safely read values stored by other threads prior to the barrier. {!}c. If no thread count is specified. a{.u32. and any-thread-true (. and bar.and). Note that a non-zero thread count is required for bar.or). bar. . When a barrier completes. operands p and c are predicates.15. b}. Execution in this case is unpredictable.popc. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.arrive. Operands a.version 2. Once the barrier count is reached.op. the waiting threads are restarted without delay. a{.sync or bar. a.sync 0.red. b}.red} introduced in PTX .op = { . Barriers are executed on a per-warp basis as if all the threads in a warp are active. {!}c. bar. Only bar.or }. b.. all-threads-true (. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.arrive using the same active barrier.sync and bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.red performs a predicate reduction across the threads participating in the barrier. Since barriers are executed on a per-warp basis. while .and. it simply marks a thread's arrival at the barrier.red instruction. thread count. execute a bar. bar.pred .

gl} introduced in PTX .sys. or system memory level. by st.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.{cta.version 1. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl will typically have a longer latency than membar. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. . . membar. membar. A memory read (e. .sys introduced in PTX .gl} supported on all target architectures.gl.sys Waits until all prior memory requests have been performed with respect to all clients.0. For communication between threads in different CTAs or even different SMs.cta. membar.PTX ISA Version 2.cta.4.gl. membar.version 2.0 Table 101. membar. including thoses communicating via PCI-E such as system and peer-to-peer memory. membar. membar. membar.{cta.sys }. when the previous value can no longer be read. 2010 . Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. this is the appropriate level of membar. A memory write (e.level = { . membar.gl. Waits until prior memory reads have been performed with respect to other threads in the CTA. level describes the scope of other clients for which membar is an ordering event. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar. that is.sys requires sm_20 or later.g. and memory reads by this thread can no longer be affected by other thread writes.cta. 134 January 24.g.sys will typically have much longer latency than membar.level. global. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. PTX ISA Notes Target ISA Notes Examples membar. membar.cta Waits until all prior memory writes are visible to other threads in the same CTA.

Within these windows. . .u32. If no state space is given. an address maps to the corresponding location in local or shared memory. . min.xor.space}.f32 Atomically loads the original value at location a into destination register d.space = { . max.space}.s32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32. or the instruction may fault.max }. . and stores the result of the specified operation at location a.op. .f32 }. c.min. . . [a]. min.Chapter 8. inc. If an address is not properly aligned.e. . .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. January 24. .u64. perform the memory accesses using generic addressing. The floating-point operations are add. i.u32. the resulting behavior is undefined. The bit-size operations are and.e.op = { . i.dec. e. For atom. cas (compare-and-swap). or. . . . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.add. 2010 135 .u32 only . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.exch. b. an address maps to global memory unless it falls within the local memory window or the shared memory window. . A register containing an address may be declared as a bit-size type or integer type. Instruction Set Table 102. atom{.type atom{. Description // // // // // . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.or. or [immAddr] an immediate absolute byte address.type d.exch to store to locations accessed by other atomic operations.inc. and max operations are single-precision. atom. xor. a de-referenced register areg containing a byte address.add. performs a reduction operation with operand b and the value in location a. .b]. The address size may be either 32-bit or 64-bit.type = { . The address must be naturally aligned to a multiple of the access size. 32-bit operations. d. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.u64 .global.b64. b.g.b32. overwriting the original value. . Operand a specifies a location in the specified state space..b64 .s32.f32. The floating-point add. by inserting barriers between normal stores and atomic operations to a common address.cas. The integer operations are add.b32 only .shared }. dec. . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. and truncated if the register width exceeds the state space address width for the target architecture. min. .and. . . .s32. . or by using atom. accesses to local memory are illegal.op. . [a]. In generic addressing. and exch (exchange). Addresses are zero-extended to the specified width as needed. The inc and dec operations return a result in the range [0. and max. .u32..

d. : r. 64-bit atom.shared. b.s. Introduced in PTX ISA version 1.global requires sm_11 or later. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.my_val.{add.my_new_val. : r+1.global.exch} requires sm_12 or later.b32 d.0 Semantics atomic { d = *a.shared operations require sm_20 or later. Use of generic addressing requires sm_20 or later.PTX ISA Version 2.[a].1.f32 atom. atom.t) = (r == s) ? t operation(*a.cas.global.[x+4]. s) = s.f32 requires sm_20 or later. cas(r.s32 atom. s) = (r > s) ? s exch(r. 64-bit atom.max} are unimplemented.f32. 2010 . atom.0.max. atom.{min. : r-1. Release Notes Examples @p 136 January 24.0. atom.add. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. c) operation(*a. d.shared requires sm_12 or later.add.cas. s) = (r >= s) ? 0 dec(r.[p]. atom. b). *a = (operation == cas) ? : } where inc(r.

min. red{. The address size may be either 32-bit or 64-bit. 2010 137 . and xor.u32.dec. by inserting barriers between normal stores and reduction operations to a common address. The floating-point add. b).e. . perform the memory accesses using generic addressing. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.op.add.e. min. or. .min.s32.global. dec. e.and.s32. A register containing an address may be declared as a bit-size type or integer type. . The bit-size operations are and.max }.inc. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.u64 . the access may proceed by silently masking off low-order address bits to achieve proper rounding.shared }. max. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.. or the instruction may fault. 32-bit operations. . dec(r. Operand a specifies a location in the specified state space. . or by using atom..Chapter 8.b64. . In generic addressing.f32. Notes Operand a must reside in either the global or shared state space. . For red. . s) = (r > s) ? s : r-1.op = { . the resulting behavior is undefined. The integer operations are add. and truncated if the register width exceeds the state space address width for the target architecture. an address maps to the corresponding location in local or shared memory.type = { . . January 24. The address must be naturally aligned to a multiple of the access size.b32 only . .add.f32 Performs a reduction operation with operand b and the value in location a. . . . The inc and dec operations return a result in the range [0. accesses to local memory are illegal. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . and max.b32.exch to store to locations accessed by other reduction operations. min.s32. Semantics *a = operation(*a.u32. . where inc(r.b]. Within these windows. red. overwriting the original value.xor. If no state space is given. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.g. and max operations are single-precision. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.f32 }. s) = (r >= s) ? 0 : r+1. The floating-point operations are add.type [a]. . Instruction Set Table 103. i.u32 only .space}. b. . an address maps to global memory unless it falls within the local memory window or the shared memory window.u32. and stores the result of the specified operation at location a. i. .or.space = { . . If an address is not properly aligned. inc. . Addresses are zero-extended to the specified width as needed. Description // // // // .u64. a de-referenced register areg containing a byte address. or [immAddr] an immediate absolute byte address.

shared requires sm_12 or later.and. 64-bit red. [p].f32 red.max} are unimplemented. red.{min. 64-bit red.shared operations require sm_20 or later.add requires sm_12 or later. Release Notes Examples @p 138 January 24.s32 red. red. red.f32 requires sm_20 or later.0.add.global requires sm_11 or later red. 2010 .global.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.b32 [a]. red.add.1.my_val.2.shared.global.PTX ISA Version 2.max. [x+4]. Use of generic addressing requires sm_20 or later.f32.

pred vote. 2010 139 .uni }. not across an entire CTA. r1.uni True if source predicate has the same value in all active threads in warp.pred d.b32 p.mode. Negate the source predicate to compute . vote.any True if source predicate is True for some active thread in warp.any. vote.Chapter 8. returns bitmask .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Description Performs a reduction of the source predicate across threads in a warp.not_all. In the ‘ballot’ form.2. Note that vote applies to threads in a single warp. Negating the source predicate also computes .uni. The reduction modes are: . {!}a. The destination predicate value is the same across all threads in the warp.pred vote. vote. Instruction Set Table 104.ballot.ballot. // ‘ballot’ form.mode = { .ballot.all.none. . {!}a.uni.all.p.all True if source predicate is True for all active threads in warp. where the bit position corresponds to the thread’s lane id.q. . vote requires sm_12 or later. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. // get ‘ballot’ across warp January 24.b32 requires sm_20 or later. vote. Negate the source predicate to compute .ballot. .b32 d. . p. vote.q.

The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).h0. // 32-bit scalar operation.h1 }. .min.asel}. Video Instructions All video instructions operate on 32-bit register operands. b{. and btype are valid.u32 or . 140 January 24.asel = . perform a scalar arithmetic operation to produce a signed 34-bit result. .dsel = .sat} d.asel}. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.b3. .atype.dtype. with optional secondary operation vop.atype = . a{. c. .max }. . . b{. the input values are extracted and signor zero.btype{.dtype.dsel. .PTX ISA Version 2.add. with optional data merge vop. b{. 2. taking into account the subword destination size in the case of optional data merging. optionally clamp the result to the range of the destination type.b1.or zero-extend byte.bsel = { . extract and sign.b2.bsel}.s33 values.extended internally to . or word values from its source operands.s34 intermediate result.u32.secop = { .bsel}. The type of each operand (.btype{. a{.sat} d.0 8.bsel}. .dtype.btype{. The source and destination operands are all 32-bit registers.s32) is specified in the instruction type.9.btype = { .sat}. The sign of the intermediate result depends on dtype. The primary operation is then performed to produce an . c. vop. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. .b0. .secop d.asel}. to produce signed 33-bit input values.atype. 2010 . Using the atype/btype and asel/bsel specifiers.7. 3.dtype = .s32 }. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. The general format of video instructions is as follows: // 32-bit scalar operation. a{. all combinations of dtype. .atype. atype. 4. half-word.

.b2: return ((tmp & 0xff) << 16) case . . default: return tmp. U32_MAX. Instruction Set . c).b2. . The lower 32-bits are then written to the destination operand.s33 c ) switch ( dsel ) { case . U8_MAX. tmp. .Chapter 8. c). The sign of the c operand is based on dtype.s33 optMerge( Modifier dsel. U32_MIN ). c).s33 c) { switch ( secop ) { .b1. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). . S32_MAX. tmp. . U16_MAX.h0.s33 optSaturate( . tmp. Bool sat.s33 optSecOp(Modifier secop. . as shown in the following pseudocode. .b0.h1: return ((tmp & 0xffff) << 16) case . S16_MIN ). c).s34 tmp. U16_MIN ). . 2010 141 . S8_MIN ). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. tmp. c).s33 tmp. } } . tmp.h0: return ((tmp & 0xffff) case . January 24. S16_MAX.add: return tmp + c.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.min: return MIN(tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case .b1: return ((tmp & 0xff) << 8) case .b3: return ((tmp & 0xff) << 24) default: return tmp. S8_MAX. Bool sign.b0: return ((tmp & 0xff) case . . Modifier dsel ) { if ( !sat ) return tmp. U8_MIN ). switch ( dsel ) { case . S32_MIN ). c).max return MAX(tmp. c).s33 tmp. .

switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.asel}. // optional merge with c operand 142 January 24. tmp.atype.atype = .atype.s32.bsel}.h1 }. r3.sat vsub. c ).b0.max }.dtype. vabsdiff.s32 }.b3. Perform scalar arithmetic operation with optional saturate. vmax require sm_20 or later. Video Instructions: vadd. isSigned(dtype). 2010 . vadd. r1. a{. btype. Integer byte/half-word/word absolute value of difference. . Integer byte/half-word/word minimum / maximum.dsel .btype{.asel = . with optional data merge vop.btype{. c. // extract byte/half-word/word and sign. tmp.s32. vabsdiff. asel ). . sat. r2. vop. vmin.btype{. a{.dsel. b{.h0.b0. tmp = MIN( ta.s32. tmp = ta – tb. .sat} d.h1.u32. vmax vadd. r3. { .s32. tmp = | ta – tb |. b{. atype. vmax }.sat}. bsel ). c. vadd. vmax Syntax Integer byte/half-word/word addition / subtraction. r3.b0. r2.b2. .s32.PTX ISA Version 2. dsel ).s32. r2.asel}.min.h0.add. and optional secondary arithmetic operation or subword data merge. vsub vabsdiff vmin. vmin. r1.0.op2 Description = = = = { vadd. d = optSecondaryOp( op2.asel}. tb = partSelectSignExtend( b. . Semantics // saturate. r2. c ).s32. c.sat vmin.sat. tmp = MAX( ta.bsel}.vop . b{. . vsub. vabsdiff.b2. r3. vsub.sat vabsdiff. c. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat} d.0 Table 105. r1. . vsub.op2 d. // 32-bit scalar operation. .s32.u32. .s32. tb ).dtype. . tb ). vmin.s32.add r1.h0. // optional secondary operation d = optMerge( dsel. taking into account destination type and merge operations tmp = optSaturate( tmp.bsel = { .bsel}. // 32-bit scalar operation.dtype.atype.b1.h1.dtype . a{.or zero-extend based on source operand type ta = partSelectSignExtend( a.btype = { . . with optional secondary operation vop.u32.

r2.atype.mode} d.u32 vshr. tb = partSelectSignExtend( b.s32 }.wrap }. Video Instructions: vshl.u32. switch ( vop ) { case vshl: tmp = ta << tb. { . with optional data merge vop. . asel ). Left shift fills with zero. .u32.s32. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.clamp && tb > 32 ) tb = 32.max }.sat}{. isSigned(dtype).asel}. } // saturate.bsel}. . 2010 143 . . a{. r2. // optional secondary operation d = optMerge( dsel.u32{.asel = . if ( mode == . { .min.mode . vshl: Shift a left by unsigned amount in b with optional saturate.op2 d. taking into account destination type and merge operations tmp = optSaturate( tmp. . vshr require sm_20 or later.dtype. vshr Syntax Integer byte/half-word/word left / right shift.dtype. c. dsel ).or zero-extend based on source operand type ta = partSelectSignExtend( a.add.wrap r1. and optional secondary arithmetic operation or subword data merge. and optional secondary arithmetic operation or subword data merge. with optional secondary operation vop. r1.mode} d. tmp.b1. . r3.asel}.bsel}. . . Instruction Set Table 106.0. vshr: Shift a right by unsigned amount in b with optional saturate. . Semantics // extract byte/half-word/word and sign. .dsel . vop. case vshr: tmp = ta >> tb. b{.dsel. c ). atype.atype.clamp.u32{.h1.vop .wrap ) tb = tb & 0x1f.bsel}. // 32-bit scalar operation. b{. c ). a{.u32.b2. r3.h0.atype.bsel = { . // 32-bit scalar operation.dtype. if ( mode == .u32. vshl. // default is . d = optSecondaryOp( op2. tmp.asel}. b{. vshr }.sat}{.h1 }. January 24. Signed shift fills with the sign bit.u32.atype = { .b3. . . c.Chapter 8.mode}.u32.op2 Description = = = = = { vshl. sat. a{.b0.u32{.sat}{. vshr vshl. vshl. unsigned shift fills with zero.clamp .dtype . bsel ).

. .dtype = .S32 // intermediate signed.b2. (a*b) is negated if and only if exactly one of a or b is negated. .S32 // intermediate signed. with optional operand negates.btype{.asel}.b1. final signed (U32 * S32) . Input c has the same sign as the intermediate result. {-}b{. The “plus one” mode (.btype = { .0 Table 107. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.asel = .PTX ISA Version 2.h0. Although PTX syntax allows separate negation of the a and b operands.bsel}. and zero-extended otherwise. Source operands may not be negated in . final signed (U32 * S32) + S32 // intermediate signed. {-}a{.scale} d. a{. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.u32.dtype. which is used in computing averages. final signed -(S32 * S32) + S32 // intermediate signed. vmad. c. {-}c.bsel}.btype. b{.po{.bsel = { .shr7.po) computes (a*b) + c + 1. final unsigned -(U32 * U32) + S32 // intermediate signed. . 2010 . . PTX allows negation of either (a*b) or c. internally this is represented as negation of the product (a*b).atype = .shr15 }. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. .sat}{. final signed (S32 * U32) .b3.po mode. this result is sign-extended if the final result is signed. The final result is unsigned if the intermediate result is unsigned and c is not negated. 144 January 24.atype.asel}. final signed -(U32 * S32) + S32 // intermediate signed. . the intermediate result is signed.U32 // intermediate unsigned. Depending on the sign of the a and b operands.scale = { .sat}{. final signed (S32 * S32) + S32 // intermediate signed. final signed (S32 * U32) + S32 // intermediate signed. That is. .b0. // 32-bit scalar operation vmad. “plus one” mode. final signed -(S32 * U32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift.S32 // intermediate signed. and scaling. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. The source operands support optional negation with some restrictions.. final signed (U32 * U32) .scale} d. . .h1 }. otherwise.dtype. and the operand negates. Description Calculate (a*b) + c.atype. final signed (S32 * S32) .s32 }.

S32_MIN). 2010 145 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. signedFinal = isSigned(atype) || isSigned(btype) || (a.s32.Chapter 8.negate) || c.or zero-extend based on source operand type ta = partSelectSignExtend( a.h0. Instruction Set Semantics // extract byte/half-word/word and sign. vmad requires sm_20 or later.shr15: result = (tmp >> 15) & 0xffffffffffffffff.u32.sat ) { if (signedFinal) result = CLAMP(result. U32_MIN). tb = partSelectSignExtend( b.u32.shr15 r0. r1. vmad. if ( . r1. r2. switch( scale ) { case .negate ^ b. } else if ( a.shr7: result = (tmp >> 7) & 0xffffffffffffffff. lsb = 1. else result = CLAMP(result. U32_MAX. S32_MAX. asel ). lsb = 1. btype. r2.h0.s32. tmp[127:0] = ta * tb.u32. lsb = 0.u32. atype.0.negate ) { tmp = ~tmp.negate ^ b. r3. -r3.negate ) { c = ~c. January 24.negate. bsel ).sat vmad. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). tmp = tmp + c128 + lsb. } else if ( c.po ) { lsb = 1. r0. } if ( . case .

c.ne r1.cmp .bsel}.atype.b1. a{. Semantics // extract byte/half-word/word and sign.ne.op2 Description = = = = . tmp.atype. . .le.h1 }.cmp. r2. r1.asel}. 2010 .bsel = { .lt. . vset. a{. tb = partSelectSignExtend( b.0.btype.asel = . // 32-bit scalar operation.asel}.btype = { . with optional secondary arithmetic operation or subword data merge.or zero-extend based on source operand type ta = partSelectSignExtend( a. tb. . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. b{.asel}.u32.eq. r3. vset. r2. .op2 d. { .b2. asel ).atype .s32. vset requires sm_20 or later.h1. Compare input values using specified comparison.b3.b0.lt vset. 146 January 24. c.add. // 32-bit scalar operation.s32 }.min. .dsel.bsel}. tmp = compare( ta. . with optional secondary operation vset.u32.PTX ISA Version 2. tmp.btype.bsel}.dsel . cmp ) ? 1 : 0. with optional data merge vset. . The intermediate result of the comparison is always unsigned.h0.cmp d. r3. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.cmp d. d = optSecondaryOp( op2. c ). . btype. . // optional secondary operation d = optMerge( dsel.max }. . { . c ). .u32.atype. . b{. . . b{.0 Table 108.gt.btype.ge }. atype. bsel ).u32. a{. and therefore the c operand and final result are also unsigned.

0. Supported on all target architectures. @p pmevent 1. brkpt.Chapter 8. brkpt Suspends execution Introduced in PTX ISA version 1. Supported on all target architectures. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Introduced in PTX ISA version 1. brkpt.0. Triggers one of a fixed number of performance monitor events. trap Abort execution and generate an interrupt to the host CPU. numbered 0 through 15. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Introduced in PTX ISA version 1. Table 110. with index specified by immediate operand a.10. trap. trap. Notes PTX ISA Notes Target ISA Notes Examples Currently. Table 111.4. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Instruction Set 8. there are sixteen performance monitor events.7. pmevent 7. pmevent a. January 24. The relationship between events and counters is programmed via API calls from the host. 2010 147 . brkpt requires sm_11 or later. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.

0 148 January 24.PTX ISA Version 2. 2010 .

Special Registers PTX includes a number of predefined.Chapter 9. which are visible as special registers and accessed through mov or cvt instructions. %clock64 %pm0. %pm3 January 24. read-only variables. %lanemask_le. %lanemask_gt %clock. %lanemask_ge. 2010 149 . %lanemask_lt. …. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq.

u32 %r1. %tid. .u32 type in PTX 2.x.sreg .z == 1 in 2D CTAs.%ntid.u32 type in PTX 2. .u32 %h2.0 Table 112.u32 %h1.x < %ntid. Redefined as .sreg .z == 0 in 2D CTAs. Every thread in the CTA has a unique %tid. %tid. or 3D vector to match the CTA shape. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.%tid.x. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.x to %rh Target ISA Notes Examples // legacy PTX 1.u32 %tid. mov. Redefined as .z).u32 %tid.y == %ntid.z == 1 in 1D CTAs. cvt.u32 %ntid. mov.z.u16 %r2.sreg . The fourth element is unused and always returns zero.y.v4. // zero-extend tid.%h2.x code accessing 16-bit component of %tid mov.0.z.x.0.u16 %rh. per-thread special register initialized with the thread identifier within the CTA. // CTA shape vector // CTA dimensions A predefined.v4. // move tid.x. PTX ISA Notes Introduced in PTX ISA version 1. It is guaranteed that: 0 <= %tid. // legacy PTX 1. // compute unified thread id for 2D CTA mov.x.u32.%tid.PTX ISA Version 2.x 0 <= %tid. %tid. %ntid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.u32 %ntid. mov.v4 .%tid. %tid.x.y == %tid. CTA dimensions are non-zero. 2010 . the fourth element is unused and always returns zero.z to %r2 Table 113.sreg . %tid component values range from 0 through %ntid–1 in each CTA dimension. %ntid. Supported on all target architectures. read-only.%r0. // thread id vector // thread id components A predefined.x code Target ISA Notes Examples 150 January 24.u32 %r0.y 0 <= %tid.0. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. The total number of threads in a CTA is (%ntid. . mov.%tid.u16 %rh.z PTX ISA Notes Introduced in PTX ISA version 1.y.y. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. 2D.%tid.z. read-only special register initialized with the number of thread ids in each CTA dimension. the %tid value in unused dimensions is 0. %ntid.y < %ntid.%ntid.z < %ntid.x * %ntid.v4 . The number of threads in each dimension are specified by the predefined special register %ntid.u32 %r0. Supported on all target architectures. . %ntid.0. The %tid special register contains a 1D.z == 0 in 1D CTAs.%h1.y * %ntid.x. mad.

g. . %nwarpid requires sm_20 or later. Introduced in PTX ISA version 1. 2010 151 . due to rescheduling of threads following preemption. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %nwarpid. . PTX ISA Notes Target ISA Notes Examples Table 116. read-only special register that returns the maximum number of warp identifiers. For this reason. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. The lane identifier ranges from zero to WARP_SZ-1.u32 %r. Supported on all target architectures.sreg .3.u32 %warpid. January 24.sreg . Table 115. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.u32 %r.Chapter 9. but its value may change during execution. Introduced in PTX ISA version 2. %laneid. mov. read-only special register that returns the thread’s lane within the warp. Special Registers Table 114. Note that %warpid is volatile and returns the location of a thread at the moment when read. . %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. mov. %warpid. A predefined. Supported on all target architectures. Introduced in PTX ISA version 1. e.0. mov.u32 %r.3. A predefined.u32 %laneid.sreg . A predefined. The warp identifier will be the same for all threads within a single warp. read-only special register that returns the thread’s warp identifier.u32 %nwarpid.

%nctaid.u32 mov.v4 .x 0 <= %ctaid.u32 %nctaid.0. The fourth element is unused and always returns zero. 2010 . // CTA id vector // CTA id components A predefined.x < %nctaid. . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. // legacy PTX 1.u32 %ctaid.%ctaid.%nctaid.y. mov.z.y. The fourth element is unused and always returns zero. Redefined as .%nctaid.z < %nctaid.0.u16 %r0. The %nctaid special register contains a 3D grid shape vector.x. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. // legacy PTX 1.{x. .x.v4.u32 type in PTX 2.u32 %nctaid .0.x. read-only special register initialized with the CTA identifier within the CTA grid.y.x code Target ISA Notes Examples 152 January 24.v4.0 Table 117. %rh. %ctaid.sreg . The %ctaid special register contains a 1D.sreg .z.u16 %r0.u32 type in PTX 2.x. . read-only special register initialized with the number of CTAs in each grid dimension. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. Supported on all target architectures. It is guaranteed that: 1 <= %nctaid. Redefined as .%nctaid. %ctaid. with each element having a value of at least 1. // Grid shape vector // Grid dimensions A predefined.x code Target ISA Notes Examples Table 118. mov.x.0. depending on the shape and rank of the CTA grid.PTX ISA Version 2.v4 .sreg . 2D.y. %rh. Each vector element value is >= 0 and < 65535.536 PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures. or 3D vector.u32 %ctaid.z PTX ISA Notes Introduced in PTX ISA version 1. It is guaranteed that: 0 <= %ctaid.sreg .y 0 <= %ctaid.y < %nctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.u32 mov.%ctaid.z} < 65.

%nsmid. mov. . 2010 153 . The SM identifier ranges from 0 to %nsmid-1. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. // initialized at grid launch A predefined. repeated launches of programs may occur. .u32 %r.0. .sreg . Note that %smid is volatile and returns the location of a thread at the moment when read.sreg . During execution. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.g. Introduced in PTX ISA version 1. read-only special register initialized with the per-grid temporal grid identifier. A predefined. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. but its value may change during execution. read-only special register that returns the maximum number of SM identifiers. where each launch starts a grid-of-CTAs. PTX ISA Notes Target ISA Notes Examples Table 121. Supported on all target architectures.u32 %nsmid.Chapter 9.u32 %gridid. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. mov. PTX ISA Notes Target ISA Notes Examples January 24. %smid.3. so %nsmid may be larger than the physical number of SMs in the device. Notes PTX ISA Notes Target ISA Notes Examples Table 120.u32 %smid. Introduced in PTX ISA version 1. This variable provides the temporal grid launch number for this context.u32 %r. %gridid. The SM identifier numbering is not guaranteed to be contiguous. The SM identifier numbering is not guaranteed to be contiguous. Special Registers Table 119. e.sreg . mov. Introduced in PTX ISA version 2. %nsmid requires sm_20 or later. A predefined. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Supported on all target architectures.0.u32 %r. due to rescheduling of threads following preemption.

u32 %r.u32 %lanemask_le. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.0 Table 122. Table 123.0. Introduced in PTX ISA version 2.0. A predefined.u32 %lanemask_lt. A predefined. A predefined. %lanemask_eq.sreg .u32 %lanemask_eq.sreg . %lanemask_lt. . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. mov. . %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg .PTX ISA Version 2. %lanemask_le requires sm_20 or later. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. mov. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_le. 154 January 24. mov. . Introduced in PTX ISA version 2.0. 2010 . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later. Table 124.u32 %r.u32 %r.

%lanemask_gt. mov. mov.u32 %r. A predefined. %lanemask_gt requires sm_20 or later. Special Registers Table 125. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.0. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg .u32 %lanemask_gt. %lanemask_ge requires sm_20 or later. A predefined. Table 126.Chapter 9.sreg . 2010 155 .u32 %lanemask_ge.0. .u32 %r. . read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. January 24. Introduced in PTX ISA version 2. %lanemask_ge.

read-only 32-bit unsigned cycle counter. Introduced in PTX ISA version 1.u32 %clock. %pm3. 2010 .sreg . Table 129. Introduced in PTX ISA version 2.u32 r1. 156 January 24. .%clock64. Supported on all target architectures.sreg . . mov. %pm3 %pm0. %pm2.u64 r1. mov. %pm1. %pm2. The lower 32-bits of %clock64 are identical to %clock.u64 %clock64. read-only 64-bit unsigned cycle counter. %pm1.u32 %pm0. %pm1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.3. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. mov. %pm2. .sreg . Their behavior is currently undefined. Special Registers: %pm0.u32 r1. %clock64 requires sm_20 or later.%pm0. Special registers %pm0.0 Table 127. Table 128.%clock. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. and %pm3 are unsigned 32-bit read-only performance monitor counters. Supported on all target architectures. …. Introduced in PTX ISA version 1.PTX ISA Version 2.0. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.0.

.4 January 24.version 1.version 2.Chapter 10. and the target architecture for which the code was generated.0 .minor // major.0. . Directives 10. Increments to the major number indicate incompatible changes to PTX.version . Supported on all target architectures. 2010 157 .version directive.version directives are allowed provided they match the original .version directive.version . minor are integers Specifies the PTX language version number. . PTX File Directives: . Each ptx file must begin with a . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Duplicate . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.target Table 130. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version Syntax Description Semantics PTX version number.version major.1.

f64 to .0. Requires map_f64_to_f32 if any . Supported on all target architectures.f32. texture and sampler information is referenced with independent . Disallows use of map_f64_to_f32.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. brkpt instructions.red}. A program with multiple . A .target directive containing a target architecture and optional platform options. including expanded rounding modifiers.target directives can be used to change the set of target features allowed during parsing. PTX File Directives: .5. sm_11.PTX ISA Version 2. Adds {atom. 2010 . Adds {atom. Texturing mode introduced in PTX ISA version 1.target Syntax Architecture and Platform target.shared. sm_10. vote instructions.global. Requires map_f64_to_f32 if any . PTX features are checked against the specified target architecture. The following table summarizes the features in PTX that vary according to target architecture.f64 storage remains as 64-bits. but subsequent . In general. 158 January 24. Note that .f64 instructions used. Target sm_20 Description Baseline feature set for sm_20 architecture.global. . Requires map_f64_to_f32 if any . texmode_independent. The texturing mode is specified for an entire module and cannot be changed within the module. and an error is generated if an unsupported feature is used. Introduced in PTX ISA version 1. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.f64 instructions used. sm_13.texmode_unified .target .texref descriptor. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.target directive specifies a single target architecture.texref and . Texturing mode: (default is .red}.samplerref descriptors.red}. Adds double-precision support. 64-bit {atom. Therefore. where each generation adds new features and retains all features of previous generations.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 instructions used. map_f64_to_f32 }. generations of SM architectures follow an “onion layer” model. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.texmode_unified) . with only half being used by instructions converted from . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. sm_12. PTX code generated for a given target can be run on later generation devices.version directive. Description Specifies the set of features in the target architecture for which the current ptx code was generated. Each PTX file must begin with a . texmode_unified.0 Table 131. immediately followed by a .texmode_independent texture and sampler information is bound together and accessed via a single .

target sm_13 // supports double-precision .target sm_10 // baseline target architecture .target sm_20. texmode_independent January 24. Directives Examples .Chapter 10. 2010 159 .

b32 %r1. 160 January 24. %ntid. Supported on all target architectures. store. For PTX ISA versions 1. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. At kernel launch.2. opaque .b32 %r2. Parameters are passed via . . and query instructions and cannot be accessed via ld. parameter variables are declared in the kernel parameter list.b32 x.param space memory and are listed within an optional parenthesized parameter list.entry kernel-name ( param-list ) kernel-body . and body for the kernel function.b32 z ) Target ISA Notes Examples [x]. In addition to normal parameters. e. PTX ISA Notes For PTX ISA version 1. .0 through 1.entry . and .entry cta_fft . The shape and size of the CTA executing the kernel are available in special registers.entry .func Table 132. with optional parameters.samplerref.entry Syntax Description Kernel entry point and body. parameter variables are declared in the kernel body. 2010 .4.param.PTX ISA Version 2. . [y]. Parameters may be referenced by name within the kernel body and loaded into registers using ld.b32 y. . ld.4 and later.param .5 and later. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.b32 %r3. Semantics Specify the entry point for a kernel program.0 10. %nctaid.entry kernel-name kernel-body Defines a kernel entry point name.param . parameters.3. . etc.param instructions.param { .reg . ld.surfref variables may be passed as parameters. the kernel dimensions and properties are established and made available via special registers.entry filter ( . [z].b32 %r<99>. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.param instructions.param. . … } .param.texref. ld. These parameters can only be referenced by name within texture and surface load.g.0 through 1. Kernel and Function Directives: .

Release Notes For PTX ISA version 1. mov. Variadic functions are represented using ellipsis following the last fixed argument. which may use a combination of registers and stack locations to pass parameters. Directives Table 133. foo. } … call (fooval). dbl. .reg . The implementation of parameter passing is left to the optimizing translator. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. (val0. ret. .f64 dbl) { . 2010 161 .param and st. and supports recursion. and recursion is illegal. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. parameters must be in the register state space. PTX ISA 2.func definition with no body provides a function prototype. Parameters in register state space may be referenced directly within instructions in the function body.b32 rval. there is no stack.param state space. Kernel and Function Directives: .b32 localVar.func fname (param-list) function-body .func Syntax Function definition.func fname function-body . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. … Description // return value in fooval January 24.2 for a description of variadic functions. .param space are accessed using ld. implements an ABI with stack.func . … use N.func (ret-param) fname (param-list) function-body Defines a function.reg .b32 rval) foo (.reg . Parameters in . Parameter passing is call-by-value. Supported on all target architectures.0 with target sm_20 supports at most one return value. Parameters must be base types in either the register or parameter state space.0.b32 N. other code. The parameter lists define locally-scoped variables in the function body.x code. PTX 2. Variadic functions are currently unimplemented. if any.Chapter 10. A .0 with target sm_20 allows parameters in the . val1).func (.reg . including input and return parameters and optional function body.param instructions in the body.result.

minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). and the .maxntid .maxnreg . the . registers) to increase total thread count and provide a greater opportunity to hide memory latency. 162 January 24. These can be used.pragma directive is supported for passing information to the PTX backend. 2010 . Performance-Tuning Directives To provide a mechanism for low-level performance tuning.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.0 10.pragma directives may appear at module (file) scope.minnctapersm . and .entry directive and its body. PTX supports the following directives. at entry-scope. The .minnctapersm directives may be applied per-entry and must appear between an .PTX ISA Version 2.3. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. . for example. to throttle the resource requirements (e.g.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. Currently. or as statements within a kernel or device function body.maxnreg.maxnctapersm (deprecated) .pragma The . which pass information to the backend optimizing compiler. The directive passes a list of strings to the backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. Note that . The directives take precedence over any module-level constraints passed to the optimizing backend.maxntid. the . and the strings have no semantics within the PTX virtual machine model.maxntid and . A general .maxntid directive specifies the maximum number of threads in a thread block (CTA). . The interpretation of .

maxctapersm.maxntid nx. Exceeding any of these limits results in a runtime error or kernel launch failure.16.maxntid nx. Introduced in PTX ISA version 1. The actual number of registers used may be less. Directives Table 134. Performance-Tuning Directives: . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. The maximum number of threads is the product of the maximum extent in each dimension. 2D.maxntid .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxntid 16. The compiler guarantees that this limit will not be exceeded.maxnreg .3.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.entry bar . or 3D CTA.maxnreg n Declare the maximum number of registers per thread in a CTA. Performance-Tuning Directives: .maxntid 256 . ny. the backend may be able to compile to fewer registers. for example. Supported on all target architectures. Supported on all target architectures. .entry foo .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid and . . This maximum is specified by giving the maximum extent of each dimention of the 1D.entry foo .maxntid nx . Introduced in PTX ISA version 1. ny . 2010 163 .maxntid Syntax Maximum number of threads in thread block (CTA). . or the maximum number of registers may be further constrained by . nz Declare the maximum number of threads in the thread block (CTA). .Chapter 10.3.

entry foo . Supported on all target architectures. Performance-Tuning Directives: .maxntid to be specified as well.maxnctapersm. .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Supported on all target architectures.maxnctapersm generally need .minnctapersm generally need .PTX ISA Version 2.minnctapersm in PTX ISA version 2.maxnctapersm has been renamed to . Introduced in PTX ISA version 2. Optimizations based on . Deprecated in PTX ISA version 2.maxntid and .0. The optimizing backend compiler uses .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. However.0 as a replacement for .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. . .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. additional CTAs may be mapped to a single multiprocessor.minnctapersm 4 { … } 164 January 24. .maxntid to be specified as well.maxnctapersm (deprecated) . if the number of registers used by the backend is sufficiently lower than this bound. Introduced in PTX ISA version 1. For this reason. Optimizations based on .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxntid 256 .maxntid 256 .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Performance-Tuning Directives: .0 Table 136. .minnctapersm .0.entry foo .3. 2010 .

pragma .0. The interpretation of .Chapter 10. See Appendix A for descriptions of the pragma strings defined in ptxas. Directives Table 138. Supported on all target architectures.pragma directive strings is implementation-specific and has no impact on PTX semantics. Pass module-scoped. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . 2010 165 . Performance-Tuning Directives: .pragma directive may occur at module-scope. entry-scoped. or at statementlevel. at entry-scope.pragma list-of-strings . Introduced in PTX ISA version 2. or statement-level directives to the PTX backend compiler. .entry foo . .pragma Syntax Description Pass directives to PTX backend compiler.pragma “nounroll”.pragma “nounroll”. { … } January 24. The .

quad int64-list // comma-separated hexadecimal integers in range [0.debug_pubnames.section directive is new in PTX ISA verison 2. 0x00000364.x code. 0x00. 0x61395a5f.byte 0x00.section directive.232-1] ..264-1] .0 but is supported for legacy PTX version 1.0 and replaces the @@DWARF syntax. 0x00. @progbits . Supported on all target architectures. “”. 0x00 166 January 24. Deprecated as of PTX 2. 2010 . Table 139.section . @@DWARF dwarf-string dwarf-string may have one of the . 0x00.debug_info .loc The .. 0x00 .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Introduced in PTX ISA version 1. 0x63613031. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.byte 0x2b.4byte label . 0x5f736f63 . replaced by . 0x00.2.4byte . The @@DWARF syntax is deprecated as of PTX version 2. 0x02.4byte 0x6e69616d.byte byte-list // comma-separated hexadecimal byte values . 0x00. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x736d6172 . 0x00.4byte 0x000006b5. 0x6150736f.section .4.0. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .file .0 10.4byte int32-list // comma-separated hexadecimal integers in range [0.PTX ISA Version 2.

0x00 0x61395a5f. Source file location..b32 0x000006b5. . 0x00000364..b32 0x6e69616d.section . 0x736d6172 0x00 Table 141.264-1] .debug_pubnames { . 2010 167 . . .b32 . 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.loc .0.debug_info .section Syntax PTX section definition. 0x63613031. 0x00. } 0x02.section . Supported on all target architectures.file filename Table 142. 0x00. 0x00. Debugging Directives: .0. .b64 int64-list // comma-separated list of integers in range [0.b32 int32-list // comma-separated list of integers in range [0.b8 byte-list // comma-separated list of integers in range [0.255] .b8 0x00. Supported on all target architectures.file . .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. Supported on all target architectures.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.loc line_number January 24.b8 0x2b.Chapter 10. Source file information.232-1] . 0x00. Directives Table 140.. 0x00. .section section_name { dwarf-lines } dwarf-lines have the following formats: . replaces @@DWARF syntax. . Debugging Directives: . 0x5f736f63 0x6150736f.b32 label . Debugging Directives: .

Supported on all target architectures.6. // foo is defined in another module Table 144.0 10.global .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.0. Linking Directives .visible identifier Declares identifier to be externally visible.visible Table 143.extern . . Linking Directives: .b32 foo. Linking Directives: . 2010 . // foo will be externally visible 168 January 24.0. Introduced in PTX ISA version 1.extern identifier Declares identifier to be defined externally.visible .b32 foo.global .extern .visible . . . . Supported on all target architectures. Introduced in PTX ISA version 1.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern .PTX ISA Version 2.

0 driver r195 PTX ISA Version PTX ISA 1.1 CUDA 2.3 PTX ISA 1.1 PTX ISA 1.0 PTX ISA 1. CUDA Release CUDA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0. and the remaining sections provide a record of changes in previous releases. The release history is as follows. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 2.1 CUDA 2.2 CUDA 2.5 PTX ISA 2.0 CUDA 1.4 PTX ISA 1.2 PTX ISA 1.3 driver r190 CUDA 3.0 January 24.Chapter 11. 2010 169 .

1. 2010 . Changes in Version 2. These are indicated by the use of a rounding modifier and require sm_20. A single-precision fused multiply-add (fma) instruction has been added. The mad.and double-precision div.rp rounding modifiers for sm_20 targets. New Features 11.ftz modifier may be used to enforce backward compatibility with sm_1x.ftz and .f32.1. sub.0 for sm_20 targets.1.sat modifiers.1.x code and sm_1x targets. The changes from PTX ISA 1. while maximizing backward compatibility with legacy PTX 1.0 11. The .1.f32 instruction also supports . fma. and mul now support . Floating-Point Extensions This section describes the floating-point changes in PTX 2.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Instructions testp and copysign have been added. The fma. Single-precision add.rn. rcp. mad.0 11.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.1. When code compiled for sm_1x is executed on sm_20 devices.PTX ISA Version 2. Single.f32 requires sm_20. The goal is to achieve IEEE 754 compliance wherever possible.f32 require a rounding modifier for sm_20 targets.f32 for sm_20 targets.f32 and mad. The mad.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. and sqrt with IEEE 754 compliant rounding have been added. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Both fma. • • • • • 170 January 24.f32 maps to fma.rm and .

Instruction cvta for converting global. e. prefetchu. 11. New special registers %nsmid. A “vote ballot” instruction. Surface instructions support additional . vote. has been added.f32 have been implemented.arrive instruction has been added. The bar instruction has been extended as follows: • • • A bar. and red now support generic addressing. bfe and bfi.shared have been extended to handle 64-bit data types for sm_20 targets. prefetch. suld. . 2010 171 .red. isspacep. The . bar now supports optional thread count and register operands. has been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. clz.gt} have been added. cvta.{and.clamp modifiers.zero.section. A “population count” instruction. A “bit reversal” instruction. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.ge.1.1.sys. %lanemask_{eq. and shared addresses to generic address and vice-versa has been added. A system-level membar instruction.add. January 24. A new directive. and sust.le. A “count leading zeros” instruction. Instructions prefetch and prefetchu have also been added.minnctapersm to better match its behavior and usage. have been added. st. Instructions {atom. Instructions {atom.ballot.red}. Instruction sust now supports formatted surface stores.1. Cache operations have been added to instructions ld. %clock64.clamp and . for prefetching to specified level of memory hierarchy.lt.or}. Release Notes 11.b32. Other new features Instructions ld.pred have been added.red}.2. has been added. Instructions bar. . has been added. st.popc. atom. Bit field extract and insert instructions.Chapter 11.g.1. popc.3. bfind. brev. has been added. ldu.u32 and bar. New instructions A “load uniform” instruction. A “find leading non-sign bit” instruction. Video instructions (includes prmt) have been added. local.red. ldu. membar. has been added. has been added.maxnctapersm directive was deprecated and replaced with .

Unimplemented Features Remaining The following table summarizes unimplemented instruction features.0 11.ftz (and cvt for .ftz for PTX ISA versions 1. or . To maintain compatibility with legacy PTX code.5 and later. Semantic Changes and Clarifications The errata in cvt. .f32 type is unimplemented. 172 January 24.5.2.p sust.max} are not implemented.target sm_1x.red}. stack-based ABI is unimplemented. 11. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.3.s32. call suld.s32.{min. Formatted surface store with . The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. Instruction bra. The underlying. where . if .{u32.f32} atom. 2010 .p. {atom. Support for variadic functions and alloca are unimplemented.version is 1. the correct number is sixteen.PTX ISA Version 2.1. cvt. In PTX version 1.1. Formatted surface load is unimplemented.4 and earlier.4 or earlier.f32. has been fixed. See individual instruction descriptions for details.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.u32. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.

0. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Ignored for sm_1x targets. … @p bra L1_end. and statement levels. Table 145. disables unrolling of0 the loop for which the current block is the loop header.func bar (…) { … L1_head: . { … } // do not unroll any loop in this function . disables unrolling for all loops in the entry function body. 2010 173 . L1_body: … L1_continue: bra L1_head. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.entry foo (…) .pragma “nounroll”. Note that in order to have the desired effect at statement level. Supported only for sm_20 targets. including loops preceding the .pragma “nounroll”. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma “nounroll”.Appendix A. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.pragma. Descriptions of . The “nounroll” pragma is allowed at module. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. . entry-function. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. L1_end: … } // do not unroll this loop January 24.pragma strings defined by ptxas. .pragma Strings This section describes the .

2010 .0 174 January 24.PTX ISA Version 2.

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