NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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........................5...............1............ Operand Type Information .......................................................................PTX ISA Version 2........2.....5.................................... 32 5...................4...........3..... 6......................... 29 Parameter State Space ....................... 27 Register State Space .............. 6..8........................1..................................................6....1..........................................................4..... Operand Costs .............1....... 33 5......................... 5......................................... 5....................................................................................... 5.. 2010 ...........3... 32 Texture State Space (deprecated) ............................................................................1......4.................................4....................................2................3................................. Type Conversion.... Summary of Constant Expression Evaluation Rules .......... 6....................4.................... 33 Fundamental Types ................................3......................1................................. and Surface Types ....................................................4................4..... 41 Using Addresses. 39 5.............................. 6........................5.............. 27 5..........................1. State Spaces ............................. 43 6...... 47 Chapter 7..... 6..... 44 Scalar Conversions .................... 5. 5........................... 46 6........................ 39 Parameterized Variable Names ........................................................................................................... Types ..............2.............. 25 Chapter 5................2..................................................................4............... 49 7.................................... 6.6...................... 6......... 38 Initializers .........1.........................................................7.................................2............................................ 5................ Types..................................... 5................... 43 Vectors as Operands .......................1........4....................5..................................................................................... 34 Variables ........... 37 Array Declarations ..................................................... 49 ii January 24...........................2.............. 38 Alignment ... 29 Global State Space ......5.......4................................ 37 Variable Declarations ............ 30 Shared State Space.... Texture.................................... Sampler......................... 42 Addresses as Operands ... 43 Labels and Function Names as Operands ..... State Spaces...........2........ 5.............................................................6................................... 41 Destination Operands .......................................................................2.... 37 Vectors .......... and Vectors ..2........................1........... 41 Source Operands................................... 5................................. 28 Special Register State Space .......... Chapter 6.........................4.................................. 6.............. Abstracting the ABI ....................4...................................4...................... Arrays.........................1.......................... 6...............................................................................................1....................................................... 5. 5............................ 28 Constant State Space .................1.............................................. 29 Local State Space ..................................................... 5...0 4............4...... 41 6................... Instruction Operands........................................................ 44 Rounding Modifiers ........... 42 Arrays as Operands .................................1.... Function declarations and definitions .........6...................5.............1.... 33 Restricted Use of Sub-Word Sizes ...................................1............................3.............................................................4.............................................. 5......... 5................................................. 5........................................................................................ and Variables ......... 5.....................................................

...... 10...............................................................................................................1........................... 8....................1................................................ 168 Chapter 11........... 62 8..... 10.................. 122 Control Flow Instructions ....................8.................... 162 Debugging Directives .. 55 PTX Instructions .. 160 Performance-Tuning Directives ........... 11......... 55 8..................... 81 Comparison and Selection Instructions ..................................9..... 7........ 8... 149 Chapter 10........7...........4.............1..............7................................................. 172 Unimplemented Features Remaining .......1............................. 11..................................1.3.................................... 170 New Features ..... 2010 iii ............................................................................7.......... 52 Variadic functions .........6................ Divergence of Threads in Control Constructs . Type Information for Instructions and Operands .....................7...... 147 8......... 60 8... 8......................... 8.................... Directives .2..... 8.7...... 63 Integer Arithmetic Instructions ........................................ 11. 100 Logic and Shift Instructions ........................................................................................................1........................................... 8...........................................3....... 8.................... 10.............4...................... 157 Specifying Kernel Entry Points and Functions ........... 157 10......................................4............7.............................................................................2......3.............................7..2............................................................................................................. 166 Linking Directives .............................. 7.................... 8........................................6............................................................ 132 Video Instructions .................1...... 104 Data Movement and Conversion Instructions . Release Notes .............................................................x .......7...... 129 Parallel Synchronization and Communication Instructions .......................... Format and Semantics of Instruction Descriptions .....................3.......................... 8................... 10......... 63 Floating-Point Instructions ....... 59 Operand Size Exceeding Instruction-Type Size ......................................................................7.....................................................2............................................. 169 11.................................. 140 Miscellaneous Instructions............................................. 8...........................................1........ 62 Semantics ............... 8........................... Instruction Set ................5........................ 54 Chapter 8.................. Chapter 9................. 57 Manipulating Predicates ........................................................................................................................ 108 Texture and Surface Instructions ......................10....................2....................................................................................................... 8...........1..... 58 8. 62 Machine-Specific Semantics of 16-bit Code ............................7.....................................3......................................................... Changes in Version 2...6.....................7........... PTX Version and Target Directives ..... 56 Comparisons ..................4............................ 170 Semantic Changes and Clarifications ...........1................................7.................1......................................................6..... Changes from PTX 1........ 8..................................... 8. 8............3....................................................1... 172 January 24............................................2. Instructions .....................................7.............. 55 Predicated Execution ....................................................................... 53 Alloca .......... 8...........0 .............................3............................... Special Registers .................................5..1...............

....................... 2010 ...............PTX ISA Version 2......0 Appendix A... Descriptions of ..pragma Strings........... 173 iv January 24........

.................................................................................. 58 Floating-Point Comparison Operators Testing for NaN . 65 Integer Arithmetic Instructions: sub................... Table 25......... 59 Relaxed Type-checking Rules for Source Operands .................................................. 68 Integer Arithmetic Instructions: mul24 ................................................................................... 69 Integer Arithmetic Instructions: mad24 .. 28 Fundamental Type Specifiers .......................... 64 Integer Arithmetic Instructions: sub ................... Table 7.............. 2010 v ................................ 66 Integer Arithmetic Instructions: subc ............... and Bit-Size Types .. Table 2............................. 66 Integer Arithmetic Instructions: mul ............. Table 18.................................................................................... 47 Operators for Signed Integer................................ 27 Properties of State Spaces ..................................... 19 Predefined Identifiers ............. Table 31.................. 25 State Spaces .............. Table 8......................... 57 Floating-Point Comparison Operators Accepting NaN .... 46 Cost Estimates for Accessing State-Spaces .............................................................................. Table 19..... Table 20..........List of Tables Table 1........................ Unsigned Integer....... Table 28...................................... Table 26........................................................ 67 Integer Arithmetic Instructions: mad ..................... Table 5......................................................................... Table 3.................. Table 29............ Table 16............................... Table 12...................................... 46 Integer Rounding Modifiers ...................................................................... Table 27.............................. Table 17.......................................................................................................... 64 Integer Arithmetic Instructions: add.. 20 Operator Precedence ...................................... 35 Convert Instruction Precision and Format .......................................................... Table 14............ Table 23.................................. Table 15...................................... 65 Integer Arithmetic Instructions: addc ......................................................................................................................... Table 13.......... 18 Reserved Instruction Keywords ........ 23 Constant Expression Evaluation Rules ........ Table 24..cc ....... Table 32..................... 45 Floating-Point Rounding Modifiers ................cc .................................................. 70 Integer Arithmetic Instructions: sad ................... 57 Floating-Point Comparison Operators ................................ 61 Integer Arithmetic Instructions: add ......... 33 Opaque Type Fields in Unified Texture Mode .............. Table 30........................ Table 21.................... 71 January 24............................................................... Table 9................................................................................................................................................................ 58 Type Checking Rules .......... Table 10....................................... Table 6............................................................................ Table 4............................................... 35 Opaque Type Fields in Independent Texture Mode ................... PTX Directives ................... Table 11............................................. 60 Relaxed Type-checking Rules for Destination Operands................................................... Table 22..................

............................... Table 65..... Table 63.............................................. Table 41...................................... 92 Floating-Point Instructions: max ....................... Table 69.................... Table 60...................... 103 vi January 24......................................................................... Table 52............................................................................................................... Table 37....................... Table 59................................................................................................ 94 Floating-Point Instructions: rsqrt ...................................... 97 Floating-Point Instructions: lg2 ............... Table 61..................... 74 Integer Arithmetic Instructions: clz ............... 91 Floating-Point Instructions: min ............................. 78 Integer Arithmetic Instructions: prmt ..................... 84 Floating-Point Instructions: sub ............................................................ 79 Summary of Floating-Point Instructions ........................................ Table 68... 95 Floating-Point Instructions: sin ................................................................................................................................................................................................................ Table 62............................... Table 54.......... Table 56...... 85 Floating-Point Instructions: mul .. Table 35................................... 96 Floating-Point Instructions: cos ...... 83 Floating-Point Instructions: add . Table 51............................................. 77 Integer Arithmetic Instructions: bfi .................. 87 Floating-Point Instructions: mad . Table 36.. Table 39...... Table 44........ 88 Floating-Point Instructions: div ......................................................................... 73 Integer Arithmetic Instructions: max ... Table 64..... Table 67...... Table 57............... 74 Integer Arithmetic Instructions: bfind ....... Table 66. Table 40..................................................................................... 73 Integer Arithmetic Instructions: popc ............................................................................................................ Table 47..............................................................................0 Table 33............. 99 Comparison and Selection Instructions: set ........................ Table 48...................................... 72 Integer Arithmetic Instructions: neg .............................. 71 Integer Arithmetic Instructions: rem ........ Table 43......................................................................................................................................................... Table 53........................................................................................................................................ 76 Integer Arithmetic Instructions: bfe ......... Table 55........................................ Table 50............................................................... Table 49........................................................ 83 Floating-Point Instructions: copysign ........ 86 Floating-Point Instructions: fma ....................... Integer Arithmetic Instructions: div ............................................................. Table 34.......... 75 Integer Arithmetic Instructions: brev .....................................PTX ISA Version 2.............................................. 90 Floating-Point Instructions: abs ........ Table 38............................................ Table 58................................. 93 Floating-Point Instructions: sqrt ................... Table 42............................ 72 Integer Arithmetic Instructions: min .......................................................................... 2010 ................................................. 92 Floating-Point Instructions: rcp .... Table 46................................................................... 101 Comparison and Selection Instructions: setp ..................... 91 Floating-Point Instructions: neg ................. 98 Floating-Point Instructions: ex2 .............................................................................................. 102 Comparison and Selection Instructions: selp ... 82 Floating-Point Instructions: testp .............. 103 Comparison and Selection Instructions: slct .................................. 71 Integer Arithmetic Instructions: abs .......................... Table 45................................

............ 118 Data Movement and Conversion Instructions: isspacep ........................................................ Table 85.................................................................... Table 82..................... vshr ........ 106 Logic and Shift Instructions: shl .................................................................................... prefetchu ....... Table 89... Table 73.............................................................. 113 Data Movement and Conversion Instructions: ldu ....................... Table 93.............. 116 Data Movement and Conversion Instructions: prefetch......................................................................................... Table 94....... Table 91..................................... 120 Texture and Surface Instructions: tex ........................... Table 80.................... 137 Parallel Synchronization and Communication Instructions: vote ... Table 77. 2010 vii ..... 142 Video Instructions: vshl......... Table 96........................................ 119 Data Movement and Conversion Instructions: cvt ....... Table 104.... 106 Logic and Shift Instructions: cnot ..................... 135 Parallel Synchronization and Communication Instructions: red ............................. Table 98.................................. Table 106................................ Table 103....... Table 92......... vmax ....................................................................... 126 Texture and Surface Instructions: sured......................................... 134 Parallel Synchronization and Communication Instructions: atom ....... Table 71. Logic and Shift Instructions: and ...................... 107 Logic and Shift Instructions: shr .................... 115 Data Movement and Conversion Instructions: st .................. 125 Texture and Surface Instructions: sust ......... 111 Data Movement and Conversion Instructions: mov ......................... vsub............ Table 81. 124 Texture and Surface Instructions: suld ......................................................... Table 86. 129 Control Flow Instructions: @ ........ 119 Data Movement and Conversion Instructions: cvta .....Table 70............... 133 Parallel Synchronization and Communication Instructions: membar ........... 130 Control Flow Instructions: ret .... 112 Data Movement and Conversion Instructions: ld .................. Table 101........................................................................................................ 105 Logic and Shift Instructions: or .............................. vabsdiff..... 106 Logic and Shift Instructions: not ........................................................................... 131 Parallel Synchronization and Communication Instructions: bar ... 128 Control Flow Instructions: { } ................... Table 105.............. Table 84............ 130 Control Flow Instructions: call ............. Table 79.... Table 100............................ 143 January 24.............................. 109 Cache Operators for Memory Store Instructions .......... vmin..... Table 90................................ Table 97........................................................................................ Table 76................................ Table 88................................................................ 110 Data Movement and Conversion Instructions: mov ... 107 Cache Operators for Memory Load Instructions ........................................................... Table 95..................................... 127 Texture and Surface Instructions: suq .... Table 75.................................................................... Table 87....... Table 72....................................... Table 83... Table 99.......................... 139 Video Instructions: vadd............ 129 Control Flow Instructions: bra ............................................... 105 Logic and Shift Instructions: xor ..................................................................................................................................................................... Table 102.................... 123 Texture and Surface Instructions: txq ................. Table 74.............. 131 Control Flow Instructions: exit ....................... Table 78................................

............................. Table 123............................. 155 Special Registers: %lanemask_gt ....................................... Table 124............. 161 Performance-Tuning Directives: .......................................................................................................................................................... 152 Special Registers: %smid ............................................................................................... 160 Kernel and Function Directives: ....................................................................................... Table 132............................................. Table 118.............maxnctapersm (deprecated) ............... 146 Miscellaneous Instructions: trap ............................................................... Table 140.....................PTX ISA Version 2.......................................section ............................. 154 Special Registers: %lanemask_le ........ Table 121...extern............................. Table 111... 153 Special Registers: %gridid .......... 150 Special Registers: %laneid ...........................................................minnctapersm ....... 167 Linking Directives: ................. Table 128..................................................................................................................... 167 Debugging Directives: ... Table 142..................................................................................... Table 133.......................loc .... Table 143........... Table 114.. 166 Debugging Directives: . 2010 .................................... 147 Special Registers: %tid .. 156 Special Registers: %clock64 .................. 156 PTX File Directives: ... Table 113......................................................................... Table 129............. Table 136.. Table 117..................... 157 PTX File Directives: .............................maxntid ......... 153 Special Registers: %nsmid .. Table 134......... Table 115...... Table 116.................... 155 Special Registers: %clock .............................................. %pm2.................................... 144 Video Instructions: vset.............. 147 Miscellaneous Instructions: pmevent...... Table 135.................................. Table 139... Table 122................... 153 Special Registers: %lanemask_eq ................................target ................................................. Table 120.............................................. Table 108......... 151 Special Registers: %warpid ............. Table 141........................................................................................................ Table 127...... 151 Special Registers: %nwarpid ..................................0 Table 107.........................file .............................................................. Table 131..... Table 130................................. %pm1........... 163 Performance-Tuning Directives: ........pragma ................ 168 viii January 24.....................entry........... 158 Kernel and Function Directives: ............ 163 Performance-Tuning Directives: ........ 164 Performance-Tuning Directives: ....................................................... Video Instructions: vmad .... 147 Miscellaneous Instructions: brkpt ................... Table 109.................... 164 Performance-Tuning Directives: .......................................... 165 Debugging Directives: @@DWARF ............................................................................................................................. Table 110..func .................................... 154 Special Registers: %lanemask_lt ............ 151 Special Registers: %ctaid .................................. Table 137......................... Table 119...... 156 Special Registers: %pm0..version..... 150 Special Registers: %ntid ............................................. 152 Special Registers: %nctaid . 167 Debugging Directives: .maxnreg ........................................ 154 Special Registers: %lanemask_ge ..... Table 138... Table 126.... Table 125................................................................... Table 112.................................................. %pm3 ..................................................................................................................................................................................

...........................................................Table 144.............................. 168 Pragma Strings: “nounroll” ....visible........................ 2010 ix .................... 173 January 24............. Linking Directives: .... Table 145.................

0 x January 24. 2010 .PTX ISA Version 2.

video encoding and decoding.2. PTX programs are translated at install time to the target hardware instruction set. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Data-parallel processing maps data elements to parallel processing threads. 1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). from general signal processing or physics simulation to computational finance or computational biology.1. image scaling. high-definition 3D graphics. Introduction This document describes PTX. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. and pattern recognition can map image blocks and pixels to parallel processing threads. the programmable GPU has evolved into a highly parallel. multithreaded. and because it is executed on many data elements and has high arithmetic intensity. stereo vision. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. 2010 1 . It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. In fact. PTX exposes the GPU as a data-parallel computing device. image and media processing applications such as post-processing of rendered images. 1. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. Because the same program is executed for each data element. the memory access latency can be hidden with calculations instead of big data caches. Similarly. which are optimized for and translated to native target-architecture instructions. January 24. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. there is a lower requirement for sophisticated flow control. PTX defines a virtual machine and ISA for general purpose parallel thread execution. many-core processor with tremendous computational horsepower and very high memory bandwidth.Chapter 1.

fma. and architecture tests. The mad. A “flush-to-zero” (.0 is in improved support for the IEEE 754 floating-point standard.rm and .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. The mad.1. performance kernels. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.ftz) modifier may be used to enforce backward compatibility with sm_1x.x code will continue to run on sm_1x targets as well. Instructions marked with .PTX ISA Version 2. When code compiled for sm_1x is executed on sm_20 devices.f32 for sm_20 targets. sub. and all PTX 1. and the introduction of many new instructions. atomic. The changes from PTX ISA 1.0 is a superset of PTX 1. 1.f32 instruction also supports .x features are supported on the new sm_20 target.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. addition of generic addressing to facilitate the use of general-purpose pointers.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.f32 maps to fma.rn. Both fma.f32 and mad.0 PTX ISA Version 2. The fma.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. A single-precision fused multiply-add (fma) instruction has been added. Facilitate hand-coding of libraries.rp rounding modifiers for sm_20 targets.x.f32. and video instructions.3. Improved Floating-Point Support A main area of change in PTX 2. 1. and mul now support . Provide a code distribution ISA for application and middleware developers. barrier. reduction.f32 require a rounding modifier for sm_20 targets. Most of the new features require a sm_20 target. PTX 2. Legacy PTX 1.f32 requires sm_20.sat modifiers. Provide a machine-independent ISA for C/C++ and other compilers to target. The main areas of change in PTX 2. Provide a common source-level ISA for optimizing code generators and translators. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.3. including integer.0 are improved support for IEEE 754 floating-point operations. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.ftz and . Achieve performance in compiled applications comparable to native GPU performance. mad. PTX ISA Version 2. which map PTX to specific target machines. Single-precision add.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. surface. • • • 2 January 24. memory. 2010 .

Instructions prefetch and prefetchu have been added. ldu. and shared state spaces. These are indicated by the use of a rounding modifier and require sm_20.4. 2010 3 . Instructions testp and copysign have been added. Surface instructions support additional clamp modifiers. In PTX 2. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. and shared addresses to generic addresses. instructions ld. isspacep.clamp and .. local. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. and sqrt with IEEE 754 compliant rounding have been added.3. these changes bring PTX 2.and double-precision div. Introduction • Single.zero. and directives are introduced in PTX 2. NOTE: The current version of PTX does not implement the underlying. and vice versa. e. Generic addressing unifies the global. special registers.g.e. st. atom.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. and red now support generic addressing.2. suld. rcp.3. so recursion is not yet supported. stack-based ABI. 1. stack layout. New Instructions The following new instructions. PTX 2. local. and Application Binary Interface (ABI). i.0 closer to full compliance with the IEEE 754 standard. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. allowing memory instructions to access these spaces without needing to specify the state space. prefetch. January 24. A new cvta instruction has been added to convert global.3. • Taken as a whole. cvta. st. 1. Cache operations have been added to instructions ld. . and shared addresses to generic address and vice-versa has been added. and sust. 1.Chapter 1. Surface Instructions • • Instruction sust now supports formatted surface stores. for prefetching to specified level of memory hierarchy. Generic Addressing Another major change is the addition of generic addressing.3. Instruction cvta for converting global.0. Support for an Application Binary Interface Rather than expose details of a particular calling convention. an address that is the same across all threads in a warp. prefetchu. local.0.

Barrier Instructions • • A system-level membar instruction.section.ballot.or}.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.shared have been extended to handle 64-bit data types for sm_20 targets.add.u32 and bar. Reduction. A “vote ballot” instruction.red.arrive instruction has been added. Other Extensions • • • Video instructions (includes prmt) have been added. Instructions {atom. %lanemask_{eq. .red}.pred have been added.sys. A bar.b32. bfi bit field extract and insert popc clz Atomic.popc. and Vote Instructions • • • New atomic and reduction instructions {atom.{and.red. has been added.PTX ISA Version 2.le.f32 have been added. New special registers %nsmid. Instructions bar. A new directive.gt} have been added. 2010 . has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. membar. 4 January 24. has been added. %clock64.ge.red}. vote. bar now supports an optional thread count and register operands.lt.

Chapter 1. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 5 describes state spaces. Chapter 11 provides release notes for PTX Version 2.4.0. Chapter 3 gives an overview of the PTX virtual machine model. January 24. types. calling convention. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and variable declarations. Chapter 10 lists the assembly directives supported in PTX. Chapter 7 describes the function and call syntax. Chapter 4 describes the basic syntax of the PTX language. Chapter 6 describes instruction operands. 2010 5 . Introduction 1. Chapter 8 describes the instruction set. Chapter 9 lists special registers.

PTX ISA Version 2. 2010 .0 6 January 24.

To that effect. but independently on different data. and results across the threads of the CTA. or 3D shape specified by a three-element vector ntid (with elements ntid.y. compute addresses. data-parallel. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. assign specific input and output positions. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. A cooperative thread array. Programming Model 2. or host: In other words. tid. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. or CTA. More precisely.x. compute-intensive portions of applications running on the host are off-loaded onto the device. work.x. 2. January 24. (with elements tid. It operates as a coprocessor to the main CPU. 2010 7 . and ntid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. The vector ntid specifies the number of threads in each CTA dimension. is an array of threads that execute a kernel concurrently or in parallel. and select work to perform.z). Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.2. To coordinate the communication of the threads within the CTA. 2D.y.2. 2. a portion of an application that is executed many times. or 3D CTA. The thread identifier is a three-element vector tid.1. can be isolated into a kernel function that is executed on the GPU as many different threads. Each thread has a unique thread identifier within the CTA.z) that specifies the thread’s position within a 1D. ntid. Cooperative thread arrays (CTAs) implement CUDA thread blocks.Chapter 2. Programs use a data parallel decomposition to partition inputs. Each CTA has a 1D. and tid.1. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. 2D. Each CTA thread uses its thread identifier to determine its assigned role. Threads within a CTA can communicate with each other.

2.0 Threads within a CTA execute in SIMT (single-instruction. Each grid of CTAs has a 1D. Threads within a warp are sequentially numbered. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. 2D . so that the total number of threads that can be launched in a single kernel invocation is very large. Multiple CTAs may execute concurrently and in parallel.PTX ISA Version 2. because threads in different CTAs cannot communicate and synchronize with each other. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). multiple-thread) fashion in groups called warps. CTAs that execute the same kernel can be batched together into a grid of CTAs. such that the threads execute the same instructions at the same time. %ntid.2.2. However. which may be used in any instruction where an immediate operand is allowed. read-only special registers %tid. WARP_SZ. or 3D shape specified by the parameter nctaid. Threads may read and use these values through predefined. Some applications may be able to maximize performance with knowledge of the warp size. or sequentially. 2010 . Each grid also has a unique temporal grid identifier (gridid). The warp size is a machine-dependent constant. The host issues a succession of kernel invocations to the device. depending on the platform. Typically. A warp is a maximal subset of threads from a single CTA. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. so PTX includes a run-time immediate constant. 8 January 24. %nctaid. This comes at the expense of reduced thread communication and synchronization. %ctaid. and %gridid. a warp has 32 threads.

0) CTA (1. 2) Thread (1. 2) Thread (4. 0) CTA (0. 0) Thread (0. 2) Thread (2. 0) Thread (2. 1) Thread (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (3.Chapter 2. Thread Batching January 24. 2010 9 . 0) Thread (1. 1) Thread (0. 1) Grid 2 Kernel 2 CTA (1. 1) CTA (1. 1) Thread (4. 1) Thread (1. 2) Thread (3. A grid is a set of CTAs that execute independently. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) CTA (2. 0) Thread (4. 1) Thread (0. Figure 1. 0) Thread (3. 1) CTA (2.

There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.3. referred to as host memory and device memory. Texture memory also offers different addressing modes. 10 January 24. 2010 . and texture memory spaces are persistent across kernel launches by the same application. The global. for more efficient transfer. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. The device memory may be mapped and read or written by the host. constant. or.PTX ISA Version 2. Finally.0 2. as well as data filtering. The global. Each thread has a private local memory. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. respectively. constant. for some specific data formats. and texture memory spaces are optimized for different memory usages. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. all threads have access to the same global memory. Both the host and the device maintain their own local memory.

1) Grid 1 Global memory Block (0. 1) Block (1. 0) Block (1. 1) Block (2. 0) Block (0. 1) Block (0. 0) Block (0. 2010 11 . 0) Block (1. 1) Block (1. 2) Figure 2.Chapter 2. 2) Block (1. 0) Block (2. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. Memory Hierarchy January 24.

PTX ISA Version 2. 2010 .0 12 January 24.

and each scalar thread executes independently with its own instruction address and register state. the multiprocessor employs a new architecture we call SIMT (single-instruction. (This term originates from weaving.Chapter 3. Parallel Thread Execution Machine Model 3. A warp executes one common instruction at a time. Branch divergence occurs only within a warp. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. The multiprocessor SIMT unit creates. different warps execute independently regardless of whether they are executing common or disjointed code paths. a multithreaded instruction unit. manages. At every instruction issue time. the warp serially executes each branch path taken. and executes threads in groups of parallel threads called warps. It implements a single-instruction barrier synchronization. allowing. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. and on-chip shared memory. A multiprocessor consists of multiple Scalar Processor (SP) cores. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs).1. so full efficiency is realized when all threads of a warp agree on their execution path. schedules. If threads of a warp diverge via a data-dependent conditional branch. new blocks are launched on the vacated multiprocessors. When a host program invokes a kernel grid. and when all paths complete. a voxel in a volume. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. The multiprocessor maps each thread to one scalar processor core. The way a block is split into warps is always the same. increasing thread IDs with the first warp containing thread 0. To manage hundreds of threads running several different programs. January 24. each warp contains threads of consecutive. When a multiprocessor is given one or more thread blocks to execute. for example. As thread blocks terminate.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. manages. multiple-thread). 2010 13 . The multiprocessor creates. a cell in a grid-based computation). The threads of a thread block execute concurrently on one multiprocessor. disabling threads that are not on that path. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. the first parallel thread technology. and executes concurrent threads in hardware with zero scheduling overhead. the threads converge back to the same execution path. it splits them into warps that get scheduled by the SIMT unit.

modify. as well as data-parallel code for coordinated threads. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. but the order in which they occur is undefined.PTX ISA Version 2. the kernel will fail to launch. SIMT enables programmers to write thread-level parallel code for independent. A key difference is that SIMD vector organizations expose the SIMD width to the software. write to that location occurs and they are all serialized.0 SIMT architecture is akin to SIMD (Single Instruction. the number of serialized writes that occur to that location and the order in which they occur is undefined. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. and writes to the same location in global memory for more than one of the threads of the warp. • The local and global memory spaces are read-write regions of device memory and are not cached. on the other hand. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. If an atomic instruction executed by a warp reads. 2010 . scalar threads. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. require the software to coalesce loads into vectors and manage divergence manually. 14 January 24. which is a read-only region of device memory. In contrast with SIMD vector machines. Vector architectures. As illustrated by Figure 3. the programmer can essentially ignore the SIMT behavior. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. modifies. each read. whereas SIMT instructions specify the execution and branching behavior of a single thread. which is a read-only region of device memory. but one of the writes is guaranteed to succeed. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. In practice. If there are not enough registers or shared memory available per multiprocessor to process at least one block. For the purposes of correctness. however. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A multiprocessor can execute as many as eight thread blocks concurrently. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge.

Chapter 3. 2010 15 . Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Figure 3.

0 16 January 24. 2010 .PTX ISA Version 2.

All whitespace characters are equivalent. Lines are separated by the newline character (‘\n’). #if.target directive specifying the target architecture assumed. #endif. #define. 4. whitespace is ignored except for its use in separating tokens in the language. #line.2. followed by a . Comments in PTX are treated as whitespace. The C preprocessor cpp may be used to process PTX source files. and using // to begin a comment that extends to the end of the current line. See Section 9 for a more information on these directives. Source Format Source files are ASCII text. #else. January 24. The following are common preprocessor directives: #include. Comments Comments in PTX follow C/C++ syntax. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.Chapter 4. using non-nested /* and */ for comments that may span multiple lines.version directive specifying the PTX language version. Each PTX file must begin with a . #ifdef. Syntax PTX programs are a collection of text source files. 4.1. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. PTX is case sensitive and uses lowercase for keywords. Pseudo-operations specify symbol and addressing management. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Lines beginning with # are preprocessor directives. 2010 17 .

Instructions have an optional guard predicate which controls conditional execution. All instruction keywords are reserved tokens in PTX.maxnreg . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. so no conflict is possible with user-defined identifiers. constant expressions. shl.3. Statements A PTX statement is either a directive or an instruction. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.target . r2. where p is a predicate register.3.section . Directive Statements Directive keywords begin with a dot. ld. Table 1. Operands may be register variables. and terminated with a semicolon. .entry .reg .b32 r1.align . The guard predicate may be optionally negated.file PTX Directives . mov.5. .global . 2.global. The guard predicate follows the optional label and precedes the opcode. 18 January 24.reg .func .visible 4. and is written as @p. followed by source operands.minnctapersm . or label names. The destination operand is first.tex .2.0 4.extern .b32 add. r1.sreg .global start: .b32 r1.3. %tid. written as @!p. Examples: . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.param .f32 array[N].maxntid .local .1. address expressions.b32 r1.f32 r2.shared .x.maxnctapersm .PTX ISA Version 2. r2.version .loc .pragma . array[r1]. Statements begin with an optional label and end with a semicolon. 2010 . r2. 0. Instruction keywords are listed in Table 2.const .

Syntax Table 2. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4.

or percentage character followed by one or more letters. between user-defined variable names and compiler-generated names. e. PTX predefines one constant and a small number of special registers that begin with the percentage sign.PTX ISA Version 2. or they start with an underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. Many high-level languages such as C and C++ follow similar rules for identifier names. Table 3. dollar.0 4. underscore. The percentage sign can be used to avoid name conflicts. underscore. PTX allows the percentage sign as the first character of an identifier. listed in Table 3.4. %pm3 WARP_SZ 20 January 24. digits. or dollar characters. 2010 . except that the percentage sign is not allowed. digits. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. ….g. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.

s64 or the unsigned suffix is specified. Syntax 4. i. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. Integer literals may be written in decimal.5.s64) unless the value cannot be fully represented in . octal. 0[fF]{hexdigit}{8} // single-precision floating point January 24. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.5.u64). where the behavior of the operation depends on the operand types. 2010 21 . in which case the literal is unsigned (. there is no suffix letter to specify size. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. and bit-size types. Unlike C and C++.u64. i.5. or binary notation. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. the constant begins with 0d or 0D followed by 16 hex digits. Constants PTX supports integer and floating-point constants and constant expressions. 4. To specify IEEE 754 single-precision floating point values. Type checking rules remain the same for integer. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. the constant begins with 0f or 0F followed by 8 hex digits. each integer constant is converted to the appropriate size based on the data or instruction type at its use. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.. the sm_1x and sm_20 targets have a WARP_SZ value of 32. These constants may be used in data initialization and as operands to instructions. 4.s64 or . integer constants are allowed and are interpreted as in C. floating-point. For predicate-type data and instructions. The syntax follows that of C. When used in an instruction or data initialization. To specify IEEE 754 doubleprecision floating point values.e.2. literals are always represented in 64-bit double-precision format. every integer constant has type .Chapter 4. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.1. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.e. hexadecimal. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Floating-point literals may be written with an optional decimal point and an optional signed exponent.. zero values are FALSE and non-zero values are TRUE.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

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or .u64 .f64 use usual conversions .u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64 same as 1st operand . Table 5.u64 .f64 converted type constant literal + ! ~ Cast Binary (.u64 .f64 use usual conversions .u64 1st unchanged.s64 . 2nd is .f64 : .u64 .f64 use usual conversions .s64 .u64 .s64 .s64) + .s64 .s64 .s64 . .Chapter 4.5.s64 .u64) (.f64 integer .f64 same as source .u64. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 converted type .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. 2010 25 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .6.f64 integer integer integer integer integer int ?.s64 .s64.u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 integer . Syntax 4.

0 26 January 24.PTX ISA Version 2. 2010 .

The list of state spaces is shown in Table 4. defined per-thread. shared by all threads. Read-only. Local memory.reg .Chapter 5. 2010 27 .tex January 24. the kinds of resources will be common across platforms.const . Global memory. addressability. All variables reside in some state space. Name State Spaces Description Registers.local . Shared. State Spaces A state space is a storage area with particular characteristics. Global texture memory (deprecated). and level of sharing between threads. pre-defined. and Variables While the specific resources available in a given target GPU will vary. 5. fast. . access speed. Table 6. and these resources are abstracted in PTX through state spaces and data types. defined per-grid.shared . or Function or local parameters. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Special registers. and properties of state spaces are shown in Table 5. State Spaces. Types.param .1.sreg . read-only memory. Kernel parameters. private to each thread. Addressable memory shared between threads in 1 CTA. platform-specific. access rights. The characteristics of a state space include its size.global .

floating point. or 128-bits.param instruction. it is not possible to refer to the address of a register. 28 January 24.0 Table 7. scalar registers have a width of 8-. platform-specific registers. 3 Accessible only via the tex instruction. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. 32-. When the limit is exceeded. Register size is restricted. Registers differ from the other state spaces in that they are not fully addressable. 2 Accessible via ld.sreg) state space holds predefined.shared . clock counters. unsigned integer. and thread parameters.PTX ISA Version 2. causing changes in performance. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . or as elements of vector tuples.2. 5.1.global . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).sreg . Register State Space Registers (. 64-.reg . For each architecture. such as grid. All special registers are predefined. register variables will be spilled to memory. 1 Accessible only via the ld.local . aside from predicate registers which are 1-bit.param and st.1. The number of registers is limited. i.reg state space) are fast storage locations. Registers may be typed (signed integer. st. and performance monitoring registers. the parameter is then located on the stack frame and its address is in the .1.local state space. and cvt instructions. The most common use of 8-bit registers is with ld. Device function input parameters may have their address taken via mov. Special Register State Space The special register (. and vector registers have a width of 16-. 32-. and will vary from platform to platform. or 64-bits.param (used in functions) . predicate) or untyped. 16-.const . CTA.tex Restricted Yes No3 5. Address may be taken via mov instruction. Registers may have alignment boundaries required by multi-word loads and stores.param (as input to kernel) . 2010 .e..param instructions.

1. and atom. all addresses are in global memory are shared. where the size is not known at compile time. For the current devices. Multiple incomplete array variables declared in the same bank become aliases. [const_buffer+4].const) state space is a read-only memory. The size is limited.local and st. The remaining banks may be used to implement “incomplete” constant arrays (in C.global) state space is memory that is accessible by all threads in a context. Banks are specified using the . ld. For example. there are eleven 64KB banks. Threads wait at the barrier until all threads in the CTA have arrived.const[bank] modifier. st. each pointing to the start address of the specified constant bank.extern .b32 const_buffer[]. All memory writes prior to the bar.5. This reiterates the kind of parallelism available in machines that run PTX. 5. the store operation updating a may still be in flight.global. the declaration . initialized by the host. the bank number must be provided in the state space of the load instruction. The constant memory is organized into fixed size banks. For any thread in a context. the stack is in local memory. results in const_buffer pointing to the start of constant bank two. Sequential consistency is provided by the bar. and Variables 5. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.3. Threads must be able to do their work without waiting for other threads to do theirs.local) is private memory for each thread to keep its own data.1. In implementations that support a stack. Use ld. Global State Space The global (. To access data in contant banks 1 through 10. b = b – 1.1. Global memory is not sequentially consistent. If no bank number is given. For example. as in lock-free and wait-free style programming. This pointer can then be used to access the entire 64KB constant bank. It is typically standard memory with cache.const[2] . State Spaces. Types. By convention.global.sync instruction. Local State Space The local state space (. It is the mechanism by which different CTAs and different grids can communicate. for example). 2010 29 . Module-scoped local memory variables are stored at fixed addresses.sync instruction are guaranteed to be visible to any reads after the barrier instruction. bank zero is used.b32 const_buffer[]. as it must be allocated on a perthread basis. // load second word 5. where bank ranges from 0 to 10.local to access local variables.b32 %r1. Constant State Space The constant (.Chapter 5.const[2]. If another thread sees the variable b change.extern .4. bank zero is used for all statically-sized constant variables. an incomplete array in bank 2 is accessed as follows: .global to access global variables.const[2] . whereas local memory variables declared January 24. Consider the case where one thread executes the following two assignments: a = a + 1. Use ld.

per-kernel versus per-thread). Note: The location of parameter space is implementation specific. For example. … 30 January 24. [%ptr].6. The kernel parameter variables are shared across all CTAs within a grid. The resulting address is in the . Note that PTX ISA versions 1.reg . ld. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.f64 %d. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). typically for passing large structures by value to a function.param .0 within a function or kernel body are allocated on the stack. No access protection is provided between parameter and global space in this case.param .b32 N. [buffer]. Example: . [N].param) state space is used (1) to pass input arguments from the host to the kernel. ld. 2010 .param. Values passed from the host to the kernel are accessed through these parameter variables using ld.b32 len ) { . The address of a kernel parameter may be moved into a register using the mov instruction. In implementations that do not support a stack.1. device function parameters were previously restricted to the register state space.1.param.6.param .f64 %d. The use of parameter state space for device function parameters is new to PTX ISA version 2. 5. Therefore.param. (2a) to declare formal input and return parameters for device functions called from within kernel execution.u32 %n. … Example: . len.u32 %ptr.entry foo ( . Kernel Function Parameters Each kernel function definition includes an optional list of parameters. %n.u32 %n.param space variables.param instructions.1.param state space.u32 %n.reg .param state space and is accessed using ld.param space. 5. Similarly. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.0 and requires target architecture sm_20.x supports only kernel function parameters in . in some implementations kernel parameters reside in global memory. read-only variables declared in the .PTX ISA Version 2.param instructions. These parameters are addressable. all local memory variables are stored at fixed addresses and recursive function calls are not supported. Parameter State Space The parameter (. ld.align 8 . . mov.reg . PTX code should make no assumptions about the relative locations or ordering of .u32 %ptr.b8 buffer[64] ) { .entry bar ( . .

it is illegal to write to an input parameter or read from a return parameter. ld. the caller will declare a locally-scoped .s32 %y. } mystruct.b32 N.param byte array variable that represents a flattened C structure or union. Example: // pass object of type struct { double d. and so the address will be in the . State Spaces. }.param.param space is also required whenever a formal parameter has its address taken within the called function. In this case.param formal parameter having the same size and alignment as the passed argument.0 extends the use of parameter space to device function parameters.6. call foo.f64 %d.reg .local and st. .param. It is not possible to use mov to get the address of a return parameter or a locally-scoped . Function input parameters may be read via ld. .align 8 .reg .param and function return parameters may be written using st. passed to foo … .Chapter 5.param .reg . … See the section on function call syntax for more details.param. such as C structures larger than 8 bytes. Aside from passing structures by value. mystruct).f64 dbl. x. and Variables 5. Device Function Parameters PTX ISA version 2. In PTX.s32 [mystruct+8].b8 buffer[12] ) { .f64 %d. the address of a function input parameter may be moved into a register using the mov instruction. The most common use is for passing objects by value that do not fit within a PTX register.param space variable.align 8 .reg . This will be passed by value to a callee. Typically.param . … st. st.2. . Types.func foo ( . [buffer+8]. which declares a . [buffer].f64 [mystruct+0].1. int y.s32 x. is flattened. (4.b8 mystruct. int y. a byte array in parameter space is used. ld.reg . January 24. Note that the parameter will be copied to the stack if necessary. 2010 31 .local state space and is accessed via ld.param.s32 %y. . . .param. … } // code snippet from the caller // struct { double d.local instructions. dbl.

shared to access shared variables. tex_d.texref. 2010 . One example is broadcast.7. 32 January 24. An address in shared memory can be read and written by any thread in a CTA. 5. Multiple names may be bound to the same physical texture identifier.texref variables in the . is equivalent to . The .tex variables are required to be defined in the global scope. and . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. tex_c. tex_f.tex directive will bind the named texture memory variable to a hardware texture identifier. Use ld.u64.shared and st. The texture name must be of type . a legacy PTX definitions such as . tex_d. It is shared by all threads in a context.u32 .u32 tex_a. and variables declared in the .tex directive is retained for backward compatibility. where all threads read from the same address. where texture identifiers are allocated sequentially beginning with zero.texref tex_a.1. Shared memory typically has some optimizations to support the sharing.u32 .global state space.global . Example: .tex state space are equivalent to module-scoped .texref type and Section 8.u32 tex_a.tex) state space is global memory accessed via the texture instruction. For example.7.tex . Shared State Space The shared (.tex .1.0 5. Physical texture resources are allocated on a per-module granularity. Texture State Space (deprecated) The texture (. The .3 for the description of the .u32 .tex .6 for its use in texture instructions.shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex . A texture’s base address is assumed to be aligned to a 16-byte boundary. Texture memory is read-only. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). See Section 5.PTX ISA Version 2.u32 or . An error is generated if the maximum number of physical resources is exceeded.8.tex . and programs should instead reference texture memory through variables of type . Another is sequential access from sequential threads.

and cvt instructions. . Two fundamental types are compatible if they have the same basic type and are the same size. . stored. and converted using regular-width registers. ld.f16. . and . and Variables 5.pred Most instructions have one or more type specifiers. For example. but typed variables enhance program readability and allow for better operand type checking.u32. Operand types and sizes are checked against instruction types for compatibility. The same typesize specifiers are used for both variable definitions and for typing instructions.f64 types. . . The bitsize type is compatible with any fundamental type having the same size.Chapter 5. . The following table lists the fundamental type specifiers for each basic type: Table 8. and instructions operate on these types. The . . Types. In principle.u64 .s8. so their names are intentionally short.f32 and . so that narrow values may be loaded. needed to fully specify instruction behavior.f64 .u8.f64 types. st. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . 2010 33 .2.2. January 24.b64 . For convenience.f32 and . A fundamental type specifies both a basic type and a size.2. .b8. 5. Signed and unsigned integer types are compatible if they have the same size. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. st.u16. the fundamental types reflect the native data types supported by the target architectures.s16. Register variables are always of a fundamental type.u8.f16 floating-point type is allowed only in conversions to and from .b16. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Restricted Use of Sub-Word Sizes The .2. or converted to other types and sizes. .b32. stored. . . Fundamental Types In PTX.s32. All floating-point instructions operate only on . Types 5.s8. State Spaces. . all variables (aside from predicates) could be declared using only bit-size types.f32.s64 .b8 instruction types are restricted to ld.1.

Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. sampler. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. For working with textures and samplers. In independent mode the fields of the . or performing pointer arithmetic will result in undefined results. sured). Creating pointers to opaque variables using mov.e. i. the resulting pointer may be stored to and loaded from memory. accessing the pointer with ld and st instructions. In the independent mode. texture and sampler information is accessed through a single . and surface descriptor variables. suld. and query instructions.texref handle.samplerref. base address. Texture.samplerref variables. sust. and Surface Types PTX includes built-in “opaque” types for defining texture. passed as a parameter to functions. opaque_var. 2010 . and overall size is hidden to a PTX program.. samplers. suq). or surfaces via texture and surface load/store instructions (tex.surfref. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. texture and sampler information each have their own handle. and de-referenced by texture and surface load. PTX has two modes of operation. In the unified mode. Retrieving the value of a named member via query instructions (txq. Referencing textures. Sampler.3.PTX ISA Version 2. but the pointer cannot otherwise be treated as an address. .0 5.texref. allowing them to be defined separately and combined at the site of usage in the program. hence the term “opaque”.u64} reg. 34 January 24. field ordering. The following tables list the named members of each type for unified and independent texture modes.{u32. and . since these properties are defined by . These types have named fields similar to structures. store. The three built-in types are . but all information about layout.texref type that describe sampler properties are ignored.

clamp_to_edge. State Spaces.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. 1 nearest. clamp_to_border 0. Member width height depth Opaque Type Fields in Independent Texture Mode . mirror. 1 ignored ignored ignored ignored . 2010 35 . clamp_to_border N/A N/A N/A N/A N/A . clamp_to_edge.Chapter 5. linear wrap. Types.samplerref values N/A N/A N/A N/A nearest. clamp_ogl. Member width height depth Opaque Type Fields in Unified Texture Mode . linear wrap.texref values in elements in elements in elements 0.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. mirror. and Variables Table 9.texref values . clamp_ogl.

As kernel parameters.param state space.PTX ISA Version 2. . .global .surfref my_surface_name. . filter_mode = nearest }.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global . At module scope. Example: . 2010 .texref tex1.global . Example: . 36 January 24.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global .global state space. the types may be initialized using a list of static expressions assigning values to the named members. When declared at module scope.global . these variables are declared in the .texref my_texture_name. these variables must be in the .samplerref my_sampler_name.

.pred p. an optional array size. 5.v4 .reg .v4 vector. . Variable Declarations All storage for data is specified with variable declarations. a variable declaration describes both the variable’s type and its state space.4.global .v4.u32 loc. . an optional initializer.f64 is not allowed.struct float4 { .global . PTX supports types for simple aggregate objects such as vectors and arrays. .b8 v. This is a common case for three-dimensional grids. Vectors must be based on a fundamental type. textures. // a length-4 vector of floats .f32 V.s32 i.const . 0}. for example.u16 uv. vector variables are aligned to a multiple of their overall size (vector length times base-type size). 5. // a length-2 vector of unsigned ints . Types. Vectors cannot exceed 128-bits in length.2.f32 bias[] = {-1. .global . and Variables 5. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .reg . 0. Three-element vectors may be handled by using a .f32 accel.u8 bg[4] = {0. // typedef . A variable declaration names the space in which the variable resides.0}.global .struct float4 coord.4. and they may reside in the register space. 1. and an optional fixed address for the variable.reg . etc. q.1. its type and size.f32 v0.0.4. 2010 37 .v4 . Every variable must reside in one of the state spaces enumerated in the previous section.v2 .v3 }. January 24.v1.v4 . . to enable vector load and store instructions which require addresses aligned to a multiple of the access size.Chapter 5. Variables In PTX.v4.v2. In addition to fundamental types.v2 or . Examples: . Predicate variables may only be declared in the register state space. 0. its name. Vectors Limited-length vector types are supported. .global . where the fourth element provides padding. State Spaces. Examples: . r.shared . // a length-4 vector of bytes By default.

label names appearing in initializers represent the address of the next instruction following the label. Similarly.global .f32 blur_kernel[][] = {{. Array Declarations Array declarations are provided to allow the programmer to reserve space.{.u8 rgba[3] = {{1. .0. // address of rgba into ptr Currently.s32 offset[][] = { {-1. 5.05}. Examples: .pred.s32 n = 10. variable initialization is supported only for constant and global state spaces. this can be used to statically initialize a pointer to a variable. . being determined by an array initializer. Variable names appearing in initializers represent the address of the variable.3. or is left empty. {0. Initializers are allowed for all types except .0}. Variables that hold addresses of variables or instructions should be of type .4.global .global .. Here are some examples: .4.0}.global .1.u64. {0..0. 38 January 24.0 5.1}.PTX ISA Version 2. 19*19 (361) halfwords are reserved (722 bytes).u16 kernel[19][19].0}}. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.u8 mailbox[128].4.05}}. A scalar takes a single value.4. The size of the array specifies how many elements should be reserved. 1} }.05.. To declare an array. where the variable name is followed by an equals sign and the initial value or values for the variable.f16 and .. The size of the dimension is either a constant expression.v4 .shared .b32 ptr = rgba. For the kernel declaration above.{.. {1.1. {0. . 0}. .0. -1}.local . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).global .05. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.u32 or .1.. 2010 . this can be used to initialize a jump table to be used with indirect branches or calls. .0. 0}.1. {0.1.

say one hundred. and may be preceded by an alignment specifier. ….b8 bar[8] = {0..0.4. Elements are bytes.0.5.4. January 24.. suppose a program uses a large number. These 100 register variables can be declared as follows: . State Spaces. not for individual elements. alignment specifies the address alignment for the starting address of the entire array. 5. The variable will be aligned to an address which is an integer multiple of byte-count. %r1. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. %r1. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. // declare %r0.align byte-count specifier immediately following the state-space specifier. .0. The default alignment for scalar and array variables is to a multiple of the base-type size. For example. Types.0. nor are initializers permitted. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.Chapter 5. Array variables cannot be declared this way. it is quite common for a compiler frontend to generate a large number of register names. Parameterized Variable Names Since PTX supports virtual registers. For arrays. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. named %r0. and Variables 5.reg .0.6.2. of .b32 variables. .const . %r99..0}.b32 %r<100>.align 4 . Rather than require explicit declaration of every name. Alignment is specified using an optional . 2010 39 . Examples: // allocate array at 4-byte aligned address. The default alignment for vector variables is to a multiple of the overall vector size.

2010 .0 40 January 24.PTX ISA Version 2.

st. Predicate operands are denoted by the names p. The bit-size type is compatible with every type having the same size. There is no automatic conversion between types. s. so operands for ALU instructions must all be in variables declared in the . Instruction Operands 6.3. as its job is to convert from nearly any data type to any other data type (and size).2.reg register state space.Chapter 6. Most instructions have an optional predicate guard that controls conditional execution. and a few instructions have additional predicate source operands. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. r. and cvt instructions copy data from one location to another. 6. The ld. PTX describes a load-store machine. The cvt (convert) instruction takes a variety of operand types and sizes. For most operations. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Operand Type Information All operands in instructions have a known type from their declarations. Integer types of a common size are compatible with each other. mov. the sizes of the operands must be consistent. The result operand is a scalar or vector variable in the register state space. Each operand type must be compatible with the type determined by the instruction template and instruction type.1. 2010 41 . 6. January 24. . Source Operands The source operands are denoted in the instruction descriptions by the names a. q. Instructions ld and st move data from/to addressable state spaces to/from registers. b. The mov instruction copies data between registers. and c.

tbl.s32 q.reg . and vectors. All addresses and address computations are byte-based.1. .v4 . . arrays. and immediate address expressions which evaluate at compile-time to a constant address.v4.reg . Examples include pointer arithmetic and pointer comparisons. [V]. address registers.gloal. address register plus byte offset.s32 mov.shared.0 6. . [tbl+12].const .shared . 2010 .global . Load and store operations move data between registers and locations in addressable state spaces. Arrays. The mov instruction can be used to move the address of a variable into a pointer. and Vectors Using scalar variables as operands is straightforward.PTX ISA Version 2.f32 ld.v4 . The syntax is similar to that used in many assembly languages. q. Address expressions include variable names. 6. ld. . . The address is an offset in the state space in which the variable is declared.const.u16 ld.reg .u16 r0.4. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. Here are a few examples: . r0.s32 tbl[256].[x]. there is no support for C-style pointer arithmetic. p.u32 42 January 24.f32 W. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. .reg . The interesting capabilities begin with addresses.4. Using Addresses.b32 p.u16 x. W.f32 V.

v4. and in move instructions to get the address of the label or function into a register.x.4.r V. The size of the array is a constant in the program.u32 s. A brace-enclosed list is used for pattern matching to pull apart vectors.b. mov. or by indexing into the array using square-bracket notation. and the identifier becomes an address constant in the space where the array is declared. c.global. The expression within square brackets is either a constant integer. b. Rd}. Vector elements can be extracted from the vector with the suffixes . Rc.v2. a[N-1]. and tex. Arrays as Operands Arrays of all types can be declared.w. [addr+offset2].v4 . // move address of a[1] into s 6.global. say {Ra. V2.f32 V. Examples are ld.b and . Elements in a brace-enclosed vector. it must be written as an address calculation prior to use. mov.d}. as well as the typical color fields . January 24.x V.z and . Vectors may also be passed as arguments to called functions.v4.u32 {a. . for use in an indirect branch or call.4.reg .c. . V. where the offset is a constant expression that is either added or subtracted from a register variable.u32 s.reg . Rb.f32 {a.a 6.g. a[1]. a[0]. . Array elements can be accessed using an explicitly calculated byte address.2. .u32 s. Instruction Operands 6.a. ld. which may improve memory performance.d}.z V.4. [addr+offset].global.w = = = = V. The registers in the load/store operations can be a vector.f32 ld.Chapter 6. which include mov. d.b V.c. Here are examples: ld. If more complicated indexing is desired.b.f32 a. a register variable. st. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. .r. ld.y V.3. 2010 43 . .y. or a braceenclosed list of similarly typed scalars.4. Vectors as Operands Vector operands are supported by a limited subset of instructions.g V. Vector loads and stores can be used to implement wide loads and stores. or a simple “register with constant offset” expression. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.global.

1.5. the u16 is zero-extended to s32.s32. Type Conversion All operands to all arithmetic.PTX ISA Version 2. and ~131. except for operations where changing the size and/or type is part of the definition of the instruction. For example. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 2010 . if a cvt.000 for f16). 44 January 24. and data movement instruction must be of the same type and size. logic.0 6.5. Operands of different sizes or types must be converted prior to the operation.u16 instruction is given a u16 source operand and s32 as a destination operand. 6. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.

January 24.u32 targeting a 32-bit register will first chop to 16-bits. then sign-extend to 32-bits. Notes 1 If the destination register is wider than the destination format. chop = keep only low bits that fit. Instruction Operands Table 11. zext = zero-extend. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.s16. u2f = unsigned-to-float. The type of extension (sign or zero) is based on the destination format.Chapter 6. f2u = float-to-unsigned. the result is extended to the destination register width after chopping. 2010 45 . f2s = float-to-signed. cvt. f2f = float-to-float. For example. s2f = signed-to-float.

rz . The following tables summarize the rounding modifiers.rpi Integer Rounding Modifiers Description round to nearest integer.PTX ISA Version 2. Modifier . 2010 .0 6.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. choosing even integer if source is equidistant between two integers.rm .rn . Table 12. Rounding Modifiers Conversion instructions may specify a rounding modifier.rni . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. In PTX.rzi .5.rmi . Modifier . there are four integer rounding modifiers and four floating-point rounding modifiers.2.

Operand Costs Operands from different state spaces affect the speed of an operation. Instruction Operands 6. Another way to hide latency is to issue the load instructions as early as possible. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Table 11 gives estimates of the costs of using different kinds of memory. The register in a store operation is available much more quickly. Much of the delay to memory can be hidden in a number of ways. 2010 47 .Chapter 6. Table 14. first access is high Notes January 24. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Registers are fastest. while global memory is slowest.6.

PTX ISA Version 2.0 48 January 24. 2010 .

Scalar and vector base-type input and return parameters may be represented simply as register variables. stack layout.1. together these specify the function’s interface. 2010 49 . we describe the features of PTX needed to achieve this hiding of the ABI. These include syntax for function definitions. The simplest function has no parameters or return values. January 24. and is represented in PTX as follows: . and Application Binary Interface (ABI). Abstracting the ABI Rather than expose details of a particular calling convention. function calls. In this section. A function must be declared or defined prior to being called. and memory allocated on the stack (“alloca”). parameter passing.func directive. and return values may be placed directly into register variables. functions are declared and defined using the . At the call. arguments may be register variables or constants. the function name. so recursion is not yet supported. A function declaration specifies an optional list of return parameters.Chapter 7.func foo { … ret. Function declarations and definitions In PTX. A function definition specifies both the interface and the body of the function. and an optional list of input parameters. … Here. Execution of the ret instruction within foo transfers control to the instruction following the call. execution of the call instruction transfers control to foo. or prototype. implicitly saving the return address. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. 7. support for variadic functions (“varargs”). NOTE: The current version of PTX does not implement the underlying. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. } … call foo. stack-based ABI.

param variable y is used in function definition bar to represent a formal parameter.b8 . st. // scalar args in .b8 .u32 %inc ) { add.param. First.param space variables are used in two ways. (%r1. [y+10].param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. .reg .c3. … st.b8 c1. … ld. In PTX. a .reg . Since memory accesses are required to be aligned to a multiple of the access size.param.f64 f1.param. st.reg . [y+8]. ld.4). Second.f1. consider the following C structure.s32 out) bar (. ret. ld. bumpptr. The . 50 January 24.reg space.param. note that . For example.f64 field are aligned.b8 c4.c2.b8 [py+ 8].param. byte array in .func (.align 8 py[12]. [y+0].param space call (%out).b8 c2.0 Example: .b32 c1.param. %rc2.param. %rd.param state space is used to pass the structure by value: . %rc1.u32 %res) inc_ptr ( . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . inc_ptr.reg . char c[4].reg .param.b64 [py+ 0].func (. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . c2.b8 c3.c1. [y+9]. this structure will be flattened into a byte array.u32 %res. ld.param space memory. .f64 f1.b8 [py+ 9]. ld.param. (%x.param . py).c4. %rc2.b8 [py+10].b8 [py+11].param. st. a . st. … … // computation using x. 2010 . [y+11]. } { .PTX ISA Version 2.u32 %ptr.align 8 y[12]) { .reg .param . } … call (%r1).s32 x. c4. . passed by value to a function: struct { double dbl.reg . %inc. }. … In this example. %rc1. %ptr. c3.

Typically. For .param variables.param instructions used for argument passing must be contained in the basic block with the call instruction. the corresponding argument may be either a . Note that the choice of . Supporting the .param or . In the case of .Chapter 7.param and ld.param variables or . size.param state space use in device functions. This enables backend optimization and ensures that the .param space formal parameters that are base-type scalar or vector variables. or a constant that can be represented in the type of the formal parameter.param argument must be declared within the local scope of the caller. • The . Parameters in .param space formal parameters that are byte arrays. Abstracting the ABI The following is a conceptual way to think about the .g. January 24. For a caller.param memory must be aligned to a multiple of 1.param or . size. For a callee. • • • For a callee.reg variables. 8.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The . • • Arguments may be . • • • Input and return parameters may be . 2010 51 . In the case of . The .reg state space in this way provides legacy support.reg space formal parameters. For a caller.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. and alignment.reg space variable of matching type and size. 2. The following restrictions apply to parameter passing. and alignment of parameters.param space byte array with matching type. In the case of .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. a .param arguments.reg variables. the argument must also be a . the corresponding argument may be either a . all st. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. A . • The .param byte array is used to collect together fields of a structure being passed by value.param state space is used to receive parameter values and/or pass return values back to the caller. or a constant that can be represented in the type of the formal parameter. or constants. .reg space variable with matching type and size.reg or .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. or 16 bytes.reg state space can be used to receive and return base-type scalar and vector values. 4..

0 7. PTX 1. In PTX ISA version 2.PTX ISA Version 2.1.1.0. and . formal parameters may be in either . and there was no support for array parameters.param byte array should be used to return objects that do not fit into a register.reg state space. Changes from PTX 1. PTX 2.x In PTX ISA version 1.0 restricts functions to a single return value.reg or . PTX 2. For sm_2x targets.param state space.x. formal parameters were restricted to . 2010 .x supports multiple return values for this purpose. Objects such as C structures were flattened and passed or returned using multiple registers. 52 January 24.0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays. and a .

u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. (2. setp. For %va_arg. call %va_end.u32 b. %s2). the size may be 1. or 8 bytes.func ( . (ap. %va_arg.u32 ap.reg . ctr. .reg . In both cases. %r3).reg . 4.func (. or 16 bytes.Chapter 7.. maxN. the alignment may be 1. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . 2.h and varargs.reg . … ) .func (. bra Loop.s32 result.u32. call (ap). or 4 bytes. bra Done. %va_start.b32 val) %va_arg (. … %va_start returns Loop: @p Done: January 24.reg .reg . To support functions with a variable number of arguments. . .s32 val.s32 result ) maxN ( .u32 N. 0x8000000. PTX provides a high-level mechanism similar to the one provided by the stdarg. iteratively access. . . ctr. Once all arguments have been processed. 0. result. %r1.reg . for %va_arg64. 2. the size may be 1. This handle is then passed to the %va_arg and %va_arg64 built-in functions. call (val). // default to MININT mov. variadic functions are declared with an ellipsis at the end of the input parameter list. 4.reg .func (.u32 align) . . 8. along with the size and alignment of the next data value to be accessed. Abstracting the ABI 7. N. Variadic functions NOTE: The current version of PTX does not support variadic functions. In PTX.b64 val) %va_arg64 (. maxN.reg .u32 a.func %va_end (. . 4. max. ) { .reg . (ap). (3.b32 ctr.b32 result.u32 sz. mov. %r2.reg .func okay ( … ) Built-in functions are provided to initialize.u32 ptr) %va_start .u32 ptr..pred p. } … call (%max).reg .reg .reg .u32 align) . %va_end is called to free the variable argument list handle.2. The function prototypes are defined as follows: . and end access to a list of variable arguments. ret. %s1. … call (%max). 2010 53 . 2.reg .reg . 4).func baz ( .u32 ptr. val. following zero or more fixed parameters: .h headers in C. .reg .ge p.u32 sz.

PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.u32 ptr ) %alloca ( .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.reg . To allocate memory.local instructions. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( . defined as follows: . If a particular alignment is required.reg .3. 54 January 24. Alloca NOTE: The current version of PTX does not support alloca. a function simply calls the built-in function %alloca.local and st.0 7.PTX ISA Version 2. 2010 . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. The array is then accessed with ld.

Chapter 8. opcode D. A. and C are the source operands. setp. We use a ‘|’ symbol to separate multiple destination registers. opcode D. B. the D operand is the destination operand. a.1. 8.s32. The setp instruction writes two destination registers. C. B. For instructions that create a result value. b. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. 2010 55 . opcode A. A. q = !(a < b). plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. while A. For some instructions the destination operand is optional. the semantics are described. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. January 24. In addition to the name and the format of the instruction. // p = (a < b). PTX Instructions PTX instructions generally have from zero to four operands. followed by some examples that attempt to show several possible instantiations of the instruction.2.lt p|q. opcode D. B. A. Instruction Set 8.

… // compare i to n // if false.PTX ISA Version 2. j. bra L1. 2010 . 1. So. Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 j. i.lt. q. predicate registers can be declared as . As an example. To implement the above example as a true conditional branch. the following PTX instruction sequence might be used: @!p L1: setp. 1. add 1 to j To get a conditional branch or conditional function call.lt. branch over 56 January 24.s32 p. n. predicate registers are virtual and have . use a predicate to control the execution of the branch or call instructions.s32 j. This can be written in PTX as @p setp. where p is a predicate variable.0 8. Predicated Execution In PTX.pred p. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. add. // p = (i < n) // if i < n.s32 p. add.3. optionally negated. consider the high-level code if (i < n) j = j + 1. n. Instructions without a guard predicate are executed unconditionally. i.reg . r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.pred as the type specifier. j.

3. lt. ne. ordering comparisons are not defined for bit-size types.2. ne (not-equal). Comparisons 8. 2010 57 . The bit-size comparisons are eq and ne. the result is false. Unsigned Integer.3. Table 15. unsigned integer. lo (lower). and ge (greater-than-or-equal). and bitsize types. If either operand is NaN. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. ne.1. hi (higher).3. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. gt.1. le (less-than-or-equal). The following table shows the operators for signed integer.Chapter 8.1. Instruction Set 8. ls (lower-or-same).1. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. le. The unsigned comparisons are eq. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. lt (less-than). gt (greater-than). Table 16. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). and hs (higher-or-same). ge.

Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.u32 %r1. or.2. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. // convert predicate to 32-bit value 58 January 24. not. geu. Table 18. unordered versions are included: equ. If either operand is NaN. Table 17.%p. 2010 .0. then the result of these comparisons is true. and nan returns true if either operand is NaN. If both operands are numeric values (not NaN).1.0 To aid comparison operations in the presence of NaN values. There is no direct conversion between predicates and integer values. ltu. two operators num (numeric) and nan (isNaN) are provided. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. then these comparisons have the same result as their ordered counterparts. neu. xor.PTX ISA Version 2.3. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. gtu. However. num returns true if both operands are numeric values (not NaN). and mov. and no direct way to load or store predicate register values. leu. for example: selp. setp can be used to generate a predicate from an integer.

u16 d. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. 2010 59 . cvt. Instruction Set 8. Table 19. For example: . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.bX . different sizes).sX ok ok ok inv . Example: . the add instruction requires type and size information to properly perform the addition operation (signed. a. a. i. • The following table summarizes these type checking rules. float. .u16 d. Floating-point types agree only if they have the same size. unsigned.. a.uX ok ok ok inv .fX ok inv inv ok Instruction Type .4.e. b. and these are placed in the same order as the operands. For example. Signed and unsigned integer types agree provided they have the same size. most notably the data conversion instruction cvt.reg .f32. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.reg .Chapter 8. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. they must match exactly. add.u16 d.f32 d.reg . and this information must be specified as a suffix to the opcode. For example.u16 a. It requires separate type-size modifiers for the result and source. and integer operands are silently cast to the instruction type if needed.bX .uX . Type Checking Rules Operand Type .fX ok ok ok ok January 24. b.sX .

2010 . or converted to other types and sizes. no conversion needed. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. stored. so that narrow values may be loaded. floating-point instruction types still require that the operand type-size matches exactly. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. When used with a narrower bit-size type. Notes 3.0 8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. The following table summarizes the relaxed type-checking rules for source operands. 1. For example. for example. the data will be truncated. Bit-size source registers may be used with any appropriately-sized instruction type. 4. the size must match exactly. so those rows are invalid for cvt. Source register size must be of equal or greater size than the instruction-type size. parse error. Table 20. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. unless the operand is of bit-size type. 2. Operand Size Exceeding Instruction-Type Size For convenience. st. the cvt instruction does not support . the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. inv = invalid.4.1. ld. When used with a floating-point instruction type.bX instruction types. “-“ = allowed. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. Floating-point source registers can only be used with bit-size or floating-point instruction types. 60 January 24. Note that some combinations may still be invalid for a particular instruction.PTX ISA Version 2. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. and converted using regular-width registers. The data is truncated to the instruction-type size and interpreted according to the instruction type. stored. When a source operand has a size that exceeds the instruction-type size.

Chapter 8. Instruction Set When a destination operand has a size that exceeds the instruction-type size. “-“ = Allowed but no conversion needed. and is zero-extended to the destination register width otherwise. 4. When used with a narrower bit-size instruction type. Notes 3. the data will be zero-extended. 1. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type.or sign-extended to the size of the destination register. Floating-point destination registers can only be used with bit-size or floating-point instruction types. January 24. parse error. 2010 61 . Table 21. the destination data is zero. When used with a floatingpoint instruction type. Destination register size must be of equal or greater size than the instruction-type size. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. The following table summarizes the relaxed type-checking rules for destination operands. otherwise. the data is sign-extended. The data is signextended to the destination register width for signed integer instruction types. The data is sign-extended to the destination register width for signed integer instruction types. 2. zext = zero-extend. the data is zeroextended. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. If the corresponding instruction type is signed integer. Bit-size destination registers may be used with any appropriately-sized instruction type. inv = Invalid. the size must match exactly.

6. by a right-shift instruction. 8. this is not desirable. and for many applications the difference in execution is preferable to limiting performance. Both situations occur often in programs. the threads are called divergent.0 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. If all of the threads act in unison and follow a single control flow path. the threads are called uniform. and 16-bit computations are “promoted” to 32-bit computations.uni suffix. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. the semantics of 16-bit instructions in PTX is machine-specific. for many performance-critical applications. until C is not expressive enough. until they come to a conditional control construct such as a conditional branch. When executing on a 32-bit data path. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. However. If threads execute down different control flow paths. 16-bit registers in PTX are mapped to 32-bit physical registers. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. 8. using the . A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. Therefore.PTX ISA Version 2. a compiler or code author targeting PTX can ignore the issue of divergent threads. 2010 . All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent.1.5. for example. conditional function call. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. For divergent control flow. the optimizing code generator automatically determines points of re-convergence. so it is important to have divergent threads re-converge as soon as possible. A compiler or programmer may chose to enforce portable.6. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 62 January 24. Divergence of Threads in Control Constructs Threads in a CTA execute together. or conditional return. These extra precision bits can become visible at the application level. at least in appearance. The semantics are described using C. At the PTX language level.

The Integer arithmetic instructions are: add sub add. addc sub.cc.1.Chapter 8. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8. the optional guard predicate is omitted from the syntax.7. Instructions All PTX instructions may be predicated. 2010 63 .7. 8. In the following descriptions.cc. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.

s32 c. . d = a + b. . .s32 d. 2010 .sat applies only to .s32 c.0. . b. .type = { .c.type sub{. PTX ISA Notes Target ISA Notes Examples Table 23. Saturation modifier: .0 Table 22. Description Semantics Notes Performs addition and writes the resulting value into a destination register.s32 type..z. a. // . . b. .. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.sat}.0. PTX ISA Notes Target ISA Notes Examples 64 January 24.s32 type.u64.u16.sat.s32 d. sub.sat}. add. Supported on all target architectures.u32 x.y. Applies only to . d.a.u64. . add Syntax Integer Arithmetic Instructions: add Add two values. a. d = a – b.s32.type = { . b.s32 .type add{.u16. Introduced in PTX ISA version 1. Supported on all target architectures.MAXINT (no overflow) for the size of the operation. d.sat limits result to MININT.s16. . b. Introduced in PTX ISA version 1. sub.MAXINT (no overflow) for the size of the operation. a.PTX ISA Version 2.u32.1.s16. // .s64 }.s32 .s64 }. Saturation modifier: . .sat limits result to MININT. add. a.u32. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. @p add.sat applies only to .b. Applies only to .s32.

b32 addc.y2. Behavior is the same for unsigned and signed integers.CF) holding carry-in/carry-out or borrowin/borrow-out.z4.cc.z3.y1.CF No integer rounding modifiers. Behavior is the same for unsigned and signed integers.2.b32 addc.2.cc.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.z2.b32 addc. sub. . addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. b. @p @p @p @p add.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.cc specified. .cc. 2010 65 .z3. addc{. Introduced in PTX ISA version 1. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. No saturation. a.y2.b32 addc. if .z4.cc. x4.y4.cc.type d.b32 x1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.z2.cc.cc.cc Add two values with carry-out. These instructions support extended-precision integer addition and subtraction.Chapter 8. x2. clearing.cc.type d. x4. or testing the condition code. Supported on all target architectures. Table 24.z1.type = { . d = a + b + CC. Instruction Set Instructions add. No other instructions access the condition code.y3. Supported on all target architectures.s32 }. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. @p @p @p @p add. . x2.y4. Introduced in PTX ISA version 1.u32.cc}.cc Syntax Integer Arithmetic Instructions: add.b32 addc.s32 }.y3.cc. . add.CF. x3. and there is no support for setting.b32 x1. d = a + b. carry-out written to CC.b32 addc.CF No integer rounding modifiers. No saturation. b.y1. a. carry-out written to CC. add. x3. addc.u32.type = {.z1.

x4. . 2010 . Supported on all target architectures. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.z4.3. sub. x2. d = a – b. x3.z4. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y1.b32 x1. @p @p @p @p sub.type d.y4.s32 }. b. x2.cc.cc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.b32 subc. if .z3. borrow-out written to CC.b32 subc.cc.z3.type = { .b32 subc. Supported on all target architectures.cc.b32 subc.y3.type = {. . a.cc. Introduced in PTX ISA version 1.b32 subc.y4. . // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc Syntax Integer Arithmetic Instructions: sub. No saturation.b32 subc.y2. subc{. b.y3.u32. withborrow-in and optional borrow-out. @p @p @p @p sub. Behavior is the same for unsigned and signed integers.CF). Behavior is the same for unsigned and signed integers.(b + CC. a.y1. d = a .cc.z1.CF No integer rounding modifiers.z2. No saturation. borrow-out written to CC.cc}.type d. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.cc. sub.z2.CF No integer rounding modifiers.PTX ISA Version 2.u32.cc.y2.s32 }.cc.b32 x1. with borrow-out.3.cc specified.cc Subract one value from another.0 Table 26. .z1. Introduced in PTX ISA version 1. x3. x4.

d = t<n-1.s16 fa. Instruction Set Table 28.type = { .wide is specified..hi or . creates 64 bit result January 24. . // for .u64.s16 fa.type d.lo.s64 }. save only the low 16 bits // 32*32 bits.fxs.s32 z.hi.lo. d = t<2n-1. mul{.s32.x.n>.0.u16. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.lo variant Notes The type of the operation represents the types of the a and b operands.wide // for .s16. mul. . and either the upper or lower half of the result is written to the destination register. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul. then d is the same size as a and b. Supported on all target architectures.Chapter 8.fxs.lo is specified. mul. a.and 32-bit integer types. then d is twice as wide as a and b to receive the full result of the multiplication.fys.fys. . // 16*16 bits yields 32 bits // 16*16 bits. d = t. ..wide}.wide suffix is supported only for 16.0>..y.wide. 2010 67 . Description Semantics Compute the product of two values.wide. If . n = bitwidth of type.. If . The . .hi variant // for .u32. t = a * b. . b.

wide suffix is supported only for 16. t + c. and either the upper or lower half of the result is written to the destination register. t n d d d = = = = = a * b. // for . .wide is specified. Supported on all target architectures.wide // for .hi or .lo variant Notes The type of the operation represents the types of the a and b operands. mad.q.s16. If . Description Semantics Multiplies two values and adds a third. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. t<n-1.0> + c.MAXINT (no overflow) for the size of the operation. a. b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi. . The .and 32-bit integer types. If .s32. @p mad.hi. . .r. .0 Table 29.. mad{.p.lo.. Saturation modifier: . c.u64.s32 d. c.0. then d and c are twice as wide as a and b to receive the result of the multiplication.sat.type mad.lo. 68 January 24. t<2n-1. . then d and c are the same size as a and b. and then writes the resulting value into a destination register.lo. a.s32 d.. Applies only to .b.c.. bitwidth of type.wide}.PTX ISA Version 2.hi mode.. b.n> + c.sat limits result to MININT. 2010 . d.lo is specified.s32 type in .u16.a.type = { .u32.s64 }.hi variant // for .s32 r.

// for . d = t<31. and return either the high or low 32-bits of the 48-bit result.a.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.u32. t = a * b.hi variant // for . mul24{..type d. Supported on all target architectures.0. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24. i. January 24. mul24. mul24. 48bits.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. Instruction Set Table 30. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 69 .e.16>.lo. mul24.type = { .hi. // low 32-bits of 24x24-bit signed multiply.0>.Chapter 8. d = t<47.lo}. b.. All operands are of the same type and size. .hi may be less efficient on machines without hardware support for 24-bit multiply.b..s32 }. .lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi may be less efficient on machines without hardware support for 24-bit multiply. d = t<31. mad24{. c.hi.s32 d. // low 32-bits of 24x24-bit signed multiply. . mad24. 70 January 24. t = a * b.MAXINT (no overflow).0 Table 31. b.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. . Description Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d.a.sat. // for .b. Applies only to .PTX ISA Version 2.0. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. and add a third.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. mad24. Supported on all target architectures. i.e.s32 }. 2010 . mad24.lo}..hi mode.0> + c. a. c.c..sat limits result of 32-bit signed addition to MININT.. Saturation modifier: .type mad24.hi.type = { . All operands are of the same type and size. 48bits.lo.s32 type in ..16> + c.hi variant // for . d. 32-bit value to either the high or low 32-bits of the 48-bit result. Return either the high or low 32-bits of the 48-bit result. d = t<47. b. a.u32. mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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} PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. } else { max = 64. d = 0. . X. a = a << 1.0. d = 0.type == .PTX ISA Version 2.type = { . mask = 0x80000000.b32 clz. X. // cnt is . clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. // cnt is . inclusively. a.b32) { max = 32. } while (d < max && (a&mask == 0) ) { d++. a. inclusively.type = { .b64 d.b64 }. clz requires sm_20 or later. clz.b64 d. For .0 Table 39. .u32 PTX ISA Notes Target ISA Notes Examples Table 40. popc.b32 type. 2010 .b32 popc. the number of leading zeros is between 0 and 64. popc. } Introduced in PTX ISA version 2. a = a >> 1. .type d.u32 Semantics 74 January 24. popc requires sm_20 or later. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. popc Syntax Integer Arithmetic Instructions: popc Population count. cnt.type d. cnt.0. a.b64 }. the number of leading zeros is between 0 and 32.b64 type.b32. mask = 0x8000000000000000. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. while (a != 0) { if (a&0x1) d++. For . if (. a. clz. .b32.

} } if (. a.shiftamt. for (i=msb.type==.shiftamt && d != -1) { d = msb . a.s64 }. break.u32 January 24. bfind returns 0xFFFFFFFF if no non-sign bit is found. bfind. Instruction Set Table 41. a.u64.s32.s64 cnt. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. .type==.u32 || . Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind returns the bit position of the most significant “1”. . bfind requires sm_20 or later.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.u32.type d. and operand d has type . Semantics msb = (. i>=0.0.type = { .u32 d. . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.d.u32. bfind. For unsigned integers. d = -1.shiftamt.type bfind. bfind. If .s32) ? 31 : 63. For signed integers. X. i--) { if (a & (1<<i)) { d = i. // cnt is .shiftamt is specified. 2010 75 . Operand a has the instruction type. d. .

type d. brev requires sm_20 or later. . for (i=0. a. . 76 January 24.b32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.PTX ISA Version 2. a. brev. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.0. brev.b32 d. 2010 .0 Table 42. Description Semantics Perform bitwise reversal of input.b32) ? 31 : 63.type==.b64 }. msb = (. i<=msb. i++) { d[i] = a[msb-i].type = { .

. bfe requires sm_20 or later.0.type d. . .u32 || .a. bfe. The destination d is padded with the sign bit of the extracted field. len = c. c.u64: . bfe. else sbit = a[min(pos+len-1. the destination d is filled with the replicated sign bit of the extracted field. . d = 0. a.u32.u64 || len==0) sbit = 0.s32) ? 31 : 63. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. b.type = { .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. . 2010 77 .u32 || . Semantics msb = (.type==. otherwise If the bit field length is zero. .type==. Description Extract bit field from a and place the zero or sign-extended result in d.u32. pos = b.u32.u64.s32. Source b gives the bit field starting bit position. and source c gives the bit field length in bits.b32 d. Operands a and d have the same type as the instruction type.Chapter 8. if (. Instruction Set Table 43. If the start position is beyond the msb of the input. and operands b and c are type . The sign bit of the extracted field is defined as: .type==.type==. i<=msb. for (i=0. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.msb)].s32. the result is zero. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.start.s64 }. January 24.len.

and f have the same type as the instruction type. for (i=0. b.b32 d. 78 January 24. 2010 .0 Table 44. bfi. f = b. bfi. If the start position is beyond the msb of the input. b. i<len && pos+i<=msb. . and operands c and d are type .len. c. len = d. If the bit field length is zero. Source c gives the starting bit position for the insertion. and place the result in f. Semantics msb = (.b32) ? 31 : 63.b32. Operands a.start. d.0. i++) { f[pos+i] = a[i].b64 }.type = { . and source d gives the bit field length in bits. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.a. the result is b. Description Align and insert a bit field from a into b.type==. a. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.u32. pos = c.type f. the result is b. bfi requires sm_20 or later.PTX ISA Version 2.b. .

b1.b2 source select c[11:8] d.ecr. . a 4-bit selection value is defined. Thus. prmt.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. . b. and reassemble them into a 32-bit destination register. In the generic form (no mode specified). The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. . c.b32{.f4e.mode} d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.rc8. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. . {b3.mode = { . b0}}. b5. as a 16b permute code. msb=1 means replicate the sign. b2.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b1 source select c[7:4] d. the four 4-bit values fully specify an arbitrary byte permute. .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. Description Pick four arbitrary bytes from two 32-bit registers. For each byte in the target register.ecl.b3 source select c[15:12] d. 2010 79 .b4e. msb=0 means copy the literal value. Note that the sign extension is only performed as part of generic form. a} = {{b7.rc16 }. Instruction Set Table 45. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). default mode index d. The bytes in the two source registers are numbered from 0 to 7: {b. b4}. b6.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. the permute control consists of four 4-bit selection values. The msb defines if the byte value should be copied. .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. a.Chapter 8.

} tmp[07:00] = ReadByte( mode. ctl[2]. tmp64 ).b32. r2. r2.0.b32 prmt. r4. prmt. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[3]. tmp[23:16] = ReadByte( mode. ctl[3] = (c >> 12) & 0xf. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[2] = (c >> 8) & 0xf. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[1]. tmp64 ). r1. ctl[1] = (c >> 4) & 0xf.f4e r1.0 Semantics tmp64 = (b<<32) | a. tmp64 ). 80 January 24.PTX ISA Version 2. 2010 . tmp64 ). r4. ctl[0]. r3. r3. prmt requires sm_20 or later. tmp[15:08] = ReadByte( mode. tmp[31:24] = ReadByte( mode.

f64 register operands and constant immediate values.7.2. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on .Chapter 8.f32 and . 2010 81 .

If no rounding modifier is specified.rnd. NaN payloads are supported for double-precision instructions.min.f32 {abs.rnd.f32 {mad. {mad.f32 {div.mul}.sqrt}.rp .rm .sub. default is . No rounding modifier. mul.rcp.sqrt}.rcp.rz .f64 rsqrt. Table 46.neg.rn and instructions may be folded into a multiply-add. sub.sqrt}. Note that future implementations may support NaN payloads for single-precision instructions. . so PTX programs should not rely on the specific single-precision NaNs being generated.fma}. The optional .ftz .approx.f32 are the same. {add.target sm_20 mad. 82 January 24.f32 .cos. but single-precision instructions return an unspecified NaN.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.mul}.rnd.lg2.rnd.f32 rsqrt.fma}.rn and instructions may be folded into a multiply-add.target sm_1x No rounding modifier.approx.sub.rnd.f64 and fma.f64 {abs.32 and fma. .sat Notes If no rounding modifier is specified.ex2}. 1.f64 div.rcp.rn .f64 mad.PTX ISA Version 2.full. Single-precision add.f64 are the same.0.0 The following table summarizes floating-point instructions in PTX.max}. 2010 .approx.approx.0].f32 {add.f32 {div.max}. default is . Double-precision instructions support subnormal inputs and results.min. Instruction Summary of Floating-Point Instructions .f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {div. and mad support saturation of results to the range [0.f64 {sin.neg.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.rnd. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. with NaNs being flushed to positive zero.target sm_20 .

Chapter 8.subnormal }. positive and negative zero are considered normal numbers. Table 48. testp.f32. B. . 2010 83 . // result is .number.f64 x. z. y.finite testp. Instruction Set Table 47. .0. . f0.f32 testp.type d.normal. Introduced in PTX ISA version 2.f64 }.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. testp.f64 isnan.normal testp.0. X. copysign. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.notanumber.op. .type . not infinity).type = { . testp requires sm_20 or later. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. . .notanumber.type = { .infinite. testp. C. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. p.number testp. January 24.op p.f64 }. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.infinite. A. .infinite testp. true if the input is a subnormal number (not NaN.f32 copysign. not infinity) As a special case.f32. b. a. and return the result as d. copysign requires sm_20 or later. a. testp Syntax Floating-Point Instructions: testp Test floating-point property.pred = { . . . copysign.finite.notanumber testp.

rn.rm.f32 f1. . NaN results are flushed to +0.0f.f64 requires sm_13 or later. 84 January 24.f64 d. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .ftz.f32 add{.f32.rz. .0]. requires sm_20 Examples @p add. In particular.f32 flushes subnormal inputs and results to sign-preserving zero.rnd}. add.rnd}{.rz.f32 clamps the result to [0.rnd = { . add{.0 Table 49. a. Description Semantics Notes Performs addition and writes the resulting value into a destination register.0.ftz}{.sat}. 2010 . add. Rounding modifiers (default is . Saturation modifier: . d. 1.rn. requires sm_13 for add.rn): .sat. subnormal numbers are supported. Rounding modifiers have the following target requirements: . mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 supports subnormal numbers.PTX ISA Version 2. b. add.f64.f32 flushes subnormal inputs and results to sign-preserving zero.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz available for all targets .rp }. a. add Syntax Floating-Point Instructions: add Add two values. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f3. sm_1x: add. . . d = a + b. add.rp for add. add.f2. .rm.rm mantissa LSB rounds towards negative infinity .0. b.ftz.f32 supported on all target architectures. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rz mantissa LSB rounds towards zero .rn mantissa LSB rounds to nearest even .

ftz. .rn mantissa LSB rounds to nearest even .f32 c.b. d = a .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.rz.ftz.f32 f1.rm mantissa LSB rounds towards negative infinity .f32 supported on all target architectures.rm. January 24.f32 sub{.rn): . . d. In particular. b.rp for sub. 1.f32. Instruction Set Table 50.rm. NaN results are flushed to +0. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. sub. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. b. sub Syntax Floating-Point Instructions: sub Subtract one value from another. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers have the following target requirements: . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sm_1x: sub.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.f64 d. subnormal numbers are supported. sub. a.0.b.f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_20 Examples sub. a.ftz}{.rnd}{. sub{. 2010 85 . sub.rn.f3. requires sm_13 for sub.rnd}. sub. .a.rn. . Rounding modifiers (default is . .rnd = { .0.Chapter 8.f32 clamps the result to [0.rz available for all targets .0].0f.sat. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. sub.rp }.f2. .f64.rz mantissa LSB rounds towards zero .sat}. Saturation modifier: sub.f64 supports subnormal numbers.

A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rnd}. mul.f64. d.f32 supported on all target architectures. sm_1x: mul. 2010 .ftz}{.0f.f32 mul{.f64 requires sm_13 or later. Rounding modifiers (default is .rp }. requires sm_13 for mul.radius.f32 circumf. . . a. d = a * b. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. In particular.ftz. .rn): .rz available for all targets . mul. 1. Saturation modifier: mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rm.0]. requires sm_20 Examples mul.rnd}{. a.f32 flushes subnormal inputs and results to sign-preserving zero. all operands must be the same size.rn.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers.rp for mul.f32 clamps the result to [0. . For floating-point multiplication. b. NaN results are flushed to +0.sat}. Rounding modifiers have the following target requirements: .0.rnd = { . Description Semantics Notes Compute the product of two values. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. subnormal numbers are supported. mul Syntax Floating-Point Instructions: mul Multiply two values.ftz. b.rz.pi // a single-precision multiply 86 January 24.rn mantissa LSB rounds to nearest even .f64 d.f32.0.rz mantissa LSB rounds towards zero . mul{. . mul.sat.rm.PTX ISA Version 2.rm mantissa LSB rounds towards negative infinity .rn. mul.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .0 Table 51.

rnd. d. a.f64 supports subnormal numbers.rm. . @p fma.f32 is unimplemented in sm_1x. b. c. d = a*b + c.rnd{.4. . fma. d.f32 clamps the result to [0.rnd.Chapter 8.0f. Saturation: fma.c. fma Syntax Floating-Point Instructions: fma Fused multiply-add.rnd.f64 d.f32 introduced in PTX ISA version 2. fma.z. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f64 requires sm_13 or later.ftz. b. sm_1x: fma. again in infinite precision.ftz}{.ftz.rnd = { . again in infinite precision. fma. The resulting value is then rounded to single precision using the rounding mode specified by . The resulting value is then rounded to double precision using the rounding mode specified by .f64 w. fma.rz mantissa LSB rounds towards zero . fma.f64 is the same as mad.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero. 1. fma.rn.f32 requires sm_20 or later. .rz.f32 computes the product of a and b to infinite precision and then adds c to this product.f64.0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn mantissa LSB rounds to nearest even .b.sat}.0.sat. c. fma. . a.a. NaN results are flushed to +0. fma.f64 introduced in PTX ISA version 1. 2010 87 .rm mantissa LSB rounds towards negative infinity .x. PTX ISA Notes Target ISA Notes Examples January 24. subnormal numbers are supported.y.f32 fma. Rounding modifiers (no default): . Instruction Set Table 52.rp }.0]. fma. fma.rn.rn.f32 fma.

and then writes the resulting value into a destination register. The exception for mad. sm_1x: mad.f64} is the same as fma.sat.{f32.target sm_20 d.rnd.sat}.f64 d. where the mantissa can be rounded and the exponent will be clamped. c. . Rounding modifiers (no default): . mad.rn.f32 clamps the result to [0.f64.e.f32). mad.ftz.f32 computes the product of a and b to infinite precision and then adds c to this product.target sm_1x: mad. but the exponent is preserved. mad. mad.0 Table 53.f64 supports subnormal numbers.rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero. again in infinite precision.rz mantissa LSB rounds towards zero .f64 computes the product of a and b to infinite precision and then adds c to this product. mad.rm mantissa LSB rounds towards negative infinity . Unlike mad.f64 computes the product of a and b to infinite precision and then adds c to this product. // .rnd{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. mad.rp }. The resulting value is then rounded to single precision using the rounding mode specified by . Note that this is different from computing the product with mul. fma. . NaN results are flushed to +0. b.f32 flushes subnormal inputs and results to sign-preserving zero.target sm_20: mad.rm.f32 is identical to the result computed using separate mul and add instructions. again in infinite precision.{f32. c. 88 January 24. a.f64 is the same as fma.f32.PTX ISA Version 2.target sm_1x d. mad. 2010 .0]. Description Semantics Notes Multiplies two values and adds a third. In this case.f32 is implemented as a fused multiply-add (i. . the treatment of subnormal inputs and output follows IEEE 754 standard.. For .rnd. c. For .f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. b.rnd. d = a*b + c. mad.ftz.f32 mad. 1.0.sat}.f32 mad. The resulting value is then rounded to double precision using the rounding mode specified by . // .f32 computes the product of a and b at double precision.target sm_13 and later . mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. mad{. a.0. and then the mantissa is truncated to 23 bits. // . a.0f. again in infinite precision. b. mad. Saturation modifier: mad.f32 is when c = +/-0.rnd.f64}.rnd = { . When JIT-compiled for SM 2.rz. subnormal numbers are supported.rn.ftz}{.0 devices.ftz}{. The resulting value is then rounded to double precision using the rounding mode specified by .

rn. In PTX ISA versions 1. Rounding modifiers have the following target requirements: .rp for mad.a. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.0.b..f32 supported on all target architectures.f64 instructions having no rounding modifier will map to mad.f32 d.. Legacy mad.4 and later. requires sm_20 Examples @p mad.f64...f64..c. January 24.f32.0 and later. 2010 89 .rp for mad.Chapter 8.f64.rz. mad. requires sm_13 .rm. Target ISA Notes mad.f32 for sm_20 targets.rn.f64 requires sm_13 or later.rn.rm. a rounding modifier is required for mad. a rounding modifier is required for mad. In PTX ISA versions 2.rz..

one of . b. div. full-range approximation that scales operands to achieve better accuracy. PTX ISA Notes div.rnd.f32 requires sm_20 or later. and rounding introduced in PTX ISA version 1. div. Subnormal inputs and results are flushed to sign-preserving zero.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 defaults to div. The maximum ulp error is 2 across the full range of inputs. stores result in d. d = a / b. Examples 90 January 24. computed as d = a * (1/b).rm mantissa LSB rounds towards negative infinity .ftz}.full. b.4. .approx. div.f32 supported on all target architectures.f64 defaults to div. a.f32 div. Fast.rn. or . div.full.approx. b. a.0.f64 introduced in PTX ISA version 1.full.rm. and div. approximate single-precision divides: div.0 through 1. . For PTX ISA version 1.approx.ftz.rn mantissa LSB rounds to nearest even .f32 div.ftz.ftz}.{rz. zd. Description Semantics Notes Divides a by b.full.ftz}. div.approx{. div Syntax Floating-Point Instructions: div Divide one value by another. For PTX ISA versions 1. div. .f64 requires sm_20 or later. d.f32 div. // // // // fast.f32 and div.f32 implements a fast approximation to divide. a.f32 div.3. div. sm_1x: div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . 2010 . 2126].f32 and div. approximate division by zero creates a value of infinity (with same sign as a).4 and later.rn. Target ISA Notes div.full{.PTX ISA Version 2. b.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 54.f64 supports subnormal numbers. For b in [2-126. . x.ftz. . xd.rnd is required. y.ftz. d.circum. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64. div. a.rnd{.approx.f32 implements a relatively fast.full. subnormal numbers are supported. .rnd. the maximum ulp error is 2.f64 d.rn. d.rz mantissa LSB rounds towards zero .f32.3.rp}.rm.ftz.rz. yd. z.rnd = { .approx. Fast.14159.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers .rn. but is not fully IEEE 754 compliant and does not support rounding modifiers.rp }. div.f64 diam.f64 requires sm_13 or later.f32 div.approx.

NaN inputs yield an unspecified NaN. sm_1x: neg. d. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f64 d.ftz. a. d = -a. d. a.ftz}. abs. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. sm_1x: abs. neg.ftz. Instruction Set Table 55. abs{.f32 abs. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 requires sm_13 or later. Subnormal numbers: sm_20: By default. subnormal numbers are supported. a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f32 neg.Chapter 8. a. abs. neg.f32 supported on all target architectures. 2010 91 . Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.ftz. Negate the sign of a and store the result in d.f0. January 24.f64 supports subnormal numbers. abs.f32 supported on all target architectures. neg. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg. abs.f64 d. Subnormal numbers: sm_20: By default.f32 x.0.f64 requires sm_13 or later. Take the absolute value of a and store the result in d.ftz}.f0.f32 flushes subnormal inputs and results to sign-preserving zero.f32 x. d = |a|. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. neg{. NaN inputs yield an unspecified NaN.f32 flushes subnormal inputs and results to sign-preserving zero.0.f64 supports subnormal numbers. Table 56.

f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. a. b. max.b. Store the minimum of a and b in d.ftz.0 Table 57.0.f64 requires sm_13 or later. b. a.f32 min.0.f32 max. d d d d = = = = NaN. d. a. 2010 . a. a.f32 min. subnormal numbers are supported.f64 f0. (a > b) ? a : b. max.f32 supported on all target architectures. d d d d = = = = NaN. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f32 flushes subnormal inputs and results to sign-preserving zero. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 d.x.f32 max.f2. sm_1x: min.b.z.c.f64 z.f64 d. max.ftz. sm_1x: max.f32 supported on all target architectures. a. a.PTX ISA Version 2.f64 supports subnormal numbers. b. min{. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. (a < b) ? a : b. max. Store the maximum of a and b in d. subnormal numbers are supported.ftz. min.ftz. d.f64 supports subnormal numbers. max{. min. max. b. Table 58. a. min.c.f32 flushes subnormal inputs and results to sign-preserving zero.f1. b. 92 January 24.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. @p min. min. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.

f32 defaults to rcp. rcp. // fast.f64 requires sm_13 or later.approx. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . rcp. subnormal numbers are supported.r.approx or .rnd.f32 rcp. rcp.f32.ftz}. General rounding modifiers were added in PTX ISA version 2.0.4. xi.f32 and rcp. a.ftz.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . a.rm.rz mantissa LSB rounds towards zero .ftz.0.approx.rp}.f32 requires sm_20 or later.f64 introduced in PTX ISA version 1. rcp.0.ftz were introduced in PTX ISA version 1. For PTX ISA version 1. .f32 implements a fast approximation to reciprocal.0 +0. and rcp.approx.4 and later.f64 ri.0-2.rnd.f64.rz. Input -Inf -subnormal -0.rm mantissa LSB rounds towards negative infinity .{rz.f64 requires sm_20 or later.f64 d.f32 rcp.0 through 1.3. store result in d.approx{. sm_1x: rcp.f32 flushes subnormal inputs and results to sign-preserving zero.rn.f32 rcp. Examples January 24.0 over the range 1.f32 supported on all target architectures. Target ISA Notes rcp.approx and .rp }.rnd is required. d.ftz}.rn.rm.rn. d = 1 / a.x. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.0 -Inf -Inf +Inf +Inf +0.x.rn mantissa LSB rounds to nearest even . 2010 93 .rn.approx. Description Semantics Notes Compute 1/a.0 +subnormal +Inf NaN Result -0. rcp.ftz. . rcp.ftz. xi.f64 and explicit modifiers . PTX ISA Notes rcp.Chapter 8.f32 rcp.f32 flushes subnormal inputs and results to sign-preserving zero. d.rn.rn. one of .f64 defaults to rcp. rcp. rcp. rcp. The maximum absolute error is 2-23.rnd{. a. For PTX ISA versions 1. rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rnd = { . Instruction Set Table 59.

For PTX ISA versions 1.x.0.f32 is TBD.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 60.{rz.0 through 1.ftz}. sqrt. approximate square root d.f32. General rounding modifiers were added in PTX ISA version 2.f32 implements a fast approximation to square root.approx.rm. // IEEE 754 compliant rounding .approx.ftz. Examples 94 January 24.rm mantissa LSB rounds towards negative infinity . sqrt.f64 requires sm_20 or later.f32 sqrt. sqrt.x. and sqrt.rn. a.f32 sqrt. 2010 .rm. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. For PTX ISA version 1.rnd is required.f32 requires sm_20 or later.ftz. . sm_1x: sqrt. // IEEE 754 compliant rounding d.f32 sqrt.ftz.rnd{.rn.0 -0.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.4 and later.rn. a. Input -Inf -normal -subnormal -0. d = sqrt(a).rn. sqrt.0 +subnormal +Inf NaN Result NaN NaN -0.f32 sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.approx.f64 d. sqrt.f64 and explicit modifiers . . The maximum absolute error for sqrt. sqrt. a.f64 introduced in PTX ISA version 1.approx{. store in d.PTX ISA Version 2.approx. sqrt.rn.approx or .f64.rn. Description Semantics Notes Compute sqrt(a).f32 supported on all target architectures. PTX ISA Notes sqrt.f64 r.approx.f32 and sqrt.ftz}. sqrt. // fast.approx and .ftz were introduced in PTX ISA version 1.rnd = { .0 +0. r. .0 +0.rn mantissa LSB rounds to nearest even . one of . r. subnormal numbers are supported.rnd.x. sqrt.rz. Target ISA Notes sqrt.rz mantissa LSB rounds towards zero .4.0.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64 requires sm_13 or later.3.f64 supports subnormal numbers.rp }.ftz.rp}. sqrt.f32 defaults to sqrt.rnd.0 +0.f64 defaults to sqrt.

d.f32 defaults to rsqrt. The maximum absolute error for rsqrt. rsqrt. 2010 95 .4.4 over the range 1. Compute 1/sqrt(a). Subnormal numbers: sm_20: By default. subnormal numbers are supported. rsqrt.0 NaN The maximum absolute error for rsqrt.f64 d.0. x.approx.Chapter 8. and rsqrt. rsqrt.f32 rsqrt.f64 supports subnormal numbers.0 through 1. the . rsqrt. rsqrt. Explicit modifiers .0 +0.approx implements an approximation to the reciprocal square root. For PTX ISA version 1.f64. a. PTX ISA Notes rsqrt.4 and later.f64 defaults to rsqrt.ftz were introduced in PTX ISA version 1.approx. rsqrt. January 24. store the result in d.f64 were introduced in PTX ISA version 1. rsqrt.approx modifier is required.ftz.approx.approx and .f32 flushes subnormal inputs and results to sign-preserving zero.approx{.f32 supported on all target architectures.f32. X. ISR.ftz}.f64 is TBD.approx.f32 rsqrt.ftz.f32 is 2-22.f64 is emulated in software and are relatively slow.0. d = 1/sqrt(a). a.approx. sm_1x: rsqrt. Target ISA Notes Examples rsqrt.f64 requires sm_13 or later.approx. Note that rsqrt. For PTX ISA versions 1. Input -Inf -normal -subnormal -0.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.3.ftz.f64 isr. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. Instruction Set Table 61.f32 and rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.0-4.

Explicit modifiers . sin.ftz. 2010 . the .approx{.approx.ftz}.9 in quadrant 00.4 and later.f32. sm_1x: Subnormal inputs and results to sign-preserving zero. Input -Inf -subnormal -0.0.approx.0 NaN NaN The maximum absolute error is 2-20.approx.f32 flushes subnormal inputs and results to sign-preserving zero. Find the sine of the angle a (in radians). subnormal numbers are supported.f32 introduced in PTX ISA version 1.f32 sa.0 +0.4.0 +0. Target ISA Notes Examples Supported on all target architectures. 96 January 24.0 Table 62.ftz. a. sin.0 through 1.f32 implements a fast approximation to sine. Subnormal numbers: sm_20: By default.ftz introduced in PTX ISA version 1. PTX ISA Notes sin.f32 defaults to sin.ftz.approx modifier is required. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.f32 d.0 -0. sin. sin. a.0 +subnormal +Inf NaN Result NaN -0.PTX ISA Version 2. d = sin(a).0 +0.approx and . sin.3. For PTX ISA version 1. For PTX ISA versions 1.

f32 ca.f32 d. Instruction Set Table 63.ftz}. Explicit modifiers . a.f32. PTX ISA Notes cos.0 +1. the .3. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz introduced in PTX ISA version 1.4 and later.f32 defaults to cos.ftz.9 in quadrant 00.0 through 1. Find the cosine of the angle a (in radians). 2010 97 . For PTX ISA versions 1.approx.4. Input -Inf -subnormal -0. cos.0.Chapter 8.approx and . subnormal numbers are supported.approx. January 24. a.approx modifier is required.approx. Target ISA Notes Examples Supported on all target architectures. cos.0 +1.approx{. For PTX ISA version 1.0 +0.ftz. cos.f32 implements a fast approximation to cosine. d = cos(a).f32 introduced in PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. cos.0 +1. Subnormal numbers: sm_20: By default.0 NaN NaN The maximum absolute error is 2-20. cos.0 +subnormal +Inf NaN Result NaN +1.ftz.

The maximum absolute error is 2-22. lg2.approx{.6 for mantissa.3. lg2.f32.0 +0.ftz}.ftz introduced in PTX ISA version 1.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Subnormal numbers: sm_20: By default. lg2. For PTX ISA version 1.f32 Determine the log2 of a. Target ISA Notes Examples Supported on all target architectures.approx and . the . subnormal numbers are supported. Input -Inf -subnormal -0. a.0 through 1.ftz. d = log(a) / log(2). PTX ISA Notes lg2.f32 implements a fast approximation to log2(a). lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.approx.4 and later. lg2.approx.PTX ISA Version 2.approx modifier is required.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 defaults to lg2.f32 la. For PTX ISA versions 1. Explicit modifiers .0.f32 introduced in PTX ISA version 1.0 Table 64.f32 flushes subnormal inputs and results to sign-preserving zero.approx.4. lg2.ftz. 98 January 24. 2010 . a.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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the comparison operators lo.i.BoolOp{. . The destinations p and q must be .f32. neu.0 Table 67.dtype. p = BoolOp(t. p[|q].u16.a.0. If either operand is NaN.dtype.pred variables. ltu. setp. higher. and (optionally) combine this result with a predicate value by applying a Boolean operator. loweror-same. The untyped.CmpOp{.ftz}.type setp. . .f64 supports subnormal numbers.s16. q = BoolOp(!t. and hs for lower.type . subnormal numbers are supported. @q setp.f32 comparisons. ge.f64 source type requires sm_13 or later. leu. lt. ls.PTX ISA Version 2.u32 p|q. p. a. For unsigned values. c). If either operand is NaN. respectively. lo. Integer Notes Floating Point Notes The ordered comparisons are eq. sm_1x: setp. le.u64.dtype. bit-size comparisons are eq and ne. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.s32. 2010 .n.b32. ltu. To aid comparison operations in the presence of NaN values. geu. Semantics t = (a CmpOp b) ? 1 : 0. ge. gt. or. setp with . ne. le. . gt. le. b.b64. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. . This result is written to the first destination operand. num returns true if both operands are numeric values (not NaN). Applies to all numeric types. A related value computed using the complement of the compare result is written to the second destination operand. hi. le. then these comparisons have the same result as their ordered counterparts. then the result of these comparisons is true. lt. gt. hs equ.lt. ls. neu. .ftz applies only to . geu. gt. leu. hi. c).ftz}. ge. . a. The signed and unsigned comparison operators are eq. setp. p[|q]. lt.and. the result is false. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The comparison operator is a suffix on the instruction.eq.f64 }.b16. . gtu. setp. and nan returns true if either operand is NaN. {!}c. . ne. ge.f32 flushes subnormal inputs to sign-preserving zero.f32 flushes subnormal inputs to sign-preserving zero. ne. b. gtu. nan The Boolean operator BoolOp(A. .r.type = { .ftz. xor. and can be one of: eq.CmpOp.B) is one of: and. num. Subnormal numbers: sm_20: By default. unordered versions are included: equ.s64. and higher-or-same may be used instead of lt. 102 January 24.s32 setp.u32. If both operands are numeric values (not NaN).b. Modifier .

. Operand c is a predicate.ftz}.xp.f32 r0.s32. . val.ftz applies only to . Introduced in PTX ISA version 1. Operands d.b32.b16.b64. . a is stored in d. Subnormal numbers: sm_20: By default. and b must be of the same type.dtype. c.u32.s32 slct{. The selected input is copied to the output without modification.x. b. . c.f32 A. slct Syntax Comparison and Selection Instructions: slct Select one source operand.f64 requires sm_13 or later. d = (c >= 0) ? a : b. selp. @q selp. and operand a is selected.f32. B.type = { . If operand c is NaN. . .f64 }.u64.b16.s16.f32 comparisons. f0.s64. a.s32.b32. .f32 flushes subnormal values of operand c to sign-preserving zero.Chapter 8. fval. Semantics Floating Point Notes January 24. .u16. selp. c.f64 }.dtype. a.f32 d.dtype. b. slct. operand c must match the second instruction type. .p.u32. otherwise b is stored in d. . based on the sign of the third operand. C. a. For . based on the value of the predicate source operand. slct. sm_1x: slct. . . b otherwise.ftz. . slct. . a.r. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.b64. .s32 selp. Description Conditional selection. negative zero equals zero.t.g.0. Modifier . and b are treated as a bitsize type of the same width as the first instruction type. y.s16. . Table 69. slct. .type d.ftz. . the comparison is unordered and operand b is selected.s64. selp Syntax Comparison and Selection Instructions: selp Select between source operands.u64. . subnormal numbers are supported.dtype = { . a.u16. . If c is True. a is stored in d.f32 comparisons.f64 requires sm_13 or later. Instruction Set Table 68. . d = (c == 1) ? a : b. 2010 103 . z.f32 flushes subnormal values of operand c to sign-preserving zero.f32. If c ≥ 0.0.u32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. slct. d. and operand a is selected.s32 x. .dtype. b. Operands d.u64.

or. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.0 8. Instructions and.7. performing bit-wise operations on operands of any type. and not also operate on predicates. 2010 . provided the operands are of the same size. xor.PTX ISA Version 2. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. This permits bit-wise operations on floating point values without having to define a union to access the bits.4.

Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b64 }. .b64 }. .pred p. a. Allowed types include predicate registers.b32 x. Introduced in PTX ISA version 1.type d. d = a & b.0. and Syntax Logic and Shift Instructions: and Bitwise AND. The size of the operands must match. a. sign.r. but not necessarily the type. or. Allowed types include predicate registers. Instruction Set Table 70.r.q. and.b32.b32.pred. Table 71. . Supported on all target architectures. Introduced in PTX ISA version 1.b32 mask mask. . . or Syntax Logic and Shift Instructions: or Bitwise OR.Chapter 8.type = { . .b16. or.type d.q. Supported on all target architectures.0x00010001 or.0. and. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.fpvalue. The size of the operands must match.pred. . d = a | b. but not necessarily the type.b16.type = { . 2010 105 . .0x80000000. January 24. b. b.b32 and.

.r. d = (a==0) ? 1 : 0.b32 mask. Introduced in PTX ISA version 1.b32. Introduced in PTX ISA version 1. Supported on all target architectures. not. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. The size of the operands must match.pred p.type d. not. not. xor. Introduced in PTX ISA version 1. . Allowed types include predicate registers.b16 d.0. .b16. . not Syntax Logic and Shift Instructions: not Bitwise negation. but not necessarily the type.type d. Supported on all target architectures. Table 73.x.b64 }.b16.b32. a. Table 74. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). xor. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b32 d.pred. b. one’s complement. . a. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. 2010 . Supported on all target architectures. . but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. .a.type = { . .type d.b64 }.PTX ISA Version 2. d. The size of the operands must match. cnot. cnot. a.0 Table 72.b16. . d = ~a. Allowed types include predicates.b64 }.0.0. 106 January 24.0x0001.b32.type = { .mask. d = a ^ b.q.b32 xor. .pred.q. but not necessarily the type. The size of the operands must match.type = { .

. Instruction Set Table 75.Chapter 8. Shift amounts greater than the register width N are clamped to N. unsigned and untyped shifts fill with 0. regardless of the instruction type. Supported on all target architectures. .2. d = a << b. a. shl. . but not necessarily the type. shr. b. The sizes of the destination and first source operand must match.b32 q. The b operand must be a 32-bit value.u32. d = a >> b.s64 }.s16. . .i.u16 shr. shl. regardless of the instruction type. . k. Bit-size types are included for symmetry with SHL.type = { . Supported on all target architectures. .b32. PTX ISA Notes Target ISA Notes Examples Table 76.type = { .b16.type d. b.0.j.s32 shr. shr.u64. .2.b16. shr Syntax Logic and Shift Instructions: shr Shift bits right.b64.a. . zero-fill on right. sign or zero fill on left. PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1.b32. . i. shl Syntax Logic and Shift Instructions: shl Shift bits left. The b operand must be a 32-bit value. . 2010 107 .b16 c.b64 }. a.type d. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. Introduced in PTX ISA version 1. Signed shifts fill with the sign bit. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. .s32.a.0. The sizes of the destination and first source operand must match.i. Shift amounts greater than the register width N are clamped to N.u16. but not necessarily the type.1.

Instructions ld. local. possibly converting it from one format to another. The cvta instruction converts addresses between generic and global. suld. or shared state spaces. st.PTX ISA Version 2. and from state space to state space. 2010 . mov. ld.7. and sust support optional cache operations.5. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. and st operate on both scalar and vector types. prefetchu isspacep cvta cvt 108 January 24. Data Movement and Conversion Instructions These instructions copy data from place to place.0 8. ldu.

.cs is applied to a Local window address. invalidates (discards) the local L1 line following the load.ca loads cached in L1. . The compiler / programmer may use ld. bypassing the L1 cache. rather than the data stored by the first thread. likely to be accessed again. Instruction Set 8.lu operation. The cache operators require a target architecture of sm_20 or later.cv to a frame buffer DRAM address is the same as ld.cs) on global addresses. The ld. Cache Operators PTX 2. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cv Cache as volatile (consider cached system memory lines stale. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. not L1).lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. the second thread may get stale L1 cache data.7.5. when applied to a local address. . Table 77.cg to cache loads only globally. The ld.ca.1. A ld. For sm_20 and later.cs Cache streaming.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. and a second thread loads that address via a second L1 cache with ld. The ld.cs. If one thread stores to global memory via one L1 cache.cg Cache at global level (cache in L2 and below.lu load last use operation.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. if the line is fully covered. The ld. fetch again).Chapter 8. As a result of this request. it performs the ld. 2010 109 .lu instruction performs a load cached streaming operation (ld. When ld. January 24.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. . Operator . the cache operators have the following definitions and behavior. The default load instruction cache operation is ld. likely to be accessed once. evict-first. but multiple L1 caches are not coherent for global data.ca. to allow the thread program to poll a SysMem location written by the CPU. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. Use ld.lu Last use. any existing cache lines that match the requested address in L1 will be evicted. Global data is coherent at the L2 level.0 introduces optional cache operators on load and store instructions. and cache only in the L2 cache.

If one thread stores to global memory. and cache only in the L2 cache.cg to local memory uses the L1 cache.ca loads.cg is the same as st. 2010 .PTX ISA Version 2. the second thread may get a hit on stale L1 cache data.wt store write-through operation applied to a global System Memory address writes through the L2 cache. in which case st. Future GPUs may have globally-coherent L1 caches.0 Table 78. which writes back cache lines of coherent cache levels with normal eviction policy. but st. to allow a CPU program to poll a SysMem location written by the GPU with st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wb could write-back global store data from L1. rather than get the data from L2 or memory stored by the first thread. .wb. Global stores bypass L1. st. and marks local L1 lines evict-first.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Use st. likely to be accessed once. The st. and discard any L1 lines that match.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cg Cache at global level (cache in L2 and below. bypassing the L1 cache.cg to cache global store data only globally. However. bypassing its L1 cache. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.ca. .wt. The default store instruction cache operation is st.wb for global data. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. regardless of the cache operation. and a second thread in a different SM later loads from that address via a different L1 cache with ld. In sm_20. Addresses not in System Memory use normal write-back.cs Cache streaming. The st. Operator . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. not L1). 110 January 24. .wt Cache write-through (to system memory).

Description .u16.b16. The generic address of a variable in global. . or function name.. 2010 111 . variable in an addressable memory space.s32.type mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.. d = &label. // address is non-generic. immediate. avar.s64.type d. the generic address of a variable declared in global. .1. d = sreg.u64. or shared state space may be taken directly using the cvta instruction. . the parameter will be copied onto the stack and the address will be in the local state space. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. local. // get address of variable // get address of label or function .s16.Chapter 8. Take the non-generic address of a variable in global. d.f64 requires sm_13 or later. i.e. .u32 mov.u32. the address of the variable in its state space) into the destination register. u. sreg.f32 mov. . d = &avar. mov.f64 }. myFunc.local. .type mov. mov. local.b64. k. Instruction Set Table 79.e.shared state spaces.u32 d. .const.f32 mov.v.0. mov places the non-generic address of the variable (i.u32 mov. within the variable’s declared state space Notes Although only predicate and bit-size types are required.b32. Semantics d = a. A.type = { . or shared state space. Operand a may be a register. addr. . and .0. . d. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. a.pred. For variables declared in . Note that if the address of a device function parameter is moved to a register. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. alternately. . Write register d with the value of a. A[5]. label.u16 mov. ptr. label.a. special register.type mov. mov.f32. . d. ptr. local. Introduced in PTX ISA version 1.global. .

23].x | (a.b64 { d..63] } // unpack 16-bit elements from .b16.w << 24) d = a.b32 { d. a[16. . d.31].a have type . mov.x.b32 mov.x.y.7].y.y.b16 { d. . {lo.0.y.x.31].b.7].u32 x.. a[32.a}. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.w}.b32.z << 32) | (a.type d. d. d.15] } // unpack 8-bit elements from . 2010 . Description Write scalar register d with the packed value of vector register a.z.z << 16) | (a.u16 %x is a double.x | (a. {r.hi}. a[48.%r1. d.31] } // unpack 16-bit elements from .b32 mov..b32 %r1.b64 112 January 24.w } = { a[0.z.31] } // unpack 8-bit elements from ..type = { .x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b32 // pack four 16-bit elements into .hi are .g.z. a[8. a[8. Supported on all target architectures.w << 48) d = a.{a. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.x | (a. d.y << 32) // pack two 8-bit elements into .z. a[32.0 Table 80... d.w } = { a[0.w have type .b}.. lo..y << 16) | (a.x | (a. d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.. For bit-size types.. // // // // a.b8 r..b have type .15]. a[16. %x. a[24.b64 mov. mov.y << 8) d = a.b64 }.b64 // pack two 32-bit elements into . d..u8 // unpack 32-bit elements from . a.y } = { a[0. %r1. a[16. .y << 8) | (a. or write vector register d with the unpacked values from scalar register a. d.y } = { a[0.b64 { d.PTX ISA Version 2..b32 { d.47]. Semantics d = a.x.y << 16) d = a.b16 // pack four 8-bit elements into .y } = { a[0.15].b32 // pack two 16-bit elements into ..g.x | (a.b.15].{x.

Semantics d d d d = = = = a. [a].cv }. .vec = { .cs.e. 2010 113 . .0.f16 data may be loaded using ld.b32. . .u32.1. and truncated if the register width exceeds the state space address width for the target architecture. and is zeroextended to the destination register width for unsigned and bit-size types. Instruction Set Table 81. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. . The .v4 }.cop}.f32.s8.reg state space. . or the instruction may fault. The address must be naturally aligned to a multiple of the access size. . Generic addressing and cache operations introduced in PTX ISA 2.ss}. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.global and . ld introduced in PTX ISA version 1.s32. PTX ISA Notes January 24. Within these windows. . Description Load register variable d from the location specified by the source address operand a in specified state space. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. Generic addressing may be used with ld.u16.u64.ss}. .Chapter 8. an address maps to global memory unless it falls within the local memory window or the shared memory window.type = { .cg. to enforce sequential consistency between threads accessing shared memory.volatile.type . and then converted to . . . [a]. 32-bit). *a. 32-bit). for example.volatile. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.type d. i. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. Cache operations are not permitted with ld. *(a+immOff).volatile{.lu. If an address is not properly aligned. .ss = { . *(immAddr).type ld. .shared }.global.f64 }.ca.ss}{. .ss}{. Addresses are zero-extended to the specified width as needed. . [a].local. If no state space is given. ld. The address size may be either 32-bit or 64-bit. or [immAddr] an immediate absolute byte address (unsigned. . an address maps to the corresponding location in local or shared memory. ld.cop}. [a]. i. the resulting behavior is undefined.param..b16.shared spaces to inhibit optimization of references to volatile memory. .f32 or .0.volatile introduced in PTX ISA version 1.volatile{.b16. A destination register wider than the specified type may be used.v2.type ld{.b8.const space suffix may have an optional bank number to indicate constant banks other than bank zero. d.volatile may be used with . . . .const. . .s16. an integer or bit-size type register reg containing a byte address.u8.vec. The value loaded is sign-extended to the destination register width for signed integers.b64.cop = { .e. perform the load using generic addressing.s64. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . d.vec. . This may be used.f64 using cvt. In generic addressing. ld{. d.

x.v4.f16 d. // negative offset %r. // access incomplete array x.PTX ISA Version 2.f64 requires sm_13 or later.b32 ld.const[4].f32.global.[p+4].0 Target ISA Notes ld.[a].[240].[p+-8].const.b32 ld. // load .f32 ld.b16 cvt.[fs].[buffer+64]. Generic addressing requires sm_20 or later.shared. ld.b32 ld.[p]. Cache operations require sm_20 or later.global. 2010 .s32 ld.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. Q.local.local. %r. // immediate address %r.%r. d.b64 ld.

. *(immAddr). to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. an address maps to the corresponding location in local or shared memory. For ldu. ldu. [areg] a register reg containing a byte address. the access may proceed by silently masking off low-order address bits to achieve proper rounding. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. Instruction Set Table 82.f32. .[p+4]. i. The addressable operand a is one of: [avar] the name of an addressable variable var. and truncated if the register width exceeds the state space address width for the target architecture. d.ss}.b16. The address size may be either 32-bit or 64-bit.f64 requires sm_13 or later. and is zeroextended to the destination register width for unsigned and bit-size types. or [immAddr] an immediate absolute byte address (unsigned. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .e. i.Chapter 8.u8. The address must be naturally aligned to a multiple of the access size.global.0.. . 32-bit).f32 d.global. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. // state space .type ldu{. . . ldu.type = { . and then converted to . the resulting behavior is undefined.f16 data may be loaded using ldu. [a].s64.u32.reg state space.f32 Q.b64. perform the load using generic addressing. ldu. . *a.vec.vec = { . . The value loaded is sign-extended to the destination register width for signed integers.u16. A register containing an address may be declared as a bit-size type or integer type. A destination register wider than the specified type may be used. Addresses are zero-extended to the specified width as needed.global }.u64. If an address is not properly aligned. or the instruction may fault.s32. . . *(a+immOff).f64 }.b32. where the address is guaranteed to be the same across all threads in the warp. 2010 115 . only generic addresses that map to global memory are legal. . .global.f64 using cvt.s8.[p].s16.[a].b8. . [a].v4 }. ldu. The data at the specified address must be read-only. Introduced in PTX ISA version 2.v4. an address maps to global memory unless it falls within the local memory window or the shared memory window. . 32-bit).v2. // load from address // vec load from address . If no state space is given.ss}.b16. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. In generic addressing.f32 or . . Within these windows. ldu{.e.type d. PTX ISA Notes Target ISA Notes Examples January 24.b32 d. Semantics d d d d = = = = a. .ss = { .

Generic addressing and cache operations introduced in PTX ISA 2. In generic addressing. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.f64 requires sm_13 or later. i. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.wt }. Cache operations are not permitted with st.volatile introduced in PTX ISA version 1.u8. st. an address maps to global memory unless it falls within the local memory window or the shared memory window.ss}. . *(d+immOffset) = a. . Generic addressing requires sm_20 or later. [a].u16. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.cop .v4 }.reg state space.s8.cop}. an integer or bit-size type register reg containing a byte address. .s64. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.ss}{. . .0. perform the store using generic addressing. st.local. Within these windows. or [immAddr] an immediate absolute byte address (unsigned. st{. { .PTX ISA Version 2.0 Table 83.b16.e. .e.ss}. . [a]. *d = a.u64.volatile.type = = = = {. The address size may be either 32-bit or 64-bit.vec. . .u32. *(immAddr) = a.wb. b. .shared }.type [a]. Addresses are zero-extended to the specified width as needed. Semantics d = a.vec.b8.v2. A source register wider than the specified type may be used.ss}{. to enforce sequential consistency between threads accessing shared memory.1.global and . If no state space is given. The lower n bits corresponding to the instruction-type width are stored to memory.s32.shared spaces to inhibit optimization of references to volatile memory. b.ss . [a].type st{. .b32. The address must be naturally aligned to a multiple of the access size. 32-bit). Cache operations require sm_20 or later. b.f64 }.volatile{. an address maps to the corresponding location in local or shared memory. and truncated if the register width exceeds the state space address width for the target architecture.type . Generic addressing may be used with st.type st. { . .global. 2010 . If an address is not properly aligned. . or the instruction may fault.0.f16 data resulting from a cvt instruction may be stored using st. . PTX ISA Notes Target ISA Notes 116 January 24.volatile{.volatile may be used with . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. st.b16.cg. st introduced in PTX ISA version 1.cop}. the resulting behavior is undefined. . b. .volatile. 32-bit).s16.vec . for example. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. { . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .cs. i.b64. . This may be used.. . . .

2010 117 . Instruction Set Examples st. // negative offset [100].Chapter 8.r7. [fs].global.local.f32 st. [q+-8].s32 st.global. [p].b16 [a]. // %r is 32-bit register // store lower 16 bits January 24. // immediate address %r.%r.s32 cvt.b.v4.a.Q.b32 st.b32 st.local.a.%r. [q+4].f16.local.f32 st.

local }.space}. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. A prefetch to a shared memory location performs no operation. 32-bit). Addresses are zero-extended to the specified width as needed.0 Table 84. an address maps to the corresponding location in local or shared memory. . prefetch{. a register reg containing a byte address.L1. i. A prefetch into the uniform cache requires a generic address.level = { . prefetchu. prefetch. // prefetch to data cache // prefetch to uniform cache . . The address size may be either 32-bit or 64-bit. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.global. the prefetch uses generic addressing.space = { . [a]. or [immAddr] an immediate absolute byte address (unsigned.global. 32-bit).L2 }. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. an address maps to global memory unless it falls within the local memory window or the shared memory window. prefetch and prefetchu require sm_20 or later. 118 January 24.e.level prefetchu.0. In generic addressing.L1 [ptr]. If no state space is given.PTX ISA Version 2. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. in specified state space. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.L1 [addr].L1 [a]. and truncated if the register width exceeds the state space address width for the target architecture. and no operation occurs if the address maps to a local or shared memory location. Within these windows. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 . .

.space p. . Take the generic address of a variable declared in global. For variables declared in global. or vice-versa. or shared state space to generic.lptr.u32 or . or shared state space.space.size cvta.0. lptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. local. islcl. isshrd.space. Description Convert a global. or vice-versa. PTX ISA Notes Target ISA Notes Examples Table 86.space = { . or shared address to a generic address.global. A program may use isspacep to guard against such incorrect behavior. local. p.size = { . isspacep requires sm_20 or later. the generic address of the variable may be taken using cvta.shared. . The source address operand must be a register of type . or shared state space.shared }.u64 }. Introduced in PTX ISA version 2.u32 gptr. The destination register must be of type .space. cvta.size p.local.u32. // convert to generic address // get generic address of var // convert generic address to global. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // local. Instruction Set Table 85.pred . cvta. a. // get generic address of svar cvta.local. p. .to. a.u32 p. // result is . cvta requires sm_20 or later. January 24. a.0.global isspacep. Use cvt. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u64. isspacep. local.local. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.shared isglbl.local isspacep. cvta. local.genptr.u32 p. or shared address.u64 or cvt.space = { . When converting a generic address into a global. gptr. The source and destination addresses must be the same size. .u32 to truncate or zero-extend addresses. isspacep. var.u64. local.Chapter 8.to.global. or shared address cvta. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u32.shared }.global. 2010 119 . sptr.pred. svar.size .

and for same-size float-tofloat conversions where the value is rounded to an integer.rni.rn. the .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.f32. i.frnd}{. a.u8.rpi }.ftz. d.0 Table 87. . . For float-to-integer conversions. .ftz.rmi. 120 January 24.f16.f32 float-tofloat conversions with integer rounding. i.sat For integer destination types.f64 }. .irnd = { .irnd}{. . the result is clamped to the destination range by default.ftz}{.u32.sat limits the result to MININT.dtype. .e. . d = convert(a). For cvt. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. The compiler will preserve this behavior for legacy PTX code.ftz modifier may be specified in these cases for clarity.f32 float-tofloat conversions with integer rounding. subnormal numbers are supported.dtype. // integer rounding // fp rounding .s16.u16. .u64. . Saturation modifier: . . .rz. .ftz. .atype d. . .sat is redundant. .s64.. . The optional .4 and earlier. . Note that saturation applies to both signed and unsigned integer types.sat}. . . Integer rounding modifiers: .rni round to nearest integer. Integer rounding is illegal in all other instances. subnormal inputs are flushed to signpreserving zero. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.s32.f32. Description Semantics Integer Notes Convert between different types and sizes.f32.MAXINT for the size of the operation.dtype.PTX ISA Version 2.frnd = { . 2010 .sat}.dtype. a.ftz}{.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits..rzi. subnormal inputs are flushed to signpreserving zero.atype = { . sm_1x: For cvt. Integer rounding is required for float-to-integer conversions.dtype = .f32 float-to-integer conversions and cvt.atype cvt{. choosing even integer if source is equidistant between two integers. Note: In PTX ISA versions 1.rzi round to nearest integer in the direction of zero . .f32 float-to-integer conversions and cvt.rmi round to nearest integer in direction of negative infinity . cvt{.rm.s8.rp }.ftz.e.

f32 x.f64 j.f64. and for integer-to-float conversions.Chapter 8. and .f16. The optional .f32. if the PTX .f16.0. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. // float-to-int saturates by default cvt. Specifically. The compiler will preserve this behavior for legacy PTX code. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. The operands must be of the same size.f32.f32.s32 f.y.f32. Saturation modifier: .y. Modifier . . cvt. // note .i.version is 1.rz mantissa LSB rounds towards zero . . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .s32. The result is an integral value.4 or earlier.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Subnormal numbers: sm_20: By default. 1. Floating-point rounding is illegal in all other instances. and cvt.f32 x.sat For floating-point destination types.rm mantissa LSB rounds towards negative infinity . // round to nearest int. result is fp cvt.sat limits the result to the range [0.ftz behavior for sm_1x targets January 24. NaN results are flushed to positive zero. cvt to or from . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.rn mantissa LSB rounds to nearest even .ftz modifier may be specified in these cases for clarity.0. cvt.r. 2010 121 .f32. cvt.4 and earlier.f64 types.f32 instructions. Floating-point rounding modifiers: . Note: In PTX ISA versions 1. stored in floating-point format. subnormal numbers are supported. Introduced in PTX ISA version 1.f32. Applies to . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32.f16.0].f64 requires sm_13 or later.rni.

Texture and Surface Instructions This section describes PTX instructions for accessing textures. texture and sampler information is accessed through a single .r4}.height. . 122 January 24. sampler. sampler. add. Texturing modes For working with textures and samplers. allowing them to be defined separately and combined at the site of usage in the program. r1. . and surface descriptors.2d.f32 r1. [tex1].u32 r5.r2. {f1.f32 r1. r3. texture and sampler information each have their own handle. If no texturing mode is declared.v4. The advantage of independent mode is that textures and samplers can be mixed and matched. r6. sampler. // get tex1’s tex.texref tex1 ) { txq. [tex1. add. r5. and surface descriptors. r1. r1. PTX has two modes of operation.. samplers. Module-scope and per-entry scope definitions of texture. div.f32. r5. cvt. } = clamp_to_border.7. mul.b32 r6. r5.target options ‘texmode_unified’ and ‘texmode_independent’. In the unified mode. Ability to query fields within texture. r2.f32. The advantage of unified mode is that it allows 128 samplers.. and surfaces.u32 r5. // get tex1’s txq. the file is assumed to use unified mode. r4.f32 r1.f32 r3. and surface descriptors: • • • Static initialization of texture.b32 r5. . The texturing mode is selected using . A PTX module may declare only one texturing mode. [tex1]. 2010 .f2}]. = nearest width height tsamp1.target texmode_independent .texref handle.r3. sampler. with the restriction that they correspond 1-to-1 with the 128 possible textures.PTX ISA Version 2.param .f32 {r1.0 8. In the independent mode.samplerref tsamp1 = { addr_mode_0 filter_mode }.width. r3. but the number of samplers is greatly restricted to 16.6.entry compute_power ( . and surface descriptors. Example: calculate an element’s power contribution as element’s power/total number of elements. PTX supports the following operations on texture. add.global .

{f1.f4}].btype tex.s32.s32. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. the square brackets are not required and . .btype d.dtype.u32.f3.r2.Chapter 8.2d.e. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. . . is a two-element vector for 2d textures.f32 }. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. If no sampler is specified. 2010 123 . d.r4}. with the extra elements being ignored. b.r2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Unified mode texturing introduced in PTX ISA version 1.f32 }.f2. c]. tex txq suld sust sured suq Table 88. Notes For compatibility with prior versions of PTX. [a. [a.geom. The instruction always returns a four-element vector of 32-bit values. .s32 {r1.geom. the sampler behavior is a property of the named texture. Description Texture lookup using a texture coordinate vector. [tex_a.3d.1d. or the instruction may fault. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. .s32.r3.v4. //Example of unified mode texturing tex.r3. PTX ISA Notes Target ISA Notes Examples January 24. If an address is not properly aligned. where the fourth element is ignored.0.r4}.s32. tex. A texture base address is assumed to be aligned to a 16-byte address. the resulting behavior is undefined.v4. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. . // explicit sampler . [tex_a.v4.1d.geom = { .5.v4 coordinate vectors are allowed for any geometry.dtype. i.v4. Supported on all target architectures. Operand c is a scalar or singleton tuple for 1d textures. Instruction Set These instructions provide access to texture and surface memory. // Example of independent mode texturing tex.f32 {r1. {f1}]. sampler_x. An optional texture sampler b may be specified. c]..3d }.dtype = { . and is a four-element vector for 3d textures.btype = { .

addr_mode_2 }.b32 %r1. // texture attributes // sampler attributes . txq.normalized_coords . // unified mode // independent mode 124 January 24. txq. . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. In unified mode. . 2010 .addr_mode_0 .b32 %r1. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. [tex_A]. [a].b32 d. d.height .addr_mode_0. Description Query an attribute of a texture or sampler.filter_mode.samplerref variable.width.b32 %r1.height.filter_mode.texref or . and in independent mode sampler attributes are accessed via a separate samplerref argument. mirror. Query: .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). [a].normalized_coords }.PTX ISA Version 2. Supported on all target architectures.5. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.width . txq. [smpl_B].addr_mode_0. Operand a is a .depth. clamp_ogl. clamp_to_edge.squery. addr_mode_1. linear } Integer from enum { wrap.b32 txq.squery = { .addr_mode_1 .filter_mode .tquery. .depth . .0 Table 89. Integer from enum { nearest. [tex_A]. sampler attributes are also accessed via a texref argument.tquery = { .width. txq.

f4}.b8 .trap. suld Syntax Texture and Surface Instructions: suld Load from surface memory. If the destination type is .f32. then .clamp field specifies how to handle out-of-bounds addresses: . 2010 125 . {x. Target ISA Notes Examples January 24.5. G. If an address is not properly aligned.f32 }. Instruction Set Table 90. {x}].clamp .v4.trap clamping modifier.trap introduced in PTX ISA version 1. size and type conversion is performed as needed to convert from the surface sample format to the destination type.Chapter 8. Destination vector elements corresponding to components that do not appear in the surface format are not written.2d. Operand a is a . suld.surfref variable.trap {r1. i. suld.cg.dtype. The . . .p is currently unimplemented. b].u32 is returned.b. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .clamp . or .3d requires sm_20 or later.u32.clamp.b32. Description Load from surface memory using a surface coordinate vector. SNORM.cop}.cop . suld.p requires sm_20 or later. // for suld. {f1. .dtype . suld.vec. b].s32.dtype . // for suld. .y. and cache operations introduced in PTX ISA version 2. .b64 }.geom{. .u32.cv }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a. [a. additional clamp modifiers. . .1d. Operand b is a scalar or singleton tuple for 1d surfaces.e.0.geom .s32 is returned.v2. suld.b32.v2.b32. .s32. .trap .trap suld. If the destination base type is .ca.b16.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. // unformatted d. and is a four-element vector for 3d surfaces.w}]. [surf_A.f32 is returned. and the size of the data transfer matches the size of destination operand d.p . then . .p.clamp suld.p.s32.3d.f3. . Coordinate elements are of type . or . if the surface format contains SINT data. if the surface format contains UINT data. the resulting behavior is undefined.3d }. A surface base address is assumed to be aligned to a 16-byte address. suld. . .r2}. // cache operation none.z.f32 based on the surface format as follows: If the surface format contains UNORM.1d.geom{.b. . .v4 }.cs.b.dtype. the surface sample elements are converted to . // formatted . The lowest dimension coordinate represents a sample offset rather than a byte offset. suld.b performs an unformatted load of binary data.zero }. and A components of the surface format.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. sm_1x targets support only the .b64. .vec .v4. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. [surf_B. B.cop}. .s32. is a two-element vector for 2d surfaces. suld.b supported on all target architectures. suld. or the instruction may fault.f2. then .. or FLOAT data. where the fourth element is ignored.b .u32.clamp = = = = = = { { { { { { d.f32.p. Cache operations require sm_20 or later.

trap [surf_A. none. Surface sample components that do not occur in the source vector will be written with an unpredictable value.clamp field specifies how to handle out-of-bounds addresses: .f32. // for sust.p requires sm_20 or later. or . sust. B. G. then .trap introduced in PTX ISA version 1.z. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.p. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. c.r2}. additional clamp modifiers. sust.3d requires sm_20 or later. The size of the data transfer matches the size of source operand c.p performs a formatted store of a vector of 32-bit data values to a surface sample. If the source base type is .wb.b // for sust. the resulting behavior is undefined. . sust. Cache operations require sm_20 or later. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.1d. . A surface base address is assumed to be aligned to a 16-byte address.f32 }. [surf_B. and cache operations introduced in PTX ISA version 2. .b8 .trap sust. or FLOAT data.s32.u32. 2010 . and is a four-element vector for 3d surfaces.b32. sust Syntax Texture and Surface Instructions: sust Store to surface memory. Source elements that do not occur in the surface sample are ignored.f3. sust.b64.clamp = = = = = = { { { { { { [a.p. . sust.trap . .clamp sust.y.v2. sust. // unformatted // formatted .cop}.v2.b performs an unformatted store of binary data. .u32 is assumed. .geom .b.b16.. Operand b is a scalar or singleton tuple for 1d surfaces.p. Target ISA Notes Examples 126 January 24.3d. {x.2d. The . Coordinate elements are of type .wt }.vec.surfref variable.s32.trap.f32. .clamp . . sust. .s32 is assumed. {x}]. sust. . if the surface format contains UINT data. and A surface components. [a. These elements are written to the corresponding surface sample components.0 Table 91. The source vector elements are interpreted left-to-right as R. {r1.vec .trap clamping modifier. is a two-element vector for 2d surfaces. b]. sm_1x targets support only the . SNORM. . i.b.3d }.cop . then .v4.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.zero }. then .f32 is assumed.ctype.v4 }. . b].f4}.0. .1d.5. The source data is then converted from this type to the surface sample format.clamp. If the source type is .geom{.b64 }.cg. Operand a is a . if the surface format contains SINT data.e. sust.b32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.p. If an address is not properly aligned. c. {f1.s32.s32. . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.ctype .ctype.{u32.clamp .PTX ISA Version 2. or the instruction may fault.cop}.b32.f2.f32} are currently unimplemented.cs. .w}]. . .geom{. size and type conversions are performed as needed between the surface sample format and the destination type.vec.ctype .b supported on all target architectures. .b. The lowest dimension coordinate represents a sample offset rather than a byte offset.p Description Store to surface memory using a surface coordinate vector.u32. where the fourth element is ignored. .

clamp.clamp [a.zero }.geom = { . .s32.clamp field specifies how to handle out-of-bounds addresses: . r1.Chapter 8.u32. . sured. .s32.b32 }. the resulting behavior is undefined.min.0. Operand b is a scalar or singleton tuple for 1d surfaces. or the instruction may fault.clamp . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. sured.b32 type.s32 is assumed. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. A surface base address is assumed to be aligned to a 16-byte address.op.p.p. .ctype = { .b performs an unformatted reduction on .clamp [a.. Instruction Set Table 92. i. and .b.op = { . sured. Coordinate elements are of type . sured requires sm_20 or later. then . sured.and.s32 types. January 24.ctype.max. then . is a two-element vector for 2d surfaces. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.u64 data.e. .u32 and . where the fourth element is ignored.u64. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. The instruction type is restricted to .surfref variable.ctype. Reduction to surface memory using a surface coordinate vector.or }.u32. operations and and or apply to .b.b32. Operand a is a .trap . 2010 127 .clamp = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding.b]. .b .trap sured.2d.2d. // for sured.u32 is assumed. . .1d. {x.geom.min.p performs a reduction on sample-addressed 32-bit data. // for sured. .3d }. {x}]. . r1. [surf_B.c. .trap [surf_A. .y}].u32 based on the surface sample format as follows: if the surface format contains UINT data. . and the data is interpreted as .b32.op. The lowest dimension coordinate represents a sample offset rather than a byte offset. Operations add applies to .add. .b].s32.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.1d. min and max apply to .ctype = { .u64.u32. if the surface format contains SINT data.s32 or .s32 types. .b32. .b32 }.add.geom. The . // byte addressing sured.p . // sample addressing .u32.c. and is a four-element vector for 3d surfaces.trap. or . If an address is not properly aligned.

suq. 2010 .b32 d.width. . Operand a is a . suq.height.width .depth }. . [a].5.query.height . [surf_A]. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.surfref variable. Description Query an attribute of a surface. Query: .0 Table 93.PTX ISA Version 2. .b32 %r1. 128 January 24.width. Supported on all target architectures.query = { .

0. p.y. { add.0. 2010 129 .f32 @!p div. {} Syntax Description Control Flow Instructions: { } Instruction grouping. Instruction Set 8. mov. Introduced in PTX ISA version 1.s32 a.7.b. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.c. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.s32 d.7. used primarily for defining a function body. } PTX ISA Notes Target ISA Notes Examples Table 95. Supported on all target architectures.x. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.a.f32 @q bra L23. Execute an instruction or instruction block for threads that have the guard predicate true.Chapter 8.eq.0. ratio. { instructionList } The curly braces create a group of instructions. Threads with a false guard predicate do nothing. @{!}p instruction.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. If {!}p then instruction Introduced in PTX ISA version 1. setp. Supported on all target architectures.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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sync and bar. the waiting threads are restarted without delay. bar.sync 0. a{. All threads in the warp are stalled until the barrier completes. {!}c. Note that a non-zero thread count is required for bar. bar.0.and and . In addition to signaling its arrival at the barrier. Once the barrier count is reached.red performs a reduction operation across threads. and any-thread-true (.sync or bar.{arrive. and the barrier is reinitialized so that it can be immediately reused. Barriers are executed on a per-warp basis as if all the threads in a warp are active. bar. Operand b specifies the number of threads participating in the barrier. a{.red. bar.{arrive. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. 2010 133 .popc).pred .sync with an immediate barrier number is supported for sm_1x targets.version 2.u32 bar. Thus. bar. {!}c.op. b. Description Performs barrier synchronization and communication within a CTA. the optional thread count must be a multiple of the warp size.or). the final value is written to the destination register in all threads waiting at the barrier. bar. and then safely read values stored by other threads prior to the barrier.arrive.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.cta. Only bar.or }.Chapter 8. The barrier instructions signal the arrival of the executing threads at the named barrier. b}. thread count..sync) until the barrier count is met.and. PTX ISA Notes Target ISA Notes Examples bar. if any thread in a warp executes a bar instruction. When a barrier completes.popc.u32. the bar.15. .red} require sm_20 or later. operands p and c are predicates. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. b. it is as if all the threads in the warp have executed the bar instruction. and bar. Since barriers are executed on a per-warp basis.red. Execution in this case is unpredictable. execute a bar. bar.sync or bar.arrive using the same active barrier.red also guarantee memory ordering among threads identical to membar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). threads within a CTA that wish to communicate via memory can store to memory. bar. b}.op = { . b}. and d have type . all threads in the CTA participate in the barrier.0.red performs a predicate reduction across the threads participating in the barrier.sync bar.sync and bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.sync without a thread count introduced in PTX ISA 1. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).arrive does not cause any waiting by the executing threads.arrive a{. p. The reduction operations for bar. while . In conditionally executed code. Operands a. Instruction Set Table 100. Each CTA instance has sixteen barriers numbered 0. If no thread count is specified.and). Thus. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. it simply marks a thread's arrival at the barrier. bar.red instruction.red are population-count (.red} introduced in PTX . thread count. Register operands. a. all-threads-true (. Register operands. d. The result of .red should not be intermixed with bar.red delays the executing threads (similar to bar.popc is the number of threads with a true predicate.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. January 24. and bar.

cta.level = { .PTX ISA Version 2. by st.version 2.0 Table 101.gl} introduced in PTX . by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. For communication between threads in different CTAs or even different SMs. and memory reads by this thread can no longer be affected by other thread writes.gl} supported on all target architectures.cta.gl will typically have a longer latency than membar.4. this is the appropriate level of membar. membar. membar. that is.g. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. level describes the scope of other clients for which membar is an ordering event. global.sys will typically have much longer latency than membar.sys. PTX ISA Notes Target ISA Notes Examples membar.{cta. .{cta. . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar. membar.cta.sys introduced in PTX . membar. membar.version 1.gl. including thoses communicating via PCI-E such as system and peer-to-peer memory. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. 2010 .sys requires sm_20 or later. . membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. when the previous value can no longer be read.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl.g.level. membar. membar.sys Waits until all prior memory requests have been performed with respect to all clients. 134 January 24. membar. membar. A memory read (e. Waits until prior memory reads have been performed with respect to other threads in the CTA. or system memory level.sys }.0.gl. A memory write (e.

s32.type d. For atom. e. The integer operations are add. cas (compare-and-swap). .exch to store to locations accessed by other atomic operations. . The floating-point add. and stores the result of the specified operation at location a. .shared }.b32. performs a reduction operation with operand b and the value in location a.space = { . or. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. The address must be naturally aligned to a multiple of the access size. .f32 }. [a]. .inc. The inc and dec operations return a result in the range [0.Chapter 8.add. Description // // // // // . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.b32. and truncated if the register width exceeds the state space address width for the target architecture. The floating-point operations are add. . .b32 only .op = { ..f32.f32 Atomically loads the original value at location a into destination register d.xor. atom{. .b64. and max. b. . . an address maps to global memory unless it falls within the local memory window or the shared memory window. Instruction Set Table 102.min. If no state space is given.b64 . . the resulting behavior is undefined. max. A register containing an address may be declared as a bit-size type or integer type.and. xor. and max operations are single-precision. atom. or the instruction may fault. The bit-size operations are and. min.u32.s32.u32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. January 24. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. b. i. The address size may be either 32-bit or 64-bit. . .e. i. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. d. 2010 135 .space}.op. . .b].or. or by using atom.type = { . . or [immAddr] an immediate absolute byte address. min. . c. . dec.g.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.dec.cas.op. . .s32. an address maps to the corresponding location in local or shared memory.u64 . min. 32-bit operations. Operand a specifies a location in the specified state space. accesses to local memory are illegal. . inc. .type atom{.global.add. perform the memory accesses using generic addressing. . overwriting the original value.u64.exch.space}. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. [a]. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Within these windows.. If an address is not properly aligned. by inserting barriers between normal stores and atomic operations to a common address. and exch (exchange).e. a de-referenced register areg containing a byte address. Addresses are zero-extended to the specified width as needed.u32 only . . In generic addressing.u32.max }.

shared. atom.{min. : r-1. Introduced in PTX ISA version 1. atom.global requires sm_11 or later.global.PTX ISA Version 2.s. Use of generic addressing requires sm_20 or later.[p]. atom. s) = (r > s) ? s exch(r.my_val. 64-bit atom.[a].shared operations require sm_20 or later.b32 d. c) operation(*a. 2010 . d. b. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. : r.my_new_val.1. 64-bit atom. *a = (operation == cas) ? : } where inc(r.s32 atom. : r+1.0.cas. s) = (r >= s) ? 0 dec(r.max} are unimplemented. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.cas.max.f32 atom. atom. cas(r.f32. d.0 Semantics atomic { d = *a.0.global. Release Notes Examples @p 136 January 24. b).add.add.f32 requires sm_20 or later.t) = (r == s) ? t operation(*a.[x+4].exch} requires sm_12 or later.shared requires sm_12 or later.{add. atom. s) = s.

and max operations are single-precision. where inc(r. .f32. For red.max }. max.u64. and max. inc. Within these windows.b64.min. or the instruction may fault. e. .add. The bit-size operations are and.exch to store to locations accessed by other reduction operations. . . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Operand a specifies a location in the specified state space..s32.op = { . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The address must be naturally aligned to a multiple of the access size. red{. and xor. .inc. b.type [a]. dec(r. b).op.b32 only . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. an address maps to global memory unless it falls within the local memory window or the shared memory window. 32-bit operations. . .u32. perform the memory accesses using generic addressing. red. or [immAddr] an immediate absolute byte address. . s) = (r >= s) ? 0 : r+1. The floating-point operations are add. The address size may be either 32-bit or 64-bit.g.Chapter 8. The floating-point add.space = { .u32. min. or. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . A register containing an address may be declared as a bit-size type or integer type. Notes Operand a must reside in either the global or shared state space.type = { . or by using atom. dec.or. by inserting barriers between normal stores and reduction operations to a common address.dec. . . If an address is not properly aligned. In generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. i. min. . .f32 Performs a reduction operation with operand b and the value in location a. Semantics *a = operation(*a.add. The inc and dec operations return a result in the range [0. If no state space is given. . .and. January 24. .f32 }. .xor. Instruction Set Table 103.space}. Addresses are zero-extended to the specified width as needed. s) = (r > s) ? s : r-1.global.u32 only . .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.u32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. min.u64 . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.e. an address maps to the corresponding location in local or shared memory. Description // // // // . . a de-referenced register areg containing a byte address.s32. overwriting the original value. accesses to local memory are illegal. i.shared }.e. 2010 137 ..s32. . The integer operations are add. and stores the result of the specified operation at location a.b].b32.

global.global requires sm_11 or later red.f32 red.global.add.f32 requires sm_20 or later.my_val.shared.and.max} are unimplemented. 64-bit red.1. red.f32.0.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [p].b32 [a]. Release Notes Examples @p 138 January 24. 2010 .PTX ISA Version 2.{min.shared operations require sm_20 or later.add. red.s32 red.2.add requires sm_12 or later.max. red. red.shared requires sm_12 or later. 64-bit red. Use of generic addressing requires sm_20 or later. [x+4].

uni True if source predicate has the same value in all active threads in warp.uni.q.all. In the ‘ballot’ form.b32 requires sm_20 or later. The destination predicate value is the same across all threads in the warp. Negate the source predicate to compute . Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.uni }. . returns bitmask . vote.all True if source predicate is True for all active threads in warp. vote.2. The reduction modes are: . . vote requires sm_12 or later.q. Negate the source predicate to compute . // ‘ballot’ form. p.mode = { . Instruction Set Table 104.ballot. r1. Negating the source predicate also computes .any True if source predicate is True for some active thread in warp.pred vote. .ballot.uni. vote.ballot.b32 p. . where the bit position corresponds to the thread’s lane id. Description Performs a reduction of the source predicate across threads in a warp.p. 2010 139 .none.Chapter 8. vote.pred vote.all.b32 d. not across an entire CTA. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. {!}a. vote.not_all.any. {!}a. Note that vote applies to threads in a single warp.pred d.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.mode.ballot. // get ‘ballot’ across warp January 24.

secop d.s33 values.asel}. .btype = { .asel}.min. The source and destination operands are all 32-bit registers. The primary operation is then performed to produce an .7. to produce signed 33-bit input values.b1.sat} d. a{.bsel}.h0. 2010 . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). . with optional data merge vop.dtype. all combinations of dtype.u32 or .extended internally to . . . 2.b3.atype. 4.atype.asel = . extract and sign. c.b0. .s32) is specified in the instruction type. a{. b{.9. atype. taking into account the subword destination size in the case of optional data merging.asel}.btype{. .or zero-extend byte. perform a scalar arithmetic operation to produce a signed 34-bit result. b{.s34 intermediate result.bsel}.btype{. a{. optionally clamp the result to the range of the destination type.sat}.0 8. . Video Instructions All video instructions operate on 32-bit register operands.atype = . The sign of the intermediate result depends on dtype. or word values from its source operands. . .dsel. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.b2. 140 January 24. and btype are valid. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.u32. with optional secondary operation vop.s32 }. vop. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.dsel = . Using the atype/btype and asel/bsel specifiers.bsel}.secop = { . the input values are extracted and signor zero. The type of each operand (. half-word. .atype.btype{.add.dtype = . c. b{. 3.h1 }.dtype. // 32-bit scalar operation.sat} d. The general format of video instructions is as follows: // 32-bit scalar operation.PTX ISA Version 2.dtype. .max }.bsel = { .

c). U16_MAX. U16_MIN ). U8_MIN ). c).h0: return ((tmp & 0xffff) case . . tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case . S8_MAX.s33 tmp. Instruction Set .add: return tmp + c. U32_MIN ).s33 c ) switch ( dsel ) { case . .b2.Chapter 8.s33 tmp. c). . c). S16_MAX.b1.h1: return ((tmp & 0xffff) << 16) case . . The lower 32-bits are then written to the destination operand. c). . U8_MAX. Modifier dsel ) { if ( !sat ) return tmp. } } . switch ( dsel ) { case .s33 optSaturate( . . default: return tmp. S32_MIN ).h0.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. January 24.s33 optSecOp(Modifier secop. Bool sign. U32_MAX. S32_MAX. . . c).s34 tmp. tmp. The sign of the c operand is based on dtype.b2: return ((tmp & 0xff) << 16) case . S16_MIN ). tmp.min: return MIN(tmp.b0.s33 optMerge( Modifier dsel. . S8_MIN ).b0: return ((tmp & 0xff) case . as shown in the following pseudocode. Bool sat. tmp.b3: return ((tmp & 0xff) << 24) default: return tmp. c). .b1: return ((tmp & 0xff) << 8) case . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. 2010 141 .s33 c) { switch ( secop ) { . tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). .max return MAX(tmp.

vmin.sat} d. sat. and optional secondary arithmetic operation or subword data merge. vop.b0.b2. vadd. btype.h0. tmp = | ta – tb |.b0.min.u32. .u32.s32.dsel . 2010 . .b2. // optional merge with c operand 142 January 24. bsel ). { . vsub.s32.h1. . // optional secondary operation d = optMerge( dsel. Integer byte/half-word/word absolute value of difference.atype. with optional secondary operation vop. tmp. tmp. // extract byte/half-word/word and sign.op2 Description = = = = { vadd.op2 d.bsel}. a{. tmp = MIN( ta.s32 }. tmp = ta – tb. with optional data merge vop. r2.h1.bsel}.0. Semantics // saturate.sat} d.s32.b3.btype{. b{. .sat vmin. r3. a{.asel}.max }.asel}. tb = partSelectSignExtend( b. vabsdiff. . dsel ). .s32. c ). .btype{. c ). c. a{.asel = .btype = { .sat. b{. Integer byte/half-word/word minimum / maximum. tb ). r3. c.h0.atype. vabsdiff. . Video Instructions: vadd. .vop . vabsdiff.sat}. vsub.bsel = { . vmax }. // 32-bit scalar operation. vsub vabsdiff vmin. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.btype{. asel ). Perform scalar arithmetic operation with optional saturate. tmp = MAX( ta.s32. d = optSecondaryOp( op2. vadd. vsub.b0. r1.dtype. r1.u32. atype.bsel}.s32. vmax require sm_20 or later. // 32-bit scalar operation.0 Table 105. c. r2. taking into account destination type and merge operations tmp = optSaturate( tmp.atype. r1.dsel.dtype .or zero-extend based on source operand type ta = partSelectSignExtend( a. vmin. r3. vmax vadd. r3.h0.dtype. tb ).s32.s32. vmax Syntax Integer byte/half-word/word addition / subtraction.sat vsub.atype = .add r1.PTX ISA Version 2. b{. .sat vabsdiff.b1. isSigned(dtype).s32. vmin. r2.dtype.s32. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.asel}. c.h1 }.add. . r2.

mode .or zero-extend based on source operand type ta = partSelectSignExtend( a. // 32-bit scalar operation.mode} d.u32. .b1. vshl: Shift a left by unsigned amount in b with optional saturate. Semantics // extract byte/half-word/word and sign. a{.mode} d.sat}{. . . r3. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.wrap ) tb = tb & 0x1f. Instruction Set Table 106.atype = { .dtype.asel}. .atype. d = optSecondaryOp( op2. c ). 2010 143 .clamp .0. and optional secondary arithmetic operation or subword data merge. tmp.wrap r1.u32{. vshl. January 24. . dsel ).asel}.add.op2 Description = = = = = { vshl. r3.dtype. vshr require sm_20 or later. atype. and optional secondary arithmetic operation or subword data merge. Video Instructions: vshl.clamp.sat}{. r1.u32.s32 }.wrap }. // optional secondary operation d = optMerge( dsel. sat.op2 d. .u32{.min. . c. vshr }.bsel}.dtype .s32. Signed shift fills with the sign bit. case vshr: tmp = ta >> tb.sat}{. .asel = . asel ).u32. isSigned(dtype). Left shift fills with zero.dtype.bsel}.b3. a{. bsel ).atype. . if ( mode == . b{. { . unsigned shift fills with zero. tb = partSelectSignExtend( b.clamp && tb > 32 ) tb = 32. with optional secondary operation vop. // 32-bit scalar operation.bsel}.u32 vshr. . vshr Syntax Integer byte/half-word/word left / right shift.h1. } // saturate. taking into account destination type and merge operations tmp = optSaturate( tmp.max }.mode}.u32. // default is . vshl.b0. vshr vshl.h1 }. b{.u32{. . tmp.dsel . c ). b{.bsel = { . if ( mode == . vop. switch ( vop ) { case vshl: tmp = ta << tb. a{. . r2.u32. { .asel}. r2.u32.h0.atype. vshr: Shift a right by unsigned amount in b with optional saturate.vop .Chapter 8.b2. c.dsel. with optional data merge vop.

(a*b) is negated if and only if exactly one of a or b is negated.asel}.U32 // intermediate unsigned.b0. vmad. . 2010 .S32 // intermediate signed. and the operand negates.b1.scale} d. . .h0.dtype = . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final signed The intermediate result is optionally scaled via right-shift. final signed (S32 * S32) + S32 // intermediate signed. c. final signed -(U32 * S32) + S32 // intermediate signed. // 32-bit scalar operation vmad.u32.atype. 144 January 24. {-}b{.dtype.btype.b3.S32 // intermediate signed.atype = . Depending on the sign of the a and b operands. Input c has the same sign as the intermediate result.shr7. final signed (S32 * S32) .po) computes (a*b) + c + 1. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.bsel}. . .po{. final signed (U32 * S32) + S32 // intermediate signed. and zero-extended otherwise.S32 // intermediate signed. with optional operand negates. final signed (S32 * U32) . . {-}a{. this result is sign-extended if the final result is signed. The source operands support optional negation with some restrictions.sat}{. . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. internally this is represented as negation of the product (a*b).asel}. final signed -(S32 * U32) + S32 // intermediate signed. PTX allows negation of either (a*b) or c. “plus one” mode..0 Table 107.btype = { . .btype{. final signed (U32 * S32) . b{. a{.scale} d. final unsigned -(U32 * U32) + S32 // intermediate signed. The “plus one” mode (. The final result is unsigned if the intermediate result is unsigned and c is not negated. .atype.b2.sat}{. .dtype. Source operands may not be negated in .bsel}.h1 }. otherwise.s32 }.po mode. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. and scaling.bsel = { . final signed -(S32 * S32) + S32 // intermediate signed. final signed (U32 * U32) . the intermediate result is signed.PTX ISA Version 2.asel = . final signed (S32 * U32) + S32 // intermediate signed. Although PTX syntax allows separate negation of the a and b operands.shr15 }. which is used in computing averages. {-}c.scale = { . Description Calculate (a*b) + c. That is.

sat ) { if (signedFinal) result = CLAMP(result.or zero-extend based on source operand type ta = partSelectSignExtend( a.sat vmad. if ( . signedFinal = isSigned(atype) || isSigned(btype) || (a. lsb = 0. btype. lsb = 1. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). else result = CLAMP(result.s32.po ) { lsb = 1. lsb = 1.negate ) { c = ~c. atype. bsel ). r0. U32_MIN). } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.negate. S32_MIN).u32.u32. 2010 145 .negate ^ b. S32_MAX.h0. -r3. case .shr15 r0. vmad. } if ( .h0. r1. switch( scale ) { case . } else if ( c.shr7: result = (tmp >> 7) & 0xffffffffffffffff. vmad requires sm_20 or later. Instruction Set Semantics // extract byte/half-word/word and sign.u32. r2.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate) || c.u32. asel ). r2. tmp = tmp + c128 + lsb. tb = partSelectSignExtend( b.0. January 24. } else if ( a.Chapter 8.negate ) { tmp = ~tmp. r3.s32. r1. U32_MAX. tmp[127:0] = ta * tb.negate ^ b.

ne r1. . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. b{. vset. . The intermediate result of the comparison is always unsigned. // 32-bit scalar operation. and therefore the c operand and final result are also unsigned.btype.asel}.b2. bsel ). . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // optional secondary operation d = optMerge( dsel.btype.btype.atype .ne. tb. . r3. tmp. Compare input values using specified comparison.s32 }. with optional secondary arithmetic operation or subword data merge. b{. . r2.h0. . c ).u32.dsel .min. with optional data merge vset. atype.cmp d. tmp.cmp .btype = { . b{. btype.op2 d.lt vset.h1 }.u32.atype. .add. a{. . tmp = compare( ta. .gt.eq.PTX ISA Version 2. .asel}. .or zero-extend based on source operand type ta = partSelectSignExtend( a. vset requires sm_20 or later.u32. tb = partSelectSignExtend( b. c.le.cmp.bsel}. vset.dsel.h1.b1. . a{.bsel = { . // 32-bit scalar operation. d = optSecondaryOp( op2. { . . 146 January 24.0. c ). c. r2.bsel}.bsel}. 2010 . . cmp ) ? 1 : 0.max }.u32.0 Table 108.atype.lt. . asel ). r1. with optional secondary operation vset.atype.asel = .cmp d. a{.b0. r3. Semantics // extract byte/half-word/word and sign.s32.ge }. { .b3.op2 Description = = = = .asel}.

@p pmevent 1.0. trap. there are sixteen performance monitor events. brkpt.4. pmevent 7.10. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Supported on all target architectures. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Instruction Set 8. The relationship between events and counters is programmed via API calls from the host. brkpt Suspends execution Introduced in PTX ISA version 1. Table 111. 2010 147 .0. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Supported on all target architectures. brkpt requires sm_11 or later. Triggers one of a fixed number of performance monitor events. with index specified by immediate operand a.7. Table 110. trap.Chapter 8. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. January 24. pmevent a. brkpt. numbered 0 through 15. trap Abort execution and generate an interrupt to the host CPU.

2010 .PTX ISA Version 2.0 148 January 24.

read-only variables. %lanemask_le. %lanemask_gt %clock. 2010 149 . which are visible as special registers and accessed through mov or cvt instructions. Special Registers PTX includes a number of predefined. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %pm3 January 24. …. %lanemask_ge. %clock64 %pm0. %lanemask_lt.Chapter 9.

cvt.0.0.z == 1 in 2D CTAs.%h2. Redefined as . %tid component values range from 0 through %ntid–1 in each CTA dimension. 2010 .sreg .%tid. . The total number of threads in a CTA is (%ntid.z == 1 in 1D CTAs.v4.z < %ntid. // zero-extend tid. mad.z == 0 in 1D CTAs.%h1.x to %rh Target ISA Notes Examples // legacy PTX 1.u32 %r1. . the %tid value in unused dimensions is 0.u32 %r0. %tid.z.%tid. %tid.sreg .x. %ntid. mov. mov. %ntid.z to %r2 Table 113. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x * %ntid.v4 . mov. %ntid.%tid.u16 %r2. Every thread in the CTA has a unique %tid.y * %ntid. Supported on all target architectures.u32 %r0.x. The %tid special register contains a 1D.0.y. or 3D vector to match the CTA shape. %tid.%ntid. // compute unified thread id for 2D CTA mov.y.%r0. It is guaranteed that: 0 <= %tid.z). Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. .u16 %rh.x code Target ISA Notes Examples 150 January 24.y == %ntid.z == 0 in 2D CTAs.u32 %ntid.z.u32 type in PTX 2. The number of threads in each dimension are specified by the predefined special register %ntid.u32 %h1. read-only special register initialized with the number of thread ids in each CTA dimension. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. %ntid.x. CTA dimensions are non-zero.x code accessing 16-bit component of %tid mov.y 0 <= %tid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. the fourth element is unused and always returns zero.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %tid.y == %tid. // move tid.z.x.u32 %h2.PTX ISA Version 2. // thread id vector // thread id components A predefined.%tid.y. mov.v4.x 0 <= %tid.x.%tid.u32 %tid. // legacy PTX 1.sreg .x. Redefined as . read-only.u16 %rh.x < %ntid.%ntid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.u32 type in PTX 2. Supported on all target architectures.sreg .0. per-thread special register initialized with the thread identifier within the CTA. The fourth element is unused and always returns zero.u32 %ntid.v4 . .y < %ntid. 2D. PTX ISA Notes Introduced in PTX ISA version 1. // CTA shape vector // CTA dimensions A predefined.x. %tid.0 Table 112.u32.

due to rescheduling of threads following preemption. A predefined. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. 2010 151 . Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %warpid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Supported on all target architectures. read-only special register that returns the thread’s lane within the warp. mov.0. read-only special register that returns the thread’s warp identifier. . Note that %warpid is volatile and returns the location of a thread at the moment when read.g. For this reason.u32 %r.u32 %r.u32 %r.3. . read-only special register that returns the maximum number of warp identifiers. but its value may change during execution. Introduced in PTX ISA version 1.u32 %laneid. A predefined.sreg . Introduced in PTX ISA version 2. %nwarpid. A predefined. The lane identifier ranges from zero to WARP_SZ-1. mov. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. . PTX ISA Notes Target ISA Notes Examples Table 116. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Introduced in PTX ISA version 1. The warp identifier will be the same for all threads within a single warp. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %nwarpid requires sm_20 or later. %laneid.Chapter 9. January 24. Table 115.sreg .3. Special Registers Table 114. e. Supported on all target architectures.u32 %nwarpid.sreg . %warpid. mov.

u32 type in PTX 2. or 3D vector.u32 %ctaid.0. It is guaranteed that: 0 <= %ctaid.x. // legacy PTX 1.x 0 <= %ctaid. 2D. The fourth element is unused and always returns zero.z PTX ISA Notes Introduced in PTX ISA version 1.0. %ctaid.%nctaid.y.PTX ISA Version 2.x.y.u32 mov. depending on the shape and rank of the CTA grid.z. The %ctaid special register contains a 1D.%ctaid.u32 type in PTX 2. Each vector element value is >= 0 and < 65535.u32 %ctaid.z} < 65.sreg .sreg . Supported on all target architectures.%ctaid. . %rh.z. %rh. // Grid shape vector // Grid dimensions A predefined. Redefined as .x.sreg . with each element having a value of at least 1. mov. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u32 %nctaid .v4 .%nctaid.v4 .y < %nctaid.x code Target ISA Notes Examples Table 118.%nctaid.z < %nctaid.x code Target ISA Notes Examples 152 January 24. read-only special register initialized with the number of CTAs in each grid dimension.v4. // CTA id vector // CTA id components A predefined.y 0 <= %ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. // legacy PTX 1. The %nctaid special register contains a 3D grid shape vector.y. %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.u16 %r0. .sreg .x.536 PTX ISA Notes Introduced in PTX ISA version 1. read-only special register initialized with the CTA identifier within the CTA grid.x < %nctaid.%nctaid.0.0. 2010 .y. The fourth element is unused and always returns zero.0 Table 117. Redefined as . mov. It is guaranteed that: 1 <= %nctaid. .u16 %r0.u32 %nctaid.{x.x.v4.u32 mov. Supported on all target architectures. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.

Introduced in PTX ISA version 1.3. PTX ISA Notes Target ISA Notes Examples January 24.Chapter 9. Supported on all target architectures. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.u32 %r.0. PTX ISA Notes Target ISA Notes Examples Table 121. 2010 153 . The SM identifier ranges from 0 to %nsmid-1.u32 %nsmid. The SM identifier numbering is not guaranteed to be contiguous.u32 %r. mov. Note that %smid is volatile and returns the location of a thread at the moment when read. where each launch starts a grid-of-CTAs. %smid.u32 %gridid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. repeated launches of programs may occur.g. Introduced in PTX ISA version 2. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. The SM identifier numbering is not guaranteed to be contiguous. A predefined. read-only special register that returns the maximum number of SM identifiers. %nsmid requires sm_20 or later. Special Registers Table 119. mov. // initialized at grid launch A predefined.0. read-only special register initialized with the per-grid temporal grid identifier. . Supported on all target architectures. . %nsmid. but its value may change during execution. due to rescheduling of threads following preemption.sreg .sreg . During execution. so %nsmid may be larger than the physical number of SMs in the device.u32 %smid. %gridid.sreg . A predefined. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Notes PTX ISA Notes Target ISA Notes Examples Table 120. e. This variable provides the temporal grid launch number for this context. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. Introduced in PTX ISA version 1.u32 %r. mov. . Special Registers: %smid %smid Syntax (predefined) Description SM identifier.

u32 %r. Table 123.u32 %lanemask_lt.u32 %lanemask_le. Introduced in PTX ISA version 2. %lanemask_le requires sm_20 or later. Introduced in PTX ISA version 2.0 Table 122. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %r. %lanemask_lt requires sm_20 or later. . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. %lanemask_eq.u32 %r.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %lanemask_eq. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. 2010 . Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . mov. Table 124. mov. Introduced in PTX ISA version 2.0.0.0.sreg .sreg . A predefined. %lanemask_le. %lanemask_lt. A predefined. . %lanemask_eq requires sm_20 or later. mov.PTX ISA Version 2. 154 January 24. A predefined.

u32 %lanemask_gt. Introduced in PTX ISA version 2. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt requires sm_20 or later. Special Registers Table 125.Chapter 9. January 24.sreg . %lanemask_ge. mov.sreg . %lanemask_gt. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Table 126. 2010 155 .u32 %r.u32 %lanemask_ge.u32 %r. mov. %lanemask_ge requires sm_20 or later.0. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Introduced in PTX ISA version 2. A predefined. . A predefined.0. . read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.

u64 %clock64. Introduced in PTX ISA version 1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Introduced in PTX ISA version 2. Supported on all target architectures. mov. %pm1.u32 %clock. %pm3 %pm0.0 Table 127. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. and %pm3 are unsigned 32-bit read-only performance monitor counters.sreg .u32 %pm0. 156 January 24.%clock.u64 r1. .0.PTX ISA Version 2. %pm2. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. read-only 64-bit unsigned cycle counter. mov. Introduced in PTX ISA version 1.0. Table 129.%pm0. %pm1. The lower 32-bits of %clock64 are identical to %clock. …. .3. %pm2.%clock64. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. %pm1.sreg . Supported on all target architectures.u32 r1.sreg . mov. Their behavior is currently undefined. %pm2. %pm3. %clock64 requires sm_20 or later. Special registers %pm0. Special Registers: %pm0. read-only 32-bit unsigned cycle counter.u32 r1. 2010 . Table 128. .

PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.Chapter 10.minor // major. minor are integers Specifies the PTX language version number.version major. . Duplicate .version directives are allowed provided they match the original .version 1. Supported on all target architectures. PTX File Directives: .version Syntax Description Semantics PTX version number.version directive.version 2.version .version . . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. 2010 157 .target Table 130. Directives 10.4 January 24.1. and the target architecture for which the code was generated. Increments to the major number indicate incompatible changes to PTX.version directive. Each ptx file must begin with a . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. .0 .

with only half being used by instructions converted from .f64 instructions used. brkpt instructions.target Syntax Architecture and Platform target.f64 to . The following table summarizes the features in PTX that vary according to target architecture. Requires map_f64_to_f32 if any .red}. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.f64 storage remains as 64-bits.texmode_unified . Texturing mode: (default is .target directive specifies a single target architecture.f64 instructions used. immediately followed by a .target .PTX ISA Version 2.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. sm_11. map_f64_to_f32 }. sm_13. Therefore. where each generation adds new features and retains all features of previous generations. Adds {atom. A program with multiple . Disallows use of map_f64_to_f32. PTX File Directives: . 158 January 24.0 Table 131. Target sm_20 Description Baseline feature set for sm_20 architecture. texmode_unified.texmode_unified) . sm_12. Supported on all target architectures. Requires map_f64_to_f32 if any . PTX features are checked against the specified target architecture.5. Adds {atom.target directive containing a target architecture and optional platform options.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.red}. The texturing mode is specified for an entire module and cannot be changed within the module.f64 instructions used.target directives can be used to change the set of target features allowed during parsing.version directive. texmode_independent.0. A . Description Specifies the set of features in the target architecture for which the current ptx code was generated.red}.texmode_independent texture and sampler information is bound together and accessed via a single . . sm_10. vote instructions. Requires map_f64_to_f32 if any . generations of SM architectures follow an “onion layer” model. Adds double-precision support.f32.global.global. texture and sampler information is referenced with independent . including expanded rounding modifiers. Introduced in PTX ISA version 1. Note that . 64-bit {atom. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.samplerref descriptors.texref descriptor. PTX code generated for a given target can be run on later generation devices. and an error is generated if an unsupported feature is used. 2010 . Each PTX file must begin with a . but subsequent . Texturing mode introduced in PTX ISA version 1.shared.texref and . In general. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.

target sm_13 // supports double-precision . 2010 159 .target sm_20. Directives Examples .target sm_10 // baseline target architecture .Chapter 10. texmode_independent January 24.

entry kernel-name kernel-body Defines a kernel entry point name. Parameters may be referenced by name within the kernel body and loaded into registers using ld.0 through 1. The shape and size of the CTA executing the kernel are available in special registers. For PTX ISA versions 1. .entry . the kernel dimensions and properties are established and made available via special registers.0 through 1. and . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. e. ld.func Table 132. opaque .param { . Semantics Specify the entry point for a kernel program. .b32 x. and query instructions and cannot be accessed via ld. Parameters are passed via . Kernel and Function Directives: . and body for the kernel function. At kernel launch. .texref.param.3.entry .PTX ISA Version 2. ld. … } . Supported on all target architectures. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. parameters. with optional parameters.g.entry Syntax Description Kernel entry point and body.4. These parameters can only be referenced by name within texture and surface load.4 and later.param instructions. PTX ISA Notes For PTX ISA version 1.2. %nctaid. parameter variables are declared in the kernel body.0 10. ld. .param instructions. .param . .b32 %r3.b32 z ) Target ISA Notes Examples [x].entry filter ( .param.reg .b32 y.5 and later. 2010 .b32 %r1.param space memory and are listed within an optional parenthesized parameter list. parameter variables are declared in the kernel parameter list. In addition to normal parameters. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. 160 January 24.b32 %r2.entry cta_fft . [y].surfref variables may be passed as parameters.entry kernel-name ( param-list ) kernel-body .b32 %r<99>.samplerref. etc. store.param . [z]. %ntid.param.

0 with target sm_20 supports at most one return value. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.reg .Chapter 10. other code.func (ret-param) fname (param-list) function-body Defines a function. ret.reg . mov.param and st. and supports recursion. val1). A . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. (val0. … Description // return value in fooval January 24.func fname function-body .b32 N.2 for a description of variadic functions.func (. Kernel and Function Directives: .func definition with no body provides a function prototype.func fname (param-list) function-body .param space are accessed using ld.result. Variadic functions are represented using ellipsis following the last fixed argument.reg . Release Notes For PTX ISA version 1.func Syntax Function definition.f64 dbl) { . Variadic functions are currently unimplemented. PTX 2. .b32 rval) foo (.b32 localVar. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Directives Table 133.0.x code. parameters must be in the register state space.0 with target sm_20 allows parameters in the .param state space. Parameter passing is call-by-value. } … call (fooval). including input and return parameters and optional function body.reg . if any. Parameters in register state space may be referenced directly within instructions in the function body. … use N.b32 rval.func .param instructions in the body. implements an ABI with stack. foo. 2010 161 . . Supported on all target architectures. Parameters in . there is no stack. PTX ISA 2. dbl. Parameters must be base types in either the register or parameter state space. The implementation of parameter passing is left to the optimizing translator. and recursion is illegal. which may use a combination of registers and stack locations to pass parameters. . The parameter lists define locally-scoped variables in the function body.

162 January 24. registers) to increase total thread count and provide a greater opportunity to hide memory latency.3.maxnreg. at entry-scope.maxnreg . The directives take precedence over any module-level constraints passed to the optimizing backend.pragma directives may appear at module (file) scope. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.g. or as statements within a kernel or device function body.maxntid. to throttle the resource requirements (e. Currently. for example. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. and the .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). 2010 .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.pragma The .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. A general . The interpretation of . and . PTX supports the following directives.entry directive and its body.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. and the strings have no semantics within the PTX virtual machine model. the .PTX ISA Version 2. which pass information to the backend optimizing compiler. . .maxntid and . Note that .maxntid . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. These can be used.maxnctapersm (deprecated) .minnctapersm .maxntid directive specifies the maximum number of threads in a thread block (CTA). the . The .pragma directive is supported for passing information to the PTX backend. The directive passes a list of strings to the backend.0 10.minnctapersm directives may be applied per-entry and must appear between an .

maxntid 16. 2D. Performance-Tuning Directives: . for example. nz Declare the maximum number of threads in the thread block (CTA). .entry foo . or the maximum number of registers may be further constrained by . Performance-Tuning Directives: .maxntid . Introduced in PTX ISA version 1.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.3.16. Supported on all target architectures.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. or 3D CTA. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid and .Chapter 10.3. ny .maxntid nx . the backend may be able to compile to fewer registers.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. Exceeding any of these limits results in a runtime error or kernel launch failure.maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg n Declare the maximum number of registers per thread in a CTA.entry bar . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Directives Table 134.maxctapersm. .maxntid 256 . The actual number of registers used may be less. Supported on all target architectures. ny. . Introduced in PTX ISA version 1. The maximum number of threads is the product of the maximum extent in each dimension. 2010 163 .maxntid nx.maxntid nx. .entry foo . The compiler guarantees that this limit will not be exceeded.maxnreg .

maxntid 256 .PTX ISA Version 2. Supported on all target architectures.entry foo .maxnctapersm has been renamed to . additional CTAs may be mapped to a single multiprocessor.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxntid and . .maxntid to be specified as well.minnctapersm generally need . Performance-Tuning Directives: . .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). The optimizing backend compiler uses .3. Deprecated in PTX ISA version 2.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. .0.maxntid 256 .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm.maxnctapersm generally need . Performance-Tuning Directives: . if the number of registers used by the backend is sufficiently lower than this bound.maxnctapersm (deprecated) .minnctapersm 4 { … } 164 January 24.minnctapersm .0 Table 136.minnctapersm in PTX ISA version 2. Optimizations based on . However. Introduced in PTX ISA version 1. Supported on all target architectures. Introduced in PTX ISA version 2.0 as a replacement for . 2010 .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.entry foo .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0. For this reason. Optimizations based on .maxntid to be specified as well. . .

.entry foo . Supported on all target architectures. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma Syntax Description Pass directives to PTX backend compiler. { … } January 24. 2010 165 . or at statementlevel. Directives Table 138.pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma “nounroll”. . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . at entry-scope. The interpretation of .pragma list-of-strings .0.Chapter 10. or statement-level directives to the PTX backend compiler.pragma “nounroll”.pragma directive may occur at module-scope.pragma . Performance-Tuning Directives: . Introduced in PTX ISA version 2. Pass module-scoped. entry-scoped. The .

PTX ISA Version 2.section directive is new in PTX ISA verison 2. 0x00 . 0x02. Deprecated as of PTX 2.quad int64-list // comma-separated hexadecimal integers in range [0. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . The @@DWARF syntax is deprecated as of PTX version 2. 0x6150736f. replaced by .232-1] . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x63613031. Table 139.byte byte-list // comma-separated hexadecimal byte values . 0x00.byte 0x2b.264-1] . 0x00. 0x00 166 January 24. 0x61395a5f. 0x00.section . 0x00.0 10.2.0 and replaces the @@DWARF syntax.section . 0x736d6172 .4byte label ..0. @@DWARF dwarf-string dwarf-string may have one of the .4byte 0x6e69616d.4. 2010 .x code.section directive..debug_pubnames.debug_info .4byte int32-list // comma-separated hexadecimal integers in range [0. 0x00000364.0 but is supported for legacy PTX version 1.4byte .4byte 0x000006b5.byte 0x00. Introduced in PTX ISA version 1. @progbits . 0x00. 0x00. “”. 0x5f736f63 .file . Supported on all target architectures.loc The .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.

0x00.. .b8 0x2b.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.file .. Source file information. 0x00 0x61395a5f.b64 int64-list // comma-separated list of integers in range [0.b32 0x000006b5.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x00.section . Supported on all target architectures.debug_info .0. Debugging Directives: . 0x00. .section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x6e69616d. .b32 .section Syntax PTX section definition. . .255] . 0x5f736f63 0x6150736f. Supported on all target architectures. replaces @@DWARF syntax.264-1] .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 int32-list // comma-separated list of integers in range [0. 0x00. } 0x02.section .file filename Table 142. 0x00.232-1] . 0x00000364. 0x00. 0x736d6172 0x00 Table 141. 2010 167 .debug_pubnames { . Debugging Directives: . Supported on all target architectures. Directives Table 140. Debugging Directives: .b32 label .0.0.b8 0x00. 0x63613031. Source file location..b8 byte-list // comma-separated list of integers in range [0. .Chapter 10.loc line_number January 24. .loc .

visible identifier Declares identifier to be externally visible.0.b32 foo. .extern . // foo will be externally visible 168 January 24. Supported on all target architectures.extern . // foo is defined in another module Table 144. Introduced in PTX ISA version 1. .PTX ISA Version 2. . Supported on all target architectures.extern identifier Declares identifier to be defined externally.visible .6. .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible Table 143.extern .b32 foo. Introduced in PTX ISA version 1. Linking Directives: .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.global .visible .global . Linking Directives .0 10. 2010 .0. Linking Directives: .

Release Notes This section describes the history of change in the PTX ISA and implementation.1 PTX ISA 1.3 driver r190 CUDA 3.2 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 driver r195 PTX ISA Version PTX ISA 1.0 PTX ISA 1. The release history is as follows.0 January 24.2 CUDA 2. CUDA Release CUDA 1.5 PTX ISA 2.0 CUDA 1.Chapter 11.1 CUDA 2.1 CUDA 2. 2010 169 .4 PTX ISA 1.0 CUDA 2.0. and the remaining sections provide a record of changes in previous releases.3 PTX ISA 1.

1. These are indicated by the use of a rounding modifier and require sm_20.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 for sm_20 targets. and sqrt with IEEE 754 compliant rounding have been added.ftz modifier may be used to enforce backward compatibility with sm_1x.1. sub.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rn.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. while maximizing backward compatibility with legacy PTX 1. Single-precision add.0 11.ftz and . Changes in Version 2.rm and .f32 require a rounding modifier for sm_20 targets.f32 and mad.f32 instruction also supports . Both fma.and double-precision div.1. The fma.f32 for sm_20 targets. 2010 . and mul now support .sat modifiers.f32 maps to fma.f32 requires sm_20.PTX ISA Version 2.1. Floating-Point Extensions This section describes the floating-point changes in PTX 2. A single-precision fused multiply-add (fma) instruction has been added. When code compiled for sm_1x is executed on sm_20 devices.1. The goal is to achieve IEEE 754 compliance wherever possible.f32. Instructions testp and copysign have been added.rp rounding modifiers for sm_20 targets. fma. • • • • • 170 January 24. The mad. The changes from PTX ISA 1. mad.1. The . The mad. rcp.x code and sm_1x targets. New Features 11.0 11. Single.

. e. . Release Notes 11.b32.1. has been added. %clock64.red}. A “population count” instruction. A system-level membar instruction.red}.1.arrive instruction has been added.pred have been added. has been added.1. isspacep. st. st. have been added. Instruction cvta for converting global. ldu. Surface instructions support additional . vote. ldu. The .Chapter 11. Bit field extract and insert instructions.2.3.sys.popc.shared have been extended to handle 64-bit data types for sm_20 targets.red.gt} have been added.clamp and . has been added. A “bit reversal” instruction. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.g. A “find leading non-sign bit” instruction. prefetch. has been added. and red now support generic addressing. and shared addresses to generic address and vice-versa has been added. Video instructions (includes prmt) have been added. for prefetching to specified level of memory hierarchy. has been added. New special registers %nsmid. and sust.maxnctapersm directive was deprecated and replaced with .le. Instructions {atom.ge. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. The bar instruction has been extended as follows: • • • A bar. membar. has been added. clz.lt. brev. 2010 171 . Instructions bar. %lanemask_{eq. Other new features Instructions ld.{and.1. local.clamp modifiers.minnctapersm to better match its behavior and usage.section. bfind. suld. atom. Cache operations have been added to instructions ld.red. Instructions prefetch and prefetchu have also been added. New instructions A “load uniform” instruction.or}. has been added. January 24.ballot.zero. bfe and bfi.u32 and bar. A new directive. Instruction sust now supports formatted surface stores. cvta. popc. A “vote ballot” instruction. bar now supports optional thread count and register operands. Instructions {atom.f32 have been implemented.add. A “count leading zeros” instruction. prefetchu. 11.

red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. the correct number is sixteen.1.s32. 11. 172 January 24.target sm_1x.f32} atom. To maintain compatibility with legacy PTX code. .f32.{min.2.1.{u32. In PTX version 1.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.0 11. 2010 .version is 1.4 and earlier.4 or earlier.3.p.p sust. The underlying.5 and later.red}.ftz for PTX ISA versions 1.ftz (and cvt for . cvt. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. if . Formatted surface load is unimplemented.max} are not implemented. Support for variadic functions and alloca are unimplemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. See individual instruction descriptions for details.f32 type is unimplemented. Semantic Changes and Clarifications The errata in cvt. Formatted surface store with . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. {atom.5. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.s32.u32. stack-based ABI is unimplemented. or .PTX ISA Version 2. call suld. Instruction bra. where . has been fixed.

Descriptions of .func bar (…) { … L1_head: . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. L1_end: … } // do not unroll this loop January 24. The “nounroll” pragma is allowed at module.pragma “nounroll”. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. disables unrolling of0 the loop for which the current block is the loop header. … @p bra L1_end. . L1_body: … L1_continue: bra L1_head. Note that in order to have the desired effect at statement level. Table 145. 2010 173 . disables unrolling for all loops in the entry function body. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma strings defined by ptxas.pragma Strings This section describes the . Supported only for sm_20 targets.pragma.Appendix A. including loops preceding the . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.entry foo (…) .pragma “nounroll”. . entry-function. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. and statement levels. { … } // do not unroll any loop in this function .pragma “nounroll”. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Ignored for sm_1x targets.0.

2010 .PTX ISA Version 2.0 174 January 24.

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