NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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.................. 5.................4................................... 49 ii January 24....................... 5.................................3............ 38 Initializers ........... 42 Arrays as Operands ........5................... 29 Global State Space .5.........................3................................................................................................... 5...............................2.......................................4.............................................. 43 Vectors as Operands ................ 5......................................................... 5.......................... Summary of Constant Expression Evaluation Rules . 42 Addresses as Operands .......4............. 44 Rounding Modifiers .............5....0 4..... 5.......3......................................................................................................... Function declarations and definitions ... and Surface Types ......................................1............................ 30 Shared State Space.. 43 Labels and Function Names as Operands ....................... 25 Chapter 5..... State Spaces ..........................................................................2................3..................4............ 5......... 5............. 5... 28 Constant State Space .....1...4.... Sampler........1............... 33 5...1......................... 5................ 46 6.. 6........2...................................8.....4...................... 41 6............... 6............................. Types....................2.............................. 29 Parameter State Space ......................................... 5.............................................1....................................4............................... Abstracting the ABI .......................................................4........ State Spaces............................... 6.................... 44 Scalar Conversions .......4.................... 29 Local State Space ............................ 6........................2................. 39 Parameterized Variable Names ................................................. 47 Chapter 7..................................................... 38 Alignment .............1................................................................................. 5........ Chapter 6............... Operand Type Information ....2..............................................................PTX ISA Version 2.............................. Operand Costs .................................. 41 Using Addresses............. 37 Variable Declarations .. and Variables .................................................... 5..............................1.... 6.1........................... Types .1...............1............6.............................................4........................................... 32 Texture State Space (deprecated) ..................... Arrays....... 33 Fundamental Types ..........................3.....................4............................................ 34 Variables ....................................... 28 Special Register State Space .................... 5. 5..................................... 43 6...............7... Type Conversion...............................................................1................................... 6............................. Texture...........................2...............................................................................................5....... 6...................................1............................6..............2.......1....1......................................... 6................................................................ 49 7...................6.................................... 27 Register State Space ........................................1..................................4.......................... 33 Restricted Use of Sub-Word Sizes ... 39 5........4............................ 37 Array Declarations .............. and Vectors ..................... 6.................................................. 41 Source Operands................................... 27 5...............................1.................2..5....................... 37 Vectors ........ 41 Destination Operands ......... 32 5............... 2010 .......4....... Instruction Operands............................................................. 5......................................................................................4...............6.................................................................5..................................

...... 8..1.......................................................... 104 Data Movement and Conversion Instructions ... 168 Chapter 11............ 8.... 62 8..........3................................. 53 Alloca ....... 81 Comparison and Selection Instructions .. 8.... 162 Debugging Directives ................7............. Directives ......4. 108 Texture and Surface Instructions ........2.........................2.....6.............................................4....7......... 149 Chapter 10..8..1...................x ...2........... Chapter 9... 10....... 58 8................................ 57 Manipulating Predicates ....................7.............................................9......................... 63 Integer Arithmetic Instructions .......................... 10........ 8........... 129 Parallel Synchronization and Communication Instructions ..................1........................................................ 52 Variadic functions ................ 166 Linking Directives .......................................................................................4..............3.................................1.............1.........................................7..........10.....................................1............ Special Registers ............ 8.............. 160 Performance-Tuning Directives . 7....2.................................... 172 January 24........... 170 Semantic Changes and Clarifications .........7....................................... 62 Semantics .............................................................................1.......... Release Notes ...................... 8...................................................................................................................................7.. 157 10.4............................................. 172 Unimplemented Features Remaining .......... PTX Version and Target Directives .................................................................................1...... 122 Control Flow Instructions ................................7........7........................................................................................ 169 11....................................................... 170 New Features ............7.................................................................. 8......... 8........................................................................................................................ Changes from PTX 1...................................................................................................... Format and Semantics of Instruction Descriptions ............. Instruction Set .................................................................................. 147 8...................... 54 Chapter 8..... 8................ 10.......1... 132 Video Instructions .. 59 Operand Size Exceeding Instruction-Type Size ................................. 10.................... Divergence of Threads in Control Constructs ...........................................7. 8.......................................3............................ 8.............1...................... 157 Specifying Kernel Entry Points and Functions ....................................................7........................... 7................................................................................... 11......5...............6. 8....................................................................7..... 63 Floating-Point Instructions ... Type Information for Instructions and Operands ......1.................................................5.6.................7.....................................3....................1..................3.................. 8..............................................................................2................................................................... 60 8..................................................... 8.........3............... 8...........................................................2......3...................... Instructions .......................... 140 Miscellaneous Instructions....1................................... 11... 8......................... 2010 iii .................... 55 PTX Instructions .... 11...0 ............... 56 Comparisons ........ Changes in Version 2...............6............ 55 Predicated Execution .... 62 Machine-Specific Semantics of 16-bit Code ........................................................ 55 8......... 100 Logic and Shift Instructions ...............

............... Descriptions of ........PTX ISA Version 2..pragma Strings................ 173 iv January 24....0 Appendix A.................. 2010 .....

.. Table 29................................................... Table 10............. Table 16................................................................................................................................................................ Table 4............................................... 65 Integer Arithmetic Instructions: addc ................ Table 31................ 64 Integer Arithmetic Instructions: sub .................................................................. Table 2....... 68 Integer Arithmetic Instructions: mul24 ....................................... Table 32............................................................................... 47 Operators for Signed Integer....................................................................................... 69 Integer Arithmetic Instructions: mad24 ......................................................................................................................... 25 State Spaces .... 19 Predefined Identifiers ..........................cc ...... 64 Integer Arithmetic Instructions: add.................................... Table 13................ Unsigned Integer.......................... Table 12.... 57 Floating-Point Comparison Operators ............................................ Table 19..................... Table 25............... 58 Floating-Point Comparison Operators Testing for NaN ................... Table 23.............................................. and Bit-Size Types ....................................... Table 26........................................ Table 22.......................... 27 Properties of State Spaces ................ 58 Type Checking Rules .................................................. Table 7............. Table 9......... Table 18............................................................................... 46 Integer Rounding Modifiers ............ Table 27................ Table 6......................................................................... 28 Fundamental Type Specifiers .............................. Table 5................... PTX Directives .................. Table 3........................................................ 70 Integer Arithmetic Instructions: sad .... 60 Relaxed Type-checking Rules for Destination Operands..................... 46 Cost Estimates for Accessing State-Spaces .......................................... 33 Opaque Type Fields in Unified Texture Mode ............... 35 Convert Instruction Precision and Format ...... 67 Integer Arithmetic Instructions: mad .cc ....... 66 Integer Arithmetic Instructions: subc ................................... 59 Relaxed Type-checking Rules for Source Operands ..................... Table 8........................... 65 Integer Arithmetic Instructions: sub........ Table 11........... 45 Floating-Point Rounding Modifiers ....... Table 15....................................................................................................... 57 Floating-Point Comparison Operators Accepting NaN ................................................................. Table 28........ Table 30. 18 Reserved Instruction Keywords ............................................................. 20 Operator Precedence .List of Tables Table 1.................. Table 17.................................. 71 January 24............................................... Table 20....................................... 23 Constant Expression Evaluation Rules ........................................ 2010 v ........................................... Table 21................ Table 24................................... 61 Integer Arithmetic Instructions: add ............ Table 14.............................. 35 Opaque Type Fields in Independent Texture Mode .......................................................................................................... 66 Integer Arithmetic Instructions: mul ...

...................................................................... 85 Floating-Point Instructions: mul .......................... 73 Integer Arithmetic Instructions: max ........................ 75 Integer Arithmetic Instructions: brev ........................................... Table 58..................................................................................................... 78 Integer Arithmetic Instructions: prmt .................. 91 Floating-Point Instructions: neg ...................... 88 Floating-Point Instructions: div ................................... Table 62................PTX ISA Version 2.................................... 71 Integer Arithmetic Instructions: rem ................................. 74 Integer Arithmetic Instructions: bfind ........................................................ Table 64....................................... Table 39........... Table 46.. Table 48.................. Table 50....................................... Table 57........................ Table 60........................................................... 77 Integer Arithmetic Instructions: bfi ................................................... 102 Comparison and Selection Instructions: selp ..................................................... 72 Integer Arithmetic Instructions: min ................ Integer Arithmetic Instructions: div ...... Table 44................................................ 96 Floating-Point Instructions: cos ... Table 41................... Table 43..... Table 59.....................................0 Table 33........................ Table 65.......................................... 90 Floating-Point Instructions: abs .................................... Table 40.. Table 69.................................... 92 Floating-Point Instructions: rcp ................... 71 Integer Arithmetic Instructions: abs ........................................................................ 83 Floating-Point Instructions: add ....................................... Table 35........ 72 Integer Arithmetic Instructions: neg .................... 84 Floating-Point Instructions: sub ...................... 83 Floating-Point Instructions: copysign ... 98 Floating-Point Instructions: ex2 ... 2010 ............................................................. 73 Integer Arithmetic Instructions: popc ................................................................. 97 Floating-Point Instructions: lg2 ............................ Table 61................................................................ Table 51........ 94 Floating-Point Instructions: rsqrt ......................... Table 55.......................................... 101 Comparison and Selection Instructions: setp ...................................................... 82 Floating-Point Instructions: testp .................................... Table 36........... Table 47................... 103 Comparison and Selection Instructions: slct ............................. 92 Floating-Point Instructions: max ........................................ 95 Floating-Point Instructions: sin ......................................................... 99 Comparison and Selection Instructions: set ..................................................... Table 66.................... 91 Floating-Point Instructions: min ................................. Table 37........................................... 87 Floating-Point Instructions: mad ........................ 103 vi January 24............................. Table 63............................................. 74 Integer Arithmetic Instructions: clz .............................................. 79 Summary of Floating-Point Instructions ................................................................... 86 Floating-Point Instructions: fma ............ Table 45............................................... Table 49................................................... Table 68......... 93 Floating-Point Instructions: sqrt .................................................................................................... Table 53.......................... Table 34........................................ Table 42..................................................................................... Table 52................................................ 76 Integer Arithmetic Instructions: bfe .................. Table 38.............................................. Table 54...................... Table 56..................................... Table 67........................................................................................................................................

.............................. Table 97................ Table 94. 123 Texture and Surface Instructions: txq .................... Table 77................................ Table 91.................................................... vshr ..................................................................... Table 90................................................................................... vmin............ Table 98..................... Table 106.............. Table 96..................................................... Table 74............ 143 January 24........... Table 78........... Table 85.............................. Table 89................... 119 Data Movement and Conversion Instructions: cvt ......... 116 Data Movement and Conversion Instructions: prefetch....... 106 Logic and Shift Instructions: shl ......................................................................................... 142 Video Instructions: vshl................................................................. 130 Control Flow Instructions: call ..................... Table 105. prefetchu .................................. Table 75.......................................... vsub............................................ 127 Texture and Surface Instructions: suq ........................ Table 93.................. vmax .. 106 Logic and Shift Instructions: not . Table 72.............................. Logic and Shift Instructions: and .... Table 71................................................. Table 86.................... Table 103................................Table 70............... 106 Logic and Shift Instructions: cnot ................................ Table 101.................. 111 Data Movement and Conversion Instructions: mov .................................. 107 Logic and Shift Instructions: shr .................................................. 126 Texture and Surface Instructions: sured.......................... 105 Logic and Shift Instructions: xor ........................................................................................................ Table 104.............................................. Table 79........ 129 Control Flow Instructions: bra ..................... 131 Parallel Synchronization and Communication Instructions: bar .............. 112 Data Movement and Conversion Instructions: ld ...... Table 83... Table 73................... 135 Parallel Synchronization and Communication Instructions: red .......................... 129 Control Flow Instructions: @ .................... 119 Data Movement and Conversion Instructions: cvta ......... 130 Control Flow Instructions: ret .......................... Table 92................ Table 102.. 107 Cache Operators for Memory Load Instructions ....... Table 87................................. Table 82......................... 137 Parallel Synchronization and Communication Instructions: vote .......................................................................... 133 Parallel Synchronization and Communication Instructions: membar ..... 134 Parallel Synchronization and Communication Instructions: atom ................................. 131 Control Flow Instructions: exit ........... Table 99............................................................................... Table 76................................................... 139 Video Instructions: vadd....... 105 Logic and Shift Instructions: or .................................................. 128 Control Flow Instructions: { } ................................................................... 2010 vii .................................................................... Table 100............... 110 Data Movement and Conversion Instructions: mov ................................... 120 Texture and Surface Instructions: tex ............ Table 84........................... 124 Texture and Surface Instructions: suld .............. 115 Data Movement and Conversion Instructions: st ................................. vabsdiff............... 118 Data Movement and Conversion Instructions: isspacep ........ 125 Texture and Surface Instructions: sust ............ Table 81............................... Table 88. 113 Data Movement and Conversion Instructions: ldu ...... Table 95.................... 109 Cache Operators for Memory Store Instructions ......... Table 80........

..........................func ..... Table 112... 157 PTX File Directives: ....................... 153 Special Registers: %lanemask_eq .............. Table 127..................................................version................................... Table 110................................................... 164 Performance-Tuning Directives: .............. Table 137............entry......... Table 139. 161 Performance-Tuning Directives: ................................... Table 140. Table 123................... Table 132................................minnctapersm ................................ Table 141................ Table 119. 147 Miscellaneous Instructions: pmevent.. 152 Special Registers: %smid ................................................................. Table 121.........................0 Table 107.........maxnreg ...............file ..................................................................extern.................................. 164 Performance-Tuning Directives: .... 146 Miscellaneous Instructions: trap ........................... Table 120.. Table 108............................. 168 viii January 24........ Video Instructions: vmad ......................... Table 117........................................... 155 Special Registers: %lanemask_gt ........................................ %pm1............................................... Table 109................................................................................................ Table 122....................................................................................... Table 131............PTX ISA Version 2...................................................................... %pm3 ............................................... 156 Special Registers: %clock64 ................................. 163 Performance-Tuning Directives: ......... Table 114.... Table 118........... Table 115...................... Table 111................................................... 151 Special Registers: %ctaid ......maxntid ................................................................................... 155 Special Registers: %clock ............................loc ................................... 166 Debugging Directives: ........... 167 Debugging Directives: .................................... Table 126......................................................................................... Table 133....... 150 Special Registers: %ntid ........................................................ Table 128............................................... 163 Performance-Tuning Directives: . Table 129..... Table 142...................................target ................................................. 147 Special Registers: %tid ............. 153 Special Registers: %nsmid ............... 151 Special Registers: %nwarpid .... 153 Special Registers: %gridid .................... 152 Special Registers: %nctaid ........................................ Table 124............................ 151 Special Registers: %warpid .. Table 130...... %pm2........... 156 Special Registers: %pm0................ Table 134........................................................ 144 Video Instructions: vset......... Table 116.................................................................. 167 Linking Directives: ..............pragma ...... 147 Miscellaneous Instructions: brkpt ........................................................ 154 Special Registers: %lanemask_lt ........................ Table 143........ Table 138......section ...................................................................................... 158 Kernel and Function Directives: ... 167 Debugging Directives: ........................................................................................... Table 125...................... Table 135................ Table 113..... 154 Special Registers: %lanemask_le ................................................................................. 154 Special Registers: %lanemask_ge ........ Table 136..................................................................................maxnctapersm (deprecated) . 156 PTX File Directives: .......................... 2010 .............. 165 Debugging Directives: @@DWARF ................ 150 Special Registers: %laneid ................................................................................................... 160 Kernel and Function Directives: ........................................

.................................. Linking Directives: ........................ 2010 ix .................... 173 January 24.. 168 Pragma Strings: “nounroll” ..............visible......................................... Table 145.................................Table 144...

2010 .0 x January 24.PTX ISA Version 2.

Because the same program is executed for each data element. Data-parallel processing maps data elements to parallel processing threads. high-definition 3D graphics. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. multithreaded.Chapter 1. In fact. 1. the programmable GPU has evolved into a highly parallel. image and media processing applications such as post-processing of rendered images. and pattern recognition can map image blocks and pixels to parallel processing threads. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Similarly. video encoding and decoding. which are optimized for and translated to native target-architecture instructions. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. PTX defines a virtual machine and ISA for general purpose parallel thread execution. many-core processor with tremendous computational horsepower and very high memory bandwidth. the memory access latency can be hidden with calculations instead of big data caches. and because it is executed on many data elements and has high arithmetic intensity. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. January 24.1. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. PTX exposes the GPU as a data-parallel computing device. image scaling. from general signal processing or physics simulation to computational finance or computational biology. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. stereo vision. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. there is a lower requirement for sophisticated flow control. 1. 2010 1 . a low-level parallel thread execution virtual machine and instruction set architecture (ISA). The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations.2. Introduction This document describes PTX. PTX programs are translated at install time to the target hardware instruction set.

ftz) modifier may be used to enforce backward compatibility with sm_1x. reduction.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. A “flush-to-zero” (. PTX 2.0 is a superset of PTX 1. PTX ISA Version 2. and architecture tests. and mul now support . barrier.rp rounding modifiers for sm_20 targets.f32 maps to fma. and the introduction of many new instructions.f32 and mad. 2010 . A single-precision fused multiply-add (fma) instruction has been added.f32 require a rounding modifier for sm_20 targets. Provide a machine-independent ISA for C/C++ and other compilers to target. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Instructions marked with .f32 instruction also supports . with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 for sm_20 targets. Provide a code distribution ISA for application and middleware developers. When code compiled for sm_1x is executed on sm_20 devices.rn.1. fma. Single-precision add.sat modifiers.0 is in improved support for the IEEE 754 floating-point standard.f32 requires sm_20. surface. The main areas of change in PTX 2.3.3. mad. atomic. • • • 2 January 24. addition of generic addressing to facilitate the use of general-purpose pointers. The mad. memory. Legacy PTX 1.0 PTX ISA Version 2. which map PTX to specific target machines. performance kernels. The fma. Most of the new features require a sm_20 target.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. and video instructions. Facilitate hand-coding of libraries. 1.x features are supported on the new sm_20 target.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.x code will continue to run on sm_1x targets as well. Provide a common source-level ISA for optimizing code generators and translators.PTX ISA Version 2.ftz and . The mad.0 are improved support for IEEE 754 floating-point operations. The changes from PTX ISA 1. Achieve performance in compiled applications comparable to native GPU performance. 1. and all PTX 1.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.rm and . including integer. Improved Floating-Point Support A main area of change in PTX 2.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.x. Both fma. sub.

clamp and .g. and sust.3. NOTE: The current version of PTX does not implement the underlying. Surface Instructions • • Instruction sust now supports formatted surface stores. and shared addresses to generic address and vice-versa has been added. A new cvta instruction has been added to convert global.0. st. i. 2010 3 . rcp. • Taken as a whole. cvta. Generic Addressing Another major change is the addition of generic addressing. instructions ld. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address.e. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. and sqrt with IEEE 754 compliant rounding have been added. 1. PTX 2. Support for an Application Binary Interface Rather than expose details of a particular calling convention. and Application Binary Interface (ABI). and vice versa. January 24. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. These are indicated by the use of a rounding modifier and require sm_20.3.0. e..zero. 1.and double-precision div. Surface instructions support additional clamp modifiers. prefetch. and shared state spaces. 1. and red now support generic addressing. and shared addresses to generic addresses. and directives are introduced in PTX 2. . st. special registers.Chapter 1. suld. local. local. an address that is the same across all threads in a warp.0 closer to full compliance with the IEEE 754 standard. prefetchu. allowing memory instructions to access these spaces without needing to specify the state space.4. Instruction cvta for converting global. local. ldu. Instructions testp and copysign have been added. Instructions prefetch and prefetchu have been added.3.3. isspacep. Generic addressing unifies the global. stack-based ABI. In PTX 2. Cache operations have been added to instructions ld. atom. for prefetching to specified level of memory hierarchy. stack layout. New Instructions The following new instructions. so recursion is not yet supported. these changes bring PTX 2.2. Introduction • Single.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.

popc. bar now supports an optional thread count and register operands.{and. has been added.lt. and Vote Instructions • • • New atomic and reduction instructions {atom.gt} have been added.red}. Instructions {atom. Reduction.shared have been extended to handle 64-bit data types for sm_20 targets. Instructions bar. New special registers %nsmid. A bar. Other Extensions • • • Video instructions (includes prmt) have been added.f32 have been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.b32. 4 January 24. %clock64.add. %lanemask_{eq.section. 2010 .or}. A “vote ballot” instruction. membar. .0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. Barrier Instructions • • A system-level membar instruction. has been added.PTX ISA Version 2.red. A new directive.sys. bfi bit field extract and insert popc clz Atomic.red}.ge.u32 and bar.pred have been added.le.ballot. vote.arrive instruction has been added.red.

Chapter 10 lists the assembly directives supported in PTX. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. calling convention. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 4 describes the basic syntax of the PTX language.Chapter 1. Introduction 1. Chapter 6 describes instruction operands. January 24. Chapter 5 describes state spaces. Chapter 9 lists special registers. and variable declarations. Chapter 11 provides release notes for PTX Version 2. Chapter 8 describes the instruction set. Chapter 7 describes the function and call syntax. 2010 5 . types.0. Chapter 3 gives an overview of the PTX virtual machine model.4.

2010 .0 6 January 24.PTX ISA Version 2.

such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. and ntid.1. or 3D shape specified by a three-element vector ntid (with elements ntid.y. The thread identifier is a three-element vector tid. a portion of an application that is executed many times. and select work to perform. or host: In other words.y. is an array of threads that execute a kernel concurrently or in parallel.2.z).x. 2. Each CTA thread uses its thread identifier to determine its assigned role. A cooperative thread array. It operates as a coprocessor to the main CPU. 2D. Programs use a data parallel decomposition to partition inputs. work. one can specify synchronization points where threads wait until all threads in the CTA have arrived. and results across the threads of the CTA. compute addresses. Each CTA has a 1D. ntid. can be isolated into a kernel function that is executed on the GPU as many different threads. or 3D CTA.z) that specifies the thread’s position within a 1D. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. To that effect. compute-intensive portions of applications running on the host are off-loaded onto the device. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. or CTA. 2D.Chapter 2. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. The vector ntid specifies the number of threads in each CTA dimension. Programming Model 2. and tid. but independently on different data. To coordinate the communication of the threads within the CTA.x. tid. assign specific input and output positions.1. 2010 7 .2. 2. Threads within a CTA can communicate with each other. More precisely. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Each thread has a unique thread identifier within the CTA. data-parallel. January 24. (with elements tid. Cooperative thread arrays (CTAs) implement CUDA thread blocks.

%ctaid. %nctaid. 2. CTAs that execute the same kernel can be batched together into a grid of CTAs. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). Multiple CTAs may execute concurrently and in parallel. or 3D shape specified by the parameter nctaid. multiple-thread) fashion in groups called warps. Some applications may be able to maximize performance with knowledge of the warp size. 2010 . %ntid. read-only special registers %tid. Threads may read and use these values through predefined. a warp has 32 threads. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Each grid also has a unique temporal grid identifier (gridid). or sequentially.0 Threads within a CTA execute in SIMT (single-instruction. 2D . The host issues a succession of kernel invocations to the device. 8 January 24. However. Typically. The warp size is a machine-dependent constant.2.PTX ISA Version 2. Threads within a warp are sequentially numbered. so PTX includes a run-time immediate constant. such that the threads execute the same instructions at the same time. so that the total number of threads that can be launched in a single kernel invocation is very large. This comes at the expense of reduced thread communication and synchronization. and %gridid. which may be used in any instruction where an immediate operand is allowed. depending on the platform. because threads in different CTAs cannot communicate and synchronize with each other. A warp is a maximal subset of threads from a single CTA. Each grid of CTAs has a 1D. WARP_SZ.2.

2) Thread (3. 1) Thread (0. 0) CTA (2. 2) Thread (2. Figure 1. 1) Thread (4. 1) CTA (2. 0) CTA (0. 1) Thread (0. 0) Thread (4.Chapter 2. 2) Thread (1. 0) Thread (3. 2010 9 . 0) CTA (1. 0) Thread (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (4. 1) CTA (1. Thread Batching January 24. 1) Thread (3. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (2. 0) Thread (1. 0) Thread (0. A grid is a set of CTAs that execute independently. 1) Thread (1.

all threads have access to the same global memory. Texture memory also offers different addressing modes. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. The global.3. constant. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2.PTX ISA Version 2. 2010 . for more efficient transfer. and texture memory spaces are optimized for different memory usages. Finally. or. constant.0 2. 10 January 24. for some specific data formats. The global. respectively. Both the host and the device maintain their own local memory. as well as data filtering. Each thread has a private local memory. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. and texture memory spaces are persistent across kernel launches by the same application. The device memory may be mapped and read or written by the host. referred to as host memory and device memory.

1) Block (1. 0) Block (1.Chapter 2. 1) Block (2. 0) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Figure 2. 1) Block (1. 0) Block (2. 1) Grid 1 Global memory Block (0. 2010 11 . 0) Block (0. 0) Block (0. Memory Hierarchy January 24. 2) Block (1. 1) Block (0.

PTX ISA Version 2.0 12 January 24. 2010 .

The threads of a thread block execute concurrently on one multiprocessor. As thread blocks terminate. A warp executes one common instruction at a time. different warps execute independently regardless of whether they are executing common or disjointed code paths. allowing. multiple-thread). a multithreaded instruction unit. the first parallel thread technology. The way a block is split into warps is always the same. and each scalar thread executes independently with its own instruction address and register state. If threads of a warp diverge via a data-dependent conditional branch. and on-chip shared memory. The multiprocessor maps each thread to one scalar processor core. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. a cell in a grid-based computation). and when all paths complete. it splits them into warps that get scheduled by the SIMT unit. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). The multiprocessor SIMT unit creates. manages. so full efficiency is realized when all threads of a warp agree on their execution path. for example. When a multiprocessor is given one or more thread blocks to execute. To manage hundreds of threads running several different programs. Parallel Thread Execution Machine Model 3.Chapter 3.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. January 24.1. a voxel in a volume. 2010 13 . a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and executes threads in groups of parallel threads called warps. It implements a single-instruction barrier synchronization. At every instruction issue time. the warp serially executes each branch path taken. the threads converge back to the same execution path. and executes concurrent threads in hardware with zero scheduling overhead. the multiprocessor employs a new architecture we call SIMT (single-instruction. disabling threads that are not on that path. When a host program invokes a kernel grid. A multiprocessor consists of multiple Scalar Processor (SP) cores. schedules. The multiprocessor creates. increasing thread IDs with the first warp containing thread 0. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. new blocks are launched on the vacated multiprocessors. manages. Branch divergence occurs only within a warp. each warp contains threads of consecutive. (This term originates from weaving.

which is a read-only region of device memory. For the purposes of correctness. the programmer can essentially ignore the SIMT behavior. scalar threads. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. on the other hand. Vector architectures. As illustrated by Figure 3. A multiprocessor can execute as many as eight thread blocks concurrently. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. modify. and writes to the same location in global memory for more than one of the threads of the warp. If there are not enough registers or shared memory available per multiprocessor to process at least one block.PTX ISA Version 2. modifies. If an atomic instruction executed by a warp reads. whereas SIMT instructions specify the execution and branching behavior of a single thread. but one of the writes is guaranteed to succeed. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. however. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering.0 SIMT architecture is akin to SIMD (Single Instruction. A key difference is that SIMD vector organizations expose the SIMD width to the software. each read. 14 January 24. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. write to that location occurs and they are all serialized. 2010 . require the software to coalesce loads into vectors and manage divergence manually. which is a read-only region of device memory. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. the kernel will fail to launch. • The local and global memory spaces are read-write regions of device memory and are not cached. SIMT enables programmers to write thread-level parallel code for independent. In practice. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. but the order in which they occur is undefined. the number of serialized writes that occur to that location and the order in which they occur is undefined. In contrast with SIMD vector machines. as well as data-parallel code for coordinated threads.

Figure 3. 2010 15 .Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.

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Lines beginning with # are preprocessor directives. Pseudo-operations specify symbol and addressing management.2. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.1. Lines are separated by the newline character (‘\n’). Comments in PTX are treated as whitespace. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. The following are common preprocessor directives: #include. The C preprocessor cpp may be used to process PTX source files. 4. January 24. All whitespace characters are equivalent. Comments Comments in PTX follow C/C++ syntax. using non-nested /* and */ for comments that may span multiple lines. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Syntax PTX programs are a collection of text source files. PTX is case sensitive and uses lowercase for keywords. Source Format Source files are ASCII text.Chapter 4. 4. 2010 17 . See Section 9 for a more information on these directives. #else. whitespace is ignored except for its use in separating tokens in the language.target directive specifying the target architecture assumed. #ifdef. #line. followed by a . #define. and using // to begin a comment that extends to the end of the current line. #endif.version directive specifying the PTX language version. Each PTX file must begin with a . #if.

f32 array[N].extern . %tid.pragma .x.sreg .reg .file PTX Directives . address expressions.global . and terminated with a semicolon.loc . array[r1].1. The guard predicate may be optionally negated.const .0 4.shared . Examples: .align . Operands may be register variables. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. mov. written as @!p.version . shl. Instructions have an optional guard predicate which controls conditional execution. followed by source operands.target . Directive Statements Directive keywords begin with a dot. Statements A PTX statement is either a directive or an instruction.global.b32 r1.visible 4. r1.local . r2. The destination operand is first.b32 r1.entry . Instruction keywords are listed in Table 2.func .2. All instruction keywords are reserved tokens in PTX.maxnctapersm .3.3. The guard predicate follows the optional label and precedes the opcode. 18 January 24. where p is a predicate register. . 2010 .minnctapersm .section . r2. so no conflict is possible with user-defined identifiers.tex . .param . constant expressions. and is written as @p. 2.maxntid .3. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.f32 r2.global start: . Table 1.5. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.reg .b32 r1. r2. 0. or label names.maxnreg . ld.PTX ISA Version 2.b32 add. Statements begin with an optional label and end with a semicolon.

2010 19 . Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.Chapter 4.

Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. digits. or percentage character followed by one or more letters. or dollar characters.PTX ISA Version 2. underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. %pm3 WARP_SZ 20 January 24. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. listed in Table 3. 2010 . dollar. except that the percentage sign is not allowed. Many high-level languages such as C and C++ follow similar rules for identifier names. …. digits. e. between user-defined variable names and compiler-generated names. PTX allows the percentage sign as the first character of an identifier. The percentage sign can be used to avoid name conflicts. PTX predefines one constant and a small number of special registers that begin with the percentage sign.0 4. underscore. or they start with an underscore.4.g. Table 3.

octal. Integer literals may be written in decimal. Type checking rules remain the same for integer. 2010 21 . Syntax 4.. zero values are FALSE and non-zero values are TRUE. Constants PTX supports integer and floating-point constants and constant expressions. For predicate-type data and instructions. To specify IEEE 754 doubleprecision floating point values.e. where the behavior of the operation depends on the operand types. the constant begins with 0d or 0D followed by 16 hex digits. 4. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.u64). there is no suffix letter to specify size. These constants may be used in data initialization and as operands to instructions.s64) unless the value cannot be fully represented in . To specify IEEE 754 single-precision floating point values. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. i. or binary notation.5.5. literals are always represented in 64-bit double-precision format. 4.2. in which case the literal is unsigned (. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic.. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. the sm_1x and sm_20 targets have a WARP_SZ value of 32. floating-point. i. each integer constant is converted to the appropriate size based on the data or instruction type at its use. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. integer constants are allowed and are interpreted as in C. hexadecimal. When used in an instruction or data initialization. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. The syntax follows that of C.5.s64 or .s64 or the unsigned suffix is specified. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. and bit-size types. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.u64.e.Chapter 4.1. every integer constant has type . The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Unlike C and C++. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Floating-point literals may be written with an optional decimal point and an optional signed exponent. the constant begins with 0f or 0F followed by 8 hex digits.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

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u64 .f64 use usual conversions . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 same as 1st operand .u64 . 2nd is .s64 . Syntax 4.s64) + .6.f64 integer integer integer integer integer int ?. Table 5.Chapter 4.f64 converted type constant literal + ! ~ Cast Binary (.u64 1st unchanged.u64 .s64.u64 . 2010 25 .s64 .f64 use usual conversions .u64 .s64 .f64 use usual conversions .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 converted type .f64 integer .s64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .5.s64 .f64 integer .u64 .s64 .u64.f64 : .u64) (.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 .s64 .f64 same as source . . or .

0 26 January 24. 2010 .PTX ISA Version 2.

and level of sharing between threads. Kernel parameters. The characteristics of a state space include its size. 5. addressability.tex January 24.reg . State Spaces. Global memory. Local memory.param . and Variables While the specific resources available in a given target GPU will vary. Addressable memory shared between threads in 1 CTA. Name State Spaces Description Registers. Global texture memory (deprecated). Table 6. State Spaces A state space is a storage area with particular characteristics.1. access speed. Special registers. fast. shared by all threads. private to each thread. The list of state spaces is shown in Table 4. Types. defined per-thread. read-only memory. the kinds of resources will be common across platforms. Shared.const . and properties of state spaces are shown in Table 5. pre-defined. defined per-grid. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. platform-specific. or Function or local parameters. 2010 27 . All variables reside in some state space. and these resources are abstracted in PTX through state spaces and data types.sreg .Chapter 5.shared .global . . access rights. Read-only.local .

causing changes in performance..PTX ISA Version 2. or 64-bits.param instructions. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). 1 Accessible only via the ld. it is not possible to refer to the address of a register. CTA. Special Register State Space The special register (.const . and vector registers have a width of 16-. such as grid.local . All special registers are predefined. Address may be taken via mov instruction.sreg) state space holds predefined. Registers may have alignment boundaries required by multi-word loads and stores.shared . 28 January 24. register variables will be spilled to memory.global . floating point. 5.sreg . and performance monitoring registers. clock counters. For each architecture. predicate) or untyped. Device function input parameters may have their address taken via mov. and thread parameters. Registers differ from the other state spaces in that they are not fully addressable. st. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. The most common use of 8-bit registers is with ld.param (as input to kernel) .param (used in functions) . or 128-bits. platform-specific registers. 64-. scalar registers have a width of 8-. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .reg state space) are fast storage locations.1. 2 Accessible via ld. 32-. When the limit is exceeded.0 Table 7.reg .e.1. The number of registers is limited.2. 32-. aside from predicate registers which are 1-bit.param and st. and will vary from platform to platform.tex Restricted Yes No3 5. 16-. 3 Accessible only via the tex instruction.1. or as elements of vector tuples. Registers may be typed (signed integer.local state space. the parameter is then located on the stack frame and its address is in the . unsigned integer.param instruction. Register State Space Registers (. 2010 . and cvt instructions. i. Register size is restricted.

as in lock-free and wait-free style programming. The remaining banks may be used to implement “incomplete” constant arrays (in C.sync instruction.global. Threads must be able to do their work without waiting for other threads to do theirs.4. the bank number must be provided in the state space of the load instruction. Use ld.b32 const_buffer[]. the store operation updating a may still be in flight. b = b – 1.Chapter 5. bank zero is used. To access data in contant banks 1 through 10.const[2] .global to access global variables. all addresses are in global memory are shared. For any thread in a context.global) state space is memory that is accessible by all threads in a context.extern . // load second word 5. Multiple incomplete array variables declared in the same bank become aliases. results in const_buffer pointing to the start of constant bank two. Sequential consistency is provided by the bar. each pointing to the start address of the specified constant bank. for example). Types. there are eleven 64KB banks. Constant State Space The constant (. This pointer can then be used to access the entire 64KB constant bank. 5. Threads wait at the barrier until all threads in the CTA have arrived.1.const[bank] modifier. The constant memory is organized into fixed size banks. If no bank number is given. Module-scoped local memory variables are stored at fixed addresses. where the size is not known at compile time.1. Global memory is not sequentially consistent.b32 %r1. Global State Space The global (. The size is limited. It is typically standard memory with cache. If another thread sees the variable b change.3. and atom. [const_buffer+4]. For example. Consider the case where one thread executes the following two assignments: a = a + 1. All memory writes prior to the bar. For example. where bank ranges from 0 to 10.extern . as it must be allocated on a perthread basis. ld. an incomplete array in bank 2 is accessed as follows: .const[2]. For the current devices.sync instruction are guaranteed to be visible to any reads after the barrier instruction. st. Local State Space The local state space (. whereas local memory variables declared January 24. 2010 29 . bank zero is used for all statically-sized constant variables. the declaration . Use ld.local and st.local) is private memory for each thread to keep its own data.const[2] . Banks are specified using the .1.5. This reiterates the kind of parallelism available in machines that run PTX. State Spaces. the stack is in local memory. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.global. In implementations that support a stack.b32 const_buffer[].local to access local variables. initialized by the host. and Variables 5. By convention. It is the mechanism by which different CTAs and different grids can communicate.const) state space is a read-only memory.

u32 %n.reg .0 and requires target architecture sm_20.param space variables. per-kernel versus per-thread). Therefore.6.param state space and is accessed using ld. . device function parameters were previously restricted to the register state space.b32 N.6.reg . Note that PTX ISA versions 1. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. The address of a kernel parameter may be moved into a register using the mov instruction. … 30 January 24. [N].u32 %ptr. No access protection is provided between parameter and global space in this case. len.f64 %d. The resulting address is in the . 2010 .PTX ISA Version 2.entry foo ( .param state space.1. (2a) to declare formal input and return parameters for device functions called from within kernel execution. The use of parameter state space for device function parameters is new to PTX ISA version 2.param .b8 buffer[64] ) { . These parameters are addressable. In implementations that do not support a stack.reg . Parameter State Space The parameter (.x supports only kernel function parameters in .param) state space is used (1) to pass input arguments from the host to the kernel.u32 %n. ld.param instructions. in some implementations kernel parameters reside in global memory. ld.param space.param .0 within a function or kernel body are allocated on the stack. all local memory variables are stored at fixed addresses and recursive function calls are not supported. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). … Example: .u32 %ptr. The kernel parameter variables are shared across all CTAs within a grid. Example: .param. [buffer].align 8 .b32 len ) { . [%ptr].1. PTX code should make no assumptions about the relative locations or ordering of .param instructions. .1.param . Similarly. %n. For example. Note: The location of parameter space is implementation specific. Values passed from the host to the kernel are accessed through these parameter variables using ld.param.param. typically for passing large structures by value to a function.f64 %d. 5. read-only variables declared in the . mov.entry bar ( . ld. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. 5.u32 %n. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.

a byte array in parameter space is used.reg . .Chapter 5.f64 dbl. is flattened.local state space and is accessed via ld.param. [buffer]. passed to foo … . … } // code snippet from the caller // struct { double d. and so the address will be in the . January 24. int y. Types. Note that the parameter will be copied to the stack if necessary. … See the section on function call syntax for more details. (4. State Spaces.local and st.align 8 .s32 x. [buffer+8]. Typically. . .param and function return parameters may be written using st.f64 %d.align 8 . it is illegal to write to an input parameter or read from a return parameter. .param space variable.s32 [mystruct+8].2.param space is also required whenever a formal parameter has its address taken within the called function. In this case. which declares a . }. the address of a function input parameter may be moved into a register using the mov instruction. the caller will declare a locally-scoped . } mystruct. The most common use is for passing objects by value that do not fit within a PTX register. . x. and Variables 5.reg . such as C structures larger than 8 bytes. int y. Aside from passing structures by value. ld.param . This will be passed by value to a callee.param.s32 %y.reg . Function input parameters may be read via ld.param formal parameter having the same size and alignment as the passed argument. 2010 31 .param.0 extends the use of parameter space to device function parameters.6.param . Device Function Parameters PTX ISA version 2. ld.b8 mystruct.f64 [mystruct+0]. .s32 %y.reg .b8 buffer[12] ) { . … st.reg . It is not possible to use mov to get the address of a return parameter or a locally-scoped .param.func foo ( . In PTX.param byte array variable that represents a flattened C structure or union. call foo.param.local instructions. st.1.f64 %d.b32 N. Example: // pass object of type struct { double d. mystruct). dbl.

Shared State Space The shared (. and programs should instead reference texture memory through variables of type . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 tex_a.1. Another is sequential access from sequential threads. An address in shared memory can be read and written by any thread in a CTA. It is shared by all threads in a context. For example. 2010 .texref type and Section 8. Physical texture resources are allocated on a per-module granularity.global .8.global state space.tex directive is retained for backward compatibility.texref tex_a. A texture’s base address is assumed to be aligned to a 16-byte boundary. and .tex) state space is global memory accessed via the texture instruction.u64. and variables declared in the .7. See Section 5. is equivalent to . An error is generated if the maximum number of physical resources is exceeded.6 for its use in texture instructions. tex_c.1.3 for the description of the . The . a legacy PTX definitions such as .u32 . tex_d. where all threads read from the same address. Multiple names may be bound to the same physical texture identifier. tex_d. tex_f.shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex variables are required to be defined in the global scope.tex .7.u32 or .tex state space are equivalent to module-scoped . Shared memory typically has some optimizations to support the sharing. where texture identifiers are allocated sequentially beginning with zero. The . The texture name must be of type .tex . Texture State Space (deprecated) The texture (.PTX ISA Version 2.0 5. 32 January 24. Example: .texref variables in the . Texture memory is read-only.texref.u32 . One example is broadcast.tex . 5.shared and st.u32 . Use ld.shared to access shared variables.tex . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.tex directive will bind the named texture memory variable to a hardware texture identifier.u32 tex_a.tex .

f32 and . or converted to other types and sizes. . 2010 33 . For convenience. Operand types and sizes are checked against instruction types for compatibility. st. Two fundamental types are compatible if they have the same basic type and are the same size. st. 5. so their names are intentionally short. January 24. .b8. .f64 types.u8.s16. . stored. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.b32.b16.u16. Restricted Use of Sub-Word Sizes The .u8.s8. Register variables are always of a fundamental type.f64 . . and instructions operate on these types. but typed variables enhance program readability and allow for better operand type checking.s8.pred Most instructions have one or more type specifiers. . and cvt instructions. . needed to fully specify instruction behavior.2.u64 . State Spaces. A fundamental type specifies both a basic type and a size. The . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. stored. and .2. .1.f64 types. .f32. The bitsize type is compatible with any fundamental type having the same size.b64 . Types 5.2. For example. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .b8 instruction types are restricted to ld. Signed and unsigned integer types are compatible if they have the same size.f16.Chapter 5. so that narrow values may be loaded. and Variables 5. The following table lists the fundamental type specifiers for each basic type: Table 8.f32 and .s64 . Fundamental Types In PTX.s32. . the fundamental types reflect the native data types supported by the target architectures.f16 floating-point type is allowed only in conversions to and from . All floating-point instructions operate only on . Types. .2. In principle. all variables (aside from predicates) could be declared using only bit-size types. The same typesize specifiers are used for both variable definitions and for typing instructions. . ld. and converted using regular-width registers.u32.

Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. samplers. Referencing textures. base address. and overall size is hidden to a PTX program.{u32.e. These types have named fields similar to structures.3. .0 5. field ordering. The three built-in types are .texref. and query instructions. In the independent mode. In independent mode the fields of the . Retrieving the value of a named member via query instructions (txq.texref handle. 2010 . and de-referenced by texture and surface load.texref type that describe sampler properties are ignored. 34 January 24. store.u64} reg. opaque_var. accessing the pointer with ld and st instructions..PTX ISA Version 2. since these properties are defined by . hence the term “opaque”. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. suq).surfref. the resulting pointer may be stored to and loaded from memory. The following tables list the named members of each type for unified and independent texture modes. passed as a parameter to functions. sust. texture and sampler information is accessed through a single . Creating pointers to opaque variables using mov. suld. i. or surfaces via texture and surface load/store instructions (tex. and . In the unified mode. and Surface Types PTX includes built-in “opaque” types for defining texture. and surface descriptor variables. texture and sampler information each have their own handle. Texture. For working with textures and samplers. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. or performing pointer arithmetic will result in undefined results. sured).samplerref. allowing them to be defined separately and combined at the site of usage in the program.samplerref variables. Sampler. sampler. PTX has two modes of operation. but the pointer cannot otherwise be treated as an address. but all information about layout.

clamp_ogl. and Variables Table 9. 1 ignored ignored ignored ignored .samplerref values N/A N/A N/A N/A nearest. linear wrap. clamp_ogl.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. mirror. mirror. clamp_to_border N/A N/A N/A N/A N/A . clamp_to_edge. Types.texref values in elements in elements in elements 0. 2010 35 .texref values . State Spaces. Member width height depth Opaque Type Fields in Independent Texture Mode .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_edge. 1 nearest. linear wrap. Member width height depth Opaque Type Fields in Unified Texture Mode .Chapter 5. clamp_to_border 0.

As kernel parameters. .param state space. 36 January 24. Example: .global state space.global .global . 2010 .PTX ISA Version 2. When declared at module scope. filter_mode = nearest }. .samplerref my_sampler_name.texref tex1.global . these variables must be in the .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. the types may be initialized using a list of static expressions assigning values to the named members.global . these variables are declared in the .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. . At module scope.surfref my_surface_name.global . Example: .texref my_texture_name.

u32 loc.Chapter 5. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. // typedef . Examples: . .global . // a length-2 vector of unsigned ints .v2. vector variables are aligned to a multiple of their overall size (vector length times base-type size). r. State Spaces. In addition to fundamental types. Types.0. Vectors Limited-length vector types are supported. where the fourth element provides padding.global .v4. .1.v4 .4. Every variable must reside in one of the state spaces enumerated in the previous section. 5. and Variables 5. PTX supports types for simple aggregate objects such as vectors and arrays. its name. for example.s32 i.v1. Variables In PTX. .2. This is a common case for three-dimensional grids.global .0}. .u16 uv. Predicate variables may only be declared in the register state space.4.v4 vector.f32 V. Variable Declarations All storage for data is specified with variable declarations. Three-element vectors may be handled by using a . textures.b8 v. .pred p.v4.reg . .shared .global .reg . 2010 37 .f32 accel.v3 }. a variable declaration describes both the variable’s type and its state space. 0. 1.v2 . an optional initializer. Vectors cannot exceed 128-bits in length.v4 . January 24. .4. 5. and an optional fixed address for the variable. an optional array size. 0. // a length-4 vector of bytes By default.const . its type and size.reg .v4 . A variable declaration names the space in which the variable resides.f32 v0.v2 or . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . Vectors must be based on a fundamental type.f64 is not allowed. Examples: . 0}.struct float4 coord. // a length-4 vector of floats .struct float4 { .global .u8 bg[4] = {0. etc. and they may reside in the register space.f32 bias[] = {-1. q.

local . Initializers Declared variables may specify an initial value using a syntax similar to C/C++..PTX ISA Version 2. 1} }. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). {0.05. ..s32 offset[][] = { {-1.. {0.0}}. or is left empty.4. Similarly.4..1.05}}. .global . Here are some examples: . 0}.4.1.u8 mailbox[128].0. Examples: .global .f16 and .u32 or .0}.b32 ptr = rgba.global .1. 2010 .f32 blur_kernel[][] = {{.global . label names appearing in initializers represent the address of the next instruction following the label. {1. .{. Initializers are allowed for all types except . For the kernel declaration above.1.v4 . this can be used to initialize a jump table to be used with indirect branches or calls.4.u64. {0. -1}.3. {0.u16 kernel[19][19].0 5.u8 rgba[3] = {{1.0. Variables that hold addresses of variables or instructions should be of type .05}. being determined by an array initializer. 0}. Array Declarations Array declarations are provided to allow the programmer to reserve space.shared .05. 5.1.0.s32 n = 10. this can be used to statically initialize a pointer to a variable.pred. A scalar takes a single value. 38 January 24.. where the variable name is followed by an equals sign and the initial value or values for the variable.0.global . .{. .1}. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. Variable names appearing in initializers represent the address of the variable. The size of the dimension is either a constant expression. 19*19 (361) halfwords are reserved (722 bytes). The size of the array specifies how many elements should be reserved.0}. variable initialization is supported only for constant and global state spaces. To declare an array. // address of rgba into ptr Currently..

nor are initializers permitted.2. For arrays. The default alignment for vector variables is to a multiple of the overall vector size.5. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. State Spaces. . it is quite common for a compiler frontend to generate a large number of register names.b32 variables.6. Parameterized Variable Names Since PTX supports virtual registers.4. Examples: // allocate array at 4-byte aligned address.0.align byte-count specifier immediately following the state-space specifier.. The default alignment for scalar and array variables is to a multiple of the base-type size. …. %r1.0.b8 bar[8] = {0.0. . alignment specifies the address alignment for the starting address of the entire array... %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. Alignment is specified using an optional . January 24. and may be preceded by an alignment specifier.b32 %r<100>. suppose a program uses a large number. named %r0. // declare %r0.align 4 . The variable will be aligned to an address which is an integer multiple of byte-count. Elements are bytes. For example.const . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. These 100 register variables can be declared as follows: . of . Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. 5.0. say one hundred. %r1.0. Types. %r99. Rather than require explicit declaration of every name. and Variables 5.reg . Array variables cannot be declared this way.0}. not for individual elements.4.Chapter 5. 2010 39 .

PTX ISA Version 2. 2010 .0 40 January 24.

Chapter 6. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. st. Integer types of a common size are compatible with each other. The mov instruction copies data between registers. Instructions ld and st move data from/to addressable state spaces to/from registers. The cvt (convert) instruction takes a variety of operand types and sizes. and c. The bit-size type is compatible with every type having the same size. .3. For most operations. 2010 41 . Instruction Operands 6. 6. as its job is to convert from nearly any data type to any other data type (and size). the sizes of the operands must be consistent. s. 6. so operands for ALU instructions must all be in variables declared in the .2. PTX describes a load-store machine. Predicate operands are denoted by the names p. There is no automatic conversion between types. The result operand is a scalar or vector variable in the register state space. Each operand type must be compatible with the type determined by the instruction template and instruction type. r. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. January 24. b. Most instructions have an optional predicate guard that controls conditional execution. Source Operands The source operands are denoted in the instruction descriptions by the names a.reg register state space.1. Operand Type Information All operands in instructions have a known type from their declarations. q. and a few instructions have additional predicate source operands. and cvt instructions copy data from one location to another. mov. The ld.

and vectors. r0.4. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. there is no support for C-style pointer arithmetic. ld. Examples include pointer arithmetic and pointer comparisons.f32 W. Load and store operations move data between registers and locations in addressable state spaces.v4. [tbl+12]. Here are a few examples: . and immediate address expressions which evaluate at compile-time to a constant address. 6.gloal. tbl. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. . .u16 x. p.reg . arrays.b32 p.shared.reg .shared . 2010 . Using Addresses. .const. The interesting capabilities begin with addresses.f32 V.[x]. The address is an offset in the state space in which the variable is declared. address register plus byte offset. [V].reg .f32 ld. The mov instruction can be used to move the address of a variable into a pointer.4. . . All addresses and address computations are byte-based.reg . and Vectors Using scalar variables as operands is straightforward.v4 .const .u16 r0.v4 . W.u16 ld. The syntax is similar to that used in many assembly languages.1. Arrays. q.global .0 6.s32 q. address registers.s32 tbl[256].PTX ISA Version 2. Address expressions include variable names.s32 mov.u32 42 January 24. .

.u32 {a. Array elements can be accessed using an explicitly calculated byte address. where the offset is a constant expression that is either added or subtracted from a register variable.u32 s.3. and the identifier becomes an address constant in the space where the array is declared.g.b and .reg .global.global.Chapter 6. The size of the array is a constant in the program. which may improve memory performance.d}. st. . Rd}.x. mov.z V. it must be written as an address calculation prior to use. or a braceenclosed list of similarly typed scalars. Instruction Operands 6.u32 s.w. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.r. [addr+offset]. Vector elements can be extracted from the vector with the suffixes . for use in an indirect branch or call. and tex.a 6. V.f32 a.v4.4. a register variable. The registers in the load/store operations can be a vector. Rc.4.y V. Elements in a brace-enclosed vector.global.a. January 24.f32 V. d. Vectors may also be passed as arguments to called functions.c. b.w = = = = V. The expression within square brackets is either a constant integer. Vectors as Operands Vector operands are supported by a limited subset of instructions.v4 .u32 s. .z and . . or a simple “register with constant offset” expression. If more complicated indexing is desired. // move address of a[1] into s 6. a[0]. ld. Arrays as Operands Arrays of all types can be declared.y. a[1]. Vector loads and stores can be used to implement wide loads and stores. Rb. mov.2.r V.x V.c. and in move instructions to get the address of the label or function into a register. which include mov. A brace-enclosed list is used for pattern matching to pull apart vectors.b.g V.d}.b. Here are examples: ld.v2. a[N-1].4. say {Ra.global.4.reg . V2.b V. c.v4. ld. or by indexing into the array using square-bracket notation. Examples are ld. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. as well as the typical color fields .f32 ld. . 2010 43 .f32 {a. [addr+offset2]. .

5. and ~131.u16 instruction is given a u16 source operand and s32 as a destination operand. For example. Operands of different sizes or types must be converted prior to the operation. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.s32. 2010 .0 6.1. logic. except for operations where changing the size and/or type is part of the definition of the instruction. and data movement instruction must be of the same type and size. 6. the u16 is zero-extended to s32. if a cvt.5.000 for f16). Type Conversion All operands to all arithmetic. 44 January 24. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.PTX ISA Version 2.

The type of extension (sign or zero) is based on the destination format.u32 targeting a 32-bit register will first chop to 16-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. the result is extended to the destination register width after chopping. For example. Notes 1 If the destination register is wider than the destination format. chop = keep only low bits that fit. 2010 45 . u2f = unsigned-to-float. cvt.Chapter 6. zext = zero-extend. s2f = signed-to-float. then sign-extend to 32-bits. January 24. f2u = float-to-unsigned.s16. f2s = float-to-signed. Instruction Operands Table 11. f2f = float-to-float.

rm . 2010 .PTX ISA Version 2.rpi Integer Rounding Modifiers Description round to nearest integer.0 6.rzi . The following tables summarize the rounding modifiers.2.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.5. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. Modifier . Rounding Modifiers Conversion instructions may specify a rounding modifier. Table 12.rni . there are four integer rounding modifiers and four floating-point rounding modifiers.rz .rmi . Modifier .rn . In PTX. choosing even integer if source is equidistant between two integers.

as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The register in a store operation is available much more quickly. Operand Costs Operands from different state spaces affect the speed of an operation.6. Table 14. Registers are fastest. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. first access is high Notes January 24. Another way to hide latency is to issue the load instructions as early as possible.Chapter 6. while global memory is slowest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Instruction Operands 6. Much of the delay to memory can be hidden in a number of ways. 2010 47 . Table 11 gives estimates of the costs of using different kinds of memory.

PTX ISA Version 2.0 48 January 24. 2010 .

the function name. … Here. or prototype. support for variadic functions (“varargs”). In this section. parameter passing. Scalar and vector base-type input and return parameters may be represented simply as register variables. arguments may be register variables or constants.func directive. Abstracting the ABI Rather than expose details of a particular calling convention. These include syntax for function definitions. A function definition specifies both the interface and the body of the function. so recursion is not yet supported. The simplest function has no parameters or return values. stack-based ABI. and memory allocated on the stack (“alloca”). together these specify the function’s interface. function calls.Chapter 7. 7. and an optional list of input parameters. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. NOTE: The current version of PTX does not implement the underlying.func foo { … ret. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. and return values may be placed directly into register variables. } … call foo. At the call. functions are declared and defined using the . January 24. stack layout. we describe the features of PTX needed to achieve this hiding of the ABI. and Application Binary Interface (ABI).1. execution of the call instruction transfers control to foo. 2010 49 . A function declaration specifies an optional list of return parameters. A function must be declared or defined prior to being called. and is represented in PTX as follows: . implicitly saving the return address. Execution of the ret instruction within foo transfers control to the instruction following the call. Function declarations and definitions In PTX.

align 8 y[12]) { . … … // computation using x.b8 [py+ 9]. %rc2. c2.b64 [py+ 0].align 8 py[12].c2. char c[4]. ld.reg . %ptr.param.param.u32 %res. %rd.f64 f1.c3. . bumpptr. st.b8 .reg .param .b8 [py+ 8].b8 [py+11]. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . } … call (%r1). ret.f1. … In this example. c3.f64 field are aligned. consider the following C structure.s32 x.param.reg . %inc.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 c3.param space call (%out).param.reg . [y+10]. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .f64 f1. a . … st.param.func (.reg . byte array in . [y+9]. c4. note that .param . For example. ld.param state space is used to pass the structure by value: . ld. 2010 .param space variables are used in two ways. (%x.reg . (%r1.param. %rc2. st.4). py). .func (. %rc1. Since memory accesses are required to be aligned to a multiple of the access size. a .b8 c2. ld. inc_ptr. st. this structure will be flattened into a byte array. [y+0].reg .u32 %ptr.0 Example: . The .param.param. %rc1.b8 c1. } { . // scalar args in . passed by value to a function: struct { double dbl. First.s32 out) bar (. … ld.c4.u32 %inc ) { add.param. 50 January 24.u32 %res) inc_ptr ( . st.b32 c1.b8 . }.b8 c4. Second.PTX ISA Version 2.param space memory.param variable y is used in function definition bar to represent a formal parameter. .param.c1.reg space. [y+11]. [y+8].b8 [py+10]. In PTX.

For a caller.param space byte array with matching type. a .reg state space in this way provides legacy support. the corresponding argument may be either a . size. Parameters in . • • • For a callee. In the case of .param state space use in device functions..reg or . In the case of .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. all st.param space formal parameters that are base-type scalar or vector variables. In the case of .g. and alignment of parameters. • The . A .reg space variable with matching type and size. • The . • • • Input and return parameters may be . size.reg state space can be used to receive and return base-type scalar and vector values.param byte array is used to collect together fields of a structure being passed by value. or constants. 4.reg space variable of matching type and size.param arguments. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. Typically. 2010 51 . Abstracting the ABI The following is a conceptual way to think about the . The . For .param or . the argument must also be a .param argument must be declared within the local scope of the caller. or 16 bytes. Supporting the .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. January 24. This enables backend optimization and ensures that the . 2.param and ld.reg variables.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param or . and alignment. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.param variables or . For a caller.param space formal parameters that are byte arrays. or a constant that can be represented in the type of the formal parameter.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. 8. The following restrictions apply to parameter passing.reg variables. For a callee. • • Arguments may be . or a constant that can be represented in the type of the formal parameter.param memory must be aligned to a multiple of 1.param instructions used for argument passing must be contained in the basic block with the call instruction.param variables.param state space is used to receive parameter values and/or pass return values back to the caller. the corresponding argument may be either a . . The .reg space formal parameters. Note that the choice of .Chapter 7.

x.0 7. For sm_2x targets. and a .param space parameters support arrays. formal parameters may be in either . and there was no support for array parameters. Objects such as C structures were flattened and passed or returned using multiple registers.1. Changes from PTX 1.reg or .0. 52 January 24.x supports multiple return values for this purpose. and .PTX ISA Version 2. PTX 2. In PTX ISA version 2.reg state space. PTX 2.x In PTX ISA version 1.0 continues to support multiple return registers for sm_1x targets.0 restricts functions to a single return value.param byte array should be used to return objects that do not fit into a register.param state space. formal parameters were restricted to .1. PTX 1. 2010 .

u32.reg . Once all arguments have been processed. // default to MININT mov. setp. To support functions with a variable number of arguments. … call (%max). 2.. . (ap). (2.2.reg .h and varargs. .reg . and end access to a list of variable arguments. . variadic functions are declared with an ellipsis at the end of the input parameter list.pred p. mov. for %va_arg64.u32 a.u32 sz. … %va_start returns Loop: @p Done: January 24.u32 align) . %r2. . PTX provides a high-level mechanism similar to the one provided by the stdarg.reg . call %va_end. 0x8000000.reg .u32 N. %s2). . 4.b64 val) %va_arg64 (. This handle is then passed to the %va_arg and %va_arg64 built-in functions. bra Loop. val.u32 ptr) %va_start . … ) . the size may be 1.reg .u32 sz.u32 ptr.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . call (ap). Variadic functions NOTE: The current version of PTX does not support variadic functions.s32 val.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. %r3).u32 ap. N. result. In both cases. ctr. . 4.ge p. max. maxN.func (.b32 result. . (ap.reg .func okay ( … ) Built-in functions are provided to initialize. Abstracting the ABI 7.reg .u32 align) . following zero or more fixed parameters: .Chapter 7.func (.s32 result ) maxN ( . 0. call (val). 4).reg .s32 result. %va_arg.h headers in C.. along with the size and alignment of the next data value to be accessed.b32 ctr. } … call (%max). .u32 ptr. In PTX. or 8 bytes. ctr. %va_end is called to free the variable argument list handle. (3.reg . For %va_arg.func %va_end (.reg . %va_start.u32 b. the alignment may be 1.b32 val) %va_arg (.reg .func (.reg .reg . maxN. bra Done. The function prototypes are defined as follows: .func baz ( . or 4 bytes.func ( . ret. 2. %s1. 2010 53 . the size may be 1. or 16 bytes. 4.reg . %r1.reg . 8. ) { . iteratively access. 2.

it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. 54 January 24.u32 ptr ) %alloca ( .reg .0 7.reg .3. a function simply calls the built-in function %alloca. Alloca NOTE: The current version of PTX does not support alloca.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. 2010 .func ( .local instructions. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. The array is then accessed with ld. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. defined as follows: . If a particular alignment is required. To allocate memory.local and st.PTX ISA Version 2.

a. We use a ‘|’ symbol to separate multiple destination registers. C. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. For some instructions the destination operand is optional. A. opcode A. while A.lt p|q. the D operand is the destination operand. PTX Instructions PTX instructions generally have from zero to four operands. followed by some examples that attempt to show several possible instantiations of the instruction.s32.Chapter 8. B. q = !(a < b). January 24. In addition to the name and the format of the instruction. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. b. For instructions that create a result value. 2010 55 . B. opcode D. and C are the source operands. setp. Instruction Set 8. the semantics are described. B. opcode D.2. The setp instruction writes two destination registers. A. // p = (a < b). opcode D.1. 8. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. A.

add.pred as the type specifier. j. 1. the following PTX instruction sequence might be used: @!p L1: setp.s32 p.reg .3. To implement the above example as a true conditional branch. use a predicate to control the execution of the branch or call instructions. n. So.pred p. Predicates are most commonly set as the result of a comparison performed by the setp instruction.lt. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.PTX ISA Version 2. predicate registers can be declared as . add. q. n.s32 j.s32 p.s32 j. predicate registers are virtual and have . … // compare i to n // if false. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. Instructions without a guard predicate are executed unconditionally. add 1 to j To get a conditional branch or conditional function call. i. consider the high-level code if (i < n) j = j + 1. Predicated Execution In PTX. 1. j. i. branch over 56 January 24. This can be written in PTX as @p setp. where p is a predicate variable. As an example.lt. optionally negated. // p = (i < n) // if i < n.0 8. 2010 . bra L1.

the result is false.Chapter 8. gt (greater-than).1. The following table shows the operators for signed integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. ge. ne (not-equal). and ge (greater-than-or-equal). gt. The unsigned comparisons are eq. and bitsize types. lt. unsigned integer. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. le (less-than-or-equal). If either operand is NaN. lt (less-than). ne.1.3. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. Unsigned Integer.1. 2010 57 .1.3. and hs (higher-or-same). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).2. hi (higher). lo (lower). Table 15. ne. ordering comparisons are not defined for bit-size types.3. The bit-size comparisons are eq and ne. ls (lower-or-same). Table 16. le. Instruction Set 8. Comparisons 8.

and nan returns true if either operand is NaN. neu.1. setp can be used to generate a predicate from an integer. If either operand is NaN. or. There is no direct conversion between predicates and integer values. leu. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.PTX ISA Version 2. two operators num (numeric) and nan (isNaN) are provided. ltu.0. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. and mov. If both operands are numeric values (not NaN). num returns true if both operands are numeric values (not NaN). then the result of these comparisons is true. 2010 .%p. // convert predicate to 32-bit value 58 January 24. Table 17.2.u32 %r1.0 To aid comparison operations in the presence of NaN values. gtu. Table 18. not. geu. xor. However. and no direct way to load or store predicate register values. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. unordered versions are included: equ. then these comparisons have the same result as their ordered counterparts.3. for example: selp.

f32 d.sX ok ok ok inv .bX . cvt. For example. For example. Table 19.bX .f32.uX ok ok ok inv . . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. most notably the data conversion instruction cvt. For example: .e.sX .reg . Example: . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 d.reg . Signed and unsigned integer types agree provided they have the same size. and these are placed in the same order as the operands.fX ok ok ok ok January 24.fX ok inv inv ok Instruction Type .uX . unsigned. add. b. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Floating-point types agree only if they have the same size. and integer operands are silently cast to the instruction type if needed. different sizes). // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.u16 d. Instruction Set 8. a.u16 d.u16 a. float. It requires separate type-size modifiers for the result and source. i.4..Chapter 8. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. and this information must be specified as a suffix to the opcode. a. • The following table summarizes these type checking rules. a. Type Checking Rules Operand Type . 2010 59 .reg . b. the add instruction requires type and size information to properly perform the addition operation (signed. they must match exactly.

“-“ = allowed. The following table summarizes the relaxed type-checking rules for source operands. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. so those rows are invalid for cvt. the data will be truncated. Bit-size source registers may be used with any appropriately-sized instruction type. When used with a narrower bit-size type. ld. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.4. unless the operand is of bit-size type. For example. no conversion needed. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. When used with a floating-point instruction type.bX instruction types. st. When a source operand has a size that exceeds the instruction-type size. 4. for example.1. Source register size must be of equal or greater size than the instruction-type size. 2. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Operand Size Exceeding Instruction-Type Size For convenience. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Note that some combinations may still be invalid for a particular instruction. parse error. 1. The data is truncated to the instruction-type size and interpreted according to the instruction type. so that narrow values may be loaded. stored. 2010 . Notes 3. the cvt instruction does not support . Floating-point source registers can only be used with bit-size or floating-point instruction types. Table 20.PTX ISA Version 2. and converted using regular-width registers. or converted to other types and sizes. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. 60 January 24. inv = invalid. the size must match exactly. floating-point instruction types still require that the operand type-size matches exactly. stored. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.0 8.

The following table summarizes the relaxed type-checking rules for destination operands. When used with a floatingpoint instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size. the data is sign-extended. parse error. the data is zeroextended. When used with a narrower bit-size instruction type. and is zero-extended to the destination register width otherwise. the size must match exactly. the data will be zero-extended. 2. 2010 61 . Destination register size must be of equal or greater size than the instruction-type size. Table 21. 4. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. zext = zero-extend.or sign-extended to the size of the destination register. inv = Invalid. January 24. Bit-size destination registers may be used with any appropriately-sized instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Notes 3. The data is signextended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer.Chapter 8. otherwise. Floating-point destination registers can only be used with bit-size or floating-point instruction types. 1. The data is sign-extended to the destination register width for signed integer instruction types. the destination data is zero. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. “-“ = Allowed but no conversion needed.

8. using the .6. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. a compiler or code author targeting PTX can ignore the issue of divergent threads. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. the semantics of 16-bit instructions in PTX is machine-specific. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. However.1. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. For divergent control flow. and for many applications the difference in execution is preferable to limiting performance. or conditional return. 16-bit registers in PTX are mapped to 32-bit physical registers. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. A compiler or programmer may chose to enforce portable. Both situations occur often in programs. 2010 . Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.0 8. until C is not expressive enough.uni suffix. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. at least in appearance. so it is important to have divergent threads re-converge as soon as possible. and 16-bit computations are “promoted” to 32-bit computations. If threads execute down different control flow paths.5. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. If all of the threads act in unison and follow a single control flow path.6. These extra precision bits can become visible at the application level. When executing on a 32-bit data path. At the PTX language level. Divergence of Threads in Control Constructs Threads in a CTA execute together. the threads are called uniform. until they come to a conditional control construct such as a conditional branch. Therefore. conditional function call. by a right-shift instruction. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. 62 January 24. for example. the optimizing code generator automatically determines points of re-convergence. The semantics are described using C. 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. this is not desirable. for many performance-critical applications.PTX ISA Version 2. the threads are called divergent.

1. 2010 63 .Chapter 8.7.cc. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. The Integer arithmetic instructions are: add sub add. In the following descriptions. Instructions All PTX instructions may be predicated. 8.cc. the optional guard predicate is omitted from the syntax.7. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8. addc sub.

d = a + b.type = { . add Syntax Integer Arithmetic Instructions: add Add two values.s32 .type = { . . // . Applies only to .u32 x. 2010 .c. PTX ISA Notes Target ISA Notes Examples Table 23. d. a.. Description Semantics Notes Performs addition and writes the resulting value into a destination register.type sub{. add.s32 type. Supported on all target architectures. . b. b.s32 d. . Applies only to . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.s32 c. .sat}.. b.sat applies only to . Supported on all target architectures.u32. PTX ISA Notes Target ISA Notes Examples 64 January 24.PTX ISA Version 2.z.0. // . .0.s32.s32 .u64. Introduced in PTX ISA version 1. add.sat}. Introduced in PTX ISA version 1. Saturation modifier: . a.0 Table 22. sub.u64. @p add. d = a – b. .sat limits result to MININT.s64 }.type add{.sat applies only to . sub. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.s32 c.a.MAXINT (no overflow) for the size of the operation.s32.sat. . d.MAXINT (no overflow) for the size of the operation.u32.s32 d.s16.sat limits result to MININT.u16. a.y. .1.u16.b.s16.s32 type. Saturation modifier: . .s64 }. b. . a.

CF) holding carry-in/carry-out or borrowin/borrow-out.Chapter 8.cc.b32 x1.u32. No other instructions access the condition code.cc specified.y2. addc{. x3. These instructions support extended-precision integer addition and subtraction. x4. add. clearing.cc Syntax Integer Arithmetic Instructions: add.2.cc}.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. add. 2010 65 . .z2. if . x2. carry-out written to CC.b32 addc. Introduced in PTX ISA version 1. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.y4. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y3.b32 x1.s32 }.z4. and there is no support for setting.CF. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers. carry-out written to CC.z2.z3. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.2.y2. Supported on all target architectures.cc. d = a + b.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. No saturation.b32 addc.z1. Supported on all target architectures.cc. Instruction Set Instructions add. x3. addc. b. x4.z1.u32.cc. x2.cc.type d.cc.type = {.y1.y4.type = { .cc.y1.cc Add two values with carry-out.cc.b32 addc.z4. Behavior is the same for unsigned and signed integers.b32 addc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. .CF No integer rounding modifiers. . @p @p @p @p add. No saturation.b32 addc.b32 addc. . sub. or testing the condition code. b.y3. Introduced in PTX ISA version 1. a. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. Table 24.z3. d = a + b + CC.type d. a.s32 }.cc. @p @p @p @p add.

Behavior is the same for unsigned and signed integers. .y2.PTX ISA Version 2. x4.cc Subract one value from another. Introduced in PTX ISA version 1. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.b32 subc. b.type d.y3.z2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.u32.cc.CF).b32 x1.cc specified. @p @p @p @p sub.z1.cc.z3. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. sub. withborrow-in and optional borrow-out.y1.cc. x2.b32 subc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.b32 x1.cc Syntax Integer Arithmetic Instructions: sub.s32 }. d = a – b. d = a . with borrow-out.CF No integer rounding modifiers. a. x3. sub. x4.cc.y2. borrow-out written to CC.z1. 2010 .cc}.cc.type = { .y4.y3.CF No integer rounding modifiers.cc. Supported on all target architectures.b32 subc.(b + CC. Behavior is the same for unsigned and signed integers.cc. Introduced in PTX ISA version 1.b32 subc. .y4. if .3. x2. .b32 subc. b. x3.z4.z4. @p @p @p @p sub.cc.type = {.cc.s32 }.type d. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y1. borrow-out written to CC. Supported on all target architectures.u32.3.z2.b32 subc. No saturation. .z3.0 Table 26. subc{. a. No saturation.

mul.0.fys.lo. If .wide..lo.s64 }. Description Semantics Compute the product of two values.hi or . d = t<n-1. d = t<2n-1.fxs. save only the low 16 bits // 32*32 bits. . Instruction Set Table 28. The .hi variant // for ..wide suffix is supported only for 16.n>. mul. If .s32 z. creates 64 bit result January 24. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.wide.s16 fa. // 16*16 bits yields 32 bits // 16*16 bits.u16.wide is specified.0>..hi.s16 fa. then d is twice as wide as a and b to receive the full result of the multiplication.s32. . mul{. .y.x.u32.and 32-bit integer types.. and either the upper or lower half of the result is written to the destination register. . .lo variant Notes The type of the operation represents the types of the a and b operands.wide // for .fys.wide}.u64.lo is specified. mul. t = a * b.Chapter 8. Supported on all target architectures. n = bitwidth of type. d = t. . b.s16. // for . 2010 67 .type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.type d. then d is the same size as a and b. a.fxs.

hi.wide suffix is supported only for 16.r. . 68 January 24.type mad.c.. .. b.a. t + c.lo. c.sat. bitwidth of type.u64. .hi mode.lo is specified. a.s32 d. Saturation modifier: . mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. 2010 .MAXINT (no overflow) for the size of the operation.type = { . .s64 }.s32.lo. . then d and c are twice as wide as a and b to receive the result of the multiplication... a. t<n-1.lo.s32 type in .hi.sat limits result to MININT. b. and either the upper or lower half of the result is written to the destination register. @p mad. If . Supported on all target architectures.u16.hi or . d.wide // for . mad{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .wide is specified.s32 d. and then writes the resulting value into a destination register.hi variant // for .PTX ISA Version 2. The .. c.s32 r. mad. Applies only to . then d and c are the same size as a and b. t<2n-1.p.n> + c. t n d d d = = = = = a * b. If .0> + c.u32.and 32-bit integer types.b.wide}.q.s16.0.0 Table 29. Description Semantics Multiplies two values and adds a third. // for .lo variant Notes The type of the operation represents the types of the a and b operands.

mul24. . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.16>.type = { . January 24. t = a * b. // low 32-bits of 24x24-bit signed multiply.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.hi. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..hi variant // for . d = t<47.type d.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.b. mul24{. 48bits.a.Chapter 8.0. .0>.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. mul24.s32 }. mul24.u32. a. Supported on all target architectures. i.hi may be less efficient on machines without hardware support for 24-bit multiply.lo. // for . b. 2010 69 .lo}. All operands are of the same type and size.e. d = t<31. Instruction Set Table 30.s32 d. mul24. and return either the high or low 32-bits of the 48-bit result..

.0 Table 31. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. Applies only to .b. t = a * b.c.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. . 48bits.type = { .sat limits result of 32-bit signed addition to MININT. i. Supported on all target architectures. a. // low 32-bits of 24x24-bit signed multiply.type mad24. c.sat. .0.hi.s32 }. d. Return either the high or low 32-bits of the 48-bit result.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.MAXINT (no overflow). All operands are of the same type and size.PTX ISA Version 2. 70 January 24.hi mode.hi variant // for .hi.16> + c.s32 d. Description Compute the product of two 24-bit integer values held in 32-bit source registers.lo}.a. Saturation modifier: . mad24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mad24. d = t<31.u32.e.s32 type in . mad24. // for . mad24{..lo.0> + c. d = t<47..s32 d. c.. 2010 . 32-bit value to either the high or low 32-bits of the 48-bit result. b. mad24.hi may be less efficient on machines without hardware support for 24-bit multiply. and add a third. b.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. a.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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a. . a = a << 1.b64 }.b32. For .type = { . mask = 0x80000000. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. For .u32 Semantics 74 January 24. . inclusively. mask = 0x8000000000000000. popc. a.b32 type. while (a != 0) { if (a&0x1) d++. } Introduced in PTX ISA version 2. . popc requires sm_20 or later.0.b32.type d. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b64 type. } else { max = 64. the number of leading zeros is between 0 and 32. d = 0. cnt. popc Syntax Integer Arithmetic Instructions: popc Population count. . clz. } while (d < max && (a&mask == 0) ) { d++. a. clz.0 Table 39. a = a >> 1. 2010 .b64 }.b32 popc. if (. inclusively. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.type == . clz requires sm_20 or later. a. the number of leading zeros is between 0 and 64. X. cnt. // cnt is . // cnt is . d = 0.b64 d. X.0.PTX ISA Version 2.type d.b64 d.type = { .u32 PTX ISA Notes Target ISA Notes Examples Table 40.b32 clz. popc. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32) { max = 32.

bfind requires sm_20 or later. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind. X.u32. } } if (. Semantics msb = (.d. bfind returns 0xFFFFFFFF if no non-sign bit is found. bfind returns the bit position of the most significant “1”.u32 || . i--) { if (a & (1<<i)) { d = i. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.shiftamt is specified. // cnt is . . If . bfind. Instruction Set Table 41. a.u32 January 24. a.u32 d.type==.0. For signed integers. i>=0.s64 }. . bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. . d.type d.type bfind. break.s32) ? 31 : 63.type = { . Operand a has the instruction type. d = -1. 2010 75 . bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.shiftamt && d != -1) { d = msb .shiftamt. and operand d has type .u64.Chapter 8.s32. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type==.shiftamt. For unsigned integers. a. for (i=msb.u32.s64 cnt. . bfind.

Description Semantics Perform bitwise reversal of input.type==. i++) { d[i] = a[msb-i].type d. a. brev. . msb = (. i<=msb.0. for (i=0. 2010 .b32 d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a.0 Table 42. 76 January 24. . brev requires sm_20 or later.type = { .b32.PTX ISA Version 2.b32) ? 31 : 63.b64 }. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. brev.

Operands a and d have the same type as the instruction type. c. If the start position is beyond the msb of the input. . Source b gives the bit field starting bit position.type==. else sbit = a[min(pos+len-1.s32.u32 || .u32.type==. the result is zero. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.u32 || .type d.b32 d.Chapter 8. . Instruction Set Table 43.s64 }.u64: . Description Extract bit field from a and place the zero or sign-extended result in d.a. Semantics msb = (.u64. .u32. otherwise If the bit field length is zero. d = 0. The sign bit of the extracted field is defined as: . 2010 77 . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u32.u64 || len==0) sbit = 0. bfe.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. i<=msb.s32. for (i=0.0.len. . . a.type==. .start. and source c gives the bit field length in bits.s32) ? 31 : 63. the destination d is filled with the replicated sign bit of the extracted field.msb)]. January 24.type = { . len = c. bfe requires sm_20 or later. and operands b and c are type . b. The destination d is padded with the sign bit of the extracted field. if (. bfe. pos = b.type==.

PTX ISA Version 2. d. and place the result in f. 78 January 24. bfi. bfi requires sm_20 or later.len. the result is b. the result is b.b64 }. c.b32 d.b32) ? 31 : 63.type f. Source c gives the starting bit position for the insertion. and operands c and d are type . b. b.b. . Operands a. for (i=0. i<len && pos+i<=msb. f = b.0.u32. Description Align and insert a bit field from a into b. pos = c. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. a. .type==. If the start position is beyond the msb of the input. and source d gives the bit field length in bits.a. If the bit field length is zero. and f have the same type as the instruction type. Semantics msb = (. bfi.start.b32. i++) { f[pos+i] = a[i]. 2010 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 44.type = { . len = d.

a} = {{b7.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. msb=0 means copy the literal value.f4e. Instruction Set Table 45.ecr. . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. as a 16b permute code.ecl. and reassemble them into a 32-bit destination register. b5. b6.rc16 }. b1. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. In the generic form (no mode specified). Description Pick four arbitrary bytes from two 32-bit registers.rc8.b3 source select c[15:12] d.mode} d. Thus. For each byte in the target register. b0}}. prmt. b2.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. 2010 79 . {b3.mode = { .b1 source select c[7:4] d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. . . the four 4-bit values fully specify an arbitrary byte permute. The bytes in the two source registers are numbered from 0 to 7: {b. the permute control consists of four 4-bit selection values. .b2 source select c[11:8] d. . default mode index d. c.b4e.b32{. b. b4}. Note that the sign extension is only performed as part of generic form.Chapter 8.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. The msb defines if the byte value should be copied. a. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. msb=1 means replicate the sign. . a 4-bit selection value is defined. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).

r4. 80 January 24. ctl[3]. ctl[1]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[0]. tmp64 ).PTX ISA Version 2. tmp64 ).0 Semantics tmp64 = (b<<32) | a. prmt. tmp64 ).b32 prmt. tmp[15:08] = ReadByte( mode. ctl[2] = (c >> 8) & 0xf. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp[23:16] = ReadByte( mode. ctl[2]. r2.0. ctl[1] = (c >> 4) & 0xf. 2010 . prmt requires sm_20 or later. r1. r3.f4e r1. ctl[3] = (c >> 12) & 0xf. r3. tmp64 ). } tmp[07:00] = ReadByte( mode. r2. r4. tmp[31:24] = ReadByte( mode.

f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .2.Chapter 8. Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8.f64 register operands and constant immediate values.7.

f64 mad.rnd.mul}.rcp. 2010 .rnd. {mad.rn . and mad support saturation of results to the range [0.neg. Double-precision instructions support subnormal inputs and results.rp .min. No rounding modifier.rnd. sub.neg.f32 {abs.approx.rn and instructions may be folded into a multiply-add.target sm_20 .sub. NaN payloads are supported for double-precision instructions.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.f64 are the same.lg2.rcp.rnd.f64 rsqrt. {add. mul.32 and fma. default is .f32 {add.sqrt}.f32 {div. .sqrt}. 1.0 The following table summarizes floating-point instructions in PTX. Table 46.max}.rm .f32 {div.fma}.sqrt}. If no rounding modifier is specified.0].ex2}.f64 and fma.mul}.f32 rsqrt.target sm_20 mad.f32 are the same.cos.fma}. Note that future implementations may support NaN payloads for single-precision instructions.f64 div.f32 .f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.PTX ISA Version 2. so PTX programs should not rely on the specific single-precision NaNs being generated.f32 {mad. default is .ftz .rnd. .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.target sm_1x No rounding modifier.approx.f64 {abs.rcp.0. Single-precision add.max}. The optional .approx.min. but single-precision instructions return an unspecified NaN.rnd. Instruction Summary of Floating-Point Instructions . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. with NaNs being flushed to positive zero.rn and instructions may be folded into a multiply-add.f64 {sin. 82 January 24.full.sub.rz .approx.f32 {div.sat Notes If no rounding modifier is specified.

f32.Chapter 8. . testp. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.op p.f32. X.0. B. . b. Table 48.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. a. 2010 83 .type .type d. not infinity). positive and negative zero are considered normal numbers. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.notanumber.f64 }.infinite. C. . testp. and return the result as d.0. copysign requires sm_20 or later. .subnormal }. A.normal testp.f32 copysign.op. a. . .finite testp.f64 }. copysign. . Instruction Set Table 47. f0.notanumber. y. true if the input is a subnormal number (not NaN. testp requires sm_20 or later.type = { . Introduced in PTX ISA version 2.type = { . p.infinite testp. copysign.infinite. not infinity) As a special case.notanumber testp. testp.number.normal.finite. z.f64 x. January 24. .f64 isnan. testp Syntax Floating-Point Instructions: testp Test floating-point property.f32 testp. // result is . .number testp.pred = { . Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.

.rp for add.PTX ISA Version 2. add.rz mantissa LSB rounds towards zero .0f.f64 supports subnormal numbers.rn. 84 January 24.ftz. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. add.rnd}.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later. b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rm.f32 supported on all target architectures. add. add.ftz}{. Description Semantics Notes Performs addition and writes the resulting value into a destination register.ftz. 1.f32 flushes subnormal inputs and results to sign-preserving zero. .f3. In particular. Saturation modifier: . add Syntax Floating-Point Instructions: add Add two values.rz available for all targets .sat.f32.rnd}{.f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_13 for add. a. add.rz. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.0. .rn): . NaN results are flushed to +0. 2010 . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers (default is . .rp }.rm.rn. a. Rounding modifiers have the following target requirements: .f32 f1.f64 d. .f32 clamps the result to [0. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. subnormal numbers are supported. sm_1x: add.f64.f32 add{. d.0 Table 49. b.0].rn mantissa LSB rounds to nearest even .rz.rnd = { . . add{. d = a + b.0. requires sm_20 Examples @p add.sat}.f2.

rz. sub{.ftz}{. NaN results are flushed to +0. Instruction Set Table 50. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rm.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f64 d. d. b.f2.rnd = { . sub Syntax Floating-Point Instructions: sub Subtract one value from another.rn): . subnormal numbers are supported.f32 clamps the result to [0. sm_1x: sub.f32 sub{.f64 supports subnormal numbers. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.0f. . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. . sub.0.rm.f32 f1.rm mantissa LSB rounds towards negative infinity .sat}.f32. a.rn mantissa LSB rounds to nearest even .a.rz available for all targets . d = a . requires sm_13 for sub.rp }. In particular.f32 flushes subnormal inputs and results to sign-preserving zero.rnd}{. sub.rp for sub. 2010 85 .f32 supported on all target architectures.sat. requires sm_20 Examples sub.0]. . Saturation modifier: sub.f3. . Rounding modifiers (default is .f64 requires sm_13 or later.rn.rnd}. b. a. sub.ftz.f32 c.rz mantissa LSB rounds towards zero .rn. sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.b.Chapter 8. January 24. .0.f64. sub. Rounding modifiers have the following target requirements: .b.

f32 flushes subnormal inputs and results to sign-preserving zero. In particular.rnd = { .PTX ISA Version 2.f32 supported on all target architectures.sat. 1. NaN results are flushed to +0.0]. a. mul. b.f64 requires sm_13 or later. . d. Saturation modifier: mul.rm mantissa LSB rounds towards negative infinity . mul.0f.rnd}.f32.ftz.rnd}{.rn.rn): . mul.ftz}{.rm. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.0. For floating-point multiplication. . 2010 .ftz. Description Semantics Notes Compute the product of two values. mul{. subnormal numbers are supported.radius.f64 d.0 Table 51. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. Rounding modifiers (default is .pi // a single-precision multiply 86 January 24. all operands must be the same size.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp for mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Rounding modifiers have the following target requirements: .f32 mul{.f32 circumf. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rz.f64 supports subnormal numbers. .f64.rn.f32 flushes subnormal inputs and results to sign-preserving zero. d = a * b. . . mul. requires sm_20 Examples mul. requires sm_13 for mul.rm.sat}. .rn mantissa LSB rounds to nearest even .0.rp }.f32 clamps the result to [0.rz available for all targets .rz mantissa LSB rounds towards zero . sm_1x: mul. a. b. mul Syntax Floating-Point Instructions: mul Multiply two values.

sat}.a.ftz. a. fma. d.f64 supports subnormal numbers.f32 fma.f32 flushes subnormal inputs and results to sign-preserving zero.4.rnd{. @p fma.f64 w. fma.ftz.f32 computes the product of a and b to infinite precision and then adds c to this product. 1. 2010 87 . again in infinite precision.f32 requires sm_20 or later. fma.rn. .f32 introduced in PTX ISA version 2.0].c. fma Syntax Floating-Point Instructions: fma Fused multiply-add.rnd. sm_1x: fma. b.rn.f64 introduced in PTX ISA version 1. c. PTX ISA Notes Target ISA Notes Examples January 24.rp }.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. The resulting value is then rounded to double precision using the rounding mode specified by .f32 clamps the result to [0.x.rm mantissa LSB rounds towards negative infinity .f64 is the same as mad.sat. subnormal numbers are supported.rn.rz mantissa LSB rounds towards zero .f32 is unimplemented in sm_1x. The resulting value is then rounded to single precision using the rounding mode specified by . fma. d. .b.f64.rnd. fma. a. c. fma.0f. Rounding modifiers (no default): . NaN results are flushed to +0.f64 requires sm_13 or later. fma.rnd = { .0. again in infinite precision. .rnd.f32 fma.Chapter 8. d = a*b + c. b.z.y.ftz}{. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. .rz.rm. fma.f64 d. fma. fma.f64 computes the product of a and b to infinite precision and then adds c to this product. Saturation: fma.0. Instruction Set Table 52.rn mantissa LSB rounds to nearest even .

e.rnd.rnd.f64 is the same as fma.f32 flushes subnormal inputs and results to sign-preserving zero. b. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f64}. The resulting value is then rounded to double precision using the rounding mode specified by .ftz. a. When JIT-compiled for SM 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1. c.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 computes the product of a and b at double precision. mad{.target sm_13 and later .sat}. mad. The exception for mad. again in infinite precision. mad.0 devices. and then the mantissa is truncated to 23 bits. b. again in infinite precision.rm mantissa LSB rounds towards negative infinity .0.f64 computes the product of a and b to infinite precision and then adds c to this product.rnd. b.rn. In this case.f64 computes the product of a and b to infinite precision and then adds c to this product. mad.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero.rn.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.{f32.ftz}{. a.rp }.PTX ISA Version 2. d = a*b + c. Saturation modifier: mad.rnd. but the exponent is preserved. Note that this is different from computing the product with mul. The resulting value is then rounded to double precision using the rounding mode specified by .f32 mad..f32 is when c = +/-0. Description Semantics Notes Multiplies two values and adds a third. mad.0.ftz}{. Unlike mad. fma. . c. 2010 .rz mantissa LSB rounds towards zero . NaN results are flushed to +0.f32 mad. Rounding modifiers (no default): .rm.f32).f32.target sm_1x: mad.f32 is identical to the result computed using separate mul and add instructions.f32 clamps the result to [0. . .sat}.{f32.0f. c.target sm_1x d.0]. subnormal numbers are supported. mad.sat.f64} is the same as fma.target sm_20: mad. The resulting value is then rounded to single precision using the rounding mode specified by .target sm_20 d. sm_1x: mad. mad. and then writes the resulting value into a destination register. mad. mad. 88 January 24. the treatment of subnormal inputs and output follows IEEE 754 standard. mad.0 Table 53. a. // .f64 supports subnormal numbers.f64. // . For .ftz.f64 d. For . again in infinite precision.rn mantissa LSB rounds to nearest even .f32 is implemented as a fused multiply-add (i.rz.rnd{. // . where the mantissa can be rounded and the exponent will be clamped.

a rounding modifier is required for mad.f64 instructions having no rounding modifier will map to mad.f64. In PTX ISA versions 1...rm. In PTX ISA versions 2..Chapter 8.0.rn..f32 d. Legacy mad. Rounding modifiers have the following target requirements: ..b. mad.rz.f32 supported on all target architectures.f64.rm.c.rz.a.f64. January 24.f32. 2010 89 . requires sm_20 Examples @p mad. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rn.rp for mad.0 and later. a rounding modifier is required for mad.4 and later.f64 requires sm_13 or later. Target ISA Notes mad..rp for mad. requires sm_13 .rn.f32 for sm_20 targets.

one of .full{.f64 diam. div.f64 d. For PTX ISA version 1. z. div Syntax Floating-Point Instructions: div Divide one value by another. Fast.ftz.f32 implements a fast approximation to divide. Explicit modifiers . div.ftz.f32 div.rnd. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . approximate division by zero creates a value of infinity (with same sign as a). subnormal numbers are supported. PTX ISA Notes div.ftz}. computed as d = a * (1/b). a. a.rn.rm mantissa LSB rounds towards negative infinity . Description Semantics Notes Divides a by b.rm.PTX ISA Version 2.ftz}. x.circum.f32 flushes subnormal inputs and results to sign-preserving zero. and rounding introduced in PTX ISA version 1. 2126]. Fast. .approx.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd{.rn mantissa LSB rounds to nearest even . d.f32.approx{.ftz.f32 and div. but is not fully IEEE 754 compliant and does not support rounding modifiers. a.rz.f32 defaults to div.f32 div.rnd. full-range approximation that scales operands to achieve better accuracy. and div.0. the maximum ulp error is 2. xd. div. b. .rp }.0 through 1.f64 supports subnormal numbers. div. . d. b.approx.f64 requires sm_20 or later.full. d = a / b.full.ftz}. The maximum ulp error is 2 across the full range of inputs. div.rnd is required. . For b in [2-126.rz mantissa LSB rounds towards zero .{rz. b.full.ftz.approx. b. stores result in d.14159. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . For PTX ISA versions 1. a.rp}. // // // // fast.f64 introduced in PTX ISA version 1.rn.f32 implements a relatively fast.approx. div. 2010 .rnd = { .full. Examples 90 January 24.f64 requires sm_13 or later.4 and later. Target ISA Notes div.3.0 Table 54. .ftz. Subnormal inputs and results are flushed to sign-preserving zero. or .f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. zd.f64 defaults to div. y.f32 div.approx. div.approx.4.rn. d. approximate single-precision divides: div. sm_1x: div.rn.full.f32 requires sm_20 or later. div. div. yd.rm.f32 and div.f32 div.f64.f32 div.3. .

sm_1x: neg.0.f32 x. abs.ftz. NaN inputs yield an unspecified NaN. abs{. subnormal numbers are supported. Negate the sign of a and store the result in d.f64 requires sm_13 or later.f0. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 supported on all target architectures. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d.Chapter 8. 2010 91 . a.f32 x. NaN inputs yield an unspecified NaN. d = -a. neg. d = |a|. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f64 supports subnormal numbers. Subnormal numbers: sm_20: By default. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs.f0.0. Instruction Set Table 55. subnormal numbers are supported.f32 abs.ftz}. Table 56. January 24. a. d. neg.ftz}. neg.f32 flushes subnormal inputs and results to sign-preserving zero. a. abs.f32 neg. sm_1x: abs. Take the absolute value of a and store the result in d.ftz.f64 d.f64 requires sm_13 or later.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. neg. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. Subnormal numbers: sm_20: By default.f64 supports subnormal numbers. a. neg{. abs.f64 d.

min. subnormal numbers are supported. @p min.0. d d d d = = = = NaN. sm_1x: max. d.0. d. subnormal numbers are supported. a.f64 supports subnormal numbers.f64 requires sm_13 or later. a.f32 supported on all target architectures. b. sm_1x: min. Table 58. (a > b) ? a : b.ftz}.PTX ISA Version 2. b. min. min. b. a.f32 flushes subnormal inputs and results to sign-preserving zero. 92 January 24.f2.f32 max.ftz.ftz}.f64 d.ftz. Store the minimum of a and b in d. min.f32 min. max. d d d d = = = = NaN. max.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f1. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f64 f0. b.f64 z.c.f32 flushes subnormal inputs and results to sign-preserving zero. max. b.x.z. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 min.f64 supports subnormal numbers.0 Table 57. min{. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. a. a. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f32 max.f32 flushes subnormal inputs and results to sign-preserving zero. max{. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 supported on all target architectures.c. max.b.b. Store the maximum of a and b in d. a. (a < b) ? a : b. a.ftz. 2010 . if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 requires sm_13 or later. max.f64 d. b.

Description Semantics Notes Compute 1/a.Chapter 8. For PTX ISA versions 1.rn.rm mantissa LSB rounds towards negative infinity .approx.rn.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn.rp }.f32 rcp.x. For PTX ISA version 1.f32 and rcp.f32 defaults to rcp.f64 requires sm_13 or later.4.f32 rcp.ftz}. sm_1x: rcp. rcp. rcp. rcp.f64 defaults to rcp. rcp.f32 implements a fast approximation to reciprocal. a.approx.0 +0. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. 2010 93 .f32 supported on all target architectures. rcp.rn. rcp.0.rn. Instruction Set Table 59.rm. // fast. rcp.ftz.{rz.approx{.f32 flushes subnormal inputs and results to sign-preserving zero.approx.ftz.f64 ri. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rz mantissa LSB rounds towards zero . General rounding modifiers were added in PTX ISA version 2. Target ISA Notes rcp. a.rnd{. . xi. Examples January 24.f64 d.4 and later.f64.f32 rcp.0-2.f32 rcp.0.f64 requires sm_20 or later.f32 requires sm_20 or later. d = 1 / a. .ftz.3. a. rcp.f64 supports subnormal numbers.0 +subnormal +Inf NaN Result -0. one of .r.0 through 1.rnd is required.approx.f64 introduced in PTX ISA version 1. store result in d.rnd. rcp. The maximum absolute error is 2-23.ftz were introduced in PTX ISA version 1. xi.0 over the range 1.rn mantissa LSB rounds to nearest even .f64 and explicit modifiers .rz.approx or .f32 flushes subnormal inputs and results to sign-preserving zero.approx and .rm.f32.rp}. d. and rcp. Input -Inf -subnormal -0.ftz}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .0 -Inf -Inf +Inf +Inf +0.0. PTX ISA Notes rcp. d.ftz.rnd. subnormal numbers are supported. rcp.rn.rnd = { .x.

rn.f32 sqrt. sqrt.f32 is TBD.f64 introduced in PTX ISA version 1.approx. sm_1x: sqrt.ftz}.ftz. // IEEE 754 compliant rounding d. sqrt. PTX ISA Notes sqrt.ftz}.0 +subnormal +Inf NaN Result NaN NaN -0. sqrt.rm mantissa LSB rounds towards negative infinity .rnd.f32 supported on all target architectures.rnd{.rp }.x.rnd is required.approx. General rounding modifiers were added in PTX ISA version 2. sqrt.0. sqrt.f32.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64 r. one of . store in d. .{rz.f64 defaults to sqrt.f32 requires sm_20 or later. sqrt.0 +0. Input -Inf -normal -subnormal -0. d = sqrt(a). 2010 .rm. // fast.rn mantissa LSB rounds to nearest even . Examples 94 January 24.0 -0.rn. a. // IEEE 754 compliant rounding . r.ftz.f32 defaults to sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. The maximum absolute error for sqrt. Description Semantics Notes Compute sqrt(a). sqrt.rn.f64 and explicit modifiers . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. a.0 Table 60.approx.rnd = { .rz. and sqrt. subnormal numbers are supported.rn.f64 requires sm_20 or later.0 +0.approx{.rn.rm.f64 requires sm_13 or later.f32 sqrt.f32 and sqrt.0 +0. . .approx.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx.0.rn.PTX ISA Version 2.ftz were introduced in PTX ISA version 1.f64 d.rz mantissa LSB rounds towards zero .f64.3.4 and later.f32 sqrt. approximate square root d. Target ISA Notes sqrt.f32 sqrt.0 through 1. sqrt. For PTX ISA versions 1. r.ftz. a.f32 implements a fast approximation to square root. For PTX ISA version 1.rp}.approx or .ftz.approx and .f64 supports subnormal numbers.x.x. sqrt.4.rnd.

PTX ISA Notes rsqrt. Instruction Set Table 61.0. rsqrt. rsqrt.approx and . subnormal numbers are supported. x.ftz.0 through 1.f64 is TBD.f32 defaults to rsqrt.approx implements an approximation to the reciprocal square root.0-4. a. rsqrt.approx. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.ftz.f64 d. For PTX ISA versions 1. d. d = 1/sqrt(a). For PTX ISA version 1. rsqrt.f32 rsqrt.4.ftz}.ftz.approx modifier is required.f64 requires sm_13 or later.approx.f64 is emulated in software and are relatively slow.Chapter 8.3.f32 supported on all target architectures.f32. and rsqrt.f64 were introduced in PTX ISA version 1.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. The maximum absolute error for rsqrt. Input -Inf -normal -subnormal -0. Explicit modifiers . rsqrt.0.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default. Note that rsqrt. Compute 1/sqrt(a).approx.4 over the range 1. a.f32 is 2-22. X. rsqrt. January 24.ftz were introduced in PTX ISA version 1.approx.f64 isr.f32 and rsqrt. Target ISA Notes Examples rsqrt. store the result in d. rsqrt.approx.4 and later.0 +0. 2010 95 . sm_1x: rsqrt.f64 supports subnormal numbers.f32 rsqrt.0 NaN The maximum absolute error for rsqrt.approx.approx{.f64 defaults to rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. the . ISR.f64.

sin.0 +subnormal +Inf NaN Result NaN -0. sin. sin. For PTX ISA version 1.ftz. d = sin(a). Find the sine of the angle a (in radians).f32. Subnormal numbers: sm_20: By default. the . 2010 .0 +0. 96 January 24.0 through 1.ftz}. a. sin. Explicit modifiers . PTX ISA Notes sin.f32 d.0 +0. a.f32 defaults to sin.PTX ISA Version 2.approx.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero.0 -0.f32 introduced in PTX ISA version 1.approx. subnormal numbers are supported.0 +0.f32 implements a fast approximation to sine. Input -Inf -subnormal -0.ftz.approx{.0 NaN NaN The maximum absolute error is 2-20. For PTX ISA versions 1.approx and .3.4.ftz introduced in PTX ISA version 1.f32 sa.0 Table 62.9 in quadrant 00.0.ftz.approx. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.4 and later. sin.f32 flushes subnormal inputs and results to sign-preserving zero. Target ISA Notes Examples Supported on all target architectures.

4 and later. the .approx. Explicit modifiers . a.0 +subnormal +Inf NaN Result NaN +1.ftz introduced in PTX ISA version 1. PTX ISA Notes cos.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.0 +0. subnormal numbers are supported. d = cos(a).f32 introduced in PTX ISA version 1.approx modifier is required. 2010 97 . Input -Inf -subnormal -0.Chapter 8.4. Find the cosine of the angle a (in radians).0 +1. sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA versions 1. cos. cos. cos.ftz.f32 d.0. cos.0 through 1. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz. cos. Target ISA Notes Examples Supported on all target architectures.9 in quadrant 00.approx.f32 defaults to cos.0 +1.approx and .0 +1. a.f32.ftz.ftz}.3. For PTX ISA version 1.0 NaN NaN The maximum absolute error is 2-20. Instruction Set Table 63.f32 ca. January 24.approx.approx{.f32 implements a fast approximation to cosine.

f32 la.f32 Determine the log2 of a.0 +0.3. the . lg2.f32 flushes subnormal inputs and results to sign-preserving zero.f32 defaults to lg2.approx. a.4. 98 January 24. Target ISA Notes Examples Supported on all target architectures. lg2. d = log(a) / log(2).ftz. For PTX ISA versions 1.f32 implements a fast approximation to log2(a). Subnormal numbers: sm_20: By default. Explicit modifiers .ftz}. 2010 . sm_1x: Subnormal inputs and results to sign-preserving zero.approx{.f32.6 for mantissa.0. lg2.approx modifier is required.f32 introduced in PTX ISA version 1. For PTX ISA version 1.ftz.PTX ISA Version 2. The maximum absolute error is 2-22.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. PTX ISA Notes lg2.0 through 1. Input -Inf -subnormal -0.approx. lg2.ftz. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz introduced in PTX ISA version 1.0 Table 64. lg2.4 and later.approx and .approx. subnormal numbers are supported. a.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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then these comparisons have the same result as their ordered counterparts. gt. ne.b. . gt. ge. ls. bit-size comparisons are eq and ne. ls. le.b16.r. @q setp.type setp. gtu. leu. 2010 . setp. b.ftz applies only to . {!}c. the result is false.a. Applies to all numeric types. loweror-same.i. Integer Notes Floating Point Notes The ordered comparisons are eq. ne.CmpOp. If both operands are numeric values (not NaN).f64 }. and higher-or-same may be used instead of lt.ftz}. p[|q]. lo. setp.s64. respectively. a. xor. gtu. and nan returns true if either operand is NaN. and hs for lower.B) is one of: and.pred variables. and can be one of: eq. c). The destinations p and q must be . gt. The untyped. For unsigned values.f32 flushes subnormal inputs to sign-preserving zero. higher. lt.f32 comparisons. The signed and unsigned comparison operators are eq. p = BoolOp(t. .BoolOp{. geu.u32. hi. nan The Boolean operator BoolOp(A. ltu.f32.dtype. c). q = BoolOp(!t.CmpOp{. This result is written to the first destination operand. setp.PTX ISA Version 2. ltu. or. .b64.0 Table 67.u32 p|q.n. ge. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.u16. geu.ftz}. b. .type = { . lt. le. setp with . .f32 flushes subnormal inputs to sign-preserving zero. and (optionally) combine this result with a predicate value by applying a Boolean operator. .ftz. num.type .f64 supports subnormal numbers. hi. If either operand is NaN. le. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 source type requires sm_13 or later. . Subnormal numbers: sm_20: By default. neu. p[|q].dtype. To aid comparison operations in the presence of NaN values.u64.s16.0.s32.s32 setp. . a. num returns true if both operands are numeric values (not NaN).and.eq. . subnormal numbers are supported. gt.dtype. leu. If either operand is NaN. A related value computed using the complement of the compare result is written to the second destination operand. neu. ne. lt. hs equ. The comparison operator is a suffix on the instruction. ge.b32. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. Semantics t = (a CmpOp b) ? 1 : 0. p. 102 January 24. ge. then the result of these comparisons is true. the comparison operators lo. . Modifier . le. sm_1x: setp. unordered versions are included: equ.lt.

s32 slct{. . a is stored in d. Operands d. The selected input is copied to the output without modification. otherwise b is stored in d. b. y.f64 requires sm_13 or later. a. c.0.s32. and b must be of the same type. .u32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and b are treated as a bitsize type of the same width as the first instruction type. a is stored in d. If operand c is NaN. Semantics Floating Point Notes January 24. .f32 A. B.Chapter 8.s16. slct. .b64. If c ≥ 0.u64.s32 x. slct. Operand c is a predicate. . val. based on the value of the predicate source operand. Table 69. d. Modifier . . Subnormal numbers: sm_20: By default. d = (c >= 0) ? a : b. . c.f32 flushes subnormal values of operand c to sign-preserving zero.p.dtype. f0. selp.type d.dtype.s32. slct Syntax Comparison and Selection Instructions: slct Select one source operand. . d = (c == 1) ? a : b.g. . .b16. a. C. .r.x. b otherwise.u32.f32. .s64.f64 requires sm_13 or later.t.u16.b64.ftz}.u32.ftz. selp Syntax Comparison and Selection Instructions: selp Select between source operands.f32 r0. @q selp. .s32 selp. b. . .type = { .ftz applies only to . If c is True. .f32 flushes subnormal values of operand c to sign-preserving zero.b32.dtype.f32 comparisons. a. slct.u64. Instruction Set Table 68.f64 }. 2010 103 . . subnormal numbers are supported. based on the sign of the third operand. sm_1x: slct. z. For . c.f32. fval.ftz. .xp. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. slct.0.f32 d.b16. .f64 }. and operand a is selected.s16.dtype.f32 comparisons.u16.dtype = { . a. negative zero equals zero. Introduced in PTX ISA version 1. and operand a is selected.u64.s64. . selp. a. . slct. operand c must match the second instruction type.b32. . b. Description Conditional selection. the comparison is unordered and operand b is selected. Operands d.

provided the operands are of the same size. performing bit-wise operations on operands of any type. 2010 . or. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. Instructions and.7.0 8. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4.PTX ISA Version 2. This permits bit-wise operations on floating point values without having to define a union to access the bits. xor. and not also operate on predicates.

0.b32.fpvalue. .b64 }. and.0x80000000.q.type = { . but not necessarily the type. but not necessarily the type.pred p.b32 x. b. .b16.pred.0. .type d. The size of the operands must match. or.r.b64 }.b32 and. Supported on all target architectures.r. a. or Syntax Logic and Shift Instructions: or Bitwise OR. . Table 71.Chapter 8.b32 mask mask. a. Introduced in PTX ISA version 1. Allowed types include predicate registers. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. Introduced in PTX ISA version 1. and Syntax Logic and Shift Instructions: and Bitwise AND. January 24. sign. 2010 105 . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.pred. Allowed types include predicate registers.type d. d = a | b. or. . and.b16.b32. . Instruction Set Table 70. The size of the operands must match. b. .0x00010001 or. Supported on all target architectures. .q.type = { . d = a & b.

d.type = { . The size of the operands must match. a.b32.b16. . but not necessarily the type. . The size of the operands must match. Introduced in PTX ISA version 1.b16. Supported on all target architectures. .type = { .0 Table 72. Table 73. not.type d. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b32 d.b64 }. but not necessarily the type.a. cnot. not.0.pred. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. .type d.0.b16 d. .b32. .type d.PTX ISA Version 2. b.q. Allowed types include predicates. Supported on all target architectures. d = (a==0) ? 1 : 0.r.pred p. d = a ^ b. Table 74. cnot. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).mask. but not necessarily the type.b32 mask. xor.b32 xor. a. . Allowed types include predicate registers. xor. 2010 . d = ~a.b32. .0x0001.b64 }.b64 }. not.type = { .q. . Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. not Syntax Logic and Shift Instructions: not Bitwise negation. Introduced in PTX ISA version 1. The size of the operands must match.pred.b16. one’s complement. 106 January 24. a. .x. Introduced in PTX ISA version 1.0.

. The sizes of the destination and first source operand must match. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. i. a.2.b16.type d.s32. zero-fill on right. .b32. The b operand must be a 32-bit value.b32. but not necessarily the type. shl. d = a << b. a. Bit-size types are included for symmetry with SHL.b32 q. shr Syntax Logic and Shift Instructions: shr Shift bits right. .type d. .s32 shr.j.b64 }. shl. PTX ISA Notes Target ISA Notes Examples January 24.u32. . . The sizes of the destination and first source operand must match. .i. unsigned and untyped shifts fill with 0.Chapter 8. shr.b16.s16. PTX ISA Notes Target ISA Notes Examples Table 76.b16 c. .type = { .0.1.2. .u64. .i. k. . regardless of the instruction type. Supported on all target architectures.s64 }.a. Instruction Set Table 75.b64. Signed shifts fill with the sign bit. Introduced in PTX ISA version 1. b. b. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.0. Supported on all target architectures. regardless of the instruction type. shl Syntax Logic and Shift Instructions: shl Shift bits left.a. sign or zero fill on left. shr. but not necessarily the type. d = a >> b. Introduced in PTX ISA version 1. .type = { .u16. The b operand must be a 32-bit value.u16 shr. Shift amounts greater than the register width N are clamped to N. Shift amounts greater than the register width N are clamped to N. 2010 107 .

The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. mov.PTX ISA Version 2. suld. Data Movement and Conversion Instructions These instructions copy data from place to place. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. st. prefetchu isspacep cvta cvt 108 January 24. 2010 . ldu. or shared state spaces. and from state space to state space.7. possibly converting it from one format to another.0 8. and st operate on both scalar and vector types. local. The cvta instruction converts addresses between generic and global. and sust support optional cache operations. ld. Instructions ld.5.

fetch again). . . rather than the data stored by the first thread.lu load last use operation.cv Cache as volatile (consider cached system memory lines stale. any existing cache lines that match the requested address in L1 will be evicted. if the line is fully covered. The compiler / programmer may use ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.Chapter 8. but multiple L1 caches are not coherent for global data. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. January 24. When ld.cs. The ld. bypassing the L1 cache. . Instruction Set 8. evict-first. The default load instruction cache operation is ld.ca loads cached in L1.cs Cache streaming. 2010 109 . Cache Operators PTX 2.lu Last use.cs is applied to a Local window address.lu operation.cv to a frame buffer DRAM address is the same as ld. . Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Operator .lu instruction performs a load cached streaming operation (ld.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.0 introduces optional cache operators on load and store instructions.1. likely to be accessed once.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The cache operators require a target architecture of sm_20 or later. The ld. A ld. Use ld. not L1).ca. As a result of this request.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. likely to be accessed again. the cache operators have the following definitions and behavior. it performs the ld. The ld. Global data is coherent at the L2 level. the second thread may get stale L1 cache data.ca. when applied to a local address. and a second thread loads that address via a second L1 cache with ld. Table 77.cg to cache loads only globally.cs) on global addresses.cg Cache at global level (cache in L2 and below.7. For sm_20 and later.5. and cache only in the L2 cache. invalidates (discards) the local L1 line following the load. The ld. to allow the thread program to poll a SysMem location written by the CPU. If one thread stores to global memory via one L1 cache.

cg to cache global store data only globally. bypassing its L1 cache. and discard any L1 lines that match. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. but st. which writes back cache lines of coherent cache levels with normal eviction policy.cg is the same as st. 2010 . to allow a CPU program to poll a SysMem location written by the GPU with st. .wt.wt store write-through operation applied to a global System Memory address writes through the L2 cache. The st.cs Cache streaming. Future GPUs may have globally-coherent L1 caches. st. Global stores bypass L1. In sm_20. regardless of the cache operation. likely to be accessed once. If one thread stores to global memory.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. bypassing the L1 cache.0 Table 78. Addresses not in System Memory use normal write-back. and marks local L1 lines evict-first.PTX ISA Version 2.ca. The default store instruction cache operation is st. and a second thread in a different SM later loads from that address via a different L1 cache with ld. in which case st.wb could write-back global store data from L1.cg to local memory uses the L1 cache. . the second thread may get a hit on stale L1 cache data. not L1).ca loads.wt Cache write-through (to system memory).wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. Use st.wb.cg Cache at global level (cache in L2 and below. However. and cache only in the L2 cache. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. Operator . . 110 January 24.wb for global data. rather than get the data from L2 or memory stored by the first thread. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. The st.

The generic address of a variable in global. avar. d = &label. . .f32 mov.a. within the variable’s declared state space Notes Although only predicate and bit-size types are required. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. d = &avar. Take the non-generic address of a variable in global.Chapter 8.e.u64. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. // address is non-generic. mov. local. addr. variable in an addressable memory space. or shared state space may be taken directly using the cvta instruction. Write register d with the value of a. alternately.shared state spaces. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.type mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.global. Instruction Set Table 79.u32 mov.type mov. d. label. k. label. mov.f32 mov. For variables declared in .u32 d.b32.v.s32. i. 2010 111 .local.f32. . the address of the variable in its state space) into the destination register. the generic address of a variable declared in global. or shared state space. local. u. and . .u32 mov.u16 mov.e.type = { .pred. immediate.u16. d. . special register.s16. Operand a may be a register.type d.type mov.const. the parameter will be copied onto the stack and the address will be in the local state space.b64. ptr. Introduced in PTX ISA version 1. . . or function name.b16. d..s64.f64 }. // get address of variable // get address of label or function . mov places the non-generic address of the variable (i. mov. ptr. .f64 requires sm_13 or later. d = sreg. .0. Semantics d = a. Description .. A[5].u32. Note that if the address of a device function parameter is moved to a register. A. . . local. .1. a. sreg. myFunc.0.

b. a[32. a[8.z. %r1.7]. .g. a[48. a[16.y.u8 // unpack 32-bit elements from . Supported on all target architectures.15].31] } // unpack 8-bit elements from .b8 r. d.y << 8) d = a.x | (a. 2010 . {lo.u16 %x is a double.x.b32 { d. d.23].{x.z. {r... d.0.y.31] } // unpack 16-bit elements from .%r1. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.y } = { a[0. .hi are .x.type = { . Both the overall size of the vector and the size of the scalar must match the size of the instruction type.y << 16) | (a. d.b32 %r1..31].b32 mov.x | (a.x.15].b16 { d.b32 { d. d.15] } // unpack 8-bit elements from . For bit-size types.w } = { a[0.. a[16.b64 112 January 24..a have type ..63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.15]..w } = { a[0.{a.y. a[24.b64 mov.7].w have type .x | (a. lo.x..b64 { d.g.47]. d. a[32.b64 // pack two 32-bit elements into ..y } = { a[0.w << 24) d = a.b16 // pack four 8-bit elements into .a}..x.b32 // pack four 16-bit elements into .w}.y << 32) // pack two 8-bit elements into .b64 { d.z << 16) | (a.z << 32) | (a.z.hi}. or write vector register d with the unpacked values from scalar register a.b.. // // // // a.0 Table 80.31].b32 mov. d. d..b16. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b64 }.x | (a. Semantics d = a.b have type . a[16. a[8. d.type d.y << 16) d = a.x | (a. a.w << 48) d = a. Description Write scalar register d with the packed value of vector register a.y << 8) | (a.b}. .63] } // unpack 16-bit elements from .PTX ISA Version 2. mov. %x.y..y } = { a[0.b32 // pack two 16-bit elements into .b32.u32 x. mov..z.

[a]. The value loaded is sign-extended to the destination register width for signed integers. Instruction Set Table 81. .. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.global and . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. [a]. .vec.cg. .local. A destination register wider than the specified type may be used.ss}{.cv }. Description Load register variable d from the location specified by the source address operand a in specified state space. *(a+immOff).type ld.volatile. ld{. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f16 data may be loaded using ld.b8. ld.type .ss}.cop}. The address size may be either 32-bit or 64-bit.type = { . .f64 }.shared }. [a]. 2010 113 . . .volatile. Cache operations are not permitted with ld. . .0.ss}{. Generic addressing and cache operations introduced in PTX ISA 2.b16. . ld.Chapter 8.type d.volatile{. .1. d.s32. The address must be naturally aligned to a multiple of the access size. . and is zeroextended to the destination register width for unsigned and bit-size types. .shared spaces to inhibit optimization of references to volatile memory. Addresses are zero-extended to the specified width as needed. If no state space is given.u64. ld introduced in PTX ISA version 1. . .global. an integer or bit-size type register reg containing a byte address. or [immAddr] an immediate absolute byte address (unsigned.ss = { . . . PTX ISA Notes January 24.u32. *a.reg state space. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s8.const space suffix may have an optional bank number to indicate constant banks other than bank zero.s16.type ld{.volatile may be used with . If an address is not properly aligned.s64. In generic addressing. .vec. . . d.cop = { . 32-bit). This may be used.ss}. Within these windows. Generic addressing may be used with ld.ca.vec = { . perform the load using generic addressing.lu.u8. . and truncated if the register width exceeds the state space address width for the target architecture. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. i. the resulting behavior is undefined.const.0. i. . to enforce sequential consistency between threads accessing shared memory. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .v4 }. or the instruction may fault.b64. d. Semantics d d d d = = = = a.b16. and then converted to .e.b32.u16.f32. .cop}. [a].param. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . an address maps to the corresponding location in local or shared memory. for example.f64 using cvt. an address maps to global memory unless it falls within the local memory window or the shared memory window.volatile introduced in PTX ISA version 1. The .volatile{. 32-bit).e.v2.cs. . . *(immAddr).f32 or .

b32 ld. // access incomplete array x. 2010 .[240].f16 d.[buffer+64].local.f64 requires sm_13 or later. %r.b64 ld.%r.b32 ld.v4. // negative offset %r.f32. ld.b32 ld.f32 ld. x.[p+4].[p+-8].[a]. d.[fs]. Generic addressing requires sm_20 or later.0 Target ISA Notes ld.const[4].global. // immediate address %r.shared. Q.const. Cache operations require sm_20 or later.s32 ld.[p].b16 cvt.global.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. // load .PTX ISA Version 2.local.

ldu. . . Semantics d d d d = = = = a.global.f32. the resulting behavior is undefined. For ldu. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e.[a]. [areg] a register reg containing a byte address. The address must be naturally aligned to a multiple of the access size.s8.ss}. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The value loaded is sign-extended to the destination register width for signed integers.b16.b8. Introduced in PTX ISA version 2.ss = { .b16. ldu.type ldu{. *(immAddr). . .v4 }.v4.e.global.type d.f32 Q. . Addresses are zero-extended to the specified width as needed.type = { .u32.Chapter 8.0.ss}. only generic addresses that map to global memory are legal.s32. *(a+immOff). ldu{. . A destination register wider than the specified type may be used.[p]. PTX ISA Notes Target ISA Notes Examples January 24.b64.f64 using cvt. In generic addressing.vec.s16. Instruction Set Table 82. If no state space is given. . .f64 requires sm_13 or later. and then converted to .global }. an address maps to global memory unless it falls within the local memory window or the shared memory window.u64.u16. .f32 d.reg state space. A register containing an address may be declared as a bit-size type or integer type.[p+4].b32 d. [a]. The addressable operand a is one of: [avar] the name of an addressable variable var.f32 or . [a]. If an address is not properly aligned. Within these windows. The address size may be either 32-bit or 64-bit. . or [immAddr] an immediate absolute byte address (unsigned. ldu. 32-bit). . . and truncated if the register width exceeds the state space address width for the target architecture.f64 }.v2. an address maps to the corresponding location in local or shared memory. // load from address // vec load from address . ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. . // state space .b32. i. The data at the specified address must be read-only.vec = { . i. 2010 115 . *a. perform the load using generic addressing. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.s64.f16 data may be loaded using ldu. 32-bit). . d. or the instruction may fault. where the address is guaranteed to be the same across all threads in the warp. and is zeroextended to the destination register width for unsigned and bit-size types. ldu.u8.. .global.

f64 }.volatile introduced in PTX ISA version 1. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.volatile{. i.1.global and .reg state space. { .type = = = = {. an integer or bit-size type register reg containing a byte address.. 2010 .volatile.0 Table 83. A source register wider than the specified type may be used. PTX ISA Notes Target ISA Notes 116 January 24. and truncated if the register width exceeds the state space address width for the target architecture.cop}. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .s16. The address size may be either 32-bit or 64-bit. Addresses are zero-extended to the specified width as needed. or [immAddr] an immediate absolute byte address (unsigned.s32.u64.PTX ISA Version 2. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. i. In generic addressing. .type st.b32. b.b16.s64. b.e.volatile may be used with .s8. .vec. b. . or the instruction may fault. . . Cache operations require sm_20 or later. . Cache operations are not permitted with st. st. The lower n bits corresponding to the instruction-type width are stored to memory. Semantics d = a. *d = a.b64. . If an address is not properly aligned.f32. [a].ss}{.e.vec . . Within these windows.cs. Generic addressing and cache operations introduced in PTX ISA 2. The address must be naturally aligned to a multiple of the access size. the resulting behavior is undefined. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.wt }. . .b8.ss . to enforce sequential consistency between threads accessing shared memory. 32-bit). st introduced in PTX ISA version 1. [a]. . This may be used. *(immAddr) = a. perform the store using generic addressing.0. st.local. for example. . . 32-bit). .vec. Generic addressing requires sm_20 or later.volatile{.ss}.shared spaces to inhibit optimization of references to volatile memory.cop .ss}{.f16 data resulting from a cvt instruction may be stored using st. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. { .wb. .shared }.v4 }.type st{.b16. If no state space is given. . .f64 requires sm_13 or later. { . st{.u16. [a]. . b. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. *(d+immOffset) = a.v2. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type .type [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. Generic addressing may be used with st. .cg.cop}.volatile.0. an address maps to the corresponding location in local or shared memory. st.u8.global.u32.ss}.

[q+4].v4. [fs].local.a.global.Chapter 8.b16 [a].b32 st.s32 st.s32 cvt.f32 st.local.global.b.a. [p].%r.Q.local.%r. 2010 117 .b32 st.r7.f32 st. // %r is 32-bit register // store lower 16 bits January 24. [q+-8].f16. Instruction Set Examples st. // negative offset [100]. // immediate address %r.

Within these windows. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.L1.global. [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.level = { . 32-bit).0.e. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. The address size may be either 32-bit or 64-bit. prefetch and prefetchu require sm_20 or later. .global. i.space = { .level prefetchu.L1 [a].L1 [ptr]. // prefetch to data cache // prefetch to uniform cache . the prefetch uses generic addressing. A prefetch into the uniform cache requires a generic address.0 Table 84. an address maps to global memory unless it falls within the local memory window or the shared memory window. Addresses are zero-extended to the specified width as needed.local }. In generic addressing. an address maps to the corresponding location in local or shared memory. . If no state space is given. and no operation occurs if the address maps to a local or shared memory location. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. and truncated if the register width exceeds the state space address width for the target architecture. prefetchu.PTX ISA Version 2. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. in specified state space.L1 [addr]. 118 January 24. 2010 . .L2 }.space}. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. A prefetch to a shared memory location performs no operation. 32-bit). a register reg containing a byte address. prefetch{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. or [immAddr] an immediate absolute byte address (unsigned. prefetch.

u32.shared }. the generic address of the variable may be taken using cvta.global isspacep.global.size cvta. a. cvta requires sm_20 or later. isspacep. Instruction Set Table 85. When converting a generic address into a global. p.space.space = { .u32. // get generic address of svar cvta. For variables declared in global. or shared state space. The source address operand must be a register of type .global.local. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.local.to.genptr. .u64 or cvt.shared.u64. The destination register must be of type . . 2010 119 . isspacep.shared isglbl.space. PTX ISA Notes Target ISA Notes Examples Table 86. Use cvt.u64 }.global. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.u32 or . cvta. gptr.size p. or shared address. local. cvta. January 24.local isspacep. .pred. a. isspacep requires sm_20 or later.lptr. a. var.Chapter 8.size . .space = { .u32 p.space. sptr.u32 p. p. Description Convert a global.0. or vice-versa.u64. islcl. Introduced in PTX ISA version 2.space p. or shared address cvta. . isshrd.pred . Take the generic address of a variable declared in global. lptr. // convert to generic address // get generic address of var // convert generic address to global. // local. or shared address to a generic address.size = { . svar.local. or vice-versa.u32 gptr. or shared state space to generic.u32 to truncate or zero-extend addresses. A program may use isspacep to guard against such incorrect behavior. cvta. The source and destination addresses must be the same size. local. local. local. // result is . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. local. . or shared state space.to.shared }.0. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.

PTX ISA Version 2. . Note that saturation applies to both signed and unsigned integer types. .rmi round to nearest integer in direction of negative infinity . d = convert(a). Integer rounding modifiers: .ftz}{.e.rzi round to nearest integer in the direction of zero .u64. // integer rounding // fp rounding . The compiler will preserve this behavior for legacy PTX code. .ftz}{. . The optional . choosing even integer if source is equidistant between two integers. .sat}.dtype.rni.ftz.dtype.f32..rz. i. .frnd = { . Saturation modifier: . . .sat is redundant. . the result is clamped to the destination range by default.s64. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.. a.ftz.s8. 2010 . .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.ftz modifier may be specified in these cases for clarity.ftz.ftz. and for same-size float-tofloat conversions where the value is rounded to an integer. Description Semantics Integer Notes Convert between different types and sizes.e. . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.f32.dtype.atype = { . .f32 float-to-integer conversions and cvt. i. subnormal numbers are supported. .f16.u32.frnd}{.s16.rm.sat}. .atype cvt{.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. subnormal inputs are flushed to signpreserving zero. cvt{. sm_1x: For cvt. .rzi. Note: In PTX ISA versions 1.rn.u8. For float-to-integer conversions. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.f32 float-to-integer conversions and cvt.f32 float-tofloat conversions with integer rounding.sat limits the result to MININT. Integer rounding is required for float-to-integer conversions. a.rp }. .MAXINT for the size of the operation. Integer rounding is illegal in all other instances.rni round to nearest integer.s32. For cvt.4 and earlier. subnormal inputs are flushed to signpreserving zero. .f64 }.irnd}{.0 Table 87. the . .irnd = { .sat For integer destination types.dtype.rpi }.u16. . 120 January 24. . .f32. d.rmi.atype d.f32 float-tofloat conversions with integer rounding.dtype = .

single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. The optional .s32 f. Introduced in PTX ISA version 1.f32.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.y.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). Subnormal numbers: sm_20: By default.f32. result is fp cvt. 2010 121 .rn mantissa LSB rounds to nearest even . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . Modifier . // note . cvt.f32.f16. NaN results are flushed to positive zero.sat For floating-point destination types.0].ftz behavior for sm_1x targets January 24. cvt.4 and earlier.f16.f32.f32 x.y. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. .i. Specifically.f64 requires sm_13 or later.0.rni. cvt. Saturation modifier: .ftz modifier may be specified in these cases for clarity. cvt to or from . // round to nearest int.version is 1. The compiler will preserve this behavior for legacy PTX code.f32.f16. subnormal numbers are supported.f32. The operands must be of the same size.f32 x.0. stored in floating-point format. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.f64 j. and for integer-to-float conversions. Floating-point rounding is illegal in all other instances. Note: In PTX ISA versions 1.f32. The result is an integral value.rm mantissa LSB rounds towards negative infinity . and cvt. if the PTX . and . Applies to . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32 instructions.Chapter 8.s32. . 1. Floating-point rounding modifiers: .f64.r.4 or earlier.rz mantissa LSB rounds towards zero .f64 types. // float-to-int saturates by default cvt.sat limits the result to the range [0.

with the restriction that they correspond 1-to-1 with the 128 possible textures.param . r1. Ability to query fields within texture. cvt. sampler. 2010 . r2.texref tex1 ) { txq.2d. add.6. . and surface descriptors..u32 r5.target options ‘texmode_unified’ and ‘texmode_independent’. texture and sampler information is accessed through a single .width.f32 r1. r3.7. add.f32 r1. and surface descriptors.f32. allowing them to be defined separately and combined at the site of usage in the program.r2. In the unified mode. r3. [tex1]. } = clamp_to_border. and surface descriptors: • • • Static initialization of texture.global . r1. samplers. Texturing modes For working with textures and samplers. r5. In the independent mode.r3. Module-scope and per-entry scope definitions of texture. texture and sampler information each have their own handle.f32 r1. // get tex1’s txq. sampler. sampler. [tex1.0 8. PTX has two modes of operation.f32. r6. PTX supports the following operations on texture.r4}. Example: calculate an element’s power contribution as element’s power/total number of elements.height. r5. The advantage of independent mode is that textures and samplers can be mixed and matched. and surface descriptors.target texmode_independent .v4.b32 r5. and surfaces. but the number of samplers is greatly restricted to 16.f32 r3.b32 r6. r4. = nearest width height tsamp1. sampler. Texture and Surface Instructions This section describes PTX instructions for accessing textures. div.f32 {r1. A PTX module may declare only one texturing mode. mul. the file is assumed to use unified mode. . If no texturing mode is declared. // get tex1’s tex. r5.entry compute_power ( . The advantage of unified mode is that it allows 128 samplers.f2}].. . [tex1].texref handle. The texturing mode is selected using . 122 January 24. {f1.samplerref tsamp1 = { addr_mode_0 filter_mode }. r1.u32 r5.PTX ISA Version 2. add.

Supported on all target architectures.f2. tex txq suld sust sured suq Table 88. [tex_a. Operand c is a scalar or singleton tuple for 1d textures.s32.3d. the sampler behavior is a property of the named texture. . A texture base address is assumed to be aligned to a 16-byte address. The instruction always returns a four-element vector of 32-bit values.u32.r4}.f32 }. An optional texture sampler b may be specified.v4 coordinate vectors are allowed for any geometry. and is a four-element vector for 3d textures. .dtype.Chapter 8. c].r2. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding..v4. [a. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. . PTX ISA Notes Target ISA Notes Examples January 24. d. tex. {f1}]. the square brackets are not required and . sampler_x.v4. with the extra elements being ignored.2d. where the fourth element is ignored.r4}.v4.f4}].5. 2010 123 . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. // Example of independent mode texturing tex.dtype. .dtype = { . // explicit sampler .btype d.1d. If an address is not properly aligned.btype = { .0.r3.btype tex. //Example of unified mode texturing tex. [a. Instruction Set These instructions provide access to texture and surface memory. c]. is a two-element vector for 2d textures.f32 {r1. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. {f1.geom = { .geom.s32.f32 }. b. . [tex_a. or the instruction may fault.e. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.r2.f3.v4.1d.s32. . Description Texture lookup using a texture coordinate vector. If no sampler is specified. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.r3. i.geom.s32 {r1. Unified mode texturing introduced in PTX ISA version 1. Notes For compatibility with prior versions of PTX.3d }.s32.

filter_mode. Description Query an attribute of a texture or sampler.tquery = { . [smpl_B]. txq.b32 d. clamp_ogl. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.addr_mode_0 . sampler attributes are also accessed via a texref argument. linear } Integer from enum { wrap. [a].PTX ISA Version 2.width.b32 %r1.depth . . txq.filter_mode . Integer from enum { nearest. Operand a is a .texref or . [tex_A].width. txq. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. clamp_to_edge. .addr_mode_0. and in independent mode sampler attributes are accessed via a separate samplerref argument. // texture attributes // sampler attributes .normalized_coords }.0 Table 89.addr_mode_0.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). d.5.samplerref variable. addr_mode_1. . [a]. [tex_A].width .height.b32 %r1. mirror. . In unified mode.squery.normalized_coords . addr_mode_2 }.b32 %r1. txq. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.squery = { .b32 txq. 2010 .height .depth. // unified mode // independent mode 124 January 24. Query: .filter_mode.addr_mode_1 . Supported on all target architectures.tquery.

v2.trap clamping modifier. suld. suld. [a. // cache operation none.trap introduced in PTX ISA version 1. If the destination type is . A surface base address is assumed to be aligned to a 16-byte address. Coordinate elements are of type .v4.geom .b32.v4 }. suld. // for suld.e.cg. [a.geom{.zero }.f2. additional clamp modifiers. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.vec. suld. .z.geom{.clamp suld. .u32. b].1d. {x}].clamp field specifies how to handle out-of-bounds addresses: .u32.trap suld.b8 . Instruction Set Table 90. .p.3d. suld.s32 is returned. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp . . [surf_A. {x.p .p requires sm_20 or later. sm_1x targets support only the . // unformatted d. suld.f32 }. .f32 is returned.v4. or . .f3.f32 based on the surface format as follows: If the surface format contains UNORM. The .ca.w}].clamp . is a two-element vector for 2d surfaces.surfref variable. If the destination base type is .b32. . and the size of the data transfer matches the size of destination operand d. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f32.Chapter 8.s32. i. Description Load from surface memory using a surface coordinate vector. or the instruction may fault.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. // formatted . SNORM. .b.v2.cop}. and cache operations introduced in PTX ISA version 2. If an address is not properly aligned.f32. then .b. B. . if the surface format contains SINT data.u32.dtype . Operand b is a scalar or singleton tuple for 1d surfaces.s32. Target ISA Notes Examples January 24.s32.vec . .p is currently unimplemented. 2010 125 .cop . Cache operations require sm_20 or later. suld.p. size and type conversion is performed as needed to convert from the surface sample format to the destination type.y.p. .5.dtype . suld Syntax Texture and Surface Instructions: suld Load from surface memory. The lowest dimension coordinate represents a sample offset rather than a byte offset.s32. or .dtype. suld.r2}. the surface sample elements are converted to .clamp = = = = = = { { { { { { d. suld.3d }. {f1.1d.b64.trap. if the surface format contains UINT data.b . the resulting behavior is undefined. or FLOAT data. then .3d requires sm_20 or later.2d.trap {r1. Operand a is a . .u32 is returned. .f4}. .clamp. G.b performs an unformatted load of binary data.0.. . . [surf_B. Destination vector elements corresponding to components that do not appear in the surface format are not written. .cv }.b16. and A components of the surface format. where the fourth element is ignored.cop}.dtype.cs.trap .zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. . and is a four-element vector for 3d surfaces. // for suld.b.b64 }. b]. then .b supported on all target architectures.b32. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.

or . and cache operations introduced in PTX ISA version 2.cs.z. .trap introduced in PTX ISA version 1.p. .vec .geom{.f32. . sust Syntax Texture and Surface Instructions: sust Store to surface memory.2d. These elements are written to the corresponding surface sample components.b.s32.b // for sust. 2010 .clamp sust.trap sust.clamp . then . Source elements that do not occur in the surface sample are ignored. . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.cop}.clamp. sust. sust.cop}. .trap [surf_A. SNORM.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. and A surface components. c. then . the resulting behavior is undefined. .clamp = = = = = = { { { { { { [a. Coordinate elements are of type .b16.r2}.b supported on all target architectures.wb. If the source type is . or the instruction may fault. // unformatted // formatted .b32. sust.{u32.f2. {x}].0.clamp field specifies how to handle out-of-bounds addresses: .p Description Store to surface memory using a surface coordinate vector.u32. additional clamp modifiers.vec. If an address is not properly aligned.b32. The source vector elements are interpreted left-to-right as R. [surf_B. .geom . then . sust.f32} are currently unimplemented.ctype .3d }. where the fourth element is ignored.3d requires sm_20 or later.p performs a formatted store of a vector of 32-bit data values to a surface sample.trap clamping modifier.e. {x.u32 is assumed. Operand b is a scalar or singleton tuple for 1d surfaces.f3. // for sust.f32.v2. b].f32 }.ctype. sust. The lowest dimension coordinate represents a sample offset rather than a byte offset. A surface base address is assumed to be aligned to a 16-byte address. . Operand a is a . .u32. sust.b. .f4}.trap .v2.p requires sm_20 or later.b64. B.p.clamp .b8 .v4 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32. . c.cop . size and type conversions are performed as needed between the surface sample format and the destination type. Target ISA Notes Examples 126 January 24. The size of the data transfer matches the size of source operand c.b performs an unformatted store of binary data.vec.s32.wt }.surfref variable.5.s32. if the surface format contains SINT data. . if the surface format contains UINT data. sust. is a two-element vector for 2d surfaces.ctype . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap. [a. . b]. .PTX ISA Version 2.. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. If the source base type is . .cg. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. G. Surface sample components that do not occur in the source vector will be written with an unpredictable value.zero }. . sust.p. i.v4.b64 }. sust.f32 is assumed.s32 is assumed. {f1. Cache operations require sm_20 or later. none.p.ctype. The .w}]. The source data is then converted from this type to the surface sample format. or FLOAT data.0 Table 91.1d. and is a four-element vector for 3d surfaces. .geom{. .1d.y.s32.b.3d. sm_1x targets support only the . . {r1.

.3d }. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b32 type. then .trap [surf_A.clamp [a. .b32. // for sured. . .u32.b performs an unformatted reduction on .ctype. 2010 127 .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.1d. .p.u64 data.c.clamp [a.s32 or . Operations add applies to .b32 }.b. r1. .clamp . The instruction type is restricted to . or .2d. sured.clamp. .min.b32. and .min.s32. Reduction to surface memory using a surface coordinate vector.geom.b.p .ctype = { .op. operations and and or apply to .0. January 24. and the data is interpreted as .ctype = { . . where the fourth element is ignored. If an address is not properly aligned. Operand b is a scalar or singleton tuple for 1d surfaces.add.1d. sured requires sm_20 or later. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. // sample addressing .add.s32 types. is a two-element vector for 2d surfaces. the resulting behavior is undefined.surfref variable.zero }. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.max.p.clamp field specifies how to handle out-of-bounds addresses: .u32 and .u32.b32 }. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.b32. .b .y}].s32 types.u64.trap . then . and is a four-element vector for 3d surfaces. .trap sured.and. {x.u32 is assumed.op = { .u64. Instruction Set Table 92. Coordinate elements are of type . .u32. sured. if the surface format contains SINT data.Chapter 8. or the instruction may fault. // for sured. The lowest dimension coordinate represents a sample offset rather than a byte offset. [surf_B. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The . . Operand a is a . .s32. A surface base address is assumed to be aligned to a 16-byte address.b]. sured. i. r1.b].or }.2d.s32.e.clamp = { .s32 is assumed.p performs a reduction on sample-addressed 32-bit data. // byte addressing sured.u32. min and max apply to .geom.c. .geom = { . .. {x}].trap.u32 based on the surface sample format as follows: if the surface format contains UINT data.op.ctype. sured.

. suq. .PTX ISA Version 2. .width. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.query = { . Description Query an attribute of a surface.5.height .b32 d.depth }.width .query.height. 128 January 24.surfref variable.b32 %r1. Supported on all target architectures. suq.width. Query: . [a]. Operand a is a . [surf_A].0 Table 93. 2010 .

Instruction Set 8. Supported on all target architectures.s32 a.eq.Chapter 8. p.s32 d. { instructionList } The curly braces create a group of instructions. Introduced in PTX ISA version 1. If {!}p then instruction Introduced in PTX ISA version 1. used primarily for defining a function body.f32 @!p div. setp. { add.x.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. ratio. @{!}p instruction. Supported on all target architectures.7. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. 2010 129 .0. Threads with a false guard predicate do nothing. mov. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.c.a.0. Execute an instruction or instruction block for threads that have the guard predicate true.0.y. } PTX ISA Notes Target ISA Notes Examples Table 95.b.7. {} Syntax Description Control Flow Instructions: { } Instruction grouping.f32 @q bra L23.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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sync and bar. The reduction operations for bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. Since barriers are executed on a per-warp basis. the final value is written to the destination register in all threads waiting at the barrier. Thus.and and .sync) until the barrier count is met..pred . In addition to signaling its arrival at the barrier.red also guarantee memory ordering among threads identical to membar. while . Barriers are executed on a per-warp basis as if all the threads in a warp are active. if any thread in a warp executes a bar instruction. . bar. thread count. and then safely read values stored by other threads prior to the barrier.red. a{. and d have type . {!}c. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. The barrier instructions signal the arrival of the executing threads at the named barrier. bar. Operand b specifies the number of threads participating in the barrier.popc). Register operands. and bar.sync bar.and).red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.sync 0.red should not be intermixed with bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). it is as if all the threads in the warp have executed the bar instruction. 2010 133 .sync or bar. Only bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Operands a.15. bar. Each CTA instance has sixteen barriers numbered 0.version 2. bar. Register operands. All threads in the warp are stalled until the barrier completes.arrive a{.sync or bar. d.red instruction.red are population-count (. bar.u32. b}.red} introduced in PTX . and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). bar. all-threads-true (.sync without a thread count introduced in PTX ISA 1. and bar. the optional thread count must be a multiple of the warp size.u32 bar. thread count. operands p and c are predicates.Chapter 8. and any-thread-true (. a{. all threads in the CTA participate in the barrier. The result of .arrive does not cause any waiting by the executing threads. Execution in this case is unpredictable. PTX ISA Notes Target ISA Notes Examples bar.popc. the bar.{arrive.red. Once the barrier count is reached.0. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. execute a bar.red performs a reduction operation across threads. Note that a non-zero thread count is required for bar.op = { .red} require sm_20 or later. b}.and.or }. When a barrier completes. b}. a.red delays the executing threads (similar to bar.arrive using the same active barrier.popc is the number of threads with a true predicate. it simply marks a thread's arrival at the barrier. the waiting threads are restarted without delay. {!}c. bar.red performs a predicate reduction across the threads participating in the barrier. b. Instruction Set Table 100.cta.or). b. bar. bar. p. and the barrier is reinitialized so that it can be immediately reused. threads within a CTA that wish to communicate via memory can store to memory. Thus.op. January 24. If no thread count is specified.sync with an immediate barrier number is supported for sm_1x targets. Description Performs barrier synchronization and communication within a CTA.{arrive.sync and bar.0.arrive. In conditionally executed code.

version 2.g.sys Waits until all prior memory requests have been performed with respect to all clients.sys }. membar.cta. red or atom) has been performed when the value written has become visible to other clients at the specified level. Waits until prior memory reads have been performed with respect to other threads in the CTA.{cta. global.gl.cta.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.0 Table 101. A memory write (e. this is the appropriate level of membar. by st. 134 January 24. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.cta Waits until all prior memory writes are visible to other threads in the same CTA.level = { . membar.PTX ISA Version 2.gl} introduced in PTX .cta.gl. membar.sys requires sm_20 or later. that is. . membar.gl will typically have a longer latency than membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar. or system memory level.sys.version 1. membar. membar. For communication between threads in different CTAs or even different SMs. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. . Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.g. membar.gl} supported on all target architectures.{cta. when the previous value can no longer be read. 2010 . Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.sys introduced in PTX .gl. A memory read (e. PTX ISA Notes Target ISA Notes Examples membar.0. membar. membar. level describes the scope of other clients for which membar is an ordering event.4. membar. and memory reads by this thread can no longer be affected by other thread writes. .sys will typically have much longer latency than membar. membar.level. including thoses communicating via PCI-E such as system and peer-to-peer memory.

Addresses are zero-extended to the specified width as needed. . [a]. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. The bit-size operations are and. xor.u64 .b64.f32 Atomically loads the original value at location a into destination register d. .. i. In generic addressing.op. min. and exch (exchange).exch. or [immAddr] an immediate absolute byte address. or the instruction may fault. The integer operations are add. .op = { .b]. .type d. max. d. an address maps to the corresponding location in local or shared memory.global. The address size may be either 32-bit or 64-bit.type = { . b. and max operations are single-precision.g.dec. The address must be naturally aligned to a multiple of the access size.b32. c. For atom. .f32 }.min. . or.f32. min. . .type atom{. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. .or. atom{. the resulting behavior is undefined. min.and. 32-bit operations.cas. an address maps to global memory unless it falls within the local memory window or the shared memory window. and stores the result of the specified operation at location a.u32 only . . . The floating-point operations are add. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. by inserting barriers between normal stores and atomic operations to a common address.e.inc. and max.space}.op. .b64 . . a de-referenced register areg containing a byte address.s32. or by using atom.space}. i. . .add. . and truncated if the register width exceeds the state space address width for the target architecture. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. The floating-point add. atom.u32.b32. Within these windows. If no state space is given. performs a reduction operation with operand b and the value in location a. cas (compare-and-swap). Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. Operand a specifies a location in the specified state space.xor. . 2010 135 . .. . If an address is not properly aligned. e.s32. overwriting the original value.u32.e.Chapter 8. dec.space = { . The inc and dec operations return a result in the range [0. inc. b. A register containing an address may be declared as a bit-size type or integer type. accesses to local memory are illegal. Description // // // // // . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.exch to store to locations accessed by other atomic operations.b32 only . [a]. Instruction Set Table 102.s32. perform the memory accesses using generic addressing.u32. January 24.add.shared }. . .u64.max }.

64-bit atom.global. : r. : r-1.add. atom. d.[a]. atom. s) = (r >= s) ? 0 dec(r.exch} requires sm_12 or later. Introduced in PTX ISA version 1. s) = s. b.b32 d. : r+1. 2010 .s32 atom.max} are unimplemented. c) operation(*a.t) = (r == s) ? t operation(*a. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. *a = (operation == cas) ? : } where inc(r.{min.0.shared operations require sm_20 or later.my_new_val. Release Notes Examples @p 136 January 24.0.{add.cas.0 Semantics atomic { d = *a.add. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.PTX ISA Version 2.shared requires sm_12 or later. Use of generic addressing requires sm_20 or later. atom. d.cas.shared.s. b). 64-bit atom. atom. s) = (r > s) ? s exch(r.[x+4].f32.global. atom.1.f32 atom.max.f32 requires sm_20 or later. cas(r.my_val.[p].global requires sm_11 or later.

. . . and max. or the instruction may fault.u64. If an address is not properly aligned. Description // // // // .and. . min. dec. or by using atom. The integer operations are add. If no state space is given. s) = (r > s) ? s : r-1.u32. . .u32. The address size may be either 32-bit or 64-bit. . i. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. e.min.b64. or. an address maps to the corresponding location in local or shared memory.type [a]. max.Chapter 8.s32. . .s32. an address maps to global memory unless it falls within the local memory window or the shared memory window. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.b32 only . January 24.dec. by inserting barriers between normal stores and reduction operations to a common address. and max operations are single-precision.b32. Within these windows. red{.. perform the memory accesses using generic addressing.f32 Performs a reduction operation with operand b and the value in location a.type = { .b]. b). 32-bit operations. s) = (r >= s) ? 0 : r+1.or. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . a de-referenced register areg containing a byte address. accesses to local memory are illegal.u32. Addresses are zero-extended to the specified width as needed.s32. . the resulting behavior is undefined. dec(r.add. Operand a specifies a location in the specified state space. min. . b. The floating-point add. . where inc(r.e. Semantics *a = operation(*a.f32.space}. The floating-point operations are add.u32 only . the access may proceed by silently masking off low-order address bits to achieve proper rounding.global. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.inc.op.op = { . red. inc. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. .shared }. In generic addressing. Notes Operand a must reside in either the global or shared state space.xor. overwriting the original value. .add. i.max }. The inc and dec operations return a result in the range [0. min. For red.u64 .exch to store to locations accessed by other reduction operations. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.e. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.g. 2010 137 ..f32 }. . The bit-size operations are and. Instruction Set Table 103. The address must be naturally aligned to a multiple of the access size. and truncated if the register width exceeds the state space address width for the target architecture. and stores the result of the specified operation at location a. . A register containing an address may be declared as a bit-size type or integer type. and xor. . or [immAddr] an immediate absolute byte address.space = { .

max} are unimplemented.my_val. red.2.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.global.shared.shared requires sm_12 or later. Release Notes Examples @p 138 January 24. 2010 . red.f32 requires sm_20 or later.PTX ISA Version 2.f32 red. 64-bit red.1. 64-bit red.max.0.global requires sm_11 or later red.and.global.shared operations require sm_20 or later. red.add.f32.s32 red.add.b32 [a]. [p].{min. [x+4]. Use of generic addressing requires sm_20 or later. red.add requires sm_12 or later.

uni }. Note that vote applies to threads in a single warp.mode = { . vote.any True if source predicate is True for some active thread in warp. In the ‘ballot’ form.ballot.ballot.uni.ballot.b32 p. where the bit position corresponds to the thread’s lane id. vote requires sm_12 or later.mode. Negate the source predicate to compute . {!}a. The destination predicate value is the same across all threads in the warp. // get ‘ballot’ across warp January 24. Negating the source predicate also computes . . . vote. vote. Instruction Set Table 104.all. Negate the source predicate to compute .pred d.p.any.Chapter 8.b32 d. // ‘ballot’ form.q. not across an entire CTA.all True if source predicate is True for all active threads in warp.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.none.ballot. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.all.b32 requires sm_20 or later. {!}a. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. 2010 139 .q.2. Description Performs a reduction of the source predicate across threads in a warp.pred vote. The reduction modes are: .pred vote.uni.not_all. r1. vote. vote. p. .uni True if source predicate has the same value in all active threads in warp. returns bitmask . .

// 32-bit scalar operation. .bsel}.btype = { .bsel = { . taking into account the subword destination size in the case of optional data merging. . 4.min. Using the atype/btype and asel/bsel specifiers. with optional secondary operation vop.asel = . 2. . or word values from its source operands.dsel.atype = .s32 }. half-word.u32 or . .atype. 2010 .dtype. all combinations of dtype.7.or zero-extend byte.dtype.s32) is specified in the instruction type. Video Instructions All video instructions operate on 32-bit register operands.btype{. The general format of video instructions is as follows: // 32-bit scalar operation. . . b{.dsel = . with optional data merge vop.b1. . c.asel}.asel}. vop. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). The source and destination operands are all 32-bit registers. . a{.h1 }. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.u32.btype{. extract and sign.9.b3.0 8. a{. 140 January 24. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. perform a scalar arithmetic operation to produce a signed 34-bit result.secop d. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. and btype are valid. .atype.max }. c. a{. b{.atype. The type of each operand (. the input values are extracted and signor zero.s33 values. b{.h0. . The sign of the intermediate result depends on dtype. The primary operation is then performed to produce an .sat} d.sat}.sat} d.dtype = . atype.asel}.PTX ISA Version 2.bsel}. 3.extended internally to .b2. optionally clamp the result to the range of the destination type. to produce signed 33-bit input values. .secop = { .s34 intermediate result.dtype.add.bsel}.btype{.b0.

s33 c) { switch ( secop ) { . . c).s33 optSecOp(Modifier secop.h1: return ((tmp & 0xffff) << 16) case . switch ( dsel ) { case .b1: return ((tmp & 0xff) << 8) case .s33 tmp. tmp. as shown in the following pseudocode. S16_MIN ).b3: if ( sign ) return CLAMP( else return CLAMP( case . } } . c). .h0: return ((tmp & 0xffff) case . tmp. S32_MAX.s33 optMerge( Modifier dsel.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.add: return tmp + c. Bool sign. . S8_MIN ). Instruction Set . .b3: return ((tmp & 0xff) << 24) default: return tmp. S32_MIN ). 2010 141 .h0. Modifier dsel ) { if ( !sat ) return tmp.s33 optSaturate( . The sign of the c operand is based on dtype.b0: return ((tmp & 0xff) case . .s33 tmp. U32_MAX.s34 tmp. Bool sat. January 24. tmp. U16_MAX.Chapter 8. .s33 c ) switch ( dsel ) { case . . U32_MIN ). The lower 32-bits are then written to the destination operand.b1. tmp.min: return MIN(tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). .b0. U8_MIN ). . c). .b2: return ((tmp & 0xff) << 16) case . U16_MIN ). c). default: return tmp. S8_MAX. . U8_MAX. tmp. S16_MAX. c). c). c).b2.max return MAX(tmp.

dtype . b{. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. Integer byte/half-word/word minimum / maximum.op2 d.h0. r1.bsel}. c ). r2.op2 Description = = = = { vadd. vop. tb = partSelectSignExtend( b. with optional data merge vop. Semantics // saturate.b1.asel}.s32. dsel ). vmax }.asel = . a{.asel}. vabsdiff. r3. r3. atype.b0. r2. vsub vabsdiff vmin. vmin. { . bsel ). .s32. c.sat.b2. vmax Syntax Integer byte/half-word/word addition / subtraction. a{. vmax require sm_20 or later.h1.dtype.h0. tmp = MIN( ta.add. vadd.btype{. Integer byte/half-word/word absolute value of difference.dsel . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vmax vadd. . . . // optional merge with c operand 142 January 24. . c ).min. Perform scalar arithmetic operation with optional saturate.h1 }. vmin.atype. tmp = ta – tb. .dsel. r3.u32.s32.u32.asel}.sat vabsdiff.btype{. r2. b{. tmp. tb ).bsel}.s32.max }.dtype. 2010 . .h0.bsel}.s32. tmp. r1. btype. // 32-bit scalar operation.atype. vabsdiff. Video Instructions: vadd.sat} d. and optional secondary arithmetic operation or subword data merge. vsub.s32. asel ). tmp = | ta – tb |.b2. r1. tb ).sat}. tmp = MAX( ta.s32 }. c.h1. d = optSecondaryOp( op2.add r1.sat vsub.b0.0 Table 105. vsub. . vsub.0.atype. vabsdiff. b{. with optional secondary operation vop.atype = . a{. r2.s32.sat} d. // extract byte/half-word/word and sign. c.bsel = { .btype = { .sat vmin. .u32. sat.btype{. vadd.or zero-extend based on source operand type ta = partSelectSignExtend( a. . // optional secondary operation d = optMerge( dsel. // 32-bit scalar operation.b3.s32.vop .dtype. r3.PTX ISA Version 2. taking into account destination type and merge operations tmp = optSaturate( tmp. c. .s32.b0. isSigned(dtype). vmin.s32.

taking into account destination type and merge operations tmp = optSaturate( tmp.b0. with optional secondary operation vop.atype. case vshr: tmp = ta >> tb. vop. { . Instruction Set Table 106.or zero-extend based on source operand type ta = partSelectSignExtend( a. c.clamp && tb > 32 ) tb = 32. vshr }.atype. .wrap }.h1 }. . isSigned(dtype). Video Instructions: vshl.sat}{.wrap r1.clamp . . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.dsel.u32.sat}{.sat}{. atype.u32{.max }.0. with optional data merge vop. . c. tb = partSelectSignExtend( b. vshr require sm_20 or later.s32 }.op2 Description = = = = = { vshl.asel}. tmp. .atype.b2.u32.bsel}.s32. 2010 143 . unsigned shift fills with zero.b3. Signed shift fills with the sign bit. vshr: Shift a right by unsigned amount in b with optional saturate. and optional secondary arithmetic operation or subword data merge.bsel}. b{. if ( mode == . dsel ).op2 d. c ). } // saturate.u32. .mode . and optional secondary arithmetic operation or subword data merge. . r3.u32.add.vop . r2. r2.atype = { . // optional secondary operation d = optMerge( dsel. b{. January 24. .u32{. . a{. r3.h0.mode} d.u32 vshr. vshl: Shift a left by unsigned amount in b with optional saturate.u32.wrap ) tb = tb & 0x1f.b1. c ).dtype . . vshl.asel}. // 32-bit scalar operation. tmp.Chapter 8. switch ( vop ) { case vshl: tmp = ta << tb. . b{. if ( mode == . bsel ). // 32-bit scalar operation. asel ).dtype. // default is .h1.mode} d.asel = .dtype. . Semantics // extract byte/half-word/word and sign. Left shift fills with zero. sat.mode}.bsel = { . d = optSecondaryOp( op2.clamp. r1.dtype. a{.asel}. vshr vshl.dsel .min.u32. { .bsel}. vshr Syntax Integer byte/half-word/word left / right shift. a{. vshl.u32{.

{-}c. final signed -(S32 * U32) + S32 // intermediate signed.po) computes (a*b) + c + 1.scale = { . Input c has the same sign as the intermediate result.b3. .atype = . That is. final signed (U32 * S32) + S32 // intermediate signed. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. and scaling.atype.sat}{.u32. this result is sign-extended if the final result is signed.shr15 }. Depending on the sign of the a and b operands. final signed (S32 * S32) . .PTX ISA Version 2. the intermediate result is signed. otherwise. {-}a{.S32 // intermediate signed. {-}b{. “plus one” mode. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.b0. . and the operand negates.scale} d. and zero-extended otherwise.b1.dtype = . vmad. The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed The intermediate result is optionally scaled via right-shift. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.asel}. which is used in computing averages. PTX allows negation of either (a*b) or c.shr7.po mode. final signed (S32 * U32) + S32 // intermediate signed.. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. 2010 . .dtype.asel}. final signed -(U32 * S32) + S32 // intermediate signed.h0.b2.atype. The “plus one” mode (. final signed (U32 * U32) .btype. final signed (S32 * U32) .bsel}. . The source operands support optional negation with some restrictions.s32 }. final signed (S32 * S32) + S32 // intermediate signed. . . final signed (U32 * S32) . final signed -(S32 * S32) + S32 // intermediate signed.S32 // intermediate signed.U32 // intermediate unsigned. Although PTX syntax allows separate negation of the a and b operands. Source operands may not be negated in .dtype. a{. final unsigned -(U32 * U32) + S32 // intermediate signed. (a*b) is negated if and only if exactly one of a or b is negated.bsel}. with optional operand negates. // 32-bit scalar operation vmad. 144 January 24. c. b{.bsel = { . .S32 // intermediate signed.scale} d.asel = .btype{. internally this is represented as negation of the product (a*b). .0 Table 107. Description Calculate (a*b) + c.po{.sat}{.h1 }.btype = { . .

r0.negate ) { c = ~c.sat vmad.shr7: result = (tmp >> 7) & 0xffffffffffffffff.u32. vmad requires sm_20 or later.sat ) { if (signedFinal) result = CLAMP(result.shr15 r0. Instruction Set Semantics // extract byte/half-word/word and sign. vmad. r1. tmp[127:0] = ta * tb. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).0.Chapter 8.u32. U32_MAX. atype.negate ^ b. S32_MIN). lsb = 1.h0.negate ) { tmp = ~tmp.s32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32.u32. -r3. bsel ). 2010 145 .po ) { lsb = 1. lsb = 1. case . lsb = 0. if ( .shr15: result = (tmp >> 15) & 0xffffffffffffffff. S32_MAX. r2. tmp = tmp + c128 + lsb.negate. } else if ( a. r2. asel ). signedFinal = isSigned(atype) || isSigned(btype) || (a. r3. btype.or zero-extend based on source operand type ta = partSelectSignExtend( a. } else if ( c.negate ^ b.h0.negate) || c. else result = CLAMP(result. tb = partSelectSignExtend( b.u32. U32_MIN). r1. switch( scale ) { case . January 24. } if ( .

Semantics // extract byte/half-word/word and sign. a{. with optional data merge vset. d = optSecondaryOp( op2. . r3. c ).btype.s32.op2 Description = = = = . tmp. bsel ).btype = { .0 Table 108.lt.cmp . . . .asel}.bsel}. c. .atype. .ge }.atype . . a{. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.dsel . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.max }. . // 32-bit scalar operation. b{. b{. tb = partSelectSignExtend( b.PTX ISA Version 2. tb.op2 d. c ).btype. with optional secondary arithmetic operation or subword data merge.min. tmp = compare( ta. The intermediate result of the comparison is always unsigned.b1.h1. 146 January 24. c. . r2. atype. vset. .atype.cmp d. .b3. // 32-bit scalar operation.cmp. asel ).asel = .dsel. tmp.u32.lt vset. { . with optional secondary operation vset.u32. r3.asel}. vset.bsel = { . . .h0. and therefore the c operand and final result are also unsigned.gt. // optional secondary operation d = optMerge( dsel.add.eq. a{. b{.bsel}.atype. vset requires sm_20 or later.or zero-extend based on source operand type ta = partSelectSignExtend( a.le.s32 }.asel}.ne r1. .u32.b2.ne.0. r2.b0. { . 2010 .cmp d.btype.bsel}.h1 }. . Compare input values using specified comparison. btype.u32. cmp ) ? 1 : 0. r1.

Supported on all target architectures. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. trap Abort execution and generate an interrupt to the host CPU. with index specified by immediate operand a.0.10. Supported on all target architectures. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Table 111. brkpt Suspends execution Introduced in PTX ISA version 1. there are sixteen performance monitor events.0. 2010 147 .7. Triggers one of a fixed number of performance monitor events. brkpt requires sm_11 or later. brkpt. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. January 24. trap.4. brkpt. numbered 0 through 15. pmevent 7. Table 110. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. trap. The relationship between events and counters is programmed via API calls from the host. pmevent a.Chapter 8. @p pmevent 1. Instruction Set 8. Notes PTX ISA Notes Target ISA Notes Examples Currently.

0 148 January 24. 2010 .PTX ISA Version 2.

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %pm3 January 24. %clock64 %pm0. Special Registers PTX includes a number of predefined. …. %lanemask_ge. which are visible as special registers and accessed through mov or cvt instructions.Chapter 9. %lanemask_gt %clock. %lanemask_le. read-only variables. 2010 149 . %lanemask_lt.

The %tid special register contains a 1D.%tid. cvt. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.z < %ntid.z to %r2 Table 113.y.y. Redefined as . // compute unified thread id for 2D CTA mov. // CTA shape vector // CTA dimensions A predefined.y 0 <= %tid. the fourth element is unused and always returns zero.0. The fourth element is unused and always returns zero.u32 %r0.u32 %r1.%h1.u32 %tid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. %ntid. %tid.x.0. the %tid value in unused dimensions is 0. mov.%ntid. Redefined as .u32. %ntid.x. .y.0. // thread id vector // thread id components A predefined. It is guaranteed that: 0 <= %tid. %ntid.u32 type in PTX 2. %tid component values range from 0 through %ntid–1 in each CTA dimension. mov. PTX ISA Notes Introduced in PTX ISA version 1. Every thread in the CTA has a unique %tid.z PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures.u32 %h1. // legacy PTX 1.v4. per-thread special register initialized with the thread identifier within the CTA. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.z == 0 in 1D CTAs.sreg . or 3D vector to match the CTA shape. The number of threads in each dimension are specified by the predefined special register %ntid.u32 %h2.%tid.z == 1 in 1D CTAs. Supported on all target architectures.z.%r0.v4 .z == 0 in 2D CTAs.y * %ntid.x code Target ISA Notes Examples 150 January 24.sreg . The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. read-only special register initialized with the number of thread ids in each CTA dimension.PTX ISA Version 2. // move tid. mov. read-only.z.y == %tid. 2D.%tid.y < %ntid.x.0 Table 112.u32 %ntid. %tid.x to %rh Target ISA Notes Examples // legacy PTX 1.x code accessing 16-bit component of %tid mov.z == 1 in 2D CTAs.%h2.x. 2010 .%tid.u16 %rh.x. mad.x * %ntid.%tid. CTA dimensions are non-zero.u16 %rh.x 0 <= %tid.y == %ntid.x.x.v4.sreg .%ntid.z.x < %ntid.z).u32 %r0.sreg . // zero-extend tid.u32 type in PTX 2. The total number of threads in a CTA is (%ntid. %ntid. mov.u32 %tid. %tid.0.u16 %r2. .v4 . %tid.u32 %ntid. . Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. .

PTX ISA Notes Target ISA Notes Examples Table 116. A predefined.u32 %r. . Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.Chapter 9. . Table 115. mov. January 24.u32 %nwarpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.u32 %r.u32 %r.g.u32 %warpid.0. Introduced in PTX ISA version 1. The warp identifier will be the same for all threads within a single warp. Supported on all target architectures. For this reason. but its value may change during execution. mov. %warpid. mov. A predefined. read-only special register that returns the maximum number of warp identifiers. read-only special register that returns the thread’s warp identifier. The lane identifier ranges from zero to WARP_SZ-1.3. A predefined. due to rescheduling of threads following preemption. 2010 151 . Introduced in PTX ISA version 1. e.sreg . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Special Registers Table 114.sreg .u32 %laneid. Note that %warpid is volatile and returns the location of a thread at the moment when read. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. . %nwarpid requires sm_20 or later.sreg . Introduced in PTX ISA version 2. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. %laneid.3. %nwarpid. Supported on all target architectures. read-only special register that returns the thread’s lane within the warp.

It is guaranteed that: 1 <= %nctaid.y.x. // CTA id vector // CTA id components A predefined.0.%nctaid.{x. %rh.y. . %rh.PTX ISA Version 2.x.z.v4.y < %nctaid.%ctaid.v4 . // Grid shape vector // Grid dimensions A predefined.sreg . . depending on the shape and rank of the CTA grid.x code Target ISA Notes Examples Table 118.0. mov. Each vector element value is >= 0 and < 65535.v4 . Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. %ctaid.sreg . It is guaranteed that: 0 <= %ctaid.z PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures. Redefined as . The %ctaid special register contains a 1D.x 0 <= %ctaid.0.%ctaid.%nctaid. .x. The fourth element is unused and always returns zero. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u32 mov.y. or 3D vector.u32 %ctaid. mov.u16 %r0.u32 mov.sreg .x code Target ISA Notes Examples 152 January 24.y. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. 2010 . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.536 PTX ISA Notes Introduced in PTX ISA version 1. Redefined as .u32 %ctaid.y 0 <= %ctaid.u32 %nctaid.sreg . The fourth element is unused and always returns zero. %ctaid. The %nctaid special register contains a 3D grid shape vector.x. Supported on all target architectures.u32 %nctaid . // legacy PTX 1. read-only special register initialized with the number of CTAs in each grid dimension.%nctaid. with each element having a value of at least 1.z} < 65.x < %nctaid.0.z < %nctaid.v4.0 Table 117.u32 type in PTX 2. read-only special register initialized with the CTA identifier within the CTA grid.u32 type in PTX 2.x. // legacy PTX 1.u16 %r0.z.%nctaid. 2D.

. mov. Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples January 24. .u32 %r. The SM identifier ranges from 0 to %nsmid-1. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. // initialized at grid launch A predefined.u32 %nsmid. During execution.sreg . Supported on all target architectures.g. Special Registers Table 119. read-only special register initialized with the per-grid temporal grid identifier. Introduced in PTX ISA version 1.sreg . Introduced in PTX ISA version 2. %gridid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. %nsmid. so %nsmid may be larger than the physical number of SMs in the device. e. %smid.u32 %smid.u32 %gridid. mov. Note that %smid is volatile and returns the location of a thread at the moment when read. due to rescheduling of threads following preemption. %nsmid requires sm_20 or later. A predefined. . Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Notes PTX ISA Notes Target ISA Notes Examples Table 120. read-only special register that returns the maximum number of SM identifiers. but its value may change during execution. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.0. Supported on all target architectures. mov. The SM identifier numbering is not guaranteed to be contiguous.3. 2010 153 . The SM identifier numbering is not guaranteed to be contiguous.0. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %r. This variable provides the temporal grid launch number for this context.u32 %r. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.Chapter 9. A predefined.sreg . repeated launches of programs may occur. PTX ISA Notes Target ISA Notes Examples Table 121. where each launch starts a grid-of-CTAs.

sreg .0. A predefined. 2010 . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later. %lanemask_eq.sreg . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. mov.0. Table 124. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. . Introduced in PTX ISA version 2.u32 %lanemask_le. %lanemask_le requires sm_20 or later. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %r. Table 123. A predefined. A predefined. . %lanemask_lt requires sm_20 or later. %lanemask_le.0. mov. 154 January 24.u32 %lanemask_eq. %lanemask_lt.u32 %r.sreg .PTX ISA Version 2.0 Table 122.u32 %r. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.u32 %lanemask_lt. mov.

2010 155 . January 24.sreg . %lanemask_ge requires sm_20 or later.u32 %r.0. mov.u32 %r. Special Registers Table 125.sreg . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_ge. .u32 %lanemask_ge. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt.Chapter 9.u32 %lanemask_gt. %lanemask_gt requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Introduced in PTX ISA version 2.0. A predefined. mov. Table 126. . Introduced in PTX ISA version 2. A predefined.

%pm3. Table 129.PTX ISA Version 2.0 Table 127. Introduced in PTX ISA version 1.%clock64. mov.sreg . Special Registers: %pm0. . %pm1. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.u32 %clock. .u32 r1. Their behavior is currently undefined. %pm3 %pm0. %pm1. Supported on all target architectures. 2010 .3.0. Supported on all target architectures. read-only 64-bit unsigned cycle counter. %clock64 requires sm_20 or later. The lower 32-bits of %clock64 are identical to %clock.u64 %clock64. . read-only 32-bit unsigned cycle counter. Special registers %pm0. …. Introduced in PTX ISA version 2.sreg . %pm2. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm1. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.%clock. 156 January 24. Table 128.0.u32 r1.sreg . Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. mov. Introduced in PTX ISA version 1. %pm2.u32 %pm0. %pm2.%pm0. and %pm3 are unsigned 32-bit read-only performance monitor counters.u64 r1. mov.

minor // major.version 2. Supported on all target architectures.version . Duplicate .version directive. minor are integers Specifies the PTX language version number.version directive.0 . and the target architecture for which the code was generated.1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.target Table 130. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.0. Directives 10.Chapter 10.version 1.version Syntax Description Semantics PTX version number. .version major. Each ptx file must begin with a . Increments to the major number indicate incompatible changes to PTX. PTX File Directives: .version directives are allowed provided they match the original . .version .4 January 24. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. . 2010 157 .

f64 instructions used.target .red}. Requires map_f64_to_f32 if any .texref descriptor.global.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. but subsequent . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. immediately followed by a .texmode_unified . and an error is generated if an unsupported feature is used.target directives can be used to change the set of target features allowed during parsing. with only half being used by instructions converted from . The following table summarizes the features in PTX that vary according to target architecture.5. Target sm_20 Description Baseline feature set for sm_20 architecture. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.PTX ISA Version 2. PTX code generated for a given target can be run on later generation devices. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. where each generation adds new features and retains all features of previous generations.samplerref descriptors.texmode_independent texture and sampler information is bound together and accessed via a single . texmode_independent.texmode_unified) . Note that . A .f64 to . map_f64_to_f32 }. 158 January 24. Supported on all target architectures. PTX File Directives: . The texturing mode is specified for an entire module and cannot be changed within the module.f32. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Adds {atom. texture and sampler information is referenced with independent . PTX features are checked against the specified target architecture. sm_10. Therefore.red}. sm_11. brkpt instructions. Disallows use of map_f64_to_f32. sm_13.0 Table 131. 64-bit {atom.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Requires map_f64_to_f32 if any . vote instructions. 2010 .target directive containing a target architecture and optional platform options. Requires map_f64_to_f32 if any . Texturing mode: (default is .red}. In general.target directive specifies a single target architecture.target Syntax Architecture and Platform target.global. generations of SM architectures follow an “onion layer” model.version directive.0. Adds double-precision support. .shared.f64 instructions used. Description Specifies the set of features in the target architecture for which the current ptx code was generated. Introduced in PTX ISA version 1. Each PTX file must begin with a . Adds {atom.texref and .f64 storage remains as 64-bits. including expanded rounding modifiers.f64 instructions used. A program with multiple . Texturing mode introduced in PTX ISA version 1. texmode_unified. sm_12.

Chapter 10.target sm_20.target sm_13 // supports double-precision . 2010 159 .target sm_10 // baseline target architecture . Directives Examples . texmode_independent January 24.

func Table 132. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Parameters may be referenced by name within the kernel body and loaded into registers using ld. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.b32 %r2.entry . the kernel dimensions and properties are established and made available via special registers. . etc. .param. %nctaid. 2010 .samplerref.b32 x.param instructions.texref. opaque . ld.entry Syntax Description Kernel entry point and body. 160 January 24.entry cta_fft . ld.b32 %r1. In addition to normal parameters.3. … } . Kernel and Function Directives: .entry filter ( .b32 z ) Target ISA Notes Examples [x]. %ntid. and body for the kernel function. store.entry .0 through 1. with optional parameters.reg .0 through 1. parameter variables are declared in the kernel body. e.param.b32 %r<99>. .param . .entry kernel-name kernel-body Defines a kernel entry point name.param instructions. These parameters can only be referenced by name within texture and surface load.g. [z]. parameters. and .0 10.4. The shape and size of the CTA executing the kernel are available in special registers.param space memory and are listed within an optional parenthesized parameter list. parameter variables are declared in the kernel parameter list. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. Semantics Specify the entry point for a kernel program. PTX ISA Notes For PTX ISA version 1.param .b32 %r3.4 and later. [y].5 and later.2.param. and query instructions and cannot be accessed via ld. For PTX ISA versions 1. .surfref variables may be passed as parameters.param { .PTX ISA Version 2. At kernel launch.entry kernel-name ( param-list ) kernel-body . . Supported on all target architectures.b32 y. Parameters are passed via . ld.

PTX ISA 2. Kernel and Function Directives: . Directives Table 133. parameters must be in the register state space. 2010 161 . … Description // return value in fooval January 24.b32 localVar. Release Notes For PTX ISA version 1.func Syntax Function definition. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.b32 rval. . } … call (fooval).b32 N. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Parameters in register state space may be referenced directly within instructions in the function body. Supported on all target architectures.func (ret-param) fname (param-list) function-body Defines a function. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.result.reg .0 with target sm_20 allows parameters in the .b32 rval) foo (.0 with target sm_20 supports at most one return value. . and recursion is illegal.Chapter 10. and supports recursion. mov.func (. … use N.func definition with no body provides a function prototype.f64 dbl) { .reg .0. which may use a combination of registers and stack locations to pass parameters.func fname (param-list) function-body .param space are accessed using ld.reg . if any. including input and return parameters and optional function body. . dbl.reg . val1). implements an ABI with stack. foo.param instructions in the body. The implementation of parameter passing is left to the optimizing translator. other code. (val0. there is no stack.2 for a description of variadic functions.param state space. Parameter passing is call-by-value. ret.x code. Parameters must be base types in either the register or parameter state space. Variadic functions are represented using ellipsis following the last fixed argument.func fname function-body . The parameter lists define locally-scoped variables in the function body. Parameters in . Variadic functions are currently unimplemented.func . PTX 2. A .param and st.

entry directive and its body.maxnreg. the . .PTX ISA Version 2. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. These can be used.pragma The . which pass information to the backend optimizing compiler.maxntid and .maxntid . A general . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. Note that . and the strings have no semantics within the PTX virtual machine model. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.minnctapersm . 2010 . to throttle the resource requirements (e.pragma directives may appear at module (file) scope. at entry-scope. or as statements within a kernel or device function body. for example. Currently. The directives take precedence over any module-level constraints passed to the optimizing backend.3.minnctapersm directives may be applied per-entry and must appear between an .pragma directive is supported for passing information to the PTX backend. registers) to increase total thread count and provide a greater opportunity to hide memory latency.0 10. .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. and .g. The interpretation of .maxntid directive specifies the maximum number of threads in a thread block (CTA). 162 January 24.maxnreg .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).maxntid.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. the . The directive passes a list of strings to the backend. and the . PTX supports the following directives.maxnctapersm (deprecated) .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. The .

. nz Declare the maximum number of threads in the thread block (CTA). Performance-Tuning Directives: .maxntid nx. Supported on all target architectures.maxnreg n Declare the maximum number of registers per thread in a CTA. The actual number of registers used may be less. Introduced in PTX ISA version 1. ny.entry bar .maxnreg .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. ny . for example.maxntid .entry foo .3.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. .maxntid 256 .maxntid 16. the backend may be able to compile to fewer registers. .16. Directives Table 134. Introduced in PTX ISA version 1. 2D.3. Supported on all target architectures. or the maximum number of registers may be further constrained by . Performance-Tuning Directives: .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxctapersm. .maxntid nx . 2010 163 . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. or 3D CTA. The compiler guarantees that this limit will not be exceeded. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid and .entry foo . The maximum number of threads is the product of the maximum extent in each dimension.maxntid Syntax Maximum number of threads in thread block (CTA).Chapter 10.maxntid nx. Exceeding any of these limits results in a runtime error or kernel launch failure.

minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Supported on all target architectures. Optimizations based on .maxnctapersm (deprecated) .minnctapersm generally need . .3.maxnctapersm generally need . if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Introduced in PTX ISA version 2.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxntid 256 .minnctapersm .maxntid to be specified as well.PTX ISA Version 2. Deprecated in PTX ISA version 2.entry foo . . For this reason.minnctapersm 4 { … } 164 January 24.maxntid and .maxnctapersm. The optimizing backend compiler uses .0 as a replacement for . additional CTAs may be mapped to a single multiprocessor. Introduced in PTX ISA version 1. . Optimizations based on .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. However.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0 Table 136. . Supported on all target architectures. Performance-Tuning Directives: .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. . 2010 .entry foo .maxntid 256 .minnctapersm in PTX ISA version 2.maxntid to be specified as well. Performance-Tuning Directives: .maxnctapersm has been renamed to .0.0.

Introduced in PTX ISA version 2. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . or at statementlevel. The interpretation of . . . Directives Table 138.pragma list-of-strings .pragma Syntax Description Pass directives to PTX backend compiler.pragma “nounroll”.pragma directive strings is implementation-specific and has no impact on PTX semantics.Chapter 10. entry-scoped.pragma . The . 2010 165 . Pass module-scoped. Supported on all target architectures. { … } January 24.0. at entry-scope. or statement-level directives to the PTX backend compiler. Performance-Tuning Directives: . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma “nounroll”.entry foo .pragma directive may occur at module-scope.

. 0x63613031. @progbits .2.264-1] . 0x00. Supported on all target architectures. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .4byte int32-list // comma-separated hexadecimal integers in range [0.byte byte-list // comma-separated hexadecimal byte values . 0x61395a5f. 0x5f736f63 .section directive. 0x00.quad int64-list // comma-separated hexadecimal integers in range [0. “”.4. 0x00. The @@DWARF syntax is deprecated as of PTX version 2. 0x00 166 January 24.0 and replaces the @@DWARF syntax.byte 0x00.0.section .4byte 0x000006b5.section . 0x02.4byte 0x6e69616d.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.file . Introduced in PTX ISA version 1. 0x00. 0x00.byte 0x2b.4byte .0 10.4byte label . 0x6150736f. 0x00000364. Deprecated as of PTX 2. @@DWARF dwarf-string dwarf-string may have one of the . 2010 . 0x00 .debug_info .debug_pubnames.232-1] ..loc The .0 but is supported for legacy PTX version 1. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00.PTX ISA Version 2. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. Table 139.section directive is new in PTX ISA verison 2.x code. replaced by . 0x736d6172 .

. Debugging Directives: . 0x00.0.file .debug_pubnames { . 0x00..section section_name { dwarf-lines } dwarf-lines have the following formats: . Source file information.b64 int64-list // comma-separated list of integers in range [0. replaces @@DWARF syntax. Supported on all target architectures. .b32 0x000006b5.debug_info .264-1] . . 0x00 0x61395a5f. 0x63613031.b32 label .232-1] .b32 int32-list // comma-separated list of integers in range [0.0. 0x5f736f63 0x6150736f. 2010 167 .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00. Debugging Directives: .b32 .section . . 0x00.Chapter 10. 0x00.b8 0x2b.section Syntax PTX section definition..b8 byte-list // comma-separated list of integers in range [0.0. . Debugging Directives: .. .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.file filename Table 142.b32 0x6e69616d.loc line_number January 24.loc . 0x736d6172 0x00 Table 141.section . Supported on all target architectures. Source file location. . Supported on all target architectures.b8 0x00. 0x00.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00000364. Directives Table 140.255] . } 0x02.

.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern .b32 foo.global . . Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. . // foo will be externally visible 168 January 24.0 10.global .extern . .6.visible . Linking Directives .0.extern identifier Declares identifier to be defined externally.extern .visible .PTX ISA Version 2.visible identifier Declares identifier to be externally visible. Linking Directives: . Supported on all target architectures.b32 foo.0. // foo is defined in another module Table 144. Supported on all target architectures.visible Table 143. 2010 .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Linking Directives: .

0.3 driver r190 CUDA 3.2 PTX ISA 1.0 CUDA 2.4 PTX ISA 1. CUDA Release CUDA 1.0 driver r195 PTX ISA Version PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.5 PTX ISA 2. The release history is as follows.Chapter 11.1 CUDA 2.0 CUDA 1.1 CUDA 2.2 CUDA 2.3 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.1 PTX ISA 1.0 PTX ISA 1.0 January 24. and the remaining sections provide a record of changes in previous releases. 2010 169 .

1. Instructions testp and copysign have been added.and double-precision div.f32. The mad. 2010 . The mad. When code compiled for sm_1x is executed on sm_20 devices.0 for sm_20 targets. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The . fma.f32 requires sm_20.0 11.1. The changes from PTX ISA 1.0 11.f32 for sm_20 targets.ftz and .f32 require a rounding modifier for sm_20 targets.rp rounding modifiers for sm_20 targets. and mul now support .x code and sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. and sqrt with IEEE 754 compliant rounding have been added.f32 maps to fma. These are indicated by the use of a rounding modifier and require sm_20.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.1. Single-precision add.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. while maximizing backward compatibility with legacy PTX 1.f32 and mad. The goal is to achieve IEEE 754 compliance wherever possible.1.rn. Both fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2.ftz modifier may be used to enforce backward compatibility with sm_1x. mad. The fma. • • • • • 170 January 24.1.sat modifiers. Changes in Version 2. New Features 11.PTX ISA Version 2. sub.rm and . rcp.1. Single.f32 instruction also supports .

New instructions A “load uniform” instruction. atom.ballot. have been added. local. %clock64.lt. ldu. A new directive. Surface instructions support additional . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Instructions bar.zero. vote.red}.popc. Bit field extract and insert instructions. Instruction sust now supports formatted surface stores.clamp and . has been added.sys. January 24. has been added. A “population count” instruction.red. has been added. has been added. Other new features Instructions ld. popc. A system-level membar instruction.1. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. cvta.red}. Instruction cvta for converting global. prefetch. Instructions prefetch and prefetchu have also been added. .minnctapersm to better match its behavior and usage. membar. Instructions {atom. has been added. ldu. brev. bfe and bfi. e. suld. and red now support generic addressing. bfind. clz. Instructions {atom.red.3. New special registers %nsmid.pred have been added.gt} have been added.u32 and bar.1. A “count leading zeros” instruction.or}. 2010 171 .b32. and shared addresses to generic address and vice-versa has been added. Release Notes 11. Cache operations have been added to instructions ld.f32 have been implemented. A “vote ballot” instruction.shared have been extended to handle 64-bit data types for sm_20 targets.le.clamp modifiers. The . %lanemask_{eq.Chapter 11. has been added. prefetchu. Video instructions (includes prmt) have been added.{and.section.arrive instruction has been added. bar now supports optional thread count and register operands.g.2. st. for prefetching to specified level of memory hierarchy. A “bit reversal” instruction.1.1. 11.ge. and sust. .add. A “find leading non-sign bit” instruction. The bar instruction has been extended as follows: • • • A bar. isspacep.maxnctapersm directive was deprecated and replaced with . st. has been added.

where . the correct number is sixteen. Instruction bra.max} are not implemented. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.target sm_1x.1. if .{u32. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.4 and earlier.s32.version is 1.f32} atom.5 and later. To maintain compatibility with legacy PTX code. call suld. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.1. Formatted surface load is unimplemented. Formatted surface store with .red}.0 11. 11.3. Support for variadic functions and alloca are unimplemented.f32.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. {atom. In PTX version 1. Semantic Changes and Clarifications The errata in cvt.f32 type is unimplemented.PTX ISA Version 2. has been fixed. cvt. .p sust.p.{min. 2010 .2. The underlying.s32.4 or earlier. stack-based ABI is unimplemented.u32.5. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.ftz (and cvt for . 172 January 24.ftz for PTX ISA versions 1. or . See individual instruction descriptions for details. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.

. disables unrolling of0 the loop for which the current block is the loop header. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. The “nounroll” pragma is allowed at module.pragma “nounroll”.func bar (…) { … L1_head: . Descriptions of . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. disables unrolling for all loops in the entry function body. L1_body: … L1_continue: bra L1_head.entry foo (…) . . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 173 . Supported only for sm_20 targets.pragma Strings This section describes the .pragma “nounroll”. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Table 145. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.0.Appendix A.pragma “nounroll”. entry-function. L1_end: … } // do not unroll this loop January 24. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Note that in order to have the desired effect at statement level. … @p bra L1_end.pragma strings defined by ptxas. and statement levels. Ignored for sm_1x targets.pragma. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. including loops preceding the . { … } // do not unroll any loop in this function .

PTX ISA Version 2. 2010 .0 174 January 24.

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