NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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..........................................................2.................... 5..........................................2.......................... 44 Rounding Modifiers ............................................1............................................ 42 Arrays as Operands ......................4...................................................................5. 42 Addresses as Operands ....... 5......................................................................................4..5... 38 Initializers ..................4.................. 6.................... 6............. 33 Fundamental Types ....................................................... 5..4.............................. 5..1............... Types........................................................ 44 Scalar Conversions ................................. 43 Vectors as Operands ................. 37 Variable Declarations ............................................................................................3..................................................................................1................. 47 Chapter 7... 6................... 33 Restricted Use of Sub-Word Sizes ....................................1....................7....................... 39 Parameterized Variable Names ... 28 Constant State Space ...1..1..................... 49 ii January 24...... 33 5................. 38 Alignment ... 29 Parameter State Space ......................................................................1........................3...................................................................... Operand Costs ........................................... 25 Chapter 5..........2................................................................ 27 Register State Space ....................................................................1.... 43 Labels and Function Names as Operands ................................. State Spaces ................................... 32 5.......................................................................................5.............................2. 41 Destination Operands ..8..........6.......................... Summary of Constant Expression Evaluation Rules .................................................. 39 5.........6.. Arrays.2........... Types ... Chapter 6...................................1....................................1..................................... State Spaces............................. 5.................1....................3............................2....................3............................... 46 6................................ Instruction Operands.......................................................................................... 41 Source Operands......................... and Surface Types ........................... 32 Texture State Space (deprecated) ............................................................. 6..... 5.............. 34 Variables .. 2010 ................................4............. 5.......................4........... Abstracting the ABI . 41 Using Addresses.......... and Variables ......................... 5..................... 41 6..... Sampler..............................1....................................... 37 Array Declarations .. 27 5............... 5.................................6..... 6.....5....................... 30 Shared State Space........................... 5..... 37 Vectors .............2... and Vectors ....1..........................4.......... 5.....................0 4............................ 6................ 5........ 49 7. 6................... 5............2...............4........................................1...................1....... 5...5........ 43 6................... Texture...........PTX ISA Version 2.............................................4....4.............................................4...............................5..... 29 Local State Space .................. Operand Type Information ..............4......................................4............. 6.... 5.....................................................3......... 28 Special Register State Space ...6.............................4. Type Conversion.1............................................4.. 5...................................................................2.................... 29 Global State Space ............................................................................................. Function declarations and definitions .................... 6......................................................................................................................

....1...............................6... 10........ 8..................7................ 8.2.. 8................................................................................1........4................ Changes from PTX 1....................................... 8.....................1.1............................ 8........................... Instruction Set ..........................................5................................ 169 11................................................................ 2010 iii .................. 157 Specifying Kernel Entry Points and Functions .........................................1...........................7...........1.. 162 Debugging Directives .......................... 58 8.....5............. 132 Video Instructions .......................................................................................................... 60 8....................................................................................................................................................................................................................................................4.............................................3..............................7...................................7............................ 122 Control Flow Instructions . 172 Unimplemented Features Remaining .................................................................. 129 Parallel Synchronization and Communication Instructions .. 62 8.7......................................................................... Format and Semantics of Instruction Descriptions ...2...6................. 104 Data Movement and Conversion Instructions ....6..................................3. Instructions .............3.................................................................... 52 Variadic functions ............. 108 Texture and Surface Instructions ............. 100 Logic and Shift Instructions ....... 140 Miscellaneous Instructions.................. 170 New Features ...................... 160 Performance-Tuning Directives ........2.......................................... 8......... 11..1..........1........................................ Directives ..........................................4........................ 8................. 157 10...................................1....................x ........................... 149 Chapter 10......... 8........................................................... 63 Integer Arithmetic Instructions .1....7.................. 8...... 56 Comparisons ........................... 59 Operand Size Exceeding Instruction-Type Size .... 62 Machine-Specific Semantics of 16-bit Code ................................ PTX Version and Target Directives .. Changes in Version 2...........7...................... 55 Predicated Execution ........................................3............................0 .............. 172 January 24................................... Type Information for Instructions and Operands ..... 11................... 7............. 55 8.... Chapter 9............................................................... 8............................. 8.... 54 Chapter 8..3................. 55 PTX Instructions ........ 170 Semantic Changes and Clarifications .................................................. 8............................. 11................. 8............................7............ 10...........1................7...3............1...................8.......................................................... Divergence of Threads in Control Constructs ................. 57 Manipulating Predicates .. Release Notes .......... 7.............................................. 8......................7.............. 168 Chapter 11................... 8..................... 8............................... 63 Floating-Point Instructions .......................................4.............................7.......2................ 166 Linking Directives ............................2......9....7...........................................................3.....6........................................................ Special Registers .............................10........................1.... 147 8... 10................................................. 81 Comparison and Selection Instructions .................................................................2......... 53 Alloca ..........................................7................................ 62 Semantics .............................. 10.........

.PTX ISA Version 2......... Descriptions of .... 173 iv January 24.......................................... 2010 ....0 Appendix A......pragma Strings..

....................... 64 Integer Arithmetic Instructions: add.......... 47 Operators for Signed Integer................................ 57 Floating-Point Comparison Operators Accepting NaN ........ 19 Predefined Identifiers ........... Table 4............................................................. 66 Integer Arithmetic Instructions: subc ............................ Table 7.............................................................. 27 Properties of State Spaces ............... Table 21.................................................................................................................. Table 10........................................ Table 31........................ 67 Integer Arithmetic Instructions: mad ........... Table 5.................................................... Table 20....... 61 Integer Arithmetic Instructions: add ................................. 18 Reserved Instruction Keywords ................................................................................................................. Table 3............. Unsigned Integer........................ Table 15.... Table 27............ Table 9...... 65 Integer Arithmetic Instructions: addc ................................................... 20 Operator Precedence ................................................................................................ 60 Relaxed Type-checking Rules for Destination Operands....................... Table 23................................................................................................................................... 35 Opaque Type Fields in Independent Texture Mode .......... 65 Integer Arithmetic Instructions: sub.................. Table 16.......... 59 Relaxed Type-checking Rules for Source Operands . 46 Cost Estimates for Accessing State-Spaces ................................ Table 2............................................................. Table 30.............. Table 11.............................. 45 Floating-Point Rounding Modifiers .......................................................................................... 68 Integer Arithmetic Instructions: mul24 ...... 70 Integer Arithmetic Instructions: sad ........ 57 Floating-Point Comparison Operators .................................... Table 22........................... 66 Integer Arithmetic Instructions: mul .. 46 Integer Rounding Modifiers ... Table 29........................................................................................................................ 64 Integer Arithmetic Instructions: sub .................................................................. Table 17...................................... 35 Convert Instruction Precision and Format .............cc ................................... Table 25................................................................................cc ........................... and Bit-Size Types .................. PTX Directives ................................................. Table 19.............. 69 Integer Arithmetic Instructions: mad24 ........ Table 12.... 58 Type Checking Rules ................. Table 24..................................... 28 Fundamental Type Specifiers . 25 State Spaces .............. Table 6................................................... 33 Opaque Type Fields in Unified Texture Mode ...........................................List of Tables Table 1................. Table 28. Table 13................... 23 Constant Expression Evaluation Rules ................................ 58 Floating-Point Comparison Operators Testing for NaN ............................................. Table 8.................................................... Table 14..................................... Table 26.................. Table 18........................................................ 2010 v ................ 71 January 24... Table 32...............................................

........... Table 46................................................................... Table 36............................................................................................................................................ 91 Floating-Point Instructions: min .................................. 75 Integer Arithmetic Instructions: brev ..... Table 39..........................................PTX ISA Version 2.......................... 102 Comparison and Selection Instructions: selp ......................................................... Table 38................. 103 vi January 24......................0 Table 33.......... Table 49....................................... Table 56........................................................................ 101 Comparison and Selection Instructions: setp .............................. Table 48.......... Table 55.............. 71 Integer Arithmetic Instructions: rem ................................................................................................................ Table 59..................................... 95 Floating-Point Instructions: sin ................................. 90 Floating-Point Instructions: abs ................... Table 52................ 94 Floating-Point Instructions: rsqrt ............. 92 Floating-Point Instructions: rcp .................... 85 Floating-Point Instructions: mul ............................................................................................................................................... Table 68.................................... 74 Integer Arithmetic Instructions: clz ................. 76 Integer Arithmetic Instructions: bfe ............... 83 Floating-Point Instructions: add ................ 72 Integer Arithmetic Instructions: min ................................. Table 53........ Table 54.. 84 Floating-Point Instructions: sub ............... 98 Floating-Point Instructions: ex2 .................................. 88 Floating-Point Instructions: div ............... Table 43............ 74 Integer Arithmetic Instructions: bfind ........ 82 Floating-Point Instructions: testp .............................................................................................................................................. Table 45...................................... 99 Comparison and Selection Instructions: set ................. Table 64.......................................................................... 71 Integer Arithmetic Instructions: abs ............................. 96 Floating-Point Instructions: cos ................................ Table 50............................................................................... Table 58. 97 Floating-Point Instructions: lg2 ................................. Table 61............. 103 Comparison and Selection Instructions: slct ....... Table 42.................................................................................................. Table 40............................................... 91 Floating-Point Instructions: neg ....................... Table 41............................................................................................................................................................................................ Table 62.......... Table 47........... Table 65................ 77 Integer Arithmetic Instructions: bfi . Table 69................... Table 51............................................................................ Table 57................................ Integer Arithmetic Instructions: div ....... Table 35....... Table 63........................................................ Table 34....................................................................................... 93 Floating-Point Instructions: sqrt ...... 86 Floating-Point Instructions: fma ............ Table 37..... Table 44.............. 2010 ................................................ 87 Floating-Point Instructions: mad ......................................................................................................... 72 Integer Arithmetic Instructions: neg .................................. 73 Integer Arithmetic Instructions: popc ......... 78 Integer Arithmetic Instructions: prmt ........................ Table 67..................................................... 92 Floating-Point Instructions: max ...... Table 60.............................. 83 Floating-Point Instructions: copysign ................................ 73 Integer Arithmetic Instructions: max .................................................. Table 66........................... 79 Summary of Floating-Point Instructions ..............

...................................................................................................................... Table 105................................ 106 Logic and Shift Instructions: not ..........................................Table 70................................................................................. 105 Logic and Shift Instructions: or .... 110 Data Movement and Conversion Instructions: mov ....................... 115 Data Movement and Conversion Instructions: st .................. Table 95......................... prefetchu . Table 83......................................................... Table 100............................... Table 71................................. Table 79............................................ Table 88...... Table 72.................................................................................................................................. 131 Control Flow Instructions: exit ............................. 118 Data Movement and Conversion Instructions: isspacep .... 129 Control Flow Instructions: bra ............................ vmin. 137 Parallel Synchronization and Communication Instructions: vote ..... Table 75... 112 Data Movement and Conversion Instructions: ld ...... Table 76.................. Table 96.............. 107 Logic and Shift Instructions: shr ....... 125 Texture and Surface Instructions: sust ..... Table 97......... 143 January 24................................................ 119 Data Movement and Conversion Instructions: cvta ... 105 Logic and Shift Instructions: xor .... 106 Logic and Shift Instructions: cnot .............................. vshr ............................................ 123 Texture and Surface Instructions: txq ......... Table 73......................... Table 94.......................................... 2010 vii ........................ Logic and Shift Instructions: and ........... Table 81......... Table 106.................................................... Table 103................................. Table 85...................................................................... Table 89............... Table 102......................................... Table 92.......... Table 80............................... 109 Cache Operators for Memory Store Instructions ............... Table 78.................... Table 77................................................................................ 113 Data Movement and Conversion Instructions: ldu ... vmax ............... 130 Control Flow Instructions: call .............. vsub.................................. 124 Texture and Surface Instructions: suld ................................................................................................................................................ Table 99..................................................... 126 Texture and Surface Instructions: sured. 106 Logic and Shift Instructions: shl ............... 120 Texture and Surface Instructions: tex .... 133 Parallel Synchronization and Communication Instructions: membar ............... Table 91........... 131 Parallel Synchronization and Communication Instructions: bar ............ vabsdiff... Table 90............................... 134 Parallel Synchronization and Communication Instructions: atom .............................. 116 Data Movement and Conversion Instructions: prefetch..................... 119 Data Movement and Conversion Instructions: cvt ..................... Table 93......................... Table 101............ 139 Video Instructions: vadd........ 127 Texture and Surface Instructions: suq ........... Table 82.............................................. Table 86................ Table 87.. 135 Parallel Synchronization and Communication Instructions: red .................................................................... Table 98..................................... 129 Control Flow Instructions: @ ........ 111 Data Movement and Conversion Instructions: mov ............................ Table 84.... 107 Cache Operators for Memory Load Instructions ................................... Table 104............................. 142 Video Instructions: vshl... Table 74.......................................... 130 Control Flow Instructions: ret ............. 128 Control Flow Instructions: { } .........................

.......................................... Table 134....... 158 Kernel and Function Directives: .... 146 Miscellaneous Instructions: trap ............................. Table 141.............................................. 155 Special Registers: %clock ................... Table 123.............................................................. 152 Special Registers: %smid ...................... 163 Performance-Tuning Directives: ............maxntid ................................................ Table 112..version....................................................................................................................... Table 140........................................... Table 114......................................................... 154 Special Registers: %lanemask_ge .... Table 142.................. 144 Video Instructions: vset............................minnctapersm .............. 164 Performance-Tuning Directives: .............................................................................. 147 Miscellaneous Instructions: brkpt ....... Table 131......... Table 136... 156 Special Registers: %clock64 ... Table 116....... Table 129................................ Table 118........ Table 124................................. 153 Special Registers: %nsmid ................... Table 135............................................... Table 109.........0 Table 107............... Table 126... 151 Special Registers: %warpid ..............................................................target ........maxnreg .. 167 Linking Directives: ................................................................................................. Video Instructions: vmad .. %pm2...................... 156 PTX File Directives: ............................................. Table 121...... Table 143........... Table 139........................ 153 Special Registers: %gridid ................................ Table 133..................extern.... Table 120.................................................. 150 Special Registers: %laneid ........................ 154 Special Registers: %lanemask_lt ......................................... Table 122.................................................. Table 115. 160 Kernel and Function Directives: .. 161 Performance-Tuning Directives: ....................... Table 132......... 156 Special Registers: %pm0.. 150 Special Registers: %ntid ...................file . Table 130..................................................................................................................... Table 125.................................................... 164 Performance-Tuning Directives: ............... Table 128..... 167 Debugging Directives: ...........................................................entry.. 153 Special Registers: %lanemask_eq ...... 147 Special Registers: %tid ...........................................................................................loc .........................................................................section ............ 151 Special Registers: %ctaid ..................................... %pm1.......................... Table 127............................................maxnctapersm (deprecated) ....... %pm3 ............................... 2010 ........................... 165 Debugging Directives: @@DWARF ..................................................................pragma ........................................................................................................func .. 163 Performance-Tuning Directives: ............................................................................. 151 Special Registers: %nwarpid ............................................. Table 110............. 157 PTX File Directives: ................ 166 Debugging Directives: .......................................................... 167 Debugging Directives: ........................... 155 Special Registers: %lanemask_gt .. 168 viii January 24...........................................................................................................................PTX ISA Version 2... Table 138.. 147 Miscellaneous Instructions: pmevent............................... Table 108........................... Table 119............ Table 117......... 152 Special Registers: %nctaid .......................................... 154 Special Registers: %lanemask_le ............ Table 137.................................................... Table 113... Table 111......

........ Table 145. 168 Pragma Strings: “nounroll” ...........................Table 144................................visible.... 173 January 24........................................ Linking Directives: ....... 2010 ix ....................................................

2010 .PTX ISA Version 2.0 x January 24.

which are optimized for and translated to native target-architecture instructions. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Data-parallel processing maps data elements to parallel processing threads. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. many-core processor with tremendous computational horsepower and very high memory bandwidth. 1. PTX exposes the GPU as a data-parallel computing device.2. January 24. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. and because it is executed on many data elements and has high arithmetic intensity. PTX defines a virtual machine and ISA for general purpose parallel thread execution. PTX programs are translated at install time to the target hardware instruction set. image and media processing applications such as post-processing of rendered images. Introduction This document describes PTX. Because the same program is executed for each data element. the programmable GPU has evolved into a highly parallel. the memory access latency can be hidden with calculations instead of big data caches.1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Many applications that process large data sets can use a data-parallel programming model to speed up the computations. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture.Chapter 1. video encoding and decoding. Similarly. 1. from general signal processing or physics simulation to computational finance or computational biology. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. stereo vision. image scaling. 2010 1 . high-definition 3D graphics. multithreaded. In fact. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. and pattern recognition can map image blocks and pixels to parallel processing threads. there is a lower requirement for sophisticated flow control.

x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. performance kernels.x code will continue to run on sm_1x targets as well.f32 maps to fma. Legacy PTX 1. sub. Achieve performance in compiled applications comparable to native GPU performance.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. atomic. Instructions marked with .rp rounding modifiers for sm_20 targets. PTX ISA Version 2.0 is in improved support for the IEEE 754 floating-point standard. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. 1. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Provide a common source-level ISA for optimizing code generators and translators. memory. and architecture tests. Provide a machine-independent ISA for C/C++ and other compilers to target.rn.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. barrier.x.3. The main areas of change in PTX 2.1.f32 and mad. 2010 . The changes from PTX ISA 1.3. Facilitate hand-coding of libraries. The fma. Most of the new features require a sm_20 target.0 PTX ISA Version 2.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.f32 for sm_20 targets. Provide a code distribution ISA for application and middleware developers. The mad.f32 require a rounding modifier for sm_20 targets. • • • 2 January 24.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. A single-precision fused multiply-add (fma) instruction has been added. The mad. surface. Improved Floating-Point Support A main area of change in PTX 2.f32 requires sm_20.f32 instruction also supports . fma.f32. mad. Single-precision add. which map PTX to specific target machines. 1. including integer. PTX 2. A “flush-to-zero” (. When code compiled for sm_1x is executed on sm_20 devices. and video instructions.rm and . and mul now support .0 are improved support for IEEE 754 floating-point operations. reduction. Both fma.x features are supported on the new sm_20 target.sat modifiers.0 is a superset of PTX 1.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. addition of generic addressing to facilitate the use of general-purpose pointers. and the introduction of many new instructions.ftz and . and all PTX 1.ftz) modifier may be used to enforce backward compatibility with sm_1x.PTX ISA Version 2.

clamp and .Chapter 1.2. A new cvta instruction has been added to convert global. special registers. and directives are introduced in PTX 2. Generic Addressing Another major change is the addition of generic addressing. and Application Binary Interface (ABI). Introduction • Single. stack layout. suld. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. 2010 3 . so recursion is not yet supported. . for prefetching to specified level of memory hierarchy. these changes bring PTX 2. atom. allowing memory instructions to access these spaces without needing to specify the state space. and vice versa. PTX 2. isspacep. an address that is the same across all threads in a warp. st. New Instructions The following new instructions. Instructions prefetch and prefetchu have been added. • Taken as a whole. Instructions testp and copysign have been added. These are indicated by the use of a rounding modifier and require sm_20. and shared addresses to generic addresses. January 24. NOTE: The current version of PTX does not implement the underlying. Cache operations have been added to instructions ld. and sqrt with IEEE 754 compliant rounding have been added.g. local.zero. Surface Instructions • • Instruction sust now supports formatted surface stores.3.3. cvta.0. Generic addressing unifies the global. 1. Instruction cvta for converting global. Surface instructions support additional clamp modifiers. local.4. ldu.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. and red now support generic addressing.and double-precision div. prefetch. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. 1. rcp. prefetchu. instructions ld.0 closer to full compliance with the IEEE 754 standard. i. st. local..3. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.3.0. 1. stack-based ABI. and shared state spaces. and shared addresses to generic address and vice-versa has been added.e. In PTX 2. and sust. Support for an Application Binary Interface Rather than expose details of a particular calling convention. e.

red}. A new directive. Reduction.popc.or}.f32 have been added. and Vote Instructions • • • New atomic and reduction instructions {atom.pred have been added. A bar. vote.PTX ISA Version 2.b32.arrive instruction has been added.gt} have been added.sys.add. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. %clock64.{and.red.lt.shared have been extended to handle 64-bit data types for sm_20 targets. has been added. Other Extensions • • • Video instructions (includes prmt) have been added. . 2010 . %lanemask_{eq. bfi bit field extract and insert popc clz Atomic. A “vote ballot” instruction. membar.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. bar now supports an optional thread count and register operands.le.ge.red. 4 January 24. Barrier Instructions • • A system-level membar instruction. Instructions bar.section.u32 and bar. has been added.red}.ballot. Instructions {atom. New special registers %nsmid.

January 24.4. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 6 describes instruction operands. Chapter 11 provides release notes for PTX Version 2. Chapter 5 describes state spaces. 2010 5 .0. and PTX support for abstracting the Application Binary Interface (ABI). types. calling convention. and variable declarations.Chapter 1. Chapter 8 describes the instruction set. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 4 describes the basic syntax of the PTX language. Chapter 10 lists the assembly directives supported in PTX. Chapter 7 describes the function and call syntax. Introduction 1. Chapter 9 lists special registers.

2010 .PTX ISA Version 2.0 6 January 24.

2. It operates as a coprocessor to the main CPU.z). (with elements tid. compute addresses. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. or CTA. Programming Model 2.Chapter 2.1. Each CTA thread uses its thread identifier to determine its assigned role. 2010 7 . can be isolated into a kernel function that is executed on the GPU as many different threads. 2. data-parallel.y. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. or 3D shape specified by a three-element vector ntid (with elements ntid.z) that specifies the thread’s position within a 1D. Cooperative thread arrays (CTAs) implement CUDA thread blocks. but independently on different data. Each CTA has a 1D.x. The vector ntid specifies the number of threads in each CTA dimension. ntid. January 24. and tid. is an array of threads that execute a kernel concurrently or in parallel. Each thread has a unique thread identifier within the CTA. and select work to perform. or host: In other words. The thread identifier is a three-element vector tid.2. assign specific input and output positions. 2D. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. More precisely. To coordinate the communication of the threads within the CTA. tid. A cooperative thread array. To that effect. Programs use a data parallel decomposition to partition inputs.x. 2. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. and ntid. Threads within a CTA can communicate with each other. compute-intensive portions of applications running on the host are off-loaded onto the device. and results across the threads of the CTA.1. work. one can specify synchronization points where threads wait until all threads in the CTA have arrived. a portion of an application that is executed many times. 2D. or 3D CTA.y.

or sequentially.PTX ISA Version 2. Threads may read and use these values through predefined. read-only special registers %tid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. The warp size is a machine-dependent constant. or 3D shape specified by the parameter nctaid. However. such that the threads execute the same instructions at the same time. which may be used in any instruction where an immediate operand is allowed. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. %ntid. Each grid of CTAs has a 1D. a warp has 32 threads. 8 January 24. Threads within a warp are sequentially numbered. %nctaid. The host issues a succession of kernel invocations to the device.2. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1).2. %ctaid. Multiple CTAs may execute concurrently and in parallel.0 Threads within a CTA execute in SIMT (single-instruction. 2D . so PTX includes a run-time immediate constant. WARP_SZ. because threads in different CTAs cannot communicate and synchronize with each other. This comes at the expense of reduced thread communication and synchronization. Typically. Each grid also has a unique temporal grid identifier (gridid). CTAs that execute the same kernel can be batched together into a grid of CTAs. multiple-thread) fashion in groups called warps. so that the total number of threads that can be launched in a single kernel invocation is very large. A warp is a maximal subset of threads from a single CTA. depending on the platform. Some applications may be able to maximize performance with knowledge of the warp size. and %gridid. 2. 2010 .

0) Thread (4. 1) Thread (3. 2) Thread (2. 0) Thread (1. 0) CTA (1.Chapter 2. Figure 1. 1) Thread (1. 2) Thread (3. 0) CTA (0. 1) Thread (4. 0) Thread (2. 1) CTA (2. 0) Thread (3. A grid is a set of CTAs that execute independently. 1) Thread (0. 1) Thread (2. 1) CTA (1. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (0. 2010 9 . 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2) Thread (1. 2) Thread (4. 1) Thread (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. Thread Batching January 24. 0) CTA (2.

copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. as well as data filtering. constant. and texture memory spaces are optimized for different memory usages. Finally. for more efficient transfer. The global. or. respectively. Texture memory also offers different addressing modes. and texture memory spaces are persistent across kernel launches by the same application. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Both the host and the device maintain their own local memory.3. Each thread has a private local memory. The device memory may be mapped and read or written by the host. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. The global. all threads have access to the same global memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. 2010 . for some specific data formats.PTX ISA Version 2. 10 January 24. constant. referred to as host memory and device memory.0 2.

0) Block (0. 1) Grid 1 Global memory Block (0. 2) Figure 2. 0) Block (1. 0) Block (2. 1) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. Memory Hierarchy January 24.Chapter 2. 1) Block (2. 0) Block (1. 2010 11 . 2) Block (1. 1) Block (1. 0) Block (0.

0 12 January 24. 2010 .PTX ISA Version 2.

and each scalar thread executes independently with its own instruction address and register state. To manage hundreds of threads running several different programs. manages. the warp serially executes each branch path taken. the first parallel thread technology. When a multiprocessor is given one or more thread blocks to execute. allowing. The multiprocessor SIMT unit creates. Branch divergence occurs only within a warp. The threads of a thread block execute concurrently on one multiprocessor. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. It implements a single-instruction barrier synchronization. new blocks are launched on the vacated multiprocessors. Parallel Thread Execution Machine Model 3. If threads of a warp diverge via a data-dependent conditional branch. The way a block is split into warps is always the same. and executes threads in groups of parallel threads called warps.1. increasing thread IDs with the first warp containing thread 0. different warps execute independently regardless of whether they are executing common or disjointed code paths.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. and executes concurrent threads in hardware with zero scheduling overhead. The multiprocessor creates. At every instruction issue time. January 24. a cell in a grid-based computation).Chapter 3. The multiprocessor maps each thread to one scalar processor core. a multithreaded instruction unit. A warp executes one common instruction at a time. disabling threads that are not on that path. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. When a host program invokes a kernel grid. (This term originates from weaving. and on-chip shared memory. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. schedules. it splits them into warps that get scheduled by the SIMT unit. the multiprocessor employs a new architecture we call SIMT (single-instruction. the threads converge back to the same execution path. 2010 13 . so full efficiency is realized when all threads of a warp agree on their execution path. multiple-thread). each warp contains threads of consecutive. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). manages. a voxel in a volume. and when all paths complete. As thread blocks terminate. A multiprocessor consists of multiple Scalar Processor (SP) cores. for example.

A multiprocessor can execute as many as eight thread blocks concurrently. the programmer can essentially ignore the SIMT behavior. the kernel will fail to launch. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. modifies. SIMT enables programmers to write thread-level parallel code for independent. as well as data-parallel code for coordinated threads. require the software to coalesce loads into vectors and manage divergence manually. each read. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. which is a read-only region of device memory. As illustrated by Figure 3. which is a read-only region of device memory. but one of the writes is guaranteed to succeed. Vector architectures. In contrast with SIMD vector machines. modify.0 SIMT architecture is akin to SIMD (Single Instruction. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. If there are not enough registers or shared memory available per multiprocessor to process at least one block. For the purposes of correctness. • The local and global memory spaces are read-write regions of device memory and are not cached. but the order in which they occur is undefined. whereas SIMT instructions specify the execution and branching behavior of a single thread. In practice. 2010 . A key difference is that SIMD vector organizations expose the SIMD width to the software. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. 14 January 24. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. however. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. and writes to the same location in global memory for more than one of the threads of the warp. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. If an atomic instruction executed by a warp reads. on the other hand. the number of serialized writes that occur to that location and the order in which they occur is undefined.PTX ISA Version 2. write to that location occurs and they are all serialized. scalar threads.

Figure 3. Hardware Model January 24.Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 .

PTX ISA Version 2.0 16 January 24. 2010 .

using non-nested /* and */ for comments that may span multiple lines.target directive specifying the target architecture assumed. and using // to begin a comment that extends to the end of the current line. 4. Each PTX file must begin with a . followed by a . The C preprocessor cpp may be used to process PTX source files. Comments in PTX are treated as whitespace. #if. PTX is case sensitive and uses lowercase for keywords. #line. Syntax PTX programs are a collection of text source files. January 24. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. See Section 9 for a more information on these directives.2. #ifdef. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. 2010 17 .Chapter 4. The following are common preprocessor directives: #include. Comments Comments in PTX follow C/C++ syntax. #else.1. Lines beginning with # are preprocessor directives. Source Format Source files are ASCII text. Pseudo-operations specify symbol and addressing management. #define. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. whitespace is ignored except for its use in separating tokens in the language. 4. Lines are separated by the newline character (‘\n’).version directive specifying the PTX language version. All whitespace characters are equivalent. #endif.

address expressions.align .f32 array[N]. . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. and is written as @p.global start: .shared .func .const . r2.3.local .maxnctapersm . r1.file PTX Directives . ld. r2. written as @!p. shl.visible 4.minnctapersm . All instruction keywords are reserved tokens in PTX.section . The guard predicate may be optionally negated.b32 r1.version .reg . array[r1].target .5.2.reg . mov.global.b32 r1.1. The destination operand is first. r2. Statements A PTX statement is either a directive or an instruction.maxntid .pragma . 2010 .entry . Statements begin with an optional label and end with a semicolon. where p is a predicate register. 0.b32 add.f32 r2.0 4.global .maxnreg .tex .loc .x. followed by source operands. and terminated with a semicolon. 18 January 24. Table 1.3.sreg .param . The guard predicate follows the optional label and precedes the opcode.extern . 2. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. so no conflict is possible with user-defined identifiers. Instructions have an optional guard predicate which controls conditional execution. Operands may be register variables. Examples: . . Instruction keywords are listed in Table 2. constant expressions. Directive Statements Directive keywords begin with a dot.b32 r1.3. or label names.PTX ISA Version 2. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. %tid.

Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .Chapter 4.

between user-defined variable names and compiler-generated names. 2010 . except that the percentage sign is not allowed.4. e. listed in Table 3. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.g. or dollar characters. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. digits. or percentage character followed by one or more letters. underscore. dollar. Table 3. …. or they start with an underscore. digits. PTX allows the percentage sign as the first character of an identifier. The percentage sign can be used to avoid name conflicts.0 4.PTX ISA Version 2. %pm3 WARP_SZ 20 January 24. Many high-level languages such as C and C++ follow similar rules for identifier names. underscore. PTX predefines one constant and a small number of special registers that begin with the percentage sign.

i.s64) unless the value cannot be fully represented in .e. or binary notation. where the behavior of the operation depends on the operand types. octal. i. The syntax follows that of C. 2010 21 . 4.Chapter 4.e. Unlike C and C++. Constants PTX supports integer and floating-point constants and constant expressions. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. in which case the literal is unsigned (. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. Integer literals may be written in decimal. To specify IEEE 754 doubleprecision floating point values. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. When used in an instruction or data initialization. each integer constant is converted to the appropriate size based on the data or instruction type at its use. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Type checking rules remain the same for integer. For predicate-type data and instructions. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.5. hexadecimal..u64). the constant begins with 0f or 0F followed by 8 hex digits. These constants may be used in data initialization and as operands to instructions. and bit-size types.2. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. literals are always represented in 64-bit double-precision format.5. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. integer constants are allowed and are interpreted as in C. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.s64 or the unsigned suffix is specified. Floating-point literals may be written with an optional decimal point and an optional signed exponent. zero values are FALSE and non-zero values are TRUE. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.s64 or . the constant begins with 0d or 0D followed by 16 hex digits. floating-point. every integer constant has type ..1.u64. Syntax 4.5. To specify IEEE 754 single-precision floating point values. the sm_1x and sm_20 targets have a WARP_SZ value of 32. there is no suffix letter to specify size. 4. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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5.f64 integer .u64 . .s64 .s64 .f64 converted type constant literal + ! ~ Cast Binary (.u64 . or .f64 use usual conversions .f64 use usual conversions .f64 : .s64 .f64 integer .u64 zero or non-zero same as sources use usual conversions Result Type same as source .Chapter 4.s64) + .s64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table. 2nd is .s64 .u64 .f64 integer integer integer integer integer int ?. 2010 25 .u64 same as 1st operand .u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .s64.u64. Table 5. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 use usual conversions .s64 .u64 .s64 . Syntax 4.s64 .u64 .u64) (.f64 same as source .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 converted type .u64 1st unchanged.6.

2010 .PTX ISA Version 2.0 26 January 24.

shared by all threads. Global texture memory (deprecated). defined per-grid. 2010 27 . The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. read-only memory. Shared. platform-specific. Table 6. The list of state spaces is shown in Table 4. access rights. Special registers. and level of sharing between threads.sreg . and properties of state spaces are shown in Table 5. Types. and these resources are abstracted in PTX through state spaces and data types. addressability. The characteristics of a state space include its size. State Spaces. 5. and Variables While the specific resources available in a given target GPU will vary. Local memory.const .Chapter 5. access speed. Name State Spaces Description Registers.shared . pre-defined. Global memory. . State Spaces A state space is a storage area with particular characteristics. private to each thread. or Function or local parameters.tex January 24.reg . fast. Addressable memory shared between threads in 1 CTA. All variables reside in some state space.global . the kinds of resources will be common across platforms. Read-only.param . defined per-thread. Kernel parameters.1.local .

sreg) state space holds predefined. Device function input parameters may have their address taken via mov.param instruction. and vector registers have a width of 16-. or 128-bits. and cvt instructions.sreg . Registers may have alignment boundaries required by multi-word loads and stores. The number of registers is limited.const . Register State Space Registers (.. and performance monitoring registers.e. such as grid. For each architecture. floating point. it is not possible to refer to the address of a register. and will vary from platform to platform. Registers differ from the other state spaces in that they are not fully addressable. Address may be taken via mov instruction.param and st. or 64-bits. 2010 . When the limit is exceeded.2. 1 Accessible only via the ld.0 Table 7. 32-. register variables will be spilled to memory. 28 January 24.PTX ISA Version 2. The most common use of 8-bit registers is with ld.param instructions. predicate) or untyped.1. i.1.shared . the parameter is then located on the stack frame and its address is in the . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). or as elements of vector tuples.reg .local state space.1. 5. CTA. causing changes in performance.param (used in functions) . clock counters. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.global .tex Restricted Yes No3 5. platform-specific registers. st.param (as input to kernel) . scalar registers have a width of 8-. Special Register State Space The special register (. 64-.reg state space) are fast storage locations. unsigned integer. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . and thread parameters. All special registers are predefined. Registers may be typed (signed integer. 3 Accessible only via the tex instruction. 16-.local . 2 Accessible via ld. Register size is restricted. 32-. aside from predicate registers which are 1-bit.

In implementations that support a stack.global) state space is memory that is accessible by all threads in a context. The constant memory is organized into fixed size banks. It is typically standard memory with cache.sync instruction are guaranteed to be visible to any reads after the barrier instruction.const) state space is a read-only memory. Use ld. ld.3.local) is private memory for each thread to keep its own data. By convention. Global memory is not sequentially consistent. the store operation updating a may still be in flight. Constant State Space The constant (.local and st. State Spaces. All memory writes prior to the bar. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.1. all addresses are in global memory are shared.1. st. b = b – 1. Module-scoped local memory variables are stored at fixed addresses. // load second word 5. This pointer can then be used to access the entire 64KB constant bank.Chapter 5. whereas local memory variables declared January 24.const[2]. and atom. Types. the declaration . 5. Global State Space The global (.extern .sync instruction.global. Threads wait at the barrier until all threads in the CTA have arrived. If another thread sees the variable b change. and Variables 5. each pointing to the start address of the specified constant bank. Multiple incomplete array variables declared in the same bank become aliases. This reiterates the kind of parallelism available in machines that run PTX. the bank number must be provided in the state space of the load instruction.b32 const_buffer[]. For any thread in a context.global to access global variables. To access data in contant banks 1 through 10. as it must be allocated on a perthread basis.b32 const_buffer[]. For example.5. an incomplete array in bank 2 is accessed as follows: .local to access local variables. [const_buffer+4]. Banks are specified using the . Sequential consistency is provided by the bar. For example. Threads must be able to do their work without waiting for other threads to do theirs. It is the mechanism by which different CTAs and different grids can communicate. Consider the case where one thread executes the following two assignments: a = a + 1. 2010 29 . If no bank number is given. The size is limited. For the current devices. the stack is in local memory. Use ld.extern .const[2] .4. as in lock-free and wait-free style programming. for example). results in const_buffer pointing to the start of constant bank two.b32 %r1. initialized by the host.const[bank] modifier. where the size is not known at compile time.1. Local State Space The local state space (. there are eleven 64KB banks. The remaining banks may be used to implement “incomplete” constant arrays (in C. bank zero is used.global. where bank ranges from 0 to 10. bank zero is used for all statically-sized constant variables.const[2] .

[%ptr].PTX ISA Version 2. Similarly. all local memory variables are stored at fixed addresses and recursive function calls are not supported. … 30 January 24.f64 %d.param space.6.b32 len ) { .reg .param. [N]. len.x supports only kernel function parameters in .1.param) state space is used (1) to pass input arguments from the host to the kernel.b8 buffer[64] ) { .param instructions.param. ld. 2010 .1. No access protection is provided between parameter and global space in this case. PTX code should make no assumptions about the relative locations or ordering of .u32 %n. in some implementations kernel parameters reside in global memory. These parameters are addressable.param state space and is accessed using ld. Therefore.param . device function parameters were previously restricted to the register state space. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).1. typically for passing large structures by value to a function.0 within a function or kernel body are allocated on the stack.param instructions. For example.entry foo ( . In implementations that do not support a stack.align 8 . The resulting address is in the .f64 %d. %n. ld. (2a) to declare formal input and return parameters for device functions called from within kernel execution. .b32 N.6.reg .param .entry bar ( . 5.param . Values passed from the host to the kernel are accessed through these parameter variables using ld. The use of parameter state space for device function parameters is new to PTX ISA version 2.0 and requires target architecture sm_20. Example: . Note that PTX ISA versions 1.u32 %ptr.param space variables. … Example: . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. [buffer]. The kernel parameter variables are shared across all CTAs within a grid. The address of a kernel parameter may be moved into a register using the mov instruction.reg .u32 %ptr. per-kernel versus per-thread).param state space. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. read-only variables declared in the . 5. ld.u32 %n. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. Note: The location of parameter space is implementation specific.param. Parameter State Space The parameter (. mov. .u32 %n.

mystruct). The most common use is for passing objects by value that do not fit within a PTX register. which declares a . }.f64 dbl. it is illegal to write to an input parameter or read from a return parameter. int y.s32 %y.reg .local and st.param and function return parameters may be written using st.param space variable. State Spaces. passed to foo … . Aside from passing structures by value. Types. In this case. … } // code snippet from the caller // struct { double d. January 24. x. . This will be passed by value to a callee. and so the address will be in the .func foo ( .param .0 extends the use of parameter space to device function parameters.1.Chapter 5. … See the section on function call syntax for more details. Typically.param. .param formal parameter having the same size and alignment as the passed argument. Device Function Parameters PTX ISA version 2. call foo.b32 N.param. the caller will declare a locally-scoped . Example: // pass object of type struct { double d.param byte array variable that represents a flattened C structure or union.param space is also required whenever a formal parameter has its address taken within the called function.f64 %d.f64 %d. the address of a function input parameter may be moved into a register using the mov instruction.reg .param. dbl.param . } mystruct. . and Variables 5. [buffer].reg . (4.local instructions.f64 [mystruct+0]. .param. .align 8 .s32 [mystruct+8]. Function input parameters may be read via ld. [buffer+8]. int y.s32 %y. .reg . is flattened. a byte array in parameter space is used. such as C structures larger than 8 bytes.param. 2010 31 . Note that the parameter will be copied to the stack if necessary. It is not possible to use mov to get the address of a return parameter or a locally-scoped . ld.local state space and is accessed via ld.b8 buffer[12] ) { .s32 x.reg . ld.2. … st. st. In PTX.b8 mystruct.6.align 8 .

1. and . and programs should instead reference texture memory through variables of type . For example. The texture name must be of type .7.tex . A texture’s base address is assumed to be aligned to a 16-byte boundary. Use ld.texref type and Section 8. It is shared by all threads in a context.shared and st. and variables declared in the .tex directive will bind the named texture memory variable to a hardware texture identifier.1.shared to access shared variables. Texture State Space (deprecated) The texture (.tex . tex_d. Texture memory is read-only.texref variables in the . Physical texture resources are allocated on a per-module granularity. See Section 5. 32 January 24.tex .u32 tex_a. 5. One example is broadcast.texref.tex .u32 or .3 for the description of the . Shared memory typically has some optimizations to support the sharing.tex variables are required to be defined in the global scope. Multiple names may be bound to the same physical texture identifier.tex) state space is global memory accessed via the texture instruction. Another is sequential access from sequential threads. tex_d.global . An address in shared memory can be read and written by any thread in a CTA. The . where texture identifiers are allocated sequentially beginning with zero. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. is equivalent to . The .shared) state space is a per-CTA region of memory for threads in a CTA to share data.0 5.texref tex_a. where all threads read from the same address.6 for its use in texture instructions.u32 . Shared State Space The shared (.7.PTX ISA Version 2. tex_c. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex state space are equivalent to module-scoped . 2010 .u32 .8. a legacy PTX definitions such as .u64. tex_f.u32 .u32 tex_a.tex . Example: .tex directive is retained for backward compatibility. An error is generated if the maximum number of physical resources is exceeded.global state space.

.f64 . A fundamental type specifies both a basic type and a size.s64 .f32 and . January 24. . or converted to other types and sizes. st. but typed variables enhance program readability and allow for better operand type checking. stored.f32 and . and .s16. The . .s32.b8.u16. The bitsize type is compatible with any fundamental type having the same size. so that narrow values may be loaded.Chapter 5. The following table lists the fundamental type specifiers for each basic type: Table 8.f64 types. . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.f16 floating-point type is allowed only in conversions to and from . . stored. ld.u8. 2010 33 .b8 instruction types are restricted to ld. .2. The same typesize specifiers are used for both variable definitions and for typing instructions. st.f64 types. Register variables are always of a fundamental type.2.f16. 5. and Variables 5. Signed and unsigned integer types are compatible if they have the same size.s8.u64 . and converted using regular-width registers. For convenience. . All floating-point instructions operate only on . Restricted Use of Sub-Word Sizes The . all variables (aside from predicates) could be declared using only bit-size types. Fundamental Types In PTX. . Operand types and sizes are checked against instruction types for compatibility. . . so their names are intentionally short. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Two fundamental types are compatible if they have the same basic type and are the same size.pred Most instructions have one or more type specifiers.s8.u32.b64 .2. State Spaces.b16. Types 5. the fundamental types reflect the native data types supported by the target architectures. needed to fully specify instruction behavior.2. For example. . .b32. and cvt instructions. In principle.u8. Types.1. and instructions operate on these types. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .f32.

and overall size is hidden to a PTX program. texture and sampler information each have their own handle.{u32. and surface descriptor variables. or performing pointer arithmetic will result in undefined results. sampler. For working with textures and samplers.3. 34 January 24. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. These types have named fields similar to structures. but all information about layout. or surfaces via texture and surface load/store instructions (tex.e. and query instructions.0 5. allowing them to be defined separately and combined at the site of usage in the program. texture and sampler information is accessed through a single . field ordering.texref. since these properties are defined by . The following tables list the named members of each type for unified and independent texture modes. PTX has two modes of operation. In independent mode the fields of the . 2010 . Referencing textures. Creating pointers to opaque variables using mov. Retrieving the value of a named member via query instructions (txq. but the pointer cannot otherwise be treated as an address. the resulting pointer may be stored to and loaded from memory.surfref. and Surface Types PTX includes built-in “opaque” types for defining texture.samplerref variables. sust. store. accessing the pointer with ld and st instructions. base address. passed as a parameter to functions. Texture. The three built-in types are . hence the term “opaque”.. i. suq). In the independent mode. Sampler. samplers.texref handle.PTX ISA Version 2.samplerref. sured).u64} reg. suld. opaque_var.texref type that describe sampler properties are ignored. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. . and de-referenced by texture and surface load. In the unified mode. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. and .

Member width height depth Opaque Type Fields in Independent Texture Mode .texref values . clamp_to_edge. clamp_ogl. Member width height depth Opaque Type Fields in Unified Texture Mode . linear wrap.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_border N/A N/A N/A N/A N/A . and Variables Table 9.samplerref values N/A N/A N/A N/A nearest. mirror. linear wrap. Types. 1 ignored ignored ignored ignored . mirror. clamp_to_edge. 2010 35 . State Spaces.Chapter 5.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. 1 nearest. clamp_to_border 0.texref values in elements in elements in elements 0. clamp_ogl.

samplerref my_sampler_name.PTX ISA Version 2.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.texref my_texture_name. At module scope. Example: .global state space. When declared at module scope. these variables must be in the . the types may be initialized using a list of static expressions assigning values to the named members. filter_mode = nearest }.global .global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global . .global . 2010 . . these variables are declared in the .surfref my_surface_name. Example: .texref tex1.global .param state space. As kernel parameters. . 36 January 24.

s32 i. Variables In PTX.0}.v4 . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . Vectors cannot exceed 128-bits in length. // a length-2 vector of unsigned ints . a variable declaration describes both the variable’s type and its state space.global . Predicate variables may only be declared in the register state space. Vectors Limited-length vector types are supported.v4 . where the fourth element provides padding. an optional initializer.2. vector variables are aligned to a multiple of their overall size (vector length times base-type size).v4.4. In addition to fundamental types. Examples: .v1. This is a common case for three-dimensional grids.v2 or .v4. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.f64 is not allowed.0.u16 uv. textures.b8 v.struct float4 { .v3 }. and an optional fixed address for the variable.Chapter 5. . // a length-4 vector of floats . . its type and size.4. its name.v2. Examples: .pred p. Three-element vectors may be handled by using a .reg . 1. 2010 37 . Every variable must reside in one of the state spaces enumerated in the previous section. 5.global .f32 V.v4 vector.v4 .reg . an optional array size.global . PTX supports types for simple aggregate objects such as vectors and arrays.u8 bg[4] = {0. .global .const .global . // typedef . for example.u32 loc. 0.shared . 0. Types. State Spaces. A variable declaration names the space in which the variable resides. Variable Declarations All storage for data is specified with variable declarations. etc. and Variables 5. r.f32 accel. . January 24. // a length-4 vector of bytes By default. and they may reside in the register space. Vectors must be based on a fundamental type. .reg . 5.f32 bias[] = {-1. .4.1.struct float4 coord. 0}.f32 v0.v2 . q. .

1}.shared .0 5.0.0}.global .05. 2010 .global . {0. Variables that hold addresses of variables or instructions should be of type .4. {0. this can be used to statically initialize a pointer to a variable.u8 mailbox[128]. Here are some examples: .local . Initializers are allowed for all types except .{.global .3. 38 January 24.0.1.0}}.pred. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.1.PTX ISA Version 2. For the kernel declaration above. {0.s32 offset[][] = { {-1..0.v4 . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. 0}.1.4. where the variable name is followed by an equals sign and the initial value or values for the variable.. The size of the dimension is either a constant expression. // address of rgba into ptr Currently.u8 rgba[3] = {{1.f32 blur_kernel[][] = {{. {1.global .05}. . Similarly. 0}. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration)... 5. A scalar takes a single value. or is left empty. label names appearing in initializers represent the address of the next instruction following the label.f16 and . . .u64.s32 n = 10. The size of the array specifies how many elements should be reserved. 1} }.4.u16 kernel[19][19]. Array Declarations Array declarations are provided to allow the programmer to reserve space. To declare an array.u32 or .1.1.b32 ptr = rgba. Variable names appearing in initializers represent the address of the variable.05.4. {0.global . variable initialization is supported only for constant and global state spaces. this can be used to initialize a jump table to be used with indirect branches or calls.0.. . Examples: .0}. ..{. 19*19 (361) halfwords are reserved (722 bytes). being determined by an array initializer. -1}.05}}.

suppose a program uses a large number. For arrays. it is quite common for a compiler frontend to generate a large number of register names. For example. of .5. . Alignment is specified using an optional .align 4 . 5. say one hundred. Array variables cannot be declared this way. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.Chapter 5.reg . and Variables 5. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.align byte-count specifier immediately following the state-space specifier. These 100 register variables can be declared as follows: .6.b32 variables. and may be preceded by an alignment specifier. // declare %r0.4. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.2. named %r0.0. Parameterized Variable Names Since PTX supports virtual registers. January 24. %r99.b8 bar[8] = {0. Examples: // allocate array at 4-byte aligned address.0.4. Types. 2010 39 . not for individual elements.0}. …. The default alignment for vector variables is to a multiple of the overall vector size.0.. The variable will be aligned to an address which is an integer multiple of byte-count. alignment specifies the address alignment for the starting address of the entire array. %r1. %r1. .0. Rather than require explicit declaration of every name.b32 %r<100>..const . The default alignment for scalar and array variables is to a multiple of the base-type size.. nor are initializers permitted. Elements are bytes.0. State Spaces.

0 40 January 24. 2010 .PTX ISA Version 2.

q.reg register state space. Instruction Operands 6. The cvt (convert) instruction takes a variety of operand types and sizes. 6. st. January 24. mov. There is no automatic conversion between types.Chapter 6. s. The result operand is a scalar or vector variable in the register state space. so operands for ALU instructions must all be in variables declared in the . Most instructions have an optional predicate guard that controls conditional execution. The bit-size type is compatible with every type having the same size. Source Operands The source operands are denoted in the instruction descriptions by the names a. 6. Predicate operands are denoted by the names p. PTX describes a load-store machine. Integer types of a common size are compatible with each other. The ld. and a few instructions have additional predicate source operands. The mov instruction copies data between registers. Each operand type must be compatible with the type determined by the instruction template and instruction type. b. .1. and c. and cvt instructions copy data from one location to another. For most operations. r. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. as its job is to convert from nearly any data type to any other data type (and size). the sizes of the operands must be consistent. Operand Type Information All operands in instructions have a known type from their declarations.2. 2010 41 .3. Instructions ld and st move data from/to addressable state spaces to/from registers. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.

u32 42 January 24.const . . Load and store operations move data between registers and locations in addressable state spaces.gloal.u16 x. Examples include pointer arithmetic and pointer comparisons.v4 . q.b32 p. The mov instruction can be used to move the address of a variable into a pointer.shared. Arrays. .PTX ISA Version 2.u16 ld.s32 q.4.u16 r0. .reg . r0. 6.reg . arrays.4. All addresses and address computations are byte-based. . Using Addresses.0 6. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. 2010 . tbl. ld. The address is an offset in the state space in which the variable is declared.1. address registers. The interesting capabilities begin with addresses.reg .f32 W. .global .f32 V.[x].const. and Vectors Using scalar variables as operands is straightforward.s32 tbl[256]. there is no support for C-style pointer arithmetic. The syntax is similar to that used in many assembly languages. address register plus byte offset. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. Here are a few examples: .v4. . Address expressions include variable names. and immediate address expressions which evaluate at compile-time to a constant address. and vectors.shared . [V]. W. [tbl+12].s32 mov. p.v4 .f32 ld.reg .

Arrays as Operands Arrays of all types can be declared.b.x V.b and . Instruction Operands 6.b. Vectors as Operands Vector operands are supported by a limited subset of instructions.y.g. d. a[N-1].a 6.v4 . it must be written as an address calculation prior to use. c. Vector loads and stores can be used to implement wide loads and stores. . b. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. as well as the typical color fields . The size of the array is a constant in the program. for use in an indirect branch or call. say {Ra.y V. which may improve memory performance.r V.4. and the identifier becomes an address constant in the space where the array is declared.4.Chapter 6. or by indexing into the array using square-bracket notation. The expression within square brackets is either a constant integer.d}. ld. mov. [addr+offset]. . a[1].g V. January 24. st. a register variable.global.u32 s. or a simple “register with constant offset” expression.v4.v4. mov.f32 ld.x. Examples are ld.u32 {a. If more complicated indexing is desired.3. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Rc.f32 {a.c.r.4.c.reg . Rd}. Vectors may also be passed as arguments to called functions. Elements in a brace-enclosed vector.reg . .b V.2.d}.a. which include mov. and tex. or a braceenclosed list of similarly typed scalars. . // move address of a[1] into s 6. Array elements can be accessed using an explicitly calculated byte address.f32 V. 2010 43 . a[0]. . where the offset is a constant expression that is either added or subtracted from a register variable. A brace-enclosed list is used for pattern matching to pull apart vectors.w = = = = V. and in move instructions to get the address of the label or function into a register. V2. Here are examples: ld.4. [addr+offset2].w. Rb. V.global.global. Vector elements can be extracted from the vector with the suffixes .u32 s.v2.f32 a.global.z V.z and . The registers in the load/store operations can be a vector. . ld.u32 s.

0 6.PTX ISA Version 2. Operands of different sizes or types must be converted prior to the operation.1. and ~131.000 for f16). and data movement instruction must be of the same type and size. 44 January 24.5. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.5. 2010 .s32. if a cvt. For example. except for operations where changing the size and/or type is part of the definition of the instruction.u16 instruction is given a u16 source operand and s32 as a destination operand. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 6. Type Conversion All operands to all arithmetic. the u16 is zero-extended to s32. logic.

f2s = float-to-signed. f2f = float-to-float. f2u = float-to-unsigned. Instruction Operands Table 11. u2f = unsigned-to-float. then sign-extend to 32-bits. The type of extension (sign or zero) is based on the destination format. the result is extended to the destination register width after chopping. zext = zero-extend.u32 targeting a 32-bit register will first chop to 16-bits. For example. s2f = signed-to-float. Notes 1 If the destination register is wider than the destination format.s16.Chapter 6. cvt. 2010 45 . chop = keep only low bits that fit. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. January 24.

0 6. Modifier . there are four integer rounding modifiers and four floating-point rounding modifiers.5. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rni . 2010 .rzi .rn .rpi Integer Rounding Modifiers Description round to nearest integer.PTX ISA Version 2.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. Modifier . In PTX. Rounding Modifiers Conversion instructions may specify a rounding modifier.rmi .rz .2. Table 12.rm . choosing even integer if source is equidistant between two integers. The following tables summarize the rounding modifiers.

Another way to hide latency is to issue the load instructions as early as possible. Table 14. while global memory is slowest. Operand Costs Operands from different state spaces affect the speed of an operation. Registers are fastest. 2010 47 . The register in a store operation is available much more quickly.Chapter 6.6. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Instruction Operands 6. Table 11 gives estimates of the costs of using different kinds of memory. first access is high Notes January 24. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Much of the delay to memory can be hidden in a number of ways.

2010 .PTX ISA Version 2.0 48 January 24.

2010 49 . At the call. … Here. and an optional list of input parameters. The simplest function has no parameters or return values. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. and is represented in PTX as follows: . A function declaration specifies an optional list of return parameters.func directive. and return values may be placed directly into register variables. stack-based ABI.Chapter 7. arguments may be register variables or constants. NOTE: The current version of PTX does not implement the underlying. parameter passing. or prototype.func foo { … ret. together these specify the function’s interface. and Application Binary Interface (ABI). the function name. so recursion is not yet supported. and memory allocated on the stack (“alloca”). execution of the call instruction transfers control to foo. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. support for variadic functions (“varargs”). we describe the features of PTX needed to achieve this hiding of the ABI. In this section. A function must be declared or defined prior to being called. function calls. Scalar and vector base-type input and return parameters may be represented simply as register variables. } … call foo. January 24. Execution of the ret instruction within foo transfers control to the instruction following the call. Function declarations and definitions In PTX.1. A function definition specifies both the interface and the body of the function. functions are declared and defined using the . implicitly saving the return address. Abstracting the ABI Rather than expose details of a particular calling convention. These include syntax for function definitions. 7. stack layout.

u32 %res) inc_ptr ( .b8 c2. bumpptr.param space call (%out). (%r1. … ld. .4). the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .b8 c3. a . [y+10].param.f64 f1.PTX ISA Version 2. %rc1. c2.reg . ld. In PTX. consider the following C structure.b64 [py+ 0].align 8 y[12]) { . }.param .reg space. 2010 .u32 %ptr.param.param. ld.param space variables are used in two ways.f64 f1.b8 [py+ 9].func (. note that . Second.0 Example: . [y+8].b8 . [y+0]. byte array in .b32 c1.param. %rc2.c2.c3. … st. } { . . %rc1. [y+11].s32 x. inc_ptr.param. The .reg .c1.func (. [y+9]. st.param space memory.reg .f64 field are aligned. c3.u32 %inc ) { add. a . ld.c4.reg . First.param. %ptr.param.b8 [py+11].reg . passed by value to a function: struct { double dbl. For example.b8 c1. %rd. .param .u32 %res.param.param. ld. … In this example. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . st.b8 [py+10]. (%x. %rc2. Since memory accesses are required to be aligned to a multiple of the access size. st. py). this structure will be flattened into a byte array. 50 January 24.f1.param variable y is used in function definition bar to represent a formal parameter.align 8 py[12].param state space is used to pass the structure by value: . %inc. // scalar args in .reg .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. … … // computation using x. st.b8 c4. } … call (%r1).param.s32 out) bar (.b8 .b8 [py+ 8]. char c[4]. c4.reg . ret.

and alignment of parameters. the corresponding argument may be either a . Abstracting the ABI The following is a conceptual way to think about the . 2. the corresponding argument may be either a . This enables backend optimization and ensures that the . Supporting the . For a caller.param memory must be aligned to a multiple of 1.reg space variable with matching type and size. 8. • • Arguments may be . • • • For a callee.param arguments.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. size. • The .param argument must be declared within the local scope of the caller.reg space formal parameters. the argument must also be a . A . For a caller. 2010 51 . . The .param state space is used to receive parameter values and/or pass return values back to the caller. • • • Input and return parameters may be .reg space variable of matching type and size. size.param or ..param variables or .reg variables. January 24. The .param space byte array with matching type. For a callee. In the case of . Parameters in . In the case of .reg variables. or constants. Note that the choice of .param byte array is used to collect together fields of a structure being passed by value.param space formal parameters that are base-type scalar or vector variables. a . In the case of .param space formal parameters that are byte arrays.param instructions used for argument passing must be contained in the basic block with the call instruction. or a constant that can be represented in the type of the formal parameter.param and ld.param state space use in device functions.Chapter 7.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. all st.reg state space in this way provides legacy support.g.reg state space can be used to receive and return base-type scalar and vector values. Typically. For . or a constant that can be represented in the type of the formal parameter.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param variables. 4.param or . The following restrictions apply to parameter passing.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. or 16 bytes.reg or . and alignment. • The .

param space parameters support arrays. 2010 . Objects such as C structures were flattened and passed or returned using multiple registers.reg or .1. formal parameters may be in either .reg state space. and a . PTX 2. In PTX ISA version 2.0 restricts functions to a single return value. Changes from PTX 1.param byte array should be used to return objects that do not fit into a register.x In PTX ISA version 1. formal parameters were restricted to .0 7. For sm_2x targets.1. 52 January 24.0 continues to support multiple return registers for sm_1x targets. PTX 2.param state space.x. and there was no support for array parameters. and . PTX 1.0.PTX ISA Version 2.x supports multiple return values for this purpose.

u32 ap.u32. or 8 bytes. 4). .reg .b32 result. val. … call (%max). the size may be 1. 2.reg . maxN.reg .func okay ( … ) Built-in functions are provided to initialize.reg . and end access to a list of variable arguments. 2010 53 .func (.reg . ) { . %r3).reg .. . %s1.reg .u32 sz. The function prototypes are defined as follows: .h and varargs. bra Done. // default to MININT mov. the alignment may be 1. 4. %va_end is called to free the variable argument list handle. result. . call %va_end. . call (ap). mov. In both cases. For %va_arg.u32 ptr.u32 ptr) %va_start . for %va_arg64. ret. maxN. (3.pred p. %r1.reg . PTX provides a high-level mechanism similar to the one provided by the stdarg.2.u32 b. the size may be 1.func (. .u32 align) . 4. (2. 0x8000000. … %va_start returns Loop: @p Done: January 24. %s2).func ( . %va_arg.func %va_end (. Variadic functions NOTE: The current version of PTX does not support variadic functions.reg . 0. . setp.s32 result. 4. ctr. Abstracting the ABI 7.ge p.. This handle is then passed to the %va_arg and %va_arg64 built-in functions. iteratively access.reg .reg . %va_start.u32 align) .u32 sz. following zero or more fixed parameters: .reg . Once all arguments have been processed. 2. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .h headers in C. (ap.reg .func (.u32 N.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg . ctr.Chapter 7. . } … call (%max).b32 ctr. … ) .func baz ( . N. 2.b64 val) %va_arg64 (. call (val). To support functions with a variable number of arguments. 8. or 4 bytes. along with the size and alignment of the next data value to be accessed. variadic functions are declared with an ellipsis at the end of the input parameter list. %r2. .u32 a.u32 ptr.s32 val.reg .b32 val) %va_arg (.reg . (ap).reg . or 16 bytes. In PTX.s32 result ) maxN ( . bra Loop. max.

u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. Alloca NOTE: The current version of PTX does not support alloca. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. a function simply calls the built-in function %alloca. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. To allocate memory.reg .func ( . The array is then accessed with ld. 54 January 24.PTX ISA Version 2.0 7.reg .local and st.3. 2010 . If a particular alignment is required.u32 ptr ) %alloca ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.local instructions. defined as follows: .

and C are the source operands. the D operand is the destination operand. 2010 55 .s32. 8. A. opcode D. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. A. Instruction Set 8. We use a ‘|’ symbol to separate multiple destination registers. setp. b. opcode D. B. while A. January 24. followed by some examples that attempt to show several possible instantiations of the instruction.2. B. The setp instruction writes two destination registers. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. PTX Instructions PTX instructions generally have from zero to four operands. the semantics are described.lt p|q. opcode A. A. In addition to the name and the format of the instruction. a. For instructions that create a result value. C. Format and Semantics of Instruction Descriptions This section describes each PTX instruction.Chapter 8. B.1. // p = (a < b). For some instructions the destination operand is optional. q = !(a < b).

n. add 1 to j To get a conditional branch or conditional function call.s32 p. As an example.s32 j.s32 j. i. … // compare i to n // if false. consider the high-level code if (i < n) j = j + 1.0 8. use a predicate to control the execution of the branch or call instructions.reg . q. j. Instructions without a guard predicate are executed unconditionally. add.lt. bra L1. optionally negated. This can be written in PTX as @p setp.pred p. Predicates are most commonly set as the result of a comparison performed by the setp instruction. 2010 . where p is a predicate variable.3.pred as the type specifier. add. predicate registers can be declared as . j. 1. Predicated Execution In PTX. To implement the above example as a true conditional branch.s32 p. branch over 56 January 24. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. // p = (i < n) // if i < n. predicate registers are virtual and have . the following PTX instruction sequence might be used: @!p L1: setp. i. So. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.lt. 1. n.PTX ISA Version 2.

le (less-than-or-equal).3. ls (lower-or-same).1.1. ordering comparisons are not defined for bit-size types. and hs (higher-or-same). ne. lo (lower). Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Comparisons 8.1. If either operand is NaN. le. gt. The following table shows the operators for signed integer. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Instruction Set 8.3. Unsigned Integer. ne (not-equal). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.Chapter 8. ge.2. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. lt (less-than). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. lt. unsigned integer. and bitsize types. Table 15. 2010 57 . and ge (greater-than-or-equal).3. Table 16.1. gt (greater-than). the result is false. hi (higher). The bit-size comparisons are eq and ne. The unsigned comparisons are eq. ne.

%p. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. If both operands are numeric values (not NaN).0. However. 2010 . and nan returns true if either operand is NaN. leu. // convert predicate to 32-bit value 58 January 24. neu. Table 18.u32 %r1. gtu. If either operand is NaN. geu. then these comparisons have the same result as their ordered counterparts.0 To aid comparison operations in the presence of NaN values.1. not. or. xor. then the result of these comparisons is true. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.PTX ISA Version 2. two operators num (numeric) and nan (isNaN) are provided. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.3. and mov. Table 17. num returns true if both operands are numeric values (not NaN). and no direct way to load or store predicate register values. ltu. unordered versions are included: equ. for example: selp. setp can be used to generate a predicate from an integer. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. There is no direct conversion between predicates and integer values.2.

For example: .sX .fX ok ok ok ok January 24.fX ok inv inv ok Instruction Type . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. and integer operands are silently cast to the instruction type if needed. different sizes).Chapter 8. they must match exactly.u16 d. and this information must be specified as a suffix to the opcode. unsigned.bX . i.bX . Type Checking Rules Operand Type . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.reg .. For example. a. Signed and unsigned integer types agree provided they have the same size. For example. b. and these are placed in the same order as the operands. most notably the data conversion instruction cvt.sX ok ok ok inv . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. a. float.u16 a.uX ok ok ok inv .uX . a.u16 d. 2010 59 . . cvt.f32 d. b. add.f32. It requires separate type-size modifiers for the result and source.reg . Instruction Set 8. Example: . the add instruction requires type and size information to properly perform the addition operation (signed.4.u16 d.reg . • The following table summarizes these type checking rules. Table 19.e. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Floating-point types agree only if they have the same size.

The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. ld. For example. unless the operand is of bit-size type. The following table summarizes the relaxed type-checking rules for source operands. Bit-size source registers may be used with any appropriately-sized instruction type. or converted to other types and sizes. inv = invalid. so that narrow values may be loaded.bX instruction types.1. stored. st. When used with a narrower bit-size type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. stored.PTX ISA Version 2. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.0 8. Source register size must be of equal or greater size than the instruction-type size. Floating-point source registers can only be used with bit-size or floating-point instruction types. the cvt instruction does not support . Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. the data will be truncated. floating-point instruction types still require that the operand type-size matches exactly. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. and converted using regular-width registers. for example. 2. Operand Size Exceeding Instruction-Type Size For convenience. When a source operand has a size that exceeds the instruction-type size. so those rows are invalid for cvt. parse error. Table 20. the size must match exactly.4. When used with a floating-point instruction type. Note that some combinations may still be invalid for a particular instruction. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. The data is truncated to the instruction-type size and interpreted according to the instruction type. “-“ = allowed. 2010 . Notes 3. 1. 4. 60 January 24. no conversion needed.

Bit-size destination registers may be used with any appropriately-sized instruction type. Table 21. 4. The following table summarizes the relaxed type-checking rules for destination operands. Destination register size must be of equal or greater size than the instruction-type size. If the corresponding instruction type is signed integer. the data is zeroextended. the size must match exactly. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Notes 3. “-“ = Allowed but no conversion needed. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. zext = zero-extend. 1. Floating-point destination registers can only be used with bit-size or floating-point instruction types. 2010 61 . 2. the data is sign-extended.or sign-extended to the size of the destination register. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. parse error.Chapter 8. the destination data is zero. the data will be zero-extended. The data is sign-extended to the destination register width for signed integer instruction types. When used with a narrower bit-size instruction type. The data is signextended to the destination register width for signed integer instruction types. and is zero-extended to the destination register width otherwise. January 24. When used with a floatingpoint instruction type. otherwise. inv = Invalid.

the threads are called uniform. by a right-shift instruction.PTX ISA Version 2. 62 January 24. Divergence of Threads in Control Constructs Threads in a CTA execute together. 8. However. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. These extra precision bits can become visible at the application level. Both situations occur often in programs. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. Therefore. at least in appearance. The semantics are described using C. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. When executing on a 32-bit data path. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. the semantics of 16-bit instructions in PTX is machine-specific. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. for many performance-critical applications. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. using the . this is not desirable. If all of the threads act in unison and follow a single control flow path.6. until C is not expressive enough. If threads execute down different control flow paths. until they come to a conditional control construct such as a conditional branch. At the PTX language level. 16-bit registers in PTX are mapped to 32-bit physical registers. 2010 . 8. the threads are called divergent. so it is important to have divergent threads re-converge as soon as possible. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. A compiler or programmer may chose to enforce portable. and for many applications the difference in execution is preferable to limiting performance. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. and 16-bit computations are “promoted” to 32-bit computations. for example.6.1. a compiler or code author targeting PTX can ignore the issue of divergent threads. For divergent control flow. the optimizing code generator automatically determines points of re-convergence.uni suffix.5. conditional function call.0 8. or conditional return.

subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 8.cc.7. Instruction Set 8. The Integer arithmetic instructions are: add sub add. 2010 63 .7.cc. addc sub. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. the optional guard predicate is omitted from the syntax. Instructions All PTX instructions may be predicated.1. In the following descriptions.Chapter 8.

@p add.c. Supported on all target architectures. sub.sat.. Description Semantics Notes Performs addition and writes the resulting value into a destination register.u16. // .s16. add. b.s32 .type add{.b.0. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. .u16.u32 x.type = { . .u64.s32 type.s32 d.MAXINT (no overflow) for the size of the operation. .s16. Applies only to . d = a + b.type = { .s32 d.sat applies only to . . PTX ISA Notes Target ISA Notes Examples Table 23. a. 2010 .s64 }.sat}.s32 type. .1.a.z.PTX ISA Version 2.s32 . add. Introduced in PTX ISA version 1. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Applies only to . . Saturation modifier: .u32.u64.MAXINT (no overflow) for the size of the operation.sat limits result to MININT. .s32 c. PTX ISA Notes Target ISA Notes Examples 64 January 24. b. a. // . d.y. Introduced in PTX ISA version 1.s32 c. d.type sub{.s64 }.s32.sat limits result to MININT. b. Saturation modifier: . a. .0 Table 22. b. d = a – b.u32. . add Syntax Integer Arithmetic Instructions: add Add two values. Supported on all target architectures. a.sat applies only to .s32.. .0.sat}. sub.

b32 x1.u32.z1. clearing. b. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. Introduced in PTX ISA version 1. @p @p @p @p add.cc. and there is no support for setting. b. .b32 addc.y3. .cc. Supported on all target architectures. or testing the condition code.Chapter 8.CF No integer rounding modifiers.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.type d. carry-out written to CC. Behavior is the same for unsigned and signed integers. d = a + b.cc. add.b32 addc. No saturation.cc.b32 addc. carry-out written to CC.b32 x1.y1. Table 24. No saturation. . Introduced in PTX ISA version 1. These instructions support extended-precision integer addition and subtraction. add. Instruction Set Instructions add. addc{.y4.cc Syntax Integer Arithmetic Instructions: add.s32 }.y2. .type = { . if .u32. x2.z4. Supported on all target architectures. x4.cc specified.cc. 2010 65 .b32 addc.b32 addc.2.cc}.z2.cc.2.y2.z1.type = {.cc. x4. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.y1. d = a + b + CC.s32 }.b32 addc.z2. a. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. x2.y4. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. addc.CF No integer rounding modifiers. x3. a. Behavior is the same for unsigned and signed integers.type d.z3. No other instructions access the condition code.cc. x3.cc.CF) holding carry-in/carry-out or borrowin/borrow-out.cc. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. @p @p @p @p add.z3. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.CF. sub.cc Add two values with carry-out.z4.y3.

a.z1.b32 subc.y2.0 Table 26. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.b32 subc.y2.u32. borrow-out written to CC. . @p @p @p @p sub. sub.cc Syntax Integer Arithmetic Instructions: sub. Behavior is the same for unsigned and signed integers. Supported on all target architectures.s32 }.CF No integer rounding modifiers. x4. x3. Introduced in PTX ISA version 1. .z4. subc{. 2010 .b32 x1. b. .cc specified. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y4.u32.PTX ISA Version 2.y3. sub. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.type = {.type = { .z2.b32 subc. Supported on all target architectures.3. b.b32 subc. Introduced in PTX ISA version 1. Behavior is the same for unsigned and signed integers.y1.z3.cc. No saturation. withborrow-in and optional borrow-out.cc.cc.cc Subract one value from another.3.b32 x1.z4. d = a .type d. d = a – b.z3. x2.CF No integer rounding modifiers.(b + CC.cc.z1.y4. x2. @p @p @p @p sub.cc.y3. if .cc.b32 subc. with borrow-out. x3.CF).type d. borrow-out written to CC.z2.cc. a.s32 }.y1. .cc. No saturation.b32 subc. x4.cc.cc}.

wide}.0>.fxs. . If . and either the upper or lower half of the result is written to the destination register.wide // for .wide is specified. mul.. mul.0.wide. d = t<n-1. save only the low 16 bits // 32*32 bits. then d is twice as wide as a and b to receive the full result of the multiplication.hi or . mul{. Description Semantics Compute the product of two values. The . . 2010 67 .u32.fys. t = a * b.Chapter 8. .fys.s64 }.wide suffix is supported only for 16..s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi variant // for .lo. . // for . If . b.. d = t<2n-1. .type = { .u64. creates 64 bit result January 24.fxs. .type d.n>.u16.lo variant Notes The type of the operation represents the types of the a and b operands.s32 z.and 32-bit integer types. then d is the same size as a and b.hi.s16 fa. mul. Instruction Set Table 28. Supported on all target architectures.lo..lo is specified.x. n = bitwidth of type. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.y. // 16*16 bits yields 32 bits // 16*16 bits.s16.wide.s16 fa. d = t. a.

t n d d d = = = = = a * b. t<n-1.hi or . .lo.s32 type in . If .u64.and 32-bit integer types.wide // for .wide is specified. If .p. d.s32 r. 68 January 24.s32 d.c.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .n> + c.0. Saturation modifier: . mad{.. bitwidth of type.hi variant // for . and then writes the resulting value into a destination register. Supported on all target architectures. and either the upper or lower half of the result is written to the destination register. // for . The . .s32.hi mode. a.sat limits result to MININT. Applies only to .0> + c.b. b..u16.wide suffix is supported only for 16.u32. .lo.r.s16. mad. .q..lo variant Notes The type of the operation represents the types of the a and b operands..MAXINT (no overflow) for the size of the operation. c.hi. then d and c are twice as wide as a and b to receive the result of the multiplication. t + c.s64 }. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.sat. @p mad.s32 d.lo is specified.a. Description Semantics Multiplies two values and adds a third.lo.type mad. . c. then d and c are the same size as a and b.wide}. a.type = { .0 Table 29. t<2n-1.PTX ISA Version 2. b.hi. 2010 .

All operands are of the same type and size.s32 }. a.hi.0. mul24.s32 d. 2010 69 .hi may be less efficient on machines without hardware support for 24-bit multiply.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.a. .. i.0>. d = t<31.lo. .u32. b. January 24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24.e. 48bits. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24.type = { . // for . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers..16>. d = t<47. t = a * b. mul24{. Supported on all target architectures. and return either the high or low 32-bits of the 48-bit result. Instruction Set Table 30..hi variant // for . mul24.lo}. // low 32-bits of 24x24-bit signed multiply.Chapter 8.b.type d.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.

hi.a.hi variant // for . c. .type mad24. // low 32-bits of 24x24-bit signed multiply.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.MAXINT (no overflow). mad24{.lo. All operands are of the same type and size. 32-bit value to either the high or low 32-bits of the 48-bit result.16> + c.s32 }. d = t<47. mad24. mad24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32 d.hi may be less efficient on machines without hardware support for 24-bit multiply.type = { . mad24. Return either the high or low 32-bits of the 48-bit result. d = t<31. i.0. b.c.hi.PTX ISA Version 2.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. t = a * b. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. mad24.hi mode.b. 70 January 24. Description Compute the product of two 24-bit integer values held in 32-bit source registers.u32.sat limits result of 32-bit signed addition to MININT. c. a. b. a. // for ..0> + c. 48bits. . d.s32 d.sat.s32 type in .. Applies only to . Supported on all target architectures. 2010 .0 Table 31. Saturation modifier: .lo}...e.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. and add a third.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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For . the number of leading zeros is between 0 and 64.type d. popc Syntax Integer Arithmetic Instructions: popc Population count.0. the number of leading zeros is between 0 and 32. if (. . Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. while (a != 0) { if (a&0x1) d++. mask = 0x8000000000000000. } Introduced in PTX ISA version 2.b64 d.u32 Semantics 74 January 24.b64 }. .b32 type. popc requires sm_20 or later. a. .type = { .type = { .0 Table 39. inclusively.b32. d = 0.b32 clz.u32 PTX ISA Notes Target ISA Notes Examples Table 40. popc. cnt.PTX ISA Version 2. mask = 0x80000000. clz requires sm_20 or later.b64 type.type == . For . X. X. clz. // cnt is .b32 popc.b32. popc.0. clz. a = a >> 1. d = 0. inclusively.type d. // cnt is . clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. a = a << 1. a. 2010 . a. } else { max = 64.b32) { max = 32. } while (d < max && (a&mask == 0) ) { d++. a.b64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .b64 d. cnt.

bfind requires sm_20 or later.type = { . .u32. Instruction Set Table 41. a.type bfind.u32.shiftamt && d != -1) { d = msb . i--) { if (a & (1<<i)) { d = i.s32) ? 31 : 63. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. a. X. . bfind.u64. and operand d has type .u32 || . Operand a has the instruction type. d. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. Description Find the bit position of the most significant non-sign bit in a and place the result in d. // cnt is . If . bfind.0. 2010 75 . Semantics msb = (.shiftamt.s64 }.shiftamt. bfind returns 0xFFFFFFFF if no non-sign bit is found. For unsigned integers. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. .s32.u32 d.d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.Chapter 8.u32 January 24. a.s64 cnt. i>=0. bfind. For signed integers. bfind returns the bit position of the most significant “1”.type d. for (i=msb. } } if (. break.shiftamt is specified.type==.type==. . d = -1.

. 76 January 24. a. Description Semantics Perform bitwise reversal of input. brev.type = { .0 Table 42. msb = (.b32) ? 31 : 63. for (i=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b64 }. i<=msb.0.PTX ISA Version 2. . 2010 .type d.type==. brev requires sm_20 or later.b32.b32 d. a. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. brev. i++) { d[i] = a[msb-i].

bfe.msb)]. the result is zero. len = c. . Semantics msb = (.a. if (. bfe.u64 || len==0) sbit = 0.type==. If the start position is beyond the msb of the input. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. January 24. for (i=0. d = 0.u32.u32 || .u32. .type==. Description Extract bit field from a and place the zero or sign-extended result in d.s32) ? 31 : 63. c.u64.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. i<=msb.type==. . The destination d is padded with the sign bit of the extracted field.u32 || . b. the destination d is filled with the replicated sign bit of the extracted field.b32 d. . Source b gives the bit field starting bit position. bfe requires sm_20 or later.u64: . a. Operands a and d have the same type as the instruction type. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type d. The sign bit of the extracted field is defined as: . otherwise If the bit field length is zero.s32. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. .len. and source c gives the bit field length in bits.Chapter 8. and operands b and c are type . 2010 77 .start. else sbit = a[min(pos+len-1. .type==. Instruction Set Table 43.u32.0.type = { . pos = b.s32.s64 }.

u32.a.PTX ISA Version 2.b32 d. f = b. 2010 . and source d gives the bit field length in bits. a. Description Align and insert a bit field from a into b.b32) ? 31 : 63. len = d.len.0 Table 44.start.0. and operands c and d are type . 78 January 24. Source c gives the starting bit position for the insertion. and f have the same type as the instruction type. b. the result is b. pos = c. i++) { f[pos+i] = a[i].b32. . If the bit field length is zero. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. Semantics msb = (. b.type==. c. Operands a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. d.type f. bfi.b64 }. the result is b. . bfi.type = { .b. for (i=0. and place the result in f. i<len && pos+i<=msb. If the start position is beyond the msb of the input. bfi requires sm_20 or later.

rc8. b1. b2.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. . a 4-bit selection value is defined. prmt.b32{. b0}}. . the permute control consists of four 4-bit selection values. b4}. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b. b6.f4e. msb=0 means copy the literal value. {b3. 2010 79 . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.ecr. Description Pick four arbitrary bytes from two 32-bit registers. a} = {{b7. For each byte in the target register.b4e.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. c. Note that the sign extension is only performed as part of generic form. . .rc16 }.b2 source select c[11:8] d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. default mode index d. The bytes in the two source registers are numbered from 0 to 7: {b. b5.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.mode} d. as a 16b permute code.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.mode = { . Instruction Set Table 45.b3 source select c[15:12] d. In the generic form (no mode specified).ecl. the four 4-bit values fully specify an arbitrary byte permute.Chapter 8. and reassemble them into a 32-bit destination register. msb=1 means replicate the sign. The msb defines if the byte value should be copied. Thus. . . a.b1 source select c[7:4] d.

ctl[0]. 2010 .f4e r1. tmp64 ).0 Semantics tmp64 = (b<<32) | a. tmp64 ). r3. ctl[3]. tmp[31:24] = ReadByte( mode. ctl[1] = (c >> 4) & 0xf. ctl[2]. ctl[2] = (c >> 8) & 0xf. ctl[3] = (c >> 12) & 0xf. r2.b32. r1. r3.b32 prmt. prmt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp64 ). } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp[23:16] = ReadByte( mode. tmp64 ). } tmp[07:00] = ReadByte( mode.PTX ISA Version 2. ctl[1]. 80 January 24. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. tmp[15:08] = ReadByte( mode. r2. r4. r4. prmt requires sm_20 or later.0.

7.2. 2010 81 . Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8.f64 register operands and constant immediate values.f32 and . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.Chapter 8.

rnd. Instruction Summary of Floating-Point Instructions .target sm_20 . 1.full.f64 mad.PTX ISA Version 2.sqrt}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.f32 are the same. NaN payloads are supported for double-precision instructions.neg.min.sqrt}.f32 {abs.rcp. The optional .approx.rz .rn .f32 {div. No rounding modifier.0. but single-precision instructions return an unspecified NaN.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. {mad.sat Notes If no rounding modifier is specified. Note that future implementations may support NaN payloads for single-precision instructions.f32 .rm . Double-precision instructions support subnormal inputs and results.f32 rsqrt.f64 {sin.f32 {mad. Table 46.sub.rp . and mad support saturation of results to the range [0.f32 {div.fma}.rnd. {add.approx.max}.fma}.f32 {add. with NaNs being flushed to positive zero.target sm_1x No rounding modifier.0 The following table summarizes floating-point instructions in PTX.f64 div.sqrt}.mul}. 82 January 24.rcp.lg2.rcp.max}. Single-precision add.f64 rsqrt.rnd.rnd.32 and fma. so PTX programs should not rely on the specific single-precision NaNs being generated.approx.f32 {div. . If no rounding modifier is specified.target sm_20 mad. sub.rn and instructions may be folded into a multiply-add.min.rnd.cos.f64 and fma. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. mul. 2010 .approx.0]. .f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.mul}.ex2}.rnd.sub. default is .rn and instructions may be folded into a multiply-add. default is .f64 are the same.neg.f64 {abs.ftz .

f64 }.f32 copysign. 2010 83 .type = { . C.f32 testp.f64 isnan.notanumber testp.number testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. .normal testp.notanumber. not infinity) As a special case.finite. A.0. .op. Introduced in PTX ISA version 2.finite testp. a.f32. . copysign requires sm_20 or later. b. .subnormal }. X.f64 x. Instruction Set Table 47. January 24.pred = { . f0. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. copysign. not infinity). B. testp. .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. testp Syntax Floating-Point Instructions: testp Test floating-point property. y.infinite. positive and negative zero are considered normal numbers. . z. testp requires sm_20 or later. Table 48.op p. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. // result is .normal.infinite testp. copysign. a. true if the input is a subnormal number (not NaN.f32. and return the result as d.type d. testp.type . testp. .type = { .f64 }.0.number.notanumber. p.Chapter 8.infinite.

f2. .f64 d. 1.f32. Saturation modifier: .0 Table 49.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. add.f64 supports subnormal numbers.rn.f32 flushes subnormal inputs and results to sign-preserving zero.PTX ISA Version 2.rz. .f32 f1. .0.rm.f64 requires sm_13 or later. b.rp }.f32 supported on all target architectures. 2010 . add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn.rn): . Description Semantics Notes Performs addition and writes the resulting value into a destination register.rz.sat}. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. Rounding modifiers (default is .f32 clamps the result to [0.0.sat. sm_1x: add. add.rn mantissa LSB rounds to nearest even . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.ftz}{. a. .0f. a.rm mantissa LSB rounds towards negative infinity . 84 January 24.f32 add{. In particular. add.rm. subnormal numbers are supported. . An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. add. .rnd}.rz mantissa LSB rounds towards zero .rz available for all targets .rnd = { . Rounding modifiers have the following target requirements: . NaN results are flushed to +0. d = a + b.0]. add Syntax Floating-Point Instructions: add Add two values.rp for add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. requires sm_20 Examples @p add. add{.ftz.rnd}{. d.f3. b. requires sm_13 for add.f64.

Saturation modifier: sub. requires sm_20 Examples sub.f32 clamps the result to [0. a.f32 f1.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}{.Chapter 8.rp }.ftz.f32 c.rp for sub. Rounding modifiers have the following target requirements: . Instruction Set Table 50. January 24.b. 1.f2.rn mantissa LSB rounds to nearest even . sub{.f64 d.0.sat}.rn. . sub.ftz. requires sm_13 for sub.rnd}{.a. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sm_1x: sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another.f3. sub. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 sub{. NaN results are flushed to +0. d = a . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. In particular. 2010 85 .rz available for all targets . mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rm.rn): . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.f64. b.rn.rm. Rounding modifiers (default is .f32 flushes subnormal inputs and results to sign-preserving zero. sub.sat. sub.f64 requires sm_13 or later.f32 supported on all target architectures. b. subnormal numbers are supported.f64 supports subnormal numbers.rz mantissa LSB rounds towards zero .rn. . .rnd = { .0.b. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rz. .rm mantissa LSB rounds towards negative infinity . d. . a.0f.f32.0].rnd}. sub.

ftz}{.f64.f32 clamps the result to [0.f64 requires sm_13 or later. . a.0f.rp }.rn): .pi // a single-precision multiply 86 January 24.f32 flushes subnormal inputs and results to sign-preserving zero.0.rnd = { .f64 supports subnormal numbers.f32 circumf. requires sm_13 for mul. b. Saturation modifier: mul.rp for mul.PTX ISA Version 2. mul{. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. 1. all operands must be the same size. .ftz. d = a * b.rz available for all targets .f32.rm.f64 d. mul.rn mantissa LSB rounds to nearest even . For floating-point multiplication. a. d.0]. mul Syntax Floating-Point Instructions: mul Multiply two values.0 Table 51. sm_1x: mul.rz.rz mantissa LSB rounds towards zero . mul.rn. .rm mantissa LSB rounds towards negative infinity . Rounding modifiers have the following target requirements: . 2010 .rm. subnormal numbers are supported. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_20 Examples mul. Description Semantics Notes Compute the product of two values.f32 mul{.rnd}.radius.sat}.sat.rn. NaN results are flushed to +0. In particular. .0. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . mul. Rounding modifiers (default is .rnd}{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. mul.f32 supported on all target architectures. b.ftz.

Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.Chapter 8. 2010 87 .f32 computes the product of a and b to infinite precision and then adds c to this product.f32 is unimplemented in sm_1x.rn mantissa LSB rounds to nearest even .f32 introduced in PTX ISA version 2.sat}.f64 introduced in PTX ISA version 1.f64 requires sm_13 or later. a. Instruction Set Table 52.b. fma.rnd.sat. .f64 is the same as mad. fma Syntax Floating-Point Instructions: fma Fused multiply-add.ftz. fma.rnd = { .4.rnd{.x. subnormal numbers are supported.f32 fma. Rounding modifiers (no default): . fma.f64 d. NaN results are flushed to +0.rnd. .rm mantissa LSB rounds towards negative infinity .c. fma.rp }.f32 requires sm_20 or later. fma. sm_1x: fma.f32 fma.a. .0.f32 clamps the result to [0. d = a*b + c. 1.f32 flushes subnormal inputs and results to sign-preserving zero. fma. @p fma.rn.0.ftz}{.f64 computes the product of a and b to infinite precision and then adds c to this product. d. fma.y.ftz.0].f64 supports subnormal numbers. fma. b.rz. PTX ISA Notes Target ISA Notes Examples January 24.f64 w.rm.rz mantissa LSB rounds towards zero . fma. again in infinite precision. The resulting value is then rounded to double precision using the rounding mode specified by . fma. d. The resulting value is then rounded to single precision using the rounding mode specified by . c.rnd. . c.z.rn. Saturation: fma.f64. b. a.0f. again in infinite precision.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.

rnd.f32.f32 mad. again in infinite precision.rp }. but the exponent is preserved. the treatment of subnormal inputs and output follows IEEE 754 standard. fma. again in infinite precision.target sm_20: mad.{f32.ftz}{.f64 d.rz. Unlike mad. mad.ftz.sat}.0.f32 flushes subnormal inputs and results to sign-preserving zero.. . mad.rn mantissa LSB rounds to nearest even . d = a*b + c. Rounding modifiers (no default): . subnormal numbers are supported. // .0.target sm_20 d. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. c. mad.f32). . where the mantissa can be rounded and the exponent will be clamped.f64 is the same as fma. mad.rnd{. 1.0 devices. and then the mantissa is truncated to 23 bits.f32 is when c = +/-0. Note that this is different from computing the product with mul. 2010 .f32 is implemented as a fused multiply-add (i.e.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.PTX ISA Version 2.rm.sat}. again in infinite precision.rn. b.f64} is the same as fma.rnd = { . and then writes the resulting value into a destination register. 88 January 24.rm mantissa LSB rounds towards negative infinity . // .f32 mad. a. a. The resulting value is then rounded to double precision using the rounding mode specified by .target sm_1x d. mad. The resulting value is then rounded to single precision using the rounding mode specified by .sat.{f32.f64 supports subnormal numbers. NaN results are flushed to +0. sm_1x: mad.f64.rnd. mad. For . a.ftz.ftz}{.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. Saturation modifier: mad. mad.0 Table 53.target sm_1x: mad.rnd. In this case. The resulting value is then rounded to double precision using the rounding mode specified by .f32 flushes subnormal inputs and results to sign-preserving zero.f64}.rz mantissa LSB rounds towards zero . c.f64 computes the product of a and b to infinite precision and then adds c to this product. c. // . mad.f32 computes the product of a and b at double precision. The exception for mad. b. For .f32 computes the product of a and b to infinite precision and then adds c to this product.f32 is identical to the result computed using separate mul and add instructions.rnd.f64 computes the product of a and b to infinite precision and then adds c to this product.0f.0]. mad.target sm_13 and later . b.f32 clamps the result to [0. mad{. Description Semantics Notes Multiplies two values and adds a third. . When JIT-compiled for SM 2.rn.

f32 d.rn.rn. January 24. 2010 89 . Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rn.f32 supported on all target architectures.c.f32. In PTX ISA versions 2.. Rounding modifiers have the following target requirements: .rp for mad. Target ISA Notes mad. a rounding modifier is required for mad.4 and later.rz.a.rm.Chapter 8.f64. requires sm_13 . Legacy mad.rz..rm. mad..f64 instructions having no rounding modifier will map to mad.. a rounding modifier is required for mad.0 and later..f64.f64. In PTX ISA versions 1.f32 for sm_20 targets.0.rp for mad..f64 requires sm_13 or later.b. requires sm_20 Examples @p mad.

yd. and div.rp}. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .circum. div. div Syntax Floating-Point Instructions: div Divide one value by another.ftz}. The maximum ulp error is 2 across the full range of inputs.rm.f32 defaults to div.0.f32 implements a relatively fast.rn. full-range approximation that scales operands to achieve better accuracy.4.f64 defaults to div. Description Semantics Notes Divides a by b.4 and later.full.rz mantissa LSB rounds towards zero . one of .14159.full{.approx.f32 implements a fast approximation to divide. Fast.ftz}. b.PTX ISA Version 2.ftz. . stores result in d.f32 supported on all target architectures. x. . 2010 .full.0 Table 54. xd.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes div. d. .f32 div. subnormal numbers are supported.f32 div.approx.f64 requires sm_20 or later.f64 supports subnormal numbers. For PTX ISA version 1. 2126]. div.rnd{.f32 and div.rn mantissa LSB rounds to nearest even . d = a / b.rnd = { .full. Subnormal inputs and results are flushed to sign-preserving zero.full.rnd is required. div. For b in [2-126. y.f32 div. d. approximate single-precision divides: div. a.rp }. . // // // // fast.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b. computed as d = a * (1/b).rm.approx. approximate division by zero creates a value of infinity (with same sign as a).f64 requires sm_13 or later.f32 div.3. and rounding introduced in PTX ISA version 1.approx{. Explicit modifiers . Fast.ftz. div.rn. . div. div. b. a.ftz}.ftz.0 through 1. a.ftz. d. sm_1x: div. b. .f32 and div.f32 flushes subnormal inputs and results to sign-preserving zero. a.approx. div. zd.full. z.ftz.f64 d. div.3.f64.approx.{rz. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .rn.rz. or .rnd.f32 div.f64 diam.f32 requires sm_20 or later.rnd.rm mantissa LSB rounds towards negative infinity . Target ISA Notes div.approx.f64 introduced in PTX ISA version 1. For PTX ISA versions 1. but is not fully IEEE 754 compliant and does not support rounding modifiers. the maximum ulp error is 2. Examples 90 January 24. div.rn.f32.

abs{. Negate the sign of a and store the result in d.f32 supported on all target architectures. a. Table 56. abs. subnormal numbers are supported. a. Instruction Set Table 55.f64 supports subnormal numbers.f0. abs.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero. d = -a. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f64 d. subnormal numbers are supported.f64 requires sm_13 or later. January 24. NaN inputs yield an unspecified NaN. Subnormal numbers: sm_20: By default. neg.f32 x. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg. sm_1x: abs.f64 requires sm_13 or later.ftz.f32 supported on all target architectures.f32 neg.Chapter 8.f32 abs. NaN inputs yield an unspecified NaN. d. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.ftz}. d = |a|. 2010 91 .f64 d. a.ftz.f0. abs.0. Take the absolute value of a and store the result in d. d. neg.f64 supports subnormal numbers. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero. neg. abs.f32 flushes subnormal inputs and results to sign-preserving zero.0. abs.ftz. a. neg.ftz. sm_1x: neg.ftz}. Subnormal numbers: sm_20: By default. neg{.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

a. a.f64 d.f32 min. @p min.f32 supported on all target architectures. subnormal numbers are supported.z.f32 flushes subnormal inputs and results to sign-preserving zero. (a < b) ? a : b. sm_1x: min.PTX ISA Version 2.f2.ftz.0. Store the minimum of a and b in d. d d d d = = = = NaN.f64 supports subnormal numbers. max. min. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.c.f32 min. Store the maximum of a and b in d. min. max. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.x. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. d d d d = = = = NaN. max.f32 supported on all target architectures.f64 requires sm_13 or later. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f1.ftz}. 92 January 24. d. (a > b) ? a : b. max{. b.f32 max.b.0. a. min. b.ftz}. max. a. subnormal numbers are supported.f64 f0.c. min. a. b. a. b. Table 58.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 57.ftz.f64 supports subnormal numbers. a. b.f64 z.f64 d. min{.f64 requires sm_13 or later.ftz. sm_1x: max. max. 2010 . b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 max. d.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.

f64.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.rn.f32 rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. subnormal numbers are supported. d.0.0.rn. rcp.f32 and rcp. xi.f64 introduced in PTX ISA version 1. d = 1 / a.0 -Inf -Inf +Inf +Inf +0.rnd is required.f32 requires sm_20 or later.ftz were introduced in PTX ISA version 1.rp}.approx.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . rcp.rn mantissa LSB rounds to nearest even . 2010 93 .0 +0. PTX ISA Notes rcp. .f32 supported on all target architectures.approx{.approx. Description Semantics Notes Compute 1/a. Target ISA Notes rcp. store result in d.ftz}. rcp. xi.f32 rcp.f64 requires sm_20 or later.{rz.rp }.ftz}.f32 rcp. a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. The maximum absolute error is 2-23. one of .f32 implements a fast approximation to reciprocal. a.rn.rn. rcp. Instruction Set Table 59.rnd.Chapter 8. rcp. General rounding modifiers were added in PTX ISA version 2.f64 and explicit modifiers .ftz.f32. For PTX ISA versions 1.rnd{.3.0.f64 d. For PTX ISA version 1. rcp.rnd = { .rn.f32 defaults to rcp. rcp.0-2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: rcp.ftz.rnd.rm.rz.rm mantissa LSB rounds towards negative infinity . and rcp. . .4 and later.f64 ri.approx.4. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .0 over the range 1.approx or . rcp.rm. Examples January 24.x. d.f64 requires sm_13 or later.0 +subnormal +Inf NaN Result -0. a. rcp. // fast.f64 defaults to rcp.approx and .x.r.approx.rz mantissa LSB rounds towards zero .ftz.0 through 1. Input -Inf -subnormal -0.f64 supports subnormal numbers.rn.f32 rcp.

x.ftz}. // IEEE 754 compliant rounding .approx.f32 sqrt. sqrt.0 +0. General rounding modifiers were added in PTX ISA version 2. Examples 94 January 24. one of .f64 introduced in PTX ISA version 1.f32 is TBD.0 Table 60.f32 sqrt.rp }.ftz were introduced in PTX ISA version 1.rm mantissa LSB rounds towards negative infinity . approximate square root d. sm_1x: sqrt. sqrt. sqrt.approx{. sqrt.rnd is required.f32 supported on all target architectures.ftz. subnormal numbers are supported.0 +subnormal +Inf NaN Result NaN NaN -0. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f32 defaults to sqrt.f32 sqrt.0 -0.rm.f32 requires sm_20 or later. Target ISA Notes sqrt.f32 implements a fast approximation to square root.rn.rn mantissa LSB rounds to nearest even .x.ftz.rm. .0 +0. The maximum absolute error for sqrt.f64 and explicit modifiers . Input -Inf -normal -subnormal -0. sqrt.approx. sqrt. .f64 requires sm_13 or later.x.rnd. a.rz mantissa LSB rounds towards zero . and sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.approx.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rnd.rnd{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0 +0.f64 d.ftz.approx or .0.f32 and sqrt. r.rn.f32. r.f64 r.rp}.f64 requires sm_20 or later.{rz.ftz. Description Semantics Notes Compute sqrt(a).3. // fast. PTX ISA Notes sqrt.rn. a.approx. store in d.f32 flushes subnormal inputs and results to sign-preserving zero.f32 sqrt.rn.approx and .ftz}. For PTX ISA versions 1.rn.4.f64 defaults to sqrt.rz. 2010 .approx.0.PTX ISA Version 2. .rnd = { . d = sqrt(a). // IEEE 754 compliant rounding d.4 and later. For PTX ISA version 1. sqrt. sqrt.0 through 1. sqrt.f64 supports subnormal numbers.f64.rn. sqrt. a.

ISR.f64 is emulated in software and are relatively slow.f32 rsqrt. and rsqrt. X.f32 rsqrt. rsqrt.3.4. Note that rsqrt. Explicit modifiers . rsqrt.f32.0 NaN The maximum absolute error for rsqrt. d = 1/sqrt(a).approx.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. Input -Inf -normal -subnormal -0. For PTX ISA versions 1. January 24.f64 supports subnormal numbers. rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt.f64 isr. The maximum absolute error for rsqrt. For PTX ISA version 1. rsqrt.f32 defaults to rsqrt.f32 and rsqrt.f64 is TBD. x.f64.approx implements an approximation to the reciprocal square root. sm_1x: rsqrt.ftz.f32 is 2-22.approx and .ftz. Instruction Set Table 61.approx{. the . Subnormal numbers: sm_20: By default. subnormal numbers are supported.ftz}.0. d. rsqrt.approx.f64 were introduced in PTX ISA version 1. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. PTX ISA Notes rsqrt.approx.f32 supported on all target architectures. store the result in d.0. Target ISA Notes Examples rsqrt.approx. a.0 +0.ftz. 2010 95 .approx. Compute 1/sqrt(a).0 through 1.Chapter 8.approx modifier is required.ftz were introduced in PTX ISA version 1.f64 requires sm_13 or later. rsqrt.approx.4 and later. a.4 over the range 1.0-4.f64 d.f64 defaults to rsqrt.

approx{. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz.ftz}.0 +0.f32.4 and later.0 Table 62. 2010 . sin.approx modifier is required. sin. subnormal numbers are supported. sin. d = sin(a). Subnormal numbers: sm_20: By default. Input -Inf -subnormal -0. a.f32 introduced in PTX ISA version 1.0 -0. sin.f32 defaults to sin.PTX ISA Version 2. sin.approx.approx. 96 January 24. For PTX ISA versions 1.approx and .0 +subnormal +Inf NaN Result NaN -0.approx.0 through 1.f32 sa.f32 flushes subnormal inputs and results to sign-preserving zero. Find the sine of the angle a (in radians). Explicit modifiers . Target ISA Notes Examples Supported on all target architectures.ftz.4.9 in quadrant 00.0. PTX ISA Notes sin.ftz.3. a.ftz introduced in PTX ISA version 1.0 NaN NaN The maximum absolute error is 2-20. For PTX ISA version 1.f32 implements a fast approximation to sine.0 +0.f32 d. the . sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.0 +0.

f32. For PTX ISA versions 1. Explicit modifiers . cos. PTX ISA Notes cos.f32 defaults to cos. sm_1x: Subnormal inputs and results to sign-preserving zero. Target ISA Notes Examples Supported on all target architectures. d = cos(a). Subnormal numbers: sm_20: By default. a.0 through 1.0 +1.approx.f32 introduced in PTX ISA version 1.0 +0.0 +1. subnormal numbers are supported.4 and later.approx.f32 flushes subnormal inputs and results to sign-preserving zero.approx modifier is required.0 +1.Chapter 8.ftz. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. January 24.f32 d. cos. Input -Inf -subnormal -0.ftz introduced in PTX ISA version 1.0 +subnormal +Inf NaN Result NaN +1.approx{.4.3. cos. Find the cosine of the angle a (in radians). 2010 97 .ftz}. Instruction Set Table 63. cos.f32 implements a fast approximation to cosine. a.approx and .0 NaN NaN The maximum absolute error is 2-20. cos.ftz.f32 ca. For PTX ISA version 1.ftz. the .0.9 in quadrant 00.approx.

f32 la.approx. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz introduced in PTX ISA version 1.4 and later.3. Input -Inf -subnormal -0.approx{. lg2. Subnormal numbers: sm_20: By default. The maximum absolute error is 2-22.approx and . lg2.f32 defaults to lg2.approx modifier is required. For PTX ISA version 1.ftz}.ftz.0.f32 flushes subnormal inputs and results to sign-preserving zero.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. PTX ISA Notes lg2.0 Table 64. lg2.ftz.f32 Determine the log2 of a. a.0 +0. 98 January 24. subnormal numbers are supported. a.approx.f32 introduced in PTX ISA version 1.approx.f32 implements a fast approximation to log2(a).f32. d = log(a) / log(2). the .6 for mantissa.0 through 1. sm_1x: Subnormal inputs and results to sign-preserving zero. 2010 .ftz.PTX ISA Version 2. lg2. For PTX ISA versions 1. Explicit modifiers .4. Target ISA Notes Examples Supported on all target architectures. lg2.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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eq. higher. .s16. ge.f32. c). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. c).type = { . . . A related value computed using the complement of the compare result is written to the second destination operand. gtu. ne.PTX ISA Version 2.b64.and.f32 flushes subnormal inputs to sign-preserving zero. gt. leu.CmpOp{. subnormal numbers are supported. The comparison operator is a suffix on the instruction.f64 source type requires sm_13 or later. geu. .dtype. {!}c. and nan returns true if either operand is NaN. p.a.i. hi. le. ge. .f64 }.ftz. lt. the result is false. Integer Notes Floating Point Notes The ordered comparisons are eq. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. . xor. .dtype. The signed and unsigned comparison operators are eq. hi.dtype. gt. ge. and (optionally) combine this result with a predicate value by applying a Boolean operator. Modifier .B) is one of: and. This result is written to the first destination operand.u32. ne. gtu. If either operand is NaN. gt. lt.ftz}. Semantics t = (a CmpOp b) ? 1 : 0.b. The destinations p and q must be .u64. 2010 . hs equ. le. lo. ge. or.CmpOp. a. sm_1x: setp. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. If both operands are numeric values (not NaN). neu. .f32 comparisons. 102 January 24. setp. gt. nan The Boolean operator BoolOp(A. leu. bit-size comparisons are eq and ne. q = BoolOp(!t. For unsigned values. p = BoolOp(t. ls. b.s32 setp. setp.BoolOp{. a.type setp.u16.lt. and higher-or-same may be used instead of lt. ne. loweror-same. To aid comparison operations in the presence of NaN values. le. and can be one of: eq. The untyped. then these comparisons have the same result as their ordered counterparts. .f32 flushes subnormal inputs to sign-preserving zero. le. unordered versions are included: equ. lt.b32. @q setp.type . p[|q].ftz applies only to .u32 p|q. setp with . p[|q]. then the result of these comparisons is true.s64. num returns true if both operands are numeric values (not NaN). respectively.s32.b16. num. Subnormal numbers: sm_20: By default.0 Table 67. ltu. b. Applies to all numeric types. ls.f64 supports subnormal numbers. . ltu. neu. If either operand is NaN. setp.ftz}. the comparison operators lo. geu. and hs for lower.r.n.pred variables.

and b must be of the same type. y. Table 69. @q selp. .u16. .s32 slct{.u32. selp Syntax Comparison and Selection Instructions: selp Select between source operands.u64.u64.Chapter 8. . Semantics Floating Point Notes January 24. . . Operands d.f32.0. .type d.s64.type = { .b32. If c ≥ 0.f64 requires sm_13 or later. . b. d = (c >= 0) ? a : b.p. .f32 flushes subnormal values of operand c to sign-preserving zero.f32 comparisons.ftz. Operands d. a. slct. a. slct. slct.0.u64. based on the sign of the third operand. selp. and b are treated as a bitsize type of the same width as the first instruction type.f64 requires sm_13 or later. operand c must match the second instruction type.b16. Description Conditional selection. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .f32 comparisons. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. B. z. . .f32 r0.f64 }.t.u32.b64. Subnormal numbers: sm_20: By default. c. If c is True. b.dtype = { .r. For . otherwise b is stored in d.f64 }. .xp.ftz}.s32. .x. C. c.dtype. d = (c == 1) ? a : b. b.g.b32.ftz. c.dtype. sm_1x: slct. . . b otherwise. Instruction Set Table 68. Modifier .b64.s16. Introduced in PTX ISA version 1.b16.f32 d.s32. based on the value of the predicate source operand.u16. and operand a is selected. negative zero equals zero.f32.dtype. a.f32 flushes subnormal values of operand c to sign-preserving zero. The selected input is copied to the output without modification. the comparison is unordered and operand b is selected. If operand c is NaN. d. a. val.s32 x. fval. f0.dtype. slct Syntax Comparison and Selection Instructions: slct Select one source operand. a is stored in d. .u32. selp.ftz applies only to .s16. slct. . a is stored in d.s32 selp. .s64. . slct. . . . and operand a is selected. Operand c is a predicate. subnormal numbers are supported. 2010 103 .f32 A. a.

performing bit-wise operations on operands of any type.PTX ISA Version 2.0 8.4. This permits bit-wise operations on floating point values without having to define a union to access the bits.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. and not also operate on predicates. 2010 . or. xor. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. Instructions and. provided the operands are of the same size.

b16. a. The size of the operands must match.b16. .type = { .0. d = a | b. or. sign.pred p.b32 and.r.q. The size of the operands must match. Table 71.b32 x.r. Allowed types include predicate registers.b64 }. January 24. Introduced in PTX ISA version 1.b64 }. a. Introduced in PTX ISA version 1. Instruction Set Table 70.fpvalue. . but not necessarily the type.0. Supported on all target architectures. 2010 105 . Supported on all target architectures.type d. and. . . b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.pred.0x80000000. .b32. Allowed types include predicate registers.0x00010001 or. or. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. and Syntax Logic and Shift Instructions: and Bitwise AND. or Syntax Logic and Shift Instructions: or Bitwise OR.b32. and. .type d.pred. b.Chapter 8. but not necessarily the type. d = a & b. .b32 mask mask.type = { .q. .

0 Table 72. Allowed types include predicates. . not.pred.b32 d. .type = { .type = { . not.0. . a.b32.x.type = { . . . Supported on all target architectures.type d.b32 xor. .PTX ISA Version 2. Introduced in PTX ISA version 1. .0.b16 d. d = a ^ b. a. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. d = ~a.r.b32 mask.0x0001. a.b64 }. cnot.b64 }. Introduced in PTX ISA version 1. . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Allowed types include predicate registers. not Syntax Logic and Shift Instructions: not Bitwise negation. Table 73. .b64 }.mask.pred.type d. but not necessarily the type. . but not necessarily the type. Introduced in PTX ISA version 1. Supported on all target architectures. 2010 .b16. The size of the operands must match. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Supported on all target architectures. The size of the operands must match. The size of the operands must match.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.pred p. Table 74.type d.0. xor. cnot. d = (a==0) ? 1 : 0. b.b16. not. . one’s complement. d.b16. 106 January 24.q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.q.b32. xor.a.

. shl Syntax Logic and Shift Instructions: shl Shift bits left.b64 }.u16 shr. shl. .type d. shr. b. .u64. The sizes of the destination and first source operand must match. d = a << b. k.s16. but not necessarily the type.0. PTX ISA Notes Target ISA Notes Examples Table 76. Signed shifts fill with the sign bit. The sizes of the destination and first source operand must match. Introduced in PTX ISA version 1. unsigned and untyped shifts fill with 0.u16. Supported on all target architectures. The b operand must be a 32-bit value. .b16 c. . shl. 2010 107 .type = { . PTX ISA Notes Target ISA Notes Examples January 24.j. .i. sign or zero fill on left. regardless of the instruction type. d = a >> b. a.b64. Supported on all target architectures. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.2. shr Syntax Logic and Shift Instructions: shr Shift bits right. .b32 q.s64 }. Shift amounts greater than the register width N are clamped to N.s32 shr.b16.b32.type d.a.u32.b32. shr. .2. zero-fill on right. Introduced in PTX ISA version 1. .1. The b operand must be a 32-bit value.0. Bit-size types are included for symmetry with SHL. Shift amounts greater than the register width N are clamped to N.type = { . i. Instruction Set Table 75. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.s32.b16. b.i. regardless of the instruction type.a. . but not necessarily the type. . .Chapter 8. a.

2010 . ldu. mov. suld. st. possibly converting it from one format to another.PTX ISA Version 2.7. prefetchu isspacep cvta cvt 108 January 24. or shared state spaces. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and sust support optional cache operations. The cvta instruction converts addresses between generic and global. and from state space to state space.5. local. Data Movement and Conversion Instructions These instructions copy data from place to place. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.0 8. Instructions ld. ld. and st operate on both scalar and vector types.

.ca. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. the second thread may get stale L1 cache data.cs is applied to a Local window address.cs. likely to be accessed again. but multiple L1 caches are not coherent for global data. . The cache operators require a target architecture of sm_20 or later. 2010 109 . invalidates (discards) the local L1 line following the load.ca loads cached in L1. .cv to a frame buffer DRAM address is the same as ld. any existing cache lines that match the requested address in L1 will be evicted. rather than the data stored by the first thread. fetch again). if the line is fully covered. If one thread stores to global memory via one L1 cache.cg Cache at global level (cache in L2 and below.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.7.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. not L1).cs Cache streaming.ca. Global data is coherent at the L2 level.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. evict-first.lu instruction performs a load cached streaming operation (ld. The default load instruction cache operation is ld. The ld. to allow the thread program to poll a SysMem location written by the CPU.lu Last use. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. Cache Operators PTX 2. When ld. A ld. and cache only in the L2 cache. Use ld. The ld. For sm_20 and later.cg to cache loads only globally.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. As a result of this request.5.cs) on global addresses. when applied to a local address. Table 77. . Instruction Set 8.Chapter 8. it performs the ld.1.lu operation. The ld. the cache operators have the following definitions and behavior.0 introduces optional cache operators on load and store instructions.cv Cache as volatile (consider cached system memory lines stale. Operator . bypassing the L1 cache. The ld. likely to be accessed once. January 24. and a second thread loads that address via a second L1 cache with ld. The compiler / programmer may use ld.lu load last use operation.

cs Cache streaming. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. but st. In sm_20. Future GPUs may have globally-coherent L1 caches. . 2010 .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. The st.wt.wt store write-through operation applied to a global System Memory address writes through the L2 cache.PTX ISA Version 2.cg is the same as st.wb could write-back global store data from L1. Operator .cg to local memory uses the L1 cache. in which case st. If one thread stores to global memory. bypassing the L1 cache. The default store instruction cache operation is st. and a second thread in a different SM later loads from that address via a different L1 cache with ld.cg Cache at global level (cache in L2 and below.wb for global data. . not L1). 110 January 24. likely to be accessed once. However.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. and marks local L1 lines evict-first.wt Cache write-through (to system memory). and discard any L1 lines that match. Addresses not in System Memory use normal write-back. rather than get the data from L2 or memory stored by the first thread. . regardless of the cache operation. the second thread may get a hit on stale L1 cache data. st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.cg to cache global store data only globally.ca. Global stores bypass L1. Use st. The st. and cache only in the L2 cache. bypassing its L1 cache.0 Table 78. to allow a CPU program to poll a SysMem location written by the GPU with st.ca loads. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.wb. which writes back cache lines of coherent cache levels with normal eviction policy. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.

Description .0. within the variable’s declared state space Notes Although only predicate and bit-size types are required. sreg. special register.s64.Chapter 8.1. Write register d with the value of a.v. mov places the non-generic address of the variable (i. mov. d = sreg.0.f32 mov.s16. . . or function name. local. Semantics d = a. the parameter will be copied onto the stack and the address will be in the local state space.pred. local.e. Introduced in PTX ISA version 1.e. mov. Take the non-generic address of a variable in global. k. . Operand a may be a register. a. label.type mov. . For variables declared in . The generic address of a variable in global.type = { .b32..s32. . // address is non-generic. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. i.u32.const. . myFunc. variable in an addressable memory space.u32 mov.local.b16. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.b64. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. local.global. u. Note that if the address of a device function parameter is moved to a register. d = &label. // get address of variable // get address of label or function . or shared state space. avar. addr. ..u64. immediate.f32 mov. .type mov.u32 d. or shared state space may be taken directly using the cvta instruction. A. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. A[5].f64 }. d = &avar. d. and .type d. label.shared state spaces. d.u16. ptr. .type mov. mov.u16 mov. d.f32. . the generic address of a variable declared in global.u32 mov. ptr. 2010 111 .a. . the address of the variable in its state space) into the destination register. Instruction Set Table 79.f64 requires sm_13 or later. . alternately.

d.y.z << 32) | (a.b have type . Both the overall size of the vector and the size of the scalar must match the size of the instruction type.. a[32.x | (a.7].x. a[8.x.y } = { a[0. a[48.hi are . {lo. d.x | (a.w have type .47]. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.b16 { d.x.b.63] } // unpack 16-bit elements from .y << 16) d = a. . d..b32 %r1.b32 // pack four 16-bit elements into .b32 mov.w << 48) d = a.u32 x.y << 8) d = a.w}.b32 // pack two 16-bit elements into . lo.. %r1. . {r.7]. Semantics d = a... Supported on all target architectures.z. a[32. Description Write scalar register d with the packed value of vector register a. a[16.y.x.%r1.15].. d. mov. a[8.u16 %x is a double. For bit-size types. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).type = { .31]..z << 16) | (a.PTX ISA Version 2.y } = { a[0.b16 // pack four 8-bit elements into .b32.15] } // unpack 8-bit elements from .y.w << 24) d = a. d. mov.x. a[16..b64 mov.y << 32) // pack two 8-bit elements into .z.31].b32 { d.y << 8) | (a.w } = { a[0.type d. d.hi}. a.a have type .b16.y << 16) | (a.x | (a.b32 mov.0.0 Table 80.b}.z.a}.15].b64 { d.31] } // unpack 8-bit elements from .g.y } = { a[0. d.z..23].31] } // unpack 16-bit elements from .b64 }..b64 { d.x | (a.. a[16.b8 r. .{a.15].{x.b64 // pack two 32-bit elements into . // // // // a.b32 { d.b. d...u8 // unpack 32-bit elements from .63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.w } = { a[0.. %x.g. or write vector register d with the unpacked values from scalar register a. a[24. d.b64 112 January 24.y. 2010 .x | (a.

ca.b16.1. . 2010 113 . Cache operations are not permitted with ld. .local.const.cs. *(a+immOff).0. . . ld.type ld{.cop = { . . The value loaded is sign-extended to the destination register width for signed integers.type d. Generic addressing and cache operations introduced in PTX ISA 2.cv }.lu. . to enforce sequential consistency between threads accessing shared memory.s64.vec.Chapter 8. Generic addressing may be used with ld. The address size may be either 32-bit or 64-bit.. In generic addressing.type . Within these windows.ss}.shared spaces to inhibit optimization of references to volatile memory. . . ld.param.volatile{. [a]. Addresses are zero-extended to the specified width as needed. . . perform the load using generic addressing.e. [a]. A destination register wider than the specified type may be used. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .volatile introduced in PTX ISA version 1.reg state space.b16. If no state space is given.f32 or .f64 }.u64. [a]. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.v4 }. This may be used. . If an address is not properly aligned.e.b8.type = { . .ss}{. the access may proceed by silently masking off low-order address bits to achieve proper rounding. for example.cop}.type ld. d. PTX ISA Notes January 24. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. d. . . ld introduced in PTX ISA version 1.u16.ss}{.s16. an address maps to global memory unless it falls within the local memory window or the shared memory window. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . an integer or bit-size type register reg containing a byte address. .s8.u32. 32-bit).volatile. i. .vec = { . *a.f16 data may be loaded using ld. i.s32. Description Load register variable d from the location specified by the source address operand a in specified state space.global. the resulting behavior is undefined.b64. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.b32. . The address must be naturally aligned to a multiple of the access size.v2. ld{. The . an address maps to the corresponding location in local or shared memory. . or the instruction may fault.ss}. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .volatile{. and then converted to .global and . .const space suffix may have an optional bank number to indicate constant banks other than bank zero.cop}. . 32-bit).shared }. or [immAddr] an immediate absolute byte address (unsigned.f64 using cvt. d.vec.u8.f32.ss = { .volatile. . . *(immAddr).cg. Instruction Set Table 81. Semantics d d d d = = = = a. [a]. .0. and is zeroextended to the destination register width for unsigned and bit-size types. and truncated if the register width exceeds the state space address width for the target architecture.volatile may be used with .

ld.[a].f32. x.0 Target ISA Notes ld.local. // access incomplete array x.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. Q.[buffer+64]. 2010 .[240]. // negative offset %r. // immediate address %r. Generic addressing requires sm_20 or later.[fs].b16 cvt.[p].[p+4].local.b32 ld.const.b32 ld.const[4].f16 d.global.%r.PTX ISA Version 2. // load .v4.b32 ld.f64 requires sm_13 or later. Cache operations require sm_20 or later.global. %r.b64 ld.[p+-8]. d.s32 ld.f32 ld.shared.

to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // load from address // vec load from address . 2010 115 . ldu{.f64 requires sm_13 or later. If no state space is given.reg state space. . .f32 or . .vec. ldu. The addressable operand a is one of: [avar] the name of an addressable variable var.e. . The data at the specified address must be read-only. The value loaded is sign-extended to the destination register width for signed integers.[p].[a]. and is zeroextended to the destination register width for unsigned and bit-size types. *(immAddr). an address maps to global memory unless it falls within the local memory window or the shared memory window. A destination register wider than the specified type may be used.ss = { . *(a+immOff). .e. In generic addressing. i.global. ldu. *a. .b64.type ldu{.type = { . .b16.u8. 32-bit). ldu.global.v4 }. and truncated if the register width exceeds the state space address width for the target architecture.[p+4]. If an address is not properly aligned. .vec = { . . .global. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. Semantics d d d d = = = = a. For ldu. or the instruction may fault. Addresses are zero-extended to the specified width as needed. 32-bit).type d.f32. .v2. perform the load using generic addressing.global }.s32. PTX ISA Notes Target ISA Notes Examples January 24. the resulting behavior is undefined.b16. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. or [immAddr] an immediate absolute byte address (unsigned. an address maps to the corresponding location in local or shared memory.0.v4. Within these windows. [areg] a register reg containing a byte address. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.ss}.Chapter 8.u64.f32 d.b8.s16. . only generic addresses that map to global memory are legal.f16 data may be loaded using ldu.b32 d.f64 }.s64. i.b32. where the address is guaranteed to be the same across all threads in the warp. [a]. ldu. // state space . the access may proceed by silently masking off low-order address bits to achieve proper rounding. and then converted to . . .s8. d. A register containing an address may be declared as a bit-size type or integer type.u16. Introduced in PTX ISA version 2.f32 Q. The address size may be either 32-bit or 64-bit. [a]. The address must be naturally aligned to a multiple of the access size.u32.ss}. Instruction Set Table 82..f64 using cvt. .

cs. . [a].e.v2. .type st. PTX ISA Notes Target ISA Notes 116 January 24. [a]. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. Generic addressing requires sm_20 or later. or [immAddr] an immediate absolute byte address (unsigned.0.shared spaces to inhibit optimization of references to volatile memory. .1. { .b16.cop}. and truncated if the register width exceeds the state space address width for the target architecture.type st{.shared }.volatile. Semantics d = a. the resulting behavior is undefined. . .0 Table 83.type .volatile may be used with .e. or the instruction may fault. . for example.u16.u8.volatile.f16 data resulting from a cvt instruction may be stored using st. [a]. Generic addressing and cache operations introduced in PTX ISA 2.vec. . Within these windows.b8. The address must be naturally aligned to a multiple of the access size. an address maps to the corresponding location in local or shared memory.ss .b64. i. Cache operations are not permitted with st. *d = a.. Generic addressing may be used with st. to enforce sequential consistency between threads accessing shared memory. The lower n bits corresponding to the instruction-type width are stored to memory. .global and . { . *(d+immOffset) = a.type = = = = {. an address maps to global memory unless it falls within the local memory window or the shared memory window.u32.u64. The address size may be either 32-bit or 64-bit. . .f64 }. st. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. b.v4 }.volatile{. Addresses are zero-extended to the specified width as needed. . st. b. an integer or bit-size type register reg containing a byte address. . b.global.type [a].s64.ss}. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. { . st. 2010 . In generic addressing.wb.vec .b16. . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.s32.f32.s8.ss}{. .reg state space.cop}. 32-bit).f64 requires sm_13 or later. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .volatile{. . This may be used.vec.s16. st{.cg. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. i. If no state space is given. st introduced in PTX ISA version 1.0.ss}.b32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. the access may proceed by silently masking off low-order address bits to achieve proper rounding.wt }. b. .ss}{.PTX ISA Version 2. . perform the store using generic addressing. 32-bit). A source register wider than the specified type may be used. *(immAddr) = a.cop .volatile introduced in PTX ISA version 1. If an address is not properly aligned. . Cache operations require sm_20 or later. .local.

a.f16.a. [q+-8].v4.Chapter 8. [p].local. // %r is 32-bit register // store lower 16 bits January 24. Instruction Set Examples st.%r. 2010 117 .s32 cvt. // negative offset [100].global.r7. [fs].Q.b32 st.b.f32 st.b16 [a].f32 st.global.s32 st.local.%r. // immediate address %r.local. [q+4].b32 st.

prefetch{. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.space = { . prefetchu Prefetch line containing generic address at specified level of memory hierarchy. in specified state space.L1 [addr]. Addresses are zero-extended to the specified width as needed. A prefetch to a shared memory location performs no operation. In generic addressing. prefetchu. the prefetch uses generic addressing.0 Table 84. or [immAddr] an immediate absolute byte address (unsigned. The address size may be either 32-bit or 64-bit.global.global. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. 32-bit). an address maps to the corresponding location in local or shared memory.space}. Within these windows. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. A prefetch into the uniform cache requires a generic address. a register reg containing a byte address. and no operation occurs if the address maps to a local or shared memory location.L1 [ptr]. [a].e. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. 2010 . and truncated if the register width exceeds the state space address width for the target architecture.L1.level prefetchu. // prefetch to data cache // prefetch to uniform cache . 118 January 24. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.0. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.L2 }. 32-bit).L1 [a]. i.local }. prefetch and prefetchu require sm_20 or later. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. an address maps to global memory unless it falls within the local memory window or the shared memory window. . .PTX ISA Version 2. prefetch. . If no state space is given.level = { .

isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. isshrd.shared.u64. or shared address to a generic address. cvta.u32. local. sptr. When converting a generic address into a global.genptr.u64.local. a.local isspacep. The source and destination addresses must be the same size. Introduced in PTX ISA version 2. a.shared }. isspacep. cvta requires sm_20 or later. gptr. . // get generic address of svar cvta.shared }. var.space p.space = { . 2010 119 .to. isspacep requires sm_20 or later.size = { .to. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. or shared address. // local.global isspacep. or vice-versa. cvta. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. a. local.u32 or .size . or shared state space to generic. Description Convert a global. local. local.space. islcl.u32 to truncate or zero-extend addresses.Chapter 8. .space.space = { .u32 p. p.u64 or cvt.pred. or shared state space. svar.pred . local. // result is . or shared address cvta. p.local. cvta. January 24.u32 gptr.u64 }. lptr.lptr. . // convert to generic address // get generic address of var // convert generic address to global. isspacep.global.shared isglbl.size p. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . For variables declared in global.global. Use cvt. The destination register must be of type .u32.0.space. or shared state space. or vice-versa.local.u32 p. The source address operand must be a register of type .0. A program may use isspacep to guard against such incorrect behavior. Take the generic address of a variable declared in global. the generic address of the variable may be taken using cvta.size cvta. . PTX ISA Notes Target ISA Notes Examples Table 86.global. Instruction Set Table 85.

atype d.sat}.sat For integer destination types. .f64 }.ftz. 120 January 24.rmi round to nearest integer in direction of negative infinity . .dtype.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.u64.MAXINT for the size of the operation.f32 float-to-integer conversions and cvt.f32 float-tofloat conversions with integer rounding.rm. .4 and earlier. cvt{. the result is clamped to the destination range by default.frnd}{. .rzi round to nearest integer in the direction of zero .s32.sat limits the result to MININT.ftz.atype = { ..s8.dtype = .f32 float-to-integer conversions and cvt. a. For float-to-integer conversions. . i.ftz modifier may be specified in these cases for clarity. . sm_1x: For cvt.rzi.ftz.f32 float-tofloat conversions with integer rounding. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.PTX ISA Version 2. Integer rounding is required for float-to-integer conversions. i. d = convert(a).sat is redundant. . .ftz. .rmi.rni. Integer rounding is illegal in all other instances.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.rni round to nearest integer.u32.rz. .rpi }.dtype.u16. Saturation modifier: . Note: In PTX ISA versions 1.frnd = { . 2010 . // integer rounding // fp rounding . choosing even integer if source is equidistant between two integers. a.0 Table 87.f32. and for same-size float-tofloat conversions where the value is rounded to an integer. The compiler will preserve this behavior for legacy PTX code.sat}.f32. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rp }. subnormal inputs are flushed to signpreserving zero. Integer rounding modifiers: .ftz}{.u8. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.e.irnd = { . Description Semantics Integer Notes Convert between different types and sizes. the .ftz}{. . Note that saturation applies to both signed and unsigned integer types.dtype. For cvt.e.dtype. . .s64. . . . .s16. . subnormal inputs are flushed to signpreserving zero. subnormal numbers are supported.atype cvt{..rn.f16. d.f32.irnd}{. . The optional . . .

sat limits the result to the range [0. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. Applies to . NaN results are flushed to positive zero. cvt to or from . The result is an integral value.i.4 or earlier. // note .rz mantissa LSB rounds towards zero .f64 requires sm_13 or later. Floating-point rounding is illegal in all other instances. 1.r. cvt. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.0].f32 x. Saturation modifier: .f16. stored in floating-point format. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).sat For floating-point destination types. Subnormal numbers: sm_20: By default. Note: In PTX ISA versions 1. Floating-point rounding modifiers: .s32. . result is fp cvt. The compiler will preserve this behavior for legacy PTX code.rni. and .f16.ftz modifier may be specified in these cases for clarity.f32. Modifier .f64 types.f32. The optional .y.f32.version is 1.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.0.f32.f32.y.f32. cvt. Specifically.4 and earlier. .f32.ftz behavior for sm_1x targets January 24.f32 x.f64 j. // float-to-int saturates by default cvt.f64. subnormal numbers are supported.Chapter 8.s32 f. if the PTX . and cvt.0.rn mantissa LSB rounds to nearest even . and for integer-to-float conversions.rm mantissa LSB rounds towards negative infinity .f32 instructions. The operands must be of the same size. Introduced in PTX ISA version 1. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. 2010 121 .f16. // round to nearest int. cvt.

PTX supports the following operations on texture. [tex1]. and surfaces. but the number of samplers is greatly restricted to 16.b32 r5. In the unified mode.height. {f1. mul. .r3.f2}]. [tex1.0 8. r3. samplers.f32 r1.PTX ISA Version 2. and surface descriptors: • • • Static initialization of texture. . allowing them to be defined separately and combined at the site of usage in the program. r3.f32. A PTX module may declare only one texturing mode.r2. texture and sampler information each have their own handle.v4. . r5. r1. In the independent mode. r1. r4. Texturing modes For working with textures and samplers. The advantage of independent mode is that textures and samplers can be mixed and matched. r6. cvt.target texmode_independent . and surface descriptors. Module-scope and per-entry scope definitions of texture.f32 r3. r2. and surface descriptors.f32 r1.6.param .texref handle. // get tex1’s txq.samplerref tsamp1 = { addr_mode_0 filter_mode }. PTX has two modes of operation. Example: calculate an element’s power contribution as element’s power/total number of elements.global .. r1. Ability to query fields within texture.f32. add.7.. add.target options ‘texmode_unified’ and ‘texmode_independent’. sampler. The texturing mode is selected using . and surface descriptors. sampler. with the restriction that they correspond 1-to-1 with the 128 possible textures.u32 r5. Texture and Surface Instructions This section describes PTX instructions for accessing textures.width. The advantage of unified mode is that it allows 128 samplers.entry compute_power ( . add. [tex1]. r5. 2010 .b32 r6. div. 122 January 24.2d.u32 r5.f32 r1. texture and sampler information is accessed through a single .f32 {r1. the file is assumed to use unified mode.r4}. } = clamp_to_border. sampler. If no texturing mode is declared.texref tex1 ) { txq. // get tex1’s tex. sampler. = nearest width height tsamp1. r5.

c]. [tex_a.r2. the resulting behavior is undefined. c]. If an address is not properly aligned.r4}. //Example of unified mode texturing tex. [tex_a.dtype.Chapter 8. and is a four-element vector for 3d textures.geom = { . . Description Texture lookup using a texture coordinate vector.geom.f2. b. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. . // explicit sampler . // Example of independent mode texturing tex.3d }. [a. tex.s32.dtype.e. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. [a. or the instruction may fault.btype = { .btype d.v4.f4}]. An optional texture sampler b may be specified.r2.s32. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.geom.v4. PTX ISA Notes Target ISA Notes Examples January 24.v4. d.btype tex. . with the extra elements being ignored.r4}. is a two-element vector for 2d textures. .f32 }.2d.v4. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.s32 {r1.5. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.f32 {r1. the square brackets are not required and . .v4 coordinate vectors are allowed for any geometry. Operand c is a scalar or singleton tuple for 1d textures. Notes For compatibility with prior versions of PTX.1d..r3. . Supported on all target architectures.dtype = { . tex txq suld sust sured suq Table 88.0. the access may proceed by silently masking off low-order address bits to achieve proper rounding. {f1. Unified mode texturing introduced in PTX ISA version 1. the sampler behavior is a property of the named texture.f3.3d.r3. . i.1d. Instruction Set These instructions provide access to texture and surface memory.u32. 2010 123 . A texture base address is assumed to be aligned to a 16-byte address. The instruction always returns a four-element vector of 32-bit values.s32.s32. where the fourth element is ignored. {f1}].f32 }. If no sampler is specified. sampler_x.

filter_mode. . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.5.width. sampler attributes are also accessed via a texref argument. In unified mode. .filter_mode. [smpl_B].squery = { .width .normalized_coords }.PTX ISA Version 2. [a]. clamp_ogl. [tex_A]. txq.b32 %r1. linear } Integer from enum { wrap. // unified mode // independent mode 124 January 24.tquery.tquery = { . 2010 . Integer from enum { nearest. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mirror. and in independent mode sampler attributes are accessed via a separate samplerref argument.texref or . Description Query an attribute of a texture or sampler.b32 %r1. clamp_to_edge.depth . Operand a is a .addr_mode_0.b32 txq. Query: . Supported on all target architectures. . txq. addr_mode_2 }. txq. [tex_A].squery.samplerref variable. // texture attributes // sampler attributes .b32 d.depth.0 Table 89. .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. [a].filter_mode . txq.height .height.normalized_coords .addr_mode_1 .width.b32 %r1. d. addr_mode_1.addr_mode_0 . .addr_mode_0.

and the size of the data transfer matches the size of destination operand d.b64.b8 . .b performs an unformatted load of binary data. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.dtype . suld Syntax Texture and Surface Instructions: suld Load from surface memory. // formatted .b32. . [a. sm_1x targets support only the . then .trap {r1. if the surface format contains SINT data.u32 is returned.e.v4 }. 2010 125 . and is a four-element vector for 3d surfaces.trap suld.y.dtype. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b supported on all target architectures.cop . If the destination base type is . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.clamp suld.f32 based on the surface format as follows: If the surface format contains UNORM. then . .f32. Instruction Set Table 90.u32.geom .p. [surf_B. i. suld. then .s32.u32. suld. if the surface format contains UINT data.surfref variable.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. and cache operations introduced in PTX ISA version 2.cs. B.dtype .r2}. suld. . . or the instruction may fault.f2. // cache operation none. suld. If the destination type is .clamp = = = = = = { { { { { { d. suld.s32 is returned. . suld. . .clamp . .cg.b16. // for suld.v2. the access may proceed by silently masking off low-order address bits to achieve proper rounding.p is currently unimplemented. suld.v4. suld.trap introduced in PTX ISA version 1. G.3d requires sm_20 or later.b. Operand a is a .b64 }. is a two-element vector for 2d surfaces.vec.3d }.geom{. {x.clamp. b].trap. Destination vector elements corresponding to components that do not appear in the surface format are not written.s32.f32.b.Chapter 8. Coordinate elements are of type . . .1d.vec . . b]. Description Load from surface memory using a surface coordinate vector.w}].b. or . [surf_A.b .5.p .clamp .cop}..u32. size and type conversion is performed as needed to convert from the surface sample format to the destination type. .3d. {f1.f32 is returned. The .p. suld. A surface base address is assumed to be aligned to a 16-byte address.f4}.b32.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.cv }.s32.geom{.trap . . . .1d.p requires sm_20 or later.v2.2d. . . // for suld.trap clamping modifier.f32 }. where the fourth element is ignored. [a. Operand b is a scalar or singleton tuple for 1d surfaces. Target ISA Notes Examples January 24. {x}].clamp field specifies how to handle out-of-bounds addresses: .cop}. or FLOAT data. The lowest dimension coordinate represents a sample offset rather than a byte offset. .0. and A components of the surface format.b32. additional clamp modifiers. SNORM. the surface sample elements are converted to .ca.z. or . the resulting behavior is undefined.dtype.zero }.p. If an address is not properly aligned.s32.v4.f3. // unformatted d. Cache operations require sm_20 or later.

These elements are written to the corresponding surface sample components.ctype. Target ISA Notes Examples 126 January 24. then .s32. sust. b]. the resulting behavior is undefined. . . c.{u32. . [a. sust Syntax Texture and Surface Instructions: sust Store to surface memory.clamp field specifies how to handle out-of-bounds addresses: . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap introduced in PTX ISA version 1.trap [surf_A.3d }.p. .b32.5. Coordinate elements are of type . The . .v2. .p performs a formatted store of a vector of 32-bit data values to a surface sample.3d. G.cs.b.clamp sust.v2.u32.PTX ISA Version 2.w}]. b]. . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. then .p.wt }.f32 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The size of the data transfer matches the size of source operand c. .cop}. and cache operations introduced in PTX ISA version 2. sust. Operand a is a .f32. or . then . The source data is then converted from this type to the surface sample format. .geom{.e.geom . A surface base address is assumed to be aligned to a 16-byte address.b16. or FLOAT data.f32 is assumed. and A surface components. none.cop}.b8 .vec .trap. sust. sust.. The source vector elements are interpreted left-to-right as R.cg.y.s32. 2010 . .2d. size and type conversions are performed as needed between the surface sample format and the destination type. The lowest dimension coordinate represents a sample offset rather than a byte offset.f3. {f1.surfref variable. if the surface format contains UINT data. // for sust.f32} are currently unimplemented. If the source type is .b supported on all target architectures.b // for sust. where the fourth element is ignored.r2}.3d requires sm_20 or later.f4}.b64.zero }. additional clamp modifiers. Surface sample components that do not occur in the source vector will be written with an unpredictable value. .b32.trap sust.1d.p requires sm_20 or later.ctype.v4. Cache operations require sm_20 or later.b64 }.0.b32.ctype . .v4 }. . .u32. . sust. B. {x}]. is a two-element vector for 2d surfaces.f32.b.1d.geom{.clamp. and is a four-element vector for 3d surfaces.trap clamping modifier.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. sust.f2. if the surface format contains SINT data. sust.s32.clamp .vec.u32 is assumed.clamp .p. [surf_B.cop .wb. sust. . // unformatted // formatted . {x.s32 is assumed. SNORM. .s32.z.b.p. Operand b is a scalar or singleton tuple for 1d surfaces.vec. sm_1x targets support only the . sust. i. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. . {r1. c. If the source base type is .0 Table 91.trap . Source elements that do not occur in the surface sample are ignored.b performs an unformatted store of binary data. . If an address is not properly aligned.ctype . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.clamp = = = = = = { { { { { { [a. .p Description Store to surface memory using a surface coordinate vector. or the instruction may fault.

The lowest dimension coordinate represents a sample offset rather than a byte offset. // for sured. sured requires sm_20 or later. sured. .c. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32.s32 is assumed. .u32. .1d.. If an address is not properly aligned. i.b32 type.2d.s32.trap . .max. {x. .b.s32 types.ctype = { .clamp field specifies how to handle out-of-bounds addresses: . sured.c.s32 types.u32 is assumed. r1. or the instruction may fault. and . and the data is interpreted as .p . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. is a two-element vector for 2d surfaces.min. if the surface format contains SINT data.s32.b32.u64. .2d.1d. sured.min.zero }. Operations add applies to .b]. then .geom. January 24.clamp [a. sured.u32.y}]. 2010 127 .0. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp [a.u64 data. . . Instruction Set Table 92.and.Chapter 8.s32. .surfref variable.trap [surf_A.clamp = { .3d }.clamp . // for sured.b performs an unformatted reduction on .s32 or . min and max apply to .p.geom = { .u64.b. Operand b is a scalar or singleton tuple for 1d surfaces. where the fourth element is ignored.or }.op. . // byte addressing sured.b32 }.p performs a reduction on sample-addressed 32-bit data.add. or .u32 and .p. The . The instruction type is restricted to . .u32. . . // sample addressing .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. {x}].clamp.b]. Reduction to surface memory using a surface coordinate vector.trap.ctype = { . r1. .trap sured.b32. [surf_B.op.add. .b32. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. and is a four-element vector for 3d surfaces.geom. A surface base address is assumed to be aligned to a 16-byte address. then .e.ctype.ctype. Coordinate elements are of type . Operand a is a . the resulting behavior is undefined. operations and and or apply to . .op = { . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.u32 based on the surface sample format as follows: if the surface format contains UINT data.b .b32 }.

Description Query an attribute of a surface. . 128 January 24.height . 2010 .b32 d. Query: .height.width .width.query = { .width. suq. Supported on all target architectures.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. [surf_A]. [a].query. . suq.0 Table 93.b32 %r1. Operand a is a .PTX ISA Version 2.surfref variable. .depth }.5.

7. Threads with a false guard predicate do nothing.a. Execute an instruction or instruction block for threads that have the guard predicate true. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. { add. 2010 129 .0. mov.b.0. Supported on all target architectures. Supported on all target architectures.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Table 95. Introduced in PTX ISA version 1.s32 d. Instruction Set 8. {} Syntax Description Control Flow Instructions: { } Instruction grouping. p. @{!}p instruction. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. setp.0. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.x. ratio.eq.f32 @q bra L23.y. If {!}p then instruction Introduced in PTX ISA version 1.s32 a. { instructionList } The curly braces create a group of instructions.f32 @!p div. used primarily for defining a function body.c.7.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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bar.red. Execution in this case is unpredictable. bar.u32 bar. The reduction operations for bar. thread count.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.red are population-count (.popc). d. thread count.or). it simply marks a thread's arrival at the barrier. if any thread in a warp executes a bar instruction. threads within a CTA that wish to communicate via memory can store to memory.arrive using the same active barrier.and. Register operands. all threads in the CTA participate in the barrier.sync) until the barrier count is met.red should not be intermixed with bar.red also guarantee memory ordering among threads identical to membar.red delays the executing threads (similar to bar.or }. All threads in the warp are stalled until the barrier completes. and bar. b. The result of . and the barrier is reinitialized so that it can be immediately reused. b.and and . The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. When a barrier completes.{arrive. Barriers are executed on a per-warp basis as if all the threads in a warp are active. Register operands.{arrive. the waiting threads are restarted without delay. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.red instruction.version 2.red performs a predicate reduction across the threads participating in the barrier.red} introduced in PTX . . {!}c.0.popc is the number of threads with a true predicate.sync and bar. Instruction Set Table 100.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.sync and bar. a{.red.15. Only bar. and bar. If no thread count is specified.sync bar.arrive.popc. Operands a. bar.u32. bar. and any-thread-true (. b}.pred . In conditionally executed code.sync or bar. a{.sync 0.arrive a{.. Once the barrier count is reached. the bar. p. a. bar. {!}c. the optional thread count must be a multiple of the warp size.0. Since barriers are executed on a per-warp basis.sync with an immediate barrier number is supported for sm_1x targets. bar. the final value is written to the destination register in all threads waiting at the barrier. In addition to signaling its arrival at the barrier. Note that a non-zero thread count is required for bar. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). Each CTA instance has sixteen barriers numbered 0. all-threads-true (.sync without a thread count introduced in PTX ISA 1. bar. b}. and then safely read values stored by other threads prior to the barrier. b}. and d have type . PTX ISA Notes Target ISA Notes Examples bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. bar. it is as if all the threads in the warp have executed the bar instruction. January 24.op = { .red performs a reduction operation across threads.cta.sync or bar.red} require sm_20 or later. execute a bar. Thus. Description Performs barrier synchronization and communication within a CTA. The barrier instructions signal the arrival of the executing threads at the named barrier. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. while . operands p and c are predicates. 2010 133 .arrive does not cause any waiting by the executing threads. Thus.op.and). and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Operand b specifies the number of threads participating in the barrier. bar.Chapter 8.

{cta. 134 January 24. when the previous value can no longer be read. that is. .level = { .sys introduced in PTX .sys Waits until all prior memory requests have been performed with respect to all clients.g.level.gl. membar.0 Table 101.gl.sys.0. 2010 .sys requires sm_20 or later.{cta. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. PTX ISA Notes Target ISA Notes Examples membar.4. membar. by st. membar. . red or atom) has been performed when the value written has become visible to other clients at the specified level.PTX ISA Version 2. level describes the scope of other clients for which membar is an ordering event. Waits until prior memory reads have been performed with respect to other threads in the CTA. global.sys }. membar.gl.version 2.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. A memory read (e.gl} supported on all target architectures. A memory write (e. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar. membar. For communication between threads in different CTAs or even different SMs. membar. membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar. or system memory level. membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.cta. . including thoses communicating via PCI-E such as system and peer-to-peer memory.gl will typically have a longer latency than membar.cta. membar. this is the appropriate level of membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.version 1. membar. and memory reads by this thread can no longer be affected by other thread writes.sys will typically have much longer latency than membar.cta.g.gl} introduced in PTX .

max }. Within these windows. . . i. an address maps to the corresponding location in local or shared memory. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. and exch (exchange). January 24. dec.or. inc. and max operations are single-precision. by inserting barriers between normal stores and atomic operations to a common address. .u64 . Operand a specifies a location in the specified state space. . performs a reduction operation with operand b and the value in location a. . .type atom{.s32. .s32. an address maps to global memory unless it falls within the local memory window or the shared memory window. min. i. If no state space is given. min.space}. . overwriting the original value. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. accesses to local memory are illegal. the resulting behavior is undefined.add. [a]. The inc and dec operations return a result in the range [0.f32. min.b32. c. The floating-point add. In generic addressing. a de-referenced register areg containing a byte address. e.space}.u32. The bit-size operations are and.b64 .u32 only . Instruction Set Table 102.op.inc.cas.min.f32 Atomically loads the original value at location a into destination register d. . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. atom. . The address must be naturally aligned to a multiple of the access size.exch to store to locations accessed by other atomic operations. . The address size may be either 32-bit or 64-bit. .e. .e.b64. xor. . b. and max.add. .space = { .. or by using atom. .u64. A register containing an address may be declared as a bit-size type or integer type. 2010 135 .type d. . max.exch. and truncated if the register width exceeds the state space address width for the target architecture.Chapter 8. .b].global. or the instruction may fault.op = { . The integer operations are add.dec. . [a]. perform the memory accesses using generic addressing.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.b32.xor. b.s32. atom{. For atom.. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.b32 only . . If an address is not properly aligned.type = { . . .shared }. or [immAddr] an immediate absolute byte address.u32. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.u32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.g.f32 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. or. . Description // // // // // . d.and. 32-bit operations. cas (compare-and-swap). The floating-point operations are add. . Addresses are zero-extended to the specified width as needed. and stores the result of the specified operation at location a.op.

f32 requires sm_20 or later.[p]. s) = (r >= s) ? 0 dec(r.f32 atom.s.1. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom. s) = s. c) operation(*a.global. 64-bit atom.my_new_val. atom.0 Semantics atomic { d = *a.PTX ISA Version 2.0.b32 d.add.max} are unimplemented. 64-bit atom.s32 atom.0.global requires sm_11 or later.exch} requires sm_12 or later. atom.shared requires sm_12 or later.add. b).shared operations require sm_20 or later. : r+1. Release Notes Examples @p 136 January 24.max. d. 2010 . atom. *a = (operation == cas) ? : } where inc(r.[a].cas. : r-1.f32. Use of generic addressing requires sm_20 or later.t) = (r == s) ? t operation(*a.my_val.global.cas. s) = (r > s) ? s exch(r. b.shared. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. cas(r.{min. Introduced in PTX ISA version 1.{add. : r. d. atom.[x+4].

xor.u32 only .space = { . where inc(r.min. .dec. an address maps to the corresponding location in local or shared memory.type [a].e. For red.u32. and xor. The bit-size operations are and. accesses to local memory are illegal. i. max.or. b. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.e. Description // // // // . The inc and dec operations return a result in the range [0. or by using atom. perform the memory accesses using generic addressing. .and. and stores the result of the specified operation at location a.u64 .b32 only .Chapter 8. s) = (r >= s) ? 0 : r+1. If no state space is given. .b]. or.type = { . Operand a specifies a location in the specified state space. . min.g.b64. The integer operations are add. . inc. i. dec. 32-bit operations.exch to store to locations accessed by other reduction operations. . If an address is not properly aligned.. In generic addressing. . by inserting barriers between normal stores and reduction operations to a common address. .u32. .op. 2010 137 . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.u32. . Addresses are zero-extended to the specified width as needed.b32. The address size may be either 32-bit or 64-bit. b). . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . The address must be naturally aligned to a multiple of the access size. an address maps to global memory unless it falls within the local memory window or the shared memory window. s) = (r > s) ? s : r-1. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. . . or [immAddr] an immediate absolute byte address. the access may proceed by silently masking off low-order address bits to achieve proper rounding. dec(r.inc.s32. overwriting the original value. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.op = { . . red.space}. January 24. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. or the instruction may fault..add.f32 Performs a reduction operation with operand b and the value in location a.f32.f32 }. the resulting behavior is undefined. Notes Operand a must reside in either the global or shared state space. . .shared }. The floating-point add. and truncated if the register width exceeds the state space address width for the target architecture. . min. a de-referenced register areg containing a byte address. min. e.max }.u64. A register containing an address may be declared as a bit-size type or integer type. Semantics *a = operation(*a.add. and max operations are single-precision. . . Within these windows. and max.s32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 103. red{. . The floating-point operations are add.s32.global.

s32 red.1.b32 [a].0.shared operations require sm_20 or later.f32 requires sm_20 or later.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.add requires sm_12 or later. Use of generic addressing requires sm_20 or later.PTX ISA Version 2.max} are unimplemented. red.f32.my_val.max.shared. [x+4].add.global requires sm_11 or later red.and. [p]. Release Notes Examples @p 138 January 24.global. 64-bit red.2.shared requires sm_12 or later. 2010 . red. red.global. 64-bit red.{min. red.add.f32 red.

pred vote. In the ‘ballot’ form. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. not across an entire CTA. Note that vote applies to threads in a single warp.b32 requires sm_20 or later.all.uni }.uni.mode. returns bitmask . vote. Instruction Set Table 104.b32 d.ballot. The reduction modes are: . {!}a.ballot.mode = { . vote.q. vote. {!}a. . r1. vote requires sm_12 or later. vote. .not_all.any True if source predicate is True for some active thread in warp.p.uni.pred vote. Negating the source predicate also computes .q.ballot. where the bit position corresponds to the thread’s lane id.2. vote. p.any. .Chapter 8.none. 2010 139 . Negate the source predicate to compute . The destination predicate value is the same across all threads in the warp.b32 p. Description Performs a reduction of the source predicate across threads in a warp. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.all True if source predicate is True for all active threads in warp.ballot.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.pred d.all. Negate the source predicate to compute . // get ‘ballot’ across warp January 24. // ‘ballot’ form.uni True if source predicate has the same value in all active threads in warp. .

the input values are extracted and signor zero.dtype.u32. The source and destination operands are all 32-bit registers.atype. b{.dsel.b0.PTX ISA Version 2. or word values from its source operands.add.max }.secop = { .bsel = { . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).b1.9.bsel}. The general format of video instructions is as follows: // 32-bit scalar operation.0 8. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. 4.btype{.btype = { . 3.btype{. 2.s33 values.secop d. .asel}. taking into account the subword destination size in the case of optional data merging. atype. and btype are valid. The sign of the intermediate result depends on dtype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. // 32-bit scalar operation. . . b{.s32) is specified in the instruction type. 2010 .b3. all combinations of dtype.u32 or .sat} d.7. .asel = .s32 }.sat}. . a{. . a{.asel}. c. 140 January 24. .extended internally to .dtype.s34 intermediate result. half-word.btype{.atype.dsel = . with optional data merge vop. a{.or zero-extend byte. .dtype.bsel}. perform a scalar arithmetic operation to produce a signed 34-bit result.min. with optional secondary operation vop.atype.sat} d. b{.h1 }.asel}. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. . Video Instructions All video instructions operate on 32-bit register operands.h0. vop. . c. optionally clamp the result to the range of the destination type. The primary operation is then performed to produce an . . to produce signed 33-bit input values.dtype = . extract and sign.bsel}.b2.atype = . Using the atype/btype and asel/bsel specifiers. The type of each operand (.

max return MAX(tmp.s33 c) { switch ( secop ) { . c). tmp. . .b1.Chapter 8.h1: return ((tmp & 0xffff) << 16) case . S32_MAX. . U16_MIN ). default: return tmp. c).b0: return ((tmp & 0xff) case . Bool sat.s33 optSecOp(Modifier secop.s33 c ) switch ( dsel ) { case . U32_MAX. Modifier dsel ) { if ( !sat ) return tmp. The lower 32-bits are then written to the destination operand. S8_MAX. .b3: if ( sign ) return CLAMP( else return CLAMP( case . . c).s34 tmp. . U32_MIN ). S8_MIN ). tmp. 2010 141 . Bool sign.b3: return ((tmp & 0xff) << 24) default: return tmp.b2: return ((tmp & 0xff) << 16) case . January 24. U16_MAX. . . S16_MIN ).s33 tmp. tmp.b1: return ((tmp & 0xff) << 8) case . S16_MAX. . Instruction Set .b2.h0.s33 optSaturate( .s33 tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). c). .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. as shown in the following pseudocode. tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. U8_MIN ).add: return tmp + c.b0. . c). tmp. The sign of the c operand is based on dtype. c).h0: return ((tmp & 0xffff) case . c). switch ( dsel ) { case .min: return MIN(tmp. } } . U8_MAX.s33 optMerge( Modifier dsel. S32_MIN ).

Perform scalar arithmetic operation with optional saturate. r2. atype.asel}. . with optional secondary operation vop.s32 }.b3. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. vsub. vop. vmin.op2 d. tmp.atype. . .s32.b0. vsub. a{. . c.PTX ISA Version 2.u32. Video Instructions: vadd. r1.add r1.h0.u32.sat vsub.vop .h1.s32.atype. vabsdiff.dtype.sat} d.sat vabsdiff. vsub vabsdiff vmin. c. r1.asel}.asel}.b2. a{. b{. isSigned(dtype). // 32-bit scalar operation. vabsdiff.max }.s32.atype. c ). . vmin.bsel = { . d = optSecondaryOp( op2.s32.bsel}.b2. r3.sat} d. vmax vadd.dtype .btype{. btype. . { . tmp = MIN( ta. tmp = MAX( ta.s32.bsel}. Semantics // saturate. c.sat.s32. r2.s32. 2010 .bsel}.b0.h1 }.s32.dtype.b0. r1. vsub. dsel ).sat}. tb ). c. vmax }. . .dsel. c ).min.h0. tmp = | ta – tb |.dtype.btype{.sat vmin.s32.0. tmp.h1. . a{. r3. r2.0 Table 105.s32.b1.btype{.atype = . // optional secondary operation d = optMerge( dsel. b{. b{. . bsel ). taking into account destination type and merge operations tmp = optSaturate( tmp.op2 Description = = = = { vadd. tmp = ta – tb. vmax Syntax Integer byte/half-word/word addition / subtraction. r3. with optional data merge vop. vabsdiff. // extract byte/half-word/word and sign.dsel . asel ). vadd. vadd.add.asel = . tb ).h0.btype = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // 32-bit scalar operation.or zero-extend based on source operand type ta = partSelectSignExtend( a. . Integer byte/half-word/word minimum / maximum. r3. r2. vmin. sat. // optional merge with c operand 142 January 24. tb = partSelectSignExtend( b. and optional secondary arithmetic operation or subword data merge.u32. vmax require sm_20 or later. Integer byte/half-word/word absolute value of difference.

{ . r2.bsel}.op2 Description = = = = = { vshl.asel}. tmp. asel ). . . vshl: Shift a left by unsigned amount in b with optional saturate. switch ( vop ) { case vshl: tmp = ta << tb.dsel .vop .wrap ) tb = tb & 0x1f. b{.atype. .h0. r3.atype. bsel ).min.mode} d. a{. vshr require sm_20 or later.b0.bsel}. vshr vshl. .or zero-extend based on source operand type ta = partSelectSignExtend( a.wrap }. r3. c ). vshl.atype. vshr }. // default is .u32{.u32. with optional data merge vop.s32. d = optSecondaryOp( op2.u32 vshr.u32.Chapter 8. unsigned shift fills with zero. case vshr: tmp = ta >> tb.dsel. with optional secondary operation vop. . and optional secondary arithmetic operation or subword data merge. Instruction Set Table 106.wrap r1.dtype. { . vshr: Shift a right by unsigned amount in b with optional saturate. 2010 143 .dtype. January 24.b1. isSigned(dtype).h1.0. b{. c ).u32{.dtype. // 32-bit scalar operation.u32. c.bsel}.op2 d.sat}{. r1. b{. c.bsel = { . a{. Signed shift fills with the sign bit. sat. Semantics // extract byte/half-word/word and sign. . Left shift fills with zero. vshr Syntax Integer byte/half-word/word left / right shift. atype. // 32-bit scalar operation.add. r2.max }. Video Instructions: vshl. if ( mode == . and optional secondary arithmetic operation or subword data merge.clamp . . dsel ). vop.u32.u32{. if ( mode == . .asel}.asel}. . tmp. vshl.u32.u32.s32 }.h1 }. } // saturate. tb = partSelectSignExtend( b. taking into account destination type and merge operations tmp = optSaturate( tmp.clamp.sat}{. a{.mode} d. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat}{.b3. . .dtype .asel = .mode}. // optional secondary operation d = optMerge( dsel. .clamp && tb > 32 ) tb = 32.b2.atype = { .mode .

Description Calculate (a*b) + c. and the operand negates. internally this is represented as negation of the product (a*b).scale} d. a{. {-}a{. final signed -(S32 * S32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift.. final signed (S32 * S32) . .dtype = . The source operands support optional negation with some restrictions.shr15 }. PTX allows negation of either (a*b) or c. final signed (S32 * S32) + S32 // intermediate signed.scale} d. with optional operand negates.sat}{. vmad. . Input c has the same sign as the intermediate result.atype. .po mode.btype.b2. // 32-bit scalar operation vmad. final signed (U32 * S32) + S32 // intermediate signed. That is.0 Table 107. . 144 January 24.dtype. c.sat}{. final signed (S32 * U32) .scale = { . b{.S32 // intermediate signed. .u32.S32 // intermediate signed. {-}c.po{.asel}. final signed -(S32 * U32) + S32 // intermediate signed. .PTX ISA Version 2.po) computes (a*b) + c + 1. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. which is used in computing averages. .h1 }.bsel = { . Source operands may not be negated in . The final result is unsigned if the intermediate result is unsigned and c is not negated. Although PTX syntax allows separate negation of the a and b operands.b1.asel}. (a*b) is negated if and only if exactly one of a or b is negated.dtype. the intermediate result is signed.atype = . and zero-extended otherwise. final signed (U32 * U32) .atype.b3. .shr7. final unsigned -(U32 * U32) + S32 // intermediate signed. final signed (U32 * S32) . “plus one” mode.bsel}. .b0. . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.h0.btype = { .bsel}. 2010 . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. and scaling. The “plus one” mode (.U32 // intermediate unsigned.s32 }. this result is sign-extended if the final result is signed.asel = .btype{.S32 // intermediate signed. final signed -(U32 * S32) + S32 // intermediate signed. {-}b{. final signed (S32 * U32) + S32 // intermediate signed. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. Depending on the sign of the a and b operands. otherwise.

vmad. tmp[127:0] = ta * tb. btype. U32_MAX. } else if ( c. U32_MIN). lsb = 1.negate ^ b. r3.s32. r1. atype. case .Chapter 8. bsel ). -r3. r1. Instruction Set Semantics // extract byte/half-word/word and sign.u32. vmad requires sm_20 or later. lsb = 1. r0. signedFinal = isSigned(atype) || isSigned(btype) || (a. S32_MAX.negate) || c. asel ). January 24.po ) { lsb = 1.negate.shr15 r0. lsb = 0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.u32.0. 2010 145 . } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). switch( scale ) { case .shr7: result = (tmp >> 7) & 0xffffffffffffffff. } if ( . } else if ( a.s32.h0. S32_MIN).u32. tb = partSelectSignExtend( b. if ( .sat ) { if (signedFinal) result = CLAMP(result. r2. else result = CLAMP(result.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a. r2.negate ^ b. tmp = tmp + c128 + lsb.sat vmad.negate ) { c = ~c.h0.negate ) { tmp = ~tmp. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

lt vset.b2.atype. .asel}. and therefore the c operand and final result are also unsigned. tmp.bsel = { . bsel ).dsel. .lt. b{. c. .cmp d.b1. c ).u32. .asel = .ne r1.btype.cmp d.s32 }. asel ). btype.atype . 2010 . r2. c ). vset. { .b0. vset requires sm_20 or later. r3. cmp ) ? 1 : 0. a{. tmp.add. . .u32.cmp .bsel}.h1 }.dsel .btype = { . b{.op2 Description = = = = .asel}.le.ge }.op2 d. The intermediate result of the comparison is always unsigned. tmp = compare( ta. a{. .bsel}. d = optSecondaryOp( op2.asel}. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. c.btype.atype. 146 January 24. with optional data merge vset. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .bsel}.0 Table 108. .gt.ne.h0.eq. r2.btype. Compare input values using specified comparison. vset.min. atype. . . // optional secondary operation d = optMerge( dsel. with optional secondary arithmetic operation or subword data merge.cmp. with optional secondary operation vset. // 32-bit scalar operation. . . r1.0. .atype. Semantics // extract byte/half-word/word and sign.or zero-extend based on source operand type ta = partSelectSignExtend( a.max }. .h1.s32. { .PTX ISA Version 2. a{.u32. tb = partSelectSignExtend( b. b{. r3.b3.u32. // 32-bit scalar operation. tb.

brkpt Suspends execution Introduced in PTX ISA version 1. 2010 147 . there are sixteen performance monitor events. trap.0. Supported on all target architectures. Table 110. Instruction Set 8.4. Table 111. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Notes PTX ISA Notes Target ISA Notes Examples Currently. @p pmevent 1. The relationship between events and counters is programmed via API calls from the host. trap Abort execution and generate an interrupt to the host CPU.7. January 24. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. numbered 0 through 15. Supported on all target architectures.0. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. brkpt. Triggers one of a fixed number of performance monitor events. trap. pmevent 7. with index specified by immediate operand a. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. pmevent a. Introduced in PTX ISA version 1. brkpt requires sm_11 or later. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.10.Chapter 8. Introduced in PTX ISA version 1. brkpt.

2010 .PTX ISA Version 2.0 148 January 24.

Chapter 9. Special Registers PTX includes a number of predefined. %clock64 %pm0. %pm3 January 24. %lanemask_lt. 2010 149 . %lanemask_ge. %lanemask_gt %clock. …. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_le. which are visible as special registers and accessed through mov or cvt instructions. read-only variables.

y < %ntid. Every thread in the CTA has a unique %tid.u32. .u32 %ntid. or 3D vector to match the CTA shape. PTX ISA Notes Introduced in PTX ISA version 1. // CTA shape vector // CTA dimensions A predefined.u32 type in PTX 2.z. .x. %ntid.0 Table 112.PTX ISA Version 2. %tid.x. %ntid. Supported on all target architectures.u16 %rh.x.u16 %r2.0. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u32 %r0.z < %ntid.z == 0 in 2D CTAs.u32 %tid.z == 1 in 2D CTAs. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. The fourth element is unused and always returns zero.x < %ntid.y. mov.u32 %r0. mov. // zero-extend tid.u32 %h1. CTA dimensions are non-zero. the %tid value in unused dimensions is 0.sreg . // compute unified thread id for 2D CTA mov.0. .y * %ntid.v4 .x code accessing 16-bit component of %tid mov. mov. %tid.x * %ntid.%tid.u32 %h2.z == 1 in 1D CTAs.y 0 <= %tid. 2010 .z.0.x.%tid.y. %ntid.v4. Redefined as . // legacy PTX 1.x to %rh Target ISA Notes Examples // legacy PTX 1.x.x code Target ISA Notes Examples 150 January 24.z to %r2 Table 113. Redefined as .u32 %ntid.x.%h2. The %tid special register contains a 1D.sreg .z). Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. // move tid. mad. The total number of threads in a CTA is (%ntid.%r0.sreg .%tid.v4. The number of threads in each dimension are specified by the predefined special register %ntid.z == 0 in 1D CTAs. %tid. the fourth element is unused and always returns zero.y == %ntid.%ntid. .y.y == %tid.u32 %r1.z PTX ISA Notes Introduced in PTX ISA version 1.%tid.0. %ntid.v4 . 2D.z.u32 type in PTX 2.x 0 <= %tid.u32 %tid. Supported on all target architectures. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. %tid component values range from 0 through %ntid–1 in each CTA dimension.sreg . read-only special register initialized with the number of thread ids in each CTA dimension. read-only.%tid.%ntid. cvt.%h1. mov. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. // thread id vector // thread id components A predefined. per-thread special register initialized with the thread identifier within the CTA.x.u16 %rh. It is guaranteed that: 0 <= %tid. %tid.

mov. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.sreg . For this reason. . Introduced in PTX ISA version 1. 2010 151 . The lane identifier ranges from zero to WARP_SZ-1. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. The warp identifier will be the same for all threads within a single warp.u32 %r. read-only special register that returns the maximum number of warp identifiers.3.u32 %nwarpid. e.u32 %warpid. .g. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. A predefined. read-only special register that returns the thread’s warp identifier.u32 %r.3. Introduced in PTX ISA version 2. Introduced in PTX ISA version 1. %laneid. A predefined. %warpid. %nwarpid requires sm_20 or later. . due to rescheduling of threads following preemption.sreg . Note that %warpid is volatile and returns the location of a thread at the moment when read. %nwarpid. Supported on all target architectures. Table 115. A predefined. but its value may change during execution. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. mov.u32 %r.0. Supported on all target architectures.u32 %laneid. Special Registers Table 114.sreg . mov. January 24.Chapter 9. PTX ISA Notes Target ISA Notes Examples Table 116. read-only special register that returns the thread’s lane within the warp. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.

y < %nctaid.0. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. // Grid shape vector // Grid dimensions A predefined. read-only special register initialized with the CTA identifier within the CTA grid.u32 %ctaid. // CTA id vector // CTA id components A predefined.sreg .x.{x.u32 mov. %ctaid.z.%nctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. with each element having a value of at least 1.y. %ctaid.z < %nctaid. mov. Supported on all target architectures.z PTX ISA Notes Introduced in PTX ISA version 1.x < %nctaid. . Supported on all target architectures. read-only special register initialized with the number of CTAs in each grid dimension. The fourth element is unused and always returns zero.x.sreg .z} < 65.x. 2010 . 2D. The fourth element is unused and always returns zero. %rh. .y.0.x.u32 %nctaid .x code Target ISA Notes Examples Table 118.sreg .0 Table 117.x.536 PTX ISA Notes Introduced in PTX ISA version 1.%nctaid. It is guaranteed that: 0 <= %ctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.%nctaid.x 0 <= %ctaid.%ctaid.sreg . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.y.v4 . The %nctaid special register contains a 3D grid shape vector.u32 type in PTX 2.u32 %nctaid.0.y 0 <= %ctaid.u16 %r0.u32 type in PTX 2. It is guaranteed that: 1 <= %nctaid. Redefined as .PTX ISA Version 2.%nctaid. The %ctaid special register contains a 1D. depending on the shape and rank of the CTA grid.0.y.u16 %r0.z.%ctaid. mov.v4. . // legacy PTX 1. // legacy PTX 1.v4 . or 3D vector.x code Target ISA Notes Examples 152 January 24. %rh. Each vector element value is >= 0 and < 65535.u32 mov.u32 %ctaid.v4. Redefined as .

u32 %gridid.0.sreg . Introduced in PTX ISA version 1. due to rescheduling of threads following preemption. %gridid. .Chapter 9.u32 %nsmid. During execution. . // initialized at grid launch A predefined. Note that %smid is volatile and returns the location of a thread at the moment when read. PTX ISA Notes Target ISA Notes Examples Table 121.u32 %r. %smid. where each launch starts a grid-of-CTAs.u32 %r. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. repeated launches of programs may occur. mov. This variable provides the temporal grid launch number for this context. Notes PTX ISA Notes Target ISA Notes Examples Table 120. 2010 153 . The SM identifier numbering is not guaranteed to be contiguous. read-only special register that returns the maximum number of SM identifiers. Supported on all target architectures. Introduced in PTX ISA version 1. Special Registers Table 119.0. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. The SM identifier numbering is not guaranteed to be contiguous.3. PTX ISA Notes Target ISA Notes Examples January 24.u32 %smid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. e.sreg . The SM identifier ranges from 0 to %nsmid-1. A predefined. so %nsmid may be larger than the physical number of SMs in the device.u32 %r. .sreg . Introduced in PTX ISA version 2. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.g. Supported on all target architectures. mov. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %nsmid requires sm_20 or later. %nsmid. mov. A predefined. but its value may change during execution. read-only special register initialized with the per-grid temporal grid identifier.

read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.PTX ISA Version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . %lanemask_lt requires sm_20 or later.0. A predefined.0.u32 %lanemask_eq. mov.u32 %r. 2010 . mov.sreg . Introduced in PTX ISA version 2.u32 %r.0 Table 122. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. Table 123. 154 January 24. %lanemask_le. %lanemask_eq. Introduced in PTX ISA version 2. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.sreg .u32 %lanemask_le. . . %lanemask_eq requires sm_20 or later. %lanemask_le requires sm_20 or later.0. Table 124. %lanemask_lt. A predefined.u32 %lanemask_lt. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.u32 %r. mov. A predefined.sreg .

u32 %r.sreg . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r.u32 %lanemask_gt. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. 2010 155 . January 24. %lanemask_ge. Introduced in PTX ISA version 2.u32 %lanemask_ge. mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg . %lanemask_gt.0. Introduced in PTX ISA version 2. . . A predefined. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov.Chapter 9. A predefined. %lanemask_ge requires sm_20 or later. Special Registers Table 125. Table 126.0. %lanemask_gt requires sm_20 or later.

The lower 32-bits of %clock64 are identical to %clock. Their behavior is currently undefined. mov. %pm2. . mov.0. ….sreg . Introduced in PTX ISA version 1. Supported on all target architectures. Introduced in PTX ISA version 1. Introduced in PTX ISA version 2. 156 January 24.u32 r1. %pm2. %pm2. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. read-only 32-bit unsigned cycle counter.sreg . %pm3 %pm0. read-only 64-bit unsigned cycle counter.%clock. 2010 .0.u64 r1. %pm1. and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm1. Table 128. mov.sreg .u32 r1. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.%clock64. . %pm1. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Special registers %pm0.3.0 Table 127. %pm3. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.%pm0. Table 129.u32 %clock.u32 %pm0. %clock64 requires sm_20 or later.PTX ISA Version 2. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special Registers: %pm0.u64 %clock64. Supported on all target architectures. .

0 .Chapter 10. Directives 10. and the target architecture for which the code was generated. .0.version 2. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Increments to the major number indicate incompatible changes to PTX. minor are integers Specifies the PTX language version number. 2010 157 .version directives are allowed provided they match the original .version 1.version Syntax Description Semantics PTX version number. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. . . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version major. Each ptx file must begin with a .version directive.minor // major.1.version .4 January 24.version .version directive. Duplicate . PTX File Directives: . Supported on all target architectures.target Table 130.

texref and . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.samplerref descriptors.f64 instructions used.f64 instructions used.f32. In general. Texturing mode introduced in PTX ISA version 1. The texturing mode is specified for an entire module and cannot be changed within the module. texture and sampler information is referenced with independent . The following table summarizes the features in PTX that vary according to target architecture. Target sm_20 Description Baseline feature set for sm_20 architecture. Therefore. Requires map_f64_to_f32 if any .red}. Texturing mode: (default is . 2010 .0 Table 131. PTX code generated for a given target can be run on later generation devices. .target directive containing a target architecture and optional platform options. Supported on all target architectures.target Syntax Architecture and Platform target. sm_10. 64-bit {atom. texmode_unified. 158 January 24. Note that . Each PTX file must begin with a .0. texmode_independent. sm_11. with only half being used by instructions converted from .target .f64 storage remains as 64-bits. PTX features are checked against the specified target architecture. A program with multiple . Introduced in PTX ISA version 1. Requires map_f64_to_f32 if any .red}. sm_12.target directive specifies a single target architecture.global. including expanded rounding modifiers. PTX File Directives: .shared. Adds double-precision support. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Adds {atom. brkpt instructions. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.texref descriptor.f64 to . immediately followed by a . Adds {atom. Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_13.red}. vote instructions.version directive.texmode_unified) . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.target directives can be used to change the set of target features allowed during parsing. where each generation adds new features and retains all features of previous generations. Disallows use of map_f64_to_f32.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.global.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.PTX ISA Version 2. and an error is generated if an unsupported feature is used. A .texmode_unified . map_f64_to_f32 }. generations of SM architectures follow an “onion layer” model.f64 instructions used. Requires map_f64_to_f32 if any .5.texmode_independent texture and sampler information is bound together and accessed via a single . but subsequent .

target sm_10 // baseline target architecture . texmode_independent January 24. 2010 159 . Directives Examples .Chapter 10.target sm_20.target sm_13 // supports double-precision .

entry Syntax Description Kernel entry point and body. [z].0 10. . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.entry . ld. parameter variables are declared in the kernel parameter list.2.param. Supported on all target architectures.b32 %r<99>.func Table 132. PTX ISA Notes For PTX ISA version 1. with optional parameters.param. . . Parameters may be referenced by name within the kernel body and loaded into registers using ld.4.3. [y]. . For PTX ISA versions 1. parameter variables are declared in the kernel body. … } . Parameters are passed via .entry kernel-name ( param-list ) kernel-body . parameters.entry cta_fft .b32 z ) Target ISA Notes Examples [x].reg . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. 160 January 24. The shape and size of the CTA executing the kernel are available in special registers. %nctaid.g.param . %ntid.5 and later.entry .param instructions. .surfref variables may be passed as parameters.param .param.param { .texref.b32 y. etc. e. the kernel dimensions and properties are established and made available via special registers.param space memory and are listed within an optional parenthesized parameter list.PTX ISA Version 2.entry kernel-name kernel-body Defines a kernel entry point name. At kernel launch. ld. Semantics Specify the entry point for a kernel program.4 and later. Kernel and Function Directives: . and body for the kernel function.0 through 1.0 through 1. ld.samplerref.b32 %r2. store. 2010 . opaque .b32 %r1. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. . In addition to normal parameters. and . These parameters can only be referenced by name within texture and surface load.param instructions.b32 x. and query instructions and cannot be accessed via ld.entry filter ( .b32 %r3.

func (. parameters must be in the register state space.func (ret-param) fname (param-list) function-body Defines a function.reg .b32 N. implements an ABI with stack. including input and return parameters and optional function body. dbl. and supports recursion. if any.x code. . … use N. which may use a combination of registers and stack locations to pass parameters. Supported on all target architectures.param and st. there is no stack. … Description // return value in fooval January 24. PTX ISA 2.b32 localVar. Variadic functions are represented using ellipsis following the last fixed argument. . The parameter lists define locally-scoped variables in the function body. } … call (fooval).0 with target sm_20 allows parameters in the .Chapter 10. Directives Table 133. Parameters in register state space may be referenced directly within instructions in the function body. The implementation of parameter passing is left to the optimizing translator.result. other code.0 with target sm_20 supports at most one return value.func fname (param-list) function-body .2 for a description of variadic functions. val1).0.func Syntax Function definition.func .b32 rval.reg . mov. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.func fname function-body . foo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Release Notes For PTX ISA version 1.param instructions in the body.param state space. PTX 2. . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Parameters must be base types in either the register or parameter state space. and recursion is illegal.reg . ret.reg . Parameter passing is call-by-value.f64 dbl) { .func definition with no body provides a function prototype.param space are accessed using ld.b32 rval) foo (. A . 2010 161 . Parameters in . Variadic functions are currently unimplemented. Kernel and Function Directives: . (val0.

2010 . Note that .maxntid .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). which pass information to the backend optimizing compiler. A general . . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. at entry-scope. or as statements within a kernel or device function body. the . for example.minnctapersm . The . . Currently.maxnreg directive specifies the maximum number of registers to be allocated to a single thread.pragma directives may appear at module (file) scope. The directives take precedence over any module-level constraints passed to the optimizing backend.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.3.pragma directive is supported for passing information to the PTX backend. The interpretation of .pragma The . the .maxnctapersm (deprecated) .maxnreg . and the . 162 January 24.maxnreg.g.0 10.maxntid. to throttle the resource requirements (e. and . registers) to increase total thread count and provide a greater opportunity to hide memory latency. The directive passes a list of strings to the backend.minnctapersm directives may be applied per-entry and must appear between an .maxntid directive specifies the maximum number of threads in a thread block (CTA). Performance-Tuning Directives To provide a mechanism for low-level performance tuning.entry directive and its body.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.PTX ISA Version 2. PTX supports the following directives. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. These can be used.maxntid and . and the strings have no semantics within the PTX virtual machine model.

for example.maxntid nx.maxntid nx. Exceeding any of these limits results in a runtime error or kernel launch failure.maxnreg n Declare the maximum number of registers per thread in a CTA. 2010 163 .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid . Introduced in PTX ISA version 1. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Performance-Tuning Directives: . Supported on all target architectures.maxntid Syntax Maximum number of threads in thread block (CTA). ny .maxnreg . 2D. ny.entry bar .3. Introduced in PTX ISA version 1.entry foo . The maximum number of threads is the product of the maximum extent in each dimension.maxntid and .maxntid 16.maxctapersm.entry foo .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. .maxntid nx . Supported on all target architectures. . the backend may be able to compile to fewer registers. Performance-Tuning Directives: . The actual number of registers used may be less. Directives Table 134. or 3D CTA.16. nz Declare the maximum number of threads in the thread block (CTA). or the maximum number of registers may be further constrained by .3. .maxntid 256 . The compiler guarantees that this limit will not be exceeded. . This maximum is specified by giving the maximum extent of each dimention of the 1D.Chapter 10.

. Deprecated in PTX ISA version 2.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. .maxntid to be specified as well. Optimizations based on . Introduced in PTX ISA version 1.0.0.entry foo .maxntid 256 .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Performance-Tuning Directives: . However.minnctapersm generally need .0 Table 136. Supported on all target architectures. For this reason. if the number of registers used by the backend is sufficiently lower than this bound.PTX ISA Version 2. The optimizing backend compiler uses .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Performance-Tuning Directives: .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).0 as a replacement for .minnctapersm 4 { … } 164 January 24.3.maxntid and .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.entry foo .maxnctapersm generally need . . Introduced in PTX ISA version 2.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid to be specified as well.maxntid 256 . additional CTAs may be mapped to a single multiprocessor.minnctapersm in PTX ISA version 2.minnctapersm . 2010 . Supported on all target architectures.maxnctapersm has been renamed to .maxnctapersm (deprecated) . .maxnctapersm. Optimizations based on . .

The interpretation of . { … } January 24. The .0.pragma “nounroll”.pragma .Chapter 10. 2010 165 . .pragma directive strings is implementation-specific and has no impact on PTX semantics. at entry-scope. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . or statement-level directives to the PTX backend compiler.pragma Syntax Description Pass directives to PTX backend compiler. or at statementlevel. Pass module-scoped. Directives Table 138. Introduced in PTX ISA version 2. entry-scoped.pragma list-of-strings .pragma directive may occur at module-scope.entry foo . . Supported on all target architectures.pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas. Performance-Tuning Directives: .

0x00.4byte label . 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.0 and replaces the @@DWARF syntax. 0x02. @@DWARF dwarf-string dwarf-string may have one of the . The @@DWARF syntax is deprecated as of PTX version 2. 0x00.section .. 0x00000364.byte byte-list // comma-separated hexadecimal byte values . 0x61395a5f.4byte .0 10.232-1] . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .section directive is new in PTX ISA verison 2. “”.0 but is supported for legacy PTX version 1.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. Introduced in PTX ISA version 1.264-1] .x code. 0x736d6172 .loc The . 0x00 166 January 24.PTX ISA Version 2. replaced by . 2010 .section . 0x00.0. 0x00 .. 0x5f736f63 .2.4byte int32-list // comma-separated hexadecimal integers in range [0.section directive. 0x00.4. 0x63613031. Supported on all target architectures. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .quad int64-list // comma-separated hexadecimal integers in range [0. 0x00.debug_info .4byte 0x6e69616d. 0x6150736f. @progbits .byte 0x2b.byte 0x00.file .debug_pubnames. Deprecated as of PTX 2. Table 139.4byte 0x000006b5.

b32 0x000006b5.section Syntax PTX section definition.264-1] . Source file location. .b8 0x2b. Debugging Directives: .b32 label .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . Supported on all target architectures. Directives Table 140. 2010 167 . } 0x02..debug_pubnames { .0.section . 0x5f736f63 0x6150736f.file filename Table 142. 0x00.b8 0x00. Source file information.255] . . 0x00. Debugging Directives: .b32 int32-list // comma-separated list of integers in range [0.232-1] . . 0x00 0x61395a5f.file . 0x00000364. 0x00.section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x6e69616d.. Supported on all target architectures.debug_info . .. . 0x00.b64 int64-list // comma-separated list of integers in range [0.section . 0x00.b8 byte-list // comma-separated list of integers in range [0.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.loc line_number January 24. 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x736d6172 0x00 Table 141. Debugging Directives: . . Supported on all target architectures.b32 .Chapter 10.0.0. 0x63613031.loc . replaces @@DWARF syntax.

global .global . Introduced in PTX ISA version 1. Supported on all target architectures. Supported on all target architectures.PTX ISA Version 2. Linking Directives: .b32 foo. .0. Introduced in PTX ISA version 1. // foo is defined in another module Table 144.6.extern . .b32 foo.0 10.extern . Linking Directives: .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible identifier Declares identifier to be externally visible. .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.0.visible Table 143. .visible .extern identifier Declares identifier to be defined externally. Linking Directives .extern . 2010 .visible . // foo will be externally visible 168 January 24.

CUDA Release CUDA 1.3 driver r190 CUDA 3.3 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1.2 PTX ISA 1.0 CUDA 2.1 CUDA 2.0 PTX ISA 1. The release history is as follows. 2010 169 .4 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.1 PTX ISA 1.Chapter 11.0 January 24.1 CUDA 2.0. and the remaining sections provide a record of changes in previous releases.0 CUDA 1.5 PTX ISA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.2 CUDA 2.

f32. 2010 .ftz and . When code compiled for sm_1x is executed on sm_20 devices. Instructions testp and copysign have been added.1. fma.1. rcp. Changes in Version 2. mad.f32 requires sm_20.rp rounding modifiers for sm_20 targets. The fma.PTX ISA Version 2.sat modifiers. A single-precision fused multiply-add (fma) instruction has been added.rm and . The mad.f32 maps to fma. and mul now support . The changes from PTX ISA 1.f32 require a rounding modifier for sm_20 targets. Single-precision add.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Both fma. The .f32 instruction also supports .1. Floating-Point Extensions This section describes the floating-point changes in PTX 2.1. • • • • • 170 January 24. New Features 11.ftz modifier may be used to enforce backward compatibility with sm_1x.0 11.0 11.1. These are indicated by the use of a rounding modifier and require sm_20. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.1. while maximizing backward compatibility with legacy PTX 1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x code and sm_1x targets. The goal is to achieve IEEE 754 compliance wherever possible. The mad.0 for sm_20 targets.f32 and mad.f32 for sm_20 targets. sub.rn.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. and sqrt with IEEE 754 compliant rounding have been added. Single.and double-precision div.

11.red}. .maxnctapersm directive was deprecated and replaced with .red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Instruction cvta for converting global. clz.u32 and bar. Instructions prefetch and prefetchu have also been added. has been added. Surface instructions support additional . A “count leading zeros” instruction. has been added. Other new features Instructions ld.1. Cache operations have been added to instructions ld. The .le.popc. Instruction sust now supports formatted surface stores.g.lt.section.clamp and . suld. January 24. brev.clamp modifiers.b32. local. popc.sys. has been added. Instructions bar. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Instructions {atom. %lanemask_{eq. prefetch. A “population count” instruction. atom.or}. has been added. prefetchu.3. A new directive.1. 2010 171 . The bar instruction has been extended as follows: • • • A bar.pred have been added. A system-level membar instruction.red}. ldu. New special registers %nsmid. vote. membar.ballot. ldu. has been added.arrive instruction has been added.2. st. Video instructions (includes prmt) have been added. and shared addresses to generic address and vice-versa has been added. New instructions A “load uniform” instruction.shared have been extended to handle 64-bit data types for sm_20 targets. st.gt} have been added.minnctapersm to better match its behavior and usage. %clock64. e. isspacep.add.1. and red now support generic addressing. bfe and bfi. has been added. have been added.red.Chapter 11.f32 have been implemented.zero. . cvta. Instructions {atom. for prefetching to specified level of memory hierarchy.ge. Bit field extract and insert instructions. has been added. bfind. A “find leading non-sign bit” instruction.{and. A “bit reversal” instruction. bar now supports optional thread count and register operands. A “vote ballot” instruction. and sust.1. Release Notes 11.

u32. Semantic Changes and Clarifications The errata in cvt. Formatted surface store with .{u32.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.1.s32.0 11. 172 January 24. 11. . Support for variadic functions and alloca are unimplemented.PTX ISA Version 2. To maintain compatibility with legacy PTX code.4 or earlier.4 and earlier. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.version is 1.s32. has been fixed. stack-based ABI is unimplemented.p.5. 2010 . The underlying. See individual instruction descriptions for details.f32} atom.3.ftz for PTX ISA versions 1.{min. {atom. call suld.f32 type is unimplemented. where .ftz (and cvt for . In PTX version 1.red}.target sm_1x. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. the correct number is sixteen. Instruction bra.1.p sust. Formatted surface load is unimplemented.f32. cvt. if .max} are not implemented. or .2.5 and later. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.

pragma “nounroll”. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.0.pragma “nounroll”. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.func bar (…) { … L1_head: . { … } // do not unroll any loop in this function .pragma strings defined by ptxas. . Note that in order to have the desired effect at statement level.pragma “nounroll”. … @p bra L1_end. 2010 173 . entry-function. Descriptions of . . and statement levels.pragma. disables unrolling of0 the loop for which the current block is the loop header. L1_end: … } // do not unroll this loop January 24. disables unrolling for all loops in the entry function body.Appendix A. Ignored for sm_1x targets. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma Strings This section describes the . Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. L1_body: … L1_continue: bra L1_head. including loops preceding the . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. The “nounroll” pragma is allowed at module.entry foo (…) . Table 145. Supported only for sm_20 targets.

PTX ISA Version 2. 2010 .0 174 January 24.

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