NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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2......................................................................................................................................................................1........4............. 5... 37 Array Declarations .......... 2010 ..............8........................ 5............................1.............. Instruction Operands.................................... Texture...................1............................................. 5.............................. 29 Local State Space ......................2.................................. 49 7........................................1......................... 5................... 38 Initializers ...1.......... 27 5............................................................. 5.............. 6..........6.......... 41 Using Addresses..........................5......... 28 Constant State Space ........................... 39 Parameterized Variable Names ......................................... 5.................... 5............................4.................................................. 47 Chapter 7............... 25 Chapter 5............................................................................................4............................. 29 Global State Space ....PTX ISA Version 2................................... 6...................... and Variables ........2.............1...............1... 33 Restricted Use of Sub-Word Sizes ..........................4..............................................................................1..........................5..................................................7..................... 6............................. 5.......... 34 Variables ..............1................................................3.0 4....1.................. Arrays..................................4......... State Spaces..................1.......................... 5.............................. 5.....................1......... 39 5... and Surface Types .................................................4...... 43 Labels and Function Names as Operands . 37 Vectors ........................................................... 6.... 41 Source Operands.........2......................... Abstracting the ABI .1.............4... 33 5......5......................................................... 5................................................................................................2......... 42 Arrays as Operands ............ 43 6......... 5....3..................................................5............................. 46 6..............4.......3...........................................2........ 44 Rounding Modifiers ............................................... 5...................... 38 Alignment .......4.....................................................................4................................................ 49 ii January 24......................................4..... Chapter 6. 6................2............. State Spaces ................................ 5........... 5..................................6............................................................. 42 Addresses as Operands .... Operand Type Information ................ Operand Costs .................. Function declarations and definitions .......... 27 Register State Space ................................................ 43 Vectors as Operands .....................4..... Types ......................................................... 44 Scalar Conversions ................... 6.....................3........................... Types.................................... 32 Texture State Space (deprecated) .. 29 Parameter State Space ....................... Sampler...........1..........1.............. 37 Variable Declarations .................................1......................... 33 Fundamental Types ........................................2............................................................... 30 Shared State Space...............4...... 6.............................................. 32 5............................................... 41 Destination Operands ............. 5........................6...........6... 28 Special Register State Space .............................4............. Summary of Constant Expression Evaluation Rules ...........................................................................5....4............. 6.............................................3.. Type Conversion...... 6........... 41 6......................................................2...............................................................5........ and Vectors ...............

........... 8............7......... 172 Unimplemented Features Remaining ............... Directives ........ 10..............................................5........ 55 PTX Instructions ........................ 8...... 100 Logic and Shift Instructions .................. 8..................................1.................2...........................7........7........................ PTX Version and Target Directives ...................................... 10...... Release Notes .......... 8................... 10.......... Instructions ........3.......1..........2.................... 168 Chapter 11.......................... 108 Texture and Surface Instructions ...........................3.... 8.................................. 8................. 11.................................0 ............................ 160 Performance-Tuning Directives ............7............................................................... 8...........................................................................1.......... 2010 iii ........9..............6................. 157 10........................................................ 52 Variadic functions ........................................................................ 7.......................... 170 New Features ........ Type Information for Instructions and Operands ......................... Special Registers ...................................................... Format and Semantics of Instruction Descriptions .............1...................................................... 140 Miscellaneous Instructions.............................. 54 Chapter 8.............. 8...... 62 Semantics ................................................... 8.....8........................................ Changes in Version 2........ 11................................................................................................................ 104 Data Movement and Conversion Instructions .............. 8. 57 Manipulating Predicates ................................................. 11...................................10.. 166 Linking Directives .........................1......... 62 Machine-Specific Semantics of 16-bit Code ...........1.....................5..........................6.......7.............................................................. 8..................................................3..............6..................................1.. 60 8...........................7....................2............................................................. 170 Semantic Changes and Clarifications . 149 Chapter 10....................3.................. 147 8........4.... 62 8....4... 122 Control Flow Instructions ................................................... 7.............. 157 Specifying Kernel Entry Points and Functions ....1...2....... 8...............x ................7................4....................................3...............2.6....3......... 8.............. 55 8.................................................................. 81 Comparison and Selection Instructions ..7..........................2.......................................................... 56 Comparisons ....................... Changes from PTX 1.................. 63 Floating-Point Instructions ...........1.......................................................1... 59 Operand Size Exceeding Instruction-Type Size ...4.1..1................................................................................................... Divergence of Threads in Control Constructs ..................................................... 8............................................ 132 Video Instructions ................................. 8....... 53 Alloca ............... 8.......................................................................................3........................................................................................................... 63 Integer Arithmetic Instructions ...............................................7........................ 162 Debugging Directives ...................... 55 Predicated Execution ...................7.7.7..................... 129 Parallel Synchronization and Communication Instructions ..................................... 58 8...................................... 10..........................................................7....................................................... Instruction Set ............. 169 11............ Chapter 9........... 172 January 24....1...................

. 2010 ................0 Appendix A.........pragma Strings....... 173 iv January 24.............PTX ISA Version 2.......... Descriptions of ............

............................ 67 Integer Arithmetic Instructions: mad ................. Table 19................. 58 Type Checking Rules ........... Table 2...... and Bit-Size Types ................................................. 46 Integer Rounding Modifiers ........................... Table 15...........cc ... Table 14................................................. 64 Integer Arithmetic Instructions: sub ................................................................................................. Table 24........................ Table 5.......................... Table 11............................................................ Table 29.......... 46 Cost Estimates for Accessing State-Spaces ...... Table 30........ 2010 v ........................................................... 19 Predefined Identifiers ........................................................................... 57 Floating-Point Comparison Operators Accepting NaN ........................ Table 32..................................................... Table 18....................... Table 22.............................................. 28 Fundamental Type Specifiers ................................................................................................ Table 31.............. Table 6. 71 January 24.... Table 26..................... Table 8................................................ Table 10.............................................. Table 17...List of Tables Table 1................ 69 Integer Arithmetic Instructions: mad24 ........................ PTX Directives ................................................................................................................. 57 Floating-Point Comparison Operators ........ 27 Properties of State Spaces ....................................... Table 21................................... Table 12....................................... 70 Integer Arithmetic Instructions: sad ...................... Table 28....................... Table 16................................................. 47 Operators for Signed Integer................ Table 13.................................................................... 33 Opaque Type Fields in Unified Texture Mode ........... 25 State Spaces ................................................................ 18 Reserved Instruction Keywords ...................................... Table 4...... Table 9................ Table 27................ 59 Relaxed Type-checking Rules for Source Operands ....................................... Unsigned Integer...... 65 Integer Arithmetic Instructions: addc ................................................................................... 68 Integer Arithmetic Instructions: mul24 .. 66 Integer Arithmetic Instructions: mul ......................................................................................................... 65 Integer Arithmetic Instructions: sub. Table 3........... 35 Convert Instruction Precision and Format ................. Table 23.................. 60 Relaxed Type-checking Rules for Destination Operands................................ 35 Opaque Type Fields in Independent Texture Mode ............................................ 20 Operator Precedence .................. 45 Floating-Point Rounding Modifiers .......... Table 25............................................... 64 Integer Arithmetic Instructions: add.................................................................................................................................................... 58 Floating-Point Comparison Operators Testing for NaN ................................................ Table 7.......cc .......................... Table 20............................................. 66 Integer Arithmetic Instructions: subc .............................. 23 Constant Expression Evaluation Rules ........................ 61 Integer Arithmetic Instructions: add ....

..................... 101 Comparison and Selection Instructions: setp ................................... Table 53......................... Table 41.......... 98 Floating-Point Instructions: ex2 ............................ 92 Floating-Point Instructions: max ............................................. 85 Floating-Point Instructions: mul ................ 84 Floating-Point Instructions: sub ............. Table 40....... Table 69.......................................................... 72 Integer Arithmetic Instructions: neg ........... Table 66................. Table 52......................... Table 59.......................................... 103 Comparison and Selection Instructions: slct ....... 75 Integer Arithmetic Instructions: brev .................. 82 Floating-Point Instructions: testp .......................PTX ISA Version 2.............................. 73 Integer Arithmetic Instructions: max ................. Table 48.................. 94 Floating-Point Instructions: rsqrt ........................ 102 Comparison and Selection Instructions: selp .... Table 60............................ Table 65................................................................................. Table 62............................................ Table 47........... 72 Integer Arithmetic Instructions: min .... 77 Integer Arithmetic Instructions: bfi ............................................. 74 Integer Arithmetic Instructions: bfind ...... 95 Floating-Point Instructions: sin ................................... Table 56........................ 2010 ................................................................................ 73 Integer Arithmetic Instructions: popc ........ Table 50.........................................0 Table 33.................... Table 34......................................................................................................... Table 37..................................... Table 63....................... Table 36.......... 91 Floating-Point Instructions: min ................................................................................................ 79 Summary of Floating-Point Instructions ................ Table 67....................... Table 39..................................... Table 55............ Table 45....... 99 Comparison and Selection Instructions: set ...................................................................................... 86 Floating-Point Instructions: fma ..................................................... Table 68............. 97 Floating-Point Instructions: lg2 .... 71 Integer Arithmetic Instructions: rem ................. Table 38...... Table 35.......................... 83 Floating-Point Instructions: add ............... 87 Floating-Point Instructions: mad .............................................................................. 92 Floating-Point Instructions: rcp .......... 96 Floating-Point Instructions: cos ... Table 61.............................................................. 103 vi January 24................................................................................................................................................................................................................................................... Table 57....................................................... Table 51........................................... Integer Arithmetic Instructions: div ............ Table 54.. Table 44......... Table 49.......................... 76 Integer Arithmetic Instructions: bfe ........................................................................................ 74 Integer Arithmetic Instructions: clz ......................... Table 58................................................................................................. Table 43................................................................................................................................................................... Table 42.............. 83 Floating-Point Instructions: copysign ................................................................................ 93 Floating-Point Instructions: sqrt ................................................................. 90 Floating-Point Instructions: abs ................. 71 Integer Arithmetic Instructions: abs .. 78 Integer Arithmetic Instructions: prmt ............................. 88 Floating-Point Instructions: div ....................................................................... Table 64................... Table 46........................................ 91 Floating-Point Instructions: neg ....................................................

.......... 106 Logic and Shift Instructions: not ......... vshr ... 2010 vii .... 129 Control Flow Instructions: @ ............................................................................................................. vmin.............................. Table 94............................................ 139 Video Instructions: vadd.................................................................................................... Table 72.. Table 88.............. 124 Texture and Surface Instructions: suld ................................. Table 76..... Table 99........................ Table 101.......................... Table 81......................... Table 98............................................................. 106 Logic and Shift Instructions: shl ..............................................................................Table 70........................... 118 Data Movement and Conversion Instructions: isspacep ................................. 116 Data Movement and Conversion Instructions: prefetch...... Table 102...... Table 79......................... 120 Texture and Surface Instructions: tex .......... 105 Logic and Shift Instructions: xor ......... Table 82........... Logic and Shift Instructions: and .......................................................... 130 Control Flow Instructions: call ........ 135 Parallel Synchronization and Communication Instructions: red ...................... Table 103................. 127 Texture and Surface Instructions: suq ............ 123 Texture and Surface Instructions: txq .............................. 130 Control Flow Instructions: ret ......... 137 Parallel Synchronization and Communication Instructions: vote ............ Table 106...... 119 Data Movement and Conversion Instructions: cvta ................................................... Table 92.... vsub...................................... 133 Parallel Synchronization and Communication Instructions: membar ............................................ 119 Data Movement and Conversion Instructions: cvt ........................... prefetchu ..................... Table 74................................ 142 Video Instructions: vshl............................................... 112 Data Movement and Conversion Instructions: ld ...................................... Table 95....................... 111 Data Movement and Conversion Instructions: mov ................................................. 126 Texture and Surface Instructions: sured.................... Table 97.................... vmax ........ 131 Control Flow Instructions: exit ............................................................ Table 75.............................. Table 96................................................... 113 Data Movement and Conversion Instructions: ldu ..................................................... 107 Logic and Shift Instructions: shr .......... Table 86............................................................... 128 Control Flow Instructions: { } ................... 131 Parallel Synchronization and Communication Instructions: bar .................................... Table 73.. Table 104................. 129 Control Flow Instructions: bra ....................................................... 115 Data Movement and Conversion Instructions: st ............. Table 93........ Table 105..... Table 80............... Table 77........... 106 Logic and Shift Instructions: cnot ............................................................................... 107 Cache Operators for Memory Load Instructions .......... 134 Parallel Synchronization and Communication Instructions: atom ... 105 Logic and Shift Instructions: or ..................... Table 78............................................. 143 January 24......... Table 100........ 125 Texture and Surface Instructions: sust ........... 110 Data Movement and Conversion Instructions: mov ..... Table 89........................................................................ Table 90................................................................................................................ 109 Cache Operators for Memory Store Instructions ................ Table 85.......... Table 84.................... Table 87.......................... Table 71.................... vabsdiff. Table 91.... Table 83.........

...................................................................................................................target ....... Table 122........................... Table 120....... 153 Special Registers: %gridid ........................... 150 Special Registers: %ntid ........ Table 132...............................................................file ..................... Table 116... Table 137............... 151 Special Registers: %warpid ............. Table 136. %pm1.................... 147 Miscellaneous Instructions: pmevent........ 150 Special Registers: %laneid ..... Table 143........................... 155 Special Registers: %lanemask_gt ............. Table 123...................................................func ......... 154 Special Registers: %lanemask_ge .... Table 125..................................................................section ........... 147 Special Registers: %tid ....... Table 109.............. 163 Performance-Tuning Directives: ......................................................................................................... Table 113........................................................ Table 117........................... 144 Video Instructions: vset........................ Table 121................. 152 Special Registers: %nctaid ............................ Video Instructions: vmad .minnctapersm ............... 2010 ........... %pm3 ........................extern....................pragma .................... Table 118............................ Table 140............... Table 128....... 167 Debugging Directives: ........................................................................... 153 Special Registers: %lanemask_eq ................. Table 127................... 155 Special Registers: %clock ......entry................ 152 Special Registers: %smid ......maxnreg ............... 154 Special Registers: %lanemask_le ....................... 164 Performance-Tuning Directives: .PTX ISA Version 2......... 151 Special Registers: %nwarpid ............................ 167 Debugging Directives: ............................... Table 115.......................version..loc ...................................... Table 112.. Table 133................. Table 114...................maxntid ... 168 viii January 24.......................................................... 167 Linking Directives: .......................... Table 141.......................................... 153 Special Registers: %nsmid ........ %pm2................................................................................................................................ Table 129............................ 151 Special Registers: %ctaid ............ 146 Miscellaneous Instructions: trap .......... Table 138........................0 Table 107........................... 154 Special Registers: %lanemask_lt ................................. Table 110..................................................................... Table 126................................................................................................ 165 Debugging Directives: @@DWARF ............................................ 160 Kernel and Function Directives: .......................... Table 119......................... Table 135.......................... 166 Debugging Directives: ..................... Table 134........................................................................................................................................maxnctapersm (deprecated) ................................... Table 111.............. Table 139.......................... 158 Kernel and Function Directives: ..................................................................... 157 PTX File Directives: ............................. Table 124..................... 163 Performance-Tuning Directives: .................. Table 130............................................................................................ 161 Performance-Tuning Directives: ............................................................... 147 Miscellaneous Instructions: brkpt .......... 164 Performance-Tuning Directives: ..................................................................................................................................... Table 108....... 156 Special Registers: %clock64 . 156 Special Registers: %pm0................ 156 PTX File Directives: ....................................................... Table 142..... Table 131.................

Linking Directives: .... 173 January 24...................................................... 2010 ix .............Table 144............................visible........................ 168 Pragma Strings: “nounroll” .............................................. Table 145..

0 x January 24.PTX ISA Version 2. 2010 .

High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. PTX exposes the GPU as a data-parallel computing device. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. PTX defines a virtual machine and ISA for general purpose parallel thread execution. Similarly. image scaling. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations.2. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). and pattern recognition can map image blocks and pixels to parallel processing threads. In fact. and because it is executed on many data elements and has high arithmetic intensity. Data-parallel processing maps data elements to parallel processing threads. high-definition 3D graphics. video encoding and decoding. from general signal processing or physics simulation to computational finance or computational biology. Because the same program is executed for each data element. 1.Chapter 1. the programmable GPU has evolved into a highly parallel. which are optimized for and translated to native target-architecture instructions. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. there is a lower requirement for sophisticated flow control. 1. stereo vision. image and media processing applications such as post-processing of rendered images. Introduction This document describes PTX. 2010 1 . many-core processor with tremendous computational horsepower and very high memory bandwidth. January 24. the memory access latency can be hidden with calculations instead of big data caches. PTX programs are translated at install time to the target hardware instruction set. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. multithreaded.

including integer.PTX ISA Version 2.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.3.x code will continue to run on sm_1x targets as well.f32 maps to fma. reduction. Provide a code distribution ISA for application and middleware developers. Legacy PTX 1. mad.f32 for sm_20 targets. PTX ISA Version 2. • • • 2 January 24. Improved Floating-Point Support A main area of change in PTX 2. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Most of the new features require a sm_20 target.f32 instruction also supports .f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. 1.ftz) modifier may be used to enforce backward compatibility with sm_1x. and video instructions.rm and .0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. When code compiled for sm_1x is executed on sm_20 devices. 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. PTX 2.f32 require a rounding modifier for sm_20 targets. A “flush-to-zero” (. atomic. Single-precision add. Provide a machine-independent ISA for C/C++ and other compilers to target.0 PTX ISA Version 2. and the introduction of many new instructions. Instructions marked with .0 is in improved support for the IEEE 754 floating-point standard. addition of generic addressing to facilitate the use of general-purpose pointers. 2010 . Both fma. barrier. Provide a common source-level ISA for optimizing code generators and translators.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.sat modifiers. sub. The mad. The changes from PTX ISA 1. The fma. and mul now support . and all PTX 1.f32 requires sm_20. and architecture tests. Facilitate hand-coding of libraries.f32 and mad.rn. The mad.3. surface.rp rounding modifiers for sm_20 targets. The main areas of change in PTX 2.f32.1.0 is a superset of PTX 1. performance kernels.x. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. Achieve performance in compiled applications comparable to native GPU performance.0 are improved support for IEEE 754 floating-point operations.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. fma.x features are supported on the new sm_20 target.ftz and . which map PTX to specific target machines. A single-precision fused multiply-add (fma) instruction has been added. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. memory.

0 closer to full compliance with the IEEE 754 standard. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Instruction cvta for converting global. these changes bring PTX 2.3. New Instructions The following new instructions.zero. prefetch.e. • Taken as a whole. Instructions prefetch and prefetchu have been added. stack layout. st.g. 1.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. Generic Addressing Another major change is the addition of generic addressing. special registers. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. an address that is the same across all threads in a warp. local. cvta.3. . Surface instructions support additional clamp modifiers. and sqrt with IEEE 754 compliant rounding have been added. e.clamp and . and shared state spaces.0. Instructions testp and copysign have been added. i. January 24. A new cvta instruction has been added to convert global. Support for an Application Binary Interface Rather than expose details of a particular calling convention. In PTX 2. atom. and shared addresses to generic address and vice-versa has been added. Cache operations have been added to instructions ld. so recursion is not yet supported. allowing memory instructions to access these spaces without needing to specify the state space. 1.and double-precision div. PTX 2. and sust.2. Generic addressing unifies the global. Surface Instructions • • Instruction sust now supports formatted surface stores. suld. for prefetching to specified level of memory hierarchy. 2010 3 . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.0. ldu. and Application Binary Interface (ABI). local. Introduction • Single. stack-based ABI.4. isspacep.Chapter 1.. and directives are introduced in PTX 2.3.3. These are indicated by the use of a rounding modifier and require sm_20. NOTE: The current version of PTX does not implement the underlying. and red now support generic addressing. 1. and shared addresses to generic addresses. prefetchu. local. rcp. st. and vice versa. instructions ld.

and Vote Instructions • • • New atomic and reduction instructions {atom. has been added. Reduction. Other Extensions • • • Video instructions (includes prmt) have been added.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. bfi bit field extract and insert popc clz Atomic. New special registers %nsmid. %lanemask_{eq.ballot. .u32 and bar.shared have been extended to handle 64-bit data types for sm_20 targets.lt.sys.PTX ISA Version 2.le. %clock64. 2010 . Instructions bar. Barrier Instructions • • A system-level membar instruction.red}.b32. membar.arrive instruction has been added.{and.red.red}.or}.gt} have been added. Instructions {atom.ge. A “vote ballot” instruction.pred have been added. vote. has been added.section.red.f32 have been added. bar now supports an optional thread count and register operands.popc. 4 January 24. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A new directive.add. A bar.

Chapter 1. January 24. Chapter 11 provides release notes for PTX Version 2. Chapter 5 describes state spaces.0. types. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 3 gives an overview of the PTX virtual machine model. Introduction 1. calling convention. Chapter 7 describes the function and call syntax. and variable declarations. 2010 5 . Chapter 6 describes instruction operands. Chapter 8 describes the instruction set. Chapter 10 lists the assembly directives supported in PTX.4. Chapter 4 describes the basic syntax of the PTX language. Chapter 9 lists special registers. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.

0 6 January 24.PTX ISA Version 2. 2010 .

2D.z). and results across the threads of the CTA.x. The thread identifier is a three-element vector tid. The vector ntid specifies the number of threads in each CTA dimension.y. To that effect. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2. or host: In other words. tid. Threads within a CTA can communicate with each other. a portion of an application that is executed many times. assign specific input and output positions. work. Each CTA thread uses its thread identifier to determine its assigned role. compute addresses. one can specify synchronization points where threads wait until all threads in the CTA have arrived. Each CTA has a 1D.2. and ntid.1. is an array of threads that execute a kernel concurrently or in parallel. (with elements tid. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. Each thread has a unique thread identifier within the CTA. or 3D shape specified by a three-element vector ntid (with elements ntid. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.z) that specifies the thread’s position within a 1D. 2D. but independently on different data. Programming Model 2.Chapter 2.2. and tid. Programs use a data parallel decomposition to partition inputs. A cooperative thread array. data-parallel. More precisely.y.1. can be isolated into a kernel function that is executed on the GPU as many different threads. 2. It operates as a coprocessor to the main CPU. ntid. or 3D CTA. To coordinate the communication of the threads within the CTA. January 24. or CTA. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. compute-intensive portions of applications running on the host are off-loaded onto the device. 2010 7 .x. and select work to perform. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.

Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). %nctaid. %ntid. because threads in different CTAs cannot communicate and synchronize with each other. Each grid also has a unique temporal grid identifier (gridid). The host issues a succession of kernel invocations to the device. The warp size is a machine-dependent constant. Threads within a warp are sequentially numbered.2. 2. 2D . which may be used in any instruction where an immediate operand is allowed. and %gridid.0 Threads within a CTA execute in SIMT (single-instruction. Each grid of CTAs has a 1D. Typically. or sequentially.2. so that the total number of threads that can be launched in a single kernel invocation is very large. multiple-thread) fashion in groups called warps. A warp is a maximal subset of threads from a single CTA. a warp has 32 threads. read-only special registers %tid. so PTX includes a run-time immediate constant. depending on the platform. This comes at the expense of reduced thread communication and synchronization. such that the threads execute the same instructions at the same time. However. Multiple CTAs may execute concurrently and in parallel. CTAs that execute the same kernel can be batched together into a grid of CTAs. Some applications may be able to maximize performance with knowledge of the warp size. %ctaid. WARP_SZ. Threads may read and use these values through predefined. or 3D shape specified by the parameter nctaid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 8 January 24.PTX ISA Version 2. 2010 . Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs.

0) CTA (2. 2) Thread (4. 0) Thread (1. 1) Thread (4. A grid is a set of CTAs that execute independently. 1) Thread (3. 1) Thread (1. 0) Thread (2. 1) Thread (2. 1) Thread (0. Figure 1. 2) Thread (2. 0) Thread (3. 0) Thread (0. 2) Thread (3.Chapter 2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2) Thread (1. 1) CTA (1. 2010 9 . Thread Batching January 24. 1) CTA (2. 0) CTA (1. 1) Grid 2 Kernel 2 CTA (1. 1) Thread (0. 0) CTA (0. 0) Thread (4.

Finally. The global. 10 January 24. Each thread has a private local memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Both the host and the device maintain their own local memory. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. respectively. constant. Texture memory also offers different addressing modes. constant.PTX ISA Version 2.0 2. for some specific data formats. for more efficient transfer. all threads have access to the same global memory. and texture memory spaces are persistent across kernel launches by the same application. and texture memory spaces are optimized for different memory usages. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. The device memory may be mapped and read or written by the host. 2010 . as well as data filtering. or. The global. referred to as host memory and device memory. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine.3.

0) Block (2. 2010 11 . 1) Block (2. Memory Hierarchy January 24. 0) Block (1. 1) Block (1.Chapter 2. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (1. 0) Block (0. 1) Block (1. 0) Block (0. 2) Block (1. 2) Figure 2. 1) Grid 1 Global memory Block (0. 1) Block (0.

2010 .0 12 January 24.PTX ISA Version 2.

a cell in a grid-based computation). The multiprocessor creates. manages. The multiprocessor maps each thread to one scalar processor core. The threads of a thread block execute concurrently on one multiprocessor. To manage hundreds of threads running several different programs. multiple-thread). each warp contains threads of consecutive. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and on-chip shared memory. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity.1. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. the threads converge back to the same execution path. The multiprocessor SIMT unit creates. allowing. the warp serially executes each branch path taken. and when all paths complete. the first parallel thread technology. different warps execute independently regardless of whether they are executing common or disjointed code paths. When a host program invokes a kernel grid. the multiprocessor employs a new architecture we call SIMT (single-instruction. and executes threads in groups of parallel threads called warps. and executes concurrent threads in hardware with zero scheduling overhead. manages. disabling threads that are not on that path. for example. schedules. If threads of a warp diverge via a data-dependent conditional branch. increasing thread IDs with the first warp containing thread 0. A multiprocessor consists of multiple Scalar Processor (SP) cores. As thread blocks terminate.Chapter 3.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. The way a block is split into warps is always the same. Parallel Thread Execution Machine Model 3. new blocks are launched on the vacated multiprocessors. January 24. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). a multithreaded instruction unit. 2010 13 . a voxel in a volume. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. (This term originates from weaving. It implements a single-instruction barrier synchronization. Branch divergence occurs only within a warp. At every instruction issue time. so full efficiency is realized when all threads of a warp agree on their execution path. it splits them into warps that get scheduled by the SIMT unit. When a multiprocessor is given one or more thread blocks to execute. and each scalar thread executes independently with its own instruction address and register state. A warp executes one common instruction at a time.

A key difference is that SIMD vector organizations expose the SIMD width to the software. on the other hand. require the software to coalesce loads into vectors and manage divergence manually. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. As illustrated by Figure 3. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge.0 SIMT architecture is akin to SIMD (Single Instruction. 14 January 24. however. and writes to the same location in global memory for more than one of the threads of the warp. modify. modifies. but one of the writes is guaranteed to succeed. the kernel will fail to launch. scalar threads. SIMT enables programmers to write thread-level parallel code for independent. as well as data-parallel code for coordinated threads. write to that location occurs and they are all serialized. If an atomic instruction executed by a warp reads. In practice. • The local and global memory spaces are read-write regions of device memory and are not cached. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. A multiprocessor can execute as many as eight thread blocks concurrently. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. Vector architectures.PTX ISA Version 2. which is a read-only region of device memory. 2010 . If there are not enough registers or shared memory available per multiprocessor to process at least one block. whereas SIMT instructions specify the execution and branching behavior of a single thread. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. the programmer can essentially ignore the SIMT behavior. the number of serialized writes that occur to that location and the order in which they occur is undefined. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. In contrast with SIMD vector machines. For the purposes of correctness. but the order in which they occur is undefined. each read. which is a read-only region of device memory. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks.

Chapter 3. Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. 2010 15 . Figure 3.

PTX ISA Version 2. 2010 .0 16 January 24.

2010 17 . followed by a . The C preprocessor cpp may be used to process PTX source files. #define. #endif. January 24. Pseudo-operations specify symbol and addressing management. #ifdef. All whitespace characters are equivalent. using non-nested /* and */ for comments that may span multiple lines. Each PTX file must begin with a . The following are common preprocessor directives: #include. Source Format Source files are ASCII text. PTX is case sensitive and uses lowercase for keywords. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor.1. #else. and using // to begin a comment that extends to the end of the current line.target directive specifying the target architecture assumed. 4.version directive specifying the PTX language version. whitespace is ignored except for its use in separating tokens in the language. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. #line. 4.2. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. Syntax PTX programs are a collection of text source files. Comments Comments in PTX follow C/C++ syntax. See Section 9 for a more information on these directives.Chapter 4. Comments in PTX are treated as whitespace. Lines are separated by the newline character (‘\n’). Lines beginning with # are preprocessor directives. #if.

r2.maxntid .reg . Instructions have an optional guard predicate which controls conditional execution.file PTX Directives . or label names. Statements A PTX statement is either a directive or an instruction.b32 add. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.local . shl.shared . array[r1].param .1. followed by source operands. 2.minnctapersm .b32 r1.tex .b32 r1. r2.sreg .global .target . mov. written as @!p.func . Examples: . Directive Statements Directive keywords begin with a dot.pragma .3. Statements begin with an optional label and end with a semicolon.2.f32 array[N]. and terminated with a semicolon. constant expressions.section . r2. Instruction keywords are listed in Table 2.maxnreg . 0. . The destination operand is first. Table 1.b32 r1. where p is a predicate register.global. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.3. so no conflict is possible with user-defined identifiers.const .reg . 2010 .version .f32 r2. 18 January 24.align .maxnctapersm . address expressions. ld.global start: .x. The guard predicate follows the optional label and precedes the opcode. Operands may be register variables.entry .PTX ISA Version 2.extern . The guard predicate may be optionally negated.5. r1.3.loc .visible 4. %tid.0 4. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. All instruction keywords are reserved tokens in PTX. and is written as @p. .

2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.

The percentage sign can be used to avoid name conflicts. %pm3 WARP_SZ 20 January 24. …. Table 3. except that the percentage sign is not allowed. e. underscore. or they start with an underscore. or percentage character followed by one or more letters. or dollar characters. Many high-level languages such as C and C++ follow similar rules for identifier names. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. PTX allows the percentage sign as the first character of an identifier. PTX predefines one constant and a small number of special registers that begin with the percentage sign.0 4. between user-defined variable names and compiler-generated names. 2010 . digits.g. listed in Table 3.4. dollar.PTX ISA Version 2. underscore. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. digits.

Chapter 4. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. Type checking rules remain the same for integer. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.s64) unless the value cannot be fully represented in . zero values are FALSE and non-zero values are TRUE. hexadecimal. Integer literals may be written in decimal. Constants PTX supports integer and floating-point constants and constant expressions. octal. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Floating-point literals may be written with an optional decimal point and an optional signed exponent.. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. When used in an instruction or data initialization.s64 or the unsigned suffix is specified. The syntax follows that of C. literals are always represented in 64-bit double-precision format. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.u64). floating-point. in which case the literal is unsigned (. integer constants are allowed and are interpreted as in C. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.u64. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.s64 or . To specify IEEE 754 single-precision floating point values.e. i. 4. For predicate-type data and instructions. the sm_1x and sm_20 targets have a WARP_SZ value of 32. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use..1. or binary notation. there is no suffix letter to specify size.e. Syntax 4. the constant begins with 0f or 0F followed by 8 hex digits. Unlike C and C++. i. where the behavior of the operation depends on the operand types.2.5. 2010 21 . every integer constant has type . the constant begins with 0d or 0D followed by 16 hex digits. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. These constants may be used in data initialization and as operands to instructions.5. To specify IEEE 754 doubleprecision floating point values.5. and bit-size types. 4. each integer constant is converted to the appropriate size based on the data or instruction type at its use.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64 .s64 .s64 .u64 . 2nd is . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.s64 .f64 integer .u64 same as 1st operand . .u64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 .f64 integer integer integer integer integer int ?. or .u64 .u64) (.f64 converted type .u64.s64) + .u64 .s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .u64 zero or non-zero same as sources use usual conversions Result Type same as source .5.f64 converted type constant literal + ! ~ Cast Binary (. 2010 25 .s64 .6.f64 use usual conversions .f64 use usual conversions .s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 use usual conversions .f64 : .s64 .u64 1st unchanged. Syntax 4.Chapter 4.f64 integer .u64 . Table 5.f64 same as source .s64.

PTX ISA Version 2.0 26 January 24. 2010 .

Special registers. Local memory. and Variables While the specific resources available in a given target GPU will vary. the kinds of resources will be common across platforms. Kernel parameters. State Spaces A state space is a storage area with particular characteristics.param . Addressable memory shared between threads in 1 CTA. private to each thread. read-only memory. The list of state spaces is shown in Table 4. 2010 27 . or Function or local parameters.local . defined per-thread. access rights. Types. Table 6. Name State Spaces Description Registers. Global memory. 5. shared by all threads. addressability. and these resources are abstracted in PTX through state spaces and data types. and level of sharing between threads. fast. All variables reside in some state space.reg .const .sreg . Shared. .shared .1. and properties of state spaces are shown in Table 5. Global texture memory (deprecated). platform-specific.tex January 24.Chapter 5. pre-defined. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.global . The characteristics of a state space include its size. State Spaces. access speed. defined per-grid. Read-only.

global . 32-. floating point. Registers may have alignment boundaries required by multi-word loads and stores. aside from predicate registers which are 1-bit. predicate) or untyped. and thread parameters.1. clock counters. All special registers are predefined.const . the parameter is then located on the stack frame and its address is in the . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). and vector registers have a width of 16-.0 Table 7. Address may be taken via mov instruction.1.e. or 128-bits.param instructions. it is not possible to refer to the address of a register.PTX ISA Version 2. unsigned integer. and performance monitoring registers. or 64-bits. 28 January 24. Registers may be typed (signed integer. Device function input parameters may have their address taken via mov. 5..param instruction.1. Special Register State Space The special register (. or as elements of vector tuples. Registers differ from the other state spaces in that they are not fully addressable. scalar registers have a width of 8-.shared . The most common use of 8-bit registers is with ld. 1 Accessible only via the ld. 32-. and will vary from platform to platform.2. i.sreg . causing changes in performance. Register State Space Registers (. 16-.reg state space) are fast storage locations.reg .tex Restricted Yes No3 5.local state space.local . For each architecture.sreg) state space holds predefined. 64-. The number of registers is limited. CTA. 2010 . register variables will be spilled to memory. st. platform-specific registers. such as grid.param (as input to kernel) . and cvt instructions. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.param and st. 3 Accessible only via the tex instruction.param (used in functions) . 2 Accessible via ld. When the limit is exceeded. Register size is restricted.

for example). Sequential consistency is provided by the bar.sync instruction.extern .b32 %r1. an incomplete array in bank 2 is accessed as follows: .extern . Local State Space The local state space (. The constant memory is organized into fixed size banks.const) state space is a read-only memory. and atom. Module-scoped local memory variables are stored at fixed addresses. It is the mechanism by which different CTAs and different grids can communicate.global) state space is memory that is accessible by all threads in a context. the bank number must be provided in the state space of the load instruction. To access data in contant banks 1 through 10. 2010 29 .5. and Variables 5.b32 const_buffer[].global to access global variables.4. // load second word 5. ld. The remaining banks may be used to implement “incomplete” constant arrays (in C.global. This reiterates the kind of parallelism available in machines that run PTX. whereas local memory variables declared January 24. For any thread in a context. Consider the case where one thread executes the following two assignments: a = a + 1.3.local to access local variables. Multiple incomplete array variables declared in the same bank become aliases. b = b – 1. the declaration . initialized by the host. all addresses are in global memory are shared. results in const_buffer pointing to the start of constant bank two. The size is limited.const[bank] modifier. If no bank number is given. Banks are specified using the . Threads must be able to do their work without waiting for other threads to do theirs. It is typically standard memory with cache. For the current devices.const[2] . [const_buffer+4].global. where the size is not known at compile time. Use ld. each pointing to the start address of the specified constant bank. where bank ranges from 0 to 10. Global State Space The global (.1.const[2] .local) is private memory for each thread to keep its own data.Chapter 5. Types.1. the stack is in local memory.sync instruction are guaranteed to be visible to any reads after the barrier instruction. This pointer can then be used to access the entire 64KB constant bank. as in lock-free and wait-free style programming. st. as it must be allocated on a perthread basis. For example. Constant State Space The constant (.local and st.b32 const_buffer[]. 5. bank zero is used. there are eleven 64KB banks.const[2]. If another thread sees the variable b change. For example. State Spaces. Global memory is not sequentially consistent. All memory writes prior to the bar. In implementations that support a stack. the store operation updating a may still be in flight. Threads wait at the barrier until all threads in the CTA have arrived. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. bank zero is used for all statically-sized constant variables. Use ld.1. By convention.

b32 N.entry bar ( .param.u32 %ptr. These parameters are addressable.param instructions. … Example: . No access protection is provided between parameter and global space in this case. typically for passing large structures by value to a function. Example: .6. In implementations that do not support a stack. [%ptr]. %n.0 within a function or kernel body are allocated on the stack.f64 %d. . [N]. read-only variables declared in the . ld.1. For example. 5.1. Similarly.param space variables.param) state space is used (1) to pass input arguments from the host to the kernel. [buffer]. device function parameters were previously restricted to the register state space. Therefore. len. Note that PTX ISA versions 1. ld. Note: The location of parameter space is implementation specific.u32 %ptr. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.entry foo ( .param .6. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). ld.param .PTX ISA Version 2.reg .b8 buffer[64] ) { .b32 len ) { . 5. The use of parameter state space for device function parameters is new to PTX ISA version 2.reg .param.u32 %n. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.reg . PTX code should make no assumptions about the relative locations or ordering of . Parameter State Space The parameter (. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.u32 %n. (2a) to declare formal input and return parameters for device functions called from within kernel execution.1.param.param instructions. Values passed from the host to the kernel are accessed through these parameter variables using ld. The address of a kernel parameter may be moved into a register using the mov instruction. 2010 . … 30 January 24.param state space and is accessed using ld. The resulting address is in the .f64 %d.align 8 .param space.u32 %n. mov.param .x supports only kernel function parameters in . per-kernel versus per-thread). The kernel parameter variables are shared across all CTAs within a grid.param state space.0 and requires target architecture sm_20. . in some implementations kernel parameters reside in global memory. all local memory variables are stored at fixed addresses and recursive function calls are not supported.

(4.param. Note that the parameter will be copied to the stack if necessary.param formal parameter having the same size and alignment as the passed argument.f64 [mystruct+0]. 2010 31 .func foo ( . and so the address will be in the . . } mystruct.f64 %d. dbl.param. passed to foo … . … } // code snippet from the caller // struct { double d.align 8 . [buffer]. the caller will declare a locally-scoped . Example: // pass object of type struct { double d. . }.param space variable.Chapter 5.param byte array variable that represents a flattened C structure or union. the address of a function input parameter may be moved into a register using the mov instruction.param .param and function return parameters may be written using st. Typically. Aside from passing structures by value. State Spaces. and Variables 5.b8 buffer[12] ) { . int y. a byte array in parameter space is used.local state space and is accessed via ld.param.f64 %d. ld.reg .param space is also required whenever a formal parameter has its address taken within the called function.align 8 .s32 %y.b32 N. which declares a . call foo. .reg . st. … st.6. ld.b8 mystruct. January 24. … See the section on function call syntax for more details. .s32 x.f64 dbl.reg . Device Function Parameters PTX ISA version 2.s32 %y.param . In PTX.local and st.s32 [mystruct+8]. int y. . It is not possible to use mov to get the address of a return parameter or a locally-scoped . Types.local instructions. is flattened.1.0 extends the use of parameter space to device function parameters. .param. In this case.reg . it is illegal to write to an input parameter or read from a return parameter.2. such as C structures larger than 8 bytes.reg . This will be passed by value to a callee. mystruct). x. Function input parameters may be read via ld.param. The most common use is for passing objects by value that do not fit within a PTX register. [buffer+8].

3 for the description of the . where all threads read from the same address.texref tex_a. One example is broadcast. 32 January 24.shared) state space is a per-CTA region of memory for threads in a CTA to share data. A texture’s base address is assumed to be aligned to a 16-byte boundary. tex_f. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 . Texture memory is read-only. Shared memory typically has some optimizations to support the sharing. and .tex) state space is global memory accessed via the texture instruction. The . An error is generated if the maximum number of physical resources is exceeded.texref type and Section 8.1.tex . 2010 .7. See Section 5. The . It is shared by all threads in a context.tex directive will bind the named texture memory variable to a hardware texture identifier.shared to access shared variables. and variables declared in the . Physical texture resources are allocated on a per-module granularity.tex .tex variables are required to be defined in the global scope.global . a legacy PTX definitions such as . Example: .texref.6 for its use in texture instructions. is equivalent to .8. 5.7. Multiple names may be bound to the same physical texture identifier.0 5.tex directive is retained for backward compatibility.global state space.1.tex state space are equivalent to module-scoped . An address in shared memory can be read and written by any thread in a CTA.u32 . Shared State Space The shared (.texref variables in the .u32 tex_a. tex_d.PTX ISA Version 2. The texture name must be of type .u64. and programs should instead reference texture memory through variables of type . Use ld.tex .shared and st.u32 .tex . tex_c. Texture State Space (deprecated) The texture (.u32 tex_a. tex_d.tex . For example. where texture identifiers are allocated sequentially beginning with zero. Another is sequential access from sequential threads.u32 or .

u64 . and instructions operate on these types.2.2.b16.f32 and . . Two fundamental types are compatible if they have the same basic type and are the same size. 5.u8.b8 instruction types are restricted to ld. . so that narrow values may be loaded.Chapter 5. . Restricted Use of Sub-Word Sizes The .u32.s8.f64 . .b8. and Variables 5.u8. .f32 and . Register variables are always of a fundamental type.u16. The following table lists the fundamental type specifiers for each basic type: Table 8. Signed and unsigned integer types are compatible if they have the same size. In principle. The . Types 5.2.f16 floating-point type is allowed only in conversions to and from . and .f64 types. . .f64 types. A fundamental type specifies both a basic type and a size. and converted using regular-width registers. all variables (aside from predicates) could be declared using only bit-size types. stored. January 24.2. or converted to other types and sizes. . The same typesize specifiers are used for both variable definitions and for typing instructions. Fundamental Types In PTX. the fundamental types reflect the native data types supported by the target architectures. so their names are intentionally short. 2010 33 . For convenience. .1. stored.s64 . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . Operand types and sizes are checked against instruction types for compatibility. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.s8. and cvt instructions.b64 .f32. but typed variables enhance program readability and allow for better operand type checking. ld. .b32. Types.f16.pred Most instructions have one or more type specifiers. All floating-point instructions operate only on . st. .s16. needed to fully specify instruction behavior.s32. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. For example. . The bitsize type is compatible with any fundamental type having the same size. State Spaces. st.

texref. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. Retrieving the value of a named member via query instructions (txq.samplerref variables. hence the term “opaque”. suld. i. Sampler.3. The three built-in types are . or surfaces via texture and surface load/store instructions (tex.e. In the unified mode. suq). These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.samplerref. the resulting pointer may be stored to and loaded from memory. sust. samplers. sured). store.{u32. In the independent mode. opaque_var. and . and Surface Types PTX includes built-in “opaque” types for defining texture. but all information about layout. and query instructions. texture and sampler information each have their own handle. passed as a parameter to functions. PTX has two modes of operation. These types have named fields similar to structures. and overall size is hidden to a PTX program. allowing them to be defined separately and combined at the site of usage in the program. sampler. and de-referenced by texture and surface load. Referencing textures. base address. but the pointer cannot otherwise be treated as an address. For working with textures and samplers.u64} reg.texref type that describe sampler properties are ignored.texref handle. accessing the pointer with ld and st instructions.0 5. field ordering. Creating pointers to opaque variables using mov. or performing pointer arithmetic will result in undefined results. In independent mode the fields of the . 2010 ..PTX ISA Version 2. texture and sampler information is accessed through a single . and surface descriptor variables. 34 January 24. The following tables list the named members of each type for unified and independent texture modes.surfref. since these properties are defined by . Texture. .

mirror. mirror. 1 nearest. State Spaces. Types. Member width height depth Opaque Type Fields in Independent Texture Mode . linear wrap. 2010 35 . linear wrap. clamp_to_border N/A N/A N/A N/A N/A .texref values in elements in elements in elements 0. clamp_to_border 0. clamp_ogl.samplerref values N/A N/A N/A N/A nearest.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10.texref values . 1 ignored ignored ignored ignored . and Variables Table 9.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Member width height depth Opaque Type Fields in Unified Texture Mode .Chapter 5. clamp_ogl. clamp_to_edge. clamp_to_edge.

. Example: .param state space. . Example: .PTX ISA Version 2.texref my_texture_name.samplerref tsamp1 = { addr_mode_0 = clamp_to_border. filter_mode = nearest }.global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global . these variables must be in the .surfref my_surface_name. these variables are declared in the . At module scope. . When declared at module scope.global state space.texref tex1.samplerref my_sampler_name.global . 2010 . As kernel parameters. 36 January 24.global .global . the types may be initialized using a list of static expressions assigning values to the named members.

struct float4 { .f32 V.global .f32 v0. Examples: .f32 bias[] = {-1.global . This is a common case for three-dimensional grids. an optional initializer. and Variables 5. Vectors must be based on a fundamental type.u16 uv. .v4 vector.v4 . // a length-4 vector of bytes By default. Variable Declarations All storage for data is specified with variable declarations. a variable declaration describes both the variable’s type and its state space.u32 loc. // a length-2 vector of unsigned ints .v4 . 2010 37 . where the fourth element provides padding. .global . textures. . // typedef .u8 bg[4] = {0. Examples: . Variables In PTX. January 24. .f32 accel. Vectors cannot exceed 128-bits in length. State Spaces. Types. 1. PTX supports types for simple aggregate objects such as vectors and arrays. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . 0. // a length-4 vector of floats . Three-element vectors may be handled by using a .4. an optional array size. to enable vector load and store instructions which require addresses aligned to a multiple of the access size.v2 . 5.2. r. q. its type and size.v1. 0}. 5.struct float4 coord.1. . Vectors Limited-length vector types are supported. A variable declaration names the space in which the variable resides.shared .v2. its name.pred p. 0. vector variables are aligned to a multiple of their overall size (vector length times base-type size).f64 is not allowed.reg .Chapter 5.4.4. .v2 or .const .global . Predicate variables may only be declared in the register state space. and an optional fixed address for the variable. and they may reside in the register space. In addition to fundamental types. etc.reg . for example. .0}.v4.global .0. Every variable must reside in one of the state spaces enumerated in the previous section.v4.v4 .b8 v.s32 i.reg .v3 }.

Initializers are allowed for all types except .4.0. .{. A scalar takes a single value.global . {0. To declare an array. {0. variable initialization is supported only for constant and global state spaces. 5. label names appearing in initializers represent the address of the next instruction following the label. 0}.0 5. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).1. The size of the array specifies how many elements should be reserved.0}. 1} }. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. being determined by an array initializer. Variables that hold addresses of variables or instructions should be of type . 2010 . Here are some examples: .u64. For the kernel declaration above.0.global . Examples: .0}}.1.05}}.. {0.0.global ..local .f32 blur_kernel[][] = {{.4.global ... The size of the dimension is either a constant expression.3.4.0}.f16 and .05}.. Similarly. .0. where the variable name is followed by an equals sign and the initial value or values for the variable.1. .u32 or .s32 n = 10.b32 ptr = rgba. this can be used to statically initialize a pointer to a variable. // address of rgba into ptr Currently.u16 kernel[19][19]. Array Declarations Array declarations are provided to allow the programmer to reserve space. .05.4. .shared .1.global .1}..1.pred. {0. 19*19 (361) halfwords are reserved (722 bytes). 38 January 24. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. or is left empty. {1.u8 mailbox[128].{. 0}. -1}. Variable names appearing in initializers represent the address of the variable.PTX ISA Version 2.05.s32 offset[][] = { {-1.u8 rgba[3] = {{1. this can be used to initialize a jump table to be used with indirect branches or calls.v4 .

. named %r0. Rather than require explicit declaration of every name. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.b32 variables..0}. not for individual elements.align 4 . PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. say one hundred. …. %r99.5. Alignment is specified using an optional . The default alignment for scalar and array variables is to a multiple of the base-type size.0.align byte-count specifier immediately following the state-space specifier.const . 2010 39 . 5. January 24.0.4..6.b8 bar[8] = {0. and Variables 5. of .Chapter 5. %r1.0.reg . For arrays.0. Examples: // allocate array at 4-byte aligned address. For example.. Array variables cannot be declared this way. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. Parameterized Variable Names Since PTX supports virtual registers. The variable will be aligned to an address which is an integer multiple of byte-count. and may be preceded by an alignment specifier. Elements are bytes.2. State Spaces. it is quite common for a compiler frontend to generate a large number of register names. // declare %r0.4. These 100 register variables can be declared as follows: .b32 %r<100>.0. %r1. The default alignment for vector variables is to a multiple of the overall vector size. alignment specifies the address alignment for the starting address of the entire array. nor are initializers permitted. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. suppose a program uses a large number. . Types.

2010 .0 40 January 24.PTX ISA Version 2.

The mov instruction copies data between registers. The bit-size type is compatible with every type having the same size. the sizes of the operands must be consistent.reg register state space. b. s. and cvt instructions copy data from one location to another. PTX describes a load-store machine. 6. st. as its job is to convert from nearly any data type to any other data type (and size).1. Operand Type Information All operands in instructions have a known type from their declarations. . There is no automatic conversion between types. and c. Integer types of a common size are compatible with each other. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.Chapter 6. January 24. and a few instructions have additional predicate source operands. Most instructions have an optional predicate guard that controls conditional execution. 2010 41 . The result operand is a scalar or vector variable in the register state space. Source Operands The source operands are denoted in the instruction descriptions by the names a. r. mov. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. The ld. Each operand type must be compatible with the type determined by the instruction template and instruction type. Predicate operands are denoted by the names p.2. Instruction Operands 6. 6. Instructions ld and st move data from/to addressable state spaces to/from registers. The cvt (convert) instruction takes a variety of operand types and sizes. q. For most operations.3. so operands for ALU instructions must all be in variables declared in the .

The syntax is similar to that used in many assembly languages. Here are a few examples: . arrays. [V]. and immediate address expressions which evaluate at compile-time to a constant address. .const. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. .f32 V.u16 r0.u16 ld.s32 q.s32 mov. ld. The mov instruction can be used to move the address of a variable into a pointer.const . 6. 2010 .0 6. . . Arrays. The interesting capabilities begin with addresses. address register plus byte offset.v4. there is no support for C-style pointer arithmetic. Using Addresses.reg . .PTX ISA Version 2. . [tbl+12]. tbl.v4 .s32 tbl[256]. and Vectors Using scalar variables as operands is straightforward. p.[x].reg . The address is an offset in the state space in which the variable is declared.f32 ld. Examples include pointer arithmetic and pointer comparisons.reg .4.u32 42 January 24.4.b32 p.global .f32 W. Load and store operations move data between registers and locations in addressable state spaces.shared . All addresses and address computations are byte-based.v4 .gloal.reg . q.u16 x. and vectors. r0.shared. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. Address expressions include variable names. address registers. W.1.

a 6.v4.global.d}.x. it must be written as an address calculation prior to use. or a braceenclosed list of similarly typed scalars. The size of the array is a constant in the program. or by indexing into the array using square-bracket notation. c.u32 s. If more complicated indexing is desired. . Vector elements can be extracted from the vector with the suffixes . which include mov.b and .4.reg . mov. .f32 a.f32 {a.global. Vectors as Operands Vector operands are supported by a limited subset of instructions.global. The registers in the load/store operations can be a vector. V.r V.v4 .reg .u32 {a.u32 s. Elements in a brace-enclosed vector. a[1].2.y. and tex. Array elements can be accessed using an explicitly calculated byte address.4.g V. as well as the typical color fields . January 24.y V. Rc. where the offset is a constant expression that is either added or subtracted from a register variable. d. and in move instructions to get the address of the label or function into a register. mov.u32 s. A brace-enclosed list is used for pattern matching to pull apart vectors. . Instruction Operands 6.g. a[N-1].b.global. Vector loads and stores can be used to implement wide loads and stores. ld.4. b. ld. .f32 V. V2. Here are examples: ld.c. Rd}. Arrays as Operands Arrays of all types can be declared.Chapter 6. which may improve memory performance. or a simple “register with constant offset” expression. [addr+offset2].f32 ld.v4.x V.w = = = = V. [addr+offset]. . say {Ra.w.v2. a[0].b V. . // move address of a[1] into s 6. Examples are ld. Rb. for use in an indirect branch or call.d}. and the identifier becomes an address constant in the space where the array is declared.a.z V. 2010 43 .z and . The expression within square brackets is either a constant integer.3.r. st. Vectors may also be passed as arguments to called functions.4. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.b.c. a register variable.

Type Conversion All operands to all arithmetic.1. logic. Operands of different sizes or types must be converted prior to the operation.0 6.000 for f16). and data movement instruction must be of the same type and size. except for operations where changing the size and/or type is part of the definition of the instruction.5.s32. the u16 is zero-extended to s32.u16 instruction is given a u16 source operand and s32 as a destination operand. For example. 6. if a cvt. and ~131. 2010 . Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.5.PTX ISA Version 2. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. 44 January 24.

u2f = unsigned-to-float.Chapter 6. f2u = float-to-unsigned. s2f = signed-to-float. The type of extension (sign or zero) is based on the destination format. For example. chop = keep only low bits that fit.s16. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2f = float-to-float. cvt.u32 targeting a 32-bit register will first chop to 16-bits. Notes 1 If the destination register is wider than the destination format. 2010 45 . the result is extended to the destination register width after chopping. Instruction Operands Table 11. then sign-extend to 32-bits. zext = zero-extend. f2s = float-to-signed. January 24.

0 6.rzi . Rounding Modifiers Conversion instructions may specify a rounding modifier.rmi . choosing even integer if source is equidistant between two integers. Modifier .PTX ISA Version 2. there are four integer rounding modifiers and four floating-point rounding modifiers.rm .rn .rni . In PTX. The following tables summarize the rounding modifiers.rz .rpi Integer Rounding Modifiers Description round to nearest integer. Modifier . 2010 . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.5. Table 12.2.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.

Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Operand Costs Operands from different state spaces affect the speed of an operation. Much of the delay to memory can be hidden in a number of ways. first access is high Notes January 24. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Instruction Operands 6. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. while global memory is slowest. Table 11 gives estimates of the costs of using different kinds of memory. 2010 47 .Chapter 6.6. Another way to hide latency is to issue the load instructions as early as possible. Table 14. The register in a store operation is available much more quickly. Registers are fastest.

0 48 January 24.PTX ISA Version 2. 2010 .

The simplest function has no parameters or return values. A function declaration specifies an optional list of return parameters. Scalar and vector base-type input and return parameters may be represented simply as register variables. A function must be declared or defined prior to being called. 2010 49 . support for variadic functions (“varargs”). stack-based ABI. or prototype. parameter passing. January 24. and is represented in PTX as follows: . together these specify the function’s interface. Abstracting the ABI Rather than expose details of a particular calling convention. 7. NOTE: The current version of PTX does not implement the underlying. and an optional list of input parameters. the function name. and memory allocated on the stack (“alloca”). In this section.1. These include syntax for function definitions.func directive. } … call foo. Function declarations and definitions In PTX.Chapter 7. stack layout. At the call. … Here. Execution of the ret instruction within foo transfers control to the instruction following the call. arguments may be register variables or constants.func foo { … ret. we describe the features of PTX needed to achieve this hiding of the ABI. functions are declared and defined using the . execution of the call instruction transfers control to foo. so recursion is not yet supported. A function definition specifies both the interface and the body of the function. function calls. and return values may be placed directly into register variables. implicitly saving the return address. and Application Binary Interface (ABI). PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters.

a .reg . inc_ptr.s32 x. c3.f1. First.b8 c2. [y+0].param.c1. In PTX.c4. %rd.param. [y+9].param space variables are used in two ways.func (. byte array in .reg .param . ld.reg .PTX ISA Version 2. .param.b8 [py+ 9]. // scalar args in .param variable y is used in function definition bar to represent a formal parameter.b32 c1.reg .c2. char c[4]. st.param.b8 c3.b8 c1. … ld.f64 f1.param space memory. %rc1.u32 %inc ) { add. [y+11]. %rc2. The . ld. } … call (%r1). … … // computation using x. %rc2.reg .reg . this structure will be flattened into a byte array. a . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . consider the following C structure. st. passed by value to a function: struct { double dbl. Since memory accesses are required to be aligned to a multiple of the access size. [y+8]. For example. ld. }.reg . %ptr. ld.b8 [py+ 8].param. 50 January 24.b8 [py+10].b64 [py+ 0]. Second.param state space is used to pass the structure by value: . %inc.f64 field are aligned.align 8 py[12]. bumpptr.func (. } { .param.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. .u32 %ptr. (%x. [y+10].f64 f1. (%r1.s32 out) bar (. note that . ret. st.reg space. %rc1.c3.0 Example: .4).b8 .u32 %res) inc_ptr ( . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .b8 [py+11].param. . py).param space call (%out). c4.param.param. st.b8 . … In this example. c2.param. 2010 .u32 %res.align 8 y[12]) { . … st.param .b8 c4.

a . the corresponding argument may be either a . or a constant that can be represented in the type of the formal parameter. • • • For a callee.param state space use in device functions. • The .param space formal parameters that are byte arrays. • The . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. In the case of .param argument must be declared within the local scope of the caller. 2010 51 . the corresponding argument may be either a .param space byte array with matching type..reg or .reg space variable of matching type and size.reg space formal parameters.param and ld. • • • Input and return parameters may be .param variables.param or . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. Abstracting the ABI The following is a conceptual way to think about the .reg variables. This enables backend optimization and ensures that the .Chapter 7. or a constant that can be represented in the type of the formal parameter.param byte array is used to collect together fields of a structure being passed by value. Parameters in . In the case of . For a caller.g.param memory must be aligned to a multiple of 1.reg state space in this way provides legacy support. For a caller. . In the case of . • • Arguments may be .reg state space can be used to receive and return base-type scalar and vector values. size.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. all st. and alignment.param arguments.param space formal parameters that are base-type scalar or vector variables. size.param state space is used to receive parameter values and/or pass return values back to the caller. The .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. Typically.reg space variable with matching type and size. Note that the choice of . 8. The following restrictions apply to parameter passing. A . or 16 bytes. 2.param state space is used to set values that will passed to a called function and/or to receive return values from a called function.param or .param instructions used for argument passing must be contained in the basic block with the call instruction. For a callee. or constants. Supporting the .param variables or . For . The . the argument must also be a . 4. and alignment of parameters. January 24.reg variables.

x In PTX ISA version 1. In PTX ISA version 2.reg state space. For sm_2x targets.param state space. formal parameters were restricted to . and there was no support for array parameters. and a . Objects such as C structures were flattened and passed or returned using multiple registers.param byte array should be used to return objects that do not fit into a register. PTX 1.1. 52 January 24.0 continues to support multiple return registers for sm_1x targets.x supports multiple return values for this purpose.0 7.1. PTX 2. formal parameters may be in either .param space parameters support arrays.PTX ISA Version 2. PTX 2.x.reg or . 2010 . and . Changes from PTX 1.0.0 restricts functions to a single return value.

maxN.u32 a. call (ap).reg . result. The function prototypes are defined as follows: . . the size may be 1. 2010 53 . ret.reg . .reg .reg .reg . bra Loop.reg .reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .h headers in C. max.u32 sz. 2. Abstracting the ABI 7. %r2.func baz ( . (ap.u32 ap.u32 ptr. bra Done.reg .u32 ptr.func (. %r3).u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg . (3. or 4 bytes.. call (val). setp.func okay ( … ) Built-in functions are provided to initialize. the size may be 1. 8. %va_end is called to free the variable argument list handle.u32.Chapter 7.reg . To support functions with a variable number of arguments. %r1.pred p.func ( . Variadic functions NOTE: The current version of PTX does not support variadic functions. the alignment may be 1. %va_start.u32 align) . Once all arguments have been processed.2. val. following zero or more fixed parameters: . .ge p. (ap). . 4. This handle is then passed to the %va_arg and %va_arg64 built-in functions.func %va_end (. N. variadic functions are declared with an ellipsis at the end of the input parameter list.reg .b32 val) %va_arg (. and end access to a list of variable arguments.u32 ptr) %va_start . .u32 N.u32 align) . 2. %s1. } … call (%max). … ) . ) { . along with the size and alignment of the next data value to be accessed. In both cases.b64 val) %va_arg64 (.u32 b. for %va_arg64. 2. maxN. . call %va_end.b32 result. For %va_arg.h and varargs.reg .func (. . iteratively access. .reg . … call (%max).s32 result. 4).s32 result ) maxN ( .func (. %s2). or 8 bytes. 4.reg .. (2.reg . %va_arg. // default to MININT mov. In PTX. 0x8000000. mov. … %va_start returns Loop: @p Done: January 24. 0. PTX provides a high-level mechanism similar to the one provided by the stdarg. ctr.s32 val.reg .b32 ctr. or 16 bytes.reg . 4.u32 sz. ctr.

reg .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. a function simply calls the built-in function %alloca.local and st.u32 ptr ) %alloca ( . 2010 .func ( . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.PTX ISA Version 2.0 7. To allocate memory. 54 January 24. The array is then accessed with ld. defined as follows: .local instructions. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.reg . Alloca NOTE: The current version of PTX does not support alloca.3. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. If a particular alignment is required.

b.Chapter 8. In addition to the name and the format of the instruction. the semantics are described. B. For instructions that create a result value. q = !(a < b). A. 8. a. while A. 2010 55 . Instruction Set 8. and C are the source operands. January 24. opcode D. The setp instruction writes two destination registers.1. opcode D. // p = (a < b). For some instructions the destination operand is optional. C. setp. B. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. opcode A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. We use a ‘|’ symbol to separate multiple destination registers. the D operand is the destination operand. PTX Instructions PTX instructions generally have from zero to four operands. opcode D. A. followed by some examples that attempt to show several possible instantiations of the instruction.s32.lt p|q. B. A.2. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode.

s32 j.reg . The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. branch over 56 January 24. // p = (i < n) // if i < n. j. consider the high-level code if (i < n) j = j + 1. the following PTX instruction sequence might be used: @!p L1: setp. Predicated Execution In PTX.s32 p. So. optionally negated. add 1 to j To get a conditional branch or conditional function call. i.0 8. q. use a predicate to control the execution of the branch or call instructions. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. Instructions without a guard predicate are executed unconditionally. This can be written in PTX as @p setp. Predicates are most commonly set as the result of a comparison performed by the setp instruction. bra L1. As an example. add. i. predicate registers can be declared as . predicate registers are virtual and have .lt.3. 1. n.s32 p.pred p.s32 j. where p is a predicate variable. 1. j. n.pred as the type specifier.PTX ISA Version 2.lt. To implement the above example as a true conditional branch. 2010 . … // compare i to n // if false. add.

1. gt. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). and hs (higher-or-same).1. lt (less-than). ls (lower-or-same).1. 2010 57 .2. Instruction Set 8. Comparisons 8. le (less-than-or-equal). ne. ordering comparisons are not defined for bit-size types. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Table 16. If either operand is NaN. ne (not-equal). unsigned integer. the result is false. hi (higher). and bitsize types.3. and ge (greater-than-or-equal). lo (lower).Chapter 8.3. The bit-size comparisons are eq and ne. ge. gt (greater-than). ne. lt. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.3.1. le. Table 15. Unsigned Integer. The following table shows the operators for signed integer. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. The unsigned comparisons are eq.

and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. gtu.u32 %r1. then these comparisons have the same result as their ordered counterparts. ltu. unordered versions are included: equ. If both operands are numeric values (not NaN).1. // convert predicate to 32-bit value 58 January 24. However. for example: selp. 2010 . or.0 To aid comparison operations in the presence of NaN values. setp can be used to generate a predicate from an integer. not.3. There is no direct conversion between predicates and integer values. neu. then the result of these comparisons is true. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. and no direct way to load or store predicate register values. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. geu.%p.0. Table 17.PTX ISA Version 2. two operators num (numeric) and nan (isNaN) are provided. leu. and mov. xor. Table 18. num returns true if both operands are numeric values (not NaN). and nan returns true if either operand is NaN. If either operand is NaN.2. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.

reg . Signed and unsigned integer types agree provided they have the same size. they must match exactly.f32.sX ok ok ok inv . different sizes). Floating-point types agree only if they have the same size. Type Checking Rules Operand Type .uX ok ok ok inv . float.u16 d. and integer operands are silently cast to the instruction type if needed.uX . Table 19. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. b.fX ok inv inv ok Instruction Type .u16 a.fX ok ok ok ok January 24. i. • The following table summarizes these type checking rules.sX .e.bX .bX . Example: . the add instruction requires type and size information to properly perform the addition operation (signed. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. cvt. . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. unsigned. most notably the data conversion instruction cvt.4. and this information must be specified as a suffix to the opcode. a. a.reg . a. add. 2010 59 . For example. It requires separate type-size modifiers for the result and source. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.reg . For example: . b.f32 d.Chapter 8. For example. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Instruction Set 8..u16 d. and these are placed in the same order as the operands.u16 d.

and cvt instructions permit source and destination data operands to be wider than the instruction-type size. The data is truncated to the instruction-type size and interpreted according to the instruction type. “-“ = allowed. no conversion needed. 4. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. unless the operand is of bit-size type. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. 1. Operand Size Exceeding Instruction-Type Size For convenience. the cvt instruction does not support . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Notes 3.1. parse error. for example.0 8. Table 20. and converted using regular-width registers. Source register size must be of equal or greater size than the instruction-type size. st. Bit-size source registers may be used with any appropriately-sized instruction type. stored. ld. For example. When used with a narrower bit-size type. floating-point instruction types still require that the operand type-size matches exactly. inv = invalid.bX instruction types. the size must match exactly. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Floating-point source registers can only be used with bit-size or floating-point instruction types. When used with a floating-point instruction type. the data will be truncated. Note that some combinations may still be invalid for a particular instruction. 60 January 24. so that narrow values may be loaded. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. 2010 .PTX ISA Version 2. so those rows are invalid for cvt. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.4. The following table summarizes the relaxed type-checking rules for source operands. stored. When a source operand has a size that exceeds the instruction-type size. 2. or converted to other types and sizes.

4. When used with a narrower bit-size instruction type. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. January 24. Destination register size must be of equal or greater size than the instruction-type size. the destination data is zero. otherwise. Table 21. 2. The data is signextended to the destination register width for signed integer instruction types. the size must match exactly. the data is zeroextended. 1. Notes 3. The following table summarizes the relaxed type-checking rules for destination operands. Bit-size destination registers may be used with any appropriately-sized instruction type. If the corresponding instruction type is signed integer.or sign-extended to the size of the destination register. Floating-point destination registers can only be used with bit-size or floating-point instruction types. “-“ = Allowed but no conversion needed. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. zext = zero-extend. Instruction Set When a destination operand has a size that exceeds the instruction-type size. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. parse error. inv = Invalid. and is zero-extended to the destination register width otherwise. When used with a floatingpoint instruction type.Chapter 8. 2010 61 . The data is sign-extended to the destination register width for signed integer instruction types. the data is sign-extended. the data will be zero-extended.

using the . These extra precision bits can become visible at the application level. Both situations occur often in programs. and 16-bit computations are “promoted” to 32-bit computations. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 16-bit registers in PTX are mapped to 32-bit physical registers. Therefore. the threads are called uniform. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. Divergence of Threads in Control Constructs Threads in a CTA execute together.uni suffix. The semantics are described using C. When executing on a 32-bit data path. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. However. by a right-shift instruction. until C is not expressive enough. a compiler or code author targeting PTX can ignore the issue of divergent threads.6. until they come to a conditional control construct such as a conditional branch. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. If all of the threads act in unison and follow a single control flow path.PTX ISA Version 2. At the PTX language level. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. the threads are called divergent.0 8. 2010 .5. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform.1. 62 January 24. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. If threads execute down different control flow paths. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. the semantics of 16-bit instructions in PTX is machine-specific. or conditional return. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. A compiler or programmer may chose to enforce portable. the optimizing code generator automatically determines points of re-convergence. so it is important to have divergent threads re-converge as soon as possible. for many performance-critical applications. 8. 8. and for many applications the difference in execution is preferable to limiting performance. For divergent control flow. conditional function call. for example. this is not desirable. at least in appearance.6.

Instructions All PTX instructions may be predicated.Chapter 8.cc. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.1.7. In the following descriptions. Instruction Set 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. 8. The Integer arithmetic instructions are: add sub add.7. addc sub. the optional guard predicate is omitted from the syntax.cc. 2010 63 .

z.u32.s32. Introduced in PTX ISA version 1. b. // . . . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. @p add.sat. a.sat limits result to MININT.0 Table 22. b.u64. sub.PTX ISA Version 2. Supported on all target architectures.s16. Introduced in PTX ISA version 1. .s32 c.type sub{. d = a + b.s64 }..sat limits result to MININT.type = { . sub. a.y.c.u32 x. Saturation modifier: .MAXINT (no overflow) for the size of the operation. add.sat}. .s32 d. Supported on all target architectures.sat applies only to .b.s32 c. . Applies only to . a.type add{.s32 type.s32 . PTX ISA Notes Target ISA Notes Examples Table 23..0. Applies only to . Saturation modifier: . .s32 .1.s32 d. d.type = { .MAXINT (no overflow) for the size of the operation. . d = a – b.s64 }. d. add Syntax Integer Arithmetic Instructions: add Add two values. PTX ISA Notes Target ISA Notes Examples 64 January 24. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. b. .s32.0. Description Semantics Notes Performs addition and writes the resulting value into a destination register.u16. add.s16. b. .sat}. a.u64.u16. // . 2010 .sat applies only to .u32.s32 type.a. .

. No saturation. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y4.cc. .z1.cc.b32 addc.cc. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.s32 }.y3. 2010 65 .CF No integer rounding modifiers.z3.cc. @p @p @p @p add.2.b32 addc. Behavior is the same for unsigned and signed integers. x3.cc.b32 addc.cc. No other instructions access the condition code.CF) holding carry-in/carry-out or borrowin/borrow-out. addc.b32 x1.u32.type = { . d = a + b + CC.b32 addc. Behavior is the same for unsigned and signed integers. These instructions support extended-precision integer addition and subtraction.z3.cc specified.CF No integer rounding modifiers.cc.y2.u32. a.b32 x1. x4. Table 24. No saturation. Supported on all target architectures.z4.b32 addc. b.Chapter 8. @p @p @p @p add. Instruction Set Instructions add. add.s32 }.y1. Supported on all target architectures.y2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. x2.2. . add. clearing.type d. x4. if .y4. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. Introduced in PTX ISA version 1. sub.y1.y3. b.cc Add two values with carry-out.cc.cc. Introduced in PTX ISA version 1.z4.type = {.z2. and there is no support for setting. . or testing the condition code. addc{.cc}.z1.cc Syntax Integer Arithmetic Instructions: add. x3. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.b32 addc.CF.z2. carry-out written to CC. a. x2.cc.type d. carry-out written to CC. d = a + b.

x2. Introduced in PTX ISA version 1.cc.cc. Supported on all target architectures.type = { . subc{.cc.b32 x1.b32 subc. x3.y4.z1. borrow-out written to CC. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers.3.y3.u32.CF No integer rounding modifiers.z3.b32 x1.y3. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.z2. Behavior is the same for unsigned and signed integers.type = {.cc.y2.cc. a.type d.u32.(b + CC. @p @p @p @p sub. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. d = a . // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. No saturation. borrow-out written to CC. withborrow-in and optional borrow-out. if . b.PTX ISA Version 2. 2010 .cc}.b32 subc.z4. x2.CF).y1.cc. with borrow-out. @p @p @p @p sub. a. .b32 subc.cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.type d.z4.b32 subc. x3.cc.s32 }. Supported on all target architectures. .b32 subc.s32 }.cc Syntax Integer Arithmetic Instructions: sub. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y2. .cc specified. sub.y4. x4.cc.y1. sub.cc Subract one value from another.3.0 Table 26. x4. d = a – b.b32 subc. .z2.z3.z1. b. No saturation. Introduced in PTX ISA version 1.

b. a. creates 64 bit result January 24.hi or .s16.lo.s16 fa. d = t. save only the low 16 bits // 32*32 bits. Instruction Set Table 28. then d is twice as wide as a and b to receive the full result of the multiplication.hi variant // for .type d.lo.wide.s16 fa. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.y. mul.wide}.u16..type = { . . t = a * b.wide. n = bitwidth of type. then d is the same size as a and b. d = t<2n-1.wide suffix is supported only for 16. If . mul{.n>. . // 16*16 bits yields 32 bits // 16*16 bits. .s32.wide is specified. Supported on all target architectures. If .s32 z.fxs. mul.wide // for .Chapter 8.0. and either the upper or lower half of the result is written to the destination register.s64 }. mul. mul Syntax Integer Arithmetic Instructions: mul Multiply two values..0>. Description Semantics Compute the product of two values. 2010 67 .. . . The .lo is specified.hi..u32.fys. d = t<n-1. // for .fxs.lo variant Notes The type of the operation represents the types of the a and b operands.u64.fys. .and 32-bit integer types.x.

Applies only to .hi. d.wide}.s64 }. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. mad.PTX ISA Version 2. bitwidth of type. t<2n-1.wide suffix is supported only for 16.. 68 January 24.type = { .sat limits result to MININT.p.wide is specified. a. If . t + c.lo.r. Saturation modifier: .u16. c.lo.type mad. and either the upper or lower half of the result is written to the destination register.c. .n> + c. If .s32 type in . @p mad. Description Semantics Multiplies two values and adds a third. .0 Table 29. t<n-1.u64..s32 r.s32. b. // for .hi mode. . The . b.hi.wide // for . 2010 .a.0.lo is specified.b.s16. mad{.sat.. . .s32 d.lo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.MAXINT (no overflow) for the size of the operation.hi variant // for .hi or . . c. t n d d d = = = = = a * b. then d and c are twice as wide as a and b to receive the result of the multiplication.and 32-bit integer types. a. Supported on all target architectures.q.0> + c.lo variant Notes The type of the operation represents the types of the a and b operands. then d and c are the same size as a and b. and then writes the resulting value into a destination register..s32 d..u32.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24{.s32 }.0>. All operands are of the same type and size.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. i.type d.a. d = t<31. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d.. mul24..lo}. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. 2010 69 .lo.hi variant // for . Instruction Set Table 30.hi. // low 32-bits of 24x24-bit signed multiply. mul24.16>. . b. .b.u32.Chapter 8.0. a. d = t<47. Supported on all target architectures. 48bits.hi may be less efficient on machines without hardware support for 24-bit multiply.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. mul24.. t = a * b. January 24.type = { . // for .e. and return either the high or low 32-bits of the 48-bit result.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24.

Supported on all target architectures. d = t<47. mad24.16> + c. Return either the high or low 32-bits of the 48-bit result. mad24. 32-bit value to either the high or low 32-bits of the 48-bit result.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. a.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.hi variant // for . mad24. and add a third.s32 d. .hi may be less efficient on machines without hardware support for 24-bit multiply. b. Saturation modifier: .type = { .hi.lo.e. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.0 Table 31. c.s32 type in .hi mode.b.sat. 2010 .. . d.a.s32 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. c.type mad24.0. a.s32 d.. All operands are of the same type and size.0> + c. i. t = a * b. 70 January 24. mad24{.u32.c..PTX ISA Version 2.MAXINT (no overflow).lo}. // low 32-bits of 24x24-bit signed multiply.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. 48bits. Applies only to . d = t<31.sat limits result of 32-bit signed addition to MININT. Description Compute the product of two 24-bit integer values held in 32-bit source registers. mad24. // for .hi. b..

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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cnt. .b32. } Introduced in PTX ISA version 2. X. .u32 PTX ISA Notes Target ISA Notes Examples Table 40. a.0. the number of leading zeros is between 0 and 32.PTX ISA Version 2.type d. // cnt is .b32 popc. d = 0. popc requires sm_20 or later. cnt. while (a != 0) { if (a&0x1) d++. a = a >> 1.u32 Semantics 74 January 24. popc. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. popc Syntax Integer Arithmetic Instructions: popc Population count. a. } else { max = 64.type d.0. the number of leading zeros is between 0 and 64.b32) { max = 32. mask = 0x80000000.type = { . a. clz requires sm_20 or later. 2010 . . a.b32. mask = 0x8000000000000000.b32 clz. inclusively. . inclusively. For . a = a << 1.b64 d.b32 type.type == . For . Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.0 Table 39. } while (d < max && (a&mask == 0) ) { d++.b64 d. d = 0.b64 }.b64 type.b64 }. // cnt is .type = { . if (. X. clz. popc.

Operand a has the instruction type.shiftamt.u64. bfind.u32 January 24.shiftamt && d != -1) { d = msb .type==. i>=0. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. .s64 cnt. bfind. .s32) ? 31 : 63. Semantics msb = (.shiftamt. and operand d has type . bfind.0.Chapter 8.u32 d. bfind returns 0xFFFFFFFF if no non-sign bit is found.s64 }. If .s32. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. . 2010 75 . i--) { if (a & (1<<i)) { d = i.shiftamt is specified. for (i=msb.type bfind. X. For signed integers.u32.u32 || . bfind requires sm_20 or later. Instruction Set Table 41. break.u32.type = { .type d. Description Find the bit position of the most significant non-sign bit in a and place the result in d. // cnt is . bfind returns the bit position of the most significant “1”. d. . For unsigned integers.d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==. } } if (. a. d = -1. a. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. a.

i++) { d[i] = a[msb-i]. Description Semantics Perform bitwise reversal of input.PTX ISA Version 2.0 Table 42. brev requires sm_20 or later. .b32) ? 31 : 63. 76 January 24.type==. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. .0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. a. a.type d. msb = (. i<=msb.type = { . brev.b32 d. for (i=0. 2010 .b64 }. brev.

.start.len. Instruction Set Table 43. Description Extract bit field from a and place the zero or sign-extended result in d. bfe. else sbit = a[min(pos+len-1.msb)]. Semantics msb = (.type==. . len = c.type==.u64 || len==0) sbit = 0. .type==.type==.s64 }.s32) ? 31 : 63. bfe requires sm_20 or later. pos = b.type d. .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. otherwise If the bit field length is zero. January 24. The sign bit of the extracted field is defined as: .s32.Chapter 8.u32 || . for (i=0.u32 || . 2010 77 . and source c gives the bit field length in bits.u32. and operands b and c are type . Operands a and d have the same type as the instruction type. a. . d = 0.a.b32 d. i<=msb. If the start position is beyond the msb of the input. the destination d is filled with the replicated sign bit of the extracted field. the result is zero. b. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.u64: . Source b gives the bit field starting bit position.type = { .u64. bfe.0.u32.u32. if (. .s32. The destination d is padded with the sign bit of the extracted field.

pos = c. Operands a.type==.PTX ISA Version 2. c. b. 78 January 24.b. a.b64 }. and source d gives the bit field length in bits.len.u32. b.b32.type = { . .0.start. bfi. the result is b. len = d. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. and f have the same type as the instruction type. . the result is b. If the start position is beyond the msb of the input.b32) ? 31 : 63. Semantics msb = (. If the bit field length is zero. i<len && pos+i<=msb. bfi. and place the result in f. for (i=0. d.type f. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Source c gives the starting bit position for the insertion.a. i++) { f[pos+i] = a[i]. and operands c and d are type . bfi requires sm_20 or later.0 Table 44. f = b. Description Align and insert a bit field from a into b.b32 d. 2010 .

b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.b2 source select c[11:8] d. .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. The msb defines if the byte value should be copied.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. b0}}. as a 16b permute code. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. prmt. the permute control consists of four 4-bit selection values.mode = { .ecl.b1 source select c[7:4] d. The bytes in the two source registers are numbered from 0 to 7: {b.Chapter 8. Description Pick four arbitrary bytes from two 32-bit registers. and reassemble them into a 32-bit destination register. b6.ecr. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. {b3. . b2. For each byte in the target register. a. Instruction Set Table 45.f4e. Note that the sign extension is only performed as part of generic form. . a} = {{b7. b4}. . .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. msb=1 means replicate the sign. 2010 79 . b1. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b32{. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. c. Thus.b4e. b5. msb=0 means copy the literal value. a 4-bit selection value is defined.rc16 }.b3 source select c[15:12] d.rc8. b. default mode index d.mode} d.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. In the generic form (no mode specified). the four 4-bit values fully specify an arbitrary byte permute. .

r3.b32 prmt. 80 January 24. tmp64 ). r4. r3. ctl[0]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[1]. 2010 . ctl[2] = (c >> 8) & 0xf. r2. tmp64 ).f4e r1. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r1. tmp[31:24] = ReadByte( mode. ctl[2]. prmt requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. tmp64 ). } tmp[07:00] = ReadByte( mode. tmp[15:08] = ReadByte( mode. tmp64 ). r2. ctl[3] = (c >> 12) & 0xf.PTX ISA Version 2. r4. ctl[1] = (c >> 4) & 0xf. tmp[23:16] = ReadByte( mode.0 Semantics tmp64 = (b<<32) | a.0. prmt. ctl[3].

2010 81 .f64 register operands and constant immediate values. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.7.Chapter 8. Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on .f32 and .2.

0].sub.rcp.sat Notes If no rounding modifier is specified.sqrt}.cos.max}.fma}.rcp.rn and instructions may be folded into a multiply-add. default is .f64 and fma.rn .sub. default is . and mad support saturation of results to the range [0. The optional .0. with NaNs being flushed to positive zero.f32 {mad.rcp.ftz .f64 {sin.min.f32 {div.full.rz .target sm_20 mad. mul. No rounding modifier.f32 {add.f32 rsqrt. {add.sqrt}.approx.f64 rsqrt. 1.rm . Table 46.approx. Double-precision instructions support subnormal inputs and results.neg.f32 {div. Note that future implementations may support NaN payloads for single-precision instructions.rnd. . sub. so PTX programs should not rely on the specific single-precision NaNs being generated. {mad.fma}.rnd.approx.target sm_1x No rounding modifier. 2010 . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f32 . If no rounding modifier is specified. NaN payloads are supported for double-precision instructions.min.mul}.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.neg. 82 January 24.rnd.rnd.f64 div. .mul}.rp . Instruction Summary of Floating-Point Instructions . but single-precision instructions return an unspecified NaN.PTX ISA Version 2.lg2.f32 are the same.f64 mad.rnd.approx.f64 are the same.rn and instructions may be folded into a multiply-add.32 and fma.max}.target sm_20 .sqrt}.f64 {abs.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {div.ex2}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.rnd.f32 {abs.0 The following table summarizes floating-point instructions in PTX. Single-precision add.

finite. testp requires sm_20 or later. copysign requires sm_20 or later.op p.f64 }.infinite. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. C. X.type d. . . and return the result as d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. January 24. .type . A.op. y. f0. Introduced in PTX ISA version 2.pred = { .type = { .f64 }.0. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. B.notanumber.notanumber testp. testp. copysign.f32 testp. true if the input is a subnormal number (not NaN. a.f32. Instruction Set Table 47. positive and negative zero are considered normal numbers. .f64 x.finite testp.notanumber.type = { . z. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.number testp.infinite testp.Chapter 8.infinite. .number.subnormal }. . not infinity).normal. testp Syntax Floating-Point Instructions: testp Test floating-point property. not infinity) As a special case. a. p. copysign.normal testp. b. 2010 83 .f64 isnan. .subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. testp. .0. testp. // result is . Table 48.f32 copysign. .f32.

mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. add.f32 flushes subnormal inputs and results to sign-preserving zero. .f64 d.sat}.f32 add{.f64 supports subnormal numbers. . Rounding modifiers (default is . subnormal numbers are supported.rn mantissa LSB rounds to nearest even . add.0 Table 49.f64. a.f32 supported on all target architectures. d. add. In particular.0f.rp for add.rnd}{. Description Semantics Notes Performs addition and writes the resulting value into a destination register.rp }.rz. requires sm_13 for add.sat.f32 clamps the result to [0.rn.f64 requires sm_13 or later.PTX ISA Version 2.f3. add{. add Syntax Floating-Point Instructions: add Add two values.rnd = { .rm.rnd}.0.ftz. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. a. Rounding modifiers have the following target requirements: . .0].rz available for all targets .ftz. add. requires sm_20 Examples @p add.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}{. Saturation modifier: . add.f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz mantissa LSB rounds towards zero . 84 January 24. d = a + b. sm_1x: add.rm mantissa LSB rounds towards negative infinity .rn. 1. b.rm. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 f1.0. .f2.rz. . NaN results are flushed to +0. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. b. .rn): . 2010 .

mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. sub. subnormal numbers are supported. d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. requires sm_20 Examples sub.sat.rn. requires sm_13 for sub.ftz}{.b. Rounding modifiers (default is . sub.rz mantissa LSB rounds towards zero .f32. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. In particular. .sat}. sm_1x: sub. b.rn.rm. . a. d = a .f64 d.f64. sub.rm mantissa LSB rounds towards negative infinity .f32 c.f32 flushes subnormal inputs and results to sign-preserving zero.0.rnd}. January 24.f3. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64 requires sm_13 or later. Rounding modifiers have the following target requirements: .f32 sub{.Chapter 8.ftz. b.ftz.rz available for all targets .f64 supports subnormal numbers. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. 2010 85 .f32 f1.rnd}{.b.rz.f32 clamps the result to [0.rn mantissa LSB rounds to nearest even . sub{. NaN results are flushed to +0. .rn. sub.a. a. sub Syntax Floating-Point Instructions: sub Subtract one value from another. .f2.0f.f32 supported on all target architectures. sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Instruction Set Table 50.rm.rn): .f32 flushes subnormal inputs and results to sign-preserving zero. . .rnd = { . Saturation modifier: sub.rp }.rp for sub. 1.0.0].

mul.ftz.rz mantissa LSB rounds towards zero . 2010 . Rounding modifiers (default is . .f32 clamps the result to [0. mul. 1.f64.0 Table 51. Rounding modifiers have the following target requirements: .rn.f32 mul{.rz.sat}. subnormal numbers are supported. requires sm_20 Examples mul. mul.f32 supported on all target architectures. .rp }.rm.f64 d. b. b.ftz}{. d.0.f64 supports subnormal numbers. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Saturation modifier: mul. a. all operands must be the same size.rn): .radius. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rm.sat.rn. . NaN results are flushed to +0.ftz.rz available for all targets .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. mul Syntax Floating-Point Instructions: mul Multiply two values.0. Description Semantics Notes Compute the product of two values. mul. a.0f. In particular. mul{.PTX ISA Version 2. requires sm_13 for mul.pi // a single-precision multiply 86 January 24.f32. sm_1x: mul. For floating-point multiplication.rm mantissa LSB rounds towards negative infinity . .rp for mul.rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.0]. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 circumf.rnd}. .f64 requires sm_13 or later.rnd}{. d = a * b.rnd = { .

c.0]. a.rnd{. b. . The resulting value is then rounded to single precision using the rounding mode specified by .sat}. Instruction Set Table 52.f32 fma.ftz. . PTX ISA Notes Target ISA Notes Examples January 24.rn.rm mantissa LSB rounds towards negative infinity . The resulting value is then rounded to double precision using the rounding mode specified by . fma. fma. .f32 is unimplemented in sm_1x. 1.ftz}{. a.f64.f64 d.4. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.f32 requires sm_20 or later.y.x. again in infinite precision. b.rn mantissa LSB rounds to nearest even . d.f64 is the same as mad. Rounding modifiers (no default): . .a.rnd. fma.rnd.0. d = a*b + c.f64 introduced in PTX ISA version 1.rnd = { . d. fma.f32 clamps the result to [0.f32 introduced in PTX ISA version 2. fma. fma.rn.Chapter 8.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.rnd.f64 w.rn.0.0f.z.b. again in infinite precision.rp }.rm. NaN results are flushed to +0.f32 fma. subnormal numbers are supported.f64 supports subnormal numbers. fma Syntax Floating-Point Instructions: fma Fused multiply-add. c.rz mantissa LSB rounds towards zero . c.rz. fma.f64 computes the product of a and b to infinite precision and then adds c to this product. fma. @p fma.ftz. 2010 87 .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Saturation: fma.f32 computes the product of a and b to infinite precision and then adds c to this product. fma. sm_1x: fma. fma.sat.

Description Semantics Notes Multiplies two values and adds a third.rn.0. . .target sm_1x d. mad. and then writes the resulting value into a destination register.{f32. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.rm. again in infinite precision..rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 2010 .0.sat.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. mad.f32). b.f64}.rn mantissa LSB rounds to nearest even .rnd = { .f32 mad. mad. Note that this is different from computing the product with mul. a.f32 flushes subnormal inputs and results to sign-preserving zero. Rounding modifiers (no default): .rp }.e. c. sm_1x: mad.target sm_13 and later . In this case.{f32. mad.rz. 88 January 24. 1. where the mantissa can be rounded and the exponent will be clamped.target sm_20: mad. The exception for mad. and then the mantissa is truncated to 23 bits.f64 is the same as fma. d = a*b + c.0].0f. Unlike mad. Saturation modifier: mad. For . The resulting value is then rounded to double precision using the rounding mode specified by .f64 d.sat}.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 mad.rnd. again in infinite precision. subnormal numbers are supported.f32 is when c = +/-0. c.f32 is implemented as a fused multiply-add (i.rnd.rm mantissa LSB rounds towards negative infinity . The resulting value is then rounded to double precision using the rounding mode specified by . For . c.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero.PTX ISA Version 2.ftz.rnd.target sm_1x: mad.f32. mad. a. mad{. // .rn. b. again in infinite precision.rz mantissa LSB rounds towards zero . fma. b.0 devices.ftz. the treatment of subnormal inputs and output follows IEEE 754 standard.f32 is identical to the result computed using separate mul and add instructions.f32 computes the product of a and b at double precision. a. mad. NaN results are flushed to +0.rnd.sat}. // . but the exponent is preserved. When JIT-compiled for SM 2.f64.f32 clamps the result to [0. mad. .f64} is the same as fma.ftz}{.0 Table 53.ftz}{. The resulting value is then rounded to single precision using the rounding mode specified by .f64 supports subnormal numbers. mad. mad.rnd{.target sm_20 d. // .

requires sm_20 Examples @p mad.rn. requires sm_13 . In PTX ISA versions 2.rz.f64. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1..a.rm.f64. a rounding modifier is required for mad.rm.rn.. mad.rp for mad.rz.f64 instructions having no rounding modifier will map to mad.0 and later. a rounding modifier is required for mad.f32 supported on all target architectures.f32.b.4 and later.. Legacy mad. Rounding modifiers have the following target requirements: . In PTX ISA versions 1..f64.Chapter 8.f32 for sm_20 targets.rp for mad.. 2010 89 .f64 requires sm_13 or later. January 24. Target ISA Notes mad.c..0.rn.f32 d.

f32 div.4 and later.f32 and div. For PTX ISA versions 1. Target ISA Notes div. b.0 through 1. a. Fast.approx.f64 introduced in PTX ISA version 1.approx. div.f32 implements a relatively fast. . d.4. or .ftz.f32 defaults to div.approx. computed as d = a * (1/b).f32.rn.3.f64 requires sm_13 or later.rn mantissa LSB rounds to nearest even . . Explicit modifiers . d.ftz}.f64 defaults to div.approx. y. stores result in d.full. For b in [2-126. zd. 2010 .rz mantissa LSB rounds towards zero . x. .approx.f32 flushes subnormal inputs and results to sign-preserving zero.f32 div. a.f32 flushes subnormal inputs and results to sign-preserving zero. div.f64 requires sm_20 or later.approx.rnd is required. Description Semantics Notes Divides a by b. and rounding introduced in PTX ISA version 1.f32 requires sm_20 or later. PTX ISA Notes div.rm.rn.ftz}.rnd.3. b.rnd. b. For PTX ISA version 1.f32 div.f32 supported on all target architectures. div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . d = a / b.rz. // // // // fast.rm.{rz. div. approximate single-precision divides: div.approx{.0 Table 54. Examples 90 January 24. a.full. z. one of . approximate division by zero creates a value of infinity (with same sign as a). the maximum ulp error is 2. The maximum ulp error is 2 across the full range of inputs. subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. div.ftz.f32 div.full.f32 and div. b. div. . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . div.0.PTX ISA Version 2. yd.f32 implements a fast approximation to divide.rnd{.ftz. Fast. .14159. a.rn.rp }. sm_1x: div. d. div Syntax Floating-Point Instructions: div Divide one value by another.ftz}. but is not fully IEEE 754 compliant and does not support rounding modifiers.rnd = { .circum.rm mantissa LSB rounds towards negative infinity .f32 div.full. full-range approximation that scales operands to achieve better accuracy. div.ftz.f64 d.full.f64. and div.full{.f64 supports subnormal numbers.ftz. div.rn. Subnormal inputs and results are flushed to sign-preserving zero. 2126]. xd.f64 diam.rp}. .

Subnormal numbers: sm_20: By default. abs. Subnormal numbers: sm_20: By default. abs. d. sm_1x: abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Negate the sign of a and store the result in d. Take the absolute value of a and store the result in d. Table 56.f32 supported on all target architectures. neg{.f32 abs. neg. sm_1x: neg.0. a. January 24.ftz. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 supported on all target architectures.Chapter 8.f32 neg.f64 requires sm_13 or later.0. abs.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. abs. abs. NaN inputs yield an unspecified NaN. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 supports subnormal numbers. subnormal numbers are supported. 2010 91 . a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. neg.f64 d.f64 requires sm_13 or later.f64 supports subnormal numbers. neg.f0.f32 flushes subnormal inputs and results to sign-preserving zero. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f32 flushes subnormal inputs and results to sign-preserving zero.f32 x. a. abs{.ftz}.ftz}. NaN inputs yield an unspecified NaN. a. d = |a|. Instruction Set Table 55.ftz.f32 x. neg. d = -a.f64 d. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. d.f0. subnormal numbers are supported.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.

Store the minimum of a and b in d. max.ftz. min.f2. b.b.f64 d. max. a.f32 flushes subnormal inputs and results to sign-preserving zero.c. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 d. b. max.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. b.0.f32 min.f32 flushes subnormal inputs and results to sign-preserving zero. min. a.f32 max.f64 requires sm_13 or later. (a < b) ? a : b. b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. (a > b) ? a : b. b.ftz}. @p min. subnormal numbers are supported.f64 z. b. min{.f64 requires sm_13 or later. Store the maximum of a and b in d. d.z. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. min.b.f32 supported on all target architectures.PTX ISA Version 2.x.f32 supported on all target architectures. sm_1x: max. a. d d d d = = = = NaN. max. Table 58. d. 92 January 24. subnormal numbers are supported. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f1. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero.f32 min.ftz. a.ftz. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. d d d d = = = = NaN.f64 f0.f64 supports subnormal numbers. min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. max. max{.f64 supports subnormal numbers.0 Table 57. a.c. a. sm_1x: min. a.ftz.0.f32 max.

f32 flushes subnormal inputs and results to sign-preserving zero.3. xi. xi.f64 supports subnormal numbers.rz mantissa LSB rounds towards zero .f64.0.rm mantissa LSB rounds towards negative infinity .ftz. 2010 93 . // fast. rcp.f32 and rcp.0. d. . rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . rcp.0 +0.f32 rcp.rp }.0 +subnormal +Inf NaN Result -0.approx. Description Semantics Notes Compute 1/a. a.f32. store result in d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz.f32 requires sm_20 or later.approx or .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .approx{.f32 rcp.4.rnd{.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f32 rcp.Chapter 8. a.f64 introduced in PTX ISA version 1.f32 defaults to rcp.rn. rcp. rcp. For PTX ISA versions 1.f64 requires sm_20 or later.rp}.f64 ri.rnd = { .0 through 1.x. .rz.0.0 over the range 1.rnd.f32 implements a fast approximation to reciprocal.f64 defaults to rcp. Examples January 24.0-2. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. . one of . The maximum absolute error is 2-23. rcp.{rz.rn mantissa LSB rounds to nearest even . Input -Inf -subnormal -0. For PTX ISA version 1. PTX ISA Notes rcp. Instruction Set Table 59.f64 and explicit modifiers . a. rcp. d. General rounding modifiers were added in PTX ISA version 2.r.rm.ftz}.f64 d. rcp.rn.rnd. d = 1 / a.approx and .rn.f32 supported on all target architectures.f32 rcp.ftz}.ftz were introduced in PTX ISA version 1.approx.4 and later. rcp.approx. rcp.rn. and rcp.rnd is required.rn. sm_1x: rcp.f64 requires sm_13 or later. Target ISA Notes rcp.approx.rm.rn. subnormal numbers are supported.ftz.x.0 -Inf -Inf +Inf +Inf +0.

f32 flushes subnormal inputs and results to sign-preserving zero. a.ftz}.rnd = { .f32 defaults to sqrt.f64 introduced in PTX ISA version 1.rn.f64 r.rn.0 -0.x. Examples 94 January 24.f32 sqrt. sqrt. General rounding modifiers were added in PTX ISA version 2. sqrt. sqrt.x.4.0 +0.rp }.0 +0. sm_1x: sqrt.3.f32 and sqrt.approx. a.x. 2010 .approx.0 through 1.f32 implements a fast approximation to square root.f64 requires sm_20 or later. sqrt. Description Semantics Notes Compute sqrt(a). sqrt. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. Target ISA Notes sqrt.PTX ISA Version 2. approximate square root d.approx. .approx{. PTX ISA Notes sqrt. d = sqrt(a).rnd.rn.rm mantissa LSB rounds towards negative infinity . store in d.0.ftz}. // IEEE 754 compliant rounding .f64 d.f32 is TBD. r.ftz.f32 sqrt.4 and later.f32 requires sm_20 or later.0 Table 60.rm.0 +0.rnd is required.0. sqrt. Input -Inf -normal -subnormal -0.approx.rn. The maximum absolute error for sqrt. sqrt. . sqrt.approx or .0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . For PTX ISA version 1. // fast.f64 requires sm_13 or later.f64 and explicit modifiers .ftz were introduced in PTX ISA version 1.f64 supports subnormal numbers.f32. // IEEE 754 compliant rounding d.ftz.ftz. sqrt.rp}.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . For PTX ISA versions 1.f32 supported on all target architectures.f64.rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero.rm.rn mantissa LSB rounds to nearest even . r.rnd. a. sqrt.rnd{. one of .approx. subnormal numbers are supported.f32 sqrt.{rz.f32 sqrt.rz.f64 defaults to sqrt.rn.0 +subnormal +Inf NaN Result NaN NaN -0.ftz. and sqrt.approx and .rn.

Note that rsqrt. Compute 1/sqrt(a). rsqrt.3.f64 supports subnormal numbers.approx.0. x.0 +0. rsqrt. rsqrt.0.ftz.f32 supported on all target architectures.f64 were introduced in PTX ISA version 1.f32 and rsqrt.0 NaN The maximum absolute error for rsqrt.approx. X. rsqrt. Explicit modifiers . January 24. a.f32 is 2-22. d.approx. store the result in d.f32 defaults to rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.0-4. rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f64 d. d = 1/sqrt(a).f32. the . 2010 95 . ISR.f64 requires sm_13 or later.ftz}.ftz. Input -Inf -normal -subnormal -0.4.4 and later.f64 defaults to rsqrt.f32 rsqrt. rsqrt.f64 is TBD.ftz.approx modifier is required. sm_1x: rsqrt.0 through 1. subnormal numbers are supported. Subnormal numbers: sm_20: By default.f32 rsqrt.f64.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. For PTX ISA versions 1.approx and . Target ISA Notes Examples rsqrt.approx implements an approximation to the reciprocal square root. For PTX ISA version 1. PTX ISA Notes rsqrt. a.f64 is emulated in software and are relatively slow. rsqrt. and rsqrt.approx.approx.f64 isr.approx{.Chapter 8.4 over the range 1.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 61. The maximum absolute error for rsqrt.ftz were introduced in PTX ISA version 1.approx.

0 +0.ftz.ftz}. 96 January 24.0. Target ISA Notes Examples Supported on all target architectures.approx. sin. sin.approx{. sin. d = sin(a). Input -Inf -subnormal -0.4.ftz introduced in PTX ISA version 1. a. subnormal numbers are supported. Subnormal numbers: sm_20: By default. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. sin. Explicit modifiers .9 in quadrant 00.f32.0 through 1. For PTX ISA version 1.f32 d.approx.f32 flushes subnormal inputs and results to sign-preserving zero.f32 sa.ftz.ftz. Find the sine of the angle a (in radians).0 NaN NaN The maximum absolute error is 2-20. For PTX ISA versions 1.0 +0.0 +subnormal +Inf NaN Result NaN -0.approx modifier is required. 2010 .f32 introduced in PTX ISA version 1.0 Table 62.4 and later.approx.PTX ISA Version 2. sin.3.approx and .f32 defaults to sin.f32 implements a fast approximation to sine.0 -0. PTX ISA Notes sin.0 +0. a. the . sm_1x: Subnormal inputs and results to sign-preserving zero.

sm_1x: Subnormal inputs and results to sign-preserving zero.0. cos.0 +1.ftz.0 through 1.0 NaN NaN The maximum absolute error is 2-20. cos.approx.Chapter 8.f32. Subnormal numbers: sm_20: By default.9 in quadrant 00.approx{.4.0 +1.3. PTX ISA Notes cos.ftz}. a. January 24.approx. d = cos(a). cos.0 +0. Input -Inf -subnormal -0. For PTX ISA versions 1.approx.ftz. Find the cosine of the angle a (in radians).f32 introduced in PTX ISA version 1.f32 d.ftz introduced in PTX ISA version 1. cos. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.approx and .4 and later.approx modifier is required.0 +1.f32 defaults to cos. a.ftz.0 +subnormal +Inf NaN Result NaN +1.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 63. 2010 97 . the . For PTX ISA version 1. Target ISA Notes Examples Supported on all target architectures. Explicit modifiers .f32 ca. subnormal numbers are supported.f32 implements a fast approximation to cosine. cos.

lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.f32 flushes subnormal inputs and results to sign-preserving zero. lg2. the . subnormal numbers are supported.0. d = log(a) / log(2).0 Table 64.f32 la.0 +0.f32 introduced in PTX ISA version 1. Explicit modifiers . Input -Inf -subnormal -0. lg2. Subnormal numbers: sm_20: By default. a.ftz.3.approx and .ftz}.ftz. lg2.approx.ftz.approx{.approx modifier is required. PTX ISA Notes lg2. For PTX ISA version 1. lg2.0 through 1.6 for mantissa. a. sm_1x: Subnormal inputs and results to sign-preserving zero. lg2.f32 Determine the log2 of a. The maximum absolute error is 2-22. For PTX ISA versions 1.ftz introduced in PTX ISA version 1.f32 defaults to lg2.approx.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. 98 January 24.PTX ISA Version 2. 2010 .4.approx. Target ISA Notes Examples Supported on all target architectures.4 and later.f32 implements a fast approximation to log2(a).f32.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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ge.s32. then these comparisons have the same result as their ordered counterparts.b32. ne. setp. le. lo.f32 comparisons. The signed and unsigned comparison operators are eq. Subnormal numbers: sm_20: By default.and. a. sm_1x: setp. p.ftz. gt. xor. ls. hi. If either operand is NaN. gt.B) is one of: and.eq. ge. unordered versions are included: equ. . ls.b64.ftz}.f32 flushes subnormal inputs to sign-preserving zero. gt. The comparison operator is a suffix on the instruction. then the result of these comparisons is true. ltu. Semantics t = (a CmpOp b) ? 1 : 0.0.CmpOp{. the comparison operators lo.pred variables. setp. gtu.ftz}. p[|q]. For unsigned values. and hs for lower.u16. b.f64 source type requires sm_13 or later. higher. . ge. ltu.BoolOp{. or. setp.n. If either operand is NaN. Applies to all numeric types.b16. lt. and (optionally) combine this result with a predicate value by applying a Boolean operator.u32 p|q. This result is written to the first destination operand. c).f32 flushes subnormal inputs to sign-preserving zero. c). If both operands are numeric values (not NaN). loweror-same. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. ge. respectively. leu. .f32. leu.f64 supports subnormal numbers.s16.u32. 102 January 24. and can be one of: eq. . 2010 .dtype.s64. .CmpOp. ne. The untyped. The destinations p and q must be . A related value computed using the complement of the compare result is written to the second destination operand. . p[|q]. lt.type = { . num.dtype.f64 }. ne. hs equ. . q = BoolOp(!t.type setp.s32 setp. b.0 Table 67. Integer Notes Floating Point Notes The ordered comparisons are eq. hi. gt.dtype. le. subnormal numbers are supported.u64. To aid comparison operations in the presence of NaN values. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and higher-or-same may be used instead of lt.PTX ISA Version 2. @q setp. geu.b. lt. neu. neu. . geu. p = BoolOp(t. gtu.r. .lt.ftz applies only to .a. num returns true if both operands are numeric values (not NaN). bit-size comparisons are eq and ne. a. le.i. the result is false. nan The Boolean operator BoolOp(A. setp with . . Modifier . {!}c. and nan returns true if either operand is NaN. le.type .

negative zero equals zero.ftz}. slct. based on the sign of the third operand. the comparison is unordered and operand b is selected. . If c ≥ 0.s32 x. .b16.s64. Operands d. and b are treated as a bitsize type of the same width as the first instruction type. selp.f64 }. based on the value of the predicate source operand. Operand c is a predicate. sm_1x: slct. .f32.x. a.dtype.u16. fval. c. c. f0. slct. The selected input is copied to the output without modification.b16.b64.f64 requires sm_13 or later.dtype. Modifier . selp Syntax Comparison and Selection Instructions: selp Select between source operands.ftz applies only to . .s16. .ftz. b otherwise.u64. For .u64.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32 slct{. a is stored in d. d = (c == 1) ? a : b.b64. Subnormal numbers: sm_20: By default. slct Syntax Comparison and Selection Instructions: slct Select one source operand. B. b.u32. d = (c >= 0) ? a : b. a is stored in d. .u64.u32.dtype.u16.s16. y. .f32 comparisons. b. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. Semantics Floating Point Notes January 24. a. . . .ftz. If operand c is NaN.0.f32 d. Operands d. Description Conditional selection.b32.f32 flushes subnormal values of operand c to sign-preserving zero.f32 flushes subnormal values of operand c to sign-preserving zero. .Chapter 8.s32. . d.f32 A. .f32 r0. a. . otherwise b is stored in d. and b must be of the same type. . selp. Instruction Set Table 68. z. slct.xp. slct.s32 selp. and operand a is selected.dtype = { .f64 }.s32.t. . b. @q selp.dtype. a. and operand a is selected. .f32.type d. C. 2010 103 . subnormal numbers are supported. Table 69.f32 comparisons.s64. .g. a. .r.f64 requires sm_13 or later. . Introduced in PTX ISA version 1. .u32. val. operand c must match the second instruction type.0.p. c. If c is True.b32. . slct.

2010 . Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. Instructions and.PTX ISA Version 2. performing bit-wise operations on operands of any type. and not also operate on predicates. or. xor.4.0 8. This permits bit-wise operations on floating point values without having to define a union to access the bits. provided the operands are of the same size.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.

b16. .0. . . Allowed types include predicate registers. Supported on all target architectures.b32 x.pred.Chapter 8.r.pred p.b32 and. and. or Syntax Logic and Shift Instructions: or Bitwise OR. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type = { . or.type = { .0x80000000. d = a | b. a. or.type d.b16. The size of the operands must match.q.q. b. . b. Supported on all target architectures.0x00010001 or.type d. sign. and Syntax Logic and Shift Instructions: and Bitwise AND.b64 }.r. but not necessarily the type. Introduced in PTX ISA version 1. 2010 105 .fpvalue.pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. Instruction Set Table 70. Allowed types include predicate registers. Introduced in PTX ISA version 1.b32. The size of the operands must match. January 24. Table 71. but not necessarily the type.b32 mask mask.b64 }. . d = a & b.b32. a. . and. .0.

b.a. . cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. d = (a==0) ? 1 : 0. a.0. . not.x. Introduced in PTX ISA version 1. .0 Table 72. d = a ^ b. Allowed types include predicate registers.PTX ISA Version 2. .pred. The size of the operands must match.type = { . 106 January 24. but not necessarily the type.type d. d = ~a. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b32 d. xor.pred.pred p. not.type d. Allowed types include predicates.r.0. Supported on all target architectures.b32 mask.type d.b32. .b16.b16.mask. Supported on all target architectures. Table 74. Introduced in PTX ISA version 1. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).type = { . The size of the operands must match. cnot. .b64 }. 2010 . d.b32.q. a. .0. Introduced in PTX ISA version 1. Supported on all target architectures. not. but not necessarily the type. one’s complement.type = { . but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. xor. .b64 }. a. .b64 }.b32 xor. The size of the operands must match.b16 d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b16. cnot.0x0001.b32. not Syntax Logic and Shift Instructions: not Bitwise negation.q. . Table 73.

sign or zero fill on left. regardless of the instruction type. a.Chapter 8.j. unsigned and untyped shifts fill with 0.b32. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. b. but not necessarily the type.b64.b64 }.s32 shr. . Signed shifts fill with the sign bit. i.b32 q. shl Syntax Logic and Shift Instructions: shl Shift bits left. Supported on all target architectures.u32. shr Syntax Logic and Shift Instructions: shr Shift bits right. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.1. Supported on all target architectures. shl. Introduced in PTX ISA version 1. The sizes of the destination and first source operand must match. shr.2. .u16.i.s64 }. .2. a. Bit-size types are included for symmetry with SHL. zero-fill on right. The sizes of the destination and first source operand must match.i.type d. Shift amounts greater than the register width N are clamped to N. d = a >> b. but not necessarily the type. regardless of the instruction type. PTX ISA Notes Target ISA Notes Examples January 24. . The b operand must be a 32-bit value.type = { .b16 c.type d.u64. d = a << b.0. Introduced in PTX ISA version 1. .a. The b operand must be a 32-bit value. Instruction Set Table 75. Shift amounts greater than the register width N are clamped to N.s16. b. shl. . . .b16. .b32. . .0.type = { .b16. PTX ISA Notes Target ISA Notes Examples Table 76.a.s32.u16 shr. shr. k. . 2010 107 .

The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.7. mov. and sust support optional cache operations. or shared state spaces. Data Movement and Conversion Instructions These instructions copy data from place to place. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. possibly converting it from one format to another. st. and from state space to state space. ld. local.0 8. and st operate on both scalar and vector types. Instructions ld. ldu.PTX ISA Version 2. The cvta instruction converts addresses between generic and global. prefetchu isspacep cvta cvt 108 January 24. 2010 .5. suld.

but multiple L1 caches are not coherent for global data.cg Cache at global level (cache in L2 and below.lu instruction performs a load cached streaming operation (ld. the cache operators have the following definitions and behavior.cv to a frame buffer DRAM address is the same as ld. . 2010 109 . If one thread stores to global memory via one L1 cache. bypassing the L1 cache.cv Cache as volatile (consider cached system memory lines stale. if the line is fully covered.0 introduces optional cache operators on load and store instructions.ca.Chapter 8. Table 77. . fetch again).ca loads cached in L1. likely to be accessed again. and a second thread loads that address via a second L1 cache with ld. The cache operators require a target architecture of sm_20 or later. The ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. The ld. Global data is coherent at the L2 level. .ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. when applied to a local address. Use ld. For sm_20 and later.cs. As a result of this request.1. The ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.lu operation.5. invalidates (discards) the local L1 line following the load. it performs the ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. .cs is applied to a Local window address. not L1).cg to cache loads only globally. and cache only in the L2 cache. any existing cache lines that match the requested address in L1 will be evicted. The ld. likely to be accessed once. rather than the data stored by the first thread. Cache Operators PTX 2. Instruction Set 8. Operator . When ld. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. A ld.lu Last use.ca.7.cs Cache streaming. to allow the thread program to poll a SysMem location written by the CPU.cs) on global addresses. The compiler / programmer may use ld. The default load instruction cache operation is ld.lu load last use operation. January 24. evict-first. the second thread may get stale L1 cache data.

0 Table 78. . not L1).cg to local memory uses the L1 cache. and discard any L1 lines that match. the second thread may get a hit on stale L1 cache data. and a second thread in a different SM later loads from that address via a different L1 cache with ld. regardless of the cache operation.wb for global data. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. rather than get the data from L2 or memory stored by the first thread. and marks local L1 lines evict-first. The st. st. 110 January 24. Future GPUs may have globally-coherent L1 caches. However. If one thread stores to global memory.wt store write-through operation applied to a global System Memory address writes through the L2 cache. but st. bypassing the L1 cache. In sm_20. The st.wt Cache write-through (to system memory).cs Cache streaming.wt. 2010 .cg is the same as st.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. likely to be accessed once. .ca. The default store instruction cache operation is st. Use st. and cache only in the L2 cache. to allow a CPU program to poll a SysMem location written by the GPU with st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.wb. Global stores bypass L1. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.cg to cache global store data only globally.wb could write-back global store data from L1. Addresses not in System Memory use normal write-back. bypassing its L1 cache. in which case st. which writes back cache lines of coherent cache levels with normal eviction policy.PTX ISA Version 2. . Operator .ca loads.cg Cache at global level (cache in L2 and below.

f32 mov.type mov. .pred. k. Note that if the address of a device function parameter is moved to a register. 2010 111 . .type d.global. . mov.f32 mov.s64.u32. the parameter will be copied onto the stack and the address will be in the local state space.. Introduced in PTX ISA version 1.e. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. d = &avar.a. special register.u16. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.type mov. . label. or shared state space may be taken directly using the cvta instruction. within the variable’s declared state space Notes Although only predicate and bit-size types are required.f32. sreg.shared state spaces. addr.b64.u32 mov. Description . local. Instruction Set Table 79.u32 d. and . alternately. Semantics d = a. . . A. variable in an addressable memory space.b16.u16 mov. avar. d = &label.type = { .0.s16.Chapter 8. For variables declared in . myFunc. A[5]. . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. . Operand a may be a register.. the generic address of a variable declared in global. d = sreg. the address of the variable in its state space) into the destination register. mov.f64 requires sm_13 or later.f64 }. . or function name. // address is non-generic. or shared state space. Write register d with the value of a. // get address of variable // get address of label or function . local.s32. immediate. u. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. d.1. mov. ptr. i. mov places the non-generic address of the variable (i. local. The generic address of a variable in global.const.type mov.v.u32 mov.b32. d.local.e. d. . .u64. Take the non-generic address of a variable in global. label. a. .0. ptr.

a[8..b64 // pack two 32-bit elements into ..y.47]..x. lo.0 Table 80.y } = { a[0. Supported on all target architectures.. Description Write scalar register d with the packed value of vector register a. .x | (a. %r1.7].0. 2010 . or write vector register d with the unpacked values from scalar register a.y << 8) d = a.x. d.PTX ISA Version 2.w}.b16. a[8.w } = { a[0. {r.7].b.b64 112 January 24..b32 %r1.y << 16) | (a.y << 32) // pack two 8-bit elements into .x | (a.a}.b32 { d.b.b8 r.. d.b16 // pack four 8-bit elements into .z << 16) | (a.x. d. d.y } = { a[0.x. d.x | (a.x | (a.g.z. a.y.%r1..y } = { a[0. a[32. a[48.x.type d..b16 { d. . a[16..b64 mov.31] } // unpack 8-bit elements from .23].31].x | (a.type = { .y << 16) d = a.b32 // pack two 16-bit elements into . d.z...31] } // unpack 16-bit elements from .. mov.15] } // unpack 8-bit elements from . Both the overall size of the vector and the size of the scalar must match the size of the instruction type.b64 }.a have type .y.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. For bit-size types. d.z.hi are . d.b32 mov.15].15].b64 { d.y << 8) | (a.z.w have type .w } = { a[0.u8 // unpack 32-bit elements from .u32 x. Semantics d = a.b have type . // // // // a.b32.w << 48) d = a. a[16. mov.hi}.g. a[16.y.b64 { d.b32 { d. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack)..{x..w << 24) d = a.u16 %x is a double.15]. a[32. .63] } // unpack 16-bit elements from . %x. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.{a. a[24. d.b}.31].z << 32) | (a. {lo.b32 // pack four 16-bit elements into .b32 mov.

.local. and then converted to .ss}{.e.u32. . If no state space is given.f32.0. an address maps to global memory unless it falls within the local memory window or the shared memory window. . perform the load using generic addressing. . . . .type d.volatile introduced in PTX ISA version 1.0. . If an address is not properly aligned.cs. . Semantics d d d d = = = = a.const space suffix may have an optional bank number to indicate constant banks other than bank zero.cg. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and is zeroextended to the destination register width for unsigned and bit-size types. d. The value loaded is sign-extended to the destination register width for signed integers.ss = { . to enforce sequential consistency between threads accessing shared memory.e. 2010 113 . . .b16.shared spaces to inhibit optimization of references to volatile memory. A destination register wider than the specified type may be used. . [a].f64 }. *a.s64.shared }. i. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. The address must be naturally aligned to a multiple of the access size. .Chapter 8.b32. Within these windows. or the instruction may fault. d. . an integer or bit-size type register reg containing a byte address.vec.type ld{. . or [immAddr] an immediate absolute byte address (unsigned.type .v2. .volatile. The address size may be either 32-bit or 64-bit. .volatile{. [a].f64 using cvt. [a]. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.cop}. and truncated if the register width exceeds the state space address width for the target architecture.param.v4 }.volatile may be used with . *(immAddr).global. for example.s8. . Cache operations are not permitted with ld. an address maps to the corresponding location in local or shared memory. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [a].volatile{. ld.f16 data may be loaded using ld..b16. This may be used. ld{. Description Load register variable d from the location specified by the source address operand a in specified state space. Instruction Set Table 81. PTX ISA Notes January 24. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. .s16. d. Generic addressing may be used with ld. 32-bit).ca.type = { . ld.cv }.type ld.vec = { . Addresses are zero-extended to the specified width as needed.u8. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .f32 or . . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. ld introduced in PTX ISA version 1.ss}{.reg state space.u16.global and .lu. The . 32-bit).b8. .volatile.s32.1.ss}. In generic addressing. the resulting behavior is undefined.cop = { . *(a+immOff).const.u64.ss}. . Generic addressing and cache operations introduced in PTX ISA 2. i. .b64.cop}.vec. . .

[p+4].local.shared. // immediate address %r.b32 ld.PTX ISA Version 2. x.const.f32 ld. %r.s32 ld.f64 requires sm_13 or later. Q.const[4]. ld. // access incomplete array x.f16 d. 2010 .global.[a].[buffer+64].b16 cvt.global.b32 ld.b32 ld.local.b64 ld.[fs]. // load .%r.v4.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. d.0 Target ISA Notes ld.f32. Cache operations require sm_20 or later. Generic addressing requires sm_20 or later.[240]. // negative offset %r.[p+-8].[p].

[p]. In generic addressing. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Semantics d d d d = = = = a.global }. For ldu. If an address is not properly aligned. .vec = { .u16. d.global. A destination register wider than the specified type may be used. . ldu.v4. where the address is guaranteed to be the same across all threads in the warp.v2. . .s64.f32 or . The data at the specified address must be read-only. . an address maps to the corresponding location in local or shared memory.vec. i. . . ldu.[a]. ldu.f64 }. . *a.b64. The address must be naturally aligned to a multiple of the access size.Chapter 8.[p+4].f32 d.type d.u32.b16.b32 d.s16. Introduced in PTX ISA version 2. A register containing an address may be declared as a bit-size type or integer type. i.e. the resulting behavior is undefined. . *(immAddr). ldu{. or [immAddr] an immediate absolute byte address (unsigned. PTX ISA Notes Target ISA Notes Examples January 24.s8.e. or the instruction may fault.0. .ss}.u64. // load from address // vec load from address . .f64 using cvt. The addressable operand a is one of: [avar] the name of an addressable variable var. Within these windows. 32-bit).reg state space.f16 data may be loaded using ldu. and then converted to ..f32 Q.type = { . and is zeroextended to the destination register width for unsigned and bit-size types. Addresses are zero-extended to the specified width as needed. .f64 requires sm_13 or later. *(a+immOff). . ldu. // state space . only generic addresses that map to global memory are legal. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . [a]. .v4 }. The value loaded is sign-extended to the destination register width for signed integers. and truncated if the register width exceeds the state space address width for the target architecture. [areg] a register reg containing a byte address.b8. Instruction Set Table 82. [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window.global.ss = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32.b16. perform the load using generic addressing. If no state space is given. .ss}.s32. The address size may be either 32-bit or 64-bit.type ldu{. 32-bit). Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. .u8. 2010 115 . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f32.global.

.b64. .f16 data resulting from a cvt instruction may be stored using st.cop}.volatile{. Within these windows. i. 2010 .type .f32.u16. . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.cg. .volatile. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.local. . . the access may proceed by silently masking off low-order address bits to achieve proper rounding. The address size may be either 32-bit or 64-bit.ss}.v4 }.f64 }. st introduced in PTX ISA version 1.ss}{. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .volatile introduced in PTX ISA version 1.0 Table 83. If no state space is given.wb.volatile.type [a]. Generic addressing may be used with st. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. an integer or bit-size type register reg containing a byte address. . b. b.e. Generic addressing and cache operations introduced in PTX ISA 2.v2.b16. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s8. Cache operations require sm_20 or later. for example. an address maps to the corresponding location in local or shared memory. an address maps to global memory unless it falls within the local memory window or the shared memory window.ss . b. { . . st. .type st{. perform the store using generic addressing.cop}.wt }.u64. the resulting behavior is undefined. b. . .PTX ISA Version 2. Semantics d = a. { . Cache operations are not permitted with st. If an address is not properly aligned. and truncated if the register width exceeds the state space address width for the target architecture. [a].vec.vec.b8.type = = = = {.volatile{. A source register wider than the specified type may be used.ss}{.ss}. 32-bit). *(immAddr) = a. . . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.b32.e.s16.type st. *d = a. st. Generic addressing requires sm_20 or later. or [immAddr] an immediate absolute byte address (unsigned. or the instruction may fault. *(d+immOffset) = a.0.cop .u8. i. PTX ISA Notes Target ISA Notes 116 January 24. Addresses are zero-extended to the specified width as needed. 32-bit). . The address must be naturally aligned to a multiple of the access size.0. to enforce sequential consistency between threads accessing shared memory. .reg state space.b16.1.vec . . . The addressable operand a is one of: [var] [reg] the name of an addressable variable var.s64. st{. In generic addressing. .shared }. [a].cs. This may be used. st.u32.volatile may be used with . . [a].f64 requires sm_13 or later. . The lower n bits corresponding to the instruction-type width are stored to memory.s32. { .shared spaces to inhibit optimization of references to volatile memory.global.global and ..

local.a.Chapter 8.b32 st.b16 [a]. [q+-8].b32 st. [fs].%r. // immediate address %r.f32 st.f32 st.Q.a.global.s32 cvt. 2010 117 .s32 st. [q+4].local. // negative offset [100].local.f16. // %r is 32-bit register // store lower 16 bits January 24.%r.b. Instruction Set Examples st.r7. [p].global.v4.

. In generic addressing. and no operation occurs if the address maps to a local or shared memory location. A prefetch into the uniform cache requires a generic address. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L1 [ptr]. the prefetch uses generic addressing.L2 }. an address maps to global memory unless it falls within the local memory window or the shared memory window.L1 [a]. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. prefetch{. 32-bit). in specified state space. an address maps to the corresponding location in local or shared memory.0 Table 84. or [immAddr] an immediate absolute byte address (unsigned. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.space}. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level.global. // prefetch to data cache // prefetch to uniform cache . Addresses are zero-extended to the specified width as needed. prefetchu. a register reg containing a byte address.0.PTX ISA Version 2.space = { . The address size may be either 32-bit or 64-bit. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. .global.L1 [addr].level prefetchu.local }. and truncated if the register width exceeds the state space address width for the target architecture. i.e. 32-bit). Within these windows. A prefetch to a shared memory location performs no operation.level = { . 118 January 24. 2010 . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. If no state space is given. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetch and prefetchu require sm_20 or later.L1. prefetch. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [a].

size p. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.global. p.shared. Description Convert a global. January 24.pred.u32 or .global isspacep. Take the generic address of a variable declared in global. PTX ISA Notes Target ISA Notes Examples Table 86.local. a.u64 }.shared isglbl. or shared state space. local.Chapter 8.0.space.space = { .local. cvta.u32 p.0. islcl. // result is .u32 gptr. . gptr.space. . For variables declared in global. // local. cvta. p. isspacep. cvta.global. When converting a generic address into a global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . cvta requires sm_20 or later. isspacep requires sm_20 or later. or shared address.u32. the generic address of the variable may be taken using cvta.local.shared }. // convert to generic address // get generic address of var // convert generic address to global.space p.u32 p. . The source and destination addresses must be the same size. lptr. a. A program may use isspacep to guard against such incorrect behavior.size cvta.local isspacep. or shared state space.u64 or cvt. . local. local. Introduced in PTX ISA version 2. or shared address to a generic address. // get generic address of svar cvta. a.u64. The destination register must be of type . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.size = { . isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.to. Instruction Set Table 85.genptr.u64. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.lptr.space = { . The source address operand must be a register of type .u32 to truncate or zero-extend addresses.space. 2010 119 .u32. or shared state space to generic. sptr.to. or vice-versa.global. local. isshrd. Use cvt.size . or vice-versa. .shared }. var.pred . or shared address cvta. isspacep. svar. local.

. i. . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32 float-to-integer conversions and cvt.rzi.f32.ftz modifier may be specified in these cases for clarity. cvt{. Integer rounding modifiers: .PTX ISA Version 2.f64 }. the result is clamped to the destination range by default.s64.ftz. . subnormal inputs are flushed to signpreserving zero. sm_1x: For cvt. and for same-size float-tofloat conversions where the value is rounded to an integer.rmi round to nearest integer in direction of negative infinity . d..e.irnd = { .rni. . a.s32.atype = { . // integer rounding // fp rounding .dtype = .rp }. . Integer rounding is illegal in all other instances.u32.sat limits the result to MININT. subnormal inputs are flushed to signpreserving zero.u16.rni round to nearest integer. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.ftz}{.rz.. . . .e.f16. The optional .ftz. The compiler will preserve this behavior for legacy PTX code.sat}. .sat modifier is illegal in cases where saturation is not possible based on the source and destination types.atype d.ftz. .MAXINT for the size of the operation. Saturation modifier: . .dtype. the .4 and earlier.sat}. subnormal numbers are supported. choosing even integer if source is equidistant between two integers.sat For integer destination types. . . a.ftz}{.ftz. .s8.f32. .dtype. i. .u64.atype cvt{. Note: In PTX ISA versions 1.f32 float-to-integer conversions and cvt.f32.rmi. .irnd}{.dtype.0 Table 87.frnd}{.f32 float-tofloat conversions with integer rounding. Note that saturation applies to both signed and unsigned integer types. . . Description Semantics Integer Notes Convert between different types and sizes. . 120 January 24. .rm. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.sat is redundant.dtype.s16. For float-to-integer conversions.frnd = { . For cvt.rn.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.f32 float-tofloat conversions with integer rounding. 2010 .rzi round to nearest integer in the direction of zero .u8. d = convert(a).rpi }. Integer rounding is required for float-to-integer conversions.

rz mantissa LSB rounds towards zero . Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.0.Chapter 8.f16.s32 f. cvt.rn mantissa LSB rounds to nearest even .0.f64 requires sm_13 or later.f32.f32.i.0].r.f16. and cvt.f32 x. Specifically.rm mantissa LSB rounds towards negative infinity . // float-to-int saturates by default cvt. Subnormal numbers: sm_20: By default.f64 types. The result is an integral value. Applies to . NaN results are flushed to positive zero. subnormal numbers are supported.f32.y. stored in floating-point format. Introduced in PTX ISA version 1.4 or earlier.f32 instructions. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f32. if the PTX .version is 1.s32. Note: In PTX ISA versions 1. and . cvt to or from .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).y. The compiler will preserve this behavior for legacy PTX code. Floating-point rounding modifiers: . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. . and for integer-to-float conversions. 1.ftz behavior for sm_1x targets January 24.f32.f16.f32.sat For floating-point destination types. The operands must be of the same size.sat limits the result to the range [0. Floating-point rounding is illegal in all other instances. // round to nearest int. result is fp cvt. // note .4 and earlier.ftz modifier may be specified in these cases for clarity.f64 j. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. The optional . cvt. . cvt.f32 x.f32. Saturation modifier: .rni. Modifier . 2010 121 .f64.

f32. Ability to query fields within texture.texref tex1 ) { txq. r5.samplerref tsamp1 = { addr_mode_0 filter_mode }. and surface descriptors.f32 r3. and surface descriptors: • • • Static initialization of texture.f32. [tex1]. Texture and Surface Instructions This section describes PTX instructions for accessing textures. } = clamp_to_border. sampler.f32 r1. texture and sampler information each have their own handle.7.v4. [tex1. r2. The advantage of unified mode is that it allows 128 samplers.global . add.width. sampler.2d.u32 r5. allowing them to be defined separately and combined at the site of usage in the program. [tex1]. . r1. sampler. Texturing modes For working with textures and samplers.r3. div. A PTX module may declare only one texturing mode.f32 r1.f2}]. r3. PTX supports the following operations on texture.f32 {r1. cvt. add. and surface descriptors.height. Example: calculate an element’s power contribution as element’s power/total number of elements. samplers. 2010 .b32 r5. the file is assumed to use unified mode.param .target options ‘texmode_unified’ and ‘texmode_independent’.r2. r5.texref handle. 122 January 24.6.f32 r1. with the restriction that they correspond 1-to-1 with the 128 possible textures. add.u32 r5.0 8. r1. r5.PTX ISA Version 2. The advantage of independent mode is that textures and samplers can be mixed and matched.entry compute_power ( . r3.r4}.target texmode_independent .. . and surface descriptors. If no texturing mode is declared. = nearest width height tsamp1. texture and sampler information is accessed through a single . // get tex1’s txq. r1. In the independent mode. . r4. mul.b32 r6. The texturing mode is selected using . r6. In the unified mode. but the number of samplers is greatly restricted to 16. PTX has two modes of operation. // get tex1’s tex. sampler.. Module-scope and per-entry scope definitions of texture. {f1. and surfaces.

btype tex.btype d. d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. {f1}].f32 {r1. Description Texture lookup using a texture coordinate vector.dtype.2d.geom = { . the square brackets are not required and .s32. If an address is not properly aligned. .r2.geom.f32 }. {f1.dtype = { . The instruction always returns a four-element vector of 32-bit values.1d.r2.r4}. . 2010 123 . the sampler behavior is a property of the named texture. .geom. // Example of independent mode texturing tex.3d.f3. [a.u32. the resulting behavior is undefined. . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.btype = { . [a. //Example of unified mode texturing tex.dtype.s32.s32 {r1. b. Unified mode texturing introduced in PTX ISA version 1. is a two-element vector for 2d textures.1d.r3. . . PTX ISA Notes Target ISA Notes Examples January 24. If no sampler is specified. [tex_a.r3.0.f32 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding..v4.r4}.v4. i. and is a four-element vector for 3d textures. sampler_x.f4}]. A texture base address is assumed to be aligned to a 16-byte address. or the instruction may fault. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.e.3d }. [tex_a. Supported on all target architectures.v4.s32. c]. // explicit sampler . . Instruction Set These instructions provide access to texture and surface memory.v4. c]. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. tex txq suld sust sured suq Table 88. Notes For compatibility with prior versions of PTX.5. An optional texture sampler b may be specified.v4 coordinate vectors are allowed for any geometry.Chapter 8. Operand c is a scalar or singleton tuple for 1d textures. tex. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. where the fourth element is ignored.f2. with the extra elements being ignored.s32.

addr_mode_0.width . txq.height . Description Query an attribute of a texture or sampler. [smpl_B]. Query: .filter_mode . In unified mode.squery.b32 %r1.addr_mode_0. [tex_A]. Operand a is a . [a]. [a]. 2010 . clamp_to_edge.0 Table 89.width. Integer from enum { nearest.tquery. sampler attributes are also accessed via a texref argument.b32 %r1.width. [tex_A].filter_mode.squery = { .normalized_coords }.5. addr_mode_2 }.texref or . txq. .addr_mode_2 Returns: value in elements 1 (true) or 0 (false).addr_mode_1 . // unified mode // independent mode 124 January 24. // texture attributes // sampler attributes . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.b32 %r1.b32 txq.b32 d. addr_mode_1.normalized_coords . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . linear } Integer from enum { wrap. txq.height.tquery = { . clamp_ogl.depth. and in independent mode sampler attributes are accessed via a separate samplerref argument.addr_mode_0 . Supported on all target architectures. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.PTX ISA Version 2. . mirror. txq. d. . .depth .filter_mode.samplerref variable.

Operand b is a scalar or singleton tuple for 1d surfaces. .y.. suld. and cache operations introduced in PTX ISA version 2.5. .3d. B. If an address is not properly aligned.v4.cg. // for suld.v4 }. suld.ca. and the size of the data transfer matches the size of destination operand d. The lowest dimension coordinate represents a sample offset rather than a byte offset.b32.cop}. suld. Operand a is a .f2.trap.1d.p is currently unimplemented. suld. {f1. then . Destination vector elements corresponding to components that do not appear in the surface format are not written. suld Syntax Texture and Surface Instructions: suld Load from surface memory.vec. suld. . [surf_A. .b32.clamp suld. . or FLOAT data.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.cv }. SNORM.b supported on all target architectures. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. then .p . the surface sample elements are converted to . [surf_B.f32 }.s32. .dtype. .u32.p.dtype .w}].geom{.f32.3d }.vec . . .trap clamping modifier. // unformatted d.f3.b16. A surface base address is assumed to be aligned to a 16-byte address. . i.v4. if the surface format contains SINT data.trap suld. [a. where the fourth element is ignored.s32.z.b.f32. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. [a.b8 .f32 is returned. If the destination base type is . size and type conversion is performed as needed to convert from the surface sample format to the destination type.clamp . sm_1x targets support only the .trap introduced in PTX ISA version 1.surfref variable. Cache operations require sm_20 or later. suld.p. .dtype .trap {r1.f32 based on the surface format as follows: If the surface format contains UNORM.b. b]. suld. Target ISA Notes Examples January 24.b64 }.f4}.geom .3d requires sm_20 or later.b64. additional clamp modifiers. the resulting behavior is undefined.2d.r2}. G. or the instruction may fault.clamp.0.v2.zero }. . // formatted . .dtype. the access may proceed by silently masking off low-order address bits to achieve proper rounding.p. 2010 125 . or .clamp .clamp = = = = = = { { { { { { d. . The .Chapter 8. suld. .s32.b32.u32. If the destination type is .s32.cop}.clamp field specifies how to handle out-of-bounds addresses: .b. // cache operation none. .cop .1d. {x. .cs.p requires sm_20 or later.b performs an unformatted load of binary data. if the surface format contains UINT data. and is a four-element vector for 3d surfaces.trap . is a two-element vector for 2d surfaces.v2. Coordinate elements are of type . // for suld. {x}].b .s32 is returned. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. or .u32. Description Load from surface memory using a surface coordinate vector. Instruction Set Table 90.geom{. b].u32 is returned.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. suld. . then .e. and A components of the surface format.

s32.p performs a formatted store of a vector of 32-bit data values to a surface sample. // for sust.clamp .b.b.trap .s32. .b // for sust.3d requires sm_20 or later. .PTX ISA Version 2.p. if the surface format contains SINT data. none.f32.v4 }. [a. B. sust.p. .v2.5.v2.wt }. where the fourth element is ignored.b64 }. [surf_B. Cache operations require sm_20 or later. c. If the source type is .f4}.f32 is assumed.f2.cop .u32.f32 }. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.vec . and cache operations introduced in PTX ISA version 2.f32.vec.clamp. SNORM. The source data is then converted from this type to the surface sample format. sust Syntax Texture and Surface Instructions: sust Store to surface memory. {x}]. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. is a two-element vector for 2d surfaces. additional clamp modifiers. .surfref variable.wb. The size of the data transfer matches the size of source operand c. then . Operand b is a scalar or singleton tuple for 1d surfaces.f32} are currently unimplemented. {f1. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.clamp field specifies how to handle out-of-bounds addresses: .clamp = = = = = = { { { { { { [a. and A surface components.ctype . {x. or .r2}.vec.cop}. . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. sust.geom{.ctype . . . c.b16.b32.s32. Surface sample components that do not occur in the source vector will be written with an unpredictable value. sust. sm_1x targets support only the . 2010 .b. If an address is not properly aligned.w}]. the access may proceed by silently masking off low-order address bits to achieve proper rounding. Source elements that do not occur in the surface sample are ignored. . .trap clamping modifier.ctype.trap [surf_A.2d.1d. . .p Description Store to surface memory using a surface coordinate vector. and is a four-element vector for 3d surfaces.b32.0 Table 91. . The lowest dimension coordinate represents a sample offset rather than a byte offset. Operand a is a .s32 is assumed.trap introduced in PTX ISA version 1.. The . b].3d.trap. If the source base type is . b].geom . or the instruction may fault. A surface base address is assumed to be aligned to a 16-byte address. . The source vector elements are interpreted left-to-right as R.geom{. then . then . sust.clamp .clamp sust. sust. These elements are written to the corresponding surface sample components.cop}. size and type conversions are performed as needed between the surface sample format and the destination type. . sust.f3.u32. . {r1. .ctype. sust.0.s32.b64.u32 is assumed. .1d.b supported on all target architectures. .zero }.y.cg.e.trap sust. sust.cs.b8 .b32. Target ISA Notes Examples 126 January 24. or FLOAT data. G.p requires sm_20 or later. if the surface format contains UINT data.b performs an unformatted store of binary data. the resulting behavior is undefined.p. .{u32. // unformatted // formatted .p. . sust. i.z.v4. Coordinate elements are of type .3d }.

u32 based on the surface sample format as follows: if the surface format contains UINT data. Coordinate elements are of type . .b32.u64 data.b32.s32 or .s32. . .op. .clamp. A surface base address is assumed to be aligned to a 16-byte address. .geom = { .b32. .0.b32 }. [surf_B. Reduction to surface memory using a surface coordinate vector.b32 }. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b]. sured requires sm_20 or later. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. Operand b is a scalar or singleton tuple for 1d surfaces. then . Instruction Set Table 92. // for sured.u64. // sample addressing . January 24.b. and . or .trap [surf_A. sured. sured. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.ctype.u32.trap.clamp field specifies how to handle out-of-bounds addresses: .y}].u32 is assumed.surfref variable.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.min.max.c. .p performs a reduction on sample-addressed 32-bit data. where the fourth element is ignored.trap .b. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.u64. 2010 127 .1d.2d.p. .clamp = { . // for sured. The . the resulting behavior is undefined. . . and is a four-element vector for 3d surfaces. operations and and or apply to .and. or the instruction may fault.p.b .s32 types. sured. .ctype = { .zero }. r1.u32. and the data is interpreted as . then . Operations add applies to .s32..ctype = { .s32 types.c.geom. if the surface format contains SINT data.clamp .e. .add. If an address is not properly aligned.b].geom.op = { . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . min and max apply to .clamp [a.u32. is a two-element vector for 2d surfaces.2d.1d. The instruction type is restricted to .u32 and .or }.b performs an unformatted reduction on . . Operand a is a .trap sured. r1. .u32.p . sured.3d }. {x.min.op. {x}]. // byte addressing sured.b32 type.Chapter 8.ctype.s32.add. The lowest dimension coordinate represents a sample offset rather than a byte offset. i.clamp [a.s32 is assumed.

width.PTX ISA Version 2.height . Supported on all target architectures. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.surfref variable.b32 %r1. 128 January 24. Query: . [surf_A].depth }. suq.0 Table 93. .width.height.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Description Query an attribute of a surface.b32 d.5. . Operand a is a . [a].query. 2010 . .width . suq.query = { .

b. } PTX ISA Notes Target ISA Notes Examples Table 95. p.a. If {!}p then instruction Introduced in PTX ISA version 1. Threads with a false guard predicate do nothing. @{!}p instruction. { instructionList } The curly braces create a group of instructions.Chapter 8. used primarily for defining a function body.x.s32 a.y.s32 d.7. ratio. { add.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.7. Instruction Set 8. Introduced in PTX ISA version 1. {} Syntax Description Control Flow Instructions: { } Instruction grouping. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.c.0. Execute an instruction or instruction block for threads that have the guard predicate true. setp.f32 @!p div. mov. Supported on all target architectures. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. 2010 129 . Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.0.0. Supported on all target architectures.f32 @q bra L23.eq.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Chapter 8.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. bar.popc is the number of threads with a true predicate.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Thus. all-threads-true (.u32 bar. Only bar. a{. thread count.red should not be intermixed with bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.red are population-count (.red also guarantee memory ordering among threads identical to membar. Operand b specifies the number of threads participating in the barrier. bar. If no thread count is specified. Operands a. Register operands. b. PTX ISA Notes Target ISA Notes Examples bar. and bar.u32.or }. The barrier instructions signal the arrival of the executing threads at the named barrier.cta. p. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.sync and bar. When a barrier completes.sync bar. Since barriers are executed on a per-warp basis. b}.red} introduced in PTX . Thus. thread count. and bar. execute a bar.popc. Execution in this case is unpredictable. bar.sync and bar. the optional thread count must be a multiple of the warp size. The result of .arrive does not cause any waiting by the executing threads. and any-thread-true (. . the final value is written to the destination register in all threads waiting at the barrier. bar. bar.red delays the executing threads (similar to bar. d. b}. and then safely read values stored by other threads prior to the barrier.red instruction.sync or bar. {!}c. bar. it simply marks a thread's arrival at the barrier.red} require sm_20 or later.sync or bar.and)..red. the bar. January 24.version 2. a.{arrive. Instruction Set Table 100. The reduction operations for bar.sync without a thread count introduced in PTX ISA 1. In conditionally executed code. Each CTA instance has sixteen barriers numbered 0. operands p and c are predicates. Barriers are executed on a per-warp basis as if all the threads in a warp are active.sync) until the barrier count is met. All threads in the warp are stalled until the barrier completes.arrive. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Description Performs barrier synchronization and communication within a CTA.0. b.op. all threads in the CTA participate in the barrier.0.pred .and. threads within a CTA that wish to communicate via memory can store to memory.sync with an immediate barrier number is supported for sm_1x targets. if any thread in a warp executes a bar instruction.sync 0. bar.or).red.arrive a{. bar. and the barrier is reinitialized so that it can be immediately reused. the waiting threads are restarted without delay.arrive using the same active barrier.red performs a reduction operation across threads. Register operands.and and . In addition to signaling its arrival at the barrier. Note that a non-zero thread count is required for bar.popc).15. {!}c.red performs a predicate reduction across the threads participating in the barrier. Once the barrier count is reached. bar. b}. a{. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. it is as if all the threads in the warp have executed the bar instruction. and d have type .op = { . while . 2010 133 .{arrive.

sys will typically have much longer latency than membar.0. or system memory level. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys Waits until all prior memory requests have been performed with respect to all clients.sys.gl. including thoses communicating via PCI-E such as system and peer-to-peer memory.g.cta. membar. 2010 .gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.level. A memory write (e. . membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. when the previous value can no longer be read.{cta. membar.gl.gl.gl} supported on all target architectures.PTX ISA Version 2. and memory reads by this thread can no longer be affected by other thread writes. . For communication between threads in different CTAs or even different SMs.{cta. that is.cta Waits until all prior memory writes are visible to other threads in the same CTA.cta.cta. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. 134 January 24. membar.4. global. PTX ISA Notes Target ISA Notes Examples membar. A memory read (e.gl will typically have a longer latency than membar. membar. by st. membar. membar.version 1. this is the appropriate level of membar. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. . membar.0 Table 101.level = { . membar.gl} introduced in PTX .sys introduced in PTX .g. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.version 2. membar. membar.sys requires sm_20 or later.sys }. red or atom) has been performed when the value written has become visible to other clients at the specified level. level describes the scope of other clients for which membar is an ordering event.

add.type atom{.s32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. an address maps to the corresponding location in local or shared memory. 32-bit operations. an address maps to global memory unless it falls within the local memory window or the shared memory window. perform the memory accesses using generic addressing.space = { . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.. . . cas (compare-and-swap). performs a reduction operation with operand b and the value in location a.. . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . and stores the result of the specified operation at location a. .u32.f32 }. a de-referenced register areg containing a byte address. min.b64 .u64.f32 Atomically loads the original value at location a into destination register d. A register containing an address may be declared as a bit-size type or integer type.e. 2010 135 .e. If no state space is given.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. accesses to local memory are illegal. min. .exch to store to locations accessed by other atomic operations.min. . Description // // // // // . the access may proceed by silently masking off low-order address bits to achieve proper rounding.add. b.shared }. . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. d.or. e.b]. . overwriting the original value. inc. The address size may be either 32-bit or 64-bit. . .b32. .type d.and. by inserting barriers between normal stores and atomic operations to a common address.g.space}. . Within these windows. Operand a specifies a location in the specified state space. xor.b64. and exch (exchange). . For atom. dec. . The address must be naturally aligned to a multiple of the access size.u64 . and truncated if the register width exceeds the state space address width for the target architecture.u32.u32 only . max. atom.s32.s32. The bit-size operations are and. The integer operations are add. c.max }. . If an address is not properly aligned. atom{. or by using atom. or. and max.exch. January 24. i.b32 only . . or [immAddr] an immediate absolute byte address. Instruction Set Table 102.Chapter 8.inc. or the instruction may fault. The inc and dec operations return a result in the range [0. Addresses are zero-extended to the specified width as needed.cas. min. The floating-point add.space}.op = { . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. i. The floating-point operations are add. . [a].u32.global.op.op. b.f32. [a]. and max operations are single-precision. .xor.b32.type = { .dec. . . . the resulting behavior is undefined. . In generic addressing.

atom.cas.add.PTX ISA Version 2.1. 64-bit atom.{min.b32 d.shared operations require sm_20 or later. c) operation(*a.my_new_val. atom.shared. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. : r-1.f32.[p]. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.s32 atom. s) = (r >= s) ? 0 dec(r.my_val.exch} requires sm_12 or later.max.0. 64-bit atom.f32 atom. Introduced in PTX ISA version 1. s) = (r > s) ? s exch(r.global.shared requires sm_12 or later. atom.f32 requires sm_20 or later. b.add. Use of generic addressing requires sm_20 or later. *a = (operation == cas) ? : } where inc(r.global.0 Semantics atomic { d = *a. cas(r. d. : r+1. atom. d. : r.s.max} are unimplemented.cas.global requires sm_11 or later. b). atom.[x+4].[a]. 2010 . Release Notes Examples @p 136 January 24.0.t) = (r == s) ? t operation(*a.{add. s) = s.

dec(r. where inc(r.inc. and stores the result of the specified operation at location a. by inserting barriers between normal stores and reduction operations to a common address. . . i. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.e. . . Semantics *a = operation(*a. Addresses are zero-extended to the specified width as needed.u64. the resulting behavior is undefined. 2010 137 . i. Description // // // // . Notes Operand a must reside in either the global or shared state space.s32. . .u64 . red. The floating-point operations are add. In generic addressing. If no state space is given.u32. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The address size may be either 32-bit or 64-bit.s32.and.u32.min. max. . . min. . The floating-point add.Chapter 8. s) = (r > s) ? s : r-1. b.b]. perform the memory accesses using generic addressing. Operand a specifies a location in the specified state space..add. or the instruction may fault. For red. The bit-size operations are and.op. and max operations are single-precision.max }.xor. dec. an address maps to the corresponding location in local or shared memory.or.space = { . . . red{.b32.global.e. .op = { .u32 only . overwriting the original value. and xor. . min. Within these windows. The address must be naturally aligned to a multiple of the access size. min. or by using atom. 32-bit operations. If an address is not properly aligned. . .f32 }. . an address maps to global memory unless it falls within the local memory window or the shared memory window. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. .f32..type [a]. e.add.s32.exch to store to locations accessed by other reduction operations. inc.f32 Performs a reduction operation with operand b and the value in location a.shared }.space}. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . or [immAddr] an immediate absolute byte address. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. The inc and dec operations return a result in the range [0. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. b).b64. s) = (r >= s) ? 0 : r+1. A register containing an address may be declared as a bit-size type or integer type. . January 24. The integer operations are add. accesses to local memory are illegal. or.g.dec.u32. Instruction Set Table 103.type = { . and max. a de-referenced register areg containing a byte address.b32 only . and truncated if the register width exceeds the state space address width for the target architecture.

0.add. red.global. Use of generic addressing requires sm_20 or later.1.f32 red. red.2.and.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [x+4]. 64-bit red.s32 red.add requires sm_12 or later.PTX ISA Version 2. Release Notes Examples @p 138 January 24.shared.shared operations require sm_20 or later.global. [p].global requires sm_11 or later red. 64-bit red.max.max} are unimplemented.f32. red.shared requires sm_12 or later. red.b32 [a]. 2010 .f32 requires sm_20 or later.add.my_val.{min.

vote.all True if source predicate is True for all active threads in warp. // get ‘ballot’ across warp January 24. not across an entire CTA. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. vote.any True if source predicate is True for some active thread in warp.ballot. vote requires sm_12 or later. vote.uni }.all. The reduction modes are: . In the ‘ballot’ form. {!}a.mode. // ‘ballot’ form. returns bitmask .uni True if source predicate has the same value in all active threads in warp.ballot.p.Chapter 8.q.uni.ballot. The destination predicate value is the same across all threads in the warp. Description Performs a reduction of the source predicate across threads in a warp.pred vote.mode = { .uni. Negating the source predicate also computes .b32 d. p.2.b32 requires sm_20 or later.q. vote.b32 p.none.all. {!}a. r1. . .pred d.not_all. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Negate the source predicate to compute . Note that vote applies to threads in a single warp. Negate the source predicate to compute . where the bit position corresponds to the thread’s lane id.any.ballot. Instruction Set Table 104.pred vote. 2010 139 . . vote. .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.

The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).b2. The sign of the intermediate result depends on dtype. The general format of video instructions is as follows: // 32-bit scalar operation.s34 intermediate result.b3.dtype = .s32) is specified in the instruction type. The primary operation is then performed to produce an . to produce signed 33-bit input values. a{.btype{. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.dtype.bsel = { . with optional secondary operation vop. atype.atype = .dtype.asel}.PTX ISA Version 2. c.secop = { .dsel = .add.9.b1. .bsel}. vop. b{. . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. all combinations of dtype. The type of each operand (.h0. a{.7. a{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.atype.max }.0 8.sat} d. perform a scalar arithmetic operation to produce a signed 34-bit result.u32 or .bsel}. 2. The source and destination operands are all 32-bit registers. b{. . with optional data merge vop.bsel}.dsel.sat} d. // 32-bit scalar operation. 2010 . optionally clamp the result to the range of the destination type. c. or word values from its source operands.min.asel}.extended internally to . the input values are extracted and signor zero. half-word.or zero-extend byte. Using the atype/btype and asel/bsel specifiers. .dtype.u32. .btype = { .b0. taking into account the subword destination size in the case of optional data merging.sat}.s32 }.btype{.asel}. 4. extract and sign. .btype{. .atype. and btype are valid.s33 values. b{.secop d.asel = . .atype.h1 }. Video Instructions All video instructions operate on 32-bit register operands. . . 140 January 24. 3. .

default: return tmp.s33 optSaturate( .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. S16_MIN ). . S16_MAX. c). S32_MIN ). . tmp. c).h1: return ((tmp & 0xffff) << 16) case . as shown in the following pseudocode.s33 tmp.s33 c ) switch ( dsel ) { case .s33 tmp.max return MAX(tmp.h0. c). tmp. tmp.b2.b3: if ( sign ) return CLAMP( else return CLAMP( case . January 24. 2010 141 . c). .b1. c). U16_MIN ).b2: return ((tmp & 0xff) << 16) case . S32_MAX.s33 c) { switch ( secop ) { . c).b1: return ((tmp & 0xff) << 8) case . Modifier dsel ) { if ( !sat ) return tmp. Bool sign.Chapter 8. switch ( dsel ) { case .s33 optSecOp(Modifier secop.min: return MIN(tmp. U32_MAX. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. c). The sign of the c operand is based on dtype.b3: return ((tmp & 0xff) << 24) default: return tmp. U16_MAX. . Bool sat. } } .s34 tmp. .add: return tmp + c. . . tmp. U8_MAX. .b0: return ((tmp & 0xff) case .s33 optMerge( Modifier dsel. . S8_MIN ).h0: return ((tmp & 0xffff) case . tmp. The lower 32-bits are then written to the destination operand. . U32_MIN ). } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). Instruction Set .b0. U8_MIN ). S8_MAX. .

asel}.s32. vmin. r3. dsel ). and optional secondary arithmetic operation or subword data merge. vabsdiff. atype. taking into account destination type and merge operations tmp = optSaturate( tmp. r1. btype. // optional merge with c operand 142 January 24. .btype{. c.btype{.asel = . vadd.sat} d.sat vabsdiff.b3. c ). vmin. .asel}. // 32-bit scalar operation. vmin. r3. vsub. { . a{.dsel . r2. .0.s32.u32. vop. r3.asel}. c. .b0.sat} d. b{.h1 }. vsub.atype.add.dtype.op2 d. bsel ).h0.sat.s32 }. a{. with optional data merge vop. .b2. b{.h1.btype{.dsel. vsub.u32.sat vmin. tb ). tmp.u32. tmp = MIN( ta. . r3.dtype. Integer byte/half-word/word absolute value of difference. Perform scalar arithmetic operation with optional saturate. r1. .bsel = { .s32.0 Table 105.b1.b0. . // optional secondary operation d = optMerge( dsel. Semantics // saturate. r1. isSigned(dtype). vsub vabsdiff vmin.b0. a{. r2. b{. c.s32. Integer byte/half-word/word minimum / maximum.min. r2.btype = { .dtype.sat}.b2. // extract byte/half-word/word and sign. c ).s32. tmp. tmp = ta – tb. sat. Video Instructions: vadd. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.dtype . 2010 . vmax }.s32.h0.or zero-extend based on source operand type ta = partSelectSignExtend( a. vmax require sm_20 or later.h1. tb = partSelectSignExtend( b. asel ). r2.max }.s32.atype.add r1.atype = .bsel}. vadd. .atype. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.vop .s32.h0. // 32-bit scalar operation. vmax vadd.bsel}. with optional secondary operation vop.op2 Description = = = = { vadd. .bsel}.s32. d = optSecondaryOp( op2. vmax Syntax Integer byte/half-word/word addition / subtraction.sat vsub.PTX ISA Version 2. c. vabsdiff. vabsdiff. . tmp = | ta – tb |.s32. tmp = MAX( ta. tb ).

bsel ). . r2. b{. } // saturate. d = optSecondaryOp( op2.u32{. .mode} d. c ).u32.sat}{.min. 2010 143 .dtype. // optional secondary operation d = optMerge( dsel. and optional secondary arithmetic operation or subword data merge. asel ).op2 Description = = = = = { vshl.bsel}.u32 vshr. . and optional secondary arithmetic operation or subword data merge. vshl: Shift a left by unsigned amount in b with optional saturate. if ( mode == .h1 }.b0.dtype. a{.wrap }.wrap r1. a{. Semantics // extract byte/half-word/word and sign. tmp.dsel.u32.dsel .asel}. vshr }.u32.bsel}. dsel ). b{. .bsel = { . b{.or zero-extend based on source operand type ta = partSelectSignExtend( a.mode .atype. a{. case vshr: tmp = ta >> tb. . r3. r2.u32. r3.s32 }.h0. vshr vshl.add. tmp. atype. // 32-bit scalar operation. vshl.atype = { .atype. . isSigned(dtype).clamp . r1. January 24.op2 d.sat}{. // 32-bit scalar operation. Left shift fills with zero.h1. // default is . c.Chapter 8.mode} d.asel = .u32.b2.max }. Instruction Set Table 106.0. { .bsel}. tb = partSelectSignExtend( b. . . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.dtype . with optional secondary operation vop.u32{. vshr require sm_20 or later.mode}. vshr Syntax Integer byte/half-word/word left / right shift. { . vop. . taking into account destination type and merge operations tmp = optSaturate( tmp.asel}. switch ( vop ) { case vshl: tmp = ta << tb. . with optional data merge vop.sat}{. vshr: Shift a right by unsigned amount in b with optional saturate.clamp. . . c. unsigned shift fills with zero.vop . sat. vshl. c ).clamp && tb > 32 ) tb = 32.dtype.asel}.u32{. if ( mode == .wrap ) tb = tb & 0x1f. Video Instructions: vshl.s32. Signed shift fills with the sign bit.b1.atype.u32.b3.

bsel}.sat}{.PTX ISA Version 2.shr7. // 32-bit scalar operation vmad.po) computes (a*b) + c + 1.atype = .b0.po{. 144 January 24. {-}b{.s32 }. b{. .po mode. The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed -(S32 * S32) + S32 // intermediate signed. final signed (U32 * U32) . The “plus one” mode (.dtype.scale} d. . .S32 // intermediate signed. Although PTX syntax allows separate negation of the a and b operands.dtype = . and zero-extended otherwise. .atype.h0. which is used in computing averages. final signed (S32 * U32) . final signed -(U32 * S32) + S32 // intermediate signed.scale} d. c.0 Table 107. final signed (S32 * S32) + S32 // intermediate signed. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. final unsigned -(U32 * U32) + S32 // intermediate signed. final signed (S32 * S32) . otherwise. vmad. and the operand negates. a{.btype{. “plus one” mode.u32.S32 // intermediate signed. The source operands support optional negation with some restrictions. .. {-}c. internally this is represented as negation of the product (a*b). this result is sign-extended if the final result is signed. . Depending on the sign of the a and b operands. Input c has the same sign as the intermediate result. final signed -(S32 * U32) + S32 // intermediate signed.asel}. and scaling.b1.btype.h1 }. final signed The intermediate result is optionally scaled via right-shift.shr15 }.dtype.S32 // intermediate signed.sat}{. (a*b) is negated if and only if exactly one of a or b is negated. .atype. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.scale = { .bsel}.U32 // intermediate unsigned.b3.b2. That is.bsel = { .btype = { . Description Calculate (a*b) + c. PTX allows negation of either (a*b) or c. final signed (U32 * S32) .asel = . . . . with optional operand negates. 2010 .asel}. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. {-}a{. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (U32 * S32) + S32 // intermediate signed. final signed (S32 * U32) + S32 // intermediate signed. Source operands may not be negated in . the intermediate result is signed.

h0. r2. case .shr15: result = (tmp >> 15) & 0xffffffffffffffff. lsb = 0. S32_MAX.u32. } else if ( c. 2010 145 .s32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. U32_MAX. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 1.negate) || c. asel ). r1.0. atype. switch( scale ) { case .Chapter 8.sat vmad. r1.negate ^ b. r3. vmad. } else if ( a. btype. bsel ). S32_MIN). tb = partSelectSignExtend( b. r2.or zero-extend based on source operand type ta = partSelectSignExtend( a. signedFinal = isSigned(atype) || isSigned(btype) || (a. vmad requires sm_20 or later. -r3.u32. tmp = tmp + c128 + lsb.s32. } if ( . tmp[127:0] = ta * tb.po ) { lsb = 1. U32_MIN).shr7: result = (tmp >> 7) & 0xffffffffffffffff.negate ) { c = ~c. January 24.h0.sat ) { if (signedFinal) result = CLAMP(result. r0. lsb = 1.negate ) { tmp = ~tmp. else result = CLAMP(result.shr15 r0. if ( .u32. Instruction Set Semantics // extract byte/half-word/word and sign.negate ^ b.negate.u32.

146 January 24.dsel.u32.op2 d.cmp . .ge }. b{.cmp d.u32. with optional secondary arithmetic operation or subword data merge. b{. .btype = { . // 32-bit scalar operation. vset requires sm_20 or later.b2.s32 }.lt. with optional data merge vset. btype. bsel ).add.atype . { . .atype.max }. vset.atype.h0.or zero-extend based on source operand type ta = partSelectSignExtend( a. c. . . // 32-bit scalar operation.0. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.btype.cmp d.ne. r1.b1.eq. c. . . c ).bsel}.u32. .s32. Semantics // extract byte/half-word/word and sign.ne r1. The intermediate result of the comparison is always unsigned. cmp ) ? 1 : 0.lt vset.dsel . .btype.PTX ISA Version 2.op2 Description = = = = . .btype. Compare input values using specified comparison. . .asel}. r3. d = optSecondaryOp( op2.bsel = { . r2. r2.bsel}.le. c ). b{. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.asel}.0 Table 108.gt. asel ). 2010 .b0. tb.bsel}. vset. and therefore the c operand and final result are also unsigned. . { . tmp. atype. . .b3. tmp = compare( ta.min. r3.u32.asel}.h1 }.h1. tb = partSelectSignExtend( b. // optional secondary operation d = optMerge( dsel. tmp. with optional secondary operation vset. a{. a{. a{.asel = .atype.cmp.

10. brkpt requires sm_11 or later. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. January 24. Introduced in PTX ISA version 1. Table 110. Triggers one of a fixed number of performance monitor events. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. @p pmevent 1. pmevent a.7. there are sixteen performance monitor events. trap. with index specified by immediate operand a. trap. Supported on all target architectures. brkpt Suspends execution Introduced in PTX ISA version 1. numbered 0 through 15.4. Instruction Set 8. brkpt. Supported on all target architectures. brkpt. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. pmevent 7. The relationship between events and counters is programmed via API calls from the host. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.Chapter 8.0. trap Abort execution and generate an interrupt to the host CPU. Introduced in PTX ISA version 1. 2010 147 . Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Notes PTX ISA Notes Target ISA Notes Examples Currently.0. Table 111.

2010 .PTX ISA Version 2.0 148 January 24.

…. %pm3 January 24. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_ge. read-only variables. %lanemask_lt. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_le.Chapter 9. 2010 149 . %clock64 %pm0. Special Registers PTX includes a number of predefined. %lanemask_gt %clock.

PTX ISA Version 2. mov. Redefined as . mad.z. %ntid. or 3D vector to match the CTA shape.z == 0 in 1D CTAs. %ntid. Redefined as .y * %ntid.x.x. // CTA shape vector // CTA dimensions A predefined. 2010 .x < %ntid. Supported on all target architectures.sreg . // thread id vector // thread id components A predefined.0.%tid.u32 %r1.x code Target ISA Notes Examples 150 January 24.y 0 <= %tid. %ntid.z. %tid. %tid. .x.z == 1 in 2D CTAs. Every thread in the CTA has a unique %tid.x.y < %ntid. the fourth element is unused and always returns zero.%ntid.u32 %tid. // zero-extend tid. %ntid.u32 %r0.y.u16 %rh. The %tid special register contains a 1D. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x.u32 type in PTX 2. %tid.u32 %ntid.%tid.y == %ntid. It is guaranteed that: 0 <= %tid.v4. PTX ISA Notes Introduced in PTX ISA version 1.y.0 Table 112.v4 . read-only. // legacy PTX 1.%r0.%h1.z to %r2 Table 113. . mov.u32 %h2.%h2. %tid.x. Supported on all target architectures. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.u32 %h1. .v4 . The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u16 %r2.0.%ntid. // compute unified thread id for 2D CTA mov. cvt.sreg .%tid.z < %ntid. .z). // move tid.sreg .x 0 <= %tid.z == 0 in 2D CTAs.x. %tid component values range from 0 through %ntid–1 in each CTA dimension. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. the %tid value in unused dimensions is 0.y == %tid.z == 1 in 1D CTAs. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.%tid. CTA dimensions are non-zero.0.x code accessing 16-bit component of %tid mov. The total number of threads in a CTA is (%ntid. read-only special register initialized with the number of thread ids in each CTA dimension.u32 %r0.0.%tid. 2D. The number of threads in each dimension are specified by the predefined special register %ntid.sreg .x to %rh Target ISA Notes Examples // legacy PTX 1. mov.v4.u32.y.u32 type in PTX 2. The fourth element is unused and always returns zero.u32 %ntid.z.x * %ntid.u16 %rh. mov. per-thread special register initialized with the thread identifier within the CTA.u32 %tid.z PTX ISA Notes Introduced in PTX ISA version 1.

Introduced in PTX ISA version 2.u32 %nwarpid. due to rescheduling of threads following preemption. A predefined. Note that %warpid is volatile and returns the location of a thread at the moment when read. The warp identifier will be the same for all threads within a single warp. read-only special register that returns the thread’s lane within the warp. %nwarpid requires sm_20 or later. read-only special register that returns the maximum number of warp identifiers.u32 %warpid. mov. but its value may change during execution. %nwarpid. 2010 151 . The lane identifier ranges from zero to WARP_SZ-1. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. A predefined.sreg .sreg . %warpid. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.g. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. e. . Supported on all target architectures. Special Registers Table 114.3. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. read-only special register that returns the thread’s warp identifier. mov. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.u32 %laneid. Supported on all target architectures. .0. A predefined.u32 %r.u32 %r. Introduced in PTX ISA version 1. mov.Chapter 9.u32 %r. January 24. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. . %laneid. PTX ISA Notes Target ISA Notes Examples Table 116. For this reason. Introduced in PTX ISA version 1.3.sreg . Table 115.

v4 . .y. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.%nctaid. // CTA id vector // CTA id components A predefined. %ctaid.x code Target ISA Notes Examples 152 January 24.%ctaid.u32 type in PTX 2.{x. // Grid shape vector // Grid dimensions A predefined.z < %nctaid.%nctaid. // legacy PTX 1.y. It is guaranteed that: 0 <= %ctaid.0.y.z} < 65. // legacy PTX 1.536 PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures. with each element having a value of at least 1.x.0 Table 117. Redefined as .sreg . read-only special register initialized with the CTA identifier within the CTA grid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. or 3D vector. It is guaranteed that: 1 <= %nctaid. .y < %nctaid.x < %nctaid. The %nctaid special register contains a 3D grid shape vector.0.%nctaid.u32 %ctaid.x.y 0 <= %ctaid.x.u32 %ctaid.x. The fourth element is unused and always returns zero.y.u32 mov. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.u32 %nctaid. Redefined as . Supported on all target architectures.z PTX ISA Notes Introduced in PTX ISA version 1.u16 %r0.v4.u32 mov.z.x 0 <= %ctaid. mov. %rh.sreg .u16 %r0.PTX ISA Version 2.%ctaid.0.sreg .%nctaid.v4 . depending on the shape and rank of the CTA grid.u32 %nctaid .x.v4. 2D. The fourth element is unused and always returns zero. %rh. The %ctaid special register contains a 1D. %ctaid. mov. read-only special register initialized with the number of CTAs in each grid dimension.z.sreg .0.x code Target ISA Notes Examples Table 118. 2010 .u32 type in PTX 2. Each vector element value is >= 0 and < 65535. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. .

read-only special register that returns the processor (SM) identifier on which a particular thread is executing.3. Introduced in PTX ISA version 1. Supported on all target architectures.sreg . The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. %nsmid requires sm_20 or later. but its value may change during execution.0. due to rescheduling of threads following preemption. . mov. Note that %smid is volatile and returns the location of a thread at the moment when read. e. The SM identifier numbering is not guaranteed to be contiguous.u32 %gridid. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. %gridid.sreg . PTX ISA Notes Target ISA Notes Examples Table 121.Chapter 9. During execution.sreg . repeated launches of programs may occur. Notes PTX ISA Notes Target ISA Notes Examples Table 120.u32 %nsmid.0. %nsmid. . so %nsmid may be larger than the physical number of SMs in the device. . A predefined. where each launch starts a grid-of-CTAs.u32 %r. PTX ISA Notes Target ISA Notes Examples January 24. mov. Supported on all target architectures. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.u32 %r. Introduced in PTX ISA version 2. %smid. The SM identifier numbering is not guaranteed to be contiguous. A predefined. 2010 153 .u32 %smid. This variable provides the temporal grid launch number for this context. read-only special register that returns the maximum number of SM identifiers. The SM identifier ranges from 0 to %nsmid-1. // initialized at grid launch A predefined. Introduced in PTX ISA version 1.g. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Special Registers Table 119.u32 %r. read-only special register initialized with the per-grid temporal grid identifier. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov.

.u32 %lanemask_eq. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. 2010 . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %r. mov.u32 %r. %lanemask_le requires sm_20 or later. .0. Introduced in PTX ISA version 2.0. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. 154 January 24.PTX ISA Version 2.sreg . %lanemask_le. A predefined.u32 %lanemask_le.u32 %r.0. Introduced in PTX ISA version 2. A predefined. Table 124.sreg . mov. %lanemask_lt.sreg . Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined. %lanemask_eq requires sm_20 or later. mov. Introduced in PTX ISA version 2.0 Table 122. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %lanemask_lt. . %lanemask_eq. %lanemask_lt requires sm_20 or later. Table 123.

%lanemask_ge.0.sreg . Table 126. Special Registers Table 125. . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. A predefined. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. Introduced in PTX ISA version 2. A predefined. %lanemask_gt requires sm_20 or later. %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %lanemask_gt. 2010 155 . mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge requires sm_20 or later.sreg .u32 %r.0.Chapter 9. Introduced in PTX ISA version 2. January 24. .u32 %lanemask_ge.

read-only 32-bit unsigned cycle counter. %clock64 requires sm_20 or later. Introduced in PTX ISA version 1. Their behavior is currently undefined.%clock64. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.%clock.u64 r1. Introduced in PTX ISA version 2. Supported on all target architectures. %pm1. mov.3. .0 Table 127.sreg .u32 r1.PTX ISA Version 2. …. Table 129. 2010 . read-only 64-bit unsigned cycle counter. mov. mov.sreg . %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Special registers %pm0. Table 128. Supported on all target architectures. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm1. . %pm2. %pm2. %pm1. %pm2.0. .sreg .u64 %clock64. Introduced in PTX ISA version 1.u32 %clock.0.u32 r1. %pm3 %pm0.u32 %pm0. 156 January 24. The lower 32-bits of %clock64 are identical to %clock. %pm3. Special Registers: %pm0. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.%pm0. and %pm3 are unsigned 32-bit read-only performance monitor counters. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.

version directive. Directives 10.target Table 130.minor // major. Supported on all target architectures.version major.version 2.1.Chapter 10. . 2010 157 . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. minor are integers Specifies the PTX language version number.version . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Duplicate .version directive. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX File Directives: .version directives are allowed provided they match the original .version .0.0 . .4 January 24. Increments to the major number indicate incompatible changes to PTX. and the target architecture for which the code was generated. .version 1. Each ptx file must begin with a .version Syntax Description Semantics PTX version number.

red}. immediately followed by a . 158 January 24. A program with multiple .f64 storage remains as 64-bits.f64 instructions used. Adds {atom.target directive containing a target architecture and optional platform options.f64 instructions used. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. texmode_independent.5.0. sm_11. where each generation adds new features and retains all features of previous generations.f64 to . Target sm_20 Description Baseline feature set for sm_20 architecture. PTX features are checked against the specified target architecture. with only half being used by instructions converted from . Note that .global. including expanded rounding modifiers. 2010 .samplerref descriptors.shared.f64 instructions used.version directive. Therefore. and an error is generated if an unsupported feature is used.0 Table 131.red}. Requires map_f64_to_f32 if any . PTX code generated for a given target can be run on later generation devices.target Syntax Architecture and Platform target. Adds double-precision support. Texturing mode: (default is .red}. map_f64_to_f32 }. generations of SM architectures follow an “onion layer” model.global.PTX ISA Version 2. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.texref descriptor. sm_12. Description Specifies the set of features in the target architecture for which the current ptx code was generated. PTX File Directives: .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. vote instructions. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.f32. A . In general. texmode_unified. The following table summarizes the features in PTX that vary according to target architecture.target .target directive specifies a single target architecture.texref and .texmode_unified .texmode_independent texture and sampler information is bound together and accessed via a single . texture and sampler information is referenced with independent . but subsequent . Texturing mode introduced in PTX ISA version 1. . Each PTX file must begin with a . sm_13. Requires map_f64_to_f32 if any . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Supported on all target architectures. brkpt instructions. Introduced in PTX ISA version 1.target directives can be used to change the set of target features allowed during parsing.texmode_unified) . Adds {atom. sm_10. Disallows use of map_f64_to_f32. 64-bit {atom.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Requires map_f64_to_f32 if any . The texturing mode is specified for an entire module and cannot be changed within the module.

target sm_10 // baseline target architecture . 2010 159 .target sm_13 // supports double-precision .target sm_20. texmode_independent January 24. Directives Examples .Chapter 10.

entry kernel-name ( param-list ) kernel-body . Parameters are passed via .0 through 1.param instructions. PTX ISA Notes For PTX ISA version 1.entry filter ( .samplerref. parameters.surfref variables may be passed as parameters.entry kernel-name kernel-body Defines a kernel entry point name.0 10. 160 January 24.PTX ISA Version 2. Kernel and Function Directives: .entry .param space memory and are listed within an optional parenthesized parameter list.2. These parameters can only be referenced by name within texture and surface load.b32 %r3. Supported on all target architectures.texref. 2010 . … } .b32 %r<99>. .func Table 132. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Parameters may be referenced by name within the kernel body and loaded into registers using ld. parameter variables are declared in the kernel body.b32 %r2.param. opaque . .4 and later.param. %ntid.entry .b32 y. etc. ld.4.b32 x. .b32 %r1. At kernel launch. with optional parameters. parameter variables are declared in the kernel parameter list. ld.entry cta_fft . Semantics Specify the entry point for a kernel program.b32 z ) Target ISA Notes Examples [x].reg . and body for the kernel function. [z]. and query instructions and cannot be accessed via ld. For PTX ISA versions 1. . .param { .5 and later.param.param . the kernel dimensions and properties are established and made available via special registers. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.g. e. store. .entry Syntax Description Kernel entry point and body. ld.param instructions. and . In addition to normal parameters. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. The shape and size of the CTA executing the kernel are available in special registers.0 through 1.param . [y]. %nctaid.3.

2010 161 . (val0. Kernel and Function Directives: .b32 N.func (ret-param) fname (param-list) function-body Defines a function. Parameters in .func (. including input and return parameters and optional function body.x code. . Variadic functions are represented using ellipsis following the last fixed argument. A . and supports recursion. ret.param instructions in the body. implements an ABI with stack.result. Variadic functions are currently unimplemented. which may use a combination of registers and stack locations to pass parameters. The implementation of parameter passing is left to the optimizing translator.0 with target sm_20 supports at most one return value. .param space are accessed using ld. mov. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.param state space. … use N. PTX 2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. other code.0 with target sm_20 allows parameters in the . .b32 rval.reg .param and st. parameters must be in the register state space. Parameters in register state space may be referenced directly within instructions in the function body.func definition with no body provides a function prototype.func fname function-body . if any. } … call (fooval). Parameter passing is call-by-value.reg . Supported on all target architectures.reg .f64 dbl) { .reg . … Description // return value in fooval January 24.func . Release Notes For PTX ISA version 1. dbl. The parameter lists define locally-scoped variables in the function body. val1).Chapter 10. Parameters must be base types in either the register or parameter state space.0.2 for a description of variadic functions. and recursion is illegal.func Syntax Function definition. there is no stack. Directives Table 133.func fname (param-list) function-body . foo. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.b32 rval) foo (.b32 localVar. PTX ISA 2.

The directives take precedence over any module-level constraints passed to the optimizing backend.maxntid .maxntid directive specifies the maximum number of threads in a thread block (CTA).pragma The . The directive passes a list of strings to the backend.PTX ISA Version 2.maxnctapersm (deprecated) . the .3. for example. Note that . and the . the . and .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. or as statements within a kernel or device function body. . The interpretation of . 2010 .minnctapersm . Currently. to throttle the resource requirements (e. 162 January 24.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.maxnreg.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. and the strings have no semantics within the PTX virtual machine model. The .pragma directive is supported for passing information to the PTX backend. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.g.maxnreg . PTX supports the following directives.0 10.maxnreg directive specifies the maximum number of registers to be allocated to a single thread.maxntid and . These can be used.pragma directives may appear at module (file) scope.maxntid. registers) to increase total thread count and provide a greater opportunity to hide memory latency. A general . at entry-scope. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.entry directive and its body.minnctapersm directives may be applied per-entry and must appear between an . which pass information to the backend optimizing compiler.

entry foo . ny. Supported on all target architectures. Introduced in PTX ISA version 1. ny .maxntid nx . Directives Table 134. The maximum number of threads is the product of the maximum extent in each dimension. or the maximum number of registers may be further constrained by .Chapter 10.3.entry foo .maxntid nx. The compiler guarantees that this limit will not be exceeded.maxntid . or 3D CTA. Supported on all target architectures. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid 256 .maxntid 16.maxntid Syntax Maximum number of threads in thread block (CTA). . nz Declare the maximum number of threads in the thread block (CTA).maxntid nx. .maxnreg n Declare the maximum number of registers per thread in a CTA. Performance-Tuning Directives: . Exceeding any of these limits results in a runtime error or kernel launch failure. the backend may be able to compile to fewer registers. 2D.entry bar .maxntid and .maxctapersm. . for example.16. . This maximum is specified by giving the maximum extent of each dimention of the 1D.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. 2010 163 .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1.maxnreg . Performance-Tuning Directives: .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.3. The actual number of registers used may be less.

Introduced in PTX ISA version 1.0 Table 136. Introduced in PTX ISA version 2.maxntid and .minnctapersm .minnctapersm 4 { … } 164 January 24.3.maxntid 256 . Optimizations based on . .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm generally need . However.maxnctapersm. Deprecated in PTX ISA version 2.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. The optimizing backend compiler uses .minnctapersm in PTX ISA version 2. Performance-Tuning Directives: .PTX ISA Version 2. Performance-Tuning Directives: . Supported on all target architectures. For this reason.0.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). additional CTAs may be mapped to a single multiprocessor.0 as a replacement for . Supported on all target architectures. .maxntid to be specified as well.maxnctapersm (deprecated) .maxntid 256 . Optimizations based on . .0.entry foo .maxntid to be specified as well. if the number of registers used by the backend is sufficiently lower than this bound.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm has been renamed to .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.entry foo . .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. .maxnctapersm generally need . 2010 .

Pass module-scoped.pragma .pragma “nounroll”. Performance-Tuning Directives: . entry-scoped.pragma “nounroll”. or at statementlevel. or statement-level directives to the PTX backend compiler.pragma list-of-strings . 2010 165 . The . { … } January 24. The interpretation of .pragma directive may occur at module-scope. Directives Table 138.Chapter 10.0.entry foo .pragma directive strings is implementation-specific and has no impact on PTX semantics. Supported on all target architectures. . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma Syntax Description Pass directives to PTX backend compiler. Introduced in PTX ISA version 2. at entry-scope. See Appendix A for descriptions of the pragma strings defined in ptxas. .

4. The @@DWARF syntax is deprecated as of PTX version 2.x code.section .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 2010 .section .. @progbits .byte 0x2b. 0x00 166 January 24. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .quad int64-list // comma-separated hexadecimal integers in range [0. Table 139. Deprecated as of PTX 2. 0x00.4byte 0x000006b5.PTX ISA Version 2. 0x00 .4byte label . 0x6150736f. 0x00.section directive is new in PTX ISA verison 2.4byte int32-list // comma-separated hexadecimal integers in range [0. 0x61395a5f.232-1] .0 10. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .264-1] .debug_info . Supported on all target architectures. 0x00.4byte .0.2. 0x736d6172 .loc The . 0x63613031.byte 0x00.4byte 0x6e69616d.0 and replaces the @@DWARF syntax. @@DWARF dwarf-string dwarf-string may have one of the . 0x00.section directive.0 but is supported for legacy PTX version 1.file . 0x00. replaced by .debug_pubnames. 0x00. “”.byte byte-list // comma-separated hexadecimal byte values . Introduced in PTX ISA version 1.. 0x5f736f63 . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x02. 0x00000364.

255] . 0x5f736f63 0x6150736f.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.264-1] .file . 0x00.loc .b32 0x000006b5. 0x00. . Supported on all target architectures.b32 int32-list // comma-separated list of integers in range [0.0. Source file information.0.0. . Directives Table 140.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00.. . Supported on all target architectures.loc line_number January 24.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.debug_pubnames { .. 0x00..b32 0x6e69616d.section section_name { dwarf-lines } dwarf-lines have the following formats: .debug_info . 0x00. 0x736d6172 0x00 Table 141.b8 0x2b. } 0x02. Debugging Directives: .b8 0x00.b8 byte-list // comma-separated list of integers in range [0.section Syntax PTX section definition. Supported on all target architectures. 0x00. Source file location.b64 int64-list // comma-separated list of integers in range [0.232-1] . 0x00000364. Debugging Directives: . .Chapter 10. 0x00 0x61395a5f.b32 label .section . . . replaces @@DWARF syntax. 0x63613031. 2010 167 .b32 .section .file filename Table 142. . Debugging Directives: .

b32 foo.0 10.0.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Supported on all target architectures.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. // foo will be externally visible 168 January 24.PTX ISA Version 2.global .b32 foo.visible . Introduced in PTX ISA version 1. 2010 .extern .extern identifier Declares identifier to be defined externally.visible Table 143. Linking Directives: . . Linking Directives: . Supported on all target architectures. Linking Directives . .6.extern . // foo is defined in another module Table 144. Introduced in PTX ISA version 1.extern .global . .visible identifier Declares identifier to be externally visible. .visible .0.

2 CUDA 2.0 PTX ISA 1.0.5 PTX ISA 2.1 PTX ISA 1.2 PTX ISA 1. 2010 169 . CUDA Release CUDA 1.1 CUDA 2. The release history is as follows.0 CUDA 2.1 CUDA 2.3 driver r190 CUDA 3. and the remaining sections provide a record of changes in previous releases.0 driver r195 PTX ISA Version PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.4 PTX ISA 1.0 CUDA 1. Release Notes This section describes the history of change in the PTX ISA and implementation.0 January 24.Chapter 11.3 PTX ISA 1.

sub. New Features 11. Instructions testp and copysign have been added.ftz modifier may be used to enforce backward compatibility with sm_1x. These are indicated by the use of a rounding modifier and require sm_20. rcp.f32 require a rounding modifier for sm_20 targets.f32 and mad. while maximizing backward compatibility with legacy PTX 1. fma. The goal is to achieve IEEE 754 compliance wherever possible.0 11. and mul now support .1.1. The mad.1.f32 for sm_20 targets.rp rounding modifiers for sm_20 targets.f32. • • • • • 170 January 24.and double-precision div.sat modifiers. Changes in Version 2.1. Floating-Point Extensions This section describes the floating-point changes in PTX 2.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 11.PTX ISA Version 2. mad. The .0 for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices. The fma. Single.1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. The mad. and sqrt with IEEE 754 compliant rounding have been added. A single-precision fused multiply-add (fma) instruction has been added.x code and sm_1x targets.rm and . 2010 .f32 requires sm_20.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 maps to fma.1.f32 instruction also supports . The changes from PTX ISA 1. Both fma.rn.ftz and . Single-precision add.

prefetchu. %lanemask_{eq. New instructions A “load uniform” instruction.or}.red}. Instruction sust now supports formatted surface stores. 2010 171 . have been added. January 24. e. .section. has been added. has been added.red. membar. atom. New special registers %nsmid. A new directive.b32. has been added.3.pred have been added. ldu. has been added.u32 and bar.popc. A “find leading non-sign bit” instruction.le.ge. and shared addresses to generic address and vice-versa has been added.clamp and .f32 have been implemented. Instruction cvta for converting global. The . has been added. Instructions {atom. st. Instructions prefetch and prefetchu have also been added. local. Video instructions (includes prmt) have been added. for prefetching to specified level of memory hierarchy. A “count leading zeros” instruction. vote.1. The bar instruction has been extended as follows: • • • A bar. suld.{and. Release Notes 11.g. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.lt. st. . clz. prefetch. bfe and bfi. Instructions {atom. brev. bar now supports optional thread count and register operands.add. isspacep. 11.sys. A “population count” instruction.maxnctapersm directive was deprecated and replaced with .minnctapersm to better match its behavior and usage. Instructions bar.shared have been extended to handle 64-bit data types for sm_20 targets. %clock64. has been added. and sust.ballot. bfind.gt} have been added. and red now support generic addressing. popc.red}. has been added.1.red. A “vote ballot” instruction.1. cvta.clamp modifiers. Bit field extract and insert instructions. A “bit reversal” instruction. Cache operations have been added to instructions ld.zero. A system-level membar instruction.arrive instruction has been added. ldu.Chapter 11. Surface instructions support additional . Other new features Instructions ld.1. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.2.

.target sm_1x.5 and later. cvt.1. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. call suld. 2010 .4 and earlier. Instruction bra. the correct number is sixteen. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. In PTX version 1.u32. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.5. {atom.3.4 or earlier.ftz for PTX ISA versions 1.max} are not implemented. 11. Formatted surface store with .f32} atom. The underlying.s32. Semantic Changes and Clarifications The errata in cvt.red}. See individual instruction descriptions for details.0 11.s32.{min.PTX ISA Version 2. stack-based ABI is unimplemented.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. Support for variadic functions and alloca are unimplemented. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.f32 type is unimplemented. To maintain compatibility with legacy PTX code.ftz (and cvt for .1. Formatted surface load is unimplemented. 172 January 24. where .p sust.p. or .version is 1.2.f32. has been fixed. if .{u32.

Supported only for sm_20 targets. { … } // do not unroll any loop in this function .Appendix A. disables unrolling of0 the loop for which the current block is the loop header. 2010 173 .pragma. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. and statement levels.pragma “nounroll”. Ignored for sm_1x targets. L1_end: … } // do not unroll this loop January 24.func bar (…) { … L1_head: . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . entry-function. Descriptions of . Table 145.pragma “nounroll”.pragma Strings This section describes the . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.0. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.entry foo (…) . L1_body: … L1_continue: bra L1_head. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. The “nounroll” pragma is allowed at module. Note that in order to have the desired effect at statement level. … @p bra L1_end. disables unrolling for all loops in the entry function body. including loops preceding the .pragma strings defined by ptxas. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. .pragma “nounroll”.

0 174 January 24. 2010 .PTX ISA Version 2.

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