NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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........... 43 6............. Type Conversion.............. 49 7...........................................4...................4.......................................... 6...............................................................................................2...... 49 ii January 24.5..................................................... 33 Restricted Use of Sub-Word Sizes ..............................6............1.....1.............1...2....................................................................................... 29 Parameter State Space .............. 5................................... 6................... 30 Shared State Space..... 44 Scalar Conversions .........................................................PTX ISA Version 2............................... 6........................................................................................ 5..........................4.......................... Function declarations and definitions .......... 43 Labels and Function Names as Operands ................. 5..............................................6..............................1.........1..................... Summary of Constant Expression Evaluation Rules . 5....... 6..........3.........................................1........................... Operand Type Information ................................ 28 Special Register State Space ........................1....................... 6.............................. State Spaces .........................................1..............................3..................................................... 42 Addresses as Operands ................................ Chapter 6............. 6............ 41 Using Addresses............................. 42 Arrays as Operands .............. 5..........................................................................................................3..........................................5............4........ 5... 39 Parameterized Variable Names .4.......... 34 Variables ........................................2..1........................................................7....4.................. 38 Initializers .....2....... 25 Chapter 5.. 5............................... State Spaces......... 43 Vectors as Operands ............................... 6................1. and Vectors ................. Types.5......................... 5...2........................................................................ 41 6.......... 38 Alignment ........................................................................................................................ Arrays.......................................................................2............................................... 37 Array Declarations .. 5............3................ 32 Texture State Space (deprecated) ....................................................... 33 5..............................................................................6.................... 5.......................... 6......................................................................................8......................................2..4...4. 5...........2................................ and Variables ....................................1..................................... 37 Variable Declarations ............... Sampler...........4............ Abstracting the ABI .....................................................................3.....................4. and Surface Types ....................................... 5.......................1................................................4............ 47 Chapter 7.6..................... 27 Register State Space ................1..... 44 Rounding Modifiers ........ 32 5....................4.5.......1............................ 33 Fundamental Types .........1......... 5............... 37 Vectors .. Operand Costs .................................................. Instruction Operands.............. 29 Local State Space .............5.................4.............. 41 Destination Operands ................................ 2010 ............ 5....................... 5.4... 27 5....... 5.. 6.... 41 Source Operands......................................0 4........ 29 Global State Space ................2................................................................................................................1............... Types ............................................ Texture............. 46 6........................4................................................................................... 28 Constant State Space .....5................ 39 5..........

........4...... Divergence of Threads in Control Constructs ...............6...........................................................6.............3..................................... 56 Comparisons ..................... 53 Alloca ......... 10... Instructions ..................... 170 Semantic Changes and Clarifications ..... 8... 8....................... 132 Video Instructions ............. 52 Variadic functions ............................................... 8............................................................. 62 Machine-Specific Semantics of 16-bit Code .......1.. 149 Chapter 10....................................................................................................... 55 8.........4............................................... Changes from PTX 1................................... 8.............................................7.................................................................................................. 8............................2...........................................2...x ..........................7.............. 8............................. 8................ 7...........2........ 104 Data Movement and Conversion Instructions ...................1..........................7.............5....................................................7.6...................................... 157 Specifying Kernel Entry Points and Functions ......................3......................... 10.............................................................4..............................3... 8...... 122 Control Flow Instructions ............................ 147 8......................1............................................... 160 Performance-Tuning Directives .................. 100 Logic and Shift Instructions ............................. 57 Manipulating Predicates ............ 170 New Features ........................................1..........2....... 60 8.............1.......................................................... 11.................. 10................ 2010 iii .........5...3...............................................................................................................2........ Format and Semantics of Instruction Descriptions ......................... Changes in Version 2............ 129 Parallel Synchronization and Communication Instructions .......... 55 PTX Instructions ................................................................. 11...7................................ 140 Miscellaneous Instructions..................... 63 Floating-Point Instructions .................. 8...... 168 Chapter 11. Type Information for Instructions and Operands ...................... Release Notes ... 7... 8........... Directives ....................................................1.................................................................... 62 Semantics .................. 8..................... 157 10....... 8................. 108 Texture and Surface Instructions ...............................................7........................................................................................... 166 Linking Directives ............... 172 Unimplemented Features Remaining ...............................................4......................................... 172 January 24..................................... 8....... 162 Debugging Directives ... 169 11................... 10...................3........................................ 81 Comparison and Selection Instructions .1.............1...................................................... 62 8..............7...............7...............0 ................... 8.................7..7..........7................................ 54 Chapter 8................................................1...................................... 55 Predicated Execution ...3.................... 59 Operand Size Exceeding Instruction-Type Size ...........................................................7.......................................................... 8..........6.. 63 Integer Arithmetic Instructions ................................. 58 8................................ Special Registers ..9..................... Chapter 9. 11............................. Instruction Set .....1................................ PTX Version and Target Directives ..................................................... 8...........10.............7........8.................1...1....1..............................2.......................3........................

........PTX ISA Version 2.... 173 iv January 24................ 2010 . Descriptions of ...........pragma Strings............0 Appendix A................

............................................................................ 57 Floating-Point Comparison Operators Accepting NaN .......................... Table 27. 69 Integer Arithmetic Instructions: mad24 ...... 18 Reserved Instruction Keywords ...................... Table 12.............. Table 32.... Table 24........................ 70 Integer Arithmetic Instructions: sad ......................... Table 18.............................................List of Tables Table 1......... 66 Integer Arithmetic Instructions: mul .............. Table 9................... Table 17....................................... 58 Floating-Point Comparison Operators Testing for NaN ..................................................................................... Table 5.. Table 13..................... Table 25.................................................................................................................. Table 8................................................................................................................................................ Table 26.................................................................................. PTX Directives ....................................................... Table 3................ 60 Relaxed Type-checking Rules for Destination Operands.......... Table 19........................................................................ 58 Type Checking Rules ......................................................... Table 2............... Table 28....................................... 65 Integer Arithmetic Instructions: sub......... 46 Integer Rounding Modifiers ......................... 66 Integer Arithmetic Instructions: subc ............................................. 35 Opaque Type Fields in Independent Texture Mode ...................................................................... 28 Fundamental Type Specifiers ....... 35 Convert Instruction Precision and Format ........... 67 Integer Arithmetic Instructions: mad . 57 Floating-Point Comparison Operators .......... 61 Integer Arithmetic Instructions: add ........ 2010 v ...................... Table 21..... 46 Cost Estimates for Accessing State-Spaces ...................... 65 Integer Arithmetic Instructions: addc ............................................... 64 Integer Arithmetic Instructions: add.................................................................. Table 7.......... Table 11......................................cc ........ 25 State Spaces ................ 59 Relaxed Type-checking Rules for Source Operands .................... Table 16.......................................... 19 Predefined Identifiers .... 71 January 24.............. 47 Operators for Signed Integer.................................................................................................................................. 27 Properties of State Spaces ............................ and Bit-Size Types ............................................................................................ 20 Operator Precedence ............................................... Table 10.....................................................cc ... Table 23............... Table 22...................... 68 Integer Arithmetic Instructions: mul24 ............................... Table 20.......... Unsigned Integer....................................... 33 Opaque Type Fields in Unified Texture Mode ................. Table 30............ Table 14................................... Table 29..... Table 31... Table 15.................................................. Table 4............ Table 6.............................................................................................. 23 Constant Expression Evaluation Rules .................................................................. 45 Floating-Point Rounding Modifiers ....... 64 Integer Arithmetic Instructions: sub .......................

93 Floating-Point Instructions: sqrt ................. 74 Integer Arithmetic Instructions: clz .................................... 72 Integer Arithmetic Instructions: neg ........................... Table 47. 92 Floating-Point Instructions: rcp ...................................... Table 40.... 95 Floating-Point Instructions: sin ................................................................................. 83 Floating-Point Instructions: copysign .... Table 51............................... Table 34............................................. Integer Arithmetic Instructions: div ............... Table 67.................................. 83 Floating-Point Instructions: add ............ 85 Floating-Point Instructions: mul ................................................................. Table 62. 78 Integer Arithmetic Instructions: prmt ...... Table 36........................ 87 Floating-Point Instructions: mad ................................................................................................................................................................................................................................................................... 76 Integer Arithmetic Instructions: bfe ........................................ 97 Floating-Point Instructions: lg2 ............................................................................................................................. 101 Comparison and Selection Instructions: setp .............................. 82 Floating-Point Instructions: testp ....................................................................................... Table 53........... Table 39.......... 98 Floating-Point Instructions: ex2 ........................................... Table 45..................... 90 Floating-Point Instructions: abs ....................... Table 64............................................ Table 57.................... Table 35..................................................................... Table 68..................... 2010 ..... 74 Integer Arithmetic Instructions: bfind ......................... Table 60......................... Table 52........................................................... 96 Floating-Point Instructions: cos ................... 99 Comparison and Selection Instructions: set .. 72 Integer Arithmetic Instructions: min ................ Table 50...................................... Table 43.............. Table 42................................................................................................ Table 56.................................. Table 41.................................. 91 Floating-Point Instructions: neg .............................................................................. Table 38.......................... 71 Integer Arithmetic Instructions: abs ............................. 84 Floating-Point Instructions: sub .......................................................................................................................................... 86 Floating-Point Instructions: fma .......PTX ISA Version 2................................... Table 61............................. Table 69........................ 103 Comparison and Selection Instructions: slct ..... 79 Summary of Floating-Point Instructions .................. 94 Floating-Point Instructions: rsqrt .... Table 58............................................................... Table 55....................... 103 vi January 24............................ Table 46. Table 66.......... 91 Floating-Point Instructions: min ................................................................. Table 44............................ 73 Integer Arithmetic Instructions: max ............................................................ 88 Floating-Point Instructions: div ........... Table 49..................................................... 77 Integer Arithmetic Instructions: bfi ..................................................... Table 59.................................... 92 Floating-Point Instructions: max ............ 102 Comparison and Selection Instructions: selp ..0 Table 33................................................ Table 37.................................................................................................. Table 65........................................... 73 Integer Arithmetic Instructions: popc ... 71 Integer Arithmetic Instructions: rem ........ Table 63............................. Table 54..... Table 48.................. 75 Integer Arithmetic Instructions: brev ...............................................................................................................

............. 105 Logic and Shift Instructions: or .................................. Table 71......................... 116 Data Movement and Conversion Instructions: prefetch...................................................................................... Table 92.................................. vsub....................................... Table 73. 105 Logic and Shift Instructions: xor ...................... 133 Parallel Synchronization and Communication Instructions: membar ......... 131 Parallel Synchronization and Communication Instructions: bar . Table 79............................ vmax .................... 120 Texture and Surface Instructions: tex ................................... 109 Cache Operators for Memory Store Instructions ...... 139 Video Instructions: vadd............ 2010 vii ... vabsdiff..... 129 Control Flow Instructions: bra . 119 Data Movement and Conversion Instructions: cvta ............................................... 130 Control Flow Instructions: call ................. Table 105.. Table 72...... Table 85............ Table 104........................................................... Table 80................................................................ 135 Parallel Synchronization and Communication Instructions: red ........................ 127 Texture and Surface Instructions: suq ....................................................... Table 88.................. Table 100................ 143 January 24............................... 111 Data Movement and Conversion Instructions: mov .................. 131 Control Flow Instructions: exit ........ 142 Video Instructions: vshl............................................................. Table 90.. 106 Logic and Shift Instructions: shl ....................... Table 83..... 113 Data Movement and Conversion Instructions: ldu ............ Logic and Shift Instructions: and ................ Table 75............................................................................................................................ Table 97......... 107 Cache Operators for Memory Load Instructions ............. Table 103...................................... 115 Data Movement and Conversion Instructions: st .......................................... Table 96............ 106 Logic and Shift Instructions: cnot ................................................................. 129 Control Flow Instructions: @ ....... 125 Texture and Surface Instructions: sust . Table 78............................ Table 93.... Table 102... Table 89................................ 126 Texture and Surface Instructions: sured.. Table 95......... 107 Logic and Shift Instructions: shr ................... 106 Logic and Shift Instructions: not ............... Table 87................................................. Table 82.............................................. Table 76.......................... Table 77...... Table 86................................................. vshr .. Table 98................ Table 74.................. 123 Texture and Surface Instructions: txq .......................... Table 91........ 112 Data Movement and Conversion Instructions: ld ................................................................ 119 Data Movement and Conversion Instructions: cvt .............................. 128 Control Flow Instructions: { } ............................................................................ Table 106.................. 130 Control Flow Instructions: ret ............... vmin.. 110 Data Movement and Conversion Instructions: mov .................................................................... 134 Parallel Synchronization and Communication Instructions: atom ................................ 124 Texture and Surface Instructions: suld ....................... 137 Parallel Synchronization and Communication Instructions: vote .................................................................... Table 99............................ prefetchu ...................Table 70..................... Table 84............................... 118 Data Movement and Conversion Instructions: isspacep .................................. Table 81............................................................................................. Table 101.............................................. Table 94......................

147 Special Registers: %tid . 156 Special Registers: %clock64 ...... Table 132.... Table 129......... Table 139........... 146 Miscellaneous Instructions: trap .............................................................. 151 Special Registers: %warpid ..... 167 Linking Directives: ........................................ Table 140....................................................... 150 Special Registers: %ntid ..............loc ..................... Table 117......................file ............... 152 Special Registers: %nctaid ..... Table 116.. Table 124............ 165 Debugging Directives: @@DWARF ........ 163 Performance-Tuning Directives: ..........................maxnctapersm (deprecated) ............ Table 113................................................................ 151 Special Registers: %nwarpid .... 160 Kernel and Function Directives: ............................................. 166 Debugging Directives: ............................................ Table 136................................................... 167 Debugging Directives: .............................................................maxntid .......................... Table 123................................ Table 127..........................................section ....... 157 PTX File Directives: ......... Table 131.....extern. Table 130................................................................maxnreg ..................................... Table 121....... Table 134. 164 Performance-Tuning Directives: ............................................................................................................ Table 128...............entry......................................................................................................... 147 Miscellaneous Instructions: brkpt ............................................................................................................... 150 Special Registers: %laneid .......................................................................... 152 Special Registers: %smid ........................ 147 Miscellaneous Instructions: pmevent.................... 154 Special Registers: %lanemask_lt ....................................................... %pm1.......................................... 2010 . 155 Special Registers: %lanemask_gt .................................................... 163 Performance-Tuning Directives: ................................. 167 Debugging Directives: ............. Table 119....................... 164 Performance-Tuning Directives: ........................................ Table 114. 156 PTX File Directives: ...............................PTX ISA Version 2.................... Table 141.........................................0 Table 107..... 154 Special Registers: %lanemask_le ............................................ Table 108........................... 156 Special Registers: %pm0...... Table 137.......... 153 Special Registers: %gridid ......... 161 Performance-Tuning Directives: ......pragma .. Table 122......................... Table 118........................................ %pm3 ............. Table 138................. Table 135................. Table 110.................................. Table 112................................................................ 144 Video Instructions: vset.................. Table 120.......... 155 Special Registers: %clock .. 153 Special Registers: %lanemask_eq ................................................................................................................... Table 142..................... Video Instructions: vmad ..........................................................................func .................................................. Table 109.......version.......................................................................................... Table 126.............................. 158 Kernel and Function Directives: ................................................................ Table 125...........target ....... 151 Special Registers: %ctaid ................. %pm2......................... Table 115.................... 153 Special Registers: %nsmid ....................................................... Table 111............................................minnctapersm .................................... 168 viii January 24.. 154 Special Registers: %lanemask_ge .............. Table 143................................................ Table 133......................

.............visible............... 173 January 24... 2010 ix ............................... Table 145..... 168 Pragma Strings: “nounroll” ...........................................................Table 144.......................... Linking Directives: ...................

0 x January 24.PTX ISA Version 2. 2010 .

2010 1 . Data-parallel processing maps data elements to parallel processing threads. high-definition 3D graphics. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming.Chapter 1. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. many-core processor with tremendous computational horsepower and very high memory bandwidth. and because it is executed on many data elements and has high arithmetic intensity. multithreaded. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. image and media processing applications such as post-processing of rendered images. the programmable GPU has evolved into a highly parallel. image scaling. PTX exposes the GPU as a data-parallel computing device. 1. Because the same program is executed for each data element. which are optimized for and translated to native target-architecture instructions. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. from general signal processing or physics simulation to computational finance or computational biology. 1. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Similarly. there is a lower requirement for sophisticated flow control. video encoding and decoding. the memory access latency can be hidden with calculations instead of big data caches. PTX defines a virtual machine and ISA for general purpose parallel thread execution. January 24. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. PTX programs are translated at install time to the target hardware instruction set.1. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. In fact. stereo vision.2. and pattern recognition can map image blocks and pixels to parallel processing threads. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Introduction This document describes PTX.

f32 requires sm_20. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.x features are supported on the new sm_20 target.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 and mad.PTX ISA Version 2. including integer.3. The mad. • • • 2 January 24. PTX ISA Version 2. Facilitate hand-coding of libraries.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 require a rounding modifier for sm_20 targets. memory.0 are improved support for IEEE 754 floating-point operations.0 is a superset of PTX 1. and architecture tests. mad. Provide a common source-level ISA for optimizing code generators and translators. and video instructions. 2010 . Most of the new features require a sm_20 target. Single-precision add. and the introduction of many new instructions. and mul now support . The main areas of change in PTX 2. Provide a machine-independent ISA for C/C++ and other compilers to target. surface.ftz) modifier may be used to enforce backward compatibility with sm_1x.ftz and .0 is in improved support for the IEEE 754 floating-point standard. sub. 1. fma. The fma.0 PTX ISA Version 2. PTX 2. The changes from PTX ISA 1.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Instructions marked with . and all PTX 1.x code will continue to run on sm_1x targets as well. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. barrier. atomic. Achieve performance in compiled applications comparable to native GPU performance. 1.rn.sat modifiers. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. Improved Floating-Point Support A main area of change in PTX 2. A “flush-to-zero” (.f32 maps to fma.1. Legacy PTX 1. A single-precision fused multiply-add (fma) instruction has been added. performance kernels.3.rp rounding modifiers for sm_20 targets. addition of generic addressing to facilitate the use of general-purpose pointers. reduction.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Both fma. When code compiled for sm_1x is executed on sm_20 devices.f32 for sm_20 targets. The mad.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.f32.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 instruction also supports . Provide a code distribution ISA for application and middleware developers.x. which map PTX to specific target machines.rm and .

and shared addresses to generic address and vice-versa has been added.Chapter 1. atom. prefetch. New Instructions The following new instructions. stack layout. 1. • Taken as a whole. Cache operations have been added to instructions ld.3.3. i. and vice versa. A new cvta instruction has been added to convert global. for prefetching to specified level of memory hierarchy. isspacep.3. Instructions testp and copysign have been added..0. 1. e.zero. Surface instructions support additional clamp modifiers.g. ldu. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. and sqrt with IEEE 754 compliant rounding have been added. prefetchu.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. These are indicated by the use of a rounding modifier and require sm_20. and sust. suld. and shared state spaces. these changes bring PTX 2. st.2.4. and shared addresses to generic addresses. 1. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Support for an Application Binary Interface Rather than expose details of a particular calling convention.0.clamp and . January 24. PTX 2. special registers. instructions ld. and red now support generic addressing. local. In PTX 2. . Generic Addressing Another major change is the addition of generic addressing. rcp. stack-based ABI. an address that is the same across all threads in a warp.0 closer to full compliance with the IEEE 754 standard. Generic addressing unifies the global. so recursion is not yet supported. and directives are introduced in PTX 2.and double-precision div. local. Surface Instructions • • Instruction sust now supports formatted surface stores.e. allowing memory instructions to access these spaces without needing to specify the state space. local. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. NOTE: The current version of PTX does not implement the underlying. 2010 3 . and Application Binary Interface (ABI). st. Instruction cvta for converting global.3. Instructions prefetch and prefetchu have been added. Introduction • Single. cvta.

b32. and Vote Instructions • • • New atomic and reduction instructions {atom. 4 January 24. bar now supports an optional thread count and register operands.le.red}. .sys.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. membar. Barrier Instructions • • A system-level membar instruction.{and. %lanemask_{eq.gt} have been added. New special registers %nsmid. Instructions bar. has been added. 2010 .pred have been added.arrive instruction has been added.red.f32 have been added. A bar. Instructions {atom.ge. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.red.PTX ISA Version 2.add. A “vote ballot” instruction. %clock64. Other Extensions • • • Video instructions (includes prmt) have been added.lt.ballot.u32 and bar.shared have been extended to handle 64-bit data types for sm_20 targets. bfi bit field extract and insert popc clz Atomic.or}. vote. Reduction.red}. has been added.section.popc. A new directive.

Chapter 4 describes the basic syntax of the PTX language. Chapter 11 provides release notes for PTX Version 2. Chapter 9 lists special registers. Chapter 3 gives an overview of the PTX virtual machine model.Chapter 1. January 24. Chapter 7 describes the function and call syntax. Chapter 5 describes state spaces. Introduction 1. Chapter 6 describes instruction operands. and variable declarations.0. 2010 5 . and PTX support for abstracting the Application Binary Interface (ABI). Chapter 8 describes the instruction set. calling convention. Chapter 10 lists the assembly directives supported in PTX. types.4. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.

PTX ISA Version 2. 2010 .0 6 January 24.

Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. (with elements tid. Each thread has a unique thread identifier within the CTA. is an array of threads that execute a kernel concurrently or in parallel. or CTA. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. and tid. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. It operates as a coprocessor to the main CPU. Threads within a CTA can communicate with each other. Programs use a data parallel decomposition to partition inputs.1. Programming Model 2. assign specific input and output positions. To that effect. Each CTA thread uses its thread identifier to determine its assigned role.2. and select work to perform.z) that specifies the thread’s position within a 1D. The vector ntid specifies the number of threads in each CTA dimension. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. compute-intensive portions of applications running on the host are off-loaded onto the device. Each CTA has a 1D. compute addresses. 2D. can be isolated into a kernel function that is executed on the GPU as many different threads. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. one can specify synchronization points where threads wait until all threads in the CTA have arrived. A cooperative thread array.y.z). data-parallel. The thread identifier is a three-element vector tid.y. 2010 7 .x. and ntid. January 24.2. To coordinate the communication of the threads within the CTA. tid.x. or 3D CTA. and results across the threads of the CTA. work.Chapter 2. but independently on different data. Cooperative thread arrays (CTAs) implement CUDA thread blocks. ntid. a portion of an application that is executed many times. More precisely. 2D. 2.1. or host: In other words. 2. or 3D shape specified by a three-element vector ntid (with elements ntid.

%ctaid. because threads in different CTAs cannot communicate and synchronize with each other. Each grid of CTAs has a 1D. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). 2010 .0 Threads within a CTA execute in SIMT (single-instruction. read-only special registers %tid. CTAs that execute the same kernel can be batched together into a grid of CTAs. WARP_SZ. or 3D shape specified by the parameter nctaid. 8 January 24.PTX ISA Version 2. Threads within a warp are sequentially numbered. Threads may read and use these values through predefined. %ntid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. Typically. which may be used in any instruction where an immediate operand is allowed. A warp is a maximal subset of threads from a single CTA. so PTX includes a run-time immediate constant. %nctaid. depending on the platform. Some applications may be able to maximize performance with knowledge of the warp size. Multiple CTAs may execute concurrently and in parallel. 2. so that the total number of threads that can be launched in a single kernel invocation is very large. 2D . The warp size is a machine-dependent constant. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. This comes at the expense of reduced thread communication and synchronization. such that the threads execute the same instructions at the same time. or sequentially. However. multiple-thread) fashion in groups called warps. The host issues a succession of kernel invocations to the device. Each grid also has a unique temporal grid identifier (gridid).2.2. a warp has 32 threads. and %gridid.

Figure 1. 2) Thread (2. 1) CTA (2. 0) Thread (0. 0) Thread (4. 1) CTA (1. 2) Thread (1. 1) Grid 2 Kernel 2 CTA (1. A grid is a set of CTAs that execute independently. 0) CTA (1. 1) Thread (3. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (4. 2) Thread (3. 2010 9 . Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Thread (0.Chapter 2. 1) Thread (1. Thread Batching January 24. 0) CTA (2. 0) CTA (0. 0) Thread (3. 0) Thread (2. 1) Thread (0. 2) Thread (4. 0) Thread (1. 1) Thread (2.

2010 . Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. 10 January 24.0 2. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. and texture memory spaces are persistent across kernel launches by the same application. constant. Finally. constant. The device memory may be mapped and read or written by the host. and texture memory spaces are optimized for different memory usages.3. respectively. as well as data filtering. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. or. all threads have access to the same global memory. for more efficient transfer. The global. Each thread has a private local memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces.PTX ISA Version 2. The global. for some specific data formats. Both the host and the device maintain their own local memory. Texture memory also offers different addressing modes. referred to as host memory and device memory.

Memory Hierarchy January 24. 0) Block (0. 1) Block (2. 1) Block (1. 1) Block (1. 0) Block (1. 1) Grid 1 Global memory Block (0. 2010 11 . 0) Block (2. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0.Chapter 2. 0) Block (0. 1) Block (0. 2) Block (1. 0) Block (1. 2) Figure 2.

2010 .PTX ISA Version 2.0 12 January 24.

The multiprocessor creates. If threads of a warp diverge via a data-dependent conditional branch.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. A multiprocessor consists of multiple Scalar Processor (SP) cores. 2010 13 . Branch divergence occurs only within a warp. a cell in a grid-based computation). January 24. and executes concurrent threads in hardware with zero scheduling overhead. Parallel Thread Execution Machine Model 3. manages. the multiprocessor employs a new architecture we call SIMT (single-instruction. When a host program invokes a kernel grid. it splits them into warps that get scheduled by the SIMT unit. each warp contains threads of consecutive. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). a voxel in a volume. and when all paths complete. multiple-thread). and each scalar thread executes independently with its own instruction address and register state. disabling threads that are not on that path. the warp serially executes each branch path taken. and on-chip shared memory. so full efficiency is realized when all threads of a warp agree on their execution path. for example. allowing. The multiprocessor maps each thread to one scalar processor core. A warp executes one common instruction at a time. As thread blocks terminate. the threads converge back to the same execution path. manages. The way a block is split into warps is always the same. new blocks are launched on the vacated multiprocessors. increasing thread IDs with the first warp containing thread 0. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity.Chapter 3. To manage hundreds of threads running several different programs. (This term originates from weaving. the first parallel thread technology. It implements a single-instruction barrier synchronization. The multiprocessor SIMT unit creates. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. different warps execute independently regardless of whether they are executing common or disjointed code paths.1. When a multiprocessor is given one or more thread blocks to execute. schedules. At every instruction issue time. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and executes threads in groups of parallel threads called warps. a multithreaded instruction unit. The threads of a thread block execute concurrently on one multiprocessor. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism.

the programmer can essentially ignore the SIMT behavior. require the software to coalesce loads into vectors and manage divergence manually. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. as well as data-parallel code for coordinated threads. which is a read-only region of device memory. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. modifies. 2010 . but the order in which they occur is undefined. on the other hand. Vector architectures. A key difference is that SIMD vector organizations expose the SIMD width to the software. • The local and global memory spaces are read-write regions of device memory and are not cached. however. the number of serialized writes that occur to that location and the order in which they occur is undefined.0 SIMT architecture is akin to SIMD (Single Instruction. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. modify. scalar threads. the kernel will fail to launch. and writes to the same location in global memory for more than one of the threads of the warp. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. each read. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. If an atomic instruction executed by a warp reads. but one of the writes is guaranteed to succeed. whereas SIMT instructions specify the execution and branching behavior of a single thread. SIMT enables programmers to write thread-level parallel code for independent. If there are not enough registers or shared memory available per multiprocessor to process at least one block. which is a read-only region of device memory. For the purposes of correctness. As illustrated by Figure 3. A multiprocessor can execute as many as eight thread blocks concurrently. 14 January 24. write to that location occurs and they are all serialized. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides.PTX ISA Version 2. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. In contrast with SIMD vector machines. In practice.

Figure 3.Chapter 3. 2010 15 . Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.

0 16 January 24.PTX ISA Version 2. 2010 .

and using // to begin a comment that extends to the end of the current line. 4. The following are common preprocessor directives: #include. #define. The C preprocessor cpp may be used to process PTX source files. Comments in PTX are treated as whitespace. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. Comments Comments in PTX follow C/C++ syntax. See Section 9 for a more information on these directives. #ifdef. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #line. Source Format Source files are ASCII text.2. whitespace is ignored except for its use in separating tokens in the language. All whitespace characters are equivalent. Syntax PTX programs are a collection of text source files. #endif. PTX is case sensitive and uses lowercase for keywords. January 24. Lines beginning with # are preprocessor directives.target directive specifying the target architecture assumed. Each PTX file must begin with a . 2010 17 . #else. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.1. followed by a .version directive specifying the PTX language version. using non-nested /* and */ for comments that may span multiple lines. Pseudo-operations specify symbol and addressing management. 4.Chapter 4. #if. Lines are separated by the newline character (‘\n’).

x. The guard predicate follows the optional label and precedes the opcode. 2010 . . and is written as @p. r2. All instruction keywords are reserved tokens in PTX.reg . so no conflict is possible with user-defined identifiers. Instructions have an optional guard predicate which controls conditional execution. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.local .version .f32 array[N].b32 r1.global.1. Statements A PTX statement is either a directive or an instruction. followed by source operands.file PTX Directives . The guard predicate may be optionally negated. 18 January 24. address expressions.minnctapersm . . mov.func .3.global .PTX ISA Version 2. ld.align . where p is a predicate register. Instruction keywords are listed in Table 2.maxntid .pragma . Table 1.f32 r2.section . Directive Statements Directive keywords begin with a dot. 2. written as @!p.b32 r1. shl.b32 add.extern . r1. Operands may be register variables.entry . %tid.reg .2.3.maxnreg . The destination operand is first.5. Examples: .3. constant expressions.param . r2.tex .visible 4. or label names.loc .0 4. array[r1]. Statements begin with an optional label and end with a semicolon.b32 r1.sreg .shared .target .const . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. r2. and terminated with a semicolon.maxnctapersm .global start: . 0.

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 . Syntax Table 2.Chapter 4.

or dollar characters. PTX allows the percentage sign as the first character of an identifier. …. 2010 . PTX predefines one constant and a small number of special registers that begin with the percentage sign.g. Table 3.0 4. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. listed in Table 3. e. digits. between user-defined variable names and compiler-generated names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. %pm3 WARP_SZ 20 January 24.4. underscore. except that the percentage sign is not allowed. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. underscore. The percentage sign can be used to avoid name conflicts. Many high-level languages such as C and C++ follow similar rules for identifier names. or they start with an underscore. or percentage character followed by one or more letters. digits.PTX ISA Version 2. dollar.

Type checking rules remain the same for integer. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. integer constants are allowed and are interpreted as in C. i.e. floating-point. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.e. the constant begins with 0d or 0D followed by 16 hex digits.2. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. To specify IEEE 754 doubleprecision floating point values.5. there is no suffix letter to specify size. the constant begins with 0f or 0F followed by 8 hex digits. The syntax follows that of C. and bit-size types. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. To specify IEEE 754 single-precision floating point values. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic.. the sm_1x and sm_20 targets have a WARP_SZ value of 32. 4. For predicate-type data and instructions. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. octal. zero values are FALSE and non-zero values are TRUE. 2010 21 .s64) unless the value cannot be fully represented in . literals are always represented in 64-bit double-precision format.s64 or the unsigned suffix is specified. Constants PTX supports integer and floating-point constants and constant expressions.5. When used in an instruction or data initialization. where the behavior of the operation depends on the operand types. or binary notation. Unlike C and C++. 4.s64 or . These constants may be used in data initialization and as operands to instructions. each integer constant is converted to the appropriate size based on the data or instruction type at its use. Floating-point literals may be written with an optional decimal point and an optional signed exponent.u64). in which case the literal is unsigned (. hexadecimal. Integer literals may be written in decimal.1. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.u64. every integer constant has type .5..Chapter 4. 0[fF]{hexdigit}{8} // single-precision floating point January 24. i. Syntax 4. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

u64 .u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 .s64 .f64 integer integer integer integer integer int ?.f64 integer .s64 . 2nd is .f64 converted type .u64 .f64 converted type constant literal + ! ~ Cast Binary (. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 use usual conversions .u64 .f64 same as source .s64 .Chapter 4.u64 .s64) + .f64 use usual conversions .s64 .f64 : .s64 . .s64. or .u64 1st unchanged. Syntax 4.u64 same as 1st operand .s64 .s64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64.5.6.u64 .f64 integer .u64 zero or non-zero same as sources use usual conversions Result Type same as source . 2010 25 .f64 use usual conversions .u64) (.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero . Table 5.

PTX ISA Version 2.0 26 January 24. 2010 .

defined per-grid. private to each thread. 5.shared . .tex January 24. Kernel parameters. Name State Spaces Description Registers. Types. the kinds of resources will be common across platforms. or Function or local parameters. State Spaces. Special registers. Table 6.reg .const . Local memory. Shared. read-only memory. shared by all threads. and level of sharing between threads. 2010 27 . Global memory. defined per-thread. Global texture memory (deprecated). and properties of state spaces are shown in Table 5.1. pre-defined. The characteristics of a state space include its size. State Spaces A state space is a storage area with particular characteristics. Addressable memory shared between threads in 1 CTA. access rights. All variables reside in some state space.sreg . fast.global . platform-specific. and these resources are abstracted in PTX through state spaces and data types. Read-only. addressability. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming.local .Chapter 5. and Variables While the specific resources available in a given target GPU will vary. access speed. The list of state spaces is shown in Table 4.param .

32-. unsigned integer. and will vary from platform to platform.param (as input to kernel) . via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . For each architecture. and thread parameters.param and st.local . 32-. 2 Accessible via ld.shared .tex Restricted Yes No3 5. Registers may be typed (signed integer. scalar registers have a width of 8-. 64-.PTX ISA Version 2.reg state space) are fast storage locations. The number of registers is limited. st.param (used in functions) . Register size is restricted.const . Address may be taken via mov instruction.global .reg . 5. Registers may have alignment boundaries required by multi-word loads and stores. 1 Accessible only via the ld. The most common use of 8-bit registers is with ld. i. the parameter is then located on the stack frame and its address is in the .sreg) state space holds predefined. aside from predicate registers which are 1-bit. Special Register State Space The special register (. Register State Space Registers (. such as grid. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.2. it is not possible to refer to the address of a register. 2010 .1.param instruction.param instructions.0 Table 7. and vector registers have a width of 16-. When the limit is exceeded.local state space. or 64-bits.sreg . register variables will be spilled to memory. Registers differ from the other state spaces in that they are not fully addressable. CTA. predicate) or untyped. or 128-bits. and cvt instructions. Device function input parameters may have their address taken via mov. 28 January 24. and performance monitoring registers. floating point.. or as elements of vector tuples. causing changes in performance. platform-specific registers. 3 Accessible only via the tex instruction. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). All special registers are predefined. 16-.e.1.1. clock counters.

for example).global. as it must be allocated on a perthread basis.sync instruction are guaranteed to be visible to any reads after the barrier instruction. The remaining banks may be used to implement “incomplete” constant arrays (in C. 2010 29 . as in lock-free and wait-free style programming. By convention. 5.const) state space is a read-only memory.4. the declaration .local) is private memory for each thread to keep its own data.global to access global variables. Global State Space The global (.1. Module-scoped local memory variables are stored at fixed addresses. each pointing to the start address of the specified constant bank. It is typically standard memory with cache. // load second word 5.const[2].const[bank] modifier. Threads must be able to do their work without waiting for other threads to do theirs. Threads wait at the barrier until all threads in the CTA have arrived. If another thread sees the variable b change. where bank ranges from 0 to 10.local and st. Consider the case where one thread executes the following two assignments: a = a + 1.global) state space is memory that is accessible by all threads in a context.global. The constant memory is organized into fixed size banks. In implementations that support a stack. Use ld. the store operation updating a may still be in flight. there are eleven 64KB banks. For example. All memory writes prior to the bar. [const_buffer+4]. bank zero is used for all statically-sized constant variables. Use ld. an incomplete array in bank 2 is accessed as follows: . The size is limited. This pointer can then be used to access the entire 64KB constant bank.extern .Chapter 5.sync instruction. Global memory is not sequentially consistent.const[2] . bank zero is used.b32 %r1. For any thread in a context. results in const_buffer pointing to the start of constant bank two. If no bank number is given. Multiple incomplete array variables declared in the same bank become aliases. For example.b32 const_buffer[]. For the current devices. This reiterates the kind of parallelism available in machines that run PTX.local to access local variables. the bank number must be provided in the state space of the load instruction. and Variables 5. the stack is in local memory.5. Local State Space The local state space (. To access data in contant banks 1 through 10.1.3. initialized by the host. whereas local memory variables declared January 24.const[2] . Types. Sequential consistency is provided by the bar.extern . ld. State Spaces. b = b – 1. all addresses are in global memory are shared. It is the mechanism by which different CTAs and different grids can communicate. and atom. Banks are specified using the . where the size is not known at compile time. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. Constant State Space The constant (. st.1.b32 const_buffer[].

[%ptr]. len.1. The resulting address is in the . Note: The location of parameter space is implementation specific.6.reg . in some implementations kernel parameters reside in global memory.6. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param) state space is used (1) to pass input arguments from the host to the kernel. [N]. all local memory variables are stored at fixed addresses and recursive function calls are not supported.x supports only kernel function parameters in . In implementations that do not support a stack. per-kernel versus per-thread). 5. ld. … 30 January 24. [buffer]. The kernel parameter variables are shared across all CTAs within a grid.entry bar ( .param . PTX code should make no assumptions about the relative locations or ordering of .b32 N.u32 %n.param space variables. %n.PTX ISA Version 2.align 8 .u32 %ptr.u32 %n. Similarly.reg . mov. For example. typically for passing large structures by value to a function.1.param.param state space. 2010 .param. … Example: .0 and requires target architecture sm_20.param. ld.reg .u32 %n.param instructions.f64 %d. .param .param space. Therefore. No access protection is provided between parameter and global space in this case. ld.param . read-only variables declared in the .entry foo ( . 5. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.1. The address of a kernel parameter may be moved into a register using the mov instruction. The use of parameter state space for device function parameters is new to PTX ISA version 2. Note that PTX ISA versions 1. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. .0 within a function or kernel body are allocated on the stack. These parameters are addressable. Values passed from the host to the kernel are accessed through these parameter variables using ld.u32 %ptr. Example: . Parameter State Space The parameter (.param state space and is accessed using ld. device function parameters were previously restricted to the register state space.b32 len ) { .f64 %d.b8 buffer[64] ) { . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).param instructions. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.

call foo.align 8 . January 24.local and st. }. passed to foo … . State Spaces. the address of a function input parameter may be moved into a register using the mov instruction.param. In this case. . mystruct). … st.s32 x. dbl. This will be passed by value to a callee.f64 %d.b8 mystruct.1. … } // code snippet from the caller // struct { double d. .b8 buffer[12] ) { .s32 %y. It is not possible to use mov to get the address of a return parameter or a locally-scoped . } mystruct.align 8 . is flattened.s32 %y. and Variables 5. Types.Chapter 5. [buffer].local state space and is accessed via ld.reg .func foo ( .param and function return parameters may be written using st. . int y.6. Example: // pass object of type struct { double d. In PTX. .f64 dbl.param. and so the address will be in the .param. Typically.param space is also required whenever a formal parameter has its address taken within the called function.s32 [mystruct+8]. Aside from passing structures by value. (4. 2010 31 . . the caller will declare a locally-scoped .0 extends the use of parameter space to device function parameters.param . Device Function Parameters PTX ISA version 2.param formal parameter having the same size and alignment as the passed argument.f64 %d. st.f64 [mystruct+0]. … See the section on function call syntax for more details. ld. .param byte array variable that represents a flattened C structure or union. ld. [buffer+8]. which declares a .param. Note that the parameter will be copied to the stack if necessary.param . int y. x.param.reg .local instructions.b32 N. such as C structures larger than 8 bytes. Function input parameters may be read via ld.reg .reg .param space variable. The most common use is for passing objects by value that do not fit within a PTX register. a byte array in parameter space is used.reg .2. it is illegal to write to an input parameter or read from a return parameter.

u32 .tex) state space is global memory accessed via the texture instruction. The texture name must be of type .texref tex_a.u64.0 5. One example is broadcast.tex . and programs should instead reference texture memory through variables of type .u32 . 32 January 24.7. Example: .1. The . Texture memory is read-only. For example.1.global state space. and variables declared in the .tex . where texture identifiers are allocated sequentially beginning with zero. It is shared by all threads in a context.tex variables are required to be defined in the global scope. tex_d.tex directive is retained for backward compatibility.PTX ISA Version 2.u32 tex_a. and .tex . Multiple names may be bound to the same physical texture identifier. 5. A texture’s base address is assumed to be aligned to a 16-byte boundary.shared and st.3 for the description of the .global .shared to access shared variables.8.tex .texref. An address in shared memory can be read and written by any thread in a CTA. Physical texture resources are allocated on a per-module granularity. tex_d. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. The . Texture State Space (deprecated) The texture (. 2010 . See Section 5. tex_c. Shared memory typically has some optimizations to support the sharing.shared) state space is a per-CTA region of memory for threads in a CTA to share data. tex_f. Use ld.7. Another is sequential access from sequential threads. a legacy PTX definitions such as .texref variables in the .tex .u32 tex_a. Shared State Space The shared (. where all threads read from the same address.u32 or .tex directive will bind the named texture memory variable to a hardware texture identifier. An error is generated if the maximum number of physical resources is exceeded.6 for its use in texture instructions.u32 . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex state space are equivalent to module-scoped .texref type and Section 8. is equivalent to .

.2. In principle. or converted to other types and sizes.s16. For example.f64 types. For convenience. . Restricted Use of Sub-Word Sizes The . The same typesize specifiers are used for both variable definitions and for typing instructions.s8. .1.u8.f16.f32. .b32. . and Variables 5. and instructions operate on these types. and converted using regular-width registers.f16 floating-point type is allowed only in conversions to and from .pred Most instructions have one or more type specifiers. . but typed variables enhance program readability and allow for better operand type checking.b64 . State Spaces.f32 and . and cvt instructions. A fundamental type specifies both a basic type and a size. Fundamental Types In PTX.f64 . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . Types.Chapter 5. .b8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.b16. Operand types and sizes are checked against instruction types for compatibility. 2010 33 . and . so their names are intentionally short. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. . . Types 5.2. ld. st. The following table lists the fundamental type specifiers for each basic type: Table 8. The bitsize type is compatible with any fundamental type having the same size.u64 .s8. .2. so that narrow values may be loaded. 5.u16. all variables (aside from predicates) could be declared using only bit-size types.s32. The . .s64 .f64 types. . Register variables are always of a fundamental type. All floating-point instructions operate only on . stored. Signed and unsigned integer types are compatible if they have the same size.2. needed to fully specify instruction behavior. January 24.u32.f32 and . Two fundamental types are compatible if they have the same basic type and are the same size.b8 instruction types are restricted to ld.u8. st. the fundamental types reflect the native data types supported by the target architectures. stored.

samplerref variables. but all information about layout. .0 5.. and query instructions. sured). and Surface Types PTX includes built-in “opaque” types for defining texture.surfref. hence the term “opaque”.e. Referencing textures. or performing pointer arithmetic will result in undefined results. 34 January 24. For working with textures and samplers. Sampler. texture and sampler information each have their own handle. The three built-in types are . and overall size is hidden to a PTX program. texture and sampler information is accessed through a single . or surfaces via texture and surface load/store instructions (tex. and de-referenced by texture and surface load. These types have named fields similar to structures. but the pointer cannot otherwise be treated as an address. sampler. suld. In the independent mode. base address. and surface descriptor variables. samplers.u64} reg. sust. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. opaque_var.texref handle. suq). accessing the pointer with ld and st instructions. store. i. since these properties are defined by .PTX ISA Version 2. the resulting pointer may be stored to and loaded from memory. field ordering. In the unified mode. The following tables list the named members of each type for unified and independent texture modes. PTX has two modes of operation.{u32. passed as a parameter to functions. 2010 . allowing them to be defined separately and combined at the site of usage in the program.samplerref.3. Texture. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. and . Retrieving the value of a named member via query instructions (txq. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. In independent mode the fields of the .texref type that describe sampler properties are ignored. Creating pointers to opaque variables using mov.texref.

Types. clamp_to_border 0. clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode . and Variables Table 9. clamp_ogl. mirror. 1 ignored ignored ignored ignored . linear wrap.samplerref values N/A N/A N/A N/A nearest. State Spaces.Chapter 5. mirror. clamp_to_edge. clamp_to_border N/A N/A N/A N/A N/A . linear wrap. 2010 35 . Member width height depth Opaque Type Fields in Unified Texture Mode .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge.texref values in elements in elements in elements 0.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.texref values . 1 nearest.

global . . Example: . 36 January 24.texref my_texture_name. the types may be initialized using a list of static expressions assigning values to the named members. .texref tex1.surfref my_surface_name. these variables must be in the .samplerref my_sampler_name.param state space. filter_mode = nearest }. When declared at module scope. As kernel parameters.global .global . .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. Example: .global .PTX ISA Version 2.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global state space. these variables are declared in the . At module scope. 2010 .global .

Every variable must reside in one of the state spaces enumerated in the previous section.1.v4 .b8 v.v4 vector. Predicate variables may only be declared in the register state space. q.global . January 24. an optional initializer. Examples: . . // a length-2 vector of unsigned ints . Types. 0}. . // a length-4 vector of floats .f32 v0. an optional array size.v2.2.v4.const . 0. 1. where the fourth element provides padding. r. its name.global . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . . 5. . Examples: .struct float4 coord.u8 bg[4] = {0. 2010 37 .4.reg . .global .global . This is a common case for three-dimensional grids. Vectors Limited-length vector types are supported. Variable Declarations All storage for data is specified with variable declarations.v4 . a variable declaration describes both the variable’s type and its state space.v2 or .f64 is not allowed. .v4.struct float4 { . State Spaces. 0. .4.4.global .u32 loc.v3 }.f32 V. Vectors must be based on a fundamental type. etc.f32 bias[] = {-1. its type and size.f32 accel.Chapter 5. textures.pred p. // a length-4 vector of bytes By default. vector variables are aligned to a multiple of their overall size (vector length times base-type size).shared . to enable vector load and store instructions which require addresses aligned to a multiple of the access size. and Variables 5. for example.0. Three-element vectors may be handled by using a . // typedef . 5.0}. Vectors cannot exceed 128-bits in length.reg . In addition to fundamental types.reg . Variables In PTX. and they may reside in the register space. PTX supports types for simple aggregate objects such as vectors and arrays. and an optional fixed address for the variable.v1.u16 uv. A variable declaration names the space in which the variable resides.v2 .s32 i.v4 .

To declare an array. Array Declarations Array declarations are provided to allow the programmer to reserve space. {0.local .v4 . The size of the dimension is either a constant expression.. this can be used to initialize a jump table to be used with indirect branches or calls.shared . Initializers are allowed for all types except .1.u8 mailbox[128]. The size of the array specifies how many elements should be reserved.{. .05}..global .u32 or . or is left empty.PTX ISA Version 2. 19*19 (361) halfwords are reserved (722 bytes). being determined by an array initializer.b32 ptr = rgba. 0}. {0. . .f32 blur_kernel[][] = {{. -1}. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).0}. Variable names appearing in initializers represent the address of the variable.u64.u16 kernel[19][19]. 1} }. A scalar takes a single value.global .05}}..1.0. 2010 . Variables that hold addresses of variables or instructions should be of type . 5. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.1.{.4.4. {0. label names appearing in initializers represent the address of the next instruction following the label.0 5.05.0..global .05.1.0. // address of rgba into ptr Currently.global . {1.4.f16 and . variable initialization is supported only for constant and global state spaces. {0.s32 n = 10.0}.0.. . For the kernel declaration above. 38 January 24.3. where the variable name is followed by an equals sign and the initial value or values for the variable.4. Here are some examples: .pred. Examples: ..1}. Similarly. 0}.0}}. .u8 rgba[3] = {{1. this can be used to statically initialize a pointer to a variable.global . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.1.s32 offset[][] = { {-1.

Elements are bytes. The default alignment for vector variables is to a multiple of the overall vector size.. named %r0. say one hundred. %r99. Array variables cannot be declared this way. suppose a program uses a large number. and Variables 5. it is quite common for a compiler frontend to generate a large number of register names. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.5.b32 variables. . 2010 39 .0. Types.b8 bar[8] = {0.reg .0}. The default alignment for scalar and array variables is to a multiple of the base-type size.6.2. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.0. of . Alignment is specified using an optional . For arrays.b32 %r<100>. Rather than require explicit declaration of every name.0.align 4 . These 100 register variables can be declared as follows: . …. alignment specifies the address alignment for the starting address of the entire array. Parameterized Variable Names Since PTX supports virtual registers. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. For example. 5. %r1.4.0. The variable will be aligned to an address which is an integer multiple of byte-count. nor are initializers permitted.Chapter 5.align byte-count specifier immediately following the state-space specifier. // declare %r0.. State Spaces. and may be preceded by an alignment specifier. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. not for individual elements. %r1. January 24.const . Examples: // allocate array at 4-byte aligned address.0.4. ..

2010 .PTX ISA Version 2.0 40 January 24.

Source Operands The source operands are denoted in the instruction descriptions by the names a. Integer types of a common size are compatible with each other. Each operand type must be compatible with the type determined by the instruction template and instruction type. Predicate operands are denoted by the names p. s. There is no automatic conversion between types. q. mov. The ld. The bit-size type is compatible with every type having the same size. and a few instructions have additional predicate source operands. Operand Type Information All operands in instructions have a known type from their declarations.2. January 24. st. The result operand is a scalar or vector variable in the register state space. . 2010 41 . r. Most instructions have an optional predicate guard that controls conditional execution. and c.1. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The cvt (convert) instruction takes a variety of operand types and sizes. The mov instruction copies data between registers. as its job is to convert from nearly any data type to any other data type (and size). Instruction Operands 6. so operands for ALU instructions must all be in variables declared in the . For most operations. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Instructions ld and st move data from/to addressable state spaces to/from registers. PTX describes a load-store machine.3. the sizes of the operands must be consistent. 6. b. 6. and cvt instructions copy data from one location to another.Chapter 6.reg register state space.

.v4 .const . and Vectors Using scalar variables as operands is straightforward. Examples include pointer arithmetic and pointer comparisons. .v4. . .reg .s32 q. [V].PTX ISA Version 2.4.4.reg .f32 ld.shared. p. Load and store operations move data between registers and locations in addressable state spaces. arrays.f32 V.gloal. address registers.u16 ld.global .0 6.u16 x. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.const. The syntax is similar to that used in many assembly languages. and immediate address expressions which evaluate at compile-time to a constant address. The address is an offset in the state space in which the variable is declared. [tbl+12]. Address expressions include variable names. 6.1. Here are a few examples: .s32 mov. tbl. The mov instruction can be used to move the address of a variable into a pointer.shared .b32 p. r0. 2010 .[x]. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. Arrays.f32 W.reg . All addresses and address computations are byte-based. The interesting capabilities begin with addresses. there is no support for C-style pointer arithmetic.v4 . q. .u16 r0.reg . and vectors. . W.u32 42 January 24. address register plus byte offset. Using Addresses.s32 tbl[256]. ld.

d}. b. Array elements can be accessed using an explicitly calculated byte address. or by indexing into the array using square-bracket notation.global.reg .x.r.c. a[1]. Vectors as Operands Vector operands are supported by a limited subset of instructions. V.u32 s.f32 {a. V2. [addr+offset2].x V.v4.u32 {a. A brace-enclosed list is used for pattern matching to pull apart vectors. c. Rc. The size of the array is a constant in the program. 2010 43 . mov.a 6. ld. a[0].3.global.c. Rb. January 24. [addr+offset].u32 s. Vectors may also be passed as arguments to called functions. or a simple “register with constant offset” expression. st.d}.global. where the offset is a constant expression that is either added or subtracted from a register variable.b V. The expression within square brackets is either a constant integer. d.g V. or a braceenclosed list of similarly typed scalars. . .u32 s.b.r V. Elements in a brace-enclosed vector. mov. Instruction Operands 6.w. as well as the typical color fields . say {Ra. ld. for use in an indirect branch or call. it must be written as an address calculation prior to use. Vector elements can be extracted from the vector with the suffixes . correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.v2. a register variable.4.4. . a[N-1].f32 V.f32 a. If more complicated indexing is desired.v4.Chapter 6. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.y. and tex.f32 ld. .4. The registers in the load/store operations can be a vector. and in move instructions to get the address of the label or function into a register. Vector loads and stores can be used to implement wide loads and stores.z V.reg . Here are examples: ld. .a.4. Arrays as Operands Arrays of all types can be declared.w = = = = V.z and . // move address of a[1] into s 6. Examples are ld. Rd}.b and .y V. which may improve memory performance. which include mov.g.b.global.v4 . and the identifier becomes an address constant in the space where the array is declared.2. .

5.000 for f16). 44 January 24. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. and data movement instruction must be of the same type and size. except for operations where changing the size and/or type is part of the definition of the instruction. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.PTX ISA Version 2.u16 instruction is given a u16 source operand and s32 as a destination operand. if a cvt. Type Conversion All operands to all arithmetic.1.5. and ~131. the u16 is zero-extended to s32. 2010 . For example.0 6. logic. 6.s32. Operands of different sizes or types must be converted prior to the operation.

s2f = signed-to-float.s16. Notes 1 If the destination register is wider than the destination format. zext = zero-extend. chop = keep only low bits that fit. January 24. For example. the result is extended to the destination register width after chopping. The type of extension (sign or zero) is based on the destination format. u2f = unsigned-to-float. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. 2010 45 . f2u = float-to-unsigned.Chapter 6.u32 targeting a 32-bit register will first chop to 16-bits. cvt. Instruction Operands Table 11. f2s = float-to-signed. then sign-extend to 32-bits. f2f = float-to-float.

2.PTX ISA Version 2.0 6. Table 12.rzi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. In PTX.5.rz .rmi . choosing even integer if source is equidistant between two integers. there are four integer rounding modifiers and four floating-point rounding modifiers.rn .rni .rm . 2010 . Rounding Modifiers Conversion instructions may specify a rounding modifier. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rpi Integer Rounding Modifiers Description round to nearest integer. Modifier . The following tables summarize the rounding modifiers. Modifier .

first access is high Notes January 24. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution.6.Chapter 6. Much of the delay to memory can be hidden in a number of ways. while global memory is slowest. Registers are fastest. Operand Costs Operands from different state spaces affect the speed of an operation. Instruction Operands 6. Table 14. Table 11 gives estimates of the costs of using different kinds of memory. The register in a store operation is available much more quickly. Another way to hide latency is to issue the load instructions as early as possible. 2010 47 .

PTX ISA Version 2. 2010 .0 48 January 24.

} … call foo. and return values may be placed directly into register variables. In this section. Execution of the ret instruction within foo transfers control to the instruction following the call. arguments may be register variables or constants. stack layout. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. or prototype. and memory allocated on the stack (“alloca”). Scalar and vector base-type input and return parameters may be represented simply as register variables. function calls. the function name. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. A function declaration specifies an optional list of return parameters. support for variadic functions (“varargs”).Chapter 7. 7.1.func directive. The simplest function has no parameters or return values. A function must be declared or defined prior to being called. together these specify the function’s interface. 2010 49 . implicitly saving the return address. parameter passing.func foo { … ret. January 24. execution of the call instruction transfers control to foo. we describe the features of PTX needed to achieve this hiding of the ABI. stack-based ABI. These include syntax for function definitions. and an optional list of input parameters. and is represented in PTX as follows: . and Application Binary Interface (ABI). Abstracting the ABI Rather than expose details of a particular calling convention. … Here. functions are declared and defined using the . so recursion is not yet supported. NOTE: The current version of PTX does not implement the underlying. Function declarations and definitions In PTX. At the call. A function definition specifies both the interface and the body of the function.

c4.4). ld. [y+8]. %ptr.param.u32 %res) inc_ptr ( . passed by value to a function: struct { double dbl. py). the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . 2010 .param. c3. [y+9].b8 c3.func (. %inc.param space variables are used in two ways.align 8 py[12].reg . char c[4].reg .reg . ld. … st.param.b8 [py+11]. st.param . Since memory accesses are required to be aligned to a multiple of the access size. In PTX. ret.param.c2.param. … … // computation using x.u32 %ptr.b64 [py+ 0]. inc_ptr.s32 x. .c1. ld.f64 f1.param. bumpptr. First. Second. [y+0].reg . a . … In this example.b8 .param. ld. this structure will be flattened into a byte array.b32 c1. … ld. }.f64 f1. (%r1.0 Example: . The .c3. %rd. 50 January 24.b8 [py+10]. %rc1. byte array in .u32 %res.reg space.param state space is used to pass the structure by value: . %rc2.param. (%x. %rc1.s32 out) bar (.PTX ISA Version 2. // scalar args in . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .b8 .reg .param. [y+10].f64 field are aligned.param.b8 c1.b8 [py+ 9]. st.b8 [py+ 8].u32 %inc ) { add.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.param . st.c4. note that . consider the following C structure. . For example. } { .reg .b8 c2.func (. } … call (%r1).align 8 y[12]) { .param space call (%out). .param space memory. [y+11].f1.b8 c4. %rc2.param variable y is used in function definition bar to represent a formal parameter. st. c2.reg . a .

param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. • • Arguments may be . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.reg space variable of matching type and size.param and ld. 8. • The .param variables. • • • For a callee.param arguments.reg variables.param state space use in device functions.param or .param space formal parameters that are byte arrays. all st. size.reg space formal parameters.reg variables.param variables or .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. or a constant that can be represented in the type of the formal parameter.param space formal parameters that are base-type scalar or vector variables. Supporting the .. and alignment. and alignment of parameters.reg state space in this way provides legacy support. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. the corresponding argument may be either a .g.Chapter 7. Note that the choice of .param state space is used to receive parameter values and/or pass return values back to the caller.reg or . the argument must also be a . This enables backend optimization and ensures that the .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. January 24. Typically. or constants. For a caller.param instructions used for argument passing must be contained in the basic block with the call instruction. the corresponding argument may be either a . In the case of . A . 2010 51 . a . size. or 16 bytes.param or .reg state space can be used to receive and return base-type scalar and vector values. 4. . In the case of . The .param byte array is used to collect together fields of a structure being passed by value. Abstracting the ABI The following is a conceptual way to think about the . For .param argument must be declared within the local scope of the caller.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The following restrictions apply to parameter passing. Parameters in .param space byte array with matching type. • • • Input and return parameters may be . • The .param memory must be aligned to a multiple of 1. In the case of .reg space variable with matching type and size. or a constant that can be represented in the type of the formal parameter. The . For a caller. 2. For a callee.

and there was no support for array parameters.1. formal parameters were restricted to .reg or .0 continues to support multiple return registers for sm_1x targets. PTX 2. and a .x In PTX ISA version 1.0 restricts functions to a single return value. formal parameters may be in either .reg state space.x. In PTX ISA version 2. 2010 .1. and . For sm_2x targets.0 7. PTX 2.param space parameters support arrays. Changes from PTX 1. 52 January 24. PTX 1. Objects such as C structures were flattened and passed or returned using multiple registers.param byte array should be used to return objects that do not fit into a register.PTX ISA Version 2.param state space.0.x supports multiple return values for this purpose.

The function prototypes are defined as follows: .reg . iteratively access. mov. . the alignment may be 1.reg .reg . %s2). maxN.u32 a.2. or 4 bytes.reg .reg .u32 N.Chapter 7.s32 result ) maxN ( . setp.u32 sz.u32 sz. for %va_arg64.u32 ptr.h headers in C. or 16 bytes. val. %r3). %s1.u32. %r1. following zero or more fixed parameters: . or 8 bytes. In both cases.b32 val) %va_arg (.u32 ap. %va_end is called to free the variable argument list handle. call (val). call %va_end. N.u32 align) . 0x8000000. … ) . } … call (%max). 2.func (.ge p. %va_arg.func (. ctr.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg . 8.h and varargs. ctr. Abstracting the ABI 7. bra Done.reg . the size may be 1.. maxN. 4. %r2.func okay ( … ) Built-in functions are provided to initialize. . along with the size and alignment of the next data value to be accessed.reg . ) { .b32 result.b64 val) %va_arg64 (. … %va_start returns Loop: @p Done: January 24.reg .u32 ptr.reg . This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg .reg .s32 val. // default to MININT mov. %va_start.func ( . .u32 align) . For %va_arg. . .reg . (2.b32 ctr. max. (ap). 4.func (. 2. Variadic functions NOTE: The current version of PTX does not support variadic functions.reg .func %va_end (. … call (%max). (ap. . result.u32 b.u32 ptr) %va_start .s32 result.reg . bra Loop. To support functions with a variable number of arguments. call (ap). the size may be 1. 2010 53 . 2.reg . variadic functions are declared with an ellipsis at the end of the input parameter list.func baz ( . ret. 4). 0. PTX provides a high-level mechanism similar to the one provided by the stdarg. and end access to a list of variable arguments.. 4. (3. . In PTX. Once all arguments have been processed.reg . . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .pred p.

PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.3.0 7.u32 ptr ) %alloca ( . Alloca NOTE: The current version of PTX does not support alloca.reg . To allocate memory.local and st. 54 January 24.reg . If a particular alignment is required. defined as follows: .PTX ISA Version 2. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. The array is then accessed with ld. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. 2010 . a function simply calls the built-in function %alloca.func ( .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.local instructions.

B. A. PTX Instructions PTX instructions generally have from zero to four operands. opcode D. 2010 55 . plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. q = !(a < b). followed by some examples that attempt to show several possible instantiations of the instruction. The setp instruction writes two destination registers.lt p|q. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. Instruction Set 8. January 24.s32. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. a. opcode A. the semantics are described. C. We use a ‘|’ symbol to separate multiple destination registers. A. 8. b. setp.1. For some instructions the destination operand is optional. the D operand is the destination operand. In addition to the name and the format of the instruction. opcode D. while A. For instructions that create a result value. B.Chapter 8. opcode D. A.2. // p = (a < b). B. and C are the source operands.

predicate registers can be declared as . To implement the above example as a true conditional branch.0 8. n. q. Predicated Execution In PTX. As an example. add 1 to j To get a conditional branch or conditional function call.PTX ISA Version 2. 2010 . the following PTX instruction sequence might be used: @!p L1: setp. This can be written in PTX as @p setp. Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 p. optionally negated. Instructions without a guard predicate are executed unconditionally. use a predicate to control the execution of the branch or call instructions. branch over 56 January 24. i.3. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. So.s32 j. j. 1. j.s32 p.pred p. 1. i. add. where p is a predicate variable.pred as the type specifier.lt.s32 j. consider the high-level code if (i < n) j = j + 1. // p = (i < n) // if i < n. … // compare i to n // if false. n. predicate registers are virtual and have . add. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.reg .lt. bra L1.

1. the result is false. 2010 57 . Unsigned Integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. The unsigned comparisons are eq. ne (not-equal). ge. lt. gt. The bit-size comparisons are eq and ne. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.Chapter 8. The following table shows the operators for signed integer. and bitsize types.1. Table 16. and hs (higher-or-same).2.3. unsigned integer. ne. Table 15. le (less-than-or-equal). If either operand is NaN.1. lt (less-than). ls (lower-or-same).3. ordering comparisons are not defined for bit-size types. Comparisons 8. and ge (greater-than-or-equal).3. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). hi (higher). Instruction Set 8. ne. le. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. lo (lower). gt (greater-than).1. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.

and mov. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8.1. leu.%p. There is no direct conversion between predicates and integer values. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. Table 17. or. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.u32 %r1. not. neu. However.0. gtu.PTX ISA Version 2. geu. If either operand is NaN. setp can be used to generate a predicate from an integer.3. num returns true if both operands are numeric values (not NaN). // convert predicate to 32-bit value 58 January 24. xor. for example: selp. 2010 .0 To aid comparison operations in the presence of NaN values. then these comparisons have the same result as their ordered counterparts. unordered versions are included: equ. and no direct way to load or store predicate register values. Table 18.2. and nan returns true if either operand is NaN. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. then the result of these comparisons is true. ltu. If both operands are numeric values (not NaN). two operators num (numeric) and nan (isNaN) are provided.

u16 a. and integer operands are silently cast to the instruction type if needed.bX . a. Type Checking Rules Operand Type . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. cvt.sX ok ok ok inv .f32 d.u16 d. the add instruction requires type and size information to properly perform the addition operation (signed. 2010 59 . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. Signed and unsigned integer types agree provided they have the same size.sX . For example: . For example.u16 d. • The following table summarizes these type checking rules. b. they must match exactly.fX ok ok ok ok January 24. a. It requires separate type-size modifiers for the result and source.reg .reg . a. add. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.uX .f32.Chapter 8.. . Floating-point types agree only if they have the same size.4.uX ok ok ok inv . i.bX . different sizes).fX ok inv inv ok Instruction Type .reg . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. Example: . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. b. and these are placed in the same order as the operands. and this information must be specified as a suffix to the opcode. most notably the data conversion instruction cvt. For example. Table 19. float.u16 d. unsigned.e. Instruction Set 8.

the data will be truncated. so those rows are invalid for cvt.bX instruction types. the cvt instruction does not support . 1. stored. When a source operand has a size that exceeds the instruction-type size. Floating-point source registers can only be used with bit-size or floating-point instruction types.4. or converted to other types and sizes. For example. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. no conversion needed. the size must match exactly. 4. When used with a floating-point instruction type. Notes 3. for example. so that narrow values may be loaded. 2010 . Table 20. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Note that some combinations may still be invalid for a particular instruction. inv = invalid. 2. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize.PTX ISA Version 2. ld.1. Operand Size Exceeding Instruction-Type Size For convenience. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. unless the operand is of bit-size type. Bit-size source registers may be used with any appropriately-sized instruction type. The data is truncated to the instruction-type size and interpreted according to the instruction type. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. parse error. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. st. 60 January 24. stored. and converted using regular-width registers. Source register size must be of equal or greater size than the instruction-type size.0 8. “-“ = allowed. floating-point instruction types still require that the operand type-size matches exactly. When used with a narrower bit-size type. The following table summarizes the relaxed type-checking rules for source operands.

Floating-point destination registers can only be used with bit-size or floating-point instruction types. The following table summarizes the relaxed type-checking rules for destination operands. If the corresponding instruction type is signed integer. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Table 21. 2010 61 . 2. the size must match exactly.or sign-extended to the size of the destination register. and is zero-extended to the destination register width otherwise. 1. zext = zero-extend. When used with a floatingpoint instruction type. the data is zeroextended. January 24. inv = Invalid. Destination register size must be of equal or greater size than the instruction-type size. Bit-size destination registers may be used with any appropriately-sized instruction type. The data is signextended to the destination register width for signed integer instruction types. 4. parse error. The data is sign-extended to the destination register width for signed integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. When used with a narrower bit-size instruction type. Notes 3. “-“ = Allowed but no conversion needed. otherwise. the destination data is zero.Chapter 8. the data will be zero-extended. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. the data is sign-extended.

However. At the PTX language level. for example. using the . 16-bit registers in PTX are mapped to 32-bit physical registers. until they come to a conditional control construct such as a conditional branch. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. at least in appearance.6. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. a compiler or code author targeting PTX can ignore the issue of divergent threads. the optimizing code generator automatically determines points of re-convergence.6.PTX ISA Version 2. the semantics of 16-bit instructions in PTX is machine-specific. for many performance-critical applications. the threads are called uniform. These extra precision bits can become visible at the application level. Both situations occur often in programs.5. so it is important to have divergent threads re-converge as soon as possible. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 2010 . and 16-bit computations are “promoted” to 32-bit computations. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Divergence of Threads in Control Constructs Threads in a CTA execute together. the threads are called divergent. A compiler or programmer may chose to enforce portable. until C is not expressive enough. this is not desirable. If all of the threads act in unison and follow a single control flow path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. or conditional return.1. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. by a right-shift instruction. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. and for many applications the difference in execution is preferable to limiting performance.0 8. When executing on a 32-bit data path. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible.uni suffix. Therefore. The semantics are described using C. For divergent control flow. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. 62 January 24. If threads execute down different control flow paths. 8. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. 8. conditional function call.

8.Chapter 8. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8.cc. In the following descriptions.1.7. addc sub. the optional guard predicate is omitted from the syntax.cc. 2010 63 .7. Instructions All PTX instructions may be predicated. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. The Integer arithmetic instructions are: add sub add.

sat limits result to MININT. b. Saturation modifier: . 2010 . . b. .MAXINT (no overflow) for the size of the operation.s32 d.s32 d.sat applies only to .u16. a. b. // . Introduced in PTX ISA version 1.0. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.u64.s32 c.u32. .s64 }.a.sat applies only to .type add{.sat. d. // . b.0 Table 22. .s32 . d. Introduced in PTX ISA version 1.z. @p add.MAXINT (no overflow) for the size of the operation. d = a + b. sub. PTX ISA Notes Target ISA Notes Examples Table 23.s16.y.s32 type. add.s32. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.type = { .u32.s64 }.. PTX ISA Notes Target ISA Notes Examples 64 January 24. Description Semantics Notes Performs addition and writes the resulting value into a destination register.c. Applies only to .u64. d = a – b.0. add.u32 x.b.type sub{. Saturation modifier: . a. . . add Syntax Integer Arithmetic Instructions: add Add two values.PTX ISA Version 2. Supported on all target architectures. sub. .type = { . a. Supported on all target architectures.s32 type. ..sat}. .1. a. Applies only to .s32 .s32.sat limits result to MININT.s32 c. .sat}.u16.s16.

x4. if .type = { .Chapter 8. and there is no support for setting. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.cc.cc Syntax Integer Arithmetic Instructions: add.cc.y4. . 2010 65 .cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. x2.z4.b32 addc. add. No other instructions access the condition code.cc Add two values with carry-out.type d.type d.b32 addc. clearing.cc.s32 }.y2. x3.y1.2. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.CF No integer rounding modifiers.b32 addc. b. Introduced in PTX ISA version 1.b32 addc.z2.cc. carry-out written to CC.cc. .u32.z3. x3. or testing the condition code. add. x4.cc specified.b32 addc.type = {. Supported on all target architectures. No saturation.z4. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.z1.CF) holding carry-in/carry-out or borrowin/borrow-out. Behavior is the same for unsigned and signed integers. @p @p @p @p add.u32. @p @p @p @p add.b32 x1.CF No integer rounding modifiers. d = a + b. addc{.y3.y3. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. b. a.cc.y1. Supported on all target architectures.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. d = a + b + CC.b32 addc.y2. sub. Instruction Set Instructions add. Behavior is the same for unsigned and signed integers.cc.cc. No saturation. carry-out written to CC. .z1.cc}. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. addc.cc. These instructions support extended-precision integer addition and subtraction.b32 x1. x2. Introduced in PTX ISA version 1. .z3.CF. Table 24.s32 }.2.y4.z2. a.

Introduced in PTX ISA version 1.cc specified.type d.z4.y4.cc. d = a – b.b32 x1.b32 subc.u32.b32 subc. b. . // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.type = { . sub.y2.CF No integer rounding modifiers. @p @p @p @p sub.y1. borrow-out written to CC. 2010 . Behavior is the same for unsigned and signed integers. . . x4.cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. No saturation. b. x3.z2. No saturation. x4. sub. x2.s32 }. Supported on all target architectures. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. a.s32 }.cc}.3.type d.cc. borrow-out written to CC.CF No integer rounding modifiers.cc Syntax Integer Arithmetic Instructions: sub.cc.y4.z4.y2.b32 subc.cc. withborrow-in and optional borrow-out.z2. d = a . a.y3.b32 subc.cc. @p @p @p @p sub. Introduced in PTX ISA version 1. with borrow-out. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y3. x3.3.CF).u32. subc{.cc.z1.0 Table 26. Behavior is the same for unsigned and signed integers.PTX ISA Version 2.type = {. if .(b + CC. Supported on all target architectures.z1.cc.y1. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.b32 x1.z3.cc Subract one value from another. .cc. x2.b32 subc.b32 subc.z3.

wide is specified. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. mul. The . If .fxs.lo is specified. mul.y. save only the low 16 bits // 32*32 bits.u32.wide}.wide.s64 }.0>. d = t<n-1.u64. .type d. If .. // 16*16 bits yields 32 bits // 16*16 bits.fxs.s32 z. . . .. then d is twice as wide as a and b to receive the full result of the multiplication.lo variant Notes The type of the operation represents the types of the a and b operands. 2010 67 .and 32-bit integer types.s32..0.type = { .hi. then d is the same size as a and b.lo. t = a * b.u16.hi variant // for .s16. d = t. a. mul{. n = bitwidth of type. // for .lo.fys. Instruction Set Table 28. . Description Semantics Compute the product of two values. .Chapter 8. and either the upper or lower half of the result is written to the destination register.hi or . creates 64 bit result January 24.x. Supported on all target architectures.wide suffix is supported only for 16. mul.s16 fa.. d = t<2n-1.wide. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.n>.fys.wide // for .s16 fa.

b. bitwidth of type.wide}. @p mad. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and either the upper or lower half of the result is written to the destination register. .lo is specified.0> + c. Saturation modifier: .. a. . Description Semantics Multiplies two values and adds a third.wide // for .hi or .s32 type in .type = { .and 32-bit integer types. a. Supported on all target architectures.lo. t<n-1.b.lo. t n d d d = = = = = a * b.wide suffix is supported only for 16.sat.MAXINT (no overflow) for the size of the operation.0 Table 29.q. The . c.lo.p.hi mode. c.hi. // for .type mad.s16. mad{. .n> + c. b. t + c.u32.s32.u64. d.sat limits result to MININT. .a.wide is specified. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. mad.hi variant // for ..lo variant Notes The type of the operation represents the types of the a and b operands.PTX ISA Version 2. t<2n-1.. . If .hi.0. then d and c are the same size as a and b.u16..s32 d.s32 r. then d and c are twice as wide as a and b to receive the result of the multiplication. If .s32 d.r. 2010 .s64 }.. . and then writes the resulting value into a destination register. Applies only to .c. 68 January 24.

hi variant // for . mul24{. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. Instruction Set Table 30. mul24.Chapter 8. d = t<47.type d..hi may be less efficient on machines without hardware support for 24-bit multiply. .a. a.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. mul24. t = a * b.type = { .s32 }..lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. b.0>.lo. .u32. Supported on all target architectures. January 24. 48bits. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. // for . // low 32-bits of 24x24-bit signed multiply.s32 d. mul24. i. d = t<31.. mul24. All operands are of the same type and size.16>. and return either the high or low 32-bits of the 48-bit result.e.lo}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 69 .0.hi.b.

lo.. 32-bit value to either the high or low 32-bits of the 48-bit result.hi may be less efficient on machines without hardware support for 24-bit multiply. a. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. 70 January 24. c.0.PTX ISA Version 2. d.s32 d.MAXINT (no overflow).sat. and add a third. // low 32-bits of 24x24-bit signed multiply. Return either the high or low 32-bits of the 48-bit result. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 . Saturation modifier: .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. c. All operands are of the same type and size. mad24{. Applies only to . mad24. .0 Table 31. t = a * b. mad24.16> + c. b. // for .s32 }.b.e. Supported on all target architectures.a.c.0> + c.s32 d. d = t<31. d = t<47. Description Compute the product of two 24-bit integer values held in 32-bit source registers.. i.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.lo}..u32.hi. 48bits. .lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. a. mad24..type mad24. mad24.sat limits result of 32-bit signed addition to MININT.type = { .hi mode.s32 type in .hi. b.hi variant // for .

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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the number of leading zeros is between 0 and 32. clz.b32 type.type == .type d. X. clz. a. popc requires sm_20 or later. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.0 Table 39. X.type = { . cnt.type d. } while (d < max && (a&mask == 0) ) { d++. . mask = 0x8000000000000000.0.b32 clz. inclusively.b32 popc. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz requires sm_20 or later. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.u32 PTX ISA Notes Target ISA Notes Examples Table 40. a. For .b64 type.b64 d. . if (. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.b32) { max = 32. mask = 0x80000000.b64 d. the number of leading zeros is between 0 and 64. // cnt is .b32. } else { max = 64. popc Syntax Integer Arithmetic Instructions: popc Population count. . For . d = 0.b32. a = a << 1.0. a.PTX ISA Version 2. 2010 . inclusively. popc. while (a != 0) { if (a&0x1) d++.b64 }. a. // cnt is . a = a >> 1. } Introduced in PTX ISA version 2. popc.type = { . d = 0.b64 }. . cnt.u32 Semantics 74 January 24.

type d.shiftamt is specified. bfind. i--) { if (a & (1<<i)) { d = i.s64 cnt. Semantics msb = (. If . a.type bfind.u32. Instruction Set Table 41. break.s32. bfind returns the bit position of the most significant “1”.u32 January 24. // cnt is .u32.u32 || .type = { . bfind returns 0xFFFFFFFF if no non-sign bit is found. i>=0. bfind.s32) ? 31 : 63.shiftamt. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. } } if (.s64 }. d. For signed integers. For unsigned integers.d.type==. Operand a has the instruction type.u64.Chapter 8.u32 d.shiftamt. . bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. d = -1. bfind requires sm_20 or later.0. a. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind.type==. and operand d has type . . a. for (i=msb. 2010 75 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. X.shiftamt && d != -1) { d = msb . . .

b32 d. .0 Table 42.type==. for (i=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 76 January 24. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. a.type d.type = { .0. i<=msb. Description Semantics Perform bitwise reversal of input. brev requires sm_20 or later.b32) ? 31 : 63. brev.b64 }. brev. msb = (.PTX ISA Version 2. a. .b32. 2010 . i++) { d[i] = a[msb-i].

.Chapter 8.u32. January 24. .u64 || len==0) sbit = 0.u32.start. if (. pos = b.u32. .msb)].type==. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.type==. Instruction Set Table 43. . a. i<=msb. 2010 77 . The sign bit of the extracted field is defined as: .a.b32 d. c. The destination d is padded with the sign bit of the extracted field. Operands a and d have the same type as the instruction type. Source b gives the bit field starting bit position.type==. bfe requires sm_20 or later.0.u32 || . and operands b and c are type . and source c gives the bit field length in bits. bfe. the result is zero. . If the start position is beyond the msb of the input. d = 0. b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the destination d is filled with the replicated sign bit of the extracted field.s32) ? 31 : 63. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u32 || . .type d. len = c. otherwise If the bit field length is zero.s32.len.type==.type = { .u64: . else sbit = a[min(pos+len-1.s64 }.u64.s32. bfe. for (i=0. Description Extract bit field from a and place the zero or sign-extended result in d. Semantics msb = (.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.

. bfi.start.PTX ISA Version 2. b. bfi.b32 d. b. a. for (i=0. Semantics msb = (.type = { .type f.u32. the result is b.0. and place the result in f. Source c gives the starting bit position for the insertion. If the bit field length is zero. d. bfi requires sm_20 or later.0 Table 44. pos = c. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. Description Align and insert a bit field from a into b. If the start position is beyond the msb of the input. len = d.b64 }. i<len && pos+i<=msb. 78 January 24. and source d gives the bit field length in bits. f = b. and f have the same type as the instruction type. Operands a. and operands c and d are type . c.b32.type==. 2010 . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.a.b32) ? 31 : 63.b. i++) { f[pos+i] = a[i]. . the result is b.len.

b1. . b4}. Note that the sign extension is only performed as part of generic form. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. In the generic form (no mode specified). the four 4-bit values fully specify an arbitrary byte permute. b5.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.Chapter 8.ecl.b1 source select c[7:4] d. default mode index d.b32{. a. a} = {{b7. For each byte in the target register.rc16 }. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.b4e. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. Description Pick four arbitrary bytes from two 32-bit registers. a 4-bit selection value is defined. Instruction Set Table 45. b6. . 2010 79 . the permute control consists of four 4-bit selection values. msb=0 means copy the literal value. {b3. . The bytes in the two source registers are numbered from 0 to 7: {b.ecr. Thus.mode} d. as a 16b permute code. prmt. .b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. The msb defines if the byte value should be copied. and reassemble them into a 32-bit destination register.rc8. msb=1 means replicate the sign. . b. b2.b2 source select c[11:8] d.f4e.b3 source select c[15:12] d. . b0}}. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). c.mode = { .b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.

r3.PTX ISA Version 2. r2. tmp[15:08] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp[31:24] = ReadByte( mode. tmp64 ). tmp64 ). ctl[1]. ctl[3] = (c >> 12) & 0xf. ctl[1] = (c >> 4) & 0xf. ctl[2] = (c >> 8) & 0xf. r1. ctl[0]. 2010 . r2. r4. tmp64 ). ctl[3]. prmt. tmp[23:16] = ReadByte( mode. } tmp[07:00] = ReadByte( mode. prmt requires sm_20 or later. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.0 Semantics tmp64 = (b<<32) | a. 80 January 24. tmp64 ).0.f4e r1.b32. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[2]. r3.b32 prmt. r4.

Chapter 8.f32 and .f64 register operands and constant immediate values. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2. 2010 81 .7. Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8.

default is .sqrt}.sat Notes If no rounding modifier is specified. .sub.f32 {div.cos.PTX ISA Version 2.f64 mad. and mad support saturation of results to the range [0.rz .f64 rsqrt.neg.approx.f32 rsqrt.f32 {mad. mul.sqrt}.approx.ftz .ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.f32 .f32 {abs.rnd.fma}.rcp. sub.ex2}. 1. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f32 {add. default is .f64 are the same.f64 and fma.0.f64 {abs.full. Instruction Summary of Floating-Point Instructions . but single-precision instructions return an unspecified NaN.rm .max}.f64 {sin.min.rnd.sqrt}.f64 div.rp . {mad. The optional .fma}.max}.rcp.f32 {div. so PTX programs should not rely on the specific single-precision NaNs being generated.f32 are the same. NaN payloads are supported for double-precision instructions. Double-precision instructions support subnormal inputs and results.min.rn and instructions may be folded into a multiply-add.lg2. No rounding modifier.target sm_20 .rn .32 and fma. 2010 .0]. If no rounding modifier is specified. Single-precision add. 82 January 24.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.rnd.rcp. with NaNs being flushed to positive zero.approx.approx.f32 {div.sub.target sm_20 mad.neg.rnd.rn and instructions may be folded into a multiply-add.target sm_1x No rounding modifier.rnd. .f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. Note that future implementations may support NaN payloads for single-precision instructions.0 The following table summarizes floating-point instructions in PTX.rnd. Table 46.mul}.mul}. {add.

f64 }.f64 isnan.subnormal }.type .normal testp. a.notanumber.infinite. testp Syntax Floating-Point Instructions: testp Test floating-point property.f64 }. Instruction Set Table 47. testp requires sm_20 or later. copysign requires sm_20 or later. and return the result as d. . not infinity). Table 48.f32.pred = { . B.normal. . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f32.f32 testp. . .finite.op p.finite testp. copysign. 2010 83 .f32 copysign. . C. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . positive and negative zero are considered normal numbers.type = { . Introduced in PTX ISA version 2. January 24.op.Chapter 8.notanumber testp. A.infinite testp. b. a. testp. .0.f64 x. testp. .number testp. f0. p. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.0.type = { .number. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. testp.infinite. z.notanumber. . copysign. X. true if the input is a subnormal number (not NaN.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.type d. y. // result is . not infinity) As a special case.

In particular.0. 84 January 24. subnormal numbers are supported. add.rn.f32 add{.f32 f1. b.sat}. requires sm_13 for add.0].rnd}{. 1. add{. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rz.rn): . add Syntax Floating-Point Instructions: add Add two values. .PTX ISA Version 2. Rounding modifiers (default is . sm_1x: add. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64 d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rp }.f32 clamps the result to [0. .rn mantissa LSB rounds to nearest even .0 Table 49. a. Description Semantics Notes Performs addition and writes the resulting value into a destination register.rnd}. d = a + b. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rm.f32 supported on all target architectures.rm mantissa LSB rounds towards negative infinity . requires sm_20 Examples @p add. .f2. . Rounding modifiers have the following target requirements: . a.0. .rz mantissa LSB rounds towards zero . NaN results are flushed to +0.f32.rn.rnd = { . b.ftz}{. add.f64 requires sm_13 or later.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.rz.0f.rm. add. 2010 . add.rp for add.ftz. Saturation modifier: . . add.rz available for all targets . d.f64.sat.ftz.f3.

sub.ftz.rn. sub.rm. requires sm_20 Examples sub. .rn. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 supported on all target architectures.sat.0f. Saturation modifier: sub.0].f32 flushes subnormal inputs and results to sign-preserving zero.0.rz available for all targets .f64 supports subnormal numbers. b. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32.f2.f64 requires sm_13 or later. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. In particular. .f64 d.f32 c. a. sub. sub. January 24.rz. Rounding modifiers have the following target requirements: .f32 clamps the result to [0. . sm_1x: sub.f32 f1. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. b.rm. Rounding modifiers (default is . 1. sub{.rn. sub Syntax Floating-Point Instructions: sub Subtract one value from another.rnd = { .rnd}. Instruction Set Table 50.rz mantissa LSB rounds towards zero .f3.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64. d.f32 flushes subnormal inputs and results to sign-preserving zero.Chapter 8.rp }. 2010 85 .sat}.rn mantissa LSB rounds to nearest even . d = a .rn): . sub.rnd}{. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.0. requires sm_13 for sub.ftz. a.ftz}{.a.rm mantissa LSB rounds towards negative infinity .b.b. subnormal numbers are supported.rp for sub. NaN results are flushed to +0. .f32 sub{.

In particular. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rnd = { .ftz. mul.rnd}{. .f32 mul{.ftz.sat}.rz. NaN results are flushed to +0. 2010 .f64 d.rp for mul. d.PTX ISA Version 2. d = a * b. . subnormal numbers are supported. b. mul{. requires sm_20 Examples mul. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.f32 circumf. Rounding modifiers (default is .0]. mul Syntax Floating-Point Instructions: mul Multiply two values. mul. sm_1x: mul.sat.f64 requires sm_13 or later. Rounding modifiers have the following target requirements: .pi // a single-precision multiply 86 January 24. . mul. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. requires sm_13 for mul. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. . Saturation modifier: mul.f64.f32. a.rn.ftz}{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd}. For floating-point multiplication.f32 flushes subnormal inputs and results to sign-preserving zero. .f64 supports subnormal numbers.radius. Description Semantics Notes Compute the product of two values.0f. .rm mantissa LSB rounds towards negative infinity .rn): .rm.rz mantissa LSB rounds towards zero .rn mantissa LSB rounds to nearest even .0.f32 supported on all target architectures.rm.rz available for all targets . b.f32 clamps the result to [0.rn. a. all operands must be the same size. mul.0.rp }.0 Table 51. 1.f32 flushes subnormal inputs and results to sign-preserving zero.

NaN results are flushed to +0. fma. again in infinite precision.0].rnd. 1. . b.f64 introduced in PTX ISA version 1. d.rnd = { . again in infinite precision.f32 fma.rnd.z.f64. PTX ISA Notes Target ISA Notes Examples January 24.f64 computes the product of a and b to infinite precision and then adds c to this product.ftz.f64 d. subnormal numbers are supported.c. Saturation: fma.Chapter 8.ftz}{.f32 fma.0f. a.rn.x. Instruction Set Table 52. fma. fma.sat}. sm_1x: fma.f64 w. d. fma Syntax Floating-Point Instructions: fma Fused multiply-add. The resulting value is then rounded to single precision using the rounding mode specified by . fma. . . @p fma.rm. The resulting value is then rounded to double precision using the rounding mode specified by . a. c. 2010 87 . fma. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.rnd{. d = a*b + c.rn mantissa LSB rounds to nearest even . Rounding modifiers (no default): .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.y.f32 clamps the result to [0.sat. fma.f32 introduced in PTX ISA version 2.rn.4.f32 is unimplemented in sm_1x. fma.a.rz.rp }. fma. b.f64 requires sm_13 or later. fma.rm mantissa LSB rounds towards negative infinity .0.ftz. fma.rn.rnd.f32 requires sm_20 or later.rz mantissa LSB rounds towards zero .f64 is the same as mad.f32 computes the product of a and b to infinite precision and then adds c to this product. .f64 supports subnormal numbers.b. c.f32 flushes subnormal inputs and results to sign-preserving zero.0.

0 Table 53. 88 January 24.0f.rm.rnd. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.target sm_20 d.f32 is implemented as a fused multiply-add (i. c. mad.rz mantissa LSB rounds towards zero . sm_1x: mad.f64 d.f32 clamps the result to [0. again in infinite precision.sat}.rm mantissa LSB rounds towards negative infinity .f64 computes the product of a and b to infinite precision and then adds c to this product. again in infinite precision.f64.f32 flushes subnormal inputs and results to sign-preserving zero. mad. . again in infinite precision. b. The resulting value is then rounded to single precision using the rounding mode specified by . but the exponent is preserved. For . When JIT-compiled for SM 2.{f32. The resulting value is then rounded to double precision using the rounding mode specified by . b. mad{.f32 flushes subnormal inputs and results to sign-preserving zero.f32 mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. c. The resulting value is then rounded to double precision using the rounding mode specified by . mad.rnd{. mad.rz. where the mantissa can be rounded and the exponent will be clamped. and then the mantissa is truncated to 23 bits.rnd. mad.ftz. mad.target sm_1x: mad.f32 is when c = +/-0.0]. In this case. The exception for mad.{f32. mad. 2010 . NaN results are flushed to +0.0. d = a*b + c. a. Saturation modifier: mad.rnd = { .f64 supports subnormal numbers.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 is identical to the result computed using separate mul and add instructions. mad. a. and then writes the resulting value into a destination register. Note that this is different from computing the product with mul.f64}. b.target sm_13 and later .PTX ISA Version 2. Rounding modifiers (no default): . Unlike mad.f32. Description Semantics Notes Multiplies two values and adds a third. .rnd. 1.f32 computes the product of a and b at double precision.rnd.f64} is the same as fma. // . a.rn mantissa LSB rounds to nearest even . // . fma. mad.target sm_1x d.0.f32).0 devices. .rn. // .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. subnormal numbers are supported.f32 mad.f32 computes the product of a and b to infinite precision and then adds c to this product.ftz}{.rn.sat}..ftz}{.rp }. For .e.f64 is the same as fma.target sm_20: mad.sat. the treatment of subnormal inputs and output follows IEEE 754 standard. c.

4 and later. requires sm_13 . a rounding modifier is required for mad.rn. In PTX ISA versions 1.b. January 24.rm.0.f32 for sm_20 targets.rp for mad.c.rp for mad.. mad.f64 instructions having no rounding modifier will map to mad. Legacy mad.a.f32 supported on all target architectures. a rounding modifier is required for mad.f32 d.0 and later. requires sm_20 Examples @p mad. In PTX ISA versions 2.. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. 2010 89 ..rz.rn. Target ISA Notes mad.rm..rn. Rounding modifiers have the following target requirements: .rz..f64.f64.f64.f64 requires sm_13 or later.f32.Chapter 8..

.f32 defaults to div.f32 div.f32 flushes subnormal inputs and results to sign-preserving zero. div.rp}.full. d.f32 implements a fast approximation to divide. d.f32 supported on all target architectures.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sm_1x: div.full. Description Semantics Notes Divides a by b. a.rn mantissa LSB rounds to nearest even .rm.approx.rm.0.rm mantissa LSB rounds towards negative infinity . // // // // fast.f32 and div.rnd is required.{rz.f64 supports subnormal numbers. .3. a.circum. . For PTX ISA version 1. . Examples 90 January 24.f32 requires sm_20 or later. d = a / b.f64 introduced in PTX ISA version 1. subnormal numbers are supported.4. b. and rounding introduced in PTX ISA version 1.ftz}.f32 div.ftz. div. 2010 .rn. y.4 and later. computed as d = a * (1/b). z. PTX ISA Notes div.0 Table 54. zd. div.ftz.rnd{. The maximum ulp error is 2 across the full range of inputs.ftz. Fast. b.rnd. and div.3. 2126].f64 defaults to div. div.ftz. For PTX ISA versions 1.f32 div. Fast. a. b. Explicit modifiers . x.0 through 1. the maximum ulp error is 2. For b in [2-126.rnd = { .PTX ISA Version 2.approx. Target ISA Notes div.approx.f64.f32 implements a relatively fast. or .approx.f64 requires sm_20 or later. div. one of .14159.approx. xd. stores result in d. b.ftz}. but is not fully IEEE 754 compliant and does not support rounding modifiers.f32 div.ftz}.rn.f32.approx{. div. div Syntax Floating-Point Instructions: div Divide one value by another.approx.full{.rn.full.f64 diam.rz mantissa LSB rounds towards zero .f64 d.full.rn. a.rz. yd. Subnormal inputs and results are flushed to sign-preserving zero.f32 div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . div.f32 flushes subnormal inputs and results to sign-preserving zero. .rnd. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . full-range approximation that scales operands to achieve better accuracy. . approximate division by zero creates a value of infinity (with same sign as a). approximate single-precision divides: div.f64 requires sm_13 or later.ftz.f32 and div.rp }. div. d. div.full.

f32 x.Chapter 8. Take the absolute value of a and store the result in d. a. Instruction Set Table 55.ftz. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. a.f0.f64 d. neg. abs. d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs. d. neg. 2010 91 . subnormal numbers are supported. neg. NaN inputs yield an unspecified NaN. Negate the sign of a and store the result in d. d = -a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. neg. abs.ftz}.f64 d. neg{.f32 supported on all target architectures. abs. subnormal numbers are supported.f32 abs.f32 x.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. a.f64 requires sm_13 or later. sm_1x: abs. Table 56. abs. neg. abs{. Subnormal numbers: sm_20: By default. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. a.0. d = |a|.f64 requires sm_13 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 supports subnormal numbers. sm_1x: neg.f32 neg.ftz. Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers.ftz. NaN inputs yield an unspecified NaN.f0.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. January 24.f32 flushes subnormal inputs and results to sign-preserving zero.0.

d. 2010 . b.b.ftz. b.f32 min.z.c. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. Store the maximum of a and b in d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0 Table 57.f32 max. a. sm_1x: min. d d d d = = = = NaN.0.c.ftz}.ftz. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f1. max. max.ftz. min.x.f32 flushes subnormal inputs and results to sign-preserving zero.f32 min. a. b. (a > b) ? a : b.f64 z.f32 flushes subnormal inputs and results to sign-preserving zero. (a < b) ? a : b. Table 58.b.f64 f0.f64 supports subnormal numbers. min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. min{. b.f2.f64 requires sm_13 or later. max. d d d d = = = = NaN.f32 flushes subnormal inputs and results to sign-preserving zero. a. 92 January 24. Store the minimum of a and b in d. max{. b. a.ftz. @p min. b. a.f64 d.f32 max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 supported on all target architectures. d. subnormal numbers are supported. a. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. min. a.PTX ISA Version 2.f32 supported on all target architectures. min. sm_1x: max.f32 flushes subnormal inputs and results to sign-preserving zero. max. a.0.f64 requires sm_13 or later.f64 d.f64 supports subnormal numbers. subnormal numbers are supported.ftz}.

4 and later.rn.rn.rn.f32 rcp.rp}.f32 defaults to rcp.Chapter 8.f32 implements a fast approximation to reciprocal. rcp.f32 rcp.0 -Inf -Inf +Inf +Inf +0.approx.rn. Input -Inf -subnormal -0. Description Semantics Notes Compute 1/a.rp }. // fast.rn mantissa LSB rounds to nearest even .ftz}. rcp.f32 requires sm_20 or later. Examples January 24. xi.rz mantissa LSB rounds towards zero . rcp.rm.rn.rn.f32 supported on all target architectures. d.rnd. The maximum absolute error is 2-23. rcp.f32 flushes subnormal inputs and results to sign-preserving zero. one of .approx.ftz. d = 1 / a.f32 and rcp. . d.0 +subnormal +Inf NaN Result -0. a. Target ISA Notes rcp. rcp.ftz}.0.ftz. a.x. and rcp.{rz.ftz were introduced in PTX ISA version 1. rcp. Instruction Set Table 59.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rz.rnd{. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.ftz.rnd. For PTX ISA version 1.0.f32.f64 and explicit modifiers .f64 ri.f32 rcp.0 over the range 1.approx and . PTX ISA Notes rcp. For PTX ISA versions 1. rcp.4. rcp. rcp. 2010 93 .rnd is required.approx or .rnd = { .0-2. .x. rcp.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. subnormal numbers are supported.ftz.3.approx.f64 requires sm_13 or later. xi.f64. a.r.f64 supports subnormal numbers.0 +0.f32 rcp. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 introduced in PTX ISA version 1.approx{. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . sm_1x: rcp.approx.0 through 1.f64 defaults to rcp.0.rm mantissa LSB rounds towards negative infinity . General rounding modifiers were added in PTX ISA version 2. store result in d.f64 requires sm_20 or later.rm.

rn.0.f32 sqrt.rp}. sqrt. For PTX ISA version 1. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.x. sqrt. sqrt. a. and sqrt. d = sqrt(a).f64 defaults to sqrt.f32 is TBD.approx. General rounding modifiers were added in PTX ISA version 2. sqrt.x.0 +0.ftz.f64 r. 2010 .0 +0. a.f64 supports subnormal numbers. r.f32 sqrt.f32 sqrt. . For PTX ISA versions 1. Examples 94 January 24.rn.4.x. sqrt.rz mantissa LSB rounds towards zero . sqrt.rm.0 -0.0 through 1. sqrt.approx. Input -Inf -normal -subnormal -0.rm mantissa LSB rounds towards negative infinity .f64. // fast.f64 and explicit modifiers .4 and later.ftz}.0 Table 60. // IEEE 754 compliant rounding . sqrt.rnd is required.0 +subnormal +Inf NaN Result NaN NaN -0.ftz.rn. The maximum absolute error for sqrt.rnd.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .approx.rz. sqrt.f64 introduced in PTX ISA version 1.0 +0. a. Target ISA Notes sqrt. store in d.f32 supported on all target architectures.rp }.rnd{.approx and .ftz were introduced in PTX ISA version 1.ftz}. .approx.f64 d.f64 requires sm_13 or later.f32 requires sm_20 or later.0.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. Description Semantics Notes Compute sqrt(a). subnormal numbers are supported. PTX ISA Notes sqrt.f32 and sqrt.rn. sqrt. one of .rm.f32 flushes subnormal inputs and results to sign-preserving zero.approx{.approx or .rn mantissa LSB rounds to nearest even .f32 defaults to sqrt. // IEEE 754 compliant rounding d.f32 sqrt.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .PTX ISA Version 2.f32.approx.rn.rn.rnd. sm_1x: sqrt.{rz.3.f64 requires sm_20 or later.f32 implements a fast approximation to square root. r. approximate square root d.ftz.rnd = { .

f32 supported on all target architectures. rsqrt.ftz were introduced in PTX ISA version 1. rsqrt.Chapter 8.f32 rsqrt. the .f64 defaults to rsqrt.approx. For PTX ISA version 1.0-4. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. x. ISR.approx and . 2010 95 .ftz.f32 defaults to rsqrt.f64 were introduced in PTX ISA version 1.ftz}.f64 is emulated in software and are relatively slow.0. d. January 24.ftz. a.4.f32 flushes subnormal inputs and results to sign-preserving zero.approx. Instruction Set Table 61. Note that rsqrt. rsqrt.f64 supports subnormal numbers. PTX ISA Notes rsqrt. The maximum absolute error for rsqrt. store the result in d.approx{.approx.f64 d.0 through 1.f32.f64.approx implements an approximation to the reciprocal square root.f32 and rsqrt.0. rsqrt.3.approx.0 +0.f64 requires sm_13 or later. subnormal numbers are supported. a.ftz. Target ISA Notes Examples rsqrt.f64 isr.approx. sm_1x: rsqrt. rsqrt.f64 is TBD.4 over the range 1. rsqrt.f32 rsqrt. For PTX ISA versions 1.0 NaN The maximum absolute error for rsqrt. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. X. Compute 1/sqrt(a). d = 1/sqrt(a). Input -Inf -normal -subnormal -0.4 and later.f32 is 2-22. and rsqrt.approx.approx modifier is required. Explicit modifiers .0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. Subnormal numbers: sm_20: By default.

3. a.ftz}. Find the sine of the angle a (in radians). the .approx. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.0 +0.f32 introduced in PTX ISA version 1.f32 d. 96 January 24. Target ISA Notes Examples Supported on all target architectures. Explicit modifiers . a.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.approx.0.f32 sa.approx modifier is required.f32 flushes subnormal inputs and results to sign-preserving zero.4. subnormal numbers are supported.ftz.0 +0. sin.9 in quadrant 00.0 Table 62.0 -0.ftz. PTX ISA Notes sin.approx{.0 +0.f32. sin.0 +subnormal +Inf NaN Result NaN -0. sin. d = sin(a).approx. 2010 . sin.0 NaN NaN The maximum absolute error is 2-20. For PTX ISA versions 1.f32 defaults to sin. Subnormal numbers: sm_20: By default.f32 implements a fast approximation to sine.4 and later.approx and . For PTX ISA version 1.0 through 1.PTX ISA Version 2. sin. Input -Inf -subnormal -0.ftz introduced in PTX ISA version 1.

cos.f32. Subnormal numbers: sm_20: By default. Explicit modifiers . the . January 24.approx modifier is required.f32 ca.approx.4 and later. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 introduced in PTX ISA version 1.0 +0.0 +subnormal +Inf NaN Result NaN +1. a.0 +1.4. PTX ISA Notes cos.f32 flushes subnormal inputs and results to sign-preserving zero.approx.approx and .f32 d.ftz introduced in PTX ISA version 1. subnormal numbers are supported.approx. cos.f32 implements a fast approximation to cosine. Target ISA Notes Examples Supported on all target architectures.9 in quadrant 00.ftz.Chapter 8.0 through 1.0.0 +1.3. For PTX ISA version 1.ftz}.f32 defaults to cos.approx{. cos.0 NaN NaN The maximum absolute error is 2-20. a. cos. d = cos(a). Find the cosine of the angle a (in radians). For PTX ISA versions 1. Instruction Set Table 63.ftz.0 +1. 2010 97 . Input -Inf -subnormal -0. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz. cos.

approx.f32 implements a fast approximation to log2(a). For PTX ISA version 1.f32 defaults to lg2. PTX ISA Notes lg2.f32. sm_1x: Subnormal inputs and results to sign-preserving zero.approx modifier is required. lg2. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.approx. The maximum absolute error is 2-22.f32 Determine the log2 of a.f32 introduced in PTX ISA version 1. the . subnormal numbers are supported.approx{.f32 flushes subnormal inputs and results to sign-preserving zero.4. lg2. 2010 . d = log(a) / log(2). Input -Inf -subnormal -0. lg2.3.ftz.approx.0 through 1.ftz. Target ISA Notes Examples Supported on all target architectures.0 Table 64.ftz. a.ftz}.approx and .0.ftz introduced in PTX ISA version 1.0 +0.f32 la.PTX ISA Version 2.4 and later.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.6 for mantissa. lg2. 98 January 24. Subnormal numbers: sm_20: By default. lg2. Explicit modifiers . a. For PTX ISA versions 1.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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dtype.f32 flushes subnormal inputs to sign-preserving zero. a. {!}c. ne. ne. le.f64 }. gt. le. . setp with .ftz}. hi.BoolOp{.s16. ge. the result is false. gt. . c).n. le. sm_1x: setp. 2010 . 102 January 24. higher.ftz}. gt. Applies to all numeric types. .f64 source type requires sm_13 or later. This result is written to the first destination operand. gtu. neu. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. hi. ge. . le. and higher-or-same may be used instead of lt. the comparison operators lo. b.u16. gtu. gt.PTX ISA Version 2.pred variables. then these comparisons have the same result as their ordered counterparts. Subnormal numbers: sm_20: By default. If either operand is NaN.s32. If both operands are numeric values (not NaN). and (optionally) combine this result with a predicate value by applying a Boolean operator.CmpOp. A related value computed using the complement of the compare result is written to the second destination operand. ls. lo.type = { . . q = BoolOp(!t. num.u32 p|q. neu.s32 setp. ls. or.r. setp.lt. a. ge.a. Integer Notes Floating Point Notes The ordered comparisons are eq.f64 supports subnormal numbers.f32.ftz.eq.ftz applies only to . Modifier .and. c).b16. .CmpOp{. bit-size comparisons are eq and ne.b64.b. p[|q]. If either operand is NaN. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. num returns true if both operands are numeric values (not NaN). For unsigned values.type .dtype. . and nan returns true if either operand is NaN. The destinations p and q must be . . ne. lt. p = BoolOp(t. leu. then the result of these comparisons is true.B) is one of: and.s64. geu. p[|q]. and hs for lower. geu.0 Table 67. setp.dtype. setp. . respectively. @q setp. ltu. xor.type setp.f32 comparisons. loweror-same. leu.u32. subnormal numbers are supported. hs equ.i. To aid comparison operations in the presence of NaN values. lt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u64.f32 flushes subnormal inputs to sign-preserving zero. unordered versions are included: equ. The comparison operator is a suffix on the instruction. Semantics t = (a CmpOp b) ? 1 : 0. and can be one of: eq. nan The Boolean operator BoolOp(A.0. p. The untyped. lt. b. ltu. . The signed and unsigned comparison operators are eq.b32. ge.

val. .f64 requires sm_13 or later.dtype.s32.Chapter 8.b16.s32 slct{.f32 comparisons.f32. C. slct.ftz.f32.dtype = { . a. and b are treated as a bitsize type of the same width as the first instruction type. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. b otherwise.p. Subnormal numbers: sm_20: By default.type = { .f32 flushes subnormal values of operand c to sign-preserving zero.x.s64. Operands d.u32. .0. .f32 d. slct Syntax Comparison and Selection Instructions: slct Select one source operand. d = (c >= 0) ? a : b.f64 requires sm_13 or later. .r. slct. a. subnormal numbers are supported. z. . . Operand c is a predicate.0. y. . otherwise b is stored in d. selp. . based on the value of the predicate source operand. sm_1x: slct.s16.t. negative zero equals zero. a.ftz. a. .type d.ftz applies only to . .s64. based on the sign of the third operand. The selected input is copied to the output without modification. a is stored in d. .s32 selp. .g. c.xp. For . . fval.u32. . Modifier . .b32.f32 comparisons. b.s32 x.f64 }. Description Conditional selection. If operand c is NaN.ftz}.u64. Instruction Set Table 68.f32 A. . slct. If c ≥ 0. slct.u64. selp Syntax Comparison and Selection Instructions: selp Select between source operands. . B. c.f64 }. 2010 103 . slct. Semantics Floating Point Notes January 24.f32 r0. selp.f32 flushes subnormal values of operand c to sign-preserving zero. a. and operand a is selected. f0. Operands d. . d.u64.b64. .dtype. and b must be of the same type.s16. b. d = (c == 1) ? a : b. a is stored in d.b32.u16. operand c must match the second instruction type.b16.s32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.dtype.dtype. the comparison is unordered and operand b is selected. Table 69. b. and operand a is selected. If c is True.b64.u16. Introduced in PTX ISA version 1. . @q selp. c. . .u32.

PTX ISA Version 2. provided the operands are of the same size. Instructions and. performing bit-wise operations on operands of any type. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. 2010 . This permits bit-wise operations on floating point values without having to define a union to access the bits. and not also operate on predicates. or. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4.7.0 8. xor.

Introduced in PTX ISA version 1.type d. Allowed types include predicate registers.0x00010001 or. . b.b32. but not necessarily the type.pred.b64 }. b. or.0.q. sign. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.r.Chapter 8. . January 24.r. a. and. d = a & b.pred.b32 x.b64 }. .q.fpvalue.type = { . Introduced in PTX ISA version 1. Instruction Set Table 70.b32. Supported on all target architectures. or Syntax Logic and Shift Instructions: or Bitwise OR. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. 2010 105 . a.type = { .type d.pred p. and Syntax Logic and Shift Instructions: and Bitwise AND.0x80000000. Table 71. .b16. The size of the operands must match. Supported on all target architectures. or. d = a | b. but not necessarily the type.0. .b32 and. .b16. The size of the operands must match.b32 mask mask. . . Allowed types include predicate registers. and.

r. d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. xor.PTX ISA Version 2. . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).a. Supported on all target architectures. . Introduced in PTX ISA version 1. The size of the operands must match. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.q.b32 xor. Table 74. not Syntax Logic and Shift Instructions: not Bitwise negation.b16.b32. Supported on all target architectures.b32.0. .pred p. . b. a. Supported on all target architectures. 106 January 24.0. not.b16. The size of the operands must match. .b64 }.type d. .0 Table 72.b64 }. one’s complement.b16. d = ~a.type = { .b32. d = (a==0) ? 1 : 0. Introduced in PTX ISA version 1. a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. cnot. cnot. .0x0001. a.type d. The size of the operands must match. Table 73. .b64 }.0. but not necessarily the type.type = { . not.x.pred.type = { . d = a ^ b. but not necessarily the type. but not necessarily the type. Allowed types include predicate registers.q. .type d. Introduced in PTX ISA version 1.b32 d. not. . 2010 . .b32 mask.mask. xor.pred. Allowed types include predicates.b16 d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.

.b16. regardless of the instruction type. shl Syntax Logic and Shift Instructions: shl Shift bits left. .b64.u16 shr. a.type = { . . Introduced in PTX ISA version 1.b32. .type d. but not necessarily the type.j. Signed shifts fill with the sign bit. Shift amounts greater than the register width N are clamped to N. Supported on all target architectures. k. zero-fill on right. The sizes of the destination and first source operand must match. shr Syntax Logic and Shift Instructions: shr Shift bits right. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Shift amounts greater than the register width N are clamped to N. d = a << b.s64 }. . regardless of the instruction type. . shl. Bit-size types are included for symmetry with SHL.b16 c. d = a >> b.s16. sign or zero fill on left.type d. .1.a. PTX ISA Notes Target ISA Notes Examples January 24. .i.type = { . .0.b32.u64. 2010 107 .2.a.Chapter 8. b. b. The b operand must be a 32-bit value. unsigned and untyped shifts fill with 0. a.s32. shl. Instruction Set Table 75. . PTX ISA Notes Target ISA Notes Examples Table 76.b32 q. Introduced in PTX ISA version 1.b64 }. but not necessarily the type. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.u16. shr. .u32. Supported on all target architectures.s32 shr. The b operand must be a 32-bit value. shr.i.b16. i.2.0. . The sizes of the destination and first source operand must match.

0 8. Instructions ld. Data Movement and Conversion Instructions These instructions copy data from place to place. suld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. 2010 . ldu. local. or shared state spaces. prefetchu isspacep cvta cvt 108 January 24. and sust support optional cache operations. possibly converting it from one format to another. and from state space to state space.7. and st operate on both scalar and vector types.PTX ISA Version 2. ld. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. The cvta instruction converts addresses between generic and global. st. mov.5.

Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. . likely to be accessed again.cs is applied to a Local window address. Operator . The ld. If one thread stores to global memory via one L1 cache. fetch again). the second thread may get stale L1 cache data. any existing cache lines that match the requested address in L1 will be evicted. likely to be accessed once.cs. the cache operators have the following definitions and behavior. . when applied to a local address.1.cv to a frame buffer DRAM address is the same as ld. Global data is coherent at the L2 level.7.Chapter 8. . A ld. The ld.cg Cache at global level (cache in L2 and below. not L1). Use ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. and a second thread loads that address via a second L1 cache with ld. Cache Operators PTX 2. .lu instruction performs a load cached streaming operation (ld. it performs the ld. The default load instruction cache operation is ld. The cache operators require a target architecture of sm_20 or later. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. 2010 109 .ca. to allow the thread program to poll a SysMem location written by the CPU. bypassing the L1 cache.ca loads cached in L1.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The ld. if the line is fully covered. The ld.lu operation. The compiler / programmer may use ld. rather than the data stored by the first thread. and cache only in the L2 cache. For sm_20 and later.lu Last use.5.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cg to cache loads only globally.lu load last use operation. Table 77.0 introduces optional cache operators on load and store instructions. evict-first. invalidates (discards) the local L1 line following the load.ca. but multiple L1 caches are not coherent for global data. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cv Cache as volatile (consider cached system memory lines stale. When ld. As a result of this request.cs) on global addresses.cs Cache streaming. January 24. Instruction Set 8.

cg to local memory uses the L1 cache.ca loads. but st. The default store instruction cache operation is st. not L1). . which writes back cache lines of coherent cache levels with normal eviction policy. st. likely to be accessed once. and a second thread in a different SM later loads from that address via a different L1 cache with ld.ca.wb. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. . and cache only in the L2 cache. and marks local L1 lines evict-first.cg to cache global store data only globally. in which case st.wt.PTX ISA Version 2. rather than get the data from L2 or memory stored by the first thread.cs Cache streaming.cg is the same as st.wb for global data. and discard any L1 lines that match. the second thread may get a hit on stale L1 cache data.wb could write-back global store data from L1.0 Table 78. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. Future GPUs may have globally-coherent L1 caches.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. bypassing its L1 cache. to allow a CPU program to poll a SysMem location written by the GPU with st. In sm_20. regardless of the cache operation.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Addresses not in System Memory use normal write-back. Operator . Global stores bypass L1.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. The st. However. . If one thread stores to global memory. The st. 2010 . 110 January 24. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.cg Cache at global level (cache in L2 and below.wt Cache write-through (to system memory). bypassing the L1 cache. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. Use st.

. avar. local. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. the address of the variable in its state space) into the destination register. sreg. and . local. mov. . u.s64. // get address of variable // get address of label or function . 2010 111 . For variables declared in . .e. ptr.s16.u32 mov.type mov.b64.u16. the generic address of a variable declared in global. the parameter will be copied onto the stack and the address will be in the local state space.f32. A[5].u64. d = &label.u32 mov.Chapter 8.local. // address is non-generic. . d. Write register d with the value of a. addr.f64 requires sm_13 or later. immediate.const. d. . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. Description . mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.. d = &avar. . or function name. myFunc.0. alternately. . ptr. d = sreg.type = { .pred. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. special register.e. d.global. mov. within the variable’s declared state space Notes Although only predicate and bit-size types are required.u32. or shared state space may be taken directly using the cvta instruction.type mov.f32 mov. The generic address of a variable in global. Operand a may be a register. label.f64 }. k..f32 mov.0.type mov. label. . Introduced in PTX ISA version 1.b32. .shared state spaces. mov. i. Note that if the address of a device function parameter is moved to a register.u16 mov. a. . Semantics d = a.a. mov places the non-generic address of the variable (i. Take the non-generic address of a variable in global. . A. . variable in an addressable memory space.s32.1.type d. or shared state space. local.b16.u32 d.v. Instruction Set Table 79.

b have type . a[16.7]. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). mov. lo.23]. a[32. d.b.y.31].b32 // pack four 16-bit elements into ..y } = { a[0. a[8. d. {r.y << 8) d = a.b16 // pack four 8-bit elements into .b16.w << 24) d = a. . a[48.b64 }.b}.hi}..u32 x. d. // // // // a.z.w}.x | (a.PTX ISA Version 2.31] } // unpack 16-bit elements from .{a.0. {lo. Semantics d = a.x | (a.{x.b32 mov.w << 48) d = a..w have type .u8 // unpack 32-bit elements from .z..hi are . a[32.63] } // unpack 16-bit elements from .z. .b32.b32 %r1..y.b64 112 January 24.y << 16) | (a.15]. d.y << 32) // pack two 8-bit elements into .z << 16) | (a. d.a}.z << 32) | (a. a.g. Supported on all target architectures.15] } // unpack 8-bit elements from .b64 // pack two 32-bit elements into ..x. %r1..b32 { d..31].. a[24.w } = { a[0.type = { .x. Description Write scalar register d with the packed value of vector register a..y. d. d.x | (a.0 Table 80.b64 mov.15].7].31] } // unpack 8-bit elements from .z.y } = { a[0.b. d. a[16.y } = { a[0... or write vector register d with the unpacked values from scalar register a.g.b64 { d. d. a[16. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.x | (a.b16 { d..y.b32 mov. a[8..y << 8) | (a.type d. mov.x.%r1. 2010 .w } = { a[0. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 { d. .b32 // pack two 16-bit elements into . For bit-size types.47].x.y << 16) d = a.b64 { d.u16 %x is a double.15].x.x | (a.a have type . %x.b8 r.

the access may proceed by silently masking off low-order address bits to achieve proper rounding.s16. or [immAddr] an immediate absolute byte address (unsigned. an integer or bit-size type register reg containing a byte address. A destination register wider than the specified type may be used.volatile introduced in PTX ISA version 1.Chapter 8.volatile.s64. The address size may be either 32-bit or 64-bit. .cv }.u32. ld{. The value loaded is sign-extended to the destination register width for signed integers. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.type ld{. 32-bit). The address must be naturally aligned to a multiple of the access size.ss = { . 32-bit). . ld introduced in PTX ISA version 1.s8. i. for example.e. . .type . and is zeroextended to the destination register width for unsigned and bit-size types.v2. . ld.cop}. .f64 using cvt. an address maps to the corresponding location in local or shared memory. and then converted to . d. d.reg state space. . i. . . .type d.e. If no state space is given. Description Load register variable d from the location specified by the source address operand a in specified state space.lu. . [a].b64. and truncated if the register width exceeds the state space address width for the target architecture.cg.ca.f64 }. .type ld.ss}. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . PTX ISA Notes January 24.0. [a]. .ss}{. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. .cop = { .ss}. [a]. Cache operations are not permitted with ld.volatile{.vec.shared spaces to inhibit optimization of references to volatile memory. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. Addresses are zero-extended to the specified width as needed. or the instruction may fault. Generic addressing and cache operations introduced in PTX ISA 2. *a. .const space suffix may have an optional bank number to indicate constant banks other than bank zero.cop}. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.vec = { . [a]. . ld.b32. *(a+immOff). the resulting behavior is undefined.v4 }.cs. .volatile{.shared }.0. .type = { . If an address is not properly aligned. . an address maps to global memory unless it falls within the local memory window or the shared memory window. 2010 113 . Semantics d d d d = = = = a..1.b8. Generic addressing may be used with ld.volatile. Within these windows. . . perform the load using generic addressing.param. .f16 data may be loaded using ld. The . *(immAddr).b16. d. . This may be used.u8.global and .global. In generic addressing.b16.s32. .vec.volatile may be used with .ss}{. Instruction Set Table 81.f32 or .f32.const.u64. to enforce sequential consistency between threads accessing shared memory.local. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .u16.

const.b32 ld. Cache operations require sm_20 or later. Generic addressing requires sm_20 or later.[a]. x. // access incomplete array x.[p+4].b32 ld.s32 ld.f32. ld.[p+-8].[240]. Q. // immediate address %r.[p].b64 ld. %r.b16 cvt.shared.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.f64 requires sm_13 or later.local.global.local.PTX ISA Version 2.f16 d. // load . d.f32 ld.global.[buffer+64].v4. // negative offset %r.b32 ld.%r.const[4].[fs]. 2010 .0 Target ISA Notes ld.

// // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . and then converted to .global }. 32-bit). d. ldu.vec = { . In generic addressing. The data at the specified address must be read-only. . i. PTX ISA Notes Target ISA Notes Examples January 24. [a]. If no state space is given. .[a]. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. and truncated if the register width exceeds the state space address width for the target architecture.0.[p+4].ss}. .type ldu{.u16.Chapter 8.global.v4. For ldu.global. and is zeroextended to the destination register width for unsigned and bit-size types. A destination register wider than the specified type may be used.ss = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. *(immAddr).s64. an address maps to global memory unless it falls within the local memory window or the shared memory window.f16 data may be loaded using ldu. ldu.type = { .s16.u8.f64 }.u64.f64 requires sm_13 or later.b32. where the address is guaranteed to be the same across all threads in the warp. ldu. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. Addresses are zero-extended to the specified width as needed. The address size may be either 32-bit or 64-bit. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e.f32 d.vec. *a. The address must be naturally aligned to a multiple of the access size.type d.b16.e. Within these windows.b32 d. ldu{. Semantics d d d d = = = = a. [a].f64 using cvt. . Introduced in PTX ISA version 2. . .s8. . If an address is not properly aligned.ss}. ldu. i. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. perform the load using generic addressing.b64. . . . .u32. The value loaded is sign-extended to the destination register width for signed integers. the resulting behavior is undefined. . 32-bit). .f32 Q.s32. 2010 115 . an address maps to the corresponding location in local or shared memory. A register containing an address may be declared as a bit-size type or integer type.reg state space. // load from address // vec load from address . .v2. . or [immAddr] an immediate absolute byte address (unsigned.b8. .[p]..f32.f32 or . // state space . Instruction Set Table 82.global. [areg] a register reg containing a byte address. The addressable operand a is one of: [avar] the name of an addressable variable var.b16. or the instruction may fault. *(a+immOff). only generic addresses that map to global memory are legal.v4 }.

1.vec.e.PTX ISA Version 2.s64. [a].type . .ss .volatile{. Generic addressing may be used with st. Cache operations require sm_20 or later.b8.global and .volatile introduced in PTX ISA version 1.f32. b. *d = a.cg.wb. [a].u16. an address maps to the corresponding location in local or shared memory. .cop}. *(d+immOffset) = a.volatile may be used with .e. . b.s8.f64 requires sm_13 or later. .. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or [immAddr] an immediate absolute byte address (unsigned.u32.b64.cop}. { . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.type st{. .b16. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. The address must be naturally aligned to a multiple of the access size. and truncated if the register width exceeds the state space address width for the target architecture. .0. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. The lower n bits corresponding to the instruction-type width are stored to memory. [a].f16 data resulting from a cvt instruction may be stored using st. PTX ISA Notes Target ISA Notes 116 January 24.0. Cache operations are not permitted with st. st. If no state space is given. i. { . st introduced in PTX ISA version 1.type [a].b16. . . . This may be used.global.ss}. . st{. Addresses are zero-extended to the specified width as needed.b32. *(immAddr) = a. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.wt }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . or the instruction may fault.u8. b.0 Table 83. the resulting behavior is undefined. .s32.volatile. .reg state space.cs.f64 }. perform the store using generic addressing. . In generic addressing. b. 2010 . .volatile{. Generic addressing and cache operations introduced in PTX ISA 2.type = = = = {. .vec .ss}. to enforce sequential consistency between threads accessing shared memory. Semantics d = a. { .v2.type st. A source register wider than the specified type may be used. The address size may be either 32-bit or 64-bit.vec.volatile. i. an integer or bit-size type register reg containing a byte address. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.local. Generic addressing requires sm_20 or later. .s16.shared spaces to inhibit optimization of references to volatile memory.ss}{.shared }. st. If an address is not properly aligned. Within these windows. 32-bit). // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .ss}{. an address maps to global memory unless it falls within the local memory window or the shared memory window.cop .v4 }. .u64. st. 32-bit). for example. . .

2010 117 . Instruction Set Examples st.s32 st.a. [p].b16 [a]. [fs].local. // %r is 32-bit register // store lower 16 bits January 24.global.r7. // immediate address %r.global.s32 cvt. [q+-8].local.%r.f32 st.local.%r.b32 st.a.v4.f32 st.b. [q+4].f16.Chapter 8.b32 st.Q. // negative offset [100].

Addresses are zero-extended to the specified width as needed. . and no operation occurs if the address maps to a local or shared memory location. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. 118 January 24. in specified state space. and truncated if the register width exceeds the state space address width for the target architecture. If no state space is given.level prefetchu. prefetch{. prefetch and prefetchu require sm_20 or later.e. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. Within these windows. In generic addressing.L2 }. an address maps to global memory unless it falls within the local memory window or the shared memory window. a register reg containing a byte address. A prefetch into the uniform cache requires a generic address. // prefetch to data cache // prefetch to uniform cache . A prefetch to a shared memory location performs no operation.0.L1 [a]. an address maps to the corresponding location in local or shared memory. prefetch. i.global. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the prefetch uses generic addressing. or [immAddr] an immediate absolute byte address (unsigned. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 2010 . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. [a]. .0 Table 84.L1 [addr].PTX ISA Version 2.space = { . prefetchu. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.global.level = { .L1 [ptr]. 32-bit). The address size may be either 32-bit or 64-bit.L1.space}. . 32-bit).local }.

space = { . // local.space = { .u64.u32.shared isglbl.size = { .u32 gptr. local.to.global. isshrd.global. or shared state space.pred.size cvta.space p. Take the generic address of a variable declared in global. the generic address of the variable may be taken using cvta.u32.local isspacep. local. p.space.space.u64 or cvt. isspacep requires sm_20 or later. or shared state space. isspacep. or shared address.shared }.lptr. or shared address cvta. local. Use cvt.space. 2010 119 . a.0. The destination register must be of type .Chapter 8. sptr. . cvta requires sm_20 or later. .size . January 24.0. cvta. . . a. or vice-versa.genptr. local. cvta. . or shared address to a generic address. svar.u32 p. Description Convert a global.shared }.to.size p. When converting a generic address into a global.pred . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. // get generic address of svar cvta. The source and destination addresses must be the same size. cvta.local. The source address operand must be a register of type . or shared state space to generic.u64 }. Introduced in PTX ISA version 2. lptr. // result is . islcl.local. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. isspacep.global.local.u32 or . gptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. local. // convert to generic address // get generic address of var // convert generic address to global. or vice-versa.u64. p.global isspacep. Instruction Set Table 85. var.u32 p. PTX ISA Notes Target ISA Notes Examples Table 86. . isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. For variables declared in global. a.u32 to truncate or zero-extend addresses. A program may use isspacep to guard against such incorrect behavior.shared.

dtype.sat For integer destination types. .u16.ftz}{.. choosing even integer if source is equidistant between two integers.4 and earlier.sat limits the result to MININT. . . .s8. .s64. For cvt. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.rzi round to nearest integer in the direction of zero . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rp }.f16.f32 float-to-integer conversions and cvt.rz. cvt{. a. Description Semantics Integer Notes Convert between different types and sizes.f32.u32.ftz modifier may be specified in these cases for clarity. Integer rounding is required for float-to-integer conversions.PTX ISA Version 2.MAXINT for the size of the operation.u8.dtype. . .rzi. i.dtype. The optional .f32.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. subnormal inputs are flushed to signpreserving zero.. . . . Saturation modifier: . the result is clamped to the destination range by default. i. . Note: In PTX ISA versions 1.ftz.atype = { .rmi round to nearest integer in direction of negative infinity . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.f32.irnd}{. and for same-size float-tofloat conversions where the value is rounded to an integer. d = convert(a).sat modifier is illegal in cases where saturation is not possible based on the source and destination types.ftz. For float-to-integer conversions.atype d. .u64. 120 January 24.irnd = { .ftz.sat is redundant. .rpi }. The compiler will preserve this behavior for legacy PTX code.f32 float-tofloat conversions with integer rounding. . the . . Note that saturation applies to both signed and unsigned integer types. a. .dtype. 2010 .s16.sat}.frnd}{.rmi. // integer rounding // fp rounding .f64 }.ftz}{.atype cvt{. .e.rn. Integer rounding is illegal in all other instances.frnd = { .s32. .dtype = . . subnormal inputs are flushed to signpreserving zero.e. Integer rounding modifiers: .rni.rm. sm_1x: For cvt.rni round to nearest integer. subnormal numbers are supported.ftz.sat}. . d. .f32 float-to-integer conversions and cvt.0 Table 87.f32 float-tofloat conversions with integer rounding.

The compiler will preserve this behavior for legacy PTX code.f32.y. Applies to .0]. stored in floating-point format. The operands must be of the same size.f32. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.rni.f32.f64 j.f16.f32 x.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.i. Note: In PTX ISA versions 1. // round to nearest int.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). . Modifier . 1.f32 x.f32 instructions.4 and earlier.r. if the PTX . subnormal numbers are supported.f16. cvt. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.4 or earlier.f64 requires sm_13 or later. // note . Specifically. Introduced in PTX ISA version 1. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .version is 1. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.f32.f64 types.ftz modifier may be specified in these cases for clarity.f32.Chapter 8. and for integer-to-float conversions. result is fp cvt.rm mantissa LSB rounds towards negative infinity . // float-to-int saturates by default cvt. and . and cvt. Floating-point rounding modifiers: .y.f32. 2010 121 .s32.f64.s32 f.f16. Floating-point rounding is illegal in all other instances. The result is an integral value.f32. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. cvt. .ftz behavior for sm_1x targets January 24. cvt. Subnormal numbers: sm_20: By default. The optional .0.0. NaN results are flushed to positive zero. cvt to or from .rz mantissa LSB rounds towards zero . Saturation modifier: .sat limits the result to the range [0.sat For floating-point destination types.rn mantissa LSB rounds to nearest even .

and surfaces.global . Texture and Surface Instructions This section describes PTX instructions for accessing textures.f32. = nearest width height tsamp1. sampler. sampler. and surface descriptors. Ability to query fields within texture. } = clamp_to_border.f32 {r1. The texturing mode is selected using .width. // get tex1’s tex. r3.target options ‘texmode_unified’ and ‘texmode_independent’. r5.. texture and sampler information each have their own handle.PTX ISA Version 2. allowing them to be defined separately and combined at the site of usage in the program.f2}]. r5. cvt. [tex1]. add. // get tex1’s txq. 2010 .target texmode_independent .entry compute_power ( . . r1. Module-scope and per-entry scope definitions of texture. r1. texture and sampler information is accessed through a single . and surface descriptors.f32 r1. 122 January 24. r3. but the number of samplers is greatly restricted to 16. .r4}. with the restriction that they correspond 1-to-1 with the 128 possible textures. PTX has two modes of operation. and surface descriptors.param .texref handle. sampler. PTX supports the following operations on texture.2d. r5..b32 r5. A PTX module may declare only one texturing mode.u32 r5. samplers.r2. {f1.texref tex1 ) { txq. the file is assumed to use unified mode.r3. add.7.f32 r3.height. [tex1]. r4.samplerref tsamp1 = { addr_mode_0 filter_mode }. add. r1. The advantage of unified mode is that it allows 128 samplers.u32 r5. [tex1. mul.v4. Example: calculate an element’s power contribution as element’s power/total number of elements. In the independent mode. In the unified mode. div.f32 r1.b32 r6. r6. r2.f32. The advantage of independent mode is that textures and samplers can be mixed and matched. and surface descriptors: • • • Static initialization of texture.f32 r1. . sampler. Texturing modes For working with textures and samplers.0 8.6. If no texturing mode is declared.

f32 }. .r3. .btype d.f32 {r1. {f1. the resulting behavior is undefined. d. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. A texture base address is assumed to be aligned to a 16-byte address. .r2. c]. Instruction Set These instructions provide access to texture and surface memory.f3.. tex txq suld sust sured suq Table 88. .s32 {r1.e.0. . Unified mode texturing introduced in PTX ISA version 1.1d. i. c]. // explicit sampler .geom. or the instruction may fault.s32.btype = { .f2. {f1}].f32 }. //Example of unified mode texturing tex. [a. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.dtype. PTX ISA Notes Target ISA Notes Examples January 24. Supported on all target architectures.geom = { .u32. Description Texture lookup using a texture coordinate vector.3d. tex.s32. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. [tex_a. where the fourth element is ignored.v4.s32.r4}. If no sampler is specified. [a. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.f4}].2d. An optional texture sampler b may be specified.3d }. with the extra elements being ignored.r4}.v4.geom.btype tex. [tex_a.s32.1d.dtype = { . sampler_x. If an address is not properly aligned. the access may proceed by silently masking off low-order address bits to achieve proper rounding. b. is a two-element vector for 2d textures. Operand c is a scalar or singleton tuple for 1d textures.v4. .Chapter 8.dtype. // Example of independent mode texturing tex.v4.r3. . Notes For compatibility with prior versions of PTX.5. The instruction always returns a four-element vector of 32-bit values.r2. 2010 123 . the sampler behavior is a property of the named texture. the square brackets are not required and .v4 coordinate vectors are allowed for any geometry. and is a four-element vector for 3d textures.

PTX ISA Version 2. Query: . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. clamp_to_edge.normalized_coords .width. [tex_A].5. 2010 .width. // unified mode // independent mode 124 January 24. and in independent mode sampler attributes are accessed via a separate samplerref argument. txq.texref or .b32 %r1. txq. .height.width .filter_mode . Description Query an attribute of a texture or sampler. In unified mode.addr_mode_0.samplerref variable.addr_mode_1 . d. sampler attributes are also accessed via a texref argument.addr_mode_0. linear } Integer from enum { wrap.b32 %r1. Supported on all target architectures.0 Table 89. . txq. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.height . addr_mode_2 }. .normalized_coords }.b32 %r1.squery = { . clamp_ogl.filter_mode.filter_mode. Integer from enum { nearest. // texture attributes // sampler attributes . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. Operand a is a .depth.depth .tquery. addr_mode_1. [smpl_B]. [a]. .tquery = { . . [tex_A].addr_mode_0 . mirror. txq.b32 txq.b32 d.squery. [a].addr_mode_2 Returns: value in elements 1 (true) or 0 (false).

. 2010 125 .1d.surfref variable.v2. sm_1x targets support only the . b]. [a. Destination vector elements corresponding to components that do not appear in the surface format are not written.u32. b].dtype . suld.b supported on all target architectures.cs. or FLOAT data.clamp . suld.cop . is a two-element vector for 2d surfaces.v4 }.clamp = = = = = = { { { { { { d.w}].0. .3d }.ca.5.b64 }.f4}.v4. .1d. .vec .s32. suld.trap suld.geom{.v2. Operand a is a . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. B. {x.s32. // for suld. [a.b performs an unformatted load of binary data.clamp suld. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.s32 is returned.vec. . .u32. if the surface format contains SINT data.f3. Operand b is a scalar or singleton tuple for 1d surfaces.cop}. and the size of the data transfer matches the size of destination operand d.e.f32 }.trap .s32.f32.s32. . . {f1.p requires sm_20 or later.z.b32. A surface base address is assumed to be aligned to a 16-byte address. size and type conversion is performed as needed to convert from the surface sample format to the destination type. .Chapter 8. i. additional clamp modifiers.3d.cg.p .clamp.geom .v4. Description Load from surface memory using a surface coordinate vector.r2}.b. or . suld. if the surface format contains UINT data.trap {r1. suld.clamp field specifies how to handle out-of-bounds addresses: .2d. and A components of the surface format.f32. .b16.y.p.b. . the resulting behavior is undefined.b. Instruction Set Table 90. If an address is not properly aligned. . G.b8 .f32 is returned.clamp . .b32.3d requires sm_20 or later. and is a four-element vector for 3d surfaces. // unformatted d. where the fourth element is ignored. or . and cache operations introduced in PTX ISA version 2.dtype. // for suld. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. suld Syntax Texture and Surface Instructions: suld Load from surface memory.dtype . suld. or the instruction may fault.geom{. . suld. . suld. the access may proceed by silently masking off low-order address bits to achieve proper rounding.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.p is currently unimplemented. Cache operations require sm_20 or later. SNORM.trap clamping modifier. // cache operation none. then .cv }.b64.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.cop}. If the destination type is . The lowest dimension coordinate represents a sample offset rather than a byte offset. [surf_B.zero }. . .p..trap. . Target ISA Notes Examples January 24.trap introduced in PTX ISA version 1.b32.u32.f2. The .b .u32 is returned. Coordinate elements are of type . {x}]. suld. the surface sample elements are converted to . If the destination base type is . . // formatted . then .f32 based on the surface format as follows: If the surface format contains UNORM.p.dtype. [surf_A. then .

{x}]. .p.cop .trap .zero }.p performs a formatted store of a vector of 32-bit data values to a surface sample.z. If an address is not properly aligned. sust.r2}. Surface sample components that do not occur in the source vector will be written with an unpredictable value. The source data is then converted from this type to the surface sample format. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.s32.b32.{u32.s32 is assumed.v4.ctype. // unformatted // formatted . [a.trap introduced in PTX ISA version 1.b64. These elements are written to the corresponding surface sample components. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.b performs an unformatted store of binary data. and is a four-element vector for 3d surfaces. .cg. The size of the data transfer matches the size of source operand c. {x.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.clamp.ctype . i.p Description Store to surface memory using a surface coordinate vector. The . 2010 .b64 }.. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.3d requires sm_20 or later. sust Syntax Texture and Surface Instructions: sust Store to surface memory. {r1. . If the source type is .0. is a two-element vector for 2d surfaces. . none. sust. c.geom{. . .f4}.u32 is assumed.b16.b. and A surface components. or FLOAT data. G.ctype.f32 }. . additional clamp modifiers. Operand a is a .p.p.f2. Operand b is a scalar or singleton tuple for 1d surfaces. b]. if the surface format contains SINT data. sust.3d }.b.cop}.b8 . .u32.geom{.surfref variable.v4 }.v2.clamp . and cache operations introduced in PTX ISA version 2. Cache operations require sm_20 or later. sust.b32. sm_1x targets support only the . or the instruction may fault. . Target ISA Notes Examples 126 January 24. .v2. . sust. b]. . The source vector elements are interpreted left-to-right as R.5. .0 Table 91.s32. .w}].trap clamping modifier.1d.f3.vec.vec . where the fourth element is ignored. .clamp = = = = = = { { { { { { [a.geom . Coordinate elements are of type . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.trap [surf_A.p.e. sust. then .trap sust.u32. size and type conversions are performed as needed between the surface sample format and the destination type. the resulting behavior is undefined.s32.clamp sust. sust. SNORM.f32.PTX ISA Version 2. The lowest dimension coordinate represents a sample offset rather than a byte offset. if the surface format contains UINT data. .wt }.cs. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . {f1.b32.y.1d.vec. // for sust.wb.b.b supported on all target architectures. . A surface base address is assumed to be aligned to a 16-byte address.f32.2d.s32.cop}.f32 is assumed.b // for sust. If the source base type is .p requires sm_20 or later.ctype . [surf_B. c. then .clamp . then .f32} are currently unimplemented. B. sust. or . .clamp field specifies how to handle out-of-bounds addresses: . Source elements that do not occur in the surface sample are ignored.trap. sust.3d.

op.b.s32 is assumed.geom.clamp [a.ctype. if the surface format contains SINT data.b32.add.p.p performs a reduction on sample-addressed 32-bit data.c. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. A surface base address is assumed to be aligned to a 16-byte address.c.clamp .u32.op = { .u64. operations and and or apply to . the resulting behavior is undefined. or .clamp field specifies how to handle out-of-bounds addresses: .ctype = { .trap .b32 }.ctype = { . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.2d.s32 or .s32.b32.clamp [a.u32.max. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. is a two-element vector for 2d surfaces. .b. or the instruction may fault. {x.clamp. . r1. Operand a is a .b performs an unformatted reduction on .2d.trap sured. The instruction type is restricted to . Reduction to surface memory using a surface coordinate vector. 2010 127 . {x}]. sured. and the data is interpreted as .and.p. Operations add applies to . .trap [surf_A. Operand b is a scalar or singleton tuple for 1d surfaces.u32 based on the surface sample format as follows: if the surface format contains UINT data. . The lowest dimension coordinate represents a sample offset rather than a byte offset. .b32 type.0. sured. If an address is not properly aligned.or }. sured. then .b .add.s32 types.. .Chapter 8.geom.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32.ctype. where the fourth element is ignored.b].u32.geom = { .u32 and . // byte addressing sured. sured requires sm_20 or later.u64 data. the access may proceed by silently masking off low-order address bits to achieve proper rounding.y}].3d }.1d.b32.min. then . and . . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.zero }.s32 types. .b]. Instruction Set Table 92.u32. i. // for sured. [surf_B.op. .e.min. . sured. January 24.p .b32 }.s32. . and is a four-element vector for 3d surfaces.surfref variable.1d. // for sured. min and max apply to .u32 is assumed. . . The . // sample addressing .trap. Coordinate elements are of type . . .u64.clamp = { . r1. .

PTX ISA Version 2. Supported on all target architectures.depth }. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. .b32 %r1.surfref variable.b32 d.width. [surf_A]. .0 Table 93. [a].height. Description Query an attribute of a surface. suq. Operand a is a . 2010 .depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq.query. . 128 January 24. Query: .height .width .5.query = { .width.

2010 129 .7. ratio. @{!}p instruction.x.a. Threads with a false guard predicate do nothing. setp.c.s32 a. Supported on all target architectures. { add. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.7.f32 @!p div. used primarily for defining a function body. } PTX ISA Notes Target ISA Notes Examples Table 95. If {!}p then instruction Introduced in PTX ISA version 1. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. {} Syntax Description Control Flow Instructions: { } Instruction grouping.y. { instructionList } The curly braces create a group of instructions. Instruction Set 8. Execute an instruction or instruction block for threads that have the guard predicate true.b. Supported on all target architectures. Introduced in PTX ISA version 1.Chapter 8.eq.0.s32 d.f32 @q bra L23. mov.0.0. p.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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the final value is written to the destination register in all threads waiting at the barrier. all-threads-true (. it is as if all the threads in the warp have executed the bar instruction. while . Operand b specifies the number of threads participating in the barrier. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. Barriers are executed on a per-warp basis as if all the threads in a warp are active.red instruction. Register operands.cta.. operands p and c are predicates. 2010 133 .u32.popc.arrive using the same active barrier. The reduction operations for bar.red are population-count (. and bar. Only bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.sync and bar.op = { . Once the barrier count is reached.sync bar. When a barrier completes.red.pred .sync with an immediate barrier number is supported for sm_1x targets.red.0. it simply marks a thread's arrival at the barrier. a. Instruction Set Table 100.{arrive.arrive a{. b. p. bar.sync and bar.sync) until the barrier count is met.Chapter 8.arrive does not cause any waiting by the executing threads.arrive.popc). In conditionally executed code. and d have type . {!}c.sync 0. All threads in the warp are stalled until the barrier completes. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.version 2. and any-thread-true (. b}. The barrier instructions signal the arrival of the executing threads at the named barrier.red also guarantee memory ordering among threads identical to membar.and. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). threads within a CTA that wish to communicate via memory can store to memory. bar.0. a{.{arrive. If no thread count is specified. Description Performs barrier synchronization and communication within a CTA.and and . The result of .red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.red performs a predicate reduction across the threads participating in the barrier.and).or }.op. and bar. Thus. b}.or). a{. and then safely read values stored by other threads prior to the barrier. thread count. thread count. bar.sync or bar. b}. In addition to signaling its arrival at the barrier. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.red delays the executing threads (similar to bar. the waiting threads are restarted without delay. Thus. Since barriers are executed on a per-warp basis. . and the barrier is reinitialized so that it can be immediately reused.red performs a reduction operation across threads. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). d.red} introduced in PTX . PTX ISA Notes Target ISA Notes Examples bar. Register operands. bar. {!}c. bar. b.popc is the number of threads with a true predicate. all threads in the CTA participate in the barrier. Execution in this case is unpredictable. January 24.red should not be intermixed with bar. Note that a non-zero thread count is required for bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.sync or bar. the bar. bar. bar. the optional thread count must be a multiple of the warp size. execute a bar.15.sync without a thread count introduced in PTX ISA 1. bar. bar. Operands a. Each CTA instance has sixteen barriers numbered 0.u32 bar.red} require sm_20 or later. if any thread in a warp executes a bar instruction.

and memory reads by this thread can no longer be affected by other thread writes.sys }. .gl} supported on all target architectures. PTX ISA Notes Target ISA Notes Examples membar.0 Table 101.level = { .version 1. level describes the scope of other clients for which membar is an ordering event.PTX ISA Version 2.sys will typically have much longer latency than membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. A memory read (e. .gl. when the previous value can no longer be read.{cta.gl. 2010 .cta.g.sys introduced in PTX .sys. membar. global. membar. A memory write (e. by st.cta Waits until all prior memory writes are visible to other threads in the same CTA. Waits until prior memory reads have been performed with respect to other threads in the CTA. that is. 134 January 24.version 2. membar.sys Waits until all prior memory requests have been performed with respect to all clients.gl} introduced in PTX . membar.sys requires sm_20 or later. membar.gl. For communication between threads in different CTAs or even different SMs. membar.0. membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.4.g.{cta. membar. including thoses communicating via PCI-E such as system and peer-to-peer memory.gl will typically have a longer latency than membar. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar. membar. or system memory level. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.level. . this is the appropriate level of membar.cta. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.cta.

xor.s32. . overwriting the original value. The bit-size operations are and. e. b. Addresses are zero-extended to the specified width as needed. dec. A register containing an address may be declared as a bit-size type or integer type. . . In generic addressing. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b32 only . and max. inc. . [a]. or. For atom. max.op. Description // // // // // .u32.b64 . atom{. If no state space is given. accesses to local memory are illegal.e. .s32. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. and stores the result of the specified operation at location a. . . the resulting behavior is undefined. . . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The integer operations are add. January 24. 32-bit operations. If an address is not properly aligned. or the instruction may fault. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . an address maps to the corresponding location in local or shared memory. Instruction Set Table 102. c.add.. .add. . or by using atom.xor.type d. . . min. a de-referenced register areg containing a byte address.b32. . .and. performs a reduction operation with operand b and the value in location a. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.type atom{.space}.s32. i.shared }. perform the memory accesses using generic addressing.u64 .g.space}.cas. The floating-point operations are add. The address must be naturally aligned to a multiple of the access size.u64.b].inc. .f32 }.b64. Operand a specifies a location in the specified state space. min. Within these windows. . min. and truncated if the register width exceeds the state space address width for the target architecture.op. The inc and dec operations return a result in the range [0.u32..u32. atom. .max }.e.exch to store to locations accessed by other atomic operations. .global.f32. d. [a].exch. . cas (compare-and-swap). . or [immAddr] an immediate absolute byte address.or. The floating-point add.op = { . an address maps to global memory unless it falls within the local memory window or the shared memory window. and exch (exchange).type = { . i. by inserting barriers between normal stores and atomic operations to a common address.f32 Atomically loads the original value at location a into destination register d.u32 only .min. . b.space = { .b32.dec.Chapter 8. and max operations are single-precision. . 2010 135 . The address size may be either 32-bit or 64-bit.

my_val.0.PTX ISA Version 2. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. 64-bit atom.global.f32.shared operations require sm_20 or later.my_new_val. atom. b). : r-1.0 Semantics atomic { d = *a. *a = (operation == cas) ? : } where inc(r.global. s) = (r > s) ? s exch(r.s32 atom. 2010 . Release Notes Examples @p 136 January 24.cas.s.{min. d.{add.add.b32 d.t) = (r == s) ? t operation(*a.shared requires sm_12 or later. cas(r. c) operation(*a. s) = s. d. s) = (r >= s) ? 0 dec(r. atom.exch} requires sm_12 or later. : r+1. 64-bit atom.max} are unimplemented.add.0.f32 atom. b.[x+4].shared. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.cas.[a].global requires sm_11 or later. atom. Introduced in PTX ISA version 1.f32 requires sm_20 or later.[p].1. atom. : r. Use of generic addressing requires sm_20 or later. atom.max.

Description // // // // . . the resulting behavior is undefined. A register containing an address may be declared as a bit-size type or integer type.s32. January 24. . dec.add. Addresses are zero-extended to the specified width as needed. The integer operations are add. The address size may be either 32-bit or 64-bit.type [a]. and truncated if the register width exceeds the state space address width for the target architecture.u64 . an address maps to the corresponding location in local or shared memory.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. an address maps to global memory unless it falls within the local memory window or the shared memory window.f32 Performs a reduction operation with operand b and the value in location a. .f32 }. min.inc.u32. Within these windows. b.. i.b].type = { . .s32.s32. red{. where inc(r.Chapter 8. In generic addressing. or by using atom. or. If an address is not properly aligned. inc.add.u64.u32 only . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. min.e. .max }.xor.space = { .b32. For red. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f32.op = { . . s) = (r > s) ? s : r-1. .or. max. by inserting barriers between normal stores and reduction operations to a common address. or [immAddr] an immediate absolute byte address. Instruction Set Table 103. and max operations are single-precision. a de-referenced register areg containing a byte address.dec. or the instruction may fault. overwriting the original value.shared }. 2010 137 . . If no state space is given. .space}. and stores the result of the specified operation at location a. .and. e.u32.b32 only .b64.u32. The floating-point operations are add.g. Notes Operand a must reside in either the global or shared state space.exch to store to locations accessed by other reduction operations. i. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . s) = (r >= s) ? 0 : r+1.min. The floating-point add. . red. min. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. 32-bit operations. Semantics *a = operation(*a. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. . The inc and dec operations return a result in the range [0.global. perform the memory accesses using generic addressing. Operand a specifies a location in the specified state space. . The address must be naturally aligned to a multiple of the access size. and max. .op. .e. . b).. . accesses to local memory are illegal. and xor. dec(r. . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . The bit-size operations are and.

[p].global.add.global requires sm_11 or later red.f32 red.my_val. 2010 .{min.and. Release Notes Examples @p 138 January 24. [x+4].b32 [a].shared requires sm_12 or later.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. red.shared operations require sm_20 or later.s32 red. 64-bit red.add requires sm_12 or later.max} are unimplemented.2.PTX ISA Version 2.add. Use of generic addressing requires sm_20 or later.f32 requires sm_20 or later.max. red.shared.f32. red.global.1. red. 64-bit red.0.

PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. vote requires sm_12 or later. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.all. Negating the source predicate also computes . returns bitmask .none.b32 d. 2010 139 .ballot. where the bit position corresponds to the thread’s lane id.pred vote. .ballot.all.2. p. vote.ballot. {!}a.all True if source predicate is True for all active threads in warp. . Instruction Set Table 104.uni }. vote.b32 p. Negate the source predicate to compute .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.any True if source predicate is True for some active thread in warp.Chapter 8.pred vote.q. {!}a.any. The reduction modes are: . The destination predicate value is the same across all threads in the warp. .p.b32 requires sm_20 or later.mode. // ‘ballot’ form. Description Performs a reduction of the source predicate across threads in a warp.q. vote.uni.not_all.ballot. // get ‘ballot’ across warp January 24.mode = { . not across an entire CTA.pred d. In the ‘ballot’ form. vote.uni True if source predicate has the same value in all active threads in warp. Negate the source predicate to compute .uni. r1. Note that vote applies to threads in a single warp. vote. .

btype = { . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. .add. and btype are valid. to produce signed 33-bit input values.b1.asel}. a{.s33 values. 4.secop = { .extended internally to . .dtype. with optional secondary operation vop.b2.atype = .s32 }.s34 intermediate result. vop.dsel. b{. 3. b{.dtype = . half-word. with optional data merge vop. .btype{.min. c. The general format of video instructions is as follows: // 32-bit scalar operation.dsel = . The primary operation is then performed to produce an .or zero-extend byte.b0. or word values from its source operands. .u32 or . b{. // 32-bit scalar operation. 2010 . .atype.h1 }. perform a scalar arithmetic operation to produce a signed 34-bit result. . Using the atype/btype and asel/bsel specifiers.7. .sat} d. 140 January 24. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.max }.bsel}. optionally clamp the result to the range of the destination type.secop d.asel = . .atype.bsel}. all combinations of dtype. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).b3. . . atype.dtype.u32.s32) is specified in the instruction type. a{. taking into account the subword destination size in the case of optional data merging.btype{.0 8.9. Video Instructions All video instructions operate on 32-bit register operands. the input values are extracted and signor zero. . a{.h0.asel}.dtype. The source and destination operands are all 32-bit registers. The type of each operand (.asel}.btype{.sat} d.sat}. c.PTX ISA Version 2. extract and sign. The sign of the intermediate result depends on dtype.bsel = { . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.atype.bsel}. 2.

s33 c) { switch ( secop ) { . U8_MAX. U8_MIN ). S8_MAX.s33 optSaturate( . } } . default: return tmp. tmp. S32_MAX. The sign of the c operand is based on dtype. . . S16_MIN ).b0.b1: return ((tmp & 0xff) << 8) case .b3: return ((tmp & 0xff) << 24) default: return tmp.b2: return ((tmp & 0xff) << 16) case . Modifier dsel ) { if ( !sat ) return tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case . U16_MIN ).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp.h1: return ((tmp & 0xffff) << 16) case . c). . 2010 141 . c).b1. U32_MIN ). U16_MAX. c).b2.s33 tmp. as shown in the following pseudocode.add: return tmp + c.s33 optMerge( Modifier dsel. c). . . c). switch ( dsel ) { case . S8_MIN ). tmp. tmp. . .Chapter 8.max return MAX(tmp. . S32_MIN ). January 24. S16_MAX. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 optSecOp(Modifier secop. tmp. c). Bool sat.min: return MIN(tmp. .h0. Bool sign.s33 c ) switch ( dsel ) { case .s34 tmp. U32_MAX.h0: return ((tmp & 0xffff) case . Instruction Set . c).s33 tmp. The lower 32-bits are then written to the destination operand. . tmp. . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).b0: return ((tmp & 0xff) case .

with optional data merge vop.sat vabsdiff.s32.asel}. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. isSigned(dtype). c. . Video Instructions: vadd.add r1. Semantics // saturate.sat.PTX ISA Version 2.s32. r1.dsel.bsel}.s32. c. dsel ).s32. vadd.u32. b{.0 Table 105.s32.sat}. vmax require sm_20 or later. .s32. tb ). vsub. tmp = MAX( ta. { .h1 }.or zero-extend based on source operand type ta = partSelectSignExtend( a. taking into account destination type and merge operations tmp = optSaturate( tmp.s32.bsel = { . . r3.h0. asel ).b0. vmax }. a{.asel}. vmin. // 32-bit scalar operation. 2010 . r2. // 32-bit scalar operation. vop.b2.atype. // optional secondary operation d = optMerge( dsel.dtype . vsub vabsdiff vmin. .sat vsub. r2.u32. tmp = MIN( ta. sat. vabsdiff.s32.dtype. vmax vadd.0. c ). tmp = | ta – tb |.atype = . vadd. .min.vop . b{. a{.op2 Description = = = = { vadd. tmp. r3. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b2. vabsdiff.dsel . with optional secondary operation vop.atype. vmin. tb ).btype{.btype = { . // extract byte/half-word/word and sign. vsub.op2 d. Perform scalar arithmetic operation with optional saturate.dtype. c ). tb = partSelectSignExtend( b.dtype. . and optional secondary arithmetic operation or subword data merge. r2.asel = .bsel}. vmax Syntax Integer byte/half-word/word addition / subtraction. r1.sat} d. r3. c.bsel}.s32. .h0.s32. .asel}. // optional merge with c operand 142 January 24.h1.add.sat vmin. r3.b0.h0. a{. tmp = ta – tb.btype{. r1.b3.sat} d. c. btype. bsel ). atype. vabsdiff.max }. vmin.h1. Integer byte/half-word/word minimum / maximum. d = optSecondaryOp( op2. r2. b{. .btype{.b1.b0.s32 }.u32. Integer byte/half-word/word absolute value of difference. .atype. . vsub. tmp.

atype. // 32-bit scalar operation.dtype. c. sat.op2 Description = = = = = { vshl.atype.mode} d.u32.dsel.asel}.clamp && tb > 32 ) tb = 32. vshr vshl. and optional secondary arithmetic operation or subword data merge.h1. taking into account destination type and merge operations tmp = optSaturate( tmp.b0. { .vop .sat}{. tmp. c ). .b1. with optional data merge vop. Semantics // extract byte/half-word/word and sign. unsigned shift fills with zero. if ( mode == .clamp . dsel ).mode}.b2. vop.u32{. c.asel}.0.wrap }. b{.h1 }. . r2.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32 }. . . 2010 143 .atype = { . tb = partSelectSignExtend( b. b{.u32.u32{. vshr require sm_20 or later.h0. vshl.wrap ) tb = tb & 0x1f. Instruction Set Table 106. a{. . vshr }. } // saturate. case vshr: tmp = ta >> tb.mode} d.s32. r1. . r2. bsel ). vshl: Shift a left by unsigned amount in b with optional saturate.sat}{.clamp.bsel}. r3. tmp. b{. // 32-bit scalar operation. .u32{. .b3.op2 d. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Signed shift fills with the sign bit.sat}{.dtype. c ).u32 vshr.Chapter 8. January 24.wrap r1. a{. switch ( vop ) { case vshl: tmp = ta << tb. { . .bsel}.add.asel}. r3. // optional secondary operation d = optMerge( dsel. asel ). isSigned(dtype).u32. and optional secondary arithmetic operation or subword data merge.atype. vshl.max }.mode .bsel}. vshr: Shift a right by unsigned amount in b with optional saturate.asel = . d = optSecondaryOp( op2.dsel .dtype .bsel = { .dtype.min. . with optional secondary operation vop. // default is . a{.u32. vshr Syntax Integer byte/half-word/word left / right shift. Video Instructions: vshl. . .atype. if ( mode == . Left shift fills with zero.u32.u32.

.po{.h0. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. this result is sign-extended if the final result is signed. c.btype. Source operands may not be negated in . . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. . with optional operand negates. .dtype = . final signed (S32 * S32) + S32 // intermediate signed.dtype. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.bsel}.b3.PTX ISA Version 2.. “plus one” mode.S32 // intermediate signed. final signed (S32 * U32) + S32 // intermediate signed. .btype = { .scale = { . Description Calculate (a*b) + c.sat}{. . 144 January 24.dtype.scale} d. final signed (U32 * S32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift. The final result is unsigned if the intermediate result is unsigned and c is not negated.shr15 }. {-}b{. the intermediate result is signed.po) computes (a*b) + c + 1.h1 }. final unsigned -(U32 * U32) + S32 // intermediate signed. The “plus one” mode (. b{.bsel = { .btype{. final signed (S32 * S32) . . {-}c. That is. Depending on the sign of the a and b operands. otherwise.s32 }. and the operand negates. 2010 . vmad. . {-}a{. and zero-extended otherwise.S32 // intermediate signed.atype = .atype.po mode.sat}{.atype. final signed -(S32 * U32) + S32 // intermediate signed. final signed -(S32 * S32) + S32 // intermediate signed. PTX allows negation of either (a*b) or c. final signed (S32 * U32) .b0. Input c has the same sign as the intermediate result. internally this is represented as negation of the product (a*b). which is used in computing averages.scale} d. .0 Table 107.bsel}.shr7. a{.u32. final signed (U32 * U32) .b1. Although PTX syntax allows separate negation of the a and b operands.asel = . (a*b) is negated if and only if exactly one of a or b is negated. final signed (U32 * S32) . The source operands support optional negation with some restrictions.S32 // intermediate signed. . final signed -(U32 * S32) + S32 // intermediate signed.U32 // intermediate unsigned. // 32-bit scalar operation vmad.asel}. and scaling.b2. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.asel}.

S32_MIN). lsb = 1. r1.shr15 r0.negate. -r3.negate ^ b. r3. else result = CLAMP(result.s32.s32. r2.sat ) { if (signedFinal) result = CLAMP(result.u32. S32_MAX. vmad. tb = partSelectSignExtend( b.negate ) { c = ~c. btype. Instruction Set Semantics // extract byte/half-word/word and sign.sat vmad. January 24.u32. U32_MAX.negate ) { tmp = ~tmp. 2010 145 . r0. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). switch( scale ) { case .negate) || c. U32_MIN). tmp = tmp + c128 + lsb.Chapter 8. lsb = 0. atype.0. asel ). } else if ( a.u32. bsel ).shr7: result = (tmp >> 7) & 0xffffffffffffffff.h0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate ^ b. vmad requires sm_20 or later. r2. signedFinal = isSigned(atype) || isSigned(btype) || (a. } else if ( c. tmp[127:0] = ta * tb. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a. lsb = 1. if ( .h0. } if ( . case . r1.po ) { lsb = 1.

c ).bsel}. b{. . c. . bsel ). // 32-bit scalar operation.s32. with optional secondary arithmetic operation or subword data merge. r1. a{.op2 d. . . with optional secondary operation vset.atype. r2.ge }. tb. Semantics // extract byte/half-word/word and sign.btype. . b{.btype = { . r2.or zero-extend based on source operand type ta = partSelectSignExtend( a. tmp.0.atype.min.s32 }. vset requires sm_20 or later. 2010 .ne.btype. and therefore the c operand and final result are also unsigned. r3.b2. Compare input values using specified comparison. cmp ) ? 1 : 0. The intermediate result of the comparison is always unsigned.b1.btype.cmp . . a{. asel ). .u32. . { . with optional data merge vset. tmp. . .op2 Description = = = = .h1 }. atype. tmp = compare( ta.h1. 146 January 24.asel}.asel = .eq.bsel}. c ). .u32. r3.add. // 32-bit scalar operation. { . // optional secondary operation d = optMerge( dsel.atype. c. b{.max }. tb = partSelectSignExtend( b.lt vset.u32. vset. .h0.atype . vset.cmp d.le. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. d = optSecondaryOp( op2.ne r1.cmp d.bsel}. .gt. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. btype.bsel = { .lt.asel}.b3.PTX ISA Version 2.u32.cmp. a{.asel}.b0.dsel .0 Table 108.dsel. . .

Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. brkpt. January 24. numbered 0 through 15.4. trap Abort execution and generate an interrupt to the host CPU. with index specified by immediate operand a.0. @p pmevent 1. pmevent 7. trap. trap.Chapter 8.7. Table 110.0. 2010 147 . Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. brkpt requires sm_11 or later. Supported on all target architectures. Instruction Set 8. Table 111. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Notes PTX ISA Notes Target ISA Notes Examples Currently. brkpt Suspends execution Introduced in PTX ISA version 1. there are sixteen performance monitor events. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Supported on all target architectures. The relationship between events and counters is programmed via API calls from the host. Introduced in PTX ISA version 1.10. Triggers one of a fixed number of performance monitor events. pmevent a. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Introduced in PTX ISA version 1. brkpt.

2010 .0 148 January 24.PTX ISA Version 2.

Chapter 9. …. %clock64 %pm0. %lanemask_lt. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_gt %clock. %pm3 January 24. 2010 149 . %lanemask_ge. %lanemask_le. read-only variables. Special Registers PTX includes a number of predefined. which are visible as special registers and accessed through mov or cvt instructions.

. The fourth element is unused and always returns zero. %ntid.y. The total number of threads in a CTA is (%ntid.%ntid. The %tid special register contains a 1D.y. %tid. // thread id vector // thread id components A predefined.y. Every thread in the CTA has a unique %tid.v4.v4 .x code accessing 16-bit component of %tid mov.PTX ISA Version 2. mad. // zero-extend tid.x. %tid.%tid. %tid component values range from 0 through %ntid–1 in each CTA dimension.z).u32 %ntid.v4.sreg .z == 0 in 2D CTAs.sreg . %ntid. The number of threads in each dimension are specified by the predefined special register %ntid.x 0 <= %tid. %tid.x.0 Table 112.u32 %r0.%h1.z == 1 in 1D CTAs. Redefined as .0.z to %r2 Table 113.z PTX ISA Notes Introduced in PTX ISA version 1.sreg .%ntid. Supported on all target architectures. PTX ISA Notes Introduced in PTX ISA version 1. // CTA shape vector // CTA dimensions A predefined. mov.y 0 <= %tid.%r0.x to %rh Target ISA Notes Examples // legacy PTX 1. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.x code Target ISA Notes Examples 150 January 24.u32 %tid.z == 1 in 2D CTAs.x. %tid.u32 %tid. 2010 . cvt.%h2. // compute unified thread id for 2D CTA mov.y == %ntid.%tid.u32. . read-only special register initialized with the number of thread ids in each CTA dimension.0. per-thread special register initialized with the thread identifier within the CTA. Redefined as .u32 type in PTX 2.v4 . Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.%tid.x * %ntid. the %tid value in unused dimensions is 0. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.z.z == 0 in 1D CTAs. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.sreg .0. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.y * %ntid.u16 %rh. read-only. 2D.x < %ntid.x.z.x.u32 %ntid.%tid.z < %ntid. mov. It is guaranteed that: 0 <= %tid.u32 %h1. CTA dimensions are non-zero.z.0. . or 3D vector to match the CTA shape.x. .u32 %r0.u32 %r1.y == %tid. mov. the fourth element is unused and always returns zero.u32 %h2. %ntid.u16 %r2. mov. // move tid. // legacy PTX 1. Supported on all target architectures.u32 type in PTX 2.y < %ntid. %ntid.u16 %rh.x.%tid.

A predefined. Introduced in PTX ISA version 1.3.0.u32 %r. Special Registers Table 114. read-only special register that returns the maximum number of warp identifiers. PTX ISA Notes Target ISA Notes Examples Table 116.sreg . read-only special register that returns the thread’s warp identifier. Introduced in PTX ISA version 2. Supported on all target architectures. read-only special register that returns the thread’s lane within the warp. A predefined. . e.u32 %laneid.sreg . Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. For this reason. 2010 151 .u32 %r.3. due to rescheduling of threads following preemption.u32 %r. A predefined. Note that %warpid is volatile and returns the location of a thread at the moment when read. mov. %nwarpid. . %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. but its value may change during execution. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. %nwarpid requires sm_20 or later.Chapter 9.u32 %nwarpid. Table 115. mov. Supported on all target architectures. The warp identifier will be the same for all threads within a single warp. January 24. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.sreg . mov. .g. The lane identifier ranges from zero to WARP_SZ-1. Introduced in PTX ISA version 1. %warpid. %laneid.u32 %warpid.

0.%nctaid. %rh.x.u16 %r0. // legacy PTX 1. mov.sreg . Redefined as . Supported on all target architectures.u16 %r0. The fourth element is unused and always returns zero. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. // CTA id vector // CTA id components A predefined. . It is guaranteed that: 0 <= %ctaid.0. %ctaid.y 0 <= %ctaid.z < %nctaid.y.%ctaid. The %nctaid special register contains a 3D grid shape vector.{x.y.%nctaid. or 3D vector.x. %rh. 2010 .u32 mov.x.x 0 <= %ctaid.x. mov.0.v4 .536 PTX ISA Notes Introduced in PTX ISA version 1. Supported on all target architectures.z} < 65.u32 %ctaid.sreg .z.%nctaid.PTX ISA Version 2. The fourth element is unused and always returns zero. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.y. read-only special register initialized with the CTA identifier within the CTA grid.x code Target ISA Notes Examples Table 118. // legacy PTX 1.u32 mov. with each element having a value of at least 1.x < %nctaid.y.v4.sreg . read-only special register initialized with the number of CTAs in each grid dimension.%ctaid.0 Table 117.z.z PTX ISA Notes Introduced in PTX ISA version 1. It is guaranteed that: 1 <= %nctaid.x code Target ISA Notes Examples 152 January 24.sreg .u32 %nctaid. %ctaid. Redefined as . .%nctaid.u32 %nctaid . Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.v4 . depending on the shape and rank of the CTA grid. 2D.0.u32 %ctaid. // Grid shape vector // Grid dimensions A predefined. . Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.u32 type in PTX 2.x.u32 type in PTX 2. The %ctaid special register contains a 1D.v4.y < %nctaid. Each vector element value is >= 0 and < 65535.

This variable provides the temporal grid launch number for this context.0.0. %smid.u32 %nsmid. 2010 153 . . %nsmid.sreg . where each launch starts a grid-of-CTAs. mov.u32 %smid. PTX ISA Notes Target ISA Notes Examples Table 121. A predefined. A predefined. Introduced in PTX ISA version 2.sreg . so %nsmid may be larger than the physical number of SMs in the device. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. read-only special register that returns the maximum number of SM identifiers. repeated launches of programs may occur.Chapter 9.u32 %r. PTX ISA Notes Target ISA Notes Examples January 24. mov. The SM identifier numbering is not guaranteed to be contiguous. Special Registers Table 119.u32 %r.u32 %gridid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. The SM identifier ranges from 0 to %nsmid-1. Note that %smid is volatile and returns the location of a thread at the moment when read.3. Supported on all target architectures.g. The SM identifier numbering is not guaranteed to be contiguous. Supported on all target architectures. mov. Introduced in PTX ISA version 1. // initialized at grid launch A predefined.sreg . . due to rescheduling of threads following preemption. During execution.u32 %r. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. read-only special register initialized with the per-grid temporal grid identifier. . e. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. but its value may change during execution. %gridid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Notes PTX ISA Notes Target ISA Notes Examples Table 120. %nsmid requires sm_20 or later. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Introduced in PTX ISA version 1.

sreg .u32 %r. . . Table 124. A predefined.u32 %lanemask_eq. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2.u32 %r. Introduced in PTX ISA version 2.0 Table 122.0.u32 %r. A predefined. mov.u32 %lanemask_le. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. 2010 . %lanemask_le.sreg . 154 January 24. %lanemask_le requires sm_20 or later. %lanemask_lt requires sm_20 or later. %lanemask_eq requires sm_20 or later. Table 123.u32 %lanemask_lt. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. .0. mov. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. mov. %lanemask_eq.0.PTX ISA Version 2. %lanemask_lt. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg .

0. A predefined. Introduced in PTX ISA version 2. %lanemask_ge. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.Chapter 9. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. January 24.u32 %lanemask_ge.sreg .u32 %lanemask_gt. Introduced in PTX ISA version 2. %lanemask_ge requires sm_20 or later. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt.u32 %r. . 2010 155 . %lanemask_gt requires sm_20 or later.0.sreg . read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. A predefined. Table 126. mov. . Special Registers Table 125. mov.

u32 r1. read-only 32-bit unsigned cycle counter. mov. %pm2. .sreg . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Introduced in PTX ISA version 2.PTX ISA Version 2.%pm0. Introduced in PTX ISA version 1. …. %pm2. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.0. %pm3.%clock.0. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. read-only 64-bit unsigned cycle counter. and %pm3 are unsigned 32-bit read-only performance monitor counters. %clock64 requires sm_20 or later. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.sreg . Table 128. 156 January 24.u32 %clock. Table 129. Special registers %pm0. .sreg . %pm3 %pm0. mov.0 Table 127. The lower 32-bits of %clock64 are identical to %clock.%clock64.u32 r1. Introduced in PTX ISA version 1. Supported on all target architectures.u32 %pm0. %pm1. Special Registers: %pm0.u64 %clock64. 2010 . Supported on all target architectures. . Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.u64 r1. Their behavior is currently undefined. %pm1. %pm1. %pm2.3. mov.

Each ptx file must begin with a .version 1. PTX File Directives: . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0 .0. 2010 157 .version .version directive. Duplicate .4 January 24. .version . . PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.version directives are allowed provided they match the original . . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. and the target architecture for which the code was generated.version major.target Table 130.version 2.version Syntax Description Semantics PTX version number. Supported on all target architectures. Increments to the major number indicate incompatible changes to PTX. Directives 10. minor are integers Specifies the PTX language version number.version directive.minor // major.Chapter 10.1.

Introduced in PTX ISA version 1.f64 to .5. Note that .f64 instructions used.target directive specifies a single target architecture.texmode_unified) .target directives can be used to change the set of target features allowed during parsing. Target sm_20 Description Baseline feature set for sm_20 architecture. Requires map_f64_to_f32 if any . sm_10.texmode_independent texture and sampler information is bound together and accessed via a single .0 Table 131. where each generation adds new features and retains all features of previous generations. Adds {atom. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. texmode_unified. A program with multiple . sm_12. with only half being used by instructions converted from .samplerref descriptors.f64 storage remains as 64-bits. sm_11. Texturing mode introduced in PTX ISA version 1. PTX code generated for a given target can be run on later generation devices. PTX features are checked against the specified target architecture.f64 instructions used. Description Specifies the set of features in the target architecture for which the current ptx code was generated. map_f64_to_f32 }.f32. PTX File Directives: .version directive. A . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. 2010 . Requires map_f64_to_f32 if any . .global. The texturing mode is specified for an entire module and cannot be changed within the module.f64 instructions used. Adds double-precision support. Requires map_f64_to_f32 if any .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Disallows use of map_f64_to_f32. immediately followed by a . texmode_independent.target Syntax Architecture and Platform target.texref descriptor.red}.shared.texmode_unified . generations of SM architectures follow an “onion layer” model. Texturing mode: (default is . 64-bit {atom. The following table summarizes the features in PTX that vary according to target architecture.PTX ISA Version 2. Adds {atom. brkpt instructions.global.target directive containing a target architecture and optional platform options. vote instructions.target . 158 January 24. including expanded rounding modifiers.red}. In general.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. but subsequent .0. texture and sampler information is referenced with independent . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Supported on all target architectures.red}. Therefore.texref and . and an error is generated if an unsupported feature is used. sm_13. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Each PTX file must begin with a .

target sm_10 // baseline target architecture .target sm_20. texmode_independent January 24. 2010 159 .target sm_13 // supports double-precision .Chapter 10. Directives Examples .

entry filter ( .entry .4 and later. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. For PTX ISA versions 1.b32 x. At kernel launch.param . ld. and query instructions and cannot be accessed via ld. 2010 .surfref variables may be passed as parameters.b32 z ) Target ISA Notes Examples [x]. Kernel and Function Directives: .b32 y.b32 %r1. … } .param space memory and are listed within an optional parenthesized parameter list. Parameters are passed via . ld.texref.b32 %r<99>. PTX ISA Notes For PTX ISA version 1. .b32 %r2.samplerref.0 through 1. The shape and size of the CTA executing the kernel are available in special registers.param. ld.entry . [z].func Table 132. with optional parameters.param. etc. 160 January 24. and body for the kernel function.param { .reg .PTX ISA Version 2. parameter variables are declared in the kernel body. e. . Supported on all target architectures.entry kernel-name ( param-list ) kernel-body .param.entry cta_fft . opaque .param instructions.param . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. and . %ntid.b32 %r3.entry Syntax Description Kernel entry point and body. . %nctaid.entry kernel-name kernel-body Defines a kernel entry point name. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. the kernel dimensions and properties are established and made available via special registers. .0 through 1. store. These parameters can only be referenced by name within texture and surface load. parameters. . parameter variables are declared in the kernel parameter list.3. .2.g.0 10. [y].5 and later. Parameters may be referenced by name within the kernel body and loaded into registers using ld. Semantics Specify the entry point for a kernel program. In addition to normal parameters.param instructions.4.

param and st. Parameters in . which may use a combination of registers and stack locations to pass parameters. implements an ABI with stack. Directives Table 133.reg .reg .0.0 with target sm_20 allows parameters in the . .Chapter 10. Variadic functions are represented using ellipsis following the last fixed argument.func fname function-body . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. there is no stack.result.0 with target sm_20 supports at most one return value. other code. mov.reg . Parameters in register state space may be referenced directly within instructions in the function body. 2010 161 .2 for a description of variadic functions.func (.func . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. and recursion is illegal. A . parameters must be in the register state space.func (ret-param) fname (param-list) function-body Defines a function.b32 localVar. … Description // return value in fooval January 24.x code. Release Notes For PTX ISA version 1.reg . Variadic functions are currently unimplemented. and supports recursion. val1). Supported on all target architectures. PTX ISA 2. (val0.b32 rval.param instructions in the body. } … call (fooval). Parameters must be base types in either the register or parameter state space. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.b32 N. . The parameter lists define locally-scoped variables in the function body. Kernel and Function Directives: . Parameter passing is call-by-value.b32 rval) foo (. … use N. PTX 2. foo. if any. ret.func fname (param-list) function-body .param state space.param space are accessed using ld. including input and return parameters and optional function body.func definition with no body provides a function prototype. . dbl.func Syntax Function definition.f64 dbl) { . The implementation of parameter passing is left to the optimizing translator.

162 January 24.maxnreg.PTX ISA Version 2.pragma directives may appear at module (file) scope. and the . which pass information to the backend optimizing compiler.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. The . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. The interpretation of .g.3. registers) to increase total thread count and provide a greater opportunity to hide memory latency. to throttle the resource requirements (e. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.pragma directive is supported for passing information to the PTX backend. or as statements within a kernel or device function body. The directive passes a list of strings to the backend. at entry-scope. for example. the . 2010 .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. and .maxnctapersm (deprecated) .pragma The . .minnctapersm directives may be applied per-entry and must appear between an .0 10.maxntid directive specifies the maximum number of threads in a thread block (CTA).maxnreg directive specifies the maximum number of registers to be allocated to a single thread.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.entry directive and its body.maxntid and . These can be used. and the strings have no semantics within the PTX virtual machine model. PTX supports the following directives. Currently.maxntid . A general . . The directives take precedence over any module-level constraints passed to the optimizing backend.minnctapersm . the .maxnreg . Note that .maxntid.

maxctapersm.3. Supported on all target architectures. Introduced in PTX ISA version 1. Supported on all target architectures.maxntid nx .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. for example. Performance-Tuning Directives: . Introduced in PTX ISA version 1. . .maxntid nx. the backend may be able to compile to fewer registers.entry foo . 2010 163 .maxntid Syntax Maximum number of threads in thread block (CTA). ny .entry bar . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Exceeding any of these limits results in a runtime error or kernel launch failure. ny.maxntid .maxnreg .Chapter 10.maxntid 16. This maximum is specified by giving the maximum extent of each dimention of the 1D. nz Declare the maximum number of threads in the thread block (CTA).maxntid nx. The maximum number of threads is the product of the maximum extent in each dimension.16. .maxntid 256 .3.maxntid and . 2D. The actual number of registers used may be less. or the maximum number of registers may be further constrained by .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. or 3D CTA.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. The compiler guarantees that this limit will not be exceeded.entry foo . Performance-Tuning Directives: . . Directives Table 134.maxnreg n Declare the maximum number of registers per thread in a CTA.

0 as a replacement for . .0.maxnctapersm.maxntid to be specified as well. Performance-Tuning Directives: .maxnctapersm (deprecated) .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. additional CTAs may be mapped to a single multiprocessor. .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm in PTX ISA version 2. Supported on all target architectures.PTX ISA Version 2.minnctapersm 4 { … } 164 January 24.maxntid 256 . Optimizations based on . . Optimizations based on . For this reason. .maxntid and .0 Table 136.minnctapersm generally need .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. The optimizing backend compiler uses .0.maxnctapersm has been renamed to .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm generally need . Performance-Tuning Directives: . .maxntid 256 .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. if the number of registers used by the backend is sufficiently lower than this bound. However.entry foo .3.entry foo . Introduced in PTX ISA version 1. 2010 .minnctapersm . Supported on all target architectures.maxntid to be specified as well. Deprecated in PTX ISA version 2. Introduced in PTX ISA version 2.

entry-scoped.Chapter 10. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Performance-Tuning Directives: .pragma directive may occur at module-scope.entry foo . 2010 165 . See Appendix A for descriptions of the pragma strings defined in ptxas. The interpretation of . at entry-scope.pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma . or at statementlevel. Introduced in PTX ISA version 2. The . Directives Table 138. . Pass module-scoped. .pragma “nounroll”.pragma “nounroll”. Supported on all target architectures.pragma Syntax Description Pass directives to PTX backend compiler. or statement-level directives to the PTX backend compiler.pragma list-of-strings .0. { … } January 24.

byte byte-list // comma-separated hexadecimal byte values .264-1] . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .4byte int32-list // comma-separated hexadecimal integers in range [0. Introduced in PTX ISA version 1. 0x63613031.debug_pubnames. 0x00 166 January 24.byte 0x00. @@DWARF dwarf-string dwarf-string may have one of the .4byte 0x6e69616d. 0x6150736f. 2010 . 0x00.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. The @@DWARF syntax is deprecated as of PTX version 2. 0x00. 0x00.232-1] .debug_info .section . 0x02..4byte 0x000006b5.quad int64-list // comma-separated hexadecimal integers in range [0.. Deprecated as of PTX 2. “”. 0x00. 0x00 . @progbits .x code.section directive is new in PTX ISA verison 2.4.2. Supported on all target architectures. replaced by .4byte label . 0x5f736f63 .file .0. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00.byte 0x2b. 0x00000364.0 but is supported for legacy PTX version 1.PTX ISA Version 2. 0x736d6172 . 0x00. 0x61395a5f. Table 139.section directive.4byte .0 and replaces the @@DWARF syntax.0 10. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.section .loc The .

b32 label .section Syntax PTX section definition.b64 int64-list // comma-separated list of integers in range [0.Chapter 10.255] .0.b8 byte-list // comma-separated list of integers in range [0.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.loc . Source file location.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures. 0x00.0. Source file information. 0x00. Debugging Directives: . .b8 0x2b.232-1] . 0x00000364. . . } 0x02. 0x736d6172 0x00 Table 141.section . 0x00 0x61395a5f. Directives Table 140.b8 0x00. 0x00.b32 int32-list // comma-separated list of integers in range [0. Debugging Directives: . .loc line_number January 24.file . Supported on all target architectures.file filename Table 142.b32 0x000006b5.debug_info . replaces @@DWARF syntax.section section_name { dwarf-lines } dwarf-lines have the following formats: .. .0.. 2010 167 .debug_pubnames { .b32 . 0x00.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.. .section . 0x00.b32 0x6e69616d. . Debugging Directives: . Supported on all target architectures. 0x5f736f63 0x6150736f. 0x00.264-1] . 0x63613031.

visible Table 143.visible .0.extern identifier Declares identifier to be defined externally.6.visible identifier Declares identifier to be externally visible. // foo is defined in another module Table 144.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. 2010 .extern . . Introduced in PTX ISA version 1.global . Linking Directives .b32 foo.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern . .PTX ISA Version 2. Linking Directives: . Linking Directives: .extern .visible . Supported on all target architectures. // foo will be externally visible 168 January 24. Supported on all target architectures.global .b32 foo. . .0 10. Introduced in PTX ISA version 1.0.

0 CUDA 1.1 CUDA 2. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 January 24. Release Notes This section describes the history of change in the PTX ISA and implementation.0 CUDA 2.2 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1. CUDA Release CUDA 1. 2010 169 .1 CUDA 2.5 PTX ISA 2.3 PTX ISA 1.Chapter 11. The release history is as follows.0 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.1 PTX ISA 1.3 driver r190 CUDA 3.0.2 CUDA 2.4 PTX ISA 1.

f32 for sm_20 targets. Both fma. Changes in Version 2.1. and mul now support .1. while maximizing backward compatibility with legacy PTX 1.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 and mad.1. Instructions testp and copysign have been added.rn.0 11. These are indicated by the use of a rounding modifier and require sm_20.1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 require a rounding modifier for sm_20 targets. • • • • • 170 January 24.1.f32 requires sm_20.0 11.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.rp rounding modifiers for sm_20 targets. The mad.f32 instruction also supports . Single-precision add. 2010 .PTX ISA Version 2.ftz and . When code compiled for sm_1x is executed on sm_20 devices. rcp. New Features 11.sat modifiers. The mad.ftz modifier may be used to enforce backward compatibility with sm_1x.and double-precision div.rm and . Floating-Point Extensions This section describes the floating-point changes in PTX 2. The .0 for sm_20 targets. fma. A single-precision fused multiply-add (fma) instruction has been added.f32.f32 maps to fma. The changes from PTX ISA 1. Single. mad. The fma.1.x code and sm_1x targets. The goal is to achieve IEEE 754 compliance wherever possible. and sqrt with IEEE 754 compliant rounding have been added. sub.

A “bit reversal” instruction. local. Release Notes 11.3.le. Video instructions (includes prmt) have been added.clamp modifiers. clz. Instructions bar.shared have been extended to handle 64-bit data types for sm_20 targets. has been added.red}. %clock64. isspacep.red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Surface instructions support additional . Other new features Instructions ld. Instructions {atom. 2010 171 . New instructions A “load uniform” instruction. has been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. prefetchu. January 24. brev. e.red}.{and. A “vote ballot” instruction.minnctapersm to better match its behavior and usage. have been added. The . suld. and shared addresses to generic address and vice-versa has been added.lt. membar. popc.clamp and .zero.u32 and bar. vote.1. A “count leading zeros” instruction. Cache operations have been added to instructions ld.Chapter 11. New special registers %nsmid.section. A new directive. st. has been added. for prefetching to specified level of memory hierarchy. ldu. cvta. Instructions prefetch and prefetchu have also been added. st.b32. A “population count” instruction. A system-level membar instruction. ldu.ballot.maxnctapersm directive was deprecated and replaced with .popc.red. and red now support generic addressing. bfe and bfi.arrive instruction has been added. A “find leading non-sign bit” instruction. has been added.gt} have been added.2. Bit field extract and insert instructions. has been added.add. Instruction sust now supports formatted surface stores.g. . Instructions {atom. bfind. has been added.pred have been added.1.ge. .1. atom. The bar instruction has been extended as follows: • • • A bar.or}. has been added. Instruction cvta for converting global.1. bar now supports optional thread count and register operands. and sust. 11.sys. %lanemask_{eq.f32 have been implemented. prefetch.

3.red}.version is 1. if .ftz (and cvt for .{u32.f32. 2010 . the correct number is sixteen.1. cvt. {atom.target sm_1x. Formatted surface store with .s32. where .f32} atom.5.2. Semantic Changes and Clarifications The errata in cvt. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. call suld.ftz for PTX ISA versions 1. Instruction bra. Formatted surface load is unimplemented. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. Support for variadic functions and alloca are unimplemented.max} are not implemented.0 11. See individual instruction descriptions for details.{min. has been fixed.5 and later.PTX ISA Version 2. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. 11. In PTX version 1.4 and earlier. or .1.u32. To maintain compatibility with legacy PTX code.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. The underlying. 172 January 24.4 or earlier.s32. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. .p. stack-based ABI is unimplemented.p sust. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.f32 type is unimplemented.

disables unrolling of0 the loop for which the current block is the loop header. Note that in order to have the desired effect at statement level. … @p bra L1_end. Descriptions of .0. Supported only for sm_20 targets. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.entry foo (…) . . L1_body: … L1_continue: bra L1_head.pragma “nounroll”. Ignored for sm_1x targets. Table 145. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. The “nounroll” pragma is allowed at module. and statement levels. { … } // do not unroll any loop in this function . Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. .pragma strings defined by ptxas. including loops preceding the . entry-function.pragma Strings This section describes the .func bar (…) { … L1_head: . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. 2010 173 .pragma.Appendix A. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. L1_end: … } // do not unroll this loop January 24. disables unrolling for all loops in the entry function body.pragma “nounroll”. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma “nounroll”.

2010 .0 174 January 24.PTX ISA Version 2.

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