NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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..........................2................4....5.........4........................................................................... 5..................................................................... 49 7.2..........................................................................4........................2....................1........................................4.................. Operand Type Information .......................... 6......2.......1....... 6...... Operand Costs .......1........................ Summary of Constant Expression Evaluation Rules ...... Instruction Operands........... 33 5............................ 5......... 6..................................4...........................................3............1....... 5........................................................................................................... Type Conversion..................................... 5......................... Texture......................................................................... 29 Global State Space ........1........ Function declarations and definitions ....... 6.................. 28 Special Register State Space ........4..........3....... 29 Parameter State Space ......... 5............................................................................. and Variables .........................6........................................ 43 Labels and Function Names as Operands .......1...................................3............2......................4................................... 43 Vectors as Operands .......................................................... 25 Chapter 5..................................................................1........................ 5. Chapter 6......................................6...................... 6........................1.................... and Surface Types ........................... Types ...3.........................8.................................. Sampler............................................. 34 Variables ...................... 28 Constant State Space . 5..............................5.............................................6.5............................. 6....................... 33 Restricted Use of Sub-Word Sizes .....................2...........2................................. and Vectors ...........................................................................PTX ISA Version 2..............................................................................................1............................................................................................5.... 30 Shared State Space...... 41 Destination Operands .................... State Spaces. 5............... 5............................ 46 6........ 39 5..... 6....................... 5....... 44 Rounding Modifiers ............................................. 2010 ........................................................................................................1................4...............................4...................................... Types....................1................................................................. 27 Register State Space .... 41 Source Operands... 5.1............1..................................... 5................2....................... 27 5......................... 5.....1....... 38 Alignment ........................ 5.............. 37 Vectors . 47 Chapter 7................................ State Spaces ...................................................6.............3.............. 44 Scalar Conversions ....................................................................................0 4.... 38 Initializers .7............... 41 6.............................. 37 Array Declarations .....................1............................................................... 32 5... Arrays.............................. 37 Variable Declarations ..... 33 Fundamental Types ...................................................................................... 49 ii January 24.... 43 6.... 39 Parameterized Variable Names ...1.....4.......... 41 Using Addresses.................................. 42 Addresses as Operands .. 42 Arrays as Operands ...............................4..... 5...4........... Abstracting the ABI ..........4.................................. 6................................................5............. 5.... 6................. 29 Local State Space ..............5..............4........ 32 Texture State Space (deprecated) ....4.........................2........................................................................................

.................................................4...........2.................................................................... PTX Version and Target Directives .................. 8......................................................... 7............. 8..................... 132 Video Instructions .. 63 Floating-Point Instructions ................ 162 Debugging Directives ......3. 10..............................................................4.................. 8........3......................................7................7....2................................... 62 Machine-Specific Semantics of 16-bit Code ................... 157 Specifying Kernel Entry Points and Functions .............................................................................................1. 8................... 8..... 8............. 8.....................8.......... Special Registers .......................................................................2.....................................6....7.......... 172 January 24.....................1.............. 108 Texture and Surface Instructions ....................7........0 ....................... 11........................................................... 59 Operand Size Exceeding Instruction-Type Size ............. 2010 iii ...................................... 129 Parallel Synchronization and Communication Instructions .......................4...................... 81 Comparison and Selection Instructions ........................... Type Information for Instructions and Operands ... 147 8............... Divergence of Threads in Control Constructs ........................................ 100 Logic and Shift Instructions .......... 11.................................................7.................. 170 Semantic Changes and Clarifications ............................................................................ 52 Variadic functions ...................... 10.. 122 Control Flow Instructions ......... 160 Performance-Tuning Directives ............................9.... Directives ....................1... Chapter 9. 11................ 55 Predicated Execution ........5...........................................................................................................1.................................. 168 Chapter 11.....7................7........... Format and Semantics of Instruction Descriptions .............................................................5........ 157 10..1..............1.........................................1...10...... Instruction Set ................3..........................................................................................1...1.. 57 Manipulating Predicates ................................ 169 11....................7...................................................7.... 60 8..........................................2............................................................................. 7... Release Notes ....................................... Changes from PTX 1................................................................7............................... 62 Semantics ........... 54 Chapter 8.............................. 56 Comparisons ...1.....7....... 104 Data Movement and Conversion Instructions ....................7............................................4............................................................................. 8................1....................................................... 166 Linking Directives ......................... 170 New Features ........ 58 8.............. 8........... 10.......................................3.................. Instructions .6...... 62 8...................................................................................... Changes in Version 2.................... 55 PTX Instructions .... 63 Integer Arithmetic Instructions .. 8....... 140 Miscellaneous Instructions....................... 8............................6.................................. 53 Alloca .. 8.............................. 8...1...................................1. 8..........x ................................................2. 55 8... 172 Unimplemented Features Remaining .. 8.................................................................3................................................................................. 10............7..... 149 Chapter 10.....2..................6...............................................3....................... 8..........................................3..................

..................PTX ISA Version 2.. 173 iv January 24............ 2010 ... Descriptions of ......0 Appendix A.............pragma Strings..............

.............. PTX Directives ................................... Table 12................................................. 46 Integer Rounding Modifiers ........... 64 Integer Arithmetic Instructions: sub ..................... Table 13................................................................ Table 9............. 27 Properties of State Spaces ............................................. 57 Floating-Point Comparison Operators Accepting NaN .................................. 35 Convert Instruction Precision and Format ......List of Tables Table 1..... Table 18............................... Table 29.cc ...................cc ........................................................................................................ Table 4........................................................................................................................................................... Table 31......................... Table 30............................ 35 Opaque Type Fields in Independent Texture Mode ...................................................................... 65 Integer Arithmetic Instructions: addc .................. Table 17... Table 24............................................................................................ Table 28... Table 14................ 69 Integer Arithmetic Instructions: mad24 ........................ Table 19............................ Table 21................................................................. Table 16............................ 66 Integer Arithmetic Instructions: mul ....................... 20 Operator Precedence .................. 59 Relaxed Type-checking Rules for Source Operands ........................ Table 3.... Table 26......... Table 15.................................................................................. Table 22.......................................... 46 Cost Estimates for Accessing State-Spaces ....................................... 61 Integer Arithmetic Instructions: add .............................................. 45 Floating-Point Rounding Modifiers . Table 32............................. Table 20........................................................... 66 Integer Arithmetic Instructions: subc ... Table 11........................ Table 27............................................................................................................ Table 10............................................................. 58 Type Checking Rules ....................... Table 7...... Table 23.................................. 70 Integer Arithmetic Instructions: sad ..................................... 23 Constant Expression Evaluation Rules ... Table 8................................. 58 Floating-Point Comparison Operators Testing for NaN ...................................................... Unsigned Integer............. 65 Integer Arithmetic Instructions: sub............................................................ 67 Integer Arithmetic Instructions: mad ........................................ Table 2.................. 71 January 24............................ 28 Fundamental Type Specifiers ........... 60 Relaxed Type-checking Rules for Destination Operands.............. 33 Opaque Type Fields in Unified Texture Mode ................... 47 Operators for Signed Integer......... 2010 v ............................................... 64 Integer Arithmetic Instructions: add.. and Bit-Size Types ............ Table 6...... 68 Integer Arithmetic Instructions: mul24 ............. 57 Floating-Point Comparison Operators ... Table 5..................... Table 25............................................................................................................................ 18 Reserved Instruction Keywords ................. 25 State Spaces .................................................................... 19 Predefined Identifiers ....................................

..... Table 51...... Table 68........................... 83 Floating-Point Instructions: add .................................... 102 Comparison and Selection Instructions: selp ................................. 79 Summary of Floating-Point Instructions .... 88 Floating-Point Instructions: div .................................................................. Table 34...... Table 38.... 91 Floating-Point Instructions: min ....... Integer Arithmetic Instructions: div ................. Table 53.. Table 56................. Table 65.....................................................................................................................PTX ISA Version 2...................... Table 54............ 71 Integer Arithmetic Instructions: abs ... Table 42................................................................. 95 Floating-Point Instructions: sin ............... Table 37....................... 90 Floating-Point Instructions: abs ................................................................... 76 Integer Arithmetic Instructions: bfe .........................................................................................0 Table 33.......................................................................................... 99 Comparison and Selection Instructions: set ................ Table 64.......................... Table 52........... 103 vi January 24.................................................................................................................................................. 73 Integer Arithmetic Instructions: max .......................... 103 Comparison and Selection Instructions: slct ............ 93 Floating-Point Instructions: sqrt ................. Table 63.. Table 62............................... Table 36... Table 39................................. Table 66........................ Table 48......... 77 Integer Arithmetic Instructions: bfi ............................................................................................................................................................................ Table 50.... 94 Floating-Point Instructions: rsqrt ........ 87 Floating-Point Instructions: mad ..................................... 92 Floating-Point Instructions: max .............. 86 Floating-Point Instructions: fma ................................. Table 69...................... 72 Integer Arithmetic Instructions: min ..... 75 Integer Arithmetic Instructions: brev ............. 74 Integer Arithmetic Instructions: bfind ............. Table 57............. 74 Integer Arithmetic Instructions: clz ................................... 72 Integer Arithmetic Instructions: neg ......................................... 82 Floating-Point Instructions: testp ....................... 2010 ................... Table 58.................... Table 49................ 83 Floating-Point Instructions: copysign .................... Table 41.......................................................... 101 Comparison and Selection Instructions: setp ...................... Table 40.............................................................................. 85 Floating-Point Instructions: mul ........................................................................................ 78 Integer Arithmetic Instructions: prmt .................................................................... 92 Floating-Point Instructions: rcp ............................................. Table 35................... 84 Floating-Point Instructions: sub ................................................... 71 Integer Arithmetic Instructions: rem ............ 97 Floating-Point Instructions: lg2 ............................................ Table 44....................................................................................................................................................................................................................................... Table 46................................................. Table 47. Table 43.................................................................................. Table 60...................... 96 Floating-Point Instructions: cos ................................................... 73 Integer Arithmetic Instructions: popc ........................................................... Table 55....... Table 45............... Table 61............................................................................................................ 98 Floating-Point Instructions: ex2 ....... Table 67........................................................................... 91 Floating-Point Instructions: neg ..................... Table 59..

... 107 Cache Operators for Memory Load Instructions ...... Table 98..................................... 135 Parallel Synchronization and Communication Instructions: red ................. 111 Data Movement and Conversion Instructions: mov .. Table 84.......... 109 Cache Operators for Memory Store Instructions ..................................................... 107 Logic and Shift Instructions: shr .......................... 131 Parallel Synchronization and Communication Instructions: bar ......................... 142 Video Instructions: vshl....... Table 104................ 120 Texture and Surface Instructions: tex ..................... prefetchu ........................................ 2010 vii ..................... Table 92.................... 106 Logic and Shift Instructions: cnot ............................. Table 85............. Table 77...................... 128 Control Flow Instructions: { } .......... 105 Logic and Shift Instructions: or ....... 137 Parallel Synchronization and Communication Instructions: vote ... Table 72. Table 94......... Table 106............................ 127 Texture and Surface Instructions: suq ................................................................... Table 105................................. Table 83.......................................................................................... Table 99.... 130 Control Flow Instructions: call ........................................................................................................ 125 Texture and Surface Instructions: sust ...................... Table 87. Table 97...................... 115 Data Movement and Conversion Instructions: st ................. Table 80. vmin................................................................ Table 103....... 133 Parallel Synchronization and Communication Instructions: membar ................. 143 January 24.............. 118 Data Movement and Conversion Instructions: isspacep ............................................................ Table 101. 116 Data Movement and Conversion Instructions: prefetch.......... 113 Data Movement and Conversion Instructions: ldu .......... 124 Texture and Surface Instructions: suld ............................... Table 75.. 134 Parallel Synchronization and Communication Instructions: atom ............................. Table 90.......................................... vshr ............... 129 Control Flow Instructions: bra . 139 Video Instructions: vadd.. 129 Control Flow Instructions: @ ............. Table 76.. 119 Data Movement and Conversion Instructions: cvta .............................. Table 78............................................................ 105 Logic and Shift Instructions: xor ................. Table 86..... Table 82.. Table 100...................... 106 Logic and Shift Instructions: shl .............................................. Table 74...... Table 95............................................................................ 131 Control Flow Instructions: exit .......... Table 73............. Table 89................................................................................ 130 Control Flow Instructions: ret .........Table 70........................................ vabsdiff...................... 106 Logic and Shift Instructions: not ............................ Table 71.................................................................. 123 Texture and Surface Instructions: txq ....................................................................................................... 119 Data Movement and Conversion Instructions: cvt .......... 112 Data Movement and Conversion Instructions: ld .......................................... Logic and Shift Instructions: and ........................................... 126 Texture and Surface Instructions: sured........................... Table 79................ Table 96.................................................................................. Table 93.................... Table 88...... 110 Data Movement and Conversion Instructions: mov ...................................................................... Table 91... Table 81................................. vsub............................................................ vmax ........................................................... Table 102................

.............. 153 Special Registers: %nsmid .. 156 Special Registers: %pm0................ 153 Special Registers: %gridid . 153 Special Registers: %lanemask_eq ................................................................................................................................................................... Table 117... Table 142..................... 164 Performance-Tuning Directives: .............................................. 158 Kernel and Function Directives: ............... Table 125.................. Table 123...................................... 151 Special Registers: %warpid .. 150 Special Registers: %laneid .................... Table 132........... %pm3 ................................................................................... Table 110............................... Table 119.......... Table 136.............. 155 Special Registers: %clock ..... 154 Special Registers: %lanemask_ge ......................... Table 126............. 161 Performance-Tuning Directives: ................. Table 141...... Table 120. Table 143..........target ........................................... Table 116.......... 168 viii January 24........................................................ Table 112...........entry..........................file .................... 160 Kernel and Function Directives: ............. 163 Performance-Tuning Directives: ............ 154 Special Registers: %lanemask_lt ................. 156 PTX File Directives: .............. 167 Debugging Directives: .......minnctapersm ...............................................PTX ISA Version 2................... 166 Debugging Directives: ..................................................................... 147 Miscellaneous Instructions: brkpt .maxnreg ............... Table 140..................................................... 2010 .. Table 113.......................................func ... Table 134........................... 150 Special Registers: %ntid .................... Table 118..................... Table 137...................... 165 Debugging Directives: @@DWARF ............................................... Table 127.............................................................. Table 109........................................ Table 128................... 151 Special Registers: %nwarpid ................................................................................................ 152 Special Registers: %smid ..................................................... Table 131............................................. Video Instructions: vmad ........................................................... 167 Linking Directives: ......................... Table 111................................. Table 138.............................................................pragma ............................................................................................... Table 135.............................................................................. %pm2......................................section ............................... Table 130............................. Table 121........... 155 Special Registers: %lanemask_gt ..... 164 Performance-Tuning Directives: ....... Table 108........................... 144 Video Instructions: vset.... 147 Miscellaneous Instructions: pmevent...........maxntid ................................ 147 Special Registers: %tid ............. Table 124.............version.......................................... 167 Debugging Directives: ............ 146 Miscellaneous Instructions: trap ............................................. Table 129.....0 Table 107........................ Table 139........... %pm1.................................. 151 Special Registers: %ctaid . 156 Special Registers: %clock64 ..................................... 152 Special Registers: %nctaid .............................. Table 115.................................................... Table 114.......................... 163 Performance-Tuning Directives: ......extern........................................... 157 PTX File Directives: ......................................................... 154 Special Registers: %lanemask_le ..maxnctapersm (deprecated) ................................................................................... Table 133.......................... Table 122...............loc .......................................................................................................

. Linking Directives: ................ 168 Pragma Strings: “nounroll” ... 2010 ix .Table 144.................... Table 145............................. 173 January 24...................................................................visible..................................

2010 .PTX ISA Version 2.0 x January 24.

Many applications that process large data sets can use a data-parallel programming model to speed up the computations. multithreaded. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. 1. there is a lower requirement for sophisticated flow control. and pattern recognition can map image blocks and pixels to parallel processing threads. high-definition 3D graphics.1. image and media processing applications such as post-processing of rendered images. PTX programs are translated at install time to the target hardware instruction set. stereo vision. Introduction This document describes PTX. 2010 1 . January 24. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Similarly.2. Data-parallel processing maps data elements to parallel processing threads. PTX exposes the GPU as a data-parallel computing device. image scaling. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. PTX defines a virtual machine and ISA for general purpose parallel thread execution. In fact. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). and because it is executed on many data elements and has high arithmetic intensity. 1. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. many-core processor with tremendous computational horsepower and very high memory bandwidth. Because the same program is executed for each data element. from general signal processing or physics simulation to computational finance or computational biology. the programmable GPU has evolved into a highly parallel. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. which are optimized for and translated to native target-architecture instructions. the memory access latency can be hidden with calculations instead of big data caches. video encoding and decoding.Chapter 1.

Most of the new features require a sm_20 target.0 are improved support for IEEE 754 floating-point operations. Legacy PTX 1. memory. addition of generic addressing to facilitate the use of general-purpose pointers. which map PTX to specific target machines. Facilitate hand-coding of libraries. A single-precision fused multiply-add (fma) instruction has been added. The fma. PTX 2. Single-precision add. A “flush-to-zero” (.3. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. reduction.0 is in improved support for the IEEE 754 floating-point standard.ftz) modifier may be used to enforce backward compatibility with sm_1x. The mad. Instructions marked with . surface. 1.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. sub.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.0 PTX ISA Version 2.1. Provide a common source-level ISA for optimizing code generators and translators. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. 2010 . PTX ISA Version 2. Achieve performance in compiled applications comparable to native GPU performance. and architecture tests. Provide a machine-independent ISA for C/C++ and other compilers to target.x code will continue to run on sm_1x targets as well. The main areas of change in PTX 2. 1.0 is a superset of PTX 1.ftz and .0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. The changes from PTX ISA 1.rm and .f32 maps to fma.f32 instruction also supports .f32 require a rounding modifier for sm_20 targets.PTX ISA Version 2.f32. mad. barrier.rn.3. • • • 2 January 24.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 for sm_20 targets. including integer.f32 and mad.sat modifiers. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.x features are supported on the new sm_20 target. and video instructions. Provide a code distribution ISA for application and middleware developers.x.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. atomic.rp rounding modifiers for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices. Both fma. and all PTX 1. performance kernels. fma.f32 requires sm_20. and mul now support . and the introduction of many new instructions. Improved Floating-Point Support A main area of change in PTX 2. The mad.

Chapter 1. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. stack-based ABI. Surface instructions support additional clamp modifiers. 1.2.. Generic Addressing Another major change is the addition of generic addressing. isspacep. suld. stack layout.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.0 closer to full compliance with the IEEE 754 standard. st. st. January 24. and Application Binary Interface (ABI). A new cvta instruction has been added to convert global. so recursion is not yet supported. Instruction cvta for converting global. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. local. allowing memory instructions to access these spaces without needing to specify the state space. for prefetching to specified level of memory hierarchy. prefetch. and shared state spaces. cvta. i. 1.0. Cache operations have been added to instructions ld. rcp. ldu. and directives are introduced in PTX 2. NOTE: The current version of PTX does not implement the underlying. an address that is the same across all threads in a warp.3. Surface Instructions • • Instruction sust now supports formatted surface stores. In PTX 2. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. 2010 3 . 1. Instructions prefetch and prefetchu have been added. local.g. These are indicated by the use of a rounding modifier and require sm_20. and vice versa.4. and sqrt with IEEE 754 compliant rounding have been added. Support for an Application Binary Interface Rather than expose details of a particular calling convention. PTX 2. Instructions testp and copysign have been added. these changes bring PTX 2.zero. and shared addresses to generic addresses. and shared addresses to generic address and vice-versa has been added. and sust.0. atom. • Taken as a whole.3. . local.e. instructions ld. Generic addressing unifies the global. New Instructions The following new instructions.3.clamp and . and red now support generic addressing.3. e. Introduction • Single.and double-precision div. special registers. prefetchu.

sys. 4 January 24. 2010 .red}.red}. has been added. bfi bit field extract and insert popc clz Atomic. Other Extensions • • • Video instructions (includes prmt) have been added. A “vote ballot” instruction.red.f32 have been added. has been added. %lanemask_{eq.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.pred have been added.shared have been extended to handle 64-bit data types for sm_20 targets. %clock64.{and.ge.popc. membar.ballot. Barrier Instructions • • A system-level membar instruction. Instructions {atom. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. and Vote Instructions • • • New atomic and reduction instructions {atom.arrive instruction has been added. Reduction.gt} have been added. .lt. New special registers %nsmid.u32 and bar.b32. A new directive. Instructions bar. A bar.add.PTX ISA Version 2.or}. vote. bar now supports an optional thread count and register operands.le.red.section.

Chapter 10 lists the assembly directives supported in PTX. Chapter 9 lists special registers.4. types. Chapter 11 provides release notes for PTX Version 2. and variable declarations. Chapter 5 describes state spaces. Chapter 7 describes the function and call syntax.Chapter 1. Chapter 8 describes the instruction set. Introduction 1. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 6 describes instruction operands. Chapter 4 describes the basic syntax of the PTX language. Chapter 3 gives an overview of the PTX virtual machine model. 2010 5 . January 24. and PTX support for abstracting the Application Binary Interface (ABI).0. calling convention.

PTX ISA Version 2.0 6 January 24. 2010 .

2010 7 . compute addresses. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. Cooperative thread arrays (CTAs) implement CUDA thread blocks.y. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.1. 2D.x. A cooperative thread array. 2. Programming Model 2.z). It operates as a coprocessor to the main CPU. The vector ntid specifies the number of threads in each CTA dimension. but independently on different data. More precisely. and select work to perform. Each CTA has a 1D. can be isolated into a kernel function that is executed on the GPU as many different threads. 2.y. work.1. compute-intensive portions of applications running on the host are off-loaded onto the device. data-parallel. Programs use a data parallel decomposition to partition inputs. Each thread has a unique thread identifier within the CTA.x. or CTA. To coordinate the communication of the threads within the CTA. (with elements tid. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. tid. Each CTA thread uses its thread identifier to determine its assigned role. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. is an array of threads that execute a kernel concurrently or in parallel.Chapter 2. ntid.2.2. or 3D shape specified by a three-element vector ntid (with elements ntid. or host: In other words. Threads within a CTA can communicate with each other. To that effect. assign specific input and output positions. and results across the threads of the CTA. one can specify synchronization points where threads wait until all threads in the CTA have arrived. a portion of an application that is executed many times. and tid. January 24. and ntid. The thread identifier is a three-element vector tid. 2D.z) that specifies the thread’s position within a 1D. or 3D CTA. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.

8 January 24. or sequentially. because threads in different CTAs cannot communicate and synchronize with each other. multiple-thread) fashion in groups called warps. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). read-only special registers %tid. The warp size is a machine-dependent constant. a warp has 32 threads. However. so that the total number of threads that can be launched in a single kernel invocation is very large. %nctaid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. or 3D shape specified by the parameter nctaid. Each grid also has a unique temporal grid identifier (gridid). WARP_SZ. Some applications may be able to maximize performance with knowledge of the warp size. Multiple CTAs may execute concurrently and in parallel. The host issues a succession of kernel invocations to the device. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. %ntid. such that the threads execute the same instructions at the same time. Each grid of CTAs has a 1D. CTAs that execute the same kernel can be batched together into a grid of CTAs. which may be used in any instruction where an immediate operand is allowed. This comes at the expense of reduced thread communication and synchronization. and %gridid. 2. 2D .PTX ISA Version 2.0 Threads within a CTA execute in SIMT (single-instruction. Threads within a warp are sequentially numbered. so PTX includes a run-time immediate constant. depending on the platform. %ctaid. Threads may read and use these values through predefined. A warp is a maximal subset of threads from a single CTA. Typically.2.2. 2010 .

0) Thread (0. Thread Batching January 24. A grid is a set of CTAs that execute independently. 1) Thread (3. 0) Thread (1. 2010 9 . 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (4. 1) Thread (0. 1) Grid 2 Kernel 2 CTA (1. 2) Thread (4. 1) CTA (2. 0) Thread (3. 0) CTA (2. 2) Thread (1. 1) Thread (0. 1) CTA (1. 2) Thread (2. Figure 1. 0) CTA (0. 2) Thread (3. 1) Thread (2. 1) Thread (4. 0) Thread (2.Chapter 2. 1) Thread (1. 0) CTA (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0.

Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. or. 10 January 24.3.PTX ISA Version 2. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. The global. 2010 . and texture memory spaces are optimized for different memory usages. The device memory may be mapped and read or written by the host. constant. Each thread has a private local memory. constant. for some specific data formats. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. respectively. as well as data filtering. The global. Finally.0 2. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. referred to as host memory and device memory. for more efficient transfer. and texture memory spaces are persistent across kernel launches by the same application. Both the host and the device maintain their own local memory. all threads have access to the same global memory. Texture memory also offers different addressing modes.

1) Grid 1 Global memory Block (0. 0) Block (1.Chapter 2. Memory Hierarchy January 24. 0) Block (0. 0) Block (0. 1) Block (2. 2010 11 . 1) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2) Block (1. 1) Block (1. 0) Block (2. 2) Figure 2. 0) Block (1.

0 12 January 24.PTX ISA Version 2. 2010 .

and on-chip shared memory. schedules. and when all paths complete. At every instruction issue time. so full efficiency is realized when all threads of a warp agree on their execution path. and each scalar thread executes independently with its own instruction address and register state. the warp serially executes each branch path taken. The multiprocessor creates.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. 2010 13 . When a host program invokes a kernel grid. A multiprocessor consists of multiple Scalar Processor (SP) cores. manages. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp.1. To manage hundreds of threads running several different programs. As thread blocks terminate. The way a block is split into warps is always the same. a voxel in a volume. disabling threads that are not on that path. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. allowing. and executes concurrent threads in hardware with zero scheduling overhead. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). the threads converge back to the same execution path. Branch divergence occurs only within a warp. and executes threads in groups of parallel threads called warps. The multiprocessor maps each thread to one scalar processor core. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. a cell in a grid-based computation). the first parallel thread technology. The multiprocessor SIMT unit creates. a multithreaded instruction unit. manages. the multiprocessor employs a new architecture we call SIMT (single-instruction. new blocks are launched on the vacated multiprocessors.Chapter 3. The threads of a thread block execute concurrently on one multiprocessor. When a multiprocessor is given one or more thread blocks to execute. for example. (This term originates from weaving. A warp executes one common instruction at a time. If threads of a warp diverge via a data-dependent conditional branch. it splits them into warps that get scheduled by the SIMT unit. It implements a single-instruction barrier synchronization. Parallel Thread Execution Machine Model 3. multiple-thread). each warp contains threads of consecutive. January 24. increasing thread IDs with the first warp containing thread 0. different warps execute independently regardless of whether they are executing common or disjointed code paths.

and writes to the same location in global memory for more than one of the threads of the warp. For the purposes of correctness. • The local and global memory spaces are read-write regions of device memory and are not cached. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. the number of serialized writes that occur to that location and the order in which they occur is undefined. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. If an atomic instruction executed by a warp reads. which is a read-only region of device memory. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. In practice. Vector architectures. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. SIMT enables programmers to write thread-level parallel code for independent. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. modify. require the software to coalesce loads into vectors and manage divergence manually. If there are not enough registers or shared memory available per multiprocessor to process at least one block. write to that location occurs and they are all serialized. whereas SIMT instructions specify the execution and branching behavior of a single thread. 2010 . the kernel will fail to launch. As illustrated by Figure 3. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. on the other hand. but the order in which they occur is undefined. as well as data-parallel code for coordinated threads. however. which is a read-only region of device memory. the programmer can essentially ignore the SIMT behavior. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. In contrast with SIMD vector machines. 14 January 24. but one of the writes is guaranteed to succeed.0 SIMT architecture is akin to SIMD (Single Instruction. A multiprocessor can execute as many as eight thread blocks concurrently. modifies.PTX ISA Version 2. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. A key difference is that SIMD vector organizations expose the SIMD width to the software. scalar threads. each read.

Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3. 2010 15 . Hardware Model January 24. Figure 3.

2010 .0 16 January 24.PTX ISA Version 2.

#if.1. whitespace is ignored except for its use in separating tokens in the language. #define.target directive specifying the target architecture assumed. Each PTX file must begin with a . PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Lines are separated by the newline character (‘\n’). Comments Comments in PTX follow C/C++ syntax.Chapter 4. January 24. Pseudo-operations specify symbol and addressing management.version directive specifying the PTX language version.2. #else. #endif. All whitespace characters are equivalent. 4. 4. Comments in PTX are treated as whitespace. followed by a . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. The following are common preprocessor directives: #include. Source Format Source files are ASCII text. See Section 9 for a more information on these directives. The C preprocessor cpp may be used to process PTX source files. Lines beginning with # are preprocessor directives. using non-nested /* and */ for comments that may span multiple lines. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. and using // to begin a comment that extends to the end of the current line. PTX is case sensitive and uses lowercase for keywords. 2010 17 . Syntax PTX programs are a collection of text source files. #ifdef. #line.

followed by source operands.version . array[r1]. The guard predicate may be optionally negated. .b32 r1. r1.pragma . Instructions have an optional guard predicate which controls conditional execution.reg .global start: .3.f32 r2.f32 array[N].minnctapersm .shared . and terminated with a semicolon. shl.reg . 18 January 24.5. All instruction keywords are reserved tokens in PTX.1. where p is a predicate register. so no conflict is possible with user-defined identifiers.file PTX Directives .global.b32 r1.3. Directive Statements Directive keywords begin with a dot. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.PTX ISA Version 2.maxnctapersm . 2. 0. Instruction keywords are listed in Table 2. The destination operand is first.x. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. or label names. address expressions.global .tex . Table 1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.entry . %tid. constant expressions. Statements A PTX statement is either a directive or an instruction.func . 2010 . ld.3.target . The guard predicate follows the optional label and precedes the opcode. Operands may be register variables. Examples: .b32 r1.maxntid . . and is written as @p. r2.extern . written as @!p. mov.const .maxnreg .sreg . r2.param .align .2. Statements begin with an optional label and end with a semicolon.b32 add.visible 4.local .0 4.loc . r2.section .

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 . Syntax Table 2.Chapter 4.

or they start with an underscore.g. dollar. digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. e. or percentage character followed by one or more letters. digits. underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. Table 3. …. The percentage sign can be used to avoid name conflicts. PTX allows the percentage sign as the first character of an identifier. Many high-level languages such as C and C++ follow similar rules for identifier names. except that the percentage sign is not allowed.4. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.0 4. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. 2010 . or dollar characters.PTX ISA Version 2. listed in Table 3. %pm3 WARP_SZ 20 January 24. between user-defined variable names and compiler-generated names.

When used in an instruction or data initialization. in which case the literal is unsigned (.5. i. integer constants are allowed and are interpreted as in C. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. To specify IEEE 754 single-precision floating point values. the constant begins with 0d or 0D followed by 16 hex digits. Integer literals may be written in decimal. literals are always represented in 64-bit double-precision format. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. 2010 21 . The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. the constant begins with 0f or 0F followed by 8 hex digits..u64. every integer constant has type . For predicate-type data and instructions.Chapter 4. there is no suffix letter to specify size. zero values are FALSE and non-zero values are TRUE.s64 or the unsigned suffix is specified. Syntax 4. To specify IEEE 754 doubleprecision floating point values.u64). i. 4. Unlike C and C++. or binary notation.e. where the behavior of the operation depends on the operand types. The syntax follows that of C.5.1. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. Floating-point literals may be written with an optional decimal point and an optional signed exponent. 0[fF]{hexdigit}{8} // single-precision floating point January 24. octal. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. Type checking rules remain the same for integer. hexadecimal. 4. each integer constant is converted to the appropriate size based on the data or instruction type at its use. These constants may be used in data initialization and as operands to instructions. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.2.s64) unless the value cannot be fully represented in . hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.e..s64 or . and bit-size types.5. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. floating-point. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. Constants PTX supports integer and floating-point constants and constant expressions. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

u64 .s64.* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 .s64 .s64 .5.f64 converted type .s64 . Table 5.u64 1st unchanged.u64 .6. Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero . or .u64 .u64 same as 1st operand .s64 .f64 converted type constant literal + ! ~ Cast Binary (. Syntax 4.f64 use usual conversions . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .Chapter 4.s64 .f64 integer .u64 . .f64 : .s64 .u64.u64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 use usual conversions .u64 .u64) (.f64 integer integer integer integer integer int ?. 2nd is .s64 .f64 use usual conversions .f64 same as source .f64 integer .s64) + . 2010 25 .

0 26 January 24.PTX ISA Version 2. 2010 .

Global memory. State Spaces A state space is a storage area with particular characteristics. Table 6. fast. access speed. and Variables While the specific resources available in a given target GPU will vary. platform-specific. private to each thread. 5. Global texture memory (deprecated).tex January 24. and level of sharing between threads. The list of state spaces is shown in Table 4. access rights. All variables reside in some state space. defined per-thread.Chapter 5. Special registers. 2010 27 . defined per-grid. or Function or local parameters.local . Name State Spaces Description Registers. and properties of state spaces are shown in Table 5. Kernel parameters. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Addressable memory shared between threads in 1 CTA. . State Spaces.global . Local memory. read-only memory. shared by all threads.1. Shared.reg .const . Types. addressability. Read-only. The characteristics of a state space include its size. pre-defined.param . and these resources are abstracted in PTX through state spaces and data types. the kinds of resources will be common across platforms.shared .sreg .

. Registers may have alignment boundaries required by multi-word loads and stores. and performance monitoring registers. Register size is restricted. such as grid. 2010 .reg . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). Register State Space Registers (.param instructions.e. predicate) or untyped.local .reg state space) are fast storage locations. and will vary from platform to platform.PTX ISA Version 2. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 32-. the parameter is then located on the stack frame and its address is in the .1.global . The number of registers is limited. Device function input parameters may have their address taken via mov. 2 Accessible via ld. Special Register State Space The special register (.param and st. causing changes in performance. aside from predicate registers which are 1-bit.const . clock counters. and cvt instructions. and vector registers have a width of 16-. 1 Accessible only via the ld. 32-. floating point. 64-.1. i. or as elements of vector tuples. 3 Accessible only via the tex instruction. and thread parameters. platform-specific registers.1. CTA. Registers may be typed (signed integer. scalar registers have a width of 8-.param instruction. unsigned integer. or 128-bits.sreg .param (as input to kernel) . st. 5.0 Table 7. Address may be taken via mov instruction. 16-.shared . register variables will be spilled to memory. 28 January 24.2.param (used in functions) . For each architecture.sreg) state space holds predefined. or 64-bits. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.tex Restricted Yes No3 5. The most common use of 8-bit registers is with ld.local state space. All special registers are predefined. When the limit is exceeded. Registers differ from the other state spaces in that they are not fully addressable. it is not possible to refer to the address of a register.

1.global. bank zero is used for all statically-sized constant variables.local and st. State Spaces.global to access global variables.extern . 5.global.Chapter 5. there are eleven 64KB banks. the bank number must be provided in the state space of the load instruction. [const_buffer+4]. st. Types. 2010 29 . the stack is in local memory. where the size is not known at compile time. It is typically standard memory with cache. an incomplete array in bank 2 is accessed as follows: . the store operation updating a may still be in flight. and atom. as in lock-free and wait-free style programming. All memory writes prior to the bar. b = b – 1. The remaining banks may be used to implement “incomplete” constant arrays (in C. The size is limited.extern . The constant memory is organized into fixed size banks.local) is private memory for each thread to keep its own data.global) state space is memory that is accessible by all threads in a context. Constant State Space The constant (.b32 %r1. For example.sync instruction are guaranteed to be visible to any reads after the barrier instruction.5. Consider the case where one thread executes the following two assignments: a = a + 1. bank zero is used. each pointing to the start address of the specified constant bank. Threads wait at the barrier until all threads in the CTA have arrived. Module-scoped local memory variables are stored at fixed addresses. whereas local memory variables declared January 24. // load second word 5. For the current devices.1. This reiterates the kind of parallelism available in machines that run PTX. For any thread in a context. Global memory is not sequentially consistent. ld.const[2] . To access data in contant banks 1 through 10. Sequential consistency is provided by the bar. If no bank number is given. If another thread sees the variable b change.b32 const_buffer[]. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.const[2] .sync instruction. Local State Space The local state space (.local to access local variables. and Variables 5. all addresses are in global memory are shared. results in const_buffer pointing to the start of constant bank two.const[2]. where bank ranges from 0 to 10.3. For example. It is the mechanism by which different CTAs and different grids can communicate. Multiple incomplete array variables declared in the same bank become aliases. the declaration . Use ld. By convention. Banks are specified using the . In implementations that support a stack. as it must be allocated on a perthread basis.const[bank] modifier.1. This pointer can then be used to access the entire 64KB constant bank. Use ld. Threads must be able to do their work without waiting for other threads to do theirs.b32 const_buffer[]. for example). initialized by the host. Global State Space The global (.4.const) state space is a read-only memory.

entry bar ( .u32 %ptr.param.reg . ld. 5.6. Similarly.b32 N.u32 %ptr.reg .param. mov. The kernel parameter variables are shared across all CTAs within a grid. No access protection is provided between parameter and global space in this case. Note: The location of parameter space is implementation specific. The use of parameter state space for device function parameters is new to PTX ISA version 2. read-only variables declared in the . The address of a kernel parameter may be moved into a register using the mov instruction. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.u32 %n.reg . The resulting address is in the .0 and requires target architecture sm_20. ld.param instructions. len.param state space. in some implementations kernel parameters reside in global memory.param.param) state space is used (1) to pass input arguments from the host to the kernel.align 8 .f64 %d. .param space.PTX ISA Version 2.1.param .6. Example: .param .f64 %d. [buffer]. Values passed from the host to the kernel are accessed through these parameter variables using ld.0 within a function or kernel body are allocated on the stack.1.1. Parameter State Space The parameter (. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. For example. These parameters are addressable. PTX code should make no assumptions about the relative locations or ordering of .param instructions. [%ptr].param state space and is accessed using ld. . [N].x supports only kernel function parameters in .u32 %n. typically for passing large structures by value to a function.param .entry foo ( . … Example: .b32 len ) { .u32 %n. device function parameters were previously restricted to the register state space. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). ld. (2a) to declare formal input and return parameters for device functions called from within kernel execution. … 30 January 24. all local memory variables are stored at fixed addresses and recursive function calls are not supported. 5. Note that PTX ISA versions 1.b8 buffer[64] ) { .param space variables. In implementations that do not support a stack. Therefore. per-kernel versus per-thread). 2010 . %n. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.

param byte array variable that represents a flattened C structure or union.f64 dbl.reg .param. x.6.b32 N. … } // code snippet from the caller // struct { double d. Function input parameters may be read via ld. and Variables 5. In this case. }.Chapter 5. the address of a function input parameter may be moved into a register using the mov instruction. 2010 31 . . . ld. It is not possible to use mov to get the address of a return parameter or a locally-scoped .reg . int y. Device Function Parameters PTX ISA version 2. … See the section on function call syntax for more details.f64 [mystruct+0]. In PTX. Note that the parameter will be copied to the stack if necessary.2.align 8 .reg . a byte array in parameter space is used. [buffer].reg . ld. .param .param . [buffer+8]. Aside from passing structures by value.param. This will be passed by value to a callee.param formal parameter having the same size and alignment as the passed argument. such as C structures larger than 8 bytes.b8 mystruct. .param space is also required whenever a formal parameter has its address taken within the called function.local and st.s32 %y. January 24.param. Typically. the caller will declare a locally-scoped . } mystruct. Types.param. The most common use is for passing objects by value that do not fit within a PTX register. Example: // pass object of type struct { double d.param. (4.f64 %d.s32 x.f64 %d.s32 %y. which declares a .param space variable.reg .b8 buffer[12] ) { . .s32 [mystruct+8].local instructions. int y. dbl. it is illegal to write to an input parameter or read from a return parameter. call foo.func foo ( . and so the address will be in the .local state space and is accessed via ld.0 extends the use of parameter space to device function parameters.1. st.param and function return parameters may be written using st. State Spaces.align 8 . . mystruct). passed to foo … . … st. is flattened.

tex . One example is broadcast. Texture memory is read-only. Example: .u32 tex_a. Shared memory typically has some optimizations to support the sharing. The . A texture’s base address is assumed to be aligned to a 16-byte boundary.tex . 5.texref variables in the .7. Another is sequential access from sequential threads. where texture identifiers are allocated sequentially beginning with zero.global .tex variables are required to be defined in the global scope. Use ld.PTX ISA Version 2.u32 .tex .6 for its use in texture instructions. Texture State Space (deprecated) The texture (. tex_d. is equivalent to .u64.1.u32 tex_a.texref tex_a. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex state space are equivalent to module-scoped .0 5.tex . and programs should instead reference texture memory through variables of type .texref type and Section 8. tex_c.u32 . The texture name must be of type . Shared State Space The shared (.tex directive is retained for backward compatibility. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.texref. For example. tex_d. and variables declared in the .tex directive will bind the named texture memory variable to a hardware texture identifier. Physical texture resources are allocated on a per-module granularity. An error is generated if the maximum number of physical resources is exceeded.tex .u32 . and . tex_f.1. where all threads read from the same address. Multiple names may be bound to the same physical texture identifier.shared to access shared variables. 2010 . An address in shared memory can be read and written by any thread in a CTA. a legacy PTX definitions such as .shared) state space is a per-CTA region of memory for threads in a CTA to share data.8.7.u32 or .global state space.3 for the description of the . It is shared by all threads in a context.tex) state space is global memory accessed via the texture instruction.shared and st. 32 January 24. The . See Section 5.

u8.pred Most instructions have one or more type specifiers. st.2. . Fundamental Types In PTX. Restricted Use of Sub-Word Sizes The . stored. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.b64 .2.s8. January 24. . A fundamental type specifies both a basic type and a size.u8. needed to fully specify instruction behavior.s16. 5. Types 5. but typed variables enhance program readability and allow for better operand type checking. In principle. Types.f64 . so that narrow values may be loaded. and cvt instructions. State Spaces.f64 types. The same typesize specifiers are used for both variable definitions and for typing instructions. stored. all variables (aside from predicates) could be declared using only bit-size types. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .f32 and . . All floating-point instructions operate only on . the fundamental types reflect the native data types supported by the target architectures. and instructions operate on these types. ld.s8. .u32.b16. The following table lists the fundamental type specifiers for each basic type: Table 8. so their names are intentionally short. Two fundamental types are compatible if they have the same basic type and are the same size.f64 types. st.Chapter 5. . .s64 . Signed and unsigned integer types are compatible if they have the same size. .f32.u16. . The bitsize type is compatible with any fundamental type having the same size.b8 instruction types are restricted to ld.f32 and .1. 2010 33 .s32.2. For example.b32.f16. The .b8. For convenience. . or converted to other types and sizes. Register variables are always of a fundamental type.f16 floating-point type is allowed only in conversions to and from .u64 . Operand types and sizes are checked against instruction types for compatibility. and . and converted using regular-width registers. . .2. and Variables 5. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. .

sured). These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. or performing pointer arithmetic will result in undefined results.texref. 2010 . but all information about layout.texref handle. accessing the pointer with ld and st instructions. base address. and . suld. and Surface Types PTX includes built-in “opaque” types for defining texture. 34 January 24. passed as a parameter to functions.PTX ISA Version 2. Referencing textures. In independent mode the fields of the .0 5. sust. and query instructions. In the unified mode. the resulting pointer may be stored to and loaded from memory.. samplers. . suq). since these properties are defined by . and overall size is hidden to a PTX program. For working with textures and samplers. texture and sampler information each have their own handle. These types have named fields similar to structures.u64} reg. sampler. or surfaces via texture and surface load/store instructions (tex. In the independent mode.surfref. Sampler. and de-referenced by texture and surface load.samplerref.{u32. The three built-in types are . but the pointer cannot otherwise be treated as an address. The following tables list the named members of each type for unified and independent texture modes. texture and sampler information is accessed through a single .samplerref variables. field ordering.3. allowing them to be defined separately and combined at the site of usage in the program. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. store. Retrieving the value of a named member via query instructions (txq. Creating pointers to opaque variables using mov. and surface descriptor variables.texref type that describe sampler properties are ignored. Texture.e. hence the term “opaque”. opaque_var. i. PTX has two modes of operation.

clamp_to_border 0. 1 ignored ignored ignored ignored . linear wrap. clamp_to_edge. clamp_to_border N/A N/A N/A N/A N/A . Member width height depth Opaque Type Fields in Independent Texture Mode .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. and Variables Table 9. 1 nearest. clamp_ogl. mirror. mirror. Member width height depth Opaque Type Fields in Unified Texture Mode . clamp_to_edge. Types.texref values . 2010 35 .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.samplerref values N/A N/A N/A N/A nearest. State Spaces. clamp_ogl.Chapter 5. linear wrap.texref values in elements in elements in elements 0.

0 Variables using these types may be declared at module scope or within kernel entry parameter lists.global state space.global .texref my_texture_name.samplerref my_sampler_name.texref tex1.global . Example: .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. 2010 .surfref my_surface_name. .global . the types may be initialized using a list of static expressions assigning values to the named members. When declared at module scope. filter_mode = nearest }. 36 January 24. As kernel parameters.global . . these variables must be in the . At module scope. Example: . .global .PTX ISA Version 2.param state space. these variables are declared in the .

// a length-2 vector of unsigned ints .v4 vector. an optional array size.v4 .v4 .reg . 2010 37 .4.const .b8 v. its type and size. A variable declaration names the space in which the variable resides. . .global .s32 i. for example.f32 V. a variable declaration describes both the variable’s type and its state space. January 24. // typedef . 0. and they may reside in the register space. 5.reg . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . .f32 v0.global . etc. 0}.v3 }. PTX supports types for simple aggregate objects such as vectors and arrays.struct float4 coord.u16 uv.reg .shared .v4. an optional initializer.v2. r. Types. Every variable must reside in one of the state spaces enumerated in the previous section. Examples: . where the fourth element provides padding. In addition to fundamental types.4. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. Predicate variables may only be declared in the register state space. q.struct float4 { . State Spaces. 1.Chapter 5. . Vectors Limited-length vector types are supported.f32 bias[] = {-1. This is a common case for three-dimensional grids.u32 loc.4. // a length-4 vector of bytes By default. Vectors must be based on a fundamental type. . vector variables are aligned to a multiple of their overall size (vector length times base-type size).global .f64 is not allowed. textures. and Variables 5.v2 or .2. . its name.pred p. Variables In PTX. Examples: . Three-element vectors may be handled by using a . .v1.v4.v2 . 5.1.v4 .global . Vectors cannot exceed 128-bits in length.u8 bg[4] = {0. and an optional fixed address for the variable. // a length-4 vector of floats .f32 accel.0.global . 0. Variable Declarations All storage for data is specified with variable declarations.0}.

0}. Variable names appearing in initializers represent the address of the variable.u64.0}.u8 rgba[3] = {{1. . {0.f16 and . 2010 .0 5. Array Declarations Array declarations are provided to allow the programmer to reserve space.0. {0.1.4. this can be used to statically initialize a pointer to a variable. The size of the array specifies how many elements should be reserved. 1} }.global . {1.f32 blur_kernel[][] = {{. For the kernel declaration above. A scalar takes a single value. -1}. or is left empty.0}}.PTX ISA Version 2.05.u32 or .1. being determined by an array initializer.1}.v4 . Examples: .0}. Similarly..s32 n = 10. {0. // address of rgba into ptr Currently.4. 0}. Variables that hold addresses of variables or instructions should be of type ...05}. .0.. this can be used to initialize a jump table to be used with indirect branches or calls.shared .global .u16 kernel[19][19]. variable initialization is supported only for constant and global state spaces.4.u8 mailbox[128]. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.1.global . Initializers are allowed for all types except . where the variable name is followed by an equals sign and the initial value or values for the variable.4. {0.3. To declare an array..1.05.1. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. The size of the dimension is either a constant expression. .pred. label names appearing in initializers represent the address of the next instruction following the label.0.local .global .b32 ptr = rgba. 19*19 (361) halfwords are reserved (722 bytes).0. . 5.global . 38 January 24. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).{. Here are some examples: .{.05}}..s32 offset[][] = { {-1. .

…. Parameterized Variable Names Since PTX supports virtual registers. The default alignment for scalar and array variables is to a multiple of the base-type size. For example. Rather than require explicit declaration of every name. named %r0.0. Elements are bytes. nor are initializers permitted. say one hundred. . PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. 5. and may be preceded by an alignment specifier. 2010 39 . For arrays. Array variables cannot be declared this way.0..Chapter 5. .reg . // declare %r0. State Spaces. Types. Examples: // allocate array at 4-byte aligned address.b32 %r<100>.const . it is quite common for a compiler frontend to generate a large number of register names.2.4.0. These 100 register variables can be declared as follows: . January 24. The variable will be aligned to an address which is an integer multiple of byte-count..b32 variables. and Variables 5. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. alignment specifies the address alignment for the starting address of the entire array. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration.6. The default alignment for vector variables is to a multiple of the overall vector size.b8 bar[8] = {0.align 4 .. %r1.align byte-count specifier immediately following the state-space specifier.4. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. of . not for individual elements. suppose a program uses a large number. %r99.5.0.0. Alignment is specified using an optional . %r1.0}.

0 40 January 24. 2010 .PTX ISA Version 2.

so operands for ALU instructions must all be in variables declared in the . The cvt (convert) instruction takes a variety of operand types and sizes. 6. The ld. Each operand type must be compatible with the type determined by the instruction template and instruction type. The result operand is a scalar or vector variable in the register state space. Integer types of a common size are compatible with each other. The mov instruction copies data between registers. For most operations. January 24. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Instruction Operands 6.1. and a few instructions have additional predicate source operands. PTX describes a load-store machine. q. Predicate operands are denoted by the names p. mov. and c. 6.Chapter 6. as its job is to convert from nearly any data type to any other data type (and size). There is no automatic conversion between types.reg register state space.2. Operand Type Information All operands in instructions have a known type from their declarations. b. Instructions ld and st move data from/to addressable state spaces to/from registers. Most instructions have an optional predicate guard that controls conditional execution. s.3. and cvt instructions copy data from one location to another. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. st. The bit-size type is compatible with every type having the same size. . 2010 41 . the sizes of the operands must be consistent. Source Operands The source operands are denoted in the instruction descriptions by the names a. r.

1.shared.reg . p. The syntax is similar to that used in many assembly languages. [tbl+12]. ld.0 6. W.4.[x].reg . Address expressions include variable names. and immediate address expressions which evaluate at compile-time to a constant address.s32 tbl[256].u16 r0. tbl. The mov instruction can be used to move the address of a variable into a pointer. Load and store operations move data between registers and locations in addressable state spaces. . 2010 .const . .const. and Vectors Using scalar variables as operands is straightforward. Here are a few examples: . . [V].b32 p.PTX ISA Version 2.v4 .f32 V. The interesting capabilities begin with addresses. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. . q.f32 W.v4. address register plus byte offset. 6. address registers.reg .gloal.s32 q.s32 mov.f32 ld.u16 x. and vectors. r0. Examples include pointer arithmetic and pointer comparisons.shared . All addresses and address computations are byte-based.v4 . Using Addresses.u32 42 January 24. arrays. .u16 ld.4.global .reg . there is no support for C-style pointer arithmetic. Arrays. . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets. The address is an offset in the state space in which the variable is declared.

g V. st. mov. or by indexing into the array using square-bracket notation.2.global.f32 V. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.c. a[0].r V. Vector elements can be extracted from the vector with the suffixes .4.4.v2. // move address of a[1] into s 6. Rd}. c. 2010 43 . [addr+offset]. Rb.w.z and . as well as the typical color fields .global.d}.r. The expression within square brackets is either a constant integer.b.reg .f32 ld. a[N-1]. ld. Vectors as Operands Vector operands are supported by a limited subset of instructions. V2. where the offset is a constant expression that is either added or subtracted from a register variable. If more complicated indexing is desired. and in move instructions to get the address of the label or function into a register. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.z V. Vectors may also be passed as arguments to called functions. .a.d}.b. or a braceenclosed list of similarly typed scalars.y V. mov. V.Chapter 6.global. .g. .y.x V.b V.b and . it must be written as an address calculation prior to use. Examples are ld. Instruction Operands 6.3. A brace-enclosed list is used for pattern matching to pull apart vectors. Rc.v4 . and tex. a register variable. [addr+offset2].v4. which may improve memory performance. Elements in a brace-enclosed vector.w = = = = V. b.v4.u32 {a.global.f32 {a. . d.u32 s.4. Arrays as Operands Arrays of all types can be declared. ld.f32 a.reg . a[1]. and the identifier becomes an address constant in the space where the array is declared.a 6. Array elements can be accessed using an explicitly calculated byte address. or a simple “register with constant offset” expression.u32 s. say {Ra.4. Vector loads and stores can be used to implement wide loads and stores.x. which include mov. for use in an indirect branch or call. January 24. The registers in the load/store operations can be a vector.u32 s. . Here are examples: ld. . The size of the array is a constant in the program.c.

1. 44 January 24.PTX ISA Version 2.s32. 2010 . and data movement instruction must be of the same type and size. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. the u16 is zero-extended to s32. Operands of different sizes or types must be converted prior to the operation. 6.u16 instruction is given a u16 source operand and s32 as a destination operand.000 for f16). logic. except for operations where changing the size and/or type is part of the definition of the instruction. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. if a cvt.5. Type Conversion All operands to all arithmetic.5.0 6. For example. and ~131.

The type of extension (sign or zero) is based on the destination format. January 24. Notes 1 If the destination register is wider than the destination format. the result is extended to the destination register width after chopping. f2f = float-to-float. then sign-extend to 32-bits. chop = keep only low bits that fit.u32 targeting a 32-bit register will first chop to 16-bits. 2010 45 . s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. zext = zero-extend. f2u = float-to-unsigned. u2f = unsigned-to-float.s16. f2s = float-to-signed. s2f = signed-to-float. For example. Instruction Operands Table 11.Chapter 6. cvt.

2010 . choosing even integer if source is equidistant between two integers.rn . The following tables summarize the rounding modifiers. Table 12. Rounding Modifiers Conversion instructions may specify a rounding modifier.rz .PTX ISA Version 2.5.0 6.2. In PTX. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. there are four integer rounding modifiers and four floating-point rounding modifiers.rpi Integer Rounding Modifiers Description round to nearest integer.rzi .rm .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rmi . Modifier . Modifier .rni .

as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Another way to hide latency is to issue the load instructions as early as possible. Registers are fastest. first access is high Notes January 24. The register in a store operation is available much more quickly. Table 11 gives estimates of the costs of using different kinds of memory. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. 2010 47 . Table 14. while global memory is slowest. Instruction Operands 6.Chapter 6.6. Operand Costs Operands from different state spaces affect the speed of an operation. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Much of the delay to memory can be hidden in a number of ways.

2010 .PTX ISA Version 2.0 48 January 24.

In this section. These include syntax for function definitions. and Application Binary Interface (ABI).Chapter 7. A function definition specifies both the interface and the body of the function. support for variadic functions (“varargs”). January 24. A function must be declared or defined prior to being called. A function declaration specifies an optional list of return parameters. together these specify the function’s interface.func foo { … ret. parameter passing. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. function calls. execution of the call instruction transfers control to foo.func directive. and memory allocated on the stack (“alloca”). arguments may be register variables or constants. } … call foo. the function name. NOTE: The current version of PTX does not implement the underlying. The simplest function has no parameters or return values. and return values may be placed directly into register variables. so recursion is not yet supported. Function declarations and definitions In PTX. Scalar and vector base-type input and return parameters may be represented simply as register variables. … Here. we describe the features of PTX needed to achieve this hiding of the ABI.1. 2010 49 . Execution of the ret instruction within foo transfers control to the instruction following the call. stack-based ABI. stack layout. implicitly saving the return address. 7. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. and an optional list of input parameters. and is represented in PTX as follows: . or prototype. functions are declared and defined using the . At the call. Abstracting the ABI Rather than expose details of a particular calling convention.

b8 c4. c3. %ptr. First. [y+11]. py). ld. %rd. [y+10]. [y+9].align 8 y[12]) { . For example.b8 [py+11].b8 [py+ 8]. st.u32 %ptr.param. inc_ptr.b8 . this structure will be flattened into a byte array. (%r1. … In this example.0 Example: . passed by value to a function: struct { double dbl. .b64 [py+ 0]. c2. %inc.PTX ISA Version 2. } { .align 8 py[12].c4. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .param space memory. . consider the following C structure.b8 c1.param. Second.b8 [py+ 9].reg .param state space is used to pass the structure by value: . ld.param space variables are used in two ways. st.reg space. // scalar args in .param.reg .c3. In PTX. . } … call (%r1). [y+0].param space call (%out). … ld.s32 out) bar (.b8 c2.b32 c1.param.param .param variable y is used in function definition bar to represent a formal parameter.param. %rc1. %rc2. st. %rc1.func (.param. a . (%x. byte array in . }. ret. %rc2.reg . char c[4]. … … // computation using x. a .param.f1.reg .param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.f64 f1.b8 [py+10].b8 c3.c1.reg . [y+8].reg .f64 f1.f64 field are aligned.b8 .param .u32 %res) inc_ptr ( . 2010 .s32 x.u32 %res. ld. c4.param. 50 January 24.4). note that . The .param. … st.func (. ld. bumpptr. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param. Since memory accesses are required to be aligned to a multiple of the access size.u32 %inc ) { add. st.reg .c2.

param or .reg space variable of matching type and size. For a caller.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. This enables backend optimization and ensures that the . and alignment of parameters. or a constant that can be represented in the type of the formal parameter. 2.reg variables.reg variables.reg space variable with matching type and size.param byte array is used to collect together fields of a structure being passed by value. 2010 51 .param memory must be aligned to a multiple of 1.param space formal parameters that are base-type scalar or vector variables. . For a callee. the corresponding argument may be either a .. 4. all st. Abstracting the ABI The following is a conceptual way to think about the . The . The .param arguments. • The .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param variables or . the argument must also be a .param space byte array with matching type. Parameters in . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. For .param space formal parameters that are byte arrays. or 16 bytes. a .reg state space can be used to receive and return base-type scalar and vector values.param or . and alignment.param instructions used for argument passing must be contained in the basic block with the call instruction. or constants.reg state space in this way provides legacy support. In the case of . • The . • • • Input and return parameters may be .param state space is used to receive parameter values and/or pass return values back to the caller.param state space use in device functions. size. Note that the choice of .reg space formal parameters. January 24.param and ld. The following restrictions apply to parameter passing. A . For a caller. Supporting the .param argument must be declared within the local scope of the caller.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.g. In the case of .Chapter 7.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. • • Arguments may be . size.param variables.reg or . • • • For a callee. In the case of . Typically. or a constant that can be represented in the type of the formal parameter. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. the corresponding argument may be either a . 8.

0. 52 January 24.1.x supports multiple return values for this purpose.reg state space.x. formal parameters may be in either . and a . PTX 2.0 7. PTX 2.param byte array should be used to return objects that do not fit into a register. For sm_2x targets.1.0 continues to support multiple return registers for sm_1x targets.PTX ISA Version 2. and there was no support for array parameters.0 restricts functions to a single return value.param space parameters support arrays. PTX 1.x In PTX ISA version 1. In PTX ISA version 2. Changes from PTX 1. 2010 .param state space. Objects such as C structures were flattened and passed or returned using multiple registers. formal parameters were restricted to . and .reg or .

variadic functions are declared with an ellipsis at the end of the input parameter list.b64 val) %va_arg64 (. … ) .reg . 2.func okay ( … ) Built-in functions are provided to initialize.u32 ptr. 2.u32 ptr.pred p. the size may be 1.s32 result ) maxN ( . mov.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 N. result. %va_start. ret. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .u32 a. For %va_arg.ge p.h headers in C. iteratively access. (ap. or 8 bytes. call %va_end. (2.func (. val. 8. … call (%max). 4). … %va_start returns Loop: @p Done: January 24. In both cases. (ap). call (val). Variadic functions NOTE: The current version of PTX does not support variadic functions.s32 val. %r1. along with the size and alignment of the next data value to be accessed. 4. To support functions with a variable number of arguments.func ( . (3. } … call (%max).u32 ptr) %va_start .reg . %s2). In PTX. and end access to a list of variable arguments.reg . Abstracting the ABI 7. This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg .reg . the size may be 1. %va_end is called to free the variable argument list handle. %s1. for %va_arg64.Chapter 7. . . or 16 bytes. . Once all arguments have been processed. .b32 val) %va_arg (. bra Done. %r2.reg .. 0x8000000.u32 sz. max. the alignment may be 1.reg . bra Loop.u32. or 4 bytes. The function prototypes are defined as follows: .b32 result.2.s32 result.u32 align) .func baz ( .reg . . ) { .func %va_end (.u32 b.b32 ctr. .reg . PTX provides a high-level mechanism similar to the one provided by the stdarg. 4. %r3). %va_arg. 4.. maxN. // default to MININT mov.func (. 2. call (ap).reg . following zero or more fixed parameters: .u32 align) .u32 ap.reg . 0. 2010 53 . N.reg .reg .u32 sz. .reg . ctr.reg . setp.func (. .reg .reg . ctr.h and varargs. maxN.

local and st. 2010 . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( .u32 ptr ) %alloca ( .PTX ISA Version 2. To allocate memory. Alloca NOTE: The current version of PTX does not support alloca. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. a function simply calls the built-in function %alloca.reg .reg .0 7. The array is then accessed with ld. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. If a particular alignment is required. 54 January 24.3.local instructions. defined as follows: .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.

B. 8. C.s32. setp. the semantics are described.2. 2010 55 . For instructions that create a result value. PTX Instructions PTX instructions generally have from zero to four operands. In addition to the name and the format of the instruction. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D.Chapter 8. Instruction Set 8. B. opcode D. and C are the source operands. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. A. opcode D. For some instructions the destination operand is optional. We use a ‘|’ symbol to separate multiple destination registers.1. The setp instruction writes two destination registers. a. opcode A. q = !(a < b).lt p|q. January 24. A. while A. b. B. // p = (a < b). Format and Semantics of Instruction Descriptions This section describes each PTX instruction. the D operand is the destination operand. followed by some examples that attempt to show several possible instantiations of the instruction.

2010 . As an example. n. j.pred p. n. optionally negated. predicate registers are virtual and have . The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. i. Predicates are most commonly set as the result of a comparison performed by the setp instruction. i. q. branch over 56 January 24. To implement the above example as a true conditional branch. This can be written in PTX as @p setp.pred as the type specifier.s32 j.0 8. the following PTX instruction sequence might be used: @!p L1: setp. add.s32 j.3.s32 p. 1. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. Instructions without a guard predicate are executed unconditionally. bra L1. where p is a predicate variable.lt. … // compare i to n // if false. add 1 to j To get a conditional branch or conditional function call. Predicated Execution In PTX.lt.s32 p. predicate registers can be declared as .reg .PTX ISA Version 2. j. add. So. 1. // p = (i < n) // if i < n. consider the high-level code if (i < n) j = j + 1. use a predicate to control the execution of the branch or call instructions.

ge. ls (lower-or-same). The unsigned comparisons are eq.3. gt. hi (higher). lt (less-than). the result is false.1.1. and ge (greater-than-or-equal).Chapter 8. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. le. Instruction Set 8. unsigned integer. and bitsize types. le (less-than-or-equal). 2010 57 . and hs (higher-or-same). Comparisons 8. If either operand is NaN.1. Unsigned Integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. The following table shows the operators for signed integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). ne (not-equal). ne. ordering comparisons are not defined for bit-size types. ne.2. lo (lower). Table 15.3.1. Table 16.3. gt (greater-than). Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. lt. The bit-size comparisons are eq and ne. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.

2010 .2. Table 17.PTX ISA Version 2. ltu. leu. geu. gtu. neu. not. then these comparisons have the same result as their ordered counterparts. and nan returns true if either operand is NaN.3. for example: selp. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. setp can be used to generate a predicate from an integer. and no direct way to load or store predicate register values. or. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. If either operand is NaN.0 To aid comparison operations in the presence of NaN values. However. If both operands are numeric values (not NaN). unordered versions are included: equ. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. There is no direct conversion between predicates and integer values.%p.0. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. Table 18. two operators num (numeric) and nan (isNaN) are provided. and mov.u32 %r1. xor. num returns true if both operands are numeric values (not NaN).1. // convert predicate to 32-bit value 58 January 24. then the result of these comparisons is true.

. the add instruction requires type and size information to properly perform the addition operation (signed.uX .fX ok inv inv ok Instruction Type .bX . add. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. • The following table summarizes these type checking rules.e. Type Checking Rules Operand Type . Instruction Set 8. most notably the data conversion instruction cvt. different sizes).f32 d.sX . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. 2010 59 .fX ok ok ok ok January 24. a. and this information must be specified as a suffix to the opcode. Example: . Signed and unsigned integer types agree provided they have the same size. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 d. .Chapter 8. they must match exactly.sX ok ok ok inv . and these are placed in the same order as the operands. b.f32. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. and integer operands are silently cast to the instruction type if needed.reg .reg . unsigned. For example. b.4.u16 d. For example: .bX .reg . cvt. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. a.u16 a. i. It requires separate type-size modifiers for the result and source. For example.u16 d. float.uX ok ok ok inv . Floating-point types agree only if they have the same size. Table 19. a.

60 January 24. ld. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. When used with a narrower bit-size type. the data will be truncated. 2. Floating-point source registers can only be used with bit-size or floating-point instruction types. the cvt instruction does not support . 4. For example. Notes 3. Source register size must be of equal or greater size than the instruction-type size.1. floating-point instruction types still require that the operand type-size matches exactly. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. When used with a floating-point instruction type. so that narrow values may be loaded.PTX ISA Version 2. for example. stored. 2010 . Operand Size Exceeding Instruction-Type Size For convenience. inv = invalid.4. The data is truncated to the instruction-type size and interpreted according to the instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. The following table summarizes the relaxed type-checking rules for source operands.0 8. so those rows are invalid for cvt. Note that some combinations may still be invalid for a particular instruction. 1. no conversion needed. stored. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. unless the operand is of bit-size type. When a source operand has a size that exceeds the instruction-type size. or converted to other types and sizes. Bit-size source registers may be used with any appropriately-sized instruction type. “-“ = allowed. parse error. the size must match exactly. and converted using regular-width registers. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.bX instruction types. st. Table 20.

b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. The data is signextended to the destination register width for signed integer instruction types. the data is sign-extended. The following table summarizes the relaxed type-checking rules for destination operands.or sign-extended to the size of the destination register. Destination register size must be of equal or greater size than the instruction-type size. Instruction Set When a destination operand has a size that exceeds the instruction-type size. “-“ = Allowed but no conversion needed. inv = Invalid. When used with a narrower bit-size instruction type. Floating-point destination registers can only be used with bit-size or floating-point instruction types. Table 21.Chapter 8. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. the destination data is zero. parse error. 4. 2010 61 . Bit-size destination registers may be used with any appropriately-sized instruction type. and is zero-extended to the destination register width otherwise. 2. If the corresponding instruction type is signed integer. zext = zero-extend. January 24. The data is sign-extended to the destination register width for signed integer instruction types. When used with a floatingpoint instruction type. the size must match exactly. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. the data will be zero-extended. Notes 3. 1. otherwise. the data is zeroextended.

At the PTX language level. Divergence of Threads in Control Constructs Threads in a CTA execute together. 8. If threads execute down different control flow paths. Therefore. or conditional return.1. the threads are called divergent. conditional function call. A compiler or programmer may chose to enforce portable. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. the threads are called uniform. Both situations occur often in programs. at least in appearance. 62 January 24.5. the optimizing code generator automatically determines points of re-convergence.0 8. using the . and 16-bit computations are “promoted” to 32-bit computations. by a right-shift instruction. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. for example. until they come to a conditional control construct such as a conditional branch. The semantics are described using C. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 2010 . If all of the threads act in unison and follow a single control flow path. a compiler or code author targeting PTX can ignore the issue of divergent threads. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. until C is not expressive enough. However. the semantics of 16-bit instructions in PTX is machine-specific. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. For divergent control flow. 8.6. and for many applications the difference in execution is preferable to limiting performance. this is not desirable.uni suffix. These extra precision bits can become visible at the application level. 16-bit registers in PTX are mapped to 32-bit physical registers.PTX ISA Version 2. When executing on a 32-bit data path. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.6. so it is important to have divergent threads re-converge as soon as possible. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. for many performance-critical applications.

cc. Instruction Set 8. the optional guard predicate is omitted from the syntax. addc sub. Instructions All PTX instructions may be predicated.cc. 2010 63 . In the following descriptions.7.7. 8.1.Chapter 8. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. The Integer arithmetic instructions are: add sub add. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.

Saturation modifier: . . Introduced in PTX ISA version 1. add.u64.s16.sat applies only to .sat}. . a.s32 .1. 2010 . d. . sub.sat limits result to MININT.sat applies only to . // . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Applies only to .0.u32..s32 .s64 }. .type = { .type add{. add Syntax Integer Arithmetic Instructions: add Add two values. b. a.b.s32. d = a + b. Applies only to .s32 c. @p add. d = a – b.type sub{. PTX ISA Notes Target ISA Notes Examples Table 23. a.0.u16. a. . sub.s32 type. .MAXINT (no overflow) for the size of the operation. // . PTX ISA Notes Target ISA Notes Examples 64 January 24. .0 Table 22. .type = { .s32 d.s32 d. . Description Semantics Notes Performs addition and writes the resulting value into a destination register.s32 type. add.MAXINT (no overflow) for the size of the operation.y.u16.c.s32 c.sat limits result to MININT. Supported on all target architectures. b. b. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. .u64. Supported on all target architectures. d.PTX ISA Version 2.s64 }. Introduced in PTX ISA version 1. Saturation modifier: .u32.s16. b.sat}.sat..z.s32.u32 x.a.

@p @p @p @p add. Behavior is the same for unsigned and signed integers.2. x2.cc.cc. @p @p @p @p add.z4.u32. addc{.CF No integer rounding modifiers. add. x3.type = {.cc. Supported on all target architectures.y4. a.CF No integer rounding modifiers. . sub. if . No saturation.z2.type d.cc Add two values with carry-out. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.b32 x1.cc. No other instructions access the condition code.type = { . Instruction Set Instructions add.z1. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. Introduced in PTX ISA version 1. x3. clearing.u32.cc.cc.y2.y3.cc.2. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc Syntax Integer Arithmetic Instructions: add.b32 addc. .b32 addc. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y4.b32 addc.s32 }. d = a + b + CC. and there is no support for setting. 2010 65 .b32 addc.cc}.z2.s32 }. b. a.CF. Table 24.cc. .y2. These instructions support extended-precision integer addition and subtraction.type d.b32 addc.b32 x1.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. d = a + b. No saturation. add.y1. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. x4. x4.Chapter 8. addc.z3. b. Supported on all target architectures.z3.cc. or testing the condition code.z1. carry-out written to CC.z4. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.y1. carry-out written to CC.b32 addc.cc. Behavior is the same for unsigned and signed integers.cc specified. x2.CF) holding carry-in/carry-out or borrowin/borrow-out. Introduced in PTX ISA version 1. .y3.

s32 }. .3.cc.z2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.z1.3.y4.0 Table 26. b. if .y1.cc specified.y3.cc. Supported on all target architectures. x2. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.cc.b32 subc.z4.b32 subc.b32 x1.z1.b32 subc.PTX ISA Version 2.b32 subc. No saturation. Introduced in PTX ISA version 1. d = a – b. sub.cc. x4. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers. x2.u32. a.z3.y2. .type d.b32 subc. @p @p @p @p sub.y2. borrow-out written to CC. Introduced in PTX ISA version 1. borrow-out written to CC. Behavior is the same for unsigned and signed integers. x4. .cc}.y1. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. Supported on all target architectures. d = a . a.type = {.(b + CC.cc. sub. withborrow-in and optional borrow-out.cc Syntax Integer Arithmetic Instructions: sub. x3.cc.CF No integer rounding modifiers.z4. .type d.type = { . subc{.u32. @p @p @p @p sub.cc.z2.cc Subract one value from another. x3.CF). No saturation.cc. with borrow-out. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.y3.b32 x1. 2010 .z3.s32 }.cc. b.y4.

mul. Instruction Set Table 28.. // for . 2010 67 .wide // for . Description Semantics Compute the product of two values.type = { . Supported on all target architectures.lo. creates 64 bit result January 24.s16 fa.lo variant Notes The type of the operation represents the types of the a and b operands. save only the low 16 bits // 32*32 bits. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.fys. . then d is the same size as a and b.. . . // 16*16 bits yields 32 bits // 16*16 bits. If . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.hi variant // for .wide}. mul{. n = bitwidth of type.0>. If .wide.s32. mul. d = t<n-1. and either the upper or lower half of the result is written to the destination register.wide suffix is supported only for 16.s16.u64. .wide..type d. then d is twice as wide as a and b to receive the full result of the multiplication. d = t.s32 z.n>.lo is specified..wide is specified. The .s64 }.and 32-bit integer types. t = a * b.y. a.fys.s16 fa. d = t<2n-1.hi. .fxs.u32. mul.u16.x.hi or . .Chapter 8.fxs.lo.0. b.

c.hi mode. then d and c are the same size as a and b.s32 r.r.sat. a.hi variant // for .. mad{.s32 d. . Applies only to .a. . . and either the upper or lower half of the result is written to the destination register. . t n d d d = = = = = a * b. .wide suffix is supported only for 16. t<2n-1.hi or .. Description Semantics Multiplies two values and adds a third. b.s32 d.s32 type in . If .type = { . // for .hi.MAXINT (no overflow) for the size of the operation. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u16. mad.hi. .0. t + c.and 32-bit integer types.lo.s32. c..type mad.PTX ISA Version 2.lo.s16. then d and c are twice as wide as a and b to receive the result of the multiplication.b. 68 January 24. If .u32.q..sat limits result to MININT.lo. t<n-1.p. b.n> + c.wide is specified. 2010 . c. and then writes the resulting value into a destination register. The .u64.s64 }. a.wide}. d. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. bitwidth of type.wide // for . Saturation modifier: .lo variant Notes The type of the operation represents the types of the a and b operands. Supported on all target architectures..0 Table 29. @p mad.0> + c.lo is specified.

.lo. a.type = { . and return either the high or low 32-bits of the 48-bit result.s32 d. mul24. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. // for .. .hi. mul24.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. .b.lo}.Chapter 8.0>.a.type d. 48bits. d = t<31. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. d = t<47. Supported on all target architectures. t = a * b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result..hi may be less efficient on machines without hardware support for 24-bit multiply. Instruction Set Table 30. mul24. mul24{.e.s32 }.hi variant // for . January 24.u32.0. // low 32-bits of 24x24-bit signed multiply.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.16>. All operands are of the same type and size. i. mul24. b. 2010 69 .

Supported on all target architectures.s32 d. b. and add a third. d = t<31.sat. mad24.PTX ISA Version 2.u32. Applies only to .sat limits result of 32-bit signed addition to MININT.0 Table 31. .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value..lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. Description Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d. mad24.MAXINT (no overflow).lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.lo}.lo. c.0> + c.type mad24.hi.0.hi variant // for . 2010 . a.a. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. .s32 }. mad24. // for . c.16> + c. d. a. mad24.hi mode. d = t<47.type = { . 70 January 24. All operands are of the same type and size. 32-bit value to either the high or low 32-bits of the 48-bit result.c. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Return either the high or low 32-bits of the 48-bit result. 48bits. // low 32-bits of 24x24-bit signed multiply.hi may be less efficient on machines without hardware support for 24-bit multiply.b..s32 type in . t = a * b. i.e. Saturation modifier: . b. mad24{...hi.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. } else { max = 64.u32 Semantics 74 January 24. cnt. mask = 0x8000000000000000.type = { . d = 0. mask = 0x80000000.type = { .b32 clz. 2010 . . clz requires sm_20 or later.u32 PTX ISA Notes Target ISA Notes Examples Table 40. popc Syntax Integer Arithmetic Instructions: popc Population count.b32.b64 d. } while (d < max && (a&mask == 0) ) { d++. .0. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. X.b64 }. // cnt is . if (. a. a.b64 type. inclusively. popc requires sm_20 or later. . while (a != 0) { if (a&0x1) d++. . the number of leading zeros is between 0 and 64. a. clz.type == . For . the number of leading zeros is between 0 and 32.b32. cnt. X. d = 0.b64 }. inclusively.0 Table 39.b32) { max = 32. For . popc. a = a << 1. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. popc. clz.b64 d.type d.b32 type. a.PTX ISA Version 2.0. } Introduced in PTX ISA version 2. // cnt is .b32 popc. a = a >> 1. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.type d.

Operand a has the instruction type.type==. bfind returns the bit position of the most significant “1”. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. Instruction Set Table 41. bfind requires sm_20 or later.s32. .type d.u32 || .type = { .type bfind. a.shiftamt && d != -1) { d = msb . bfind. break. i--) { if (a & (1<<i)) { d = i.u32 January 24. For signed integers.shiftamt.s32) ? 31 : 63.type==. bfind returns 0xFFFFFFFF if no non-sign bit is found. } } if (.u64. a. For unsigned integers. and operand d has type . // cnt is .0. for (i=msb. bfind. Semantics msb = (. If . . d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. d = -1. bfind. 2010 75 .shiftamt is specified.Chapter 8. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.u32. X. i>=0.s64 cnt.u32 d. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.d. .s64 }.u32. a. .shiftamt. Description Find the bit position of the most significant non-sign bit in a and place the result in d.

a. a.type==. Description Semantics Perform bitwise reversal of input.0.type = { . brev requires sm_20 or later.b32) ? 31 : 63. msb = (.b64 }. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. . 2010 . i<=msb.b32. brev.b32 d. for (i=0. brev.0 Table 42. i++) { d[i] = a[msb-i]. 76 January 24.PTX ISA Version 2.type d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .

Chapter 8. January 24. bfe. . the result is zero. . 2010 77 .a. and operands b and c are type .u32. the destination d is filled with the replicated sign bit of the extracted field. a. Semantics msb = (. b. Source b gives the bit field starting bit position. The sign bit of the extracted field is defined as: . c.u32 || . .s32) ? 31 : 63.s32.u64. i<=msb.type==.type==. for (i=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.msb)]. The destination d is padded with the sign bit of the extracted field.b32 d.u32 || . d = 0. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. else sbit = a[min(pos+len-1. otherwise If the bit field length is zero.s64 }. if (.start. len = c. and source c gives the bit field length in bits.u32. Operands a and d have the same type as the instruction type.type==. bfe.u32. pos = b. . Description Extract bit field from a and place the zero or sign-extended result in d.len. .u64: . If the start position is beyond the msb of the input.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.s32. Instruction Set Table 43. bfe requires sm_20 or later.type==.type d.0. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.u64 || len==0) sbit = 0.type = { . .

If the start position is beyond the msb of the input. f = b.start.b32 d. and source d gives the bit field length in bits.len. bfi. Semantics msb = (.type==. and f have the same type as the instruction type. and operands c and d are type . 2010 .b32) ? 31 : 63. c. bfi. Operands a. bfi requires sm_20 or later.b64 }.a.type = { . for (i=0. b.0.type f. i<len && pos+i<=msb.PTX ISA Version 2. . the result is b.u32. pos = c. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If the bit field length is zero.b. the result is b. b.b32. 78 January 24. i++) { f[pos+i] = a[i]. and place the result in f. d. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. len = d.0 Table 44. Source c gives the starting bit position for the insertion. . a. Description Align and insert a bit field from a into b.

mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. b1. the permute control consists of four 4-bit selection values.mode} d.rc8.ecr.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. Note that the sign extension is only performed as part of generic form.mode = { . b0}}. b.f4e. Thus. c. {b3.rc16 }.ecl. Description Pick four arbitrary bytes from two 32-bit registers. prmt. a.b2 source select c[11:8] d.b1 source select c[7:4] d. b2. The bytes in the two source registers are numbered from 0 to 7: {b. .b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. . In the generic form (no mode specified). . The msb defines if the byte value should be copied. as a 16b permute code.b4e. . msb=1 means replicate the sign. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.b32{. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). For each byte in the target register. a 4-bit selection value is defined. 2010 79 . . and reassemble them into a 32-bit destination register.b3 source select c[15:12] d. b5. . b4}. Instruction Set Table 45. b6.Chapter 8. the four 4-bit values fully specify an arbitrary byte permute. default mode index d.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. msb=0 means copy the literal value. a} = {{b7.

0 Semantics tmp64 = (b<<32) | a. r2. tmp[15:08] = ReadByte( mode.0. r4. ctl[2]. } tmp[07:00] = ReadByte( mode. tmp64 ). prmt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp[23:16] = ReadByte( mode. prmt requires sm_20 or later. r1.f4e r1. r2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ).b32. ctl[0]. tmp64 ). tmp[31:24] = ReadByte( mode.PTX ISA Version 2. r3.b32 prmt. 2010 . ctl[3] = (c >> 12) & 0xf. r4. ctl[3]. r3. tmp64 ). 80 January 24. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[1]. ctl[1] = (c >> 4) & 0xf. ctl[2] = (c >> 8) & 0xf.

Instruction Set 8. Floating-Point Instructions Floating-point instructions operate on .Chapter 8. 2010 81 .f32 and .2.f64 register operands and constant immediate values. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.7.

sqrt}. Double-precision instructions support subnormal inputs and results. and mad support saturation of results to the range [0. NaN payloads are supported for double-precision instructions. so PTX programs should not rely on the specific single-precision NaNs being generated. {mad.mul}.rcp.f32 are the same.cos.f32 {abs. Table 46.f64 are the same.0. mul.PTX ISA Version 2. No rounding modifier. If no rounding modifier is specified.rz . 82 January 24.rn .lg2.approx.sqrt}. default is . but single-precision instructions return an unspecified NaN.neg.rnd.f64 and fma.32 and fma.rcp.0 The following table summarizes floating-point instructions in PTX.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.ex2}.neg.rnd.f32 {div.rnd.sat Notes If no rounding modifier is specified.f64 {abs. Note that future implementations may support NaN payloads for single-precision instructions.rcp. sub.rp .approx.mul}. 2010 .rnd.rnd. 1. Single-precision add. . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.target sm_1x No rounding modifier.approx.target sm_20 . {add.max}.f64 {sin.f64 rsqrt.min.rnd.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 {add.f32 . with NaNs being flushed to positive zero.sub.f32 {div.rn and instructions may be folded into a multiply-add.full.f32 {div.f64 mad.fma}.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f64 div.rm .f32 rsqrt. .ftz .0].rn and instructions may be folded into a multiply-add.approx.max}.target sm_20 mad.fma}.min. Instruction Summary of Floating-Point Instructions .f32 {mad. default is . The optional .sqrt}.sub.

f32.notanumber. X.notanumber. not infinity) As a special case.infinite. 2010 83 .notanumber testp.f64 }. testp.number testp. true if the input is a subnormal number (not NaN. z.finite testp. f0. a. positive and negative zero are considered normal numbers.op. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. .normal testp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.f64 isnan. and return the result as d. .number.finite. .type = { .pred = { . a. copysign. copysign requires sm_20 or later. Introduced in PTX ISA version 2. copysign.normal. .subnormal }.f64 }.0. Table 48.0.f32 testp. not infinity).subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.infinite testp. January 24.type = { .f64 x. testp requires sm_20 or later. . B.op p. . p. // result is . . b. y. testp.f32 copysign. testp.infinite. testp Syntax Floating-Point Instructions: testp Test floating-point property. Instruction Set Table 47. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.f32. C. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.type .Chapter 8.type d. . A. .

0f.f64 d.f32 add{.ftz}{. add.rn): .f32 f1. add. . add.f3. d.ftz.sat}. b.rm.f64.f64 supports subnormal numbers. Saturation modifier: .sat.rz mantissa LSB rounds towards zero .rz.f32 clamps the result to [0. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.rnd}.PTX ISA Version 2.f64 requires sm_13 or later. Rounding modifiers have the following target requirements: . .f2. 2010 . Description Semantics Notes Performs addition and writes the resulting value into a destination register. requires sm_20 Examples @p add. 1.f32 flushes subnormal inputs and results to sign-preserving zero.rp }.rz.0]. .rm mantissa LSB rounds towards negative infinity .f32 flushes subnormal inputs and results to sign-preserving zero. .rnd}{.0.0 Table 49. add Syntax Floating-Point Instructions: add Add two values. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. In particular. NaN results are flushed to +0. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. subnormal numbers are supported. 84 January 24.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd = { . add.f32 supported on all target architectures. a. .f32.rn. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rn. .rp for add. Rounding modifiers (default is .rz available for all targets .rn mantissa LSB rounds to nearest even . requires sm_13 for add. b. sm_1x: add.rm.0. add{. add.ftz. a. d = a + b.

A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn. sub. sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f3. NaN results are flushed to +0. 2010 85 . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. requires sm_20 Examples sub.Chapter 8. Instruction Set Table 50.rz available for all targets .f64 d.f64.rnd}{. subnormal numbers are supported. a.0.rn): .f2.rn mantissa LSB rounds to nearest even .f32 supported on all target architectures. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz.ftz}{. b.0].rn. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. .f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { .rm. In particular. 1. . Rounding modifiers (default is . sub{.b. a. .rn. Rounding modifiers have the following target requirements: .a. sub. .0.rz. Saturation modifier: sub.f64 supports subnormal numbers. sub.sat.b. January 24. b.f32 c. requires sm_13 for sub.f32 sub{.rnd}.0f. .rp for sub. d. sub Syntax Floating-Point Instructions: sub Subtract one value from another.f32 flushes subnormal inputs and results to sign-preserving zero. d = a . .rz mantissa LSB rounds towards zero .ftz.rm mantissa LSB rounds towards negative infinity .rm.sat}.f64 requires sm_13 or later.f32 f1. sub.f32 clamps the result to [0.rp }.f32. sm_1x: sub.

. Rounding modifiers have the following target requirements: .f64 requires sm_13 or later.0f.f32 mul{. . mul.rnd}. all operands must be the same size.0. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_13 for mul. d. sm_1x: mul. d = a * b.rnd = { .rn mantissa LSB rounds to nearest even .PTX ISA Version 2. mul.rp for mul.rz available for all targets .rz mantissa LSB rounds towards zero .f32 flushes subnormal inputs and results to sign-preserving zero. . For floating-point multiplication. 2010 . A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. mul Syntax Floating-Point Instructions: mul Multiply two values.rn): .f32 clamps the result to [0.0 Table 51. a. requires sm_20 Examples mul.rn.sat. .rm. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. mul{.f64 d. mul. b.0.pi // a single-precision multiply 86 January 24. NaN results are flushed to +0.f32.f64 supports subnormal numbers. .rm.rz. Description Semantics Notes Compute the product of two values.rm mantissa LSB rounds towards negative infinity . subnormal numbers are supported.rnd}{. Rounding modifiers (default is .rn.f32 supported on all target architectures.radius.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}{.0]. b. In particular.f64.f32 circumf. 1.sat}. mul. Saturation modifier: mul.ftz. .ftz.rp }. a.

fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.4.x.f64 w.sat. Instruction Set Table 52. c.f64 computes the product of a and b to infinite precision and then adds c to this product.f64.rz mantissa LSB rounds towards zero . d.rnd. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. 1.f64 is the same as mad.f32 requires sm_20 or later.ftz.rn mantissa LSB rounds to nearest even . again in infinite precision.f32 flushes subnormal inputs and results to sign-preserving zero. again in infinite precision. .rnd.rn. fma.f32 fma. @p fma. fma.f64 requires sm_13 or later. 2010 87 . fma. fma.f32 clamps the result to [0. .a.0f. PTX ISA Notes Target ISA Notes Examples January 24. a.z. a. fma Syntax Floating-Point Instructions: fma Fused multiply-add. subnormal numbers are supported.f32 introduced in PTX ISA version 2. .f64 supports subnormal numbers.sat}.ftz. . fma. Saturation: fma. The resulting value is then rounded to double precision using the rounding mode specified by .0]. d = a*b + c.f32 fma. The resulting value is then rounded to single precision using the rounding mode specified by .c.rn.f32 computes the product of a and b to infinite precision and then adds c to this product.rp }.f64 introduced in PTX ISA version 1.ftz}{.Chapter 8. sm_1x: fma. d. Rounding modifiers (no default): . NaN results are flushed to +0.f32 is unimplemented in sm_1x.rm mantissa LSB rounds towards negative infinity . fma.rn.b.rnd{.f64 d. fma. c. fma. b.rnd. fma.rnd = { .y.0.rz.rm. b.0.

mad.f32).target sm_20 d. Saturation modifier: mad. mad.rz mantissa LSB rounds towards zero .f32 mad.rm mantissa LSB rounds towards negative infinity . and then the mantissa is truncated to 23 bits.rn. The resulting value is then rounded to double precision using the rounding mode specified by . mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero. // . // .f64} is the same as fma.e.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.f32. again in infinite precision. a. Unlike mad.0. .target sm_1x d.f32 is implemented as a fused multiply-add (i. a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b. but the exponent is preserved. Rounding modifiers (no default): .target sm_13 and later .0 devices.0].0 Table 53. mad.ftz}{.0. mad.rnd. c.{f32.sat. and then writes the resulting value into a destination register. b.f32 mad.f32 computes the product of a and b to infinite precision and then adds c to this product.rnd. 88 January 24.rnd{.f64 is the same as fma. NaN results are flushed to +0. again in infinite precision. fma. sm_1x: mad. mad. . where the mantissa can be rounded and the exponent will be clamped.rn mantissa LSB rounds to nearest even .ftz.f64 d.f64.sat}.f64}.{f32. again in infinite precision.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 clamps the result to [0. Note that this is different from computing the product with mul.f32 is when c = +/-0. d = a*b + c.target sm_20: mad. mad.rnd.ftz.target sm_1x: mad.rp }. mad. For .f64 supports subnormal numbers. mad.ftz}{.rnd. 1. The resulting value is then rounded to double precision using the rounding mode specified by .0f. The exception for mad. the treatment of subnormal inputs and output follows IEEE 754 standard.f32 computes the product of a and b at double precision.rnd = { .PTX ISA Version 2.rz. mad. c. .f64 computes the product of a and b to infinite precision and then adds c to this product. For .f32 is identical to the result computed using separate mul and add instructions. When JIT-compiled for SM 2. c. Description Semantics Notes Multiplies two values and adds a third. The resulting value is then rounded to single precision using the rounding mode specified by .sat}. b.rn.f32 flushes subnormal inputs and results to sign-preserving zero.rm. a. In this case. // . mad{. subnormal numbers are supported..

In PTX ISA versions 1. requires sm_13 . In PTX ISA versions 2.rn.. 2010 89 .b.rm. Legacy mad.0.f64 instructions having no rounding modifier will map to mad.f64.Chapter 8.rp for mad.f32 d. a rounding modifier is required for mad.rz.f32 for sm_20 targets. a rounding modifier is required for mad. Rounding modifiers have the following target requirements: .4 and later. requires sm_20 Examples @p mad.rp for mad.a... Target ISA Notes mad.f64. January 24.c.f32.rn.f32 supported on all target architectures..0 and later.f64 requires sm_13 or later.f64.. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rm.rn.rz.. mad.

b.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. subnormal numbers are supported.f32 implements a relatively fast.approx. xd.f32 flushes subnormal inputs and results to sign-preserving zero. The maximum ulp error is 2 across the full range of inputs. .f32 requires sm_20 or later.rp}.rnd.full. div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . . div.full.full. Target ISA Notes div. stores result in d. approximate single-precision divides: div.f32 implements a fast approximation to divide.rn mantissa LSB rounds to nearest even . PTX ISA Notes div. div. Explicit modifiers .rp }. d = a / b.0 through 1.approx. the maximum ulp error is 2. For PTX ISA version 1. sm_1x: div.rm mantissa LSB rounds towards negative infinity .ftz.ftz}.f64 requires sm_20 or later. yd.ftz.rn.rz. d. Examples 90 January 24. a.approx. a.rn. d. div.ftz.ftz}. div.ftz}.3.approx{. a. approximate division by zero creates a value of infinity (with same sign as a).0 Table 54.3.approx.f32 defaults to div. computed as d = a * (1/b).f64 diam. and div.f32 and div. but is not fully IEEE 754 compliant and does not support rounding modifiers.full{. div Syntax Floating-Point Instructions: div Divide one value by another.PTX ISA Version 2. div.4. b. 2126]. div. .f32 div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . For PTX ISA versions 1.rnd = { .f32 div.0.f64 supports subnormal numbers. a. // // // // fast.rn. zd.f64 defaults to div. or .f32 supported on all target architectures. one of .rnd{. b.rnd. x. Description Semantics Notes Divides a by b. Fast. Subnormal inputs and results are flushed to sign-preserving zero.f32. For b in [2-126.f64.f32 div.f32 div. div.f64 d. z.f32 flushes subnormal inputs and results to sign-preserving zero.rn.f64 introduced in PTX ISA version 1. b. d.approx. .rm.14159.ftz.f32 div.{rz.f64 requires sm_13 or later. and rounding introduced in PTX ISA version 1. y.approx.rz mantissa LSB rounds towards zero .rm.circum. Fast.4 and later.ftz. . full-range approximation that scales operands to achieve better accuracy. 2010 .full. div.f32 and div.rnd is required.full. .

Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.0.ftz}. abs. Table 56. d. Subnormal numbers: sm_20: By default. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f0. Subnormal numbers: sm_20: By default. NaN inputs yield an unspecified NaN.f32 x. neg.f32 flushes subnormal inputs and results to sign-preserving zero. Negate the sign of a and store the result in d. sm_1x: neg. abs{. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 supported on all target architectures. abs. abs. January 24. Instruction Set Table 55.ftz.ftz.f64 supports subnormal numbers.f64 d.f32 neg.f32 x. d = -a. subnormal numbers are supported. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. NaN inputs yield an unspecified NaN. d. neg. abs. neg{. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.0.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.f32 supported on all target architectures. a.f32 abs. a.f64 d.ftz.Chapter 8. d = |a|. a. 2010 91 .ftz.ftz}. a.f0. abs.f64 supports subnormal numbers. Take the absolute value of a and store the result in d.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: abs.

min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.ftz}. a.b.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. min{. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. min. d. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. Table 58. subnormal numbers are supported. subnormal numbers are supported. d d d d = = = = NaN.f32 min. min.f64 d.x. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.0. 92 January 24.0.f32 flushes subnormal inputs and results to sign-preserving zero.f32 max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. sm_1x: max.f64 requires sm_13 or later.0 Table 57. Store the minimum of a and b in d.b.f2. Store the maximum of a and b in d. b.ftz. @p min. (a > b) ? a : b.f64 requires sm_13 or later. (a < b) ? a : b. b. d d d d = = = = NaN. sm_1x: min.PTX ISA Version 2.f32 min. max.f32 max.f64 z.f64 f0. b. a.c.f64 supports subnormal numbers.f64 d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. max. b.f32 supported on all target architectures. a. b. max{.c. a. min. a.z. a. min.ftz. max. b.ftz}. 2010 .ftz. max. max. d. a.f1.

rcp.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.rz mantissa LSB rounds towards zero .rn.rn.f32 requires sm_20 or later.rm.rp}. rcp.ftz were introduced in PTX ISA version 1.rm mantissa LSB rounds towards negative infinity .rn.f32 defaults to rcp.f64 and explicit modifiers . . For PTX ISA version 1.approx.f32.ftz}. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .approx{.f64 requires sm_13 or later. .4 and later. .f64 introduced in PTX ISA version 1.approx and . and rcp.f64 requires sm_20 or later. // fast.f64 ri.f32 rcp.x.f32 and rcp.f32 rcp.f64 d. d.{rz. a.ftz.f32 supported on all target architectures.0 over the range 1. a. d = 1 / a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. a.rn.approx. sm_1x: rcp.f32 rcp.f64.ftz}.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . Description Semantics Notes Compute 1/a.approx. subnormal numbers are supported. Instruction Set Table 59. rcp. xi.approx or .f64 supports subnormal numbers.rnd{. PTX ISA Notes rcp.0. rcp. Examples January 24. xi.3.rnd = { . For PTX ISA versions 1.0-2.f64 defaults to rcp.rn mantissa LSB rounds to nearest even .rnd. The maximum absolute error is 2-23. 2010 93 . store result in d. Target ISA Notes rcp.rp }.x.rn. one of . d. rcp.rn.rnd.approx. General rounding modifiers were added in PTX ISA version 2.ftz.rz.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.0.Chapter 8. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. Input -Inf -subnormal -0. rcp.0 +subnormal +Inf NaN Result -0.rnd is required.0.0 +0.f32 implements a fast approximation to reciprocal.4.ftz.rm. rcp.0 through 1. rcp.ftz.f32 rcp.r.0 -Inf -Inf +Inf +Inf +0.

f32 requires sm_20 or later.rz.0.f64 d.approx or . sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .ftz. approximate square root d. sqrt. sqrt.0 -0. r.rnd{. // IEEE 754 compliant rounding . sqrt.rnd is required. sm_1x: sqrt.f32 is TBD.rn.rp}.0 Table 60. sqrt.approx{.approx.rn.f32 sqrt. 2010 .f32 defaults to sqrt.ftz}.f64 supports subnormal numbers.0 +subnormal +Inf NaN Result NaN NaN -0.f32 implements a fast approximation to square root. sqrt.x.ftz. For PTX ISA version 1. Examples 94 January 24.f32 and sqrt.approx.ftz. one of .f32.f64 and explicit modifiers .f32 sqrt.f64 requires sm_13 or later. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. .f64 r.rnd. Description Semantics Notes Compute sqrt(a).f64 defaults to sqrt.0 through 1. // IEEE 754 compliant rounding d.rn.f64 requires sm_20 or later.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn.ftz were introduced in PTX ISA version 1.0 +0.PTX ISA Version 2. a.0 +0. a.f32 sqrt.approx and .0.rm.f64 introduced in PTX ISA version 1.rn.rnd.rn. PTX ISA Notes sqrt. d = sqrt(a).rp }.rnd = { . sqrt. sqrt. a. sqrt.approx. . and sqrt.0 +0. General rounding modifiers were added in PTX ISA version 2. store in d.f32 flushes subnormal inputs and results to sign-preserving zero.rz mantissa LSB rounds towards zero . // fast. r.f32 sqrt.4.ftz}.rm mantissa LSB rounds towards negative infinity .f64.approx. Target ISA Notes sqrt.approx. For PTX ISA versions 1.rn mantissa LSB rounds to nearest even . Input -Inf -normal -subnormal -0. The maximum absolute error for sqrt.{rz.f32 supported on all target architectures.ftz. sqrt.x.x. subnormal numbers are supported.3.4 and later.rm.

0-4.0 +0. Explicit modifiers .ftz}.f32 is 2-22.approx. For PTX ISA versions 1.f32 rsqrt. store the result in d.approx. Input -Inf -normal -subnormal -0. and rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. January 24.ftz were introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. For PTX ISA version 1. X.4.3. rsqrt. Target ISA Notes Examples rsqrt. a.ftz. sm_1x: rsqrt. 2010 95 .f64 is emulated in software and are relatively slow.ftz. Compute 1/sqrt(a).0. rsqrt. rsqrt.approx implements an approximation to the reciprocal square root.f64 were introduced in PTX ISA version 1.f64.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f64 d.0 through 1.approx{.approx. d.f32 defaults to rsqrt. PTX ISA Notes rsqrt. The maximum absolute error for rsqrt.approx. rsqrt.approx. a. rsqrt.f64 is TBD.approx.f32. Subnormal numbers: sm_20: By default. rsqrt.f32 rsqrt. ISR.0. x. rsqrt. d = 1/sqrt(a).f64 requires sm_13 or later.f64 defaults to rsqrt. the .f64 isr.4 and later.f32 and rsqrt.f32 supported on all target architectures.0 NaN The maximum absolute error for rsqrt.approx modifier is required. Instruction Set Table 61.Chapter 8.f64 supports subnormal numbers. subnormal numbers are supported.approx and . rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.4 over the range 1.ftz. Note that rsqrt.

PTX ISA Notes sin.ftz introduced in PTX ISA version 1.9 in quadrant 00.approx{.ftz. sin. Target ISA Notes Examples Supported on all target architectures.0 -0. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.f32 sa.f32. Find the sine of the angle a (in radians).f32 implements a fast approximation to sine. sin. d = sin(a).0. a. sin.ftz}. sin.0 NaN NaN The maximum absolute error is 2-20.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1.ftz.f32 d.0 +0.4.ftz.PTX ISA Version 2. Input -Inf -subnormal -0.3. For PTX ISA version 1.4 and later.0 +0.0 +subnormal +Inf NaN Result NaN -0.0 Table 62.approx modifier is required.approx.approx and .f32 introduced in PTX ISA version 1. the . sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA versions 1.0 +0. 2010 . subnormal numbers are supported.approx.approx. a. Explicit modifiers .f32 defaults to sin. Subnormal numbers: sm_20: By default. 96 January 24. sin.

sm_1x: Subnormal inputs and results to sign-preserving zero. For PTX ISA version 1.approx. For PTX ISA versions 1.f32 flushes subnormal inputs and results to sign-preserving zero.0 NaN NaN The maximum absolute error is 2-20. cos. cos.0 +1. Find the cosine of the angle a (in radians).3. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.4 and later.0 +0. January 24. PTX ISA Notes cos.9 in quadrant 00. d = cos(a). Target ISA Notes Examples Supported on all target architectures. Explicit modifiers . cos.f32 implements a fast approximation to cosine.Chapter 8.approx. Input -Inf -subnormal -0.ftz. Instruction Set Table 63.0.0 through 1.f32. Subnormal numbers: sm_20: By default.ftz introduced in PTX ISA version 1.f32 introduced in PTX ISA version 1.approx modifier is required. the .4.0 +1. subnormal numbers are supported. cos.f32 d.ftz.ftz.f32 ca. cos.f32 defaults to cos. a.approx.0 +subnormal +Inf NaN Result NaN +1.approx{. 2010 97 .0 +1. a.ftz}.approx and .

approx modifier is required.f32 implements a fast approximation to log2(a).0.f32. The maximum absolute error is 2-22.0 +0.approx and .4.ftz introduced in PTX ISA version 1. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz}.approx.6 for mantissa. lg2.approx{. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz. For PTX ISA versions 1. d = log(a) / log(2).PTX ISA Version 2.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.f32 la. subnormal numbers are supported.0 Table 64. a.f32 flushes subnormal inputs and results to sign-preserving zero. the .f32 defaults to lg2.3. 2010 .approx.f32 introduced in PTX ISA version 1. lg2. PTX ISA Notes lg2. lg2. Target ISA Notes Examples Supported on all target architectures. Explicit modifiers . For PTX ISA version 1.4 and later.ftz. 98 January 24.approx.f32 Determine the log2 of a. Input -Inf -subnormal -0. Subnormal numbers: sm_20: By default.ftz. lg2. a. lg2.0 through 1.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

. c).a. neu. 102 January 24.dtype. num returns true if both operands are numeric values (not NaN).ftz. q = BoolOp(!t. .CmpOp{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.and. respectively.f32 flushes subnormal inputs to sign-preserving zero. loweror-same. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. and higher-or-same may be used instead of lt. leu. and (optionally) combine this result with a predicate value by applying a Boolean operator. . gt.b.pred variables. hi. then the result of these comparisons is true. higher.u32. ge. setp. Integer Notes Floating Point Notes The ordered comparisons are eq. and nan returns true if either operand is NaN. {!}c. gtu.u32 p|q.f32 comparisons.type setp. nan The Boolean operator BoolOp(A. ne. Applies to all numeric types.B) is one of: and. setp. p.type . gtu. ge. subnormal numbers are supported. bit-size comparisons are eq and ne. geu. . a. gt. lo.u64. A related value computed using the complement of the compare result is written to the second destination operand. ge. le. ge. neu.s64. leu.type = { . le.PTX ISA Version 2. .i.dtype.CmpOp. p = BoolOp(t. p[|q].ftz}. Semantics t = (a CmpOp b) ? 1 : 0. b. ne. and hs for lower. b. ltu. ne. If either operand is NaN. . The untyped. ls. hs equ. and can be one of: eq.b64.f64 supports subnormal numbers.f32 flushes subnormal inputs to sign-preserving zero. This result is written to the first destination operand.n. c).u16. For unsigned values. ltu. le.ftz}. a. xor. gt.b16. The destinations p and q must be .dtype. gt. geu. @q setp.BoolOp{. 2010 .lt. or. setp. . the result is false.s32. hi. Subnormal numbers: sm_20: By default. the comparison operators lo. unordered versions are included: equ.f32. lt. To aid comparison operations in the presence of NaN values. . sm_1x: setp.s16. le. then these comparisons have the same result as their ordered counterparts. setp with .0 Table 67. If both operands are numeric values (not NaN).ftz applies only to . ls. Modifier .eq.r. lt. .s32 setp. The comparison operator is a suffix on the instruction. lt. p[|q].f64 }.0. . If either operand is NaN. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. num.b32.f64 source type requires sm_13 or later. The signed and unsigned comparison operators are eq.

b32. c.f32 A.0. b.f32 d. operand c must match the second instruction type. and operand a is selected. . and operand a is selected. b.p. For . .s32.t. slct. f0. slct.u64.xp. If operand c is NaN. slct.s64.u32. d. Introduced in PTX ISA version 1. 2010 103 .s16. . d = (c >= 0) ? a : b. .x. Subnormal numbers: sm_20: By default. Operands d. .f64 }. . .dtype. If c is True.s32 selp.s32. Table 69. Operand c is a predicate. subnormal numbers are supported.Chapter 8. .f32 flushes subnormal values of operand c to sign-preserving zero. slct. and b must be of the same type. .s32 slct{. . If c ≥ 0. b otherwise.dtype. c. . a. .f64 }.f32. fval. @q selp.ftz applies only to . based on the sign of the third operand. selp.ftz.g. slct Syntax Comparison and Selection Instructions: slct Select one source operand.ftz.b32.u16. The selected input is copied to the output without modification. negative zero equals zero.0. a is stored in d. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. a. . a. a.b64. Semantics Floating Point Notes January 24. Modifier .u32.dtype. the comparison is unordered and operand b is selected.s64. . otherwise b is stored in d.f32.type = { . val. selp.f32 comparisons. and b are treated as a bitsize type of the same width as the first instruction type. . slct.r. . .u64. a is stored in d.f64 requires sm_13 or later.f32 comparisons. z. b.dtype. .dtype = { . .b16. Description Conditional selection. Operands d.u64.u32. . based on the value of the predicate source operand. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s16. c. y. d = (c == 1) ? a : b. Instruction Set Table 68.f32 flushes subnormal values of operand c to sign-preserving zero.f32 r0.u16.type d.s32 x.f64 requires sm_13 or later.b64. a.ftz}. B. selp Syntax Comparison and Selection Instructions: selp Select between source operands. sm_1x: slct. C. .b16. .

and not also operate on predicates. Instructions and.7.0 8. xor. This permits bit-wise operations on floating point values without having to define a union to access the bits. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. performing bit-wise operations on operands of any type.PTX ISA Version 2. or. 2010 .4. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. provided the operands are of the same size.

.q.b64 }. but not necessarily the type. a. Introduced in PTX ISA version 1. Table 71.type d. or. The size of the operands must match. b. 2010 105 .q.b64 }.b32 mask mask.b32 x. a.b32 and.type d.b16. Introduced in PTX ISA version 1.r. .b16. .pred.type = { .0x80000000. and Syntax Logic and Shift Instructions: and Bitwise AND. sign. Allowed types include predicate registers. Supported on all target architectures. d = a | b.pred. or.fpvalue.type = { . . January 24. Allowed types include predicate registers. .Chapter 8. and.pred p. Supported on all target architectures.0.b32. or Syntax Logic and Shift Instructions: or Bitwise OR.0. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.r. and. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b32. The size of the operands must match. . Instruction Set Table 70. but not necessarily the type. b. .0x00010001 or. d = a & b.

b32. xor.0. cnot. d. . b. Allowed types include predicates. Supported on all target architectures. Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. a.b32 mask. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. . .a.type = { . d = ~a. 2010 .0 Table 72. d = (a==0) ? 1 : 0. Introduced in PTX ISA version 1. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).b32 xor. Table 73. . not.b64 }.type = { . Allowed types include predicate registers. not.q. .0. but not necessarily the type. d = a ^ b. Supported on all target architectures.pred p.type = { .type d.b64 }. but not necessarily the type.type d. . The size of the operands must match.b32.type d.b16. Table 74. not Syntax Logic and Shift Instructions: not Bitwise negation. xor. a.b64 }. .b16.b32 d. one’s complement. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b16 d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b16. cnot.mask. 106 January 24.b32.0x0001. . .PTX ISA Version 2.x. Introduced in PTX ISA version 1.pred.q. but not necessarily the type. The size of the operands must match. not. a. Introduced in PTX ISA version 1. .0.r.pred. The size of the operands must match.

a.type d. Bit-size types are included for symmetry with SHL. i. The b operand must be a 32-bit value.b32.u16 shr. but not necessarily the type.1. . b.j.b16. shl. .s16. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. PTX ISA Notes Target ISA Notes Examples Table 76.type = { .0.type d. d = a >> b. The sizes of the destination and first source operand must match. sign or zero fill on left.type = { . b.s32.b64 }.b16. Signed shifts fill with the sign bit. . shr. . The sizes of the destination and first source operand must match. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Shift amounts greater than the register width N are clamped to N. shr.2. Shift amounts greater than the register width N are clamped to N.b32.2.b64.a. Introduced in PTX ISA version 1. a.i. 2010 107 .0. . Instruction Set Table 75. . but not necessarily the type. Introduced in PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples January 24. The b operand must be a 32-bit value.u16. . shl.b32 q. unsigned and untyped shifts fill with 0. . zero-fill on right. shl Syntax Logic and Shift Instructions: shl Shift bits left.Chapter 8.s64 }. k. d = a << b. regardless of the instruction type.i. Supported on all target architectures. .u32. . . Supported on all target architectures.a.u64. .b16 c.s32 shr. regardless of the instruction type. shr Syntax Logic and Shift Instructions: shr Shift bits right.

mov.PTX ISA Version 2. The cvta instruction converts addresses between generic and global. 2010 .7. Instructions ld. ldu. Data Movement and Conversion Instructions These instructions copy data from place to place.5. suld. and from state space to state space. local.0 8. and sust support optional cache operations. and st operate on both scalar and vector types. ld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. prefetchu isspacep cvta cvt 108 January 24. st. possibly converting it from one format to another. or shared state spaces.

cs is applied to a Local window address. January 24. Use ld. it performs the ld. Global data is coherent at the L2 level. likely to be accessed once. any existing cache lines that match the requested address in L1 will be evicted. if the line is fully covered. not L1). the cache operators have the following definitions and behavior. when applied to a local address. but multiple L1 caches are not coherent for global data.cs. rather than the data stored by the first thread. The default load instruction cache operation is ld. . Cache Operators PTX 2. the second thread may get stale L1 cache data.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The compiler / programmer may use ld.5. and cache only in the L2 cache. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. The cache operators require a target architecture of sm_20 or later. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. When ld.0 introduces optional cache operators on load and store instructions. A ld.lu Last use. 2010 109 .cv Cache as volatile (consider cached system memory lines stale. The ld.cs Cache streaming. For sm_20 and later. bypassing the L1 cache.cv to a frame buffer DRAM address is the same as ld. As a result of this request.7. fetch again). .cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. evict-first.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The ld. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. Instruction Set 8. to allow the thread program to poll a SysMem location written by the CPU.1.lu load last use operation. The ld. invalidates (discards) the local L1 line following the load.ca.Chapter 8. If one thread stores to global memory via one L1 cache. .cg Cache at global level (cache in L2 and below. Operator . and a second thread loads that address via a second L1 cache with ld.lu operation.lu instruction performs a load cached streaming operation (ld.ca loads cached in L1.ca. likely to be accessed again. The ld. Table 77.cg to cache loads only globally. .cs) on global addresses.

not L1). and marks local L1 lines evict-first. regardless of the cache operation. and cache only in the L2 cache. Operator .ca loads. Use st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. and discard any L1 lines that match. st.wb for global data.ca. bypassing the L1 cache. the second thread may get a hit on stale L1 cache data. The st.cg Cache at global level (cache in L2 and below.wt.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.wb. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. 110 January 24. Addresses not in System Memory use normal write-back.wt store write-through operation applied to a global System Memory address writes through the L2 cache.cg to cache global store data only globally. and a second thread in a different SM later loads from that address via a different L1 cache with ld. which writes back cache lines of coherent cache levels with normal eviction policy. but st.PTX ISA Version 2. However. The st. . Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. Global stores bypass L1. .cg is the same as st. The default store instruction cache operation is st.cg to local memory uses the L1 cache. 2010 .0 Table 78. to allow a CPU program to poll a SysMem location written by the GPU with st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. In sm_20. in which case st.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.wt Cache write-through (to system memory). If one thread stores to global memory. likely to be accessed once. Future GPUs may have globally-coherent L1 caches. bypassing its L1 cache. .wb could write-back global store data from L1. rather than get the data from L2 or memory stored by the first thread.cs Cache streaming.

local.a.u16. A. . .u32 mov. u. d. mov.b16. Description . mov. or shared state space may be taken directly using the cvta instruction.e. A[5]. addr. Introduced in PTX ISA version 1.f32. or shared state space. myFunc. local. . within the variable’s declared state space Notes Although only predicate and bit-size types are required. d = &label. . // get address of variable // get address of label or function .global. d = &avar.0. Instruction Set Table 79. label. .b64.f64 requires sm_13 or later. For variables declared in . .s64. variable in an addressable memory space. alternately. i.b32. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. ptr. . a. . . or function name. Semantics d = a. sreg. ptr. and . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.v.type mov. d. mov.local. special register. .f32 mov. the parameter will be copied onto the stack and the address will be in the local state space.1.s16. Note that if the address of a device function parameter is moved to a register. immediate.const. Operand a may be a register. .type d. the address of the variable in its state space) into the destination register.pred.f32 mov. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. d = sreg. 2010 111 .Chapter 8. avar. Take the non-generic address of a variable in global.u64.s32.shared state spaces.u32 mov.e. label.0.f64 }. Write register d with the value of a.u16 mov. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.u32. the generic address of a variable declared in global. // address is non-generic. local. d.u32 d.type = { . The generic address of a variable in global. k... mov places the non-generic address of the variable (i. .type mov.type mov.

g. a[48.type = { .. d.x | (a. lo.47]. d...y } = { a[0. a.a}.b.23]. %x.0.%r1.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 // pack two 16-bit elements into .z. {r. a[32.z.type d. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.15].x | (a. For bit-size types. d. a[24.z..u16 %x is a double.b32. .w}.b. {lo.b16 { d. d.x.w << 24) d = a.b32 %r1.x | (a.b64 mov. d.PTX ISA Version 2.u32 x.a have type .31].w } = { a[0. %r1.b32 { d.hi}.g. a[8. d.15]. Description Write scalar register d with the packed value of vector register a.x. d.7].b}.z.0 Table 80.b64 { d.u8 // unpack 32-bit elements from .31].y << 16) | (a.y } = { a[0.{a.y } = { a[0. a[8. a[16..b64 112 January 24.b32 { d. mov. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b16 // pack four 8-bit elements into .15].x.b32 mov.y.x | (a.b64 { d.7]. a[32.w have type .y.31] } // unpack 16-bit elements from ...x..y << 32) // pack two 8-bit elements into . or write vector register d with the unpacked values from scalar register a.y... ..y. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. .{x. a[16.w } = { a[0.. Supported on all target architectures.15] } // unpack 8-bit elements from .y << 8) d = a.y << 8) | (a.z << 16) | (a. Semantics d = a. a[16. 2010 ..x | (a. // // // // a.b64 // pack two 32-bit elements into .b have type .b16.31] } // unpack 8-bit elements from .y << 16) d = a.w << 48) d = a.b32 // pack four 16-bit elements into .63] } // unpack 16-bit elements from . d.z << 32) | (a.b32 mov. d..hi are .b64 }. mov.b8 r.x.

ca. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.u16.v4 }.f32. Within these windows.cs. for example. [a]. [a]. Addresses are zero-extended to the specified width as needed.b16. Instruction Set Table 81. . *(a+immOff). d. ld{.cop}. This may be used.ss}. *(immAddr). to enforce sequential consistency between threads accessing shared memory. PTX ISA Notes January 24.v2.type . . .s16. [a].ss}{.e. The address size may be either 32-bit or 64-bit.1. A destination register wider than the specified type may be used.cop = { .s8. .ss = { . 2010 113 .vec = { .f64 }. an address maps to global memory unless it falls within the local memory window or the shared memory window. . an address maps to the corresponding location in local or shared memory. Generic addressing may be used with ld.type ld{.type d.reg state space.volatile{.global and . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . .global. or the instruction may fault. .b16. perform the load using generic addressing. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . .f32 or . .f16 data may be loaded using ld. d. Description Load register variable d from the location specified by the source address operand a in specified state space.const. ld introduced in PTX ISA version 1.b32.Chapter 8.0.vec.u32. . [a].volatile may be used with .ss}{.shared }.type ld. *a.s32. an integer or bit-size type register reg containing a byte address. . Generic addressing and cache operations introduced in PTX ISA 2.b8.lu. The value loaded is sign-extended to the destination register width for signed integers. .f64 using cvt. .shared spaces to inhibit optimization of references to volatile memory. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.0. . .volatile introduced in PTX ISA version 1.cop}. . . . . .cg.vec. . and truncated if the register width exceeds the state space address width for the target architecture.u8.b64. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. the resulting behavior is undefined.s64.const space suffix may have an optional bank number to indicate constant banks other than bank zero. i.volatile{. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. i.e.local.param. In generic addressing. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.u64. . and then converted to .. The .volatile.cv }. d.volatile. 32-bit). 32-bit). and is zeroextended to the destination register width for unsigned and bit-size types. . . Cache operations are not permitted with ld. Semantics d d d d = = = = a. If no state space is given. If an address is not properly aligned. or [immAddr] an immediate absolute byte address (unsigned. ld.type = { . The address must be naturally aligned to a multiple of the access size.ss}. ld.

local. 2010 .[240].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[buffer+64]. d.b16 cvt.f64 requires sm_13 or later.[p+-8]. x.local. ld.f32 ld.[p].f16 d. %r.[fs].[p+4].const.0 Target ISA Notes ld.const[4].b32 ld.f32.v4.shared. Generic addressing requires sm_20 or later.PTX ISA Version 2.%r. Q. // load .b64 ld.global.s32 ld. // immediate address %r. // access incomplete array x.global. Cache operations require sm_20 or later. // negative offset %r.b32 ld.b32 ld.[a].

type d.ss = { . .reg state space. If no state space is given. perform the load using generic addressing. .s16.vec.b16. 2010 115 . d. ldu. . . .s64. ldu.f32 d. and truncated if the register width exceeds the state space address width for the target architecture.b16.[p+4]. The data at the specified address must be read-only. ldu{. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. i. . *(a+immOff). the access may proceed by silently masking off low-order address bits to achieve proper rounding. . where the address is guaranteed to be the same across all threads in the warp. A register containing an address may be declared as a bit-size type or integer type. . Addresses are zero-extended to the specified width as needed. and then converted to .[p].u16. an address maps to global memory unless it falls within the local memory window or the shared memory window.e.u32.global. Introduced in PTX ISA version 2.global. or the instruction may fault. The value loaded is sign-extended to the destination register width for signed integers.s32. [a].v4 }.f16 data may be loaded using ldu. . ldu. The address size may be either 32-bit or 64-bit.[a]. or [immAddr] an immediate absolute byte address (unsigned.f32. [a].f64 using cvt.b64. ldu. // load from address // vec load from address .u64.global }. .global.v4. The addressable operand a is one of: [avar] the name of an addressable variable var. PTX ISA Notes Target ISA Notes Examples January 24.0. the resulting behavior is undefined. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. i. A destination register wider than the specified type may be used. 32-bit). . . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . Instruction Set Table 82.v2. The address must be naturally aligned to a multiple of the access size. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. an address maps to the corresponding location in local or shared memory. 32-bit).b32 d.u8.. Semantics d d d d = = = = a.s8. *(immAddr).b8.e. *a. . .ss}. If an address is not properly aligned.type ldu{. only generic addresses that map to global memory are legal.f32 Q.type = { .f32 or . Within these windows.Chapter 8.ss}.b32. In generic addressing.f64 requires sm_13 or later. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f64 }. // state space . . For ldu. [areg] a register reg containing a byte address. and is zeroextended to the destination register width for unsigned and bit-size types.vec = { .

type . i.1. to enforce sequential consistency between threads accessing shared memory. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. Generic addressing and cache operations introduced in PTX ISA 2.wt }.v4 }. st.b32. . b.u32.cop}. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. [a]. [a].volatile{.e. .vec .global and . an address maps to the corresponding location in local or shared memory.volatile. If an address is not properly aligned.volatile.b8. Addresses are zero-extended to the specified width as needed.vec. { .cg.ss}. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . The address must be naturally aligned to a multiple of the access size. or [immAddr] an immediate absolute byte address (unsigned.s8. Generic addressing requires sm_20 or later.f64 }. . . Cache operations are not permitted with st. st{.volatile{.f16 data resulting from a cvt instruction may be stored using st.ss}{.ss . [a].vec. *(d+immOffset) = a. perform the store using generic addressing.reg state space. ..type = = = = {.local. .global. 32-bit). { . .volatile may be used with . . A source register wider than the specified type may be used. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.0.u64. an address maps to global memory unless it falls within the local memory window or the shared memory window.f64 requires sm_13 or later.b64. . This may be used. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.wb. the resulting behavior is undefined. an integer or bit-size type register reg containing a byte address. .f32.ss}{. i. . If no state space is given. . PTX ISA Notes Target ISA Notes 116 January 24.s64. *(immAddr) = a. .b16. { . b.v2. . . .s16. st introduced in PTX ISA version 1.cs. or the instruction may fault.type st{.b16. *d = a.shared }. 2010 . . In generic addressing.u16.volatile introduced in PTX ISA version 1. st.type st. st. b. Within these windows. Semantics d = a. b. the access may proceed by silently masking off low-order address bits to achieve proper rounding.cop}. The address size may be either 32-bit or 64-bit.e. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. Cache operations require sm_20 or later.u8.PTX ISA Version 2.shared spaces to inhibit optimization of references to volatile memory. for example. Generic addressing may be used with st. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. . .0 Table 83.s32.cop .0.ss}. and truncated if the register width exceeds the state space address width for the target architecture. 32-bit). The lower n bits corresponding to the instruction-type width are stored to memory.type [a].

r7.global.f32 st.f32 st.a.global.b32 st.b32 st.local. // immediate address %r.Chapter 8.local.%r. [p].Q.v4. Instruction Set Examples st.s32 cvt.b.b16 [a]. // %r is 32-bit register // store lower 16 bits January 24. [q+-8].%r.local. 2010 117 .s32 st.a. [q+4]. [fs].f16. // negative offset [100].

the prefetch uses generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. in specified state space. A prefetch to a shared memory location performs no operation.PTX ISA Version 2.space}. 118 January 24. an address maps to global memory unless it falls within the local memory window or the shared memory window. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. The address size may be either 32-bit or 64-bit.0 Table 84. . prefetchu Prefetch line containing generic address at specified level of memory hierarchy. prefetchu. prefetch{. a register reg containing a byte address. an address maps to the corresponding location in local or shared memory. // prefetch to data cache // prefetch to uniform cache . prefetch and prefetchu require sm_20 or later. 32-bit). and no operation occurs if the address maps to a local or shared memory location.global.e.L1 [a]. i. [a].L1.L1 [addr]. prefetch.global.space = { .L2 }.local }. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.level prefetchu. A prefetch into the uniform cache requires a generic address.L1 [ptr]. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. 32-bit). Within these windows.0. .level = { . If no state space is given. and truncated if the register width exceeds the state space address width for the target architecture. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. or [immAddr] an immediate absolute byte address (unsigned. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. Addresses are zero-extended to the specified width as needed. 2010 . . In generic addressing.

local. PTX ISA Notes Target ISA Notes Examples Table 86.global. // get generic address of svar cvta. or shared state space. or shared address.Chapter 8.space = { .u32 gptr. Take the generic address of a variable declared in global. Introduced in PTX ISA version 2. . a. or vice-versa. .0. . The destination register must be of type .0. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u64.local.lptr. The source and destination addresses must be the same size.space p.local isspacep. local. or shared state space.space. isspacep.local. The source address operand must be a register of type . local.size p. p. svar. or shared address to a generic address. cvta. cvta. local.space. January 24. p. isspacep requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.to. A program may use isspacep to guard against such incorrect behavior.global. the generic address of the variable may be taken using cvta. or shared state space to generic. . a. isspacep. .space = { .global isspacep.size . Use cvt. When converting a generic address into a global. or vice-versa. or shared address cvta.u32 to truncate or zero-extend addresses.size = { .space.shared }. // convert to generic address // get generic address of var // convert generic address to global. islcl.u64 }.u32 or . isshrd. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.to.pred.genptr.shared }.global.u64 or cvt. lptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. a. gptr.size cvta. For variables declared in global. sptr. .u32. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. Instruction Set Table 85.u32 p. cvta requires sm_20 or later. cvta. 2010 119 .shared. // result is . local. Description Convert a global. local. // local.u32.shared isglbl.u32 p. var.u64.pred .

d = convert(a). . Integer rounding modifiers: . Integer rounding is illegal in all other instances.f16.f32.rni. .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. 120 January 24.f32 float-to-integer conversions and cvt.ftz}{.ftz modifier may be specified in these cases for clarity.dtype. Saturation modifier: . Integer rounding is required for float-to-integer conversions.dtype = . For float-to-integer conversions.rni round to nearest integer.e. sm_1x: For cvt. . . the result is clamped to the destination range by default. The optional .0 Table 87.PTX ISA Version 2. . .e. subnormal numbers are supported.dtype. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.atype cvt{.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. . . subnormal inputs are flushed to signpreserving zero. a. // integer rounding // fp rounding .u64. .u8.sat}.4 and earlier. . .s8.sat For integer destination types..frnd = { .f32.f32 float-to-integer conversions and cvt. . .irnd}{.f32. .f64 }.s32.dtype. i.f32 float-tofloat conversions with integer rounding.frnd}{. The compiler will preserve this behavior for legacy PTX code.u16.ftz.s64. . and for same-size float-tofloat conversions where the value is rounded to an integer. choosing even integer if source is equidistant between two integers.f32 float-tofloat conversions with integer rounding. Description Semantics Integer Notes Convert between different types and sizes. For cvt.sat limits the result to MININT.rzi round to nearest integer in the direction of zero . the .atype d.. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.s16.ftz. d.sat is redundant.rz. i.rpi }.atype = { . . .rp }.rmi. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.MAXINT for the size of the operation.irnd = { . .ftz}{.ftz. cvt{.sat}.rm.dtype. a.ftz.rzi.rmi round to nearest integer in direction of negative infinity . .rn.u32. . . subnormal inputs are flushed to signpreserving zero. Note: In PTX ISA versions 1. Note that saturation applies to both signed and unsigned integer types. 2010 .

Floating-point rounding modifiers: . Note: In PTX ISA versions 1.rn mantissa LSB rounds to nearest even . // float-to-int saturates by default cvt.4 and earlier.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).0].sat limits the result to the range [0. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. Applies to . // round to nearest int. The optional .f32.f32.s32 f.f32 x. The operands must be of the same size. and for integer-to-float conversions.f16.ftz behavior for sm_1x targets January 24. Specifically.f64 types. cvt. . the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .rm mantissa LSB rounds towards negative infinity . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32 x. .Chapter 8.f32.f64.i.f32 instructions. cvt.r.f32.f32. if the PTX .sat For floating-point destination types. Modifier .f16.rni. subnormal numbers are supported.f32. stored in floating-point format.0.f16.y.s32.f64 j. The result is an integral value.0. 1.ftz modifier may be specified in these cases for clarity. result is fp cvt. and . Subnormal numbers: sm_20: By default. The compiler will preserve this behavior for legacy PTX code. cvt to or from . Saturation modifier: .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.version is 1.f32. Introduced in PTX ISA version 1.4 or earlier. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. NaN results are flushed to positive zero. // note .rz mantissa LSB rounds towards zero .f64 requires sm_13 or later. 2010 121 . Floating-point rounding is illegal in all other instances. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. cvt.y. and cvt.

samplerref tsamp1 = { addr_mode_0 filter_mode }..r4}. Ability to query fields within texture.r3.7. // get tex1’s tex.height.global .u32 r5. and surface descriptors. r5.b32 r5. 122 January 24. . If no texturing mode is declared. r6. r4. r1. r5. A PTX module may declare only one texturing mode. In the independent mode.b32 r6. r2. [tex1].f32.f2}]. and surface descriptors.v4.f32 r1. Module-scope and per-entry scope definitions of texture. . allowing them to be defined separately and combined at the site of usage in the program. PTX has two modes of operation. {f1. cvt. with the restriction that they correspond 1-to-1 with the 128 possible textures. The texturing mode is selected using . r3. r1. r3. the file is assumed to use unified mode. and surface descriptors. mul. r5.param . sampler. = nearest width height tsamp1.. . texture and sampler information is accessed through a single . // get tex1’s txq.texref handle.r2. [tex1.2d. Example: calculate an element’s power contribution as element’s power/total number of elements. } = clamp_to_border.PTX ISA Version 2.entry compute_power ( . sampler.width.6. r1. sampler. The advantage of independent mode is that textures and samplers can be mixed and matched. The advantage of unified mode is that it allows 128 samplers.f32 r3. 2010 . add. add. and surface descriptors: • • • Static initialization of texture. add. texture and sampler information each have their own handle. and surfaces. but the number of samplers is greatly restricted to 16. PTX supports the following operations on texture.u32 r5. In the unified mode. samplers.f32 r1.f32.target texmode_independent .texref tex1 ) { txq. Texturing modes For working with textures and samplers.f32 r1.0 8. Texture and Surface Instructions This section describes PTX instructions for accessing textures. [tex1].target options ‘texmode_unified’ and ‘texmode_independent’. sampler.f32 {r1. div.

geom.geom = { .1d. // Example of independent mode texturing tex.v4. c].u32. {f1}]. If no sampler is specified.v4.btype = { . 2010 123 .btype d. Instruction Set These instructions provide access to texture and surface memory. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. i.geom. b. with the extra elements being ignored.r3.1d. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. The instruction always returns a four-element vector of 32-bit values. // explicit sampler . Description Texture lookup using a texture coordinate vector. where the fourth element is ignored.0.f3.f32 {r1. tex. . the resulting behavior is undefined. is a two-element vector for 2d textures. [tex_a.dtype = { .v4 coordinate vectors are allowed for any geometry. //Example of unified mode texturing tex.btype tex.s32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.r4}.f32 }. the sampler behavior is a property of the named texture. [a. .r2. tex txq suld sust sured suq Table 88. sampler_x. .f4}]. A texture base address is assumed to be aligned to a 16-byte address.s32 {r1. An optional texture sampler b may be specified. [a. . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.Chapter 8.3d }..dtype.5.f32 }. [tex_a. .s32. Supported on all target architectures.v4.2d. {f1.r2. Operand c is a scalar or singleton tuple for 1d textures.s32.r3. c].e.3d. or the instruction may fault. .dtype.r4}. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.f2. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32. the square brackets are not required and . If an address is not properly aligned. Notes For compatibility with prior versions of PTX. PTX ISA Notes Target ISA Notes Examples January 24. Unified mode texturing introduced in PTX ISA version 1. and is a four-element vector for 3d textures. d.v4.

b32 %r1.samplerref variable.squery = { . 2010 .addr_mode_0. and in independent mode sampler attributes are accessed via a separate samplerref argument. txq. [smpl_B].normalized_coords .height. // texture attributes // sampler attributes . addr_mode_2 }.b32 d. . txq.0 Table 89.normalized_coords }. txq.tquery. [a].PTX ISA Version 2. .b32 %r1.addr_mode_2 Returns: value in elements 1 (true) or 0 (false). // unified mode // independent mode 124 January 24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. [a].squery.height . mirror. linear } Integer from enum { wrap.filter_mode.depth .filter_mode . Supported on all target architectures. [tex_A]. Description Query an attribute of a texture or sampler.texref or . In unified mode. addr_mode_1. Operand a is a . txq. .tquery = { .b32 txq.addr_mode_0. . clamp_to_edge.addr_mode_0 .addr_mode_1 . [tex_A].width. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.5. Integer from enum { nearest. clamp_ogl.width. sampler attributes are also accessed via a texref argument. d.width . Query: . . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.b32 %r1.depth.filter_mode.

cop}.cv }. and cache operations introduced in PTX ISA version 2.b64 }.e.dtype.dtype .trap .s32. If the destination base type is . .2d.v4. suld. .cop . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. and the size of the data transfer matches the size of destination operand d. where the fourth element is ignored.p requires sm_20 or later.s32. // formatted . i.surfref variable. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. {x}].v2.b supported on all target architectures.b32. then .zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. B. or .clamp. suld.trap.b64. SNORM. Operand a is a . suld. b]. suld. and A components of the surface format. the resulting behavior is undefined. // cache operation none.b32.clamp suld.b8 . Operand b is a scalar or singleton tuple for 1d surfaces.3d }.p.b.y.5. .f32 }.b. is a two-element vector for 2d surfaces. . // unformatted d. G. The lowest dimension coordinate represents a sample offset rather than a byte offset. [surf_B.cg. .u32 is returned. .s32. if the surface format contains SINT data.p .dtype . .3d requires sm_20 or later.u32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32. sm_1x targets support only the .zero }.u32.b16. if the surface format contains UINT data. {f1.f4}. [a. .w}].dtype. 2010 125 . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.clamp . . [a.1d. suld.clamp field specifies how to handle out-of-bounds addresses: .f3. .v2. suld.clamp . size and type conversion is performed as needed to convert from the surface sample format to the destination type. Destination vector elements corresponding to components that do not appear in the surface format are not written. . [surf_A. .b.v4 }.vec .trap suld.trap clamping modifier. {x. the surface sample elements are converted to .cs. . suld Syntax Texture and Surface Instructions: suld Load from surface memory.. Instruction Set Table 90.geom .trap introduced in PTX ISA version 1. Coordinate elements are of type .cop}.trap {r1. suld.b32. suld.f32.b performs an unformatted load of binary data. The . or FLOAT data. If an address is not properly aligned.f2. If the destination type is .f32 is returned. or .Chapter 8. then . b].1d. .u32.geom{. // for suld. suld.geom{.3d. . . Cache operations require sm_20 or later.v4. // for suld. or the instruction may fault. and is a four-element vector for 3d surfaces. .ca. then . .p.clamp = = = = = = { { { { { { d.z. A surface base address is assumed to be aligned to a 16-byte address.p.f32 based on the surface format as follows: If the surface format contains UNORM. Description Load from surface memory using a surface coordinate vector.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. additional clamp modifiers.r2}.p is currently unimplemented.f32. Target ISA Notes Examples January 24.0. .vec.s32 is returned.b .

ctype .b64 }. Coordinate elements are of type . The source vector elements are interpreted left-to-right as R.0.cg.trap introduced in PTX ISA version 1. If the source type is . A surface base address is assumed to be aligned to a 16-byte address. sust.s32 is assumed. sust.p requires sm_20 or later. . . Target ISA Notes Examples 126 January 24.clamp sust.b supported on all target architectures. . The .b32.b performs an unformatted store of binary data. c. then .geom{. {r1. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .b8 . [a.f32.u32 is assumed.w}].b64. SNORM. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.5.1d. .trap .vec. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. or the instruction may fault.p. G. additional clamp modifiers.1d.0 Table 91.cop}. . and cache operations introduced in PTX ISA version 2.v4 }. and A surface components.p. size and type conversions are performed as needed between the surface sample format and the destination type.wb. sust Syntax Texture and Surface Instructions: sust Store to surface memory. .clamp = = = = = = { { { { { { [a.b16. .u32.clamp field specifies how to handle out-of-bounds addresses: .cs.vec. These elements are written to the corresponding surface sample components.cop}. sust. is a two-element vector for 2d surfaces.3d }.u32.y. 2010 . sust.f3. sust. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The size of the data transfer matches the size of source operand c.z. .v2.p.vec . where the fourth element is ignored. sust.b32.b.b32. or FLOAT data.clamp .ctype.{u32.trap sust. sm_1x targets support only the . the resulting behavior is undefined. . .f32.trap clamping modifier.s32.p performs a formatted store of a vector of 32-bit data values to a surface sample.b // for sust. and is a four-element vector for 3d surfaces. [surf_B.v2.b.e.clamp . b]. . .s32.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.zero }. Surface sample components that do not occur in the source vector will be written with an unpredictable value. . {x.geom{. i.p.ctype .b. c.s32. . b]. .f2.v4. .2d. If an address is not properly aligned.p Description Store to surface memory using a surface coordinate vector. or . The source data is then converted from this type to the surface sample format. if the surface format contains SINT data.ctype. if the surface format contains UINT data.3d. // unformatted // formatted . sust.geom .3d requires sm_20 or later.f32 }. If the source base type is . then .r2}. none.f32} are currently unimplemented. sust.cop .clamp. Source elements that do not occur in the surface sample are ignored.wt }. {f1. // for sust. . . then .f32 is assumed. The lowest dimension coordinate represents a sample offset rather than a byte offset. B. Operand b is a scalar or singleton tuple for 1d surfaces.PTX ISA Version 2.s32. Cache operations require sm_20 or later. sust.surfref variable.trap [surf_A.f4}. .trap. {x}]. Operand a is a .

. // sample addressing .min. .u32. The lowest dimension coordinate represents a sample offset rather than a byte offset.max. and .c. sured. min and max apply to .u32. then . or . {x.b32 type. sured.ctype.b . r1. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.or }. .s32. .ctype = { . Instruction Set Table 92.p.y}]. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. 2010 127 .s32. and is a four-element vector for 3d surfaces.clamp .geom. .u32. if the surface format contains SINT data. {x}].op. the resulting behavior is undefined.and.b32.u32 and . . A surface base address is assumed to be aligned to a 16-byte address.p performs a reduction on sample-addressed 32-bit data. .3d }.p. Coordinate elements are of type .surfref variable.Chapter 8.u32 based on the surface sample format as follows: if the surface format contains UINT data.p . and the data is interpreted as . .min. . sured. then .b32.c.b32.geom.2d.op = { .s32.clamp = { .trap.b.b.op.clamp [a.add. Operand b is a scalar or singleton tuple for 1d surfaces.ctype = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. sured requires sm_20 or later.ctype. January 24. // for sured. The .trap . .clamp [a.b32 }.b]. // for sured. is a two-element vector for 2d surfaces.b performs an unformatted reduction on .u64 data.s32 or .1d.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32 types. .u64.trap [surf_A.s32 types.2d. Operations add applies to . Operand a is a .trap sured.0. i.u64. r1. sured. // byte addressing sured. where the fourth element is ignored. . If an address is not properly aligned.clamp.add.clamp field specifies how to handle out-of-bounds addresses: .. or the instruction may fault. Reduction to surface memory using a surface coordinate vector.u32 is assumed. .zero }.e.geom = { . [surf_B. .u32.s32 is assumed. operations and and or apply to .b].1d. . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b32 }. The instruction type is restricted to .

surfref variable.width. 128 January 24.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. . [a]. . [surf_A].height. Operand a is a . suq. Query: .width .depth }.query.height .PTX ISA Version 2.5. Description Query an attribute of a surface.width. . suq Syntax Texture and Surface Instructions: suq Query a surface attribute. Supported on all target architectures.0 Table 93.b32 d.b32 %r1.query = { . 2010 . suq.

Supported on all target architectures. Instruction Set 8.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Threads with a false guard predicate do nothing.0.s32 d. 2010 129 . mov. Execute an instruction or instruction block for threads that have the guard predicate true. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.0.0.Chapter 8.7. If {!}p then instruction Introduced in PTX ISA version 1.f32 @!p div. {} Syntax Description Control Flow Instructions: { } Instruction grouping. { instructionList } The curly braces create a group of instructions. p.b.f32 @q bra L23. Supported on all target architectures. used primarily for defining a function body.c. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. setp. Introduced in PTX ISA version 1.y. } PTX ISA Notes Target ISA Notes Examples Table 95. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. { add. ratio.eq.s32 a.a. @{!}p instruction.7.x.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). bar. and bar. Thus. Note that a non-zero thread count is required for bar.u32 bar. Since barriers are executed on a per-warp basis.sync) until the barrier count is met. PTX ISA Notes Target ISA Notes Examples bar. all-threads-true (. The barrier instructions signal the arrival of the executing threads at the named barrier.arrive. while . b}.{arrive.popc. In addition to signaling its arrival at the barrier.popc).sync or bar. and then safely read values stored by other threads prior to the barrier. bar. bar.u32.red are population-count (. b.red} require sm_20 or later. The reduction operations for bar. bar. d. thread count. In conditionally executed code. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. b}. bar.. Register operands. bar.red instruction. If no thread count is specified. Thus. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. threads within a CTA that wish to communicate via memory can store to memory.and. if any thread in a warp executes a bar instruction. operands p and c are predicates. Each CTA instance has sixteen barriers numbered 0.sync and bar. and bar. .red also guarantee memory ordering among threads identical to membar.red. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.15. the bar. Operands a. a. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Instruction Set Table 100.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.sync 0.or).arrive does not cause any waiting by the executing threads. p.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.sync and bar. bar. and d have type .or }. execute a bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. the optional thread count must be a multiple of the warp size. The result of .red performs a reduction operation across threads. When a barrier completes.arrive using the same active barrier. a{. January 24.sync without a thread count introduced in PTX ISA 1.version 2. and the barrier is reinitialized so that it can be immediately reused. bar.red delays the executing threads (similar to bar. Execution in this case is unpredictable.0.sync or bar.popc is the number of threads with a true predicate. Operand b specifies the number of threads participating in the barrier. {!}c. it is as if all the threads in the warp have executed the bar instruction. the final value is written to the destination register in all threads waiting at the barrier.pred . b}.and and . thread count.op = { .0. Only bar.red} introduced in PTX . Register operands.{arrive. Barriers are executed on a per-warp basis as if all the threads in a warp are active. {!}c. All threads in the warp are stalled until the barrier completes.arrive a{. Once the barrier count is reached.red performs a predicate reduction across the threads participating in the barrier. b.Chapter 8. Description Performs barrier synchronization and communication within a CTA. all threads in the CTA participate in the barrier. and any-thread-true (. it simply marks a thread's arrival at the barrier.red.sync with an immediate barrier number is supported for sm_1x targets.cta. 2010 133 . the waiting threads are restarted without delay. bar.op.red should not be intermixed with bar.sync bar.and). a{.

0. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar.gl. A memory write (e.gl will typically have a longer latency than membar.gl} supported on all target architectures. level describes the scope of other clients for which membar is an ordering event. 134 January 24. and memory reads by this thread can no longer be affected by other thread writes. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.{cta. . when the previous value can no longer be read. membar.sys Waits until all prior memory requests have been performed with respect to all clients.version 1.sys requires sm_20 or later. A memory read (e.0 Table 101. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl} introduced in PTX . this is the appropriate level of membar. Waits until prior memory reads have been performed with respect to other threads in the CTA. membar. including thoses communicating via PCI-E such as system and peer-to-peer memory.gl. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. 2010 .sys will typically have much longer latency than membar.{cta. PTX ISA Notes Target ISA Notes Examples membar. membar. membar. membar. membar. membar.sys introduced in PTX .version 2.g. global.gl.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.sys }. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.sys. by st.level = { .cta. .cta Waits until all prior memory writes are visible to other threads in the same CTA.cta.4. membar.level. that is. membar. .g. For communication between threads in different CTAs or even different SMs. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. or system memory level.PTX ISA Version 2.cta.

If an address is not properly aligned. . .cas.b32.b]. . atom. Instruction Set Table 102. cas (compare-and-swap).b64. The bit-size operations are and..and. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.op = { . The integer operations are add.global. dec. . . . [a]. . or by using atom.u32 only . 2010 135 . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.u32.op.exch to store to locations accessed by other atomic operations.min.b64 . atom{. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. perform the memory accesses using generic addressing. The address size may be either 32-bit or 64-bit.type = { . . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. . d. .u32. and max operations are single-precision. the resulting behavior is undefined. overwriting the original value. an address maps to global memory unless it falls within the local memory window or the shared memory window. a de-referenced register areg containing a byte address. Within these windows. January 24. . . b.e.. and stores the result of the specified operation at location a.g. min. or the instruction may fault. In generic addressing. 32-bit operations. The inc and dec operations return a result in the range [0.add. by inserting barriers between normal stores and atomic operations to a common address. i. . an address maps to the corresponding location in local or shared memory. and truncated if the register width exceeds the state space address width for the target architecture. If no state space is given. min. .space = { .space}. accesses to local memory are illegal.Chapter 8. .dec.f32. inc.add. b.f32 Atomically loads the original value at location a into destination register d. .inc.b32. . .type d.type atom{. xor.b32 only . and max. c. min.u64. . or.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.or. . Addresses are zero-extended to the specified width as needed. max.s32. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.shared }. .e.xor. A register containing an address may be declared as a bit-size type or integer type. The floating-point operations are add. . . performs a reduction operation with operand b and the value in location a.s32. i. The floating-point add.f32 }. . The address must be naturally aligned to a multiple of the access size. and exch (exchange).op. Operand a specifies a location in the specified state space.s32.exch.u32. e. For atom. or [immAddr] an immediate absolute byte address.max }. the access may proceed by silently masking off low-order address bits to achieve proper rounding.space}. Description // // // // // . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. [a].u64 .

s) = (r >= s) ? 0 dec(r.[x+4]. d.0.global. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. atom.t) = (r == s) ? t operation(*a. s) = (r > s) ? s exch(r.cas.s.s32 atom. : r.max.1.exch} requires sm_12 or later.{min. b.shared. *a = (operation == cas) ? : } where inc(r.f32 atom.0.my_val.max} are unimplemented. d.f32 requires sm_20 or later.global requires sm_11 or later. 2010 .f32. s) = s. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.my_new_val. atom.shared requires sm_12 or later. atom. Use of generic addressing requires sm_20 or later.cas.[p]. cas(r.0 Semantics atomic { d = *a. c) operation(*a. 64-bit atom. b). : r+1. atom. Release Notes Examples @p 136 January 24.add.[a]. : r-1. atom.b32 d.global.shared operations require sm_20 or later.PTX ISA Version 2.add.{add. 64-bit atom. Introduced in PTX ISA version 1.

dec(r.f32 Performs a reduction operation with operand b and the value in location a. .f32 }.op = { . The floating-point add. .s32. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Addresses are zero-extended to the specified width as needed.and.b64.exch to store to locations accessed by other reduction operations. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. an address maps to the corresponding location in local or shared memory. Notes Operand a must reside in either the global or shared state space. . b). e. where inc(r. . . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.dec.u32. i. s) = (r > s) ? s : r-1.Chapter 8. .op.or.shared }. or [immAddr] an immediate absolute byte address.max }. perform the memory accesses using generic addressing. and max.add. Instruction Set Table 103. or. 2010 137 .u64 . accesses to local memory are illegal. and truncated if the register width exceeds the state space address width for the target architecture. If an address is not properly aligned. The bit-size operations are and. or by using atom.s32. In generic addressing.e.g. the resulting behavior is undefined. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. by inserting barriers between normal stores and reduction operations to a common address. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.type [a].f32. min.u32 only . the access may proceed by silently masking off low-order address bits to achieve proper rounding. and stores the result of the specified operation at location a. .s32.b32. s) = (r >= s) ? 0 : r+1.min. The floating-point operations are add.type = { . For red. Description // // // // . or the instruction may fault.e. . dec. inc. . Within these windows.xor.space = { . January 24. . The inc and dec operations return a result in the range [0. i. . Operand a specifies a location in the specified state space. 32-bit operations. max. . A register containing an address may be declared as a bit-size type or integer type. and xor.u64. red{. and max operations are single-precision.inc. . min. . an address maps to global memory unless it falls within the local memory window or the shared memory window. If no state space is given... to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. b.add. min. a de-referenced register areg containing a byte address. .space}.b32 only .u32. . .b]. The address size may be either 32-bit or 64-bit. The address must be naturally aligned to a multiple of the access size.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.u32. Semantics *a = operation(*a. red. . .global. overwriting the original value. The integer operations are add. .

max. red. red.0.shared. [p]. [x+4].f32. Release Notes Examples @p 138 January 24.global.s32 red.shared requires sm_12 or later.b32 [a].and.global.max} are unimplemented. 64-bit red.add requires sm_12 or later. red.{min.add.shared operations require sm_20 or later.1.f32 red. red.f32 requires sm_20 or later.global requires sm_11 or later red. 2010 .2.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 64-bit red.add.my_val. Use of generic addressing requires sm_20 or later.PTX ISA Version 2.

. Negating the source predicate also computes .q. Note that vote applies to threads in a single warp.Chapter 8.ballot.uni True if source predicate has the same value in all active threads in warp. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Negate the source predicate to compute .any.pred d. vote.all. {!}a. The reduction modes are: . 2010 139 . p.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d. .ballot. vote. In the ‘ballot’ form.2.b32 d. returns bitmask . .ballot.pred vote. not across an entire CTA.pred vote.uni. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. vote. Description Performs a reduction of the source predicate across threads in a warp. vote. .all.ballot.uni }. r1. Instruction Set Table 104. // ‘ballot’ form.any True if source predicate is True for some active thread in warp.mode.uni. {!}a.b32 requires sm_20 or later.mode = { .q.not_all. vote requires sm_12 or later.all True if source predicate is True for all active threads in warp. Negate the source predicate to compute . The destination predicate value is the same across all threads in the warp. vote.none.b32 p.p. // get ‘ballot’ across warp January 24. where the bit position corresponds to the thread’s lane id.

half-word. 2010 . 140 January 24.dsel = .7.PTX ISA Version 2.asel}. .b3. .asel}. atype. extract and sign. . . a{.s32 }. optionally clamp the result to the range of the destination type. The type of each operand (.atype. The general format of video instructions is as follows: // 32-bit scalar operation. perform a scalar arithmetic operation to produce a signed 34-bit result. 3. Video Instructions All video instructions operate on 32-bit register operands. or word values from its source operands.atype = . The source and destination operands are all 32-bit registers. .bsel}.secop d. // 32-bit scalar operation. b{.dsel. all combinations of dtype.sat} d.btype{.sat}. Using the atype/btype and asel/bsel specifiers. b{.s34 intermediate result.h0.h1 }.dtype.9. . .secop = { . a{.b1. c. and btype are valid. taking into account the subword destination size in the case of optional data merging. . b{.dtype. . .or zero-extend byte.b2. with optional secondary operation vop. 4.u32 or .atype.dtype = . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. The primary operation is then performed to produce an . The sign of the intermediate result depends on dtype. with optional data merge vop. vop. c. .sat} d.btype{.bsel}.btype = { .asel}.s33 values.bsel}. to produce signed 33-bit input values.extended internally to .bsel = { . a{.b0.atype.min. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. 2.max }.add. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.asel = .0 8.dtype.s32) is specified in the instruction type.btype{.u32. the input values are extracted and signor zero.

U32_MIN ). January 24. . tmp. . . . c). . . S16_MIN ). 2010 141 .s33 optSecOp(Modifier secop. tmp. tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. . Bool sat.b3: if ( sign ) return CLAMP( else return CLAMP( case . Modifier dsel ) { if ( !sat ) return tmp.s33 c ) switch ( dsel ) { case .min: return MIN(tmp. tmp.add: return tmp + c. U8_MIN ).b0: return ((tmp & 0xff) case . U8_MAX.s33 tmp. c). . S8_MAX.s33 optSaturate( .max return MAX(tmp.b2. Instruction Set . The lower 32-bits are then written to the destination operand. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). .b1: return ((tmp & 0xff) << 8) case .h0: return ((tmp & 0xffff) case . c).s34 tmp.b2: return ((tmp & 0xff) << 16) case .s33 optMerge( Modifier dsel. S32_MAX. tmp. U16_MIN ).h0.b1. S16_MAX.s33 tmp.b3: return ((tmp & 0xff) << 24) default: return tmp. S8_MIN ). as shown in the following pseudocode. } } . default: return tmp. U32_MAX. Bool sign. .b0. c).h1: return ((tmp & 0xffff) << 16) case . c). switch ( dsel ) { case .Chapter 8. c). . S32_MIN ). U16_MAX. c). The sign of the c operand is based on dtype.s33 c) { switch ( secop ) { . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.

tmp. tmp = ta – tb.h1 }. vadd. Perform scalar arithmetic operation with optional saturate.s32.op2 d.b2. . and optional secondary arithmetic operation or subword data merge. vsub vabsdiff vmin.asel = .h0. // optional merge with c operand 142 January 24.s32. dsel ). vsub.add.sat vmin.add r1. Integer byte/half-word/word absolute value of difference.bsel}.bsel}. r1. r2. vsub. .vop .sat vsub.0 Table 105.op2 Description = = = = { vadd.PTX ISA Version 2.btype{.s32. isSigned(dtype).atype = . 2010 . // extract byte/half-word/word and sign. // optional secondary operation d = optMerge( dsel. vmin.asel}.btype = { .dsel. r3. vmin.b0. r2.b0.dtype. sat.h1. Semantics // saturate. c ). d = optSecondaryOp( op2.dsel .sat vabsdiff. c. . with optional secondary operation vop. vmax Syntax Integer byte/half-word/word addition / subtraction. tmp = | ta – tb |. btype. vsub.asel}.b0.u32. b{.max }. vmax require sm_20 or later.s32. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.bsel = { .h1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vabsdiff.asel}. Video Instructions: vadd. c ).u32. vmin. { . r3. Integer byte/half-word/word minimum / maximum. .h0.0. b{.btype{. . vmax vadd.s32 }. r3.b2.s32.dtype.s32. tb = partSelectSignExtend( b. with optional data merge vop. vmax }.sat} d. .btype{.sat}.b3. a{. . // 32-bit scalar operation. .atype. r1. c. vabsdiff.or zero-extend based on source operand type ta = partSelectSignExtend( a. asel ). . r3. .sat. // 32-bit scalar operation. taking into account destination type and merge operations tmp = optSaturate( tmp.s32. vop.atype. tmp = MIN( ta.s32.sat} d. c. tmp = MAX( ta.h0.b1. c.atype.dtype.u32. vabsdiff. tb ).bsel}. vadd.min.s32. tb ). b{. tmp.s32. atype. bsel ). a{. r1. . r2.dtype . r2. a{.

b2. .u32{. vshr }. a{. vshr require sm_20 or later. vshl.bsel}.b1. a{. asel ). January 24.u32.b0. Video Instructions: vshl.dtype.atype. // optional secondary operation d = optMerge( dsel. tb = partSelectSignExtend( b.wrap ) tb = tb & 0x1f.u32{. dsel ).min.u32. .mode} d.atype = { .mode} d.Chapter 8. isSigned(dtype). . d = optSecondaryOp( op2. . .asel}. . vop. r3.wrap }. 2010 143 .s32.clamp && tb > 32 ) tb = 32. b{.or zero-extend based on source operand type ta = partSelectSignExtend( a.sat}{. with optional secondary operation vop. c ). b{.clamp. .dtype .asel}. tmp. Signed shift fills with the sign bit. .u32. // 32-bit scalar operation. { .u32. bsel ).u32 vshr.bsel = { . c ). sat. c. .wrap r1. Instruction Set Table 106.s32 }.sat}{.mode}. case vshr: tmp = ta >> tb.dsel .dtype. switch ( vop ) { case vshl: tmp = ta << tb. atype. Semantics // extract byte/half-word/word and sign. vshr: Shift a right by unsigned amount in b with optional saturate.h0. unsigned shift fills with zero.mode .op2 d. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32.bsel}. and optional secondary arithmetic operation or subword data merge. // 32-bit scalar operation.clamp .asel = . c.dtype. // default is . and optional secondary arithmetic operation or subword data merge. . Left shift fills with zero. r3.vop .h1 }.dsel.op2 Description = = = = = { vshl.bsel}. b{.max }.u32{.sat}{.asel}. } // saturate. . taking into account destination type and merge operations tmp = optSaturate( tmp. r2. a{. with optional data merge vop. vshl: Shift a left by unsigned amount in b with optional saturate. tmp. vshl.add. { . if ( mode == .atype. r1.b3.h1. . r2.0.atype. vshr vshl. if ( mode == . vshr Syntax Integer byte/half-word/word left / right shift.u32.

The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. . b{.asel}. final signed -(S32 * U32) + S32 // intermediate signed.asel = .dtype. final signed (S32 * U32) .scale} d. The source operands support optional negation with some restrictions. and zero-extended otherwise.dtype = . The “plus one” mode (. which is used in computing averages. . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. The final result is unsigned if the intermediate result is unsigned and c is not negated.dtype. otherwise. Input c has the same sign as the intermediate result. Description Calculate (a*b) + c. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. . c.h1 }. PTX allows negation of either (a*b) or c. .atype. with optional operand negates. final signed (S32 * U32) + S32 // intermediate signed. vmad. .0 Table 107. That is. {-}a{.po{. 144 January 24.s32 }. {-}b{..PTX ISA Version 2. final signed (U32 * U32) . Although PTX syntax allows separate negation of the a and b operands.u32.sat}{.atype. final unsigned -(U32 * U32) + S32 // intermediate signed. 2010 . . . Source operands may not be negated in .atype = .S32 // intermediate signed. final signed (S32 * S32) + S32 // intermediate signed. and the operand negates.b0.scale} d. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.scale = { . “plus one” mode. final signed (U32 * S32) .bsel = { .btype{. final signed (S32 * S32) .bsel}.bsel}.U32 // intermediate unsigned. Depending on the sign of the a and b operands. . {-}c. final signed The intermediate result is optionally scaled via right-shift.sat}{. the intermediate result is signed.po) computes (a*b) + c + 1.h0.b1.asel}. final signed -(U32 * S32) + S32 // intermediate signed. final signed (U32 * S32) + S32 // intermediate signed.btype = { . internally this is represented as negation of the product (a*b).b2. .po mode.b3. a{. final signed -(S32 * S32) + S32 // intermediate signed. (a*b) is negated if and only if exactly one of a or b is negated. this result is sign-extended if the final result is signed. // 32-bit scalar operation vmad.btype.shr7.S32 // intermediate signed.S32 // intermediate signed. and scaling.shr15 }. .

r3. 2010 145 . } else if ( a.negate ) { tmp = ~tmp.shr15 r0. else result = CLAMP(result. S32_MIN). -r3. tmp = tmp + c128 + lsb. U32_MAX.u32. if ( . tb = partSelectSignExtend( b. r0. case .negate ^ b. S32_MAX.negate. vmad.sat vmad.Chapter 8.sat ) { if (signedFinal) result = CLAMP(result.negate ) { c = ~c.shr7: result = (tmp >> 7) & 0xffffffffffffffff. r2.h0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. } else if ( c.s32. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).s32.0. signedFinal = isSigned(atype) || isSigned(btype) || (a.u32. Instruction Set Semantics // extract byte/half-word/word and sign.h0. tmp[127:0] = ta * tb. lsb = 1.negate) || c. r2. U32_MIN). switch( scale ) { case .or zero-extend based on source operand type ta = partSelectSignExtend( a. lsb = 1. r1. January 24. vmad requires sm_20 or later. bsel ).po ) { lsb = 1. r1.u32. asel ). lsb = 0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. atype.u32. btype.negate ^ b. } if ( .

cmp .atype . { . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.btype.u32.u32. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison. vset requires sm_20 or later.s32 }.b1. tmp.lt.add. . tb. // 32-bit scalar operation. b{. { .eq.h1 }.0.bsel}.ge }.gt.PTX ISA Version 2.s32.0 Table 108. . btype. .b0. .op2 d. vset.u32. bsel ).cmp d.asel}. r2. 146 January 24.ne r1. .bsel}. c.atype.le.cmp.max }. tmp. .h1. . . a{. c. b{.dsel.asel}. vset.atype.asel = . with optional secondary arithmetic operation or subword data merge. r3. b{. r3.h0.b2. The intermediate result of the comparison is always unsigned. // 32-bit scalar operation. // optional secondary operation d = optMerge( dsel.or zero-extend based on source operand type ta = partSelectSignExtend( a. a{.bsel = { .op2 Description = = = = .min. c ).bsel}. . atype.lt vset. cmp ) ? 1 : 0. . with optional secondary operation vset.u32.b3. asel ).asel}.ne. Semantics // extract byte/half-word/word and sign. and therefore the c operand and final result are also unsigned. . .dsel . c ). 2010 .btype.cmp d.atype. Compare input values using specified comparison. r2. . . d = optSecondaryOp( op2. with optional data merge vset. a{.btype = { . tmp = compare( ta. . r1. tb = partSelectSignExtend( b.btype.

Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint.0. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Introduced in PTX ISA version 1. Instruction Set 8.4. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. trap. Table 111. pmevent a. brkpt.Chapter 8. numbered 0 through 15. trap.10. with index specified by immediate operand a. Triggers one of a fixed number of performance monitor events. brkpt.0. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Table 110. brkpt Suspends execution Introduced in PTX ISA version 1. @p pmevent 1. there are sixteen performance monitor events. January 24. 2010 147 . Notes PTX ISA Notes Target ISA Notes Examples Currently. trap Abort execution and generate an interrupt to the host CPU. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. pmevent 7. brkpt requires sm_11 or later. Supported on all target architectures.7. The relationship between events and counters is programmed via API calls from the host. Introduced in PTX ISA version 1. Supported on all target architectures.

0 148 January 24.PTX ISA Version 2. 2010 .

The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. Special Registers PTX includes a number of predefined. %clock64 %pm0. %lanemask_lt. 2010 149 . which are visible as special registers and accessed through mov or cvt instructions.Chapter 9. %lanemask_ge. %pm3 January 24. read-only variables. %lanemask_le. %lanemask_gt %clock. ….

z.x.%tid. Redefined as .z.y * %ntid.%h1.u32 %tid.z). mov. Redefined as .u32 %r0.x < %ntid. read-only.y 0 <= %tid.y.u32 %tid. %tid.x code accessing 16-bit component of %tid mov. mov. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.0 Table 112. The number of threads in each dimension are specified by the predefined special register %ntid.y.v4 . .z PTX ISA Notes Introduced in PTX ISA version 1.x 0 <= %tid. // legacy PTX 1. .u32 %ntid.sreg .u32 type in PTX 2.z == 1 in 1D CTAs.x.0.0.y == %tid.z to %r2 Table 113.z == 1 in 2D CTAs.0.z == 0 in 1D CTAs. %tid.x * %ntid.x. // thread id vector // thread id components A predefined. CTA dimensions are non-zero.u32 %ntid. %ntid. The total number of threads in a CTA is (%ntid.x.y == %ntid. // zero-extend tid.u16 %rh.x.sreg .z. %ntid. 2D.PTX ISA Version 2. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. or 3D vector to match the CTA shape. PTX ISA Notes Introduced in PTX ISA version 1. %tid.y < %ntid.u32 %r1.%ntid. %tid.z < %ntid. It is guaranteed that: 0 <= %tid.0. 2010 . Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. %ntid. // compute unified thread id for 2D CTA mov.u16 %r2.%tid. The %tid special register contains a 1D.u32 type in PTX 2. cvt.x.sreg .x.u32.u32 %r0. mad.z == 0 in 2D CTAs. . %ntid.v4.%tid.v4.u16 %rh. Supported on all target architectures.x to %rh Target ISA Notes Examples // legacy PTX 1. Every thread in the CTA has a unique %tid. // move tid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.y. read-only special register initialized with the number of thread ids in each CTA dimension.sreg .%tid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. The fourth element is unused and always returns zero. the %tid value in unused dimensions is 0.%tid.%r0.v4 .x code Target ISA Notes Examples 150 January 24. . mov. // CTA shape vector // CTA dimensions A predefined.%h2. mov. %tid component values range from 0 through %ntid–1 in each CTA dimension. per-thread special register initialized with the thread identifier within the CTA. the fourth element is unused and always returns zero.u32 %h1.u32 %h2.%ntid. Supported on all target architectures.

. read-only special register that returns the maximum number of warp identifiers. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. A predefined.u32 %nwarpid. %nwarpid.3. Supported on all target architectures.g. For this reason. read-only special register that returns the thread’s lane within the warp.3. Table 115. . Introduced in PTX ISA version 1. The warp identifier will be the same for all threads within a single warp. PTX ISA Notes Target ISA Notes Examples Table 116. . but its value may change during execution.u32 %r. January 24.u32 %warpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Introduced in PTX ISA version 1. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. read-only special register that returns the thread’s warp identifier. mov.sreg .u32 %r. Introduced in PTX ISA version 2. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. due to rescheduling of threads following preemption.u32 %laneid. e.sreg . %nwarpid requires sm_20 or later. Special Registers Table 114. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. mov. Note that %warpid is volatile and returns the location of a thread at the moment when read. %laneid.0. %warpid. 2010 151 . mov. Supported on all target architectures.Chapter 9. The lane identifier ranges from zero to WARP_SZ-1. A predefined.u32 %r.sreg . A predefined.

z.%nctaid.%ctaid.sreg .%nctaid. mov. 2010 . The fourth element is unused and always returns zero.u32 mov. The %ctaid special register contains a 1D.y. Redefined as .z. or 3D vector.0. .sreg .u32 type in PTX 2.u32 %ctaid. The fourth element is unused and always returns zero. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. %ctaid.x code Target ISA Notes Examples Table 118.u32 type in PTX 2.%nctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. It is guaranteed that: 1 <= %nctaid.0. Supported on all target architectures.{x.y < %nctaid. // legacy PTX 1. .z PTX ISA Notes Introduced in PTX ISA version 1.u32 %nctaid .PTX ISA Version 2. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u16 %r0. %ctaid.z < %nctaid. 2D.x.0.u32 mov. It is guaranteed that: 0 <= %ctaid.v4 . depending on the shape and rank of the CTA grid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.y.u16 %r0. %rh.y.x.536 PTX ISA Notes Introduced in PTX ISA version 1.x. with each element having a value of at least 1.x < %nctaid.x.v4. Supported on all target architectures.v4.0 Table 117. // legacy PTX 1.sreg .z} < 65. mov.y.x 0 <= %ctaid.y 0 <= %ctaid. %rh.0. // Grid shape vector // Grid dimensions A predefined. Redefined as . Each vector element value is >= 0 and < 65535.sreg .%ctaid.v4 . // CTA id vector // CTA id components A predefined. The %nctaid special register contains a 3D grid shape vector. read-only special register initialized with the number of CTAs in each grid dimension.x. .x code Target ISA Notes Examples 152 January 24.u32 %ctaid. read-only special register initialized with the CTA identifier within the CTA grid.%nctaid.u32 %nctaid.

The SM identifier numbering is not guaranteed to be contiguous. e. During execution. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Supported on all target architectures. 2010 153 .u32 %r. .0.u32 %r. PTX ISA Notes Target ISA Notes Examples Table 121. Introduced in PTX ISA version 1. Special Registers Table 119. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.g. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. A predefined. A predefined. due to rescheduling of threads following preemption. . The SM identifier numbering is not guaranteed to be contiguous. . %nsmid requires sm_20 or later. This variable provides the temporal grid launch number for this context. %smid. mov.Chapter 9.u32 %smid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. read-only special register that returns the maximum number of SM identifiers. repeated launches of programs may occur. %gridid. but its value may change during execution. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Introduced in PTX ISA version 2.u32 %gridid. so %nsmid may be larger than the physical number of SMs in the device. %nsmid. // initialized at grid launch A predefined.0.3. mov. Introduced in PTX ISA version 1.u32 %nsmid. where each launch starts a grid-of-CTAs. PTX ISA Notes Target ISA Notes Examples January 24. The SM identifier ranges from 0 to %nsmid-1.sreg . Note that %smid is volatile and returns the location of a thread at the moment when read. mov. Supported on all target architectures. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. read-only special register initialized with the per-grid temporal grid identifier.u32 %r.sreg .sreg .

u32 %lanemask_le.u32 %lanemask_lt.0 Table 122. %lanemask_lt.u32 %r.sreg . A predefined. Introduced in PTX ISA version 2. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Table 124.sreg . 2010 . .u32 %lanemask_eq. 154 January 24. mov.0.PTX ISA Version 2. Introduced in PTX ISA version 2. mov. A predefined. . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg . mov.u32 %r. %lanemask_le requires sm_20 or later. %lanemask_le. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.0. A predefined. %lanemask_lt requires sm_20 or later. %lanemask_eq requires sm_20 or later. Introduced in PTX ISA version 2.0.u32 %r. Table 123. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_eq.

%lanemask_ge. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. A predefined. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt requires sm_20 or later. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. mov.sreg . . 2010 155 . . Introduced in PTX ISA version 2.u32 %lanemask_ge. mov.Chapter 9. %lanemask_ge requires sm_20 or later.u32 %lanemask_gt.u32 %r. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg . Introduced in PTX ISA version 2. January 24.0. Table 126.0.u32 %r. Special Registers Table 125. %lanemask_gt.

Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm2. .%clock. …. Special Registers: %pm0. %pm1. Supported on all target architectures.0. Supported on all target architectures. %pm3 %pm0.3. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. mov. The lower 32-bits of %clock64 are identical to %clock. read-only 64-bit unsigned cycle counter. Table 128.sreg . %pm2. .u64 %clock64. %pm1.%clock64. 156 January 24. mov. 2010 . %pm1.0. Table 129.%pm0.u32 r1. Their behavior is currently undefined. and %pm3 are unsigned 32-bit read-only performance monitor counters. . %pm3. Introduced in PTX ISA version 1.u32 %clock. Introduced in PTX ISA version 1. read-only 32-bit unsigned cycle counter. Introduced in PTX ISA version 2.PTX ISA Version 2. Special registers %pm0.u64 r1. mov. %clock64 requires sm_20 or later.sreg . Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. %pm2. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.u32 %pm0.sreg .u32 r1.0 Table 127.

version 2.0. minor are integers Specifies the PTX language version number.version 1.version .version directive. and the target architecture for which the code was generated.version directives are allowed provided they match the original . PTX File Directives: . Each ptx file must begin with a . . Increments to the major number indicate incompatible changes to PTX. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.4 January 24.1.version directive. Directives 10.version .minor // major. 2010 157 .Chapter 10. . Duplicate . .version major.target Table 130.0 .version Syntax Description Semantics PTX version number. Supported on all target architectures. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.

A program with multiple . vote instructions. The following table summarizes the features in PTX that vary according to target architecture. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Adds {atom. Therefore. Introduced in PTX ISA version 1. PTX code generated for a given target can be run on later generation devices. Requires map_f64_to_f32 if any . Texturing mode: (default is . including expanded rounding modifiers.texmode_unified) .target Syntax Architecture and Platform target.f64 instructions used.version directive. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. sm_13. where each generation adds new features and retains all features of previous generations. sm_10.red}.texmode_independent texture and sampler information is bound together and accessed via a single .target . Description Specifies the set of features in the target architecture for which the current ptx code was generated. .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.f64 instructions used. but subsequent . with only half being used by instructions converted from .texmode_unified . Each PTX file must begin with a .f64 storage remains as 64-bits.target directives can be used to change the set of target features allowed during parsing. map_f64_to_f32 }.red}. texture and sampler information is referenced with independent .PTX ISA Version 2. Note that .0 Table 131. In general. Texturing mode introduced in PTX ISA version 1.samplerref descriptors. 158 January 24.global.red}. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. texmode_independent.global. sm_12. texmode_unified.f32. PTX features are checked against the specified target architecture. brkpt instructions. Adds {atom.0. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. A .f64 instructions used. Requires map_f64_to_f32 if any .texref descriptor. The texturing mode is specified for an entire module and cannot be changed within the module. 64-bit {atom.f64 to .target directive containing a target architecture and optional platform options.target directive specifies a single target architecture.5. Supported on all target architectures.shared. Target sm_20 Description Baseline feature set for sm_20 architecture. immediately followed by a . sm_11.texref and . 2010 . and an error is generated if an unsupported feature is used. PTX File Directives: . Requires map_f64_to_f32 if any . generations of SM architectures follow an “onion layer” model. Adds double-precision support.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Disallows use of map_f64_to_f32.

target sm_10 // baseline target architecture .target sm_13 // supports double-precision .target sm_20. texmode_independent January 24.Chapter 10. 2010 159 . Directives Examples .

texref.b32 x. 2010 .entry kernel-name ( param-list ) kernel-body .samplerref.b32 %r3. [y]. .func Table 132. opaque . Kernel and Function Directives: . e.entry Syntax Description Kernel entry point and body. %ntid.param { .entry cta_fft .param . Parameters may be referenced by name within the kernel body and loaded into registers using ld. the kernel dimensions and properties are established and made available via special registers.param . . Semantics Specify the entry point for a kernel program.param space memory and are listed within an optional parenthesized parameter list. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. parameter variables are declared in the kernel body.param instructions.0 through 1.param.g.entry .5 and later. and query instructions and cannot be accessed via ld. Parameters are passed via . PTX ISA Notes For PTX ISA version 1.param. At kernel launch. For PTX ISA versions 1. etc.b32 %r2. parameter variables are declared in the kernel parameter list. . 160 January 24.PTX ISA Version 2. Supported on all target architectures.0 through 1. store.entry . with optional parameters.b32 z ) Target ISA Notes Examples [x].reg .b32 y. In addition to normal parameters. ld.surfref variables may be passed as parameters.b32 %r1.2.param. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. and . [z]. … } . .entry kernel-name kernel-body Defines a kernel entry point name. parameters. ld.entry filter ( . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. These parameters can only be referenced by name within texture and surface load. . and body for the kernel function.4 and later. The shape and size of the CTA executing the kernel are available in special registers. .0 10.param instructions.3. ld.4. %nctaid.b32 %r<99>.

A .func (ret-param) fname (param-list) function-body Defines a function.func fname function-body . PTX ISA 2. . PTX 2.b32 rval) foo (.param state space. … use N.param instructions in the body. 2010 161 .func (. including input and return parameters and optional function body.2 for a description of variadic functions. } … call (fooval). The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.reg . val1). Parameters in . which may use a combination of registers and stack locations to pass parameters. Directives Table 133.func Syntax Function definition.func . and supports recursion. (val0.reg . Parameter passing is call-by-value. Variadic functions are currently unimplemented.param and st. foo. The implementation of parameter passing is left to the optimizing translator.func fname (param-list) function-body . other code. The parameter lists define locally-scoped variables in the function body. Parameters must be base types in either the register or parameter state space. .0 with target sm_20 supports at most one return value. ret.b32 rval. there is no stack.0. Release Notes For PTX ISA version 1.x code. Parameters in register state space may be referenced directly within instructions in the function body. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Variadic functions are represented using ellipsis following the last fixed argument.Chapter 10.f64 dbl) { .reg . Supported on all target architectures. implements an ABI with stack. Kernel and Function Directives: .reg .b32 N. mov.result. parameters must be in the register state space. . and recursion is illegal.func definition with no body provides a function prototype. if any.b32 localVar.0 with target sm_20 allows parameters in the . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. … Description // return value in fooval January 24.param space are accessed using ld. dbl.

for example.pragma directive is supported for passing information to the PTX backend.minnctapersm directives may be applied per-entry and must appear between an .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxntid directive specifies the maximum number of threads in a thread block (CTA).maxntid .pragma directives may appear at module (file) scope. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. The directives take precedence over any module-level constraints passed to the optimizing backend.PTX ISA Version 2. The .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). and the strings have no semantics within the PTX virtual machine model. 162 January 24. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. 2010 . registers) to increase total thread count and provide a greater opportunity to hide memory latency. and the .maxnreg. .entry directive and its body. Currently.maxntid. Note that .3. and .pragma The . . The interpretation of .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. to throttle the resource requirements (e. the . PTX supports the following directives. which pass information to the backend optimizing compiler. These can be used.minnctapersm . The directive passes a list of strings to the backend. at entry-scope. or as statements within a kernel or device function body. the .maxntid and .maxnctapersm (deprecated) . A general .maxnreg .0 10.g.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.

Chapter 10. Exceeding any of these limits results in a runtime error or kernel launch failure.16. ny.maxntid .maxntid nx.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.entry foo .maxntid 16. or the maximum number of registers may be further constrained by .maxntid 256 . Performance-Tuning Directives: .maxnreg .maxntid and . Supported on all target architectures. 2010 163 . Introduced in PTX ISA version 1. or 3D CTA. 2D. The maximum number of threads is the product of the maximum extent in each dimension. Introduced in PTX ISA version 1. Directives Table 134.entry bar .maxntid nx. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. nz Declare the maximum number of threads in the thread block (CTA).3. the backend may be able to compile to fewer registers.maxctapersm. The actual number of registers used may be less.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. Supported on all target architectures. for example.maxntid nx .maxnreg n Declare the maximum number of registers per thread in a CTA. . This maximum is specified by giving the maximum extent of each dimention of the 1D. ny . .entry foo . The compiler guarantees that this limit will not be exceeded.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid Syntax Maximum number of threads in thread block (CTA). Performance-Tuning Directives: .3. . .

.minnctapersm . Optimizations based on .entry foo . However. Performance-Tuning Directives: .maxntid 256 . Deprecated in PTX ISA version 2.maxnctapersm (deprecated) . .minnctapersm 4 { … } 164 January 24. The optimizing backend compiler uses . Optimizations based on .maxntid and .0.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. if the number of registers used by the backend is sufficiently lower than this bound.PTX ISA Version 2.entry foo . Supported on all target architectures. 2010 .0 as a replacement for . Performance-Tuning Directives: . Introduced in PTX ISA version 1.maxnctapersm.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. Supported on all target architectures.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. .maxnctapersm generally need .minnctapersm generally need . . additional CTAs may be mapped to a single multiprocessor. Introduced in PTX ISA version 2.3.0.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid to be specified as well.minnctapersm in PTX ISA version 2.maxnctapersm has been renamed to . .maxntid to be specified as well. For this reason.0 Table 136.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid 256 .

Introduced in PTX ISA version 2.pragma list-of-strings .0.Chapter 10.pragma “nounroll”. Pass module-scoped. The .pragma directive may occur at module-scope. See Appendix A for descriptions of the pragma strings defined in ptxas. . The interpretation of . .entry foo . at entry-scope. or statement-level directives to the PTX backend compiler. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma Syntax Description Pass directives to PTX backend compiler. Performance-Tuning Directives: . Supported on all target architectures. 2010 165 .pragma “nounroll”.pragma directive strings is implementation-specific and has no impact on PTX semantics. { … } January 24. entry-scoped. or at statementlevel.pragma . Directives Table 138.

0x00. 0x02. 0x6150736f.section .section directive is new in PTX ISA verison 2.4byte label .file .byte 0x00. 0x61395a5f.section . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x5f736f63 . 0x00 166 January 24. “”.4byte int32-list // comma-separated hexadecimal integers in range [0. Table 139.PTX ISA Version 2. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x00.loc The . 0x63613031.2.0.quad int64-list // comma-separated hexadecimal integers in range [0.byte 0x2b.section directive.0 but is supported for legacy PTX version 1. Deprecated as of PTX 2. replaced by . 0x736d6172 .x code. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF ..0 10. Supported on all target architectures.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. @@DWARF dwarf-string dwarf-string may have one of the .4byte . 0x00000364.0 and replaces the @@DWARF syntax. 0x00. Introduced in PTX ISA version 1.debug_pubnames.264-1] . 0x00.232-1] . 0x00 .4. 0x00. The @@DWARF syntax is deprecated as of PTX version 2.4byte 0x000006b5.debug_info .4byte 0x6e69616d.byte byte-list // comma-separated hexadecimal byte values . @progbits .. 2010 . 0x00.

b32 int32-list // comma-separated list of integers in range [0. 0x00 0x61395a5f.section section_name { dwarf-lines } dwarf-lines have the following formats: .0. Source file information.255] . 0x00.section . 0x00000364.debug_pubnames { . Source file location.b32 .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Supported on all target architectures.file . . 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x00. Debugging Directives: . Supported on all target architectures. 2010 167 .232-1] .section .Chapter 10.loc . 0x736d6172 0x00 Table 141. . 0x00..section Syntax PTX section definition. .loc line_number January 24. replaces @@DWARF syntax.b32 label .b32 0x000006b5. . Directives Table 140.0.b8 0x2b. 0x00. } 0x02... . Supported on all target architectures. 0x00.b32 0x6e69616d.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .b8 byte-list // comma-separated list of integers in range [0.b64 int64-list // comma-separated list of integers in range [0.b8 0x00.debug_info . Debugging Directives: .file filename Table 142. 0x5f736f63 0x6150736f.264-1] . . 0x63613031. Debugging Directives: .0.

0. Supported on all target architectures. . 2010 . // foo is defined in another module Table 144. . // foo will be externally visible 168 January 24.visible Table 143. . .visible .extern . Introduced in PTX ISA version 1.global .PTX ISA Version 2.extern .0.b32 foo.6. Introduced in PTX ISA version 1.0 10. Linking Directives: .extern identifier Declares identifier to be defined externally.global . Linking Directives: . Linking Directives . Supported on all target architectures.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible identifier Declares identifier to be externally visible.b32 foo.visible .extern .

0 CUDA 2. CUDA Release CUDA 1.0 CUDA 1.1 PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation. 2010 169 .5 PTX ISA 2.1 CUDA 2.0.2 PTX ISA 1. The release history is as follows.2 CUDA 2.1 CUDA 2.0 PTX ISA 1.4 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.Chapter 11.0 January 24. and the remaining sections provide a record of changes in previous releases.3 driver r190 CUDA 3.0 driver r195 PTX ISA Version PTX ISA 1.3 PTX ISA 1.

Changes in Version 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 for sm_20 targets. 2010 . and mul now support . The mad. while maximizing backward compatibility with legacy PTX 1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32 instruction also supports . Single. fma. The fma. When code compiled for sm_1x is executed on sm_20 devices.ftz modifier may be used to enforce backward compatibility with sm_1x. New Features 11. rcp.ftz and .and double-precision div.f32 maps to fma. • • • • • 170 January 24.rp rounding modifiers for sm_20 targets. A single-precision fused multiply-add (fma) instruction has been added. Floating-Point Extensions This section describes the floating-point changes in PTX 2. Both fma. Single-precision add. sub.f32 require a rounding modifier for sm_20 targets. and sqrt with IEEE 754 compliant rounding have been added.1. The .1.f32 and mad.f32 requires sm_20.sat modifiers.f32 for sm_20 targets.rm and .rn. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. These are indicated by the use of a rounding modifier and require sm_20.PTX ISA Version 2. The goal is to achieve IEEE 754 compliance wherever possible.0 11.1.x code and sm_1x targets.f32.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.1. The changes from PTX ISA 1.0 11.1. The mad. mad.1. Instructions testp and copysign have been added.

The bar instruction has been extended as follows: • • • A bar. and sust.shared have been extended to handle 64-bit data types for sm_20 targets. prefetch. A “population count” instruction. The . has been added.minnctapersm to better match its behavior and usage. Instructions {atom.u32 and bar. has been added. and shared addresses to generic address and vice-versa has been added. local. 11. has been added. has been added.or}.f32 have been implemented. ldu. bar now supports optional thread count and register operands. Surface instructions support additional . has been added. A new directive. %lanemask_{eq. clz. A “vote ballot” instruction.red.clamp modifiers. Instructions prefetch and prefetchu have also been added. for prefetching to specified level of memory hierarchy.red.ballot. Instructions {atom. bfind. New special registers %nsmid. Instruction sust now supports formatted surface stores.2. e. 2010 171 .lt. st. New instructions A “load uniform” instruction. have been added. Other new features Instructions ld.1. vote. January 24. popc.section. Instruction cvta for converting global.1. prefetchu. A “bit reversal” instruction. A system-level membar instruction.red}.arrive instruction has been added.Chapter 11. A “count leading zeros” instruction. suld. isspacep. and red now support generic addressing. has been added.ge.{and. atom. st. membar.clamp and . Instructions bar.3.add. Bit field extract and insert instructions.zero.popc. has been added. Release Notes 11. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.sys. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. %clock64.pred have been added. Cache operations have been added to instructions ld. brev.red}.maxnctapersm directive was deprecated and replaced with .g. cvta.le. A “find leading non-sign bit” instruction. .1. Video instructions (includes prmt) have been added. ldu.b32.1. bfe and bfi. .gt} have been added.

2.PTX ISA Version 2. Semantic Changes and Clarifications The errata in cvt. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.max} are not implemented.1. has been fixed. {atom. or . To maintain compatibility with legacy PTX code.p. cvt. the correct number is sixteen. See individual instruction descriptions for details.u32.p sust. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.ftz (and cvt for . .f32} atom.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.5. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. stack-based ABI is unimplemented. The underlying.1.f32. In PTX version 1. Instruction bra.s32. call suld. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.target sm_1x. 172 January 24.{u32. 11.5 and later. Formatted surface load is unimplemented.red}.f32 type is unimplemented.3.4 and earlier. Support for variadic functions and alloca are unimplemented. where . if .4 or earlier.version is 1. Formatted surface store with .{min.s32. Unimplemented Features Remaining The following table summarizes unimplemented instruction features. 2010 .0 11.ftz for PTX ISA versions 1.

Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Ignored for sm_1x targets. Note that in order to have the desired effect at statement level. L1_end: … } // do not unroll this loop January 24. and statement levels. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. Descriptions of . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. L1_body: … L1_continue: bra L1_head. 2010 173 .pragma “nounroll”. including loops preceding the . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. disables unrolling of0 the loop for which the current block is the loop header.entry foo (…) .func bar (…) { … L1_head: .pragma.pragma “nounroll”.0.Appendix A. .pragma strings defined by ptxas. Supported only for sm_20 targets. The “nounroll” pragma is allowed at module. disables unrolling for all loops in the entry function body.pragma Strings This section describes the . … @p bra L1_end. Table 145. . { … } // do not unroll any loop in this function .pragma “nounroll”. entry-function. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

PTX ISA Version 2.0 174 January 24. 2010 .

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