ptx_isa_2.0 | Thread (Computing) | Parallel Computing

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PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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.............. 28 Special Register State Space ................5..................................................................................................................................6........................................................... 44 Scalar Conversions ..... Chapter 6........ 37 Variable Declarations ............................. 41 Using Addresses............... 39 Parameterized Variable Names .. 43 Labels and Function Names as Operands ...................0 4............ Abstracting the ABI ............................................. 49 ii January 24........................... 33 5...........1... 5.......................... 41 6......1............... 6.......... Texture.. 44 Rounding Modifiers ......................................... 5...............................4....................6...................................................................................3.......... 27 5...3...............PTX ISA Version 2..................4.......1.................. 34 Variables ..1...............1.........................................................1.............................5...............................................2............. 6......2......... State Spaces ....................................... 42 Addresses as Operands ...................1.................................................................1..... 32 Texture State Space (deprecated) .................................................................1....................8...............................................5................................................................................................................ 28 Constant State Space ................................................................... 6................ 41 Destination Operands ....................................................2........................................................................ 5.............................3................... 37 Array Declarations ........................................... 5...................4......................... Arrays........ 29 Global State Space ......................4... 43 6......................... 6........4..............................3................1......................................................... 32 5..........................................4...............................2.... 6.............................................. 5............... 29 Local State Space ............... and Surface Types ......2.............................................................................. 5...................... 43 Vectors as Operands . 25 Chapter 5.......2...... Types....... 49 7......... Operand Costs ......... 5........... 46 6......................................... 38 Initializers ................... 41 Source Operands...........2................................................. 5............... 47 Chapter 7......................................... 38 Alignment ..........................6........................7....................................... State Spaces..............4................. Instruction Operands...................................................2...............................4.....4.............................................. Sampler...........................1.......... 5........................................... 5..4............1.............................. 6.......... 5....... 5..................6.........................4......................4...............5..... 29 Parameter State Space .. 33 Restricted Use of Sub-Word Sizes .............................................. Operand Type Information .........................1....... and Vectors .......................5...................... 42 Arrays as Operands ....3............................................. 5.............. Type Conversion.............................. 6.................... 5............ 5...............................................................................................1...................... 30 Shared State Space............... Function declarations and definitions ................. Types .....................5.................4....................... 5....... 2010 ........ 39 5..... 6...............................................1.................................... 27 Register State Space ........................4...... 37 Vectors ...... and Variables ........................... 33 Fundamental Types ...1. 6............. Summary of Constant Expression Evaluation Rules .............................................................................2.........................4........................

........................................... 55 PTX Instructions ..0 ...............3.........1.................................. 8.7..4.....8.. 63 Floating-Point Instructions ......................................... 8....6............................. 8. 157 Specifying Kernel Entry Points and Functions ... 81 Comparison and Selection Instructions ....... 11.............1.3..........................1..........1...7....................................3.............. Divergence of Threads in Control Constructs ..x . 62 Machine-Specific Semantics of 16-bit Code ... 8................ 149 Chapter 10................................................ PTX Version and Target Directives ..... Format and Semantics of Instruction Descriptions ................................... 8....................... 122 Control Flow Instructions .......2......................10........ 160 Performance-Tuning Directives ....................5..3...... 55 8..3.....................................1.....................2.. 8.............1............7....7...... 140 Miscellaneous Instructions..................... 57 Manipulating Predicates ..................... 157 10...........................4.. 10.......... 10..........6............7...................................... 8.. Special Registers ............................... 52 Variadic functions .......7................. 62 Semantics ................................. 8.............................................................................. 58 8..............................7.............................................. 62 8..................................2....................3............................................... 2010 iii ..................................... 53 Alloca ................................ Instruction Set ................................................................................................................................. 172 January 24......................................1............................... 54 Chapter 8...6.................................... 8..............1........7......................... Release Notes .............................................................7..........................1.......................................... 132 Video Instructions ..... Instructions .......................................................................................................7. 7................................................. 108 Texture and Surface Instructions ........ 129 Parallel Synchronization and Communication Instructions ............................................................................................................................................ 172 Unimplemented Features Remaining ................................................................ 7...................................................................................... 170 New Features .....................................................................................................................2........................................ 104 Data Movement and Conversion Instructions ....... 8. 169 11...................1...............................................4................................... 8....................................................................2...........................................................7............................................................................4........1.........................................3.................... 11... 8..................1......... 55 Predicated Execution ...................... 162 Debugging Directives ................ Changes from PTX 1..... 10.........7...2............ 56 Comparisons ................... 8..7... 11...................... 59 Operand Size Exceeding Instruction-Type Size .................................................................................................. 100 Logic and Shift Instructions ............................................... 8........... Chapter 9................5...........1. Directives ......................9....................... 10..... 60 8......................................... 63 Integer Arithmetic Instructions ....... 8................... 8...6........ 166 Linking Directives ......... Changes in Version 2........................... Type Information for Instructions and Operands .................. 147 8........................................................................................ 168 Chapter 11.. 170 Semantic Changes and Clarifications ........

......PTX ISA Version 2.... Descriptions of .................0 Appendix A. 173 iv January 24...................... 2010 ...........pragma Strings.......

........... Table 25........ 61 Integer Arithmetic Instructions: add ................................................................................... Table 28................. 68 Integer Arithmetic Instructions: mul24 .................... Table 12.... 58 Type Checking Rules ........................................................ 20 Operator Precedence .............................. 65 Integer Arithmetic Instructions: addc ...................... Table 27................ 25 State Spaces .................................................................................................................................................................... Table 15..... 27 Properties of State Spaces ............. Table 29..................... Table 26..................cc ................ 67 Integer Arithmetic Instructions: mad .......................................... 58 Floating-Point Comparison Operators Testing for NaN ........................................List of Tables Table 1...................................... Table 4.................................. Table 2. 60 Relaxed Type-checking Rules for Destination Operands.. Table 23.................................................... 19 Predefined Identifiers ....................................................................................... Table 3................. Table 16............... Table 21.................................... 64 Integer Arithmetic Instructions: sub .................... 33 Opaque Type Fields in Unified Texture Mode .......... 57 Floating-Point Comparison Operators ................. 35 Convert Instruction Precision and Format ........................................ Table 11.................... Table 13................ Table 30....... 2010 v ..........................................cc ......................... 59 Relaxed Type-checking Rules for Source Operands .......................................................................... and Bit-Size Types ....... Table 6........... 28 Fundamental Type Specifiers ....... 46 Cost Estimates for Accessing State-Spaces .............................. 57 Floating-Point Comparison Operators Accepting NaN .......................................................................................... PTX Directives ....................................................................................... 64 Integer Arithmetic Instructions: add.......... 69 Integer Arithmetic Instructions: mad24 ..................... Table 19................ 65 Integer Arithmetic Instructions: sub...... Table 7......................................................... Unsigned Integer........................................................ Table 31........ 35 Opaque Type Fields in Independent Texture Mode .......... 47 Operators for Signed Integer..................................................................... Table 18............................... 66 Integer Arithmetic Instructions: mul ......................... Table 14........... 18 Reserved Instruction Keywords .............. 70 Integer Arithmetic Instructions: sad ........ 66 Integer Arithmetic Instructions: subc ............ 46 Integer Rounding Modifiers ........ Table 10................... Table 8......................................................................................................... Table 5.. Table 9........................................ Table 20................................................................ Table 17.............. 23 Constant Expression Evaluation Rules ............... 45 Floating-Point Rounding Modifiers ....................................................................... 71 January 24............. Table 24................................................................................................................... Table 32....................................................... Table 22....................................................................................

PTX ISA Version 2............ 74 Integer Arithmetic Instructions: clz ............................. 94 Floating-Point Instructions: rsqrt .................................................................... 72 Integer Arithmetic Instructions: neg ................................. 71 Integer Arithmetic Instructions: abs ............ 102 Comparison and Selection Instructions: selp ....................................... Table 56......... 92 Floating-Point Instructions: max ........................ Table 34..................0 Table 33....................................... Table 43...... 95 Floating-Point Instructions: sin ................. Integer Arithmetic Instructions: div .............................. 72 Integer Arithmetic Instructions: min ........... 91 Floating-Point Instructions: neg ................................................................................................................. Table 67................................. Table 62.................................................................... Table 53............................................. Table 45.................................... 82 Floating-Point Instructions: testp .......................................... 88 Floating-Point Instructions: div ........................................ Table 69.... 85 Floating-Point Instructions: mul ......................... Table 39............................................ 103 vi January 24.............................. 74 Integer Arithmetic Instructions: bfind .......................... Table 51................................................. 75 Integer Arithmetic Instructions: brev ................................................................................................................................................................ 93 Floating-Point Instructions: sqrt .... Table 50...... 99 Comparison and Selection Instructions: set ........... Table 66................................................................................................................ Table 61........ 97 Floating-Point Instructions: lg2 ................................................................ 96 Floating-Point Instructions: cos ................................................................................... 71 Integer Arithmetic Instructions: rem .......... Table 37............................................................ 103 Comparison and Selection Instructions: slct .............. 83 Floating-Point Instructions: add ................................... Table 36........................................................................................................................................................................................................................ Table 57................................................................. 77 Integer Arithmetic Instructions: bfi .............. Table 48....................... Table 59.................................. 73 Integer Arithmetic Instructions: popc .............. Table 46............ Table 65............ Table 58......... Table 54................ Table 60............................................................ Table 47.. 2010 ............................................. 91 Floating-Point Instructions: min ............................... 73 Integer Arithmetic Instructions: max .. 76 Integer Arithmetic Instructions: bfe ......... Table 52............................................................. 84 Floating-Point Instructions: sub ....................... Table 63............. 83 Floating-Point Instructions: copysign ....... Table 55.................................................................... Table 40.............................. 87 Floating-Point Instructions: mad ............................... 101 Comparison and Selection Instructions: setp ............................................................................................. 90 Floating-Point Instructions: abs ................................................. Table 38............................................................................................. 98 Floating-Point Instructions: ex2 .. Table 49.......................................... 92 Floating-Point Instructions: rcp .. Table 44.................... 86 Floating-Point Instructions: fma ............................................................... 79 Summary of Floating-Point Instructions .......... Table 64.................. Table 68........................ Table 41...................................................................... Table 42......... Table 35................. 78 Integer Arithmetic Instructions: prmt ..................................

.......................... Table 72........................................................................ Table 97............... 105 Logic and Shift Instructions: xor ............. 119 Data Movement and Conversion Instructions: cvta ........................................... Table 88..................... 120 Texture and Surface Instructions: tex . 139 Video Instructions: vadd.................... 142 Video Instructions: vshl........................ 116 Data Movement and Conversion Instructions: prefetch.............. 127 Texture and Surface Instructions: suq ......... Table 84......... Table 91. Table 76.... Table 99.... 106 Logic and Shift Instructions: shl ........................................................ 129 Control Flow Instructions: bra ....................................................................................................................... Table 78........................ prefetchu ... 130 Control Flow Instructions: ret ...................................... 131 Parallel Synchronization and Communication Instructions: bar .......................................................... 107 Cache Operators for Memory Load Instructions ............... 118 Data Movement and Conversion Instructions: isspacep ......................... vmax .................... Table 104.......................................................................................... 106 Logic and Shift Instructions: cnot ..................................................................................................................................... 135 Parallel Synchronization and Communication Instructions: red ............ 133 Parallel Synchronization and Communication Instructions: membar ........... Table 105................................................. 109 Cache Operators for Memory Store Instructions ........................ Table 81................................................. Table 77.... vsub... Table 71.... Table 73................... 130 Control Flow Instructions: call ................. 129 Control Flow Instructions: @ ......................... vshr ...... Table 80.......... 111 Data Movement and Conversion Instructions: mov ..................................................................................................... 2010 vii ............ Table 101...... Table 79............................... 113 Data Movement and Conversion Instructions: ldu .... Table 98....... vmin... 126 Texture and Surface Instructions: sured.................................................... Table 90....... Table 102.................................................................................................... 128 Control Flow Instructions: { } . 123 Texture and Surface Instructions: txq ................ Table 106.Table 70..... 112 Data Movement and Conversion Instructions: ld ................ Table 85... 105 Logic and Shift Instructions: or ............... Table 87.............................................................................. 110 Data Movement and Conversion Instructions: mov ........................................... 134 Parallel Synchronization and Communication Instructions: atom ... 137 Parallel Synchronization and Communication Instructions: vote ..................... Table 100... 125 Texture and Surface Instructions: sust ............... 124 Texture and Surface Instructions: suld .................................. Table 74.................................................... Table 82......... 143 January 24........................................................ 107 Logic and Shift Instructions: shr .......................... Table 93....... Table 75.................................. Table 89.................. 106 Logic and Shift Instructions: not ... Table 83......................... vabsdiff................................................................... Logic and Shift Instructions: and ............... Table 94.............................. 119 Data Movement and Conversion Instructions: cvt ........................ Table 95.................................... 115 Data Movement and Conversion Instructions: st ........... 131 Control Flow Instructions: exit ............................. Table 92............................................ Table 86.......... Table 103............................................................. Table 96.....

.......................................................... 163 Performance-Tuning Directives: ........................ 147 Miscellaneous Instructions: pmevent..................................................maxntid ................................................................................................... 151 Special Registers: %warpid .................. Table 133...................................... Table 137.............................target ....................................................................................................version..................................................... 154 Special Registers: %lanemask_ge ............. Table 115............. 152 Special Registers: %nctaid ............................................0 Table 107.... 167 Debugging Directives: .. Table 129......... 147 Miscellaneous Instructions: brkpt ......... Table 142..................................... 154 Special Registers: %lanemask_lt ............. 151 Special Registers: %ctaid .... 158 Kernel and Function Directives: .... Table 143.. 156 Special Registers: %pm0........................ Table 136.............. 167 Debugging Directives: ..................................................maxnctapersm (deprecated) ......................... Table 109................ Table 132... Table 112................................. Table 119.... 152 Special Registers: %smid .............................. Table 108................................................................................................................ 166 Debugging Directives: .......... Table 141.............................................................................................. 167 Linking Directives: ........... 151 Special Registers: %nwarpid ....................................... Table 118.................... Table 113..................................... 147 Special Registers: %tid ............... Table 125.............................................. Table 131............PTX ISA Version 2................................................. Table 120.......loc .................................. 154 Special Registers: %lanemask_le ....................................... Table 135...... 155 Special Registers: %clock ................................................................. Table 114. Table 134..................................................................... 144 Video Instructions: vset.... 157 PTX File Directives: ................... Table 126.....................................................................entry........section ............... 155 Special Registers: %lanemask_gt ............................. 156 Special Registers: %clock64 ....... 168 viii January 24....................maxnreg ..................................... Table 130. Table 128...................................func .......... 153 Special Registers: %lanemask_eq ................................................................................ 150 Special Registers: %laneid ................................................file ..... 153 Special Registers: %nsmid ...................... 160 Kernel and Function Directives: .............................................................................. Table 117................. Table 140..................................... Table 116........................ 156 PTX File Directives: ....................... Table 138.......................... 163 Performance-Tuning Directives: .................................. 164 Performance-Tuning Directives: ....................... %pm1................................................................ 165 Debugging Directives: @@DWARF ......................................................................................... 153 Special Registers: %gridid ...........minnctapersm .... %pm3 ....................... 164 Performance-Tuning Directives: ........... 150 Special Registers: %ntid ......................................... Table 122... Table 121.............. Video Instructions: vmad ..................... %pm2................. Table 124.............................................. 2010 ................................................. Table 123.................... 146 Miscellaneous Instructions: trap ......... Table 110.................... Table 111....extern... Table 139................................................... 161 Performance-Tuning Directives: ..................... Table 127.......pragma .....................................................

.................. 2010 ix ...............Table 144..................................... Linking Directives: .. Table 145................... 168 Pragma Strings: “nounroll” .........visible................................................................. 173 January 24......

2010 .PTX ISA Version 2.0 x January 24.

from general signal processing or physics simulation to computational finance or computational biology. the memory access latency can be hidden with calculations instead of big data caches. In fact. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Because the same program is executed for each data element. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. multithreaded. PTX defines a virtual machine and ISA for general purpose parallel thread execution. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. image scaling. PTX exposes the GPU as a data-parallel computing device. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. Similarly. many-core processor with tremendous computational horsepower and very high memory bandwidth.Chapter 1. PTX programs are translated at install time to the target hardware instruction set. Introduction This document describes PTX. high-definition 3D graphics. 2010 1 . and pattern recognition can map image blocks and pixels to parallel processing threads. 1. 1. stereo vision. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). January 24. image and media processing applications such as post-processing of rendered images. Data-parallel processing maps data elements to parallel processing threads.1. which are optimized for and translated to native target-architecture instructions. Many applications that process large data sets can use a data-parallel programming model to speed up the computations.2. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. video encoding and decoding. the programmable GPU has evolved into a highly parallel. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. and because it is executed on many data elements and has high arithmetic intensity. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. there is a lower requirement for sophisticated flow control.

Provide a common source-level ISA for optimizing code generators and translators. Provide a machine-independent ISA for C/C++ and other compilers to target.0 is a superset of PTX 1. Improved Floating-Point Support A main area of change in PTX 2.ftz and . When code compiled for sm_1x is executed on sm_20 devices.x. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. Provide a code distribution ISA for application and middleware developers. Instructions marked with . and architecture tests. sub. A “flush-to-zero” (.x code will continue to run on sm_1x targets as well.ftz) modifier may be used to enforce backward compatibility with sm_1x. Facilitate hand-coding of libraries.0 is in improved support for the IEEE 754 floating-point standard. The changes from PTX ISA 1. addition of generic addressing to facilitate the use of general-purpose pointers.f32 instruction also supports . 1.0 PTX ISA Version 2. reduction. Both fma. and mul now support . memory. atomic.3. fma.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. which map PTX to specific target machines.f32 requires sm_20.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.x features are supported on the new sm_20 target. The main areas of change in PTX 2. performance kernels. • • • 2 January 24.f32 for sm_20 targets. Most of the new features require a sm_20 target. 1. The mad. PTX ISA Version 2. PTX 2.1.rp rounding modifiers for sm_20 targets.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. mad. surface.PTX ISA Version 2. Achieve performance in compiled applications comparable to native GPU performance.f32 and mad.rn.3. 2010 .f32 maps to fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.sat modifiers. The mad. including integer.f32. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. and the introduction of many new instructions. Single-precision add.f32 require a rounding modifier for sm_20 targets.0 are improved support for IEEE 754 floating-point operations. Legacy PTX 1. and video instructions.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. and all PTX 1.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.rm and . The fma. barrier. A single-precision fused multiply-add (fma) instruction has been added.

zero. and shared state spaces. and Application Binary Interface (ABI). and red now support generic addressing. and shared addresses to generic addresses. stack-based ABI.g. January 24..3. and shared addresses to generic address and vice-versa has been added. Instruction cvta for converting global. st. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. • Taken as a whole. 1.4.e. local. ldu. st. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. In PTX 2. Instructions prefetch and prefetchu have been added. prefetch. cvta. These are indicated by the use of a rounding modifier and require sm_20. New Instructions The following new instructions. NOTE: The current version of PTX does not implement the underlying. special registers. prefetchu.0. 2010 3 . these changes bring PTX 2. Instructions testp and copysign have been added. suld. 1.3. rcp. and vice versa. stack layout. Surface instructions support additional clamp modifiers.Chapter 1.0 closer to full compliance with the IEEE 754 standard. an address that is the same across all threads in a warp. Generic addressing unifies the global. Cache operations have been added to instructions ld.clamp and . local. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. isspacep. 1. Generic Addressing Another major change is the addition of generic addressing.0. and directives are introduced in PTX 2. atom. . A new cvta instruction has been added to convert global. e. and sust.3. PTX 2. so recursion is not yet supported. for prefetching to specified level of memory hierarchy.and double-precision div. Surface Instructions • • Instruction sust now supports formatted surface stores. allowing memory instructions to access these spaces without needing to specify the state space. local.2. Introduction • Single. i.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. and sqrt with IEEE 754 compliant rounding have been added. Support for an Application Binary Interface Rather than expose details of a particular calling convention.3. instructions ld.

A “vote ballot” instruction. has been added.gt} have been added. A bar.sys.shared have been extended to handle 64-bit data types for sm_20 targets.add. vote. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added.red}.{and.red}.red. Instructions {atom. . bar now supports an optional thread count and register operands. Instructions bar.u32 and bar.f32 have been added. %clock64.arrive instruction has been added.le.pred have been added. %lanemask_{eq. bfi bit field extract and insert popc clz Atomic. 2010 . Barrier Instructions • • A system-level membar instruction. Reduction.popc.lt. A new directive. membar. and Vote Instructions • • • New atomic and reduction instructions {atom.PTX ISA Version 2. New special registers %nsmid.ballot. Other Extensions • • • Video instructions (includes prmt) have been added. 4 January 24.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.section.red.b32.ge.or}.

types. Chapter 10 lists the assembly directives supported in PTX. Chapter 4 describes the basic syntax of the PTX language.0. Introduction 1. Chapter 11 provides release notes for PTX Version 2. Chapter 8 describes the instruction set. Chapter 9 lists special registers. Chapter 3 gives an overview of the PTX virtual machine model. and PTX support for abstracting the Application Binary Interface (ABI).4. Chapter 6 describes instruction operands. calling convention. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. and variable declarations.Chapter 1. Chapter 5 describes state spaces. January 24. Chapter 7 describes the function and call syntax. 2010 5 .

PTX ISA Version 2. 2010 .0 6 January 24.

and select work to perform. ntid. and tid.2. 2. or CTA. compute-intensive portions of applications running on the host are off-loaded onto the device.y.x. or 3D CTA. Threads within a CTA can communicate with each other.2. 2D. but independently on different data.y. More precisely. and ntid. The vector ntid specifies the number of threads in each CTA dimension. Programming Model 2. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. or 3D shape specified by a three-element vector ntid (with elements ntid.x. Cooperative thread arrays (CTAs) implement CUDA thread blocks. tid. It operates as a coprocessor to the main CPU. Each thread has a unique thread identifier within the CTA. To that effect. 2. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. (with elements tid. 2D.Chapter 2. Each CTA thread uses its thread identifier to determine its assigned role.z) that specifies the thread’s position within a 1D. To coordinate the communication of the threads within the CTA. Programs use a data parallel decomposition to partition inputs. Each CTA has a 1D. assign specific input and output positions. January 24.1. can be isolated into a kernel function that is executed on the GPU as many different threads. and results across the threads of the CTA. The thread identifier is a three-element vector tid. compute addresses. data-parallel. a portion of an application that is executed many times. one can specify synchronization points where threads wait until all threads in the CTA have arrived. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.z). 2010 7 . work. is an array of threads that execute a kernel concurrently or in parallel. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. or host: In other words.1. A cooperative thread array.

Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. a warp has 32 threads. 8 January 24. CTAs that execute the same kernel can be batched together into a grid of CTAs. Some applications may be able to maximize performance with knowledge of the warp size. This comes at the expense of reduced thread communication and synchronization. Threads within a warp are sequentially numbered. depending on the platform.2.PTX ISA Version 2. WARP_SZ. However. 2. and %gridid. multiple-thread) fashion in groups called warps. The warp size is a machine-dependent constant.0 Threads within a CTA execute in SIMT (single-instruction. 2D . Each grid also has a unique temporal grid identifier (gridid). The host issues a succession of kernel invocations to the device. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). because threads in different CTAs cannot communicate and synchronize with each other. 2010 . read-only special registers %tid. Multiple CTAs may execute concurrently and in parallel.2. %ntid. Typically. which may be used in any instruction where an immediate operand is allowed. Threads may read and use these values through predefined. such that the threads execute the same instructions at the same time. or 3D shape specified by the parameter nctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. or sequentially. %nctaid. so PTX includes a run-time immediate constant. so that the total number of threads that can be launched in a single kernel invocation is very large. A warp is a maximal subset of threads from a single CTA. Each grid of CTAs has a 1D. %ctaid.

2) Thread (2. 1) CTA (1. 1) Thread (4. 1) Thread (2. 0) Thread (4. 1) Thread (0. 1) Thread (0. 0) Thread (3. 2010 9 . Programming Model Host GPU Grid 1 Kernel 1 CTA (0. Figure 1. 1) Grid 2 Kernel 2 CTA (1. 0) CTA (1. 2) Thread (1. 0) CTA (2. Thread Batching January 24. 0) CTA (0. 2) Thread (4. 1) Thread (1. 0) Thread (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (2.Chapter 2. 0) Thread (0. 1) Thread (3. 1) CTA (2. A grid is a set of CTAs that execute independently. 2) Thread (3.

3. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. all threads have access to the same global memory. 10 January 24. Texture memory also offers different addressing modes. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. The device memory may be mapped and read or written by the host. The global. constant. for some specific data formats. Each thread has a private local memory.0 2. Finally. constant. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. Both the host and the device maintain their own local memory. or. as well as data filtering. and texture memory spaces are persistent across kernel launches by the same application. respectively. referred to as host memory and device memory. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. for more efficient transfer.PTX ISA Version 2. and texture memory spaces are optimized for different memory usages. 2010 .

1) Block (2.Chapter 2. 2010 11 . 2) Figure 2. 1) Grid 1 Global memory Block (0. 2) Block (1. 0) Block (0. 1) Block (0. 0) Block (1. 0) Block (2. 1) Block (1. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (1. 1) Block (1. Memory Hierarchy January 24.

PTX ISA Version 2.0 12 January 24. 2010 .

When a host program invokes a kernel grid. the threads converge back to the same execution path. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. increasing thread IDs with the first warp containing thread 0. so full efficiency is realized when all threads of a warp agree on their execution path. A multiprocessor consists of multiple Scalar Processor (SP) cores. and each scalar thread executes independently with its own instruction address and register state. and executes concurrent threads in hardware with zero scheduling overhead. The threads of a thread block execute concurrently on one multiprocessor. for example. the first parallel thread technology. If threads of a warp diverge via a data-dependent conditional branch. At every instruction issue time. When a multiprocessor is given one or more thread blocks to execute. and executes threads in groups of parallel threads called warps. the warp serially executes each branch path taken. schedules. 2010 13 .) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. each warp contains threads of consecutive. January 24. Parallel Thread Execution Machine Model 3. Branch divergence occurs only within a warp. and when all paths complete.1. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. manages. different warps execute independently regardless of whether they are executing common or disjointed code paths. multiple-thread). A warp executes one common instruction at a time. the multiprocessor employs a new architecture we call SIMT (single-instruction. and on-chip shared memory. To manage hundreds of threads running several different programs. a cell in a grid-based computation). it splits them into warps that get scheduled by the SIMT unit.Chapter 3. The multiprocessor creates. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). a multithreaded instruction unit. The way a block is split into warps is always the same. It implements a single-instruction barrier synchronization. manages. allowing. disabling threads that are not on that path. (This term originates from weaving. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. The multiprocessor SIMT unit creates. As thread blocks terminate. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. new blocks are launched on the vacated multiprocessors. a voxel in a volume. The multiprocessor maps each thread to one scalar processor core.

If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. Vector architectures. A multiprocessor can execute as many as eight thread blocks concurrently. modify. as well as data-parallel code for coordinated threads.PTX ISA Version 2. • The local and global memory spaces are read-write regions of device memory and are not cached. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. In practice. If there are not enough registers or shared memory available per multiprocessor to process at least one block. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space.0 SIMT architecture is akin to SIMD (Single Instruction. modifies. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. require the software to coalesce loads into vectors and manage divergence manually. but one of the writes is guaranteed to succeed. For the purposes of correctness. A key difference is that SIMD vector organizations expose the SIMD width to the software. but the order in which they occur is undefined. and writes to the same location in global memory for more than one of the threads of the warp. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. 14 January 24. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. write to that location occurs and they are all serialized. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. which is a read-only region of device memory. In contrast with SIMD vector machines. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. the programmer can essentially ignore the SIMT behavior. which is a read-only region of device memory. the kernel will fail to launch. As illustrated by Figure 3. the number of serialized writes that occur to that location and the order in which they occur is undefined. 2010 . however. whereas SIMT instructions specify the execution and branching behavior of a single thread. each read. scalar threads. on the other hand. If an atomic instruction executed by a warp reads. SIMT enables programmers to write thread-level parallel code for independent.

Figure 3. 2010 15 .Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.

PTX ISA Version 2.0 16 January 24. 2010 .

Lines beginning with # are preprocessor directives. whitespace is ignored except for its use in separating tokens in the language. #define. See Section 9 for a more information on these directives. January 24. Each PTX file must begin with a .2. #if.version directive specifying the PTX language version. The C preprocessor cpp may be used to process PTX source files. Comments Comments in PTX follow C/C++ syntax. 4. and using // to begin a comment that extends to the end of the current line. All whitespace characters are equivalent. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #ifdef. 2010 17 .1. #line. using non-nested /* and */ for comments that may span multiple lines. followed by a . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. The following are common preprocessor directives: #include. Source Format Source files are ASCII text. Comments in PTX are treated as whitespace.Chapter 4.target directive specifying the target architecture assumed. Lines are separated by the newline character (‘\n’). #endif. PTX is case sensitive and uses lowercase for keywords. Pseudo-operations specify symbol and addressing management. 4. #else. Syntax PTX programs are a collection of text source files.

ld.global .0 4. r1. %tid. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. written as @!p.entry .const .reg . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.3. 2. mov. The destination operand is first.PTX ISA Version 2.shared . Directive Statements Directive keywords begin with a dot. and is written as @p.b32 r1. address expressions.f32 r2.target . or label names.b32 r1.pragma .x.section . Statements A PTX statement is either a directive or an instruction.func . The guard predicate follows the optional label and precedes the opcode. so no conflict is possible with user-defined identifiers.3.param . r2. 18 January 24.tex .reg .3. followed by source operands.5.visible 4.align .minnctapersm . The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.global start: . array[r1]. r2. .loc . and terminated with a semicolon.maxntid . constant expressions.b32 r1.b32 add.sreg .local . Table 1. . 0.extern .maxnreg . Instructions have an optional guard predicate which controls conditional execution. The guard predicate may be optionally negated.1. Instruction keywords are listed in Table 2. Statements begin with an optional label and end with a semicolon. shl.2.global. Examples: . r2.file PTX Directives . Operands may be register variables. 2010 .f32 array[N].maxnctapersm . All instruction keywords are reserved tokens in PTX. where p is a predicate register.version .

abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. Syntax Table 2.Chapter 4. 2010 19 .

The percentage sign can be used to avoid name conflicts. underscore. …. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Table 3. or percentage character followed by one or more letters. dollar. digits. between user-defined variable names and compiler-generated names. listed in Table 3. %pm3 WARP_SZ 20 January 24. 2010 . underscore. PTX allows the percentage sign as the first character of an identifier. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.PTX ISA Version 2. or they start with an underscore. except that the percentage sign is not allowed. e. Many high-level languages such as C and C++ follow similar rules for identifier names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.g. PTX predefines one constant and a small number of special registers that begin with the percentage sign.0 4.4. digits. or dollar characters.

the constant begins with 0d or 0D followed by 16 hex digits.Chapter 4. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. When used in an instruction or data initialization.5.s64 or . i. octal. These constants may be used in data initialization and as operands to instructions. Floating-point literals may be written with an optional decimal point and an optional signed exponent. the constant begins with 0f or 0F followed by 8 hex digits. zero values are FALSE and non-zero values are TRUE. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. literals are always represented in 64-bit double-precision format.. Unlike C and C++. or binary notation.s64) unless the value cannot be fully represented in .e. Type checking rules remain the same for integer. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned.e. integer constants are allowed and are interpreted as in C. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. 4. Syntax 4. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.5. in which case the literal is unsigned (. Constants PTX supports integer and floating-point constants and constant expressions. To specify IEEE 754 single-precision floating point values. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. 2010 21 .2. the sm_1x and sm_20 targets have a WARP_SZ value of 32. floating-point. For predicate-type data and instructions. and bit-size types.u64). where the behavior of the operation depends on the operand types. every integer constant has type . Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.. To specify IEEE 754 doubleprecision floating point values. 0[fF]{hexdigit}{8} // single-precision floating point January 24.1. each integer constant is converted to the appropriate size based on the data or instruction type at its use.u64. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. The syntax follows that of C. 4.5.s64 or the unsigned suffix is specified. i. there is no suffix letter to specify size. Integer literals may be written in decimal. hexadecimal.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64 1st unchanged.u64 .f64 converted type constant literal + ! ~ Cast Binary (.u64 .s64.u64 . or . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .f64 converted type .f64 integer .f64 use usual conversions .u64.u64 .s64 . .s64 .u64) (.s64 .f64 use usual conversions .f64 same as source .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .Chapter 4.s64 .f64 integer integer integer integer integer int ?.s64 .5. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .s64 . Table 5.f64 : . Syntax 4.u64 .6.s64) + . 2010 25 . 2nd is .u64 .u64 same as 1st operand .f64 integer .s64 .f64 use usual conversions .

PTX ISA Version 2.0 26 January 24. 2010 .

Chapter 5. read-only memory. access speed. Global texture memory (deprecated). The characteristics of a state space include its size. State Spaces.sreg . Addressable memory shared between threads in 1 CTA. pre-defined. the kinds of resources will be common across platforms.shared . Global memory.param . 5. State Spaces A state space is a storage area with particular characteristics. All variables reside in some state space.1. defined per-grid. and these resources are abstracted in PTX through state spaces and data types. fast.local . platform-specific. access rights. and level of sharing between threads.reg . defined per-thread.const . Local memory.global . Name State Spaces Description Registers. The list of state spaces is shown in Table 4. private to each thread. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Table 6. and properties of state spaces are shown in Table 5. 2010 27 . addressability. or Function or local parameters. . Read-only. and Variables While the specific resources available in a given target GPU will vary. Kernel parameters. Special registers. Shared. shared by all threads.tex January 24. Types.

or as elements of vector tuples. The number of registers is limited. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).. 32-. Registers may be typed (signed integer. 28 January 24. and vector registers have a width of 16-. Registers may have alignment boundaries required by multi-word loads and stores.2. 1 Accessible only via the ld.param (used in functions) . and thread parameters. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.const . 64-. 2010 . via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .global . or 128-bits.e. Address may be taken via mov instruction. Register size is restricted.shared .1.param (as input to kernel) .PTX ISA Version 2. floating point. or 64-bits. 5. 2 Accessible via ld. Special Register State Space The special register (.0 Table 7. 3 Accessible only via the tex instruction.local state space.reg state space) are fast storage locations. All special registers are predefined. The most common use of 8-bit registers is with ld. For each architecture. CTA.param instructions. and will vary from platform to platform. st. the parameter is then located on the stack frame and its address is in the . predicate) or untyped. and cvt instructions. Registers differ from the other state spaces in that they are not fully addressable.1.sreg .param instruction. When the limit is exceeded. 32-.sreg) state space holds predefined. scalar registers have a width of 8-. it is not possible to refer to the address of a register. 16-. Device function input parameters may have their address taken via mov.tex Restricted Yes No3 5. aside from predicate registers which are 1-bit. i. clock counters. such as grid. register variables will be spilled to memory. Register State Space Registers (.param and st. causing changes in performance. platform-specific registers.local . and performance monitoring registers. unsigned integer.1.reg .

where the size is not known at compile time.b32 %r1. Local State Space The local state space (. 2010 29 . Consider the case where one thread executes the following two assignments: a = a + 1. For any thread in a context. All memory writes prior to the bar. Banks are specified using the . Use ld. It is the mechanism by which different CTAs and different grids can communicate. In implementations that support a stack.local to access local variables.const[2].global) state space is memory that is accessible by all threads in a context. For example. Sequential consistency is provided by the bar. each pointing to the start address of the specified constant bank.global to access global variables. 5. st. results in const_buffer pointing to the start of constant bank two. initialized by the host. for example). State Spaces.const[2] .sync instruction are guaranteed to be visible to any reads after the barrier instruction. bank zero is used. there are eleven 64KB banks.extern . ld.sync instruction. If no bank number is given.global.local and st.1.4. Use ld. Threads wait at the barrier until all threads in the CTA have arrived. the store operation updating a may still be in flight.Chapter 5. To access data in contant banks 1 through 10. It is typically standard memory with cache. and Variables 5. an incomplete array in bank 2 is accessed as follows: . [const_buffer+4]. If another thread sees the variable b change. Types.b32 const_buffer[]. By convention.local) is private memory for each thread to keep its own data. For the current devices. Constant State Space The constant (.const[2] . The remaining banks may be used to implement “incomplete” constant arrays (in C. // load second word 5. Module-scoped local memory variables are stored at fixed addresses.b32 const_buffer[]. This reiterates the kind of parallelism available in machines that run PTX. b = b – 1. as in lock-free and wait-free style programming. the declaration . The size is limited. Global State Space The global (. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.1. all addresses are in global memory are shared.const) state space is a read-only memory. as it must be allocated on a perthread basis.1. where bank ranges from 0 to 10. the stack is in local memory.extern . Multiple incomplete array variables declared in the same bank become aliases.5. This pointer can then be used to access the entire 64KB constant bank. Global memory is not sequentially consistent. bank zero is used for all statically-sized constant variables. For example. and atom.const[bank] modifier.3. Threads must be able to do their work without waiting for other threads to do theirs.global. The constant memory is organized into fixed size banks. whereas local memory variables declared January 24. the bank number must be provided in the state space of the load instruction.

param state space.b32 len ) { . %n.entry bar ( . per-kernel versus per-thread). These parameters are addressable.0 and requires target architecture sm_20. In implementations that do not support a stack. .6.1. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param space. (2a) to declare formal input and return parameters for device functions called from within kernel execution. Note that PTX ISA versions 1.reg .b32 N.reg . read-only variables declared in the .PTX ISA Version 2. PTX code should make no assumptions about the relative locations or ordering of .u32 %n.align 8 .param state space and is accessed using ld. No access protection is provided between parameter and global space in this case.f64 %d. The address of a kernel parameter may be moved into a register using the mov instruction. For example.u32 %n.b8 buffer[64] ) { .1. Values passed from the host to the kernel are accessed through these parameter variables using ld.u32 %n.entry foo ( . [N]. all local memory variables are stored at fixed addresses and recursive function calls are not supported. device function parameters were previously restricted to the register state space.0 within a function or kernel body are allocated on the stack.param instructions.param space variables. 5.param instructions.u32 %ptr. Parameter State Space The parameter (.6.param. Therefore. Similarly. [%ptr].1. . and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param . mov. typically for passing large structures by value to a function.param.param . ld. The use of parameter state space for device function parameters is new to PTX ISA version 2. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). The resulting address is in the . [buffer]. len.param. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. ld. 2010 .x supports only kernel function parameters in . ld. Example: .f64 %d. … 30 January 24.u32 %ptr. 5. Note: The location of parameter space is implementation specific. The kernel parameter variables are shared across all CTAs within a grid.param) state space is used (1) to pass input arguments from the host to the kernel.param . in some implementations kernel parameters reside in global memory. … Example: .reg .

x.f64 dbl. Function input parameters may be read via ld.reg . . it is illegal to write to an input parameter or read from a return parameter. State Spaces.f64 %d.s32 x. In PTX. . (4. such as C structures larger than 8 bytes. This will be passed by value to a callee. st.s32 %y.b8 buffer[12] ) { .6. which declares a .Chapter 5.local and st.s32 [mystruct+8]. ld.param . … } // code snippet from the caller // struct { double d.2.align 8 . In this case.param.param.f64 [mystruct+0]. int y. }.param space is also required whenever a formal parameter has its address taken within the called function. … st. Typically.align 8 . dbl.param byte array variable that represents a flattened C structure or union. and so the address will be in the . .local instructions. } mystruct. The most common use is for passing objects by value that do not fit within a PTX register. the caller will declare a locally-scoped . call foo.param and function return parameters may be written using st.reg .reg . is flattened. Aside from passing structures by value. Note that the parameter will be copied to the stack if necessary. Types. a byte array in parameter space is used. int y.s32 %y.reg . Device Function Parameters PTX ISA version 2.f64 %d.local state space and is accessed via ld.b8 mystruct. mystruct).param. passed to foo … . . Example: // pass object of type struct { double d.param . [buffer].b32 N.param space variable.1. [buffer+8].func foo ( . . January 24.param formal parameter having the same size and alignment as the passed argument. and Variables 5. .param. … See the section on function call syntax for more details.0 extends the use of parameter space to device function parameters. It is not possible to use mov to get the address of a return parameter or a locally-scoped .reg .param. 2010 31 . ld. the address of a function input parameter may be moved into a register using the mov instruction.

u32 .shared and st.tex variables are required to be defined in the global scope. Use ld. and programs should instead reference texture memory through variables of type .PTX ISA Version 2.global .1. Example: . The . An address in shared memory can be read and written by any thread in a CTA. Shared memory typically has some optimizations to support the sharing.tex state space are equivalent to module-scoped . tex_d. Shared State Space The shared (.u64.tex directive is retained for backward compatibility. a legacy PTX definitions such as .tex . tex_c.u32 or . and . Multiple names may be bound to the same physical texture identifier.u32 tex_a.texref.3 for the description of the . Texture State Space (deprecated) The texture (. Texture memory is read-only.7. where all threads read from the same address. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). tex_f.tex .8.u32 . The .tex . An error is generated if the maximum number of physical resources is exceeded. One example is broadcast. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. 5.shared) state space is a per-CTA region of memory for threads in a CTA to share data.texref tex_a.tex .tex) state space is global memory accessed via the texture instruction.7. Physical texture resources are allocated on a per-module granularity. See Section 5.shared to access shared variables. For example.tex directive will bind the named texture memory variable to a hardware texture identifier. and variables declared in the . The texture name must be of type . It is shared by all threads in a context. Another is sequential access from sequential threads. 32 January 24.u32 .global state space. tex_d. 2010 .1. where texture identifiers are allocated sequentially beginning with zero. is equivalent to .0 5.texref type and Section 8.u32 tex_a.tex .6 for its use in texture instructions.texref variables in the . A texture’s base address is assumed to be aligned to a 16-byte boundary.

All floating-point instructions operate only on . A fundamental type specifies both a basic type and a size. January 24. Two fundamental types are compatible if they have the same basic type and are the same size.b64 . .f16 floating-point type is allowed only in conversions to and from . . stored.u64 . and instructions operate on these types.s8. st.s32. so that narrow values may be loaded. Signed and unsigned integer types are compatible if they have the same size. needed to fully specify instruction behavior. Register variables are always of a fundamental type.f64 .s16. .f32 and .s8. Restricted Use of Sub-Word Sizes The .b8. .f16. or converted to other types and sizes.b8 instruction types are restricted to ld. all variables (aside from predicates) could be declared using only bit-size types. ld. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . and cvt instructions. .f64 types.Chapter 5.pred Most instructions have one or more type specifiers.u32.2.s64 . State Spaces. Types 5. In principle. . Fundamental Types In PTX. and . . 5.f32 and . The same typesize specifiers are used for both variable definitions and for typing instructions. For convenience.b32. . The following table lists the fundamental type specifiers for each basic type: Table 8. 2010 33 . .2. stored.u16.f64 types. . For example.b16. . . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. the fundamental types reflect the native data types supported by the target architectures. Operand types and sizes are checked against instruction types for compatibility. so their names are intentionally short. and Variables 5.u8.f32. and converted using regular-width registers. st. The .2. Types.u8. The bitsize type is compatible with any fundamental type having the same size.2.1. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. but typed variables enhance program readability and allow for better operand type checking.

i.u64} reg. since these properties are defined by . texture and sampler information each have their own handle. and overall size is hidden to a PTX program.surfref. field ordering.. texture and sampler information is accessed through a single . 2010 . accessing the pointer with ld and st instructions.{u32. Texture. The three built-in types are . and Surface Types PTX includes built-in “opaque” types for defining texture.samplerref variables. Creating pointers to opaque variables using mov. PTX has two modes of operation. samplers.texref type that describe sampler properties are ignored. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. In independent mode the fields of the . suld. store. hence the term “opaque”. the resulting pointer may be stored to and loaded from memory.texref. Referencing textures. .texref handle. These types have named fields similar to structures. and . suq). Sampler.samplerref. In the unified mode.3. base address. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. 34 January 24. or surfaces via texture and surface load/store instructions (tex.e. but the pointer cannot otherwise be treated as an address. For working with textures and samplers. sured). sampler.0 5. In the independent mode. sust. and de-referenced by texture and surface load. The following tables list the named members of each type for unified and independent texture modes. but all information about layout. allowing them to be defined separately and combined at the site of usage in the program. and query instructions. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. or performing pointer arithmetic will result in undefined results. Retrieving the value of a named member via query instructions (txq.PTX ISA Version 2. and surface descriptor variables. passed as a parameter to functions. opaque_var.

linear wrap. 1 nearest.Chapter 5. Member width height depth Opaque Type Fields in Independent Texture Mode . 1 ignored ignored ignored ignored . and Variables Table 9. mirror. clamp_to_border 0. mirror. linear wrap. clamp_to_edge.samplerref values N/A N/A N/A N/A nearest. Member width height depth Opaque Type Fields in Unified Texture Mode . Types.texref values .texref values in elements in elements in elements 0.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_ogl. clamp_to_border N/A N/A N/A N/A N/A .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. State Spaces. 2010 35 . clamp_ogl. clamp_to_edge.

surfref my_surface_name.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.PTX ISA Version 2. filter_mode = nearest }. the types may be initialized using a list of static expressions assigning values to the named members.samplerref my_sampler_name.global . When declared at module scope. As kernel parameters.global . these variables must be in the .texref tex1.global state space.samplerref tsamp1 = { addr_mode_0 = clamp_to_border. 2010 . .global . these variables are declared in the .param state space. At module scope. Example: . . 36 January 24.global . Example: .global . .texref my_texture_name.

b8 v.4.global .v4. . January 24. 1. its type and size. // a length-2 vector of unsigned ints . an optional array size. where the fourth element provides padding.1. 0.v1.global .0.global . . Vectors must be based on a fundamental type.struct float4 { .f64 is not allowed. . Vectors cannot exceed 128-bits in length.4. This is a common case for three-dimensional grids. 0}. and they may reside in the register space.4.u32 loc. and Variables 5. // a length-4 vector of floats .f32 V.2.v4. Predicate variables may only be declared in the register state space. vector variables are aligned to a multiple of their overall size (vector length times base-type size).v4 .global . for example.u8 bg[4] = {0.u16 uv.shared . and an optional fixed address for the variable. 0. Types.f32 v0. 5.f32 accel.pred p.v4 .v3 }. . . a variable declaration describes both the variable’s type and its state space.global . 5. Variable Declarations All storage for data is specified with variable declarations. A variable declaration names the space in which the variable resides.reg .0}. PTX supports types for simple aggregate objects such as vectors and arrays.v2 .v2.s32 i.v4 vector. Examples: . // a length-4 vector of bytes By default. .struct float4 coord. // typedef . to enable vector load and store instructions which require addresses aligned to a multiple of the access size.Chapter 5.v4 .v2 or . r. In addition to fundamental types. . 2010 37 .reg . an optional initializer. Variables In PTX. Vectors Limited-length vector types are supported. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . its name. Examples: . State Spaces. Three-element vectors may be handled by using a . Every variable must reside in one of the state spaces enumerated in the previous section. etc. textures.const .f32 bias[] = {-1. q.reg .

// address of rgba into ptr Currently. .05}}.f32 blur_kernel[][] = {{. or is left empty.0}.05. The size of the array specifies how many elements should be reserved.1.1}. -1}.0}.0.u8 mailbox[128].u64. Variables that hold addresses of variables or instructions should be of type . this can be used to initialize a jump table to be used with indirect branches or calls.0.pred.u32 or . {0. Examples: . The size of the dimension is either a constant expression.global .1.local . .PTX ISA Version 2. Array Declarations Array declarations are provided to allow the programmer to reserve space. where the variable name is followed by an equals sign and the initial value or values for the variable.shared .u8 rgba[3] = {{1. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. Similarly.{.b32 ptr = rgba. Here are some examples: .global . For the kernel declaration above.s32 offset[][] = { {-1. label names appearing in initializers represent the address of the next instruction following the label..global . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. 38 January 24.4.s32 n = 10.1. 0}.3. 0}. this can be used to statically initialize a pointer to a variable. Variable names appearing in initializers represent the address of the variable. 19*19 (361) halfwords are reserved (722 bytes). {1. {0..4.0. 5.1.f16 and . .{. {0.. 1} }.05.0 5. A scalar takes a single value.1.global .. 2010 . {0.0. .0}}. To declare an array. variable initialization is supported only for constant and global state spaces. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).4. Initializers are allowed for all types except .global ...4. being determined by an array initializer.05}.v4 .u16 kernel[19][19]. .

Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size.b32 %r<100>. The default alignment for vector variables is to a multiple of the overall vector size.6.5.2.. say one hundred. and Variables 5.Chapter 5.0. 2010 39 . Parameterized Variable Names Since PTX supports virtual registers.align byte-count specifier immediately following the state-space specifier.0}. …. and may be preceded by an alignment specifier.4. Array variables cannot be declared this way.reg .b32 variables. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. . Types. For example. it is quite common for a compiler frontend to generate a large number of register names.0. State Spaces.b8 bar[8] = {0. named %r0.. %r99.0.4. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Elements are bytes. %r1. For arrays. 5. These 100 register variables can be declared as follows: . Rather than require explicit declaration of every name. not for individual elements.const . . alignment specifies the address alignment for the starting address of the entire array. Examples: // allocate array at 4-byte aligned address. The variable will be aligned to an address which is an integer multiple of byte-count.. suppose a program uses a large number. %r1. nor are initializers permitted.0. // declare %r0.align 4 . January 24. The default alignment for scalar and array variables is to a multiple of the base-type size.0. of . Alignment is specified using an optional .

2010 .0 40 January 24.PTX ISA Version 2.

6. Operand Type Information All operands in instructions have a known type from their declarations. The ld. January 24. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. There is no automatic conversion between types. PTX describes a load-store machine. mov. 6. . and cvt instructions copy data from one location to another. st. Integer types of a common size are compatible with each other. For most operations. The bit-size type is compatible with every type having the same size.3. Instruction Operands 6. the sizes of the operands must be consistent. and a few instructions have additional predicate source operands.reg register state space. The cvt (convert) instruction takes a variety of operand types and sizes. Each operand type must be compatible with the type determined by the instruction template and instruction type. and c. Instructions ld and st move data from/to addressable state spaces to/from registers. 2010 41 . Most instructions have an optional predicate guard that controls conditional execution. s. so operands for ALU instructions must all be in variables declared in the . r. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. Source Operands The source operands are denoted in the instruction descriptions by the names a.2. The mov instruction copies data between registers. Predicate operands are denoted by the names p.1.Chapter 6. q. The result operand is a scalar or vector variable in the register state space. b. as its job is to convert from nearly any data type to any other data type (and size).

v4. r0. address register plus byte offset. The address is an offset in the state space in which the variable is declared. address registers.u16 ld.shared . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.4.f32 V. The mov instruction can be used to move the address of a variable into a pointer. .v4 .global . 6.f32 ld.shared. The interesting capabilities begin with addresses.reg .s32 mov.const . [V]. 2010 . arrays. [tbl+12]. .4. Arrays.reg . tbl. The syntax is similar to that used in many assembly languages. W.f32 W. . Here are a few examples: . and immediate address expressions which evaluate at compile-time to a constant address. and vectors. and Vectors Using scalar variables as operands is straightforward.reg .0 6.reg . ld. Using Addresses. Address expressions include variable names.[x]. there is no support for C-style pointer arithmetic.b32 p. .u16 x.const.gloal.u16 r0.1.PTX ISA Version 2.u32 42 January 24. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. q.v4 .s32 tbl[256]. Load and store operations move data between registers and locations in addressable state spaces. All addresses and address computations are byte-based. Examples include pointer arithmetic and pointer comparisons. .s32 q. p. .

r. 2010 43 .w = = = = V.reg .x V.4.global. Arrays as Operands Arrays of all types can be declared. and tex. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. [addr+offset].b and . Rc.reg .v4. mov.z V. Vector elements can be extracted from the vector with the suffixes .global. ld. Here are examples: ld.b V. mov.v2. Vector loads and stores can be used to implement wide loads and stores. Instruction Operands 6.y. V2.u32 s. Rb. a[0]. Examples are ld.c.x.f32 V.4. . and the identifier becomes an address constant in the space where the array is declared. Array elements can be accessed using an explicitly calculated byte address.f32 {a. which include mov.f32 a. Vectors as Operands Vector operands are supported by a limited subset of instructions. and in move instructions to get the address of the label or function into a register. a[1]. // move address of a[1] into s 6. it must be written as an address calculation prior to use. The expression within square brackets is either a constant integer. . say {Ra. Vectors may also be passed as arguments to called functions.v4 .u32 {a. b.c.global. ld.u32 s.global.b. Rd}.3.a 6.2.u32 s. [addr+offset2]. for use in an indirect branch or call. V. c. . or by indexing into the array using square-bracket notation.z and . or a simple “register with constant offset” expression.g V. If more complicated indexing is desired. where the offset is a constant expression that is either added or subtracted from a register variable.g. d. or a braceenclosed list of similarly typed scalars. .r V.y V. .w.b.Chapter 6. Elements in a brace-enclosed vector.d}. The size of the array is a constant in the program. January 24. The registers in the load/store operations can be a vector.f32 ld. A brace-enclosed list is used for pattern matching to pull apart vectors.v4. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.4.a.d}. . which may improve memory performance. a register variable. st. a[N-1].4. as well as the typical color fields .

Type Conversion All operands to all arithmetic.PTX ISA Version 2. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.000 for f16). Operands of different sizes or types must be converted prior to the operation. the u16 is zero-extended to s32.5.1.s32.5. if a cvt. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.u16 instruction is given a u16 source operand and s32 as a destination operand. and ~131. 44 January 24. For example. logic. 6. except for operations where changing the size and/or type is part of the definition of the instruction.0 6. and data movement instruction must be of the same type and size. 2010 .

then sign-extend to 32-bits. u2f = unsigned-to-float. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend.u32 targeting a 32-bit register will first chop to 16-bits. s2f = signed-to-float. Notes 1 If the destination register is wider than the destination format. 2010 45 . chop = keep only low bits that fit.s16. The type of extension (sign or zero) is based on the destination format. zext = zero-extend. For example. Instruction Operands Table 11. f2f = float-to-float. cvt.Chapter 6. January 24. f2u = float-to-unsigned. the result is extended to the destination register width after chopping. f2s = float-to-signed.

rni . The following tables summarize the rounding modifiers. In PTX.PTX ISA Version 2. choosing even integer if source is equidistant between two integers.rpi Integer Rounding Modifiers Description round to nearest integer.5.rm . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.0 6. there are four integer rounding modifiers and four floating-point rounding modifiers. Rounding Modifiers Conversion instructions may specify a rounding modifier.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rz . 2010 .rn . Modifier . Modifier . Table 12.rzi .rmi .2.

Operand Costs Operands from different state spaces affect the speed of an operation.6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. The register in a store operation is available much more quickly. first access is high Notes January 24. Table 11 gives estimates of the costs of using different kinds of memory.Chapter 6. while global memory is slowest. Registers are fastest. Another way to hide latency is to issue the load instructions as early as possible. Much of the delay to memory can be hidden in a number of ways. Instruction Operands 6. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Table 14. 2010 47 .

PTX ISA Version 2.0 48 January 24. 2010 .

parameter passing.func directive. Execution of the ret instruction within foo transfers control to the instruction following the call. function calls.Chapter 7. January 24.func foo { … ret. we describe the features of PTX needed to achieve this hiding of the ABI. 2010 49 . execution of the call instruction transfers control to foo. Scalar and vector base-type input and return parameters may be represented simply as register variables. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. } … call foo. At the call. arguments may be register variables or constants. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. The simplest function has no parameters or return values. In this section. NOTE: The current version of PTX does not implement the underlying. A function declaration specifies an optional list of return parameters. functions are declared and defined using the . Function declarations and definitions In PTX. so recursion is not yet supported.1. implicitly saving the return address. stack-based ABI. … Here. or prototype. stack layout. and is represented in PTX as follows: . 7. and Application Binary Interface (ABI). A function definition specifies both the interface and the body of the function. together these specify the function’s interface. and return values may be placed directly into register variables. These include syntax for function definitions. and memory allocated on the stack (“alloca”). A function must be declared or defined prior to being called. support for variadic functions (“varargs”). Abstracting the ABI Rather than expose details of a particular calling convention. the function name. and an optional list of input parameters.

[y+9].s32 x. a .param. }.reg .align 8 y[12]) { . [y+0].param state space is used to pass the structure by value: . [y+11].4). %rd. st.f64 field are aligned. [y+10]. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .c4. c3.b8 c1.b8 [py+ 9].s32 out) bar (. inc_ptr.param. [y+8].reg . note that .f1.b64 [py+ 0].param variable y is used in function definition bar to represent a formal parameter. (%x. %inc.param.func (. } … call (%r1).align 8 py[12]. c2.b8 [py+ 8].reg .b32 c1. %rc1. ld.b8 [py+11]. st.u32 %inc ) { add.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. c4.reg space. ret. ld. For example.b8 c2. ld. Second.param space variables are used in two ways.b8 c4. bumpptr.param . st. %rc2.param. char c[4].b8 . %rc1. %ptr. passed by value to a function: struct { double dbl.c3.param space memory. consider the following C structure.reg . … st.param. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .param. (%r1.b8 c3. First.f64 f1. In PTX.reg . py). this structure will be flattened into a byte array. st. .reg . byte array in .u32 %res. . … … // computation using x.0 Example: . … ld.f64 f1.param space call (%out). %rc2.param. 2010 .PTX ISA Version 2. a .reg .b8 . The . ld.b8 [py+10].param.c2. 50 January 24.param. .u32 %res) inc_ptr ( .c1.param.u32 %ptr. } { .func (. // scalar args in .param . … In this example. Since memory accesses are required to be aligned to a multiple of the access size.

reg space variable with matching type and size.param memory must be aligned to a multiple of 1. The . The following restrictions apply to parameter passing.Chapter 7. Note that the choice of ..reg variables.param state space is used to receive parameter values and/or pass return values back to the caller. For .reg state space in this way provides legacy support. • • • Input and return parameters may be .param or .g.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg or . the corresponding argument may be either a .param variables or .param variables. • • • For a callee. This enables backend optimization and ensures that the . In the case of . structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. or a constant that can be represented in the type of the formal parameter.reg space formal parameters. In the case of . 8.reg variables. 4. and alignment of parameters. size.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. or constants. or a constant that can be represented in the type of the formal parameter. • The .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. all st. . The . the corresponding argument may be either a .param or .reg space variable of matching type and size. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.param space byte array with matching type. Supporting the . • • Arguments may be . or 16 bytes. Abstracting the ABI The following is a conceptual way to think about the . For a caller. and alignment.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. For a callee.param state space use in device functions.reg state space can be used to receive and return base-type scalar and vector values.param and ld.param arguments. the argument must also be a . For a caller.param argument must be declared within the local scope of the caller.param instructions used for argument passing must be contained in the basic block with the call instruction.param space formal parameters that are byte arrays. 2010 51 . A .param byte array is used to collect together fields of a structure being passed by value. Typically. • The . In the case of . Parameters in . a . size.param space formal parameters that are base-type scalar or vector variables. January 24. 2.

PTX ISA Version 2.0 continues to support multiple return registers for sm_1x targets. and a .reg or . and .param space parameters support arrays.param byte array should be used to return objects that do not fit into a register. formal parameters may be in either .0. PTX 2.x In PTX ISA version 1.0 restricts functions to a single return value. For sm_2x targets. formal parameters were restricted to . PTX 2. In PTX ISA version 2.param state space.0 7. and there was no support for array parameters.1.x. PTX 1.reg state space. 52 January 24.x supports multiple return values for this purpose. Changes from PTX 1. 2010 . Objects such as C structures were flattened and passed or returned using multiple registers.1.

In PTX.reg . For %va_arg. iteratively access. . the size may be 1. Variadic functions NOTE: The current version of PTX does not support variadic functions.ge p. (ap. . .u32 b.reg .reg .s32 result ) maxN ( .reg .u32 N.pred p.. Once all arguments have been processed. 2. The function prototypes are defined as follows: . val. N.. %r1.u32 sz. 2.u32. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg . max. ctr. maxN. .func ( .reg .reg . %va_end is called to free the variable argument list handle. … %va_start returns Loop: @p Done: January 24. %s1.s32 val.b32 val) %va_arg (. result.Chapter 7. setp. %r2. 2.reg . ret. PTX provides a high-level mechanism similar to the one provided by the stdarg. Abstracting the ABI 7.reg . (2. In both cases. %va_arg.reg . (3.u32 ptr. %r3).func okay ( … ) Built-in functions are provided to initialize. 4.u32 ap. 0. .u32 a. call (ap). 0x8000000. // default to MININT mov.b32 ctr. .reg . … ) . the alignment may be 1. and end access to a list of variable arguments.func (.h headers in C.reg .func (. 8. 4. the size may be 1. . ctr. 2010 53 .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.h and varargs.s32 result.u32 align) .u32 ptr) %va_start . or 8 bytes.reg . or 4 bytes. maxN. variadic functions are declared with an ellipsis at the end of the input parameter list.reg . %s2).func baz ( . call (val). 4). mov. } … call (%max). … call (%max). following zero or more fixed parameters: .reg .func (.u32 sz. bra Loop. (ap).u32 align) .func %va_end (. %va_start. . To support functions with a variable number of arguments.u32 ptr.reg . call %va_end.2.reg . This handle is then passed to the %va_arg and %va_arg64 built-in functions. 4. or 16 bytes.b64 val) %va_arg64 (. ) { . along with the size and alignment of the next data value to be accessed.b32 result. for %va_arg64. bra Done.

it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.0 7.local instructions. The array is then accessed with ld. Alloca NOTE: The current version of PTX does not support alloca.u32 ptr ) %alloca ( . a function simply calls the built-in function %alloca.local and st.reg . defined as follows: .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.PTX ISA Version 2. 2010 . If a particular alignment is required. To allocate memory.3. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.func ( . 54 January 24.reg .

Format and Semantics of Instruction Descriptions This section describes each PTX instruction. A. 8.s32. opcode A. 2010 55 . a. A. A. while A. opcode D. setp. opcode D.1. opcode D. In addition to the name and the format of the instruction. q = !(a < b). C. For instructions that create a result value. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. b. the D operand is the destination operand.Chapter 8.2. the semantics are described. PTX Instructions PTX instructions generally have from zero to four operands. The setp instruction writes two destination registers. For some instructions the destination operand is optional. B. and C are the source operands. // p = (a < b). January 24. B. Instruction Set 8. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.lt p|q. B. We use a ‘|’ symbol to separate multiple destination registers. followed by some examples that attempt to show several possible instantiations of the instruction.

optionally negated. the following PTX instruction sequence might be used: @!p L1: setp. This can be written in PTX as @p setp. j. q. … // compare i to n // if false.3. branch over 56 January 24.pred as the type specifier. Predicated Execution In PTX. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.lt. As an example. use a predicate to control the execution of the branch or call instructions.0 8. add 1 to j To get a conditional branch or conditional function call.s32 j. where p is a predicate variable. add.lt. bra L1. To implement the above example as a true conditional branch. 2010 . // p = (i < n) // if i < n. 1. 1. n.s32 j. Instructions without a guard predicate are executed unconditionally. predicate registers are virtual and have . Predicates are most commonly set as the result of a comparison performed by the setp instruction. add. consider the high-level code if (i < n) j = j + 1.s32 p. j. n. i.PTX ISA Version 2. So.pred p. i.s32 p.reg . predicate registers can be declared as .

3. and ge (greater-than-or-equal). hi (higher). lt. gt (greater-than). The bit-size comparisons are eq and ne.3. If either operand is NaN. gt. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). Table 15. ls (lower-or-same). ordering comparisons are not defined for bit-size types. and hs (higher-or-same).Chapter 8. ne. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24.1. The following table shows the operators for signed integer. ne (not-equal). and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Instruction Set 8. Unsigned Integer. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.3. the result is false.2. ne.1. Comparisons 8. lo (lower). le. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq.1.1. unsigned integer. le (less-than-or-equal). ge. Table 16. The unsigned comparisons are eq. lt (less-than). and bitsize types. 2010 57 .

If both operands are numeric values (not NaN). two operators num (numeric) and nan (isNaN) are provided.u32 %r1. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. setp can be used to generate a predicate from an integer. and no direct way to load or store predicate register values. gtu. leu.3. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. Table 17. There is no direct conversion between predicates and integer values. However.0 To aid comparison operations in the presence of NaN values. and mov.1. then these comparisons have the same result as their ordered counterparts. not.%p. Table 18. geu. xor. neu.2. // convert predicate to 32-bit value 58 January 24. num returns true if both operands are numeric values (not NaN). unordered versions are included: equ. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.PTX ISA Version 2.0. ltu. 2010 . and nan returns true if either operand is NaN. If either operand is NaN. then the result of these comparisons is true. or. for example: selp.

reg . Example: . Floating-point types agree only if they have the same size.u16 d.u16 d. they must match exactly.fX ok ok ok ok January 24. add.f32.4. For example. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.uX ok ok ok inv . Table 19. and integer operands are silently cast to the instruction type if needed.reg . a.e.fX ok inv inv ok Instruction Type . Type Checking Rules Operand Type . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. b.sX . most notably the data conversion instruction cvt. a.sX ok ok ok inv . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. and these are placed in the same order as the operands.u16 a.bX . For example: . unsigned. 2010 59 . and this information must be specified as a suffix to the opcode.reg .u16 d. a. different sizes). an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. .bX .f32 d. It requires separate type-size modifiers for the result and source. For example. cvt.uX .. Instruction Set 8. i. Signed and unsigned integer types agree provided they have the same size. b. the add instruction requires type and size information to properly perform the addition operation (signed. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.Chapter 8. • The following table summarizes these type checking rules. float.

stored. or converted to other types and sizes. inv = invalid. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. unless the operand is of bit-size type. The following table summarizes the relaxed type-checking rules for source operands. 1. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Table 20. When used with a floating-point instruction type.1. so those rows are invalid for cvt. for example. the data will be truncated. When used with a narrower bit-size type.bX instruction types. Bit-size source registers may be used with any appropriately-sized instruction type. 2010 . The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. 2. st. floating-point instruction types still require that the operand type-size matches exactly. the size must match exactly. Note that some combinations may still be invalid for a particular instruction. so that narrow values may be loaded.4. Notes 3. 60 January 24. The data is truncated to the instruction-type size and interpreted according to the instruction type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Floating-point source registers can only be used with bit-size or floating-point instruction types. parse error.PTX ISA Version 2. 4. “-“ = allowed.0 8. Operand Size Exceeding Instruction-Type Size For convenience. the cvt instruction does not support . the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. When a source operand has a size that exceeds the instruction-type size. no conversion needed. and converted using regular-width registers. stored. ld. Source register size must be of equal or greater size than the instruction-type size. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. For example. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.

The data is sign-extended to the destination register width for signed integer instruction types. 2010 61 . Notes 3. the size must match exactly. Instruction Set When a destination operand has a size that exceeds the instruction-type size. The data is signextended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer. 2. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types.Chapter 8. and is zero-extended to the destination register width otherwise. the data is sign-extended. the destination data is zero. Table 21. the data will be zero-extended. Floating-point destination registers can only be used with bit-size or floating-point instruction types.or sign-extended to the size of the destination register. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. inv = Invalid. Bit-size destination registers may be used with any appropriately-sized instruction type. parse error. otherwise. The following table summarizes the relaxed type-checking rules for destination operands. When used with a narrower bit-size instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Destination register size must be of equal or greater size than the instruction-type size. 4. When used with a floatingpoint instruction type. “-“ = Allowed but no conversion needed. the data is zeroextended. January 24. zext = zero-extend. 1.

Divergence of Threads in Control Constructs Threads in a CTA execute together. by a right-shift instruction. until C is not expressive enough. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. the threads are called uniform. If threads execute down different control flow paths. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 2010 .1.6. and for many applications the difference in execution is preferable to limiting performance. the semantics of 16-bit instructions in PTX is machine-specific.5. For divergent control flow. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. for example. However.6. A compiler or programmer may chose to enforce portable. If all of the threads act in unison and follow a single control flow path. At the PTX language level.PTX ISA Version 2. at least in appearance. The semantics are described using C. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. When executing on a 32-bit data path. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path.uni suffix. the optimizing code generator automatically determines points of re-convergence. Therefore. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. Both situations occur often in programs. this is not desirable. the threads are called divergent. These extra precision bits can become visible at the application level. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. so it is important to have divergent threads re-converge as soon as possible. 8. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. and 16-bit computations are “promoted” to 32-bit computations. using the . conditional function call.0 8. for many performance-critical applications. a compiler or code author targeting PTX can ignore the issue of divergent threads. 62 January 24. or conditional return. 16-bit registers in PTX are mapped to 32-bit physical registers. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. 8. until they come to a conditional control construct such as a conditional branch.

Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. addc sub.Chapter 8. The Integer arithmetic instructions are: add sub add.cc. 2010 63 . In the following descriptions.1.cc. Instruction Set 8.7. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7. the optional guard predicate is omitted from the syntax. 8. Instructions All PTX instructions may be predicated.

s32 .s32. . add.sat applies only to . Supported on all target architectures. Saturation modifier: .sat. add Syntax Integer Arithmetic Instructions: add Add two values. add. . b.sat limits result to MININT. Introduced in PTX ISA version 1.0.type = { . .a. d. 2010 . .s32 c.s64 }. a.u64.sat applies only to . .s32 d.b.s32 . . b.s32 type.u16.type add{. Saturation modifier: . @p add.u32 x. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0. sub. a.PTX ISA Version 2. . a.z. sub. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.u32. PTX ISA Notes Target ISA Notes Examples 64 January 24. Applies only to . .sat}.s32 d.s32 c.1. Introduced in PTX ISA version 1..s32. d = a – b. d = a + b.type sub{. .sat}.s16.c.s32 type. Applies only to .MAXINT (no overflow) for the size of the operation.u16.y. b.u32.s64 }. Supported on all target architectures. // . b. a.MAXINT (no overflow) for the size of the operation.u64.sat limits result to MININT.. // . Description Semantics Notes Performs addition and writes the resulting value into a destination register.s16. PTX ISA Notes Target ISA Notes Examples Table 23. . d.0 Table 22.type = { .

cc.cc. . b. x4.cc. 2010 65 .cc. x4.cc.z4. . Instruction Set Instructions add. x2.z2.z2. or testing the condition code. and there is no support for setting. clearing. These instructions support extended-precision integer addition and subtraction. No saturation. d = a + b + CC.b32 addc.b32 addc.type = { .z1.b32 x1.type d.cc.cc specified. Introduced in PTX ISA version 1.cc}. a.cc.y1.b32 x1. .y2.z3.y4.cc Syntax Integer Arithmetic Instructions: add. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.type = {. .b32 addc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. add.y4. addc. No saturation. No other instructions access the condition code.z1. @p @p @p @p add.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.z3.b32 addc.cc.2. if . x2. carry-out written to CC. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.b32 addc. Table 24.CF No integer rounding modifiers.s32 }. addc{.cc. x3.cc Add two values with carry-out.s32 }. Behavior is the same for unsigned and signed integers.Chapter 8.y3. sub.u32. b. carry-out written to CC.CF) holding carry-in/carry-out or borrowin/borrow-out.cc. Supported on all target architectures. @p @p @p @p add.y1.b32 addc. Introduced in PTX ISA version 1. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.CF. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. Behavior is the same for unsigned and signed integers. x3.y2. d = a + b. Supported on all target architectures. add.type d.CF No integer rounding modifiers.u32.2. a.z4.y3.

cc. b. sub. Behavior is the same for unsigned and signed integers. Behavior is the same for unsigned and signed integers. x4.cc.cc.u32. with borrow-out. 2010 .cc.z3. Supported on all target architectures. x3.3.s32 }. withborrow-in and optional borrow-out. x4.y4. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. b. .b32 subc.type d.cc Syntax Integer Arithmetic Instructions: sub.z4.y3. .CF No integer rounding modifiers. subc{.b32 subc.y4.b32 subc.z1. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y2.u32. Introduced in PTX ISA version 1. borrow-out written to CC.0 Table 26.cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.type = { . x3. @p @p @p @p sub.y3.z4.b32 subc.z2.y1.(b + CC. Supported on all target architectures.z1.b32 x1. @p @p @p @p sub. if . No saturation. a.s32 }. x2.cc. d = a .cc. . x2. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.CF).PTX ISA Version 2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. d = a – b.type = {.cc specified.b32 subc. Introduced in PTX ISA version 1. a. sub.cc.type d.cc.z3. borrow-out written to CC.y1. No saturation.b32 x1.z2.cc Subract one value from another.cc}.CF No integer rounding modifiers.b32 subc. .y2.3.

wide}. n = bitwidth of type.u32.type d.type = { .wide // for .wide. mul.hi or . If .fys. . b.y. a.x. .n>. then d is twice as wide as a and b to receive the full result of the multiplication.0>. and either the upper or lower half of the result is written to the destination register.fxs.lo variant Notes The type of the operation represents the types of the a and b operands.wide.s16 fa. save only the low 16 bits // 32*32 bits. d = t<2n-1.hi variant // for .fys.and 32-bit integer types.u16.0.s16. // 16*16 bits yields 32 bits // 16*16 bits. The ..lo. .. t = a * b. mul. . .s32 z.s32. // for . . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.u64. mul. d = t<n-1. Instruction Set Table 28.Chapter 8. Description Semantics Compute the product of two values. d = t.wide suffix is supported only for 16.lo.s16 fa..wide is specified. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.fxs. creates 64 bit result January 24. If . then d is the same size as a and b.hi. 2010 67 ..lo is specified. Supported on all target architectures.s64 }. mul{.

type = { . b.s32 type in . // for .type mad. and then writes the resulting value into a destination register. mad{. Description Semantics Multiplies two values and adds a third. If .c.wide // for . t<n-1.MAXINT (no overflow) for the size of the operation. .lo is specified. then d and c are the same size as a and b.and 32-bit integer types.s32 d. b.wide}.lo.hi variant // for . .b.0. @p mad.lo variant Notes The type of the operation represents the types of the a and b operands.. 2010 . Applies only to .0> + c. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. mad. 68 January 24.PTX ISA Version 2.hi.u32.lo. d. Saturation modifier: . . c. a..s64 }. t<2n-1. t n d d d = = = = = a * b.hi mode.a.s32 d. .. If . . Supported on all target architectures.wide is specified. and either the upper or lower half of the result is written to the destination register. .0 Table 29.sat limits result to MININT.sat.. then d and c are twice as wide as a and b to receive the result of the multiplication.hi or .p.lo.n> + c.u16.. c. t + c.s32 r. bitwidth of type.q.wide suffix is supported only for 16. a.hi.r. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32.u64. The .s16.

PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d = t<47.0. . mul24. and return either the high or low 32-bits of the 48-bit result. // for . mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.a. t = a * b.16>. Supported on all target architectures.u32.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.hi. i. b.lo}.0>.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. 48bits..hi variant // for ..lo. 2010 69 . . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.s32 d.type d.. mul24.e. mul24{. // low 32-bits of 24x24-bit signed multiply.s32 }. January 24.Chapter 8. mul24. mul24. d = t<31.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. Instruction Set Table 30. All operands are of the same type and size.type = { . a.b.hi may be less efficient on machines without hardware support for 24-bit multiply.

u32. mad24{. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.16> + c.MAXINT (no overflow). d = t<31.0> + c.sat limits result of 32-bit signed addition to MININT.s32 type in . Applies only to . 32-bit value to either the high or low 32-bits of the 48-bit result..lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.hi variant // for .e. 70 January 24. mad24. Saturation modifier: .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. c. d = t<47.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.s32 d. and add a third..0 Table 31.hi. d.hi. All operands are of the same type and size. i. // low 32-bits of 24x24-bit signed multiply. . b. Description Compute the product of two 24-bit integer values held in 32-bit source registers.sat.type = { . mad24.s32 }.PTX ISA Version 2. t = a * b. mad24. Return either the high or low 32-bits of the 48-bit result. b.hi may be less efficient on machines without hardware support for 24-bit multiply.lo. c.a. 48bits.c.hi mode. 2010 .lo}. a. // for .. Supported on all target architectures.s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .type mad24. mad24..b.0. a.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b32.0.0 Table 39. 2010 .type = { . } Introduced in PTX ISA version 2.b64 }.u32 PTX ISA Notes Target ISA Notes Examples Table 40. d = 0. the number of leading zeros is between 0 and 64. a. X. . // cnt is .type = { . a = a << 1. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. . } while (d < max && (a&mask == 0) ) { d++. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. inclusively. a. mask = 0x8000000000000000. For . cnt.b32) { max = 32.type d. a = a >> 1. } else { max = 64.b32. popc. d = 0. inclusively.b64 }. while (a != 0) { if (a&0x1) d++. // cnt is . cnt. X. For .type == .b64 type. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. . if (. popc. a.b32 popc. mask = 0x80000000.type d. clz requires sm_20 or later. the number of leading zeros is between 0 and 32.PTX ISA Version 2. popc requires sm_20 or later.b64 d. a. clz.b64 d. clz.u32 Semantics 74 January 24.0. .b32 type. popc Syntax Integer Arithmetic Instructions: popc Population count.b32 clz.

u32 d. Operand a has the instruction type. i--) { if (a & (1<<i)) { d = i. a. bfind requires sm_20 or later. for (i=msb. i>=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. d = -1. Semantics msb = (.shiftamt is specified. .u32. bfind returns 0xFFFFFFFF if no non-sign bit is found.d.type = { .shiftamt. bfind. and operand d has type .type d. . bfind.u32 January 24. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. X. 2010 75 . bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.shiftamt. bfind.s32) ? 31 : 63.shiftamt && d != -1) { d = msb . break.type bfind.u32.Chapter 8. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. For signed integers.s64 }. If . // cnt is . a. bfind returns the bit position of the most significant “1”.u64. Instruction Set Table 41.0. a.type==. } } if (. For unsigned integers. .u32 || .type==.s64 cnt. .s32. d.

brev.b32. msb = (. for (i=0.PTX ISA Version 2. a.b32 d. a. brev requires sm_20 or later.b64 }. 76 January 24.b32) ? 31 : 63. Description Semantics Perform bitwise reversal of input. i++) { d[i] = a[msb-i]. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. . i<=msb.0 Table 42.type==. 2010 . .type = { . brev. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0.type d.

for (i=0. If the start position is beyond the msb of the input. .len. .s32. bfe.b32 d. else sbit = a[min(pos+len-1. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u64: .u32 || . b. bfe requires sm_20 or later. January 24.type==.type==. a.Chapter 8.u32 || . if (. d = 0. i<=msb. otherwise If the bit field length is zero.0.s32.u64. and source c gives the bit field length in bits.type = { . len = c. The destination d is padded with the sign bit of the extracted field.a. 2010 77 .u64 || len==0) sbit = 0.type==. Instruction Set Table 43.start. Semantics msb = (.type==.u32.s32) ? 31 : 63. bfe. the result is zero. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. Operands a and d have the same type as the instruction type.u32. the destination d is filled with the replicated sign bit of the extracted field. pos = b. The sign bit of the extracted field is defined as: .type d.u32. and operands b and c are type .msb)]. . Description Extract bit field from a and place the zero or sign-extended result in d. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. Source b gives the bit field starting bit position. . . .s64 }.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. c.

bfi requires sm_20 or later. c. Description Align and insert a bit field from a into b. and operands c and d are type .type = { . bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.0 Table 44. pos = c. f = b.b32.type==.b32) ? 31 : 63.b32 d. the result is b.PTX ISA Version 2.a. the result is b. len = d. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. and f have the same type as the instruction type. If the start position is beyond the msb of the input.len. 2010 . i<len && pos+i<=msb. d. and place the result in f. Semantics msb = (. bfi. for (i=0.b. b. If the bit field length is zero. Operands a. Source c gives the starting bit position for the insertion.start.0.type f.b64 }. . and source d gives the bit field length in bits. 78 January 24. bfi. i++) { f[pos+i] = a[i]. b. a.

b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. b0}}. a} = {{b7.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.Chapter 8. Thus.ecr.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. c. . Description Pick four arbitrary bytes from two 32-bit registers.b2 source select c[11:8] d. The msb defines if the byte value should be copied.mode = { .mode} d.f4e.rc16 }. msb=1 means replicate the sign. . The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.b1 source select c[7:4] d. b. default mode index d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.ecl. In the generic form (no mode specified). b6. 2010 79 . . Instruction Set Table 45. b5. b4}. For each byte in the target register. msb=0 means copy the literal value.rc8. The bytes in the two source registers are numbered from 0 to 7: {b. .b4e.b32{. . the permute control consists of four 4-bit selection values. b2. prmt. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. {b3.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. the four 4-bit values fully specify an arbitrary byte permute. as a 16b permute code. a 4-bit selection value is defined.b3 source select c[15:12] d. and reassemble them into a 32-bit destination register. . a. Note that the sign extension is only performed as part of generic form. b1.

r2.PTX ISA Version 2. tmp[15:08] = ReadByte( mode.0. tmp64 ). ctl[2]. r4.f4e r1. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[3]. r1. ctl[1]. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. 80 January 24.b32 prmt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[0].b32. prmt requires sm_20 or later. r2. r3. prmt. 2010 . tmp64 ). tmp64 ). tmp[31:24] = ReadByte( mode. tmp[23:16] = ReadByte( mode. ctl[3] = (c >> 12) & 0xf. } tmp[07:00] = ReadByte( mode. r3. r4. ctl[2] = (c >> 8) & 0xf. ctl[1] = (c >> 4) & 0xf.0 Semantics tmp64 = (b<<32) | a. tmp64 ).

Floating-Point Instructions Floating-point instructions operate on .7. Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .f64 register operands and constant immediate values.f32 and .2.Chapter 8.

rnd.sub.rcp.rcp. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.f32 . Instruction Summary of Floating-Point Instructions .approx.0 The following table summarizes floating-point instructions in PTX. but single-precision instructions return an unspecified NaN. sub.sqrt}.sqrt}. 1.0].mul}.rz .rm .target sm_20 .min.neg.rnd.approx.max}.target sm_1x No rounding modifier.f64 rsqrt. Table 46.rn and instructions may be folded into a multiply-add.neg.rnd. Double-precision instructions support subnormal inputs and results. NaN payloads are supported for double-precision instructions.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 rsqrt.fma}.f32 {mad.rnd. Note that future implementations may support NaN payloads for single-precision instructions. {mad.0.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.PTX ISA Version 2.mul}.f32 are the same.f64 div.f32 {abs. . default is . If no rounding modifier is specified. The optional .approx. No rounding modifier.ftz .f32 {add.lg2.approx.target sm_20 mad.32 and fma.f32 {div.rcp. mul.max}.rn and instructions may be folded into a multiply-add.full.ex2}.f64 {sin.f32 {div. so PTX programs should not rely on the specific single-precision NaNs being generated.fma}. and mad support saturation of results to the range [0. with NaNs being flushed to positive zero.rnd.sat Notes If no rounding modifier is specified.sub.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad. 82 January 24. .rnd.rn .cos. {add.f32 {div.sqrt}. Single-precision add.f64 mad.f64 {abs.rp . default is .f64 are the same. 2010 .min.f64 and fma.

infinite. . positive and negative zero are considered normal numbers. // result is . p. z.number testp. a.f32. . B.normal testp. .type = { .type d. Instruction Set Table 47. testp requires sm_20 or later. true if the input is a subnormal number (not NaN.infinite. y. January 24.finite testp. C. copysign.f32 testp. 2010 83 .f32 copysign.normal. copysign requires sm_20 or later. A.subnormal }.0. . and return the result as d.f32.op. not infinity).notanumber testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.f64 x. testp Syntax Floating-Point Instructions: testp Test floating-point property.f64 isnan. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. . testp.type = { .notanumber.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. not infinity) As a special case. . X. a.type . Table 48.finite. .notanumber. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.f64 }. testp. . .op p. Introduced in PTX ISA version 2.infinite testp. f0.pred = { .Chapter 8. b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0.number.f64 }. copysign. testp.

f64 d.sat.ftz}{. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.0 Table 49. . Rounding modifiers have the following target requirements: .f32 f1.rn.rz.rp for add.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1. NaN results are flushed to +0. Rounding modifiers (default is . subnormal numbers are supported.0f. b. 84 January 24.f64.f64 requires sm_13 or later. a. requires sm_20 Examples @p add.rnd}{.f32 clamps the result to [0.rnd = { .f32 supported on all target architectures. add. add.ftz. . .rz mantissa LSB rounds towards zero .0.rp }.f64 supports subnormal numbers.f3.f32 flushes subnormal inputs and results to sign-preserving zero.rm. .f32.0]. .rnd}.ftz. b. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 add{. In particular. requires sm_13 for add.rz available for all targets . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. .rn mantissa LSB rounds to nearest even .rn): .PTX ISA Version 2. add Syntax Floating-Point Instructions: add Add two values. add. add. a. Saturation modifier: . An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f32 flushes subnormal inputs and results to sign-preserving zero.rz.sat}.rm. 2010 . add.f2. sm_1x: add.0. add{. d = a + b.rn. d. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.

ftz. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rp for sub. sub. requires sm_13 for sub.f32.sat}.b.rp }.b.sat. sub.0. a.f32 c. subnormal numbers are supported.0f. Rounding modifiers have the following target requirements: .f32 sub{.rn. . b.ftz.f64 requires sm_13 or later.rn.rn): . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. .rm mantissa LSB rounds towards negative infinity .rm. sub{.rz. . .0].f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.rz available for all targets . sub.f32 f1. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sm_1x: sub. 2010 85 . In particular. d = a .f32 clamps the result to [0.rn.f3.f32 flushes subnormal inputs and results to sign-preserving zero.rm.rz mantissa LSB rounds towards zero .f64 d.f64.rnd}.rn mantissa LSB rounds to nearest even . sub Syntax Floating-Point Instructions: sub Subtract one value from another. d. January 24. b.f2. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. 1.a.rnd = { .0. Rounding modifiers (default is .rnd}{. sub.ftz}{. a. Saturation modifier: sub. Instruction Set Table 50. sub. requires sm_20 Examples sub. NaN results are flushed to +0.Chapter 8.f32 supported on all target architectures. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.

subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .0f.sat}.rn mantissa LSB rounds to nearest even .rp }.rz. Description Semantics Notes Compute the product of two values. 1.f64.rz available for all targets . a.rp for mul.radius. NaN results are flushed to +0. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz. For floating-point multiplication.rm. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.ftz}{.f32. .rm.f32 clamps the result to [0.f32 mul{. In particular.f64 d. .f32 flushes subnormal inputs and results to sign-preserving zero.ftz. mul{. requires sm_20 Examples mul. mul Syntax Floating-Point Instructions: mul Multiply two values. d = a * b. b.f64 requires sm_13 or later. Rounding modifiers (default is .rnd}{.sat. d.rn): . sm_1x: mul.0 Table 51.f32 flushes subnormal inputs and results to sign-preserving zero. . mul. mul. Rounding modifiers have the following target requirements: .f64 supports subnormal numbers.0.f32 supported on all target architectures. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 2010 .f32 circumf. requires sm_13 for mul.rnd = { .rn.rnd}. . mul. a. all operands must be the same size.0. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.pi // a single-precision multiply 86 January 24. .PTX ISA Version 2.0]. b.rz mantissa LSB rounds towards zero . mul.rm mantissa LSB rounds towards negative infinity .rn. Saturation modifier: mul.

fma.ftz. 2010 87 . again in infinite precision. fma. .rn.b.rnd{. fma.0].0f. .ftz}{. d = a*b + c. .rn. PTX ISA Notes Target ISA Notes Examples January 24.Chapter 8. c.f32 is unimplemented in sm_1x.rz mantissa LSB rounds towards zero .f32 fma.f64 supports subnormal numbers.0.rm mantissa LSB rounds towards negative infinity .a. Rounding modifiers (no default): . fma.f32 computes the product of a and b to infinite precision and then adds c to this product.4. fma. Saturation: fma.rnd = { . fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma.f32 introduced in PTX ISA version 2.f64 w. b.f64 is the same as mad. fma.ftz. fma.f64 introduced in PTX ISA version 1.f64 requires sm_13 or later.rn.f32 clamps the result to [0. The resulting value is then rounded to single precision using the rounding mode specified by . @p fma.z.rm. a. sm_1x: fma.x.rnd. a.f64 computes the product of a and b to infinite precision and then adds c to this product.y.rnd. . NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero.sat.f64.c. 1.rp }. Instruction Set Table 52.0.f32 fma. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat}. c.rnd.rn mantissa LSB rounds to nearest even . subnormal numbers are supported. b.rz. d. The resulting value is then rounded to double precision using the rounding mode specified by . again in infinite precision.f64 d. fma. fma.f32 requires sm_20 or later.

ftz.f64}. For . The resulting value is then rounded to double precision using the rounding mode specified by .0. mad. c.e.ftz}{.. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f32). In this case.rm. b. the treatment of subnormal inputs and output follows IEEE 754 standard.f64 supports subnormal numbers.f32 mad.f64 computes the product of a and b to infinite precision and then adds c to this product. sm_1x: mad.rnd = { . a. mad.rz. Unlike mad.ftz}{. a. but the exponent is preserved.rn mantissa LSB rounds to nearest even .sat. .f32 computes the product of a and b to infinite precision and then adds c to this product. Note that this is different from computing the product with mul.0.f32 flushes subnormal inputs and results to sign-preserving zero. // .f32 clamps the result to [0.f64} is the same as fma. mad. 1. .target sm_20: mad. fma. Rounding modifiers (no default): .0 Table 53. mad.f32 is identical to the result computed using separate mul and add instructions. c.rm mantissa LSB rounds towards negative infinity . a. subnormal numbers are supported.target sm_20 d. mad. and then the mantissa is truncated to 23 bits. b.f32 is when c = +/-0. The exception for mad. 88 January 24.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. b.rp }. d = a*b + c. mad.0f. 2010 . again in infinite precision.rnd. mad{. // .sat}.rnd. again in infinite precision. NaN results are flushed to +0.f32 mad. Saturation modifier: mad.sat}. c.f32 computes the product of a and b at double precision. again in infinite precision. Description Semantics Notes Multiplies two values and adds a third.f32. For .f32 flushes subnormal inputs and results to sign-preserving zero.target sm_1x d.f32 is implemented as a fused multiply-add (i.rnd.0 devices. and then writes the resulting value into a destination register.PTX ISA Version 2.target sm_13 and later .rz mantissa LSB rounds towards zero .{f32.f64. When JIT-compiled for SM 2.rn.f64 computes the product of a and b to infinite precision and then adds c to this product.0]. where the mantissa can be rounded and the exponent will be clamped. mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. . The resulting value is then rounded to single precision using the rounding mode specified by .rn.{f32. The resulting value is then rounded to double precision using the rounding mode specified by . // .ftz.rnd{.rnd.target sm_1x: mad.f64 is the same as fma. mad. mad.f64 d.

.f32.rn.f32 for sm_20 targets.rm..rp for mad.a. In PTX ISA versions 1.f32 d..f64 requires sm_13 or later.. requires sm_13 .Chapter 8. January 24..f32 supported on all target architectures. a rounding modifier is required for mad.0 and later. mad.f64. Target ISA Notes mad. 2010 89 . Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. Legacy mad. In PTX ISA versions 2.f64.f64 instructions having no rounding modifier will map to mad. requires sm_20 Examples @p mad.c.rp for mad.b.0.f64.rm.rz.rn.rn. Rounding modifiers have the following target requirements: .4 and later. a rounding modifier is required for mad..rz.

rnd = { .f32 supported on all target architectures. Description Semantics Notes Divides a by b.approx. .rz mantissa LSB rounds towards zero . .rm mantissa LSB rounds towards negative infinity . Subnormal inputs and results are flushed to sign-preserving zero. full-range approximation that scales operands to achieve better accuracy.ftz}.rm.3.circum.f32 div.0. div. For b in [2-126.f32 requires sm_20 or later.ftz}. yd. div.3. div. d. 2010 . stores result in d.{rz. For PTX ISA versions 1.rn.approx.f32 flushes subnormal inputs and results to sign-preserving zero. d. x.ftz. div. or .full. . zd. Target ISA Notes div. div Syntax Floating-Point Instructions: div Divide one value by another. Examples 90 January 24. sm_1x: div.ftz. div. b.f32 div.approx.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1. approximate division by zero creates a value of infinity (with same sign as a).full.ftz. y.f64. PTX ISA Notes div. computed as d = a * (1/b).rnd.f32 and div. a.full. subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 div.rp }.full. approximate single-precision divides: div.f32 and div.approx. and div. Fast.rnd is required. the maximum ulp error is 2. d.f64 requires sm_13 or later. xd. div. div.f64 diam.rp}. Fast.approx.PTX ISA Version 2. a. b.full.rz.ftz}. . z. div.f32 implements a relatively fast.approx{. div. // // // // fast.rn.rm.rnd.rnd{. but is not fully IEEE 754 compliant and does not support rounding modifiers.f64 defaults to div. d = a / b.f64 d.f32 implements a fast approximation to divide.f64 supports subnormal numbers. a.0 Table 54.f32 div. b. The maximum ulp error is 2 across the full range of inputs. and rounding introduced in PTX ISA version 1. Explicit modifiers .4.ftz. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . a.f32. one of . 2126]. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn. .full{.rn mantissa LSB rounds to nearest even . For PTX ISA version 1.4 and later.f64 requires sm_20 or later. b.f32 defaults to div.f32 div. .rn.approx.14159.f64 introduced in PTX ISA version 1.

f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a. abs{. subnormal numbers are supported. subnormal numbers are supported. d = -a.f32 abs. a.0.ftz. d = |a|. d. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. Subnormal numbers: sm_20: By default. abs. sm_1x: abs. abs.f64 requires sm_13 or later.f0.f32 flushes subnormal inputs and results to sign-preserving zero. neg{.ftz. neg. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 supports subnormal numbers. neg.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. neg. NaN inputs yield an unspecified NaN. neg.f32 x.ftz}. abs. Subnormal numbers: sm_20: By default.0.ftz.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero.f0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.Chapter 8. 2010 91 . Take the absolute value of a and store the result in d.f32 x. sm_1x: neg.f64 requires sm_13 or later. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. Negate the sign of a and store the result in d. abs. NaN inputs yield an unspecified NaN. January 24. neg. abs.ftz}.f64 supports subnormal numbers. Table 56. a. a. d.f64 d.f32 neg. Instruction Set Table 55.ftz.f32 supported on all target architectures. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.

max.f64 supports subnormal numbers. d.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero.f64 requires sm_13 or later.ftz.z. min.c.ftz}. d.PTX ISA Version 2.ftz. max{. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 min.f64 z.f32 flushes subnormal inputs and results to sign-preserving zero. max.f2. @p min.f32 max. min.f64 d.f32 min. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b. b. b.f32 max.0.b. a. b.0.f32 supported on all target architectures. min. max. a.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 flushes subnormal inputs and results to sign-preserving zero. b. Store the minimum of a and b in d. a. max. Table 58.c. a. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. d d d d = = = = NaN. max.f64 f0. sm_1x: max. min{. d d d d = = = = NaN.f64 requires sm_13 or later.ftz. (a < b) ? a : b. 2010 .f64 d.x. 92 January 24.0 Table 57. a. subnormal numbers are supported. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 supports subnormal numbers. subnormal numbers are supported. min. (a > b) ? a : b.b. a. Store the maximum of a and b in d. a.ftz.f1. b. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. sm_1x: min.

f32 flushes subnormal inputs and results to sign-preserving zero.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .approx or .x. rcp. For PTX ISA version 1.f32 requires sm_20 or later. a. sm_1x: rcp. rcp. d = 1 / a.f64 d.4 and later.0-2. one of .ftz.f64 supports subnormal numbers.Chapter 8.rz mantissa LSB rounds towards zero .f64 introduced in PTX ISA version 1. For PTX ISA versions 1.0 over the range 1.0.rz.rn. rcp.x.f32. xi. rcp. PTX ISA Notes rcp. . General rounding modifiers were added in PTX ISA version 2. rcp.rm.rn mantissa LSB rounds to nearest even .0 through 1.3. Description Semantics Notes Compute 1/a.f32 defaults to rcp.f64. subnormal numbers are supported. d. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.ftz}. rcp.4. . // fast.rm. rcp.r.rnd.f64 requires sm_20 or later. a. and rcp. rcp. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .f64 and explicit modifiers .rn.{rz.f32 implements a fast approximation to reciprocal.rn.0 -Inf -Inf +Inf +Inf +0.f32 rcp.rm mantissa LSB rounds towards negative infinity .ftz.approx.rn.approx.0 +0.f64 requires sm_13 or later.f32 supported on all target architectures. rcp.f32 rcp.f32 flushes subnormal inputs and results to sign-preserving zero. rcp.approx and . 2010 93 .rnd. d. Target ISA Notes rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0. Instruction Set Table 59.approx. store result in d.f32 and rcp.ftz.rn. a.0.approx.rp}. The maximum absolute error is 2-23.rp }.rn. Input -Inf -subnormal -0.f64 defaults to rcp. xi.ftz.ftz were introduced in PTX ISA version 1.f32 rcp. Examples January 24.rnd = { .ftz}.rnd is required.0 +subnormal +Inf NaN Result -0.f64 ri.approx{.f32 rcp. .rnd{.

2010 .f32 sqrt.rz. sqrt. For PTX ISA versions 1.f64 supports subnormal numbers.0 +0.ftz.f64 d.rn.approx and .f32 sqrt.rnd = { .ftz were introduced in PTX ISA version 1.rn. // fast.f32 requires sm_20 or later.0 through 1.rm.rnd. PTX ISA Notes sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.x. Target ISA Notes sqrt. sqrt. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.0. r.f64 and explicit modifiers . General rounding modifiers were added in PTX ISA version 2.{rz. . sqrt. // IEEE 754 compliant rounding .rnd is required. // IEEE 754 compliant rounding d.f64 defaults to sqrt.rm.f32 is TBD. sqrt.rnd{.4 and later.f64 requires sm_13 or later. a. a. .approx.f32 sqrt.ftz}. and sqrt.approx.approx{.rn.0 +subnormal +Inf NaN Result NaN NaN -0. Input -Inf -normal -subnormal -0.rn.rp}.PTX ISA Version 2. subnormal numbers are supported.ftz.f32 implements a fast approximation to square root.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.x. For PTX ISA version 1.x.approx.f64 r. sqrt. approximate square root d.ftz. store in d.0 +0.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .approx.rz mantissa LSB rounds towards zero . a. The maximum absolute error for sqrt. d = sqrt(a).rn.0.approx or .f32 sqrt. sqrt.f64.0 +0. Examples 94 January 24. sqrt.f32 and sqrt.rn mantissa LSB rounds to nearest even . sm_1x: sqrt.rp }. one of .rnd. sqrt.0 -0.f32 defaults to sqrt.ftz}.rm mantissa LSB rounds towards negative infinity .0 Table 60. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero. r. Description Semantics Notes Compute sqrt(a).approx.f32 supported on all target architectures.3. sqrt.f64 introduced in PTX ISA version 1.rn.f32.f64 requires sm_20 or later.4. .ftz.

4 over the range 1.f32 flushes subnormal inputs and results to sign-preserving zero.f64 isr. 2010 95 .f32 defaults to rsqrt. rsqrt.0. X. rsqrt. rsqrt.ftz.3. the .f32 rsqrt.ftz}.ftz were introduced in PTX ISA version 1. Instruction Set Table 61. subnormal numbers are supported.4. rsqrt.f32 supported on all target architectures.Chapter 8.f64 d. Subnormal numbers: sm_20: By default. The maximum absolute error for rsqrt. rsqrt.0 +0. Input -Inf -normal -subnormal -0.f32 is 2-22. a.0. d.f64 supports subnormal numbers.f32. ISR.f64 is emulated in software and are relatively slow. sm_1x: rsqrt.approx.approx{.approx implements an approximation to the reciprocal square root. PTX ISA Notes rsqrt.f64 were introduced in PTX ISA version 1.f64. Explicit modifiers . x.0 through 1.approx.approx. and rsqrt. Compute 1/sqrt(a). For PTX ISA versions 1.approx.f32 and rsqrt.f64 defaults to rsqrt.approx and .ftz. Note that rsqrt. store the result in d.approx modifier is required.f32 rsqrt.approx.4 and later. Target ISA Notes Examples rsqrt.ftz. rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. d = 1/sqrt(a). rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f64 requires sm_13 or later. January 24.0-4.f32 flushes subnormal inputs and results to sign-preserving zero.f64 is TBD. a. For PTX ISA version 1.0 NaN The maximum absolute error for rsqrt. rsqrt.approx.

9 in quadrant 00.0 +0. PTX ISA Notes sin.approx modifier is required.ftz.ftz.approx.f32 flushes subnormal inputs and results to sign-preserving zero.0 -0. subnormal numbers are supported.0 +0. 96 January 24.3.ftz introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default.0 Table 62.f32 implements a fast approximation to sine.PTX ISA Version 2.0 +subnormal +Inf NaN Result NaN -0.0 NaN NaN The maximum absolute error is 2-20.0 +0. Find the sine of the angle a (in radians). sin. Input -Inf -subnormal -0. a.0 through 1.0. For PTX ISA versions 1. sin.approx.f32 sa.f32 defaults to sin. a. For PTX ISA version 1.approx.ftz.approx and . Explicit modifiers . d = sin(a). sin. sin.ftz}.f32 d.f32. 2010 .f32 introduced in PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.4 and later. the . sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx{. Target ISA Notes Examples Supported on all target architectures. sin.4.

cos.0 +1. cos.approx.ftz.0.approx modifier is required. 2010 97 . a.Chapter 8. Find the cosine of the angle a (in radians). cos. Input -Inf -subnormal -0.f32 ca. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 through 1.f32 d. For PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.approx and .ftz. January 24.f32 defaults to cos. Target ISA Notes Examples Supported on all target architectures.f32 implements a fast approximation to cosine.0 +1.4 and later.3.ftz introduced in PTX ISA version 1.f32 introduced in PTX ISA version 1. Explicit modifiers .0 +subnormal +Inf NaN Result NaN +1.9 in quadrant 00.approx.approx.ftz}.approx{. a.0 +0.0 +1. d = cos(a). Subnormal numbers: sm_20: By default.ftz.f32.4. For PTX ISA versions 1. Instruction Set Table 63. cos. PTX ISA Notes cos. cos. the .f32 flushes subnormal inputs and results to sign-preserving zero.0 NaN NaN The maximum absolute error is 2-20. subnormal numbers are supported.

2010 .ftz. lg2.ftz.approx.approx modifier is required.approx{. lg2.f32 flushes subnormal inputs and results to sign-preserving zero.0 through 1. PTX ISA Notes lg2. d = log(a) / log(2).ftz introduced in PTX ISA version 1. lg2. a.approx.f32 la.ftz}. For PTX ISA version 1. a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.f32 Determine the log2 of a.f32 introduced in PTX ISA version 1.f32 defaults to lg2.approx and .0. subnormal numbers are supported. Input -Inf -subnormal -0.3.ftz. lg2. sm_1x: Subnormal inputs and results to sign-preserving zero.4.f32. For PTX ISA versions 1. The maximum absolute error is 2-22. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.0 Table 64.4 and later. lg2.f32 implements a fast approximation to log2(a). Target ISA Notes Examples Supported on all target architectures. Subnormal numbers: sm_20: By default.6 for mantissa.PTX ISA Version 2.0 +0. Explicit modifiers .approx. the . 98 January 24.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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le. {!}c.ftz}. subnormal numbers are supported.s32.type = { . . gtu. @q setp. ge. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Integer Notes Floating Point Notes The ordered comparisons are eq. The comparison operator is a suffix on the instruction. Applies to all numeric types. respectively. leu. To aid comparison operations in the presence of NaN values. the comparison operators lo. then these comparisons have the same result as their ordered counterparts.b. If either operand is NaN.PTX ISA Version 2. . gt.u64. This result is written to the first destination operand.u32. leu.f32 flushes subnormal inputs to sign-preserving zero.f32. gtu. . b.type . 102 January 24.b32.s64. ge. ls.f32 comparisons. lt.B) is one of: and. ne.s32 setp.u16.r. hi. the result is false. Semantics t = (a CmpOp b) ? 1 : 0. Subnormal numbers: sm_20: By default. p[|q]. sm_1x: setp. .CmpOp.dtype. gt.i. If both operands are numeric values (not NaN). num returns true if both operands are numeric values (not NaN). ls. lt. lt. A related value computed using the complement of the compare result is written to the second destination operand. b. and hs for lower. The signed and unsigned comparison operators are eq.s16.f64 supports subnormal numbers. ltu. The untyped.BoolOp{.f32 flushes subnormal inputs to sign-preserving zero. p = BoolOp(t. neu.and. num. geu. le. a. c). bit-size comparisons are eq and ne. q = BoolOp(!t. hs equ.u32 p|q.0. higher. ge. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. a.eq.pred variables. setp with . and (optionally) combine this result with a predicate value by applying a Boolean operator. The destinations p and q must be . . ne.n.ftz applies only to . and can be one of: eq. ne. setp.lt.f64 }. or.f64 source type requires sm_13 or later. . nan The Boolean operator BoolOp(A. .ftz. geu. setp.type setp. ltu. p[|q]. 2010 .dtype. gt. then the result of these comparisons is true. and nan returns true if either operand is NaN. Modifier . p. ge. .b64. hi. xor. le.0 Table 67. neu. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. c).b16. If either operand is NaN.dtype. and higher-or-same may be used instead of lt.CmpOp{. . le.ftz}. For unsigned values. loweror-same. lo. unordered versions are included: equ. . gt. setp.a.

If c is True.ftz.f64 requires sm_13 or later. b. a.p.f32 d. and b are treated as a bitsize type of the same width as the first instruction type.ftz.dtype = { . .f32 A. C. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .s16. a is stored in d.s32. . a.t. .dtype. c. b.s64. b otherwise. slct.u32. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. .s16.b64. and b must be of the same type.dtype.f32. val. For . Semantics Floating Point Notes January 24. slct. slct Syntax Comparison and Selection Instructions: slct Select one source operand.f64 }. subnormal numbers are supported. Description Conditional selection.s32 selp. . y.xp.s32. a.ftz applies only to . c. d.b16. Instruction Set Table 68. a.f32. . d = (c >= 0) ? a : b. Operands d. selp Syntax Comparison and Selection Instructions: selp Select between source operands.f32 flushes subnormal values of operand c to sign-preserving zero. the comparison is unordered and operand b is selected.u16. slct. operand c must match the second instruction type.x. . slct. sm_1x: slct. f0.u32. . based on the value of the predicate source operand. If c ≥ 0. z. Operand c is a predicate.b16.dtype.u64.b64. Table 69. based on the sign of the third operand. fval. . . B.r. The selected input is copied to the output without modification.u32.g.f64 }. . Operands d.0. . Introduced in PTX ISA version 1.type d. . .u64.f32 comparisons. Modifier . If operand c is NaN. . and operand a is selected. Subnormal numbers: sm_20: By default. . d = (c == 1) ? a : b. c. slct.u16.s32 x.type = { . otherwise b is stored in d. .s32 slct{. @q selp. selp.Chapter 8. . a is stored in d.s64. .ftz}. 2010 103 .dtype. a.f32 comparisons. selp. and operand a is selected.b32.f64 requires sm_13 or later.f32 r0.f32 flushes subnormal values of operand c to sign-preserving zero. . b. negative zero equals zero.b32.u64.0.

This permits bit-wise operations on floating point values without having to define a union to access the bits. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.0 8. Instructions and. provided the operands are of the same size. 2010 .PTX ISA Version 2. xor.7. or.4. and not also operate on predicates. performing bit-wise operations on operands of any type. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.

The size of the operands must match. or.0x80000000. sign. a. Supported on all target architectures.b32. Supported on all target architectures. or. b. and.r. .b32 mask mask.type = { . Introduced in PTX ISA version 1. Allowed types include predicate registers. .b32 and. Instruction Set Table 70. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.q. .fpvalue. Introduced in PTX ISA version 1. . but not necessarily the type.b64 }. d = a | b. and. d = a & b.pred.r.type d. January 24.b32. and Syntax Logic and Shift Instructions: and Bitwise AND. b. The size of the operands must match.pred. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. Allowed types include predicate registers. Table 71.pred p.Chapter 8.0.type = { .b64 }.q. 2010 105 . or Syntax Logic and Shift Instructions: or Bitwise OR.b16.0x00010001 or. but not necessarily the type.b16.0. .b32 x. a. . . .type d.

a. not. . a. d = ~a.type d. Introduced in PTX ISA version 1. . a. 2010 .b16. . one’s complement.b32.b64 }. The size of the operands must match.b32 mask. Allowed types include predicates. 106 January 24. Table 73.0. d = (a==0) ? 1 : 0. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. d = a ^ b.0.type = { . but not necessarily the type.mask. xor.b16. . Supported on all target architectures.type d.b64 }.0. not.x.type = { . .b32 d. Supported on all target architectures.PTX ISA Version 2. .b32.type d. Table 74. not.pred. Allowed types include predicate registers.b32.q. a. .b64 }. not Syntax Logic and Shift Instructions: not Bitwise negation.pred.q. The size of the operands must match. . . cnot. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1.0x0001.b16.pred p. but not necessarily the type. The size of the operands must match. Supported on all target architectures.b16 d.b32 xor. . . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. but not necessarily the type.r. cnot.0 Table 72.type = { . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). xor. d. b.

The sizes of the destination and first source operand must match. Supported on all target architectures. b.2.u32.b32.s64 }. regardless of the instruction type.b32 q. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.i. PTX ISA Notes Target ISA Notes Examples Table 76.a.b32.u16. . PTX ISA Notes Target ISA Notes Examples January 24.type d. sign or zero fill on left. regardless of the instruction type. The b operand must be a 32-bit value.b16 c.s16. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. .u64. b. Supported on all target architectures.j. shr. d = a >> b.u16 shr.b64 }. Instruction Set Table 75. shl Syntax Logic and Shift Instructions: shl Shift bits left. . .s32 shr. The b operand must be a 32-bit value. . . Signed shifts fill with the sign bit. . Shift amounts greater than the register width N are clamped to N.i. Introduced in PTX ISA version 1. .type d. shl.0. zero-fill on right.Chapter 8.a. but not necessarily the type. unsigned and untyped shifts fill with 0. d = a << b.2. k. shr Syntax Logic and Shift Instructions: shr Shift bits right. Bit-size types are included for symmetry with SHL.b16. a.type = { .b16. Introduced in PTX ISA version 1. but not necessarily the type. . Shift amounts greater than the register width N are clamped to N. shl.0. 2010 107 . .s32. The sizes of the destination and first source operand must match. shr.1. . .type = { . a.b64. i.

and sust support optional cache operations. local. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. ldu. 2010 . Data Movement and Conversion Instructions These instructions copy data from place to place.7. and from state space to state space. Instructions ld. prefetchu isspacep cvta cvt 108 January 24. st. or shared state spaces. mov. and st operate on both scalar and vector types. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. suld.PTX ISA Version 2.0 8.5. The cvta instruction converts addresses between generic and global. ld. possibly converting it from one format to another.

but multiple L1 caches are not coherent for global data.0 introduces optional cache operators on load and store instructions. A ld.lu instruction performs a load cached streaming operation (ld.lu Last use. it performs the ld. invalidates (discards) the local L1 line following the load. if the line is fully covered. . . when applied to a local address. likely to be accessed again. and a second thread loads that address via a second L1 cache with ld. . As a result of this request. January 24. Table 77. If one thread stores to global memory via one L1 cache. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. The ld. Cache Operators PTX 2.cg Cache at global level (cache in L2 and below.lu load last use operation. The compiler / programmer may use ld.ca.lu operation. The ld. The ld. the second thread may get stale L1 cache data.cs Cache streaming.Chapter 8.5. fetch again). the cache operators have the following definitions and behavior. and cache only in the L2 cache.cs) on global addresses. Instruction Set 8.ca. Operator .cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. When ld. to allow the thread program to poll a SysMem location written by the CPU.cg to cache loads only globally. bypassing the L1 cache.7.cs is applied to a Local window address.cv Cache as volatile (consider cached system memory lines stale.cv to a frame buffer DRAM address is the same as ld. Use ld. . For sm_20 and later.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.1.ca loads cached in L1. evict-first. not L1).cs. The default load instruction cache operation is ld. Global data is coherent at the L2 level. rather than the data stored by the first thread. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. any existing cache lines that match the requested address in L1 will be evicted. likely to be accessed once. 2010 109 . The cache operators require a target architecture of sm_20 or later. The ld.

wb could write-back global store data from L1.wt Cache write-through (to system memory). In sm_20.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cs Cache streaming. but st. bypassing its L1 cache.ca loads.wt store write-through operation applied to a global System Memory address writes through the L2 cache. rather than get the data from L2 or memory stored by the first thread. Operator . sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. in which case st. and discard any L1 lines that match. Use st. bypassing the L1 cache. .cg Cache at global level (cache in L2 and below. and cache only in the L2 cache. Global stores bypass L1. and a second thread in a different SM later loads from that address via a different L1 cache with ld. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.PTX ISA Version 2. regardless of the cache operation. st. The st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. The st. to allow a CPU program to poll a SysMem location written by the GPU with st. . not L1). If one thread stores to global memory. and marks local L1 lines evict-first. . 2010 .ca. 110 January 24. the second thread may get a hit on stale L1 cache data. which writes back cache lines of coherent cache levels with normal eviction policy. Addresses not in System Memory use normal write-back.wb.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.0 Table 78.wb for global data.cg is the same as st.cg to cache global store data only globally. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. likely to be accessed once.cg to local memory uses the L1 cache. The default store instruction cache operation is st. However. Future GPUs may have globally-coherent L1 caches.wt.

. label. local. 2010 111 . Semantics d = a. . mov. Write register d with the value of a. the parameter will be copied onto the stack and the address will be in the local state space. i.f32 mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.type mov. d = &label.u32 mov.u16.pred. or function name.u32 d. Introduced in PTX ISA version 1. or shared state space. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.b64. d = sreg.s16. a.u16 mov. A. Take the non-generic address of a variable in global. ..type d. special register. // get address of variable // get address of label or function .u64. ptr. mov. d. within the variable’s declared state space Notes Although only predicate and bit-size types are required.f64 }.1. Description .global.type mov.e.s64. mov.0.s32.b32. immediate. Operand a may be a register. . Instruction Set Table 79.. the generic address of a variable declared in global. myFunc. alternately. // address is non-generic.e.Chapter 8. For variables declared in . .type = { . .u32. d. d = &avar. mov places the non-generic address of the variable (i.f32. sreg. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. label.local. . variable in an addressable memory space. k.0. addr.const. or shared state space may be taken directly using the cvta instruction. local. . The generic address of a variable in global.b16. A[5].u32 mov. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. ptr. d. Note that if the address of a device function parameter is moved to a register. .shared state spaces. u. . .type mov. .a.f64 requires sm_13 or later.f32 mov. local. the address of the variable in its state space) into the destination register.v. and . avar.

b.31] } // unpack 16-bit elements from .z.b64 { d... a[8.y << 32) // pack two 8-bit elements into .g.x. a[16.b32 mov.b.%r1.7]. d.PTX ISA Version 2.z.y << 16) d = a. %r1.b16.. a[24... d.hi are .z. For bit-size types. .z.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b64 { d.b32 mov.. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). lo.. mov.b64 }.0.w } = { a[0.b}. d. {lo.b8 r.u8 // unpack 32-bit elements from . a[8. {r.z << 16) | (a.b32 // pack four 16-bit elements into .23]. d.b64 mov. d.b have type .w}. mov.w } = { a[0.x.y } = { a[0..y << 8) | (a.u32 x. a.15].31].type d. d.x | (a.u16 %x is a double.w have type .b64 112 January 24.31].b32 %r1.b16 // pack four 8-bit elements into .x.47].y << 16) | (a.x | (a. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.15].y. a[32.7].z << 32) | (a. // // // // a.x.y } = { a[0. a[16.15] } // unpack 8-bit elements from .{x. d.x | (a. a[16. .b64 // pack two 32-bit elements into . Semantics d = a.x. Supported on all target architectures. Description Write scalar register d with the packed value of vector register a.0 Table 80. a[32.31] } // unpack 8-bit elements from ..w << 48) d = a. d.b16 { d.type = { .63] } // unpack 16-bit elements from . . %x..y << 8) d = a.b32.b32 { d.x | (a.a}. a[48.w << 24) d = a. or write vector register d with the unpacked values from scalar register a.x | (a.y } = { a[0.hi}.b32 { d.y.. 2010 ..{a..15]..y. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.y.g.a have type .b32 // pack two 16-bit elements into . d.

32-bit).u8.reg state space.lu.global.b16. ld.u32.ca.f32 or . [a].volatile{. . ld. .s64. .s32.ss}. *(immAddr). Addresses are zero-extended to the specified width as needed.f64 }. perform the load using generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. 2010 113 . . . The address size may be either 32-bit or 64-bit. .vec.cop = { .0.volatile. ld introduced in PTX ISA version 1. an address maps to global memory unless it falls within the local memory window or the shared memory window.b32. an address maps to the corresponding location in local or shared memory. . . .cv }. for example. .local. i.1. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . [a].volatile introduced in PTX ISA version 1. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.shared }. the resulting behavior is undefined.ss}{. . .type d.volatile{.s16. . . Cache operations are not permitted with ld. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.volatile.v4 }. to enforce sequential consistency between threads accessing shared memory. If an address is not properly aligned. *a.const space suffix may have an optional bank number to indicate constant banks other than bank zero. *(a+immOff). . .0. .u64.b16.type = { .const. 32-bit).cop}. ld{.ss = { . Generic addressing and cache operations introduced in PTX ISA 2. . i. .b8. Description Load register variable d from the location specified by the source address operand a in specified state space. Instruction Set Table 81.type .cop}.e. The address must be naturally aligned to a multiple of the access size. . This may be used.f64 using cvt.vec = { .Chapter 8. or the instruction may fault.cg. . d.u16. the access may proceed by silently masking off low-order address bits to achieve proper rounding.ss}. In generic addressing.f16 data may be loaded using ld.f32. .ss}{. d. d. A destination register wider than the specified type may be used.e. The value loaded is sign-extended to the destination register width for signed integers. If no state space is given.volatile may be used with ..vec. and is zeroextended to the destination register width for unsigned and bit-size types.b64. [a].shared spaces to inhibit optimization of references to volatile memory. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. and then converted to . Semantics d d d d = = = = a. The . and truncated if the register width exceeds the state space address width for the target architecture.type ld{. [a].v2. PTX ISA Notes January 24.type ld.s8. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. Generic addressing may be used with ld. Within these windows. or [immAddr] an immediate absolute byte address (unsigned. . an integer or bit-size type register reg containing a byte address.global and .cs.param.

// access incomplete array x.[p+4].[p]. // immediate address %r.b32 ld.const[4].b32 ld. d. // load . x.s32 ld.local.0 Target ISA Notes ld.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.b32 ld.f64 requires sm_13 or later.global.[fs].[buffer+64].f16 d.PTX ISA Version 2. 2010 .[240]. Cache operations require sm_20 or later.local. Generic addressing requires sm_20 or later.[p+-8].[a]. // negative offset %r.b64 ld.b16 cvt.global.shared.%r. Q.f32.v4.f32 ld. ld.const. %r.

*(a+immOff). ldu.f32 Q. . Semantics d d d d = = = = a.type d. or the instruction may fault.s16.u32.s64. The address must be naturally aligned to a multiple of the access size.ss}. // state space . . . .f16 data may be loaded using ldu.f32 or . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.global }.ss}. The value loaded is sign-extended to the destination register width for signed integers.s8.type ldu{.u64. [areg] a register reg containing a byte address. i.v4 }. *a.vec = { .b16. only generic addresses that map to global memory are legal.ss = { . .e. // load from address // vec load from address .f32 d..global.b32 d.b8. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. the resulting behavior is undefined. The address size may be either 32-bit or 64-bit.b32. and truncated if the register width exceeds the state space address width for the target architecture. . where the address is guaranteed to be the same across all threads in the warp. In generic addressing. 32-bit). [a]. *(immAddr).type = { . ldu.vec.global.b16.reg state space.f64 requires sm_13 or later. Addresses are zero-extended to the specified width as needed.u16. .e. .v4. Within these windows. .[p].u8.[p+4]. A destination register wider than the specified type may be used. For ldu. an address maps to the corresponding location in local or shared memory. d.f64 }. . perform the load using generic addressing. i. The addressable operand a is one of: [avar] the name of an addressable variable var.global. or [immAddr] an immediate absolute byte address (unsigned. . PTX ISA Notes Target ISA Notes Examples January 24. . . If no state space is given. and is zeroextended to the destination register width for unsigned and bit-size types.b64. If an address is not properly aligned. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .[a]. A register containing an address may be declared as a bit-size type or integer type. .0. ldu. and then converted to . Introduced in PTX ISA version 2.f32.s32. .Chapter 8. an address maps to global memory unless it falls within the local memory window or the shared memory window. 32-bit). Instruction Set Table 82.f64 using cvt. [a]. 2010 115 . The data at the specified address must be read-only.v2. the access may proceed by silently masking off low-order address bits to achieve proper rounding. ldu. ldu{. . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.

the access may proceed by silently masking off low-order address bits to achieve proper rounding. an address maps to global memory unless it falls within the local memory window or the shared memory window. .b8.b16. Generic addressing requires sm_20 or later. b. . The address must be naturally aligned to a multiple of the access size. st{. and truncated if the register width exceeds the state space address width for the target architecture.u8. or the instruction may fault.shared }.local. 32-bit).wb.f64 requires sm_13 or later. . . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or [immAddr] an immediate absolute byte address (unsigned. .vec.volatile may be used with . { .cs. st. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.ss}. . .b16.e.cop}. *d = a. .volatile{. In generic addressing. Within these windows. The address size may be either 32-bit or 64-bit.vec. PTX ISA Notes Target ISA Notes 116 January 24. i.global.global and . st.ss}. i. to enforce sequential consistency between threads accessing shared memory.f32. an address maps to the corresponding location in local or shared memory.0.cg. 32-bit). // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .1. .volatile. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.type st{.ss}{.type [a].s16. . for example. This may be used. [a]. Cache operations require sm_20 or later.volatile{.cop . perform the store using generic addressing.ss}{. Generic addressing and cache operations introduced in PTX ISA 2. b.v4 }. .b64. .0 Table 83. If an address is not properly aligned. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. .volatile. { . b. . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.type .s8.s32. an integer or bit-size type register reg containing a byte address. the resulting behavior is undefined. .u32.u16.u64.wt }.volatile introduced in PTX ISA version 1. [a].s64.v2. The lower n bits corresponding to the instruction-type width are stored to memory. Generic addressing may be used with st. { . b.cop}.f64 }.e. [a]. st. .shared spaces to inhibit optimization of references to volatile memory. st introduced in PTX ISA version 1. .ss .type = = = = {.f16 data resulting from a cvt instruction may be stored using st. Addresses are zero-extended to the specified width as needed. Semantics d = a. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. 2010 .reg state space. Cache operations are not permitted with st.vec . A source register wider than the specified type may be used. .PTX ISA Version 2.b32. If no state space is given. *(immAddr) = a.type st..0. . *(d+immOffset) = a.

// %r is 32-bit register // store lower 16 bits January 24.global.local.a.b32 st.f32 st.b. [p]. [q+-8].%r.global.Q.s32 st.f16.a. // negative offset [100].%r.f32 st.s32 cvt.b16 [a]. 2010 117 .local.v4. [q+4].r7. Instruction Set Examples st.Chapter 8.local. // immediate address %r. [fs].b32 st.

a register reg containing a byte address. A prefetch to a shared memory location performs no operation.L1 [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. . Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.PTX ISA Version 2. prefetch and prefetchu require sm_20 or later. 2010 . Within these windows.space}. 32-bit).L1 [ptr].L2 }.level = { .space = { . If no state space is given.level prefetchu. [a].local }. .L1 [addr]. in specified state space. A prefetch into the uniform cache requires a generic address. prefetchu. prefetch. In generic addressing. Addresses are zero-extended to the specified width as needed. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. 32-bit). i.e. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.L1. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. 118 January 24. // prefetch to data cache // prefetch to uniform cache . or [immAddr] an immediate absolute byte address (unsigned. prefetch{.global. . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. and truncated if the register width exceeds the state space address width for the target architecture.global.0.0 Table 84. an address maps to the corresponding location in local or shared memory. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. and no operation occurs if the address maps to a local or shared memory location. the prefetch uses generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The address size may be either 32-bit or 64-bit.

. or shared address to a generic address.u32. A program may use isspacep to guard against such incorrect behavior.pred .size . Introduced in PTX ISA version 2. local. or shared state space.u32 to truncate or zero-extend addresses.u32 gptr.local isspacep. gptr.global.pred.genptr.space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.space = { . isspacep. or shared state space. local. // get generic address of svar cvta. January 24. cvta.shared }. Instruction Set Table 85. Take the generic address of a variable declared in global.shared. .shared isglbl. The source address operand must be a register of type . .space. cvta. . . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. a. // result is . local. or shared address cvta.u32 or .size cvta. PTX ISA Notes Target ISA Notes Examples Table 86.space = { . or vice-versa. or shared state space to generic. Description Convert a global.space. a. // local. Use cvt. or shared address. p.local. 2010 119 .size p.global. the generic address of the variable may be taken using cvta.global isspacep. isshrd. var. a.to. cvta requires sm_20 or later.space p. The source and destination addresses must be the same size.0. local.u32 p. cvta. // convert to generic address // get generic address of var // convert generic address to global. local. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.lptr.u64 or cvt.global. isspacep requires sm_20 or later.u64. svar.u64 }.size = { . The destination register must be of type . p. isspacep.Chapter 8. or vice-versa. When converting a generic address into a global. .local. sptr.local. lptr.u32 p.0. islcl.u32. For variables declared in global.to.shared }. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u64.

.atype cvt{. the . Description Semantics Integer Notes Convert between different types and sizes.sat}. .ftz. .f32. Integer rounding is illegal in all other instances.s16.ftz.u64. .sat}.sat For integer destination types. . .frnd = { .dtype.rz. Note that saturation applies to both signed and unsigned integer types.atype = { . i.frnd}{. Note: In PTX ISA versions 1. . 2010 .s8. Integer rounding is required for float-to-integer conversions.u8. 120 January 24. For float-to-integer conversions.e. d.rni round to nearest integer.rm.f16.f32 float-tofloat conversions with integer rounding.rzi round to nearest integer in the direction of zero .f32 float-to-integer conversions and cvt. ..irnd}{. subnormal inputs are flushed to signpreserving zero.f32 float-to-integer conversions and cvt. Saturation modifier: . . the result is clamped to the destination range by default.ftz. i.u16. .ftz.rpi }.s64.ftz}{.dtype = . .dtype.atype d.sat limits the result to MININT. subnormal numbers are supported.rzi.f64 }.u32.f32. d = convert(a).dtype. .f32.4 and earlier.MAXINT for the size of the operation.PTX ISA Version 2. . . and for same-size float-tofloat conversions where the value is rounded to an integer.rmi. // integer rounding // fp rounding . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. .sat is redundant. choosing even integer if source is equidistant between two integers. . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.dtype.rn. .ftz modifier may be specified in these cases for clarity. The compiler will preserve this behavior for legacy PTX code. a. Integer rounding modifiers: . cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rmi round to nearest integer in direction of negative infinity . cvt{. a.e.rni.f32 float-tofloat conversions with integer rounding.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.rp }. . The optional . sm_1x: For cvt.s32. .irnd = { . .ftz}{. For cvt.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.. . subnormal inputs are flushed to signpreserving zero.0 Table 87.

ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.y.f32. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.s32 f. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.rni.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).0].0. cvt.f32.version is 1. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64. 2010 121 . and for integer-to-float conversions.r.f32.rn mantissa LSB rounds to nearest even . subnormal numbers are supported.sat limits the result to the range [0.Chapter 8.ftz modifier may be specified in these cases for clarity. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .4 and earlier.f16. // note . // float-to-int saturates by default cvt.f32.f32 x.f32.f64 requires sm_13 or later. cvt to or from .rz mantissa LSB rounds towards zero .f32. The compiler will preserve this behavior for legacy PTX code.4 or earlier. Floating-point rounding modifiers: . cvt. Saturation modifier: .0.f32 instructions.f32 x. and cvt. Applies to .f16. .rm mantissa LSB rounds towards negative infinity . Modifier .ftz behavior for sm_1x targets January 24. result is fp cvt.f32. Subnormal numbers: sm_20: By default. 1.sat For floating-point destination types.y. The optional . The operands must be of the same size. if the PTX . . // round to nearest int. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.f64 types. stored in floating-point format. Floating-point rounding is illegal in all other instances.f64 j.s32. Specifically. Introduced in PTX ISA version 1. and .i. cvt. NaN results are flushed to positive zero. The result is an integral value. Note: In PTX ISA versions 1.f16.

The texturing mode is selected using .samplerref tsamp1 = { addr_mode_0 filter_mode }. r4.2d. r3. The advantage of unified mode is that it allows 128 samplers. Texturing modes For working with textures and samplers.b32 r6. [tex1].7.r3..u32 r5.r2. Module-scope and per-entry scope definitions of texture. PTX has two modes of operation.f32. sampler. // get tex1’s txq..target options ‘texmode_unified’ and ‘texmode_independent’. PTX supports the following operations on texture. In the independent mode. 122 January 24. cvt. A PTX module may declare only one texturing mode. r1.b32 r5.f32.global . sampler. = nearest width height tsamp1. and surface descriptors. r1. r5. . add.param . 2010 . with the restriction that they correspond 1-to-1 with the 128 possible textures.6. r5. r5.f2}]. If no texturing mode is declared. texture and sampler information is accessed through a single .v4. and surface descriptors.texref handle.height. but the number of samplers is greatly restricted to 16. sampler. sampler.f32 r1.width. The advantage of independent mode is that textures and samplers can be mixed and matched.0 8. the file is assumed to use unified mode. // get tex1’s tex. add. In the unified mode. and surfaces. [tex1]. {f1. samplers.f32 r1.entry compute_power ( . mul. and surface descriptors. add. and surface descriptors: • • • Static initialization of texture. . .f32 r3. r2.target texmode_independent . r1. [tex1. div. texture and sampler information each have their own handle.f32 {r1. r6.PTX ISA Version 2. allowing them to be defined separately and combined at the site of usage in the program.u32 r5. r3. Texture and Surface Instructions This section describes PTX instructions for accessing textures.r4}.f32 r1. Ability to query fields within texture. } = clamp_to_border. Example: calculate an element’s power contribution as element’s power/total number of elements.texref tex1 ) { txq.

e.f32 }. // explicit sampler .1d.v4. Operand c is a scalar or singleton tuple for 1d textures. [a.btype tex. If no sampler is specified. .. An optional texture sampler b may be specified. [a. with the extra elements being ignored.s32.f4}].btype d. Instruction Set These instructions provide access to texture and surface memory. tex.r3. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.0. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. [tex_a.v4.v4 coordinate vectors are allowed for any geometry. tex txq suld sust sured suq Table 88.btype = { .r2. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. the sampler behavior is a property of the named texture.u32. {f1}]. the resulting behavior is undefined. and is a four-element vector for 3d textures.2d. Notes For compatibility with prior versions of PTX. // Example of independent mode texturing tex.Chapter 8. Supported on all target architectures.1d. PTX ISA Notes Target ISA Notes Examples January 24.r4}.f32 {r1. b.s32. . 2010 123 . . .s32. d.geom. i. . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.3d }.f32 }.geom. . {f1.3d. the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom = { .r2. sampler_x.s32. or the instruction may fault.dtype.f3. the square brackets are not required and . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.v4. Unified mode texturing introduced in PTX ISA version 1.dtype = { . . If an address is not properly aligned.dtype.5.f2. c]. Description Texture lookup using a texture coordinate vector. where the fourth element is ignored. //Example of unified mode texturing tex.s32 {r1. The instruction always returns a four-element vector of 32-bit values. [tex_a. c].v4. A texture base address is assumed to be aligned to a 16-byte address. is a two-element vector for 2d textures.r3.r4}.

addr_mode_0 . [a].b32 %r1. txq. 2010 .b32 %r1. [tex_A].PTX ISA Version 2.addr_mode_0.addr_mode_1 . [smpl_B]. d. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. [a].height . Description Query an attribute of a texture or sampler.0 Table 89.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).width.width. Operand a is a . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.5. txq. // unified mode // independent mode 124 January 24.b32 txq.squery. addr_mode_1.b32 d.squery = { . // texture attributes // sampler attributes .depth . clamp_ogl. .filter_mode . clamp_to_edge. and in independent mode sampler attributes are accessed via a separate samplerref argument.texref or .width .b32 %r1.normalized_coords . addr_mode_2 }.samplerref variable.tquery = { .normalized_coords }. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq. . txq.height. In unified mode. Query: .addr_mode_0.filter_mode. mirror. txq. linear } Integer from enum { wrap.tquery. [tex_A]. sampler attributes are also accessed via a texref argument. .depth. Supported on all target architectures.filter_mode. . . Integer from enum { nearest.

r2}.s32 is returned.clamp. suld. Operand b is a scalar or singleton tuple for 1d surfaces.p is currently unimplemented.3d }.dtype.b8 .v2.b64. size and type conversion is performed as needed to convert from the surface sample format to the destination type. the surface sample elements are converted to . is a two-element vector for 2d surfaces. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.clamp suld. suld. . . or . suld. [a. .b. . A surface base address is assumed to be aligned to a 16-byte address. and is a four-element vector for 3d surfaces.e. suld Syntax Texture and Surface Instructions: suld Load from surface memory.v4 }.clamp field specifies how to handle out-of-bounds addresses: .s32. // for suld. then . {f1.z.b32. and cache operations introduced in PTX ISA version 2. G.clamp = = = = = = { { { { { { d. and the size of the data transfer matches the size of destination operand d. SNORM.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. . If an address is not properly aligned. 2010 125 .p.s32. if the surface format contains SINT data. additional clamp modifiers.1d. // for suld. the access may proceed by silently masking off low-order address bits to achieve proper rounding. // formatted .cv }. ..Chapter 8.p . If the destination base type is .cg.p. // cache operation none.1d.p. then .v4. B. or . then . i. Cache operations require sm_20 or later.zero }. . {x.p requires sm_20 or later.u32. If the destination type is .geom{.vec.cs.s32.0. . Target ISA Notes Examples January 24. .clamp . sm_1x targets support only the .w}].u32. . [surf_A.3d requires sm_20 or later.s32.u32.v2.3d. . .cop .ca. the resulting behavior is undefined.y.vec . .surfref variable.dtype.5.b .b16. suld. [a.f32. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.b performs an unformatted load of binary data. // unformatted d. Destination vector elements corresponding to components that do not appear in the surface format are not written. or the instruction may fault.trap clamping modifier.dtype . .u32 is returned. suld. . suld.geom{. [surf_B.f32 is returned.b.2d.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.f32 }.trap introduced in PTX ISA version 1.b supported on all target architectures. The lowest dimension coordinate represents a sample offset rather than a byte offset. suld. if the surface format contains UINT data.f4}.cop}.trap.b.geom .cop}.v4.f3. Operand a is a . suld. The . b]. .b32.trap .b32. Description Load from surface memory using a surface coordinate vector.clamp .f2. suld. {x}].trap {r1. or FLOAT data. Instruction Set Table 90.b64 }. Coordinate elements are of type .f32. . and A components of the surface format. where the fourth element is ignored.f32 based on the surface format as follows: If the surface format contains UNORM. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. .trap suld. b].dtype .

v2.3d. is a two-element vector for 2d surfaces.b.clamp = = = = = = { { { { { { [a.s32.clamp field specifies how to handle out-of-bounds addresses: . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.f32 is assumed. If an address is not properly aligned. The source data is then converted from this type to the surface sample format. B. Surface sample components that do not occur in the source vector will be written with an unpredictable value.1d.trap [surf_A. sust Syntax Texture and Surface Instructions: sust Store to surface memory. and is a four-element vector for 3d surfaces. .p requires sm_20 or later.geom . {x}]. {x.v4. . and cache operations introduced in PTX ISA version 2. . additional clamp modifiers. b].cg.p.f32.cop}.surfref variable.vec.f3.5.clamp sust.b.3d }. if the surface format contains UINT data. sust. These elements are written to the corresponding surface sample components.zero }.3d requires sm_20 or later.s32. or the instruction may fault. the resulting behavior is undefined. The source vector elements are interpreted left-to-right as R. If the source base type is . . then . c. c. then .v2.2d.vec . sust. sust.cs. {f1. The lowest dimension coordinate represents a sample offset rather than a byte offset.trap sust. sust.f2. The .p. Target ISA Notes Examples 126 January 24.p.1d. sust.w}]. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Operand b is a scalar or singleton tuple for 1d surfaces.0 Table 91. if the surface format contains SINT data. // unformatted // formatted . where the fourth element is ignored.u32.u32.ctype .b32. 2010 . The size of the data transfer matches the size of source operand c. .p.p Description Store to surface memory using a surface coordinate vector.cop .ctype.wt }. Operand a is a .trap.b32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.trap .clamp .b supported on all target architectures. .b performs an unformatted store of binary data. G.b16.u32 is assumed.f4}.wb.s32.clamp . sust.y. . and A surface components. or .b64. .r2}. . sm_1x targets support only the .z. {r1. size and type conversions are performed as needed between the surface sample format and the destination type.p performs a formatted store of a vector of 32-bit data values to a surface sample. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.ctype. [a.. . i. A surface base address is assumed to be aligned to a 16-byte address.trap introduced in PTX ISA version 1. or FLOAT data.b8 .geom{. then . b]. .e.PTX ISA Version 2.f32} are currently unimplemented.f32.b // for sust. [surf_B.b64 }.s32.0.b. . Coordinate elements are of type . .{u32.b32.cop}. .s32 is assumed.vec. sust. . sust. Cache operations require sm_20 or later. sust. If the source type is . .geom{.v4 }.trap clamping modifier. none. Source elements that do not occur in the surface sample are ignored. SNORM.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.clamp.ctype . . . // for sust.f32 }. . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.

The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b32.0. . . 2010 127 .op. Coordinate elements are of type .s32 is assumed.trap. min and max apply to .s32. sured. i. operations and and or apply to .max. .zero }.2d. Operations add applies to .u64. [surf_B.geom.min. sured.add.p.u32 based on the surface sample format as follows: if the surface format contains UINT data.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 and . // byte addressing sured. . . or . // for sured.u32.clamp [a.Chapter 8. If an address is not properly aligned.geom = { .clamp field specifies how to handle out-of-bounds addresses: .trap [surf_A. where the fourth element is ignored. r1.b32.ctype = { . . . The . or the instruction may fault. Operand a is a .s32.clamp.b].add. Reduction to surface memory using a surface coordinate vector. // for sured. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.ctype. . The lowest dimension coordinate represents a sample offset rather than a byte offset.trap .s32 or .u64.and. // sample addressing .1d. and the data is interpreted as .p performs a reduction on sample-addressed 32-bit data. . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.min.2d. if the surface format contains SINT data.trap sured.c.s32 types. {x.. the resulting behavior is undefined. .b . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.or }.b32.b performs an unformatted reduction on .clamp = { .clamp . January 24. r1.1d. then . sured.ctype.e. Instruction Set Table 92.geom. . sured requires sm_20 or later. {x}]. .op.b32 type. and .3d }.surfref variable. is a two-element vector for 2d surfaces.b.u32 is assumed. then .p .s32 types.u32.b.u32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b].clamp [a. . . sured.u64 data.b32 }.y}]. The instruction type is restricted to . .c.p.u32. and is a four-element vector for 3d surfaces.ctype = { .s32. .op = { . A surface base address is assumed to be aligned to a 16-byte address. Operand b is a scalar or singleton tuple for 1d surfaces.b32 }.

suq.b32 d. 128 January 24. [surf_A]. .0 Table 93. [a].b32 %r1.5.width.query.width .depth }. . .height. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.width. Description Query an attribute of a surface. Supported on all target architectures.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.query = { .PTX ISA Version 2.surfref variable. suq. Operand a is a . Query: .height . 2010 .

s32 d.c.s32 a. Supported on all target architectures. Threads with a false guard predicate do nothing.7. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. If {!}p then instruction Introduced in PTX ISA version 1.b. } PTX ISA Notes Target ISA Notes Examples Table 95. 2010 129 .0. Introduced in PTX ISA version 1. ratio. Supported on all target architectures. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.0. setp.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.0.f32 @q bra L23.f32 @!p div. Instruction Set 8.eq.y.a.7. used primarily for defining a function body. { add. { instructionList } The curly braces create a group of instructions. {} Syntax Description Control Flow Instructions: { } Instruction grouping.x. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. mov. p. Execute an instruction or instruction block for threads that have the guard predicate true. @{!}p instruction.Chapter 8.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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bar. d. it simply marks a thread's arrival at the barrier. operands p and c are predicates.{arrive. In addition to signaling its arrival at the barrier.u32 bar. January 24. bar.op. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).0. If no thread count is specified. b.red} introduced in PTX . The reduction operations for bar. a{.red delays the executing threads (similar to bar. while . b}. Register operands. Operands a. 2010 133 .cta.arrive a{.or }. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).red are population-count (.{arrive.sync bar.red. . bar. all-threads-true (. bar. Each CTA instance has sixteen barriers numbered 0.popc is the number of threads with a true predicate. The barrier instructions signal the arrival of the executing threads at the named barrier. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. bar. {!}c.red instruction. and bar. Only bar.red also guarantee memory ordering among threads identical to membar. thread count. the final value is written to the destination register in all threads waiting at the barrier.sync 0. In conditionally executed code.sync) until the barrier count is met. Once the barrier count is reached. the bar.red} require sm_20 or later. Thus.and and . Thus. bar. When a barrier completes.pred . bar.red should not be intermixed with bar. Register operands.sync or bar. p.arrive using the same active barrier.popc. Description Performs barrier synchronization and communication within a CTA.sync and bar.sync and bar. and bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. Since barriers are executed on a per-warp basis. bar.. Execution in this case is unpredictable. and d have type . and any-thread-true (.popc). Barriers are executed on a per-warp basis as if all the threads in a warp are active. the optional thread count must be a multiple of the warp size.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. Instruction Set Table 100.and. and the barrier is reinitialized so that it can be immediately reused.and). Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.or).Chapter 8. and then safely read values stored by other threads prior to the barrier. all threads in the CTA participate in the barrier. threads within a CTA that wish to communicate via memory can store to memory. it is as if all the threads in the warp have executed the bar instruction.red performs a reduction operation across threads. PTX ISA Notes Target ISA Notes Examples bar. {!}c.arrive. b}. thread count.sync without a thread count introduced in PTX ISA 1.red performs a predicate reduction across the threads participating in the barrier.0.version 2.u32. execute a bar. All threads in the warp are stalled until the barrier completes. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. The result of .sync or bar. bar.15.arrive does not cause any waiting by the executing threads. the waiting threads are restarted without delay. a{. b}. a.red.op = { .sync with an immediate barrier number is supported for sm_1x targets. Note that a non-zero thread count is required for bar. if any thread in a warp executes a bar instruction. b. Operand b specifies the number of threads participating in the barrier.

sys introduced in PTX . membar. level describes the scope of other clients for which membar is an ordering event. by st. PTX ISA Notes Target ISA Notes Examples membar.{cta. membar.g.sys }.gl will typically have a longer latency than membar.gl. 2010 . membar.cta. 134 January 24. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. including thoses communicating via PCI-E such as system and peer-to-peer memory. For communication between threads in different CTAs or even different SMs.sys Waits until all prior memory requests have been performed with respect to all clients.sys will typically have much longer latency than membar.cta Waits until all prior memory writes are visible to other threads in the same CTA.level = { . this is the appropriate level of membar. when the previous value can no longer be read. membar. membar. .level.gl.0 Table 101.PTX ISA Version 2. membar.cta. membar. . Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. Waits until prior memory reads have been performed with respect to other threads in the CTA.cta. membar.version 1. global.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.version 2.{cta. red or atom) has been performed when the value written has become visible to other clients at the specified level.g. that is. A memory write (e.gl} supported on all target architectures.0. membar.4.gl} introduced in PTX . and memory reads by this thread can no longer be affected by other thread writes. membar. . A memory read (e. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.sys. or system memory level. membar. membar. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.sys requires sm_20 or later.gl. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.

global. . If no state space is given. and stores the result of the specified operation at location a.s32. b. The address size may be either 32-bit or 64-bit. Description // // // // // . and max.type d.exch to store to locations accessed by other atomic operations. The integer operations are add.f32 Atomically loads the original value at location a into destination register d.op.add. The inc and dec operations return a result in the range [0.b32. an address maps to the corresponding location in local or shared memory.op.space}. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. The address must be naturally aligned to a multiple of the access size.Chapter 8. [a]..u32. .inc. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.dec. or.u64. by inserting barriers between normal stores and atomic operations to a common address. overwriting the original value.max }. i. . . The floating-point add.add. an address maps to global memory unless it falls within the local memory window or the shared memory window.b32 only . b.min.space = { .u32 only .type atom{. The floating-point operations are add.f32.b32.u64 . c. . . and truncated if the register width exceeds the state space address width for the target architecture. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. 2010 135 . atom. . and max operations are single-precision. The bit-size operations are and. . e.s32.xor. the resulting behavior is undefined. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.s32. . xor. or the instruction may fault. .cas.space}. A register containing an address may be declared as a bit-size type or integer type. . [a].b64. . .u32. .or. . Instruction Set Table 102. . . min. Operand a specifies a location in the specified state space.b].f32 }. cas (compare-and-swap). i. Addresses are zero-extended to the specified width as needed. . min. .e.b64 . . atom{.. If an address is not properly aligned.and. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .u32. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. 32-bit operations. d. and exch (exchange). or by using atom. max.g.exch.e. accesses to local memory are illegal. or [immAddr] an immediate absolute byte address. Within these windows.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. a de-referenced register areg containing a byte address. In generic addressing. . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. performs a reduction operation with operand b and the value in location a.type = { . . For atom.shared }. inc. perform the memory accesses using generic addressing. .op = { . January 24. min. dec.

0.shared requires sm_12 or later. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.PTX ISA Version 2.1. c) operation(*a. 2010 .[p].t) = (r == s) ? t operation(*a.max. atom.s.add.my_val. s) = (r > s) ? s exch(r.add. Release Notes Examples @p 136 January 24.b32 d.shared.global.0 Semantics atomic { d = *a. d. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.my_new_val.{add. 64-bit atom.f32 atom.global requires sm_11 or later.global. : r. *a = (operation == cas) ? : } where inc(r.[a].cas. b.[x+4]. s) = s. Use of generic addressing requires sm_20 or later. : r-1.exch} requires sm_12 or later.f32.0. atom.max} are unimplemented. 64-bit atom. d. s) = (r >= s) ? 0 dec(r.s32 atom. atom. atom. : r+1.shared operations require sm_20 or later.{min. cas(r. atom. b).f32 requires sm_20 or later.cas. Introduced in PTX ISA version 1.

inc.u32. where inc(r. .inc. and xor. .shared }.xor. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. Description // // // // . Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. The address size may be either 32-bit or 64-bit.. . 32-bit operations. .u64.add.type = { .s32. Instruction Set Table 103. Operand a specifies a location in the specified state space.f32 Performs a reduction operation with operand b and the value in location a. . .g. . and truncated if the register width exceeds the state space address width for the target architecture.type [a]. an address maps to global memory unless it falls within the local memory window or the shared memory window. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.or. by inserting barriers between normal stores and reduction operations to a common address.op = { . 2010 137 . . or by using atom.e. max. a de-referenced register areg containing a byte address. and stores the result of the specified operation at location a. . min.b32 only .u32. accesses to local memory are illegal. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. For red. . overwriting the original value.u64 . i.global. . In generic addressing.b]. If an address is not properly aligned. .b32. .b64. dec(r. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. Semantics *a = operation(*a.dec. January 24. . or the instruction may fault. . red. or [immAddr] an immediate absolute byte address. perform the memory accesses using generic addressing.space}. A register containing an address may be declared as a bit-size type or integer type.s32.f32 }. b).u32 only .. Within these windows.u32. an address maps to the corresponding location in local or shared memory. Notes Operand a must reside in either the global or shared state space.s32.add.f32.max }. . . . The integer operations are add. and max operations are single-precision. i. dec. . s) = (r >= s) ? 0 : r+1. . The address must be naturally aligned to a multiple of the access size.space = { . red{.op. s) = (r > s) ? s : r-1.e.min.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. If no state space is given. min.Chapter 8. and max.exch to store to locations accessed by other reduction operations.and. . or. Addresses are zero-extended to the specified width as needed. The floating-point add. The floating-point operations are add. min. The inc and dec operations return a result in the range [0. the resulting behavior is undefined. b. e. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The bit-size operations are and.

red.2. red.shared requires sm_12 or later.add.0.1.max} are unimplemented.add.b32 [a].global requires sm_11 or later red.shared operations require sm_20 or later. 64-bit red. red.global. 2010 .f32. [p].and. Release Notes Examples @p 138 January 24.f32 requires sm_20 or later.{min.s32 red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 red.my_val. [x+4].PTX ISA Version 2.shared.max. Use of generic addressing requires sm_20 or later.add requires sm_12 or later. 64-bit red. red.global.

{!}a. vote.ballot. . Note that vote applies to threads in a single warp.b32 requires sm_20 or later. // ‘ballot’ form.all True if source predicate is True for all active threads in warp. {!}a. where the bit position corresponds to the thread’s lane id.uni.uni True if source predicate has the same value in all active threads in warp. . Negate the source predicate to compute .not_all. r1.uni.all. vote. The destination predicate value is the same across all threads in the warp.q.b32 p. vote.any True if source predicate is True for some active thread in warp. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.pred vote. Negating the source predicate also computes . not across an entire CTA.pred vote. Negate the source predicate to compute . In the ‘ballot’ form.uni }. . vote.mode = { .all. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. Description Performs a reduction of the source predicate across threads in a warp.ballot.any.p. // get ‘ballot’ across warp January 24. p. vote requires sm_12 or later.ballot.b32 d. Instruction Set Table 104.2. .ballot. 2010 139 .q.mode.Chapter 8. The reduction modes are: .none. returns bitmask .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.pred d. vote.

dtype. The sign of the intermediate result depends on dtype.s32) is specified in the instruction type. with optional secondary operation vop.or zero-extend byte. 4. a{.asel}.9.b3.u32. optionally clamp the result to the range of the destination type.bsel = { .bsel}.h1 }.atype = . The primary operation is then performed to produce an . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. a{.atype.bsel}. all combinations of dtype. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.s33 values.add. . 3. atype.s32 }. .bsel}. The type of each operand (. The source and destination operands are all 32-bit registers.min.dsel = . . Using the atype/btype and asel/bsel specifiers.s34 intermediate result. Video Instructions All video instructions operate on 32-bit register operands. half-word.btype = { .sat}. .b0. the input values are extracted and signor zero. .asel}.max }. .asel}.btype{.sat} d. 140 January 24. c.0 8. . 2010 . // 32-bit scalar operation. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). a{. perform a scalar arithmetic operation to produce a signed 34-bit result.b2. with optional data merge vop.btype{. . b{. b{. extract and sign. .btype{.asel = . .7. taking into account the subword destination size in the case of optional data merging.atype. to produce signed 33-bit input values.u32 or . . 2.b1. c.PTX ISA Version 2.dtype.secop = { .extended internally to .dtype. or word values from its source operands. b{.dsel. and btype are valid.sat} d.h0. vop.dtype = . The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.atype. The general format of video instructions is as follows: // 32-bit scalar operation.secop d.

s33 c ) switch ( dsel ) { case . U16_MIN ). The lower 32-bits are then written to the destination operand. 2010 141 .h0: return ((tmp & 0xffff) case . tmp. S16_MIN ). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 optSecOp(Modifier secop. U8_MAX. .Chapter 8. . . . S32_MIN ). tmp. Modifier dsel ) { if ( !sat ) return tmp. U16_MAX.b1. as shown in the following pseudocode.b2: return ((tmp & 0xff) << 16) case .s33 optMerge( Modifier dsel. . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). January 24. S8_MIN ). . Bool sign.b0: return ((tmp & 0xff) case . } } . tmp. .h1: return ((tmp & 0xffff) << 16) case .b1: return ((tmp & 0xff) << 8) case .min: return MIN(tmp. c). c). c). tmp.s33 tmp. c). tmp. c). default: return tmp.b3: if ( sign ) return CLAMP( else return CLAMP( case . . U32_MIN ). The sign of the c operand is based on dtype.s33 optSaturate( . S8_MAX.b0.add: return tmp + c. . . Bool sat.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. U32_MAX. c). Instruction Set . S16_MAX.b3: return ((tmp & 0xff) << 24) default: return tmp. c).s33 tmp.s33 c) { switch ( secop ) { . S32_MAX. U8_MIN ).s34 tmp.b2.max return MAX(tmp. switch ( dsel ) { case . .h0.

r2.h0. Video Instructions: vadd.btype{. vsub vabsdiff vmin. vadd. with optional secondary operation vop.s32. r2. . vsub.s32. . tmp = MAX( ta. c ). .u32.s32. b{.bsel}.asel}. r3.op2 d.s32. c. vmin.b0. .b3.PTX ISA Version 2. Integer byte/half-word/word minimum / maximum. r3. vabsdiff. .h1.dtype .asel = .atype = . // optional merge with c operand 142 January 24.atype. tmp = | ta – tb |.dtype.sat vmin. vmax require sm_20 or later.u32. . r3. r2. dsel ).dtype.h1 }. . vabsdiff.h1.bsel = { . // optional secondary operation d = optMerge( dsel. c.b0.sat}. tmp = MIN( ta.max }. 2010 .s32.sat vabsdiff. // extract byte/half-word/word and sign. . // 32-bit scalar operation. Integer byte/half-word/word absolute value of difference. vmin. b{.btype{.sat} d.s32.h0.b0. atype.dsel . and optional secondary arithmetic operation or subword data merge. Semantics // saturate. tmp. tmp = ta – tb.add r1. r2. c. d = optSecondaryOp( op2. // 32-bit scalar operation. sat.sat} d. vsub. r1. isSigned(dtype). tb ).btype{. vmin.s32. vop. a{.sat vsub.s32. a{. .s32 }. vsub.asel}.bsel}.dtype. taking into account destination type and merge operations tmp = optSaturate( tmp.min. .s32. tb ).add.btype = { .sat. vmax vadd.atype. Perform scalar arithmetic operation with optional saturate. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b2. tmp. r1.u32. { . bsel ).atype. r3.b1.s32. b{.op2 Description = = = = { vadd. vabsdiff. vadd.0.asel}. c ). r1. vmax Syntax Integer byte/half-word/word addition / subtraction. tb = partSelectSignExtend( b.dsel. c.bsel}.h0. btype.vop . vmax }.b2. . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. asel ).0 Table 105. a{. with optional data merge vop.or zero-extend based on source operand type ta = partSelectSignExtend( a.

// optional secondary operation d = optMerge( dsel. { . with optional data merge vop.clamp && tb > 32 ) tb = 32. vshl. unsigned shift fills with zero.asel}.mode} d.mode} d. . Signed shift fills with the sign bit. { .h1 }.bsel = { . c.min.0. // 32-bit scalar operation.dtype . case vshr: tmp = ta >> tb.op2 Description = = = = = { vshl. vshl.b2.b3. .bsel}. a{. r1. c ). . . c ).u32.mode . // default is . tmp.s32. January 24. r2. b{. bsel ). dsel ).u32. tb = partSelectSignExtend( b.u32{.h1.clamp. vshr require sm_20 or later. a{.s32 }. switch ( vop ) { case vshl: tmp = ta << tb. Instruction Set Table 106. taking into account destination type and merge operations tmp = optSaturate( tmp.asel}. . .asel}.or zero-extend based on source operand type ta = partSelectSignExtend( a. r2.u32{.op2 d. d = optSecondaryOp( op2. .b0. isSigned(dtype). . asel ). .bsel}.asel = .u32{. } // saturate.dsel.atype.vop . .u32 vshr. Left shift fills with zero. vshr }.u32.dsel . a{.sat}{.clamp . Video Instructions: vshl.b1. .wrap }.u32.mode}. vop. and optional secondary arithmetic operation or subword data merge.atype.Chapter 8. sat. if ( mode == . tmp. vshr Syntax Integer byte/half-word/word left / right shift. with optional secondary operation vop. vshr: Shift a right by unsigned amount in b with optional saturate.atype = { . vshl: Shift a left by unsigned amount in b with optional saturate. r3. 2010 143 .add.u32. Semantics // extract byte/half-word/word and sign. and optional secondary arithmetic operation or subword data merge. r3. b{. atype. vshr vshl. if ( mode == .sat}{.wrap ) tb = tb & 0x1f. c.dtype. .bsel}.u32.dtype.dtype.atype.wrap r1.sat}{.h0.max }. // 32-bit scalar operation. b{. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

btype = { . b{.PTX ISA Version 2. final signed (S32 * S32) + S32 // intermediate signed.asel}. c.dtype = .b0.S32 // intermediate signed. PTX allows negation of either (a*b) or c.po mode.bsel = { .s32 }. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. final signed (U32 * U32) .po{. and zero-extended otherwise. .atype.. That is.sat}{.dtype.b2. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated. Although PTX syntax allows separate negation of the a and b operands. {-}c. . .b1.S32 // intermediate signed. Input c has the same sign as the intermediate result. 144 January 24. final signed -(S32 * S32) + S32 // intermediate signed.scale} d. which is used in computing averages.h0. a{.b3. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed (S32 * U32) + S32 // intermediate signed.shr7.0 Table 107.po) computes (a*b) + c + 1. {-}b{. final signed -(U32 * S32) + S32 // intermediate signed. The source operands support optional negation with some restrictions.bsel}. with optional operand negates.dtype. final signed -(S32 * U32) + S32 // intermediate signed. otherwise. and the operand negates. and scaling. Description Calculate (a*b) + c. final signed (S32 * S32) . . final signed (S32 * U32) . The “plus one” mode (.h1 }.btype.asel}. (a*b) is negated if and only if exactly one of a or b is negated. final unsigned -(U32 * U32) + S32 // intermediate signed. the intermediate result is signed. final signed (U32 * S32) + S32 // intermediate signed.sat}{. 2010 . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.u32. internally this is represented as negation of the product (a*b).scale} d.atype. vmad. // 32-bit scalar operation vmad. “plus one” mode.atype = . .S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift. this result is sign-extended if the final result is signed. . . Depending on the sign of the a and b operands.bsel}.asel = . final signed (U32 * S32) .btype{. . The final result is unsigned if the intermediate result is unsigned and c is not negated. . Source operands may not be negated in . {-}a{.shr15 }.U32 // intermediate unsigned. .scale = { .

signedFinal = isSigned(atype) || isSigned(btype) || (a.u32. else result = CLAMP(result. U32_MIN).u32. r3. } if ( . asel ). tmp[127:0] = ta * tb.sat ) { if (signedFinal) result = CLAMP(result.u32. U32_MAX.negate ) { c = ~c. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r2. atype.s32. r0.shr15 r0. S32_MAX.0. tb = partSelectSignExtend( b. -r3.h0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. lsb = 0.shr7: result = (tmp >> 7) & 0xffffffffffffffff.negate ^ b. vmad. if ( .negate ^ b. r1.h0. S32_MIN). lsb = 1.po ) { lsb = 1. lsb = 1.or zero-extend based on source operand type ta = partSelectSignExtend( a.s32. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). 2010 145 . } else if ( a. } else if ( c. bsel ). r1. btype. January 24. case .u32.negate ) { tmp = ~tmp.Chapter 8. Instruction Set Semantics // extract byte/half-word/word and sign. switch( scale ) { case . vmad requires sm_20 or later.negate. r2. tmp = tmp + c128 + lsb.sat vmad.negate) || c.

tmp. 146 January 24. 2010 . . . atype. bsel ). cmp ) ? 1 : 0.bsel}.h0.btype = { . The intermediate result of the comparison is always unsigned. r2. asel ). .ne. // optional secondary operation d = optMerge( dsel.atype.btype. with optional data merge vset. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.cmp d. . c ). c. c.add.cmp.cmp d. vset requires sm_20 or later.ne r1.b2.b3.u32. c ). Semantics // extract byte/half-word/word and sign.atype. { .0. // 32-bit scalar operation.le. .bsel}. tmp = compare( ta. { . d = optSecondaryOp( op2. btype. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.s32 }.btype.cmp .eq. b{. .gt.bsel}.lt vset.asel}. vset.lt. . vset.dsel .PTX ISA Version 2. b{. r1. tmp.asel = . r3. with optional secondary operation vset.min.h1 }. tb.asel}.b1.s32.dsel. a{. Compare input values using specified comparison. . .b0.atype.op2 d. tb = partSelectSignExtend( b.btype.h1. r3.atype . . with optional secondary arithmetic operation or subword data merge. .0 Table 108.max }.u32. a{. .asel}.ge }. and therefore the c operand and final result are also unsigned. a{.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a. . b{. .op2 Description = = = = .u32.bsel = { . // 32-bit scalar operation. r2.

0. Table 110. pmevent 7. there are sixteen performance monitor events. brkpt. trap. Notes PTX ISA Notes Target ISA Notes Examples Currently. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. brkpt Suspends execution Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Supported on all target architectures. numbered 0 through 15.7. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.10. Supported on all target architectures. Triggers one of a fixed number of performance monitor events. brkpt requires sm_11 or later. The relationship between events and counters is programmed via API calls from the host. Instruction Set 8. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.Chapter 8. brkpt. with index specified by immediate operand a. Introduced in PTX ISA version 1. 2010 147 .0. pmevent a. trap.4. Table 111. @p pmevent 1. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. January 24. trap Abort execution and generate an interrupt to the host CPU.

0 148 January 24.PTX ISA Version 2. 2010 .

%clock64 %pm0. %lanemask_gt %clock. 2010 149 . %lanemask_le. %pm3 January 24. %lanemask_ge. …. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq.Chapter 9. Special Registers PTX includes a number of predefined. read-only variables. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_lt.

the %tid value in unused dimensions is 0.0. // move tid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. PTX ISA Notes Introduced in PTX ISA version 1.y < %ntid.z == 0 in 2D CTAs.%h1.v4. read-only. mad.sreg .x.u32 type in PTX 2.%tid. %tid.z == 1 in 1D CTAs. cvt.y == %ntid. CTA dimensions are non-zero.u32 %h2.z.%tid.u32 type in PTX 2.0. Every thread in the CTA has a unique %tid. %tid. The number of threads in each dimension are specified by the predefined special register %ntid. or 3D vector to match the CTA shape.v4 .x. Supported on all target architectures. It is guaranteed that: 0 <= %tid. mov.z. // CTA shape vector // CTA dimensions A predefined.u16 %rh. %tid.sreg .%ntid.y.u16 %r2. The fourth element is unused and always returns zero.x * %ntid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.0 Table 112. // legacy PTX 1.u16 %rh. %ntid.u32 %ntid. // zero-extend tid.x. 2D. mov.u32 %r0.z to %r2 Table 113. // compute unified thread id for 2D CTA mov. %tid component values range from 0 through %ntid–1 in each CTA dimension. the fourth element is unused and always returns zero.x code accessing 16-bit component of %tid mov. mov. Supported on all target architectures. %ntid.x.u32 %r1.y == %tid. Redefined as .y 0 <= %tid.%ntid. read-only special register initialized with the number of thread ids in each CTA dimension.v4.y * %ntid. mov. The %tid special register contains a 1D.v4 .%r0.u32 %r0.x to %rh Target ISA Notes Examples // legacy PTX 1. .u32 %tid. .PTX ISA Version 2.x. .z == 0 in 1D CTAs.x code Target ISA Notes Examples 150 January 24. %tid.u32.x. per-thread special register initialized with the thread identifier within the CTA. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.%tid. The total number of threads in a CTA is (%ntid.%h2.y.z == 1 in 2D CTAs. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.0.y.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %tid.sreg . // thread id vector // thread id components A predefined.0.%tid. Redefined as .z < %ntid.u32 %h1.x < %ntid. .%tid. %ntid.x 0 <= %tid.u32 %ntid. %ntid.x. 2010 .z.z).sreg .

Introduced in PTX ISA version 1. . e. Introduced in PTX ISA version 2.sreg . but its value may change during execution. Introduced in PTX ISA version 1.u32 %warpid. The warp identifier will be the same for all threads within a single warp. read-only special register that returns the thread’s warp identifier. Supported on all target architectures. read-only special register that returns the maximum number of warp identifiers. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.u32 %laneid. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Special Registers Table 114.0. %laneid. mov.sreg . Note that %warpid is volatile and returns the location of a thread at the moment when read. For this reason. A predefined.g. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers.u32 %r. %nwarpid. The lane identifier ranges from zero to WARP_SZ-1. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.3. . A predefined. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. PTX ISA Notes Target ISA Notes Examples Table 116. A predefined. mov.u32 %nwarpid.u32 %r.sreg . %nwarpid requires sm_20 or later. January 24. . read-only special register that returns the thread’s lane within the warp.u32 %r. Supported on all target architectures.Chapter 9.3. Table 115. %warpid. 2010 151 . due to rescheduling of threads following preemption.

x.z} < 65.0 Table 117. depending on the shape and rank of the CTA grid.u32 type in PTX 2. // Grid shape vector // Grid dimensions A predefined. It is guaranteed that: 0 <= %ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.z.sreg . // CTA id vector // CTA id components A predefined. The %nctaid special register contains a 3D grid shape vector.x.x 0 <= %ctaid.v4 . Each vector element value is >= 0 and < 65535.x. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u32 mov.x code Target ISA Notes Examples 152 January 24. 2010 .sreg . .y 0 <= %ctaid.z < %nctaid. The %ctaid special register contains a 1D. // legacy PTX 1. with each element having a value of at least 1.u32 type in PTX 2. %rh. // legacy PTX 1.%nctaid. The fourth element is unused and always returns zero.y.x. %ctaid. Redefined as . %ctaid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.%ctaid.x. .0.PTX ISA Version 2.{x.y.%ctaid.0.u32 %nctaid.y < %nctaid.y. It is guaranteed that: 1 <= %nctaid.%nctaid.%nctaid. .z PTX ISA Notes Introduced in PTX ISA version 1.536 PTX ISA Notes Introduced in PTX ISA version 1. Redefined as .u16 %r0. mov.sreg .0. 2D. mov.v4 .%nctaid.u32 %ctaid.sreg .z.y. or 3D vector.u32 %ctaid.v4. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.v4.u32 %nctaid . %rh.u16 %r0. Supported on all target architectures.0.u32 mov. read-only special register initialized with the CTA identifier within the CTA grid. read-only special register initialized with the number of CTAs in each grid dimension. The fourth element is unused and always returns zero.x < %nctaid. Supported on all target architectures.x code Target ISA Notes Examples Table 118.

sreg . PTX ISA Notes Target ISA Notes Examples Table 121. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.u32 %r. A predefined. The SM identifier numbering is not guaranteed to be contiguous. %nsmid. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. PTX ISA Notes Target ISA Notes Examples January 24. // initialized at grid launch A predefined. mov. repeated launches of programs may occur. read-only special register that returns the maximum number of SM identifiers. .g. Note that %smid is volatile and returns the location of a thread at the moment when read. read-only special register initialized with the per-grid temporal grid identifier.Chapter 9.sreg . Introduced in PTX ISA version 1.u32 %gridid. Supported on all target architectures. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. so %nsmid may be larger than the physical number of SMs in the device.3. where each launch starts a grid-of-CTAs. . mov. Introduced in PTX ISA version 2. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. This variable provides the temporal grid launch number for this context.sreg .u32 %r. Notes PTX ISA Notes Target ISA Notes Examples Table 120. The SM identifier numbering is not guaranteed to be contiguous. . During execution. A predefined. Special Registers Table 119. mov. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. %smid. The SM identifier ranges from 0 to %nsmid-1.u32 %nsmid.u32 %r. but its value may change during execution. 2010 153 . e. Introduced in PTX ISA version 1. %nsmid requires sm_20 or later.0. due to rescheduling of threads following preemption. Supported on all target architectures. %gridid.u32 %smid.0.

Table 124. . Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_eq. %lanemask_eq requires sm_20 or later.sreg . mov. 154 January 24. mov. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.sreg .0 Table 122.0. .0. A predefined.PTX ISA Version 2. 2010 . Introduced in PTX ISA version 2.u32 %r. Introduced in PTX ISA version 2. . A predefined. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later.sreg . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Table 123. mov.u32 %r. %lanemask_eq. %lanemask_lt.u32 %r. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.0.u32 %lanemask_le. %lanemask_le requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %lanemask_lt. A predefined. %lanemask_le.

u32 %lanemask_ge. A predefined. mov. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.u32 %r.0. 2010 155 . %lanemask_ge. mov.0. A predefined. Table 126. January 24.sreg . read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg . . %lanemask_ge requires sm_20 or later. %lanemask_gt requires sm_20 or later. . Special Registers Table 125. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %r. %lanemask_gt. Introduced in PTX ISA version 2.Chapter 9. Introduced in PTX ISA version 2.

mov.sreg .%pm0.u64 r1. mov.PTX ISA Version 2. Special registers %pm0.u32 r1. Table 129. %pm1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. . %clock64 requires sm_20 or later. Table 128. ….0 Table 127. Introduced in PTX ISA version 1. read-only 32-bit unsigned cycle counter. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm3. Their behavior is currently undefined. %pm3 %pm0. Supported on all target architectures. Introduced in PTX ISA version 1. %pm1. %pm1. The lower 32-bits of %clock64 are identical to %clock.3. %pm2.u64 %clock64. 156 January 24.0. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. . %pm2.sreg .%clock64. Special Registers: %pm0. %pm2. . mov.u32 %clock. 2010 . read-only 64-bit unsigned cycle counter. and %pm3 are unsigned 32-bit read-only performance monitor counters. Supported on all target architectures.sreg .%clock.0.u32 %pm0. Introduced in PTX ISA version 2.u32 r1. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.

minor are integers Specifies the PTX language version number.1.version directive.version directives are allowed provided they match the original .Chapter 10. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version . Supported on all target architectures. PTX File Directives: .version 2. 2010 157 . . .version 1.target Table 130. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directive.version major.version . Increments to the major number indicate incompatible changes to PTX.0. . Duplicate .minor // major.0 .4 January 24. and the target architecture for which the code was generated.version Syntax Description Semantics PTX version number. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Directives 10. Each ptx file must begin with a .

target directive specifies a single target architecture.red}. sm_13.f64 storage remains as 64-bits.target directive containing a target architecture and optional platform options. and an error is generated if an unsupported feature is used.f64 instructions used. with only half being used by instructions converted from .f64 to . sm_12.PTX ISA Version 2. Introduced in PTX ISA version 1. including expanded rounding modifiers. A . Target sm_20 Description Baseline feature set for sm_20 architecture.f64 instructions used. Texturing mode: (default is . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.global. PTX File Directives: .global. texture and sampler information is referenced with independent .0. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.red}.f64 instructions used. Adds {atom. immediately followed by a . 64-bit {atom.shared. Adds {atom. Texturing mode introduced in PTX ISA version 1. texmode_independent.red}. Therefore. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. A program with multiple . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.version directive. Note that . 2010 . The texturing mode is specified for an entire module and cannot be changed within the module. Description Specifies the set of features in the target architecture for which the current ptx code was generated. where each generation adds new features and retains all features of previous generations. Requires map_f64_to_f32 if any . The following table summarizes the features in PTX that vary according to target architecture.target Syntax Architecture and Platform target.texmode_unified . .texref and .0 Table 131. but subsequent . Requires map_f64_to_f32 if any . In general. PTX code generated for a given target can be run on later generation devices.f32. generations of SM architectures follow an “onion layer” model.texref descriptor.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Adds double-precision support. Requires map_f64_to_f32 if any . vote instructions. map_f64_to_f32 }.target . Disallows use of map_f64_to_f32. 158 January 24. brkpt instructions. sm_11. Supported on all target architectures.texmode_independent texture and sampler information is bound together and accessed via a single . Each PTX file must begin with a .5. texmode_unified. PTX features are checked against the specified target architecture. sm_10.target directives can be used to change the set of target features allowed during parsing.texmode_unified) .target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.samplerref descriptors.

Chapter 10. texmode_independent January 24.target sm_10 // baseline target architecture .target sm_13 // supports double-precision . 2010 159 .target sm_20. Directives Examples .

.PTX ISA Version 2. and body for the kernel function.param { .param. parameter variables are declared in the kernel parameter list. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.entry . Kernel and Function Directives: . store.b32 z ) Target ISA Notes Examples [x]. and query instructions and cannot be accessed via ld. PTX ISA Notes For PTX ISA version 1.param space memory and are listed within an optional parenthesized parameter list.entry kernel-name ( param-list ) kernel-body . .0 through 1.2.0 10. with optional parameters. The shape and size of the CTA executing the kernel are available in special registers.entry kernel-name kernel-body Defines a kernel entry point name. . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.texref. e.b32 %r<99>.5 and later. .param.entry Syntax Description Kernel entry point and body.0 through 1. parameter variables are declared in the kernel body. Supported on all target architectures. … } .param instructions.entry . ld. opaque . the kernel dimensions and properties are established and made available via special registers. For PTX ISA versions 1.param .param instructions. In addition to normal parameters.entry filter ( . [z].3. Parameters are passed via .entry cta_fft .func Table 132. parameters. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. At kernel launch. .b32 %r2. Parameters may be referenced by name within the kernel body and loaded into registers using ld.surfref variables may be passed as parameters.b32 %r1. %ntid. and .reg .b32 y.b32 x. 2010 . These parameters can only be referenced by name within texture and surface load.4 and later. etc.samplerref. ld.4.b32 %r3. Semantics Specify the entry point for a kernel program. 160 January 24.param .param. [y]. %nctaid. ld.g. .

(val0.b32 N. Release Notes For PTX ISA version 1.0 with target sm_20 supports at most one return value.reg .param state space. Parameters in register state space may be referenced directly within instructions in the function body. } … call (fooval). Directives Table 133.func (. … Description // return value in fooval January 24. Parameters in .func fname function-body .func Syntax Function definition. … use N. there is no stack. . including input and return parameters and optional function body.reg .b32 rval) foo (.func . Variadic functions are currently unimplemented. The parameter lists define locally-scoped variables in the function body.b32 rval.Chapter 10.func definition with no body provides a function prototype.f64 dbl) { . mov.param and st. A . dbl. .func fname (param-list) function-body . PTX 2. val1). if any. Variadic functions are represented using ellipsis following the last fixed argument. Supported on all target architectures.0. PTX ISA 2. implements an ABI with stack. parameters must be in the register state space.2 for a description of variadic functions.reg .param instructions in the body.x code. The implementation of parameter passing is left to the optimizing translator. ret.0 with target sm_20 allows parameters in the . which may use a combination of registers and stack locations to pass parameters. other code. foo. and recursion is illegal.func (ret-param) fname (param-list) function-body Defines a function.reg . and supports recursion. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Kernel and Function Directives: . Parameters must be base types in either the register or parameter state space. Parameter passing is call-by-value. 2010 161 .b32 localVar.result. . Semantics The PTX syntax hides all details of the underlying calling convention and ABI.param space are accessed using ld.

3. to throttle the resource requirements (e. The directives take precedence over any module-level constraints passed to the optimizing backend. A general . .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. and the strings have no semantics within the PTX virtual machine model.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). PTX supports the following directives. 2010 . The directive passes a list of strings to the backend.g. registers) to increase total thread count and provide a greater opportunity to hide memory latency.maxntid . or as statements within a kernel or device function body. The interpretation of .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.minnctapersm directives may be applied per-entry and must appear between an . . at entry-scope.pragma directives may appear at module (file) scope. and the .0 10.entry directive and its body. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. the . Performance-Tuning Directives To provide a mechanism for low-level performance tuning.minnctapersm .pragma directive is supported for passing information to the PTX backend. which pass information to the backend optimizing compiler.maxnreg.PTX ISA Version 2. and .maxnctapersm (deprecated) .maxntid and .maxntid. for example. Note that . 162 January 24.maxnreg .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. These can be used.maxntid directive specifies the maximum number of threads in a thread block (CTA). The . the .pragma The . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. Currently.

or 3D CTA. This maximum is specified by giving the maximum extent of each dimention of the 1D.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.entry foo . The actual number of registers used may be less.16.3.maxntid . 2010 163 . Supported on all target architectures.maxntid 16. . The compiler guarantees that this limit will not be exceeded.maxntid nx . ny .Chapter 10. .maxntid and . Exceeding any of these limits results in a runtime error or kernel launch failure. Supported on all target architectures. Performance-Tuning Directives: .maxnreg .maxctapersm.maxntid 256 .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. nz Declare the maximum number of threads in the thread block (CTA). The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. The maximum number of threads is the product of the maximum extent in each dimension. ny.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.entry foo . 2D.3. or the maximum number of registers may be further constrained by .maxntid nx. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Directives Table 134. . for example. .maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid nx.entry bar . the backend may be able to compile to fewer registers. Performance-Tuning Directives: .maxntid Syntax Maximum number of threads in thread block (CTA).

maxnctapersm generally need . .0 as a replacement for .minnctapersm in PTX ISA version 2. . if the number of registers used by the backend is sufficiently lower than this bound.0 Table 136. Supported on all target architectures.maxntid 256 . However.maxnctapersm (deprecated) . For this reason. Introduced in PTX ISA version 1.3. additional CTAs may be mapped to a single multiprocessor.maxnctapersm has been renamed to . Optimizations based on .0. . Optimizations based on . The optimizing backend compiler uses .entry foo . .maxnctapersm.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.PTX ISA Version 2. Supported on all target architectures.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. 2010 .maxntid to be specified as well.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm generally need . Performance-Tuning Directives: .maxntid and . Performance-Tuning Directives: .maxntid to be specified as well. Deprecated in PTX ISA version 2.minnctapersm . Introduced in PTX ISA version 2.maxntid 256 .entry foo .minnctapersm 4 { … } 164 January 24.0.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.

or at statementlevel.pragma . Pass module-scoped.entry foo . entry-scoped. or statement-level directives to the PTX backend compiler. .pragma “nounroll”. Introduced in PTX ISA version 2.pragma list-of-strings . The .pragma directive strings is implementation-specific and has no impact on PTX semantics. Performance-Tuning Directives: .pragma “nounroll”. . Supported on all target architectures. 2010 165 .0.Chapter 10. { … } January 24. Directives Table 138.pragma directive may occur at module-scope. The interpretation of . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma Syntax Description Pass directives to PTX backend compiler. at entry-scope. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .

loc The .0 and replaces the @@DWARF syntax. Introduced in PTX ISA version 1.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x00 166 January 24..debug_pubnames.0 10. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .264-1] .x code. The @@DWARF syntax is deprecated as of PTX version 2. 0x00.0 but is supported for legacy PTX version 1. replaced by . 0x02. Supported on all target architectures.PTX ISA Version 2.byte byte-list // comma-separated hexadecimal byte values . @progbits . Table 139.4byte . 0x61395a5f. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.section .debug_info .0.4byte 0x000006b5. 0x5f736f63 .4.section .. 0x736d6172 .4byte label . Deprecated as of PTX 2. 0x6150736f.byte 0x2b.4byte int32-list // comma-separated hexadecimal integers in range [0.quad int64-list // comma-separated hexadecimal integers in range [0.file .2. @@DWARF dwarf-string dwarf-string may have one of the . 0x63613031.232-1] . 0x00.4byte 0x6e69616d. 0x00. 0x00.byte 0x00.section directive is new in PTX ISA verison 2. 0x00. 0x00 .section directive. “”. 2010 . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00000364. 0x00.

0x00. Directives Table 140. 0x736d6172 0x00 Table 141.b8 0x2b. 0x00. 0x00.b32 .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Supported on all target architectures.loc .Chapter 10. ..b32 int32-list // comma-separated list of integers in range [0.b8 byte-list // comma-separated list of integers in range [0. .file filename Table 142.b32 0x6e69616d. 0x00 0x61395a5f.section .0.264-1] .section .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. ..file . Debugging Directives: .232-1] . 0x00.. } 0x02.b64 int64-list // comma-separated list of integers in range [0. Debugging Directives: . . .b8 0x00. 0x00000364. 0x5f736f63 0x6150736f.loc line_number January 24. Debugging Directives: .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 167 . 0x00. Source file location.0. Source file information.section Syntax PTX section definition. Supported on all target architectures. . 0x63613031. replaces @@DWARF syntax.b32 label .debug_pubnames { .section section_name { dwarf-lines } dwarf-lines have the following formats: .b32 0x000006b5.debug_info . Supported on all target architectures.255] . . 0x00.

Supported on all target architectures.b32 foo. 2010 . .extern . Supported on all target architectures. Linking Directives . .visible identifier Declares identifier to be externally visible.b32 foo.0.visible Table 143.extern . Introduced in PTX ISA version 1.extern identifier Declares identifier to be defined externally.visible .global . // foo is defined in another module Table 144.0.PTX ISA Version 2.global .0 10.extern . // foo will be externally visible 168 January 24.6. . Linking Directives: .visible .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Introduced in PTX ISA version 1. Linking Directives: . .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.

The release history is as follows.0. 2010 169 .0 CUDA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.Chapter 11.3 driver r190 CUDA 3.0 driver r195 PTX ISA Version PTX ISA 1.2 PTX ISA 1.3 PTX ISA 1.0 CUDA 2.0 PTX ISA 1.1 CUDA 2. and the remaining sections provide a record of changes in previous releases.1 CUDA 2. CUDA Release CUDA 1.4 PTX ISA 1.5 PTX ISA 2.0 January 24.2 CUDA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.1 PTX ISA 1.

f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Both fma. and mul now support .f32 and mad. Floating-Point Extensions This section describes the floating-point changes in PTX 2.1. sub.ftz and . The mad. Single. The goal is to achieve IEEE 754 compliance wherever possible.ftz modifier may be used to enforce backward compatibility with sm_1x.f32 for sm_20 targets.0 11. Instructions testp and copysign have been added. The .f32.x code and sm_1x targets. fma. When code compiled for sm_1x is executed on sm_20 devices. A single-precision fused multiply-add (fma) instruction has been added.sat modifiers.rn. The changes from PTX ISA 1. • • • • • 170 January 24.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.rp rounding modifiers for sm_20 targets. while maximizing backward compatibility with legacy PTX 1.PTX ISA Version 2. mad.1. Changes in Version 2. and sqrt with IEEE 754 compliant rounding have been added.1. 2010 . These are indicated by the use of a rounding modifier and require sm_20. The mad.1. Single-precision add. The fma.f32 maps to fma.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.rm and .0 11.f32 instruction also supports .1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.0 for sm_20 targets.f32 requires sm_20. New Features 11.f32 require a rounding modifier for sm_20 targets.1. rcp.and double-precision div.

bfe and bfi. A “bit reversal” instruction. . suld. The . prefetch.popc.zero.lt. 11. and shared addresses to generic address and vice-versa has been added.ge.red}. Other new features Instructions ld. . has been added. 2010 171 . Instruction sust now supports formatted surface stores. has been added.gt} have been added.red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.g. A “find leading non-sign bit” instruction.f32 have been implemented. Instructions {atom. ldu.3.1. New special registers %nsmid. New instructions A “load uniform” instruction.maxnctapersm directive was deprecated and replaced with .1. has been added.section. Video instructions (includes prmt) have been added.1.red. Instructions prefetch and prefetchu have also been added. A “vote ballot” instruction. popc. Instructions bar.pred have been added. st.clamp and .arrive instruction has been added. A “count leading zeros” instruction. and sust. A system-level membar instruction. isspacep. has been added.minnctapersm to better match its behavior and usage. vote. has been added.or}.clamp modifiers.u32 and bar. ldu. brev. cvta. clz. Instructions {atom. Surface instructions support additional . has been added. Bit field extract and insert instructions.red}. %lanemask_{eq. Release Notes 11. has been added. membar.b32. Instruction cvta for converting global. %clock64.Chapter 11.shared have been extended to handle 64-bit data types for sm_20 targets.sys. bar now supports optional thread count and register operands.{and. for prefetching to specified level of memory hierarchy.add. and red now support generic addressing. January 24. have been added.le. Cache operations have been added to instructions ld. A new directive. A “population count” instruction. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.1. bfind.ballot. prefetchu. e. local. The bar instruction has been extended as follows: • • • A bar.2. st. atom.

single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.{u32. 172 January 24. if . the correct number is sixteen.f32} atom.1.3.5 and later.f32 type is unimplemented. In PTX version 1. 2010 . where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. where . See individual instruction descriptions for details. Semantic Changes and Clarifications The errata in cvt.f32.red}.p sust. stack-based ABI is unimplemented. cvt. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. has been fixed.4 or earlier.target sm_1x. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.p.5. Formatted surface store with . . {atom. call suld.1.2. 11.ftz for PTX ISA versions 1.version is 1.ftz (and cvt for .u32. or . To maintain compatibility with legacy PTX code. Support for variadic functions and alloca are unimplemented. Formatted surface load is unimplemented.PTX ISA Version 2.max} are not implemented.{min. The underlying.s32. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.s32.0 11.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.4 and earlier. Instruction bra.

Supported only for sm_20 targets. and statement levels. { … } // do not unroll any loop in this function . entry-function. including loops preceding the . Ignored for sm_1x targets. The “nounroll” pragma is allowed at module. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.Appendix A. Table 145. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.pragma “nounroll”. L1_end: … } // do not unroll this loop January 24.pragma Strings This section describes the .pragma “nounroll”. disables unrolling of0 the loop for which the current block is the loop header.pragma. L1_body: … L1_continue: bra L1_head.0.entry foo (…) . Descriptions of . 2010 173 .pragma “nounroll”. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. disables unrolling for all loops in the entry function body. . Note that in order to have the desired effect at statement level.func bar (…) { … L1_head: .pragma strings defined by ptxas. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. … @p bra L1_end.

2010 .PTX ISA Version 2.0 174 January 24.

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