NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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............................................ 49 ii January 24..2............4............................... 5................................................................................... 6....................................................3........................................................................ 5............................. 5....................................... 5..... 29 Parameter State Space ............................................1................1.4................ 2010 ....................................................4........4........................................................................................ 42 Arrays as Operands ........ 37 Variable Declarations . Instruction Operands.......................2........................................... and Surface Types ......................................................... 41 Destination Operands ........ 5......................1...... 33 Fundamental Types ..2.......... 38 Alignment .........................4..............5....................1.................................5........................................... and Variables .. 5...........................................................1.......................... 5........ 34 Variables ...... Texture...................................5..... 37 Array Declarations ..............5.. 46 6.... 49 7................................................... 28 Constant State Space ..........6............. 37 Vectors ................................................ 6............3............................ 43 Labels and Function Names as Operands ..... Operand Type Information ..... 25 Chapter 5... 5........................... 29 Local State Space .................. 6.................................. Function declarations and definitions ............................ State Spaces ..........4........................2..................PTX ISA Version 2... 5.............. 29 Global State Space . 5........................................................................3.. 5.......................................2..............................6..........1.......4............................................................................................. Sampler................. 6......................7....... 5............... 44 Scalar Conversions ....................................0 4............................ 6..........................4.......................................1.............2........1........................1.........2.............. Types..............4........1..............................4........................ 6.. 33 5...................... 32 5...............................................................1........................... Chapter 6... State Spaces.................................................................................. 6....................................... 41 Using Addresses...............1.....5......4....... 32 Texture State Space (deprecated) .................................... 43 6.......................... 38 Initializers ...8........ 6........................................................................................... 27 Register State Space ..................................... 28 Special Register State Space ... 47 Chapter 7.............1........................ 44 Rounding Modifiers ..... 39 Parameterized Variable Names ...... 6......................................................................................................1...3........... 30 Shared State Space...........................4.......... 39 5.................................................................... Types ..................................4........................ 5................................ 41 6...........................................................1...........................................................6.............................. 41 Source Operands....... Operand Costs ...... Arrays....................1... 5.................5.................... and Vectors .............................4.......... 43 Vectors as Operands .................................. 5...................6...........2................... Type Conversion...................... Abstracting the ABI ......................................................................................................................3.. 42 Addresses as Operands ...4................................................ Summary of Constant Expression Evaluation Rules .... 27 5.......................2.................................................... 5........................... 33 Restricted Use of Sub-Word Sizes .........

.................9..7. 60 8.........................3................ 10.. 7............................ Directives ..................7............................................ Special Registers ............................................................................................. 56 Comparisons .........0 ...................................... 170 Semantic Changes and Clarifications ....... 63 Integer Arithmetic Instructions .. Instruction Set .............................................. 63 Floating-Point Instructions .......6...................... 140 Miscellaneous Instructions.....7................. 168 Chapter 11......1..7..................................... 52 Variadic functions ...................... 157 Specifying Kernel Entry Points and Functions ..... 57 Manipulating Predicates ..........7........................................................ 8............... Divergence of Threads in Control Constructs ............................................. 55 8........................... 108 Texture and Surface Instructions ...................... 8.................... 58 8...........7........... 53 Alloca ..........7.........................1...........1................................7.......................2...................................3...... 8.................................................................... 59 Operand Size Exceeding Instruction-Type Size ...7........ 81 Comparison and Selection Instructions .................5................................4.............................7...................10.... 160 Performance-Tuning Directives ...................................1.. 62 Semantics ......... 100 Logic and Shift Instructions ............................ 8..................... 172 January 24................ 62 8...................5.......................................... Chapter 9.......................................... 10..........6........... 8... 122 Control Flow Instructions .........................................................1............... Release Notes ........................................................................................3................................. 8....6....1.................................1....................... 8..........................................................................1...... Instructions ......... 104 Data Movement and Conversion Instructions ......6.... Type Information for Instructions and Operands ............... 8.............................1..................... Format and Semantics of Instruction Descriptions ...........................3................4......................... Changes from PTX 1........ 169 11....................................3..........1............................................................................. 7.................................................................................................................................. 172 Unimplemented Features Remaining ................................................ Changes in Version 2.................. 11.4............................................................ 170 New Features ................ 8........... 149 Chapter 10......... 147 8............................... 8............................................. 8..........3....................... 8.................................2........................................................... 166 Linking Directives ........................1.................................... 11..........................2.......8.................................... 11.... 132 Video Instructions ................................................................................................ 55 Predicated Execution ...................4...............................................................................................1.......2..................................7................................. 8.......................2...................... 2010 iii ..................7.1.................................. 10......... PTX Version and Target Directives .......3..........7............... 62 Machine-Specific Semantics of 16-bit Code ........ 54 Chapter 8......... 8........................ 8.. 157 10.2.............................. 8.... 10..................................... 162 Debugging Directives ................................................................................x ................................ 129 Parallel Synchronization and Communication Instructions ......... 55 PTX Instructions ...........

....0 Appendix A..................... 173 iv January 24........... 2010 ......PTX ISA Version 2....pragma Strings.................... Descriptions of ..

...................................................................................................................................... 58 Type Checking Rules ..................................... Table 8.................................................................................... 45 Floating-Point Rounding Modifiers .............................................. Table 25.... 65 Integer Arithmetic Instructions: addc .................. 64 Integer Arithmetic Instructions: sub .......................................................................................................................... 61 Integer Arithmetic Instructions: add .................. 57 Floating-Point Comparison Operators .......... Table 23....................... Table 4............ 69 Integer Arithmetic Instructions: mad24 ........ Table 18............. 71 January 24................................... Table 27.................................List of Tables Table 1.......... Table 14..cc ................................ 27 Properties of State Spaces ...... Table 30.................................................................................... 46 Integer Rounding Modifiers ............................................ Table 5......... Table 21......... Table 22.... Table 19................................................................ Table 15........................................................................................... Table 32............. Table 6...................................................... Table 31.. 28 Fundamental Type Specifiers ............................. 66 Integer Arithmetic Instructions: subc .............................................. Table 26....................... PTX Directives .............................................................................. 23 Constant Expression Evaluation Rules ........................................... 67 Integer Arithmetic Instructions: mad ....................................... 68 Integer Arithmetic Instructions: mul24 .............. 2010 v ................................................ Table 20............................................................................................................................................... 60 Relaxed Type-checking Rules for Destination Operands.............................. Table 11.............................................................. Table 2............ 59 Relaxed Type-checking Rules for Source Operands ................................................................ Table 28........... 47 Operators for Signed Integer................... 19 Predefined Identifiers ................... Table 16................. 35 Convert Instruction Precision and Format .................................................. Table 7....... Table 24........ 70 Integer Arithmetic Instructions: sad ............ 65 Integer Arithmetic Instructions: sub...... Table 17....... Table 3........ 33 Opaque Type Fields in Unified Texture Mode .... 58 Floating-Point Comparison Operators Testing for NaN ......... and Bit-Size Types ................... 20 Operator Precedence .................................. 46 Cost Estimates for Accessing State-Spaces .......................... Unsigned Integer.............. Table 10......................................................................................... Table 13.............................................cc ..................................... 57 Floating-Point Comparison Operators Accepting NaN ..................................................................................... 66 Integer Arithmetic Instructions: mul .......... 64 Integer Arithmetic Instructions: add.................. 35 Opaque Type Fields in Independent Texture Mode ................. 25 State Spaces . Table 9....................................................... Table 29.......... Table 12.................................. 18 Reserved Instruction Keywords .......

............... Table 54......................... Table 37.... Table 64........... 90 Floating-Point Instructions: abs ................ Table 69............... 91 Floating-Point Instructions: min ................................... Table 51......................................... 88 Floating-Point Instructions: div ...... 82 Floating-Point Instructions: testp ......................................................... Table 47.... 103 Comparison and Selection Instructions: slct ......... Table 45... Table 35..................................................................................................................................................................... 99 Comparison and Selection Instructions: set ............................................................................ Table 63...................................................................................................................................................... Table 56............. Table 42....................... 78 Integer Arithmetic Instructions: prmt ................. Table 41........... 92 Floating-Point Instructions: rcp ................................................ 84 Floating-Point Instructions: sub .............. Table 61.................. 83 Floating-Point Instructions: copysign ....................................................... Table 44................... 73 Integer Arithmetic Instructions: max ........ 94 Floating-Point Instructions: rsqrt .... 85 Floating-Point Instructions: mul ................... Table 46................................................. Table 62........................................................................................................................ Table 59......................... 72 Integer Arithmetic Instructions: neg ................................................................................................................... 92 Floating-Point Instructions: max ......................... Table 65........................ Table 66... 98 Floating-Point Instructions: ex2 .................................................................................................... Integer Arithmetic Instructions: div ................................................................................................................................ 71 Integer Arithmetic Instructions: rem .... Table 38........................................... Table 53........... 2010 ............................ 101 Comparison and Selection Instructions: setp ............... Table 40................................................... Table 43................................................ 97 Floating-Point Instructions: lg2 ............................................................... Table 52.......................................... 73 Integer Arithmetic Instructions: popc ... Table 60.. 87 Floating-Point Instructions: mad ... 74 Integer Arithmetic Instructions: bfind ....................................................... 95 Floating-Point Instructions: sin ............................ 74 Integer Arithmetic Instructions: clz ..................................... 91 Floating-Point Instructions: neg ........................................ Table 39.............................................. 77 Integer Arithmetic Instructions: bfi .................................................................................................. 76 Integer Arithmetic Instructions: bfe ................................. Table 34.................... Table 48........... Table 50........................................ 83 Floating-Point Instructions: add .... 96 Floating-Point Instructions: cos ..................... Table 57.............. Table 58............................0 Table 33. 102 Comparison and Selection Instructions: selp .............................................. Table 36................................................ 75 Integer Arithmetic Instructions: brev ................................ 72 Integer Arithmetic Instructions: min ................................... 79 Summary of Floating-Point Instructions ............................................................... 103 vi January 24.............. 86 Floating-Point Instructions: fma ................... Table 55................................. Table 67.......................................................PTX ISA Version 2....................................... 93 Floating-Point Instructions: sqrt ........ Table 49............................................. Table 68................................................... 71 Integer Arithmetic Instructions: abs .................................................................

.................................. 131 Control Flow Instructions: exit ..................................... Table 97.............................. 111 Data Movement and Conversion Instructions: mov ................. 116 Data Movement and Conversion Instructions: prefetch...... 129 Control Flow Instructions: bra ...................................... vmax ............... Table 100......................... 119 Data Movement and Conversion Instructions: cvta ............................................... Table 104... Table 80......... 118 Data Movement and Conversion Instructions: isspacep ............... 128 Control Flow Instructions: { } ...... Table 88......... 2010 vii ........................................................ Table 103......... Table 101........ Table 90................. 139 Video Instructions: vadd.... 107 Cache Operators for Memory Load Instructions ........................................ 106 Logic and Shift Instructions: cnot .............. 105 Logic and Shift Instructions: xor ..... Table 77................................................ 113 Data Movement and Conversion Instructions: ldu ....... 107 Logic and Shift Instructions: shr ............................... Table 79............. Table 75.................. 129 Control Flow Instructions: @ . Table 102....................................................... Table 74................... Table 91............ 106 Logic and Shift Instructions: not ....... 130 Control Flow Instructions: ret ............. 143 January 24................................ Table 72..................... Logic and Shift Instructions: and ............................................................................................. 106 Logic and Shift Instructions: shl ..... Table 87................ Table 83............. Table 89................ 105 Logic and Shift Instructions: or .................................... 137 Parallel Synchronization and Communication Instructions: vote ........................................................ 120 Texture and Surface Instructions: tex ................................... 126 Texture and Surface Instructions: sured......................................................................................... 124 Texture and Surface Instructions: suld ............................................... 133 Parallel Synchronization and Communication Instructions: membar .............................................Table 70...................... 134 Parallel Synchronization and Communication Instructions: atom ....................... Table 71............................................. Table 95.............................................. 125 Texture and Surface Instructions: sust ................................ vsub.. Table 78................................................ Table 92............ Table 98..... 112 Data Movement and Conversion Instructions: ld ........................................... vmin.......................................................... Table 93..... Table 106............................... 110 Data Movement and Conversion Instructions: mov ..... 131 Parallel Synchronization and Communication Instructions: bar .............................................................. 130 Control Flow Instructions: call .............. Table 84.......................................... 109 Cache Operators for Memory Store Instructions .. Table 86............... 135 Parallel Synchronization and Communication Instructions: red .......................... Table 96............................................................. Table 82....................................... 115 Data Movement and Conversion Instructions: st .. 123 Texture and Surface Instructions: txq .......... 127 Texture and Surface Instructions: suq ...................................................... 142 Video Instructions: vshl.. vabsdiff.............................. Table 81............................................... Table 73....................................................... Table 76........... Table 99.......... Table 85................................................................................. vshr ............................. Table 105.......... Table 94........................................... prefetchu .... 119 Data Movement and Conversion Instructions: cvt ...............................

............... Video Instructions: vmad . 146 Miscellaneous Instructions: trap ............. 156 Special Registers: %clock64 ........... 167 Debugging Directives: ......................... 153 Special Registers: %gridid ...................................................................................... 154 Special Registers: %lanemask_le ........ 147 Miscellaneous Instructions: pmevent........................ 167 Debugging Directives: ...... 160 Kernel and Function Directives: ..... Table 134.........................................................................pragma .................................................. Table 114.............. 151 Special Registers: %ctaid .................. Table 138................entry.............. %pm1........... 151 Special Registers: %warpid ........ Table 111....... 167 Linking Directives: ............... Table 140......... %pm2..................................................................... 153 Special Registers: %lanemask_eq .................................................................. 161 Performance-Tuning Directives: ....version... Table 127........................ Table 122........................................ Table 118.......................... Table 124....maxnctapersm (deprecated) ...... Table 113.................... Table 123................ 151 Special Registers: %nwarpid .............. Table 137..........................PTX ISA Version 2.............................. 164 Performance-Tuning Directives: ............ %pm3 ........................................... Table 139................... Table 133................ Table 125. 152 Special Registers: %nctaid .................................................................................................... 168 viii January 24.............................................. 147 Special Registers: %tid .................................minnctapersm ......................................................................................... 165 Debugging Directives: @@DWARF ................................. Table 116........................... Table 128...... 150 Special Registers: %ntid ........ 144 Video Instructions: vset................................................................section ....................... 156 Special Registers: %pm0...................... Table 136....................................loc .................................. 158 Kernel and Function Directives: .............................................................................................. 2010 ......maxntid .............................. Table 112.................................................................. 154 Special Registers: %lanemask_ge ...... Table 109........................... Table 142......................................................... 150 Special Registers: %laneid .......... 155 Special Registers: %clock ......................... Table 132.......................................................................................................... Table 126................................ 164 Performance-Tuning Directives: .....target ......................... Table 121... Table 110.... Table 119.............................. Table 129..........................0 Table 107......................... 163 Performance-Tuning Directives: .................extern.......... Table 143.............................................................. 157 PTX File Directives: . 153 Special Registers: %nsmid .. Table 108....................................... Table 130...................................................................... 152 Special Registers: %smid .................. 155 Special Registers: %lanemask_gt ........................... Table 115............................................................................................................ 163 Performance-Tuning Directives: .. 166 Debugging Directives: ............... Table 120. Table 135.................. Table 117...........................................................func ........................maxnreg .................... 154 Special Registers: %lanemask_lt ...............................file ............................................................................... Table 141..................................... 156 PTX File Directives: ................. 147 Miscellaneous Instructions: brkpt . Table 131....................................................................................................................

. 2010 ix ............................ 168 Pragma Strings: “nounroll” ...................................visible.......................................... 173 January 24............. Linking Directives: ........................Table 144...... Table 145......................

PTX ISA Version 2. 2010 .0 x January 24.

from general signal processing or physics simulation to computational finance or computational biology. PTX exposes the GPU as a data-parallel computing device. 1. which are optimized for and translated to native target-architecture instructions. image and media processing applications such as post-processing of rendered images. high-definition 3D graphics. PTX programs are translated at install time to the target hardware instruction set. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. image scaling. Because the same program is executed for each data element. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. In fact. the memory access latency can be hidden with calculations instead of big data caches. and pattern recognition can map image blocks and pixels to parallel processing threads. the programmable GPU has evolved into a highly parallel. Similarly. there is a lower requirement for sophisticated flow control. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. Introduction This document describes PTX. 2010 1 . Many applications that process large data sets can use a data-parallel programming model to speed up the computations. Data-parallel processing maps data elements to parallel processing threads. January 24.1. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. multithreaded. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. many-core processor with tremendous computational horsepower and very high memory bandwidth. video encoding and decoding. PTX defines a virtual machine and ISA for general purpose parallel thread execution. 1.Chapter 1. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. stereo vision. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. and because it is executed on many data elements and has high arithmetic intensity.2.

f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Achieve performance in compiled applications comparable to native GPU performance.sat modifiers. and all PTX 1.3. Legacy PTX 1. 2010 . barrier.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. • • • 2 January 24.f32.x features are supported on the new sm_20 target.rm and . performance kernels. addition of generic addressing to facilitate the use of general-purpose pointers. and the introduction of many new instructions. The mad.f32 requires sm_20.1. and architecture tests. Single-precision add. The changes from PTX ISA 1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. and mul now support . When code compiled for sm_1x is executed on sm_20 devices. fma.x.f32 maps to fma. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. The main areas of change in PTX 2.0 PTX ISA Version 2. atomic. Facilitate hand-coding of libraries.0 is in improved support for the IEEE 754 floating-point standard.x code will continue to run on sm_1x targets as well. PTX ISA Version 2. 1. A single-precision fused multiply-add (fma) instruction has been added.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 is a superset of PTX 1. including integer. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.PTX ISA Version 2. Provide a common source-level ISA for optimizing code generators and translators.f32 for sm_20 targets. reduction. The fma. The mad.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.rp rounding modifiers for sm_20 targets.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.rn. Most of the new features require a sm_20 target. surface. memory. A “flush-to-zero” (.f32 and mad. Provide a machine-independent ISA for C/C++ and other compilers to target. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. and video instructions.f32 instruction also supports . sub.ftz) modifier may be used to enforce backward compatibility with sm_1x. PTX 2. which map PTX to specific target machines.3.0 are improved support for IEEE 754 floating-point operations. Both fma. 1. Instructions marked with .f32 require a rounding modifier for sm_20 targets. mad. Improved Floating-Point Support A main area of change in PTX 2. Provide a code distribution ISA for application and middleware developers.ftz and .

so recursion is not yet supported.zero.3..0. • Taken as a whole.3. Support for an Application Binary Interface Rather than expose details of a particular calling convention.4. These are indicated by the use of a rounding modifier and require sm_20. PTX 2. prefetchu.3. .0 provides a slightly higher-level abstraction and supports multiple ABI implementations. In PTX 2. special registers. Introduction • Single. NOTE: The current version of PTX does not implement the underlying. e.g.3. i. st. local. allowing memory instructions to access these spaces without needing to specify the state space. isspacep.clamp and . See Section 7 for details of the function definition and call syntax needed to abstract the ABI.0. rcp. A new cvta instruction has been added to convert global. 1.Chapter 1. cvta. Instructions prefetch and prefetchu have been added. Instruction cvta for converting global. for prefetching to specified level of memory hierarchy. Generic Addressing Another major change is the addition of generic addressing. local. stack-based ABI. these changes bring PTX 2. New Instructions The following new instructions. 2010 3 . and directives are introduced in PTX 2. and sust. 1. and shared addresses to generic addresses. instructions ld. and shared state spaces.e. an address that is the same across all threads in a warp.and double-precision div. suld. Surface instructions support additional clamp modifiers. stack layout. 1. and sqrt with IEEE 754 compliant rounding have been added. Surface Instructions • • Instruction sust now supports formatted surface stores.0 closer to full compliance with the IEEE 754 standard. and shared addresses to generic address and vice-versa has been added. local. Cache operations have been added to instructions ld. Generic addressing unifies the global. and vice versa. January 24. Instructions testp and copysign have been added. and Application Binary Interface (ABI). Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.2. prefetch. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. atom. st. ldu. and red now support generic addressing.

vote. %lanemask_{eq.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.u32 and bar. has been added. Instructions bar. Barrier Instructions • • A system-level membar instruction. %clock64. bar now supports an optional thread count and register operands. .red}.ballot.shared have been extended to handle 64-bit data types for sm_20 targets. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A new directive.arrive instruction has been added.or}.{and.red.lt.red}.popc.b32.add. 4 January 24.red.sys. and Vote Instructions • • • New atomic and reduction instructions {atom. has been added. A “vote ballot” instruction.section. Other Extensions • • • Video instructions (includes prmt) have been added. A bar. membar. 2010 . Instructions {atom.ge. Reduction.pred have been added.gt} have been added.f32 have been added. bfi bit field extract and insert popc clz Atomic. New special registers %nsmid.PTX ISA Version 2.le.

Chapter 7 describes the function and call syntax.Chapter 1. January 24.4. 2010 5 . types. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 11 provides release notes for PTX Version 2. Introduction 1. Chapter 10 lists the assembly directives supported in PTX.0. Chapter 4 describes the basic syntax of the PTX language. Chapter 8 describes the instruction set. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 9 lists special registers. calling convention. Chapter 6 describes instruction operands. and PTX support for abstracting the Application Binary Interface (ABI). and variable declarations. Chapter 5 describes state spaces.

PTX ISA Version 2. 2010 .0 6 January 24.

x. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. and tid. 2D. January 24. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. 2D. compute addresses. and results across the threads of the CTA. More precisely. A cooperative thread array. It operates as a coprocessor to the main CPU. and select work to perform.1. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. or 3D shape specified by a three-element vector ntid (with elements ntid. Each CTA has a 1D.y. Threads within a CTA can communicate with each other. work. Programs use a data parallel decomposition to partition inputs. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.z). compute-intensive portions of applications running on the host are off-loaded onto the device. (with elements tid. or 3D CTA. or host: In other words.x.z) that specifies the thread’s position within a 1D. but independently on different data. To coordinate the communication of the threads within the CTA. To that effect. or CTA. is an array of threads that execute a kernel concurrently or in parallel. 2. Cooperative thread arrays (CTAs) implement CUDA thread blocks. 2. can be isolated into a kernel function that is executed on the GPU as many different threads. Programming Model 2.2.1. one can specify synchronization points where threads wait until all threads in the CTA have arrived. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. Each CTA thread uses its thread identifier to determine its assigned role. data-parallel.2. tid.Chapter 2. and ntid. Each thread has a unique thread identifier within the CTA.y. The vector ntid specifies the number of threads in each CTA dimension. ntid. a portion of an application that is executed many times. assign specific input and output positions. The thread identifier is a three-element vector tid. 2010 7 .

PTX ISA Version 2. Multiple CTAs may execute concurrently and in parallel. 2. so that the total number of threads that can be launched in a single kernel invocation is very large. 2010 . %ntid. Threads may read and use these values through predefined. 8 January 24. %nctaid. The warp size is a machine-dependent constant. Each grid also has a unique temporal grid identifier (gridid). multiple-thread) fashion in groups called warps. depending on the platform. 2D . which may be used in any instruction where an immediate operand is allowed. a warp has 32 threads. or sequentially. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. A warp is a maximal subset of threads from a single CTA. %ctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Some applications may be able to maximize performance with knowledge of the warp size. so PTX includes a run-time immediate constant. read-only special registers %tid.2. However. and %gridid. WARP_SZ.0 Threads within a CTA execute in SIMT (single-instruction. such that the threads execute the same instructions at the same time. or 3D shape specified by the parameter nctaid. because threads in different CTAs cannot communicate and synchronize with each other. This comes at the expense of reduced thread communication and synchronization. Typically. CTAs that execute the same kernel can be batched together into a grid of CTAs. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). The host issues a succession of kernel invocations to the device. Threads within a warp are sequentially numbered.2. Each grid of CTAs has a 1D.

1) Thread (0. 1) Thread (0. 1) Thread (1. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. Thread Batching January 24. 2010 9 . Figure 1. 0) Thread (3. 0) Thread (0. 0) CTA (2.Chapter 2. 2) Thread (3. 1) Thread (3. 2) Thread (1. 1) CTA (2. 1) CTA (1. 0) Thread (4. 0) CTA (1. 0) CTA (0. A grid is a set of CTAs that execute independently. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (2. 1) Thread (2. 0) Thread (1. 1) Grid 2 Kernel 2 CTA (1. 1) Thread (4. 2) Thread (4. 0) Thread (2.

The global. Each thread has a private local memory. as well as data filtering. Finally. constant. all threads have access to the same global memory. Both the host and the device maintain their own local memory.0 2. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.3. and texture memory spaces are optimized for different memory usages. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. referred to as host memory and device memory. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. for more efficient transfer. and texture memory spaces are persistent across kernel launches by the same application. Texture memory also offers different addressing modes. 10 January 24. The device memory may be mapped and read or written by the host. The global. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. respectively. 2010 . or. for some specific data formats. constant.PTX ISA Version 2.

1) Block (2. 2010 11 . 0) Block (1. 2) Figure 2. 0) Block (1. 1) Block (1. 0) Block (0. 1) Block (1. 0) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 1) Block (0.Chapter 2. 1) Grid 1 Global memory Block (0. 0) Block (2. Memory Hierarchy January 24. 2) Block (1.

2010 .0 12 January 24.PTX ISA Version 2.

new blocks are launched on the vacated multiprocessors. The multiprocessor creates. disabling threads that are not on that path. As thread blocks terminate. so full efficiency is realized when all threads of a warp agree on their execution path. 2010 13 . each warp contains threads of consecutive.1. allowing. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. the first parallel thread technology. a cell in a grid-based computation). At every instruction issue time. The threads of a thread block execute concurrently on one multiprocessor. The multiprocessor SIMT unit creates. the threads converge back to the same execution path.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. The multiprocessor maps each thread to one scalar processor core. When a host program invokes a kernel grid. a multithreaded instruction unit. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. manages. the warp serially executes each branch path taken. January 24. Parallel Thread Execution Machine Model 3. and executes threads in groups of parallel threads called warps. it splits them into warps that get scheduled by the SIMT unit. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image.Chapter 3. and on-chip shared memory. To manage hundreds of threads running several different programs. different warps execute independently regardless of whether they are executing common or disjointed code paths. and when all paths complete. A warp executes one common instruction at a time. and executes concurrent threads in hardware with zero scheduling overhead. a voxel in a volume. A multiprocessor consists of multiple Scalar Processor (SP) cores. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. increasing thread IDs with the first warp containing thread 0. and each scalar thread executes independently with its own instruction address and register state. manages. Branch divergence occurs only within a warp. The way a block is split into warps is always the same. for example. When a multiprocessor is given one or more thread blocks to execute. schedules. (This term originates from weaving. multiple-thread). If threads of a warp diverge via a data-dependent conditional branch. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). the multiprocessor employs a new architecture we call SIMT (single-instruction. It implements a single-instruction barrier synchronization.

How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. require the software to coalesce loads into vectors and manage divergence manually. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. but the order in which they occur is undefined. • The local and global memory spaces are read-write regions of device memory and are not cached. which is a read-only region of device memory.PTX ISA Version 2. Vector architectures. however. A multiprocessor can execute as many as eight thread blocks concurrently. As illustrated by Figure 3. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. the number of serialized writes that occur to that location and the order in which they occur is undefined. If an atomic instruction executed by a warp reads. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. on the other hand. the programmer can essentially ignore the SIMT behavior. but one of the writes is guaranteed to succeed. A key difference is that SIMD vector organizations expose the SIMD width to the software. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. and writes to the same location in global memory for more than one of the threads of the warp. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. scalar threads.0 SIMT architecture is akin to SIMD (Single Instruction. the kernel will fail to launch. For the purposes of correctness. modify. whereas SIMT instructions specify the execution and branching behavior of a single thread. write to that location occurs and they are all serialized. In contrast with SIMD vector machines. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. as well as data-parallel code for coordinated threads. which is a read-only region of device memory. 2010 . modifies. 14 January 24. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. If there are not enough registers or shared memory available per multiprocessor to process at least one block. In practice. SIMT enables programmers to write thread-level parallel code for independent. each read.

Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3. 2010 15 . Figure 3.

PTX ISA Version 2. 2010 .0 16 January 24.

and using // to begin a comment that extends to the end of the current line. #ifdef. using non-nested /* and */ for comments that may span multiple lines. The following are common preprocessor directives: #include. Lines are separated by the newline character (‘\n’). Each PTX file must begin with a . followed by a . #if.target directive specifying the target architecture assumed. All whitespace characters are equivalent. whitespace is ignored except for its use in separating tokens in the language. Source Format Source files are ASCII text. #define. The C preprocessor cpp may be used to process PTX source files. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.Chapter 4. See Section 9 for a more information on these directives. Comments Comments in PTX follow C/C++ syntax. 4.2. PTX is case sensitive and uses lowercase for keywords. 2010 17 .1. #line. 4.version directive specifying the PTX language version. #else. Comments in PTX are treated as whitespace. Lines beginning with # are preprocessor directives. Pseudo-operations specify symbol and addressing management. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. January 24. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #endif. Syntax PTX programs are a collection of text source files.

. All instruction keywords are reserved tokens in PTX.version .reg .1.f32 r2. 2. r2.f32 array[N]. 18 January 24.3.extern . written as @!p. so no conflict is possible with user-defined identifiers. where p is a predicate register. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.global.b32 r1.global .PTX ISA Version 2. Examples: . mov.local . 0.3. Instructions have an optional guard predicate which controls conditional execution.pragma .file PTX Directives .shared .minnctapersm . .b32 r1.entry .maxntid .target . 2010 .sreg . constant expressions. Instruction keywords are listed in Table 2. r2. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. r1. r2.loc .reg . shl.3. %tid.func .section .global start: . Directive Statements Directive keywords begin with a dot.0 4.tex .b32 add.b32 r1.maxnreg .x. The guard predicate may be optionally negated.align . Operands may be register variables. The destination operand is first. Table 1. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. and is written as @p.param .const . ld.5.2. The guard predicate follows the optional label and precedes the opcode. Statements begin with an optional label and end with a semicolon. or label names. and terminated with a semicolon.visible 4. array[r1].maxnctapersm . address expressions. Statements A PTX statement is either a directive or an instruction. followed by source operands.

Syntax Table 2. 2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

digits. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. underscore.g. listed in Table 3. or percentage character followed by one or more letters. or they start with an underscore. PTX allows the percentage sign as the first character of an identifier.4. underscore. except that the percentage sign is not allowed. 2010 . or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. Table 3.PTX ISA Version 2. The percentage sign can be used to avoid name conflicts.0 4. e. PTX predefines one constant and a small number of special registers that begin with the percentage sign. …. digits. %pm3 WARP_SZ 20 January 24. or dollar characters. Many high-level languages such as C and C++ follow similar rules for identifier names. between user-defined variable names and compiler-generated names. dollar. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.

Syntax 4. Type checking rules remain the same for integer. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.1.2. i. octal. and bit-size types.5. 4. To specify IEEE 754 single-precision floating point values. When used in an instruction or data initialization. i. each integer constant is converted to the appropriate size based on the data or instruction type at its use. The syntax follows that of C.. integer constants are allowed and are interpreted as in C. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.e.5. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. For predicate-type data and instructions. there is no suffix letter to specify size. the constant begins with 0d or 0D followed by 16 hex digits. 4. Constants PTX supports integer and floating-point constants and constant expressions. 0[fF]{hexdigit}{8} // single-precision floating point January 24.s64 or .s64) unless the value cannot be fully represented in . The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Integer literals may be written in decimal. floating-point. or binary notation. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. 2010 21 .5.s64 or the unsigned suffix is specified. To specify IEEE 754 doubleprecision floating point values. literals are always represented in 64-bit double-precision format.Chapter 4. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. in which case the literal is unsigned (.e. Unlike C and C++. hexadecimal. These constants may be used in data initialization and as operands to instructions. zero values are FALSE and non-zero values are TRUE.u64.u64). where the behavior of the operation depends on the operand types. Floating-point literals may be written with an optional decimal point and an optional signed exponent. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. every integer constant has type . the sm_1x and sm_20 targets have a WARP_SZ value of 32. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. the constant begins with 0f or 0F followed by 8 hex digits.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

5.f64 integer .f64 converted type constant literal + ! ~ Cast Binary (.u64 zero or non-zero same as sources use usual conversions Result Type same as source .Chapter 4.u64 .6.f64 integer integer integer integer integer int ?.f64 converted type .u64 same as 1st operand .s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 use usual conversions .f64 : .s64 . 2010 25 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 1st unchanged.s64 .u64.s64) + . Table 5.f64 use usual conversions . . Syntax 4. or .f64 use usual conversions .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 .s64 .f64 integer .u64 .s64 .s64 .u64 .u64 .s64.u64 .s64 .s64 .u64) (.f64 same as source .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. 2nd is .

2010 .PTX ISA Version 2.0 26 January 24.

defined per-thread. the kinds of resources will be common across platforms. Table 6. . All variables reside in some state space. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Name State Spaces Description Registers.param . The characteristics of a state space include its size.sreg .global . private to each thread.const . and these resources are abstracted in PTX through state spaces and data types. and level of sharing between threads. The list of state spaces is shown in Table 4. State Spaces. Addressable memory shared between threads in 1 CTA. access rights. addressability. shared by all threads. 2010 27 . read-only memory.shared . and Variables While the specific resources available in a given target GPU will vary. platform-specific. fast.tex January 24. Global memory.Chapter 5. defined per-grid. Kernel parameters. and properties of state spaces are shown in Table 5. access speed.local . Types. Shared. pre-defined. Local memory. 5. Global texture memory (deprecated). Read-only.reg .1. State Spaces A state space is a storage area with particular characteristics. or Function or local parameters. Special registers.

clock counters. 2 Accessible via ld. Registers differ from the other state spaces in that they are not fully addressable. Register State Space Registers (.local . 2010 . 32-. and performance monitoring registers.1. 16-.0 Table 7.local state space. Device function input parameters may have their address taken via mov.const . All special registers are predefined. it is not possible to refer to the address of a register. st.sreg) state space holds predefined. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . For each architecture. floating point. register variables will be spilled to memory.sreg . Address may be taken via mov instruction.1.param and st.param instruction. scalar registers have a width of 8-. Register size is restricted. 3 Accessible only via the tex instruction. i. or as elements of vector tuples..param (used in functions) . 64-. 5.global . and will vary from platform to platform. platform-specific registers. causing changes in performance. and vector registers have a width of 16-. The most common use of 8-bit registers is with ld. aside from predicate registers which are 1-bit. and thread parameters. and cvt instructions. The number of registers is limited. 1 Accessible only via the ld. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. 28 January 24. 32-.param (as input to kernel) . such as grid.reg state space) are fast storage locations. Registers may have alignment boundaries required by multi-word loads and stores. CTA.e. or 128-bits. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).param instructions. or 64-bits.tex Restricted Yes No3 5. Registers may be typed (signed integer. the parameter is then located on the stack frame and its address is in the . predicate) or untyped. When the limit is exceeded.shared . unsigned integer.2.1. Special Register State Space The special register (.reg .PTX ISA Version 2.

By convention. // load second word 5. Types. The constant memory is organized into fixed size banks. Multiple incomplete array variables declared in the same bank become aliases. where bank ranges from 0 to 10.3.global. the stack is in local memory.b32 const_buffer[]. where the size is not known at compile time. For any thread in a context. whereas local memory variables declared January 24.global to access global variables. 5.local to access local variables. results in const_buffer pointing to the start of constant bank two. This reiterates the kind of parallelism available in machines that run PTX. initialized by the host. the store operation updating a may still be in flight. as in lock-free and wait-free style programming. ld. This pointer can then be used to access the entire 64KB constant bank.local) is private memory for each thread to keep its own data.5. there are eleven 64KB banks.Chapter 5. b = b – 1. 2010 29 . all addresses are in global memory are shared. and atom. each pointing to the start address of the specified constant bank. st. Banks are specified using the . It is the mechanism by which different CTAs and different grids can communicate.b32 const_buffer[]. the bank number must be provided in the state space of the load instruction.extern . To access data in contant banks 1 through 10. For example.const) state space is a read-only memory. as it must be allocated on a perthread basis.sync instruction are guaranteed to be visible to any reads after the barrier instruction. If no bank number is given.extern . In implementations that support a stack. bank zero is used. Use ld.1. an incomplete array in bank 2 is accessed as follows: .1. Global memory is not sequentially consistent.1. Threads wait at the barrier until all threads in the CTA have arrived.global. Global State Space The global (. Constant State Space The constant (. the declaration . [const_buffer+4]. and Variables 5.b32 %r1. Local State Space The local state space (. Consider the case where one thread executes the following two assignments: a = a + 1.4. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. State Spaces.const[bank] modifier.const[2].const[2] .const[2] . It is typically standard memory with cache. Sequential consistency is provided by the bar. Module-scoped local memory variables are stored at fixed addresses.sync instruction. The size is limited. The remaining banks may be used to implement “incomplete” constant arrays (in C. bank zero is used for all statically-sized constant variables. If another thread sees the variable b change. Use ld. for example). For example. All memory writes prior to the bar. Threads must be able to do their work without waiting for other threads to do theirs.local and st.global) state space is memory that is accessible by all threads in a context. For the current devices.

For example. Values passed from the host to the kernel are accessed through these parameter variables using ld. per-kernel versus per-thread). The resulting address is in the .param state space. . Kernel Function Parameters Each kernel function definition includes an optional list of parameters. … Example: .param .entry bar ( .param . Parameter State Space The parameter (. ld. all local memory variables are stored at fixed addresses and recursive function calls are not supported.param . The kernel parameter variables are shared across all CTAs within a grid.0 and requires target architecture sm_20. Example: . [%ptr]. The use of parameter state space for device function parameters is new to PTX ISA version 2.param instructions.6.b32 len ) { . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. Therefore.1.reg .param instructions. read-only variables declared in the .param. 2010 . ld.align 8 . 5. (2a) to declare formal input and return parameters for device functions called from within kernel execution. PTX code should make no assumptions about the relative locations or ordering of .param state space and is accessed using ld.u32 %n.1.u32 %n. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. ld. len.u32 %ptr. These parameters are addressable.6. mov.entry foo ( .u32 %ptr. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). .reg . The address of a kernel parameter may be moved into a register using the mov instruction.param) state space is used (1) to pass input arguments from the host to the kernel. No access protection is provided between parameter and global space in this case.param space.b32 N.param.reg .param space variables. Note that PTX ISA versions 1. Similarly.b8 buffer[64] ) { .u32 %n. in some implementations kernel parameters reside in global memory.param. [buffer]. … 30 January 24.f64 %d.x supports only kernel function parameters in . %n. [N].f64 %d.1. Note: The location of parameter space is implementation specific. device function parameters were previously restricted to the register state space. typically for passing large structures by value to a function. 5.0 within a function or kernel body are allocated on the stack.PTX ISA Version 2. In implementations that do not support a stack.

local instructions. [buffer+8]. In PTX. … } // code snippet from the caller // struct { double d.f64 %d.reg . and so the address will be in the . passed to foo … . Typically.s32 %y. it is illegal to write to an input parameter or read from a return parameter. } mystruct. dbl.param and function return parameters may be written using st. .f64 %d. .param .Chapter 5. is flattened. Function input parameters may be read via ld. State Spaces.b32 N. [buffer]. the caller will declare a locally-scoped . ld.param. the address of a function input parameter may be moved into a register using the mov instruction. ld.f64 [mystruct+0]. a byte array in parameter space is used.b8 mystruct. (4.b8 buffer[12] ) { . Types. . st. int y. It is not possible to use mov to get the address of a return parameter or a locally-scoped . … See the section on function call syntax for more details. int y. such as C structures larger than 8 bytes.local and st.reg . which declares a .param . .0 extends the use of parameter space to device function parameters. mystruct). The most common use is for passing objects by value that do not fit within a PTX register. x.2.param byte array variable that represents a flattened C structure or union.align 8 .reg .6. January 24.param space variable. call foo. This will be passed by value to a callee.1.s32 [mystruct+8].f64 dbl.param space is also required whenever a formal parameter has its address taken within the called function. … st. Aside from passing structures by value.s32 x. . and Variables 5.local state space and is accessed via ld.param formal parameter having the same size and alignment as the passed argument.param. Note that the parameter will be copied to the stack if necessary. In this case.func foo ( .param.param.s32 %y.reg . .reg . Example: // pass object of type struct { double d. }.param.align 8 . 2010 31 . Device Function Parameters PTX ISA version 2.

0 5.shared to access shared variables.7. where texture identifiers are allocated sequentially beginning with zero.tex) state space is global memory accessed via the texture instruction.texref variables in the . and programs should instead reference texture memory through variables of type .u32 .8. It is shared by all threads in a context. Texture memory is read-only. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).tex variables are required to be defined in the global scope. Texture State Space (deprecated) The texture (. Use ld. A texture’s base address is assumed to be aligned to a 16-byte boundary. See Section 5. tex_f.global . tex_d.tex .tex .tex .tex . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Multiple names may be bound to the same physical texture identifier.u32 .7.texref. For example.global state space. 5.tex directive will bind the named texture memory variable to a hardware texture identifier. and variables declared in the . Another is sequential access from sequential threads.texref type and Section 8. tex_d.u32 tex_a.1. The .tex . The . Shared State Space The shared (. Physical texture resources are allocated on a per-module granularity.u64.tex state space are equivalent to module-scoped . where all threads read from the same address. An address in shared memory can be read and written by any thread in a CTA. The texture name must be of type . 32 January 24. Shared memory typically has some optimizations to support the sharing.u32 .u32 or . is equivalent to .shared) state space is a per-CTA region of memory for threads in a CTA to share data.shared and st. One example is broadcast.PTX ISA Version 2.u32 tex_a. An error is generated if the maximum number of physical resources is exceeded.3 for the description of the .6 for its use in texture instructions. a legacy PTX definitions such as . tex_c.tex directive is retained for backward compatibility.1. 2010 . Example: . and .texref tex_a.

. . needed to fully specify instruction behavior.s8.2.2.s32. Two fundamental types are compatible if they have the same basic type and are the same size.2. Restricted Use of Sub-Word Sizes The . st. st.u32.s8. The same typesize specifiers are used for both variable definitions and for typing instructions.f32 and . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. .1.Chapter 5. . the fundamental types reflect the native data types supported by the target architectures. stored. or converted to other types and sizes.f64 types. A fundamental type specifies both a basic type and a size. . and Variables 5.f64 types. State Spaces.f32. . so their names are intentionally short. Types.f64 . ld.f16 floating-point type is allowed only in conversions to and from .u8. and instructions operate on these types. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers .s64 . . In principle.b8 instruction types are restricted to ld.2.b32. January 24.f16. Fundamental Types In PTX. For convenience. Operand types and sizes are checked against instruction types for compatibility. 5. .u8. Types 5. The .f32 and . and . and cvt instructions. 2010 33 . The bitsize type is compatible with any fundamental type having the same size. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. . Signed and unsigned integer types are compatible if they have the same size.b16.b64 . . Register variables are always of a fundamental type. so that narrow values may be loaded. stored. and converted using regular-width registers. but typed variables enhance program readability and allow for better operand type checking.u16. All floating-point instructions operate only on .s16.u64 . . For example. . The following table lists the fundamental type specifiers for each basic type: Table 8.pred Most instructions have one or more type specifiers.b8. all variables (aside from predicates) could be declared using only bit-size types.

{u32. sust. 2010 . and surface descriptor variables. and de-referenced by texture and surface load. In independent mode the fields of the . suq). but the pointer cannot otherwise be treated as an address.u64} reg. Retrieving the value of a named member via query instructions (txq. opaque_var. .. since these properties are defined by . PTX has two modes of operation. and . For working with textures and samplers.texref type that describe sampler properties are ignored. Creating pointers to opaque variables using mov. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. accessing the pointer with ld and st instructions. 34 January 24. Texture. store.samplerref variables. texture and sampler information each have their own handle. suld. In the independent mode. field ordering. i.0 5. In the unified mode.3.e. but all information about layout. Sampler.texref. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. sured). or performing pointer arithmetic will result in undefined results. and query instructions. base address.PTX ISA Version 2. allowing them to be defined separately and combined at the site of usage in the program.samplerref. The three built-in types are . The following tables list the named members of each type for unified and independent texture modes. and overall size is hidden to a PTX program. hence the term “opaque”. or surfaces via texture and surface load/store instructions (tex. samplers. the resulting pointer may be stored to and loaded from memory. passed as a parameter to functions. Referencing textures. These types have named fields similar to structures. texture and sampler information is accessed through a single .texref handle. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. and Surface Types PTX includes built-in “opaque” types for defining texture. sampler.surfref.

1 nearest.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Types. clamp_to_border N/A N/A N/A N/A N/A . 1 ignored ignored ignored ignored . clamp_to_border 0.samplerref values N/A N/A N/A N/A nearest. clamp_to_edge. and Variables Table 9. clamp_ogl. State Spaces. mirror.texref values in elements in elements in elements 0. linear wrap.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_ogl. clamp_to_edge. linear wrap. 2010 35 . Member width height depth Opaque Type Fields in Unified Texture Mode .texref values .Chapter 5. mirror. Member width height depth Opaque Type Fields in Independent Texture Mode .

filter_mode = nearest }.global . 2010 . . . the types may be initialized using a list of static expressions assigning values to the named members.global .PTX ISA Version 2. At module scope.samplerref tsamp1 = { addr_mode_0 = clamp_to_border.texref tex1.surfref my_surface_name.global .param state space. When declared at module scope.global state space. Example: . 36 January 24.texref my_texture_name. these variables must be in the . Example: .global . As kernel parameters. .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. these variables are declared in the .global .samplerref my_sampler_name.

u32 loc. Predicate variables may only be declared in the register state space. Every variable must reside in one of the state spaces enumerated in the previous section. Three-element vectors may be handled by using a . vector variables are aligned to a multiple of their overall size (vector length times base-type size). // a length-4 vector of floats .v4.pred p.v2. Vectors must be based on a fundamental type. // a length-4 vector of bytes By default.b8 v.f32 V.reg . 1.f32 v0. Types. Vectors Limited-length vector types are supported. its name. 5. and they may reside in the register space.global . and Variables 5.v4 . PTX supports types for simple aggregate objects such as vectors and arrays. textures.4.1. .s32 i. Variables In PTX. a variable declaration describes both the variable’s type and its state space.f32 bias[] = {-1.global .Chapter 5.reg . A variable declaration names the space in which the variable resides. Examples: . // a length-2 vector of unsigned ints .v1. Examples: .struct float4 coord.0. 0.v2 .v3 }.v4 . . 0}.v4 .4.shared . . . In addition to fundamental types. State Spaces.v4. This is a common case for three-dimensional grids. an optional initializer.v4 vector.u8 bg[4] = {0. r.global .f32 accel.f64 is not allowed. // typedef .2. an optional array size. where the fourth element provides padding.v2 or . .global . etc. Variable Declarations All storage for data is specified with variable declarations.const . Vectors cannot exceed 128-bits in length. and an optional fixed address for the variable. 5.struct float4 { . for example. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. .reg .global .4. q. its type and size.u16 uv. January 24. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . .0}. 2010 37 . 0.

.global . Variables that hold addresses of variables or instructions should be of type . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.shared .05.. A scalar takes a single value.1.f32 blur_kernel[][] = {{. 5. or is left empty. // address of rgba into ptr Currently. Initializers are allowed for all types except . 19*19 (361) halfwords are reserved (722 bytes). {0.0}. Variable names appearing in initializers represent the address of the variable.1.s32 offset[][] = { {-1.4. Here are some examples: . 38 January 24. {1..s32 n = 10.PTX ISA Version 2. label names appearing in initializers represent the address of the next instruction following the label. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.0. 1} }..{. where the variable name is followed by an equals sign and the initial value or values for the variable.global . For the kernel declaration above. The size of the array specifies how many elements should be reserved. To declare an array.global .0.u32 or . 0}. this can be used to initialize a jump table to be used with indirect branches or calls. -1}.0}.0.3.0.4.f16 and . {0.pred.local ..05}.global .0}}. .u8 rgba[3] = {{1.4. Similarly.1}. 2010 . .u64.b32 ptr = rgba.v4 .05}}.05.1.1. Array Declarations Array declarations are provided to allow the programmer to reserve space.u8 mailbox[128].{.0 5..global . {0. . The size of the dimension is either a constant expression. {0.4. variable initialization is supported only for constant and global state spaces. . being determined by an array initializer. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).u16 kernel[19][19]. 0}. this can be used to statically initialize a pointer to a variable. Examples: .1. .

%r99.b32 %r<100>. Rather than require explicit declaration of every name. . not for individual elements. January 24.0}.0. . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. nor are initializers permitted. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. it is quite common for a compiler frontend to generate a large number of register names. and may be preceded by an alignment specifier. The default alignment for scalar and array variables is to a multiple of the base-type size. 2010 39 .4. // declare %r0. Alignment is specified using an optional . of .. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space.0..0. say one hundred. Types. Parameterized Variable Names Since PTX supports virtual registers. Array variables cannot be declared this way. %r1. named %r0.Chapter 5. For arrays.2.5. ….0.reg . For example. suppose a program uses a large number.6.b8 bar[8] = {0. State Spaces. 5.b32 variables.const . alignment specifies the address alignment for the starting address of the entire array. Examples: // allocate array at 4-byte aligned address.0. These 100 register variables can be declared as follows: .align byte-count specifier immediately following the state-space specifier. The variable will be aligned to an address which is an integer multiple of byte-count.4. %r1.. The default alignment for vector variables is to a multiple of the overall vector size. Elements are bytes.align 4 . and Variables 5.

PTX ISA Version 2.0 40 January 24. 2010 .

s. st. r. Instructions ld and st move data from/to addressable state spaces to/from registers.Chapter 6. . as its job is to convert from nearly any data type to any other data type (and size). Instruction Operands 6. The result operand is a scalar or vector variable in the register state space. 6. and cvt instructions copy data from one location to another. b. mov. PTX describes a load-store machine. Integer types of a common size are compatible with each other. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. The cvt (convert) instruction takes a variety of operand types and sizes. Predicate operands are denoted by the names p. the sizes of the operands must be consistent.3. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. The mov instruction copies data between registers.2. The bit-size type is compatible with every type having the same size. q. and a few instructions have additional predicate source operands. For most operations. Most instructions have an optional predicate guard that controls conditional execution. There is no automatic conversion between types. 2010 41 . Each operand type must be compatible with the type determined by the instruction template and instruction type. and c. January 24. Operand Type Information All operands in instructions have a known type from their declarations. so operands for ALU instructions must all be in variables declared in the .reg register state space. The ld. Source Operands The source operands are denoted in the instruction descriptions by the names a.1. 6.

0 6.u16 x.reg .f32 ld. Examples include pointer arithmetic and pointer comparisons.shared . Here are a few examples: . Load and store operations move data between registers and locations in addressable state spaces. .u16 r0. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. tbl. address register plus byte offset. arrays.4. .PTX ISA Version 2. and immediate address expressions which evaluate at compile-time to a constant address.v4. and vectors. . Address expressions include variable names.f32 V. Using Addresses. q.global . The syntax is similar to that used in many assembly languages. there is no support for C-style pointer arithmetic.[x]. address registers.4. r0. .reg . W. All addresses and address computations are byte-based. . . 6.s32 mov.v4 .v4 .gloal.u32 42 January 24. ld.s32 tbl[256]. p.reg . [V]. The interesting capabilities begin with addresses.f32 W. Arrays.b32 p. The mov instruction can be used to move the address of a variable into a pointer.u16 ld. The address is an offset in the state space in which the variable is declared.shared.1.reg .s32 q. [tbl+12].const . and Vectors Using scalar variables as operands is straightforward.const. 2010 . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.

4.2. Instruction Operands 6.b.global. which may improve memory performance. Elements in a brace-enclosed vector. which include mov. Rb.f32 {a.u32 s.reg . Vector loads and stores can be used to implement wide loads and stores.r. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.g.w = = = = V. .v4.d}.v4 .d}. V2.z V. or a braceenclosed list of similarly typed scalars.u32 s. . Examples are ld.w.u32 {a.f32 V.c. mov.r V. V. Rc.u32 s. Array elements can be accessed using an explicitly calculated byte address. it must be written as an address calculation prior to use.x. A brace-enclosed list is used for pattern matching to pull apart vectors. a register variable. .global.3. mov.g V.v2.f32 a. [addr+offset].y V.y.z and . or a simple “register with constant offset” expression. or by indexing into the array using square-bracket notation. b. Arrays as Operands Arrays of all types can be declared.global. // move address of a[1] into s 6. The registers in the load/store operations can be a vector. . and tex.v4. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. where the offset is a constant expression that is either added or subtracted from a register variable. c. 2010 43 . st. January 24.Chapter 6.f32 ld. If more complicated indexing is desired. a[1].x V. say {Ra.global. and the identifier becomes an address constant in the space where the array is declared.b V. and in move instructions to get the address of the label or function into a register. Here are examples: ld. [addr+offset2].c. ld. as well as the typical color fields . ld. a[N-1]. .a. Rd}.4. The size of the array is a constant in the program.a 6.4. a[0]. Vectors as Operands Vector operands are supported by a limited subset of instructions.b and .b. for use in an indirect branch or call. Vector elements can be extracted from the vector with the suffixes . .reg .4. d. Vectors may also be passed as arguments to called functions. The expression within square brackets is either a constant integer.

PTX ISA Version 2.1.5. logic. For example. and ~131. and data movement instruction must be of the same type and size.000 for f16).5. 2010 . Operands of different sizes or types must be converted prior to the operation. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.0 6. the u16 is zero-extended to s32.u16 instruction is given a u16 source operand and s32 as a destination operand. 44 January 24. 6. Type Conversion All operands to all arithmetic. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. if a cvt. except for operations where changing the size and/or type is part of the definition of the instruction.s32.

u2f = unsigned-to-float. chop = keep only low bits that fit. f2f = float-to-float. January 24. the result is extended to the destination register width after chopping. f2s = float-to-signed. cvt. 2010 45 . then sign-extend to 32-bits.u32 targeting a 32-bit register will first chop to 16-bits.Chapter 6.s16. s2f = signed-to-float. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. zext = zero-extend. For example. The type of extension (sign or zero) is based on the destination format. f2u = float-to-unsigned. Notes 1 If the destination register is wider than the destination format. Instruction Operands Table 11.

Modifier . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.0 6.5.rm . The following tables summarize the rounding modifiers.rzi . there are four integer rounding modifiers and four floating-point rounding modifiers. Rounding Modifiers Conversion instructions may specify a rounding modifier. 2010 .rni .rz . choosing even integer if source is equidistant between two integers.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.PTX ISA Version 2.rmi .2.rn . Table 12. In PTX.rpi Integer Rounding Modifiers Description round to nearest integer. Modifier .

Table 14.6. while global memory is slowest. Instruction Operands 6. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Operand Costs Operands from different state spaces affect the speed of an operation. Registers are fastest. Another way to hide latency is to issue the load instructions as early as possible. The register in a store operation is available much more quickly. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Much of the delay to memory can be hidden in a number of ways. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. 2010 47 .Chapter 6. Table 11 gives estimates of the costs of using different kinds of memory. first access is high Notes January 24.

0 48 January 24. 2010 .PTX ISA Version 2.

stack layout. the function name. 2010 49 . parameter passing. together these specify the function’s interface. or prototype. } … call foo. A function definition specifies both the interface and the body of the function. implicitly saving the return address. Abstracting the ABI Rather than expose details of a particular calling convention. In this section. execution of the call instruction transfers control to foo. support for variadic functions (“varargs”). NOTE: The current version of PTX does not implement the underlying. Execution of the ret instruction within foo transfers control to the instruction following the call. The simplest function has no parameters or return values. A function must be declared or defined prior to being called. Function declarations and definitions In PTX. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. and is represented in PTX as follows: . January 24. functions are declared and defined using the . These include syntax for function definitions. so recursion is not yet supported. Scalar and vector base-type input and return parameters may be represented simply as register variables.1. 7. stack-based ABI. A function declaration specifies an optional list of return parameters. and an optional list of input parameters. arguments may be register variables or constants. and Application Binary Interface (ABI). we describe the features of PTX needed to achieve this hiding of the ABI.func foo { … ret. function calls.func directive.Chapter 7. At the call. … Here. and memory allocated on the stack (“alloca”). and return values may be placed directly into register variables. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations.

bumpptr. [y+11].b8 [py+ 9]. .c2. Since memory accesses are required to be aligned to a multiple of the access size.f1.align 8 py[12]. consider the following C structure.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.func (. ld. [y+9].b8 [py+11].param.PTX ISA Version 2.4). In PTX. byte array in .param .param.param space memory.reg . st.param space variables are used in two ways. The . %rc1.param. For example. 50 January 24.c1. ld. 2010 .s32 x.reg .reg . (%r1. passed by value to a function: struct { double dbl.b8 c2. %rc1. st. inc_ptr.param state space is used to pass the structure by value: . c3. this structure will be flattened into a byte array.param.reg . c4.param variable y is used in function definition bar to represent a formal parameter.u32 %ptr.b8 c4. [y+0]. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .s32 out) bar (. } … call (%r1). %inc.f64 f1. a .param.b8 c1. First. st. … ld. %ptr.f64 f1. … … // computation using x.c3.param . %rc2. [y+8].reg . // scalar args in .func (.b8 . char c[4].c4.b8 [py+ 8].param. ret. Second.param.u32 %inc ) { add. st. … In this example. %rd. } { .0 Example: . [y+10].b32 c1.param.align 8 y[12]) { .f64 field are aligned.b8 [py+10]. ld. ld. . note that . py).param.reg space. %rc2. (%x.b64 [py+ 0]. c2.b8 c3. a . … st.u32 %res) inc_ptr ( .u32 %res.b8 . }.param space call (%out).param. .reg .reg .

param state space use in device functions. • • Arguments may be .param variables. a .param byte array is used to collect together fields of a structure being passed by value.param space byte array with matching type. 2.reg state space can be used to receive and return base-type scalar and vector values. For .param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. • The . This enables backend optimization and ensures that the . the corresponding argument may be either a .reg space variable with matching type and size. Abstracting the ABI The following is a conceptual way to think about the . Note that the choice of . Supporting the .reg state space in this way provides legacy support. In the case of . The following restrictions apply to parameter passing.Chapter 7. For a callee.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. size. • The . size. A . The . 4. • • • Input and return parameters may be .reg space formal parameters. In the case of . the argument must also be a . Parameters in . • • • For a callee.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. January 24. 8.g.param memory must be aligned to a multiple of 1.reg space variable of matching type and size..param argument must be declared within the local scope of the caller.param instructions used for argument passing must be contained in the basic block with the call instruction.param or . The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. In the case of . The . the corresponding argument may be either a . or 16 bytes. or constants.reg or .param variables or .param arguments. .param space formal parameters that are base-type scalar or vector variables. all st. For a caller.param space formal parameters that are byte arrays.param and ld.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. and alignment of parameters. 2010 51 . or a constant that can be represented in the type of the formal parameter. or a constant that can be represented in the type of the formal parameter.reg variables. and alignment.param state space is used to receive parameter values and/or pass return values back to the caller.param or .reg variables. Typically. For a caller.

reg state space.0. PTX 2.reg or . formal parameters may be in either . and . 52 January 24. Changes from PTX 1. and a .x In PTX ISA version 1. and there was no support for array parameters.1.0 continues to support multiple return registers for sm_1x targets. For sm_2x targets.param state space.param space parameters support arrays.x supports multiple return values for this purpose. In PTX ISA version 2. formal parameters were restricted to . Objects such as C structures were flattened and passed or returned using multiple registers.1.0 restricts functions to a single return value. PTX 1. 2010 .param byte array should be used to return objects that do not fit into a register.x. PTX 2.PTX ISA Version 2.0 7.

u32 ptr. . bra Loop.reg . call (ap). %va_end is called to free the variable argument list handle.s32 result ) maxN ( .func baz ( .reg . setp. along with the size and alignment of the next data value to be accessed.reg . iteratively access. .func (. 8. call %va_end.func (.u32 ptr.u32 align) . ) { . bra Done. 4.reg .s32 result. 0x8000000. Variadic functions NOTE: The current version of PTX does not support variadic functions. or 8 bytes.reg .b64 val) %va_arg64 (. max. variadic functions are declared with an ellipsis at the end of the input parameter list.func okay ( … ) Built-in functions are provided to initialize. maxN.b32 val) %va_arg (. ret. . In PTX.s32 val. } … call (%max). … %va_start returns Loop: @p Done: January 24.u32 sz.u32 ptr) %va_start ..reg . for %va_arg64. The function prototypes are defined as follows: .reg . 4. call (val). %va_start. maxN. %r3). Once all arguments have been processed. This handle is then passed to the %va_arg and %va_arg64 built-in functions.h headers in C. 2. .reg .func ( . N. . mov. 2010 53 . .func (.reg . %r1. 0. %va_arg. val. ctr. // default to MININT mov.u32.reg . (ap). following zero or more fixed parameters: .u32 a.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. 2. %s1. . … ) . (3.reg . .h and varargs. %s2). and end access to a list of variable arguments. In both cases.2. or 4 bytes. For %va_arg. result.reg .func %va_end (. 4).reg . the alignment may be 1.reg . To support functions with a variable number of arguments.ge p.u32 b.u32 sz. ctr.u32 align) . the size may be 1. (2.b32 ctr. %r2.reg .Chapter 7. the size may be 1. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . 2. … call (%max)..pred p.b32 result. Abstracting the ABI 7. or 16 bytes. (ap.reg .reg . PTX provides a high-level mechanism similar to the one provided by the stdarg. 4.u32 ap.u32 N.

The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.local instructions. The array is then accessed with ld. Alloca NOTE: The current version of PTX does not support alloca.3. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.reg . 2010 .PTX ISA Version 2. 54 January 24. defined as follows: . To allocate memory.0 7. a function simply calls the built-in function %alloca.reg .local and st.func ( . If a particular alignment is required.u32 ptr ) %alloca ( .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.

a.s32. opcode D. 8. B. The setp instruction writes two destination registers.1. Instruction Set 8. followed by some examples that attempt to show several possible instantiations of the instruction. // p = (a < b). C.2. opcode D. while A. opcode A. A. the D operand is the destination operand. setp. We use a ‘|’ symbol to separate multiple destination registers. B.Chapter 8. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. January 24. the semantics are described. For some instructions the destination operand is optional. and C are the source operands. A. B. In addition to the name and the format of the instruction. q = !(a < b). PTX Instructions PTX instructions generally have from zero to four operands. For instructions that create a result value. b. A. opcode D. 2010 55 .lt p|q. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register.

s32 j. n. predicate registers are virtual and have . So.s32 p.reg . This can be written in PTX as @p setp. 2010 . The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. add 1 to j To get a conditional branch or conditional function call. i. As an example.0 8. … // compare i to n // if false. add.3. 1. predicate registers can be declared as . Instructions without a guard predicate are executed unconditionally.PTX ISA Version 2. To implement the above example as a true conditional branch.pred as the type specifier. i. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. use a predicate to control the execution of the branch or call instructions. 1. branch over 56 January 24. n. add. Predicated Execution In PTX. optionally negated. // p = (i < n) // if i < n.lt. consider the high-level code if (i < n) j = j + 1. q. the following PTX instruction sequence might be used: @!p L1: setp. Predicates are most commonly set as the result of a comparison performed by the setp instruction.pred p. j.lt. where p is a predicate variable.s32 p.s32 j. bra L1. j.

ne (not-equal). and bitsize types. Table 16. gt (greater-than).1. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. lo (lower).1. The unsigned comparisons are eq. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. ne. Instruction Set 8.3. and hs (higher-or-same). gt. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and ge (greater-than-or-equal).1. ge. The following table shows the operators for signed integer. ls (lower-or-same). Table 15. unsigned integer. the result is false. The bit-size comparisons are eq and ne. lt (less-than). 2010 57 . ordering comparisons are not defined for bit-size types. ne. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).3. Comparisons 8. le. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.3. Unsigned Integer.1. hi (higher).Chapter 8. If either operand is NaN. le (less-than-or-equal).2. lt.

However. two operators num (numeric) and nan (isNaN) are provided.%p. Table 17. 2010 . gtu. num returns true if both operands are numeric values (not NaN). Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. leu. ltu.3. xor. then these comparisons have the same result as their ordered counterparts. unordered versions are included: equ. not. If either operand is NaN. and no direct way to load or store predicate register values. // convert predicate to 32-bit value 58 January 24.PTX ISA Version 2. Table 18.2.1. and nan returns true if either operand is NaN. geu.0. or. then the result of these comparisons is true.u32 %r1. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. for example: selp. neu. There is no direct conversion between predicates and integer values. If both operands are numeric values (not NaN).0 To aid comparison operations in the presence of NaN values. setp can be used to generate a predicate from an integer. and mov. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.

a. Floating-point types agree only if they have the same size. b.u16 d. a. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.fX ok inv inv ok Instruction Type . and these are placed in the same order as the operands. b.uX ok ok ok inv . and integer operands are silently cast to the instruction type if needed.u16 a. • The following table summarizes these type checking rules. Example: . and this information must be specified as a suffix to the opcode.fX ok ok ok ok January 24. For example. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.f32 d. Signed and unsigned integer types agree provided they have the same size. different sizes). most notably the data conversion instruction cvt.f32.reg . Instruction Set 8. ..4. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. i.e.reg . For example.bX . they must match exactly.reg . For example: .sX ok ok ok inv . It requires separate type-size modifiers for the result and source. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. a. the add instruction requires type and size information to properly perform the addition operation (signed. Type Checking Rules Operand Type .bX . unsigned.u16 d. float. cvt. add.Chapter 8. 2010 59 .u16 d.sX .uX . Table 19.

PTX ISA Version 2. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 2010 . The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. for example. ld. 1. floating-point instruction types still require that the operand type-size matches exactly. 60 January 24. Operand Size Exceeding Instruction-Type Size For convenience. parse error. Table 20. Floating-point source registers can only be used with bit-size or floating-point instruction types. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. or converted to other types and sizes. so those rows are invalid for cvt.1. Note that some combinations may still be invalid for a particular instruction. the cvt instruction does not support . Bit-size source registers may be used with any appropriately-sized instruction type. The data is truncated to the instruction-type size and interpreted according to the instruction type. 2. no conversion needed. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. so that narrow values may be loaded. “-“ = allowed. For example. When used with a narrower bit-size type.0 8. 4. When used with a floating-point instruction type. Source register size must be of equal or greater size than the instruction-type size. inv = invalid. the data will be truncated. Notes 3. The following table summarizes the relaxed type-checking rules for source operands.4. stored. the size must match exactly. st. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. and converted using regular-width registers. stored.bX instruction types. unless the operand is of bit-size type. When a source operand has a size that exceeds the instruction-type size.

When used with a floatingpoint instruction type.Chapter 8. zext = zero-extend. January 24. inv = Invalid.or sign-extended to the size of the destination register. Notes 3. 4. the data is sign-extended. and is zero-extended to the destination register width otherwise. the data will be zero-extended. Floating-point destination registers can only be used with bit-size or floating-point instruction types. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. 2. parse error. “-“ = Allowed but no conversion needed. If the corresponding instruction type is signed integer. The data is signextended to the destination register width for signed integer instruction types. The following table summarizes the relaxed type-checking rules for destination operands. 2010 61 . otherwise. Destination register size must be of equal or greater size than the instruction-type size. Table 21. the size must match exactly. the destination data is zero. When used with a narrower bit-size instruction type. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. The data is sign-extended to the destination register width for signed integer instruction types. 1. Bit-size destination registers may be used with any appropriately-sized instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size. the data is zeroextended.

5.PTX ISA Version 2. When executing on a 32-bit data path. for example. These extra precision bits can become visible at the application level. At the PTX language level. the semantics of 16-bit instructions in PTX is machine-specific. 8. The semantics are described using C. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. For divergent control flow. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. 8. conditional function call. or conditional return. A compiler or programmer may chose to enforce portable. by a right-shift instruction. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. a compiler or code author targeting PTX can ignore the issue of divergent threads. Therefore. If all of the threads act in unison and follow a single control flow path.6. until C is not expressive enough. However.6. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine.0 8.1. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. at least in appearance. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform.uni suffix. this is not desirable. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. until they come to a conditional control construct such as a conditional branch. and for many applications the difference in execution is preferable to limiting performance. 2010 . 62 January 24. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. using the . and 16-bit computations are “promoted” to 32-bit computations. If threads execute down different control flow paths. Both situations occur often in programs. for many performance-critical applications. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. the threads are called uniform. Divergence of Threads in Control Constructs Threads in a CTA execute together. so it is important to have divergent threads re-converge as soon as possible. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. the threads are called divergent. 16-bit registers in PTX are mapped to 32-bit physical registers. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. the optimizing code generator automatically determines points of re-convergence.

Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.7. In the following descriptions.Chapter 8. 8. Instructions All PTX instructions may be predicated. addc sub.cc. the optional guard predicate is omitted from the syntax.1. The Integer arithmetic instructions are: add sub add. 2010 63 .cc. Instruction Set 8. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7.

u32 x.s16.0 Table 22.MAXINT (no overflow) for the size of the operation. b.0. Description Semantics Notes Performs addition and writes the resulting value into a destination register.sat}. a. .type = { . .s32 . a.sat limits result to MININT.MAXINT (no overflow) for the size of the operation. add Syntax Integer Arithmetic Instructions: add Add two values.s32.c. d = a – b.type sub{.b.z.type add{.s32 c.sat.s16.s32. a. . 2010 . Saturation modifier: .u32. add. . Applies only to . Introduced in PTX ISA version 1. . d.s32 d. d. a.s64 }. Saturation modifier: .0.u32. PTX ISA Notes Target ISA Notes Examples Table 23. sub.sat applies only to .s32 .s32 type.PTX ISA Version 2. @p add. sub.y.a. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. add..1.s32 c.s32 type. Supported on all target architectures. b.s32 d.type = { . . .sat}. . . Introduced in PTX ISA version 1.u64.sat applies only to . b. Supported on all target architectures. // . d = a + b. .. // .u64.s64 }. Applies only to .u16.u16. PTX ISA Notes Target ISA Notes Examples 64 January 24.sat limits result to MININT.

x2.cc Add two values with carry-out. @p @p @p @p add. and there is no support for setting.cc.z2. or testing the condition code. Table 24. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.cc Syntax Integer Arithmetic Instructions: add. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.s32 }.cc. x2.s32 }. x4. sub. These instructions support extended-precision integer addition and subtraction. d = a + b. add.cc. No other instructions access the condition code.cc.CF) holding carry-in/carry-out or borrowin/borrow-out.u32. Behavior is the same for unsigned and signed integers.z3. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. clearing. if .y2.y1.cc specified. b.z4.u32. Instruction Set Instructions add. Introduced in PTX ISA version 1.y3.cc}.b32 x1. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.cc.b32 addc.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.b32 addc. addc.type d.type = {.y2. a.cc. add.b32 addc.cc.cc.CF No integer rounding modifiers. x3. @p @p @p @p add.z1. Supported on all target architectures.CF. d = a + b + CC. carry-out written to CC. carry-out written to CC.b32 addc. No saturation. .2. x4. 2010 65 . addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.2.cc.z1.b32 x1.b32 addc. x3.CF No integer rounding modifiers.z2. .y4.y3. Introduced in PTX ISA version 1.z3.z4.cc. Supported on all target architectures.y4. .type = { . a. .Chapter 8.b32 addc. No saturation.type d.y1. b. Behavior is the same for unsigned and signed integers. addc{.

.y2.y2.b32 subc. Behavior is the same for unsigned and signed integers. if .y3. x2. sub.y4.cc.z1.3.cc. d = a . . sub.cc specified.b32 subc. x4. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.s32 }. with borrow-out. Introduced in PTX ISA version 1.z3. x2.y3. b. a.u32.cc Subract one value from another.CF No integer rounding modifiers.y4.z3. borrow-out written to CC.cc}.b32 subc.z2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.y1. b. @p @p @p @p sub. Introduced in PTX ISA version 1.type = { .s32 }. @p @p @p @p sub.cc Syntax Integer Arithmetic Instructions: sub.cc. x4.b32 x1.y1.b32 subc.cc.(b + CC.z2. x3.z4.cc. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.type = {. . Supported on all target architectures.CF). Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. subc{.cc.z4.b32 subc. Supported on all target architectures.CF No integer rounding modifiers. 2010 . borrow-out written to CC.3.PTX ISA Version 2. Behavior is the same for unsigned and signed integers.0 Table 26. .type d.type d.z1. withborrow-in and optional borrow-out. x3.cc.b32 subc. No saturation.b32 x1.cc. a. No saturation.cc.u32. d = a – b.

x. . t = a * b. . Instruction Set Table 28.fys. d = t<n-1..fxs.u16. save only the low 16 bits // 32*32 bits. d = t<2n-1.y. If . mul Syntax Integer Arithmetic Instructions: mul Multiply two values. The .type d. mul. If .wide suffix is supported only for 16.s32 z. Description Semantics Compute the product of two values.wide // for .fys.hi variant // for .wide is specified.0>.. d = t.wide.wide.n>. . .type = { . mul{. a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi. mul.s64 }. Supported on all target architectures.lo is specified..s16.. n = bitwidth of type. // 16*16 bits yields 32 bits // 16*16 bits. . creates 64 bit result January 24.lo. then d is twice as wide as a and b to receive the full result of the multiplication.s16 fa. 2010 67 . b.u64.fxs.0. .s32.lo. mul.Chapter 8.s16 fa. and either the upper or lower half of the result is written to the destination register.lo variant Notes The type of the operation represents the types of the a and b operands. then d is the same size as a and b.u32. // for .hi or .wide}.and 32-bit integer types.

. @p mad.hi or . mad..lo variant Notes The type of the operation represents the types of the a and b operands. a. Description Semantics Multiplies two values and adds a third.q.MAXINT (no overflow) for the size of the operation. b. bitwidth of type.lo. ..lo..s32 type in . Applies only to .hi mode. .hi. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.and 32-bit integer types. and then writes the resulting value into a destination register.wide // for .sat limits result to MININT.c.s32.s32 d.u32. c.type = { .0 Table 29. .s32 r.s32 d.lo..u16.PTX ISA Version 2. If . d.wide is specified.n> + c. b. Saturation modifier: . // for . .0> + c. Supported on all target architectures.r.wide suffix is supported only for 16. The .s64 }..wide}.type mad. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. t + c.lo is specified.u64. t<2n-1. If . 2010 . and either the upper or lower half of the result is written to the destination register.sat. t<n-1. mad{. then d and c are the same size as a and b. .hi. c.s16.a.hi variant // for . 68 January 24.0. t n d d d = = = = = a * b. then d and c are twice as wide as a and b to receive the result of the multiplication.p. a.b.

.s32 d. mul24.u32.b.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. mul24.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. i.hi. . a. // for . mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24.0>.Chapter 8. January 24. 2010 69 . .type d. All operands are of the same type and size.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.lo.e. // low 32-bits of 24x24-bit signed multiply.hi may be less efficient on machines without hardware support for 24-bit multiply.0. d = t<31.16>. b. and return either the high or low 32-bits of the 48-bit result. mul24.lo}.. 48bits. d = t<47.. Instruction Set Table 30.hi variant // for . Supported on all target architectures. mul24{.s32 }.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.a. t = a * b.

. 32-bit value to either the high or low 32-bits of the 48-bit result. t = a * b. c.type = { .lo}.0.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.PTX ISA Version 2. c. Applies only to . Saturation modifier: .type mad24.. .hi. mad24. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.sat. Supported on all target architectures.MAXINT (no overflow).a. a. mad24{. . b.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.u32.c.b. All operands are of the same type and size.lo.s32 d.sat limits result of 32-bit signed addition to MININT. mad24. 48bits. mad24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32 type in . d.e.hi.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. b. d = t<47. mad24.16> + c. // for .. Return either the high or low 32-bits of the 48-bit result. 70 January 24.0> + c.hi may be less efficient on machines without hardware support for 24-bit multiply..s32 }.hi variant // for . a. d = t<31. // low 32-bits of 24x24-bit signed multiply.hi mode. 2010 . and add a third.s32 d. Description Compute the product of two 24-bit integer values held in 32-bit source registers. i.0 Table 31.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b64 }. } else { max = 64.b32 type. popc Syntax Integer Arithmetic Instructions: popc Population count.b64 d. clz. .0.u32 Semantics 74 January 24. popc requires sm_20 or later. .b64 d. . while (a != 0) { if (a&0x1) d++. For .type == . d = 0. For . // cnt is . .b32 clz. } Introduced in PTX ISA version 2. X. X. a. d = 0.0 Table 39.b32. clz requires sm_20 or later. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. clz. } while (d < max && (a&mask == 0) ) { d++. inclusively. mask = 0x80000000. a. popc.type = { . the number of leading zeros is between 0 and 32.u32 PTX ISA Notes Target ISA Notes Examples Table 40. inclusively. cnt.b32) { max = 32.PTX ISA Version 2. mask = 0x8000000000000000. 2010 . popc. a = a << 1.0.b64 }. a. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.type = { . // cnt is . if (. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.type d. a.b32 popc.b32.b64 type. cnt. a = a >> 1. the number of leading zeros is between 0 and 64. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.type d.

.u32 || . .d. For signed integers. Instruction Set Table 41. bfind returns 0xFFFFFFFF if no non-sign bit is found.shiftamt is specified.s64 }.u64. bfind. .type d. d = -1. If .s32) ? 31 : 63.s32. // cnt is . a. bfind. bfind returns the bit position of the most significant “1”. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.shiftamt. 2010 75 . bfind.u32.shiftamt. Semantics msb = (.s64 cnt. a. i--) { if (a & (1<<i)) { d = i.u32 January 24. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. break. a. and operand d has type .u32 d. bfind requires sm_20 or later.type bfind. i>=0.Chapter 8. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. for (i=msb. . Description Find the bit position of the most significant non-sign bit in a and place the result in d. } } if (. Operand a has the instruction type.u32. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. For unsigned integers.type==.type = { . d.type==. X.shiftamt && d != -1) { d = msb .0.

Description Semantics Perform bitwise reversal of input.PTX ISA Version 2. a.b32 d.b32.b64 }. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 76 January 24.0 Table 42.0. i++) { d[i] = a[msb-i]. brev.type = { . a. for (i=0. brev requires sm_20 or later. 2010 . brev Syntax Integer Arithmetic Instructions: brev Bit reverse. i<=msb.type==. . .type d. msb = (. brev.b32) ? 31 : 63.

a.s32.u64. Operands a and d have the same type as the instruction type. i<=msb. and source c gives the bit field length in bits. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. . the destination d is filled with the replicated sign bit of the extracted field. else sbit = a[min(pos+len-1. len = c. The sign bit of the extracted field is defined as: .u32 || . bfe.u32. and operands b and c are type . b.s32. bfe requires sm_20 or later.u64: .0. . January 24.type==. bfe.type d.type==. Semantics msb = (.a. .u32 || . pos = b.type==. if (.u32. If the start position is beyond the msb of the input. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.start. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.s64 }. The destination d is padded with the sign bit of the extracted field.b32 d. otherwise If the bit field length is zero.msb)].s32) ? 31 : 63. . Description Extract bit field from a and place the zero or sign-extended result in d.type==. . the result is zero.Chapter 8.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.len.u64 || len==0) sbit = 0. .type = { . Source b gives the bit field starting bit position. Instruction Set Table 43.u32. c. for (i=0. d = 0. 2010 77 .

0. d. the result is b. Operands a. 2010 .len. b.b64 }. bfi.0 Table 44.u32. i++) { f[pos+i] = a[i]. the result is b.type f. and source d gives the bit field length in bits. for (i=0. f = b. If the start position is beyond the msb of the input. and f have the same type as the instruction type.b32) ? 31 : 63. 78 January 24. pos = c. Description Align and insert a bit field from a into b. Semantics msb = (. If the bit field length is zero. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. a. and operands c and d are type .start. . b. bfi.b32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i<len && pos+i<=msb.b32 d. and place the result in f. bfi requires sm_20 or later.type==.b.type = { . Source c gives the starting bit position for the insertion.a. c.PTX ISA Version 2. . len = d.

Note that the sign extension is only performed as part of generic form. 2010 79 . c.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b3 source select c[15:12] d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. the permute control consists of four 4-bit selection values.Chapter 8. a 4-bit selection value is defined. . The msb defines if the byte value should be copied. . . and reassemble them into a 32-bit destination register. default mode index d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. the four 4-bit values fully specify an arbitrary byte permute. b. msb=0 means copy the literal value.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.mode} d.b4e. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. b5. prmt. The bytes in the two source registers are numbered from 0 to 7: {b. Thus. msb=1 means replicate the sign.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.ecr. For each byte in the target register.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.f4e. b0}}.b2 source select c[11:8] d. Instruction Set Table 45. b1. as a 16b permute code. {b3.b1 source select c[7:4] d.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.mode = { . a} = {{b7. . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). In the generic form (no mode specified). a.rc16 }.rc8. b2. .b32{. b6. . b4}. Description Pick four arbitrary bytes from two 32-bit registers.ecl.

} else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. 2010 .0 Semantics tmp64 = (b<<32) | a. prmt. tmp[15:08] = ReadByte( mode. tmp64 ). tmp[31:24] = ReadByte( mode. 80 January 24. prmt requires sm_20 or later.f4e r1. r3. r2. } tmp[07:00] = ReadByte( mode.0. ctl[0]. r1. ctl[3]. r4. r3. tmp[23:16] = ReadByte( mode. tmp64 ). tmp64 ). r4.PTX ISA Version 2. ctl[1] = (c >> 4) & 0xf. ctl[2]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[2] = (c >> 8) & 0xf. tmp64 ). ctl[3] = (c >> 12) & 0xf. r2. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 prmt. ctl[1].b32.

f64 register operands and constant immediate values.7. Instruction Set 8. 2010 81 . Floating-Point Instructions Floating-point instructions operate on .2.f32 and .Chapter 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.

target sm_1x No rounding modifier.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. {mad.f64 rsqrt.sqrt}.f32 . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.PTX ISA Version 2.sub.min.approx.sqrt}.target sm_20 mad.f32 {div. Table 46.f32 {mad. but single-precision instructions return an unspecified NaN.rnd.approx.f64 {sin.min.f64 mad.rnd. Single-precision add.f32 rsqrt.fma}.mul}.0]. default is .32 and fma.sqrt}. with NaNs being flushed to positive zero.f64 are the same. 82 January 24.0 The following table summarizes floating-point instructions in PTX.f32 {add. sub. .rcp.max}. Note that future implementations may support NaN payloads for single-precision instructions.mul}. default is .rm . .rnd.neg.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.f32 {abs. 1.rn and instructions may be folded into a multiply-add.rnd.target sm_20 . {add.sub. 2010 .approx.ftz . Instruction Summary of Floating-Point Instructions .rp .f32 {div.rnd.sat Notes If no rounding modifier is specified.rcp.f64 div.rz . mul.approx.lg2.f64 and fma.rcp. If no rounding modifier is specified.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {div.fma}.neg.full.cos.max}.f64 {abs. The optional .rn and instructions may be folded into a multiply-add. Double-precision instructions support subnormal inputs and results. NaN payloads are supported for double-precision instructions. and mad support saturation of results to the range [0.f32 are the same.ex2}.0. No rounding modifier.rnd. so PTX programs should not rely on the specific single-precision NaNs being generated.rn .

testp.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.notanumber.f32 testp. a. testp. z.normal testp.0. C. B. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.f32. .notanumber.finite.notanumber testp. y.f32. copysign.infinite testp. b.number. f0. January 24.0. .op.f64 }.Chapter 8.f64 }. testp Syntax Floating-Point Instructions: testp Test floating-point property. // result is . and return the result as d. p. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.type = { .f64 x. X.finite testp.type = { . not infinity) As a special case. a. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. . positive and negative zero are considered normal numbers.pred = { .type .subnormal }.op p. 2010 83 . . .f32 copysign. testp. . .f64 isnan. Introduced in PTX ISA version 2. Instruction Set Table 47.type d. . Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. A. Table 48. .infinite. copysign.infinite. true if the input is a subnormal number (not NaN. copysign requires sm_20 or later. not infinity). testp requires sm_20 or later.normal.number testp.

0.rnd}. add Syntax Floating-Point Instructions: add Add two values.rz. d.f32 add{.0 Table 49.PTX ISA Version 2.0.f32 supported on all target architectures. a.ftz. d = a + b. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 f1.rn. .rp for add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. 1.rm.0f.f32 flushes subnormal inputs and results to sign-preserving zero. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add{. add. In particular. requires sm_13 for add.f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64.rn mantissa LSB rounds to nearest even . NaN results are flushed to +0.rn.rz available for all targets .f64 d. add. Rounding modifiers (default is . . Rounding modifiers have the following target requirements: .rm.rz.sat}.rnd = { . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 clamps the result to [0.ftz.rm mantissa LSB rounds towards negative infinity .rnd}{.f32. 84 January 24. add.ftz}{. sm_1x: add.f2. requires sm_20 Examples @p add.sat.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 2010 .f64 requires sm_13 or later.rp }. add. a. .f3.0]. add. b. Saturation modifier: . .rn): . subnormal numbers are supported.f64 supports subnormal numbers.rz mantissa LSB rounds towards zero . . . b.

Chapter 8.f64 supports subnormal numbers.rnd}.rnd}{. sub Syntax Floating-Point Instructions: sub Subtract one value from another.rn mantissa LSB rounds to nearest even .f32 clamps the result to [0.f32 c. January 24.rn.f32 sub{. sub.f32 supported on all target architectures. Rounding modifiers have the following target requirements: .0f.sat}. In particular.b.f3. 1.rz mantissa LSB rounds towards zero .rp }. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 f1. sub. b. sub{. sm_1x: sub.rz available for all targets . A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz}{.ftz.ftz.rn. . sub.0].0. . d = a . .f32.rn): . .rm. sub.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later. b.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 50. NaN results are flushed to +0.rnd = { . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rp for sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. . requires sm_20 Examples sub.f64 d. a.sat. .rm.b.f2.rn.0. requires sm_13 for sub. Rounding modifiers (default is . subnormal numbers are supported. Saturation modifier: sub.f64. 2010 85 . sub.rz.a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. a. d.f32 flushes subnormal inputs and results to sign-preserving zero.

2010 .rnd}{.f64 supports subnormal numbers. mul.ftz.0f. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. mul. b. mul{.rn.f64.sat. mul.rnd}.rm.rz mantissa LSB rounds towards zero . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.sat}.0].rp for mul. a. .ftz. requires sm_13 for mul.rn): . . .rn mantissa LSB rounds to nearest even .f32 supported on all target architectures. subnormal numbers are supported. .rm. d.rnd = { . mul Syntax Floating-Point Instructions: mul Multiply two values.0. requires sm_20 Examples mul.rm mantissa LSB rounds towards negative infinity .rn.rz.PTX ISA Version 2. d = a * b.radius.pi // a single-precision multiply 86 January 24.f32 circumf.ftz}{.f64 requires sm_13 or later. a. . Saturation modifier: mul.0 Table 51.f64 d. Rounding modifiers (default is .rz available for all targets . NaN results are flushed to +0.rp }. all operands must be the same size.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1. For floating-point multiplication. mul.f32 flushes subnormal inputs and results to sign-preserving zero.f32 clamps the result to [0. sm_1x: mul. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. Rounding modifiers have the following target requirements: .f32 mul{. Description Semantics Notes Compute the product of two values. . In particular.f32.f32 flushes subnormal inputs and results to sign-preserving zero. b. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0.

rn. fma.rn mantissa LSB rounds to nearest even .z. fma. fma.rn.rm.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later. fma. again in infinite precision. Instruction Set Table 52.4. sm_1x: fma.0.rnd{. a.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. fma.f64 supports subnormal numbers. .rnd. @p fma.f64.Chapter 8. .rnd.x.rnd = { . fma.rnd.rz. c.f32 fma.c. d. fma.rp }. fma Syntax Floating-Point Instructions: fma Fused multiply-add.ftz}{.f32 fma.f64 d.f64 introduced in PTX ISA version 1. The resulting value is then rounded to double precision using the rounding mode specified by .rn. subnormal numbers are supported.0. b.f64 computes the product of a and b to infinite precision and then adds c to this product.f64 w.f64 is the same as mad. . . d = a*b + c.f32 introduced in PTX ISA version 2. Saturation: fma.0f. The resulting value is then rounded to single precision using the rounding mode specified by .a.sat}. again in infinite precision. fma.sat. 2010 87 . fma.f32 is unimplemented in sm_1x. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. c.y. b. a. Rounding modifiers (no default): . NaN results are flushed to +0.0].rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz. PTX ISA Notes Target ISA Notes Examples January 24.b. d. fma. 1.f32 clamps the result to [0.f32 requires sm_20 or later.rz mantissa LSB rounds towards zero .

target sm_1x d. but the exponent is preserved.rm mantissa LSB rounds towards negative infinity .ftz. again in infinite precision.target sm_1x: mad. Description Semantics Notes Multiplies two values and adds a third. a. 2010 .rnd = { .f64 supports subnormal numbers.sat}. a. d = a*b + c. When JIT-compiled for SM 2. Unlike mad.f64 computes the product of a and b to infinite precision and then adds c to this product. mad.0 Table 53. mad.{f32. again in infinite precision.ftz}{.f32 flushes subnormal inputs and results to sign-preserving zero.sat}. mad.rnd{.PTX ISA Version 2. mad.f64 is the same as fma.0f. The resulting value is then rounded to single precision using the rounding mode specified by .f32 clamps the result to [0. b.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. For . .f32 computes the product of a and b to infinite precision and then adds c to this product. 88 January 24.rnd.rz mantissa LSB rounds towards zero .target sm_20 d. Saturation modifier: mad.f32 computes the product of a and b at double precision.rm.f64} is the same as fma.target sm_20: mad. // .ftz}{. Note that this is different from computing the product with mul.0. The resulting value is then rounded to double precision using the rounding mode specified by . mad. . c. For . 1. sm_1x: mad.f64. b. and then writes the resulting value into a destination register. // . the treatment of subnormal inputs and output follows IEEE 754 standard.rn.f64}..rn mantissa LSB rounds to nearest even . mad. mad.rp }. a. fma. b. mad. Rounding modifiers (no default): . mad{. The exception for mad. . The resulting value is then rounded to double precision using the rounding mode specified by .f64 d.sat.0.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 computes the product of a and b to infinite precision and then adds c to this product.{f32.e.target sm_13 and later . where the mantissa can be rounded and the exponent will be clamped.f32 is implemented as a fused multiply-add (i.f32 mad.rz. and then the mantissa is truncated to 23 bits.rnd.f32 flushes subnormal inputs and results to sign-preserving zero. // . c.0]. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f32. NaN results are flushed to +0.f32).ftz. again in infinite precision.f32 is when c = +/-0.0 devices.f32 is identical to the result computed using separate mul and add instructions.f32 mad.rnd. c. subnormal numbers are supported.rnd. mad. In this case.

Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rm. a rounding modifier is required for mad.rn.rz. Target ISA Notes mad. Legacy mad.f32...rp for mad. requires sm_13 .b.0 and later.f64 instructions having no rounding modifier will map to mad.f64.0.. mad. a rounding modifier is required for mad.f64 requires sm_13 or later.rn. January 24. requires sm_20 Examples @p mad.rm. 2010 89 ..rp for mad..rn. In PTX ISA versions 2..f64.f32 supported on all target architectures.a.c.f32 for sm_20 targets.Chapter 8. Rounding modifiers have the following target requirements: . In PTX ISA versions 1.4 and later.f64.f32 d.rz.

ftz.f64.f32 implements a relatively fast.rm.f32 supported on all target architectures.rnd{. d. The maximum ulp error is 2 across the full range of inputs.f32 div. Description Semantics Notes Divides a by b.full.f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. or . sm_1x: div.3.approx. zd. Examples 90 January 24.ftz. For PTX ISA version 1. d = a / b. a. and rounding introduced in PTX ISA version 1.rp }.3.ftz.rp}. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . b. .rz mantissa LSB rounds towards zero . d.rnd = { .full. Fast. div. one of .approx.0 through 1.approx{.f64 requires sm_13 or later. div.f32 div. Subnormal inputs and results are flushed to sign-preserving zero.ftz.full.f64 requires sm_20 or later.f64 introduced in PTX ISA version 1.approx. div. z. a. div Syntax Floating-Point Instructions: div Divide one value by another.ftz}. approximate division by zero creates a value of infinity (with same sign as a).circum.full.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 54.rm. div.14159.0. .rn mantissa LSB rounds to nearest even . .rm mantissa LSB rounds towards negative infinity .rnd is required.rn.approx.ftz}. Target ISA Notes div. approximate single-precision divides: div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . For b in [2-126.{rz. y. For PTX ISA versions 1. the maximum ulp error is 2. div.ftz}.approx.full. d. xd.f32 requires sm_20 or later.rnd. . div. a.full{. computed as d = a * (1/b).rnd.f32 and div. Fast.f32 div. div.f32 flushes subnormal inputs and results to sign-preserving zero.f64 diam. div. . full-range approximation that scales operands to achieve better accuracy.4.f64 defaults to div. subnormal numbers are supported. PTX ISA Notes div. b.f32 and div.rn. // // // // fast.f32 implements a fast approximation to divide. b. a. and div.approx.rn.f32 div.f32 div. . 2010 . div.f64 d.rz. b. x. yd.PTX ISA Version 2. stores result in d.ftz.rn.f64 supports subnormal numbers. Explicit modifiers .4 and later. 2126]. but is not fully IEEE 754 compliant and does not support rounding modifiers.f32 defaults to div.

f32 flushes subnormal inputs and results to sign-preserving zero. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. abs. a.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.Chapter 8.f32 x. d. NaN inputs yield an unspecified NaN. abs. Negate the sign of a and store the result in d. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. d = |a|.ftz}. neg. Take the absolute value of a and store the result in d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. Subnormal numbers: sm_20: By default. Instruction Set Table 55. abs.0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f64 d.f64 requires sm_13 or later.ftz}.f32 supported on all target architectures.f32 supported on all target architectures.ftz. a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.ftz. subnormal numbers are supported.f32 abs.f64 supports subnormal numbers. January 24. neg.f0. subnormal numbers are supported.f32 x. d. d = -a. sm_1x: abs. Table 56. abs{. neg.0. 2010 91 . abs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: neg.ftz. abs.f64 requires sm_13 or later.f64 d. neg{.f32 neg. a. a.f0. neg. NaN inputs yield an unspecified NaN.

f64 supports subnormal numbers.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. min.f32 min. a.b.f32 min. min. min.ftz. b. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.c. a.f64 supports subnormal numbers. max.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. d d d d = = = = NaN. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. min{.ftz.f2. max{. d d d d = = = = NaN.ftz}. max. b. a.ftz.ftz}.b. b. sm_1x: min. b.x. b.f1.f64 f0.0. Store the minimum of a and b in d. max. min.f32 max. a. a.z. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. a.0. subnormal numbers are supported.0 Table 57. max. (a > b) ? a : b.f64 requires sm_13 or later. sm_1x: max. d. max.f64 requires sm_13 or later.f32 supported on all target architectures. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. Store the maximum of a and b in d. (a < b) ? a : b.f32 max.f32 supported on all target architectures. Table 58. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.c. @p min. 92 January 24. d. 2010 .f64 d. b.f64 z. subnormal numbers are supported.

rn.rm mantissa LSB rounds towards negative infinity . Examples January 24. and rcp. subnormal numbers are supported.ftz. Target ISA Notes rcp. rcp. d = 1 / a. a.rnd = { .approx and . . Description Semantics Notes Compute 1/a.0. rcp.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers.rm. rcp. .{rz.approx or .rn.ftz.f64 introduced in PTX ISA version 1.rnd.rnd is required.rn. rcp.ftz}.rn. Instruction Set Table 59. rcp.rm.f32 rcp.rnd{.f32 rcp.f64 requires sm_13 or later.x.rnd. .x.rn.0-2.f64 requires sm_20 or later. rcp. sm_1x: rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.f64 d. a.f32 flushes subnormal inputs and results to sign-preserving zero. store result in d.f32 and rcp.f64. 2010 93 . Input -Inf -subnormal -0.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .0.f64 defaults to rcp.approx. The maximum absolute error is 2-23.rz.ftz.rp}.ftz were introduced in PTX ISA version 1.0 -Inf -Inf +Inf +Inf +0.rz mantissa LSB rounds towards zero .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rn mantissa LSB rounds to nearest even .approx.rp }. rcp.4. d.approx.0 +0.f32 defaults to rcp. rcp. PTX ISA Notes rcp.3. one of .0. For PTX ISA versions 1.f32 supported on all target architectures.r.approx. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .ftz. // fast.f32 requires sm_20 or later. xi. xi.f32 rcp. a.0 over the range 1.approx{.4 and later. d.0 +subnormal +Inf NaN Result -0. For PTX ISA version 1.f32 implements a fast approximation to reciprocal. rcp. General rounding modifiers were added in PTX ISA version 2.Chapter 8.f32 rcp.ftz}.f64 and explicit modifiers . rcp.f64 ri.f32.rn.0 through 1.

approximate square root d.0.rnd.rn. a.f32. sqrt. subnormal numbers are supported.approx. sqrt.{rz.ftz.ftz. The maximum absolute error for sqrt.x.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f64 requires sm_13 or later.0 +subnormal +Inf NaN Result NaN NaN -0.rm. a.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is TBD.x.rnd{. . sqrt.rn mantissa LSB rounds to nearest even .f32 implements a fast approximation to square root. . 2010 .f64 supports subnormal numbers.4.f64 requires sm_20 or later.rz mantissa LSB rounds towards zero .ftz}.rnd is required.rz.ftz.3.approx{. Examples 94 January 24.f64 and explicit modifiers .PTX ISA Version 2.f64.ftz were introduced in PTX ISA version 1. r. Target ISA Notes sqrt.approx. and sqrt. // IEEE 754 compliant rounding d. For PTX ISA version 1.f32 sqrt.0.approx or .x.f32 defaults to sqrt.0 +0. Description Semantics Notes Compute sqrt(a). store in d.f64 d. // fast. // IEEE 754 compliant rounding .4 and later.rm mantissa LSB rounds towards negative infinity .f32 supported on all target architectures.rnd. sm_1x: sqrt.rn. Input -Inf -normal -subnormal -0.f32 sqrt.rn.f32 sqrt.f32 and sqrt.f64 r.ftz}.0 +0.approx.0 +0. sqrt. General rounding modifiers were added in PTX ISA version 2.approx and . sqrt.rp }.rnd = { .f64 introduced in PTX ISA version 1. sqrt. d = sqrt(a).approx. PTX ISA Notes sqrt.0 Table 60.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0 -0.rn.rp}. sqrt.rn.approx. sqrt.rm. a. For PTX ISA versions 1. one of .rn. . sqrt. sqrt.f64 defaults to sqrt.ftz.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 sqrt. r.f32 requires sm_20 or later.0 through 1.

rsqrt.f32 supported on all target architectures. store the result in d. Input -Inf -normal -subnormal -0. Explicit modifiers .f32 defaults to rsqrt.f64 supports subnormal numbers. For PTX ISA versions 1. d = 1/sqrt(a). The maximum absolute error for rsqrt.f32 is 2-22.approx.0. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. X.0. rsqrt.approx.Chapter 8. For PTX ISA version 1.f32. and rsqrt.approx and .f64 is TBD. January 24. Target ISA Notes Examples rsqrt.0-4.ftz were introduced in PTX ISA version 1.approx.0 +0. Instruction Set Table 61.0 NaN The maximum absolute error for rsqrt. ISR. a.3.f64 requires sm_13 or later. x.f64 defaults to rsqrt.f64 isr.approx{. a.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f64 is emulated in software and are relatively slow. rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. sm_1x: rsqrt. Subnormal numbers: sm_20: By default.approx.approx modifier is required.4 and later.f32 and rsqrt. rsqrt.0 through 1.approx.f64.f32 rsqrt. PTX ISA Notes rsqrt. rsqrt.ftz. rsqrt.4. 2010 95 .4 over the range 1.f64 d.f64 were introduced in PTX ISA version 1. Compute 1/sqrt(a).approx implements an approximation to the reciprocal square root.ftz}.approx. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero. Note that rsqrt.ftz. d. the .f32 rsqrt.ftz.

d = sin(a).f32 sa.approx{. the .approx.4.approx and .f32 d.0 through 1.9 in quadrant 00.f32.0 +0. sin.0 -0. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero. 96 January 24.ftz introduced in PTX ISA version 1.0 +0.0 Table 62. For PTX ISA version 1. Subnormal numbers: sm_20: By default.f32 implements a fast approximation to sine.f32 introduced in PTX ISA version 1.4 and later. sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. subnormal numbers are supported. Input -Inf -subnormal -0. sin.0.approx.0 NaN NaN The maximum absolute error is 2-20.ftz. Target ISA Notes Examples Supported on all target architectures.PTX ISA Version 2. Find the sine of the angle a (in radians).f32 defaults to sin. For PTX ISA versions 1.approx. PTX ISA Notes sin.ftz}.0 +subnormal +Inf NaN Result NaN -0. 2010 .0 +0. a. a.ftz.3.ftz.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero. sin. sin.

4.approx.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 ca.f32 implements a fast approximation to cosine. d = cos(a).approx{.0 +0.4 and later.3. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.ftz.ftz introduced in PTX ISA version 1.0 +1. Instruction Set Table 63.ftz.Chapter 8.f32 introduced in PTX ISA version 1. PTX ISA Notes cos. For PTX ISA versions 1. 2010 97 .ftz}.0 +subnormal +Inf NaN Result NaN +1. Find the cosine of the angle a (in radians). a. January 24. cos.9 in quadrant 00.approx. cos. Subnormal numbers: sm_20: By default.approx.f32 defaults to cos. Input -Inf -subnormal -0. cos. Target ISA Notes Examples Supported on all target architectures.0. the . cos.approx modifier is required.0 +1. subnormal numbers are supported. Explicit modifiers .f32 d. For PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. a.0 NaN NaN The maximum absolute error is 2-20.f32.0 through 1.approx and . cos.0 +1.

0 Table 64.0.4 and later. d = log(a) / log(2).ftz.ftz.approx.f32 implements a fast approximation to log2(a).ftz introduced in PTX ISA version 1. 98 January 24. For PTX ISA versions 1. lg2.3.f32 Determine the log2 of a.f32 la. The maximum absolute error is 2-22.PTX ISA Version 2.approx modifier is required.approx. For PTX ISA version 1.f32 introduced in PTX ISA version 1.4.0 +0. lg2.f32 defaults to lg2.approx{. lg2.0 through 1. PTX ISA Notes lg2. sm_1x: Subnormal inputs and results to sign-preserving zero.approx and . 2010 .approx.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. Subnormal numbers: sm_20: By default. the . a. Input -Inf -subnormal -0. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz}.f32. lg2. a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Explicit modifiers . lg2.6 for mantissa. Target ISA Notes Examples Supported on all target architectures.ftz.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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CmpOp. lt. Modifier . and hs for lower. .u32 p|q. q = BoolOp(!t.ftz applies only to .CmpOp{.eq. num returns true if both operands are numeric values (not NaN). gt. b. gt. and higher-or-same may be used instead of lt. If either operand is NaN. p[|q]. unordered versions are included: equ.PTX ISA Version 2.type . ne. gtu. b. 2010 .dtype. a. higher. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.and. The destinations p and q must be . num.ftz. lt.BoolOp{. ltu. then the result of these comparisons is true.b. To aid comparison operations in the presence of NaN values.f32 flushes subnormal inputs to sign-preserving zero.0. gt.b64. respectively. lo. For unsigned values. a.b16. geu. ge. @q setp.f64 source type requires sm_13 or later. bit-size comparisons are eq and ne. . nan The Boolean operator BoolOp(A. sm_1x: setp. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.ftz}.f32 comparisons.f64 supports subnormal numbers. leu. setp with . le. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.i. p. hs equ. then these comparisons have the same result as their ordered counterparts.n. .pred variables. leu.B) is one of: and. . hi.ftz}. le. le. setp. or. ge. ne.type = { . c).u16. hi. loweror-same. The signed and unsigned comparison operators are eq. ge. c). gtu. neu. p[|q]. A related value computed using the complement of the compare result is written to the second destination operand. Integer Notes Floating Point Notes The ordered comparisons are eq. . The comparison operator is a suffix on the instruction.s32. {!}c. lt. If both operands are numeric values (not NaN).s16. The untyped. . neu.dtype.0 Table 67.dtype. If either operand is NaN.s32 setp. subnormal numbers are supported. Semantics t = (a CmpOp b) ? 1 : 0.s64. gt.a. 102 January 24. Subnormal numbers: sm_20: By default. setp.type setp. ls.f64 }. This result is written to the first destination operand. and nan returns true if either operand is NaN. . ltu. and (optionally) combine this result with a predicate value by applying a Boolean operator.lt.f32. ge. and can be one of: eq.f32 flushes subnormal inputs to sign-preserving zero.b32. ls. . the result is false.u64.u32. . xor.r. . p = BoolOp(t. the comparison operators lo. le. Applies to all numeric types. setp. geu. ne.

.f32 A. slct.b16.f32 d. the comparison is unordered and operand b is selected.0. Introduced in PTX ISA version 1. . a. Instruction Set Table 68.f32.ftz. a.u32. otherwise b is stored in d.f32 comparisons. . and b are treated as a bitsize type of the same width as the first instruction type.t.u16. d = (c == 1) ? a : b.b64. .ftz applies only to . .s16.b64. For . slct.xp.dtype.type = { . based on the value of the predicate source operand. If c ≥ 0.u32.f32.0. If operand c is NaN. a.f64 requires sm_13 or later.x. Modifier . slct.f64 requires sm_13 or later. z.u16.f64 }.u64. selp. based on the sign of the third operand. . Description Conditional selection. d. fval. . y. 2010 103 . . .f64 }.ftz}. b.b32. a. d = (c >= 0) ? a : b.b16. If c is True. @q selp. sm_1x: slct. b. c. b otherwise. . Operands d.p.r. Table 69.b32. . slct. .g. a.s64.f32 flushes subnormal values of operand c to sign-preserving zero.s16.s64. c. subnormal numbers are supported.ftz. . . a is stored in d. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.s32 selp. a is stored in d.f32 comparisons. b.u64.dtype.dtype. B.dtype.u64. Operands d. . . . and operand a is selected. Subnormal numbers: sm_20: By default. c. C. . and operand a is selected. slct.s32 x. Operand c is a predicate. .s32 slct{. . slct Syntax Comparison and Selection Instructions: slct Select one source operand. operand c must match the second instruction type.s32. negative zero equals zero. .f32 flushes subnormal values of operand c to sign-preserving zero.type d. f0.f32 r0. . val. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The selected input is copied to the output without modification. selp.Chapter 8. and b must be of the same type.s32.u32.dtype = { . Semantics Floating Point Notes January 24. selp Syntax Comparison and Selection Instructions: selp Select between source operands.

0 8. xor. Instructions and. 2010 .PTX ISA Version 2.7. and not also operate on predicates. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. performing bit-wise operations on operands of any type.4. This permits bit-wise operations on floating point values without having to define a union to access the bits. provided the operands are of the same size. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. or.

b32 mask mask. Introduced in PTX ISA version 1. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.r.b16. and. or. . or Syntax Logic and Shift Instructions: or Bitwise OR.0. and.pred. b. d = a & b. Table 71.q.type d.b64 }. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.b32 and.0. Supported on all target architectures.type = { .fpvalue. or. . but not necessarily the type. sign.b32. . Introduced in PTX ISA version 1. b.pred. . . .0x80000000.b64 }.b16.type d.Chapter 8. Instruction Set Table 70. January 24. d = a | b. Supported on all target architectures.q.type = { . a. 2010 105 . .b32 x. The size of the operands must match. The size of the operands must match. but not necessarily the type.pred p.b32. Allowed types include predicate registers. a. Allowed types include predicate registers.r.0x00010001 or. and Syntax Logic and Shift Instructions: and Bitwise AND.

b64 }. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.b32 xor.mask.b32.PTX ISA Version 2. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. .x. The size of the operands must match.0.b32 mask.0 Table 72. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. The size of the operands must match.pred. but not necessarily the type. Table 73. but not necessarily the type.q.b32 d. Supported on all target architectures. . .pred p.type d. d = ~a.0x0001. d. not.b32. xor. one’s complement.b64 }. a. Supported on all target architectures. 2010 . d = (a==0) ? 1 : 0. . xor. The size of the operands must match. Allowed types include predicate registers. not.type = { . . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.type d. d = a ^ b. cnot. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). . not.pred.r. 106 January 24.b16 d. not Syntax Logic and Shift Instructions: not Bitwise negation.b16. Introduced in PTX ISA version 1. a. . Introduced in PTX ISA version 1. a. Introduced in PTX ISA version 1. . .b32.a.b64 }.q. Supported on all target architectures. b. . Table 74.0. .type = { . Allowed types include predicates.b16.0. cnot.b16.type = { .type d.

. Instruction Set Table 75. but not necessarily the type.b32. The sizes of the destination and first source operand must match.s32 shr. regardless of the instruction type.b16 c.b64 }. shl Syntax Logic and Shift Instructions: shl Shift bits left. .b32 q. .u64. k.b16. PTX ISA Notes Target ISA Notes Examples January 24.a.0. . but not necessarily the type. sign or zero fill on left. Introduced in PTX ISA version 1.b32. . Shift amounts greater than the register width N are clamped to N. shr Syntax Logic and Shift Instructions: shr Shift bits right. . The b operand must be a 32-bit value. shl.Chapter 8. . d = a << b. The b operand must be a 32-bit value. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.b64.i.j.type = { . .type = { . Supported on all target architectures. regardless of the instruction type. PTX ISA Notes Target ISA Notes Examples Table 76.type d.i. shr.u16 shr.b16. b. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Signed shifts fill with the sign bit. 2010 107 . Bit-size types are included for symmetry with SHL.2.type d. . i.2. zero-fill on right. d = a >> b. Shift amounts greater than the register width N are clamped to N. The sizes of the destination and first source operand must match. a. Introduced in PTX ISA version 1.u16. b. shr. . Supported on all target architectures.u32.s32.1.s16. . shl. unsigned and untyped shifts fill with 0.s64 }.0. a.a. .

ldu. Instructions ld. The cvta instruction converts addresses between generic and global. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. and sust support optional cache operations. mov. or shared state spaces. ld.PTX ISA Version 2. 2010 . possibly converting it from one format to another. st. suld.7. local. and from state space to state space.0 8. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. and st operate on both scalar and vector types.5. Data Movement and Conversion Instructions These instructions copy data from place to place. prefetchu isspacep cvta cvt 108 January 24.

ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.5. Table 77.lu operation. . Cache Operators PTX 2. The cache operators require a target architecture of sm_20 or later.cs. The ld. As a result of this request. A ld. bypassing the L1 cache. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. If one thread stores to global memory via one L1 cache. The ld. and cache only in the L2 cache. 2010 109 . When ld. if the line is fully covered.cg Cache at global level (cache in L2 and below.cs Cache streaming. For sm_20 and later.lu load last use operation. The compiler / programmer may use ld. January 24.7. The default load instruction cache operation is ld. invalidates (discards) the local L1 line following the load.Chapter 8. Operator . Use ld.cs) on global addresses. not L1). evict-first.1. it performs the ld.0 introduces optional cache operators on load and store instructions.cs is applied to a Local window address. likely to be accessed once.cv Cache as volatile (consider cached system memory lines stale. and a second thread loads that address via a second L1 cache with ld. fetch again). the second thread may get stale L1 cache data. to allow the thread program to poll a SysMem location written by the CPU. rather than the data stored by the first thread.ca.ca loads cached in L1. any existing cache lines that match the requested address in L1 will be evicted. The ld.cg to cache loads only globally. .cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. .ca. when applied to a local address. The ld. Global data is coherent at the L2 level. Instruction Set 8.lu instruction performs a load cached streaming operation (ld. .cv to a frame buffer DRAM address is the same as ld. likely to be accessed again. but multiple L1 caches are not coherent for global data. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.lu Last use. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. the cache operators have the following definitions and behavior.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.

which writes back cache lines of coherent cache levels with normal eviction policy. Global stores bypass L1.cs Cache streaming.cg to local memory uses the L1 cache. . st. in which case st. bypassing the L1 cache. rather than get the data from L2 or memory stored by the first thread. the second thread may get a hit on stale L1 cache data. If one thread stores to global memory. In sm_20. 110 January 24.wt Cache write-through (to system memory). to allow a CPU program to poll a SysMem location written by the GPU with st. .ca loads.cg is the same as st. not L1).cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. 2010 .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cg to cache global store data only globally. and discard any L1 lines that match. Future GPUs may have globally-coherent L1 caches. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. bypassing its L1 cache.wb for global data.ca. However. The st. likely to be accessed once. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.wt. Addresses not in System Memory use normal write-back.0 Table 78.wb could write-back global store data from L1.wb. and cache only in the L2 cache.cg Cache at global level (cache in L2 and below. .PTX ISA Version 2. The st. Use st. and a second thread in a different SM later loads from that address via a different L1 cache with ld. but st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wt store write-through operation applied to a global System Memory address writes through the L2 cache. and marks local L1 lines evict-first. regardless of the cache operation. The default store instruction cache operation is st. Operator .

Operand a may be a register. d = &avar.e. mov places the non-generic address of the variable (i.s16. the parameter will be copied onto the stack and the address will be in the local state space. mov. Description .f64 }.type = { . and . label. A.s64. .u16 mov.1. or function name. .u64. The generic address of a variable in global. Note that if the address of a device function parameter is moved to a register. ptr. d = sreg. mov. . local. Semantics d = a. Write register d with the value of a.0. 2010 111 . // address is non-generic.f32 mov. .e. variable in an addressable memory space.type mov. a.a.local. k.u32.b16.s32.v. . u.const.u16.type mov.f32 mov. or shared state space may be taken directly using the cvta instruction. For variables declared in . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.. d. special register. sreg. . local. the generic address of a variable declared in global. d.0.f64 requires sm_13 or later. . the address of the variable in its state space) into the destination register. d = &label.type d. myFunc. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. . avar. Introduced in PTX ISA version 1. or shared state space.b32. local. Instruction Set Table 79.global. A[5]. alternately. . i. . immediate.b64. Take the non-generic address of a variable in global. ptr. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. within the variable’s declared state space Notes Although only predicate and bit-size types are required. // get address of variable // get address of label or function .shared state spaces..u32 mov. . d.f32.u32 mov.type mov.Chapter 8.u32 d.pred. label. addr. mov. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. .

.b32 { d.b64 mov. d.{a.x | (a.b have type . Both the overall size of the vector and the size of the scalar must match the size of the instruction type..b32 %r1.x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). . a[48.g.hi}. 2010 .31] } // unpack 16-bit elements from . d. For bit-size types..b16 { d..b8 r.w } = { a[0.b64 { d.z.hi are .. {lo.b..b32 { d.x.0 Table 80. mov. mov.31].w << 24) d = a.b32 // pack four 16-bit elements into .type = { .0.b. a[16. Description Write scalar register d with the packed value of vector register a. d. Supported on all target architectures.b32 mov.w } = { a[0. d... %r1. // // // // a..31]..y.a}.y << 8) d = a.%r1.15].b16.u16 %x is a double.b16 // pack four 8-bit elements into .31] } // unpack 8-bit elements from .y.7].y } = { a[0.g.15] } // unpack 8-bit elements from .b32 // pack two 16-bit elements into .23]. . a. d. .u32 x.z. a[8.y.w have type ..y } = { a[0.a have type ..{x.x.PTX ISA Version 2. a[16..x. %x.y << 32) // pack two 8-bit elements into .y << 16) d = a. {r.w << 48) d = a.b64 // pack two 32-bit elements into .63] } // unpack 16-bit elements from .z << 32) | (a.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.x | (a.w}. d. d.z.b64 112 January 24.. d. d. a[24.z.y } = { a[0. or write vector register d with the unpacked values from scalar register a.15].y << 8) | (a.15].y. a[32.x.x | (a. lo. Semantics d = a.7].x | (a. a[8.b32. a[16. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.z << 16) | (a.b64 }.x | (a.b}.b64 { d.u8 // unpack 32-bit elements from . a[32.type d.b32 mov.47].y << 16) | (a.

the resulting behavior is undefined.cv }. . [a]. . ld.ca.volatile.vec = { .1. . i. d. This may be used. . *a.f64 using cvt. The address must be naturally aligned to a multiple of the access size.shared }.ss}.cop = { .vec.type d.s64. . or [immAddr] an immediate absolute byte address (unsigned.v4 }.e. . Generic addressing may be used with ld.f32 or .type ld.ss}{.0. . . perform the load using generic addressing. . an address maps to global memory unless it falls within the local memory window or the shared memory window.ss}{. ld{. . *(immAddr).vec.reg state space.b16.f64 }. . .global. d. .param.s16. for example.b8.b16.u32.local. [a]. [a].f32.volatile. Description Load register variable d from the location specified by the source address operand a in specified state space. [a]. The value loaded is sign-extended to the destination register width for signed integers.cg.volatile{.b64.type . 32-bit). Generic addressing and cache operations introduced in PTX ISA 2.0. 32-bit). to enforce sequential consistency between threads accessing shared memory.e.type ld{.ss = { .b32.global and .cop}. or the instruction may fault. 2010 113 . Addresses are zero-extended to the specified width as needed. d..const. . ld introduced in PTX ISA version 1.volatile may be used with . . and then converted to .f16 data may be loaded using ld. .u16. Within these windows. and truncated if the register width exceeds the state space address width for the target architecture.lu.volatile introduced in PTX ISA version 1.ss}.cop}.s8. .u64. . and is zeroextended to the destination register width for unsigned and bit-size types.v2. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .u8. If an address is not properly aligned. .s32. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. the access may proceed by silently masking off low-order address bits to achieve proper rounding. If no state space is given. i. . ld. . Semantics d d d d = = = = a. .type = { . an address maps to the corresponding location in local or shared memory. Cache operations are not permitted with ld. an integer or bit-size type register reg containing a byte address. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. In generic addressing. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. The . *(a+immOff). . A destination register wider than the specified type may be used.volatile{. . . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.cs. Instruction Set Table 81. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. The address size may be either 32-bit or 64-bit.const space suffix may have an optional bank number to indicate constant banks other than bank zero.shared spaces to inhibit optimization of references to volatile memory. PTX ISA Notes January 24.Chapter 8.

[fs]. Q.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[a].b32 ld.b32 ld.const.local.[p+-8].[p+4].f16 d.global. // load .b16 cvt.f32 ld. 2010 . x.const[4]. Generic addressing requires sm_20 or later. ld. %r.shared. // negative offset %r. // access incomplete array x.local.b64 ld.0 Target ISA Notes ld.f64 requires sm_13 or later.v4.b32 ld.[p].PTX ISA Version 2.[buffer+64]. Cache operations require sm_20 or later.global.f32. d.s32 ld. // immediate address %r.%r.[240].

*a. If no state space is given. PTX ISA Notes Target ISA Notes Examples January 24.[p+4]. or [immAddr] an immediate absolute byte address (unsigned.type d. In generic addressing.ss}. .v2.f16 data may be loaded using ldu. . and then converted to .type ldu{.b32. . [a].global. *(immAddr).u64.b16. The value loaded is sign-extended to the destination register width for signed integers. ldu. Instruction Set Table 82.Chapter 8.type = { . 2010 115 . . . Addresses are zero-extended to the specified width as needed. an address maps to global memory unless it falls within the local memory window or the shared memory window. ldu. . A destination register wider than the specified type may be used. // load from address // vec load from address . The address must be naturally aligned to a multiple of the access size. and is zeroextended to the destination register width for unsigned and bit-size types.s16. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . Introduced in PTX ISA version 2. .vec. For ldu.v4.f32.b32 d.f32 d. i.b64. only generic addresses that map to global memory are legal.global }. . The data at the specified address must be read-only.u8.s64.s8. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. If an address is not properly aligned.u32.u16. perform the load using generic addressing.v4 }. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. . A register containing an address may be declared as a bit-size type or integer type. // state space . .b8. . d. [areg] a register reg containing a byte address. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . ldu.global. Within these windows. or the instruction may fault.b16. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f64 }.vec = { .. The addressable operand a is one of: [avar] the name of an addressable variable var.[p]. Semantics d d d d = = = = a. 32-bit). .ss = { . where the address is guaranteed to be the same across all threads in the warp. *(a+immOff).f64 using cvt. and truncated if the register width exceeds the state space address width for the target architecture.0. the resulting behavior is undefined. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.global. ldu.reg state space.f64 requires sm_13 or later. i. ldu{. [a].[a].f32 Q.e. an address maps to the corresponding location in local or shared memory.s32. The address size may be either 32-bit or 64-bit. . . . 32-bit).ss}.e.f32 or .

the access may proceed by silently masking off low-order address bits to achieve proper rounding. . The address size may be either 32-bit or 64-bit.b64.b16. b. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.f64 }. [a]. .u64. and truncated if the register width exceeds the state space address width for the target architecture. In generic addressing. 32-bit).s64.s16.type st. . an integer or bit-size type register reg containing a byte address.b16.global and . PTX ISA Notes Target ISA Notes 116 January 24.wt }. If no state space is given. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.type [a].volatile{. . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. { . A source register wider than the specified type may be used. an address maps to global memory unless it falls within the local memory window or the shared memory window. . i. or [immAddr] an immediate absolute byte address (unsigned. st{. .s8. .vec. [a]. Semantics d = a. 2010 .vec . { .ss . .reg state space. .0. { . .e.cg. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .volatile may be used with .volatile. for example.u16.cs. *(immAddr) = a. to enforce sequential consistency between threads accessing shared memory. Within these windows.b32. Cache operations are not permitted with st.u8.1.global. Cache operations require sm_20 or later.f64 requires sm_13 or later. If an address is not properly aligned.volatile.s32. Generic addressing and cache operations introduced in PTX ISA 2.type st{. [a]. *d = a. b. . st. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. st.f32. . .shared spaces to inhibit optimization of references to volatile memory.ss}{. Addresses are zero-extended to the specified width as needed.cop}.cop}. st introduced in PTX ISA version 1. an address maps to the corresponding location in local or shared memory. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.e. b.shared }.b8.ss}. .ss}{. b.type = = = = {.v4 }. .volatile{.ss}. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.wb.0 Table 83.f16 data resulting from a cvt instruction may be stored using st. .PTX ISA Version 2.type . or the instruction may fault. . i. .0. perform the store using generic addressing. Generic addressing may be used with st. 32-bit). st.volatile introduced in PTX ISA version 1. .vec. Generic addressing requires sm_20 or later. *(d+immOffset) = a. .u32. the resulting behavior is undefined.cop . The address must be naturally aligned to a multiple of the access size. This may be used.v2. The lower n bits corresponding to the instruction-type width are stored to memory..local.

Q.f32 st.b32 st. [q+4].b32 st.r7.%r. [fs]. 2010 117 .local. Instruction Set Examples st.s32 st. // immediate address %r.local.v4.f32 st.global.%r. // negative offset [100].b.Chapter 8.local. [q+-8].b16 [a].f16.global. [p].s32 cvt. // %r is 32-bit register // store lower 16 bits January 24.a.a.

prefetch. the prefetch uses generic addressing.L1 [addr]. Addresses are zero-extended to the specified width as needed. 118 January 24. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. i. A prefetch into the uniform cache requires a generic address.L1 [a].0.space = { .space}. In generic addressing. an address maps to global memory unless it falls within the local memory window or the shared memory window. A prefetch to a shared memory location performs no operation. The address size may be either 32-bit or 64-bit. 2010 . prefetchu.L1. .e.L1 [ptr]. prefetch{. and no operation occurs if the address maps to a local or shared memory location. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. If no state space is given. Within these windows.global. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.L2 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.PTX ISA Version 2. // prefetch to data cache // prefetch to uniform cache .local }. prefetch and prefetchu require sm_20 or later. . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.0 Table 84. an address maps to the corresponding location in local or shared memory. a register reg containing a byte address.global. and truncated if the register width exceeds the state space address width for the target architecture.level = { .level prefetchu. 32-bit). 32-bit). [a]. in specified state space. . or [immAddr] an immediate absolute byte address (unsigned.

cvta. Introduced in PTX ISA version 2.u32 to truncate or zero-extend addresses. isspacep. isshrd. The source and destination addresses must be the same size.global. islcl. When converting a generic address into a global.local. or shared address.Chapter 8.u64 }. . For variables declared in global.space = { . . January 24. . // convert to generic address // get generic address of var // convert generic address to global.u32.to.pred .genptr. A program may use isspacep to guard against such incorrect behavior.local.size p.shared.global. // get generic address of svar cvta. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. cvta.shared }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.to.u64. Use cvt.u64. local. isspacep requires sm_20 or later. a. or shared address to a generic address. . cvta. sptr. Instruction Set Table 85.space. . . Description Convert a global.size = { .u32 or . the generic address of the variable may be taken using cvta.global isspacep. a. cvta requires sm_20 or later. // local. or shared state space. p.size . The destination register must be of type . local.space.u32 p.space p. a. or shared address cvta.size cvta.u32 gptr.space = { .shared isglbl.u32. 2010 119 .u64 or cvt. isspacep. or vice-versa.0.lptr. lptr. or vice-versa. The source address operand must be a register of type . Take the generic address of a variable declared in global. // result is .0.space.global. var. or shared state space to generic. or shared state space. p. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. local. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.local.local isspacep. PTX ISA Notes Target ISA Notes Examples Table 86. gptr. local. svar. local.u32 p.pred. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.shared }.

rni round to nearest integer. . For float-to-integer conversions. . . . .sat limits the result to MININT. cvt{. i. . a.frnd}{.irnd = { .rmi. 120 January 24.rp }.rmi round to nearest integer in direction of negative infinity . a. .rz. .irnd}{.dtype. and for same-size float-tofloat conversions where the value is rounded to an integer. subnormal inputs are flushed to signpreserving zero.f32.ftz.sat is redundant. subnormal numbers are supported.ftz}{.4 and earlier.s64. The compiler will preserve this behavior for legacy PTX code.dtype.atype = { . For cvt.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.f32 float-tofloat conversions with integer rounding.rpi }.f32 float-to-integer conversions and cvt.rm. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.sat For integer destination types.frnd = { . the result is clamped to the destination range by default. Note that saturation applies to both signed and unsigned integer types. 2010 .ftz.rn. . .PTX ISA Version 2. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rzi round to nearest integer in the direction of zero .s8.s16.u32. . .sat modifier is illegal in cases where saturation is not possible based on the source and destination types. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. Note: In PTX ISA versions 1.e. .sat}.rni. The optional .ftz modifier may be specified in these cases for clarity. choosing even integer if source is equidistant between two integers.f32 float-to-integer conversions and cvt.ftz.f32.u8. .0 Table 87. sm_1x: For cvt. Integer rounding modifiers: . .f64 }.. d = convert(a).ftz}{. .atype cvt{. Description Semantics Integer Notes Convert between different types and sizes. Integer rounding is illegal in all other instances. Saturation modifier: .MAXINT for the size of the operation.e.f16. i. subnormal inputs are flushed to signpreserving zero. . d.dtype..dtype. Integer rounding is required for float-to-integer conversions. . the .f32 float-tofloat conversions with integer rounding.u64. // integer rounding // fp rounding . .sat}.rzi.u16. . .atype d.dtype = .f32.ftz.s32.

Chapter 8. if the PTX .4 or earlier. // round to nearest int. subnormal numbers are supported.r. and . cvt. and cvt. . 1.f32 x.0.f32.s32. result is fp cvt. and for integer-to-float conversions.0]. Specifically.f64 requires sm_13 or later.s32 f.rni.f32.f16. Note: In PTX ISA versions 1.rz mantissa LSB rounds towards zero .0. Floating-point rounding modifiers: .f32. The result is an integral value. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. The operands must be of the same size.f64 j.sat For floating-point destination types. // float-to-int saturates by default cvt. cvt. The compiler will preserve this behavior for legacy PTX code. Subnormal numbers: sm_20: By default.f32. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . . Floating-point rounding is illegal in all other instances. The optional .f32.f32 x.version is 1.4 and earlier. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. Introduced in PTX ISA version 1. 2010 121 .ftz behavior for sm_1x targets January 24.y. cvt.f64 types.f32.rm mantissa LSB rounds towards negative infinity .sat limits the result to the range [0.f32. Applies to .y. // note .ftz modifier may be specified in these cases for clarity.f16.i. stored in floating-point format. Saturation modifier: .rn mantissa LSB rounds to nearest even .f16.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). NaN results are flushed to positive zero.f64.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. cvt to or from . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32 instructions. Modifier .

Texturing modes For working with textures and samplers. samplers.target options ‘texmode_unified’ and ‘texmode_independent’. {f1. add.. // get tex1’s txq. . . and surface descriptors. r1. cvt.global . allowing them to be defined separately and combined at the site of usage in the program. r5. sampler.v4.height. // get tex1’s tex. r3.entry compute_power ( .f32 r1.f2}]. and surface descriptors: • • • Static initialization of texture. mul. the file is assumed to use unified mode.target texmode_independent . A PTX module may declare only one texturing mode. but the number of samplers is greatly restricted to 16. Ability to query fields within texture. r5. 2010 .0 8.2d.r3.texref tex1 ) { txq. [tex1]. sampler. In the independent mode.width. . The advantage of unified mode is that it allows 128 samplers. texture and sampler information is accessed through a single .7.f32 r3.f32 {r1.f32.texref handle. The texturing mode is selected using .f32 r1.samplerref tsamp1 = { addr_mode_0 filter_mode }.u32 r5.r4}. add.PTX ISA Version 2. r5. div. = nearest width height tsamp1. r2.b32 r5.param . In the unified mode. r6. Texture and Surface Instructions This section describes PTX instructions for accessing textures. sampler. PTX has two modes of operation.r2. The advantage of independent mode is that textures and samplers can be mixed and matched. sampler. Module-scope and per-entry scope definitions of texture. If no texturing mode is declared. texture and sampler information each have their own handle. and surface descriptors. PTX supports the following operations on texture. r1. 122 January 24. r4. [tex1].. with the restriction that they correspond 1-to-1 with the 128 possible textures.u32 r5. [tex1. and surface descriptors. r1.b32 r6. add.f32. } = clamp_to_border.f32 r1.6. Example: calculate an element’s power contribution as element’s power/total number of elements. r3. and surfaces.

or the instruction may fault.s32 {r1.r4}. .geom. Notes For compatibility with prior versions of PTX.f32 }. Operand c is a scalar or singleton tuple for 1d textures. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.r2. Unified mode texturing introduced in PTX ISA version 1.dtype. with the extra elements being ignored.f32 }.s32. b. // explicit sampler . and is a four-element vector for 3d textures.e. The instruction always returns a four-element vector of 32-bit values.geom.r3. // Example of independent mode texturing tex.0..v4. the access may proceed by silently masking off low-order address bits to achieve proper rounding.dtype = { . . A texture base address is assumed to be aligned to a 16-byte address. Supported on all target architectures. is a two-element vector for 2d textures. .f32 {r1. . tex.f4}].r4}.u32. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.f3. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. .dtype. .v4.geom = { .btype = { . the sampler behavior is a property of the named texture. PTX ISA Notes Target ISA Notes Examples January 24. If an address is not properly aligned. {f1}].3d.v4.r2. c]. c].s32. sampler_x.btype tex. d.1d. i. 2010 123 . {f1. where the fourth element is ignored.s32. . Description Texture lookup using a texture coordinate vector. [tex_a. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.v4.s32. tex txq suld sust sured suq Table 88.2d. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. [a.f2. the resulting behavior is undefined.1d. //Example of unified mode texturing tex.r3.v4 coordinate vectors are allowed for any geometry. Instruction Set These instructions provide access to texture and surface memory.3d }. [tex_a.btype d. [a.Chapter 8. An optional texture sampler b may be specified. If no sampler is specified. the square brackets are not required and .5.

texref or . // unified mode // independent mode 124 January 24. d. Description Query an attribute of a texture or sampler. Supported on all target architectures.addr_mode_0. clamp_ogl.squery = { . // texture attributes // sampler attributes .b32 %r1. [tex_A]. . . [smpl_B]. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. In unified mode. Operand a is a . [a]. [a]. . mirror.b32 %r1.b32 d. sampler attributes are also accessed via a texref argument.tquery.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).0 Table 89.filter_mode. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. [tex_A]. and in independent mode sampler attributes are accessed via a separate samplerref argument. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.squery.filter_mode .width. addr_mode_2 }.samplerref variable. .addr_mode_0 .width . txq.5.b32 txq.normalized_coords }.depth.filter_mode. addr_mode_1. Integer from enum { nearest.height .depth . txq.addr_mode_1 .PTX ISA Version 2. Query: .width.normalized_coords . clamp_to_edge.addr_mode_0. . 2010 .b32 %r1.height. txq.tquery = { . txq. linear } Integer from enum { wrap.

[surf_B. {f1.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. suld Syntax Texture and Surface Instructions: suld Load from surface memory. // for suld. // unformatted d. suld.s32.3d. Destination vector elements corresponding to components that do not appear in the surface format are not written. // cache operation none.0. . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.p.dtype .trap clamping modifier. the access may proceed by silently masking off low-order address bits to achieve proper rounding. then .1d.b . Coordinate elements are of type . b]. If the destination base type is .cop}.f3. and the size of the data transfer matches the size of destination operand d.trap.b32.u32 is returned.y.1d.b supported on all target architectures.b32. and is a four-element vector for 3d surfaces. suld. [a.v4.v4. .f4}. // for suld. {x. Target ISA Notes Examples January 24.Chapter 8.. and A components of the surface format.surfref variable.w}]. sm_1x targets support only the . the surface sample elements are converted to .p requires sm_20 or later.dtype . The .v2.f32 is returned. Operand a is a .trap introduced in PTX ISA version 1. the resulting behavior is undefined. suld. suld.b64.zero }. .5. A surface base address is assumed to be aligned to a 16-byte address.vec. .v4 }. suld.cop . // formatted . .b16.e. .geom{.v2. {x}]. if the surface format contains UINT data. suld. If an address is not properly aligned. .zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. then .vec . or FLOAT data. . then .dtype.f32 based on the surface format as follows: If the surface format contains UNORM.trap {r1.b64 }. if the surface format contains SINT data.trap .s32 is returned.p . If the destination type is . where the fourth element is ignored. or the instruction may fault.cg.clamp = = = = = = { { { { { { d.b.u32. The lowest dimension coordinate represents a sample offset rather than a byte offset. Operand b is a scalar or singleton tuple for 1d surfaces.s32. .trap suld. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . [a.u32. Description Load from surface memory using a surface coordinate vector.f32. or . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .2d.u32. and cache operations introduced in PTX ISA version 2. Instruction Set Table 90.b performs an unformatted load of binary data.ca. .3d requires sm_20 or later.z. .b.p.f2. B.cop}.cs.f32.b. suld. Cache operations require sm_20 or later. size and type conversion is performed as needed to convert from the surface sample format to the destination type.s32. is a two-element vector for 2d surfaces.p is currently unimplemented. G. .clamp suld. additional clamp modifiers.s32. suld.dtype. b]. SNORM.clamp. .r2}. or . i.geom{.clamp . . suld.p. 2010 125 .b8 .3d }.cv }.geom .clamp . [surf_A. .f32 }.clamp field specifies how to handle out-of-bounds addresses: . . .b32.

sust.clamp.. The lowest dimension coordinate represents a sample offset rather than a byte offset.u32.r2}.f32 is assumed.cop . sm_1x targets support only the .0. or FLOAT data.5. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and A surface components.1d. .trap.vec.vec .b64 }.u32.trap [surf_A. sust. c.ctype. . . .e. sust.1d.s32 is assumed. if the surface format contains UINT data.cg. sust Syntax Texture and Surface Instructions: sust Store to surface memory. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.p.0 Table 91.s32.clamp sust.p performs a formatted store of a vector of 32-bit data values to a surface sample. Coordinate elements are of type .v2. {r1.PTX ISA Version 2. sust. The size of the data transfer matches the size of source operand c. If the source base type is . . is a two-element vector for 2d surfaces. then .geom .{u32.b.w}]. or the instruction may fault. .wt }. . and cache operations introduced in PTX ISA version 2. .v2.cop}. then . The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.trap sust.p. Source elements that do not occur in the surface sample are ignored. If an address is not properly aligned.2d.trap . Operand a is a . These elements are written to the corresponding surface sample components. {x}].b supported on all target architectures. then . {f1.p Description Store to surface memory using a surface coordinate vector.y.b64. i. B. {x. c. sust.vec.s32.3d. .f32. the resulting behavior is undefined.cs. Cache operations require sm_20 or later. [a. .f2. // unformatted // formatted . sust. sust.b8 . or . Operand b is a scalar or singleton tuple for 1d surfaces.s32.b. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.b // for sust.surfref variable.v4 }.f32 }.clamp .geom{. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.s32.geom{. G.p. b]. . .f3.b.zero }.b16.ctype . The . Target ISA Notes Examples 126 January 24.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.clamp . [surf_B. Surface sample components that do not occur in the source vector will be written with an unpredictable value.ctype . sust.u32 is assumed. // for sust.clamp field specifies how to handle out-of-bounds addresses: . if the surface format contains SINT data.wb.clamp = = = = = = { { { { { { [a. The source vector elements are interpreted left-to-right as R. .p requires sm_20 or later. sust. 2010 . If the source type is .trap introduced in PTX ISA version 1.f32. and is a four-element vector for 3d surfaces. additional clamp modifiers.b32. .b32. .3d }.v4. b]. where the fourth element is ignored. . . SNORM.f32} are currently unimplemented. The source data is then converted from this type to the surface sample format.cop}.ctype. A surface base address is assumed to be aligned to a 16-byte address.trap clamping modifier.z. size and type conversions are performed as needed between the surface sample format and the destination type.b32.b performs an unformatted store of binary data.p. none.f4}.3d requires sm_20 or later. . . .

January 24.trap [surf_A. sured. If an address is not properly aligned. the resulting behavior is undefined.b].or }.p.and.op.u32 is assumed. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. // sample addressing . The instruction type is restricted to .ctype.clamp field specifies how to handle out-of-bounds addresses: .ctype = { . .s32.u64 data.u64. .min.op.u32.u32.u32 and .Chapter 8. then . Operand b is a scalar or singleton tuple for 1d surfaces. {x}].trap sured.clamp .s32. Coordinate elements are of type . Instruction Set Table 92.p performs a reduction on sample-addressed 32-bit data.geom.0.b].b .clamp.zero }. The lowest dimension coordinate represents a sample offset rather than a byte offset.b32. and the data is interpreted as . {x. if the surface format contains SINT data.s32 is assumed. .ctype = { . sured.c.clamp [a. . 2010 127 . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . sured. .u32 based on the surface sample format as follows: if the surface format contains UINT data. r1. where the fourth element is ignored.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.2d.e.p.b32 }. the access may proceed by silently masking off low-order address bits to achieve proper rounding.3d }. sured.b32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. // for sured.y}]. // for sured. Operand a is a .b performs an unformatted reduction on .min.add.1d. or .geom = { .surfref variable. .trap .s32 types. . . sured requires sm_20 or later. is a two-element vector for 2d surfaces.b. operations and and or apply to . . .p . A surface base address is assumed to be aligned to a 16-byte address.b32 }.u32.1d.u32.clamp [a. and . // byte addressing sured. Reduction to surface memory using a surface coordinate vector. .b. Operations add applies to .max. r1. or the instruction may fault. .s32 types.2d..c. . . and is a four-element vector for 3d surfaces.geom.ctype.op = { .clamp = { .b32 type.s32. i. The . min and max apply to .trap. then .add. .b32.s32 or . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.u64. [surf_B.

.query. Query: .depth }. [a].query = { . Operand a is a .b32 %r1. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. 2010 .height . .5.height. Supported on all target architectures.width .b32 d. suq.surfref variable. Description Query an attribute of a surface. . suq.PTX ISA Version 2.0 Table 93.width.width. [surf_A]. 128 January 24.

b. Instruction Set 8. If {!}p then instruction Introduced in PTX ISA version 1. Supported on all target architectures. Supported on all target architectures. used primarily for defining a function body.eq.a.x.7. {} Syntax Description Control Flow Instructions: { } Instruction grouping. { add. @{!}p instruction. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.f32 @q bra L23. setp.7. Execute an instruction or instruction block for threads that have the guard predicate true.Chapter 8. Threads with a false guard predicate do nothing.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.0.0. ratio.0. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. } PTX ISA Notes Target ISA Notes Examples Table 95.c. 2010 129 . { instructionList } The curly braces create a group of instructions.s32 a. p.f32 @!p div. mov.s32 d. Introduced in PTX ISA version 1.y.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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January 24.red instruction.red. and any-thread-true (. bar.and).op = { .red should not be intermixed with bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution..red also guarantee memory ordering among threads identical to membar. {!}c. In conditionally executed code.sync) until the barrier count is met. bar. Execution in this case is unpredictable. and then safely read values stored by other threads prior to the barrier. all-threads-true (. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. Register operands.arrive does not cause any waiting by the executing threads.and and .sync bar. b.sync and bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. all threads in the CTA participate in the barrier.0.version 2. Only bar. Since barriers are executed on a per-warp basis. thread count. b}.u32. threads within a CTA that wish to communicate via memory can store to memory.pred . The result of . All threads in the warp are stalled until the barrier completes. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). the waiting threads are restarted without delay.sync and bar. . Operands a. 2010 133 .popc).red} require sm_20 or later.red delays the executing threads (similar to bar. and d have type .arrive a{. execute a bar. {!}c. Note that a non-zero thread count is required for bar.arrive.red performs a reduction operation across threads.{arrive.arrive using the same active barrier. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). the final value is written to the destination register in all threads waiting at the barrier. bar.0. The reduction operations for bar. b}. bar. Thus. it simply marks a thread's arrival at the barrier.or). while . thread count. b.red} introduced in PTX . Once the barrier count is reached.sync or bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. If no thread count is specified. d.popc is the number of threads with a true predicate. Thus.u32 bar. it is as if all the threads in the warp have executed the bar instruction. a{. a. Instruction Set Table 100. Description Performs barrier synchronization and communication within a CTA. and bar.red performs a predicate reduction across the threads participating in the barrier. b}. In addition to signaling its arrival at the barrier. and the barrier is reinitialized so that it can be immediately reused. bar.or }.Chapter 8.red. Register operands. if any thread in a warp executes a bar instruction. The barrier instructions signal the arrival of the executing threads at the named barrier.cta. Operand b specifies the number of threads participating in the barrier.popc.15. operands p and c are predicates. the bar. Each CTA instance has sixteen barriers numbered 0. a{. bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active.op.sync or bar.red are population-count (.and. When a barrier completes. bar. p.sync with an immediate barrier number is supported for sm_1x targets. the optional thread count must be a multiple of the warp size.sync 0. bar. PTX ISA Notes Target ISA Notes Examples bar. bar.{arrive. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. and bar.sync without a thread count introduced in PTX ISA 1.

membar.{cta.level. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.gl} supported on all target architectures. A memory read (e. membar. that is.cta Waits until all prior memory writes are visible to other threads in the same CTA.gl.4. membar.gl} introduced in PTX . red or atom) has been performed when the value written has become visible to other clients at the specified level.gl.level = { .gl. this is the appropriate level of membar. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys will typically have much longer latency than membar. A memory write (e. . membar. including thoses communicating via PCI-E such as system and peer-to-peer memory.{cta. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. .sys. and memory reads by this thread can no longer be affected by other thread writes. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.sys introduced in PTX . membar. membar.sys requires sm_20 or later.version 2. membar.cta. level describes the scope of other clients for which membar is an ordering event. membar. membar. For communication between threads in different CTAs or even different SMs. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. 134 January 24.cta.g. or system memory level.cta. PTX ISA Notes Target ISA Notes Examples membar.sys Waits until all prior memory requests have been performed with respect to all clients. 2010 . by st. global.0 Table 101.0.g.PTX ISA Version 2.gl will typically have a longer latency than membar.sys }. membar. .version 1. membar. when the previous value can no longer be read. membar.

an address maps to the corresponding location in local or shared memory. .op = { . accesses to local memory are illegal. Instruction Set Table 102. the access may proceed by silently masking off low-order address bits to achieve proper rounding.e. an address maps to global memory unless it falls within the local memory window or the shared memory window. atom.s32. . For atom..u32. overwriting the original value.space = { . xor. . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.space}. .inc.e. cas (compare-and-swap).op. e.shared }.u64.s32. . . [a].u32. perform the memory accesses using generic addressing.. .b64 . . and max. max.u32. If no state space is given. The floating-point add.exch to store to locations accessed by other atomic operations.b32. . a de-referenced register areg containing a byte address. inc. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . . . . . atom{. Operand a specifies a location in the specified state space. performs a reduction operation with operand b and the value in location a. min. Description // // // // // . c. If an address is not properly aligned.u64 .exch. the resulting behavior is undefined. min. .b32 only . by inserting barriers between normal stores and atomic operations to a common address. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Addresses are zero-extended to the specified width as needed. The address must be naturally aligned to a multiple of the access size. .xor. A register containing an address may be declared as a bit-size type or integer type. . .type atom{.s32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. .type d. 32-bit operations. In generic addressing.b32. .u32 only . The integer operations are add. and stores the result of the specified operation at location a. The floating-point operations are add. [a].add. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.Chapter 8.max }.add. d. or the instruction may fault. The bit-size operations are and. b.f32 Atomically loads the original value at location a into destination register d. i.min. min.type = { . January 24. b.or.g.b64.cas.and. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. .global.f32.space}. or. or by using atom. i. 2010 135 . and truncated if the register width exceeds the state space address width for the target architecture. . The address size may be either 32-bit or 64-bit. and max operations are single-precision.b]. The inc and dec operations return a result in the range [0. or [immAddr] an immediate absolute byte address.f32 }.op.dec. Within these windows. and exch (exchange). dec. .

Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.t) = (r == s) ? t operation(*a. : r+1.s.shared requires sm_12 or later.shared.max.1. c) operation(*a.max} are unimplemented.s32 atom. 64-bit atom.{add.f32.0.exch} requires sm_12 or later.PTX ISA Version 2. atom. Use of generic addressing requires sm_20 or later. d.add. d.shared operations require sm_20 or later. Introduced in PTX ISA version 1.0.{min. Release Notes Examples @p 136 January 24. atom.0 Semantics atomic { d = *a.[a].global requires sm_11 or later. s) = (r >= s) ? 0 dec(r. atom.f32 requires sm_20 or later. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. : r.global.add.[p].b32 d.my_new_val. b. *a = (operation == cas) ? : } where inc(r. s) = (r > s) ? s exch(r. cas(r.cas.cas.f32 atom. : r-1. 64-bit atom.my_val. 2010 .[x+4].global. b). atom. s) = s. atom.

add. A register containing an address may be declared as a bit-size type or integer type. and max. . perform the memory accesses using generic addressing..u32. or. . red{.space}. . . If an address is not properly aligned. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The floating-point operations are add. i. .space = { . dec. Addresses are zero-extended to the specified width as needed.e. .u32. . Notes Operand a must reside in either the global or shared state space.dec.inc.u32. . .global. Operand a specifies a location in the specified state space. 2010 137 .and. The floating-point add. b.xor.b]. . The address size may be either 32-bit or 64-bit. an address maps to the corresponding location in local or shared memory. . and xor. s) = (r > s) ? s : r-1. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. and stores the result of the specified operation at location a. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. the resulting behavior is undefined. and truncated if the register width exceeds the state space address width for the target architecture.f32. . where inc(r. . a de-referenced register areg containing a byte address. b). The address must be naturally aligned to a multiple of the access size.u64.min. . or by using atom. e. min. . Instruction Set Table 103. red. 32-bit operations.s32. and max operations are single-precision. accesses to local memory are illegal.or.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . .type [a]. min. i.shared }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . Description // // // // .exch to store to locations accessed by other reduction operations. or the instruction may fault. or [immAddr] an immediate absolute byte address.. Within these windows.e. an address maps to global memory unless it falls within the local memory window or the shared memory window.add.s32. . For red.s32. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.b64.u32 only .Chapter 8.max }. overwriting the original value. max. dec(r. In generic addressing. inc. The inc and dec operations return a result in the range [0. .u64 . The integer operations are add.b32 only . s) = (r >= s) ? 0 : r+1.f32 }.b32. . The bit-size operations are and. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.op = { .op. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.type = { . min.g. by inserting barriers between normal stores and reduction operations to a common address. January 24.f32 Performs a reduction operation with operand b and the value in location a. If no state space is given. Semantics *a = operation(*a.

PTX ISA Version 2.{min.max. red. Release Notes Examples @p 138 January 24.and.add. 64-bit red. [p].global. [x+4].max} are unimplemented.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.s32 red. 2010 . 64-bit red.f32 red.add requires sm_12 or later. red. red.1.global requires sm_11 or later red.f32. red.f32 requires sm_20 or later.shared.my_val.global.shared requires sm_12 or later.add.b32 [a].2. Use of generic addressing requires sm_20 or later.shared operations require sm_20 or later.0.

Negate the source predicate to compute . r1.uni True if source predicate has the same value in all active threads in warp. The destination predicate value is the same across all threads in the warp.b32 d. where the bit position corresponds to the thread’s lane id. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.none. {!}a. vote.pred vote. vote. vote. Negating the source predicate also computes .uni.Chapter 8. The reduction modes are: .all.ballot. .b32 requires sm_20 or later. not across an entire CTA. returns bitmask .ballot. Description Performs a reduction of the source predicate across threads in a warp.any True if source predicate is True for some active thread in warp.ballot.2. Negate the source predicate to compute .b32 p. .ballot. p.uni.q.p. vote.all True if source predicate is True for all active threads in warp. // ‘ballot’ form.all.pred d. . In the ‘ballot’ form. .pred vote. Note that vote applies to threads in a single warp.any. {!}a.mode. // get ‘ballot’ across warp January 24. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.q.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.mode = { . vote. 2010 139 . vote requires sm_12 or later.uni }.not_all. Instruction Set Table 104.

c. 140 January 24. 4. a{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.h0.sat} d.asel = . optionally clamp the result to the range of the destination type. .max }.or zero-extend byte. b{.b1. or word values from its source operands. .secop d. .add. The source and destination operands are all 32-bit registers. to produce signed 33-bit input values.asel}.bsel = { . .b2. extract and sign.dtype. .sat}.min. The sign of the intermediate result depends on dtype. .s32 }. a{. The primary operation is then performed to produce an . 2. perform a scalar arithmetic operation to produce a signed 34-bit result. 3.0 8.b3.asel}.u32.secop = { . with optional data merge vop. b{. The type of each operand (.atype.btype{.atype. half-word. taking into account the subword destination size in the case of optional data merging. the input values are extracted and signor zero. all combinations of dtype. Using the atype/btype and asel/bsel specifiers.dsel.btype = { . The general format of video instructions is as follows: // 32-bit scalar operation.bsel}.s33 values.btype{.dtype.h1 }. b{.s34 intermediate result. . with optional secondary operation vop.dtype.s32) is specified in the instruction type. and btype are valid.bsel}. // 32-bit scalar operation.bsel}.atype = . atype. . .sat} d. a{. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. .b0. vop.7.dsel = . c. . 2010 .btype{.9. Video Instructions All video instructions operate on 32-bit register operands. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).u32 or .atype.extended internally to .asel}.dtype = .PTX ISA Version 2.

U8_MIN ). .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. 2010 141 . tmp. S32_MAX.b0: return ((tmp & 0xff) case . .Chapter 8. c). . default: return tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). U16_MIN ). Bool sat.b0. S32_MIN ). S16_MIN ). .h1: return ((tmp & 0xffff) << 16) case . S8_MAX.s33 optSecOp(Modifier secop. Bool sign. . . c). The sign of the c operand is based on dtype.s33 c ) switch ( dsel ) { case .s34 tmp. U16_MAX. . The lower 32-bits are then written to the destination operand.b3: if ( sign ) return CLAMP( else return CLAMP( case .h0. switch ( dsel ) { case .s33 c) { switch ( secop ) { . Modifier dsel ) { if ( !sat ) return tmp. . tmp. January 24. as shown in the following pseudocode. U32_MIN ). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 tmp. c). } } . . tmp.add: return tmp + c. U8_MAX.b1: return ((tmp & 0xff) << 8) case .b2. . . S16_MAX.s33 optSaturate( . c). tmp. c).h0: return ((tmp & 0xffff) case . Instruction Set .max return MAX(tmp. U32_MAX.b3: return ((tmp & 0xff) << 24) default: return tmp.min: return MIN(tmp.b1. c).s33 optMerge( Modifier dsel. c).b2: return ((tmp & 0xff) << 16) case .s33 tmp. S8_MIN ). tmp.

PTX ISA Version 2. vsub. c.bsel = { . c ). tmp = ta – tb. d = optSecondaryOp( op2. tmp. . vsub.s32.s32. a{.dtype. tb ).sat}.h0.b2. r2. .dtype. vadd. vabsdiff. b{. asel ).min. atype.s32. 2010 . // 32-bit scalar operation.b2. // optional secondary operation d = optMerge( dsel. vsub vabsdiff vmin. r3.s32. . r1. tmp = | ta – tb |. isSigned(dtype).s32.atype. Video Instructions: vadd.s32.asel = .asel}.h1.b0. btype. tmp = MAX( ta. with optional data merge vop.s32.sat.atype. // optional merge with c operand 142 January 24.dtype . Perform scalar arithmetic operation with optional saturate. Integer byte/half-word/word minimum / maximum. tmp = MIN( ta.bsel}.bsel}. . vabsdiff. r1.0.u32.op2 d. a{. b{.s32. r3. .b3.u32.atype. a{.h0. Semantics // saturate. r1.btype{. bsel ).max }.sat} d. vmax Syntax Integer byte/half-word/word addition / subtraction. vmin.atype = .h0. r2.add. vabsdiff. vop. r3.sat vsub.0 Table 105. r2. r3. and optional secondary arithmetic operation or subword data merge.h1.dsel . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. vmin.s32. vmax vadd. vmin. .bsel}.asel}. c ). tb ). .u32. c.op2 Description = = = = { vadd. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vsub. vmax require sm_20 or later.s32 }. // 32-bit scalar operation.btype = { . sat. vmax }. dsel ).sat} d. .b0. tmp. c.dsel.h1 }. // extract byte/half-word/word and sign.sat vabsdiff. taking into account destination type and merge operations tmp = optSaturate( tmp.btype{.b1. tb = partSelectSignExtend( b. .or zero-extend based on source operand type ta = partSelectSignExtend( a.sat vmin. b{. . .add r1.s32.asel}. vadd. with optional secondary operation vop.vop .dtype. Integer byte/half-word/word absolute value of difference.b0. c. { . r2.btype{.

b0. b{. Instruction Set Table 106. a{. vshl. Signed shift fills with the sign bit.s32 }. vshr: Shift a right by unsigned amount in b with optional saturate. c ).clamp .h1 }.mode .u32.bsel}. tb = partSelectSignExtend( b. . .wrap ) tb = tb & 0x1f.Chapter 8.b1.bsel = { . vop.dtype. r3. c.wrap }.u32.u32 vshr.dtype .dtype. . // 32-bit scalar operation.min.sat}{.asel}. unsigned shift fills with zero. sat. c ). a{. 2010 143 .atype.atype. .clamp && tb > 32 ) tb = 32.atype = { .h0. r3.mode}. a{.mode} d. atype.add.asel}. vshr vshl. // 32-bit scalar operation.u32. { . vshr require sm_20 or later. tmp.dsel. vshr }. asel ). and optional secondary arithmetic operation or subword data merge.op2 d.s32. switch ( vop ) { case vshl: tmp = ta << tb. } // saturate.wrap r1.u32{. Semantics // extract byte/half-word/word and sign. b{. . with optional secondary operation vop. r1.dsel . bsel ).asel}. r2. . taking into account destination type and merge operations tmp = optSaturate( tmp. { . .asel = . // optional secondary operation d = optMerge( dsel. if ( mode == . . case vshr: tmp = ta >> tb. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . . vshl.h1.clamp.b2. January 24.sat}{.u32{.u32{. . . dsel ). vshl: Shift a left by unsigned amount in b with optional saturate.max }.vop . // default is . tmp. c.bsel}.bsel}. Video Instructions: vshl.u32. b{. isSigned(dtype). with optional data merge vop.b3.u32.mode} d.dtype.op2 Description = = = = = { vshl. vshr Syntax Integer byte/half-word/word left / right shift. Left shift fills with zero. r2. if ( mode == . d = optSecondaryOp( op2.u32.sat}{. and optional secondary arithmetic operation or subword data merge.or zero-extend based on source operand type ta = partSelectSignExtend( a.atype.0.

with optional operand negates. final signed (S32 * U32) . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. . .0 Table 107. .asel}.btype = { . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.po mode.sat}{.dtype = . b{.scale} d. 2010 .atype. . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.U32 // intermediate unsigned. Although PTX syntax allows separate negation of the a and b operands.atype.dtype.scale = { . The source operands support optional negation with some restrictions. final signed (U32 * S32) .po) computes (a*b) + c + 1. internally this is represented as negation of the product (a*b). final signed The intermediate result is optionally scaled via right-shift. “plus one” mode.b3. and the operand negates. {-}c. final signed (S32 * S32) . Description Calculate (a*b) + c. final signed -(S32 * S32) + S32 // intermediate signed. otherwise.s32 }. .b0. and scaling.shr15 }.S32 // intermediate signed. c. final unsigned -(U32 * U32) + S32 // intermediate signed.po{. which is used in computing averages. (a*b) is negated if and only if exactly one of a or b is negated. .bsel}. and zero-extended otherwise. final signed -(S32 * U32) + S32 // intermediate signed. {-}a{.S32 // intermediate signed.atype = . final signed (U32 * U32) . . That is. Input c has the same sign as the intermediate result. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.btype{. vmad.bsel = { . Source operands may not be negated in .scale} d.h1 }. .h0. final signed -(U32 * S32) + S32 // intermediate signed..PTX ISA Version 2. a{. .S32 // intermediate signed.dtype. this result is sign-extended if the final result is signed. . PTX allows negation of either (a*b) or c. the intermediate result is signed.b1. The final result is unsigned if the intermediate result is unsigned and c is not negated. Depending on the sign of the a and b operands. The “plus one” mode (.sat}{.asel = .asel}.bsel}.btype. // 32-bit scalar operation vmad.u32. final signed (S32 * U32) + S32 // intermediate signed. {-}b{. 144 January 24.shr7. final signed (U32 * S32) + S32 // intermediate signed. final signed (S32 * S32) + S32 // intermediate signed.b2.

u32.negate ^ b.or zero-extend based on source operand type ta = partSelectSignExtend( a. lsb = 1. tmp[127:0] = ta * tb.sat ) { if (signedFinal) result = CLAMP(result. case . Instruction Set Semantics // extract byte/half-word/word and sign. r0. signedFinal = isSigned(atype) || isSigned(btype) || (a.negate.s32. tmp = tmp + c128 + lsb. U32_MIN). } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. -r3. switch( scale ) { case .u32. } else if ( c.u32. S32_MIN).po ) { lsb = 1. r2. r1. January 24. btype. S32_MAX. if ( .s32.negate ) { c = ~c. else result = CLAMP(result. lsb = 0. r3. U32_MAX.shr15: result = (tmp >> 15) & 0xffffffffffffffff.u32.0. vmad requires sm_20 or later. atype. lsb = 1.shr7: result = (tmp >> 7) & 0xffffffffffffffff. bsel ). asel ). vmad. r1. } else if ( a.negate) || c. 2010 145 . } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).sat vmad.h0.shr15 r0. tb = partSelectSignExtend( b. } if ( .Chapter 8.h0. r2.negate ) { tmp = ~tmp.negate ^ b.

2010 .cmp. tmp. .b1.atype.s32 }.s32.ge }. a{.op2 d.btype.min. vset requires sm_20 or later. atype. with optional secondary arithmetic operation or subword data merge. Compare input values using specified comparison.dsel.b3. { . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r3.h1 }. . // 32-bit scalar operation.asel}. b{.u32.ne. r2. vset. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.lt vset.ne r1.bsel}. tmp = compare( ta. . a{.cmp d.asel}.le. c. .cmp . .bsel = { . with optional secondary operation vset. .0.b0. r2.btype. vset. Semantics // extract byte/half-word/word and sign. bsel ).0 Table 108. . r3. b{.gt. tmp. The intermediate result of the comparison is always unsigned.dsel . with optional data merge vset. . and therefore the c operand and final result are also unsigned. tb = partSelectSignExtend( b. . . cmp ) ? 1 : 0. .b2.atype. c ).h0. tb.asel = . d = optSecondaryOp( op2.u32.cmp d.asel}. r1. { .u32.eq. .max }.op2 Description = = = = .add. .lt.PTX ISA Version 2. . // 32-bit scalar operation. a{. asel ).bsel}.bsel}.atype .u32.h1. b{. .btype = { .btype.or zero-extend based on source operand type ta = partSelectSignExtend( a. // optional secondary operation d = optMerge( dsel. c ). 146 January 24.atype. c. btype.

brkpt. trap Abort execution and generate an interrupt to the host CPU.0.Chapter 8. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. @p pmevent 1. Table 110.10. Supported on all target architectures.4. Instruction Set 8. trap. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. 2010 147 .7. Notes PTX ISA Notes Target ISA Notes Examples Currently. pmevent a. brkpt. brkpt Suspends execution Introduced in PTX ISA version 1. January 24. brkpt requires sm_11 or later.0. pmevent 7. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. with index specified by immediate operand a. Introduced in PTX ISA version 1. numbered 0 through 15. Supported on all target architectures. Introduced in PTX ISA version 1. there are sixteen performance monitor events. Table 111. Triggers one of a fixed number of performance monitor events. The relationship between events and counters is programmed via API calls from the host. trap.

0 148 January 24.PTX ISA Version 2. 2010 .

%lanemask_le. 2010 149 . The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %pm3 January 24. read-only variables. Special Registers PTX includes a number of predefined. %lanemask_gt %clock. %clock64 %pm0.Chapter 9. …. which are visible as special registers and accessed through mov or cvt instructions. %lanemask_ge. %lanemask_lt.

y. cvt. // thread id vector // thread id components A predefined. . mad. mov. read-only special register initialized with the number of thread ids in each CTA dimension. mov. %tid.%h2.u32 %r1. // legacy PTX 1. %ntid.v4 . Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.v4.u32 %ntid.x < %ntid.u16 %rh.z to %r2 Table 113. %tid component values range from 0 through %ntid–1 in each CTA dimension.x code Target ISA Notes Examples 150 January 24.x to %rh Target ISA Notes Examples // legacy PTX 1.z PTX ISA Notes Introduced in PTX ISA version 1. // zero-extend tid.sreg . %ntid. Redefined as . the %tid value in unused dimensions is 0.%tid.%r0. mov. Supported on all target architectures. . Every thread in the CTA has a unique %tid. // move tid.u16 %r2.0.u32 %r0.u32 %r0.x code accessing 16-bit component of %tid mov.%ntid.u32 %h2. .x.%tid.u32 %h1. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.0. 2D.y 0 <= %tid. The fourth element is unused and always returns zero. or 3D vector to match the CTA shape.x 0 <= %tid.0 Table 112.u32.u32 %tid. per-thread special register initialized with the thread identifier within the CTA. The total number of threads in a CTA is (%ntid.x. CTA dimensions are non-zero.v4.PTX ISA Version 2.%h1.u16 %rh.u32 type in PTX 2. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. %ntid. It is guaranteed that: 0 <= %tid.z. %ntid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.x.sreg .y. PTX ISA Notes Introduced in PTX ISA version 1. 2010 . The number of threads in each dimension are specified by the predefined special register %ntid.y == %tid. read-only.0.sreg . %tid.x.z == 0 in 2D CTAs.z == 1 in 2D CTAs.z).z. %tid. // compute unified thread id for 2D CTA mov. the fourth element is unused and always returns zero.u32 %tid.%ntid.z == 0 in 1D CTAs.y * %ntid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u32 type in PTX 2.y == %ntid.sreg .z == 1 in 1D CTAs. // CTA shape vector // CTA dimensions A predefined. .y < %ntid.%tid. The %tid special register contains a 1D.z.x.u32 %ntid. Supported on all target architectures.z < %ntid.x * %ntid. Redefined as .v4 .%tid.x.%tid.0.x.y. %tid. mov.

The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. 2010 151 .u32 %r. Note that %warpid is volatile and returns the location of a thread at the moment when read. For this reason. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. %laneid. Introduced in PTX ISA version 1.u32 %warpid.u32 %laneid.u32 %r. Introduced in PTX ISA version 1. mov. %warpid. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. e.3. mov. The warp identifier will be the same for all threads within a single warp. read-only special register that returns the maximum number of warp identifiers. Supported on all target architectures.3. Table 115. A predefined. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. mov.sreg . The lane identifier ranges from zero to WARP_SZ-1.sreg . read-only special register that returns the thread’s warp identifier.g.u32 %r. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %nwarpid requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Table 116. . January 24. A predefined. Introduced in PTX ISA version 2. %nwarpid.0. A predefined. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. . . but its value may change during execution. read-only special register that returns the thread’s lane within the warp. Supported on all target architectures. Special Registers Table 114. due to rescheduling of threads following preemption.Chapter 9.sreg .u32 %nwarpid.

.0 Table 117.y < %nctaid.v4 . %rh.y.z < %nctaid.{x. The fourth element is unused and always returns zero. %ctaid.0. mov.x 0 <= %ctaid.u32 mov. read-only special register initialized with the CTA identifier within the CTA grid. . Redefined as .y.x. mov.536 PTX ISA Notes Introduced in PTX ISA version 1. %rh.z. // legacy PTX 1. . Redefined as .v4.%nctaid.y.u32 type in PTX 2.sreg .%nctaid.v4 .x.u32 %nctaid .%nctaid.%ctaid. Supported on all target architectures.u32 type in PTX 2. It is guaranteed that: 0 <= %ctaid.y. // Grid shape vector // Grid dimensions A predefined.%ctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.0. The %nctaid special register contains a 3D grid shape vector. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.u32 mov.u16 %r0. or 3D vector.0.u16 %r0.z PTX ISA Notes Introduced in PTX ISA version 1. The %ctaid special register contains a 1D.x.u32 %ctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.v4.u32 %nctaid. // CTA id vector // CTA id components A predefined. 2D.z} < 65. with each element having a value of at least 1. Each vector element value is >= 0 and < 65535.x.x code Target ISA Notes Examples Table 118. The fourth element is unused and always returns zero.sreg . read-only special register initialized with the number of CTAs in each grid dimension. %ctaid.PTX ISA Version 2.x.sreg . Supported on all target architectures.y 0 <= %ctaid.0.z.sreg . // legacy PTX 1. 2010 . depending on the shape and rank of the CTA grid. It is guaranteed that: 1 <= %nctaid.x code Target ISA Notes Examples 152 January 24.u32 %ctaid.%nctaid.x < %nctaid.

so %nsmid may be larger than the physical number of SMs in the device.sreg . Note that %smid is volatile and returns the location of a thread at the moment when read.0.3. repeated launches of programs may occur.g. This variable provides the temporal grid launch number for this context. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. Supported on all target architectures. where each launch starts a grid-of-CTAs. mov. Introduced in PTX ISA version 1.sreg .u32 %nsmid. 2010 153 . The SM identifier numbering is not guaranteed to be contiguous. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. The SM identifier ranges from 0 to %nsmid-1. but its value may change during execution.0. Introduced in PTX ISA version 1. %nsmid.sreg . read-only special register initialized with the per-grid temporal grid identifier. The SM identifier numbering is not guaranteed to be contiguous. PTX ISA Notes Target ISA Notes Examples Table 121.u32 %r. due to rescheduling of threads following preemption. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. // initialized at grid launch A predefined. During execution. mov. A predefined.u32 %r.Chapter 9.u32 %gridid. mov. A predefined. %smid. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.u32 %smid. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. e. . %gridid. . Notes PTX ISA Notes Target ISA Notes Examples Table 120. PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 2.u32 %r. . read-only special register that returns the maximum number of SM identifiers. %nsmid requires sm_20 or later. Special Registers Table 119. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. Supported on all target architectures.

%lanemask_eq. A predefined. mov. %lanemask_lt. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. mov.PTX ISA Version 2.u32 %r. %lanemask_le requires sm_20 or later. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.sreg . A predefined.sreg . .u32 %r.0. Introduced in PTX ISA version 2. %lanemask_lt requires sm_20 or later. 2010 . 154 January 24. Table 124.0. %lanemask_le.u32 %lanemask_eq.0 Table 122.sreg . mov. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. . Introduced in PTX ISA version 2.u32 %lanemask_le. Introduced in PTX ISA version 2. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %r. . Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.0.u32 %lanemask_lt. Table 123. %lanemask_eq requires sm_20 or later. A predefined.

January 24. %lanemask_gt requires sm_20 or later.u32 %r. %lanemask_ge requires sm_20 or later.sreg .u32 %r. %lanemask_ge. Table 126. . A predefined.0.u32 %lanemask_gt.0.Chapter 9. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. Special Registers Table 125. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. .u32 %lanemask_ge. A predefined.sreg . 2010 155 . mov.

%clock64 requires sm_20 or later. . read-only 64-bit unsigned cycle counter. %pm3 %pm0.%clock64.sreg .%clock.u64 r1. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Table 128. Introduced in PTX ISA version 1. …. %pm1. Table 129. 156 January 24.u32 %clock.u32 r1.u64 %clock64. .sreg . 2010 . %pm1.u32 r1. %pm2. Special registers %pm0. Supported on all target architectures. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Supported on all target architectures. Introduced in PTX ISA version 1. Their behavior is currently undefined. read-only 32-bit unsigned cycle counter. Special Registers: %pm0. %pm2. Introduced in PTX ISA version 2.%pm0.sreg . Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm1.u32 %pm0. mov. mov. %pm3. The lower 32-bits of %clock64 are identical to %clock. %pm2.0.0 Table 127.3. mov.PTX ISA Version 2. .0.

minor are integers Specifies the PTX language version number.version major.version .version 1. Supported on all target architectures.version directive. . .version Syntax Description Semantics PTX version number.0. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version 2. PTX File Directives: .version .4 January 24. Duplicate .minor // major. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0 .version directives are allowed provided they match the original . Directives 10.version directive.Chapter 10. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.target Table 130. 2010 157 .1. and the target architecture for which the code was generated. Increments to the major number indicate incompatible changes to PTX. Each ptx file must begin with a . .

Description Specifies the set of features in the target architecture for which the current ptx code was generated. sm_10.target directive specifies a single target architecture.samplerref descriptors. Texturing mode introduced in PTX ISA version 1.texmode_independent texture and sampler information is bound together and accessed via a single .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. Adds {atom.red}. and an error is generated if an unsupported feature is used.shared.target Syntax Architecture and Platform target. generations of SM architectures follow an “onion layer” model.f64 instructions used.texref descriptor. Requires map_f64_to_f32 if any .0 Table 131. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.0. including expanded rounding modifiers. A . PTX code generated for a given target can be run on later generation devices.global. texmode_unified. Requires map_f64_to_f32 if any . Requires map_f64_to_f32 if any . 2010 . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.texmode_unified .f64 to .texmode_unified) . Adds {atom.red}.texref and . Disallows use of map_f64_to_f32.target directive containing a target architecture and optional platform options. sm_13. texture and sampler information is referenced with independent .f64 instructions used.target . PTX features are checked against the specified target architecture. where each generation adds new features and retains all features of previous generations.version directive. Adds double-precision support. Introduced in PTX ISA version 1.5. sm_12. immediately followed by a . but subsequent . In general. Supported on all target architectures. brkpt instructions.target directives can be used to change the set of target features allowed during parsing. The texturing mode is specified for an entire module and cannot be changed within the module. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Note that . The following table summarizes the features in PTX that vary according to target architecture. Texturing mode: (default is . Therefore.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. texmode_independent. vote instructions. with only half being used by instructions converted from .f64 storage remains as 64-bits.global. map_f64_to_f32 }. 158 January 24. A program with multiple . Each PTX file must begin with a .red}. 64-bit {atom.f32. . Target sm_20 Description Baseline feature set for sm_20 architecture.PTX ISA Version 2. PTX File Directives: . sm_11.f64 instructions used. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.

target sm_20. Directives Examples . texmode_independent January 24.target sm_10 // baseline target architecture . 2010 159 .Chapter 10.target sm_13 // supports double-precision .

[y].param.entry filter ( . Kernel and Function Directives: .b32 z ) Target ISA Notes Examples [x]. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1. In addition to normal parameters.reg .entry kernel-name ( param-list ) kernel-body . .5 and later. PTX ISA Notes For PTX ISA version 1.param .param { .param.4 and later. the kernel dimensions and properties are established and made available via special registers. At kernel launch.surfref variables may be passed as parameters. The shape and size of the CTA executing the kernel are available in special registers.texref. . … } . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.PTX ISA Version 2. store.entry Syntax Description Kernel entry point and body. Parameters are passed via .entry kernel-name kernel-body Defines a kernel entry point name. Supported on all target architectures.entry . . parameters. etc.param.0 10.3. and .b32 %r2. For PTX ISA versions 1. .g. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. e.samplerref.param instructions.b32 %r1. 160 January 24.b32 x. and body for the kernel function.func Table 132. parameter variables are declared in the kernel parameter list.b32 %r<99>. Parameters may be referenced by name within the kernel body and loaded into registers using ld.4.b32 %r3. ld. These parameters can only be referenced by name within texture and surface load.b32 y. 2010 .entry .param . ld. Semantics Specify the entry point for a kernel program. %ntid. opaque . .0 through 1.param space memory and are listed within an optional parenthesized parameter list.entry cta_fft .2. %nctaid. ld. [z].0 through 1. and query instructions and cannot be accessed via ld. with optional parameters.param instructions. . parameter variables are declared in the kernel body.

func (ret-param) fname (param-list) function-body Defines a function. PTX ISA 2. Release Notes For PTX ISA version 1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Parameters in register state space may be referenced directly within instructions in the function body. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.Chapter 10. 2010 161 . which may use a combination of registers and stack locations to pass parameters. if any. … Description // return value in fooval January 24. parameters must be in the register state space.param state space. foo.b32 localVar. Parameters in . … use N. Directives Table 133.result.reg .reg .x code.func fname (param-list) function-body . A . Kernel and Function Directives: .reg . dbl.reg .func fname function-body . and recursion is illegal.0 with target sm_20 supports at most one return value. Variadic functions are currently unimplemented.b32 rval) foo (.func . ret. there is no stack. The parameter lists define locally-scoped variables in the function body. Parameter passing is call-by-value. other code. Supported on all target architectures. .0 with target sm_20 allows parameters in the .func definition with no body provides a function prototype.func (.0.func Syntax Function definition. . Variadic functions are represented using ellipsis following the last fixed argument.param space are accessed using ld. mov. The implementation of parameter passing is left to the optimizing translator. val1). and supports recursion. implements an ABI with stack.2 for a description of variadic functions.f64 dbl) { . Parameters must be base types in either the register or parameter state space.b32 N. } … call (fooval).b32 rval. . PTX 2. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.param and st.param instructions in the body. (val0. including input and return parameters and optional function body.

This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).pragma directive is supported for passing information to the PTX backend.minnctapersm directives may be applied per-entry and must appear between an . A general . Performance-Tuning Directives To provide a mechanism for low-level performance tuning. .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. registers) to increase total thread count and provide a greater opportunity to hide memory latency. . The directive passes a list of strings to the backend. The directives take precedence over any module-level constraints passed to the optimizing backend.maxnctapersm (deprecated) . The . The interpretation of . These can be used. for example.0 10. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.maxntid and .maxntid . and . or as statements within a kernel or device function body.3. the . the .g.entry directive and its body. and the strings have no semantics within the PTX virtual machine model. Note that . and the .maxntid.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. Currently.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. to throttle the resource requirements (e. PTX supports the following directives.maxnreg. which pass information to the backend optimizing compiler.maxnreg .pragma directives may appear at module (file) scope.maxntid directive specifies the maximum number of threads in a thread block (CTA). 162 January 24.PTX ISA Version 2. at entry-scope.pragma The .minnctapersm . 2010 .

.3. The actual number of registers used may be less.maxnreg . for example.3.entry foo . . ny . Supported on all target architectures. Introduced in PTX ISA version 1. Performance-Tuning Directives: . .Chapter 10. 2D. nz Declare the maximum number of threads in the thread block (CTA). Directives Table 134. Introduced in PTX ISA version 1. Performance-Tuning Directives: .maxntid nx. the backend may be able to compile to fewer registers. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. Supported on all target architectures. .maxntid and . Exceeding any of these limits results in a runtime error or kernel launch failure. The compiler guarantees that this limit will not be exceeded.maxntid .maxntid nx .maxntid 16. or 3D CTA. The maximum number of threads is the product of the maximum extent in each dimension.maxntid nx.maxntid Syntax Maximum number of threads in thread block (CTA).entry foo .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxctapersm. or the maximum number of registers may be further constrained by .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxnreg n Declare the maximum number of registers per thread in a CTA.entry bar .16. ny. 2010 163 . This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid 256 .

maxntid 256 .0.0 as a replacement for .maxnctapersm (deprecated) . . The optimizing backend compiler uses . However. Deprecated in PTX ISA version 2.0 Table 136. Performance-Tuning Directives: .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxntid to be specified as well.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.3. additional CTAs may be mapped to a single multiprocessor.PTX ISA Version 2.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. Optimizations based on .entry foo . .0.minnctapersm in PTX ISA version 2. Performance-Tuning Directives: . Introduced in PTX ISA version 1.minnctapersm generally need . .maxnctapersm.minnctapersm . if the number of registers used by the backend is sufficiently lower than this bound.entry foo . Introduced in PTX ISA version 2.maxntid 256 .maxntid to be specified as well.maxntid and . Supported on all target architectures. Supported on all target architectures. . For this reason.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm 4 { … } 164 January 24.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxnctapersm generally need .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Optimizations based on . .maxnctapersm has been renamed to . 2010 .

The .pragma . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Pass module-scoped. or statement-level directives to the PTX backend compiler. at entry-scope.Chapter 10.pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas. .pragma Syntax Description Pass directives to PTX backend compiler.pragma list-of-strings .pragma directive strings is implementation-specific and has no impact on PTX semantics. or at statementlevel. Supported on all target architectures. 2010 165 . .entry foo . Directives Table 138.0. Introduced in PTX ISA version 2. { … } January 24. Performance-Tuning Directives: . The interpretation of .pragma directive may occur at module-scope. entry-scoped.pragma “nounroll”.

0x61395a5f.x code.byte byte-list // comma-separated hexadecimal byte values .2. 0x5f736f63 .264-1] . Introduced in PTX ISA version 1. Supported on all target architectures.section directive is new in PTX ISA verison 2. 0x6150736f.byte 0x00.section .debug_info . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .4. 0x02.0.4byte int32-list // comma-separated hexadecimal integers in range [0. 0x736d6172 .PTX ISA Version 2.. Table 139. 0x00 . Deprecated as of PTX 2.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. replaced by .0 but is supported for legacy PTX version 1. 0x00.loc The .byte 0x2b.4byte 0x6e69616d.quad int64-list // comma-separated hexadecimal integers in range [0. 0x00000364. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. “”.debug_pubnames.0 10. 0x63613031. 2010 . The @@DWARF syntax is deprecated as of PTX version 2.0 and replaces the @@DWARF syntax. 0x00 166 January 24.232-1] .section directive. 0x00.4byte label . @progbits .4byte ..4byte 0x000006b5.file . 0x00. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . @@DWARF dwarf-string dwarf-string may have one of the . 0x00. 0x00.section .

b8 byte-list // comma-separated list of integers in range [0. 0x00.0.section .section Syntax PTX section definition. .debug_pubnames { .b32 int32-list // comma-separated list of integers in range [0.. 0x5f736f63 0x6150736f. 0x736d6172 0x00 Table 141.section . 2010 167 .0.255] .b32 0x000006b5.b8 0x00. Supported on all target architectures.b32 .b32 label .file filename Table 142.loc . .file . Debugging Directives: ..debug_info .b8 0x2b. } 0x02.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Debugging Directives: . replaces @@DWARF syntax. Supported on all target architectures. Source file information. 0x63613031.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Source file location. . . Directives Table 140.264-1] . 0x00. . . Supported on all target architectures. 0x00000364.Chapter 10.b32 0x6e69616d.b64 int64-list // comma-separated list of integers in range [0. 0x00 0x61395a5f.0. 0x00.section section_name { dwarf-lines } dwarf-lines have the following formats: . . 0x00.232-1] . 0x00. Debugging Directives: ..loc line_number January 24. 0x00.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible .PTX ISA Version 2. .visible identifier Declares identifier to be externally visible.b32 foo.visible . Linking Directives . Introduced in PTX ISA version 1. Linking Directives: .extern identifier Declares identifier to be defined externally.extern .6.0 10.0. Supported on all target architectures. 2010 .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. // foo will be externally visible 168 January 24. .extern .global .visible Table 143. // foo is defined in another module Table 144.global .b32 foo.0.extern . Supported on all target architectures. . Introduced in PTX ISA version 1. . Linking Directives: .

The first section describes ISA and implementation changes in the current release of PTX ISA 2. Release Notes This section describes the history of change in the PTX ISA and implementation.4 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.3 PTX ISA 1.0 CUDA 2.1 CUDA 2.1 PTX ISA 1.2 PTX ISA 1.2 CUDA 2. CUDA Release CUDA 1.0 CUDA 1.5 PTX ISA 2.Chapter 11.1 CUDA 2.0.0 January 24.3 driver r190 CUDA 3. 2010 169 . The release history is as follows.0 driver r195 PTX ISA Version PTX ISA 1.0 PTX ISA 1.

0 for sm_20 targets. fma. The mad.ftz modifier may be used to enforce backward compatibility with sm_1x. The mad. Both fma.0 11. Single-precision add. The changes from PTX ISA 1.rp rounding modifiers for sm_20 targets.f32 requires sm_20. rcp.f32 require a rounding modifier for sm_20 targets.0 11. • • • • • 170 January 24.rn. These are indicated by the use of a rounding modifier and require sm_20.x code and sm_1x targets. while maximizing backward compatibility with legacy PTX 1.and double-precision div.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The fma. sub.rm and . Instructions testp and copysign have been added. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Floating-Point Extensions This section describes the floating-point changes in PTX 2.f32 instruction also supports . Single.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. New Features 11.1. The . Changes in Version 2. A single-precision fused multiply-add (fma) instruction has been added.1.1. and sqrt with IEEE 754 compliant rounding have been added.ftz and .f32 maps to fma. The goal is to achieve IEEE 754 compliance wherever possible.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 and mad. and mul now support .f32.f32 for sm_20 targets.PTX ISA Version 2.1.1. 2010 . mad.1. When code compiled for sm_1x is executed on sm_20 devices.sat modifiers.

add. .1. suld.Chapter 11. Instruction cvta for converting global.u32 and bar.b32. A system-level membar instruction.or}. st. Cache operations have been added to instructions ld.gt} have been added.1.g.minnctapersm to better match its behavior and usage.3. .1. popc.sys. local. membar. A “vote ballot” instruction.lt. A new directive.clamp and . for prefetching to specified level of memory hierarchy.f32 have been implemented. Surface instructions support additional . bar now supports optional thread count and register operands.1. atom. Other new features Instructions ld. clz. %clock64.clamp modifiers. has been added. ldu. has been added. bfe and bfi. %lanemask_{eq. January 24. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. has been added. A “bit reversal” instruction. prefetch. Instructions bar.zero. and red now support generic addressing. and sust.2.pred have been added. Release Notes 11. has been added. ldu.ge. and shared addresses to generic address and vice-versa has been added. Instructions {atom. 11. The bar instruction has been extended as follows: • • • A bar. st. has been added. e.ballot. New special registers %nsmid. A “population count” instruction. Video instructions (includes prmt) have been added.red.arrive instruction has been added.red}.shared have been extended to handle 64-bit data types for sm_20 targets.popc.section. A “find leading non-sign bit” instruction. has been added. The . vote. A “count leading zeros” instruction. New instructions A “load uniform” instruction. have been added. 2010 171 .red}. bfind.red.maxnctapersm directive was deprecated and replaced with .le. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.{and. cvta. Instruction sust now supports formatted surface stores. has been added. isspacep. Instructions prefetch and prefetchu have also been added. Bit field extract and insert instructions. brev. prefetchu. Instructions {atom.

Unimplemented Features Remaining The following table summarizes unimplemented instruction features. stack-based ABI is unimplemented. See individual instruction descriptions for details.target sm_1x.ftz for PTX ISA versions 1.1. Support for variadic functions and alloca are unimplemented. 11.u32. 2010 . . if .s32.max} are not implemented. the correct number is sixteen. or .{u32.f32 type is unimplemented.0 11.5 and later.4 or earlier. where . single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.{min.ftz (and cvt for .ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.4 and earlier.s32. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. has been fixed. To maintain compatibility with legacy PTX code.f32. 172 January 24. Formatted surface load is unimplemented.3.5. In PTX version 1.version is 1. Semantic Changes and Clarifications The errata in cvt.PTX ISA Version 2. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.p.p sust. Formatted surface store with .red}. cvt. Instruction bra.1.f32} atom. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. call suld.2. The underlying. {atom.

Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. Descriptions of .Appendix A. { … } // do not unroll any loop in this function . disables unrolling for all loops in the entry function body. entry-function. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma “nounroll”.pragma “nounroll”. and statement levels. Supported only for sm_20 targets. L1_end: … } // do not unroll this loop January 24.pragma strings defined by ptxas. . disables unrolling of0 the loop for which the current block is the loop header.0. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma Strings This section describes the . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.pragma. L1_body: … L1_continue: bra L1_head. … @p bra L1_end.entry foo (…) . including loops preceding the . 2010 173 . Ignored for sm_1x targets.func bar (…) { … L1_head: . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. Note that in order to have the desired effect at statement level. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. Table 145. The “nounroll” pragma is allowed at module.pragma “nounroll”. .

2010 .PTX ISA Version 2.0 174 January 24.

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