NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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.....1............................ 6.............................1.......2......... 49 ii January 24................ Abstracting the ABI ................. Arrays.. 6.....................................4.............5..... and Vectors ................................................. 33 Fundamental Types .......5...3..............................4................................. 33 Restricted Use of Sub-Word Sizes .............. State Spaces.......................... 42 Addresses as Operands ........ 34 Variables ................ 47 Chapter 7.......................... 41 6.3...................1.......................................................................... Operand Type Information ............ 38 Alignment .......2...........4...........................................................5............................. Operand Costs ..........................1...............................................................................................................1.....1.. 41 Destination Operands ............... 37 Vectors ............................... 5........ 25 Chapter 5............ 41 Source Operands.......6......... 49 7......PTX ISA Version 2............................................................ 5..................4................................................................................................................ 37 Array Declarations .......................... 6.. and Surface Types ..........................................................1................................ State Spaces .................... 5... Function declarations and definitions .........................................................................1...4...............4..................................3......................... 2010 ................................................................................. 5.. 5....................................2.................................................4........................ 44 Rounding Modifiers ......................................................... 5................ 39 Parameterized Variable Names .......4...........1.............. 29 Global State Space ........ 28 Constant State Space . 6................ 28 Special Register State Space ...... 29 Local State Space ... Types ... 32 Texture State Space (deprecated) ...................... 46 6..............6..............2........................................ 5......4.................. 39 5...........................................3................................................. 33 5......................... 5......................................................................................................................... 5.............4........................2........................ Summary of Constant Expression Evaluation Rules ................................... 5........ 44 Scalar Conversions .. 32 5.................................1.......................................................................................... 30 Shared State Space.. Type Conversion......................... 6..2........................1..1............................................................ 5........................................2............................................ 5.......7................................................4...........5.........................4................................................................ Sampler... 42 Arrays as Operands ........................................6........... 5................................................................... 43 Labels and Function Names as Operands ...................1...............0 4............................. 6..................................................................................................... and Variables ............................................................ 43 Vectors as Operands ............................................ 6..................................2............4......................... Chapter 6..........................................1..................... 6.................. 27 Register State Space ...... 27 5....... Types...................... 37 Variable Declarations ............1..... 5..... Texture................5.4......... 6................................................ 5....2........................................................................ 43 6...............8......................................... Instruction Operands........... 41 Using Addresses....1..............3.................. 5...................5................4..... 29 Parameter State Space ..........6......... 38 Initializers ..........

1...x ............................... 55 8.............1........................................ 8.........2...................7.................................... 8..........................1............. 10.....................7................................... 157 Specifying Kernel Entry Points and Functions .....2............................... 55 Predicated Execution .............. 8.......... 168 Chapter 11..................................................2...............................1...........................................................................................................................................2............................................................ 169 11...... Instructions ............................................ Special Registers ....... 7.............10........3...1............................. 60 8.......... 140 Miscellaneous Instructions......... 172 Unimplemented Features Remaining ...................7..............1.................................................................... PTX Version and Target Directives ............................... 62 Semantics ... Format and Semantics of Instruction Descriptions .........4................................2. Chapter 9............................................................... 52 Variadic functions .....1.... Divergence of Threads in Control Constructs ....................7................. 132 Video Instructions .... 8.3.....................4................... 104 Data Movement and Conversion Instructions ............. 8.........................3......................................................... 8... Instruction Set ...............................................2....0 .........................6.............. 11......... 56 Comparisons . 11..........................4..... 63 Floating-Point Instructions .........................5......1............... 162 Debugging Directives ...1............................................................ 108 Texture and Surface Instructions .............6..... 8..7............................................................................. 8...................................................... 160 Performance-Tuning Directives ...................1....3........................................... 172 January 24................................................................................................................ 7...3...................................................................................................5............3..... 100 Logic and Shift Instructions ......................................................... 149 Chapter 10.......... 10...........3... 62 Machine-Specific Semantics of 16-bit Code ..............................7..... 10.7....................................... Changes in Version 2......................................... Changes from PTX 1................ 58 8...........1........................... 147 8..........................................7....... 54 Chapter 8.............7....................... 62 8................................................... 8........... 57 Manipulating Predicates .......................................... 122 Control Flow Instructions .......................................... 10..............7................................................. 11.........9...................................... 8............................................4................................................................................................ 8......7........................................................ 8.............. 63 Integer Arithmetic Instructions ................................ 2010 iii .... 81 Comparison and Selection Instructions .. 166 Linking Directives ................... 170 New Features ........................ Directives ...........7.....8............1............... 8.......................................7.... 8.............................. 8.................. 53 Alloca .. Type Information for Instructions and Operands .....6................................ 59 Operand Size Exceeding Instruction-Type Size ..................................................................................... 129 Parallel Synchronization and Communication Instructions ............................................... Release Notes ..... 8................................................1................................................ 55 PTX Instructions .. 170 Semantic Changes and Clarifications ..6......... 157 10.........................

....pragma Strings..... 173 iv January 24. Descriptions of .............PTX ISA Version 2......... 2010 ...........0 Appendix A.........................

........................................................................................ Table 12...... Table 31... Table 7........................................ 71 January 24..... Table 32........................... 57 Floating-Point Comparison Operators .................List of Tables Table 1......................................................................................... 66 Integer Arithmetic Instructions: mul .................................................. Table 18........................................................cc . Table 29..... 58 Type Checking Rules ............................................................................................................................ Table 5........... Table 24.......... 2010 v ................................................................................................. Table 22..... Table 16..................... 57 Floating-Point Comparison Operators Accepting NaN .......... Table 17.. Table 19.. 65 Integer Arithmetic Instructions: sub....... 69 Integer Arithmetic Instructions: mad24 ..................... 68 Integer Arithmetic Instructions: mul24 .......... Table 15..................................................... 23 Constant Expression Evaluation Rules .......................................................................................................................................................................... 67 Integer Arithmetic Instructions: mad ........ 70 Integer Arithmetic Instructions: sad ........... Table 25.................................................................... Table 14...................................................................................................... 58 Floating-Point Comparison Operators Testing for NaN .... Table 13.......................................................................................................................... 59 Relaxed Type-checking Rules for Source Operands .............. Unsigned Integer...... 25 State Spaces ........ Table 9....... Table 23.............................................................. 47 Operators for Signed Integer............................ 33 Opaque Type Fields in Unified Texture Mode ........ 46 Cost Estimates for Accessing State-Spaces ..........cc .......................... PTX Directives ............................................... 65 Integer Arithmetic Instructions: addc ............ 18 Reserved Instruction Keywords .............................................. Table 28............... 20 Operator Precedence ........................ Table 3.................................................................................................... 64 Integer Arithmetic Instructions: add.................................... 46 Integer Rounding Modifiers ......................................................... and Bit-Size Types .................................................... Table 4.......... 64 Integer Arithmetic Instructions: sub ............ 35 Convert Instruction Precision and Format .......... 45 Floating-Point Rounding Modifiers .... Table 11..... 28 Fundamental Type Specifiers ........................................ Table 2........................................... 19 Predefined Identifiers ..... Table 21............................... 35 Opaque Type Fields in Independent Texture Mode .......................................... Table 8. 66 Integer Arithmetic Instructions: subc ............ 27 Properties of State Spaces ......... 61 Integer Arithmetic Instructions: add .......................................................... Table 10......................... Table 30..................................... Table 26.. Table 20.................. 60 Relaxed Type-checking Rules for Destination Operands.......................................... Table 27................................................................................. Table 6........................................

......... 71 Integer Arithmetic Instructions: abs .................................................................................. Table 48.. Table 57........................... Table 35...................................................................................................................... 73 Integer Arithmetic Instructions: max ................................ Table 34............. 82 Floating-Point Instructions: testp ..... 92 Floating-Point Instructions: max ................................................................................................ Integer Arithmetic Instructions: div ............. 73 Integer Arithmetic Instructions: popc ..... 103 Comparison and Selection Instructions: slct ............................ Table 66...................................................... Table 51.............................................................................................. Table 43.................. Table 63................... Table 69........................................................................................................................................................................PTX ISA Version 2................................................................................................................. 87 Floating-Point Instructions: mad ........................................... 91 Floating-Point Instructions: neg ..................... 76 Integer Arithmetic Instructions: bfe .......................................................................................... 88 Floating-Point Instructions: div .......................................................................... 97 Floating-Point Instructions: lg2 .................... Table 64......... 101 Comparison and Selection Instructions: setp .............................................................................................................................................. Table 52...... 94 Floating-Point Instructions: rsqrt ......................................0 Table 33.................... 92 Floating-Point Instructions: rcp ..................................................................................... 90 Floating-Point Instructions: abs .............................. 74 Integer Arithmetic Instructions: bfind ..................................... 102 Comparison and Selection Instructions: selp ............................ 71 Integer Arithmetic Instructions: rem ............................... 93 Floating-Point Instructions: sqrt .................. Table 49..... Table 41.............................. Table 46.............................................................................................................. 96 Floating-Point Instructions: cos ............................................ 72 Integer Arithmetic Instructions: min ................................................... Table 44............................................................................. Table 62................ 86 Floating-Point Instructions: fma .......... 103 vi January 24... 91 Floating-Point Instructions: min ..................................... 78 Integer Arithmetic Instructions: prmt ................... Table 67.................... Table 58............... Table 50........ Table 60.... Table 47................................. 75 Integer Arithmetic Instructions: brev ...................... Table 56............. 84 Floating-Point Instructions: sub ................................................. Table 55.. Table 59................................................................. 83 Floating-Point Instructions: add .................................................. Table 37..... 72 Integer Arithmetic Instructions: neg .............................................................................................................................. Table 40.............................. 2010 ................... 85 Floating-Point Instructions: mul ........................... 79 Summary of Floating-Point Instructions ..... 77 Integer Arithmetic Instructions: bfi ................................... Table 38.. Table 68.............. 83 Floating-Point Instructions: copysign ........ Table 45.......... Table 61............... 98 Floating-Point Instructions: ex2 ................... 95 Floating-Point Instructions: sin ..... Table 53............................. 99 Comparison and Selection Instructions: set . 74 Integer Arithmetic Instructions: clz ...................................................................................................... Table 54.. Table 39................................ Table 65............... Table 36...................... Table 42..................

. Table 85......... 106 Logic and Shift Instructions: not ... Table 75........................ 133 Parallel Synchronization and Communication Instructions: membar ...................... 142 Video Instructions: vshl............................................................................ 129 Control Flow Instructions: @ ............................................... 129 Control Flow Instructions: bra ........................................................ vsub. 106 Logic and Shift Instructions: shl .............. Table 76.................. Table 91..................................... Table 106.... 124 Texture and Surface Instructions: suld .................................................................................. 131 Control Flow Instructions: exit .... Table 73....... Table 104....... vabsdiff...... Table 99.......................... 107 Logic and Shift Instructions: shr .. 115 Data Movement and Conversion Instructions: st .............. 137 Parallel Synchronization and Communication Instructions: vote . Table 105............. Logic and Shift Instructions: and ... vmax ............. 131 Parallel Synchronization and Communication Instructions: bar .............................................................................................. vshr ............................. Table 77........................ Table 98.................... 135 Parallel Synchronization and Communication Instructions: red .... Table 102......................... 130 Control Flow Instructions: ret ................................................................................... Table 89....................................... 143 January 24........ Table 92................................................................. Table 72. 105 Logic and Shift Instructions: or ..................... Table 88.................................................... 118 Data Movement and Conversion Instructions: isspacep .................................... Table 83................................. 113 Data Movement and Conversion Instructions: ldu ............................ Table 93............................ Table 96............. Table 80........................................... 123 Texture and Surface Instructions: txq ............ 105 Logic and Shift Instructions: xor .... Table 103................................... 112 Data Movement and Conversion Instructions: ld ........... prefetchu ..... 127 Texture and Surface Instructions: suq .................. 120 Texture and Surface Instructions: tex ......... Table 74............. 107 Cache Operators for Memory Load Instructions ....................................................................... Table 78................................. Table 81.................. Table 95......................... Table 100................................................ 106 Logic and Shift Instructions: cnot ........ Table 86............. 119 Data Movement and Conversion Instructions: cvta ................................. Table 82..................................... Table 101....... 116 Data Movement and Conversion Instructions: prefetch..........................Table 70............... 126 Texture and Surface Instructions: sured................................. Table 84....................... 109 Cache Operators for Memory Store Instructions ......................... 2010 vii .................................................... Table 90........................................................................... Table 87...... 128 Control Flow Instructions: { } .............. Table 79.. 111 Data Movement and Conversion Instructions: mov ........................................................................................... vmin....................... 125 Texture and Surface Instructions: sust ........... 130 Control Flow Instructions: call ............................................. Table 71........... 139 Video Instructions: vadd.................................... 110 Data Movement and Conversion Instructions: mov ..................................................... 134 Parallel Synchronization and Communication Instructions: atom ............... Table 97.............................................. 119 Data Movement and Conversion Instructions: cvt .................................................................................. Table 94.........

................................ Table 133............................................. 147 Miscellaneous Instructions: pmevent............................ 161 Performance-Tuning Directives: ................... Table 109.....version............... Table 117...extern...... Video Instructions: vmad .............................................. Table 128..................................... 158 Kernel and Function Directives: . 155 Special Registers: %clock .............minnctapersm ...................................................................entry..................................................... Table 116.............................................................................................pragma ...................... 153 Special Registers: %nsmid ... 151 Special Registers: %ctaid .............................. Table 124.................................................................................................................................... 165 Debugging Directives: @@DWARF ........ 153 Special Registers: %gridid ........... Table 120........0 Table 107....... 164 Performance-Tuning Directives: ...................... 156 Special Registers: %clock64 ................................................................. Table 113... 168 viii January 24......................... %pm3 .........maxnreg .. 167 Debugging Directives: ........... Table 135.. 153 Special Registers: %lanemask_eq ........ %pm2........ 164 Performance-Tuning Directives: ......... %pm1....................................................................................... Table 129... 163 Performance-Tuning Directives: ...........................................................................PTX ISA Version 2........... 163 Performance-Tuning Directives: ............... 155 Special Registers: %lanemask_gt ............................................................................................ Table 134......................................................... Table 111.............................. 147 Miscellaneous Instructions: brkpt ......................................... Table 141....... Table 108..............................................loc ........maxntid ....................................................... 144 Video Instructions: vset................................................................................ 156 PTX File Directives: ...... 147 Special Registers: %tid ............................. 146 Miscellaneous Instructions: trap ............. 152 Special Registers: %smid ...............section .................... Table 119...................... Table 127................................................... 154 Special Registers: %lanemask_ge .......................................................... Table 131................................................................. 156 Special Registers: %pm0................................. Table 112.............................................. 152 Special Registers: %nctaid ... Table 137............................................... Table 136... Table 139................................................................................................ Table 118................ 154 Special Registers: %lanemask_lt ............................ 2010 ............................ Table 110................. 167 Debugging Directives: ...... 157 PTX File Directives: .... Table 121..... Table 114............. 151 Special Registers: %nwarpid ............................. 151 Special Registers: %warpid ............. Table 143.................................. 166 Debugging Directives: .......... Table 142............... Table 130.................................func ..maxnctapersm (deprecated) .......................................................................................... Table 140.............. 150 Special Registers: %ntid . 154 Special Registers: %lanemask_le .................................................target ......................................... Table 122.....................................................................................................................................................file ................................. 167 Linking Directives: ...... Table 123............................................................... Table 138..... 150 Special Registers: %laneid .................................. 160 Kernel and Function Directives: . Table 115...... Table 126............ Table 132......... Table 125............

...visible............ 168 Pragma Strings: “nounroll” .......................................... 2010 ix ..........................................Table 144...... Linking Directives: ............................................ Table 145................ 173 January 24......

0 x January 24. 2010 .PTX ISA Version 2.

In fact.2. January 24. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time.Chapter 1. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. the memory access latency can be hidden with calculations instead of big data caches. PTX defines a virtual machine and ISA for general purpose parallel thread execution. many-core processor with tremendous computational horsepower and very high memory bandwidth. and because it is executed on many data elements and has high arithmetic intensity. the programmable GPU has evolved into a highly parallel. image and media processing applications such as post-processing of rendered images. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. 2010 1 . In 3D rendering large sets of pixels and vertices are mapped to parallel threads. 1. high-definition 3D graphics. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing.1. Introduction This document describes PTX. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Data-parallel processing maps data elements to parallel processing threads. stereo vision. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. video encoding and decoding. PTX exposes the GPU as a data-parallel computing device. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. there is a lower requirement for sophisticated flow control. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Similarly. and pattern recognition can map image blocks and pixels to parallel processing threads. image scaling. 1. which are optimized for and translated to native target-architecture instructions. Because the same program is executed for each data element. multithreaded. from general signal processing or physics simulation to computational finance or computational biology. PTX programs are translated at install time to the target hardware instruction set.

ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. including integer. memory. Instructions marked with . When code compiled for sm_1x is executed on sm_20 devices.f32 maps to fma. Provide a code distribution ISA for application and middleware developers. and mul now support .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 is a superset of PTX 1.rn.0 are improved support for IEEE 754 floating-point operations.ftz) modifier may be used to enforce backward compatibility with sm_1x.0 PTX ISA Version 2.rm and .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. The fma. atomic. • • • 2 January 24.PTX ISA Version 2.f32 require a rounding modifier for sm_20 targets. The main areas of change in PTX 2. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. A single-precision fused multiply-add (fma) instruction has been added.x code will continue to run on sm_1x targets as well. sub. Most of the new features require a sm_20 target. Provide a common source-level ISA for optimizing code generators and translators. 2010 .3.0 is in improved support for the IEEE 754 floating-point standard. Facilitate hand-coding of libraries. 1.1. and video instructions.ftz and . PTX 2.x features are supported on the new sm_20 target.f32 requires sm_20. reduction. Both fma. A “flush-to-zero” (. barrier. PTX ISA Version 2.f32 for sm_20 targets. Achieve performance in compiled applications comparable to native GPU performance. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.sat modifiers. Improved Floating-Point Support A main area of change in PTX 2. 1. The mad.f32. surface. and the introduction of many new instructions. fma. Legacy PTX 1.3. Provide a machine-independent ISA for C/C++ and other compilers to target. The changes from PTX ISA 1. which map PTX to specific target machines. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. addition of generic addressing to facilitate the use of general-purpose pointers.x.f32 instruction also supports . and all PTX 1. mad. Single-precision add.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture.f32 and mad. and architecture tests.rp rounding modifiers for sm_20 targets. performance kernels. The mad.

NOTE: The current version of PTX does not implement the underlying.g.zero. and directives are introduced in PTX 2. January 24. rcp. 2010 3 . See Section 7 for details of the function definition and call syntax needed to abstract the ABI.clamp and . Instructions testp and copysign have been added. and shared addresses to generic addresses.and double-precision div. cvta. atom.3.e.0 closer to full compliance with the IEEE 754 standard.3. and Application Binary Interface (ABI). and sqrt with IEEE 754 compliant rounding have been added. suld. Support for an Application Binary Interface Rather than expose details of a particular calling convention. local. . local. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. isspacep. New Instructions The following new instructions. instructions ld. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. and vice versa.Chapter 1. local. Introduction • Single.0. Instruction cvta for converting global. prefetch. prefetchu. 1. and shared addresses to generic address and vice-versa has been added. Surface Instructions • • Instruction sust now supports formatted surface stores.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. stack-based ABI. 1. an address that is the same across all threads in a warp. and sust. i. allowing memory instructions to access these spaces without needing to specify the state space. and red now support generic addressing.3. A new cvta instruction has been added to convert global..4. • Taken as a whole.0.2. e. In PTX 2. and shared state spaces. for prefetching to specified level of memory hierarchy. stack layout. Generic addressing unifies the global. these changes bring PTX 2. Instructions prefetch and prefetchu have been added. 1. Cache operations have been added to instructions ld. Generic Addressing Another major change is the addition of generic addressing. These are indicated by the use of a rounding modifier and require sm_20. st. st.3. ldu. special registers. so recursion is not yet supported. PTX 2. Surface instructions support additional clamp modifiers.

%clock64.red.ballot. bar now supports an optional thread count and register operands. has been added.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. vote. Other Extensions • • • Video instructions (includes prmt) have been added.section. 2010 . A “vote ballot” instruction.red}.add. %lanemask_{eq. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Instructions {atom.sys.u32 and bar.ge. New special registers %nsmid. Barrier Instructions • • A system-level membar instruction.lt.pred have been added.b32. Instructions bar. and Vote Instructions • • • New atomic and reduction instructions {atom.red.f32 have been added.popc. . A new directive.PTX ISA Version 2.{and.red}. 4 January 24. has been added.gt} have been added.arrive instruction has been added. membar.or}.le. Reduction. A bar. bfi bit field extract and insert popc clz Atomic.shared have been extended to handle 64-bit data types for sm_20 targets.

Chapter 7 describes the function and call syntax.0. Chapter 11 provides release notes for PTX Version 2. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 3 gives an overview of the PTX virtual machine model. 2010 5 . Chapter 4 describes the basic syntax of the PTX language.4. Chapter 9 lists special registers. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. calling convention. Chapter 8 describes the instruction set. Introduction 1. and variable declarations. Chapter 5 describes state spaces. Chapter 10 lists the assembly directives supported in PTX. Chapter 6 describes instruction operands. types.Chapter 1. January 24.

2010 .0 6 January 24.PTX ISA Version 2.

z). and tid. Programming Model 2. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.x. Threads within a CTA can communicate with each other. or host: In other words. 2. and results across the threads of the CTA.x. 2D. To that effect. (with elements tid. compute-intensive portions of applications running on the host are off-loaded onto the device. A cooperative thread array. 2010 7 .y. work. but independently on different data. or 3D CTA. tid.1. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. More precisely. or CTA.y. Each CTA thread uses its thread identifier to determine its assigned role. 2. To coordinate the communication of the threads within the CTA. 2D. Programs use a data parallel decomposition to partition inputs.z) that specifies the thread’s position within a 1D. or 3D shape specified by a three-element vector ntid (with elements ntid.2. It operates as a coprocessor to the main CPU. one can specify synchronization points where threads wait until all threads in the CTA have arrived. is an array of threads that execute a kernel concurrently or in parallel. compute addresses. Cooperative thread arrays (CTAs) implement CUDA thread blocks. Each thread has a unique thread identifier within the CTA. Each CTA has a 1D. and ntid.Chapter 2.2. The thread identifier is a three-element vector tid. assign specific input and output positions. can be isolated into a kernel function that is executed on the GPU as many different threads. data-parallel. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. The vector ntid specifies the number of threads in each CTA dimension. a portion of an application that is executed many times. and select work to perform. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. January 24.1. ntid. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.

PTX ISA Version 2. such that the threads execute the same instructions at the same time. Each grid of CTAs has a 1D. %nctaid. or 3D shape specified by the parameter nctaid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. Some applications may be able to maximize performance with knowledge of the warp size. Multiple CTAs may execute concurrently and in parallel. Each grid also has a unique temporal grid identifier (gridid). so PTX includes a run-time immediate constant. and %gridid. multiple-thread) fashion in groups called warps. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. read-only special registers %tid.2. %ntid. Typically.2. However.0 Threads within a CTA execute in SIMT (single-instruction. %ctaid. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). CTAs that execute the same kernel can be batched together into a grid of CTAs. depending on the platform. 2. or sequentially. Threads within a warp are sequentially numbered. WARP_SZ. The host issues a succession of kernel invocations to the device. a warp has 32 threads. because threads in different CTAs cannot communicate and synchronize with each other. so that the total number of threads that can be launched in a single kernel invocation is very large. 2D . A warp is a maximal subset of threads from a single CTA. This comes at the expense of reduced thread communication and synchronization. 2010 . Threads may read and use these values through predefined. which may be used in any instruction where an immediate operand is allowed. The warp size is a machine-dependent constant. 8 January 24.

A grid is a set of CTAs that execute independently. 2) Thread (4. Figure 1. 1) Thread (1. 0) Thread (3. Thread Batching January 24. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (4. 1) CTA (2. 1) Thread (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2010 9 . 2) Thread (2. 0) Thread (2. 0) CTA (0. 2) Thread (1. 0) CTA (1. 1) CTA (1. 0) CTA (2. 1) Thread (4. 0) Thread (1.Chapter 2. 0) Thread (0. 1) Thread (3. 2) Thread (3. 1) Thread (0. 1) Thread (0.

referred to as host memory and device memory. Texture memory also offers different addressing modes. for some specific data formats. The device memory may be mapped and read or written by the host. constant. for more efficient transfer. 2010 . Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. constant. as well as data filtering. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global.0 2. and texture memory spaces are optimized for different memory usages. Each thread has a private local memory. Both the host and the device maintain their own local memory. Finally.PTX ISA Version 2. and texture memory spaces are persistent across kernel launches by the same application. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. or. respectively.3. The global. 10 January 24. all threads have access to the same global memory. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.

0) Block (2. 1) Grid 1 Global memory Block (0. Memory Hierarchy January 24. 0) Block (0. 2) Block (1. 0) Block (1. 1) Block (0. 2) Figure 2. 2010 11 .Chapter 2. 0) Block (1. 1) Block (2. 0) Block (0. 1) Block (1. 1) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0.

2010 .PTX ISA Version 2.0 12 January 24.

The way a block is split into warps is always the same. 2010 13 . The threads of a thread block execute concurrently on one multiprocessor. The multiprocessor SIMT unit creates. and each scalar thread executes independently with its own instruction address and register state. The multiprocessor creates. and executes concurrent threads in hardware with zero scheduling overhead. the multiprocessor employs a new architecture we call SIMT (single-instruction. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. and on-chip shared memory. the threads converge back to the same execution path. new blocks are launched on the vacated multiprocessors. As thread blocks terminate. (This term originates from weaving. multiple-thread). January 24. for example. Parallel Thread Execution Machine Model 3. it splits them into warps that get scheduled by the SIMT unit. a cell in a grid-based computation). A warp executes one common instruction at a time. the first parallel thread technology. Branch divergence occurs only within a warp. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs).1. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. each warp contains threads of consecutive. and when all paths complete. It implements a single-instruction barrier synchronization. At every instruction issue time. When a multiprocessor is given one or more thread blocks to execute. When a host program invokes a kernel grid. A multiprocessor consists of multiple Scalar Processor (SP) cores. and executes threads in groups of parallel threads called warps. the warp serially executes each branch path taken. increasing thread IDs with the first warp containing thread 0. so full efficiency is realized when all threads of a warp agree on their execution path. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. If threads of a warp diverge via a data-dependent conditional branch. manages. The multiprocessor maps each thread to one scalar processor core. manages. different warps execute independently regardless of whether they are executing common or disjointed code paths. a voxel in a volume.Chapter 3.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. schedules. a multithreaded instruction unit. allowing. To manage hundreds of threads running several different programs. disabling threads that are not on that path.

If there are not enough registers or shared memory available per multiprocessor to process at least one block. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. modifies. however. and writes to the same location in global memory for more than one of the threads of the warp. on the other hand. each read. which is a read-only region of device memory. In contrast with SIMD vector machines. but one of the writes is guaranteed to succeed. which is a read-only region of device memory. Vector architectures. require the software to coalesce loads into vectors and manage divergence manually. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. but the order in which they occur is undefined. write to that location occurs and they are all serialized. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. 2010 . modify.PTX ISA Version 2. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. A key difference is that SIMD vector organizations expose the SIMD width to the software. If an atomic instruction executed by a warp reads. whereas SIMT instructions specify the execution and branching behavior of a single thread. For the purposes of correctness. SIMT enables programmers to write thread-level parallel code for independent. • The local and global memory spaces are read-write regions of device memory and are not cached. the number of serialized writes that occur to that location and the order in which they occur is undefined. A multiprocessor can execute as many as eight thread blocks concurrently. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. In practice. 14 January 24. the kernel will fail to launch. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. As illustrated by Figure 3. scalar threads. the programmer can essentially ignore the SIMT behavior. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor.0 SIMT architecture is akin to SIMD (Single Instruction. as well as data-parallel code for coordinated threads.

Figure 3. Hardware Model January 24. 2010 15 .Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

2010 .PTX ISA Version 2.0 16 January 24.

See Section 9 for a more information on these directives. All whitespace characters are equivalent. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 4.version directive specifying the PTX language version. January 24. Lines are separated by the newline character (‘\n’). #ifdef. Comments in PTX are treated as whitespace. Syntax PTX programs are a collection of text source files. 2010 17 . whitespace is ignored except for its use in separating tokens in the language. Source Format Source files are ASCII text. Each PTX file must begin with a . PTX is case sensitive and uses lowercase for keywords.2. Pseudo-operations specify symbol and addressing management. #endif. and using // to begin a comment that extends to the end of the current line.1. using non-nested /* and */ for comments that may span multiple lines. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands.Chapter 4. 4. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #define. #if.target directive specifying the target architecture assumed. The C preprocessor cpp may be used to process PTX source files. Lines beginning with # are preprocessor directives. followed by a . #else. #line. The following are common preprocessor directives: #include. Comments Comments in PTX follow C/C++ syntax.

The destination operand is first. The guard predicate may be optionally negated. 2. r2.loc . %tid.pragma .global. shl. r2.visible 4.sreg . followed by source operands.target .f32 r2.section .b32 add.version .PTX ISA Version 2. mov. so no conflict is possible with user-defined identifiers. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.func . Examples: . Instruction keywords are listed in Table 2.b32 r1.const . Table 1. .global .minnctapersm .maxnctapersm . and terminated with a semicolon. Instructions have an optional guard predicate which controls conditional execution.align .extern .1. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. Operands may be register variables. where p is a predicate register.maxntid . r2.shared .0 4.3. address expressions.reg . Statements begin with an optional label and end with a semicolon. array[r1]. or label names.3.b32 r1. Directive Statements Directive keywords begin with a dot. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.maxnreg .reg . ld.param . 2010 . All instruction keywords are reserved tokens in PTX. and is written as @p. 0.entry .local .b32 r1.3.2.5.global start: . r1. written as @!p. .file PTX Directives .x. Statements A PTX statement is either a directive or an instruction.tex .f32 array[N]. The guard predicate follows the optional label and precedes the opcode. 18 January 24. constant expressions.

Syntax Table 2.Chapter 4. 2010 19 . abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

listed in Table 3.4. underscore. e. Table 3. between user-defined variable names and compiler-generated names. Many high-level languages such as C and C++ follow similar rules for identifier names. dollar. or percentage character followed by one or more letters. underscore. except that the percentage sign is not allowed.0 4. The percentage sign can be used to avoid name conflicts. or dollar characters. PTX allows the percentage sign as the first character of an identifier. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. digits.PTX ISA Version 2. PTX predefines one constant and a small number of special registers that begin with the percentage sign. …. 2010 . %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or they start with an underscore.g. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. digits. %pm3 WARP_SZ 20 January 24.

e. Syntax 4. integer constants are allowed and are interpreted as in C.s64 or the unsigned suffix is specified. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. i. The syntax follows that of C. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. 2010 21 . every integer constant has type . The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned.e. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Floating-point literals may be written with an optional decimal point and an optional signed exponent.5.s64) unless the value cannot be fully represented in . Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. i. or binary notation. in which case the literal is unsigned (..u64.u64). For predicate-type data and instructions. there is no suffix letter to specify size. the constant begins with 0d or 0D followed by 16 hex digits. floating-point. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.5.5. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value.. To specify IEEE 754 doubleprecision floating point values. To specify IEEE 754 single-precision floating point values. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. and bit-size types. the sm_1x and sm_20 targets have a WARP_SZ value of 32. 4. Unlike C and C++. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. the constant begins with 0f or 0F followed by 8 hex digits. hexadecimal. Type checking rules remain the same for integer.Chapter 4. These constants may be used in data initialization and as operands to instructions. zero values are FALSE and non-zero values are TRUE. octal. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. each integer constant is converted to the appropriate size based on the data or instruction type at its use. 0[fF]{hexdigit}{8} // single-precision floating point January 24.s64 or . literals are always represented in 64-bit double-precision format. Constants PTX supports integer and floating-point constants and constant expressions. where the behavior of the operation depends on the operand types.2.1. 4. Integer literals may be written in decimal. When used in an instruction or data initialization.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

u64) (.Chapter 4.f64 use usual conversions . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 .5.f64 integer integer integer integer integer int ?.f64 : . 2010 25 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 integer . .u64 zero or non-zero same as sources use usual conversions Result Type same as source .u64.f64 use usual conversions . or .u64 .f64 integer .s64 .u64 .s64 .u64 .s64 .s64 .f64 same as source .f64 use usual conversions .u64 .s64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .s64 .s64) + .s64.f64 converted type .6.f64 converted type constant literal + ! ~ Cast Binary (.u64 same as 1st operand .u64 1st unchanged. Syntax 4.u64 .s64 . 2nd is . Table 5.s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .

2010 .0 26 January 24.PTX ISA Version 2.

and properties of state spaces are shown in Table 5. read-only memory. Kernel parameters.1. access rights. Types. private to each thread. 2010 27 . pre-defined. Table 6. and these resources are abstracted in PTX through state spaces and data types.param .global . defined per-thread. addressability.reg . The characteristics of a state space include its size.shared .tex January 24. 5.local . access speed. Global memory. Shared. platform-specific. .const .sreg . Special registers. Addressable memory shared between threads in 1 CTA. shared by all threads. Global texture memory (deprecated). All variables reside in some state space. Name State Spaces Description Registers.Chapter 5. the kinds of resources will be common across platforms. and level of sharing between threads. State Spaces. and Variables While the specific resources available in a given target GPU will vary. Local memory. Read-only. State Spaces A state space is a storage area with particular characteristics. or Function or local parameters. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. The list of state spaces is shown in Table 4. fast. defined per-grid.

sreg) state space holds predefined.param (used in functions) . floating point.PTX ISA Version 2.param instructions.0 Table 7.sreg . unsigned integer. aside from predicate registers which are 1-bit. st. register variables will be spilled to memory. and performance monitoring registers. 28 January 24. causing changes in performance.reg state space) are fast storage locations. platform-specific registers. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.tex Restricted Yes No3 5. The number of registers is limited. scalar registers have a width of 8-. Registers may have alignment boundaries required by multi-word loads and stores.. Special Register State Space The special register (. it is not possible to refer to the address of a register. 3 Accessible only via the tex instruction. CTA. predicate) or untyped.param (as input to kernel) . The most common use of 8-bit registers is with ld. such as grid. and vector registers have a width of 16-. All special registers are predefined.shared .local . 2 Accessible via ld. 64-.local state space. and will vary from platform to platform.param instruction. Registers differ from the other state spaces in that they are not fully addressable. 2010 . and cvt instructions. Device function input parameters may have their address taken via mov. Address may be taken via mov instruction.reg . or 128-bits.1. 5. Register size is restricted.2. 1 Accessible only via the ld. When the limit is exceeded. i. clock counters. or 64-bits. Registers may be typed (signed integer. 16-. For each architecture.1.param and st. 32-. 32-. the parameter is then located on the stack frame and its address is in the . Register State Space Registers (.e.const .global . there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). and thread parameters.1. or as elements of vector tuples. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .

where the size is not known at compile time.1. It is typically standard memory with cache. For example. The remaining banks may be used to implement “incomplete” constant arrays (in C. The constant memory is organized into fixed size banks.local) is private memory for each thread to keep its own data.const[2] . there are eleven 64KB banks. bank zero is used.b32 const_buffer[].1. // load second word 5.const[bank] modifier. By convention. results in const_buffer pointing to the start of constant bank two. the stack is in local memory.global. all addresses are in global memory are shared.5. 2010 29 . For the current devices. Constant State Space The constant (. Sequential consistency is provided by the bar. All memory writes prior to the bar. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. Threads must be able to do their work without waiting for other threads to do theirs. It is the mechanism by which different CTAs and different grids can communicate. Threads wait at the barrier until all threads in the CTA have arrived. For any thread in a context. To access data in contant banks 1 through 10.extern . as it must be allocated on a perthread basis. The size is limited. st. This reiterates the kind of parallelism available in machines that run PTX. as in lock-free and wait-free style programming. Use ld. whereas local memory variables declared January 24.global) state space is memory that is accessible by all threads in a context. If another thread sees the variable b change.local and st. Multiple incomplete array variables declared in the same bank become aliases. an incomplete array in bank 2 is accessed as follows: . where bank ranges from 0 to 10. ld. Use ld. for example).global. the declaration . b = b – 1.b32 %r1. This pointer can then be used to access the entire 64KB constant bank.3.const[2]. Banks are specified using the . the store operation updating a may still be in flight. initialized by the host. In implementations that support a stack.b32 const_buffer[]. 5. If no bank number is given.sync instruction are guaranteed to be visible to any reads after the barrier instruction.4.const[2] . Local State Space The local state space (. [const_buffer+4]. Global memory is not sequentially consistent.global to access global variables.local to access local variables. and Variables 5. each pointing to the start address of the specified constant bank. State Spaces.const) state space is a read-only memory. Module-scoped local memory variables are stored at fixed addresses. the bank number must be provided in the state space of the load instruction.Chapter 5. bank zero is used for all statically-sized constant variables. Global State Space The global (.1.sync instruction.extern . Consider the case where one thread executes the following two assignments: a = a + 1. and atom. Types. For example.

No access protection is provided between parameter and global space in this case.param .f64 %d. device function parameters were previously restricted to the register state space. [N]. per-kernel versus per-thread). Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.reg . The address of a kernel parameter may be moved into a register using the mov instruction.u32 %n.u32 %ptr.param space. read-only variables declared in the .u32 %n.param state space and is accessed using ld.u32 %n.1.entry bar ( .PTX ISA Version 2. For example.reg .entry foo ( . (2a) to declare formal input and return parameters for device functions called from within kernel execution.param state space. ld.param) state space is used (1) to pass input arguments from the host to the kernel.b32 N.1.b8 buffer[64] ) { .0 and requires target architecture sm_20. typically for passing large structures by value to a function. .x supports only kernel function parameters in . Note: The location of parameter space is implementation specific. … 30 January 24.param instructions. These parameters are addressable. 5.u32 %ptr.align 8 . ld. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. The use of parameter state space for device function parameters is new to PTX ISA version 2.reg . .1.param instructions. … Example: . Example: . mov.6.param.param. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param . The kernel parameter variables are shared across all CTAs within a grid. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). len.b32 len ) { . Note that PTX ISA versions 1. in some implementations kernel parameters reside in global memory. The resulting address is in the .0 within a function or kernel body are allocated on the stack. Parameter State Space The parameter (. Values passed from the host to the kernel are accessed through these parameter variables using ld. [buffer]. [%ptr]. %n. 5.param space variables.param . Similarly. Therefore. 2010 . all local memory variables are stored at fixed addresses and recursive function calls are not supported.6. ld.f64 %d.param. In implementations that do not support a stack. PTX code should make no assumptions about the relative locations or ordering of .

. such as C structures larger than 8 bytes.param. Function input parameters may be read via ld. x. int y. .param. and so the address will be in the . a byte array in parameter space is used. it is illegal to write to an input parameter or read from a return parameter. Aside from passing structures by value. ld.s32 %y.f64 %d.1. (4. Note that the parameter will be copied to the stack if necessary.func foo ( . The most common use is for passing objects by value that do not fit within a PTX register.local state space and is accessed via ld.param and function return parameters may be written using st. 2010 31 . } mystruct.b8 mystruct. st. … } // code snippet from the caller // struct { double d.local instructions. January 24.param formal parameter having the same size and alignment as the passed argument.local and st. call foo.2. State Spaces.param . }.s32 [mystruct+8].param space is also required whenever a formal parameter has its address taken within the called function.param.s32 x.reg .reg . In this case.f64 %d.param .param space variable. .align 8 . . Types. . [buffer]. .reg . Typically.0 extends the use of parameter space to device function parameters. is flattened. ld.s32 %y.b8 buffer[12] ) { . Example: // pass object of type struct { double d.reg . … See the section on function call syntax for more details. the caller will declare a locally-scoped . passed to foo … .f64 [mystruct+0]. dbl. Device Function Parameters PTX ISA version 2.b32 N.reg .param. It is not possible to use mov to get the address of a return parameter or a locally-scoped .align 8 . and Variables 5. the address of a function input parameter may be moved into a register using the mov instruction.Chapter 5. In PTX. mystruct). … st.param byte array variable that represents a flattened C structure or union. int y.f64 dbl.param. [buffer+8]. which declares a . This will be passed by value to a callee.6.

An error is generated if the maximum number of physical resources is exceeded. 32 January 24.global .texref variables in the . Texture State Space (deprecated) The texture (. A texture’s base address is assumed to be aligned to a 16-byte boundary.tex variables are required to be defined in the global scope.7. Another is sequential access from sequential threads. For example. 2010 . tex_d. Shared State Space The shared (. Use ld.tex .u32 tex_a. a legacy PTX definitions such as . and . Multiple names may be bound to the same physical texture identifier.tex .u32 or .tex directive will bind the named texture memory variable to a hardware texture identifier.u32 tex_a.global state space.u32 . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).u32 . It is shared by all threads in a context.1.tex .tex . where all threads read from the same address.0 5.tex state space are equivalent to module-scoped .PTX ISA Version 2.texref tex_a. tex_f. where texture identifiers are allocated sequentially beginning with zero.u64. An address in shared memory can be read and written by any thread in a CTA. Texture memory is read-only. tex_d.shared) state space is a per-CTA region of memory for threads in a CTA to share data. tex_c.shared to access shared variables. The . and programs should instead reference texture memory through variables of type . is equivalent to .u32 . 5. See Section 5.7.tex directive is retained for backward compatibility.tex) state space is global memory accessed via the texture instruction. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. Physical texture resources are allocated on a per-module granularity.1. Shared memory typically has some optimizations to support the sharing.3 for the description of the . The . The texture name must be of type .texref.8.texref type and Section 8. and variables declared in the .6 for its use in texture instructions.tex .shared and st. One example is broadcast. Example: .

5.f16 floating-point type is allowed only in conversions to and from .b8. stored.Chapter 5. Types. stored. For example.u8. Restricted Use of Sub-Word Sizes The .1. the fundamental types reflect the native data types supported by the target architectures.f32 and .f64 .f64 types. Fundamental Types In PTX.2.b16. and . . . and cvt instructions. .u16.2. but typed variables enhance program readability and allow for better operand type checking.b8 instruction types are restricted to ld. Signed and unsigned integer types are compatible if they have the same size. .f32 and . st.u32. . or converted to other types and sizes. so that narrow values may be loaded. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . For convenience.2. and Variables 5.s8. and instructions operate on these types.u8. so their names are intentionally short. A fundamental type specifies both a basic type and a size. ld. January 24. .s64 . needed to fully specify instruction behavior. Register variables are always of a fundamental type. . and converted using regular-width registers.u64 . 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. The bitsize type is compatible with any fundamental type having the same size. All floating-point instructions operate only on . Operand types and sizes are checked against instruction types for compatibility. all variables (aside from predicates) could be declared using only bit-size types. Two fundamental types are compatible if they have the same basic type and are the same size. .b64 .s8.b32.pred Most instructions have one or more type specifiers. The following table lists the fundamental type specifiers for each basic type: Table 8. .f64 types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. In principle. The same typesize specifiers are used for both variable definitions and for typing instructions.f32. 2010 33 . The . . . State Spaces.s16. .f16. Types 5.2. st.s32.

and de-referenced by texture and surface load. and overall size is hidden to a PTX program.e. passed as a parameter to functions. accessing the pointer with ld and st instructions.samplerref variables. field ordering.texref type that describe sampler properties are ignored. or performing pointer arithmetic will result in undefined results. and surface descriptor variables.surfref. Referencing textures. For working with textures and samplers. Retrieving the value of a named member via query instructions (txq. since these properties are defined by . In the unified mode. 2010 . These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.texref handle. allowing them to be defined separately and combined at the site of usage in the program.0 5.texref. These types have named fields similar to structures. 34 January 24.PTX ISA Version 2. store. Creating pointers to opaque variables using mov. but the pointer cannot otherwise be treated as an address. and Surface Types PTX includes built-in “opaque” types for defining texture. PTX has two modes of operation. texture and sampler information each have their own handle. and query instructions. samplers. suq). suld. In independent mode the fields of the . sust. . The three built-in types are . the resulting pointer may be stored to and loaded from memory.{u32. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. or surfaces via texture and surface load/store instructions (tex. and .samplerref. base address.u64} reg. In the independent mode. Texture. opaque_var. Sampler.3.. but all information about layout. sampler. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. i. The following tables list the named members of each type for unified and independent texture modes. hence the term “opaque”. sured). texture and sampler information is accessed through a single .

1 ignored ignored ignored ignored . clamp_ogl. Member width height depth Opaque Type Fields in Unified Texture Mode . mirror. Member width height depth Opaque Type Fields in Independent Texture Mode . linear wrap. clamp_to_edge. 1 nearest. 2010 35 . Types. clamp_ogl. clamp_to_border 0. State Spaces. and Variables Table 9.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_edge.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. linear wrap.texref values . mirror.Chapter 5.samplerref values N/A N/A N/A N/A nearest. clamp_to_border N/A N/A N/A N/A N/A .texref values in elements in elements in elements 0.

As kernel parameters. When declared at module scope. these variables must be in the .param state space. 2010 . the types may be initialized using a list of static expressions assigning values to the named members.PTX ISA Version 2. Example: .global .texref tex1.global .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global .global state space.global .samplerref my_sampler_name. At module scope. filter_mode = nearest }. these variables are declared in the . . . .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. 36 January 24.texref my_texture_name.global .surfref my_surface_name. Example: .

f64 is not allowed. January 24. Vectors must be based on a fundamental type. a variable declaration describes both the variable’s type and its state space. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. // typedef . an optional initializer.0. 2010 37 . for example. vector variables are aligned to a multiple of their overall size (vector length times base-type size).u8 bg[4] = {0.4.const . Examples: . .global .f32 V. // a length-4 vector of bytes By default. r.v2.struct float4 coord.reg . .pred p. 5. . . an optional array size. its type and size.v4 vector.1. In addition to fundamental types.f32 bias[] = {-1.global . .f32 accel. Vectors Limited-length vector types are supported.4. 5. . PTX supports types for simple aggregate objects such as vectors and arrays. 0. This is a common case for three-dimensional grids. // a length-2 vector of unsigned ints .v4 .u16 uv. Types.0}. and they may reside in the register space. . and Variables 5. etc. where the fourth element provides padding.2.v1.v4.v2 . 1.b8 v. A variable declaration names the space in which the variable resides.struct float4 { .v4 . // a length-4 vector of floats .shared . 0}.Chapter 5. q. Examples: .global . 0. and an optional fixed address for the variable.u32 loc.v2 or . State Spaces. Predicate variables may only be declared in the register state space.reg .reg . textures.global . Vectors cannot exceed 128-bits in length.s32 i. Variable Declarations All storage for data is specified with variable declarations. Variables In PTX.f32 v0. Three-element vectors may be handled by using a .global . its name.v3 }.v4 . Every variable must reside in one of the state spaces enumerated in the previous section.v4.4. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with .

To declare an array.3. // address of rgba into ptr Currently.f32 blur_kernel[][] = {{.shared .f16 and ..u64.0.05. Similarly. 0}.0}. A scalar takes a single value.u16 kernel[19][19].0}}. {0. Array Declarations Array declarations are provided to allow the programmer to reserve space.4. {0.PTX ISA Version 2. being determined by an array initializer.4.0. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. this can be used to initialize a jump table to be used with indirect branches or calls. 38 January 24.{.global .u8 mailbox[128]. Initializers are allowed for all types except .s32 offset[][] = { {-1. {1.. Here are some examples: .1.1.v4 .05}. .0.u32 or . 19*19 (361) halfwords are reserved (722 bytes). Variable names appearing in initializers represent the address of the variable. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.05}}. variable initialization is supported only for constant and global state spaces.pred.local .1}.0. For the kernel declaration above.{.. . this can be used to statically initialize a pointer to a variable.global . -1}. .global .0 5..1. 5.4. The size of the dimension is either a constant expression.b32 ptr = rgba. . .0}. 0}. or is left empty.u8 rgba[3] = {{1. 2010 . where the variable name is followed by an equals sign and the initial value or values for the variable. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). {0. 1} }.global . Examples: .1. {0.global . label names appearing in initializers represent the address of the next instruction following the label. The size of the array specifies how many elements should be reserved. Variables that hold addresses of variables or instructions should be of type .4.s32 n = 10..1.05..

Rather than require explicit declaration of every name. . The default alignment for scalar and array variables is to a multiple of the base-type size. Array variables cannot be declared this way. January 24.b32 variables. Elements are bytes.0. For example. 5. not for individual elements.4. and Variables 5.0}. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. Examples: // allocate array at 4-byte aligned address. it is quite common for a compiler frontend to generate a large number of register names. For arrays.const . %r1. . PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.0. %r99..Chapter 5. These 100 register variables can be declared as follows: . %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. The variable will be aligned to an address which is an integer multiple of byte-count. named %r0.5. nor are initializers permitted.. Alignment is specified using an optional .align 4 . // declare %r0.reg . 2010 39 . of . ….6. Parameterized Variable Names Since PTX supports virtual registers. and may be preceded by an alignment specifier. alignment specifies the address alignment for the starting address of the entire array.0. State Spaces. say one hundred.0.0.. Types.2. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. suppose a program uses a large number.align byte-count specifier immediately following the state-space specifier. The default alignment for vector variables is to a multiple of the overall vector size. %r1.b32 %r<100>.b8 bar[8] = {0.4.

2010 .0 40 January 24.PTX ISA Version 2.

as its job is to convert from nearly any data type to any other data type (and size). For most operations.3. q. . The mov instruction copies data between registers. and cvt instructions copy data from one location to another. Integer types of a common size are compatible with each other. st. Predicate operands are denoted by the names p. b. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions.2. Each operand type must be compatible with the type determined by the instruction template and instruction type. s. and c. the sizes of the operands must be consistent. Operand Type Information All operands in instructions have a known type from their declarations. r. Instruction Operands 6. 6. mov. PTX describes a load-store machine. 6. The ld. The bit-size type is compatible with every type having the same size. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. The result operand is a scalar or vector variable in the register state space. Source Operands The source operands are denoted in the instruction descriptions by the names a. January 24.reg register state space. The cvt (convert) instruction takes a variety of operand types and sizes. and a few instructions have additional predicate source operands. There is no automatic conversion between types.1. Instructions ld and st move data from/to addressable state spaces to/from registers. so operands for ALU instructions must all be in variables declared in the . 2010 41 .Chapter 6. Most instructions have an optional predicate guard that controls conditional execution.

W.v4 .v4 .1. .s32 mov. ld. and immediate address expressions which evaluate at compile-time to a constant address.f32 ld. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.shared .[x]. . The mov instruction can be used to move the address of a variable into a pointer.const.4. arrays. address register plus byte offset.gloal.f32 W.global .s32 tbl[256]. The syntax is similar to that used in many assembly languages. Examples include pointer arithmetic and pointer comparisons.reg . Using Addresses. [tbl+12].reg . . The interesting capabilities begin with addresses.4. and vectors.PTX ISA Version 2. . The address is an offset in the state space in which the variable is declared. Here are a few examples: .u16 r0.f32 V.shared. Address expressions include variable names.reg . All addresses and address computations are byte-based. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.s32 q. [V]. r0.b32 p. 2010 .reg .u16 x.u32 42 January 24. tbl. . 6.0 6.u16 ld. Arrays. q. . there is no support for C-style pointer arithmetic. and Vectors Using scalar variables as operands is straightforward.const . Load and store operations move data between registers and locations in addressable state spaces. address registers.v4. p.

y. c. .f32 a.b V.b and . Elements in a brace-enclosed vector.u32 s. . and tex.u32 {a. Vectors as Operands Vector operands are supported by a limited subset of instructions.v2. which may improve memory performance.global. Vector loads and stores can be used to implement wide loads and stores. .y V.4.d}. Rb. Rc.x V. January 24.global. 2010 43 .global. say {Ra. and the identifier becomes an address constant in the space where the array is declared.z V. The expression within square brackets is either a constant integer.b. or by indexing into the array using square-bracket notation. .u32 s.u32 s. a[1].c.w. V.z and .v4.a. a[0]. d. The size of the array is a constant in the program. where the offset is a constant expression that is either added or subtracted from a register variable.4. . If more complicated indexing is desired.g V. Arrays as Operands Arrays of all types can be declared. . a register variable. ld.4.c. Vector elements can be extracted from the vector with the suffixes . Array elements can be accessed using an explicitly calculated byte address.r V.4.w = = = = V. // move address of a[1] into s 6.r. which include mov. mov. The registers in the load/store operations can be a vector.f32 V. Vectors may also be passed as arguments to called functions. Instruction Operands 6. st. V2. a[N-1].reg . or a simple “register with constant offset” expression. Examples are ld.d}. or a braceenclosed list of similarly typed scalars.v4.a 6.global. it must be written as an address calculation prior to use.f32 ld. A brace-enclosed list is used for pattern matching to pull apart vectors.v4 .reg . ld.x. Here are examples: ld. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.f32 {a.g.3.b. as well as the typical color fields .2.Chapter 6. and in move instructions to get the address of the label or function into a register. for use in an indirect branch or call. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. mov. b. [addr+offset2]. Rd}. [addr+offset].

6.PTX ISA Version 2. 2010 . if a cvt. except for operations where changing the size and/or type is part of the definition of the instruction. 44 January 24. Type Conversion All operands to all arithmetic.1.u16 instruction is given a u16 source operand and s32 as a destination operand. For example.000 for f16). and ~131. Operands of different sizes or types must be converted prior to the operation. and data movement instruction must be of the same type and size.5.s32. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.0 6. logic. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. the u16 is zero-extended to s32.5.

Instruction Operands Table 11.u32 targeting a 32-bit register will first chop to 16-bits. Notes 1 If the destination register is wider than the destination format. f2u = float-to-unsigned. f2s = float-to-signed. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. zext = zero-extend. s2f = signed-to-float. cvt. the result is extended to the destination register width after chopping. For example. chop = keep only low bits that fit.Chapter 6. then sign-extend to 32-bits. u2f = unsigned-to-float. f2f = float-to-float. 2010 45 .s16. January 24. The type of extension (sign or zero) is based on the destination format.

The following tables summarize the rounding modifiers. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.0 6.rm . Table 12.2. choosing even integer if source is equidistant between two integers. Modifier .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. there are four integer rounding modifiers and four floating-point rounding modifiers.rni .rzi .rmi .PTX ISA Version 2.rz .5. In PTX.rn .rpi Integer Rounding Modifiers Description round to nearest integer. 2010 . Rounding Modifiers Conversion instructions may specify a rounding modifier. Modifier .

The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. while global memory is slowest. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Instruction Operands 6. 2010 47 . Much of the delay to memory can be hidden in a number of ways. Operand Costs Operands from different state spaces affect the speed of an operation. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Table 14. Another way to hide latency is to issue the load instructions as early as possible.Chapter 6. Table 11 gives estimates of the costs of using different kinds of memory. Registers are fastest. The register in a store operation is available much more quickly.6. first access is high Notes January 24.

PTX ISA Version 2. 2010 .0 48 January 24.

and is represented in PTX as follows: .func foo { … ret. Function declarations and definitions In PTX. and an optional list of input parameters. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. } … call foo. … Here. At the call. Scalar and vector base-type input and return parameters may be represented simply as register variables. the function name. January 24. 7.func directive. execution of the call instruction transfers control to foo. implicitly saving the return address. and Application Binary Interface (ABI). functions are declared and defined using the . we describe the features of PTX needed to achieve this hiding of the ABI. and memory allocated on the stack (“alloca”). so recursion is not yet supported. or prototype. These include syntax for function definitions. stack layout. stack-based ABI. 2010 49 . A function definition specifies both the interface and the body of the function. NOTE: The current version of PTX does not implement the underlying. and return values may be placed directly into register variables. arguments may be register variables or constants. function calls. Abstracting the ABI Rather than expose details of a particular calling convention. support for variadic functions (“varargs”). The simplest function has no parameters or return values.Chapter 7.1. A function declaration specifies an optional list of return parameters. together these specify the function’s interface. In this section. parameter passing. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Execution of the ret instruction within foo transfers control to the instruction following the call. A function must be declared or defined prior to being called.

param state space is used to pass the structure by value: . [y+9]. %rc1.param.b32 c1.param. %rc1.f64 f1. For example. The . ret. ld. (%x. bumpptr.align 8 y[12]) { . st.b64 [py+ 0].align 8 py[12].reg .param.0 Example: .param . st.f64 f1. . Since memory accesses are required to be aligned to a multiple of the access size. byte array in .param .reg .b8 c4. %rd.func (. c2.reg space.param variable y is used in function definition bar to represent a formal parameter.s32 out) bar (.PTX ISA Version 2. [y+11].param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.b8 .param space call (%out). %inc. c4. st. passed by value to a function: struct { double dbl.param. char c[4]. a . %rc2. st.param space variables are used in two ways. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .param. First.c3.b8 .reg .param space memory.param. … … // computation using x.reg . } … call (%r1). consider the following C structure.c2.b8 [py+ 9].param. (%r1. … ld.reg .u32 %inc ) { add. . … st. note that . inc_ptr. . // scalar args in .func (. ld.b8 [py+11].b8 [py+ 8].param.b8 c1.param. 2010 . } { . c3.reg . 50 January 24. [y+10]. }. Second.reg . [y+0]. … In this example. In PTX.param.u32 %res) inc_ptr ( .c1.c4. py).u32 %ptr. %rc2. a . [y+8]. ld. ld.u32 %res. %ptr.b8 [py+10].b8 c3.4).s32 x.f1. this structure will be flattened into a byte array. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .f64 field are aligned.b8 c2.

the corresponding argument may be either a .param space byte array with matching type. 4. or constants. In the case of .param state space is used to receive parameter values and/or pass return values back to the caller.param and ld. January 24. all st.param arguments. Note that the choice of . For .param state space is used to set values that will passed to a called function and/or to receive return values from a called function.param or .reg or . • The . size. • • • Input and return parameters may be . In the case of .g. 2. • • • For a callee. A . Parameters in .reg space variable of matching type and size. • • Arguments may be . . For a caller. The following restrictions apply to parameter passing.param variables.reg state space can be used to receive and return base-type scalar and vector values.reg variables. or 16 bytes.param or .reg space variable with matching type and size. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. a .param argument must be declared within the local scope of the caller.param variables or . or a constant that can be represented in the type of the formal parameter. The . and alignment of parameters.param space formal parameters that are byte arrays.param byte array is used to collect together fields of a structure being passed by value.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. Supporting the . or a constant that can be represented in the type of the formal parameter. the corresponding argument may be either a . The .Chapter 7.param memory must be aligned to a multiple of 1.reg space formal parameters. the argument must also be a .reg variables. size.param variable does not consume extra space in the caller’s frame beyond that needed by the ABI..param state space use in device functions. In the case of . For a caller. Abstracting the ABI The following is a conceptual way to think about the . and alignment. For a callee. 2010 51 . This enables backend optimization and ensures that the .param space formal parameters that are base-type scalar or vector variables.reg state space in this way provides legacy support. • The . 8.param instructions used for argument passing must be contained in the basic block with the call instruction. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. Typically.

and a .param space parameters support arrays. formal parameters were restricted to .0 7. For sm_2x targets. and .1.0. 52 January 24. and there was no support for array parameters. PTX 1. Changes from PTX 1. In PTX ISA version 2.x supports multiple return values for this purpose.reg state space.x In PTX ISA version 1. PTX 2. 2010 . Objects such as C structures were flattened and passed or returned using multiple registers.x.param byte array should be used to return objects that do not fit into a register.PTX ISA Version 2.0 continues to support multiple return registers for sm_1x targets.0 restricts functions to a single return value. formal parameters may be in either .reg or . PTX 2.param state space.1.

maxN. along with the size and alignment of the next data value to be accessed. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg . 4). .reg . . 2010 53 .func (. or 8 bytes.func (.reg . max. (ap. } … call (%max).u32 align) .u32 sz. variadic functions are declared with an ellipsis at the end of the input parameter list.reg . . 0. The function prototypes are defined as follows: . (2. following zero or more fixed parameters: .b32 result. %s1.reg .s32 result. the size may be 1.s32 result ) maxN ( . for %va_arg64.func %va_end (. This handle is then passed to the %va_arg and %va_arg64 built-in functions.reg .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.u32 b.reg .reg . 4. or 16 bytes. (3.s32 val.. %va_start.Chapter 7. bra Done. In PTX.u32 align) .u32 sz. %s2). maxN.pred p. To support functions with a variable number of arguments.h headers in C. . Abstracting the ABI 7. .2. (ap). %r1. 2.reg . … ) . . call (val).reg . call %va_end.reg . 4. 4. .reg . setp.func baz ( . call (ap).u32 a.reg . ) { . %va_arg. mov.u32 ap. the alignment may be 1. the size may be 1.u32 ptr. ret. result. … %va_start returns Loop: @p Done: January 24. In both cases. %va_end is called to free the variable argument list handle. %r3). 2.. . 8.func ( . … call (%max).u32 ptr) %va_start .func (. N. ctr.reg . Once all arguments have been processed.b32 ctr. Variadic functions NOTE: The current version of PTX does not support variadic functions. 0x8000000.reg .h and varargs.u32. For %va_arg. PTX provides a high-level mechanism similar to the one provided by the stdarg. %r2.reg . ctr. or 4 bytes.u32 ptr.b32 val) %va_arg (.b64 val) %va_arg64 (. val. and end access to a list of variable arguments.ge p. 2.u32 N. // default to MININT mov. iteratively access.reg .func okay ( … ) Built-in functions are provided to initialize. bra Loop.

PTX ISA Version 2. a function simply calls the built-in function %alloca. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. Alloca NOTE: The current version of PTX does not support alloca. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.local instructions. defined as follows: .reg . To allocate memory.3. The array is then accessed with ld. 54 January 24. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( .local and st.0 7.reg .u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.u32 ptr ) %alloca ( . 2010 . If a particular alignment is required.

PTX Instructions PTX instructions generally have from zero to four operands. We use a ‘|’ symbol to separate multiple destination registers. opcode D. Instruction Set 8. followed by some examples that attempt to show several possible instantiations of the instruction. the D operand is the destination operand. while A. B. For some instructions the destination operand is optional. C. b. opcode D. setp. A.lt p|q. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. 2010 55 . 8. B. B. and C are the source operands. The setp instruction writes two destination registers.Chapter 8. January 24. opcode A. opcode D. For instructions that create a result value. A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. In addition to the name and the format of the instruction. a. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. // p = (a < b). A.1.2.s32. the semantics are described. q = !(a < b).

1.lt. So. Instructions without a guard predicate are executed unconditionally. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”.pred p.s32 p. i. consider the high-level code if (i < n) j = j + 1.pred as the type specifier. q. predicate registers can be declared as . use a predicate to control the execution of the branch or call instructions. branch over 56 January 24. the following PTX instruction sequence might be used: @!p L1: setp. 1. n. add. add. bra L1.3. To implement the above example as a true conditional branch.PTX ISA Version 2. j.reg . i. predicate registers are virtual and have . // p = (i < n) // if i < n.s32 j. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.s32 j. add 1 to j To get a conditional branch or conditional function call. … // compare i to n // if false. Predicated Execution In PTX. Predicates are most commonly set as the result of a comparison performed by the setp instruction. where p is a predicate variable. optionally negated. n. As an example. 2010 . j.s32 p.0 8. This can be written in PTX as @p setp.lt.

Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. lt. Instruction Set 8. 2010 57 . hi (higher). The following table shows the operators for signed integer. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. ne (not-equal). ls (lower-or-same). If either operand is NaN. The unsigned comparisons are eq. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal).2.3. and hs (higher-or-same). Unsigned Integer.1. le (less-than-or-equal). unsigned integer. ordering comparisons are not defined for bit-size types.Chapter 8. and ge (greater-than-or-equal). The bit-size comparisons are eq and ne.3. the result is false. Table 16. ne. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. and bitsize types.1. ge.1. le.3. gt (greater-than). Table 15. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ne. lt (less-than).1. lo (lower). Comparisons 8. gt.

xor. geu.0. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.u32 %r1. then the result of these comparisons is true. not. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. If either operand is NaN.0 To aid comparison operations in the presence of NaN values. setp can be used to generate a predicate from an integer. However. // convert predicate to 32-bit value 58 January 24. gtu. two operators num (numeric) and nan (isNaN) are provided.%p. There is no direct conversion between predicates and integer values. If both operands are numeric values (not NaN). for example: selp. then these comparisons have the same result as their ordered counterparts. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. and no direct way to load or store predicate register values. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.2. Table 17. Table 18. unordered versions are included: equ. or. and mov.1. 2010 . num returns true if both operands are numeric values (not NaN). leu.3. neu.PTX ISA Version 2. ltu. and nan returns true if either operand is NaN.

f32.uX ok ok ok inv .u16 a. Table 19. a.reg .uX . Type Information for Instructions and Operands Typed instructions must have a type-size modifier. and these are placed in the same order as the operands. different sizes). // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. i. and this information must be specified as a suffix to the opcode. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.reg . and integer operands are silently cast to the instruction type if needed. add. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.fX ok ok ok ok January 24.f32 d. For example.sX . they must match exactly. .fX ok inv inv ok Instruction Type .4.bX . Example: .bX .sX ok ok ok inv . cvt. It requires separate type-size modifiers for the result and source. For example. Type Checking Rules Operand Type . unsigned. the add instruction requires type and size information to properly perform the addition operation (signed.u16 d. For example: . Instruction Set 8.. float. a. b. Floating-point types agree only if they have the same size.reg . most notably the data conversion instruction cvt. • The following table summarizes these type checking rules. a. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. b. 2010 59 .e.u16 d.u16 d.Chapter 8. Signed and unsigned integer types agree provided they have the same size.

Bit-size source registers may be used with any appropriately-sized instruction type. 2. no conversion needed. st. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.4. Source register size must be of equal or greater size than the instruction-type size. floating-point instruction types still require that the operand type-size matches exactly. When a source operand has a size that exceeds the instruction-type size. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. “-“ = allowed. For example. Floating-point source registers can only be used with bit-size or floating-point instruction types. unless the operand is of bit-size type.bX instruction types. the size must match exactly. the data will be truncated. Notes 3. The following table summarizes the relaxed type-checking rules for source operands. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. The data is truncated to the instruction-type size and interpreted according to the instruction type. 60 January 24. and converted using regular-width registers. Table 20. so those rows are invalid for cvt. Operand Size Exceeding Instruction-Type Size For convenience. parse error. 1.PTX ISA Version 2. When used with a narrower bit-size type. stored. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Note that some combinations may still be invalid for a particular instruction. stored. inv = invalid.1. the cvt instruction does not support . or converted to other types and sizes. so that narrow values may be loaded. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. 2010 . for example.0 8. ld. When used with a floating-point instruction type. 4. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type.

otherwise. 2. If the corresponding instruction type is signed integer.or sign-extended to the size of the destination register. When used with a floatingpoint instruction type. Table 21. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. Destination register size must be of equal or greater size than the instruction-type size. January 24. “-“ = Allowed but no conversion needed. The data is sign-extended to the destination register width for signed integer instruction types. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. inv = Invalid. The following table summarizes the relaxed type-checking rules for destination operands. 1. Notes 3. the size must match exactly. 4. The data is signextended to the destination register width for signed integer instruction types. Bit-size destination registers may be used with any appropriately-sized instruction type. Instruction Set When a destination operand has a size that exceeds the instruction-type size. 2010 61 . the data will be zero-extended. and is zero-extended to the destination register width otherwise. the destination data is zero. Floating-point destination registers can only be used with bit-size or floating-point instruction types. zext = zero-extend.Chapter 8. parse error. the data is zeroextended. the data is sign-extended. When used with a narrower bit-size instruction type.

If threads execute down different control flow paths. Both situations occur often in programs.uni suffix. When executing on a 32-bit data path.6. so it is important to have divergent threads re-converge as soon as possible.5. at least in appearance. conditional function call. A compiler or programmer may chose to enforce portable. the semantics of 16-bit instructions in PTX is machine-specific. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. If all of the threads act in unison and follow a single control flow path. the threads are called divergent. For divergent control flow. the optimizing code generator automatically determines points of re-convergence.1. Therefore. 16-bit registers in PTX are mapped to 32-bit physical registers. However.6. by a right-shift instruction. for example.0 8. the threads are called uniform. until C is not expressive enough. At the PTX language level. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. a compiler or code author targeting PTX can ignore the issue of divergent threads. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. 8. and 16-bit computations are “promoted” to 32-bit computations. and for many applications the difference in execution is preferable to limiting performance. 2010 . These extra precision bits can become visible at the application level. until they come to a conditional control construct such as a conditional branch. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. or conditional return. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. The semantics are described using C.PTX ISA Version 2. using the . 8. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. for many performance-critical applications. 62 January 24. this is not desirable. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. Divergence of Threads in Control Constructs Threads in a CTA execute together.

Instructions All PTX instructions may be predicated.Chapter 8. In the following descriptions. the optional guard predicate is omitted from the syntax. The Integer arithmetic instructions are: add sub add. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.cc. 2010 63 . subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. Instruction Set 8.1.cc.7. 8. addc sub.7.

0 Table 22. sub. .u16. b.s32 .sat}. add. a.u16. .s32 c. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another. . add.sat applies only to .s32.. 2010 . .sat. .c.type add{. .. // . d. . Supported on all target architectures. Saturation modifier: .sat applies only to . d = a + b.s32 type.sat limits result to MININT.0. a.type sub{. b. . d.s64 }.u32.sat limits result to MININT.PTX ISA Version 2.z.MAXINT (no overflow) for the size of the operation. Introduced in PTX ISA version 1.0. Applies only to .y.1. sub. // . @p add. Saturation modifier: . a.s32 d. PTX ISA Notes Target ISA Notes Examples 64 January 24.s32 d.s16.s64 }. d = a – b.sat}.s32.s32 type. .s32 c. a. .u64.type = { . b.u32.s16. add Syntax Integer Arithmetic Instructions: add Add two values. PTX ISA Notes Target ISA Notes Examples Table 23.u32 x.a. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Introduced in PTX ISA version 1.u64.b. Description Semantics Notes Performs addition and writes the resulting value into a destination register. b.type = { . Applies only to .s32 . Supported on all target architectures.MAXINT (no overflow) for the size of the operation.

No other instructions access the condition code. d = a + b + CC. or testing the condition code. 2010 65 .b32 addc.y3.cc. Behavior is the same for unsigned and signed integers. No saturation. x4.b32 addc. . Instruction Set Instructions add. Supported on all target architectures.CF. carry-out written to CC. x3. . Supported on all target architectures. add.u32. x2. and there is no support for setting. These instructions support extended-precision integer addition and subtraction. Introduced in PTX ISA version 1.y4. . @p @p @p @p add. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out.2. .b32 addc. if . d = a + b.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. a. add. b. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.y1. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.CF) holding carry-in/carry-out or borrowin/borrow-out.z4.cc.cc.2. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc.cc specified.cc Syntax Integer Arithmetic Instructions: add.b32 addc.z2.type d. clearing.cc Add two values with carry-out.type d. addc{.y3. x4.y2. x3.cc. b.s32 }. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.cc.type = {.u32.cc}. addc.b32 addc.z3.y2.cc. Introduced in PTX ISA version 1.z1. carry-out written to CC.cc.s32 }.y4.z4.z1.cc.Chapter 8. sub.b32 x1.z3.y1.b32 x1.z2. Table 24. a. Behavior is the same for unsigned and signed integers.type = { .b32 addc.CF No integer rounding modifiers. @p @p @p @p add.cc.CF No integer rounding modifiers. x2. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. No saturation.

cc.z3.cc. Supported on all target architectures.b32 subc. d = a .b32 subc.y2. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. No saturation.b32 subc.cc. x2. 2010 . a.type d. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.cc}.y3. x3.b32 x1. @p @p @p @p sub.z2.(b + CC.CF No integer rounding modifiers.y1.s32 }.y4. subc{. borrow-out written to CC. Introduced in PTX ISA version 1.u32. b.y3.b32 subc. Behavior is the same for unsigned and signed integers.cc Syntax Integer Arithmetic Instructions: sub.b32 subc.cc Subract one value from another.3. d = a – b. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. a. b. withborrow-in and optional borrow-out.z2. sub. @p @p @p @p sub.z4.3. sub. x4. . .cc.z4.cc specified.s32 }. if .type = {.CF No integer rounding modifiers. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register. .cc. .PTX ISA Version 2. No saturation.CF).cc.z1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.cc. x2. borrow-out written to CC. Supported on all target architectures.b32 subc.y2. x3. Introduced in PTX ISA version 1.b32 x1.z3. with borrow-out.type d.type = { .cc. x4.y1.cc.y4.0 Table 26.u32.z1. Behavior is the same for unsigned and signed integers.

s16 fa.fys. . If .. d = t. t = a * b. and either the upper or lower half of the result is written to the destination register.lo.0.type = { .x.fys. .hi or .fxs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi variant // for . The . save only the low 16 bits // 32*32 bits. .type d. then d is the same size as a and b.u64. mul.s64 }.s32 z.s32.s16 fa. creates 64 bit result January 24...u16.wide is specified. . then d is twice as wide as a and b to receive the full result of the multiplication.wide}. If .0>. // 16*16 bits yields 32 bits // 16*16 bits.wide suffix is supported only for 16. . mul. // for .u32.lo variant Notes The type of the operation represents the types of the a and b operands.y. b.lo is specified.Chapter 8. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. mul.s16.wide // for . Instruction Set Table 28. mul{. Description Semantics Compute the product of two values..wide.lo. n = bitwidth of type. Supported on all target architectures. d = t<n-1. 2010 67 .hi. d = t<2n-1.n>. a.fxs.and 32-bit integer types. .wide.

@p mad.sat. t<n-1.and 32-bit integer types..q.s32 d. t n d d d = = = = = a * b.hi.a. Description Semantics Multiplies two values and adds a third. . Saturation modifier: .p.b. .s32 d.u64. If . then d and c are the same size as a and b.u32.s32.lo.hi or .lo. 68 January 24.n> + c.hi..s32 r.. b.type mad.u16. b. bitwidth of type. . . The . Supported on all target architectures.r. mad{. and either the upper or lower half of the result is written to the destination register.MAXINT (no overflow) for the size of the operation. .0 Table 29.0> + c.PTX ISA Version 2.s64 }..s32 type in .sat limits result to MININT. d.wide is specified. then d and c are twice as wide as a and b to receive the result of the multiplication. // for .lo.wide // for .wide}. . 2010 .wide suffix is supported only for 16. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. mad.lo variant Notes The type of the operation represents the types of the a and b operands.lo is specified. a. If . t + c.. t<2n-1. Applies only to .hi variant // for . and then writes the resulting value into a destination register.c. c.type = { . a.hi mode. c.0.s16. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

mul24. b. // for .u32. a. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. January 24.a.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.hi variant // for .. .lo}. 2010 69 .hi..lo.0>.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result. mul24{.type d.type = { . All operands are of the same type and size. d = t<31.s32 d.Chapter 8. t = a * b.e. mul24. 48bits.s32 }. d = t<47. // low 32-bits of 24x24-bit signed multiply. Instruction Set Table 30. Supported on all target architectures. mul24. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. i. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. and return either the high or low 32-bits of the 48-bit result.b.. mul24.0. .16>.hi may be less efficient on machines without hardware support for 24-bit multiply.

. mad24.s32 d.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.u32. Return either the high or low 32-bits of the 48-bit result.type mad24.type = { .s32 type in . 48bits. a. 70 January 24.b. mad24{. and add a third. Applies only to . Saturation modifier: . a. . All operands are of the same type and size.sat limits result of 32-bit signed addition to MININT.0 Table 31.sat. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.hi may be less efficient on machines without hardware support for 24-bit multiply.hi..s32 d. b. d = t<47. c. . i.lo}.MAXINT (no overflow). b. // low 32-bits of 24x24-bit signed multiply. 32-bit value to either the high or low 32-bits of the 48-bit result. d. t = a * b.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. mad24. // for . 2010 .lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.c.hi.s32 }. mad24.. Description Compute the product of two 24-bit integer values held in 32-bit source registers.0.a.hi variant // for .0> + c.16> + c.e..PTX ISA Version 2. Supported on all target architectures. d = t<31.hi mode. c. mad24.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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type d. . popc. // cnt is . while (a != 0) { if (a&0x1) d++. mask = 0x80000000. a. } Introduced in PTX ISA version 2. d = 0. . } else { max = 64. For . a.b32 type. X.u32 PTX ISA Notes Target ISA Notes Examples Table 40.b64 }. cnt.b64 }. X. clz requires sm_20 or later.0 Table 39.0. the number of leading zeros is between 0 and 64.b64 type. clz. mask = 0x8000000000000000.b32 clz. a = a >> 1.type d.b32. a.b64 d. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b64 d. popc Syntax Integer Arithmetic Instructions: popc Population count.b32.b32 popc. For . d = 0. popc requires sm_20 or later. . if (. inclusively. . } while (d < max && (a&mask == 0) ) { d++. a. the number of leading zeros is between 0 and 32.type = { .type = { . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a = a << 1.type == . Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. // cnt is . inclusively. popc.PTX ISA Version 2. 2010 .b32) { max = 32. clz.u32 Semantics 74 January 24.0. cnt.

bfind requires sm_20 or later.Chapter 8. bfind returns 0xFFFFFFFF if no non-sign bit is found. Instruction Set Table 41. If . .d.shiftamt && d != -1) { d = msb . // cnt is . Operand a has the instruction type.s32) ? 31 : 63. } } if (.shiftamt is specified. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.u32.s32. i>=0. X.type d.s64 }.type==. a. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind.type==.u32. for (i=msb. For unsigned integers. bfind returns the bit position of the most significant “1”.u32 January 24.shiftamt. i--) { if (a & (1<<i)) { d = i. d.type = { .shiftamt. .u64. bfind. . d = -1.u32 || .u32 d. a.s64 cnt.type bfind. . Description Find the bit position of the most significant non-sign bit in a and place the result in d. 2010 75 . bfind.0. break. and operand d has type . Semantics msb = (. For signed integers. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. a.

type = { . brev. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==. brev.0 Table 42. brev requires sm_20 or later. Description Semantics Perform bitwise reversal of input. a. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. for (i=0.0. 76 January 24. i++) { d[i] = a[msb-i].type d. . . 2010 .b32. i<=msb.b32 d.b64 }.b32) ? 31 : 63.PTX ISA Version 2. a. msb = (.

bfe.type==. if (. .u32.start. d = 0. bfe requires sm_20 or later.len. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. .type = { . pos = b. Operands a and d have the same type as the instruction type.Chapter 8. and operands b and c are type . a.s64 }. . bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. The sign bit of the extracted field is defined as: .u32.u32 || .type==.msb)]. the destination d is filled with the replicated sign bit of the extracted field. The destination d is padded with the sign bit of the extracted field. bfe. len = c. .0. c. .u32. 2010 77 .u64 || len==0) sbit = 0.a.s32. b. . Description Extract bit field from a and place the zero or sign-extended result in d. else sbit = a[min(pos+len-1. Instruction Set Table 43. and source c gives the bit field length in bits.b32 d. Semantics msb = (.type==. i<=msb. Source b gives the bit field starting bit position. If the start position is beyond the msb of the input.u64: .u64. January 24. for (i=0. otherwise If the bit field length is zero.u32 || .s32) ? 31 : 63.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type==.s32.type d. the result is zero.

a. pos = c. bfi requires sm_20 or later. and f have the same type as the instruction type. and operands c and d are type . .type = { . d. 2010 . the result is b. If the start position is beyond the msb of the input. f = b. . bfi.type f.b64 }. If the bit field length is zero. 78 January 24. b. b. for (i=0.b32 d.b32) ? 31 : 63. Description Align and insert a bit field from a into b. Operands a.PTX ISA Version 2.b.start. the result is b.b32. c. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 44. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.0. i<len && pos+i<=msb. len = d. Source c gives the starting bit position for the insertion.len.u32. and place the result in f.type==. i++) { f[pos+i] = a[i]. bfi. and source d gives the bit field length in bits. Semantics msb = (.a.

c.rc8. b5. b. b6.ecr. b0}}. .b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. prmt. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.b4e. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.rc16 }.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. .b32{. a 4-bit selection value is defined. msb=0 means copy the literal value. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. 2010 79 .mode = { . default mode index d. The bytes in the two source registers are numbered from 0 to 7: {b. .b3 source select c[15:12] d.Chapter 8.b2 source select c[11:8] d. Description Pick four arbitrary bytes from two 32-bit registers. as a 16b permute code. Note that the sign extension is only performed as part of generic form. . the four 4-bit values fully specify an arbitrary byte permute. For each byte in the target register.ecl. b1. a} = {{b7.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. {b3. . and reassemble them into a 32-bit destination register. b4}. the permute control consists of four 4-bit selection values. In the generic form (no mode specified).b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b1 source select c[7:4] d.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. . a. The msb defines if the byte value should be copied. Instruction Set Table 45. Thus. b2.mode} d. msb=1 means replicate the sign.f4e.

r2. r4. tmp[23:16] = ReadByte( mode. r3.0. 2010 .b32 prmt.0 Semantics tmp64 = (b<<32) | a.PTX ISA Version 2. r1. tmp64 ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[2]. prmt requires sm_20 or later. } tmp[07:00] = ReadByte( mode. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp64 ). ctl[3]. ctl[1] = (c >> 4) & 0xf. tmp[15:08] = ReadByte( mode. prmt. 80 January 24. ctl[2] = (c >> 8) & 0xf.b32. ctl[3] = (c >> 12) & 0xf. tmp64 ). tmp64 ). tmp[31:24] = ReadByte( mode. ctl[1]. r4.f4e r1. r3. ctl[0]. r2.

Instruction Set 8. 2010 81 .f32 and .Chapter 8. Floating-Point Instructions Floating-point instructions operate on .7. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.2.f64 register operands and constant immediate values.

rn and instructions may be folded into a multiply-add.f64 and fma.max}. Instruction Summary of Floating-Point Instructions .mul}. The optional .f64 {abs.lg2.rn and instructions may be folded into a multiply-add.ftz . 82 January 24. mul.neg.f32 {div.min.PTX ISA Version 2.rz .min. Single-precision add. No rounding modifier. .f64 are the same.rcp. default is . {mad.fma}.rcp.f32 are the same. so PTX programs should not rely on the specific single-precision NaNs being generated.rnd.f64 {sin.sub. NaN payloads are supported for double-precision instructions. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.mul}. default is .target sm_20 mad.0 The following table summarizes floating-point instructions in PTX.rnd.full.approx.fma}.sqrt}. Note that future implementations may support NaN payloads for single-precision instructions.f32 {div.rp .f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.sqrt}.rnd.f32 {abs.f32 {mad. Double-precision instructions support subnormal inputs and results.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.f32 .sqrt}.rcp.0.32 and fma.f32 {div.target sm_1x No rounding modifier.sub.approx.0].f32 rsqrt. but single-precision instructions return an unspecified NaN.rn .f32 {add.f64 div.f64 rsqrt.f64 mad.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. 2010 .rnd. Table 46.max}.approx.rnd. .cos. and mad support saturation of results to the range [0. 1. with NaNs being flushed to positive zero.neg. If no rounding modifier is specified. sub. {add.approx.target sm_20 .ex2}.rm .sat Notes If no rounding modifier is specified.rnd.

a. .notanumber.type = { . f0. January 24. y.0. b.type = { .f64 }. positive and negative zero are considered normal numbers. testp.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. .f32. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. . .infinite. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.f32 copysign.finite.subnormal }. testp requires sm_20 or later.type d.notanumber. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Instruction Set Table 47. z. 2010 83 .op. . true if the input is a subnormal number (not NaN.f64 }. // result is . testp Syntax Floating-Point Instructions: testp Test floating-point property. X.number.infinite testp.f64 isnan. .number testp.finite testp.0.notanumber testp. Table 48. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.f64 x.normal. . A.f32. not infinity) As a special case. .f32 testp.normal testp. testp. C. B. .pred = { . and return the result as d.Chapter 8.infinite. copysign. not infinity). copysign.type .op p. p. Introduced in PTX ISA version 2. testp. a. copysign requires sm_20 or later.

Rounding modifiers have the following target requirements: .f32 add{. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.0f.f3.ftz. a.f32 clamps the result to [0.0 Table 49. add{. 2010 .f32 flushes subnormal inputs and results to sign-preserving zero.0].rnd}{.f32 flushes subnormal inputs and results to sign-preserving zero.0. add. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f64.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. add. a. b.rnd = { . Description Semantics Notes Performs addition and writes the resulting value into a destination register. add Syntax Floating-Point Instructions: add Add two values.f32.rm.rp }.sat.rn.rp for add.rn): . add. 84 January 24. In particular. add.0. 1.rm mantissa LSB rounds towards negative infinity .f32 f1. NaN results are flushed to +0. . add. sm_1x: add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 requires sm_13 or later. . . .f2.rn.rn mantissa LSB rounds to nearest even .rnd}. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. d = a + b. d.ftz}{. requires sm_20 Examples @p add. subnormal numbers are supported. b.f64 d.sat}.rz. . requires sm_13 for add. Rounding modifiers (default is .PTX ISA Version 2. .rz available for all targets .f64 supports subnormal numbers.rz.rz mantissa LSB rounds towards zero .rm.ftz.f32 supported on all target architectures. Saturation modifier: .

a. . sub{.rz mantissa LSB rounds towards zero .f32 c. sub.rnd}{.rp }.f64.sat}.f32 supported on all target architectures.0].f2. sub. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64 supports subnormal numbers.rnd = { .f3. sm_1x: sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .ftz. a. .a. 1. requires sm_13 for sub. 2010 85 . Saturation modifier: sub.f32 flushes subnormal inputs and results to sign-preserving zero.Chapter 8.rn.rm mantissa LSB rounds towards negative infinity .f32 sub{. d = a .f32 clamps the result to [0.b. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0.rz available for all targets .rnd}.0f. subnormal numbers are supported. January 24. NaN results are flushed to +0. Rounding modifiers (default is . sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another. Rounding modifiers have the following target requirements: .f32 flushes subnormal inputs and results to sign-preserving zero.rz.f32. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0.rn. . In particular. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.ftz}{.rn): . . b. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rn mantissa LSB rounds to nearest even . b. sub. . Instruction Set Table 50.sat. sub.f64 d.b. requires sm_20 Examples sub.rn.rm.ftz. d.rp for sub.rm.f32 f1.f64 requires sm_13 or later.

mul{. mul Syntax Floating-Point Instructions: mul Multiply two values. Rounding modifiers (default is .0f.rm.f32 mul{. d = a * b. requires sm_20 Examples mul.0. sm_1x: mul.radius. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32.ftz}{. For floating-point multiplication.rn): . all operands must be the same size.rz available for all targets .f32 flushes subnormal inputs and results to sign-preserving zero. requires sm_13 for mul.f64.rz.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . . . Rounding modifiers have the following target requirements: .f32 circumf. . Saturation modifier: mul.rp }. 1.f64 requires sm_13 or later. subnormal numbers are supported.f32 flushes subnormal inputs and results to sign-preserving zero. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rnd = { .rn. b.rn mantissa LSB rounds to nearest even . Description Semantics Notes Compute the product of two values.sat}.rm. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero .pi // a single-precision multiply 86 January 24.rnd}{.ftz.f64 d. .ftz. d. In particular. . NaN results are flushed to +0.0]. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. mul.sat.0.f32 clamps the result to [0.f32 supported on all target architectures.f64 supports subnormal numbers. mul. a. 2010 . b. mul.rp for mul.rnd}. mul.PTX ISA Version 2.0 Table 51.rn. a.

rz mantissa LSB rounds towards zero .c.f32 is unimplemented in sm_1x.rnd. subnormal numbers are supported. sm_1x: fma. d = a*b + c.f32 fma.f64 requires sm_13 or later. fma. . fma.sat}.rm mantissa LSB rounds towards negative infinity . fma.f64 supports subnormal numbers. d. fma.x.f32 requires sm_20 or later. again in infinite precision.0].f64 w.rnd{.f64.Chapter 8. fma. The resulting value is then rounded to double precision using the rounding mode specified by .a.y.f64 d. fma.ftz.rnd. 2010 87 . .b.ftz. Instruction Set Table 52.f32 clamps the result to [0. .rn. NaN results are flushed to +0. PTX ISA Notes Target ISA Notes Examples January 24. c.0.rn.ftz}{.sat. d.f32 introduced in PTX ISA version 2.rnd = { . fma. fma.rp }. a. c.0f.f32 computes the product of a and b to infinite precision and then adds c to this product.z.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. fma. The resulting value is then rounded to single precision using the rounding mode specified by .f32 flushes subnormal inputs and results to sign-preserving zero. fma Syntax Floating-Point Instructions: fma Fused multiply-add.0. . a.rnd.rn mantissa LSB rounds to nearest even .4. again in infinite precision.f32 fma.rm.f64 is the same as mad. b. 1. Saturation: fma.f64 introduced in PTX ISA version 1. b.f64 computes the product of a and b to infinite precision and then adds c to this product. Rounding modifiers (no default): . fma. @p fma.

mad.ftz}{. When JIT-compiled for SM 2.f32). Saturation modifier: mad. Description Semantics Notes Multiplies two values and adds a third.rnd. Unlike mad.sat}. The resulting value is then rounded to double precision using the rounding mode specified by . The exception for mad.f64}. sm_1x: mad.f32 computes the product of a and b to infinite precision and then adds c to this product. mad. // .sat.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. and then writes the resulting value into a destination register. b.f64} is the same as fma. a.ftz. mad{. c.f64 computes the product of a and b to infinite precision and then adds c to this product.target sm_1x: mad.0 devices.rn. The resulting value is then rounded to single precision using the rounding mode specified by .f32 clamps the result to [0. again in infinite precision. a. c.ftz.rn.ftz}{.rz. .rnd{. mad.f32 is implemented as a fused multiply-add (i.PTX ISA Version 2.target sm_1x d.f64 d.sat}. . Note that this is different from computing the product with mul.target sm_20 d.e.{f32.f32 mad.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.0].0. b. mad.rp }. mad.rm mantissa LSB rounds towards negative infinity .f64 computes the product of a and b to infinite precision and then adds c to this product.f64 supports subnormal numbers.f64 is the same as fma.{f32.f32 mad.rm.f64.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is when c = +/-0.rn mantissa LSB rounds to nearest even . b. the treatment of subnormal inputs and output follows IEEE 754 standard. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.target sm_20: mad.rnd. 88 January 24. mad. and then the mantissa is truncated to 23 bits.rnd. fma. d = a*b + c.. mad. .rnd. Rounding modifiers (no default): . // . // .f32 flushes subnormal inputs and results to sign-preserving zero.rz mantissa LSB rounds towards zero .target sm_13 and later . In this case. For . The resulting value is then rounded to double precision using the rounding mode specified by .0f. 2010 .0 Table 53.f32 computes the product of a and b at double precision. again in infinite precision. 1. c.f32. NaN results are flushed to +0. mad.rnd = { .0. a. where the mantissa can be rounded and the exponent will be clamped. but the exponent is preserved. For . subnormal numbers are supported.f32 is identical to the result computed using separate mul and add instructions. again in infinite precision. mad.

0.f32 d.f64 instructions having no rounding modifier will map to mad.Chapter 8.f64.rz.f32 supported on all target architectures.rn. mad.f64. Legacy mad.f32.a..0 and later.c.b.. 2010 89 .rp for mad.rn. a rounding modifier is required for mad.rm. Rounding modifiers have the following target requirements: .f64. In PTX ISA versions 1. In PTX ISA versions 2.rm.rn. Target ISA Notes mad. January 24.f32 for sm_20 targets.rp for mad. a rounding modifier is required for mad..f64 requires sm_13 or later. requires sm_20 Examples @p mad. requires sm_13 .4 and later.rz. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1....

approximate division by zero creates a value of infinity (with same sign as a).rz.rz mantissa LSB rounds towards zero . a. z.rm. PTX ISA Notes div.f32 flushes subnormal inputs and results to sign-preserving zero.rp }. x.rn. b. but is not fully IEEE 754 compliant and does not support rounding modifiers. d.14159. xd.full{. computed as d = a * (1/b). zd.circum. .f32 implements a relatively fast. div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .rm.f32 div.rn.{rz.ftz.3.f64.PTX ISA Version 2.approx.rnd. div.f32 implements a fast approximation to divide.f64 requires sm_20 or later. div Syntax Floating-Point Instructions: div Divide one value by another. b.approx{. The maximum ulp error is 2 across the full range of inputs.f64 introduced in PTX ISA version 1.full. Description Semantics Notes Divides a by b.f32 and div.f32 flushes subnormal inputs and results to sign-preserving zero. div.rnd.f64 supports subnormal numbers. or . sm_1x: div. one of . 2010 .f64 requires sm_13 or later.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 requires sm_20 or later.4. Subnormal inputs and results are flushed to sign-preserving zero. .approx. b.approx.rnd is required.f32 supported on all target architectures.f32 div. div.full. d.0. the maximum ulp error is 2. For PTX ISA versions 1.rnd{. For PTX ISA version 1.rnd = { . For b in [2-126.rn.ftz. Fast.f32 and div.ftz. div. and rounding introduced in PTX ISA version 1. stores result in d.ftz}.rn.f64 defaults to div. div.4 and later. approximate single-precision divides: div. yd.ftz}.rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity . . .approx. Target ISA Notes div.full.full.f64 diam. div. Examples 90 January 24.ftz.rp}. subnormal numbers are supported.ftz.f64 d. .f32. d.f32 div. // // // // fast. a.approx.3. a. d = a / b.f32 defaults to div. b. div.0 Table 54. div. a. Explicit modifiers .f32 div. .ftz}. Fast. and div.full.approx. full-range approximation that scales operands to achieve better accuracy. y. 2126].f32 div.0 through 1.

d = |a|.ftz.f32 neg.0.f64 d.ftz. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f64 supports subnormal numbers.f32 supported on all target architectures. Subnormal numbers: sm_20: By default. a. subnormal numbers are supported. d = -a. neg{. abs.ftz. Table 56. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.0. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: abs.ftz}.f0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz}.f32 abs. Subnormal numbers: sm_20: By default. abs.f0. neg. a. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Instruction Set Table 55.f32 supported on all target architectures.Chapter 8. NaN inputs yield an unspecified NaN.f64 d.f32 x. neg. d. Negate the sign of a and store the result in d. a. abs{.f32 flushes subnormal inputs and results to sign-preserving zero. NaN inputs yield an unspecified NaN.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero. Take the absolute value of a and store the result in d.f64 supports subnormal numbers.ftz. a. abs. 2010 91 . abs. neg.f32 x. January 24. subnormal numbers are supported. neg.f64 requires sm_13 or later. sm_1x: neg. neg. d. abs.

f1.ftz.c.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d. a. (a > b) ? a : b.b. Table 58. d d d d = = = = NaN. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. sm_1x: min. subnormal numbers are supported.f64 requires sm_13 or later. a. 92 January 24.f32 max.f64 requires sm_13 or later. min.ftz. a. a.f32 flushes subnormal inputs and results to sign-preserving zero. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. max. subnormal numbers are supported. Store the minimum of a and b in d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.f64 supports subnormal numbers.f64 z. Store the maximum of a and b in d. min.f32 min. min. min{.ftz}. sm_1x: max.b.ftz.PTX ISA Version 2.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.c.f2. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. a.0. b. a.f32 max. @p min.f32 supported on all target architectures.z.f64 f0.f64 supports subnormal numbers. (a < b) ? a : b.ftz. a. max{. d. b. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. min. a.x. b. max.0.ftz}. 2010 .f32 min.0 Table 57. d d d d = = = = NaN. b. d. max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. b. max.

Instruction Set Table 59.approx and . xi. The maximum absolute error is 2-23.f32 and rcp. . d.0 -Inf -Inf +Inf +Inf +0.{rz.rn. rcp. 2010 93 .approx. a.rz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 rcp.0. For PTX ISA versions 1.3.ftz were introduced in PTX ISA version 1.rn. and rcp.rn mantissa LSB rounds to nearest even .x.0-2. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .rnd.approx.f32 flushes subnormal inputs and results to sign-preserving zero.f64 introduced in PTX ISA version 1. Examples January 24.f32 supported on all target architectures.f64 and explicit modifiers .rp }. a.x.rm mantissa LSB rounds towards negative infinity . a.rnd = { .rnd. d = 1 / a.rm.f32 rcp. d.ftz}.rn.f64 defaults to rcp.f32 defaults to rcp.0.f32. rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.4. rcp.rnd{. rcp.f64 requires sm_20 or later.approx or .rn.rn. rcp.r.0.0 through 1.f32 requires sm_20 or later.f64 requires sm_13 or later. . PTX ISA Notes rcp. .ftz.ftz.Chapter 8. rcp. rcp.rn.f32 rcp. rcp. Input -Inf -subnormal -0.4 and later.approx{.ftz.f64. rcp.rp}.approx.0 over the range 1. sm_1x: rcp.f64 supports subnormal numbers. subnormal numbers are supported. store result in d.0 +subnormal +Inf NaN Result -0.f64 ri.rz mantissa LSB rounds towards zero .approx. General rounding modifiers were added in PTX ISA version 2.f32 rcp. // fast. one of .f32 implements a fast approximation to reciprocal.f32 flushes subnormal inputs and results to sign-preserving zero. Target ISA Notes rcp. Description Semantics Notes Compute 1/a. xi.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rm.f64 d. rcp.0 +0.ftz}.rnd is required.ftz. For PTX ISA version 1.

{rz.rn mantissa LSB rounds to nearest even .rm mantissa LSB rounds towards negative infinity . 2010 .rn.ftz.f32.approx or .f32 sqrt.approx.f32 requires sm_20 or later.x.4.rnd = { .f32 and sqrt. General rounding modifiers were added in PTX ISA version 2.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is TBD.approx.f64 requires sm_13 or later.rn.rn.rnd. // IEEE 754 compliant rounding d. For PTX ISA versions 1. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 supported on all target architectures. approximate square root d.f32 flushes subnormal inputs and results to sign-preserving zero.rn.rz.0.0. Examples 94 January 24.ftz.ftz}. For PTX ISA version 1. r. one of .f64 introduced in PTX ISA version 1. sqrt.approx and .ftz}. a. sqrt. sqrt.3.rnd{.rp}.f64 d.f64.rz mantissa LSB rounds towards zero .rnd is required. sqrt. sm_1x: sqrt.approx.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . subnormal numbers are supported.0 through 1.ftz. PTX ISA Notes sqrt. r.f64 supports subnormal numbers.rn. store in d.0 -0. // IEEE 754 compliant rounding .f32 sqrt.f64 and explicit modifiers . Input -Inf -normal -subnormal -0.x. sqrt. sqrt.0 +0.f32 defaults to sqrt.0 +0. Target ISA Notes sqrt.rp }.ftz. Description Semantics Notes Compute sqrt(a).0 +subnormal +Inf NaN Result NaN NaN -0. sqrt.0 +0.PTX ISA Version 2.ftz were introduced in PTX ISA version 1.0 Table 60.f32 sqrt.f64 requires sm_20 or later. d = sqrt(a). // fast.rm. and sqrt. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. sqrt.f64 defaults to sqrt.x.rnd.approx{.approx. sqrt.approx.rn. The maximum absolute error for sqrt.f32 implements a fast approximation to square root. a. a. .4 and later.f32 sqrt.rm. sqrt. .f64 r.

subnormal numbers are supported. rsqrt.approx.f64 isr.f32 flushes subnormal inputs and results to sign-preserving zero.f32 rsqrt. rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. For PTX ISA versions 1.4 over the range 1.f32 is 2-22.f32 and rsqrt.f32.approx modifier is required.f32 rsqrt.approx. Instruction Set Table 61. d.0 through 1.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 95 . Target ISA Notes Examples rsqrt.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt. Subnormal numbers: sm_20: By default. d = 1/sqrt(a).f32 supported on all target architectures. Note that rsqrt.approx and . PTX ISA Notes rsqrt. rsqrt.f64 requires sm_13 or later.f64 is TBD. store the result in d. Compute 1/sqrt(a).ftz. The maximum absolute error for rsqrt.4 and later. Input -Inf -normal -subnormal -0. a. rsqrt. rsqrt.approx.f32 defaults to rsqrt.approx.ftz.f64 is emulated in software and are relatively slow. X. Explicit modifiers .approx. the .approx{.f64 d.0-4.Chapter 8.approx implements an approximation to the reciprocal square root. rsqrt. x.0.0 NaN The maximum absolute error for rsqrt.3. a.f64 defaults to rsqrt.0 +0.f64.f64 were introduced in PTX ISA version 1.approx. and rsqrt. January 24. For PTX ISA version 1. ISR.0.4.ftz.ftz were introduced in PTX ISA version 1.f64 supports subnormal numbers. sm_1x: rsqrt.ftz}.

Explicit modifiers .0 through 1.ftz.f32 introduced in PTX ISA version 1.f32 d.approx and . Find the sine of the angle a (in radians).ftz}.ftz.approx.0 NaN NaN The maximum absolute error is 2-20.0 -0.0. sm_1x: Subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.3.f32 sa.approx{. a.PTX ISA Version 2.0 +0. For PTX ISA version 1.approx.0 +0.4 and later.ftz introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. d = sin(a).f32 implements a fast approximation to sine.f32 defaults to sin. 2010 . 96 January 24.4.0 +subnormal +Inf NaN Result NaN -0. PTX ISA Notes sin.ftz. sin. sin. sin. For PTX ISA versions 1.approx modifier is required.0 +0.f32. Subnormal numbers: sm_20: By default.9 in quadrant 00. sin. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. Target ISA Notes Examples Supported on all target architectures. a.approx. sin. the .0 Table 62. Input -Inf -subnormal -0.

cos.Chapter 8. For PTX ISA versions 1.f32 flushes subnormal inputs and results to sign-preserving zero.9 in quadrant 00.0 +1.4 and later.f32 defaults to cos.approx.0 through 1. sm_1x: Subnormal inputs and results to sign-preserving zero.ftz. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. Input -Inf -subnormal -0. a. Find the cosine of the angle a (in radians).ftz introduced in PTX ISA version 1. Explicit modifiers .f32 introduced in PTX ISA version 1.0 NaN NaN The maximum absolute error is 2-20.ftz.3.approx. Target ISA Notes Examples Supported on all target architectures. d = cos(a).approx and .0 +1.0 +subnormal +Inf NaN Result NaN +1.4. Instruction Set Table 63.ftz. the . cos.0 +0.f32 implements a fast approximation to cosine. 2010 97 . subnormal numbers are supported.approx modifier is required.ftz}. cos.0 +1.f32 ca. January 24. Subnormal numbers: sm_20: By default. For PTX ISA version 1.approx{. PTX ISA Notes cos. a.0. cos.approx.f32.f32 d. cos.

d = log(a) / log(2). 98 January 24. lg2. Explicit modifiers .approx modifier is required. lg2.0.f32 la. PTX ISA Notes lg2.f32.approx{. lg2. subnormal numbers are supported. a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.f32 Determine the log2 of a.f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default. Target ISA Notes Examples Supported on all target architectures.3.ftz.ftz.PTX ISA Version 2. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz introduced in PTX ISA version 1.approx. The maximum absolute error is 2-22.f32 flushes subnormal inputs and results to sign-preserving zero.approx and .f32 implements a fast approximation to log2(a).approx. Input -Inf -subnormal -0. For PTX ISA version 1.ftz.ftz}.0 Table 64. lg2.approx.0 through 1.6 for mantissa. For PTX ISA versions 1. the .0 +0.4. 2010 . a. sm_1x: Subnormal inputs and results to sign-preserving zero. lg2.f32 defaults to lg2.4 and later.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

The comparison operator is a suffix on the instruction. To aid comparison operations in the presence of NaN values. Integer Notes Floating Point Notes The ordered comparisons are eq. le.s64. bit-size comparisons are eq and ne. respectively. leu. le. ne. nan The Boolean operator BoolOp(A.ftz}. the result is false. . gtu. ne. .u16. and nan returns true if either operand is NaN. c).ftz}. num. setp. For unsigned values.B) is one of: and. num returns true if both operands are numeric values (not NaN).dtype. p = BoolOp(t.pred variables. ls.eq.type setp. and (optionally) combine this result with a predicate value by applying a Boolean operator.i.0 Table 67. p[|q]. This result is written to the first destination operand.s32. p. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. then these comparisons have the same result as their ordered counterparts. 2010 . . unordered versions are included: equ. . Semantics t = (a CmpOp b) ? 1 : 0. and higher-or-same may be used instead of lt. lt. .ftz applies only to . sm_1x: setp.f64 source type requires sm_13 or later.and. Subnormal numbers: sm_20: By default. a. hi. . neu.type . lt. b. c). gt. ge.CmpOp. the comparison operators lo. ge. lo. lt.CmpOp{. The signed and unsigned comparison operators are eq. ltu.f32. ls. . or.s32 setp. Applies to all numeric types. {!}c. Modifier . If either operand is NaN.f32 comparisons.PTX ISA Version 2. a. gt. gtu.b32. then the result of these comparisons is true. ltu. leu. xor. hs equ. setp with . and hs for lower. . loweror-same.type = { . b.f32 flushes subnormal inputs to sign-preserving zero. ge. geu.a. The destinations p and q must be .s16.u32. A related value computed using the complement of the compare result is written to the second destination operand.lt.f64 }. neu. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Description Compares two values and combines the result with another predicate value by applying a Boolean operator.0. If both operands are numeric values (not NaN). setp.f64 supports subnormal numbers. and can be one of: eq.n. gt.ftz. If either operand is NaN. .dtype.b16. le. geu. ne.f32 flushes subnormal inputs to sign-preserving zero. The untyped. le. higher. @q setp.b.u32 p|q.u64.b64. 102 January 24. setp. . p[|q]. hi. subnormal numbers are supported.BoolOp{. q = BoolOp(!t.r. ge. gt.dtype.

a.b16. . b. The selected input is copied to the output without modification. a is stored in d. . .f64 requires sm_13 or later. . . y. b otherwise. . subnormal numbers are supported. f0. .s32 selp. b.Chapter 8. and b must be of the same type. slct. . a. 2010 103 .u64. a.f32. d.s32 slct{. . . selp.b64. Subnormal numbers: sm_20: By default. slct. and operand a is selected.b64.ftz}. d = (c >= 0) ? a : b.f32 r0. If c is True.f32 flushes subnormal values of operand c to sign-preserving zero.f64 requires sm_13 or later. a. the comparison is unordered and operand b is selected. and operand a is selected. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.f32. . slct.g.u16. Description Conditional selection. Operands d. . Introduced in PTX ISA version 1. Instruction Set Table 68.f32 flushes subnormal values of operand c to sign-preserving zero. If operand c is NaN. operand c must match the second instruction type. slct. otherwise b is stored in d. Operands d.xp. sm_1x: slct. B. . a. and b are treated as a bitsize type of the same width as the first instruction type. .f64 }. Modifier .b32. selp.dtype.s32 x. If c ≥ 0.u64. selp Syntax Comparison and Selection Instructions: selp Select between source operands.dtype.s64. .dtype.0. based on the value of the predicate source operand.u64. . negative zero equals zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.u32. z.s16.s32. c. d = (c == 1) ? a : b. Operand c is a predicate. .u16. . a is stored in d.s16.x.dtype = { .u32.f32 d.t. fval. based on the sign of the third operand. Semantics Floating Point Notes January 24.p. Table 69. .f32 comparisons. .s32.u32. b.0.b16. slct Syntax Comparison and Selection Instructions: slct Select one source operand. For .r.f32 A.ftz applies only to . C. slct. c. .f32 comparisons.b32. . val.dtype.type d. @q selp.type = { .f64 }.ftz.s64.ftz. c.

Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. provided the operands are of the same size. xor. Instructions and. and not also operate on predicates. This permits bit-wise operations on floating point values without having to define a union to access the bits. performing bit-wise operations on operands of any type. 2010 .0 8. or.PTX ISA Version 2.7.4. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.

. The size of the operands must match. 2010 105 . Supported on all target architectures.b32. or Syntax Logic and Shift Instructions: or Bitwise OR.q. d = a & b. d = a | b. Introduced in PTX ISA version 1.b32 and.q.0.0.fpvalue. Instruction Set Table 70.b32 mask mask.pred. Allowed types include predicate registers.0x00010001 or.type = { . but not necessarily the type. or.b32. Introduced in PTX ISA version 1.pred. .type d.b64 }. and. .pred p. January 24. Allowed types include predicate registers. The size of the operands must match. or. and Syntax Logic and Shift Instructions: and Bitwise AND. but not necessarily the type. Table 71. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. .r.0x80000000.type = { .b64 }. b.r.b16. a. b.Chapter 8. sign.b16. . . .type d. and.b32 x. a. Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.

b32.r. d. The size of the operands must match. not.0x0001. a. one’s complement.type = { .x. b. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. cnot. xor.b16. Introduced in PTX ISA version 1. not. The size of the operands must match. Table 74. d = (a==0) ? 1 : 0. but not necessarily the type.q. 2010 . .type d.b64 }. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Introduced in PTX ISA version 1. Supported on all target architectures.pred.b16 d.type d.type = { .PTX ISA Version 2. d = a ^ b. d = ~a.b16. . but not necessarily the type. .q.b32 xor.b16.b64 }. . Allowed types include predicate registers. The size of the operands must match.type d. 106 January 24.type = { . . Supported on all target architectures. . .0 Table 72. .b64 }.pred p.a.b32.b32 d. Table 73.0.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.0. a. not. Introduced in PTX ISA version 1. Supported on all target architectures. .b32 mask.mask.pred.0. Allowed types include predicates. but not necessarily the type. cnot. . not Syntax Logic and Shift Instructions: not Bitwise negation. a. xor. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.

b16 c.1. .u32. The sizes of the destination and first source operand must match. regardless of the instruction type.i.a. but not necessarily the type.b32. zero-fill on right. d = a >> b. . Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.type = { . a.b16. . PTX ISA Notes Target ISA Notes Examples January 24.type d. a. . The sizes of the destination and first source operand must match. shr Syntax Logic and Shift Instructions: shr Shift bits right.u16. Introduced in PTX ISA version 1. sign or zero fill on left. d = a << b. Shift amounts greater than the register width N are clamped to N. .2. i.0. regardless of the instruction type. b. Supported on all target architectures. Instruction Set Table 75.s16.b64. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. shl Syntax Logic and Shift Instructions: shl Shift bits left. Bit-size types are included for symmetry with SHL. shr. Signed shifts fill with the sign bit.j. .b16.type d. but not necessarily the type. k.Chapter 8. . PTX ISA Notes Target ISA Notes Examples Table 76. The b operand must be a 32-bit value. shl. . Supported on all target architectures. The b operand must be a 32-bit value.2.s32.b64 }. b.a. .s32 shr.i. shl. . shr. unsigned and untyped shifts fill with 0. 2010 107 .type = { . Introduced in PTX ISA version 1.b32 q.s64 }.u16 shr.0.b32. .u64. . Shift amounts greater than the register width N are clamped to N.

and from state space to state space. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. ld.5. st. prefetchu isspacep cvta cvt 108 January 24.0 8. suld. ldu.PTX ISA Version 2. possibly converting it from one format to another.7. mov. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. 2010 . and st operate on both scalar and vector types. The cvta instruction converts addresses between generic and global. and sust support optional cache operations. Instructions ld. Data Movement and Conversion Instructions These instructions copy data from place to place. local. or shared state spaces.

The ld.lu load last use operation. fetch again). January 24. and cache only in the L2 cache. Cache Operators PTX 2.cg Cache at global level (cache in L2 and below. likely to be accessed once.cs. Global data is coherent at the L2 level. and a second thread loads that address via a second L1 cache with ld.5.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. if the line is fully covered. bypassing the L1 cache.ca loads cached in L1.lu operation. The ld.cg to cache loads only globally. Use ld. As a result of this request. .ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. The compiler / programmer may use ld. likely to be accessed again. When ld. For sm_20 and later. rather than the data stored by the first thread. to allow the thread program to poll a SysMem location written by the CPU.cs) on global addresses. not L1). when applied to a local address. but multiple L1 caches are not coherent for global data. .lu instruction performs a load cached streaming operation (ld. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.ca. If one thread stores to global memory via one L1 cache. Operator . The driver must invalidate global L1 cache lines between dependent grids of parallel threads.cv to a frame buffer DRAM address is the same as ld. A ld. The ld. the second thread may get stale L1 cache data. The cache operators require a target architecture of sm_20 or later.lu Last use.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice.1. any existing cache lines that match the requested address in L1 will be evicted. the cache operators have the following definitions and behavior.cs Cache streaming.Chapter 8. Instruction Set 8. The ld. Table 77. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.7.0 introduces optional cache operators on load and store instructions. . The default load instruction cache operation is ld. invalidates (discards) the local L1 line following the load. evict-first.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. . it performs the ld.cs is applied to a Local window address. 2010 109 .ca.cv Cache as volatile (consider cached system memory lines stale.

ca. 2010 .cs Cache streaming. to allow a CPU program to poll a SysMem location written by the GPU with st. st. in which case st. If one thread stores to global memory. .cg to local memory uses the L1 cache.PTX ISA Version 2.cg to cache global store data only globally. and cache only in the L2 cache. Use st.0 Table 78. Global stores bypass L1. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. Addresses not in System Memory use normal write-back. The st. and marks local L1 lines evict-first. the second thread may get a hit on stale L1 cache data. Future GPUs may have globally-coherent L1 caches.ca loads. but st.wt. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. and a second thread in a different SM later loads from that address via a different L1 cache with ld. likely to be accessed once.wt store write-through operation applied to a global System Memory address writes through the L2 cache. which writes back cache lines of coherent cache levels with normal eviction policy. not L1).wb could write-back global store data from L1. and discard any L1 lines that match. . In sm_20. bypassing the L1 cache.wb for global data. 110 January 24.cg Cache at global level (cache in L2 and below.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. .wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.wb. bypassing its L1 cache. The st. The default store instruction cache operation is st.wt Cache write-through (to system memory). The driver must invalidate global L1 cache lines between dependent grids of thread arrays. rather than get the data from L2 or memory stored by the first thread. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.cg is the same as st. regardless of the cache operation. Operator . However.

avar. label.u16 mov.e. d.u32. . or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. or shared state space may be taken directly using the cvta instruction. . i.a. myFunc.0. Semantics d = a. .u32 d. Note that if the address of a device function parameter is moved to a register. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. Introduced in PTX ISA version 1. ptr. the generic address of a variable declared in global. mov. variable in an addressable memory space.u16. . Description . . mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.u32 mov.type = { .v. a. local. .s32.type d.u64.global. special register.0.type mov. d. A. the parameter will be copied onto the stack and the address will be in the local state space.f32 mov. 2010 111 .f32.. Take the non-generic address of a variable in global. . Write register d with the value of a. // address is non-generic.const. immediate. Operand a may be a register.s64.e. k.Chapter 8. within the variable’s declared state space Notes Although only predicate and bit-size types are required. sreg. label. . local. . mov places the non-generic address of the variable (i. alternately. d = sreg.f32 mov.f64 requires sm_13 or later. A[5]. mov.shared state spaces.b32. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. addr. The generic address of a variable in global.s16. or shared state space. or function name. .b64.type mov. the address of the variable in its state space) into the destination register.pred. d = &label. d.f64 }.type mov.local.1.u32 mov. and . Instruction Set Table 79. u.b16.. local. ptr. For variables declared in . // get address of variable // get address of label or function . d = &avar. . .

d. a[8. a[32.{a. {r.PTX ISA Version 2. d.z.b64 }.z..b32 // pack four 16-bit elements into .x.z << 32) | (a..b64 { d.type = { .y << 8) d = a. d.b.g. Supported on all target architectures.. a[24.. {lo.b32 { d..x | (a.b have type .b32 mov.b32 // pack two 16-bit elements into .x.b64 112 January 24.7]. // // // // a.b32 mov.z << 16) | (a.w } = { a[0.b32 %r1.{x.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.. d.hi are . d. a[16.b16 { d.b16.15].y.x. .w << 48) d = a.b}.0.b64 mov.type d.63] } // unpack 16-bit elements from .y << 8) | (a. or write vector register d with the unpacked values from scalar register a. a[32.31].47]. d.y.a have type . .x | (a.b8 r.w << 24) d = a. %r1.w } = { a[0. d.u32 x. a[16.u16 %x is a double..0 Table 80. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.y << 32) // pack two 8-bit elements into ..31].. mov. For bit-size types.. a[8. Semantics d = a.15].23]. lo.b64 { d.y } = { a[0..x | (a. 2010 .y.y << 16) d = a..y } = { a[0.z.u8 // unpack 32-bit elements from .a}.w have type . a[16.15].b32 { d.g.x. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).y. .b64 // pack two 32-bit elements into .31] } // unpack 16-bit elements from .b32.w}.y } = { a[0.x | (a.31] } // unpack 8-bit elements from .%r1.b16 // pack four 8-bit elements into .15] } // unpack 8-bit elements from .x | (a. a. mov.z. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.. d.x. %x.. a[48.7].y << 16) | (a. Description Write scalar register d with the packed value of vector register a. d.b.hi}.

. d. d. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.volatile introduced in PTX ISA version 1.type d. ld introduced in PTX ISA version 1.param.f32. .0.b16.b8. The . . an integer or bit-size type register reg containing a byte address. . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.s32.ss}{.const. ld.global. . . [a]. The address size may be either 32-bit or 64-bit.f16 data may be loaded using ld. [a].s64. an address maps to the corresponding location in local or shared memory.ss}.lu.volatile. and truncated if the register width exceeds the state space address width for the target architecture. In generic addressing. for example.global and . . .v4 }. If no state space is given. *(immAddr).u64.cop}. to enforce sequential consistency between threads accessing shared memory. . 32-bit). .cs. an address maps to global memory unless it falls within the local memory window or the shared memory window. .const space suffix may have an optional bank number to indicate constant banks other than bank zero. . .shared spaces to inhibit optimization of references to volatile memory.cg. . Generic addressing may be used with ld. *(a+immOff).u8. The value loaded is sign-extended to the destination register width for signed integers. Cache operations are not permitted with ld. the resulting behavior is undefined. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . .s16.ss}. [a].volatile. . ld. A destination register wider than the specified type may be used. Addresses are zero-extended to the specified width as needed.cop}.u32. .b32.volatile{.vec. perform the load using generic addressing. This may be used. Generic addressing and cache operations introduced in PTX ISA 2. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. . d.v2.b64. If an address is not properly aligned.s8. .type ld{. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f32 or . Within these windows.volatile{. .reg state space.e. ld{. *a. Instruction Set Table 81. and is zeroextended to the destination register width for unsigned and bit-size types.volatile may be used with . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.1. Description Load register variable d from the location specified by the source address operand a in specified state space.local.0.e. The address must be naturally aligned to a multiple of the access size.cop = { . .cv }.Chapter 8..type ld. or [immAddr] an immediate absolute byte address (unsigned.type = { .u16. or the instruction may fault. . [a].b16. 32-bit).f64 }. i.ss}{. PTX ISA Notes January 24. Semantics d d d d = = = = a.f64 using cvt.vec. . . and then converted to .ca.vec = { . 2010 113 . i.shared }.type .ss = { .

local.f16 d.[p].f32 ld. x.b32 ld.shared. Q. // negative offset %r. // load .[p+4].PTX ISA Version 2. // immediate address %r.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. %r.b64 ld. // access incomplete array x.0 Target ISA Notes ld.f32.f64 requires sm_13 or later.s32 ld.b16 cvt.[fs].const[4]. ld.[p+-8]. Cache operations require sm_20 or later. 2010 .const.local.[a].b32 ld.b32 ld.global. d.%r.[240].global. Generic addressing requires sm_20 or later.v4.[buffer+64].

. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. . 2010 115 . The addressable operand a is one of: [avar] the name of an addressable variable var.u64.u8. . The data at the specified address must be read-only. ldu{. [a].s32. Instruction Set Table 82. [a]. If no state space is given.v2. .f32 Q.global. . A destination register wider than the specified type may be used. . For ldu.v4.f32 or . Addresses are zero-extended to the specified width as needed. and truncated if the register width exceeds the state space address width for the target architecture. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. A register containing an address may be declared as a bit-size type or integer type. Within these windows. ldu. perform the load using generic addressing. // load from address // vec load from address . .f64 requires sm_13 or later. [areg] a register reg containing a byte address. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. Semantics d d d d = = = = a.f32 d.vec.v4 }.b32.e.s64. The address must be naturally aligned to a multiple of the access size. an address maps to the corresponding location in local or shared memory. // state space . *(a+immOff).s16.u32.s8. *a.global. 32-bit). ldu. .b64. . an address maps to global memory unless it falls within the local memory window or the shared memory window.global }.f64 using cvt. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. and is zeroextended to the destination register width for unsigned and bit-size types. .[p+4]. i.f64 }. where the address is guaranteed to be the same across all threads in the warp. i.ss}. . If an address is not properly aligned. .[a]. ldu. In generic addressing.f32.type = { . The value loaded is sign-extended to the destination register width for signed integers. PTX ISA Notes Target ISA Notes Examples January 24.ss}.type ldu{.f16 data may be loaded using ldu. .e. or the instruction may fault.b16. The address size may be either 32-bit or 64-bit. Introduced in PTX ISA version 2. *(immAddr). .b32 d. 32-bit).vec = { . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . only generic addresses that map to global memory are legal.global.b16. . the resulting behavior is undefined. d.Chapter 8. ldu. .reg state space.b8.0.[p].. the access may proceed by silently masking off low-order address bits to achieve proper rounding. or [immAddr] an immediate absolute byte address (unsigned.ss = { .u16. and then converted to .type d.

PTX ISA Version 2. If no state space is given.0. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . 2010 . // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. Within these windows.b64. or the instruction may fault. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. . . { . Generic addressing requires sm_20 or later. 32-bit). st. { .e.volatile.ss}{. . . The address size may be either 32-bit or 64-bit. for example.cg. .. PTX ISA Notes Target ISA Notes 116 January 24.global and . b.ss}. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. .ss}. st introduced in PTX ISA version 1. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. . This may be used.type [a]. or [immAddr] an immediate absolute byte address (unsigned.1. Semantics d = a.b16.e. [a].s8.vec . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . st. Generic addressing and cache operations introduced in PTX ISA 2. b.v2.cop}. . b. an address maps to the corresponding location in local or shared memory.vec. [a]. Cache operations require sm_20 or later. . .0 Table 83. *(d+immOffset) = a.type . i. the resulting behavior is undefined.cop}.u8.type st{.f16 data resulting from a cvt instruction may be stored using st.volatile may be used with .u32. an address maps to global memory unless it falls within the local memory window or the shared memory window. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . .u16. The lower n bits corresponding to the instruction-type width are stored to memory. to enforce sequential consistency between threads accessing shared memory. If an address is not properly aligned.reg state space.b16. *d = a.u64. i.f32.type st.type = = = = {.global. Addresses are zero-extended to the specified width as needed.f64 }.0. In generic addressing.local.cop . . .volatile{. [a].v4 }. . st. *(immAddr) = a. A source register wider than the specified type may be used.ss .s16. perform the store using generic addressing. . Cache operations are not permitted with st. . Generic addressing may be used with st. The address must be naturally aligned to a multiple of the access size.cs.volatile{.wt }. .volatile. .vec. st{.wb.volatile introduced in PTX ISA version 1.f64 requires sm_13 or later.shared }.s32.b32.b8. b. and truncated if the register width exceeds the state space address width for the target architecture. { .s64. 32-bit).ss}{. an integer or bit-size type register reg containing a byte address.shared spaces to inhibit optimization of references to volatile memory.

f32 st. // immediate address %r.s32 cvt.f32 st.a. [q+-8].b32 st. [p].a. // negative offset [100]. // %r is 32-bit register // store lower 16 bits January 24.b16 [a].%r.b32 st.local.b. Instruction Set Examples st.local.%r.s32 st.global. 2010 117 .f16.local.r7.Q.Chapter 8. [fs].global. [q+4].v4.

prefetchu Prefetch line containing generic address at specified level of memory hierarchy. 118 January 24.0 Table 84.L1 [addr]. If no state space is given. // prefetch to data cache // prefetch to uniform cache . [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. or [immAddr] an immediate absolute byte address (unsigned.0. 32-bit). A prefetch to a shared memory location performs no operation.L1. [a].level prefetchu. .global. prefetch and prefetchu require sm_20 or later.PTX ISA Version 2. in specified state space. The address size may be either 32-bit or 64-bit. . 2010 . the prefetch uses generic addressing.L1 [ptr]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Within these windows. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. . 32-bit). prefetch. Addresses are zero-extended to the specified width as needed. and truncated if the register width exceeds the state space address width for the target architecture.L1 [a]. and no operation occurs if the address maps to a local or shared memory location.space = { .level = { . A prefetch into the uniform cache requires a generic address. prefetchu.global.local }.space}. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. In generic addressing. a register reg containing a byte address. an address maps to global memory unless it falls within the local memory window or the shared memory window. an address maps to the corresponding location in local or shared memory. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.e. prefetch{.L2 }. i.

the generic address of the variable may be taken using cvta. The destination register must be of type .Chapter 8. The source and destination addresses must be the same size.u32. . Description Convert a global.u32 p. The source address operand must be a register of type .u64 or cvt. // result is .global. PTX ISA Notes Target ISA Notes Examples Table 86. local.local. .u64. For variables declared in global. or shared state space. cvta.lptr. local. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. sptr. cvta requires sm_20 or later.u64 }. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. // convert to generic address // get generic address of var // convert generic address to global. Take the generic address of a variable declared in global.local isspacep.space = { . local.u64.space = { . a.pred.0. . gptr. Use cvt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // get generic address of svar cvta.to. islcl.shared }. p. cvta.space p. or vice-versa. Instruction Set Table 85.size = { .size cvta. a.local.global. . isspacep. isshrd. or shared state space. or shared address.space.u32 p.u32.pred . or shared address cvta.local. local. p. or shared state space to generic. a. A program may use isspacep to guard against such incorrect behavior. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. isspacep.u32 or .shared isglbl.global. or shared address to a generic address. Introduced in PTX ISA version 2.u32 gptr.shared }.to. lptr. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.size p. svar. . When converting a generic address into a global. or vice-versa.0. // local.size .global isspacep.space. 2010 119 . var. cvta. isspacep requires sm_20 or later. January 24.u32 to truncate or zero-extend addresses.shared. local.genptr.space. .

atype cvt{. . .sat}. . a.e. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.rni round to nearest integer. the . ..f16.e.atype d.ftz modifier may be specified in these cases for clarity.f64 }.ftz}{.rmi round to nearest integer in direction of negative infinity .dtype = .sat}.0 Table 87.PTX ISA Version 2.rni. choosing even integer if source is equidistant between two integers. Description Semantics Integer Notes Convert between different types and sizes.u32. cvt{.ftz.ftz.s64. d.rm.ftz. . .4 and earlier. i. .ftz. .rn. Note that saturation applies to both signed and unsigned integer types.rz. a. .dtype. subnormal inputs are flushed to signpreserving zero.irnd}{. subnormal numbers are supported.rzi round to nearest integer in the direction of zero .f32.sat is redundant.u16. Integer rounding is illegal in all other instances.s32.irnd = { . // integer rounding // fp rounding .dtype. .dtype.s8.f32. .sat For integer destination types.rp }. The optional . Saturation modifier: . Integer rounding modifiers: . sm_1x: For cvt. i. For cvt. subnormal inputs are flushed to signpreserving zero. .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.dtype. . Note: In PTX ISA versions 1.rzi. the result is clamped to the destination range by default.frnd = { .f32 float-tofloat conversions with integer rounding.frnd}{. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. 2010 .rmi. and for same-size float-tofloat conversions where the value is rounded to an integer..s16. .sat limits the result to MININT. For float-to-integer conversions. .ftz}{. The compiler will preserve this behavior for legacy PTX code. .u64.f32 float-tofloat conversions with integer rounding.f32.rpi }. Integer rounding is required for float-to-integer conversions.f32 float-to-integer conversions and cvt. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. d = convert(a).f32 float-to-integer conversions and cvt. . .MAXINT for the size of the operation. .atype = { . . . 120 January 24.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.u8.

ftz modifier may be specified in these cases for clarity. // note . Applies to .f16.f32 x.f64. Saturation modifier: .4 or earlier.ftz behavior for sm_1x targets January 24.f16.rm mantissa LSB rounds towards negative infinity . The compiler will preserve this behavior for legacy PTX code. stored in floating-point format.i. .sat limits the result to the range [0. Specifically. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f16.f32.0]. // round to nearest int. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. and cvt.rz mantissa LSB rounds towards zero .f64 requires sm_13 or later. and for integer-to-float conversions. 2010 121 .f32. Floating-point rounding is illegal in all other instances. Introduced in PTX ISA version 1.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. The optional .Chapter 8. cvt.f64 types.f32. Floating-point rounding modifiers: . // float-to-int saturates by default cvt. .f32 x. result is fp cvt.0. Subnormal numbers: sm_20: By default.f32. The result is an integral value.f32.f32 instructions.y. if the PTX . cvt. cvt. 1. Modifier .s32.0. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .rni.s32 f. and .y.version is 1. NaN results are flushed to positive zero.f32. cvt to or from . Note: In PTX ISA versions 1.r. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. subnormal numbers are supported.sat For floating-point destination types. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). The operands must be of the same size.f32.4 and earlier.f64 j.rn mantissa LSB rounds to nearest even .

texture and sampler information each have their own handle.6. div.width. In the independent mode. . r3. and surfaces.v4.r3. with the restriction that they correspond 1-to-1 with the 128 possible textures.global .PTX ISA Version 2. and surface descriptors. samplers.param . The advantage of independent mode is that textures and samplers can be mixed and matched. . sampler.target texmode_independent . allowing them to be defined separately and combined at the site of usage in the program. The texturing mode is selected using .f32. 122 January 24. but the number of samplers is greatly restricted to 16. add.0 8. sampler.texref handle.f32 {r1.f2}]. sampler.r2. and surface descriptors. . cvt.r4}. Module-scope and per-entry scope definitions of texture.f32.f32 r1.height. add. r3. [tex1]. The advantage of unified mode is that it allows 128 samplers. A PTX module may declare only one texturing mode. r5.7.texref tex1 ) { txq. the file is assumed to use unified mode. [tex1.entry compute_power ( . In the unified mode.b32 r5.b32 r6. r5..samplerref tsamp1 = { addr_mode_0 filter_mode }.f32 r1. {f1. r2.target options ‘texmode_unified’ and ‘texmode_independent’.. r1. // get tex1’s txq.f32 r3. r5. Ability to query fields within texture. [tex1]. Texture and Surface Instructions This section describes PTX instructions for accessing textures. If no texturing mode is declared.u32 r5. Texturing modes For working with textures and samplers. } = clamp_to_border. sampler. // get tex1’s tex.u32 r5. and surface descriptors: • • • Static initialization of texture.2d. add. Example: calculate an element’s power contribution as element’s power/total number of elements. 2010 . texture and sampler information is accessed through a single . PTX has two modes of operation. r4. mul.f32 r1. r6. r1. r1. PTX supports the following operations on texture. and surface descriptors. = nearest width height tsamp1.

. .u32. If no sampler is specified.s32. .r3. i.v4 coordinate vectors are allowed for any geometry. c]. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. or the instruction may fault.0.3d }.f2.5. . //Example of unified mode texturing tex. [tex_a. [tex_a. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.dtype = { .r2. {f1}]. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom. with the extra elements being ignored.r4}.v4.v4. {f1. An optional texture sampler b may be specified. .s32.geom. [a.e. where the fourth element is ignored. .r4}. the sampler behavior is a property of the named texture. Notes For compatibility with prior versions of PTX.f32 }.1d. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.dtype.f32 }. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. the square brackets are not required and . Supported on all target architectures. 2010 123 .2d. sampler_x. the resulting behavior is undefined.s32. [a. The instruction always returns a four-element vector of 32-bit values. If an address is not properly aligned.f3. A texture base address is assumed to be aligned to a 16-byte address.r3.btype tex. // Example of independent mode texturing tex. is a two-element vector for 2d textures.. d.dtype.btype d. Description Texture lookup using a texture coordinate vector.3d.geom = { .btype = { .s32.f4}].v4. tex txq suld sust sured suq Table 88. Instruction Set These instructions provide access to texture and surface memory.v4. tex.r2.f32 {r1. PTX ISA Notes Target ISA Notes Examples January 24. b.Chapter 8.1d. // explicit sampler . Unified mode texturing introduced in PTX ISA version 1. Operand c is a scalar or singleton tuple for 1d textures. c]. and is a four-element vector for 3d textures.s32 {r1.

addr_mode_1 . // unified mode // independent mode 124 January 24. .b32 d.b32 %r1. In unified mode. Operand a is a .depth .width. mirror. clamp_to_edge. addr_mode_1. clamp_ogl. txq. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.addr_mode_0.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).b32 %r1.squery = { . Supported on all target architectures.addr_mode_0 .addr_mode_0.height . Integer from enum { nearest.tquery. Description Query an attribute of a texture or sampler.tquery = { . d.PTX ISA Version 2. .0 Table 89. [a].b32 %r1.height.normalized_coords . linear } Integer from enum { wrap. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.depth. 2010 .squery.texref or . [tex_A]. . [a].filter_mode . [tex_A].width. txq. . // texture attributes // sampler attributes . txq.filter_mode.width . and in independent mode sampler attributes are accessed via a separate samplerref argument. txq. sampler attributes are also accessed via a texref argument. [smpl_B].filter_mode. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.b32 txq. Query: .samplerref variable. addr_mode_2 }.5.normalized_coords }. .

additional clamp modifiers. and the size of the data transfer matches the size of destination operand d.p . . then . // for suld.cg. .b32. b]. then .b64 }. Operand a is a . the resulting behavior is undefined.f32. // cache operation none.clamp . if the surface format contains SINT data. . suld. The . is a two-element vector for 2d surfaces.5. the access may proceed by silently masking off low-order address bits to achieve proper rounding.3d }.b.dtype . 2010 125 .f32 is returned. A surface base address is assumed to be aligned to a 16-byte address.v4. SNORM.u32 is returned.ca. suld.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.1d. Cache operations require sm_20 or later.trap introduced in PTX ISA version 1. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.trap suld. or the instruction may fault.y. and is a four-element vector for 3d surfaces. b].v2.u32.cop}. // unformatted d.b . if the surface format contains UINT data.b32.clamp.cv }.b64. suld.. suld.3d.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R.trap.b32.2d. sm_1x targets support only the .b. . .p is currently unimplemented. . the surface sample elements are converted to .geom . . .dtype.p.vec. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.f4}. [a. and cache operations introduced in PTX ISA version 2.clamp . or FLOAT data. Description Load from surface memory using a surface coordinate vector.clamp suld. Instruction Set Table 90. // for suld.cs. If the destination base type is .s32.b supported on all target architectures. // formatted . Operand b is a scalar or singleton tuple for 1d surfaces.3d requires sm_20 or later. .u32. .surfref variable.cop}.b.0. {f1.clamp = = = = = = { { { { { { d. The lowest dimension coordinate represents a sample offset rather than a byte offset.vec . . . and A components of the surface format. suld. . suld.Chapter 8.cop . i. {x.zero }.b16. If an address is not properly aligned. suld.z.clamp field specifies how to handle out-of-bounds addresses: . Coordinate elements are of type .trap {r1. .v4. .p. [surf_B.trap clamping modifier. [a.s32.b performs an unformatted load of binary data. then .geom{. {x}]. If the destination type is .w}]. suld Syntax Texture and Surface Instructions: suld Load from surface memory. Target ISA Notes Examples January 24. where the fourth element is ignored. G.f2.b8 . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. . .dtype.s32.p requires sm_20 or later.e. suld.f3.1d.u32. . [surf_A.r2}.v4 }.p. or . .v2.f32.trap .s32.f32 }. size and type conversion is performed as needed to convert from the surface sample format to the destination type.geom{.s32 is returned. suld. Destination vector elements corresponding to components that do not appear in the surface format are not written.f32 based on the surface format as follows: If the surface format contains UNORM.dtype . B. or .

b32. A surface base address is assumed to be aligned to a 16-byte address.clamp .PTX ISA Version 2.5.3d requires sm_20 or later. .ctype. sust. and A surface components.3d.trap clamping modifier. {r1. .0. [surf_B. {x}]. The size of the data transfer matches the size of source operand c. These elements are written to the corresponding surface sample components.y. // unformatted // formatted . ..r2}.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.f32.trap introduced in PTX ISA version 1. then .f2. Coordinate elements are of type .f32 }. sust.geom{.geom{. then . .u32 is assumed.b32.s32.0 Table 91.clamp . {x.geom . {f1. and cache operations introduced in PTX ISA version 2. b]. . is a two-element vector for 2d surfaces. . The source vector elements are interpreted left-to-right as R.v4 }.b8 . . i.u32. if the surface format contains UINT data.s32 is assumed. sust.clamp sust.{u32. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. or .p. .cop .cop}.cg.b performs an unformatted store of binary data.clamp. // for sust.b supported on all target architectures.cop}. . 2010 .clamp = = = = = = { { { { { { [a.w}]. . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.surfref variable.trap [surf_A.z.s32.vec.3d }.f4}.trap. . G.e. The source data is then converted from this type to the surface sample format. . sust.v2.ctype . .p. where the fourth element is ignored. sust.u32. Source elements that do not occur in the surface sample are ignored.vec . or FLOAT data.clamp field specifies how to handle out-of-bounds addresses: .1d.zero }. c. . size and type conversions are performed as needed between the surface sample format and the destination type. .ctype. . then .v2.p. Operand b is a scalar or singleton tuple for 1d surfaces.b32.b16.b // for sust. . B. If the source type is . Operand a is a .2d.p requires sm_20 or later.trap . the resulting behavior is undefined.b64. Target ISA Notes Examples 126 January 24. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. additional clamp modifiers.f3.wb. sm_1x targets support only the . c.p. sust Syntax Texture and Surface Instructions: sust Store to surface memory. SNORM.f32 is assumed. none.f32.p performs a formatted store of a vector of 32-bit data values to a surface sample. sust.b.p Description Store to surface memory using a surface coordinate vector. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. If an address is not properly aligned.b64 }. . or the instruction may fault. sust.wt }.f32} are currently unimplemented.cs. . [a. The lowest dimension coordinate represents a sample offset rather than a byte offset.ctype . and is a four-element vector for 3d surfaces. Cache operations require sm_20 or later. If the source base type is .vec.s32.b. if the surface format contains SINT data. The . the access may proceed by silently masking off low-order address bits to achieve proper rounding.1d. sust.trap sust.b.s32.v4. b]. Surface sample components that do not occur in the source vector will be written with an unpredictable value. sust.

The lowest dimension coordinate represents a byte offset into the surface and is not scaled. ..geom. Coordinate elements are of type .min. and the data is interpreted as . and is a four-element vector for 3d surfaces.1d. or .p performs a reduction on sample-addressed 32-bit data. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b.b performs an unformatted reduction on .y}]. . // for sured.3d }.u32 based on the surface sample format as follows: if the surface format contains UINT data. sured.trap.b].b32 type. sured.trap . .c.s32 or . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.max.and.zero }.trap sured. and .clamp [a.u64. the resulting behavior is undefined.p.c. .u64 data.b32. The instruction type is restricted to .b32. .add.op.2d. [surf_B. .geom. // for sured.u64. Instruction Set Table 92. operations and and or apply to .b32 }. January 24.s32.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32 types.trap [surf_A.Chapter 8. min and max apply to . Operand b is a scalar or singleton tuple for 1d surfaces. {x}].b.1d.surfref variable. {x. r1.add.0.u32.u32. sured. .b32. i. .s32.min.clamp field specifies how to handle out-of-bounds addresses: . The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. if the surface format contains SINT data. .ctype = { .p. If an address is not properly aligned.u32.ctype = { . Operations add applies to .clamp. . then .2d. . Reduction to surface memory using a surface coordinate vector. where the fourth element is ignored.p . // sample addressing .s32 is assumed. then .op. Operand a is a .b]. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . A surface base address is assumed to be aligned to a 16-byte address. sured. .clamp = { .b . is a two-element vector for 2d surfaces. . 2010 127 . . The .ctype. sured requires sm_20 or later.clamp . The lowest dimension coordinate represents a sample offset rather than a byte offset.b32 }. r1.op = { .geom = { .s32 types. .e.clamp [a. or the instruction may fault. // byte addressing sured.u32 is assumed.s32.u32.ctype.u32 and .or }.

. 128 January 24. Query: . .depth }.height.query. suq Syntax Texture and Surface Instructions: suq Query a surface attribute. Supported on all target architectures. [surf_A].0 Table 93.query = { .b32 %r1. .PTX ISA Version 2.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. suq. 2010 .b32 d. Description Query an attribute of a surface.width.width . [a]. suq.surfref variable.width.5. Operand a is a .height .

0.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. p. mov.7. Supported on all target architectures.0. } PTX ISA Notes Target ISA Notes Examples Table 95. If {!}p then instruction Introduced in PTX ISA version 1.f32 @q bra L23.s32 d. Supported on all target architectures. Execute an instruction or instruction block for threads that have the guard predicate true.a. setp.x.eq. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.s32 a.f32 @!p div. used primarily for defining a function body.b. @{!}p instruction.7. 2010 129 . Instruction Set 8.Chapter 8. { add. {} Syntax Description Control Flow Instructions: { } Instruction grouping. { instructionList } The curly braces create a group of instructions. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.c.y. ratio.0. Introduced in PTX ISA version 1. Threads with a false guard predicate do nothing.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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if any thread in a warp executes a bar instruction. Thus. PTX ISA Notes Target ISA Notes Examples bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. All threads in the warp are stalled until the barrier completes. the final value is written to the destination register in all threads waiting at the barrier.and and .sync with an immediate barrier number is supported for sm_1x targets. bar.sync bar. January 24.and). b. Since barriers are executed on a per-warp basis. If no thread count is specified. the bar. while .sync and bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. When a barrier completes. Execution in this case is unpredictable.or }. thread count. {!}c. Description Performs barrier synchronization and communication within a CTA.arrive using the same active barrier.or). the optional thread count must be a multiple of the warp size. a. and d have type .popc). bar. Operands a. b. Register operands. bar.0.op.sync and bar.u32 bar. bar.red instruction.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.red are population-count (. In addition to signaling its arrival at the barrier.cta.red performs a reduction operation across threads. Instruction Set Table 100.red} require sm_20 or later.sync or bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. and any-thread-true (.arrive does not cause any waiting by the executing threads. Register operands.sync without a thread count introduced in PTX ISA 1. Each CTA instance has sixteen barriers numbered 0.{arrive. thread count.red.red should not be intermixed with bar.red} introduced in PTX .. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.0. Once the barrier count is reached.op = { .sync) until the barrier count is met.sync or bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active.15.and. the waiting threads are restarted without delay.red also guarantee memory ordering among threads identical to membar. all-threads-true (. a{. b}. Note that a non-zero thread count is required for bar. and bar. . and the barrier is reinitialized so that it can be immediately reused.pred . bar. d. bar.arrive a{.red performs a predicate reduction across the threads participating in the barrier. bar. p. b}. operands p and c are predicates. execute a bar. bar. 2010 133 .Chapter 8. {!}c.version 2. The barrier instructions signal the arrival of the executing threads at the named barrier. threads within a CTA that wish to communicate via memory can store to memory. bar. and then safely read values stored by other threads prior to the barrier. a{.arrive. and bar.popc. The reduction operations for bar. The result of . Thus.sync 0.red. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). it is as if all the threads in the warp have executed the bar instruction. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.u32. Only bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Operand b specifies the number of threads participating in the barrier. it simply marks a thread's arrival at the barrier.red delays the executing threads (similar to bar. all threads in the CTA participate in the barrier.{arrive.popc is the number of threads with a true predicate. b}. In conditionally executed code.

. membar. membar.gl.version 2.cta Waits until all prior memory writes are visible to other threads in the same CTA.sys Waits until all prior memory requests have been performed with respect to all clients.g. that is.gl.sys.version 1.g. 2010 . A memory read (e. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers. membar. red or atom) has been performed when the value written has become visible to other clients at the specified level.sys introduced in PTX .gl} introduced in PTX . membar. global. this is the appropriate level of membar. membar. membar. and memory reads by this thread can no longer be affected by other thread writes. membar. membar. when the previous value can no longer be read. .cta.sys will typically have much longer latency than membar.cta. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. For communication between threads in different CTAs or even different SMs. Waits until prior memory reads have been performed with respect to other threads in the CTA.PTX ISA Version 2. A memory write (e.{cta. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.4.level = { . membar.level.sys requires sm_20 or later. .0 Table 101.gl will typically have a longer latency than membar.sys }. or system memory level. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. 134 January 24.gl} supported on all target architectures. membar. level describes the scope of other clients for which membar is an ordering event. membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.gl. by st. PTX ISA Notes Target ISA Notes Examples membar.cta. membar.{cta.0. including thoses communicating via PCI-E such as system and peer-to-peer memory.

c.shared }. . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. b.b32. d. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. .g. . or by using atom.op. If an address is not properly aligned.u32.e. . .u64. or.inc.s32.u64 . .f32.f32 }. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. or [immAddr] an immediate absolute byte address. min.add. For atom. and max. . . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. the resulting behavior is undefined.b64. . The integer operations are add.or. an address maps to the corresponding location in local or shared memory.f32 Atomically loads the original value at location a into destination register d.space}. atom{.Chapter 8. by inserting barriers between normal stores and atomic operations to a common address. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . Operand a specifies a location in the specified state space. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. The inc and dec operations return a result in the range [0.type atom{. .b32.u32.op = { . overwriting the original value. and max operations are single-precision. If no state space is given. inc.b32 only . .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. an address maps to global memory unless it falls within the local memory window or the shared memory window. [a].e. dec. . .b].s32.exch. xor. In generic addressing. max.min. The floating-point add.u32. e. Instruction Set Table 102. accesses to local memory are illegal.space}. 2010 135 .exch to store to locations accessed by other atomic operations.max }. min. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Description // // // // // . . .and. . or the instruction may fault. performs a reduction operation with operand b and the value in location a.b64 . Within these windows. . The bit-size operations are and.dec...type = { .type d. January 24. . [a]. 32-bit operations. min.s32. atom.u32 only . b. . a de-referenced register areg containing a byte address.xor. .space = { . cas (compare-and-swap). and exch (exchange). The address must be naturally aligned to a multiple of the access size. i. A register containing an address may be declared as a bit-size type or integer type.cas. The address size may be either 32-bit or 64-bit. perform the memory accesses using generic addressing.op.global. and stores the result of the specified operation at location a. and truncated if the register width exceeds the state space address width for the target architecture. Addresses are zero-extended to the specified width as needed. The floating-point operations are add. . i. .add.

Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.shared operations require sm_20 or later. : r. *a = (operation == cas) ? : } where inc(r.{add.s.[a].f32 requires sm_20 or later.max.global.f32 atom.add.0. d. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom. Introduced in PTX ISA version 1.shared.0. c) operation(*a.my_new_val.1. s) = (r > s) ? s exch(r.b32 d.f32.{min.global requires sm_11 or later. : r+1.add. atom. atom. atom.exch} requires sm_12 or later.shared requires sm_12 or later.my_val. s) = (r >= s) ? 0 dec(r.cas.cas.0 Semantics atomic { d = *a.t) = (r == s) ? t operation(*a. d. Release Notes Examples @p 136 January 24. : r-1. cas(r. 64-bit atom.s32 atom.global.PTX ISA Version 2. atom.max} are unimplemented. 64-bit atom. b. Use of generic addressing requires sm_20 or later.[p]. s) = s. 2010 . b).[x+4].

.b32 only . Instruction Set Table 103. the access may proceed by silently masking off low-order address bits to achieve proper rounding.b]. or the instruction may fault. The floating-point operations are add. b. . i. If an address is not properly aligned. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The floating-point add.Chapter 8. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. and max. . perform the memory accesses using generic addressing.or. . The address size may be either 32-bit or 64-bit. Semantics *a = operation(*a. overwriting the original value. an address maps to the corresponding location in local or shared memory.b64. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.u32. Notes Operand a must reside in either the global or shared state space. Description // // // // .type [a].u64.op = { . i.add. min. . 2010 137 .e. by inserting barriers between normal stores and reduction operations to a common address. s) = (r >= s) ? 0 : r+1.u32 only . Operand a specifies a location in the specified state space. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. The integer operations are add. . s) = (r > s) ? s : r-1.f32. Addresses are zero-extended to the specified width as needed.and.u64 . and max operations are single-precision. In generic addressing.min.exch to store to locations accessed by other reduction operations.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. e. .shared }.dec. 32-bit operations. . .s32. .f32 }.g.add. and truncated if the register width exceeds the state space address width for the target architecture. . inc.u32. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. or [immAddr] an immediate absolute byte address. . red{. an address maps to global memory unless it falls within the local memory window or the shared memory window. the resulting behavior is undefined. or. . and stores the result of the specified operation at location a.max }. b). .space = { . where inc(r.op.f32 Performs a reduction operation with operand b and the value in location a. . accesses to local memory are illegal.type = { .inc. The inc and dec operations return a result in the range [0. .s32. . .s32. . For red. a de-referenced register areg containing a byte address. dec. .u32. red. dec(r. or by using atom. The address must be naturally aligned to a multiple of the access size.e. If no state space is given. Within these windows.global. min.. The bit-size operations are and.xor. min. max.b32. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. .. A register containing an address may be declared as a bit-size type or integer type.space}. and xor. January 24.

[p]. red. Use of generic addressing requires sm_20 or later.my_val. red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. [x+4].f32 requires sm_20 or later.0.shared requires sm_12 or later.global.s32 red.1.f32.global requires sm_11 or later red. 64-bit red.shared operations require sm_20 or later.max} are unimplemented.global.shared.add.PTX ISA Version 2.and. 64-bit red. red.max.b32 [a]. 2010 . Release Notes Examples @p 138 January 24.f32 red.add.{min.2.add requires sm_12 or later. red.

Instruction Set Table 104. Negate the source predicate to compute .q. Negating the source predicate also computes .ballot. where the bit position corresponds to the thread’s lane id. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. 2010 139 . .2.b32 d.all.uni }. r1. vote. The reduction modes are: .uni.all.mode.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.ballot.not_all.any True if source predicate is True for some active thread in warp.any. Description Performs a reduction of the source predicate across threads in a warp.p. . Negate the source predicate to compute . {!}a. {!}a. // ‘ballot’ form. vote. vote requires sm_12 or later.ballot. // get ‘ballot’ across warp January 24.none.pred d. p.all True if source predicate is True for all active threads in warp.ballot. vote. .pred vote. The destination predicate value is the same across all threads in the warp. In the ‘ballot’ form.uni. returns bitmask .Chapter 8.mode = { . .pred vote.uni True if source predicate has the same value in all active threads in warp. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.q.b32 p. not across an entire CTA. vote.b32 requires sm_20 or later. vote. Note that vote applies to threads in a single warp.

dtype.secop d. 140 January 24. b{. . the input values are extracted and signor zero.h1 }.max }.b2.PTX ISA Version 2. . The primary operation is then performed to produce an .add. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).bsel}. all combinations of dtype. Using the atype/btype and asel/bsel specifiers. half-word.bsel}. The general format of video instructions is as follows: // 32-bit scalar operation. with optional secondary operation vop.s32 }.b3. . a{. b{.atype.dtype. .atype. and btype are valid.s32) is specified in the instruction type.h0. .dsel.u32.asel = . b{.dsel = . or word values from its source operands. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.bsel}. . 2010 .atype.btype{. . to produce signed 33-bit input values. The source and destination operands are all 32-bit registers. vop.asel}.s34 intermediate result.0 8. perform a scalar arithmetic operation to produce a signed 34-bit result.sat} d. 3.b0.u32 or .s33 values. 2.btype = { . Video Instructions All video instructions operate on 32-bit register operands.asel}. . taking into account the subword destination size in the case of optional data merging. c. The type of each operand (.asel}. The sign of the intermediate result depends on dtype.btype{. a{.bsel = { . c. .min. a{. extract and sign.sat}. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. .b1.or zero-extend byte.dtype.9. with optional data merge vop. 4.dtype = . optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.sat} d.7.atype = . atype. .btype{.secop = { . optionally clamp the result to the range of the destination type. // 32-bit scalar operation.extended internally to .

2010 141 . c).b1: return ((tmp & 0xff) << 8) case .s33 c) { switch ( secop ) { . The lower 32-bits are then written to the destination operand. . S32_MAX. U16_MAX. . . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. U8_MIN ). } } . Instruction Set . U32_MAX. default: return tmp. . Modifier dsel ) { if ( !sat ) return tmp. U8_MAX. U32_MIN ).b2.s33 tmp.add: return tmp + c. . .b2: return ((tmp & 0xff) << 16) case .s33 optSecOp(Modifier secop.h0. . S16_MIN ).s33 c ) switch ( dsel ) { case . . S16_MAX. The sign of the c operand is based on dtype.s33 optSaturate( .b0. January 24.min: return MIN(tmp.Chapter 8.s33 optMerge( Modifier dsel. tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. tmp.s33 tmp. tmp. c). . as shown in the following pseudocode. S8_MIN ). } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). U16_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. c).b1. switch ( dsel ) { case .b0: return ((tmp & 0xff) case .b3: if ( sign ) return CLAMP( else return CLAMP( case .max return MAX(tmp.s34 tmp. .h1: return ((tmp & 0xffff) << 16) case .h0: return ((tmp & 0xffff) case . Bool sat. c). tmp. c). Bool sign. S32_MIN ). S8_MAX. tmp. c). . c).

tmp = | ta – tb |. r1.asel}.add r1.h0. // optional merge with c operand 142 January 24.add. . Integer byte/half-word/word minimum / maximum. .bsel}. vmin.sat.s32. vmax }.s32 }.s32. asel ). Perform scalar arithmetic operation with optional saturate.u32. atype. . tb = partSelectSignExtend( b.op2 Description = = = = { vadd. .b2. vmax vadd.dtype .asel}. c. // 32-bit scalar operation.sat} d. tmp. isSigned(dtype).atype. and optional secondary arithmetic operation or subword data merge.sat}. r2.min. vmax require sm_20 or later. bsel ). c. a{. . // 32-bit scalar operation. .asel = . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.dtype.PTX ISA Version 2.0. vmin.op2 d. vabsdiff.sat vabsdiff.b0. tb ). tmp. r3. r1. c.b0.or zero-extend based on source operand type ta = partSelectSignExtend( a. taking into account destination type and merge operations tmp = optSaturate( tmp.b3. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb.atype. with optional data merge vop.s32. r3. dsel ).sat vmin.b2. sat. tmp = MIN( ta.atype = . c ). 2010 .sat} d. d = optSecondaryOp( op2.max }. { . b{. .dtype. r2.u32. vop.bsel}. c. Semantics // saturate. vsub.vop .asel}.u32. a{. vsub. c ). vabsdiff. tb ). vsub vabsdiff vmin. a{.s32. tmp = ta – tb. b{. vsub. // optional secondary operation d = optMerge( dsel.btype{. Integer byte/half-word/word absolute value of difference. r2.h0. vadd.dsel.btype{. vadd.b1. tmp = MAX( ta. r3. btype.s32. . vmax Syntax Integer byte/half-word/word addition / subtraction. vabsdiff.s32.btype = { .s32.b0.atype.h1 }.h1.s32.s32. .h0.bsel}.s32. vmin.sat vsub.h1.dsel . r2. r3. .dtype.btype{. Video Instructions: vadd. // extract byte/half-word/word and sign.bsel = { . b{. with optional secondary operation vop. r1. .0 Table 105.

u32. b{.wrap }.asel}. asel ). unsigned shift fills with zero. January 24.add.bsel}. vshr Syntax Integer byte/half-word/word left / right shift.wrap r1. and optional secondary arithmetic operation or subword data merge. . dsel ). // optional secondary operation d = optMerge( dsel.u32{.sat}{.dtype. a{. a{.atype.h1 }.bsel}. vshl. sat. . c.atype. r1. if ( mode == .u32 vshr.u32. with optional secondary operation vop. b{. b{.u32{.b0.mode} d.min. } // saturate.u32. switch ( vop ) { case vshl: tmp = ta << tb. r2.mode} d. . vshl: Shift a left by unsigned amount in b with optional saturate.bsel}. . Video Instructions: vshl.b3. isSigned(dtype). Left shift fills with zero.b2. d = optSecondaryOp( op2. atype.h1.dtype. .asel}.atype = { . and optional secondary arithmetic operation or subword data merge. vshr }. 2010 143 .clamp. if ( mode == .u32. { .sat}{.h0.wrap ) tb = tb & 0x1f. { .dsel .op2 d. .mode}.max }.0.u32{. taking into account destination type and merge operations tmp = optSaturate( tmp. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . c.atype. vshr: Shift a right by unsigned amount in b with optional saturate. // 32-bit scalar operation. .asel = .vop .dsel. tmp. Signed shift fills with the sign bit. .b1. case vshr: tmp = ta >> tb.mode . a{.u32.Chapter 8. c ). tb = partSelectSignExtend( b. // default is .asel}. r2.bsel = { . r3. bsel ). vshr vshl. c ). . // 32-bit scalar operation. with optional data merge vop. r3. .u32. vshr require sm_20 or later.clamp .sat}{. tmp.dtype .s32 }.op2 Description = = = = = { vshl.or zero-extend based on source operand type ta = partSelectSignExtend( a.dtype.s32. . vop.clamp && tb > 32 ) tb = 32. Semantics // extract byte/half-word/word and sign. Instruction Set Table 106. vshl.

The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.btype = { . The final result is unsigned if the intermediate result is unsigned and c is not negated. .scale} d. {-}c.dtype = . 2010 .u32.b2.scale} d.scale = { . .dtype. which is used in computing averages.atype = . {-}b{.atype. final signed (S32 * U32) . Although PTX syntax allows separate negation of the a and b operands. . The “plus one” mode (. (a*b) is negated if and only if exactly one of a or b is negated. The source operands support optional negation with some restrictions. Source operands may not be negated in . .S32 // intermediate signed.0 Table 107.sat}{.h1 }. Description Calculate (a*b) + c.S32 // intermediate signed.bsel}. and scaling.atype.S32 // intermediate signed. final signed (S32 * S32) .bsel}. final signed -(S32 * U32) + S32 // intermediate signed. final unsigned -(U32 * U32) + S32 // intermediate signed. “plus one” mode. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. PTX allows negation of either (a*b) or c.shr15 }. and zero-extended otherwise. .s32 }.asel = .U32 // intermediate unsigned. internally this is represented as negation of the product (a*b).b3.asel}.po{. final signed (U32 * S32) + S32 // intermediate signed. // 32-bit scalar operation vmad..b0. . vmad. Input c has the same sign as the intermediate result. and the operand negates.bsel = { . final signed (U32 * S32) . final signed (U32 * U32) .btype. .shr7. . Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. . final signed -(S32 * S32) + S32 // intermediate signed. otherwise.btype{.po) computes (a*b) + c + 1. with optional operand negates. .sat}{. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. a{. 144 January 24.b1. the intermediate result is signed. Depending on the sign of the a and b operands. {-}a{. b{.h0. final signed (S32 * S32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift.po mode.dtype.asel}. That is. c. this result is sign-extended if the final result is signed. final signed (S32 * U32) + S32 // intermediate signed. final signed -(U32 * S32) + S32 // intermediate signed.PTX ISA Version 2.

negate ) { c = ~c.sat ) { if (signedFinal) result = CLAMP(result.u32.negate ^ b. S32_MAX.or zero-extend based on source operand type ta = partSelectSignExtend( a.h0. case . btype. signedFinal = isSigned(atype) || isSigned(btype) || (a. r1. lsb = 1. tmp = tmp + c128 + lsb.negate. -r3. r1. } else if ( a. U32_MIN).shr7: result = (tmp >> 7) & 0xffffffffffffffff. vmad requires sm_20 or later. 2010 145 . bsel ).s32. U32_MAX. r2. r3. } if ( . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. switch( scale ) { case . vmad. S32_MIN).negate ^ b. lsb = 0. tmp[127:0] = ta * tb.negate) || c.u32. } else if ( c.s32.u32. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).negate ) { tmp = ~tmp.h0. asel ). tb = partSelectSignExtend( b. Instruction Set Semantics // extract byte/half-word/word and sign.shr15 r0.Chapter 8.0. atype. January 24. r2.sat vmad.po ) { lsb = 1. r0.shr15: result = (tmp >> 15) & 0xffffffffffffffff. if ( . else result = CLAMP(result. lsb = 1.u32.

.u32. 2010 . . . Compare input values using specified comparison.eq. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.lt vset. .asel}. .btype. asel ).b3.h1.btype.u32. . .cmp d.btype. vset.s32 }.b0. tmp = compare( ta. a{.ge }.b1. c.atype.bsel}.op2 Description = = = = .u32. .cmp . { . Semantics // extract byte/half-word/word and sign. tb. atype.cmp d. btype. cmp ) ? 1 : 0.dsel . c ). vset requires sm_20 or later.dsel. d = optSecondaryOp( op2.bsel}.gt. r2. with optional data merge vset. bsel ). c.bsel}.le. 146 January 24. r3. The intermediate result of the comparison is always unsigned. with optional secondary arithmetic operation or subword data merge. // 32-bit scalar operation. b{.ne r1.asel = . // optional secondary operation d = optMerge( dsel.asel}.or zero-extend based on source operand type ta = partSelectSignExtend( a. .h0. . .bsel = { . .u32. tmp. vset. r2.cmp. { . . a{.0. r1. with optional secondary operation vset.PTX ISA Version 2. b{.s32.btype = { . b{.max }.atype.asel}. r3.ne. .op2 d. // 32-bit scalar operation.atype.lt.0 Table 108.atype . a{. .b2. tmp.h1 }.min. and therefore the c operand and final result are also unsigned.add. tb = partSelectSignExtend( b. c ).

Table 110. Table 111. brkpt.7. The relationship between events and counters is programmed via API calls from the host. Triggers one of a fixed number of performance monitor events. Introduced in PTX ISA version 1. 2010 147 . Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. @p pmevent 1. with index specified by immediate operand a. pmevent a. trap. trap Abort execution and generate an interrupt to the host CPU. Introduced in PTX ISA version 1.0. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. brkpt. Supported on all target architectures. brkpt Suspends execution Introduced in PTX ISA version 1. pmevent 7. trap.4. Instruction Set 8. numbered 0 through 15.10. Notes PTX ISA Notes Target ISA Notes Examples Currently.Chapter 8. brkpt requires sm_11 or later.0. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. January 24. Supported on all target architectures. there are sixteen performance monitor events. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.

0 148 January 24. 2010 .PTX ISA Version 2.

%clock64 %pm0. %lanemask_gt %clock.Chapter 9. %pm3 January 24. %lanemask_lt. which are visible as special registers and accessed through mov or cvt instructions. 2010 149 . %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_le. Special Registers PTX includes a number of predefined. read-only variables. ….

x. mov. CTA dimensions are non-zero.0.%ntid. .v4. per-thread special register initialized with the thread identifier within the CTA.z == 1 in 1D CTAs.0 Table 112. %ntid. mov. // legacy PTX 1.x.0. %ntid. the %tid value in unused dimensions is 0.u32 %ntid. %tid.%h2. // zero-extend tid.%tid.0.u32 %r0.u16 %r2.v4 . %tid.u32 %tid.sreg .y 0 <= %tid.z == 0 in 2D CTAs.y * %ntid. cvt. // compute unified thread id for 2D CTA mov.x. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.y == %ntid. Supported on all target architectures.u16 %rh. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x * %ntid.sreg . It is guaranteed that: 0 <= %tid. Every thread in the CTA has a unique %tid. The number of threads in each dimension are specified by the predefined special register %ntid. mad.u32 type in PTX 2.v4.v4 . read-only special register initialized with the number of thread ids in each CTA dimension.z).x code accessing 16-bit component of %tid mov.z == 0 in 1D CTAs.x. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. The total number of threads in a CTA is (%ntid.y == %tid. Redefined as .%tid. Supported on all target architectures.u32 %r1. .%h1.z. The fourth element is unused and always returns zero. .u32 %tid.z == 1 in 2D CTAs.sreg .y < %ntid. read-only. . 2D.y. %ntid. // CTA shape vector // CTA dimensions A predefined. the fourth element is unused and always returns zero. Redefined as .x.x 0 <= %tid.z. 2010 . The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.%tid.u32 %h2.y.%r0. mov. %ntid.x code Target ISA Notes Examples 150 January 24.z.x. PTX ISA Notes Introduced in PTX ISA version 1. %tid.u16 %rh. %tid.%tid.u32 type in PTX 2.z PTX ISA Notes Introduced in PTX ISA version 1.PTX ISA Version 2.%tid.u32 %r0.x. The %tid special register contains a 1D.x to %rh Target ISA Notes Examples // legacy PTX 1.z to %r2 Table 113.u32.sreg . or 3D vector to match the CTA shape.u32 %ntid. %tid component values range from 0 through %ntid–1 in each CTA dimension.%ntid.0.x < %ntid. // thread id vector // thread id components A predefined. // move tid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. mov.u32 %h1.y.z < %ntid.

A predefined.3. A predefined. mov.sreg .u32 %r.3. A predefined. Table 115.sreg . but its value may change during execution. mov.0.u32 %r. . Introduced in PTX ISA version 2. %warpid. read-only special register that returns the maximum number of warp identifiers. Supported on all target architectures. Special Registers Table 114. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. due to rescheduling of threads following preemption. .u32 %nwarpid. mov. Supported on all target architectures. Note that %warpid is volatile and returns the location of a thread at the moment when read.u32 %warpid. The lane identifier ranges from zero to WARP_SZ-1. read-only special register that returns the thread’s lane within the warp. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. 2010 151 . read-only special register that returns the thread’s warp identifier. %laneid. %nwarpid.u32 %r.Chapter 9. PTX ISA Notes Target ISA Notes Examples Table 116. %nwarpid requires sm_20 or later. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.g. January 24. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. . The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. For this reason.u32 %laneid. e. The warp identifier will be the same for all threads within a single warp.sreg .

y. %rh.%nctaid. or 3D vector.%nctaid.z. It is guaranteed that: 0 <= %ctaid.x.x < %nctaid. // legacy PTX 1.u16 %r0. The fourth element is unused and always returns zero. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. . read-only special register initialized with the number of CTAs in each grid dimension. with each element having a value of at least 1.z PTX ISA Notes Introduced in PTX ISA version 1. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.z} < 65.%nctaid. It is guaranteed that: 1 <= %nctaid.y.x 0 <= %ctaid. mov.v4. %rh. read-only special register initialized with the CTA identifier within the CTA grid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.u32 %nctaid . %ctaid.sreg .y.0.x.x.%ctaid. // CTA id vector // CTA id components A predefined.u32 type in PTX 2.y < %nctaid. Supported on all target architectures. Each vector element value is >= 0 and < 65535. The %ctaid special register contains a 1D.y 0 <= %ctaid.v4 . depending on the shape and rank of the CTA grid.u32 %nctaid.z < %nctaid.0 Table 117.sreg . Redefined as .%ctaid.0.536 PTX ISA Notes Introduced in PTX ISA version 1. 2010 . mov.u16 %r0.u32 type in PTX 2.u32 mov.%nctaid.u32 %ctaid. .u32 mov. Supported on all target architectures.z.sreg .x. %ctaid.x code Target ISA Notes Examples 152 January 24. The %nctaid special register contains a 3D grid shape vector. The fourth element is unused and always returns zero. Redefined as . .0. 2D.u32 %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid. // legacy PTX 1.x.0.sreg .x code Target ISA Notes Examples Table 118. // Grid shape vector // Grid dimensions A predefined.PTX ISA Version 2.{x.y.v4 .v4.

The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. PTX ISA Notes Target ISA Notes Examples Table 121. PTX ISA Notes Target ISA Notes Examples January 24. Introduced in PTX ISA version 1. Introduced in PTX ISA version 2.u32 %smid.0. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. 2010 153 . The SM identifier numbering is not guaranteed to be contiguous. %smid. mov. read-only special register that returns the maximum number of SM identifiers. Introduced in PTX ISA version 1. The SM identifier ranges from 0 to %nsmid-1. mov. e.g. // initialized at grid launch A predefined.u32 %r. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. During execution. Supported on all target architectures. Note that %smid is volatile and returns the location of a thread at the moment when read.sreg . but its value may change during execution. Notes PTX ISA Notes Target ISA Notes Examples Table 120.Chapter 9. Supported on all target architectures. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. .0. This variable provides the temporal grid launch number for this context. repeated launches of programs may occur. Special Registers Table 119.3. mov. so %nsmid may be larger than the physical number of SMs in the device.u32 %r. %nsmid. where each launch starts a grid-of-CTAs.u32 %gridid. %gridid. %nsmid requires sm_20 or later. read-only special register that returns the processor (SM) identifier on which a particular thread is executing.sreg .u32 %nsmid. . A predefined. . The SM identifier numbering is not guaranteed to be contiguous. read-only special register initialized with the per-grid temporal grid identifier.sreg . A predefined.u32 %r. due to rescheduling of threads following preemption.

%lanemask_le requires sm_20 or later.0.sreg .u32 %lanemask_le. Table 124.u32 %lanemask_eq. Introduced in PTX ISA version 2. A predefined. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. . mov.u32 %r.sreg . %lanemask_lt. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. mov. %lanemask_le. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.u32 %lanemask_lt. A predefined.0. %lanemask_eq requires sm_20 or later. %lanemask_lt requires sm_20 or later. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. Table 123. 2010 . %lanemask_eq.u32 %r. A predefined. .sreg .0 Table 122.PTX ISA Version 2. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Introduced in PTX ISA version 2. mov.0. .u32 %r. 154 January 24.

mov. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_gt. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. .u32 %r.u32 %lanemask_gt.Chapter 9. .sreg . A predefined. Introduced in PTX ISA version 2. mov.0.u32 %lanemask_ge. January 24. A predefined. %lanemask_ge requires sm_20 or later.sreg . Special Registers Table 125. 2010 155 . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.0. %lanemask_gt requires sm_20 or later. %lanemask_ge.u32 %r. Table 126.

0. .0 Table 127. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. mov. ….u32 %clock.u64 %clock64. %pm1. mov. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.sreg . Special Registers: %pm0. %clock64 requires sm_20 or later.%clock64.%clock. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm2.0. %pm1. read-only 64-bit unsigned cycle counter. %pm2. read-only 32-bit unsigned cycle counter.u32 %pm0.u32 r1. Introduced in PTX ISA version 1. Supported on all target architectures. %pm3.u32 r1. and %pm3 are unsigned 32-bit read-only performance monitor counters.PTX ISA Version 2.%pm0.3. Introduced in PTX ISA version 2. . mov. Special registers %pm0. Introduced in PTX ISA version 1. 156 January 24. Their behavior is currently undefined. %pm1. . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Table 129. %pm2. Supported on all target architectures.u64 r1.sreg . Table 128. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.sreg . %pm3 %pm0. 2010 . The lower 32-bits of %clock64 are identical to %clock.

.version 2. Each ptx file must begin with a . .version major. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. Supported on all target architectures.version 1. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. minor are integers Specifies the PTX language version number.1.version .target Table 130. Directives 10.Chapter 10. PTX File Directives: . and the target architecture for which the code was generated. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version .version directive.0.0 .4 January 24. Duplicate . Increments to the major number indicate incompatible changes to PTX.version Syntax Description Semantics PTX version number. .minor // major.version directive.version directives are allowed provided they match the original . 2010 157 .

f32. Requires map_f64_to_f32 if any .5.target .0. Disallows use of map_f64_to_f32. sm_13.texref and . PTX File Directives: . Adds {atom. sm_12.texmode_unified) . Adds {atom.f64 instructions used. Texturing mode introduced in PTX ISA version 1. 64-bit {atom. texture and sampler information is referenced with independent .global. The following table summarizes the features in PTX that vary according to target architecture. A .f64 storage remains as 64-bits. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. map_f64_to_f32 }.red}.texmode_unified . vote instructions.version directive. where each generation adds new features and retains all features of previous generations. Description Specifies the set of features in the target architecture for which the current ptx code was generated.red}.0 Table 131. brkpt instructions.texmode_independent texture and sampler information is bound together and accessed via a single . 2010 . .f64 instructions used.f64 to .target directives can be used to change the set of target features allowed during parsing.global. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.shared. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. immediately followed by a .target directive specifies a single target architecture.texref descriptor. with only half being used by instructions converted from . and an error is generated if an unsupported feature is used. 158 January 24. Requires map_f64_to_f32 if any .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. texmode_unified.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. PTX features are checked against the specified target architecture. Supported on all target architectures. A program with multiple . including expanded rounding modifiers. Each PTX file must begin with a . The texturing mode is specified for an entire module and cannot be changed within the module.red}.samplerref descriptors. PTX code generated for a given target can be run on later generation devices. sm_11. texmode_independent. Introduced in PTX ISA version 1.target Syntax Architecture and Platform target. Note that . Therefore.f64 instructions used.target directive containing a target architecture and optional platform options. generations of SM architectures follow an “onion layer” model. Adds double-precision support. Requires map_f64_to_f32 if any . but subsequent . Texturing mode: (default is . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. In general. sm_10.PTX ISA Version 2. Target sm_20 Description Baseline feature set for sm_20 architecture.

target sm_10 // baseline target architecture . 2010 159 . texmode_independent January 24.target sm_20. Directives Examples .target sm_13 // supports double-precision .Chapter 10.

parameters. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. with optional parameters.reg .3. Kernel and Function Directives: . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.2. The shape and size of the CTA executing the kernel are available in special registers. and body for the kernel function.entry .param { .param instructions. For PTX ISA versions 1. . .param . parameter variables are declared in the kernel body. store. parameter variables are declared in the kernel parameter list. [y].0 through 1. e.param. 160 January 24. At kernel launch.PTX ISA Version 2.param .4.entry filter ( . [z].samplerref.b32 z ) Target ISA Notes Examples [x].surfref variables may be passed as parameters.b32 %r2. ld.g.param. 2010 . Parameters are passed via .b32 y.entry Syntax Description Kernel entry point and body.b32 %r<99>. . ld. the kernel dimensions and properties are established and made available via special registers.b32 %r3. opaque . etc.texref. and query instructions and cannot be accessed via ld.0 through 1.b32 %r1.b32 x.5 and later. PTX ISA Notes For PTX ISA version 1. %ntid.param.entry cta_fft . . . and . . In addition to normal parameters. Semantics Specify the entry point for a kernel program. These parameters can only be referenced by name within texture and surface load. … } . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. %nctaid.param space memory and are listed within an optional parenthesized parameter list.param instructions.0 10.entry kernel-name ( param-list ) kernel-body .func Table 132.4 and later. Parameters may be referenced by name within the kernel body and loaded into registers using ld.entry . ld. Supported on all target architectures.entry kernel-name kernel-body Defines a kernel entry point name.

and supports recursion.f64 dbl) { . if any. .0.param state space. Release Notes For PTX ISA version 1.reg . 2010 161 .func .b32 N. other code.func (ret-param) fname (param-list) function-body Defines a function. mov. Directives Table 133. Kernel and Function Directives: .b32 rval) foo (. Variadic functions are currently unimplemented.0 with target sm_20 allows parameters in the .b32 localVar. Parameters in . Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Parameters must be base types in either the register or parameter state space. parameters must be in the register state space. Variadic functions are represented using ellipsis following the last fixed argument. which may use a combination of registers and stack locations to pass parameters.func fname function-body .b32 rval. Parameter passing is call-by-value. . foo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. A . … use N. Parameters in register state space may be referenced directly within instructions in the function body.func Syntax Function definition.func (. dbl.param space are accessed using ld.reg .Chapter 10. Supported on all target architectures. PTX ISA 2.param instructions in the body. and recursion is illegal. there is no stack.x code. … Description // return value in fooval January 24. val1). . implements an ABI with stack.2 for a description of variadic functions.param and st. The parameter lists define locally-scoped variables in the function body.reg . PTX 2.result. ret.func definition with no body provides a function prototype. } … call (fooval). (val0. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. including input and return parameters and optional function body. The implementation of parameter passing is left to the optimizing translator.reg .func fname (param-list) function-body .0 with target sm_20 supports at most one return value.

PTX ISA Version 2.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. for example. . the .maxnctapersm (deprecated) .minnctapersm directives may be applied per-entry and must appear between an .g. PTX supports the following directives.pragma The . and . and the strings have no semantics within the PTX virtual machine model. . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. which pass information to the backend optimizing compiler. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.0 10.3. registers) to increase total thread count and provide a greater opportunity to hide memory latency. Currently. or as statements within a kernel or device function body. The directive passes a list of strings to the backend.pragma directive is supported for passing information to the PTX backend. A general . The .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.maxntid.maxnreg .minnctapersm .maxnreg.maxntid and . 162 January 24.maxntid directive specifies the maximum number of threads in a thread block (CTA).maxntid . and the .entry directive and its body. The interpretation of . the . at entry-scope. 2010 . Note that . to throttle the resource requirements (e. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. The directives take precedence over any module-level constraints passed to the optimizing backend. These can be used.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.pragma directives may appear at module (file) scope.

maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. The actual number of registers used may be less.maxntid . for example. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid 256 . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxntid nx. Performance-Tuning Directives: .entry foo . nz Declare the maximum number of threads in the thread block (CTA).maxntid nx.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. The maximum number of threads is the product of the maximum extent in each dimension. the backend may be able to compile to fewer registers.maxnreg n Declare the maximum number of registers per thread in a CTA.3. Introduced in PTX ISA version 1.maxntid nx .entry foo . ny. Directives Table 134.entry bar . or the maximum number of registers may be further constrained by .maxctapersm. 2010 163 . Supported on all target architectures. Introduced in PTX ISA version 1. Performance-Tuning Directives: . ny . Supported on all target architectures. . Exceeding any of these limits results in a runtime error or kernel launch failure.maxntid and . 2D. The compiler guarantees that this limit will not be exceeded.16.Chapter 10.maxntid Syntax Maximum number of threads in thread block (CTA).maxntid 16. or 3D CTA.maxnreg . . .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. .3.

.entry foo . Deprecated in PTX ISA version 2.maxntid 256 .0.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxntid to be specified as well. However. .maxntid 256 . 2010 .minnctapersm .0 as a replacement for .entry foo . Supported on all target architectures.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm Syntax Description Notes Maximum number of CTAs per SM.0 Table 136.minnctapersm 4 { … } 164 January 24.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Performance-Tuning Directives: .maxntid to be specified as well. Optimizations based on . Supported on all target architectures. additional CTAs may be mapped to a single multiprocessor.maxnctapersm.minnctapersm in PTX ISA version 2. if the number of registers used by the backend is sufficiently lower than this bound. Introduced in PTX ISA version 2.maxnctapersm has been renamed to . . Optimizations based on .3.maxnctapersm (deprecated) . The optimizing backend compiler uses . Introduced in PTX ISA version 1.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid and .maxnctapersm generally need .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm generally need . . For this reason. Performance-Tuning Directives: .PTX ISA Version 2. .0.

Supported on all target architectures. Performance-Tuning Directives: .Chapter 10. Directives Table 138.pragma list-of-strings .0. . 2010 165 . . See Appendix A for descriptions of the pragma strings defined in ptxas.pragma . // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .entry foo .pragma “nounroll”. The interpretation of . { … } January 24.pragma directive may occur at module-scope. or at statementlevel. entry-scoped. or statement-level directives to the PTX backend compiler. The . Introduced in PTX ISA version 2. at entry-scope.pragma Syntax Description Pass directives to PTX backend compiler.pragma directive strings is implementation-specific and has no impact on PTX semantics. Pass module-scoped.pragma “nounroll”.

Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .section .section directive. 0x00 166 January 24.section directive is new in PTX ISA verison 2.2. Introduced in PTX ISA version 1.PTX ISA Version 2. 0x736d6172 . 0x00.debug_pubnames. 0x6150736f. 0x00 .4.264-1] .section .quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.quad int64-list // comma-separated hexadecimal integers in range [0.0 but is supported for legacy PTX version 1.4byte 0x000006b5.4byte . The @@DWARF syntax is deprecated as of PTX version 2. 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0. Supported on all target architectures. Deprecated as of PTX 2. Table 139. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.byte 0x00.x code.232-1] .byte byte-list // comma-separated hexadecimal byte values .0 and replaces the @@DWARF syntax. 0x00. 0x61395a5f.4byte 0x6e69616d. replaced by . 0x00. 2010 . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .debug_info . 0x00.. 0x02. 0x63613031.loc The . @@DWARF dwarf-string dwarf-string may have one of the . “”.0 10. 0x00. @progbits .byte 0x2b.0. 0x00000364.file . 0x5f736f63 ..4byte label .

file filename Table 142. Source file information.file .section .b32 0x6e69616d..file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.section Syntax PTX section definition. . 0x736d6172 0x00 Table 141. Debugging Directives: . Debugging Directives: .b32 label .b64 int64-list // comma-separated list of integers in range [0. . 0x63613031. .0. Debugging Directives: . 0x00. .section section_name { dwarf-lines } dwarf-lines have the following formats: .loc line_number January 24. } 0x02. 0x00. 0x00..b32 0x000006b5. Directives Table 140. 0x5f736f63 0x6150736f. Supported on all target architectures.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.232-1] . .section .b8 0x00.debug_pubnames { . 0x00.b32 . 0x00.loc .0. . replaces @@DWARF syntax.255] .0. 0x00000364.debug_info .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. .264-1] . Supported on all target architectures. Source file location. 2010 167 ..b8 byte-list // comma-separated list of integers in range [0.Chapter 10. Supported on all target architectures.b8 0x2b. 0x00. 0x00 0x61395a5f.b32 int32-list // comma-separated list of integers in range [0.

Introduced in PTX ISA version 1.b32 foo. Supported on all target architectures.visible Table 143.visible identifier Declares identifier to be externally visible.extern . .0.extern .6. Linking Directives: . .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. 2010 . // foo is defined in another module Table 144.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.global . . Supported on all target architectures.visible .b32 foo.PTX ISA Version 2. // foo will be externally visible 168 January 24.extern . Linking Directives . Linking Directives: .0 10.visible .global . Introduced in PTX ISA version 1.extern identifier Declares identifier to be defined externally. .0.

The first section describes ISA and implementation changes in the current release of PTX ISA 2.1 PTX ISA 1.5 PTX ISA 2.0 driver r195 PTX ISA Version PTX ISA 1.4 PTX ISA 1.2 PTX ISA 1.0 CUDA 1.3 PTX ISA 1. 2010 169 .1 CUDA 2. The release history is as follows.0 January 24.Chapter 11. CUDA Release CUDA 1.3 driver r190 CUDA 3. and the remaining sections provide a record of changes in previous releases. Release Notes This section describes the history of change in the PTX ISA and implementation.0 PTX ISA 1.2 CUDA 2.1 CUDA 2.0 CUDA 2.0.

rcp. The goal is to achieve IEEE 754 compliance wherever possible.1. The mad.f32 maps to fma.1. and sqrt with IEEE 754 compliant rounding have been added. and mul now support .f32 for sm_20 targets. The mad.ftz modifier may be used to enforce backward compatibility with sm_1x.0 11. New Features 11.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The .0 11. These are indicated by the use of a rounding modifier and require sm_20. The changes from PTX ISA 1.sat modifiers. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 and mad. Single. When code compiled for sm_1x is executed on sm_20 devices. Instructions testp and copysign have been added. Changes in Version 2.rm and . mad.f32 instruction also supports .PTX ISA Version 2. Both fma. • • • • • 170 January 24. The fma.1.1.ftz and .f32.1. A single-precision fused multiply-add (fma) instruction has been added.and double-precision div.rp rounding modifiers for sm_20 targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. 2010 .f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. while maximizing backward compatibility with legacy PTX 1.rn.x code and sm_1x targets.f32 require a rounding modifier for sm_20 targets.0 for sm_20 targets. Single-precision add. Floating-Point Extensions This section describes the floating-point changes in PTX 2. fma.f32 requires sm_20. sub.1.

The .ballot.red. prefetchu. have been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.shared have been extended to handle 64-bit data types for sm_20 targets. cvta. has been added. Instructions bar. and shared addresses to generic address and vice-versa has been added.clamp and .Chapter 11.1.lt. ldu. brev. A “find leading non-sign bit” instruction.3. bfind. bar now supports optional thread count and register operands. has been added.add.1.red}. 2010 171 . vote.f32 have been implemented. and red now support generic addressing.1. has been added. A new directive.gt} have been added. has been added. suld.g.maxnctapersm directive was deprecated and replaced with . . A “count leading zeros” instruction. isspacep. local.1.pred have been added.ge.clamp modifiers. Cache operations have been added to instructions ld. clz. Instruction sust now supports formatted surface stores.sys. Video instructions (includes prmt) have been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.u32 and bar. %clock64. has been added. The bar instruction has been extended as follows: • • • A bar. has been added. New special registers %nsmid.popc. Bit field extract and insert instructions.arrive instruction has been added. A “population count” instruction.2. A system-level membar instruction. e. A “vote ballot” instruction. ldu. Instruction cvta for converting global.zero. popc. .{and. st. prefetch. st.section. 11. Release Notes 11. Instructions prefetch and prefetchu have also been added. bfe and bfi. and sust.b32. %lanemask_{eq. Surface instructions support additional .or}.red. Instructions {atom.red}. membar. atom. A “bit reversal” instruction.le. for prefetching to specified level of memory hierarchy. January 24.minnctapersm to better match its behavior and usage. Instructions {atom. New instructions A “load uniform” instruction. Other new features Instructions ld. has been added.

{atom. Formatted surface store with .5 and later.u32.1.1.p.red}. where .ftz (and cvt for . where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.{u32. the correct number is sixteen.ftz for PTX ISA versions 1.{min.4 and earlier. stack-based ABI is unimplemented.target sm_1x. Instruction bra. 172 January 24. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.s32.4 or earlier.3. The underlying. has been fixed. or .ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types. See individual instruction descriptions for details.f32. Support for variadic functions and alloca are unimplemented. if . .0 11. call suld. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.version is 1. In PTX version 1.max} are not implemented.f32 type is unimplemented. To maintain compatibility with legacy PTX code. cvt. Semantic Changes and Clarifications The errata in cvt. 11.PTX ISA Version 2. Formatted surface load is unimplemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. 2010 .2.s32.p sust. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.f32} atom.5.

pragma “nounroll”. disables unrolling of0 the loop for which the current block is the loop header.pragma.pragma strings defined by ptxas.pragma Strings This section describes the .func bar (…) { … L1_head: . Table 145. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. L1_end: … } // do not unroll this loop January 24. . . disables unrolling for all loops in the entry function body. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. Note that in order to have the desired effect at statement level.entry foo (…) . with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Supported only for sm_20 targets. Descriptions of . and statement levels.0.pragma “nounroll”. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. including loops preceding the .pragma “nounroll”. 2010 173 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The “nounroll” pragma is allowed at module. L1_body: … L1_continue: bra L1_head. Ignored for sm_1x targets. { … } // do not unroll any loop in this function .Appendix A. entry-function. … @p bra L1_end.

2010 .PTX ISA Version 2.0 174 January 24.

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