NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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...............1....2.........................1............................ 37 Array Declarations ... 6..............4.......................... 39 Parameterized Variable Names ..... 5................................................... 28 Constant State Space ...... 34 Variables ...................................................2....................... 5..... Arrays..... 5....... 6.....4............................................1............... 5........................................................................ 44 Scalar Conversions ........ 5................................ 44 Rounding Modifiers ......1..............................................................................................3......... Operand Type Information . 27 5........................... Abstracting the ABI .................1..... 5.......................................................1..................1.................4..... 5..5.......................... 38 Initializers ............... State Spaces ........4. 6.............. Types............................................................................................. Types .......5. and Surface Types ........ 28 Special Register State Space ............................................... 6............ 47 Chapter 7..............4................................................................6...................................3. 6...................................... 5....................................................................................................... 43 Vectors as Operands ......4.. 41 Destination Operands ................. 5...... 33 5.....................................4................................7.....................................1......................... 5.................................................................8............................................. 37 Vectors .................... 32 5..................... 42 Addresses as Operands ............2... 6................................PTX ISA Version 2.. 6........................ 5............ Function declarations and definitions .......................3............................................................4.......................6.....................................................1..... 25 Chapter 5. State Spaces............4..1.................................4.............................................................0 4...........................................................................................2...1........................ Instruction Operands. 5........4.........................................................3............................. 49 7..............................1........................................... 27 Register State Space ..... 32 Texture State Space (deprecated) ............... 2010 .................4......... Sampler.1.......2.................... Type Conversion.........................2...........5.................................. 5..........5.............. Texture............................................... 29 Parameter State Space .................... 49 ii January 24......5.....................4........ 38 Alignment ........................................... 6.............................. 29 Global State Space ............................. 6................... 39 5.............2........................................................ 41 Source Operands..................................................4................... 33 Restricted Use of Sub-Word Sizes ... 41 6.............................2........... 42 Arrays as Operands ............................................................................... Chapter 6.......... 5...........................1.......... 5.......2.......1.................. 41 Using Addresses......5............4..................... 5....................3........................................................................................................... 43 6................... Operand Costs ....................................................... 30 Shared State Space.6.............. 46 6...................................................................... 33 Fundamental Types ...............................1..................................................................... Summary of Constant Expression Evaluation Rules .............. 43 Labels and Function Names as Operands ..................................................................................................................... and Vectors ... 37 Variable Declarations ................................... and Variables .......6................. 29 Local State Space ..

............................. 108 Texture and Surface Instructions ...........5...................................... 62 Semantics ........ Changes in Version 2...................7.. 52 Variadic functions ................... 8..... 53 Alloca .......................................................................6................................ Chapter 9......................... 8..................................... Instructions ............................................................................1.............................2....... Release Notes .............................................................................................................................................................. Special Registers ..................... Divergence of Threads in Control Constructs .................................................7.2.......................3............7............................................................................ 8........ 100 Logic and Shift Instructions ..7............ Type Information for Instructions and Operands ................... 2010 iii .......................................1......................... 8.... 58 8.....7....................... 122 Control Flow Instructions ......................................2.......... 166 Linking Directives ..............................................4................... 8....4........................................................................... 8................. 81 Comparison and Selection Instructions .................................. 56 Comparisons ......................... 8................6................................................................. 62 Machine-Specific Semantics of 16-bit Code .......7..3.... 8...........1..............................................................................x .............. 54 Chapter 8....................................7.....9...... 162 Debugging Directives ............................................. 11.............. 62 8....2. 168 Chapter 11.....................6......2................................ 10.......................... 57 Manipulating Predicates ....................... 157 Specifying Kernel Entry Points and Functions ........................... Instruction Set ............... PTX Version and Target Directives ................. 160 Performance-Tuning Directives ..... 8........................ 7........... 10............................ 147 8.. Directives ........ 60 8......................................... 172 January 24...............7....... 132 Video Instructions ............................................................1................................................ 8...........................................1............ 55 8..............................8............................. 11........................................3.......................1.1........................ 8..10...........7....3... 8........7................................................................................5......................... Changes from PTX 1...............7................................. 170 New Features .............................. 129 Parallel Synchronization and Communication Instructions ..7............................................3.... 55 PTX Instructions ..1............3............1............... Format and Semantics of Instruction Descriptions ................................................ 172 Unimplemented Features Remaining ................................................... 63 Integer Arithmetic Instructions ................................................................................................. 157 10....... 11............. 169 11. 59 Operand Size Exceeding Instruction-Type Size . 8..............................1.... 8..............................................4... 149 Chapter 10... 140 Miscellaneous Instructions......1........................................4.................................. 7...................................................2................ 55 Predicated Execution ....... 8....... 63 Floating-Point Instructions .................... 10.......1.............................1.......................................................................................... 8........... 104 Data Movement and Conversion Instructions ...7.....................................3.....0 ............. 170 Semantic Changes and Clarifications ................6................................................................................. 10.......

...........................0 Appendix A...... 2010 ..PTX ISA Version 2...pragma Strings........... 173 iv January 24........... Descriptions of ........

........................................................................................................ Table 8................. Table 7............... Table 25....................................................................... Table 19......................List of Tables Table 1............... Table 30........... 20 Operator Precedence .................................................................................................................................................................................................................................................................. Table 2................................... 66 Integer Arithmetic Instructions: subc .............. Table 31.............................. 64 Integer Arithmetic Instructions: add...................................................... 47 Operators for Signed Integer....... Table 28............................. 45 Floating-Point Rounding Modifiers .......................................................................... 60 Relaxed Type-checking Rules for Destination Operands................... 69 Integer Arithmetic Instructions: mad24 ......... Table 16.................................................................................... Table 20............................................ 35 Opaque Type Fields in Independent Texture Mode ...... 70 Integer Arithmetic Instructions: sad .... 57 Floating-Point Comparison Operators Accepting NaN ....................... Table 13.................. 65 Integer Arithmetic Instructions: sub..... Table 4............................................ Table 9.......... Table 24.......... 61 Integer Arithmetic Instructions: add ......... 18 Reserved Instruction Keywords ..................................... Unsigned Integer...................... Table 32................................................................... Table 11........... 66 Integer Arithmetic Instructions: mul .................................................................................. 59 Relaxed Type-checking Rules for Source Operands ...................... Table 27........................................................................................................................................ 2010 v ............................................. 58 Floating-Point Comparison Operators Testing for NaN ..................................................... Table 14............ Table 26.... 35 Convert Instruction Precision and Format ...............cc .............................................................................cc .......... 65 Integer Arithmetic Instructions: addc .......................... 57 Floating-Point Comparison Operators .................................................... 58 Type Checking Rules .... and Bit-Size Types .......................................... Table 10............... Table 29..... 46 Integer Rounding Modifiers ........................................ Table 6............................... Table 12.......... Table 5...................... Table 17.. Table 15..................................................................................... Table 23........................................................................... Table 18.................. 25 State Spaces .. Table 21................................ 27 Properties of State Spaces .......................................... 68 Integer Arithmetic Instructions: mul24 ............................ Table 3..................... 19 Predefined Identifiers ............. 67 Integer Arithmetic Instructions: mad ....... PTX Directives ..................................... 23 Constant Expression Evaluation Rules ... 33 Opaque Type Fields in Unified Texture Mode ......... 71 January 24.. Table 22...................... 64 Integer Arithmetic Instructions: sub ............ 46 Cost Estimates for Accessing State-Spaces ............................ 28 Fundamental Type Specifiers ...........

........ 83 Floating-Point Instructions: copysign .................................................. Table 62..............PTX ISA Version 2....................................... 83 Floating-Point Instructions: add ........................... 77 Integer Arithmetic Instructions: bfi ........................................... 79 Summary of Floating-Point Instructions . 96 Floating-Point Instructions: cos ....................................... 86 Floating-Point Instructions: fma .................................................................................... 71 Integer Arithmetic Instructions: rem ................................................... 94 Floating-Point Instructions: rsqrt ............................. 88 Floating-Point Instructions: div ......................................................................... Table 36....... 74 Integer Arithmetic Instructions: bfind ................................................................................. Table 63................................................................... 73 Integer Arithmetic Instructions: max ............................................................................................................ Table 61......................................................................................................................... Table 40............ 85 Floating-Point Instructions: mul ............ Table 58.................. 75 Integer Arithmetic Instructions: brev ................................................ Table 52........... Table 37..................... 92 Floating-Point Instructions: rcp ........ 74 Integer Arithmetic Instructions: clz ................ Table 41....0 Table 33...................... Table 45........................................ 92 Floating-Point Instructions: max .... Table 34............................................................................................................................................. 103 Comparison and Selection Instructions: slct ............... Table 55....................................... 87 Floating-Point Instructions: mad ........................................................... Table 42......................................................... Integer Arithmetic Instructions: div .......... 2010 . 91 Floating-Point Instructions: neg ............................................... 78 Integer Arithmetic Instructions: prmt ................................. 95 Floating-Point Instructions: sin .................................................................................................. Table 59......................... Table 44............................ Table 65.. 82 Floating-Point Instructions: testp ............... Table 67.......... 72 Integer Arithmetic Instructions: min ................. 90 Floating-Point Instructions: abs .................................................................................................................................... 71 Integer Arithmetic Instructions: abs ........................................................ 97 Floating-Point Instructions: lg2 .. 72 Integer Arithmetic Instructions: neg .. Table 57........................................... 103 vi January 24................................................................................................................................ Table 49............................. Table 60............. Table 66........................................................ 73 Integer Arithmetic Instructions: popc .............................................................. Table 38..... Table 69.......... Table 48........................................................................................ 102 Comparison and Selection Instructions: selp .................................................... Table 43..... Table 64................................................ 98 Floating-Point Instructions: ex2 ....... Table 39...... 91 Floating-Point Instructions: min ............................................. Table 51.... Table 50............... Table 54.................... Table 68............................................................. Table 35................................ Table 53................................. Table 47....................................... 93 Floating-Point Instructions: sqrt ...................................... Table 46................................... Table 56................................................. 84 Floating-Point Instructions: sub ................. 101 Comparison and Selection Instructions: setp .. 99 Comparison and Selection Instructions: set ............... 76 Integer Arithmetic Instructions: bfe ........

................... 143 January 24.......................... Table 80.. vmin........ 119 Data Movement and Conversion Instructions: cvt .......................................... Table 84.......................................... 106 Logic and Shift Instructions: shl ............................................................................................ 118 Data Movement and Conversion Instructions: isspacep .................................................... Table 81....................... Logic and Shift Instructions: and ............. Table 74........ 130 Control Flow Instructions: call ............. 129 Control Flow Instructions: @ ............................................................................ Table 83.................................. vabsdiff....Table 70........................ Table 91................................................................. Table 106................ Table 86.... Table 89........................... Table 103.... 131 Parallel Synchronization and Communication Instructions: bar ............................. 2010 vii .............. Table 101............................ prefetchu .......................... 111 Data Movement and Conversion Instructions: mov ............... 106 Logic and Shift Instructions: cnot ....... 127 Texture and Surface Instructions: suq ................. vsub... Table 71...................................................................................................... 110 Data Movement and Conversion Instructions: mov ................................................. 135 Parallel Synchronization and Communication Instructions: red ...... 131 Control Flow Instructions: exit .............................................. Table 104.. vshr .. Table 90............ Table 82................... Table 97...... Table 105.................................................... 107 Logic and Shift Instructions: shr .................... 106 Logic and Shift Instructions: not ......................................... 133 Parallel Synchronization and Communication Instructions: membar .................. 129 Control Flow Instructions: bra ........................ 116 Data Movement and Conversion Instructions: prefetch...... Table 100......................................................................... Table 72................ 142 Video Instructions: vshl...................................................................... 124 Texture and Surface Instructions: suld .............. Table 92............ Table 94.......... 139 Video Instructions: vadd.. Table 99................... Table 95..................... Table 98.................... 109 Cache Operators for Memory Store Instructions ................................. 113 Data Movement and Conversion Instructions: ldu .................. Table 96.... Table 75.......... Table 77................................................. vmax ......... 105 Logic and Shift Instructions: or ......................... Table 79............ 134 Parallel Synchronization and Communication Instructions: atom .................................................................................... 126 Texture and Surface Instructions: sured.................. Table 76........................................................................................................ 112 Data Movement and Conversion Instructions: ld ............. 130 Control Flow Instructions: ret .. Table 85....................................................................................... Table 87............ Table 88... Table 93............... Table 73.......... 115 Data Movement and Conversion Instructions: st .............. 120 Texture and Surface Instructions: tex ................................... 125 Texture and Surface Instructions: sust .......................................... Table 78.............................................. 137 Parallel Synchronization and Communication Instructions: vote .. 128 Control Flow Instructions: { } ....... 107 Cache Operators for Memory Load Instructions ............................ 119 Data Movement and Conversion Instructions: cvta ..................................... 105 Logic and Shift Instructions: xor ....................................... 123 Texture and Surface Instructions: txq ............... Table 102.............................................................

.................... 156 Special Registers: %pm0....................................................................................................................... Table 141......................... Table 135........... Table 134.................... 158 Kernel and Function Directives: ............. 151 Special Registers: %nwarpid ......................... 153 Special Registers: %gridid ......................................... 164 Performance-Tuning Directives: .............................................maxntid ...................... 167 Linking Directives: ............................. Table 131................................ 147 Miscellaneous Instructions: brkpt ................................... Table 143................ 156 PTX File Directives: ...............entry.................................... Table 120......................... 168 viii January 24........................................................................... %pm1.func ...... 147 Miscellaneous Instructions: pmevent. Table 127.version....................target ................... %pm3 ................ Table 133.............. Table 132............................... Table 125..............................................0 Table 107............... Table 129...................................................PTX ISA Version 2........ 156 Special Registers: %clock64 ....................... Table 138........................ Table 113................. 154 Special Registers: %lanemask_le .................................................................. 163 Performance-Tuning Directives: .......................... Table 118...... 152 Special Registers: %nctaid ...................... 166 Debugging Directives: ................... Table 128...........pragma ..section ....................maxnctapersm (deprecated) .................................................................. 150 Special Registers: %ntid ........... Table 137.... 164 Performance-Tuning Directives: ............... Table 142........................................................ 165 Debugging Directives: @@DWARF .... 163 Performance-Tuning Directives: ......... 155 Special Registers: %clock .................... Table 111....................................... 160 Kernel and Function Directives: ........................................... Table 108.................................................... 154 Special Registers: %lanemask_ge ................. 151 Special Registers: %ctaid ........................................................ 150 Special Registers: %laneid ........................................................................... Table 139........................ Table 114......................... 152 Special Registers: %smid ................................ Table 112.. Table 110.............. Table 116..............maxnreg .............................................................................................. 2010 ..............................file .......... Table 117............................................................................ 167 Debugging Directives: ......................................... Table 124...........................loc ....................... Table 140................................................ %pm2.................................................................................................................. 153 Special Registers: %lanemask_eq .. Table 119........ 155 Special Registers: %lanemask_gt .... Table 109.............................................. 157 PTX File Directives: ..........................................minnctapersm ... 167 Debugging Directives: ................................................................. 161 Performance-Tuning Directives: .............. Table 122....................................... Table 123......................................................................... Table 130..... Table 126....................................extern..................................................................................... 151 Special Registers: %warpid .... Video Instructions: vmad ............... Table 136........................................ Table 121............................................ 147 Special Registers: %tid ......................................... 144 Video Instructions: vset.. 153 Special Registers: %nsmid .. Table 115.... 146 Miscellaneous Instructions: trap .......................... 154 Special Registers: %lanemask_lt ..............................

...... Table 145..............Table 144.......visible........... Linking Directives: .... 2010 ix ........ 173 January 24........................................................... 168 Pragma Strings: “nounroll” ..............................................................

PTX ISA Version 2.0 x January 24. 2010 .

and because it is executed on many data elements and has high arithmetic intensity. image scaling. high-definition 3D graphics. Introduction This document describes PTX.1. from general signal processing or physics simulation to computational finance or computational biology. PTX defines a virtual machine and ISA for general purpose parallel thread execution. PTX exposes the GPU as a data-parallel computing device. and pattern recognition can map image blocks and pixels to parallel processing threads. image and media processing applications such as post-processing of rendered images.Chapter 1. the programmable GPU has evolved into a highly parallel. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. In fact. Data-parallel processing maps data elements to parallel processing threads. the memory access latency can be hidden with calculations instead of big data caches. stereo vision.2. which are optimized for and translated to native target-architecture instructions. there is a lower requirement for sophisticated flow control. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Because the same program is executed for each data element. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. many-core processor with tremendous computational horsepower and very high memory bandwidth. Similarly. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). video encoding and decoding. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. January 24. PTX programs are translated at install time to the target hardware instruction set. 1. 1. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. 2010 1 . multithreaded.

• • • 2 January 24. A single-precision fused multiply-add (fma) instruction has been added. Provide a common source-level ISA for optimizing code generators and translators.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. Instructions marked with . Facilitate hand-coding of libraries.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.x features are supported on the new sm_20 target. including integer.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.sat modifiers. The fma. barrier. The mad. performance kernels.f32 for sm_20 targets.PTX ISA Version 2.0 is a superset of PTX 1. sub.3.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.3. addition of generic addressing to facilitate the use of general-purpose pointers. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.ftz) modifier may be used to enforce backward compatibility with sm_1x. and architecture tests.f32 requires sm_20. Improved Floating-Point Support A main area of change in PTX 2.x code will continue to run on sm_1x targets as well. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rn. 2010 . A “flush-to-zero” (.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.f32. The changes from PTX ISA 1. Achieve performance in compiled applications comparable to native GPU performance.ftz and . Provide a machine-independent ISA for C/C++ and other compilers to target.1. Most of the new features require a sm_20 target. surface.f32 instruction also supports .0 is in improved support for the IEEE 754 floating-point standard. atomic.f32 and mad. fma. memory. Provide a code distribution ISA for application and middleware developers.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Legacy PTX 1. which map PTX to specific target machines. 1.rp rounding modifiers for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices. and mul now support . extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables. and all PTX 1. Both fma.0 PTX ISA Version 2. PTX 2.rm and . and video instructions. The mad. 1. The main areas of change in PTX 2.f32 require a rounding modifier for sm_20 targets.0 are improved support for IEEE 754 floating-point operations. mad.f32 maps to fma.x. Single-precision add. PTX ISA Version 2. reduction. and the introduction of many new instructions.

stack-based ABI.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.4. January 24. st. . Introduction • Single.3. 1. prefetch. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. NOTE: The current version of PTX does not implement the underlying. an address that is the same across all threads in a warp.0 closer to full compliance with the IEEE 754 standard. ldu. These are indicated by the use of a rounding modifier and require sm_20.zero. stack layout.g. these changes bring PTX 2. Instruction cvta for converting global. local. Surface instructions support additional clamp modifiers.clamp and . instructions ld.0. In PTX 2. and red now support generic addressing. Instructions prefetch and prefetchu have been added. A new cvta instruction has been added to convert global. for prefetching to specified level of memory hierarchy. Instructions testp and copysign have been added. 2010 3 . PTX 2. Generic Addressing Another major change is the addition of generic addressing. and directives are introduced in PTX 2. and vice versa. st. atom.3.3.3. suld. allowing memory instructions to access these spaces without needing to specify the state space. and sqrt with IEEE 754 compliant rounding have been added. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Support for an Application Binary Interface Rather than expose details of a particular calling convention. and shared addresses to generic address and vice-versa has been added. New Instructions The following new instructions. cvta.and double-precision div. Generic addressing unifies the global. 1.. and shared addresses to generic addresses. Surface Instructions • • Instruction sust now supports formatted surface stores. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. prefetchu. 1. isspacep. and Application Binary Interface (ABI). and sust. local.0.Chapter 1. rcp. so recursion is not yet supported. Cache operations have been added to instructions ld. i. special registers. local. and shared state spaces. • Taken as a whole.e.2. e.

has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. bar now supports an optional thread count and register operands. .red.or}.pred have been added.red}.sys.{and.b32.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. 2010 . 4 January 24. Barrier Instructions • • A system-level membar instruction.popc. vote. and Vote Instructions • • • New atomic and reduction instructions {atom.ballot. %clock64. A bar. New special registers %nsmid.red. membar.PTX ISA Version 2.red}.gt} have been added. Instructions {atom.lt. bfi bit field extract and insert popc clz Atomic. has been added. has been added.shared have been extended to handle 64-bit data types for sm_20 targets. A new directive.u32 and bar.arrive instruction has been added. Reduction. A “vote ballot” instruction.add. Instructions bar.section.le.ge.f32 have been added. %lanemask_{eq. Other Extensions • • • Video instructions (includes prmt) have been added.

Chapter 8 describes the instruction set.0. and PTX support for abstracting the Application Binary Interface (ABI). The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. January 24. Chapter 6 describes instruction operands. Chapter 7 describes the function and call syntax. Chapter 10 lists the assembly directives supported in PTX. Chapter 11 provides release notes for PTX Version 2. and variable declarations. calling convention. Introduction 1. Chapter 5 describes state spaces. Chapter 4 describes the basic syntax of the PTX language. Chapter 3 gives an overview of the PTX virtual machine model.4. types. Chapter 9 lists special registers. 2010 5 .Chapter 1.

0 6 January 24.PTX ISA Version 2. 2010 .

Threads within a CTA can communicate with each other. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. 2.x. or CTA. The vector ntid specifies the number of threads in each CTA dimension. 2D. a portion of an application that is executed many times. and select work to perform. Cooperative thread arrays (CTAs) implement CUDA thread blocks. or host: In other words. but independently on different data. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. Programming Model 2.Chapter 2. Programs use a data parallel decomposition to partition inputs. assign specific input and output positions. To coordinate the communication of the threads within the CTA. is an array of threads that execute a kernel concurrently or in parallel. data-parallel. tid.z) that specifies the thread’s position within a 1D.z). compute-intensive portions of applications running on the host are off-loaded onto the device. 2010 7 . Each CTA thread uses its thread identifier to determine its assigned role.2. It operates as a coprocessor to the main CPU. and ntid. work. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Each thread has a unique thread identifier within the CTA.x. compute addresses. one can specify synchronization points where threads wait until all threads in the CTA have arrived. ntid. (with elements tid. More precisely. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.1. can be isolated into a kernel function that is executed on the GPU as many different threads. The thread identifier is a three-element vector tid. Each CTA has a 1D. 2. January 24.1. or 3D shape specified by a three-element vector ntid (with elements ntid. or 3D CTA. and results across the threads of the CTA. A cooperative thread array. and tid.y. To that effect.y.2. 2D. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.

read-only special registers %tid.PTX ISA Version 2. or sequentially. A warp is a maximal subset of threads from a single CTA. depending on the platform. The host issues a succession of kernel invocations to the device. 2D . or 3D shape specified by the parameter nctaid. so PTX includes a run-time immediate constant. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain.2. Threads may read and use these values through predefined. 8 January 24. %nctaid. Each grid of CTAs has a 1D. a warp has 32 threads. This comes at the expense of reduced thread communication and synchronization. Threads within a warp are sequentially numbered. 2010 . because threads in different CTAs cannot communicate and synchronize with each other. so that the total number of threads that can be launched in a single kernel invocation is very large. WARP_SZ. The warp size is a machine-dependent constant. such that the threads execute the same instructions at the same time. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. 2.0 Threads within a CTA execute in SIMT (single-instruction. However. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). which may be used in any instruction where an immediate operand is allowed.2. multiple-thread) fashion in groups called warps. %ntid. and %gridid. Multiple CTAs may execute concurrently and in parallel. %ctaid. Typically. Some applications may be able to maximize performance with knowledge of the warp size. Each grid also has a unique temporal grid identifier (gridid). CTAs that execute the same kernel can be batched together into a grid of CTAs.

Chapter 2. 2) Thread (2. 0) Thread (2. 1) Thread (0. 1) Thread (1. 0) CTA (1. 2) Thread (4. 0) CTA (2. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 1) CTA (2. 0) Thread (0. A grid is a set of CTAs that execute independently. Thread Batching January 24. 2010 9 . 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (3. 0) Thread (1. 2) Thread (1. 1) Thread (2. 1) Thread (0. 0) CTA (0. Figure 1. 0) Thread (4. 1) Thread (4. 1) Thread (3. 1) CTA (1.

for more efficient transfer. The device memory may be mapped and read or written by the host. all threads have access to the same global memory.3. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. referred to as host memory and device memory. or. 10 January 24.PTX ISA Version 2. 2010 . constant. for some specific data formats. Both the host and the device maintain their own local memory. constant.0 2. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. The global. respectively. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. and texture memory spaces are persistent across kernel launches by the same application. Texture memory also offers different addressing modes. Each thread has a private local memory. and texture memory spaces are optimized for different memory usages. as well as data filtering. The global. Finally.

0) Block (2. 2) Block (1. 1) Grid 1 Global memory Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 2010 11 . 2) Figure 2. 1) Block (1. Memory Hierarchy January 24.Chapter 2. 0) Block (1. 0) Block (1. 1) Block (2. 1) Block (1. 0) Block (0. 0) Block (0. 1) Block (0.

PTX ISA Version 2.0 12 January 24. 2010 .

) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. and on-chip shared memory. When a host program invokes a kernel grid. and each scalar thread executes independently with its own instruction address and register state. As thread blocks terminate. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. allowing. the first parallel thread technology. The multiprocessor maps each thread to one scalar processor core. It implements a single-instruction barrier synchronization. If threads of a warp diverge via a data-dependent conditional branch. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). manages. the threads converge back to the same execution path. The multiprocessor creates. it splits them into warps that get scheduled by the SIMT unit. so full efficiency is realized when all threads of a warp agree on their execution path. a cell in a grid-based computation). new blocks are launched on the vacated multiprocessors. schedules. Branch divergence occurs only within a warp. 2010 13 . a voxel in a volume. a multithreaded instruction unit.1. multiple-thread). increasing thread IDs with the first warp containing thread 0. At every instruction issue time. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and executes threads in groups of parallel threads called warps.Chapter 3. (This term originates from weaving. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. manages. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. and when all paths complete. different warps execute independently regardless of whether they are executing common or disjointed code paths. To manage hundreds of threads running several different programs. the multiprocessor employs a new architecture we call SIMT (single-instruction. Parallel Thread Execution Machine Model 3. and executes concurrent threads in hardware with zero scheduling overhead. The threads of a thread block execute concurrently on one multiprocessor. The multiprocessor SIMT unit creates. January 24. The way a block is split into warps is always the same. disabling threads that are not on that path. When a multiprocessor is given one or more thread blocks to execute. the warp serially executes each branch path taken. each warp contains threads of consecutive. for example. A multiprocessor consists of multiple Scalar Processor (SP) cores. A warp executes one common instruction at a time.

SIMT enables programmers to write thread-level parallel code for independent. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. A key difference is that SIMD vector organizations expose the SIMD width to the software. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. A multiprocessor can execute as many as eight thread blocks concurrently. If an atomic instruction executed by a warp reads. as well as data-parallel code for coordinated threads. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. and writes to the same location in global memory for more than one of the threads of the warp. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. but one of the writes is guaranteed to succeed. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. whereas SIMT instructions specify the execution and branching behavior of a single thread. modify. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. In practice. the number of serialized writes that occur to that location and the order in which they occur is undefined. on the other hand. scalar threads. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. require the software to coalesce loads into vectors and manage divergence manually. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. 14 January 24. each read. modifies. 2010 . however.PTX ISA Version 2. the programmer can essentially ignore the SIMT behavior. In contrast with SIMD vector machines. which is a read-only region of device memory. which is a read-only region of device memory. write to that location occurs and they are all serialized. If there are not enough registers or shared memory available per multiprocessor to process at least one block. • The local and global memory spaces are read-write regions of device memory and are not cached. the kernel will fail to launch. Vector architectures. but the order in which they occur is undefined. For the purposes of correctness. As illustrated by Figure 3.0 SIMT architecture is akin to SIMD (Single Instruction.

Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24. 2010 15 . Figure 3.

PTX ISA Version 2.0 16 January 24. 2010 .

4.target directive specifying the target architecture assumed. The following are common preprocessor directives: #include. #line. Pseudo-operations specify symbol and addressing management. Source Format Source files are ASCII text. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. and using // to begin a comment that extends to the end of the current line. 4. Lines beginning with # are preprocessor directives. #if. The C preprocessor cpp may be used to process PTX source files. #endif.Chapter 4. Lines are separated by the newline character (‘\n’). The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. 2010 17 . followed by a . PTX is case sensitive and uses lowercase for keywords. #define. using non-nested /* and */ for comments that may span multiple lines. January 24. whitespace is ignored except for its use in separating tokens in the language. See Section 9 for a more information on these directives. All whitespace characters are equivalent. #ifdef. #else. Syntax PTX programs are a collection of text source files. Comments in PTX are treated as whitespace.1.2.version directive specifying the PTX language version. Comments Comments in PTX follow C/C++ syntax. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Each PTX file must begin with a .

array[r1]. and is written as @p. shl.tex .0 4.maxnreg . All instruction keywords are reserved tokens in PTX.maxnctapersm . ld.visible 4.version .shared . 18 January 24. where p is a predicate register.entry . .func .section . The destination operand is first.target .loc . Instruction keywords are listed in Table 2.global. address expressions. written as @!p. and terminated with a semicolon.global . r2.3.f32 array[N]. or label names. Statements A PTX statement is either a directive or an instruction.3. mov.minnctapersm . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4.b32 add.PTX ISA Version 2. 2. constant expressions. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. Examples: . Instructions have an optional guard predicate which controls conditional execution.3. . 0.pragma . The guard predicate may be optionally negated.b32 r1. The guard predicate follows the optional label and precedes the opcode.global start: .1.x.sreg . Statements begin with an optional label and end with a semicolon.maxntid . r2. Operands may be register variables.param .const . r2. followed by source operands.file PTX Directives . Directive Statements Directive keywords begin with a dot. so no conflict is possible with user-defined identifiers. %tid.reg .b32 r1.extern .2.b32 r1. Table 1.f32 r2. 2010 .local .align .reg . r1.5. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.

Syntax Table 2.Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .

or dollar characters.0 4. digits. digits. dollar. The percentage sign can be used to avoid name conflicts. or percentage character followed by one or more letters. %pm3 WARP_SZ 20 January 24. or they start with an underscore. except that the percentage sign is not allowed. Table 3. listed in Table 3. PTX allows the percentage sign as the first character of an identifier. e.4.PTX ISA Version 2. Many high-level languages such as C and C++ follow similar rules for identifier names. ….g. 2010 . %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. underscore. between user-defined variable names and compiler-generated names. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters.

The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. every integer constant has type .5. or binary notation..s64) unless the value cannot be fully represented in . 4. Syntax 4. To specify IEEE 754 doubleprecision floating point values. Type checking rules remain the same for integer. and bit-size types. 4.s64 or the unsigned suffix is specified.5. Floating-point literals may be written with an optional decimal point and an optional signed exponent. The syntax follows that of C.e. To specify IEEE 754 single-precision floating point values. i. hexadecimal. When used in an instruction or data initialization. floating-point.Chapter 4. For predicate-type data and instructions. zero values are FALSE and non-zero values are TRUE. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. there is no suffix letter to specify size.5. 0[fF]{hexdigit}{8} // single-precision floating point January 24. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. Unlike C and C++. octal. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.2. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. i.e. the constant begins with 0d or 0D followed by 16 hex digits.1.. Integer literals may be written in decimal. 2010 21 . in which case the literal is unsigned (. These constants may be used in data initialization and as operands to instructions. integer constants are allowed and are interpreted as in C. each integer constant is converted to the appropriate size based on the data or instruction type at its use. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.u64. the constant begins with 0f or 0F followed by 8 hex digits. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.u64). The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.s64 or . where the behavior of the operation depends on the operand types. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Constants PTX supports integer and floating-point constants and constant expressions. literals are always represented in 64-bit double-precision format.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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u64 . Table 5.f64 integer .s64 . .6.5.f64 integer . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 .u64.s64) + .u64 .u64) (.s64 .s64 . or .u64 .s64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 use usual conversions .s64.u64 same as 1st operand .f64 converted type constant literal + ! ~ Cast Binary (.u64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . 2nd is .s64 .f64 use usual conversions .f64 use usual conversions . Syntax 4.f64 : .f64 converted type .u64 1st unchanged.u64 .Chapter 4.s64 .s64 .s64 .f64 integer integer integer integer integer int ?.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 zero or non-zero same as sources use usual conversions Result Type same as source .f64 same as source . 2010 25 .

PTX ISA Version 2. 2010 .0 26 January 24.

All variables reside in some state space. Global memory.local . . and properties of state spaces are shown in Table 5. Name State Spaces Description Registers. State Spaces A state space is a storage area with particular characteristics. addressability. access speed.tex January 24. the kinds of resources will be common across platforms. 5.param . Types.sreg . and level of sharing between threads. read-only memory. platform-specific. shared by all threads. private to each thread. State Spaces.1. defined per-grid.global . Addressable memory shared between threads in 1 CTA. The list of state spaces is shown in Table 4. defined per-thread. Read-only.const . Global texture memory (deprecated). The characteristics of a state space include its size. or Function or local parameters. and these resources are abstracted in PTX through state spaces and data types.Chapter 5. fast.reg .shared . The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Table 6. 2010 27 . Local memory. Shared. Kernel parameters. Special registers. access rights. and Variables While the specific resources available in a given target GPU will vary. pre-defined.

predicate) or untyped. clock counters.1. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 2 Accessible via ld. and vector registers have a width of 16-.sreg) state space holds predefined.e. All special registers are predefined. st. the parameter is then located on the stack frame and its address is in the . The most common use of 8-bit registers is with ld. or 128-bits. When the limit is exceeded. 32-. and will vary from platform to platform. and cvt instructions. Register size is restricted.param (used in functions) .reg .local . Registers may be typed (signed integer.shared . or as elements of vector tuples.const . 1 Accessible only via the ld. 5.tex Restricted Yes No3 5. Special Register State Space The special register (.sreg . CTA.global . Address may be taken via mov instruction.local state space.param (as input to kernel) .0 Table 7. scalar registers have a width of 8-.1. or 64-bits.PTX ISA Version 2.param instructions. Register State Space Registers (. aside from predicate registers which are 1-bit. causing changes in performance. register variables will be spilled to memory. it is not possible to refer to the address of a register. and thread parameters. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. such as grid. 16-. i. 32-.. 64-.2. 3 Accessible only via the tex instruction. Device function input parameters may have their address taken via mov.reg state space) are fast storage locations.param and st. Registers differ from the other state spaces in that they are not fully addressable. For each architecture.1. unsigned integer. 2010 .param instruction. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details). floating point. 28 January 24. Registers may have alignment boundaries required by multi-word loads and stores. platform-specific registers. The number of registers is limited. and performance monitoring registers.

where the size is not known at compile time.const[2] . Banks are specified using the . All memory writes prior to the bar.1.b32 %r1.local and st. It is the mechanism by which different CTAs and different grids can communicate. Multiple incomplete array variables declared in the same bank become aliases.3. If no bank number is given. For example. // load second word 5.global.const[2]. as in lock-free and wait-free style programming. Module-scoped local memory variables are stored at fixed addresses. the store operation updating a may still be in flight. initialized by the host. For the current devices.local to access local variables. ld.local) is private memory for each thread to keep its own data. all addresses are in global memory are shared. where bank ranges from 0 to 10. Constant State Space The constant (. each pointing to the start address of the specified constant bank.sync instruction. b = b – 1. Global memory is not sequentially consistent.const) state space is a read-only memory. st. as it must be allocated on a perthread basis. bank zero is used.b32 const_buffer[]. Consider the case where one thread executes the following two assignments: a = a + 1. The remaining banks may be used to implement “incomplete” constant arrays (in C. an incomplete array in bank 2 is accessed as follows: .extern . This reiterates the kind of parallelism available in machines that run PTX. Threads wait at the barrier until all threads in the CTA have arrived. By convention. and atom.extern . Global State Space The global (.5.4.global) state space is memory that is accessible by all threads in a context. State Spaces. [const_buffer+4].b32 const_buffer[]. there are eleven 64KB banks. Threads must be able to do their work without waiting for other threads to do theirs. Local State Space The local state space (. If another thread sees the variable b change. and Variables 5.global to access global variables. Use ld. The size is limited. Types. For example. for example). This pointer can then be used to access the entire 64KB constant bank. the stack is in local memory. Use ld.1.const[bank] modifier. For any thread in a context. Sequential consistency is provided by the bar. bank zero is used for all statically-sized constant variables. The constant memory is organized into fixed size banks. results in const_buffer pointing to the start of constant bank two.1. In implementations that support a stack.Chapter 5. whereas local memory variables declared January 24. To access data in contant banks 1 through 10. 2010 29 . the declaration . Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.const[2] . the bank number must be provided in the state space of the load instruction.global. It is typically standard memory with cache.sync instruction are guaranteed to be visible to any reads after the barrier instruction. 5.

u32 %ptr. The resulting address is in the . Note that PTX ISA versions 1. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. … 30 January 24. ld. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).b8 buffer[64] ) { .reg . %n. 5.entry bar ( . … Example: .b32 N.param instructions. Similarly.u32 %n. Parameter State Space The parameter (. per-kernel versus per-thread). These parameters are addressable.param .param . device function parameters were previously restricted to the register state space.1. The address of a kernel parameter may be moved into a register using the mov instruction. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param space. all local memory variables are stored at fixed addresses and recursive function calls are not supported.align 8 . The use of parameter state space for device function parameters is new to PTX ISA version 2.f64 %d. No access protection is provided between parameter and global space in this case.1. typically for passing large structures by value to a function. Note: The location of parameter space is implementation specific. For example.b32 len ) { .1. [%ptr]. Values passed from the host to the kernel are accessed through these parameter variables using ld.param space variables.u32 %n.x supports only kernel function parameters in . .f64 %d.param instructions.param.param) state space is used (1) to pass input arguments from the host to the kernel. . read-only variables declared in the .param . The kernel parameter variables are shared across all CTAs within a grid.param state space. mov.param. len. Example: . [N].param.6. PTX code should make no assumptions about the relative locations or ordering of .u32 %n. 2010 .PTX ISA Version 2. ld. [buffer].entry foo ( .0 within a function or kernel body are allocated on the stack.0 and requires target architecture sm_20.reg .6. In implementations that do not support a stack. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.u32 %ptr. Therefore. in some implementations kernel parameters reside in global memory. ld.reg . 5. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param state space and is accessed using ld.

. Types.6.local and st. which declares a . January 24. Example: // pass object of type struct { double d. mystruct).reg . . Typically.param space variable. x. Device Function Parameters PTX ISA version 2. the address of a function input parameter may be moved into a register using the mov instruction. .s32 %y. . and Variables 5.0 extends the use of parameter space to device function parameters.s32 x. (4.align 8 .b8 mystruct. … st. dbl.2.param.local state space and is accessed via ld. Aside from passing structures by value. In this case.s32 %y. 2010 31 .local instructions. [buffer]. … } // code snippet from the caller // struct { double d.param . .param byte array variable that represents a flattened C structure or union.func foo ( . passed to foo … .reg .f64 %d. State Spaces.param.reg . [buffer+8]. and so the address will be in the .f64 dbl. It is not possible to use mov to get the address of a return parameter or a locally-scoped . This will be passed by value to a callee. . int y.param.param formal parameter having the same size and alignment as the passed argument. call foo.param. such as C structures larger than 8 bytes.reg . }. Note that the parameter will be copied to the stack if necessary. ld. a byte array in parameter space is used.1.param space is also required whenever a formal parameter has its address taken within the called function.f64 %d. int y. Function input parameters may be read via ld.reg .f64 [mystruct+0]. The most common use is for passing objects by value that do not fit within a PTX register. is flattened.param and function return parameters may be written using st. … See the section on function call syntax for more details. the caller will declare a locally-scoped .param.Chapter 5.align 8 .s32 [mystruct+8]. ld. In PTX. } mystruct. it is illegal to write to an input parameter or read from a return parameter.b32 N.param . st.b8 buffer[12] ) { .

3 for the description of the . It is shared by all threads in a context. The texture name must be of type .shared) state space is a per-CTA region of memory for threads in a CTA to share data.PTX ISA Version 2. Texture State Space (deprecated) The texture (. See Section 5. 2010 . Texture memory is read-only. 5.tex) state space is global memory accessed via the texture instruction.shared to access shared variables. An address in shared memory can be read and written by any thread in a CTA. where texture identifiers are allocated sequentially beginning with zero. tex_f.global state space. and variables declared in the .tex . The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). Shared memory typically has some optimizations to support the sharing. Multiple names may be bound to the same physical texture identifier. a legacy PTX definitions such as .6 for its use in texture instructions.1. An error is generated if the maximum number of physical resources is exceeded.global . One example is broadcast. and . is equivalent to .u32 tex_a.u32 or .tex variables are required to be defined in the global scope. The .u32 . Example: .texref variables in the .texref tex_a.texref. 32 January 24.u32 .1. Shared State Space The shared (.0 5.tex state space are equivalent to module-scoped .tex . where all threads read from the same address.tex .u32 tex_a.tex directive is retained for backward compatibility. and programs should instead reference texture memory through variables of type . tex_d. tex_d. Use ld. Another is sequential access from sequential threads.tex . The .u64.8.7.shared and st.tex directive will bind the named texture memory variable to a hardware texture identifier.texref type and Section 8. A texture’s base address is assumed to be aligned to a 16-byte boundary.7.u32 . tex_c.tex . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. For example. Physical texture resources are allocated on a per-module granularity.

2.2. 2010 33 .b16.u8. and cvt instructions.f16 floating-point type is allowed only in conversions to and from . In principle. stored. . . st. The bitsize type is compatible with any fundamental type having the same size. .1. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . Types. but typed variables enhance program readability and allow for better operand type checking.b8. The same typesize specifiers are used for both variable definitions and for typing instructions. all variables (aside from predicates) could be declared using only bit-size types. All floating-point instructions operate only on .s32.f64 types. so their names are intentionally short. January 24. or converted to other types and sizes.f32 and . Restricted Use of Sub-Word Sizes The . A fundamental type specifies both a basic type and a size.2. For convenience. State Spaces. The .f16. ld.f32 and . The following table lists the fundamental type specifiers for each basic type: Table 8.s8. Operand types and sizes are checked against instruction types for compatibility.f32.Chapter 5. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.u16.f64 . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. .u8.b8 instruction types are restricted to ld. Types 5. and . Fundamental Types In PTX. the fundamental types reflect the native data types supported by the target architectures. . . . Signed and unsigned integer types are compatible if they have the same size. stored.pred Most instructions have one or more type specifiers. and converted using regular-width registers.b32. . and instructions operate on these types.s16.s8.u64 .u32. 5. st. .2. so that narrow values may be loaded. For example. needed to fully specify instruction behavior. and Variables 5. Two fundamental types are compatible if they have the same basic type and are the same size. Register variables are always of a fundamental type.f64 types.b64 . . .s64 .

and de-referenced by texture and surface load.. sampler. accessing the pointer with ld and st instructions.texref type that describe sampler properties are ignored. 34 January 24. or performing pointer arithmetic will result in undefined results.3. opaque_var. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. 2010 . and . The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. sust.e. and overall size is hidden to a PTX program. . texture and sampler information is accessed through a single . store. In the independent mode. PTX has two modes of operation. but the pointer cannot otherwise be treated as an address. hence the term “opaque”. allowing them to be defined separately and combined at the site of usage in the program. Retrieving the value of a named member via query instructions (txq. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. field ordering. and Surface Types PTX includes built-in “opaque” types for defining texture. For working with textures and samplers. suq).texref. base address. These types have named fields similar to structures. and surface descriptor variables.samplerref variables.u64} reg. The following tables list the named members of each type for unified and independent texture modes. In independent mode the fields of the . In the unified mode. samplers. i. The three built-in types are .{u32. Creating pointers to opaque variables using mov. Sampler.0 5. since these properties are defined by . Referencing textures.texref handle. but all information about layout.PTX ISA Version 2.samplerref. Texture. suld.surfref. passed as a parameter to functions. the resulting pointer may be stored to and loaded from memory. or surfaces via texture and surface load/store instructions (tex. sured). and query instructions. texture and sampler information each have their own handle.

clamp_to_border N/A N/A N/A N/A N/A . linear wrap.samplerref values N/A N/A N/A N/A nearest. linear wrap. clamp_ogl. clamp_to_edge.texref values . mirror. clamp_ogl. 1 ignored ignored ignored ignored .Chapter 5. clamp_to_edge. and Variables Table 9.texref values in elements in elements in elements 0. Member width height depth Opaque Type Fields in Unified Texture Mode . Types. mirror. 2010 35 .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_border 0.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. State Spaces. 1 nearest. Member width height depth Opaque Type Fields in Independent Texture Mode .

.global .global . As kernel parameters.global . these variables must be in the .global . these variables are declared in the . filter_mode = nearest }.global state space.0 Variables using these types may be declared at module scope or within kernel entry parameter lists. At module scope. When declared at module scope.global .texref tex1. .samplerref my_sampler_name.surfref my_surface_name. .samplerref tsamp1 = { addr_mode_0 = clamp_to_border. Example: . the types may be initialized using a list of static expressions assigning values to the named members.param state space.PTX ISA Version 2. Example: . 36 January 24.texref my_texture_name. 2010 .

Vectors cannot exceed 128-bits in length.global .s32 i. .global .0}.v4. January 24. Vectors must be based on a fundamental type.shared .v1. and an optional fixed address for the variable. // typedef . r.v2 . and they may reside in the register space.reg .f32 v0. 0.f32 accel. 5. Examples: .global . // a length-4 vector of floats . // a length-2 vector of unsigned ints . // a length-4 vector of bytes By default. 0}.reg . State Spaces. . PTX supports types for simple aggregate objects such as vectors and arrays.u8 bg[4] = {0.v4 . . Predicate variables may only be declared in the register state space. for example. A variable declaration names the space in which the variable resides. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. its name.struct float4 coord. its type and size.reg . an optional initializer. where the fourth element provides padding.0. a variable declaration describes both the variable’s type and its state space. 2010 37 .4.global . . and Variables 5.v2 or . 0.u32 loc. Variables In PTX. 1.1.f64 is not allowed.v4 .f32 bias[] = {-1.pred p. This is a common case for three-dimensional grids. In addition to fundamental types.v4 vector.b8 v. 5. .global .v3 }.2. Types.const . Variable Declarations All storage for data is specified with variable declarations. etc.4. Every variable must reside in one of the state spaces enumerated in the previous section. an optional array size.struct float4 { . . vector variables are aligned to a multiple of their overall size (vector length times base-type size).4. textures.Chapter 5.v4.u16 uv. . q. Examples: . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . Three-element vectors may be handled by using a .f32 V. Vectors Limited-length vector types are supported.v2.v4 .

pred.u64. 0}.u8 mailbox[128]. Similarly.f16 and . while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). this can be used to statically initialize a pointer to a variable.shared .. .PTX ISA Version 2.. The size of the array specifies how many elements should be reserved.v4 . Array Declarations Array declarations are provided to allow the programmer to reserve space.0. 5. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. 38 January 24. // address of rgba into ptr Currently.3.1. 2010 .global .1}. being determined by an array initializer. {0. For the kernel declaration above.{. Examples: . or is left empty.0}}.global . Variables that hold addresses of variables or instructions should be of type . 0}.0. .0}.b32 ptr = rgba.4.0 5. {0. To declare an array.1. -1}.1.u32 or . .global . {0. Here are some examples: . where the variable name is followed by an equals sign and the initial value or values for the variable.f32 blur_kernel[][] = {{. this can be used to initialize a jump table to be used with indirect branches or calls.s32 offset[][] = { {-1. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.1.4.4.1.05}.0. .local . {1.global .global .. 19*19 (361) halfwords are reserved (722 bytes).4. Variable names appearing in initializers represent the address of the variable.. .u8 rgba[3] = {{1. label names appearing in initializers represent the address of the next instruction following the label.0}.0. Initializers are allowed for all types except ..05}}.05..u16 kernel[19][19]. {0. The size of the dimension is either a constant expression. variable initialization is supported only for constant and global state spaces. A scalar takes a single value. 1} }.05.{.s32 n = 10.

b32 variables. For arrays.5. The variable will be aligned to an address which is an integer multiple of byte-count. not for individual elements. The default alignment for vector variables is to a multiple of the overall vector size.b8 bar[8] = {0. // declare %r0. named %r0. alignment specifies the address alignment for the starting address of the entire array. ….4. and may be preceded by an alignment specifier. January 24. . %r99. say one hundred. State Spaces. %r1.Chapter 5.4. nor are initializers permitted.align 4 .2.. suppose a program uses a large number.b32 %r<100>..0.align byte-count specifier immediately following the state-space specifier. Rather than require explicit declaration of every name.0. of . The default alignment for scalar and array variables is to a multiple of the base-type size.0}. 2010 39 .reg .const . . Elements are bytes. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. %r1.0. Parameterized Variable Names Since PTX supports virtual registers. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. Types. 5. it is quite common for a compiler frontend to generate a large number of register names.0.0. Alignment is specified using an optional . Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. These 100 register variables can be declared as follows: . For example. and Variables 5. Examples: // allocate array at 4-byte aligned address.6. Array variables cannot be declared this way. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space..

PTX ISA Version 2.0 40 January 24. 2010 .

. PTX describes a load-store machine.Chapter 6.2. and a few instructions have additional predicate source operands. The cvt (convert) instruction takes a variety of operand types and sizes. January 24. 6. 6. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Each operand type must be compatible with the type determined by the instruction template and instruction type. Operand Type Information All operands in instructions have a known type from their declarations. Integer types of a common size are compatible with each other. There is no automatic conversion between types. s. the sizes of the operands must be consistent. The ld. The mov instruction copies data between registers. Instructions ld and st move data from/to addressable state spaces to/from registers. so operands for ALU instructions must all be in variables declared in the . Instruction Operands 6. r. Most instructions have an optional predicate guard that controls conditional execution. For most operations. The bit-size type is compatible with every type having the same size.1. and cvt instructions copy data from one location to another. Predicate operands are denoted by the names p.reg register state space. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. st. Source Operands The source operands are denoted in the instruction descriptions by the names a. mov. The result operand is a scalar or vector variable in the register state space.3. 2010 41 . as its job is to convert from nearly any data type to any other data type (and size). b. and c. q.

f32 W. Examples include pointer arithmetic and pointer comparisons. arrays. ld.u32 42 January 24.reg .v4 .reg . Using Addresses. Arrays.4.const.const .PTX ISA Version 2. Load and store operations move data between registers and locations in addressable state spaces. The address is an offset in the state space in which the variable is declared.reg . .global .reg . All addresses and address computations are byte-based. q.f32 ld. [tbl+12]. .shared. address register plus byte offset. The syntax is similar to that used in many assembly languages. tbl. and vectors. Address expressions include variable names. [V]. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.u16 r0. and Vectors Using scalar variables as operands is straightforward.s32 mov.shared .0 6.gloal. . there is no support for C-style pointer arithmetic. address registers.[x]. p. The interesting capabilities begin with addresses.1.f32 V.b32 p. . Here are a few examples: .4. . The mov instruction can be used to move the address of a variable into a pointer.v4.s32 tbl[256].s32 q. . where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.u16 ld. and immediate address expressions which evaluate at compile-time to a constant address. 6. W.u16 x. 2010 .v4 . r0.

d. a register variable.d}.g V. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.r V. ld. The registers in the load/store operations can be a vector. // move address of a[1] into s 6.f32 a. Examples are ld.x V.a 6.v2.reg .b and .4. [addr+offset2].a. for use in an indirect branch or call.u32 {a. b. or a braceenclosed list of similarly typed scalars. . V2.4.reg . .f32 V. Rd}.Chapter 6. a[1]. a[N-1]. where the offset is a constant expression that is either added or subtracted from a register variable.w.g. The size of the array is a constant in the program. . or a simple “register with constant offset” expression.u32 s. Instruction Operands 6. V. . 2010 43 . c.b.u32 s. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.b. Here are examples: ld.z and . which may improve memory performance.f32 {a.b V.y V. and tex. Vector elements can be extracted from the vector with the suffixes . ld.global.global. and the identifier becomes an address constant in the space where the array is declared. it must be written as an address calculation prior to use. mov.3.u32 s. January 24.2.x. . or by indexing into the array using square-bracket notation. Rc.d}.v4.4.f32 ld. Vector loads and stores can be used to implement wide loads and stores.global. Vectors as Operands Vector operands are supported by a limited subset of instructions. Elements in a brace-enclosed vector. st. a[0]. which include mov.r.y. mov.4. Vectors may also be passed as arguments to called functions.c. as well as the typical color fields . The expression within square brackets is either a constant integer. A brace-enclosed list is used for pattern matching to pull apart vectors. .w = = = = V. Arrays as Operands Arrays of all types can be declared. If more complicated indexing is desired. and in move instructions to get the address of the label or function into a register. [addr+offset].z V. Array elements can be accessed using an explicitly calculated byte address.global. Rb.c.v4 .v4. say {Ra.

Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.PTX ISA Version 2. 44 January 24.5. except for operations where changing the size and/or type is part of the definition of the instruction.5.1. 6. and data movement instruction must be of the same type and size. Type Conversion All operands to all arithmetic.000 for f16). For example. and ~131. logic.0 6. 2010 .u16 instruction is given a u16 source operand and s32 as a destination operand. if a cvt.s32. Operands of different sizes or types must be converted prior to the operation. the u16 is zero-extended to s32. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.

Chapter 6. s2f = signed-to-float. f2f = float-to-float. Instruction Operands Table 11. January 24. Notes 1 If the destination register is wider than the destination format. the result is extended to the destination register width after chopping. For example. f2s = float-to-signed. u2f = unsigned-to-float. chop = keep only low bits that fit. zext = zero-extend. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2u = float-to-unsigned. The type of extension (sign or zero) is based on the destination format. 2010 45 . cvt. then sign-extend to 32-bits.u32 targeting a 32-bit register will first chop to 16-bits.s16.

choosing even integer if source is equidistant between two integers. Modifier .2. Rounding Modifiers Conversion instructions may specify a rounding modifier.rm . In PTX. 2010 . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. there are four integer rounding modifiers and four floating-point rounding modifiers.PTX ISA Version 2.rn . The following tables summarize the rounding modifiers.rpi Integer Rounding Modifiers Description round to nearest integer. Modifier .0 6.rni .rmi . Table 12.5.rzi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rz .

Table 14. Table 11 gives estimates of the costs of using different kinds of memory.Chapter 6. Registers are fastest. first access is high Notes January 24. Instruction Operands 6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. while global memory is slowest. 2010 47 . Another way to hide latency is to issue the load instructions as early as possible. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. The register in a store operation is available much more quickly. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution.6. Much of the delay to memory can be hidden in a number of ways. Operand Costs Operands from different state spaces affect the speed of an operation.

2010 .0 48 January 24.PTX ISA Version 2.

The simplest function has no parameters or return values.Chapter 7. 2010 49 . The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. 7. stack-based ABI. NOTE: The current version of PTX does not implement the underlying. Scalar and vector base-type input and return parameters may be represented simply as register variables. and an optional list of input parameters. and return values may be placed directly into register variables. } … call foo. January 24. support for variadic functions (“varargs”). A function declaration specifies an optional list of return parameters.func foo { … ret. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. Abstracting the ABI Rather than expose details of a particular calling convention. function calls. Execution of the ret instruction within foo transfers control to the instruction following the call. the function name. A function must be declared or defined prior to being called. and is represented in PTX as follows: . These include syntax for function definitions. or prototype. Function declarations and definitions In PTX. together these specify the function’s interface. execution of the call instruction transfers control to foo. In this section. functions are declared and defined using the .func directive. we describe the features of PTX needed to achieve this hiding of the ABI. A function definition specifies both the interface and the body of the function.1. parameter passing. implicitly saving the return address. arguments may be register variables or constants. At the call. stack layout. … Here. and memory allocated on the stack (“alloca”). so recursion is not yet supported. and Application Binary Interface (ABI).

ld.param. c4.0 Example: .align 8 py[12]. Since memory accesses are required to be aligned to a multiple of the access size.reg . a . . st. %inc.c3.align 8 y[12]) { . The .b8 [py+ 9].b8 .b64 [py+ 0].c1. %rc2.s32 x. [y+10]. 2010 .b8 [py+10]. }. ld. %ptr.param . byte array in . passed by value to a function: struct { double dbl.param.reg . . ld.f64 field are aligned.b8 c2. %rc1. [y+9].u32 %res) inc_ptr ( .param. ld. this structure will be flattened into a byte array.param variable y is used in function definition bar to represent a formal parameter.b8 . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . note that . %rc2.u32 %ptr.reg .param.param.s32 out) bar (. ret. (%r1. py). } … call (%r1).f1.f64 f1. consider the following C structure. … … // computation using x.c2.b8 [py+11].b32 c1.param.PTX ISA Version 2.param space memory.reg .b8 [py+ 8]. … ld.4).param . … In this example.reg . bumpptr.param.param space call (%out). [y+8].reg space. c2.func (. .param. … st. In PTX. Second. 50 January 24.param. } { .b8 c1. // scalar args in .c4. (%x.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. st. %rd.param space variables are used in two ways.f64 f1.param state space is used to pass the structure by value: .b8 c4. [y+0].u32 %res. [y+11].reg .u32 %inc ) { add.reg . char c[4]. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . For example. c3. st. a . inc_ptr.param.b8 c3.func (. %rc1. st. First.

the corresponding argument may be either a . and alignment of parameters. The . or a constant that can be represented in the type of the formal parameter.reg or . a . or constants.reg state space can be used to receive and return base-type scalar and vector values.param argument must be declared within the local scope of the caller. • The . 2010 51 .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. The . the argument must also be a .reg space variable of matching type and size.param and ld. or 16 bytes.param memory must be aligned to a multiple of 1.param arguments. Parameters in . • • Arguments may be .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. • • • Input and return parameters may be .param state space is used to receive parameter values and/or pass return values back to the caller. For . size. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. • • • For a callee..param state space is used to set values that will passed to a called function and/or to receive return values from a called function. 8.param byte array is used to collect together fields of a structure being passed by value. For a callee. For a caller. A . Note that the choice of .Chapter 7. This enables backend optimization and ensures that the .param variables.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. The following restrictions apply to parameter passing.param or .param space formal parameters that are byte arrays. .param state space use in device functions.reg state space in this way provides legacy support.param or . For a caller. In the case of . 2. Typically. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. and alignment.param space formal parameters that are base-type scalar or vector variables.param space byte array with matching type.param variables or .reg space variable with matching type and size. In the case of .param instructions used for argument passing must be contained in the basic block with the call instruction. 4. size. • The . Supporting the .reg space formal parameters. In the case of .reg variables.g.reg variables. the corresponding argument may be either a . all st. Abstracting the ABI The following is a conceptual way to think about the . or a constant that can be represented in the type of the formal parameter. January 24.

1.0 restricts functions to a single return value.1. Objects such as C structures were flattened and passed or returned using multiple registers. PTX 2. formal parameters may be in either . PTX 1.0 7. 52 January 24.PTX ISA Version 2. PTX 2. and .x In PTX ISA version 1. and a .param byte array should be used to return objects that do not fit into a register.0.0 continues to support multiple return registers for sm_1x targets. Changes from PTX 1.x supports multiple return values for this purpose.reg state space. formal parameters were restricted to . For sm_2x targets.x.param state space.param space parameters support arrays. and there was no support for array parameters. 2010 .reg or . In PTX ISA version 2.

bra Loop. .h headers in C.reg . (3.u32 sz.s32 val. %r3).u32 b. In PTX. following zero or more fixed parameters: . setp.ge p.s32 result ) maxN ( . 4). .u32. } … call (%max). %r1.reg .u32 align) .reg . (2.reg . To support functions with a variable number of arguments.reg .u32 sz. the size may be 1. (ap).s32 result. . call %va_end.func (. The function prototypes are defined as follows: .. This handle is then passed to the %va_arg and %va_arg64 built-in functions. For %va_arg.u32 ptr. the size may be 1.func ( . %va_end is called to free the variable argument list handle. call (val). … ) . PTX provides a high-level mechanism similar to the one provided by the stdarg.reg . .b32 ctr. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg . max.reg . val. maxN.reg . // default to MININT mov. 0x8000000.h and varargs. for %va_arg64.u32 ptr) %va_start .reg . ret. Abstracting the ABI 7.func baz ( .reg .u32 N. mov. ctr. maxN. … call (%max). ctr. N.b32 result. or 16 bytes.reg . . result.reg . call (ap). Variadic functions NOTE: The current version of PTX does not support variadic functions.u32 a. %va_start. Once all arguments have been processed. along with the size and alignment of the next data value to be accessed. 2.func (. (ap. iteratively access. . .reg . … %va_start returns Loop: @p Done: January 24.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists.reg . %s2). variadic functions are declared with an ellipsis at the end of the input parameter list. the alignment may be 1.reg .2. 0. 2.func %va_end (.u32 ptr. 4. %r2..reg .b32 val) %va_arg (.Chapter 7. or 4 bytes.func okay ( … ) Built-in functions are provided to initialize. %va_arg.u32 ap. or 8 bytes. 2010 53 . ) { . 4. and end access to a list of variable arguments. 2.b64 val) %va_arg64 (.u32 align) .func (. In both cases. %s1. 8.pred p. 4. bra Done. .

reg . defined as follows: . To allocate memory.u32 ptr ) %alloca ( .func ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. 54 January 24. The array is then accessed with ld.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. a function simply calls the built-in function %alloca.local and st. If a particular alignment is required.0 7. 2010 . Alloca NOTE: The current version of PTX does not support alloca. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.local instructions. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.PTX ISA Version 2.3.reg .

lt p|q. the semantics are described. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. For instructions that create a result value. B. opcode D. Format and Semantics of Instruction Descriptions This section describes each PTX instruction.2. opcode D. The setp instruction writes two destination registers. // p = (a < b). PTX Instructions PTX instructions generally have from zero to four operands. A.s32. q = !(a < b). the D operand is the destination operand.1. B. 2010 55 . setp. We use a ‘|’ symbol to separate multiple destination registers. A. January 24. In addition to the name and the format of the instruction. while A. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. opcode D. C. B. opcode A. 8. and C are the source operands. b. For some instructions the destination operand is optional. Instruction Set 8. A. a. followed by some examples that attempt to show several possible instantiations of the instruction.Chapter 8.

Predicates are most commonly set as the result of a comparison performed by the setp instruction. consider the high-level code if (i < n) j = j + 1. … // compare i to n // if false. Instructions without a guard predicate are executed unconditionally. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. i.reg . optionally negated. As an example. add. 2010 . q. n. add 1 to j To get a conditional branch or conditional function call.lt. add. So. bra L1.PTX ISA Version 2.s32 j. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. This can be written in PTX as @p setp. the following PTX instruction sequence might be used: @!p L1: setp. 1.lt. Predicated Execution In PTX. i. where p is a predicate variable. // p = (i < n) // if i < n. predicate registers are virtual and have . n. branch over 56 January 24. j.s32 p. j. use a predicate to control the execution of the branch or call instructions.0 8.3.s32 p. 1.pred p.pred as the type specifier. To implement the above example as a true conditional branch. predicate registers can be declared as .s32 j.

1. If either operand is NaN.1.2.3. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. and bitsize types. ne. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. and hs (higher-or-same). The unsigned comparisons are eq.1. Comparisons 8. ne. le. Table 15. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). unsigned integer. Instruction Set 8. The bit-size comparisons are eq and ne. lt (less-than). ls (lower-or-same). Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. hi (higher). ne (not-equal). gt (greater-than).1. The following table shows the operators for signed integer. Unsigned Integer. ge.3. 2010 57 . Table 16. lt. gt. lo (lower).3. ordering comparisons are not defined for bit-size types. le (less-than-or-equal).Chapter 8. the result is false. and ge (greater-than-or-equal).

0.1. unordered versions are included: equ. However. and mov. geu. xor.2. setp can be used to generate a predicate from an integer. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. and no direct way to load or store predicate register values.0 To aid comparison operations in the presence of NaN values. then the result of these comparisons is true. then these comparisons have the same result as their ordered counterparts. There is no direct conversion between predicates and integer values. Table 18. leu. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. 2010 . not. for example: selp. If both operands are numeric values (not NaN). If either operand is NaN.u32 %r1. gtu. Table 17. ltu. two operators num (numeric) and nan (isNaN) are provided. // convert predicate to 32-bit value 58 January 24. and nan returns true if either operand is NaN. or. neu. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. num returns true if both operands are numeric values (not NaN).3.%p. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.PTX ISA Version 2.

bX . most notably the data conversion instruction cvt. b. i. cvt. float.e. For example.reg . • The following table summarizes these type checking rules. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. unsigned. a. For example: .reg . the add instruction requires type and size information to properly perform the addition operation (signed. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. 2010 59 . Instruction Set 8. add. and integer operands are silently cast to the instruction type if needed.fX ok inv inv ok Instruction Type . Floating-point types agree only if they have the same size.reg . different sizes). Example: . Table 19. It requires separate type-size modifiers for the result and source. . and this information must be specified as a suffix to the opcode. they must match exactly. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.fX ok ok ok ok January 24.sX . Type Checking Rules Operand Type . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.u16 a.u16 d. a.u16 d. Signed and unsigned integer types agree provided they have the same size.Chapter 8.bX . a. b.sX ok ok ok inv . For example.f32.4.f32 d.. and these are placed in the same order as the operands.uX ok ok ok inv .uX .u16 d. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.

bX instruction types. for example. When a source operand has a size that exceeds the instruction-type size. stored. the data will be truncated. 2. st. the cvt instruction does not support . Bit-size source registers may be used with any appropriately-sized instruction type. 2010 . so that narrow values may be loaded. When used with a narrower bit-size type.4. Notes 3. or converted to other types and sizes. The data is truncated to the instruction-type size and interpreted according to the instruction type. Source register size must be of equal or greater size than the instruction-type size. parse error. The following table summarizes the relaxed type-checking rules for source operands.PTX ISA Version 2.0 8. 60 January 24. no conversion needed. 1. so those rows are invalid for cvt. Note that some combinations may still be invalid for a particular instruction. unless the operand is of bit-size type. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. For example. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. Operand Size Exceeding Instruction-Type Size For convenience. When used with a floating-point instruction type. and converted using regular-width registers. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. the size must match exactly. 4. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. ld. stored. inv = invalid. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Table 20. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. “-“ = allowed. Floating-point source registers can only be used with bit-size or floating-point instruction types. floating-point instruction types still require that the operand type-size matches exactly. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type.1.

the size must match exactly. Destination register size must be of equal or greater size than the instruction-type size. 2. “-“ = Allowed but no conversion needed. 2010 61 . Table 21. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Notes 3. the data is zeroextended. the destination data is zero. The following table summarizes the relaxed type-checking rules for destination operands. 1. and is zero-extended to the destination register width otherwise. Bit-size destination registers may be used with any appropriately-sized instruction type. 4. When used with a floatingpoint instruction type. When used with a narrower bit-size instruction type. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. the data is sign-extended. The data is signextended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. zext = zero-extend.or sign-extended to the size of the destination register.Chapter 8. January 24. Floating-point destination registers can only be used with bit-size or floating-point instruction types. The data is sign-extended to the destination register width for signed integer instruction types. parse error. inv = Invalid. the data will be zero-extended. otherwise.

a compiler or code author targeting PTX can ignore the issue of divergent threads. the optimizing code generator automatically determines points of re-convergence. using the . For divergent control flow. 16-bit registers in PTX are mapped to 32-bit physical registers. When executing on a 32-bit data path. If threads execute down different control flow paths. conditional function call. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.1. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. the threads are called uniform. However. at least in appearance. for many performance-critical applications. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. or conditional return.5. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs.0 8. and 16-bit computations are “promoted” to 32-bit computations.PTX ISA Version 2. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent.uni suffix. 8. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. Both situations occur often in programs. so it is important to have divergent threads re-converge as soon as possible.6. The semantics are described using C. until they come to a conditional control construct such as a conditional branch. and for many applications the difference in execution is preferable to limiting performance.6. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. Therefore. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. this is not desirable. for example. by a right-shift instruction. If all of the threads act in unison and follow a single control flow path. 62 January 24. the semantics of 16-bit instructions in PTX is machine-specific. the threads are called divergent. At the PTX language level. 8. These extra precision bits can become visible at the application level. Divergence of Threads in Control Constructs Threads in a CTA execute together. A compiler or programmer may chose to enforce portable. until C is not expressive enough. 2010 . This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.

cc. The Integer arithmetic instructions are: add sub add. In the following descriptions.Chapter 8. 2010 63 . Instruction Set 8.cc.7. addc sub. the optional guard predicate is omitted from the syntax. 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7. Instructions All PTX instructions may be predicated.1.

2010 . Applies only to .s32 type.s32.type sub{. . Supported on all target architectures.sat applies only to . Introduced in PTX ISA version 1.b.z. . .sat applies only to . add. b. a.s32 d. . b.type = { . PTX ISA Notes Target ISA Notes Examples 64 January 24. .MAXINT (no overflow) for the size of the operation. a.s32 .s32 c.sat}.0.a.u64.s32.sat limits result to MININT.. Applies only to . add. . b.s64 }. d. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.s16. Introduced in PTX ISA version 1..PTX ISA Version 2. . PTX ISA Notes Target ISA Notes Examples Table 23.u16.1. a. a.u32.s16. Description Semantics Notes Performs addition and writes the resulting value into a destination register.u32 x.0. Supported on all target architectures. d = a + b.u32.u64. sub.s32 d. d = a – b. // .MAXINT (no overflow) for the size of the operation.s32 type.s64 }. . Saturation modifier: . . add Syntax Integer Arithmetic Instructions: add Add two values.y.type add{.type = { .sat. @p add.sat limits result to MININT. sub.u16.s32 c.0 Table 22.sat}. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. d.s32 . b. . // .c. Saturation modifier: .

if . Introduced in PTX ISA version 1.type = {.y2. a.z4.y1.cc Syntax Integer Arithmetic Instructions: add. addc{.y3. x3.b32 addc. add. x4.cc.b32 addc.type d. carry-out written to CC.CF) holding carry-in/carry-out or borrowin/borrow-out. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. .y1. Behavior is the same for unsigned and signed integers. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.z2.y4. x4.y4.y3.b32 x1.cc specified.cc. No saturation.cc. Introduced in PTX ISA version 1.CF No integer rounding modifiers. add.cc.2. @p @p @p @p add.cc. Supported on all target architectures.z3. a. sub. .z4. These instructions support extended-precision integer addition and subtraction. b.s32 }. and there is no support for setting. clearing.y2.cc Add two values with carry-out. x2. or testing the condition code. Supported on all target architectures. @p @p @p @p add. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.CF No integer rounding modifiers.z2.b32 addc.cc.z3. carry-out written to CC. Behavior is the same for unsigned and signed integers. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. b.cc. d = a + b + CC.cc. .z1. No other instructions access the condition code.s32 }.cc}. addc. Table 24. x3.b32 addc.b32 addc.b32 addc. 2010 65 .type = { . // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. No saturation.u32.2.cc.z1.Chapter 8. .u32. x2.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. Instruction Set Instructions add.CF. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. d = a + b.b32 x1.cc.type d.

if .cc. Introduced in PTX ISA version 1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.cc specified. x4.y3.cc.type = {.cc}.cc.type d.CF).y4. . a.y2.PTX ISA Version 2.s32 }.CF No integer rounding modifiers. No saturation. x2.type = { . Introduced in PTX ISA version 1. @p @p @p @p sub. Supported on all target architectures.y4.y3.cc.b32 x1. x4. x2.u32. borrow-out written to CC. a. .z4.z2. Behavior is the same for unsigned and signed integers.b32 subc.type d. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.3. x3. b. d = a .b32 subc. 2010 .b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y1.b32 x1.3.z4. sub. with borrow-out.CF No integer rounding modifiers.0 Table 26. subc{.cc Syntax Integer Arithmetic Instructions: sub. borrow-out written to CC.u32.z3. Behavior is the same for unsigned and signed integers.z3. sub.cc. No saturation.cc.z1.b32 subc.b32 subc.s32 }. withborrow-in and optional borrow-out. @p @p @p @p sub.cc Subract one value from another. x3.cc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. .z1. Supported on all target architectures. b.y1. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.cc.y2. d = a – b. .(b + CC.b32 subc.cc.z2.

u16. mul{. // 16*16 bits yields 32 bits // 16*16 bits..x. t = a * b.s16 fa. d = t<n-1.hi. . d = t<2n-1.wide.0>.s32 z. d = t.wide. and either the upper or lower half of the result is written to the destination register.lo.fys. b.s16 fa. Supported on all target architectures. then d is twice as wide as a and b to receive the full result of the multiplication. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.n>.wide suffix is supported only for 16. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.and 32-bit integer types.fxs.wide // for . Description Semantics Compute the product of two values.wide is specified.type d.s32. then d is the same size as a and b. save only the low 16 bits // 32*32 bits.s64 }. mul.u32.Chapter 8..type = { . n = bitwidth of type. mul. If . a. creates 64 bit result January 24.fys.u64.fxs. .hi or . // for ...lo is specified. Instruction Set Table 28. . .lo variant Notes The type of the operation represents the types of the a and b operands.y.wide}. . .hi variant // for .0. 2010 67 . The .s16. If .lo. mul.

s32. b. .0 Table 29. Applies only to . The .type = { .hi mode. then d and c are the same size as a and b. c.lo is specified. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi or .0.lo.wide suffix is supported only for 16.lo. 68 January 24.s32 d.s32 r.hi.. . // for .b.PTX ISA Version 2.u32.type mad. Saturation modifier: . t n d d d = = = = = a * b.. If . t + c.sat.lo.s64 }. . b.q. and either the upper or lower half of the result is written to the destination register. .s32 d. t<n-1.hi. mad.sat limits result to MININT. d. 2010 . Supported on all target architectures.p.hi variant // for .s16.wide // for . then d and c are twice as wide as a and b to receive the result of the multiplication. mad{.u64.c.s32 type in . . and then writes the resulting value into a destination register. @p mad.r.MAXINT (no overflow) for the size of the operation. Description Semantics Multiplies two values and adds a third. .. If .u16. a.n> + c.wide is specified... t<2n-1. bitwidth of type.0> + c.and 32-bit integer types.a.wide}. a.lo variant Notes The type of the operation represents the types of the a and b operands. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. c.

d = t<47. and return either the high or low 32-bits of the 48-bit result.lo}.Chapter 8. 48bits. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. mul24..lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. mul24.lo. 2010 69 . .u32. Instruction Set Table 30. b.16>.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. t = a * b. d = t<31.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // low 32-bits of 24x24-bit signed multiply.e. Supported on all target architectures. All operands are of the same type and size.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.a. // for ...0>.b. .type d. mul24{.s32 d. mul24. a.s32 }. mul24. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.hi variant // for . January 24. i.0.hi.hi may be less efficient on machines without hardware support for 24-bit multiply.

hi may be less efficient on machines without hardware support for 24-bit multiply.u32. 48bits.s32 d.MAXINT (no overflow). Description Compute the product of two 24-bit integer values held in 32-bit source registers. b. a. t = a * b. d. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value.16> + c. All operands are of the same type and size.e.s32 }.lo. // for .s32 type in .lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value..sat limits result of 32-bit signed addition to MININT. c.hi. c. Applies only to . Saturation modifier: .hi mode. . mad24. a. 2010 . mad24.0 Table 31. i.c. 32-bit value to either the high or low 32-bits of the 48-bit result. d = t<47. 70 January 24.PTX ISA Version 2. .lo}. Return either the high or low 32-bits of the 48-bit result. b. Supported on all target architectures.a..type mad24. mad24.s32 d.0..0> + c.hi.hi variant // for .sat. and add a third.type = { .b.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // low 32-bits of 24x24-bit signed multiply. mad24.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. mad24{. d = t<31.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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X. a.b32. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. a. a = a << 1.b64 }.0 Table 39.b64 }. . popc requires sm_20 or later.PTX ISA Version 2. clz.type == .b32.type = { .b32 clz. For . if (. inclusively. popc. } Introduced in PTX ISA version 2.0. } else { max = 64. 2010 . .b64 d. a.type d. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. clz.u32 PTX ISA Notes Target ISA Notes Examples Table 40. clz requires sm_20 or later. // cnt is .b32) { max = 32.b32 popc. popc. d = 0. the number of leading zeros is between 0 and 32.type d. mask = 0x8000000000000000. mask = 0x80000000. . d = 0.b32 type. // cnt is . cnt.b64 d. while (a != 0) { if (a&0x1) d++.0. } while (d < max && (a&mask == 0) ) { d++. For . a. inclusively. the number of leading zeros is between 0 and 64. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. a = a >> 1. X.type = { .b64 type. cnt. popc Syntax Integer Arithmetic Instructions: popc Population count. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 Semantics 74 January 24.

i--) { if (a & (1<<i)) { d = i. a.type = { . bfind requires sm_20 or later.u32 || . and operand d has type . a.u32 d. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. .s32.u32. . Semantics msb = (.shiftamt. bfind returns the bit position of the most significant “1”. Instruction Set Table 41. bfind returns 0xFFFFFFFF if no non-sign bit is found.type bfind. Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.u32. For signed integers.s64 cnt. break.Chapter 8. . 2010 75 . a.type==. } } if (.u64. d = -1. Operand a has the instruction type.0. X.shiftamt && d != -1) { d = msb . i>=0. for (i=msb.s32) ? 31 : 63. bfind. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. For unsigned integers. bfind. . bfind.shiftamt is specified.type d.u32 January 24. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.d. // cnt is .type==.shiftamt.s64 }. d. If .

0 Table 42. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .b32) ? 31 : 63. brev. a. brev requires sm_20 or later. 76 January 24. for (i=0.b32.type d. i++) { d[i] = a[msb-i]. 2010 . brev. msb = (.type==. . a. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. i<=msb. Description Semantics Perform bitwise reversal of input.type = { .b64 }.0.b32 d.PTX ISA Version 2.

s32.type==.u32. bfe. c.u64: . Semantics msb = (. and source c gives the bit field length in bits. else sbit = a[min(pos+len-1. 2010 77 . Instruction Set Table 43.a.b32 d.type = { . pos = b. a. January 24. Source b gives the bit field starting bit position.type==. bfe requires sm_20 or later. for (i=0. .type d.u32 || .len.u64.type==. Description Extract bit field from a and place the zero or sign-extended result in d. . . b.s64 }. if (. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.type==. .s32.msb)]. bfe.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. The sign bit of the extracted field is defined as: . If the start position is beyond the msb of the input. i<=msb.u64 || len==0) sbit = 0.u32 || . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. The destination d is padded with the sign bit of the extracted field.start. Operands a and d have the same type as the instruction type. . and operands b and c are type . . d = 0. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. otherwise If the bit field length is zero. the destination d is filled with the replicated sign bit of the extracted field. the result is zero.u32.0.s32) ? 31 : 63.u32.Chapter 8. len = c.

start.u32. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. len = d. a. Description Align and insert a bit field from a into b. bfi. bfi. and operands c and d are type . c. f = b. for (i=0. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. b.b32.type f.type==. the result is b. d. If the start position is beyond the msb of the input. and source d gives the bit field length in bits.b64 }. Source c gives the starting bit position for the insertion.a. . and f have the same type as the instruction type. the result is b. . pos = c. 2010 .b.len. i<len && pos+i<=msb. 78 January 24.0 Table 44.PTX ISA Version 2. bfi requires sm_20 or later. b. If the bit field length is zero.0.b32) ? 31 : 63. i++) { f[pos+i] = a[i].type = { . Semantics msb = (.b32 d. and place the result in f. Operands a.

b2. a 4-bit selection value is defined. . Thus. b5. Description Pick four arbitrary bytes from two 32-bit registers.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24.b1 source select c[7:4] d.Chapter 8. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.f4e. b1. For each byte in the target register.b4e.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b3 source select c[15:12] d. . .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. {b3. a} = {{b7. prmt. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. default mode index d.b32{. b.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. In the generic form (no mode specified).rc8. msb=1 means replicate the sign. c.mode} d. b0}}. . . The msb defines if the byte value should be copied. as a 16b permute code. . b4}. msb=0 means copy the literal value. a. b6. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. the permute control consists of four 4-bit selection values. and reassemble them into a 32-bit destination register. the four 4-bit values fully specify an arbitrary byte permute.mode = { . Note that the sign extension is only performed as part of generic form. The bytes in the two source registers are numbered from 0 to 7: {b. 2010 79 .ecl.b2 source select c[11:8] d.rc16 }.ecr. Instruction Set Table 45.

prmt. tmp64 ). ctl[3] = (c >> 12) & 0xf. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf.b32 prmt. 80 January 24. ctl[2] = (c >> 8) & 0xf. r3. tmp[15:08] = ReadByte( mode.b32. r3. tmp64 ).0.PTX ISA Version 2. r4. tmp64 ). r2. ctl[1]. tmp[31:24] = ReadByte( mode. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. ctl[2]. } tmp[07:00] = ReadByte( mode. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[1] = (c >> 4) & 0xf. r2. r4. tmp[23:16] = ReadByte( mode.f4e r1. prmt requires sm_20 or later. ctl[0]. ctl[3]. r1.0 Semantics tmp64 = (b<<32) | a. 2010 . tmp64 ).

7.2. Instruction Set 8. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 .f32 and . Floating-Point Instructions Floating-point instructions operate on .Chapter 8.f64 register operands and constant immediate values.

f64 rsqrt. sub.mul}.sqrt}.sub. {mad.rp .f64 mad. NaN payloads are supported for double-precision instructions.rcp.lg2.f32 {div.rn and instructions may be folded into a multiply-add. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. Note that future implementations may support NaN payloads for single-precision instructions. Table 46. If no rounding modifier is specified. but single-precision instructions return an unspecified NaN. Double-precision instructions support subnormal inputs and results. with NaNs being flushed to positive zero.rnd.cos.f64 are the same.approx.32 and fma.f32 .PTX ISA Version 2.f64 and fma.fma}.f64 {sin.rm .mul}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.fma}.full.0.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f64 div.ex2}.rnd.approx.rnd. No rounding modifier.sat Notes If no rounding modifier is specified. mul.target sm_20 .0].rz . default is .sqrt}.f32 {div.approx. .target sm_1x No rounding modifier.f32 {abs.neg.f32 {div.sqrt}.f32 {add. and mad support saturation of results to the range [0.rnd.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.max}.neg. 82 January 24.sub.f32 rsqrt.ftz .rnd.rcp.min.rcp.rn .rn and instructions may be folded into a multiply-add. . Instruction Summary of Floating-Point Instructions . {add. 1.max}.f32 are the same. so PTX programs should not rely on the specific single-precision NaNs being generated. Single-precision add.f32 {mad.approx. The optional .target sm_20 mad.0 The following table summarizes floating-point instructions in PTX.min. default is .f64 {abs.rnd. 2010 .

normal.0. p.type d. .0. testp requires sm_20 or later.pred = { . copysign requires sm_20 or later. A. not infinity) As a special case. a.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.infinite.f32 testp. copysign. f0. a. .f64 }. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.normal testp. b.finite. and return the result as d.Chapter 8. .infinite. B.subnormal }.f64 x.type = { . . testp.f32. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. // result is . positive and negative zero are considered normal numbers.op. testp Syntax Floating-Point Instructions: testp Test floating-point property.finite testp. January 24. 2010 83 .infinite testp.notanumber. testp.notanumber. Table 48. testp.f64 }. C.f64 isnan.type = { . .f32 copysign.op p. X.number testp.number. true if the input is a subnormal number (not NaN. . z. . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. Introduced in PTX ISA version 2.notanumber testp. y.f32. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. . Instruction Set Table 47. not infinity). copysign.type .

sm_1x: add.f32 flushes subnormal inputs and results to sign-preserving zero. 84 January 24.f64.rm.f32 add{.PTX ISA Version 2.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . NaN results are flushed to +0.rz. 2010 . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. add{.f32.ftz. .f3.f32 clamps the result to [0. . In particular.rn.f2.rm.0 Table 49.f32 flushes subnormal inputs and results to sign-preserving zero.0. add.rn): . b. Description Semantics Notes Performs addition and writes the resulting value into a destination register.f32 f1. d.ftz}{. .f32 supported on all target architectures.rm mantissa LSB rounds towards negative infinity . requires sm_13 for add. 1.rn mantissa LSB rounds to nearest even .rp }.0.rnd = { . Rounding modifiers (default is . add. . add Syntax Floating-Point Instructions: add Add two values.f64 supports subnormal numbers. add.rz available for all targets . b.0f. subnormal numbers are supported.rz. Rounding modifiers have the following target requirements: .ftz. a.f64 requires sm_13 or later. a. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_20 Examples @p add. add. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.rnd}.f64 d. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Saturation modifier: .sat.rn.sat}.rnd}{.rp for add. d = a + b.0]. . add.rz mantissa LSB rounds towards zero .

a.rn. subnormal numbers are supported.f32 supported on all target architectures.0].rz mantissa LSB rounds towards zero . d = a .rm. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f2. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0.rm mantissa LSB rounds towards negative infinity . January 24. requires sm_20 Examples sub.f32 clamps the result to [0. b. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 sub{.0. a. d. sub.f64 requires sm_13 or later.f32.Chapter 8. sub. . requires sm_13 for sub.f3.rn.0f. sm_1x: sub.f64 d.rz available for all targets .f32 c. . sub. Saturation modifier: sub.rz.f32 flushes subnormal inputs and results to sign-preserving zero. sub.ftz}{.rn): .rp for sub. .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz.rn mantissa LSB rounds to nearest even .b. . sub Syntax Floating-Point Instructions: sub Subtract one value from another.rnd = { .rm. sub.rnd}.f64. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64 supports subnormal numbers. In particular.b.rn. Rounding modifiers (default is .f32 flushes subnormal inputs and results to sign-preserving zero.f32 f1. 1.sat}. 2010 85 . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sub{. b. .ftz.rp }. a. Rounding modifiers have the following target requirements: .rnd}{.sat. Instruction Set Table 50. . NaN results are flushed to +0.

. Rounding modifiers (default is . requires sm_13 for mul.pi // a single-precision multiply 86 January 24.radius. . 1. . .sat.rz mantissa LSB rounds towards zero . mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. Saturation modifier: mul.0f.ftz}{. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. d. For floating-point multiplication. mul.f64 supports subnormal numbers.rp }. all operands must be the same size.rm mantissa LSB rounds towards negative infinity .rp for mul.f32 mul{. NaN results are flushed to +0. .rnd}{. Description Semantics Notes Compute the product of two values. mul{. b. . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. d = a * b.ftz.f64 d.0].f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.PTX ISA Version 2.rn.f32 flushes subnormal inputs and results to sign-preserving zero.0 Table 51.rm. a.rz.0. b.rn mantissa LSB rounds to nearest even . In particular.f32 clamps the result to [0. mul.f32 flushes subnormal inputs and results to sign-preserving zero.0.rnd}. subnormal numbers are supported. sm_1x: mul.rnd = { . mul. mul Syntax Floating-Point Instructions: mul Multiply two values.f32 circumf.rz available for all targets . 2010 . requires sm_20 Examples mul.sat}. mul.ftz.rn. a.f32 supported on all target architectures.f64 requires sm_13 or later.f64.rm.rn): . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Rounding modifiers have the following target requirements: .

0. fma.x. b. fma. fma. again in infinite precision. again in infinite precision.sat.f64 d.c. c. fma.rnd = { .0. d. fma.f64. sm_1x: fma. The resulting value is then rounded to double precision using the rounding mode specified by . Rounding modifiers (no default): .rnd. fma.f64 is the same as mad.f32 computes the product of a and b to infinite precision and then adds c to this product.ftz.rm mantissa LSB rounds towards negative infinity . c.rnd.sat}.f32 flushes subnormal inputs and results to sign-preserving zero. NaN results are flushed to +0.f32 fma. d.z.rm. a.b.a.rp }.rn. 1.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Saturation: fma.Chapter 8.f32 is unimplemented in sm_1x. @p fma.0f. .rz mantissa LSB rounds towards zero .ftz}{. Instruction Set Table 52.f64 computes the product of a and b to infinite precision and then adds c to this product. .4. fma. fma.f32 clamps the result to [0.0]. The resulting value is then rounded to single precision using the rounding mode specified by .f32 requires sm_20 or later.ftz. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. a.f64 requires sm_13 or later.rz. . subnormal numbers are supported.rn mantissa LSB rounds to nearest even .rnd. . b.f64 w.y.rn. d = a*b + c. 2010 87 .rnd{.f32 introduced in PTX ISA version 2. PTX ISA Notes Target ISA Notes Examples January 24. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma. fma.f64 supports subnormal numbers.f32 fma.f64 introduced in PTX ISA version 1.rn.

a.ftz}{. b. the treatment of subnormal inputs and output follows IEEE 754 standard.rnd.rnd. mad. Description Semantics Notes Multiplies two values and adds a third. subnormal numbers are supported. . 2010 . b. a.f64 d.f32 is implemented as a fused multiply-add (i.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.f64 computes the product of a and b to infinite precision and then adds c to this product. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.f32 clamps the result to [0. // .rn. In this case.rz mantissa LSB rounds towards zero .f64}.f32 flushes subnormal inputs and results to sign-preserving zero.target sm_20 d. mad. // . a.sat. Saturation modifier: mad.rnd{.f32 computes the product of a and b at double precision.f32).{f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. again in infinite precision. sm_1x: mad.rn mantissa LSB rounds to nearest even . 1. d = a*b + c. and then writes the resulting value into a destination register.f64 supports subnormal numbers. The resulting value is then rounded to double precision using the rounding mode specified by .rp }. b.e.f32 mad. again in infinite precision. mad. mad. c.0].rn. but the exponent is preserved. mad.. . Note that this is different from computing the product with mul. The resulting value is then rounded to single precision using the rounding mode specified by . mad{.0f. The exception for mad.rnd = { .f64 computes the product of a and b to infinite precision and then adds c to this product. mad.target sm_20: mad.f64 is the same as fma. where the mantissa can be rounded and the exponent will be clamped. Unlike mad.ftz. For .PTX ISA Version 2. and then the mantissa is truncated to 23 bits.f32 is identical to the result computed using separate mul and add instructions. // . fma. For .0.sat}. 88 January 24.f32 is when c = +/-0.0 Table 53. The resulting value is then rounded to double precision using the rounding mode specified by .rm.sat}.target sm_13 and later .rnd.f32 mad.target sm_1x: mad. mad.{f32. mad.rm mantissa LSB rounds towards negative infinity . NaN results are flushed to +0.target sm_1x d. c.0. c. Rounding modifiers (no default): .rz.f64} is the same as fma.f32.0 devices.ftz. again in infinite precision.ftz}{.f64.f32 flushes subnormal inputs and results to sign-preserving zero. When JIT-compiled for SM 2.f32 computes the product of a and b to infinite precision and then adds c to this product.rnd. mad. .

rz. Legacy mad..Chapter 8. a rounding modifier is required for mad.. requires sm_13 . a rounding modifier is required for mad.rm... Target ISA Notes mad.f64 instructions having no rounding modifier will map to mad.f64.f32 supported on all target architectures.f64 requires sm_13 or later..rn.f64. Rounding modifiers have the following target requirements: .f32..f32 d. In PTX ISA versions 1. requires sm_20 Examples @p mad.c.rn. January 24.0 and later.rp for mad.rn.b.a. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.0.rm. 2010 89 .rz.rp for mad. mad.4 and later.f64.f32 for sm_20 targets. In PTX ISA versions 2.

ftz}. but is not fully IEEE 754 compliant and does not support rounding modifiers. or .f64. div. div.f64 defaults to div. a.f64 introduced in PTX ISA version 1.f64 requires sm_13 or later. a.approx.rn mantissa LSB rounds to nearest even . b.approx.f32 implements a fast approximation to divide. one of .f32 flushes subnormal inputs and results to sign-preserving zero. div Syntax Floating-Point Instructions: div Divide one value by another.rnd is required. The maximum ulp error is 2 across the full range of inputs. full-range approximation that scales operands to achieve better accuracy. and div.f32 div.full. .approx.rm. subnormal numbers are supported. b.f32 div. d.f64 supports subnormal numbers.ftz}. x. Fast.{rz. approximate division by zero creates a value of infinity (with same sign as a).PTX ISA Version 2. For b in [2-126. .rn.rnd{. div.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 .rz.ftz.rn.f32 div. div. stores result in d.ftz}. .approx.full.rn. zd.rm mantissa LSB rounds towards negative infinity .0 Table 54.approx.3. .4. For PTX ISA version 1.full.approx.f32 implements a relatively fast.full. y. a. Examples 90 January 24.ftz.f32 and div. the maximum ulp error is 2.rn.rp}.0. d.0 through 1. Target ISA Notes div.f32 div.f32.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. For PTX ISA versions 1.f64 d.4 and later. 2126]. // // // // fast.rnd = { . div.ftz.ftz.3. d = a / b.f32 div. d.14159.f32 supported on all target architectures. and rounding introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero . z. Fast. div.approx{. PTX ISA Notes div.full{. b. Description Semantics Notes Divides a by b. .rnd. xd. a.full.ftz. Subnormal inputs and results are flushed to sign-preserving zero. approximate single-precision divides: div.rnd.f64 requires sm_20 or later.f32 requires sm_20 or later.f32 and div. Explicit modifiers . . div.circum. sm_1x: div.rp }. b. yd.f32 defaults to div.f64 diam. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): . approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . div.rm. computed as d = a * (1/b). div.

Subnormal numbers: sm_20: By default.f64 d. Take the absolute value of a and store the result in d.f32 supported on all target architectures. Table 56.Chapter 8. Instruction Set Table 55. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f0.f64 requires sm_13 or later. abs. Negate the sign of a and store the result in d. neg.0.ftz. sm_1x: neg.ftz.f64 d. subnormal numbers are supported.f64 supports subnormal numbers. January 24.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.f0. neg.f64 supports subnormal numbers.ftz}.ftz.f32 supported on all target architectures. neg.f32 x. d = -a. sm_1x: abs. abs. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz}. a. NaN inputs yield an unspecified NaN.f32 x. d. abs. neg{. 2010 91 . NaN inputs yield an unspecified NaN. a. neg. Subnormal numbers: sm_20: By default. a. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.0.f32 neg.ftz. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero. d. a. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 flushes subnormal inputs and results to sign-preserving zero. abs.f64 requires sm_13 or later. abs. abs{.f32 abs. neg. d = |a|.

a.f64 z.f32 min. b. max{. d. subnormal numbers are supported. 2010 .x.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. max. min.0. min. Store the maximum of a and b in d. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f1.f32 max. d d d d = = = = NaN. a. Table 58. sm_1x: max.f32 flushes subnormal inputs and results to sign-preserving zero. @p min. b. a.ftz. sm_1x: min.c.z.b. a.0 Table 57.b.ftz. min{.ftz}.f32 max. min. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.f64 d.f64 supports subnormal numbers. b.PTX ISA Version 2. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. b.f32 supported on all target architectures.f2. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Store the minimum of a and b in d. subnormal numbers are supported. d. a. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. a. 92 January 24.c.ftz. max. max.0. (a < b) ? a : b.f32 min. b.ftz. a. min. max.f64 requires sm_13 or later. b.f64 d. max.f64 f0.f32 flushes subnormal inputs and results to sign-preserving zero. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. d d d d = = = = NaN. (a > b) ? a : b.f64 requires sm_13 or later.ftz}.

PTX ISA Notes rcp.rn. rcp.3. d.f64 defaults to rcp. store result in d. and rcp.f32 implements a fast approximation to reciprocal.approx.rn.rn.f64 requires sm_13 or later.f32 flushes subnormal inputs and results to sign-preserving zero.f32 rcp.f32 rcp. General rounding modifiers were added in PTX ISA version 2.ftz.approx or . approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .{rz.ftz}.0 +subnormal +Inf NaN Result -0.ftz were introduced in PTX ISA version 1.4 and later. rcp.f32 flushes subnormal inputs and results to sign-preserving zero.0. rcp.rp }. a.0.0-2.rm.ftz.f64 supports subnormal numbers.ftz.approx and .f32 requires sm_20 or later.rz mantissa LSB rounds towards zero .0 -Inf -Inf +Inf +Inf +0. one of .ftz. For PTX ISA version 1.rn. d = 1 / a. rcp. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.Chapter 8.approx.rnd{. Input -Inf -subnormal -0.rn.f64 d. a. rcp.rz. sm_1x: rcp. // fast.f64.approx.f64 introduced in PTX ISA version 1. Target ISA Notes rcp. xi.0 +0.0 over the range 1.x.rnd. a.f64 ri.x. xi. .rp}. d.f64 requires sm_20 or later.0 through 1. rcp. The maximum absolute error is 2-23.f64 and explicit modifiers . Examples January 24.f32 defaults to rcp.f32 rcp. rcp.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . Description Semantics Notes Compute 1/a.rnd = { .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): .rm. Instruction Set Table 59. rcp.f32 and rcp.rnd is required.approx{.f32 rcp. 2010 93 .f32.rm mantissa LSB rounds towards negative infinity .f32 supported on all target architectures.4. rcp.rnd.approx.0. subnormal numbers are supported. rcp.ftz}. For PTX ISA versions 1. .rn.rn mantissa LSB rounds to nearest even .r.

f64 requires sm_13 or later.approx.PTX ISA Version 2.rm.rp}.rn. d = sqrt(a).f32 defaults to sqrt.ftz.f32 sqrt.x.rnd is required. // IEEE 754 compliant rounding . r.f32 sqrt. PTX ISA Notes sqrt. The maximum absolute error for sqrt. sqrt.rn.rnd. and sqrt.rm.3.{rz.approx.f32.ftz}.f64 defaults to sqrt.4. sqrt. Target ISA Notes sqrt.x.f64 supports subnormal numbers.ftz.f32 implements a fast approximation to square root. Input -Inf -normal -subnormal -0.ftz. a. General rounding modifiers were added in PTX ISA version 2. a.f32 sqrt.0 +subnormal +Inf NaN Result NaN NaN -0. For PTX ISA version 1.ftz were introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f64 r.0 Table 60. 2010 .f32 is TBD. // fast.f64 introduced in PTX ISA version 1. sqrt. one of .f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . .rn. sqrt.rp }. For PTX ISA versions 1.approx.approx.rnd. . sqrt. r.f64.f32 sqrt.rm mantissa LSB rounds towards negative infinity .ftz}.rn mantissa LSB rounds to nearest even .rnd{.0 +0.0 through 1. sm_1x: sqrt. approximate square root d.f32 and sqrt. sqrt. subnormal numbers are supported.ftz.rn. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. // IEEE 754 compliant rounding d.0 -0.rz mantissa LSB rounds towards zero .approx or .f64 and explicit modifiers . sqrt.approx and . Examples 94 January 24.0. .rn.0 +0.rz. store in d. sqrt. a.f64 requires sm_20 or later.4 and later.f32 supported on all target architectures.0 +0.rn.rnd = { .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Description Semantics Notes Compute sqrt(a).0.approx. sqrt. sqrt.f32 requires sm_20 or later.approx{.x.

rsqrt.Chapter 8. Input -Inf -normal -subnormal -0.approx modifier is required.approx{.4 over the range 1.3.0 +0.f32 and rsqrt. Target ISA Notes Examples rsqrt.ftz. The maximum absolute error for rsqrt. rsqrt.approx.4.f64 supports subnormal numbers.approx.ftz.f32 rsqrt.f32 rsqrt. Instruction Set Table 61. a.f32.f32 flushes subnormal inputs and results to sign-preserving zero. the .0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.approx. store the result in d.0.f64 isr.f64 defaults to rsqrt. Compute 1/sqrt(a).approx. January 24.f64 is TBD. PTX ISA Notes rsqrt. X. Explicit modifiers .0 through 1.f32 supported on all target architectures.approx.f64 requires sm_13 or later. For PTX ISA version 1. Note that rsqrt.approx implements an approximation to the reciprocal square root. rsqrt.f32 defaults to rsqrt.ftz}. subnormal numbers are supported. 2010 95 . For PTX ISA versions 1.0-4. sm_1x: rsqrt. ISR.4 and later.approx.approx and . rsqrt. and rsqrt. d.f64 were introduced in PTX ISA version 1. rsqrt. rsqrt. rsqrt.ftz. x. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 NaN The maximum absolute error for rsqrt.f32 is 2-22.f32 flushes subnormal inputs and results to sign-preserving zero.f64 is emulated in software and are relatively slow. Subnormal numbers: sm_20: By default.ftz were introduced in PTX ISA version 1.f64. d = 1/sqrt(a).f64 d.0. a.

Target ISA Notes Examples Supported on all target architectures.4 and later. sin.0.0 through 1. sin.3.f32 introduced in PTX ISA version 1. 96 January 24.0 +0.f32 d. subnormal numbers are supported.approx.approx.approx{.ftz}.0 +subnormal +Inf NaN Result NaN -0.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero. sin.0 Table 62. Find the sine of the angle a (in radians). 2010 .f32 defaults to sin. sin.0 +0. For PTX ISA version 1. a. the . PTX ISA Notes sin.9 in quadrant 00.ftz.0 NaN NaN The maximum absolute error is 2-20.f32 implements a fast approximation to sine.f32 sa. Subnormal numbers: sm_20: By default.f32.4. Input -Inf -subnormal -0.f32 flushes subnormal inputs and results to sign-preserving zero. Explicit modifiers .0 +0.approx. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. d = sin(a).approx and .ftz.0 -0.approx modifier is required. sin. For PTX ISA versions 1.ftz introduced in PTX ISA version 1. a.PTX ISA Version 2.

4.approx modifier is required. Instruction Set Table 63. cos.f32 introduced in PTX ISA version 1. d = cos(a).f32 d. subnormal numbers are supported. For PTX ISA version 1.approx.approx.f32 defaults to cos. PTX ISA Notes cos. Input -Inf -subnormal -0.9 in quadrant 00.0 through 1. cos.f32 implements a fast approximation to cosine.0 +1.approx.f32 ca.3. a.ftz introduced in PTX ISA version 1.approx and .0 +1.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default.ftz. 2010 97 .f32.Chapter 8. Find the cosine of the angle a (in radians).ftz. Explicit modifiers . the .0 NaN NaN The maximum absolute error is 2-20.approx{. January 24. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. cos.0.4 and later. cos.0 +subnormal +Inf NaN Result NaN +1. cos. Target ISA Notes Examples Supported on all target architectures.0 +1.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.0 +0. For PTX ISA versions 1. a.

f32 defaults to lg2. d = log(a) / log(2). lg2. The maximum absolute error is 2-22.f32 la. Subnormal numbers: sm_20: By default.ftz. Target ISA Notes Examples Supported on all target architectures. a.ftz. sm_1x: Subnormal inputs and results to sign-preserving zero.0 Table 64. 98 January 24.4.0 +0. subnormal numbers are supported. lg2.ftz.f32 Determine the log2 of a.PTX ISA Version 2.f32. For PTX ISA versions 1.approx modifier is required. lg2.f32 implements a fast approximation to log2(a).6 for mantissa. lg2. For PTX ISA version 1.f32 introduced in PTX ISA version 1. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.3.ftz}. a.approx{. 2010 .approx. lg2.0 through 1. PTX ISA Notes lg2.approx. the .0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d.approx and . Explicit modifiers .approx. Input -Inf -subnormal -0.ftz introduced in PTX ISA version 1.0.f32 flushes subnormal inputs and results to sign-preserving zero.4 and later.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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CmpOp.0 Table 67.f32 flushes subnormal inputs to sign-preserving zero. geu. For unsigned values. gt. The destinations p and q must be .lt. then these comparisons have the same result as their ordered counterparts.u16.u64.s32 setp. or. leu.u32. Subnormal numbers: sm_20: By default.f32 comparisons. 2010 .ftz}. ne.f64 supports subnormal numbers. respectively. The comparison operator is a suffix on the instruction.f32 flushes subnormal inputs to sign-preserving zero.dtype. c). and higher-or-same may be used instead of lt. Modifier . .PTX ISA Version 2. subnormal numbers are supported. . hi. ge. sm_1x: setp.b64. hi. ls.ftz. Semantics t = (a CmpOp b) ? 1 : 0. p. nan The Boolean operator BoolOp(A. .f64 source type requires sm_13 or later.dtype.0. ge. If both operands are numeric values (not NaN). gtu. setp. p[|q]. le. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. @q setp. To aid comparison operations in the presence of NaN values. ltu. num. A related value computed using the complement of the compare result is written to the second destination operand. ge. the result is false. If either operand is NaN. gt. bit-size comparisons are eq and ne. setp. p = BoolOp(t.s16.n. gt.eq.f64 }. ltu. lt.b32.type = { .i. then the result of these comparisons is true. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.r. p[|q]. The signed and unsigned comparison operators are eq.BoolOp{. the comparison operators lo. .ftz applies only to . . and can be one of: eq.CmpOp{. xor. neu. num returns true if both operands are numeric values (not NaN). setp.b16. .ftz}. a. ls. c).pred variables.b.f32. q = BoolOp(!t. gt. b. le. This result is written to the first destination operand. b. ne. {!}c. le. and nan returns true if either operand is NaN. and (optionally) combine this result with a predicate value by applying a Boolean operator.s64. .u32 p|q.dtype. lt. . setp with . neu.and. leu. lo. lt. The untyped. . hs equ.B) is one of: and. ge. Integer Notes Floating Point Notes The ordered comparisons are eq.type setp. gtu. Applies to all numeric types.type .s32. and hs for lower. loweror-same. a.a. higher. 102 January 24. unordered versions are included: equ. geu. If either operand is NaN. ne. le. .

C.f32.dtype.s64. . Operands d. .s32 x. selp Syntax Comparison and Selection Instructions: selp Select between source operands. .dtype.f64 }.f32. . y. . slct. d = (c >= 0) ? a : b.g. .type d. c.f32 d. and operand a is selected. slct.Chapter 8.type = { . B.t.0. negative zero equals zero.s64. . d = (c == 1) ? a : b. a. b. a. f0.s32 slct{.u32.ftz. For .ftz. fval.b16.b16. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. slct. the comparison is unordered and operand b is selected. .xp. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. b. a.u16. slct Syntax Comparison and Selection Instructions: slct Select one source operand. .0.f32 comparisons. @q selp. Description Conditional selection. c.ftz}.u64.u32. . Modifier . z. Table 69.s32.s16.ftz applies only to . selp.r. a. a. . d.u64.dtype. and b must be of the same type. If operand c is NaN. . 2010 103 . .f32 A. b otherwise.s32.dtype.dtype = { . Subnormal numbers: sm_20: By default. otherwise b is stored in d.f32 comparisons. .u64. b. Operand c is a predicate. based on the value of the predicate source operand. If c is True.b64. and b are treated as a bitsize type of the same width as the first instruction type. The selected input is copied to the output without modification.f64 requires sm_13 or later.s16. .b32.f64 requires sm_13 or later. selp.f32 r0. operand c must match the second instruction type. . Operands d.f32 flushes subnormal values of operand c to sign-preserving zero. a is stored in d.b32. slct. and operand a is selected. Instruction Set Table 68. a is stored in d. c. Introduced in PTX ISA version 1.x. . val. .b64. If c ≥ 0. .f32 flushes subnormal values of operand c to sign-preserving zero. .f64 }.u32. subnormal numbers are supported.s32 selp. . Semantics Floating Point Notes January 24.u16. sm_1x: slct. slct. based on the sign of the third operand.p.

7. Instructions and. This permits bit-wise operations on floating point values without having to define a union to access the bits. provided the operands are of the same size. or. performing bit-wise operations on operands of any type. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.0 8.4. and not also operate on predicates.PTX ISA Version 2. 2010 . The logical shift instructions are: and or xor not cnot shl shr 104 January 24. xor.

Chapter 8.type d. Allowed types include predicate registers. . and. .0x80000000. but not necessarily the type.pred p. .r.0. Table 71.q. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. or.b16. Instruction Set Table 70.b64 }.pred. Introduced in PTX ISA version 1. b.b32 mask mask. a.type = { .type d. Allowed types include predicate registers. Supported on all target architectures.pred.b16.b32. or Syntax Logic and Shift Instructions: or Bitwise OR. b. January 24.0x00010001 or. Supported on all target architectures.b32 and. d = a & b. sign.fpvalue.0.q.b64 }. The size of the operands must match. .b32.type = { . . Introduced in PTX ISA version 1. but not necessarily the type. 2010 105 .r. or. and. . d = a | b. a. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. and Syntax Logic and Shift Instructions: and Bitwise AND. . The size of the operands must match.b32 x.

Supported on all target architectures. but not necessarily the type. Supported on all target architectures. not. d = (a==0) ? 1 : 0. b. cnot. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. a. The size of the operands must match. Table 74.r.b16. Supported on all target architectures. but not necessarily the type.PTX ISA Version 2.b32. d = ~a. d.a.b32.b16 d. . not. . but not necessarily the type. cnot.b32.b64 }. a. .type d.b16. . Introduced in PTX ISA version 1.pred. .mask.q.type = { . a.x.pred p.type d.b32 mask. xor. xor. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. 2010 .b64 }. Introduced in PTX ISA version 1.0 Table 72. not Syntax Logic and Shift Instructions: not Bitwise negation.q.b16. . Allowed types include predicates.0. . .0x0001. Table 73. 106 January 24.type = { .b32 d. . .0. Introduced in PTX ISA version 1. The size of the operands must match.0. not. .type d. Allowed types include predicate registers.type = { .pred. d = a ^ b. one’s complement.b32 xor. The size of the operands must match.b64 }.

Instruction Set Table 75. . The sizes of the destination and first source operand must match. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.s16. .0. Shift amounts greater than the register width N are clamped to N. k. . PTX ISA Notes Target ISA Notes Examples January 24. Shift amounts greater than the register width N are clamped to N. shr.u32. zero-fill on right.b32. .1.0. Bit-size types are included for symmetry with SHL. Supported on all target architectures. d = a >> b.u64. unsigned and untyped shifts fill with 0. b. .u16. The b operand must be a 32-bit value.Chapter 8. shr.2.b16. .2. Introduced in PTX ISA version 1.b16 c. shl Syntax Logic and Shift Instructions: shl Shift bits left. . i.s32.type = { .b32 q. a. but not necessarily the type.b32. Signed shifts fill with the sign bit. a. Supported on all target architectures. The sizes of the destination and first source operand must match.type d.b64.u16 shr. .type = { . .s64 }. regardless of the instruction type. shr Syntax Logic and Shift Instructions: shr Shift bits right.a. .b16. Introduced in PTX ISA version 1. shl. sign or zero fill on left.i. The b operand must be a 32-bit value. b.s32 shr. regardless of the instruction type.i. 2010 107 .a.b64 }. .j. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. but not necessarily the type. PTX ISA Notes Target ISA Notes Examples Table 76. . d = a << b.type d. shl.

local. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. prefetchu isspacep cvta cvt 108 January 24. and from state space to state space. possibly converting it from one format to another. st. ld. Instructions ld.0 8. and st operate on both scalar and vector types.5. The cvta instruction converts addresses between generic and global. suld. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. and sust support optional cache operations. Data Movement and Conversion Instructions These instructions copy data from place to place.7. or shared state spaces. ldu. 2010 .PTX ISA Version 2. mov.

and a second thread loads that address via a second L1 cache with ld. when applied to a local address. likely to be accessed once. The cache operators require a target architecture of sm_20 or later.lu load last use operation. likely to be accessed again. Operator . When ld. Table 77.lu operation.7. The compiler / programmer may use ld.lu instruction performs a load cached streaming operation (ld. evict-first. rather than the data stored by the first thread. any existing cache lines that match the requested address in L1 will be evicted. . As a result of this request.cs) on global addresses.cg to cache loads only globally. A ld. If one thread stores to global memory via one L1 cache. but multiple L1 caches are not coherent for global data.cv to a frame buffer DRAM address is the same as ld.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.cs is applied to a Local window address. and cache only in the L2 cache.cs Cache streaming.cv Cache as volatile (consider cached system memory lines stale. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.Chapter 8. Global data is coherent at the L2 level. The ld. January 24.5. the cache operators have the following definitions and behavior. . to allow the thread program to poll a SysMem location written by the CPU. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.ca.cg Cache at global level (cache in L2 and below.0 introduces optional cache operators on load and store instructions. 2010 109 .cs.ca. The ld. The default load instruction cache operation is ld. not L1).1. bypassing the L1 cache. The ld. Use ld. The ld. fetch again). . it performs the ld.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. . if the line is fully covered.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.lu Last use. the second thread may get stale L1 cache data. For sm_20 and later.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. invalidates (discards) the local L1 line following the load. Cache Operators PTX 2.ca loads cached in L1. Instruction Set 8.

Addresses not in System Memory use normal write-back.wb for global data. and marks local L1 lines evict-first. not L1). . regardless of the cache operation.cg is the same as st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. but st. bypassing its L1 cache. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. Use st. The st.cg Cache at global level (cache in L2 and below.PTX ISA Version 2. The st. The default store instruction cache operation is st. to allow a CPU program to poll a SysMem location written by the GPU with st. which writes back cache lines of coherent cache levels with normal eviction policy. and a second thread in a different SM later loads from that address via a different L1 cache with ld. and discard any L1 lines that match. 110 January 24.wt store write-through operation applied to a global System Memory address writes through the L2 cache. bypassing the L1 cache.wt. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. likely to be accessed once. . Future GPUs may have globally-coherent L1 caches. If one thread stores to global memory. Operator . and cache only in the L2 cache.wb. rather than get the data from L2 or memory stored by the first thread. in which case st.cg to local memory uses the L1 cache.wb could write-back global store data from L1.cg to cache global store data only globally.cs Cache streaming. Global stores bypass L1. However. 2010 . In sm_20. st.ca loads.wt Cache write-through (to system memory).ca. the second thread may get a hit on stale L1 cache data. .0 Table 78. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.

local. alternately. . mov. .f32 mov.b64. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. u. within the variable’s declared state space Notes Although only predicate and bit-size types are required. d = &label. // get address of variable // get address of label or function . . .s16.b32. a.f32.global. Operand a may be a register. label. local.b16. i. . or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. A. avar.u16 mov. Introduced in PTX ISA version 1. local. For variables declared in . the parameter will be copied onto the stack and the address will be in the local state space. label..u32.1.type mov. // address is non-generic.s64.u16. d.f64 }. .type mov.u64. variable in an addressable memory space. . special register. Instruction Set Table 79. . d = &avar. Semantics d = a.u32 mov.0.pred.Chapter 8. Note that if the address of a device function parameter is moved to a register. or shared state space may be taken directly using the cvta instruction. or shared state space. d = sreg.type mov. .type = { . The generic address of a variable in global.. d. d. sreg. or function name. mov.u32 d. mov places the non-generic address of the variable (i.e. addr. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.a.e.type d.f32 mov. and . .f64 requires sm_13 or later.shared state spaces. 2010 111 . the generic address of a variable declared in global.const. .v. the address of the variable in its state space) into the destination register. ptr. ptr. k. . immediate. Description .u32 mov. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.0.s32. myFunc. Write register d with the value of a.local. mov. A[5]. Take the non-generic address of a variable in global.

mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).b16 // pack four 8-bit elements into .y. a[24.y << 16) | (a..b64 112 January 24.b.b16...x | (a. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. .type = { . d.b64 mov.x | (a.z.. mov.w << 48) d = a.{x.g.. a[48. a[8.b32 mov.b64 }.y << 32) // pack two 8-bit elements into .b32 { d.b64 // pack two 32-bit elements into .63] } // unpack 16-bit elements from .{a.y } = { a[0.y. Description Write scalar register d with the packed value of vector register a. %x.0.31].31].w } = { a[0. %r1.7].b32 { d.b}. a[16.type d. lo. or write vector register d with the unpacked values from scalar register a.b32.x. For bit-size types.w}.z << 32) | (a. d.b64 { d. a[32.15].a have type .x. mov.b32 // pack two 16-bit elements into .15]. d. d.%r1.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.y.PTX ISA Version 2.hi are .47].x.. d.w } = { a[0. a[8.z << 16) | (a. .b32 %r1.0 Table 80.15] } // unpack 8-bit elements from . a[16. {r..x. 2010 .b16 { d.u16 %x is a double.x | (a. // // // // a.z. d.x. d.x | (a. a[16.b have type ..u8 // unpack 32-bit elements from .b64 { d.y << 8) | (a.z.y } = { a[0.a}...y << 16) d = a.b32 // pack four 16-bit elements into .g.hi}. d.y << 8) d = a. .z..23]... a[32.y } = { a[0. d. Semantics d = a. Supported on all target architectures. {lo.15].31] } // unpack 8-bit elements from ..x | (a. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.31] } // unpack 16-bit elements from .b32 mov.w have type .w << 24) d = a.b8 r. a.u32 x.y.7].b.

shared }. The address size may be either 32-bit or 64-bit.cs. i.lu. an address maps to the corresponding location in local or shared memory. [a].local. and truncated if the register width exceeds the state space address width for the target architecture.u16.1.b8. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [a]. .s8.f64 using cvt. .s32. [a]. . Generic addressing may be used with ld.Chapter 8. .vec. ld. perform the load using generic addressing. the access may proceed by silently masking off low-order address bits to achieve proper rounding. an integer or bit-size type register reg containing a byte address.ss}{. . d. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. . .v4 }. 2010 113 .volatile{. PTX ISA Notes January 24.type = { . and is zeroextended to the destination register width for unsigned and bit-size types.ca. . .b16. and then converted to .param. ld introduced in PTX ISA version 1. .e. the resulting behavior is undefined.b32.cop}. If no state space is given.s64.e. Cache operations are not permitted with ld. Semantics d d d d = = = = a. d.ss = { . . to enforce sequential consistency between threads accessing shared memory.. Description Load register variable d from the location specified by the source address operand a in specified state space. If an address is not properly aligned.ss}. . 32-bit).v2. ld. .ss}.vec = { .type d. ld{.reg state space. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.global. The address must be naturally aligned to a multiple of the access size. . . .type ld. Generic addressing and cache operations introduced in PTX ISA 2.cop = { .b16.b64. . . This may be used. for example.const. Instruction Set Table 81. [a].const space suffix may have an optional bank number to indicate constant banks other than bank zero.type . Addresses are zero-extended to the specified width as needed.u32. an address maps to global memory unless it falls within the local memory window or the shared memory window. or [immAddr] an immediate absolute byte address (unsigned.s16. A destination register wider than the specified type may be used.global and .0.ss}{. Within these windows.volatile. In generic addressing.volatile{.type ld{. . or the instruction may fault. The value loaded is sign-extended to the destination register width for signed integers. The .volatile may be used with . . *(immAddr).volatile. *(a+immOff).shared spaces to inhibit optimization of references to volatile memory.cop}.cv }.vec. . .f32 or .f16 data may be loaded using ld. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. 32-bit). .volatile introduced in PTX ISA version 1.u8.f64 }.u64. .f32. . d. i.0.cg. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. *a. .

// access incomplete array x.0 Target ISA Notes ld.b64 ld.const.[p+4]. // negative offset %r. d.global.f32 ld. Generic addressing requires sm_20 or later.shared.global.[a].[p+-8]. x.b32 ld. // load .f32.v4.b16 cvt.f64 requires sm_13 or later.[buffer+64]. ld.[240]. // immediate address %r.%r.local.[p]. Cache operations require sm_20 or later. Q. 2010 .b32 ld. %r.b32 ld.const[4].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.[fs].PTX ISA Version 2.f16 d.s32 ld.local.

[p+4].u8. .f64 requires sm_13 or later.global }.ss}. ldu. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.type = { .s8.b16. ldu.f64 }.f16 data may be loaded using ldu.ss}. In generic addressing. A destination register wider than the specified type may be used. Addresses are zero-extended to the specified width as needed. . only generic addresses that map to global memory are legal. 32-bit). the access may proceed by silently masking off low-order address bits to achieve proper rounding.s16. or the instruction may fault.ss = { .b32 d. If no state space is given. .v4. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . If an address is not properly aligned. .b64. The address must be naturally aligned to a multiple of the access size. . For ldu. d. 32-bit).. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .type d. [a]. i.global.v2.global. .s64.f32 or .vec. Within these windows. .u16. [areg] a register reg containing a byte address. The value loaded is sign-extended to the destination register width for signed integers. The addressable operand a is one of: [avar] the name of an addressable variable var.v4 }. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. ldu.0. .f32 d. i. 2010 115 . an address maps to the corresponding location in local or shared memory.s32.f32. .f64 using cvt. The address size may be either 32-bit or 64-bit. perform the load using generic addressing. [a]. PTX ISA Notes Target ISA Notes Examples January 24. an address maps to global memory unless it falls within the local memory window or the shared memory window. and truncated if the register width exceeds the state space address width for the target architecture. . Semantics d d d d = = = = a.[a]. // state space .u32. . ldu{. ldu. . the resulting behavior is undefined. .type ldu{.f32 Q. *(immAddr). or [immAddr] an immediate absolute byte address (unsigned.vec = { . Introduced in PTX ISA version 2. A register containing an address may be declared as a bit-size type or integer type. // load from address // vec load from address .u64. The data at the specified address must be read-only.Chapter 8.b16.global. *(a+immOff).reg state space.b8. . where the address is guaranteed to be the same across all threads in the warp. and is zeroextended to the destination register width for unsigned and bit-size types.e.[p].b32. *a.e. Instruction Set Table 82. . and then converted to . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.

Generic addressing and cache operations introduced in PTX ISA 2.ss}.global.local.wb. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.f32. The lower n bits corresponding to the instruction-type width are stored to memory. . . .e.global and .PTX ISA Version 2.u64.b64. Within these windows.1.cop}.reg state space.type . perform the store using generic addressing. . [a].type st. A source register wider than the specified type may be used. . an address maps to global memory unless it falls within the local memory window or the shared memory window. or the instruction may fault.b16. *(immAddr) = a. { . an address maps to the corresponding location in local or shared memory.b16. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.u8. the resulting behavior is undefined. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.ss}{. In generic addressing.0.volatile introduced in PTX ISA version 1. This may be used. Generic addressing may be used with st. If no state space is given. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s8. . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . i.cop . PTX ISA Notes Target ISA Notes 116 January 24. . [a].cop}. 2010 .b32. .s64. Addresses are zero-extended to the specified width as needed.u32. . st introduced in PTX ISA version 1. an integer or bit-size type register reg containing a byte address.0.volatile{. i. b. [a].volatile. b.f64 }. 32-bit).u16. { . st.cg. . Semantics d = a.ss . b. 32-bit). Cache operations require sm_20 or later. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .b8. .wt }.v4 }. st{. .cs.0 Table 83. to enforce sequential consistency between threads accessing shared memory.ss}{. . .v2.vec.volatile{. *d = a. .vec . Cache operations are not permitted with st.type st{. Generic addressing requires sm_20 or later. st. . b. The address size may be either 32-bit or 64-bit.e. If an address is not properly aligned.type [a].shared spaces to inhibit optimization of references to volatile memory.vec.ss}.f64 requires sm_13 or later.type = = = = {. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. *(d+immOffset) = a. .f16 data resulting from a cvt instruction may be stored using st. or [immAddr] an immediate absolute byte address (unsigned.s16. .volatile may be used with . { .volatile.. and truncated if the register width exceeds the state space address width for the target architecture.s32. st. .shared }. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. for example. The address must be naturally aligned to a multiple of the access size.

%r.b16 [a]. [p]. [q+-8]. // negative offset [100].s32 st.r7.f32 st.global. [q+4].b32 st.f32 st.local.local.b32 st.%r.s32 cvt. // immediate address %r.Chapter 8.v4. // %r is 32-bit register // store lower 16 bits January 24.a.a.Q. 2010 117 .b. [fs].global. Instruction Set Examples st.local.f16.

to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. prefetch and prefetchu require sm_20 or later.global. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. prefetchu Prefetch line containing generic address at specified level of memory hierarchy. 32-bit). i.PTX ISA Version 2. or [immAddr] an immediate absolute byte address (unsigned.level = { .space}.L1. .0 Table 84. and truncated if the register width exceeds the state space address width for the target architecture. 118 January 24.L2 }.L1 [ptr]. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. an address maps to global memory unless it falls within the local memory window or the shared memory window. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.e. If no state space is given. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. 2010 . prefetchu.level prefetchu. a register reg containing a byte address. and no operation occurs if the address maps to a local or shared memory location. In generic addressing.space = { .L1 [addr]. . an address maps to the corresponding location in local or shared memory.0. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. . // prefetch to data cache // prefetch to uniform cache . Addresses are zero-extended to the specified width as needed. A prefetch into the uniform cache requires a generic address. prefetch{. prefetch. in specified state space.local }. Within these windows. A prefetch to a shared memory location performs no operation. the prefetch uses generic addressing. 32-bit). [a].L1 [a]. The address size may be either 32-bit or 64-bit. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch.global.

January 24. The source and destination addresses must be the same size. When converting a generic address into a global.lptr.size p. 2010 119 . lptr. p.size = { . isspacep requires sm_20 or later. cvta.shared }. .size cvta. cvta. . . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.u32 p. Description Convert a global. Use cvt. Take the generic address of a variable declared in global. Instruction Set Table 85.u32 or .global.global isspacep. local. the generic address of the variable may be taken using cvta. . A program may use isspacep to guard against such incorrect behavior. svar. local.local isspacep.local. islcl. // convert to generic address // get generic address of var // convert generic address to global.u32 p.u64.0.space = { .space p. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u64 }. or vice-versa. local.u64 or cvt.global.local.global. or shared state space.space.space = { . or shared address to a generic address.shared }. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.u32. The destination register must be of type . or vice-versa.shared. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.local. a.to. or shared state space. isspacep.space. a. cvta requires sm_20 or later. cvta.u32 gptr.u64. or shared address. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. The source address operand must be a register of type . gptr. sptr.shared isglbl. a. // local.u32. isspacep.to.pred.u32 to truncate or zero-extend addresses.0. isshrd. Introduced in PTX ISA version 2. // result is . local.space. local.size . . or shared address cvta.genptr. . PTX ISA Notes Target ISA Notes Examples Table 86. p. var. // get generic address of svar cvta. For variables declared in global.Chapter 8. or shared state space to generic.pred .

For cvt. The compiler will preserve this behavior for legacy PTX code.sat is redundant.f32 float-to-integer conversions and cvt.s64. a.u8.frnd}{. d = convert(a).sat}.0 Table 87. . Description Semantics Integer Notes Convert between different types and sizes. Saturation modifier: .sat For integer destination types. . The optional . . . i.f16. Note that saturation applies to both signed and unsigned integer types.ftz.4 and earlier.irnd = { .u64.sat limits the result to MININT.ftz. subnormal inputs are flushed to signpreserving zero.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.dtype.dtype = .dtype.sat}.s32. Integer rounding is illegal in all other instances. .s8.frnd = { . .rpi }.rni round to nearest integer. . For float-to-integer conversions. .f32 float-tofloat conversions with integer rounding.f32.atype d.ftz}{. choosing even integer if source is equidistant between two integers. . . and for same-size float-tofloat conversions where the value is rounded to an integer.u32. . .dtype.rni.ftz.irnd}{.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. subnormal inputs are flushed to signpreserving zero.ftz}{. .rzi.PTX ISA Version 2. d. subnormal numbers are supported. cvt{. sm_1x: For cvt.u16.rm. 120 January 24.f32 float-to-integer conversions and cvt.rzi round to nearest integer in the direction of zero . . .ftz.s16.ftz modifier may be specified in these cases for clarity. // integer rounding // fp rounding . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. the . .f32. .atype cvt{.f32.rz. 2010 . the result is clamped to the destination range by default. .dtype. Integer rounding is required for float-to-integer conversions.. . .atype = { .f32 float-tofloat conversions with integer rounding.rmi round to nearest integer in direction of negative infinity . .rn. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. a.f64 }. i.e..e.MAXINT for the size of the operation. Integer rounding modifiers: .rp }. Note: In PTX ISA versions 1.rmi. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range.

single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. The optional . and cvt. stored in floating-point format.ftz modifier may be specified in these cases for clarity. and . Modifier . The result is an integral value. cvt.0.f32.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f64 j.f64 requires sm_13 or later. Applies to . // float-to-int saturates by default cvt.sat limits the result to the range [0.f32.0.rni.4 or earlier. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.f32. if the PTX . cvt. // round to nearest int. . result is fp cvt. subnormal numbers are supported. 2010 121 .f64. cvt.f32 x.f32.rn mantissa LSB rounds to nearest even . Floating-point rounding is illegal in all other instances. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.y. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. The operands must be of the same size.f32 x.version is 1.f32.4 and earlier. . Subnormal numbers: sm_20: By default. 1. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .ftz behavior for sm_1x targets January 24.s32 f. NaN results are flushed to positive zero.f32.rm mantissa LSB rounds towards negative infinity . Saturation modifier: .f16. The compiler will preserve this behavior for legacy PTX code.f16.y.f64 types. Specifically.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).r.Chapter 8. Note: In PTX ISA versions 1.sat For floating-point destination types. // note .f32.f32 instructions.0].i. Introduced in PTX ISA version 1.f16. and for integer-to-float conversions. cvt to or from .rz mantissa LSB rounds towards zero . Floating-point rounding modifiers: .s32.

texref tex1 ) { txq. add.f32 r3.6.global . Example: calculate an element’s power contribution as element’s power/total number of elements.target texmode_independent . In the unified mode. sampler. r2. // get tex1’s txq.f32 r1.f32. r3. r5. {f1. [tex1]. [tex1]. The texturing mode is selected using . Texture and Surface Instructions This section describes PTX instructions for accessing textures. sampler. mul. and surface descriptors.PTX ISA Version 2. . If no texturing mode is declared.u32 r5. cvt. samplers. The advantage of unified mode is that it allows 128 samplers.f2}]. r3. but the number of samplers is greatly restricted to 16. allowing them to be defined separately and combined at the site of usage in the program. r1.width.height. 122 January 24.r4}. r1. r1. Module-scope and per-entry scope definitions of texture. r4. The advantage of independent mode is that textures and samplers can be mixed and matched.target options ‘texmode_unified’ and ‘texmode_independent’. Texturing modes For working with textures and samplers.b32 r5. . PTX has two modes of operation.r3. and surface descriptors. r5.f32 r1. In the independent mode. and surface descriptors.. and surfaces..f32.f32 {r1. add. . [tex1. } = clamp_to_border. and surface descriptors: • • • Static initialization of texture. add. // get tex1’s tex. r6. texture and sampler information each have their own handle. = nearest width height tsamp1. A PTX module may declare only one texturing mode.samplerref tsamp1 = { addr_mode_0 filter_mode }. sampler.u32 r5. r5.7. texture and sampler information is accessed through a single .param . div.f32 r1.v4.texref handle.0 8. the file is assumed to use unified mode.b32 r6.entry compute_power ( .2d. Ability to query fields within texture. with the restriction that they correspond 1-to-1 with the 128 possible textures. sampler.r2. PTX supports the following operations on texture. 2010 .

[tex_a. [a. A texture base address is assumed to be aligned to a 16-byte address.u32. sampler_x.r4}. //Example of unified mode texturing tex. b.r3.btype = { . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.f3.btype d. Unified mode texturing introduced in PTX ISA version 1. {f1. . Supported on all target architectures. If an address is not properly aligned. {f1}].f2.s32 {r1. [tex_a.1d. .. Instruction Set These instructions provide access to texture and surface memory. Operand c is a scalar or singleton tuple for 1d textures.r2. d.v4. // explicit sampler . the access may proceed by silently masking off low-order address bits to achieve proper rounding. .geom.e. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. c]. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.v4 coordinate vectors are allowed for any geometry. PTX ISA Notes Target ISA Notes Examples January 24. . tex txq suld sust sured suq Table 88.f32 {r1.dtype = { . An optional texture sampler b may be specified. tex. .geom. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. i. The instruction always returns a four-element vector of 32-bit values.3d }.dtype. // Example of independent mode texturing tex. and is a four-element vector for 3d textures. [a.dtype. the sampler behavior is a property of the named texture.s32.s32.r3.f32 }.v4. 2010 123 .0. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup.5. c].1d. Description Texture lookup using a texture coordinate vector.s32.v4. .Chapter 8. where the fourth element is ignored. If no sampler is specified.r4}.r2.geom = { .s32. the square brackets are not required and . with the extra elements being ignored.v4. or the instruction may fault.2d.3d. is a two-element vector for 2d textures.f4}].f32 }.btype tex. . the resulting behavior is undefined. Notes For compatibility with prior versions of PTX.

mirror. addr_mode_2 }. linear } Integer from enum { wrap.depth. sampler attributes are also accessed via a texref argument. d. [tex_A]. addr_mode_1.normalized_coords .height. [a].5. // texture attributes // sampler attributes .tquery.b32 %r1. [a].b32 %r1.normalized_coords }. .samplerref variable.filter_mode . .width . In unified mode.b32 d. Description Query an attribute of a texture or sampler. .tquery = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. txq.squery = { . . Integer from enum { nearest. Query: . clamp_to_edge. .PTX ISA Version 2. [tex_A].depth . txq.addr_mode_0 . txq.width.texref or .addr_mode_1 . Supported on all target architectures. [smpl_B].addr_mode_0.filter_mode. and in independent mode sampler attributes are accessed via a separate samplerref argument.height .squery.0 Table 89. txq. // unified mode // independent mode 124 January 24. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.width.b32 %r1.filter_mode.b32 txq.addr_mode_0. Operand a is a . 2010 . clamp_ogl.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).

.b32.1d. is a two-element vector for 2d surfaces.p is currently unimplemented.b32. and is a four-element vector for 3d surfaces. . {x}]. Operand a is a .trap . [surf_B.u32. If the destination base type is . suld.v4. If the destination type is . If an address is not properly aligned. .u32. Operand b is a scalar or singleton tuple for 1d surfaces. the resulting behavior is undefined. suld.f32 is returned. and A components of the surface format.clamp . if the surface format contains SINT data. the surface sample elements are converted to .trap {r1. . b].dtype. Instruction Set Table 90.z.0. . suld. additional clamp modifiers. suld. then .b .dtype.f32.f32 based on the surface format as follows: If the surface format contains UNORM.s32. Coordinate elements are of type .u32.s32.b performs an unformatted load of binary data. .cop .e. // cache operation none.f3.3d requires sm_20 or later.v4 }. where the fourth element is ignored.p . B.r2}. .vec.p. {f1. A surface base address is assumed to be aligned to a 16-byte address.w}].b supported on all target architectures.s32.b8 . size and type conversion is performed as needed to convert from the surface sample format to the destination type. [a. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .dtype . or .3d }. Cache operations require sm_20 or later.b.f4}.b16.trap suld. {x. suld Syntax Texture and Surface Instructions: suld Load from surface memory.trap clamping modifier.cv }. .s32.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. or .trap. if the surface format contains UINT data.b.b.v2. b].cop}.ca. and the size of the data transfer matches the size of destination operand d.geom . . The lowest dimension coordinate represents a sample offset rather than a byte offset. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.b32.zero }. The .u32 is returned.f32 }.clamp field specifies how to handle out-of-bounds addresses: . Target ISA Notes Examples January 24..v2. suld.b64 }. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. i. or FLOAT data. G.p requires sm_20 or later. . [surf_A. suld.v4. .dtype . . Description Load from surface memory using a surface coordinate vector.vec . [a.clamp. // unformatted d. .Chapter 8. suld. // formatted .p.geom{. .trap introduced in PTX ISA version 1. // for suld.y. suld.f2. . and cache operations introduced in PTX ISA version 2. // for suld. SNORM.2d.5. sm_1x targets support only the .s32 is returned.p.1d.b64.clamp = = = = = = { { { { { { d. Destination vector elements corresponding to components that do not appear in the surface format are not written.clamp suld. then . 2010 125 .cop}. . .p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. or the instruction may fault.f32.cg.geom{. suld.3d.surfref variable.cs. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.clamp . . then .

. . sust.f32.s32.geom{. where the fourth element is ignored.ctype .b. sust Syntax Texture and Surface Instructions: sust Store to surface memory.b // for sust.u32. if the surface format contains SINT data.1d. sust. then .v2.cop}. sm_1x targets support only the .zero }.clamp . then .{u32. . . G. The lowest dimension coordinate represents a sample offset rather than a byte offset. 2010 .cop . c.3d requires sm_20 or later. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. none. The size of the data transfer matches the size of source operand c. sust.3d }.wb.2d. b]. or the instruction may fault.f32} are currently unimplemented. . {f1. .p.geom . . {x}].zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.p. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Cache operations require sm_20 or later.cg.b32. B.clamp = = = = = = { { { { { { [a. . additional clamp modifiers.p. . // for sust.s32. .vec.ctype.b64. {r1.. b]. The source vector elements are interpreted left-to-right as R. These elements are written to the corresponding surface sample components.f4}.trap sust. . Surface sample components that do not occur in the source vector will be written with an unpredictable value. and is a four-element vector for 3d surfaces. or .f32 is assumed.e. Target ISA Notes Examples 126 January 24. The . is a two-element vector for 2d surfaces.b. If the source type is . If the source base type is . If an address is not properly aligned.b supported on all target architectures.trap.0 Table 91.s32.clamp.p performs a formatted store of a vector of 32-bit data values to a surface sample.v2.cs.3d.ctype. Operand b is a scalar or singleton tuple for 1d surfaces. and A surface components.b performs an unformatted store of binary data.surfref variable.wt }.trap .cop}.p requires sm_20 or later. Coordinate elements are of type .b8 .geom{. sust.f3. .v4 }.1d.z. .vec. {x.5.trap introduced in PTX ISA version 1.f32.p.b32.clamp . then . if the surface format contains UINT data. c. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . .y. The source data is then converted from this type to the surface sample format. or FLOAT data. .PTX ISA Version 2. sust.w}].b32.f32 }.clamp sust. sust. . // unformatted // formatted .vec . .p Description Store to surface memory using a surface coordinate vector. .0. and cache operations introduced in PTX ISA version 2. .ctype .f2.s32 is assumed.r2}. i. Operand a is a . [surf_B.trap [surf_A. Source elements that do not occur in the surface sample are ignored.u32.trap clamping modifier. the resulting behavior is undefined. sust. A surface base address is assumed to be aligned to a 16-byte address.clamp field specifies how to handle out-of-bounds addresses: . sust.b16.b. size and type conversions are performed as needed between the surface sample format and the destination type.s32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. sust. the access may proceed by silently masking off low-order address bits to achieve proper rounding. [a. SNORM.b64 }.u32 is assumed.v4.

.u32.trap [surf_A. sured requires sm_20 or later.u32. Operations add applies to .b.add.p .b32. .b32 }.c.clamp [a. The instruction type is restricted to .min. . . r1. .geom. the access may proceed by silently masking off low-order address bits to achieve proper rounding. . then . or . {x.ctype. .op. sured.b32 }.3d }. .trap .p.surfref variable. sured.u32.ctype = { .b performs an unformatted reduction on .min.b].b . Reduction to surface memory using a surface coordinate vector.b].clamp field specifies how to handle out-of-bounds addresses: .s32 or . . the resulting behavior is undefined..clamp = { . 2010 127 . sured. and the data is interpreted as . Operand b is a scalar or singleton tuple for 1d surfaces. if the surface format contains SINT data.geom = { .u32.1d. .e.s32. {x}]. min and max apply to . is a two-element vector for 2d surfaces.p.u32 and .0.c. where the fourth element is ignored.b. // for sured.u32 is assumed.p performs a reduction on sample-addressed 32-bit data. then . Coordinate elements are of type .trap.clamp . If an address is not properly aligned.add.s32.u64.Chapter 8. and is a four-element vector for 3d surfaces.u64. // for sured.y}].or }. sured.op. or the instruction may fault.2d.ctype. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. [surf_B.b32. and .zero }.op = { .clamp. A surface base address is assumed to be aligned to a 16-byte address. . // byte addressing sured.1d. // sample addressing . Operand a is a .u64 data. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .trap sured. . i.s32 types. The lowest dimension coordinate represents a sample offset rather than a byte offset.geom.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.s32 types.b32 type. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. Instruction Set Table 92. operations and and or apply to .ctype = { .u32 based on the surface sample format as follows: if the surface format contains UINT data. .and.b32.clamp [a.2d. r1. January 24.s32.s32 is assumed. The . . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.max. .

b32 d.depth }. . . . Description Query an attribute of a surface. Query: . [surf_A].surfref variable. 128 January 24. [a].query = { .b32 %r1.height.PTX ISA Version 2. suq.0 Table 93. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. Supported on all target architectures.height .width.5.width.query. suq.width . Operand a is a . 2010 .

b. { add. 2010 129 . Execute an instruction or instruction block for threads that have the guard predicate true.eq.Chapter 8.f32 @!p div. ratio.s32 a. Introduced in PTX ISA version 1.0. Supported on all target architectures.0. mov. setp. Threads with a false guard predicate do nothing. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. } PTX ISA Notes Target ISA Notes Examples Table 95.s32 d. used primarily for defining a function body.a. Supported on all target architectures. { instructionList } The curly braces create a group of instructions. {} Syntax Description Control Flow Instructions: { } Instruction grouping. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution. Instruction Set 8.f32 @q bra L23.x.y.c.7.7.0.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. If {!}p then instruction Introduced in PTX ISA version 1. @{!}p instruction. p.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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sync and bar.popc).red.cta.sync with an immediate barrier number is supported for sm_1x targets. while . the optional thread count must be a multiple of the warp size. a.arrive. bar. bar. Note that a non-zero thread count is required for bar. all threads in the CTA participate in the barrier. bar.0. bar.and).Chapter 8.. 2010 133 . When a barrier completes. it is as if all the threads in the warp have executed the bar instruction.sync bar.popc. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). Thus. bar.arrive a{.15.u32.red} introduced in PTX . and any-thread-true (.red performs a reduction operation across threads.and and .sync) until the barrier count is met.sync or bar. Operand b specifies the number of threads participating in the barrier.sync and bar. thread count. a{.or). Register operands. Operands a. PTX ISA Notes Target ISA Notes Examples bar.0. thread count.version 2.op = { . Each CTA instance has sixteen barriers numbered 0. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.red instruction. Since barriers are executed on a per-warp basis.red delays the executing threads (similar to bar. Barriers are executed on a per-warp basis as if all the threads in a warp are active. bar.u32 bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. Register operands. bar. January 24. a{.popc is the number of threads with a true predicate. bar. b.red should not be intermixed with bar.op. threads within a CTA that wish to communicate via memory can store to memory.sync 0. all-threads-true (. Thus. {!}c. bar. The reduction operations for bar. In addition to signaling its arrival at the barrier. Instruction Set Table 100.{arrive. Execution in this case is unpredictable. execute a bar. and the barrier is reinitialized so that it can be immediately reused.sync or bar. Only bar. The barrier instructions signal the arrival of the executing threads at the named barrier. d.red} require sm_20 or later. p. b}. the final value is written to the destination register in all threads waiting at the barrier. the waiting threads are restarted without delay. Description Performs barrier synchronization and communication within a CTA.red performs a predicate reduction across the threads participating in the barrier. b}.sync without a thread count introduced in PTX ISA 1.pred .arrive does not cause any waiting by the executing threads. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). the bar. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.arrive using the same active barrier. and d have type .red.or }. All threads in the warp are stalled until the barrier completes.red are population-count (. and bar. Once the barrier count is reached. b}. if any thread in a warp executes a bar instruction.red also guarantee memory ordering among threads identical to membar. and then safely read values stored by other threads prior to the barrier. The result of . . If no thread count is specified.{arrive. In conditionally executed code. it simply marks a thread's arrival at the barrier.and. b. {!}c. and bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. operands p and c are predicates.

this is the appropriate level of membar.gl.level = { . by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. and memory reads by this thread can no longer be affected by other thread writes.PTX ISA Version 2.sys requires sm_20 or later.gl will typically have a longer latency than membar.gl} supported on all target architectures. global. membar. membar. membar.gl.g. A memory write (e.version 1. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.4. that is. by st.gl.{cta. red or atom) has been performed when the value written has become visible to other clients at the specified level.cta.gl} introduced in PTX .level. membar. when the previous value can no longer be read.0. 134 January 24. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level.version 2. . Waits until prior memory reads have been performed with respect to other threads in the CTA.0 Table 101. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. membar.sys }.cta Waits until all prior memory writes are visible to other threads in the same CTA.sys introduced in PTX . .cta.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. membar.{cta. or system memory level.g. .sys. membar. membar. including thoses communicating via PCI-E such as system and peer-to-peer memory.sys Waits until all prior memory requests have been performed with respect to all clients. 2010 . level describes the scope of other clients for which membar is an ordering event. PTX ISA Notes Target ISA Notes Examples membar. membar.cta. membar. membar. membar. A memory read (e.sys will typically have much longer latency than membar. For communication between threads in different CTAs or even different SMs.

[a]. .type atom{.type d. . . . Addresses are zero-extended to the specified width as needed.b32 only . b. and max.op = { .exch to store to locations accessed by other atomic operations. . min.space}. min. or.f32 Atomically loads the original value at location a into destination register d.dec. . Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. The bit-size operations are and. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b32.b32.Chapter 8. Instruction Set Table 102. .shared }. atom.xor.f32. A register containing an address may be declared as a bit-size type or integer type. . cas (compare-and-swap). dec.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.. If an address is not properly aligned. perform the memory accesses using generic addressing.type = { .s32. inc. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. an address maps to global memory unless it falls within the local memory window or the shared memory window.cas.space = { . max. and exch (exchange). .op. i.s32. The address size may be either 32-bit or 64-bit.u32.s32. and max operations are single-precision.op. and stores the result of the specified operation at location a.add. 32-bit operations.u32..or. . . an address maps to the corresponding location in local or shared memory. . .e. January 24. .exch.space}.b64. . If no state space is given. . xor. The floating-point add. atom{. .global. the access may proceed by silently masking off low-order address bits to achieve proper rounding. The inc and dec operations return a result in the range [0. The floating-point operations are add. min. The integer operations are add.b]. a de-referenced register areg containing a byte address. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication. In generic addressing.b64 . . . accesses to local memory are illegal. . or [immAddr] an immediate absolute byte address.and. c. b. . i.max }. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.e. Within these windows. or by using atom. and truncated if the register width exceeds the state space address width for the target architecture. . For atom. .u64 . overwriting the original value. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. Operand a specifies a location in the specified state space.u32. or the instruction may fault. [a]. Description // // // // // . e.add. .g. The address must be naturally aligned to a multiple of the access size.inc. the resulting behavior is undefined. d.u32 only .u64.f32 }. 2010 135 .min. performs a reduction operation with operand b and the value in location a. by inserting barriers between normal stores and atomic operations to a common address.

: r-1.{min.0 Semantics atomic { d = *a.max} are unimplemented. Use of generic addressing requires sm_20 or later.b32 d. 64-bit atom.global.0. b).[x+4]. c) operation(*a.shared requires sm_12 or later.exch} requires sm_12 or later.s. Introduced in PTX ISA version 1.0. atom. atom. Release Notes Examples @p 136 January 24. : r+1. 64-bit atom. atom.global requires sm_11 or later. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. s) = (r >= s) ? 0 dec(r.s32 atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. s) = s.[a]. d.f32. atom.add.{add.my_val.shared. 2010 .1.f32 atom.f32 requires sm_20 or later.global.my_new_val.max.[p]. s) = (r > s) ? s exch(r.add.PTX ISA Version 2. atom.cas. *a = (operation == cas) ? : } where inc(r. cas(r. : r.t) = (r == s) ? t operation(*a.shared operations require sm_20 or later. b. d.cas.

dec.u64. or by using atom. .. min. inc.min. where inc(r. .s32. and stores the result of the specified operation at location a. For red. If no state space is given. A register containing an address may be declared as a bit-size type or integer type. Notes Operand a must reside in either the global or shared state space. b. .u32.or.global. an address maps to the corresponding location in local or shared memory. red.and. 2010 137 .g.xor. or. .u32.exch to store to locations accessed by other reduction operations.s32. . min.u32 only .type [a]. . overwriting the original value. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.f32 }.b32.b].space = { . or the instruction may fault. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . . If an address is not properly aligned. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. .. and truncated if the register width exceeds the state space address width for the target architecture. .max }. The address must be naturally aligned to a multiple of the access size.b64. min. Description // // // // . Semantics *a = operation(*a. and max. The floating-point add. The floating-point operations are add. by inserting barriers between normal stores and reduction operations to a common address. The inc and dec operations return a result in the range [0.Chapter 8. The integer operations are add. Operand a specifies a location in the specified state space. The bit-size operations are and. . accesses to local memory are illegal. . or [immAddr] an immediate absolute byte address.f32 Performs a reduction operation with operand b and the value in location a.u32. i.add.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.space}. Within these windows. . . perform the memory accesses using generic addressing. the resulting behavior is undefined.u64 . . s) = (r >= s) ? 0 : r+1. .add. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. dec.f32. and xor. 32-bit operations. e. dec(r.op. a de-referenced register areg containing a byte address. January 24. The address size may be either 32-bit or 64-bit. Instruction Set Table 103.shared }. . and max operations are single-precision. . max. . b). .e. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory.inc. Addresses are zero-extended to the specified width as needed. red{. an address maps to global memory unless it falls within the local memory window or the shared memory window. s) = (r > s) ? s : r-1.b32 only . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions.type = { .op = { . In generic addressing.s32. i.e.

1. [x+4].b32 [a]. Use of generic addressing requires sm_20 or later.shared operations require sm_20 or later.max} are unimplemented.2.s32 red.shared. 64-bit red. 64-bit red.shared requires sm_12 or later.global requires sm_11 or later red.PTX ISA Version 2.f32 requires sm_20 or later.my_val.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.max. 2010 .f32.global.and.f32 red.{min.global. red.add.add requires sm_12 or later. red. red. red.0. Release Notes Examples @p 138 January 24.add. [p].

any.q. r1. Negating the source predicate also computes .b32 d.all.ballot. returns bitmask . The destination predicate value is the same across all threads in the warp.all. . Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.uni.ballot.q.not_all. vote.pred vote.uni.pred d. Negate the source predicate to compute . // ‘ballot’ form. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Description Performs a reduction of the source predicate across threads in a warp. not across an entire CTA. // get ‘ballot’ across warp January 24.ballot. vote requires sm_12 or later.uni }.uni True if source predicate has the same value in all active threads in warp.Chapter 8. Negate the source predicate to compute . . vote.pred vote.mode. In the ‘ballot’ form.none. . where the bit position corresponds to the thread’s lane id.2.any True if source predicate is True for some active thread in warp. Note that vote applies to threads in a single warp.all True if source predicate is True for all active threads in warp. vote. Instruction Set Table 104. {!}a. {!}a.b32 p. vote. p.p. The reduction modes are: . .b32 requires sm_20 or later.ballot.mode = { . 2010 139 . vote.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.

bsel}.secop d.max }. . Using the atype/btype and asel/bsel specifiers. The type of each operand (.b1.bsel}. The sign of the intermediate result depends on dtype. a{. b{.h0. .b2. .b3.sat}. taking into account the subword destination size in the case of optional data merging. . The general format of video instructions is as follows: // 32-bit scalar operation.asel}. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).dtype. optionally clamp the result to the range of the destination type.atype = .btype{.atype.dsel = .btype = { .dtype.asel}. . The primary operation is then performed to produce an . // 32-bit scalar operation. . Video Instructions All video instructions operate on 32-bit register operands.dtype. . 140 January 24. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.9.0 8.sat} d. The source and destination operands are all 32-bit registers. a{. c. .min.or zero-extend byte.PTX ISA Version 2.u32 or . extract and sign. all combinations of dtype. a{.asel}.s32 }. b{.h1 }.asel = .s34 intermediate result. b{. perform a scalar arithmetic operation to produce a signed 34-bit result.u32.bsel = { .s32) is specified in the instruction type. or word values from its source operands. the input values are extracted and signor zero. half-word. 4.extended internally to . to produce signed 33-bit input values.7. with optional data merge vop. c. . with optional secondary operation vop.btype{. 2.sat} d. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.bsel}.dtype = .atype.dsel. vop. and btype are valid. 2010 . . atype.b0.atype.btype{. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand.add. 3.secop = { .s33 values. .

s33 tmp.b2.b0: return ((tmp & 0xff) case .b1: return ((tmp & 0xff) << 8) case .min: return MIN(tmp. S32_MAX.s34 tmp. U16_MIN ). as shown in the following pseudocode. tmp. c). c).max return MAX(tmp. c). U8_MAX. Instruction Set . c).h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. U8_MIN ). S8_MIN ).b3: if ( sign ) return CLAMP( else return CLAMP( case . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). U32_MAX.add: return tmp + c. . .h0: return ((tmp & 0xffff) case .b1.b0. Bool sign.s33 tmp. . . tmp. c). January 24.s33 c ) switch ( dsel ) { case . .s33 optMerge( Modifier dsel. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. U16_MAX. c).s33 optSecOp(Modifier secop. S8_MAX.s33 c) { switch ( secop ) { . tmp.b2: return ((tmp & 0xff) << 16) case . S32_MIN ). tmp. . } } . . default: return tmp. . U32_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. switch ( dsel ) { case . c). The sign of the c operand is based on dtype. tmp.s33 optSaturate( . Modifier dsel ) { if ( !sat ) return tmp. Bool sat. 2010 141 . . .h0. S16_MIN ).Chapter 8. The lower 32-bits are then written to the destination operand. . S16_MAX.h1: return ((tmp & 0xffff) << 16) case .

r3. // optional secondary operation d = optMerge( dsel. r2.s32. b{. c ).asel}.u32. r2. vadd.asel = . asel ). switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. c. b{.op2 d. // 32-bit scalar operation.b2. tmp.s32. r1.dtype. Integer byte/half-word/word minimum / maximum. . vsub. // extract byte/half-word/word and sign.PTX ISA Version 2. tmp.0 Table 105.b0. vmax Syntax Integer byte/half-word/word addition / subtraction.add r1. vmin. vsub. . 2010 . atype. btype. b{.dtype. tmp = MIN( ta. taking into account destination type and merge operations tmp = optSaturate( tmp.bsel}.s32 }.h1 }.dsel. a{. vop.sat vsub.asel}. vmax vadd.dtype. isSigned(dtype). // 32-bit scalar operation.u32. // optional merge with c operand 142 January 24.h0. r2.b0.h0. vabsdiff.atype. r1. Video Instructions: vadd. r3. sat. c.s32. vmin. a{. . . tb = partSelectSignExtend( b.b0.s32. tmp = | ta – tb |. tb ).b1.b2.dtype .btype{.max }.s32. c.s32.atype. a{.bsel = { . { .sat} d. .u32.h1. vadd.vop . Perform scalar arithmetic operation with optional saturate.asel}. .bsel}. bsel ).min. vmax }. vmin. tb ). r2. vsub vabsdiff vmin. vmax require sm_20 or later.dsel .sat vmin.s32. with optional data merge vop.s32.atype = .btype = { .btype{.sat} d. dsel ). r1. .h1. tmp = MAX( ta. r3. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vabsdiff. Integer byte/half-word/word absolute value of difference.add.sat. vsub. .b3. vabsdiff.s32.sat}.0. . c ). Semantics // saturate.h0.atype. c. . and optional secondary arithmetic operation or subword data merge. r3.or zero-extend based on source operand type ta = partSelectSignExtend( a.sat vabsdiff. tmp = ta – tb.bsel}.btype{.op2 Description = = = = { vadd. . with optional secondary operation vop.s32. d = optSecondaryOp( op2.

vshl: Shift a left by unsigned amount in b with optional saturate. { .atype = { .dtype. { .mode}. if ( mode == .u32.bsel = { . // optional secondary operation d = optMerge( dsel. r3. } // saturate.min.u32{. bsel ).Chapter 8. Semantics // extract byte/half-word/word and sign. // 32-bit scalar operation. c ).clamp. . January 24. Instruction Set Table 106. c. . d = optSecondaryOp( op2. r2.mode} d.u32. vshr Syntax Integer byte/half-word/word left / right shift.or zero-extend based on source operand type ta = partSelectSignExtend( a.dsel. .vop . dsel ). vshr require sm_20 or later. . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.asel = . a{. Video Instructions: vshl. // 32-bit scalar operation.dtype.b1. and optional secondary arithmetic operation or subword data merge.dtype.u32.s32 }.sat}{.h1 }.0. .atype. .sat}{.atype. with optional secondary operation vop.b2. tmp. b{.wrap ) tb = tb & 0x1f.add.op2 Description = = = = = { vshl. . vop.u32. 2010 143 .asel}. isSigned(dtype). r1. r2.u32. c ). tb = partSelectSignExtend( b.b0. and optional secondary arithmetic operation or subword data merge.mode . if ( mode == .dsel . . vshr }.bsel}. vshr: Shift a right by unsigned amount in b with optional saturate. // default is . sat. .max }.h1. . a{. c.bsel}.u32.sat}{. r3.wrap }.h0.bsel}. with optional data merge vop. a{.asel}. . b{.clamp . taking into account destination type and merge operations tmp = optSaturate( tmp.u32{. tmp. vshr vshl.dtype . Signed shift fills with the sign bit.u32 vshr.mode} d. .wrap r1. atype.u32{. case vshr: tmp = ta >> tb. Left shift fills with zero.atype. vshl. vshl.s32.b3.clamp && tb > 32 ) tb = 32. switch ( vop ) { case vshl: tmp = ta << tb. unsigned shift fills with zero. asel ).asel}.op2 d. b{.

“plus one” mode. {-}c. and the operand negates.asel = .b1. That is.b3. final signed (S32 * S32) + S32 // intermediate signed. Description Calculate (a*b) + c. . . The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.atype = . 144 January 24. The final result is unsigned if the intermediate result is unsigned and c is not negated.dtype = .S32 // intermediate signed.U32 // intermediate unsigned.btype{. . final signed (S32 * S32) .atype.scale} d. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. Although PTX syntax allows separate negation of the a and b operands. {-}b{. final unsigned -(U32 * U32) + S32 // intermediate signed.shr15 }.S32 // intermediate signed.s32 }. The source operands support optional negation with some restrictions. and zero-extended otherwise.asel}. The “plus one” mode (. a{.b0.S32 // intermediate signed.b2. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. {-}a{. .po) computes (a*b) + c + 1. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.po mode. Source operands may not be negated in . which is used in computing averages. final signed (U32 * S32) + S32 // intermediate signed. . otherwise. final signed (U32 * U32) . c. .u32.0 Table 107.scale} d.dtype.h0.btype = { . // 32-bit scalar operation vmad.shr7.scale = { .atype. vmad.bsel}. .sat}{. (a*b) is negated if and only if exactly one of a or b is negated. . Depending on the sign of the a and b operands. 2010 . final signed (S32 * U32) . final signed (S32 * U32) + S32 // intermediate signed. and scaling.dtype. PTX allows negation of either (a*b) or c. final signed -(S32 * S32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift.h1 }.btype. .bsel = { .PTX ISA Version 2. the intermediate result is signed. internally this is represented as negation of the product (a*b).sat}{.bsel}. b{. with optional operand negates. Input c has the same sign as the intermediate result. this result is sign-extended if the final result is signed..asel}. .po{. final signed -(U32 * S32) + S32 // intermediate signed. final signed (U32 * S32) . final signed -(S32 * U32) + S32 // intermediate signed.

negate) || c. } if ( .po ) { lsb = 1. tb = partSelectSignExtend( b.h0. vmad requires sm_20 or later.h0.u32. lsb = 0.shr15: result = (tmp >> 15) & 0xffffffffffffffff.negate ^ b.u32. r3. tmp = tmp + c128 + lsb. atype. switch( scale ) { case .Chapter 8. bsel ).negate ) { c = ~c. r0. signedFinal = isSigned(atype) || isSigned(btype) || (a. btype. 2010 145 . } else if ( c.sat ) { if (signedFinal) result = CLAMP(result.negate ) { tmp = ~tmp. if ( .sat vmad. vmad.s32. else result = CLAMP(result. } else if ( a. asel ). } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).negate ^ b. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0. r2. U32_MAX.s32.shr7: result = (tmp >> 7) & 0xffffffffffffffff. case .shr15 r0.u32. January 24. -r3. S32_MAX. U32_MIN). lsb = 1. Instruction Set Semantics // extract byte/half-word/word and sign. tmp[127:0] = ta * tb. r1. S32_MIN). r2. lsb = 1.negate.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a. r1.

0 Table 108. b{.btype. 146 January 24.asel}.ge }.atype. r2.cmp d.eq.bsel}.bsel}.op2 d. a{.u32.btype. .cmp .atype. .0.btype. with optional secondary operation vset. cmp ) ? 1 : 0. a{. // optional secondary operation d = optMerge( dsel. . with optional data merge vset.PTX ISA Version 2.max }. r3.s32 }.b2.btype = { .h1 }.u32. r1. 2010 . .op2 Description = = = = . c ). . . a{.dsel. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.h1. b{. r3. vset. The intermediate result of the comparison is always unsigned. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.asel}. vset. btype.gt.u32. tmp. Compare input values using specified comparison.h0. // 32-bit scalar operation.b1.lt vset. c ).b3.dsel . tb. d = optSecondaryOp( op2. Semantics // extract byte/half-word/word and sign.add.bsel}. { . tb = partSelectSignExtend( b.cmp d. .ne.atype . r2.lt. .b0. c. atype.bsel = { .min.s32. bsel ). { .atype. asel ). tmp. . . . .or zero-extend based on source operand type ta = partSelectSignExtend( a.le. and therefore the c operand and final result are also unsigned.cmp.ne r1. . . // 32-bit scalar operation.u32. c. .asel = . vset requires sm_20 or later.asel}. with optional secondary arithmetic operation or subword data merge. tmp = compare( ta. b{.

brkpt.10. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. trap. Instruction Set 8. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. trap. Notes PTX ISA Notes Target ISA Notes Examples Currently. Supported on all target architectures. @p pmevent 1.7. trap Abort execution and generate an interrupt to the host CPU. Introduced in PTX ISA version 1.Chapter 8.0. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. 2010 147 . Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. numbered 0 through 15. Table 110. January 24. Triggers one of a fixed number of performance monitor events. with index specified by immediate operand a. Introduced in PTX ISA version 1. there are sixteen performance monitor events. brkpt requires sm_11 or later. Table 111. brkpt Suspends execution Introduced in PTX ISA version 1. brkpt.4. pmevent a. Supported on all target architectures.0. The relationship between events and counters is programmed via API calls from the host. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. pmevent 7.

2010 .PTX ISA Version 2.0 148 January 24.

Special Registers PTX includes a number of predefined. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. which are visible as special registers and accessed through mov or cvt instructions. %clock64 %pm0. %lanemask_gt %clock. %lanemask_lt. ….Chapter 9. %pm3 January 24. %lanemask_ge. %lanemask_le. read-only variables. 2010 149 .

u32 %ntid.u32 %r0. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.x. %tid.x to %rh Target ISA Notes Examples // legacy PTX 1.%tid.u32 %tid.y.x.sreg . 2D. Supported on all target architectures. CTA dimensions are non-zero.x.u32.u16 %rh. mad.%tid.x code Target ISA Notes Examples 150 January 24.0.x.u32 %h1.0. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. // move tid.x. the fourth element is unused and always returns zero. read-only.z == 1 in 1D CTAs. 2010 .z == 0 in 1D CTAs. Supported on all target architectures.0. mov.PTX ISA Version 2.%r0.sreg .%tid.0 Table 112. .y.y < %ntid.sreg .v4 . // compute unified thread id for 2D CTA mov.z < %ntid. // legacy PTX 1. .u32 %h2.x. . %ntid.z == 1 in 2D CTAs.u16 %r2. Every thread in the CTA has a unique %tid.y == %ntid. %tid.%tid.z.x. PTX ISA Notes Introduced in PTX ISA version 1.0.x 0 <= %tid.x * %ntid. Redefined as . .u32 type in PTX 2.x code accessing 16-bit component of %tid mov.y 0 <= %tid.z PTX ISA Notes Introduced in PTX ISA version 1.%tid. %tid.u32 %r0.z.u32 type in PTX 2. The fourth element is unused and always returns zero. The number of threads in each dimension are specified by the predefined special register %ntid.y == %tid.v4. // thread id vector // thread id components A predefined. %ntid.v4 . cvt. The total number of threads in a CTA is (%ntid. or 3D vector to match the CTA shape.%h1. %tid. %ntid.u32 %ntid.x < %ntid.z.%h2.u32 %tid.y * %ntid.sreg .%ntid.z == 0 in 2D CTAs. per-thread special register initialized with the thread identifier within the CTA. %tid component values range from 0 through %ntid–1 in each CTA dimension.%ntid.y. %ntid. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.u16 %rh. mov.z to %r2 Table 113. The %tid special register contains a 1D.v4. // zero-extend tid. mov. read-only special register initialized with the number of thread ids in each CTA dimension. mov.u32 %r1.z). Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. // CTA shape vector // CTA dimensions A predefined. Redefined as . It is guaranteed that: 0 <= %tid. the %tid value in unused dimensions is 0.

Table 115.sreg . Note that %warpid is volatile and returns the location of a thread at the moment when read. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. mov.u32 %warpid. %laneid. mov.u32 %laneid. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Supported on all target architectures. 2010 151 . %nwarpid. Supported on all target architectures. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. Introduced in PTX ISA version 1. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.u32 %r. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. The lane identifier ranges from zero to WARP_SZ-1. A predefined.sreg . For this reason. Special Registers Table 114. due to rescheduling of threads following preemption. read-only special register that returns the maximum number of warp identifiers. A predefined. .u32 %r. Introduced in PTX ISA version 1. read-only special register that returns the thread’s lane within the warp. January 24.sreg .u32 %r. %warpid.3.Chapter 9. read-only special register that returns the thread’s warp identifier. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.u32 %nwarpid. A predefined. e. Introduced in PTX ISA version 2. PTX ISA Notes Target ISA Notes Examples Table 116. but its value may change during execution. .g. The warp identifier will be the same for all threads within a single warp. %nwarpid requires sm_20 or later. .0.3. mov.

x code Target ISA Notes Examples 152 January 24. The %ctaid special register contains a 1D. It is guaranteed that: 1 <= %nctaid.%ctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.%ctaid.y.{x. .y < %nctaid.u32 %nctaid .x. The %nctaid special register contains a 3D grid shape vector.0.x.u16 %r0. depending on the shape and rank of the CTA grid.0 Table 117.sreg .y.u32 type in PTX 2.y.z < %nctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u32 %ctaid. %rh. %ctaid.u32 mov. The fourth element is unused and always returns zero. .0. with each element having a value of at least 1.%nctaid.x.z} < 65. .y 0 <= %ctaid.v4 . Each vector element value is >= 0 and < 65535. %rh.0.536 PTX ISA Notes Introduced in PTX ISA version 1.sreg .z.v4.z PTX ISA Notes Introduced in PTX ISA version 1.y. It is guaranteed that: 0 <= %ctaid.u16 %r0. 2D.u32 %nctaid.PTX ISA Version 2.%nctaid.u32 type in PTX 2.x. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. Supported on all target architectures. %ctaid.%nctaid.sreg .x.v4. read-only special register initialized with the number of CTAs in each grid dimension. Supported on all target architectures.0.z.x 0 <= %ctaid.u32 mov.sreg . 2010 .v4 . // legacy PTX 1. Redefined as .x code Target ISA Notes Examples Table 118. Redefined as . mov. // legacy PTX 1. The fourth element is unused and always returns zero. // Grid shape vector // Grid dimensions A predefined.%nctaid. read-only special register initialized with the CTA identifier within the CTA grid. or 3D vector.u32 %ctaid. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.x < %nctaid. // CTA id vector // CTA id components A predefined. mov.

Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Introduced in PTX ISA version 2. Special Registers Table 119. This variable provides the temporal grid launch number for this context. due to rescheduling of threads following preemption.sreg . mov. read-only special register that returns the maximum number of SM identifiers. %gridid. %nsmid. .u32 %nsmid. . 2010 153 . %smid. PTX ISA Notes Target ISA Notes Examples January 24.u32 %gridid. where each launch starts a grid-of-CTAs. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. // initialized at grid launch A predefined. A predefined.3. Note that %smid is volatile and returns the location of a thread at the moment when read.u32 %r. Supported on all target architectures. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers.0. PTX ISA Notes Target ISA Notes Examples Table 121. During execution.u32 %r.u32 %r.sreg . mov.g. The SM identifier numbering is not guaranteed to be contiguous.sreg . The SM identifier ranges from 0 to %nsmid-1. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. A predefined.Chapter 9. e. %nsmid requires sm_20 or later. repeated launches of programs may occur. read-only special register initialized with the per-grid temporal grid identifier. but its value may change during execution.u32 %smid. . mov. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Notes PTX ISA Notes Target ISA Notes Examples Table 120. Supported on all target architectures. so %nsmid may be larger than the physical number of SMs in the device. The SM identifier numbering is not guaranteed to be contiguous.0.

u32 %r. A predefined. 2010 . .u32 %r.0. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.sreg .0. %lanemask_lt requires sm_20 or later.0 Table 122. Table 124.0. A predefined. 154 January 24. Introduced in PTX ISA version 2. Introduced in PTX ISA version 2.sreg . %lanemask_le requires sm_20 or later. mov. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. Table 123.sreg . Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. . . %lanemask_le. %lanemask_eq requires sm_20 or later. mov.u32 %lanemask_eq. %lanemask_lt. mov.u32 %r.PTX ISA Version 2.u32 %lanemask_lt. %lanemask_eq.u32 %lanemask_le. A predefined. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.

read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. January 24. Introduced in PTX ISA version 2.sreg . Introduced in PTX ISA version 2. %lanemask_gt.u32 %lanemask_gt. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov. .0. A predefined. %lanemask_ge.0.u32 %r. Special Registers Table 125.sreg .u32 %r. %lanemask_gt requires sm_20 or later.Chapter 9. . %lanemask_ge requires sm_20 or later. A predefined. 2010 155 .u32 %lanemask_ge. Table 126.

%clock. Special registers %pm0. The lower 32-bits of %clock64 are identical to %clock. …. . 2010 . . read-only 32-bit unsigned cycle counter. Table 128. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. Introduced in PTX ISA version 1.PTX ISA Version 2. .u32 r1.sreg . %pm3. mov. mov.0. read-only 64-bit unsigned cycle counter. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Table 129. %pm2. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.u64 %clock64. Their behavior is currently undefined. %pm2.%clock64.sreg . %pm3 %pm0.0. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. Supported on all target architectures. Special Registers: %pm0. Introduced in PTX ISA version 1. %pm1. %pm1. 156 January 24.u32 %clock.sreg . mov.u32 r1. %pm1.%pm0.3. Introduced in PTX ISA version 2.u64 r1. and %pm3 are unsigned 32-bit read-only performance monitor counters.u32 %pm0. %pm2.0 Table 127. Supported on all target architectures. %clock64 requires sm_20 or later. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.

version 1.target Table 130. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . minor are integers Specifies the PTX language version number.0 .1. PTX File Directives: .version directive.4 January 24.version directives are allowed provided they match the original .0.version .Chapter 10. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version Syntax Description Semantics PTX version number. Supported on all target architectures.minor // major. 2010 157 . . Each ptx file must begin with a .version 2.version directive. Duplicate . . and the target architecture for which the code was generated.version .version major. Increments to the major number indicate incompatible changes to PTX. Directives 10.

sm_12. sm_11.f32. Supported on all target architectures. The following table summarizes the features in PTX that vary according to target architecture.target directives can be used to change the set of target features allowed during parsing.global. but subsequent . Adds {atom. including expanded rounding modifiers. and an error is generated if an unsupported feature is used.global. Adds double-precision support.texmode_independent texture and sampler information is bound together and accessed via a single .texref descriptor.samplerref descriptors.shared. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Texturing mode: (default is .0 Table 131. Disallows use of map_f64_to_f32. sm_10.PTX ISA Version 2. In general. A . . vote instructions. The texturing mode is specified for an entire module and cannot be changed within the module.f64 instructions used.texmode_unified .target Syntax Architecture and Platform target. sm_13.red}. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.f64 instructions used.target directive containing a target architecture and optional platform options. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set.5. Adds {atom.texref and . map_f64_to_f32 }. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. brkpt instructions. 158 January 24.f64 to . A program with multiple . Introduced in PTX ISA version 1. Description Specifies the set of features in the target architecture for which the current ptx code was generated. Each PTX file must begin with a .texmode_unified) .target directive specifies a single target architecture.f64 storage remains as 64-bits. Therefore. texture and sampler information is referenced with independent .version directive.f64 instructions used.red}. PTX code generated for a given target can be run on later generation devices. PTX File Directives: .target . Note that . texmode_unified. PTX features are checked against the specified target architecture. Texturing mode introduced in PTX ISA version 1. with only half being used by instructions converted from .red}. where each generation adds new features and retains all features of previous generations. generations of SM architectures follow an “onion layer” model. immediately followed by a . Target sm_20 Description Baseline feature set for sm_20 architecture.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Requires map_f64_to_f32 if any . Requires map_f64_to_f32 if any . 2010 . Requires map_f64_to_f32 if any .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. texmode_independent.0. 64-bit {atom.

target sm_20. Directives Examples .target sm_13 // supports double-precision .Chapter 10.target sm_10 // baseline target architecture . 2010 159 . texmode_independent January 24.

surfref variables may be passed as parameters.0 through 1. .5 and later. and .PTX ISA Version 2. etc.entry cta_fft . ld.entry filter ( .entry kernel-name kernel-body Defines a kernel entry point name. . Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. ld.b32 x. In addition to normal parameters.param . Parameters may be referenced by name within the kernel body and loaded into registers using ld.b32 z ) Target ISA Notes Examples [x]. Kernel and Function Directives: .b32 y. .param.samplerref.entry . .entry Syntax Description Kernel entry point and body.4 and later. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.func Table 132. 160 January 24.b32 %r3. Semantics Specify the entry point for a kernel program. [z]. store. and body for the kernel function.reg .2.entry . PTX ISA Notes For PTX ISA version 1. For PTX ISA versions 1. the kernel dimensions and properties are established and made available via special registers. . [y].b32 %r<99>. parameters. These parameters can only be referenced by name within texture and surface load.3. %ntid.param instructions.0 through 1. ld.b32 %r1. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.param. and query instructions and cannot be accessed via ld.entry kernel-name ( param-list ) kernel-body .param { .4. 2010 . opaque . .texref.param.param .b32 %r2. %nctaid. with optional parameters.param instructions.0 10.param space memory and are listed within an optional parenthesized parameter list.g. Parameters are passed via . parameter variables are declared in the kernel parameter list. e. … } . At kernel launch. parameter variables are declared in the kernel body. Supported on all target architectures. The shape and size of the CTA executing the kernel are available in special registers.

mov. . .param and st. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 localVar. dbl.reg . The implementation of parameter passing is left to the optimizing translator. implements an ABI with stack.Chapter 10. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. Release Notes For PTX ISA version 1. including input and return parameters and optional function body.func fname (param-list) function-body .reg .result.0 with target sm_20 supports at most one return value. 2010 161 . A .param space are accessed using ld. there is no stack.b32 N. Parameters in . if any. Variadic functions are represented using ellipsis following the last fixed argument. PTX 2. val1).reg .func (ret-param) fname (param-list) function-body Defines a function. .b32 rval. Kernel and Function Directives: . parameters must be in the register state space. Supported on all target architectures.func Syntax Function definition.func definition with no body provides a function prototype. … use N. which may use a combination of registers and stack locations to pass parameters. The parameter lists define locally-scoped variables in the function body. foo. Parameters must be base types in either the register or parameter state space. PTX ISA 2.func (. … Description // return value in fooval January 24.func .2 for a description of variadic functions. Parameters in register state space may be referenced directly within instructions in the function body.b32 rval) foo (. and recursion is illegal.param state space.x code. Parameter passing is call-by-value. ret.param instructions in the body. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. (val0. and supports recursion.0. Variadic functions are currently unimplemented.reg .f64 dbl) { . other code.func fname function-body .0 with target sm_20 allows parameters in the . Directives Table 133. } … call (fooval).

A general .maxntid . .maxntid directive specifies the maximum number of threads in a thread block (CTA). which pass information to the backend optimizing compiler.pragma directive is supported for passing information to the PTX backend.0 10.maxnreg .maxnreg. the . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.maxnctapersm (deprecated) . to throttle the resource requirements (e. and the .3. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.entry directive and its body. Currently. The interpretation of .PTX ISA Version 2. and the strings have no semantics within the PTX virtual machine model.maxntid. the . registers) to increase total thread count and provide a greater opportunity to hide memory latency.g. PTX supports the following directives.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. . or as statements within a kernel or device function body.pragma directives may appear at module (file) scope. 162 January 24. 2010 . and .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.pragma The . Note that .minnctapersm . at entry-scope. for example.minnctapersm directives may be applied per-entry and must appear between an . The directive passes a list of strings to the backend. The . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. The directives take precedence over any module-level constraints passed to the optimizing backend.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. These can be used.maxntid and .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).

for example.maxntid 16.maxntid 256 . nz Declare the maximum number of threads in the thread block (CTA).entry foo . or the maximum number of registers may be further constrained by . Supported on all target architectures. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Performance-Tuning Directives: . The actual number of registers used may be less. ny. ny .maxnreg .3. Directives Table 134.maxntid nx. the backend may be able to compile to fewer registers.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.entry foo .maxntid nx. This maximum is specified by giving the maximum extent of each dimention of the 1D.entry bar .maxctapersm. Supported on all target architectures. . Exceeding any of these limits results in a runtime error or kernel launch failure.Chapter 10. The maximum number of threads is the product of the maximum extent in each dimension.maxntid Syntax Maximum number of threads in thread block (CTA). The compiler guarantees that this limit will not be exceeded.maxntid and .maxntid nx .maxntid .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. 2010 163 .maxnreg n Declare the maximum number of registers per thread in a CTA. . Performance-Tuning Directives: . . 2D. or 3D CTA.16.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. .3.

Supported on all target architectures.maxntid to be specified as well.0 Table 136. .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). Optimizations based on . additional CTAs may be mapped to a single multiprocessor. .entry foo . .maxntid 256 .minnctapersm .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. 2010 . Optimizations based on . However. Introduced in PTX ISA version 1. Supported on all target architectures.minnctapersm generally need .maxnctapersm.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Performance-Tuning Directives: .maxntid 256 .0 as a replacement for .maxnctapersm has been renamed to . Introduced in PTX ISA version 2.maxntid and .maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.minnctapersm 4 { … } 164 January 24.PTX ISA Version 2.entry foo .maxntid to be specified as well. Deprecated in PTX ISA version 2. The optimizing backend compiler uses .maxnctapersm (deprecated) . if the number of registers used by the backend is sufficiently lower than this bound.3.0.minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.minnctapersm in PTX ISA version 2. For this reason.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). . . Performance-Tuning Directives: .maxnctapersm generally need .0.

// disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . { … } January 24. at entry-scope.pragma directive may occur at module-scope. See Appendix A for descriptions of the pragma strings defined in ptxas. or at statementlevel.0. Performance-Tuning Directives: . .pragma “nounroll”. 2010 165 .pragma directive strings is implementation-specific and has no impact on PTX semantics.Chapter 10. . or statement-level directives to the PTX backend compiler. Pass module-scoped. entry-scoped. Supported on all target architectures.entry foo . Introduced in PTX ISA version 2.pragma Syntax Description Pass directives to PTX backend compiler. The interpretation of .pragma list-of-strings . The . Directives Table 138.pragma .pragma “nounroll”.

Table 139.4byte . @progbits . 0x00.4byte label .section directive is new in PTX ISA verison 2.x code. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information..4. 0x00 . 0x6150736f. Supported on all target architectures. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .0 but is supported for legacy PTX version 1.4byte int32-list // comma-separated hexadecimal integers in range [0.section . 0x00. @@DWARF dwarf-string dwarf-string may have one of the .0 and replaces the @@DWARF syntax. 0x61395a5f.264-1] .quad int64-list // comma-separated hexadecimal integers in range [0.byte 0x2b.byte 0x00. 0x02.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.section . Deprecated as of PTX 2. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00 166 January 24.232-1] . 0x00.byte byte-list // comma-separated hexadecimal byte values .. 0x736d6172 .0.2.loc The .PTX ISA Version 2.debug_info .4byte 0x000006b5. 0x00. 0x5f736f63 . 2010 . The @@DWARF syntax is deprecated as of PTX version 2. 0x63613031.file .0 10. 0x00.debug_pubnames. 0x00000364.4byte 0x6e69616d. replaced by . Introduced in PTX ISA version 1. 0x00. “”.section directive.

0x736d6172 0x00 Table 141. Debugging Directives: . Supported on all target architectures. 0x00. replaces @@DWARF syntax.0. Debugging Directives: . 0x00.section . . .file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.255] .0.section Syntax PTX section definition.b8 byte-list // comma-separated list of integers in range [0.b32 int32-list // comma-separated list of integers in range [0.b64 int64-list // comma-separated list of integers in range [0.file .b32 0x000006b5.b32 label . 2010 167 .. 0x63613031.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 . Directives Table 140. 0x00. Source file location. . .b8 0x2b. . 0x00.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.debug_info . .debug_pubnames { .loc line_number January 24. Supported on all target architectures.0. 0x00.section .b8 0x00.section section_name { dwarf-lines } dwarf-lines have the following formats: .264-1] .b32 0x6e69616d. 0x00000364. 0x00. 0x5f736f63 0x6150736f. Supported on all target architectures. .. Source file information. 0x00 0x61395a5f..232-1] .loc . } 0x02. Debugging Directives: .file filename Table 142.Chapter 10.

2010 .visible .extern identifier Declares identifier to be defined externally.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. . Introduced in PTX ISA version 1.global .6.b32 foo.visible identifier Declares identifier to be externally visible. Linking Directives: .extern . // foo is defined in another module Table 144.visible .0. Supported on all target architectures. Linking Directives .b32 foo.PTX ISA Version 2.extern . Supported on all target architectures.extern .visible Table 143.0 10. Introduced in PTX ISA version 1. Linking Directives: .global . .0. // foo will be externally visible 168 January 24. . .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.

1 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0. 2010 169 . and the remaining sections provide a record of changes in previous releases.0 PTX ISA 1.5 PTX ISA 2.2 PTX ISA 1.0 CUDA 2.0 CUDA 1.1 CUDA 2.Chapter 11. Release Notes This section describes the history of change in the PTX ISA and implementation.3 driver r190 CUDA 3.1 CUDA 2.0 January 24.0 driver r195 PTX ISA Version PTX ISA 1.4 PTX ISA 1.3 PTX ISA 1. The release history is as follows.2 CUDA 2. CUDA Release CUDA 1.

and double-precision div. Single-precision add. Both fma. and mul now support . Changes in Version 2. sub. Single.ftz and . When code compiled for sm_1x is executed on sm_20 devices. and sqrt with IEEE 754 compliant rounding have been added.1. The goal is to achieve IEEE 754 compliance wherever possible.1.1.f32 instruction also supports . Instructions testp and copysign have been added. The mad.sat modifiers.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. A single-precision fused multiply-add (fma) instruction has been added.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.rm and .f32 and mad. These are indicated by the use of a rounding modifier and require sm_20.f32 require a rounding modifier for sm_20 targets.x code and sm_1x targets. mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.f32 for sm_20 targets.rn. The changes from PTX ISA 1.0 for sm_20 targets.1. The mad. while maximizing backward compatibility with legacy PTX 1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. 2010 .1. fma.f32 maps to fma. rcp.f32.0 11.ftz modifier may be used to enforce backward compatibility with sm_1x. New Features 11. Floating-Point Extensions This section describes the floating-point changes in PTX 2.PTX ISA Version 2. The fma. • • • • • 170 January 24. The .rp rounding modifiers for sm_20 targets.f32 requires sm_20.0 11.1.

minnctapersm to better match its behavior and usage. A “find leading non-sign bit” instruction.add.zero.shared have been extended to handle 64-bit data types for sm_20 targets. ldu. A “population count” instruction.le. have been added.red}.clamp and . Instruction sust now supports formatted surface stores.1. A new directive.1.maxnctapersm directive was deprecated and replaced with . local. A “bit reversal” instruction. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. A system-level membar instruction. Instructions {atom. e. . Instruction cvta for converting global. has been added. Video instructions (includes prmt) have been added. st.red}. The . Surface instructions support additional . membar. has been added. Cache operations have been added to instructions ld. has been added. has been added. bfe and bfi. Bit field extract and insert instructions. st. New instructions A “load uniform” instruction.red. %clock64. prefetch. isspacep. 2010 171 . and shared addresses to generic address and vice-versa has been added. popc. brev. A “count leading zeros” instruction.b32. for prefetching to specified level of memory hierarchy. and red now support generic addressing. Instructions bar.f32 have been implemented.{and. Instructions prefetch and prefetchu have also been added. Other new features Instructions ld. A “vote ballot” instruction. ldu. 11. New special registers %nsmid. clz.lt. has been added.ballot.2. bfind.sys.ge.arrive instruction has been added.section.3.g. vote. prefetchu. Release Notes 11. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX.clamp modifiers.u32 and bar. .pred have been added.gt} have been added. atom.Chapter 11.1. bar now supports optional thread count and register operands. January 24. suld.1.or}. cvta. has been added. and sust. %lanemask_{eq. Instructions {atom. The bar instruction has been extended as follows: • • • A bar.red.popc.

p. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.{u32. where .{min. Formatted surface store with . Formatted surface load is unimplemented.max} are not implemented.s32.1. See individual instruction descriptions for details. . call suld.0 11.3.version is 1.s32.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.red}. 11. Semantic Changes and Clarifications The errata in cvt. In PTX version 1.target sm_1x. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.ftz for PTX ISA versions 1. Instruction bra.2. 172 January 24.1.f32 type is unimplemented. has been fixed. cvt. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. the correct number is sixteen. or .5.p sust. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. {atom. 2010 .f32} atom.ftz (and cvt for . stack-based ABI is unimplemented.4 and earlier.PTX ISA Version 2. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented.5 and later. Support for variadic functions and alloca are unimplemented.u32.4 or earlier.f32. if . To maintain compatibility with legacy PTX code. The underlying.

func bar (…) { … L1_head: . … @p bra L1_end.pragma strings defined by ptxas. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.pragma. entry-function. including loops preceding the . Table 145. . Ignored for sm_1x targets. { … } // do not unroll any loop in this function . The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. The “nounroll” pragma is allowed at module. 2010 173 . Descriptions of . L1_body: … L1_continue: bra L1_head.Appendix A. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. Supported only for sm_20 targets.pragma Strings This section describes the .pragma “nounroll”. disables unrolling of0 the loop for which the current block is the loop header.pragma “nounroll”. Note that in order to have the desired effect at statement level. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.0. . L1_end: … } // do not unroll this loop January 24. disables unrolling for all loops in the entry function body. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.pragma “nounroll”.entry foo (…) . and statement levels. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.

2010 .0 174 January 24.PTX ISA Version 2.

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