NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

i

............................. Arrays.................................................................................................. 41 Using Addresses........... Chapter 6.................................................. Types.2.............. 6............ 44 Scalar Conversions ...... 39 5............................. 28 Constant State Space ....... 30 Shared State Space............ and Surface Types .. Operand Costs .............6... 6........2.......... 5.......................................4....... 39 Parameterized Variable Names ........................................................................4...2..............7. Sampler.................3.............5.. 37 Vectors ......................4..........................................1......... 5...... State Spaces ....................... 27 Register State Space ...............1..................... 5..... 49 ii January 24...................................................................... and Vectors .................. 6........................ 32 5.................................................1................... Function declarations and definitions ......................... 46 6..... 41 Destination Operands ...................................................4..............................4...... 5.....1.. 42 Arrays as Operands ....................1...........................1.............................................................................................2........4.....................4.............................................. 5...............1.........................................................................................................4........................................ 44 Rounding Modifiers ..................... State Spaces...................PTX ISA Version 2. 6......................................................... 42 Addresses as Operands ........................................... Operand Type Information .........4............................................ 37 Variable Declarations ......0 4......... 34 Variables ........................ Instruction Operands.............2.............. 6....................1.1.............................. 29 Local State Space ..............3.6....................... 5............................................................... 38 Initializers ..................... 5.......1........................................................2.3................................ 25 Chapter 5.............................................................................. 5....... 2010 ........ 6........ 43 6.................................................................................. 41 6..................................................... 5....4...........................5............... 6................................................................4...............2....1....................................1................... 5.............2............... 6................................................................... 27 5........... 5................................... and Variables ......4..............5................................... 28 Special Register State Space ..........................................2................................5......... Summary of Constant Expression Evaluation Rules .......... 33 5...................4....8.......... 29 Global State Space .....4...........................................................................................3................................................. 33 Fundamental Types ..........1... 37 Array Declarations .....4......... 5.............6............................... 43 Vectors as Operands ...................................................... 5...............................................................................................................................................................................................1............................... Abstracting the ABI ................6.............................3............................. 43 Labels and Function Names as Operands ... 33 Restricted Use of Sub-Word Sizes ............. 47 Chapter 7............1..........5.....1........ 41 Source Operands............................... 6...................................... 5............ 29 Parameter State Space ....................... 38 Alignment .................... 49 7................................ Texture.............................................................................. Type Conversion........ 5.......5........... Types ................. 5.......................... 32 Texture State Space (deprecated) ........

......................................................................................................................................... 168 Chapter 11...............3........ PTX Version and Target Directives ..............................7........................................................................7............ 132 Video Instructions ..................................................................................................................................................................... 8............ 8.................... 8................... 55 8..... 62 Machine-Specific Semantics of 16-bit Code . 8................. 8................... Changes from PTX 1................................ 11.... 52 Variadic functions .... 160 Performance-Tuning Directives ......................9....... 8..7....................................................................6...............................1......5........................ 10........ 166 Linking Directives ......7........................................................3......................................................................................3............ 8................ 62 Semantics .........7.............................................7......................................................7............... 122 Control Flow Instructions .............................0 ....................................... 56 Comparisons .....1.. 7..... Instruction Set ..................................... Chapter 9................................... 104 Data Movement and Conversion Instructions ..................................................... 57 Manipulating Predicates ..............................................................................1..........................................................7... 172 Unimplemented Features Remaining ............... 8......... 10....................3.......................3............................1.....................3.............x ................. Release Notes .............1................................ 7................................2.......10. 8......................... 100 Logic and Shift Instructions ...................................................6.................................. 8....................1................1.. Instructions ............. Special Registers ......4...7.............................................................. 53 Alloca .. 149 Chapter 10............ 129 Parallel Synchronization and Communication Instructions ................................................... 157 10.................................. 170 Semantic Changes and Clarifications ..................................... 63 Integer Arithmetic Instructions ........................................................................ 62 8.....................4......... Directives ............................2.................... 169 11...................................2...... 162 Debugging Directives . 8................... Type Information for Instructions and Operands .......... 63 Floating-Point Instructions ...6....1....7......................... 8...4....1.............................. Format and Semantics of Instruction Descriptions ..... 58 8...................... 59 Operand Size Exceeding Instruction-Type Size .. 60 8......2..7.....................................................5.......................... 55 Predicated Execution ............... 170 New Features ............. 10.............................................1................. Divergence of Threads in Control Constructs ........ 172 January 24... 157 Specifying Kernel Entry Points and Functions ...................... 8..................................................................................... 11..... 11.......... 81 Comparison and Selection Instructions ................................................. 140 Miscellaneous Instructions...................................................1......... 147 8................................... Changes in Version 2.................... 108 Texture and Surface Instructions ...............................8.....................................................6.............. 54 Chapter 8...............4............................. 2010 iii ..........2...............2....... 10.7........................7............................ 8............................3.1............................................. 8.....................1......... 8.............................. 55 PTX Instructions .........................

....... Descriptions of .... 2010 .............................PTX ISA Version 2.........0 Appendix A..pragma Strings.............. 173 iv January 24...

.................................. 46 Cost Estimates for Accessing State-Spaces .................................................. Table 4.......................................................... 46 Integer Rounding Modifiers ....................................................... 47 Operators for Signed Integer. Table 12.......................... Table 5................................... Table 13.............................. Table 14...cc ..............................................List of Tables Table 1.................................. Table 31.......... Table 17..................................................... 27 Properties of State Spaces ................................................................ and Bit-Size Types ..................................................... 66 Integer Arithmetic Instructions: subc ......................................................... 57 Floating-Point Comparison Operators ..........................................................................cc ..... 67 Integer Arithmetic Instructions: mad ........................................................................... Table 25....................................................... 28 Fundamental Type Specifiers ..................... 45 Floating-Point Rounding Modifiers ............................... 57 Floating-Point Comparison Operators Accepting NaN ................. 64 Integer Arithmetic Instructions: add........................ Table 10............................................... Table 2............. Table 21............................. Table 8................................................................................... 69 Integer Arithmetic Instructions: mad24 .......................................................................................... Table 19............................................. 59 Relaxed Type-checking Rules for Source Operands ............ 25 State Spaces ................................................ 65 Integer Arithmetic Instructions: sub...................... Table 6......... 65 Integer Arithmetic Instructions: addc .......................................................................... 35 Opaque Type Fields in Independent Texture Mode ........ Table 26....................... 19 Predefined Identifiers ................ Table 18............ Table 27........ 71 January 24................. 64 Integer Arithmetic Instructions: sub .. 35 Convert Instruction Precision and Format .......... Table 11.......... 60 Relaxed Type-checking Rules for Destination Operands........................................................................ 68 Integer Arithmetic Instructions: mul24 ........................................................... Table 24.............................. 58 Type Checking Rules ......................................... 70 Integer Arithmetic Instructions: sad ................................................... 61 Integer Arithmetic Instructions: add ..... Unsigned Integer............................................ Table 28............................................................................... PTX Directives ............................................................... 2010 v ....................... Table 32................................................................. Table 20...... Table 15.................................................. 18 Reserved Instruction Keywords ........ Table 16............................................ 66 Integer Arithmetic Instructions: mul ........................ Table 22.... Table 23......................... 20 Operator Precedence ...... Table 7.................. Table 29....................................... 58 Floating-Point Comparison Operators Testing for NaN ................. 23 Constant Expression Evaluation Rules ................ Table 30........ 33 Opaque Type Fields in Unified Texture Mode .................................... Table 3... Table 9.....

................. Table 52.......... 92 Floating-Point Instructions: rcp ....0 Table 33......... Table 35........................................................................................................................ 101 Comparison and Selection Instructions: setp ................................................. 83 Floating-Point Instructions: add . Table 41............... 76 Integer Arithmetic Instructions: bfe ............................................................. Table 59............................................ Table 63............................... 103 vi January 24............ Table 55................................ Table 45................ 99 Comparison and Selection Instructions: set .............................................................................................................................................................................. 74 Integer Arithmetic Instructions: bfind ... Table 46.. Table 67...................... 78 Integer Arithmetic Instructions: prmt ............... 96 Floating-Point Instructions: cos .............. 71 Integer Arithmetic Instructions: rem ............... Table 50........... 83 Floating-Point Instructions: copysign ................... Table 58................................................................................................ 90 Floating-Point Instructions: abs .................................................................................................................... 86 Floating-Point Instructions: fma .................................................. Table 48...... Table 39.................. 75 Integer Arithmetic Instructions: brev ....... Table 61. Table 62......................................................................................... 91 Floating-Point Instructions: min ................................................................. 94 Floating-Point Instructions: rsqrt ..... Table 65.................................... 93 Floating-Point Instructions: sqrt ........ 103 Comparison and Selection Instructions: slct .................. Table 44...................................................................................... Table 64............................................................................................................................................................... 79 Summary of Floating-Point Instructions .......................... Table 42...................................................................................................................................................... Table 43................................ Integer Arithmetic Instructions: div ... 2010 ........................................ 88 Floating-Point Instructions: div ..... 95 Floating-Point Instructions: sin ................ 87 Floating-Point Instructions: mad .................................................... Table 60........................... Table 66............................................................... Table 57........... Table 51.. 84 Floating-Point Instructions: sub .............. Table 40. 85 Floating-Point Instructions: mul ............. 71 Integer Arithmetic Instructions: abs ............... Table 56.................................. 92 Floating-Point Instructions: max ......................................... 91 Floating-Point Instructions: neg ............................ Table 38............................. 102 Comparison and Selection Instructions: selp ... 77 Integer Arithmetic Instructions: bfi ............................ Table 54............... 98 Floating-Point Instructions: ex2 ..................... 73 Integer Arithmetic Instructions: popc ............................ 74 Integer Arithmetic Instructions: clz .......................................................... Table 53........................................................................... Table 49....... Table 69.................................................................................... Table 47............. Table 37.................................................. 72 Integer Arithmetic Instructions: neg ................... 97 Floating-Point Instructions: lg2 ......................................................................................PTX ISA Version 2................................... 82 Floating-Point Instructions: testp ........................... Table 34........ Table 68.......................... Table 36............................................................................................................. 72 Integer Arithmetic Instructions: min ............................................. 73 Integer Arithmetic Instructions: max .................

....................................... Table 78....................................................... Table 93...................................................... 113 Data Movement and Conversion Instructions: ldu ................................... 109 Cache Operators for Memory Store Instructions ....... 110 Data Movement and Conversion Instructions: mov ................... 127 Texture and Surface Instructions: suq ........................................ 124 Texture and Surface Instructions: suld ........................................................................................................................... Table 101................................................. Table 96... Table 97. Table 99...... 119 Data Movement and Conversion Instructions: cvta ........ 129 Control Flow Instructions: @ ............................................................... Table 90. Table 94...... Logic and Shift Instructions: and ................... Table 103. 116 Data Movement and Conversion Instructions: prefetch............. vmax ........................ 106 Logic and Shift Instructions: not . Table 100.................................... Table 106. 139 Video Instructions: vadd.......... 129 Control Flow Instructions: bra .. Table 105......... 106 Logic and Shift Instructions: cnot ............. Table 76.................................................. Table 74............................ Table 81..................................................... Table 104............ Table 92................................ Table 73. 130 Control Flow Instructions: ret ... prefetchu ......................... 107 Logic and Shift Instructions: shr ....................... vabsdiff................. 111 Data Movement and Conversion Instructions: mov ................................... 126 Texture and Surface Instructions: sured..................................................... Table 95....................... Table 89........ 112 Data Movement and Conversion Instructions: ld ... 120 Texture and Surface Instructions: tex .. 137 Parallel Synchronization and Communication Instructions: vote ............. Table 83................................. 128 Control Flow Instructions: { } ......................................... 118 Data Movement and Conversion Instructions: isspacep ................. vshr .......... 143 January 24....................Table 70............................................................ Table 88...................... 105 Logic and Shift Instructions: or .................................................. 134 Parallel Synchronization and Communication Instructions: atom ................................. Table 80......... Table 91.................................................................................................................. Table 75.... vsub.......... Table 98. vmin..... 123 Texture and Surface Instructions: txq .......... 125 Texture and Surface Instructions: sust ................. Table 87.................... Table 86................................................... Table 72................. Table 102..................... Table 82......................................... 119 Data Movement and Conversion Instructions: cvt ....... 130 Control Flow Instructions: call ............................... 133 Parallel Synchronization and Communication Instructions: membar ........ 2010 vii ... 142 Video Instructions: vshl......... Table 71......................... 131 Parallel Synchronization and Communication Instructions: bar .... Table 84.......................... Table 79............... 107 Cache Operators for Memory Load Instructions ..................................................................................................... 115 Data Movement and Conversion Instructions: st ............................................................................................................................... 131 Control Flow Instructions: exit ...................................................................... 135 Parallel Synchronization and Communication Instructions: red .................... 105 Logic and Shift Instructions: xor .... 106 Logic and Shift Instructions: shl ........... Table 77.............. Table 85.................................................................................................................................

.......................version............... Table 117.................................... 156 PTX File Directives: .................................................................................................................................................................... 167 Debugging Directives: ..... Table 110.............. 155 Special Registers: %lanemask_gt . 153 Special Registers: %lanemask_eq .............................. 150 Special Registers: %laneid .........0 Table 107............................................... Table 108........................loc ........... Video Instructions: vmad ............................... Table 140....... 165 Debugging Directives: @@DWARF .................................................entry.............. Table 132..... 164 Performance-Tuning Directives: .. Table 127....... 154 Special Registers: %lanemask_le .... 152 Special Registers: %nctaid ...........file ........ 154 Special Registers: %lanemask_ge ................................ 2010 .......................................... 151 Special Registers: %warpid ................................................. 146 Miscellaneous Instructions: trap ................................................................................... 152 Special Registers: %smid ......... Table 120......... 158 Kernel and Function Directives: ...... 166 Debugging Directives: ........................... Table 116.............................................................................................. Table 138........ Table 122.............. Table 119...... 156 Special Registers: %clock64 .. Table 133............ Table 128............................................................ Table 126................func .... Table 137............... Table 136............................................................................................... 153 Special Registers: %gridid ..maxntid ................ Table 130............................................................extern................................ %pm2.............................. Table 113........................... Table 141............................... Table 129...................................................... 163 Performance-Tuning Directives: . 150 Special Registers: %ntid . Table 125................................... 160 Kernel and Function Directives: ............................... 161 Performance-Tuning Directives: ............ Table 115..................................... Table 142................................................................................................... %pm3 . Table 139..... Table 135... 144 Video Instructions: vset...........................maxnctapersm (deprecated) ................. 147 Miscellaneous Instructions: pmevent......................................................................... Table 114................................. 164 Performance-Tuning Directives: .............. Table 118...................................................................................... 168 viii January 24.........................pragma .. Table 131............................... 155 Special Registers: %clock .. Table 134.......................... 156 Special Registers: %pm0............ Table 123................................................................................................. Table 109........................................................................ 157 PTX File Directives: ... Table 121.............................................................................................................................maxnreg ................ Table 111. %pm1...................................................................... 167 Linking Directives: ................................................................................................................. Table 124.........section ................... 147 Miscellaneous Instructions: brkpt ....... 151 Special Registers: %nwarpid ............ Table 143.............................. 154 Special Registers: %lanemask_lt ..PTX ISA Version 2......................... Table 112................target ............................ 151 Special Registers: %ctaid ...............................minnctapersm ..................... 147 Special Registers: %tid .................................... 163 Performance-Tuning Directives: ......................... 153 Special Registers: %nsmid ... 167 Debugging Directives: ......................................................

......... 173 January 24....... 2010 ix .....visible.....................................Table 144......................... 168 Pragma Strings: “nounroll” ........................................................................... Table 145. Linking Directives: ............

2010 .PTX ISA Version 2.0 x January 24.

Similarly. Introduction This document describes PTX. and pattern recognition can map image blocks and pixels to parallel processing threads. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. In fact. the programmable GPU has evolved into a highly parallel. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. multithreaded. January 24. Because the same program is executed for each data element.2. the memory access latency can be hidden with calculations instead of big data caches. there is a lower requirement for sophisticated flow control. many-core processor with tremendous computational horsepower and very high memory bandwidth. 2010 1 .Chapter 1. stereo vision. high-definition 3D graphics.1. 1. PTX exposes the GPU as a data-parallel computing device. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. which are optimized for and translated to native target-architecture instructions. PTX programs are translated at install time to the target hardware instruction set. 1. and because it is executed on many data elements and has high arithmetic intensity. image scaling. image and media processing applications such as post-processing of rendered images. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. from general signal processing or physics simulation to computational finance or computational biology. PTX defines a virtual machine and ISA for general purpose parallel thread execution. video encoding and decoding. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Data-parallel processing maps data elements to parallel processing threads. Many applications that process large data sets can use a data-parallel programming model to speed up the computations.

extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.ftz and . 1.1. • • • 2 January 24. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.PTX ISA Version 2.sat modifiers.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Improved Floating-Point Support A main area of change in PTX 2.f32 require a rounding modifier for sm_20 targets.0 are improved support for IEEE 754 floating-point operations.f32 instruction also supports . sub.0 is a superset of PTX 1.ftz) modifier may be used to enforce backward compatibility with sm_1x. 1. which map PTX to specific target machines. fma. and the introduction of many new instructions. 2010 . Both fma. and all PTX 1. Provide a machine-independent ISA for C/C++ and other compilers to target.0 PTX ISA Version 2. Facilitate hand-coding of libraries.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. PTX 2.rp rounding modifiers for sm_20 targets. The main areas of change in PTX 2. Single-precision add. addition of generic addressing to facilitate the use of general-purpose pointers.f32 requires sm_20. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. and video instructions. When code compiled for sm_1x is executed on sm_20 devices. The mad.rn.x code will continue to run on sm_1x targets as well.x features are supported on the new sm_20 target.3.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.f32 maps to fma. barrier. Instructions marked with . Most of the new features require a sm_20 target. A “flush-to-zero” (.f32.3. Provide a code distribution ISA for application and middleware developers.rm and . mad.0 is in improved support for the IEEE 754 floating-point standard. atomic.f32 for sm_20 targets.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. and architecture tests. including integer. surface.f32 and mad.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.x. and mul now support . performance kernels. Provide a common source-level ISA for optimizing code generators and translators. The fma. The changes from PTX ISA 1. A single-precision fused multiply-add (fma) instruction has been added. Legacy PTX 1. Achieve performance in compiled applications comparable to native GPU performance. reduction. The mad. memory. PTX ISA Version 2.

and shared state spaces.e. prefetch. and directives are introduced in PTX 2. these changes bring PTX 2.. and shared addresses to generic address and vice-versa has been added. PTX 2. 1.3. A new cvta instruction has been added to convert global. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. i. 1. local.3.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.zero. and vice versa. instructions ld. an address that is the same across all threads in a warp. Generic Addressing Another major change is the addition of generic addressing. for prefetching to specified level of memory hierarchy. January 24. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. . and sust. Generic addressing unifies the global. suld. • Taken as a whole. atom.3. Introduction • Single. rcp. local. allowing memory instructions to access these spaces without needing to specify the state space. prefetchu.2. 1. cvta. st. Instructions prefetch and prefetchu have been added. e. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Instruction cvta for converting global. stack-based ABI. isspacep.clamp and . and Application Binary Interface (ABI). ldu. Surface Instructions • • Instruction sust now supports formatted surface stores.4. Cache operations have been added to instructions ld. and shared addresses to generic addresses. and sqrt with IEEE 754 compliant rounding have been added.0. In PTX 2. Support for an Application Binary Interface Rather than expose details of a particular calling convention.and double-precision div.g. and red now support generic addressing.Chapter 1. st. Instructions testp and copysign have been added. Surface instructions support additional clamp modifiers. New Instructions The following new instructions. These are indicated by the use of a rounding modifier and require sm_20.0. NOTE: The current version of PTX does not implement the underlying.3.0 closer to full compliance with the IEEE 754 standard. so recursion is not yet supported. local. special registers. 2010 3 . stack layout.

red.lt.ballot. New special registers %nsmid. 2010 . .red}.f32 have been added. and Vote Instructions • • • New atomic and reduction instructions {atom.b32. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. %lanemask_{eq.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe. Other Extensions • • • Video instructions (includes prmt) have been added.or}.arrive instruction has been added. bar now supports an optional thread count and register operands. 4 January 24. has been added.popc. A bar.shared have been extended to handle 64-bit data types for sm_20 targets.le. Barrier Instructions • • A system-level membar instruction. Instructions bar.PTX ISA Version 2. Instructions {atom. bfi bit field extract and insert popc clz Atomic. A new directive. Reduction.section.u32 and bar. %clock64.{and.sys. A “vote ballot” instruction.red}. membar.ge.gt} have been added.pred have been added.red. vote. has been added.add.

Chapter 9 lists special registers. types. Introduction 1. January 24. Chapter 6 describes instruction operands. Chapter 3 gives an overview of the PTX virtual machine model.Chapter 1. Chapter 10 lists the assembly directives supported in PTX. Chapter 4 describes the basic syntax of the PTX language. Chapter 5 describes state spaces. 2010 5 . and variable declarations.4. and PTX support for abstracting the Application Binary Interface (ABI). Chapter 11 provides release notes for PTX Version 2. calling convention.0. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 7 describes the function and call syntax. Chapter 8 describes the instruction set.

2010 .PTX ISA Version 2.0 6 January 24.

Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array.z) that specifies the thread’s position within a 1D. but independently on different data. and ntid. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.2. 2D. or 3D CTA.x. To coordinate the communication of the threads within the CTA. It operates as a coprocessor to the main CPU.1. and tid. can be isolated into a kernel function that is executed on the GPU as many different threads. Each CTA has a 1D. The thread identifier is a three-element vector tid. 2. Cooperative thread arrays (CTAs) implement CUDA thread blocks. A cooperative thread array. compute-intensive portions of applications running on the host are off-loaded onto the device. Programming Model 2. or host: In other words. The vector ntid specifies the number of threads in each CTA dimension. and results across the threads of the CTA. To that effect. ntid.y.Chapter 2. work.2. or CTA. is an array of threads that execute a kernel concurrently or in parallel. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. data-parallel. 2010 7 . compute addresses. and select work to perform. Threads within a CTA can communicate with each other. (with elements tid. Each CTA thread uses its thread identifier to determine its assigned role. 2. January 24. tid. or 3D shape specified by a three-element vector ntid (with elements ntid.x.1. Each thread has a unique thread identifier within the CTA.y. More precisely. 2D.z). Programs use a data parallel decomposition to partition inputs. a portion of an application that is executed many times. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. assign specific input and output positions. one can specify synchronization points where threads wait until all threads in the CTA have arrived.

This comes at the expense of reduced thread communication and synchronization. The warp size is a machine-dependent constant. which may be used in any instruction where an immediate operand is allowed. %nctaid. Typically.2. such that the threads execute the same instructions at the same time. multiple-thread) fashion in groups called warps.PTX ISA Version 2. Threads within a warp are sequentially numbered. The host issues a succession of kernel invocations to the device. depending on the platform. Multiple CTAs may execute concurrently and in parallel.2. Threads may read and use these values through predefined. a warp has 32 threads. However. %ntid. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. 2D . %ctaid. CTAs that execute the same kernel can be batched together into a grid of CTAs.0 Threads within a CTA execute in SIMT (single-instruction. 8 January 24. Some applications may be able to maximize performance with knowledge of the warp size. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). so that the total number of threads that can be launched in a single kernel invocation is very large. 2010 . WARP_SZ. or sequentially. because threads in different CTAs cannot communicate and synchronize with each other. A warp is a maximal subset of threads from a single CTA. Each grid of CTAs has a 1D. Each grid also has a unique temporal grid identifier (gridid). read-only special registers %tid. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. and %gridid. 2. so PTX includes a run-time immediate constant. or 3D shape specified by the parameter nctaid.

1) Thread (3. 0) CTA (0. 0) Thread (3. 2010 9 . 1) Thread (1. 1) Thread (0. 0) Thread (4. Figure 1.Chapter 2. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (2. A grid is a set of CTAs that execute independently. 1) CTA (1. 0) CTA (1. 1) Thread (4. 2) Thread (3. 1) Thread (2. 0) Thread (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2) Thread (1. 2) Thread (2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (1. 1) Thread (0. 1) CTA (2. 2) Thread (4. Thread Batching January 24. 0) CTA (2.

2010 . and texture memory spaces are persistent across kernel launches by the same application.PTX ISA Version 2. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. as well as data filtering. and texture memory spaces are optimized for different memory usages. Each thread has a private local memory. referred to as host memory and device memory. The global. for some specific data formats.3. all threads have access to the same global memory. constant. for more efficient transfer. The global. constant. Both the host and the device maintain their own local memory. Finally. respectively. Texture memory also offers different addressing modes. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. or. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. The device memory may be mapped and read or written by the host. 10 January 24. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2.0 2.

0) Block (0. 1) Block (1.Chapter 2. 1) Block (2. 0) Block (1. 2) Figure 2. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (0. 2) Block (1. Memory Hierarchy January 24. 1) Grid 1 Global memory Block (0. 0) Block (2. 1) Block (0. 2010 11 . 0) Block (1. 1) Block (1.

2010 .PTX ISA Version 2.0 12 January 24.

each warp contains threads of consecutive. January 24. If threads of a warp diverge via a data-dependent conditional branch. A multiprocessor consists of multiple Scalar Processor (SP) cores. the first parallel thread technology. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. When a multiprocessor is given one or more thread blocks to execute. 2010 13 . a voxel in a volume. and on-chip shared memory.1. and executes threads in groups of parallel threads called warps. The multiprocessor maps each thread to one scalar processor core. The way a block is split into warps is always the same. and executes concurrent threads in hardware with zero scheduling overhead. for example. disabling threads that are not on that path. a cell in a grid-based computation). As thread blocks terminate. the multiprocessor employs a new architecture we call SIMT (single-instruction. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). the threads converge back to the same execution path. Parallel Thread Execution Machine Model 3. It implements a single-instruction barrier synchronization. allowing. and when all paths complete. Branch divergence occurs only within a warp. schedules. new blocks are launched on the vacated multiprocessors. The multiprocessor creates. The multiprocessor SIMT unit creates.Chapter 3. The threads of a thread block execute concurrently on one multiprocessor. A warp executes one common instruction at a time. At every instruction issue time.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. and each scalar thread executes independently with its own instruction address and register state. (This term originates from weaving. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. a multithreaded instruction unit. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. so full efficiency is realized when all threads of a warp agree on their execution path. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. manages. multiple-thread). the warp serially executes each branch path taken. To manage hundreds of threads running several different programs. When a host program invokes a kernel grid. increasing thread IDs with the first warp containing thread 0. manages. it splits them into warps that get scheduled by the SIMT unit. different warps execute independently regardless of whether they are executing common or disjointed code paths.

however. whereas SIMT instructions specify the execution and branching behavior of a single thread. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. and writes to the same location in global memory for more than one of the threads of the warp. If there are not enough registers or shared memory available per multiprocessor to process at least one block. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. In practice. SIMT enables programmers to write thread-level parallel code for independent. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. Vector architectures. but the order in which they occur is undefined. 2010 . which is a read-only region of device memory. A key difference is that SIMD vector organizations expose the SIMD width to the software. modify. If an atomic instruction executed by a warp reads. As illustrated by Figure 3. modifies. the programmer can essentially ignore the SIMT behavior.0 SIMT architecture is akin to SIMD (Single Instruction. In contrast with SIMD vector machines. write to that location occurs and they are all serialized. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. but one of the writes is guaranteed to succeed. For the purposes of correctness. on the other hand. the number of serialized writes that occur to that location and the order in which they occur is undefined. as well as data-parallel code for coordinated threads. require the software to coalesce loads into vectors and manage divergence manually. 14 January 24. each read. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. the kernel will fail to launch. • The local and global memory spaces are read-write regions of device memory and are not cached. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space.PTX ISA Version 2. A multiprocessor can execute as many as eight thread blocks concurrently. which is a read-only region of device memory. scalar threads.

2010 15 . Hardware Model January 24. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.Chapter 3. Figure 3.

2010 .0 16 January 24.PTX ISA Version 2.

Each PTX file must begin with a . #line. Comments in PTX are treated as whitespace. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. and using // to begin a comment that extends to the end of the current line. The C preprocessor cpp may be used to process PTX source files. Lines are separated by the newline character (‘\n’). 4. #endif. Source Format Source files are ASCII text. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. #if.target directive specifying the target architecture assumed. All whitespace characters are equivalent. 4.1. January 24. 2010 17 . using non-nested /* and */ for comments that may span multiple lines. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Syntax PTX programs are a collection of text source files.2. followed by a . See Section 9 for a more information on these directives. Pseudo-operations specify symbol and addressing management.Chapter 4. whitespace is ignored except for its use in separating tokens in the language. #ifdef.version directive specifying the PTX language version. The following are common preprocessor directives: #include. Lines beginning with # are preprocessor directives. Comments Comments in PTX follow C/C++ syntax. PTX is case sensitive and uses lowercase for keywords. #else. #define.

loc . Directive Statements Directive keywords begin with a dot. r1. The guard predicate follows the optional label and precedes the opcode.local .3. constant expressions.global . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.f32 r2. .PTX ISA Version 2. 18 January 24.f32 array[N].0 4. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10.version . ld.x.section . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. r2.reg .param .3. written as @!p. mov.reg .visible 4. All instruction keywords are reserved tokens in PTX.minnctapersm . Instructions have an optional guard predicate which controls conditional execution. and terminated with a semicolon.5. followed by source operands. .maxntid . The destination operand is first. Operands may be register variables. Examples: . 2.sreg . so no conflict is possible with user-defined identifiers. shl.b32 r1. array[r1].shared . Statements begin with an optional label and end with a semicolon. %tid. Table 1.align .target .b32 r1. r2. address expressions. Statements A PTX statement is either a directive or an instruction.3.func .b32 add. The guard predicate may be optionally negated.file PTX Directives . 0.global.maxnctapersm .1. and is written as @p.tex . r2.extern .const .2.pragma .entry . or label names.global start: . Instruction keywords are listed in Table 2. 2010 .maxnreg .b32 r1. where p is a predicate register.

Syntax Table 2. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .Chapter 4.

PTX predefines one constant and a small number of special registers that begin with the percentage sign. The percentage sign can be used to avoid name conflicts. 2010 .PTX ISA Version 2. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. …. e. Table 3. except that the percentage sign is not allowed. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. dollar. or percentage character followed by one or more letters. or they start with an underscore. underscore. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. between user-defined variable names and compiler-generated names. %pm3 WARP_SZ 20 January 24. Many high-level languages such as C and C++ follow similar rules for identifier names.4. underscore. digits. digits.g. or dollar characters.0 4. listed in Table 3. PTX allows the percentage sign as the first character of an identifier.

1. where the behavior of the operation depends on the operand types. Floating-point literals may be written with an optional decimal point and an optional signed exponent. The syntax follows that of C. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.Chapter 4.u64). Unlike C and C++. the constant begins with 0d or 0D followed by 16 hex digits. octal. To specify IEEE 754 single-precision floating point values. 4.s64 or . Integer literals may be written in decimal. When used in an instruction or data initialization. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. in which case the literal is unsigned (. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. floating-point.. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. To specify IEEE 754 doubleprecision floating point values. These constants may be used in data initialization and as operands to instructions. 2010 21 .u64.5. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Constants PTX supports integer and floating-point constants and constant expressions. every integer constant has type . zero values are FALSE and non-zero values are TRUE. 4.5. 0[fF]{hexdigit}{8} // single-precision floating point January 24.2. or binary notation.s64 or the unsigned suffix is specified. Syntax 4. the constant begins with 0f or 0F followed by 8 hex digits. For predicate-type data and instructions. and bit-size types.s64) unless the value cannot be fully represented in . and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. integer constants are allowed and are interpreted as in C.5. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values. i. hexadecimal. Type checking rules remain the same for integer.. i. each integer constant is converted to the appropriate size based on the data or instruction type at its use.e.e. there is no suffix letter to specify size. literals are always represented in 64-bit double-precision format.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

January 24, 2010

Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

• • •

January 24, 2010

23

PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

24

January 24, 2010

s64 . .s64 .s64 .s64 . Syntax 4.5.u64 .f64 integer integer integer integer integer int ?.s64 .u64 .s64.f64 converted type .6.s64 .f64 use usual conversions .s64) + . 2nd is .s64 .u64.Chapter 4.f64 same as source .u64 .u64 zero or non-zero same as sources use usual conversions Result Type same as source .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24. Table 5.u64) (. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .f64 converted type constant literal + ! ~ Cast Binary (. 2010 25 .f64 use usual conversions .u64 .u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .u64 1st unchanged.f64 : .u64 . or . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 integer .f64 use usual conversions .f64 integer .s64 .u64 same as 1st operand .

2010 .PTX ISA Version 2.0 26 January 24.

Name State Spaces Description Registers. Read-only. Kernel parameters. addressability. State Spaces.sreg . shared by all threads.Chapter 5. Global texture memory (deprecated).1.global . the kinds of resources will be common across platforms. Shared.local . read-only memory. and level of sharing between threads. The list of state spaces is shown in Table 4. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. Addressable memory shared between threads in 1 CTA. and properties of state spaces are shown in Table 5. Global memory. access speed.tex January 24. and Variables While the specific resources available in a given target GPU will vary. access rights. pre-defined. defined per-grid. 5. platform-specific.param . fast.const . Local memory. . Special registers. Types. Table 6. The characteristics of a state space include its size. and these resources are abstracted in PTX through state spaces and data types. private to each thread.reg . defined per-thread.shared . 2010 27 . State Spaces A state space is a storage area with particular characteristics. or Function or local parameters. All variables reside in some state space.

1.local . 3 Accessible only via the tex instruction. Registers differ from the other state spaces in that they are not fully addressable. The most common use of 8-bit registers is with ld.param (as input to kernel) . 16-.param instruction. causing changes in performance. Registers may have alignment boundaries required by multi-word loads and stores. 28 January 24. Register size is restricted.reg . or 128-bits. the parameter is then located on the stack frame and its address is in the . and thread parameters. and will vary from platform to platform. it is not possible to refer to the address of a register. predicate) or untyped. 32-. and vector registers have a width of 16-. Address may be taken via mov instruction. 64-. such as grid. 5.tex Restricted Yes No3 5. All special registers are predefined. Registers may be typed (signed integer.sreg) state space holds predefined.2. aside from predicate registers which are 1-bit. or 64-bits. When the limit is exceeded. Special Register State Space The special register (. Register State Space Registers (..global .PTX ISA Version 2. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . and cvt instructions. and performance monitoring registers.0 Table 7. platform-specific registers. 32-. clock counters.reg state space) are fast storage locations. i. CTA.param (used in functions) .param instructions.e. 1 Accessible only via the ld. floating point.1.param and st. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes.shared . unsigned integer. register variables will be spilled to memory. 2010 . Device function input parameters may have their address taken via mov.1. For each architecture. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).const .sreg . 2 Accessible via ld.local state space. or as elements of vector tuples. The number of registers is limited. scalar registers have a width of 8-. st.

b32 const_buffer[]. The remaining banks may be used to implement “incomplete” constant arrays (in C.1. Local State Space The local state space (. To access data in contant banks 1 through 10. an incomplete array in bank 2 is accessed as follows: . ld.global.local and st. Use ld. bank zero is used. For example.extern . the declaration . where bank ranges from 0 to 10.4.1. b = b – 1.sync instruction are guaranteed to be visible to any reads after the barrier instruction. This pointer can then be used to access the entire 64KB constant bank. 2010 29 . Global memory is not sequentially consistent. It is the mechanism by which different CTAs and different grids can communicate. where the size is not known at compile time. bank zero is used for all statically-sized constant variables. All memory writes prior to the bar. whereas local memory variables declared January 24.global to access global variables. The size is limited. there are eleven 64KB banks. The constant memory is organized into fixed size banks. It is typically standard memory with cache. the stack is in local memory.const[2] .const[2]. For any thread in a context. Module-scoped local memory variables are stored at fixed addresses.1.Chapter 5.const) state space is a read-only memory. Consider the case where one thread executes the following two assignments: a = a + 1.local to access local variables. By convention. for example). [const_buffer+4]. Multiple incomplete array variables declared in the same bank become aliases. and atom. If no bank number is given.b32 %r1. // load second word 5.global) state space is memory that is accessible by all threads in a context. as it must be allocated on a perthread basis.extern .const[bank] modifier.b32 const_buffer[]. results in const_buffer pointing to the start of constant bank two. Types. Constant State Space The constant (. the store operation updating a may still be in flight. Sequential consistency is provided by the bar. If another thread sees the variable b change. State Spaces. Use ld.3. as in lock-free and wait-free style programming. In implementations that support a stack. Threads wait at the barrier until all threads in the CTA have arrived. Threads must be able to do their work without waiting for other threads to do theirs. and Variables 5. 5. all addresses are in global memory are shared. Banks are specified using the . Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.sync instruction. the bank number must be provided in the state space of the load instruction. initialized by the host. each pointing to the start address of the specified constant bank. For example.local) is private memory for each thread to keep its own data. For the current devices.const[2] . This reiterates the kind of parallelism available in machines that run PTX. Global State Space The global (. st.global.5.

param state space.0 and requires target architecture sm_20. read-only variables declared in the .x supports only kernel function parameters in .param instructions. These parameters are addressable. For example.PTX ISA Version 2.param space variables. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. len.entry foo ( . … Example: . The address of a kernel parameter may be moved into a register using the mov instruction.u32 %ptr.b32 N. typically for passing large structures by value to a function.1. 5. The kernel parameter variables are shared across all CTAs within a grid. (2a) to declare formal input and return parameters for device functions called from within kernel execution.0 within a function or kernel body are allocated on the stack.u32 %n.param instructions. ld. The use of parameter state space for device function parameters is new to PTX ISA version 2. Therefore.b8 buffer[64] ) { .param. .6.u32 %n. per-kernel versus per-thread).6.f64 %d.param . [%ptr].param . . [buffer]. Values passed from the host to the kernel are accessed through these parameter variables using ld. PTX code should make no assumptions about the relative locations or ordering of .reg . [N].reg .u32 %ptr. %n. in some implementations kernel parameters reside in global memory.b32 len ) { . all local memory variables are stored at fixed addresses and recursive function calls are not supported. … 30 January 24.param space. ld. mov. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Note that PTX ISA versions 1.reg .param state space and is accessed using ld.param.1.param. No access protection is provided between parameter and global space in this case.align 8 . Similarly.entry bar ( . In implementations that do not support a stack. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. 5.1. Parameter State Space The parameter (. The resulting address is in the .param . device function parameters were previously restricted to the register state space. Note: The location of parameter space is implementation specific. 2010 . and (2b) to declare locally-scoped byte array variables that serve as function call arguments. ld.f64 %d.u32 %n. Example: .param) state space is used (1) to pass input arguments from the host to the kernel.

reg .f64 %d. It is not possible to use mov to get the address of a return parameter or a locally-scoped . Types. (4. and Variables 5. x.local and st. In this case. Aside from passing structures by value.func foo ( . ld. This will be passed by value to a callee.s32 x.b8 mystruct.param .param.param and function return parameters may be written using st. call foo.2.param space is also required whenever a formal parameter has its address taken within the called function.param. }.param byte array variable that represents a flattened C structure or union.param formal parameter having the same size and alignment as the passed argument. which declares a .align 8 . the caller will declare a locally-scoped . … See the section on function call syntax for more details. … } // code snippet from the caller // struct { double d. In PTX.param.0 extends the use of parameter space to device function parameters.align 8 .local instructions. State Spaces. mystruct). Device Function Parameters PTX ISA version 2. .s32 %y. st. int y.param. 2010 31 . . dbl.param space variable. the address of a function input parameter may be moved into a register using the mov instruction. is flattened. The most common use is for passing objects by value that do not fit within a PTX register.reg .f64 %d. Note that the parameter will be copied to the stack if necessary.f64 [mystruct+0].s32 %y. int y. ld.param . passed to foo … . [buffer+8]. . [buffer]. such as C structures larger than 8 bytes. a byte array in parameter space is used.reg .6.reg .f64 dbl.b32 N. . .reg . . … st.b8 buffer[12] ) { .local state space and is accessed via ld. January 24. Function input parameters may be read via ld. and so the address will be in the .Chapter 5.1. Example: // pass object of type struct { double d. } mystruct.s32 [mystruct+8].param. Typically. it is illegal to write to an input parameter or read from a return parameter.

Multiple names may be bound to the same physical texture identifier.texref tex_a.shared to access shared variables. is equivalent to .tex) state space is global memory accessed via the texture instruction. tex_f. tex_c. The texture name must be of type . where all threads read from the same address.global state space. Texture State Space (deprecated) The texture (. Texture memory is read-only.global . It is shared by all threads in a context. and . Shared memory typically has some optimizations to support the sharing. The .tex . Another is sequential access from sequential threads.u32 tex_a. A texture’s base address is assumed to be aligned to a 16-byte boundary.3 for the description of the . One example is broadcast. An error is generated if the maximum number of physical resources is exceeded.6 for its use in texture instructions.tex state space are equivalent to module-scoped .tex .1.u32 . For example. The .tex variables are required to be defined in the global scope.u32 tex_a.0 5. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). Use ld. Physical texture resources are allocated on a per-module granularity.texref. Shared State Space The shared (.7. An address in shared memory can be read and written by any thread in a CTA. and programs should instead reference texture memory through variables of type . tex_d.1.tex directive will bind the named texture memory variable to a hardware texture identifier.u32 .tex . a legacy PTX definitions such as .tex . See Section 5.tex . 5.u32 .tex directive is retained for backward compatibility.texref variables in the .PTX ISA Version 2. 32 January 24.7. tex_d. Example: . 2010 . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.shared) state space is a per-CTA region of memory for threads in a CTA to share data.shared and st. and variables declared in the . where texture identifiers are allocated sequentially beginning with zero.u32 or .texref type and Section 8.u64.8.

f64 . and .u8. Register variables are always of a fundamental type.b32. Types 5.s8. Fundamental Types In PTX.u8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. 5. The same typesize specifiers are used for both variable definitions and for typing instructions. needed to fully specify instruction behavior.b8. 2010 33 . . and instructions operate on these types. st. . For example.u32. so that narrow values may be loaded. . Types. ld. The following table lists the fundamental type specifiers for each basic type: Table 8. the fundamental types reflect the native data types supported by the target architectures. State Spaces. .u64 . and Variables 5.f64 types.2. st.2.s16.Chapter 5.u16. For convenience. January 24. The bitsize type is compatible with any fundamental type having the same size.f16 floating-point type is allowed only in conversions to and from . and cvt instructions permit source and destination data operands to be wider than the instruction-type size.2. In principle.pred Most instructions have one or more type specifiers. or converted to other types and sizes.b16. . . .b64 . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . .f32 and . so their names are intentionally short. Restricted Use of Sub-Word Sizes The . . stored.f64 types. Two fundamental types are compatible if they have the same basic type and are the same size. . . Signed and unsigned integer types are compatible if they have the same size.f32 and .s64 . The .s32.b8 instruction types are restricted to ld. all variables (aside from predicates) could be declared using only bit-size types.f16.f32. A fundamental type specifies both a basic type and a size. All floating-point instructions operate only on . but typed variables enhance program readability and allow for better operand type checking. and converted using regular-width registers.s8. . and cvt instructions. Operand types and sizes are checked against instruction types for compatibility. stored.2.1.

{u32. Sampler. store.PTX ISA Version 2. but the pointer cannot otherwise be treated as an address. opaque_var. sampler.texref handle. 2010 .texref type that describe sampler properties are ignored.u64} reg. base address. For working with textures and samplers. Referencing textures.surfref.e. texture and sampler information each have their own handle.3. hence the term “opaque”. suq). and overall size is hidden to a PTX program.. allowing them to be defined separately and combined at the site of usage in the program. and Surface Types PTX includes built-in “opaque” types for defining texture. and query instructions. samplers. The three built-in types are . sust. PTX has two modes of operation. and . The following tables list the named members of each type for unified and independent texture modes.texref. sured). accessing the pointer with ld and st instructions. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists.samplerref. texture and sampler information is accessed through a single . Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. or surfaces via texture and surface load/store instructions (tex. In the independent mode. Creating pointers to opaque variables using mov. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. the resulting pointer may be stored to and loaded from memory. and de-referenced by texture and surface load. Texture. These types have named fields similar to structures. field ordering. and surface descriptor variables. . passed as a parameter to functions. 34 January 24. In the unified mode. but all information about layout. i.0 5. since these properties are defined by . Retrieving the value of a named member via query instructions (txq.samplerref variables. or performing pointer arithmetic will result in undefined results. suld. In independent mode the fields of the .

mirror.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_to_border N/A N/A N/A N/A N/A . clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode . 2010 35 . clamp_to_edge.texref values in elements in elements in elements 0.Chapter 5. linear wrap. clamp_to_border 0. clamp_to_edge. Types.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. 1 ignored ignored ignored ignored . linear wrap. State Spaces. clamp_ogl. mirror. and Variables Table 9. Member width height depth Opaque Type Fields in Unified Texture Mode .texref values .samplerref values N/A N/A N/A N/A nearest. 1 nearest.

samplerref my_sampler_name.global . As kernel parameters.global . Example: .global .PTX ISA Version 2. the types may be initialized using a list of static expressions assigning values to the named members. . filter_mode = nearest }. When declared at module scope. . these variables are declared in the . these variables must be in the . Example: .global state space.surfref my_surface_name.texref my_texture_name.texref tex1.global . 2010 .global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. At module scope. 36 January 24.param state space. .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.

0.struct float4 { . 5. // a length-4 vector of floats . 5. State Spaces. Every variable must reside in one of the state spaces enumerated in the previous section.reg .v1. . r.global .struct float4 coord.v4 vector.b8 v. and an optional fixed address for the variable.v4. A variable declaration names the space in which the variable resides.0. Vectors Limited-length vector types are supported. // typedef . and Variables 5. its name. Vectors must be based on a fundamental type.reg . Vectors cannot exceed 128-bits in length. an optional initializer.f32 v0. // a length-4 vector of bytes By default. January 24. to enable vector load and store instructions which require addresses aligned to a multiple of the access size. Predicate variables may only be declared in the register state space.v3 }.u32 loc.4. where the fourth element provides padding. // a length-2 vector of unsigned ints .0}. vector variables are aligned to a multiple of their overall size (vector length times base-type size).2. its type and size. 0. Types. an optional array size.reg .v4 . and they may reside in the register space. . Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . . . etc.v2 . In addition to fundamental types.u16 uv.global . 1.4.f64 is not allowed.v4 .f32 accel.v2 or . q.shared .f32 V. .f32 bias[] = {-1. a variable declaration describes both the variable’s type and its state space.global . This is a common case for three-dimensional grids. .u8 bg[4] = {0. 0}. . for example.pred p. Examples: .v4.v2.Chapter 5.1.global . textures.4. Variables In PTX.const .s32 i. Examples: .v4 . Three-element vectors may be handled by using a .global . Variable Declarations All storage for data is specified with variable declarations. PTX supports types for simple aggregate objects such as vectors and arrays. 2010 37 .

global .shared . 19*19 (361) halfwords are reserved (722 bytes).1}. this can be used to statically initialize a pointer to a variable. Array Declarations Array declarations are provided to allow the programmer to reserve space. . The size of the dimension is either a constant expression. The size of the array specifies how many elements should be reserved..b32 ptr = rgba.s32 offset[][] = { {-1.0}. {0.f16 and . . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.05.pred.0 5.05}. 0}. 38 January 24. or is left empty. {0.4. -1}. 0}.global .u8 mailbox[128].u8 rgba[3] = {{1.0}.4. Variables that hold addresses of variables or instructions should be of type . To declare an array.3.u16 kernel[19][19]. . For the kernel declaration above.. being determined by an array initializer. 1} }.u64. 5.local . variable initialization is supported only for constant and global state spaces. 2010 .global .4.05.. Initializers Declared variables may specify an initial value using a syntax similar to C/C++..0.1. Examples: . label names appearing in initializers represent the address of the next instruction following the label.f32 blur_kernel[][] = {{. Variable names appearing in initializers represent the address of the variable.global . Initializers are allowed for all types except .PTX ISA Version 2. {1. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). this can be used to initialize a jump table to be used with indirect branches or calls. {0.0. Here are some examples: .global . Similarly.u32 or .s32 n = 10.0}}.{.0.05}}. {0. // address of rgba into ptr Currently..1.1. . A scalar takes a single value.4.1..v4 .0.1. where the variable name is followed by an equals sign and the initial value or values for the variable. .{.

const . January 24. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. State Spaces.5.align byte-count specifier immediately following the state-space specifier. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. These 100 register variables can be declared as follows: . Types. Rather than require explicit declaration of every name. . suppose a program uses a large number. Alignment is specified using an optional . say one hundred.. %r1.6. The default alignment for scalar and array variables is to a multiple of the base-type size. not for individual elements..0.0.b8 bar[8] = {0. 5. and may be preceded by an alignment specifier.Chapter 5.b32 variables. For arrays.0.0}. . …. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. nor are initializers permitted. For example.0.4. // declare %r0. %r99. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. 2010 39 . Array variables cannot be declared this way. named %r0. it is quite common for a compiler frontend to generate a large number of register names.. Parameterized Variable Names Since PTX supports virtual registers. The default alignment for vector variables is to a multiple of the overall vector size.align 4 . alignment specifies the address alignment for the starting address of the entire array.2.reg . of .0.4. The variable will be aligned to an address which is an integer multiple of byte-count.b32 %r<100>. Elements are bytes. %r1. and Variables 5. Examples: // allocate array at 4-byte aligned address.

0 40 January 24.PTX ISA Version 2. 2010 .

Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Integer types of a common size are compatible with each other. and c. as its job is to convert from nearly any data type to any other data type (and size). Most instructions have an optional predicate guard that controls conditional execution. 2010 41 . The cvt (convert) instruction takes a variety of operand types and sizes. 6. The bit-size type is compatible with every type having the same size. PTX describes a load-store machine. Instruction Operands 6. and a few instructions have additional predicate source operands. Predicate operands are denoted by the names p.Chapter 6. so operands for ALU instructions must all be in variables declared in the . January 24. r. Instructions ld and st move data from/to addressable state spaces to/from registers. 6.1. s. The result operand is a scalar or vector variable in the register state space. Operand Type Information All operands in instructions have a known type from their declarations. Each operand type must be compatible with the type determined by the instruction template and instruction type. st. . The mov instruction copies data between registers. The ld. the sizes of the operands must be consistent. For most operations. Source Operands The source operands are denoted in the instruction descriptions by the names a. and cvt instructions copy data from one location to another. b. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. There is no automatic conversion between types. q. mov.3.reg register state space.2.

arrays. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.reg .gloal.global . there is no support for C-style pointer arithmetic.s32 mov. The syntax is similar to that used in many assembly languages. and vectors. Address expressions include variable names. address register plus byte offset.reg .4. .const . and Vectors Using scalar variables as operands is straightforward. Examples include pointer arithmetic and pointer comparisons. [V]. r0. . [tbl+12].s32 q. The interesting capabilities begin with addresses. . .u16 x.4. W. The address is an offset in the state space in which the variable is declared.shared.u16 r0. 6.v4 .reg .reg .[x]. 2010 . Arrays. All addresses and address computations are byte-based. p.1.b32 p. q. tbl.const. and immediate address expressions which evaluate at compile-time to a constant address.0 6. .v4 . Load and store operations move data between registers and locations in addressable state spaces.f32 W.shared .s32 tbl[256]. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. ld. address registers. Using Addresses. Here are a few examples: .v4.f32 V.u32 42 January 24.f32 ld.u16 ld. .PTX ISA Version 2. The mov instruction can be used to move the address of a variable into a pointer.

Arrays as Operands Arrays of all types can be declared. it must be written as an address calculation prior to use. d. which may improve memory performance.g V.z and .global.x. or by indexing into the array using square-bracket notation. V. . The size of the array is a constant in the program.f32 V.reg .2.w = = = = V. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.y. Vectors as Operands Vector operands are supported by a limited subset of instructions. Vector elements can be extracted from the vector with the suffixes . [addr+offset]. . ld. ld. say {Ra. .c. or a simple “register with constant offset” expression. V2. Vectors may also be passed as arguments to called functions. Vector loads and stores can be used to implement wide loads and stores. a[N-1]. Instruction Operands 6. January 24.r. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. for use in an indirect branch or call.b V. Here are examples: ld.4.c.v2. st.a. as well as the typical color fields . [addr+offset2].reg . where the offset is a constant expression that is either added or subtracted from a register variable. The expression within square brackets is either a constant integer.b and .global. mov.u32 s. // move address of a[1] into s 6. .f32 a. Rd}.f32 ld.u32 {a.global. b.d}. Rc. If more complicated indexing is desired. a[1].d}.b.z V.global. .y V.4.x V.Chapter 6. and in move instructions to get the address of the label or function into a register. Rb. and the identifier becomes an address constant in the space where the array is declared. c. a register variable. Examples are ld.b.4.u32 s.4.v4 . and tex. which include mov. a[0].f32 {a. mov. Array elements can be accessed using an explicitly calculated byte address.v4. . Elements in a brace-enclosed vector.v4.r V.g. 2010 43 .3.w. The registers in the load/store operations can be a vector. or a braceenclosed list of similarly typed scalars. A brace-enclosed list is used for pattern matching to pull apart vectors.a 6.u32 s.

5.000 for f16). 44 January 24.PTX ISA Version 2. if a cvt.0 6.u16 instruction is given a u16 source operand and s32 as a destination operand.s32. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. except for operations where changing the size and/or type is part of the definition of the instruction. For example. 2010 . logic.5.1. Type Conversion All operands to all arithmetic. Operands of different sizes or types must be converted prior to the operation. and ~131. and data movement instruction must be of the same type and size. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. the u16 is zero-extended to s32. 6.

u32 targeting a 32-bit register will first chop to 16-bits. f2u = float-to-unsigned. f2s = float-to-signed.Chapter 6. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. 2010 45 . The type of extension (sign or zero) is based on the destination format.s16. chop = keep only low bits that fit. Instruction Operands Table 11. then sign-extend to 32-bits. f2f = float-to-float. s2f = signed-to-float. For example. Notes 1 If the destination register is wider than the destination format. zext = zero-extend. u2f = unsigned-to-float. cvt. the result is extended to the destination register width after chopping. January 24.

In PTX.PTX ISA Version 2. Modifier .rm . Rounding Modifiers Conversion instructions may specify a rounding modifier. The following tables summarize the rounding modifiers.rz . Table 12.rni . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. choosing even integer if source is equidistant between two integers.5.0 6.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13. there are four integer rounding modifiers and four floating-point rounding modifiers. 2010 .rpi Integer Rounding Modifiers Description round to nearest integer.rn .2. Modifier .rmi .rzi .

6. Registers are fastest. Table 11 gives estimates of the costs of using different kinds of memory.Chapter 6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. The register in a store operation is available much more quickly. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Much of the delay to memory can be hidden in a number of ways. 2010 47 . Another way to hide latency is to issue the load instructions as early as possible. while global memory is slowest. Instruction Operands 6. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Operand Costs Operands from different state spaces affect the speed of an operation. first access is high Notes January 24. Table 14.

PTX ISA Version 2. 2010 .0 48 January 24.

2010 49 . and an optional list of input parameters.1. Execution of the ret instruction within foo transfers control to the instruction following the call. execution of the call instruction transfers control to foo. The simplest function has no parameters or return values. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. Function declarations and definitions In PTX. January 24. These include syntax for function definitions. At the call. the function name. together these specify the function’s interface.func foo { … ret. support for variadic functions (“varargs”). or prototype. A function declaration specifies an optional list of return parameters. NOTE: The current version of PTX does not implement the underlying. parameter passing. and memory allocated on the stack (“alloca”). and is represented in PTX as follows: . In this section. function calls. and return values may be placed directly into register variables.Chapter 7. A function definition specifies both the interface and the body of the function. Abstracting the ABI Rather than expose details of a particular calling convention. arguments may be register variables or constants. so recursion is not yet supported. } … call foo.func directive. implicitly saving the return address. and Application Binary Interface (ABI). stack layout. 7. stack-based ABI. functions are declared and defined using the . we describe the features of PTX needed to achieve this hiding of the ABI. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. A function must be declared or defined prior to being called. Scalar and vector base-type input and return parameters may be represented simply as register variables. … Here.

b8 [py+11]. … … // computation using x.s32 out) bar (.u32 %res) inc_ptr ( . a .param.f64 field are aligned.c4. (%x. In PTX. 50 January 24. Second. // scalar args in . py).reg . .param. a .reg .b8 c2. consider the following C structure. char c[4]. [y+0]. %rc2.reg . note that .b8 c3. ld. … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using .param. }. Since memory accesses are required to be aligned to a multiple of the access size.param space call (%out).align 8 y[12]) { .param .b8 c1. c3. passed by value to a function: struct { double dbl. .PTX ISA Version 2.param space memory. bumpptr.func (. ld.align 8 py[12].b64 [py+ 0].param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. st.b8 [py+10]. byte array in . … ld.param.u32 %inc ) { add. [y+8]. ret.c2.c3. } … call (%r1).u32 %res.param variable y is used in function definition bar to represent a formal parameter. st.param.param. c2.param.param space variables are used in two ways. %inc.param.b8 . … st. [y+11].4). inc_ptr. st. (%r1. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . %rc1. st. } { . %rc2.param. . First.0 Example: .reg .s32 x.param .b8 c4.b32 c1. [y+10]. The . %ptr.u32 %ptr.f64 f1.c1.f64 f1.b8 [py+ 8].reg . [y+9]. 2010 .reg . %rd. ld.param state space is used to pass the structure by value: . For example.reg . this structure will be flattened into a byte array.reg space. … In this example.param.func (.f1.b8 . %rc1.b8 [py+ 9]. ld. c4.

param state space is used to receive parameter values and/or pass return values back to the caller.param memory must be aligned to a multiple of 1. January 24. For a caller.param argument must be declared within the local scope of the caller. size. the argument must also be a . Parameters in . The . and alignment.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. a .Chapter 7. Typically. The . For a caller.param byte array is used to collect together fields of a structure being passed by value. Abstracting the ABI The following is a conceptual way to think about the . or a constant that can be represented in the type of the formal parameter. the corresponding argument may be either a . • The .param variables.param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. • • • For a callee.reg state space in this way provides legacy support. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.reg variables. For . 4.param or .param space formal parameters that are byte arrays. A . or constants. This enables backend optimization and ensures that the .param state space use in device functions. 8.reg variables.param space formal parameters that are base-type scalar or vector variables.param instructions used for argument passing must be contained in the basic block with the call instruction. 2.param arguments.param and ld.. all st. Note that the choice of .param space byte array with matching type.reg space variable of matching type and size. or a constant that can be represented in the type of the formal parameter.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param variables or . • The .reg space variable with matching type and size. 2010 51 . In the case of .reg space formal parameters. The following restrictions apply to parameter passing.param or . • • Arguments may be .g. Supporting the . .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. In the case of . For a callee.reg state space can be used to receive and return base-type scalar and vector values. the corresponding argument may be either a . size. and alignment of parameters.reg or . In the case of . • • • Input and return parameters may be . or 16 bytes.

Changes from PTX 1.reg state space.x In PTX ISA version 1. PTX 2.x.param state space. formal parameters were restricted to . 2010 . For sm_2x targets. PTX 2. 52 January 24. and .1. and there was no support for array parameters.0 continues to support multiple return registers for sm_1x targets.1.param space parameters support arrays.0 restricts functions to a single return value. and a .param byte array should be used to return objects that do not fit into a register. formal parameters may be in either . PTX 1.reg or .x supports multiple return values for this purpose. Objects such as C structures were flattened and passed or returned using multiple registers.0 7.0.PTX ISA Version 2. In PTX ISA version 2.

func (. To support functions with a variable number of arguments. . variadic functions are declared with an ellipsis at the end of the input parameter list. ret.reg .u32 a.s32 val.reg . following zero or more fixed parameters: . %s1.reg .func baz ( . or 8 bytes.. 2.reg . %r1.u32 b.. ctr.func (. %va_start. maxN. %s2). Once all arguments have been processed.u32 ptr) %va_start .b32 ctr. %va_arg. … ) . call (val). or 16 bytes. } … call (%max).u32 sz. 4. .reg .b32 result. val. max. 8. … %va_start returns Loop: @p Done: January 24. along with the size and alignment of the next data value to be accessed.u32 sz.u32 align) .reg .reg . 0x8000000. . PTX provides a high-level mechanism similar to the one provided by the stdarg. . // default to MININT mov. 2010 53 .reg . the alignment may be 1. and end access to a list of variable arguments.Chapter 7. %va_end is called to free the variable argument list handle.ge p.u32 N. 0. … call (%max). 4. This handle is then passed to the %va_arg and %va_arg64 built-in functions. (2. . 4).reg .u32 ptr. In PTX. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers . . %r3). result.u32 ap. 2. call (ap).reg . ) { . .reg . Abstracting the ABI 7. the size may be 1.func okay ( … ) Built-in functions are provided to initialize. In both cases. (3.2.reg .u32. mov. ctr. or 4 bytes. 4.reg .func ( .h and varargs.func %va_end (. The function prototypes are defined as follows: .reg .u32 align) .func (. iteratively access.h headers in C.s32 result ) maxN ( . the size may be 1.reg .s32 result. (ap.reg . call %va_end. %r2.reg . for %va_arg64.b64 val) %va_arg64 (. setp. N. bra Done. . (ap). bra Loop. maxN.pred p.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. Variadic functions NOTE: The current version of PTX does not support variadic functions.u32 ptr. 2. For %va_arg.b32 val) %va_arg (.

defined as follows: . Alloca NOTE: The current version of PTX does not support alloca.reg . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.u32 ptr ) %alloca ( .func ( .reg . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.local and st. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. To allocate memory.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. The array is then accessed with ld.local instructions.PTX ISA Version 2. 54 January 24.3. If a particular alignment is required.0 7. 2010 . a function simply calls the built-in function %alloca.

January 24. PTX Instructions PTX instructions generally have from zero to four operands. We use a ‘|’ symbol to separate multiple destination registers.2. Format and Semantics of Instruction Descriptions This section describes each PTX instruction.lt p|q.1. A. // p = (a < b). 2010 55 .Chapter 8.s32. a. 8. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. while A. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. followed by some examples that attempt to show several possible instantiations of the instruction. In addition to the name and the format of the instruction. Instruction Set 8. b. the D operand is the destination operand. B. For some instructions the destination operand is optional. opcode D. A. opcode D. setp. opcode D. B. q = !(a < b). C. For instructions that create a result value. The setp instruction writes two destination registers. opcode A. B. A. and C are the source operands. the semantics are described.

Predicated Execution In PTX. add. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. use a predicate to control the execution of the branch or call instructions. i. consider the high-level code if (i < n) j = j + 1. add.pred p. optionally negated. As an example. To implement the above example as a true conditional branch. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. … // compare i to n // if false.lt. n. bra L1. 1.s32 p.pred as the type specifier. predicate registers can be declared as .PTX ISA Version 2. j.lt. add 1 to j To get a conditional branch or conditional function call. Predicates are most commonly set as the result of a comparison performed by the setp instruction.s32 j. branch over 56 January 24. This can be written in PTX as @p setp.s32 p. 2010 . predicate registers are virtual and have . i.s32 j.0 8. where p is a predicate variable. Instructions without a guard predicate are executed unconditionally. 1. So. j. the following PTX instruction sequence might be used: @!p L1: setp. n. // p = (i < n) // if i < n.3. q.reg .

3. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. ne (not-equal). ge. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and hs (higher-or-same). Table 16. 2010 57 .3. Instruction Set 8.Chapter 8. unsigned integer. Comparisons 8. If either operand is NaN. ne. and ge (greater-than-or-equal). gt (greater-than).1. the result is false. le (less-than-or-equal). ne. Unsigned Integer. The following table shows the operators for signed integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). and bitsize types.1. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. le. lt (less-than).1. gt.1. hi (higher). ordering comparisons are not defined for bit-size types. Table 15.2. lo (lower).3. The bit-size comparisons are eq and ne. The unsigned comparisons are eq. ls (lower-or-same). lt.

two operators num (numeric) and nan (isNaN) are provided. xor. neu.1. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values.u32 %r1.PTX ISA Version 2. Table 17. ltu.%p. However. or. then the result of these comparisons is true.0 To aid comparison operations in the presence of NaN values. Table 18.0. If either operand is NaN.3. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. then these comparisons have the same result as their ordered counterparts. and no direct way to load or store predicate register values. for example: selp. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. unordered versions are included: equ. num returns true if both operands are numeric values (not NaN). There is no direct conversion between predicates and integer values. geu. gtu. setp can be used to generate a predicate from an integer. leu. If both operands are numeric values (not NaN). not. and mov.2. and nan returns true if either operand is NaN. 2010 . // convert predicate to 32-bit value 58 January 24.

unsigned. a. and these are placed in the same order as the operands. most notably the data conversion instruction cvt.reg .u16 a. cvt. b.u16 d. For example. b.fX ok inv inv ok Instruction Type .e.f32 d.sX . they must match exactly.fX ok ok ok ok January 24. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. add.u16 d.bX . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. .f32. float. and this information must be specified as a suffix to the opcode. For example: . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. different sizes).. Example: .reg . Instruction Set 8.reg . For example.u16 d. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. i.bX . the add instruction requires type and size information to properly perform the addition operation (signed. 2010 59 . Signed and unsigned integer types agree provided they have the same size.uX ok ok ok inv .sX ok ok ok inv .Chapter 8. a. and integer operands are silently cast to the instruction type if needed. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.uX . Floating-point types agree only if they have the same size. It requires separate type-size modifiers for the result and source. Table 19. Type Checking Rules Operand Type . • The following table summarizes these type checking rules.4. a.

When a source operand has a size that exceeds the instruction-type size. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. 2. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. parse error. no conversion needed. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. Table 20. Operand Size Exceeding Instruction-Type Size For convenience. When used with a floating-point instruction type. 4. “-“ = allowed. st. the data will be truncated. The data is truncated to the instruction-type size and interpreted according to the instruction type. Source register size must be of equal or greater size than the instruction-type size. For example. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. 2010 . Floating-point source registers can only be used with bit-size or floating-point instruction types.0 8. for example. stored. so that narrow values may be loaded. floating-point instruction types still require that the operand type-size matches exactly.PTX ISA Version 2. The following table summarizes the relaxed type-checking rules for source operands. 1. 60 January 24. Note that some combinations may still be invalid for a particular instruction. and converted using regular-width registers. Bit-size source registers may be used with any appropriately-sized instruction type. so those rows are invalid for cvt. unless the operand is of bit-size type. Notes 3. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. stored. ld. the cvt instruction does not support . and cvt instructions permit source and destination data operands to be wider than the instruction-type size.4. the size must match exactly.bX instruction types.1. or converted to other types and sizes. inv = invalid. When used with a narrower bit-size type. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.

parse error. 2010 61 . the size must match exactly.Chapter 8. 1. When used with a narrower bit-size instruction type. the destination data is zero. 4. and is zero-extended to the destination register width otherwise. zext = zero-extend. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. The following table summarizes the relaxed type-checking rules for destination operands. Notes 3. 2. “-“ = Allowed but no conversion needed. The data is signextended to the destination register width for signed integer instruction types. Destination register size must be of equal or greater size than the instruction-type size. the data is sign-extended. January 24. Floating-point destination registers can only be used with bit-size or floating-point instruction types. Bit-size destination registers may be used with any appropriately-sized instruction type. Table 21. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types.or sign-extended to the size of the destination register. inv = Invalid. The data is sign-extended to the destination register width for signed integer instruction types. Instruction Set When a destination operand has a size that exceeds the instruction-type size. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. the data is zeroextended. otherwise. the data will be zero-extended. If the corresponding instruction type is signed integer. When used with a floatingpoint instruction type.

the threads are called divergent. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. If all of the threads act in unison and follow a single control flow path. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. or conditional return. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. and for many applications the difference in execution is preferable to limiting performance. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. When executing on a 32-bit data path.5. for many performance-critical applications. the semantics of 16-bit instructions in PTX is machine-specific. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. until they come to a conditional control construct such as a conditional branch. this is not desirable. Divergence of Threads in Control Constructs Threads in a CTA execute together. For divergent control flow.PTX ISA Version 2. A compiler or programmer may chose to enforce portable. 8. a compiler or code author targeting PTX can ignore the issue of divergent threads. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. at least in appearance. for example. 8. The semantics are described using C. by a right-shift instruction.1.uni suffix. 16-bit registers in PTX are mapped to 32-bit physical registers. However. the threads are called uniform.0 8.6. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. using the . conditional function call. At the PTX language level. 2010 . since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. If threads execute down different control flow paths.6. so it is important to have divergent threads re-converge as soon as possible. until C is not expressive enough. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. 62 January 24. Therefore. These extra precision bits can become visible at the application level. Both situations occur often in programs. and 16-bit computations are “promoted” to 32-bit computations. the optimizing code generator automatically determines points of re-convergence.

Instructions All PTX instructions may be predicated. 2010 63 . addc sub. Instruction Set 8. In the following descriptions.7. The Integer arithmetic instructions are: add sub add. the optional guard predicate is omitted from the syntax.7.Chapter 8.cc. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. 8.1.cc. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.

// .MAXINT (no overflow) for the size of the operation. add Syntax Integer Arithmetic Instructions: add Add two values.sat}. Saturation modifier: .s32 c.s16. 2010 . a.s32 d.0. add. sub. . . a. . Applies only to .. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.0 Table 22. Description Semantics Notes Performs addition and writes the resulting value into a destination register.s32 c. d = a – b.sat limits result to MININT.y. d.s32 .u32. PTX ISA Notes Target ISA Notes Examples 64 January 24.0. PTX ISA Notes Target ISA Notes Examples Table 23. . .u64.s32 .type add{.u16.s64 }.type = { .s64 }. Supported on all target architectures.u32 x.sat applies only to . Supported on all target architectures. // . d. b. d = a + b. sub.type sub{. Applies only to . add.PTX ISA Version 2.u64.b. Introduced in PTX ISA version 1. a.a. @p add. b. Introduced in PTX ISA version 1.. b. Saturation modifier: .type = { .s32.z.s32 type. . sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.sat.u32.1.u16.s32 d.s32. .c.s16.sat}. .s32 type. .sat limits result to MININT. .MAXINT (no overflow) for the size of the operation. b.sat applies only to . a.

b32 x1.2. .2.y2.cc.u32. x3. b. or testing the condition code.z4.cc}. Introduced in PTX ISA version 1. a. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. sub.CF) holding carry-in/carry-out or borrowin/borrow-out.z3.u32. Behavior is the same for unsigned and signed integers.z4.y4.y3. addc. x4. x2.cc Syntax Integer Arithmetic Instructions: add.s32 }. No other instructions access the condition code. add.b32 x1.cc Add two values with carry-out.cc.s32 }. b. Supported on all target architectures.cc specified.y4.y3. d = a + b.z3. 2010 65 .y1.y2.cc.Chapter 8.type d.cc.CF.cc. Supported on all target architectures. Instruction Set Instructions add. x2. No saturation.z2. clearing. x3.z2. .z1.cc.b32 addc. These instructions support extended-precision integer addition and subtraction. Table 24. if . No saturation. @p @p @p @p add. .z1.cc.CF No integer rounding modifiers. carry-out written to CC.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register. Behavior is the same for unsigned and signed integers.y1.type = { .b32 addc. . // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.b32 addc. d = a + b + CC.cc. @p @p @p @p add. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. a. carry-out written to CC.type d. and there is no support for setting. x4. Introduced in PTX ISA version 1.b32 addc. add.type = {.b32 addc.CF No integer rounding modifiers. addc{.cc.cc.b32 addc.

subc{. sub. a. .CF No integer rounding modifiers. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. .(b + CC. x4.z2. .b32 subc.cc. x2.b32 subc.b32 subc. Behavior is the same for unsigned and signed integers. Introduced in PTX ISA version 1.CF No integer rounding modifiers.cc}. No saturation.y3. x3. with borrow-out.cc.b32 x1.y4.cc specified.cc.cc. x2.y2.0 Table 26.y3. @p @p @p @p sub.u32. d = a – b.y4. x4. if .CF). d = a .y1.z3.cc.cc.b32 subc. @p @p @p @p sub.3. Supported on all target architectures. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.type d.b32 x1. a.b32 subc.z3. x3.cc.PTX ISA Version 2. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.z4.b32 subc. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.z2.cc.z4. 2010 . sub. Introduced in PTX ISA version 1. borrow-out written to CC. Supported on all target architectures.y1.type = { .z1.y2.s32 }. No saturation.3.u32.type = {. Behavior is the same for unsigned and signed integers.cc Subract one value from another.s32 }. b. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. withborrow-in and optional borrow-out.z1.cc.type d. . borrow-out written to CC.cc Syntax Integer Arithmetic Instructions: sub. b.

then d is twice as wide as a and b to receive the full result of the multiplication.type = { .0>. . t = a * b. creates 64 bit result January 24.y.s32. mul{.hi variant // for .. and either the upper or lower half of the result is written to the destination register. d = t<2n-1.u64.wide // for .u32.0.s32 z. .and 32-bit integer types. Description Semantics Compute the product of two values.x. save only the low 16 bits // 32*32 bits.lo.wide. mul. . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.wide suffix is supported only for 16.fys.hi.lo.s16.type d. b.s16 fa. n = bitwidth of type..n>.fxs.lo is specified. a. The . mul.fxs.. Supported on all target architectures.wide. // for . mul. . d = t<n-1. // 16*16 bits yields 32 bits // 16*16 bits.hi or .wide is specified.fys. .s64 }. If . then d is the same size as a and b.u16. .Chapter 8. If . 2010 67 . Instruction Set Table 28.lo variant Notes The type of the operation represents the types of the a and b operands.wide}.s16 fa.. d = t. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

and either the upper or lower half of the result is written to the destination register.hi mode.MAXINT (no overflow) for the size of the operation.wide}..s32 type in .s16. then d and c are the same size as a and b. a.hi variant // for . . t<2n-1.hi..q.s32.a. a. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. @p mad..type mad.lo. . t n d d d = = = = = a * b.b.hi. then d and c are twice as wide as a and b to receive the result of the multiplication..c.and 32-bit integer types.wide suffix is supported only for 16.u64. d.s64 }. ..s32 d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Description Semantics Multiplies two values and adds a third. Saturation modifier: .wide // for .r. and then writes the resulting value into a destination register. Supported on all target architectures. bitwidth of type.0> + c.lo variant Notes The type of the operation represents the types of the a and b operands.sat limits result to MININT.lo. b. // for . mad{. t<n-1. b. 68 January 24. The .p.sat. .n> + c. .PTX ISA Version 2.s32 d. mad.type = { . If . c.0. t + c.hi or .s32 r.u32. If .lo is specified. Applies only to .u16. . c.lo. 2010 .wide is specified.0 Table 29.

0. .hi variant // for .e. and return either the high or low 32-bits of the 48-bit result. // for .s32 }. .. a.a. 2010 69 .hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.hi may be less efficient on machines without hardware support for 24-bit multiply.b.. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. // low 32-bits of 24x24-bit signed multiply.0>.u32. All operands are of the same type and size. January 24. d = t<47. mul24.lo.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.16>.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.s32 d. mul24{.hi.Chapter 8. mul24.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Instruction Set Table 30. Supported on all target architectures. d = t<31. b. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values. 48bits. i.lo}.type d. mul24. mul24. t = a * b..

s32 d. mad24..u32. mad24.16> + c. mad24. 48bits.0 Table 31. // for . i. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. // low 32-bits of 24x24-bit signed multiply.hi variant // for . Description Compute the product of two 24-bit integer values held in 32-bit source registers.lo}.hi.0> + c. Supported on all target architectures.type = { . c.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. Return either the high or low 32-bits of the 48-bit result. Saturation modifier: .lo. t = a * b. 70 January 24. c. mad24{.hi mode. .s32 type in . and add a third.0.a. b.hi may be less efficient on machines without hardware support for 24-bit multiply. Applies only to . mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. d.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value. .b. a.e. b. d = t<47.s32 }. All operands are of the same type and size.c. d = t<31..hi..type mad24.. 32-bit value to either the high or low 32-bits of the 48-bit result.PTX ISA Version 2.sat.MAXINT (no overflow).lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. mad24. a.sat limits result of 32-bit signed addition to MININT. 2010 .s32 d.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

January 24, 2010

71

PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

72

January 24, 2010

Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

January 24, 2010

73

.type = { .b64 }. mask = 0x8000000000000000.b32 type. } while (d < max && (a&mask == 0) ) { d++. clz. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. popc Syntax Integer Arithmetic Instructions: popc Population count.b32) { max = 32. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros.type = { .b32 clz.b64 d.b32 popc. For .0 Table 39. X. // cnt is . For . // cnt is . . .type == . mask = 0x80000000. cnt. a = a << 1. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b32. .b64 d. clz requires sm_20 or later.0. the number of leading zeros is between 0 and 64. inclusively. a.b64 }. } Introduced in PTX ISA version 2. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. X. a. clz. d = 0. } else { max = 64. a.u32 PTX ISA Notes Target ISA Notes Examples Table 40.0. if (. popc requires sm_20 or later.type d.type d.b64 type.b32. a.u32 Semantics 74 January 24. a = a >> 1.PTX ISA Version 2. d = 0. popc. the number of leading zeros is between 0 and 32. 2010 . cnt. popc. inclusively. while (a != 0) { if (a&0x1) d++.

bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. Operand a has the instruction type. d. 2010 75 .u64. bfind returns 0xFFFFFFFF if no non-sign bit is found. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32 January 24. If . } } if (.shiftamt. // cnt is .shiftamt is specified. a.s64 cnt. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.u32 d.d. a. i>=0.s32) ? 31 : 63. break.Chapter 8. bfind. For signed integers. i--) { if (a & (1<<i)) { d = i. Semantics msb = (. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs.type==.type = { . For unsigned integers.u32. . Description Find the bit position of the most significant non-sign bit in a and place the result in d. bfind. .0. and operand d has type .type==. bfind requires sm_20 or later.shiftamt. bfind returns the bit position of the most significant “1”. for (i=msb.u32 || .u32.type d.s64 }. d = -1. Instruction Set Table 41. . .s32. bfind.shiftamt && d != -1) { d = msb . a. X.type bfind.

type d. . brev requires sm_20 or later. for (i=0.b32.type==. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i++) { d[i] = a[msb-i]. i<=msb.b32 d. Description Semantics Perform bitwise reversal of input.0.PTX ISA Version 2. brev. 2010 . msb = (.0 Table 42. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. brev. a.type = { .b32) ? 31 : 63. a. 76 January 24. .b64 }.

type==. Source b gives the bit field starting bit position. 2010 77 . i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.msb)].len. The destination d is padded with the sign bit of the extracted field.u32.type==. The sign bit of the extracted field is defined as: .u32.0.s32) ? 31 : 63. January 24. bfe. pos = b. .Chapter 8.u32 || . .u64. Description Extract bit field from a and place the zero or sign-extended result in d. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. and operands b and c are type . b. If the start position is beyond the msb of the input.type = { . .s32. d = 0. Semantics msb = (. Operands a and d have the same type as the instruction type.a. if (.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. len = c. i<=msb. bfe requires sm_20 or later. else sbit = a[min(pos+len-1. for (i=0.type==. the destination d is filled with the replicated sign bit of the extracted field. and source c gives the bit field length in bits.b32 d. the result is zero. Instruction Set Table 43. otherwise If the bit field length is zero. bfe.type d.u32 || . a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .s32. .u64 || len==0) sbit = 0.u32.type==.s64 }. .u64: .start. c.

b32 d. Semantics msb = (.type f. b. pos = c.PTX ISA Version 2. 78 January 24. . d. len = d. c. the result is b. Source c gives the starting bit position for the insertion. i<len && pos+i<=msb.b32.0 Table 44. Description Align and insert a bit field from a into b. bfi.b. Operands a.b32) ? 31 : 63.type==. and source d gives the bit field length in bits. and f have the same type as the instruction type. If the bit field length is zero.u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If the start position is beyond the msb of the input. for (i=0. a.len. bfi requires sm_20 or later. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. and place the result in f.0.start. f = b. 2010 . i++) { f[pos+i] = a[i]. the result is b. and operands c and d are type .a. b.b64 }. .type = { . bfi.

f4e.ecl. In the generic form (no mode specified). Instruction Set Table 45. a.b4e. default mode index d. msb=1 means replicate the sign. a} = {{b7.ecr.b2 source select c[11:8] d.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. prmt. 2010 79 . or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). the permute control consists of four 4-bit selection values. and reassemble them into a 32-bit destination register. b0}}. the four 4-bit values fully specify an arbitrary byte permute. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair.rc16 }. . mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. The msb defines if the byte value should be copied. b2.b1 source select c[7:4] d. Note that the sign extension is only performed as part of generic form.mode = { . {b3. b6. . Description Pick four arbitrary bytes from two 32-bit registers. For each byte in the target register. . . b1. a 4-bit selection value is defined. b4}.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. . as a 16b permute code.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. c. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. .mode} d. msb=0 means copy the literal value.b3 source select c[15:12] d.Chapter 8. b. b5.rc8. Thus. The bytes in the two source registers are numbered from 0 to 7: {b.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d.b32{.

} else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. tmp[23:16] = ReadByte( mode. r2. 80 January 24. r3. ctl[1] = (c >> 4) & 0xf. ctl[1]. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. } tmp[07:00] = ReadByte( mode. tmp[15:08] = ReadByte( mode.f4e r1. r4.b32 prmt. ctl[2]. r3. ctl[2] = (c >> 8) & 0xf. 2010 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prmt. tmp[31:24] = ReadByte( mode.PTX ISA Version 2. r2.0 Semantics tmp64 = (b<<32) | a.b32. tmp64 ).0. prmt requires sm_20 or later. tmp64 ). ctl[3] = (c >> 12) & 0xf. r4. ctl[3]. tmp64 ). ctl[0]. r1. tmp64 ).

2010 81 . Instruction Set 8.f32 and .f64 register operands and constant immediate values.Chapter 8.7. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. Floating-Point Instructions Floating-point instructions operate on .2.

sqrt}.min.f64 mad.ftz .rnd.sub. Note that future implementations may support NaN payloads for single-precision instructions.rn and instructions may be folded into a multiply-add.rn .f32 {div.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture. but single-precision instructions return an unspecified NaN.f64 {sin.max}. Instruction Summary of Floating-Point Instructions . 2010 . with NaNs being flushed to positive zero.32 and fma.min. Double-precision instructions support subnormal inputs and results. Table 46.approx.0 The following table summarizes floating-point instructions in PTX. . sub.0.approx.rcp.rn and instructions may be folded into a multiply-add.f64 {abs.rnd.sat Notes If no rounding modifier is specified.rnd.0].target sm_1x No rounding modifier.PTX ISA Version 2.f64 div.f64 are the same. 1.rcp. Single-precision add.approx.neg.full. The optional . so PTX programs should not rely on the specific single-precision NaNs being generated. 82 January 24.neg.lg2.sqrt}.cos. NaN payloads are supported for double-precision instructions.rnd.f64 rsqrt.rcp. If no rounding modifier is specified. mul.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. . {mad.mul}.target sm_20 mad.max}.f32 rsqrt. and mad support saturation of results to the range [0. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.sub.f32 .fma}. {add.f32 {div.f64 and fma.mul}.f32 {abs. default is . default is .fma}.f32 {add.rnd.f32 {mad.rp .target sm_20 .f32 are the same.rm .rz .rnd.approx. No rounding modifier.ex2}.sqrt}.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {div.

op p. testp.type = { . .f32. C.0. .number. true if the input is a subnormal number (not NaN. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. X. f0.f64 isnan. copysign requires sm_20 or later.number testp. . 2010 83 .f32 testp. A.f32 copysign. a. positive and negative zero are considered normal numbers. .op.type = { .f64 x.finite testp. and return the result as d.f32. not infinity). B. Table 48.notanumber testp. testp Syntax Floating-Point Instructions: testp Test floating-point property.0. .finite. . z. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. testp requires sm_20 or later.f64 }. Instruction Set Table 47. .notanumber.type d. // result is .notanumber. testp. Introduced in PTX ISA version 2.subnormal }. not infinity) As a special case. copysign.Chapter 8.pred = { . b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. copysign.infinite.normal.infinite testp. January 24.infinite.type .normal testp. p. a. y. . .f64 }.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. testp.

add.rm mantissa LSB rounds towards negative infinity .0.rm. Rounding modifiers have the following target requirements: . Saturation modifier: . An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.rz. .rn mantissa LSB rounds to nearest even .f32 flushes subnormal inputs and results to sign-preserving zero. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 flushes subnormal inputs and results to sign-preserving zero. a.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64 requires sm_13 or later. .PTX ISA Version 2.rn): . d. a.rz mantissa LSB rounds towards zero .rnd}.0].rz available for all targets . add.f32. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. sm_1x: add.f3. add Syntax Floating-Point Instructions: add Add two values. .ftz.f64. 1. requires sm_20 Examples @p add. Description Semantics Notes Performs addition and writes the resulting value into a destination register. Rounding modifiers (default is .f32 clamps the result to [0. .f32 add{.rp for add.rm.rnd}{. b.f32 f1.0 Table 49.sat. NaN results are flushed to +0.rz.0. add{. 84 January 24. b.ftz}{. 2010 .rp }. add. .ftz. .f64 d.0f. In particular.f32 supported on all target architectures.sat}. subnormal numbers are supported. requires sm_13 for add.rn.rn.f2.f64 supports subnormal numbers. add. add. d = a + b.rnd = { .

sub. b.rp for sub.f64 d.f64 requires sm_13 or later. In particular. Instruction Set Table 50. sub.b. January 24.0f. d = a . NaN results are flushed to +0.rm.Chapter 8.0.sat.rn.f32 sub{.a. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. . .sat}. .rn.f32 flushes subnormal inputs and results to sign-preserving zero.rz available for all targets .ftz.0.rn.f32 c. b.ftz.ftz}{. sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f3. a. sub Syntax Floating-Point Instructions: sub Subtract one value from another. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rnd}{. Saturation modifier: sub.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero.rm.b. requires sm_13 for sub.f64 supports subnormal numbers.rp }.rz mantissa LSB rounds towards zero . Rounding modifiers have the following target requirements: . .rnd}. . A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.f2.0]. sub{.rz. requires sm_20 Examples sub. sub.f32 f1.rm mantissa LSB rounds towards negative infinity . 2010 85 . sub.rn): . d.rnd = { .f64. subnormal numbers are supported.f32.f32 clamps the result to [0. . a. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Rounding modifiers (default is .rn mantissa LSB rounds to nearest even . sm_1x: sub. 1.

. .f32.PTX ISA Version 2. For floating-point multiplication.ftz. requires sm_13 for mul. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. subnormal numbers are supported.0.rn.f32 circumf.rnd}{.f64 d. 2010 .rm.0]. NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.rnd = { . b. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .rn. Saturation modifier: mul. a.rz available for all targets .rm.rnd}. . sm_1x: mul. .sat}.sat.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz. d = a * b. d. In particular.rp }. all operands must be the same size. Rounding modifiers have the following target requirements: . Description Semantics Notes Compute the product of two values. mul Syntax Floating-Point Instructions: mul Multiply two values.rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later.rn): . A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer. mul{. mul.0.rz mantissa LSB rounds towards zero . Rounding modifiers (default is .ftz}{.0 Table 51.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.pi // a single-precision multiply 86 January 24.rp for mul. mul. . mul. mul.f32 mul{.f64. a.rn mantissa LSB rounds to nearest even .f32 clamps the result to [0.0f.f32 supported on all target architectures. 1. requires sm_20 Examples mul. b.ftz.radius.

d.f32 requires sm_20 or later.4. fma. Instruction Set Table 52.x.0]. fma.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.ftz}{.sat. d = a*b + c. Rounding modifiers (no default): .rm mantissa LSB rounds towards negative infinity .f64 introduced in PTX ISA version 1. fma. subnormal numbers are supported. fma.b.0. d. The resulting value is then rounded to double precision using the rounding mode specified by . again in infinite precision. b.f32 clamps the result to [0. NaN results are flushed to +0. fma.f64 supports subnormal numbers. sm_1x: fma.rn.rnd = { .f32 fma.rnd.f32 fma.f64 requires sm_13 or later. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition.sat}. fma.rnd{.f64.f32 flushes subnormal inputs and results to sign-preserving zero. .rnd.a.rn.rn mantissa LSB rounds to nearest even . 1.f64 computes the product of a and b to infinite precision and then adds c to this product.0.f32 is unimplemented in sm_1x.c. a.f64 is the same as mad.ftz. . a.z. c.rz.rz mantissa LSB rounds towards zero . fma. PTX ISA Notes Target ISA Notes Examples January 24. fma.rn. fma Syntax Floating-Point Instructions: fma Fused multiply-add.f64 w.f32 computes the product of a and b to infinite precision and then adds c to this product.0f. @p fma. .rnd.Chapter 8.y. again in infinite precision.rm. . c. fma. fma. 2010 87 . Saturation: fma.f64 d.rp }. b. The resulting value is then rounded to single precision using the rounding mode specified by .f32 introduced in PTX ISA version 2.ftz.

f64 computes the product of a and b to infinite precision and then adds c to this product. but the exponent is preserved.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. mad. mad.f32 is identical to the result computed using separate mul and add instructions.target sm_1x: mad. Unlike mad.rnd.rn. . mad.ftz.f64.e.rnd. Rounding modifiers (no default): . the treatment of subnormal inputs and output follows IEEE 754 standard.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to double precision using the rounding mode specified by . . c.{f32. where the mantissa can be rounded and the exponent will be clamped. For . again in infinite precision. c.rz mantissa LSB rounds towards zero . fma. For .rnd = { . c. Description Semantics Notes Multiplies two values and adds a third.rm. mad. // .rp }.f32 clamps the result to [0.PTX ISA Version 2. mad. mad. // .rnd.f64}. subnormal numbers are supported. sm_1x: mad.rnd. The resulting value is then rounded to single precision using the rounding mode specified by . The exception for mad.rz. mad. and then the mantissa is truncated to 23 bits. The resulting value is then rounded to double precision using the rounding mode specified by .f32 mad. d = a*b + c.f32 is when c = +/-0.rn mantissa LSB rounds to nearest even . b. a.0f. When JIT-compiled for SM 2. Saturation modifier: mad.{f32.rn. again in infinite precision. b.sat}. In this case.ftz}{.f32.sat}.f32 mad.f32 computes the product of a and b to infinite precision and then adds c to this product. 1. .0].f32 flushes subnormal inputs and results to sign-preserving zero.0. and then writes the resulting value into a destination register.0 Table 53.f64} is the same as fma. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.ftz}{..f32).target sm_20: mad. b.target sm_20 d. mad.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 computes the product of a and b to infinite precision and then adds c to this product.target sm_1x d.f64 d.0.rnd{. 2010 .f64 supports subnormal numbers.f32 computes the product of a and b at double precision. mad{.f32 is implemented as a fused multiply-add (i. a. // .0 devices. a.f64 is the same as fma. 88 January 24. mad. NaN results are flushed to +0.sat. Note that this is different from computing the product with mul. again in infinite precision.rm mantissa LSB rounds towards negative infinity .target sm_13 and later .

a.f64. requires sm_20 Examples @p mad.f32 supported on all target architectures. Legacy mad.. mad..rz. Target ISA Notes mad.0. 2010 89 .f64 instructions having no rounding modifier will map to mad.b.f32 for sm_20 targets.rm..rp for mad.f64 requires sm_13 or later.c.f32.rn. January 24.f64..f32 d..4 and later.rp for mad.rm. a rounding modifier is required for mad.0 and later.rn. In PTX ISA versions 2..rz. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.Chapter 8. Rounding modifiers have the following target requirements: . requires sm_13 .rn. In PTX ISA versions 1.f64. a rounding modifier is required for mad.

f64 requires sm_13 or later. // // // // fast.rz mantissa LSB rounds towards zero .approx. approximate division by zero creates a value of infinity (with same sign as a). For PTX ISA version 1. 2010 .full. sm_1x: div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .full{. and div. one of .f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. div Syntax Floating-Point Instructions: div Divide one value by another. . b.approx. or .f32 div. .approx{.f64 defaults to div.ftz.f32 supported on all target architectures. x. Fast.PTX ISA Version 2. div.full. For b in [2-126.3. computed as d = a * (1/b).f32 implements a fast approximation to divide.approx.f64 introduced in PTX ISA version 1.rn. PTX ISA Notes div.approx. b.f32 and div.f32 div. and rounding introduced in PTX ISA version 1. zd.f64 d.ftz.f64. b.ftz}.full. subnormal numbers are supported.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. but is not fully IEEE 754 compliant and does not support rounding modifiers. .rm.4.f64 supports subnormal numbers. a. Subnormal inputs and results are flushed to sign-preserving zero.rnd.f32 implements a relatively fast. . d = a / b. div.rnd. xd. b.full.0 through 1.ftz. div.14159.approx.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.3.ftz. div.approx.rnd = { .rz. Description Semantics Notes Divides a by b. d. approximate single-precision divides: div. . .circum. a. y.ftz.f32 div. full-range approximation that scales operands to achieve better accuracy. yd. div. div.rn mantissa LSB rounds to nearest even .f32 div. Fast.f64 diam. the maximum ulp error is 2. stores result in d.{rz. d. For PTX ISA versions 1.0 Table 54. a. d.rm mantissa LSB rounds towards negative infinity .f32 defaults to div.4 and later.rnd{. Examples 90 January 24. z. 2126].rn.rn. div.f64 requires sm_20 or later. The maximum ulp error is 2 across the full range of inputs. div. a.full. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .rn. div.rp}. Explicit modifiers . Target ISA Notes div.f32 requires sm_20 or later.rp }.rnd is required.f32 div.0.f32.f32 and div.rm.

a. Take the absolute value of a and store the result in d. d = |a|. Negate the sign of a and store the result in d. d = -a.f32 flushes subnormal inputs and results to sign-preserving zero. abs. sm_1x: abs. a.ftz.f0. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. abs. neg.f32 supported on all target architectures. abs.f0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz}. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.f32 x.f64 d.f32 abs. d. January 24. 2010 91 . abs{. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.ftz. subnormal numbers are supported. neg.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0.f32 flushes subnormal inputs and results to sign-preserving zero. Instruction Set Table 55. neg. Subnormal numbers: sm_20: By default.f64 requires sm_13 or later.ftz. NaN inputs yield an unspecified NaN. sm_1x: neg. Table 56. d.f32 neg.f32 flushes subnormal inputs and results to sign-preserving zero. a.f64 requires sm_13 or later.Chapter 8.f64 supports subnormal numbers.f32 supported on all target architectures.f32 x. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. subnormal numbers are supported.ftz. Subnormal numbers: sm_20: By default.0.f64 supports subnormal numbers. NaN inputs yield an unspecified NaN. neg. abs. neg. neg{.ftz}.f64 d. abs. a.

ftz.f32 supported on all target architectures.f64 z. a. b. (a < b) ? a : b. subnormal numbers are supported.f2.ftz}. max. Store the maximum of a and b in d. 2010 .z.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. b.c.f1.ftz. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.0. a. a. a. (a > b) ? a : b. a.f32 flushes subnormal inputs and results to sign-preserving zero.f32 min. min. max.0 Table 57. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. max. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. a.f64 requires sm_13 or later.PTX ISA Version 2. a. Store the minimum of a and b in d. min{. sm_1x: min. sm_1x: max. b. max. d d d d = = = = NaN. a. @p min. d.f64 d. b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.x.f32 min.c.0. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. min.b.b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.f32 supported on all target architectures. max{. 92 January 24.f64 f0. d. d d d d = = = = NaN. min. b. Table 58.f32 max. min. max.f32 flushes subnormal inputs and results to sign-preserving zero. subnormal numbers are supported. b.f64 supports subnormal numbers.f32 max.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f64 d.ftz.f64 requires sm_13 or later.

General rounding modifiers were added in PTX ISA version 2.Chapter 8.approx.f32 defaults to rcp.0 over the range 1. d = 1 / a. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding . rcp. a.4 and later.rnd = { . For PTX ISA version 1.x.f32. rcp.rn.rnd is required. .f64 requires sm_13 or later.ftz. rcp.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rm.0.r.f32 rcp.rm mantissa LSB rounds towards negative infinity .rn mantissa LSB rounds to nearest even .0. For PTX ISA versions 1. Examples January 24.f64 supports subnormal numbers.rm.rn.rn.f64 introduced in PTX ISA version 1. xi.ftz.0 -Inf -Inf +Inf +Inf +0.approx and .ftz}.0.ftz were introduced in PTX ISA version 1.approx.ftz.0 +subnormal +Inf NaN Result -0.rz. sm_1x: rcp.0-2. and rcp.3. xi.rp }. PTX ISA Notes rcp. rcp. // fast.rnd. a. one of .f32 flushes subnormal inputs and results to sign-preserving zero. store result in d.f64 defaults to rcp.f32 requires sm_20 or later.rnd{.{rz.f64 ri. Description Semantics Notes Compute 1/a. Target ISA Notes rcp. Input -Inf -subnormal -0.f64 d. 2010 93 .f32 rcp. . rcp. rcp.f64.approx or .rn. rcp. d.approx{. The maximum absolute error is 2-23. rcp.rnd. a.0 +0.approx.4.f32 rcp.f32 and rcp.rn.ftz}.f32 flushes subnormal inputs and results to sign-preserving zero. d. rcp.f64 and explicit modifiers .ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Instruction Set Table 59.rz mantissa LSB rounds towards zero .f32 rcp. rcp.rn.x.rp}. .0 through 1.f32 implements a fast approximation to reciprocal.f64 requires sm_20 or later.f32 supported on all target architectures. subnormal numbers are supported.approx.

0 Table 60.approx.rnd is required.rnd = { .0 through 1.0.ftz.f32 and sqrt.4 and later. approximate square root d.rz.0 +subnormal +Inf NaN Result NaN NaN -0.rm. .approx.rp}.0. sqrt. sqrt.{rz.x.ftz.ftz}.approx or .rnd{.approx.rnd. a. store in d. sqrt.f32 sqrt.approx and . General rounding modifiers were added in PTX ISA version 2. // fast.f64 supports subnormal numbers. a. r.f64 r. 2010 .f32 supported on all target architectures.f64. The maximum absolute error for sqrt.0 +0. PTX ISA Notes sqrt.f64 and explicit modifiers .ftz.approx. .f32 requires sm_20 or later.PTX ISA Version 2.0 +0.ftz}.f32 sqrt.rn. sqrt.x.f32 sqrt.rn. sqrt. sqrt.f32.rn.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . a.rn.ftz. // IEEE 754 compliant rounding . Target ISA Notes sqrt.f64 requires sm_20 or later.f64 introduced in PTX ISA version 1.rn. For PTX ISA version 1. and sqrt. Description Semantics Notes Compute sqrt(a). sm_1x: sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f32 is TBD.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f32 implements a fast approximation to square root. Input -Inf -normal -subnormal -0. sqrt. subnormal numbers are supported.rz mantissa LSB rounds towards zero .rnd.f64 d. one of . For PTX ISA versions 1.approx{.x. d = sqrt(a). // IEEE 754 compliant rounding d.3. sqrt.f32 defaults to sqrt.f64 requires sm_13 or later.4. sqrt.f64 defaults to sqrt. r.f32 sqrt.approx. Examples 94 January 24. .rm.0 +0.ftz were introduced in PTX ISA version 1.rp }.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. sqrt.0 -0.rn.rn mantissa LSB rounds to nearest even .

0.approx.f64 d.approx{.f32 flushes subnormal inputs and results to sign-preserving zero.f64 isr.f32.f32 defaults to rsqrt.ftz were introduced in PTX ISA version 1. Compute 1/sqrt(a). The maximum absolute error for rsqrt.ftz}. Input -Inf -normal -subnormal -0.f32 flushes subnormal inputs and results to sign-preserving zero.approx implements an approximation to the reciprocal square root.f32 rsqrt.0 +0.0 NaN The maximum absolute error for rsqrt.approx. subnormal numbers are supported.f64 defaults to rsqrt.f64 supports subnormal numbers.approx.ftz. a.4. rsqrt. rsqrt. x. X. d = 1/sqrt(a).ftz.approx and . sm_1x: rsqrt. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. January 24. rsqrt. the . Target ISA Notes Examples rsqrt. a.f32 rsqrt.f64 is TBD.f32 and rsqrt.0 through 1.f32 supported on all target architectures. and rsqrt.ftz. Subnormal numbers: sm_20: By default. store the result in d. 2010 95 .approx.4 over the range 1. rsqrt.Chapter 8.approx.f64 is emulated in software and are relatively slow. Note that rsqrt.4 and later. rsqrt. rsqrt.3.0.approx modifier is required. d.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.approx. ISR.f64.f64 were introduced in PTX ISA version 1. For PTX ISA version 1. Explicit modifiers .f32 is 2-22. PTX ISA Notes rsqrt.f64 requires sm_13 or later. For PTX ISA versions 1. Instruction Set Table 61. rsqrt.0-4.

approx.ftz. Input -Inf -subnormal -0.ftz}.approx.f32 introduced in PTX ISA version 1.0 through 1. sin. PTX ISA Notes sin.0 +0. Find the sine of the angle a (in radians).4. 2010 .9 in quadrant 00.0 Table 62.f32. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.approx. For PTX ISA version 1.4 and later.0 -0.0.0 +0.ftz introduced in PTX ISA version 1. 96 January 24. For PTX ISA versions 1.approx{. Target ISA Notes Examples Supported on all target architectures. a.approx and . subnormal numbers are supported. a. Explicit modifiers .f32 d.ftz. sin. sin.ftz.f32 sa. d = sin(a).0 NaN NaN The maximum absolute error is 2-20. sin.PTX ISA Version 2.approx modifier is required. Subnormal numbers: sm_20: By default.3.0 +subnormal +Inf NaN Result NaN -0.0 +0.f32 defaults to sin.f32 implements a fast approximation to sine.f32 flushes subnormal inputs and results to sign-preserving zero. sin. the . sm_1x: Subnormal inputs and results to sign-preserving zero.

Explicit modifiers .0 through 1. a. cos.ftz introduced in PTX ISA version 1. For PTX ISA versions 1.Chapter 8.0. Input -Inf -subnormal -0. Subnormal numbers: sm_20: By default. Instruction Set Table 63.f32 introduced in PTX ISA version 1.ftz. a. d = cos(a).0 +1.f32.approx modifier is required. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 +1.f32 d.4.approx.approx.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}. cos.approx and . cos. the . cos.0 +subnormal +Inf NaN Result NaN +1. Find the cosine of the angle a (in radians).0 NaN NaN The maximum absolute error is 2-20.0 +1.9 in quadrant 00. Target ISA Notes Examples Supported on all target architectures.approx. cos. subnormal numbers are supported.f32 ca.4 and later.3.0 +0. For PTX ISA version 1. PTX ISA Notes cos. 2010 97 . sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to cosine.f32 defaults to cos.approx{.ftz.ftz. January 24.

2010 . the . Explicit modifiers .0 through 1.ftz.4 and later.0 +0. lg2.approx.f32 la.ftz introduced in PTX ISA version 1. lg2.0 Table 64. Target ISA Notes Examples Supported on all target architectures. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz.0.ftz.ftz}.approx modifier is required. sm_1x: Subnormal inputs and results to sign-preserving zero.PTX ISA Version 2.f32 Determine the log2 of a.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. The maximum absolute error is 2-22. subnormal numbers are supported.approx. PTX ISA Notes lg2. For PTX ISA version 1. lg2.4.f32 introduced in PTX ISA version 1. Input -Inf -subnormal -0. For PTX ISA versions 1. 98 January 24. lg2.approx{.f32 flushes subnormal inputs and results to sign-preserving zero. a.f32 defaults to lg2. d = log(a) / log(2). a.approx.f32 implements a fast approximation to log2(a).3.f32. Subnormal numbers: sm_20: By default.6 for mantissa.approx and . lg2.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

January 24, 2010

99

PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

100

January 24, 2010

Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

January 24, 2010

101

le. geu. Integer Notes Floating Point Notes The ordered comparisons are eq. . Applies to all numeric types. @q setp. .f32 flushes subnormal inputs to sign-preserving zero. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.ftz}.B) is one of: and.u32 p|q. then these comparisons have the same result as their ordered counterparts. sm_1x: setp. le.f32. num. a. hs equ.s32. 2010 .dtype. and hs for lower. setp with . neu.PTX ISA Version 2. ge.s16. gt. loweror-same.BoolOp{. p[|q]. If either operand is NaN. For unsigned values. ltu. {!}c. hi. ls.CmpOp{.pred variables.dtype.0. . lt. the comparison operators lo.ftz}.s64.b. gtu. gt. setp. nan The Boolean operator BoolOp(A. gtu. hi. c).ftz. neu. subnormal numbers are supported.f32 flushes subnormal inputs to sign-preserving zero. and nan returns true if either operand is NaN. and can be one of: eq. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.eq. geu. ne. le. setp. . Description Compares two values and combines the result with another predicate value by applying a Boolean operator. unordered versions are included: equ.s32 setp. b. ltu. and (optionally) combine this result with a predicate value by applying a Boolean operator. ne. or.u32. lt. The destinations p and q must be . b. num returns true if both operands are numeric values (not NaN). leu. ls.f32 comparisons.and.i.b64. . 102 January 24. gt. .a. gt.f64 source type requires sm_13 or later.type setp.0 Table 67. Subnormal numbers: sm_20: By default.u64. ge. The untyped.r. The signed and unsigned comparison operators are eq.f64 }.type . If both operands are numeric values (not NaN). higher. respectively. leu. Semantics t = (a CmpOp b) ? 1 : 0. a.CmpOp. then the result of these comparisons is true.dtype. p. . ne.f64 supports subnormal numbers. c). setp. p[|q]. p = BoolOp(t. q = BoolOp(!t.type = { . Modifier .lt. and higher-or-same may be used instead of lt. ge. lt. . To aid comparison operations in the presence of NaN values.ftz applies only to . bit-size comparisons are eq and ne. the result is false. This result is written to the first destination operand. le. . A related value computed using the complement of the compare result is written to the second destination operand. . ge. If either operand is NaN.n.b32. lo. xor.u16. The comparison operator is a suffix on the instruction.b16.

dtype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. B. 2010 103 .u64. d = (c == 1) ? a : b. .s16.dtype = { . c.f32 A. Semantics Floating Point Notes January 24. Instruction Set Table 68.f64 requires sm_13 or later. y. z.f32 flushes subnormal values of operand c to sign-preserving zero.u32. a is stored in d.u64. b. @q selp. . Operands d. .s32 selp. Modifier .p. . c.ftz. The selected input is copied to the output without modification. and operand a is selected. based on the sign of the third operand. and b must be of the same type.s16.ftz}. a. slct Syntax Comparison and Selection Instructions: slct Select one source operand.f32. C. negative zero equals zero. slct. . . selp Syntax Comparison and Selection Instructions: selp Select between source operands. . If c is True. Introduced in PTX ISA version 1. . b otherwise.u16.f32 d. For . . . Description Conditional selection.u16. slct. b.Chapter 8.ftz. Operand c is a predicate.s32 x.dtype.f64 requires sm_13 or later. .dtype. val.f32 comparisons.dtype. fval.0.ftz applies only to . a. If operand c is NaN. a.s64. f0. a is stored in d. a. and operand a is selected. Table 69.0. otherwise b is stored in d.b16.f32.u32.b16. slct. . . .u32. Subnormal numbers: sm_20: By default.b64. .type = { .type d.b32.f64 }. c. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. sm_1x: slct. based on the value of the predicate source operand.g. . selp.x. operand c must match the second instruction type.u64.f32 comparisons.b32.s64.f64 }. slct. d.t. . selp.s32. . d = (c >= 0) ? a : b. . subnormal numbers are supported. and b are treated as a bitsize type of the same width as the first instruction type. If c ≥ 0. a. .f32 r0.xp. Operands d.s32.b64.s32 slct{. slct.r.f32 flushes subnormal values of operand c to sign-preserving zero. . . b. the comparison is unordered and operand b is selected.

0 8. Instructions and.7. or.PTX ISA Version 2. This permits bit-wise operations on floating point values without having to define a union to access the bits. 2010 . xor. performing bit-wise operations on operands of any type. and not also operate on predicates. provided the operands are of the same size. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4. The logical shift instructions are: and or xor not cnot shl shr 104 January 24.

b32. or Syntax Logic and Shift Instructions: or Bitwise OR.q. d = a | b. . .type = { .0x80000000.r. and Syntax Logic and Shift Instructions: and Bitwise AND.0. d = a & b. and. January 24.0.pred.type = { . Supported on all target architectures. The size of the operands must match.b32 mask mask.pred p. Supported on all target architectures. Table 71.type d. . The size of the operands must match. sign.b32.b16.b32 and. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.type d. Introduced in PTX ISA version 1. .r. a.0x00010001 or.fpvalue.b16. but not necessarily the type.b32 x. b. or. . Allowed types include predicate registers.Chapter 8. . . Introduced in PTX ISA version 1. a.q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.pred.b64 }. 2010 105 .b64 }. b. Instruction Set Table 70. and. or. but not necessarily the type. Allowed types include predicate registers.

mask.q. d = a ^ b. Supported on all target architectures. . The size of the operands must match.b32. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.x. xor. .b16 d. d.b16.b32 xor.b32.type d.0 Table 72. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. 106 January 24. The size of the operands must match. but not necessarily the type. a. . Allowed types include predicate registers.0.b16.pred. .b32.type = { . not.a.b64 }.b64 }.q.pred.b64 }. The size of the operands must match. a.b16. .type d. cnot. not. not Syntax Logic and Shift Instructions: not Bitwise negation. .0.b32 d.type d. Supported on all target architectures.pred p.b32 mask. one’s complement. . 2010 . Supported on all target architectures. not. Introduced in PTX ISA version 1. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. xor. Table 74. but not necessarily the type. Introduced in PTX ISA version 1. Allowed types include predicates. d = ~a.type = { . b. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. a.PTX ISA Version 2. Table 73. . xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). cnot. . Introduced in PTX ISA version 1.0x0001. d = (a==0) ? 1 : 0.r.0. but not necessarily the type. .type = { .

Signed shifts fill with the sign bit.s32 shr.b16.a. shr Syntax Logic and Shift Instructions: shr Shift bits right. .1. Supported on all target architectures.j. b. . a.s32. shl. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.a.u16.i.s64 }. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. . Shift amounts greater than the register width N are clamped to N.b64 }. The sizes of the destination and first source operand must match. PTX ISA Notes Target ISA Notes Examples January 24.s16. shl. . The b operand must be a 32-bit value. . The sizes of the destination and first source operand must match. but not necessarily the type. a. zero-fill on right. . d = a >> b.u64. Bit-size types are included for symmetry with SHL.type d. PTX ISA Notes Target ISA Notes Examples Table 76. shr. Introduced in PTX ISA version 1. 2010 107 . i. . regardless of the instruction type.b16.2. b. Instruction Set Table 75.b32. regardless of the instruction type. Shift amounts greater than the register width N are clamped to N.b16 c. .type = { .b32 q. k.type = { . . d = a << b.b64.u32.2.type d. but not necessarily the type. Introduced in PTX ISA version 1. sign or zero fill on left. .u16 shr. unsigned and untyped shifts fill with 0. shl Syntax Logic and Shift Instructions: shl Shift bits left.Chapter 8. . The b operand must be a 32-bit value.0.b32.i. .0. Supported on all target architectures. shr.

The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.7. ld. local. and sust support optional cache operations. suld. and st operate on both scalar and vector types. or shared state spaces. mov. The isspacep instruction is provided to query whether a generic address falls within a particular state space window.PTX ISA Version 2.5. Instructions ld. possibly converting it from one format to another. 2010 . ldu.0 8. st. and from state space to state space. Data Movement and Conversion Instructions These instructions copy data from place to place. prefetchu isspacep cvta cvt 108 January 24. The cvta instruction converts addresses between generic and global.

when applied to a local address. . .ca. but multiple L1 caches are not coherent for global data.0 introduces optional cache operators on load and store instructions. invalidates (discards) the local L1 line following the load.cs is applied to a Local window address. . evict-first. 2010 109 . the cache operators have the following definitions and behavior.7. not L1). and a second thread loads that address via a second L1 cache with ld. The cache operators require a target architecture of sm_20 or later. likely to be accessed once.cs Cache streaming. Cache Operators PTX 2.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. . The ld.Chapter 8. As a result of this request.lu instruction performs a load cached streaming operation (ld.cs) on global addresses.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.ca loads cached in L1. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.cs. Operator . The compiler / programmer may use ld. if the line is fully covered.cv to a frame buffer DRAM address is the same as ld.1. When ld. The default load instruction cache operation is ld. it performs the ld. The ld.ca. A ld. For sm_20 and later. the second thread may get stale L1 cache data.cg Cache at global level (cache in L2 and below.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. bypassing the L1 cache. which allocates cache lines in all levels (L1 and L2) with normal eviction policy. likely to be accessed again. and cache only in the L2 cache. rather than the data stored by the first thread. Global data is coherent at the L2 level. The driver must invalidate global L1 cache lines between dependent grids of parallel threads.lu Last use. any existing cache lines that match the requested address in L1 will be evicted.5. Table 77.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.lu operation. Use ld. January 24. The ld. Instruction Set 8.cg to cache loads only globally. to allow the thread program to poll a SysMem location written by the CPU. The ld.lu load last use operation.cv Cache as volatile (consider cached system memory lines stale. If one thread stores to global memory via one L1 cache. fetch again).

wb could write-back global store data from L1.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels. rather than get the data from L2 or memory stored by the first thread. Use st. Future GPUs may have globally-coherent L1 caches.wt store write-through operation applied to a global System Memory address writes through the L2 cache.cg to cache global store data only globally.wt Cache write-through (to system memory). bypassing its L1 cache. 2010 . bypassing the L1 cache.wt. to allow a CPU program to poll a SysMem location written by the GPU with st. The default store instruction cache operation is st. In sm_20. The st. . The driver must invalidate global L1 cache lines between dependent grids of thread arrays. .cg Cache at global level (cache in L2 and below.ca loads.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. which writes back cache lines of coherent cache levels with normal eviction policy.cg to local memory uses the L1 cache. regardless of the cache operation. Global stores bypass L1. likely to be accessed once. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data.ca. not L1). and discard any L1 lines that match. the second thread may get a hit on stale L1 cache data.PTX ISA Version 2.cs Cache streaming. Addresses not in System Memory use normal write-back.cg is the same as st. but st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. and cache only in the L2 cache. However. If one thread stores to global memory. Operator .0 Table 78. in which case st. 110 January 24. st. and a second thread in a different SM later loads from that address via a different L1 cache with ld.wb. The st. .wb for global data. and marks local L1 lines evict-first.

k.type = { .shared state spaces. and .Chapter 8.u32. Take the non-generic address of a variable in global.u32 d. Description . // get address of variable // get address of label or function . i. within the variable’s declared state space Notes Although only predicate and bit-size types are required. variable in an addressable memory space. For variables declared in . local. mov.f32 mov.f32. myFunc. . addr.f64 }.f64 requires sm_13 or later.local.1. u.const.b64. d = sreg. A. label. ptr. PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. 2010 111 . sreg. alternately. d. .type mov.u16 mov. a.global. . d = &avar.type mov. label. . . immediate. . d.0. local. // address is non-generic. mov.v.s16.u64.u32 mov.e. the generic address of a variable declared in global. .b32. or shared state space may be taken directly using the cvta instruction. Instruction Set Table 79.b16. or function name. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking.a.. the parameter will be copied onto the stack and the address will be in the local state space.f32 mov. mov places the non-generic address of the variable (i..s64. avar. . special register. . Introduced in PTX ISA version 1. d = &label. Semantics d = a. Operand a may be a register.u16.u32 mov. . . . A[5]. ptr.type mov. or shared state space. d.type d.e.s32. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. The generic address of a variable in global. Note that if the address of a device function parameter is moved to a register.0.pred. the address of the variable in its state space) into the destination register. mov. Write register d with the value of a. local.

z << 16) | (a.y << 16) | (a.w } = { a[0. lo.g. %r1.b64 }.type d. Description Write scalar register d with the packed value of vector register a. d.. {lo. For bit-size types.31]. a[16. or write vector register d with the unpacked values from scalar register a.w << 24) d = a. a[16.b64 112 January 24.x | (a.x | (a.b64 mov. .b32 mov.b32 mov.w << 48) d = a.y. d.g.b32 // pack four 16-bit elements into .63] } // unpack 16-bit elements from .x. {r.y.z. d.7].b}.u16 %x is a double. Semantics d = a.b have type . mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector.hi are . a[8.b32 %r1.x.b16 // pack four 8-bit elements into .%r1.x. d.x..y.a}..23]. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).u8 // unpack 32-bit elements from .0.x | (a.u32 x..y } = { a[0..b32 // pack two 16-bit elements into .0 Table 80.. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.{x. . .PTX ISA Version 2.. a[24. %x. mov..w } = { a[0.31] } // unpack 16-bit elements from .z. Supported on all target architectures.b64 { d. // // // // a. a[8.b8 r.b16.type = { . a[32.{a.y << 16) d = a.z. d.15] } // unpack 8-bit elements from ..b16 { d. a. d.b32 { d.w}..a have type . d.z << 32) | (a.y } = { a[0.b64 { d. d.47]. a[32.y << 32) // pack two 8-bit elements into .15].hi}.15]. d.b32.x | (a..7].y. a[16.b.y << 8) | (a.z.b64 // pack two 32-bit elements into . a[48.. mov.b.w have type .63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.15]..x | (a.. 2010 .31].b32 { d.y << 8) d = a.31] } // unpack 8-bit elements from .x.y } = { a[0.

s32. .cs. [a]. The .ca. Within these windows.ss = { . .shared spaces to inhibit optimization of references to volatile memory. If an address is not properly aligned.ss}{.type ld{. ld introduced in PTX ISA version 1.Chapter 8. .vec. . .b64. .const space suffix may have an optional bank number to indicate constant banks other than bank zero.ss}. If no state space is given. an address maps to the corresponding location in local or shared memory.u16.volatile. ld{.local. the resulting behavior is undefined.volatile.v2.u8. and then converted to .f32 or . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. [a].cv }. 32-bit). d. .1..s64. . . an integer or bit-size type register reg containing a byte address. Generic addressing may be used with ld. .0. .type ld.f64 using cvt. . ld. .global and .vec. perform the load using generic addressing. d.cop}. .volatile may be used with . ld. to enforce sequential consistency between threads accessing shared memory. *(immAddr).global. or the instruction may fault. A destination register wider than the specified type may be used. for example. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b16. .volatile{. Description Load register variable d from the location specified by the source address operand a in specified state space. and is zeroextended to the destination register width for unsigned and bit-size types.shared }. This may be used.type = { . . . [a]. . . and truncated if the register width exceeds the state space address width for the target architecture. *a.s16. or [immAddr] an immediate absolute byte address (unsigned.v4 }.u32.cop}. i. In generic addressing. 32-bit). . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable.e.f16 data may be loaded using ld. *(a+immOff). The value loaded is sign-extended to the destination register width for signed integers.type d. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.f64 }. .const. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .param.ss}.reg state space. PTX ISA Notes January 24. The address size may be either 32-bit or 64-bit.volatile introduced in PTX ISA version 1. the access may proceed by silently masking off low-order address bits to achieve proper rounding. d. Instruction Set Table 81. [a]. . .b16.u64. 2010 113 . .type . Cache operations are not permitted with ld.s8.cop = { . i.b32.ss}{. .cg. Generic addressing and cache operations introduced in PTX ISA 2.vec = { . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.e. Semantics d d d d = = = = a.lu. .f32. an address maps to global memory unless it falls within the local memory window or the shared memory window. The address must be naturally aligned to a multiple of the access size.volatile{.b8.0. Addresses are zero-extended to the specified width as needed.

[p]. // load .PTX ISA Version 2. x. ld.b32 ld.[p+4].f64 requires sm_13 or later.b32 ld. d.[buffer+64].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.global. 2010 .f32 ld.[a].[p+-8]. %r.b64 ld.v4.b16 cvt. Cache operations require sm_20 or later.local.b32 ld. Q.f16 d.const.const[4].s32 ld.shared.[240].f32.0 Target ISA Notes ld. // immediate address %r. // access incomplete array x.[fs].global.local. Generic addressing requires sm_20 or later. // negative offset %r.%r.

Chapter 8.[a]. where the address is guaranteed to be the same across all threads in the warp. and truncated if the register width exceeds the state space address width for the target architecture. The value loaded is sign-extended to the destination register width for signed integers. // load from address // vec load from address .e. .v4. . the resulting behavior is undefined. i.f64 requires sm_13 or later.b16.[p+4].f64 }.f32.global. . Semantics d d d d = = = = a. 2010 115 . .global }. an address maps to the corresponding location in local or shared memory. ldu.v4 }. . or the instruction may fault.u64. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.b32 d.e. . 32-bit).f32 d. *(immAddr). the access may proceed by silently masking off low-order address bits to achieve proper rounding. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. PTX ISA Notes Target ISA Notes Examples January 24. ldu. A destination register wider than the specified type may be used.ss}. *a. and is zeroextended to the destination register width for unsigned and bit-size types. The addressable operand a is one of: [avar] the name of an addressable variable var.b16. ldu{. Within these windows. an address maps to global memory unless it falls within the local memory window or the shared memory window.b32.s64. .v2. .vec = { . A register containing an address may be declared as a bit-size type or integer type.type ldu{.ss = { .vec. ldu. .f32 Q. d.global.0. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.type d.b8.f16 data may be loaded using ldu. only generic addresses that map to global memory are legal. perform the load using generic addressing.reg state space. In generic addressing. Instruction Set Table 82.s16..u32. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp.ss}. [a].b64.f32 or . The address size may be either 32-bit or 64-bit. [areg] a register reg containing a byte address.type = { . The address must be naturally aligned to a multiple of the access size. i. . and then converted to . Introduced in PTX ISA version 2. .global. [a]. If no state space is given.u16. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .u8. . *(a+immOff).[p]. // state space . ldu.f64 using cvt. If an address is not properly aligned. .s32. Addresses are zero-extended to the specified width as needed. 32-bit).s8. . For ldu. The data at the specified address must be read-only. or [immAddr] an immediate absolute byte address (unsigned.

ss}. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.type = = = = {. Addresses are zero-extended to the specified width as needed.f16 data resulting from a cvt instruction may be stored using st. the access may proceed by silently masking off low-order address bits to achieve proper rounding.0.type .u64.cs. [a]. Semantics d = a.vec. .v2. .b16. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. st. { . i. an address maps to global memory unless it falls within the local memory window or the shared memory window.PTX ISA Version 2. . { . i.s64.0 Table 83. . st. st.1. the resulting behavior is undefined. . . The lower n bits corresponding to the instruction-type width are stored to memory. . to enforce sequential consistency between threads accessing shared memory. . Generic addressing requires sm_20 or later. PTX ISA Notes Target ISA Notes 116 January 24.reg state space.volatile{. *(immAddr) = a. b. .shared spaces to inhibit optimization of references to volatile memory. or the instruction may fault. b.b16. [a].u8.ss}. Within these windows.cop}.global. or [immAddr] an immediate absolute byte address (unsigned. . b.cop}.b32. The address must be naturally aligned to a multiple of the access size.volatile. [a]. and truncated if the register width exceeds the state space address width for the target architecture.0.f32. If an address is not properly aligned.u16.f64 requires sm_13 or later.. . perform the store using generic addressing.s8.wt }. 32-bit).ss}{.local.volatile may be used with . Cache operations require sm_20 or later.b8. A source register wider than the specified type may be used. { .global and . Cache operations are not permitted with st.type [a].cop . for example. If no state space is given. *(d+immOffset) = a. Generic addressing may be used with st.s32. . . .vec. .ss .volatile. st{.type st{. an integer or bit-size type register reg containing a byte address.shared }. . 32-bit). The address size may be either 32-bit or 64-bit. .b64. .u32.cg. .ss}{. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.v4 }. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .s16. In generic addressing. an address maps to the corresponding location in local or shared memory.vec . *d = a.wb. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.type st.e. Generic addressing and cache operations introduced in PTX ISA 2. st introduced in PTX ISA version 1.e.volatile{. b.volatile introduced in PTX ISA version 1. .f64 }. 2010 . This may be used.

b32 st. 2010 117 .global.Q.Chapter 8.b16 [a].b32 st.local.%r. Instruction Set Examples st.a. // immediate address %r. [q+4].local.global. [p].local. [q+-8].v4. // negative offset [100].%r.s32 cvt.f32 st. // %r is 32-bit register // store lower 16 bits January 24.s32 st.r7.f16.a.f32 st. [fs].b.

prefetchu Prefetch line containing generic address at specified level of memory hierarchy.level prefetchu.e. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. an address maps to the corresponding location in local or shared memory. 118 January 24. prefetch and prefetchu require sm_20 or later.global.L1 [a]. Within these windows. a register reg containing a byte address. and truncated if the register width exceeds the state space address width for the target architecture. The address size may be either 32-bit or 64-bit. and no operation occurs if the address maps to a local or shared memory location.L2 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetch{. In generic addressing. 32-bit). .PTX ISA Version 2.space}.L1 [ptr]. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. i.L1. in specified state space. [a]. Addresses are zero-extended to the specified width as needed. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. . 32-bit). A prefetch to a shared memory location performs no operation. or [immAddr] an immediate absolute byte address (unsigned.space = { . the prefetch uses generic addressing.global. 2010 . prefetchu.0 Table 84.local }. A prefetch into the uniform cache requires a generic address. prefetch. an address maps to global memory unless it falls within the local memory window or the shared memory window. // prefetch to data cache // prefetch to uniform cache .0.level = { .L1 [addr]. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. If no state space is given.

u64.to.size cvta. cvta. cvta.shared isglbl.u32. // result is .u32 to truncate or zero-extend addresses. the generic address of the variable may be taken using cvta. // local. Description Convert a global. local. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Introduced in PTX ISA version 2. isshrd.space. .local isspacep.to. The destination register must be of type . Instruction Set Table 85. or vice-versa. local.local. a. PTX ISA Notes Target ISA Notes Examples Table 86. or shared address. When converting a generic address into a global. The source and destination addresses must be the same size. For variables declared in global.global.0. // get generic address of svar cvta.u64 or cvt.u32 p.u32 gptr.space p.u64 }. cvta. a.global. local. lptr.size .space. isspacep requires sm_20 or later. .genptr. var.shared }. Use cvt. islcl. The source address operand must be a register of type . or vice-versa. . a.u32 or . isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. sptr.local. local.u64. or shared address to a generic address. isspacep. // convert to generic address // get generic address of var // convert generic address to global.shared.u32 p. cvta requires sm_20 or later. isspacep. p.pred . January 24. or shared address cvta. svar. . Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. .space = { . Take the generic address of a variable declared in global. or shared state space to generic. 2010 119 . or shared state space.0. . p. local.local.global isspacep.u32. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.size p.space = { .space. A program may use isspacep to guard against such incorrect behavior. or shared state space.global.shared }. gptr.lptr.Chapter 8.pred.size = { .

atype cvt{. i.u64. a. Note that saturation applies to both signed and unsigned integer types. and for same-size float-tofloat conversions where the value is rounded to an integer.e.PTX ISA Version 2.irnd = { . . .u32. The compiler will preserve this behavior for legacy PTX code.u16. . Integer rounding modifiers: .ftz.s32. Description Semantics Integer Notes Convert between different types and sizes. 2010 .. .. a.rni.s64. .rpi }.ftz.sat}. the . choosing even integer if source is equidistant between two integers.sat}. Note: In PTX ISA versions 1. The optional .dtype = .0 Table 87.ftz.ftz}{. i.f32 float-to-integer conversions and cvt.dtype. . .atype = { .rzi round to nearest integer in the direction of zero . The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. Integer rounding is illegal in all other instances.s16.4 and earlier.f16. . . Saturation modifier: .sat limits the result to MININT.rzi. .ftz modifier may be specified in these cases for clarity.s8.irnd}{. . the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. . subnormal numbers are supported. cvt{. subnormal inputs are flushed to signpreserving zero.sat is redundant. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.f32.rz.f32 float-to-integer conversions and cvt. d. d = convert(a). . .frnd = { . . subnormal inputs are flushed to signpreserving zero. .rm.sat modifier is illegal in cases where saturation is not possible based on the source and destination types.sat For integer destination types. For float-to-integer conversions. . sm_1x: For cvt.f32 float-tofloat conversions with integer rounding. .dtype.rp }. For cvt. .rmi.rn.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.ftz.dtype.f32. . .e.frnd}{.u8. 120 January 24.f32.ftz}{.rni round to nearest integer.rmi round to nearest integer in direction of negative infinity .atype d.f64 }. // integer rounding // fp rounding .MAXINT for the size of the operation.dtype.f32 float-tofloat conversions with integer rounding. the result is clamped to the destination range by default. Integer rounding is required for float-to-integer conversions.

1.rz mantissa LSB rounds towards zero . and for integer-to-float conversions.f32. cvt to or from .ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. The result is an integral value. Specifically.version is 1. 2010 121 .sat For floating-point destination types. if the PTX . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.0].s32 f. Note: In PTX ISA versions 1. and cvt.f32 instructions. Introduced in PTX ISA version 1. The compiler will preserve this behavior for legacy PTX code. cvt. Saturation modifier: . // round to nearest int. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).rm mantissa LSB rounds towards negative infinity .f32. Modifier . subnormal numbers are supported.0. .f32.y.Chapter 8. .f64 j. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero.4 or earlier. The operands must be of the same size.f32. Floating-point rounding is illegal in all other instances.0. stored in floating-point format. cvt.f32.4 and earlier.rni.s32.f16.sat limits the result to the range [0.f16. Applies to . Subnormal numbers: sm_20: By default.i.f32.f64 types. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f32 x.ftz behavior for sm_1x targets January 24. NaN results are flushed to positive zero. // note . // float-to-int saturates by default cvt.f64. cvt. and .r. Floating-point rounding modifiers: .f64 requires sm_13 or later.y. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.ftz modifier may be specified in these cases for clarity. result is fp cvt.f32.f16. The optional .f32 x.rn mantissa LSB rounds to nearest even .

PTX has two modes of operation.target texmode_independent .entry compute_power ( . and surface descriptors. 2010 . add. In the unified mode.f2}].f32. the file is assumed to use unified mode. r5.global . . add.6. r3.b32 r6. add. Ability to query fields within texture. r5..0 8.width.r3. In the independent mode. [tex1]. . Example: calculate an element’s power contribution as element’s power/total number of elements.target options ‘texmode_unified’ and ‘texmode_independent’. div. sampler. sampler. r5. r1. and surface descriptors. {f1. If no texturing mode is declared. Module-scope and per-entry scope definitions of texture.r2.f32 r1. r2. but the number of samplers is greatly restricted to 16. // get tex1’s txq.2d.7. allowing them to be defined separately and combined at the site of usage in the program. texture and sampler information is accessed through a single . A PTX module may declare only one texturing mode. r3. . The texturing mode is selected using . r4.. and surface descriptors. mul. and surface descriptors: • • • Static initialization of texture. samplers. sampler.f32 {r1.param . PTX supports the following operations on texture. [tex1.height.f32 r1.v4. 122 January 24.samplerref tsamp1 = { addr_mode_0 filter_mode }.PTX ISA Version 2. [tex1].u32 r5.texref tex1 ) { txq.texref handle. texture and sampler information each have their own handle.r4}. = nearest width height tsamp1. } = clamp_to_border. r1.f32. The advantage of unified mode is that it allows 128 samplers. The advantage of independent mode is that textures and samplers can be mixed and matched. cvt. r6. // get tex1’s tex. Texturing modes For working with textures and samplers. and surfaces. Texture and Surface Instructions This section describes PTX instructions for accessing textures.u32 r5. r1.b32 r5.f32 r3. with the restriction that they correspond 1-to-1 with the 128 possible textures. sampler.f32 r1.

dtype. c]. tex txq suld sust sured suq Table 88. [tex_a. [tex_a.v4. b.5. tex. where the fourth element is ignored.dtype. . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. i. .geom.3d }.r4}.Chapter 8. // Example of independent mode texturing tex. [a. . with the extra elements being ignored. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. Unified mode texturing introduced in PTX ISA version 1. . [a.s32 {r1. Operand c is a scalar or singleton tuple for 1d textures.s32.s32.f3. the resulting behavior is undefined.v4. Notes For compatibility with prior versions of PTX.f32 }. //Example of unified mode texturing tex. . and is a four-element vector for 3d textures.u32. .btype d. d.3d.r4}. A texture base address is assumed to be aligned to a 16-byte address.v4. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.f2.0. An optional texture sampler b may be specified. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.geom = { .1d. the sampler behavior is a property of the named texture. The instruction always returns a four-element vector of 32-bit values.f32 }.btype = { .f32 {r1. {f1. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.1d.r3. sampler_x. Supported on all target architectures. PTX ISA Notes Target ISA Notes Examples January 24. Description Texture lookup using a texture coordinate vector.s32. or the instruction may fault.geom. If an address is not properly aligned.dtype = { .e. is a two-element vector for 2d textures.2d. the square brackets are not required and . 2010 123 .v4 coordinate vectors are allowed for any geometry. // explicit sampler .. {f1}]. If no sampler is specified.r3. Instruction Set These instructions provide access to texture and surface memory.r2. c].s32.btype tex.v4.f4}].r2.

linear } Integer from enum { wrap. d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.squery = { .squery. // unified mode // independent mode 124 January 24.b32 d. txq.depth . [a]. . .normalized_coords .addr_mode_0 .addr_mode_2 Returns: value in elements 1 (true) or 0 (false).5.width. addr_mode_2 }.0 Table 89.height . .tquery.depth. txq.filter_mode.tquery = { . // texture attributes // sampler attributes . Description Query an attribute of a texture or sampler. In unified mode. Operand a is a .width .filter_mode . clamp_ogl. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.texref or . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. . mirror. Integer from enum { nearest. 2010 .addr_mode_1 . clamp_to_edge.addr_mode_0. [tex_A]. [smpl_B].b32 %r1.samplerref variable.height. [tex_A]. txq.filter_mode. txq.addr_mode_0.b32 txq. addr_mode_1.width. . [a]. sampler attributes are also accessed via a texref argument. Supported on all target architectures.normalized_coords }.b32 %r1.b32 %r1. and in independent mode sampler attributes are accessed via a separate samplerref argument.PTX ISA Version 2. Query: .

r2}.v2.trap introduced in PTX ISA version 1. and cache operations introduced in PTX ISA version 2.trap clamping modifier.p .geom{.s32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.s32 is returned.z. i. suld.b32.cg. The .geom . [a.f32 based on the surface format as follows: If the surface format contains UNORM. Instruction Set Table 90.clamp .u32.vec . then . // for suld. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. .0. [a. . additional clamp modifiers.trap. [surf_A. If an address is not properly aligned. and A components of the surface format.b32. is a two-element vector for 2d surfaces.v4. and the size of the data transfer matches the size of destination operand d.b .b64 }.s32. suld.p is currently unimplemented. .f32 is returned.ca.zero }. .geom{. or . {f1. suld. .cop}.u32.3d }.u32 is returned.3d.y.v4 }.1d. Cache operations require sm_20 or later. suld.dtype .clamp suld.p requires sm_20 or later.clamp.1d.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.f2. then .v2. suld. and is a four-element vector for 3d surfaces. . or the instruction may fault.b64.b. {x. .trap . Target ISA Notes Examples January 24. A surface base address is assumed to be aligned to a 16-byte address. b]. .dtype. Description Load from surface memory using a surface coordinate vector.s32.trap suld. [surf_B. suld.p.cv }. suld Syntax Texture and Surface Instructions: suld Load from surface memory.b performs an unformatted load of binary data. . if the surface format contains UINT data. . .5.surfref variable. sm_1x targets support only the . or . the resulting behavior is undefined. // for suld.f32 }.dtype .2d.b supported on all target architectures. the surface sample elements are converted to .b8 . {x}].p.cop}.b. .clamp . suld.s32.v4. // cache operation none.b. . If the destination type is .e. where the fourth element is ignored.. If the destination base type is . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. G. .b32.vec.trap {r1. . . if the surface format contains SINT data.f4}. Operand b is a scalar or singleton tuple for 1d surfaces.dtype. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.w}].Chapter 8.p.f32.b16.clamp = = = = = = { { { { { { d. The lowest dimension coordinate represents a sample offset rather than a byte offset. Destination vector elements corresponding to components that do not appear in the surface format are not written. then . suld.cop . 2010 125 . SNORM. Coordinate elements are of type .3d requires sm_20 or later.cs. size and type conversion is performed as needed to convert from the surface sample format to the destination type.f32. or FLOAT data. // unformatted d.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. . // formatted . B. b]. suld. .clamp field specifies how to handle out-of-bounds addresses: . .u32. Operand a is a .f3.

p performs a formatted store of a vector of 32-bit data values to a surface sample.1d. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. b]. and A surface components.p Description Store to surface memory using a surface coordinate vector. . where the fourth element is ignored.3d requires sm_20 or later.f32} are currently unimplemented.v4.cs.ctype .clamp sust. sust Syntax Texture and Surface Instructions: sust Store to surface memory. additional clamp modifiers. .0. . Operand b is a scalar or singleton tuple for 1d surfaces.f3.p requires sm_20 or later.p.cop .PTX ISA Version 2.geom{.vec .v4 }. // for sust. .u32 is assumed.ctype. . .wb. {r1.b32.trap sust.geom{.b64 }. These elements are written to the corresponding surface sample components. Surface sample components that do not occur in the source vector will be written with an unpredictable value.clamp = = = = = = { { { { { { [a. sust.r2}.u32. Coordinate elements are of type . .p.f32. . sust.3d }. i.p. sust.s32.f32.clamp . . The . .s32. . {f1. then .p. size and type conversions are performed as needed between the surface sample format and the destination type.b8 . Target ISA Notes Examples 126 January 24. the resulting behavior is undefined. If an address is not properly aligned. b]. The lowest dimension coordinate represents a sample offset rather than a byte offset.f4}.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.geom . sm_1x targets support only the . .cop}.clamp . . then .2d. . The source data is then converted from this type to the surface sample format.clamp.v2. sust. G. // unformatted // formatted .b. B.trap clamping modifier..zero }.b.u32. Cache operations require sm_20 or later. SNORM.z.b performs an unformatted store of binary data. is a two-element vector for 2d surfaces.w}]. . and is a four-element vector for 3d surfaces. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b.ctype.vec.trap. .s32. sust. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The source vector elements are interpreted left-to-right as R.b supported on all target architectures. sust.surfref variable.f32 }. {x. c.0 Table 91. and cache operations introduced in PTX ISA version 2.s32.5.s32 is assumed. sust. or the instruction may fault. Operand a is a . . sust.{u32. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.e.1d. the access may proceed by silently masking off low-order address bits to achieve proper rounding.vec. A surface base address is assumed to be aligned to a 16-byte address.b64. The size of the data transfer matches the size of source operand c.b16. If the source base type is . if the surface format contains SINT data.cg.f32 is assumed. 2010 . Source elements that do not occur in the surface sample are ignored. or FLOAT data.3d. if the surface format contains UINT data.b // for sust.b32.clamp field specifies how to handle out-of-bounds addresses: . or .trap .y. [a.v2. none.b32. then .cop}. . {x}]. c. sust.f2.ctype .b.trap [surf_A. [surf_B.wt }.trap introduced in PTX ISA version 1. If the source type is . .

min.geom = { .and. The lowest dimension coordinate represents a sample offset rather than a byte offset. and the data is interpreted as .b performs an unformatted reduction on . The . .2d.c.s32 types. // for sured.b32 }. and . the access may proceed by silently masking off low-order address bits to achieve proper rounding. .p . // for sured. Coordinate elements are of type .e. [surf_B. the resulting behavior is undefined. .u32 is assumed.u64. {x}].p. January 24.3d }. or the instruction may fault. // byte addressing sured. sured. . . sured requires sm_20 or later.b].op = { . If an address is not properly aligned.trap.op. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. .s32 types.ctype = { ..clamp field specifies how to handle out-of-bounds addresses: .2d. Instruction Set Table 92.b.geom. sured.b32 type.Chapter 8.1d.ctype = { . . .u32.b32 }.u32 based on the surface sample format as follows: if the surface format contains UINT data.u64 data.u32 and . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. Operations add applies to . A surface base address is assumed to be aligned to a 16-byte address. min and max apply to .or }.u32. Operand a is a .surfref variable.s32 is assumed.min.trap [surf_A. sured.p performs a reduction on sample-addressed 32-bit data. 2010 127 .clamp . sured. . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.1d. then .add. operations and and or apply to . . r1.clamp [a.b. The instruction type is restricted to .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . r1. Operand b is a scalar or singleton tuple for 1d surfaces.s32.ctype.b]. .max. // sample addressing . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. .add.s32.s32. is a two-element vector for 2d surfaces. then . if the surface format contains SINT data.b32.trap sured.b32.b32.u32. or .ctype. .clamp = { .clamp [a. .u64.s32 or .u32.p. {x. i.op. Reduction to surface memory using a surface coordinate vector.zero }. and is a four-element vector for 3d surfaces.b .clamp.trap . .geom.y}].0. where the fourth element is ignored.c.

suq.b32 d.height.depth }.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.surfref variable.query = { . 128 January 24. suq.PTX ISA Version 2.width.b32 %r1. .0 Table 93.query. [surf_A].5. Operand a is a . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.height .width . Supported on all target architectures. .width. 2010 . [a]. Query: . Description Query an attribute of a surface. .

c.a. Execute an instruction or instruction block for threads that have the guard predicate true.f32 @q bra L23. ratio.0.Chapter 8. { instructionList } The curly braces create a group of instructions.7.eq.x.0. Introduced in PTX ISA version 1. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Supported on all target architectures. 2010 129 .s32 d. used primarily for defining a function body. Supported on all target architectures. {} Syntax Description Control Flow Instructions: { } Instruction grouping.7. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.f32 @!p div.b. p.y.s32 a. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. { add.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. } PTX ISA Notes Target ISA Notes Examples Table 95.0. If {!}p then instruction Introduced in PTX ISA version 1. Threads with a false guard predicate do nothing. Instruction Set 8. @{!}p instruction. setp. mov.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

130

January 24, 2010

Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

January 24, 2010

131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

132

January 24, 2010

In conditionally executed code. the bar. Operands a. . a{. Only bar. a. the final value is written to the destination register in all threads waiting at the barrier.and. Since barriers are executed on a per-warp basis.red should not be intermixed with bar. a{. bar. bar. Operand b specifies the number of threads participating in the barrier. b. If no thread count is specified. b}. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).and).or).u32.pred . Register operands. Thus. the optional thread count must be a multiple of the warp size.red performs a predicate reduction across the threads participating in the barrier. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.0. The barrier instructions signal the arrival of the executing threads at the named barrier. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.popc.sync with an immediate barrier number is supported for sm_1x targets. all threads in the CTA participate in the barrier. and d have type . the waiting threads are restarted without delay..red} introduced in PTX .{arrive. All threads in the warp are stalled until the barrier completes.Chapter 8.popc). p.and and . b}.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. bar.version 2.red also guarantee memory ordering among threads identical to membar.sync bar.red are population-count (. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. bar. and then safely read values stored by other threads prior to the barrier.red} require sm_20 or later. Instruction Set Table 100.red. {!}c.cta.sync and bar. {!}c. Note that a non-zero thread count is required for bar. and any-thread-true (. execute a bar.or }.red delays the executing threads (similar to bar. while . it is as if all the threads in the warp have executed the bar instruction. operands p and c are predicates. if any thread in a warp executes a bar instruction. it simply marks a thread's arrival at the barrier.u32 bar. b. The reduction operations for bar. bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.sync without a thread count introduced in PTX ISA 1. bar. In addition to signaling its arrival at the barrier. all-threads-true (.red performs a reduction operation across threads. Barriers are executed on a per-warp basis as if all the threads in a warp are active.sync) until the barrier count is met. Once the barrier count is reached.popc is the number of threads with a true predicate.0. 2010 133 .sync or bar. d.15. and bar. Register operands.arrive using the same active barrier. When a barrier completes. Description Performs barrier synchronization and communication within a CTA.arrive does not cause any waiting by the executing threads.{arrive.sync or bar. Execution in this case is unpredictable. thread count. PTX ISA Notes Target ISA Notes Examples bar. January 24. and bar.sync 0.arrive a{. thread count. The result of .red. bar.op = { . Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. bar. bar.arrive.red instruction. Each CTA instance has sixteen barriers numbered 0. Thus. threads within a CTA that wish to communicate via memory can store to memory.sync and bar. b}. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). and the barrier is reinitialized so that it can be immediately reused.op.

This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.gl.gl} introduced in PTX .0 Table 101. membar.g.{cta.gl. when the previous value can no longer be read. by st. membar. that is.sys }. For communication between threads in different CTAs or even different SMs. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. 134 January 24. this is the appropriate level of membar. . including thoses communicating via PCI-E such as system and peer-to-peer memory.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar. global. membar. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.gl} supported on all target architectures.version 1. membar. membar.0. PTX ISA Notes Target ISA Notes Examples membar. or system memory level.gl. membar.version 2. level describes the scope of other clients for which membar is an ordering event.g.cta. A memory write (e.PTX ISA Version 2. membar. . membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar.sys will typically have much longer latency than membar.4.cta Waits until all prior memory writes are visible to other threads in the same CTA.level = { . .sys Waits until all prior memory requests have been performed with respect to all clients.sys introduced in PTX .level. A memory read (e. and memory reads by this thread can no longer be affected by other thread writes.gl will typically have a longer latency than membar.sys. membar.sys requires sm_20 or later. Waits until prior memory reads have been performed with respect to other threads in the CTA.{cta. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.cta.cta. membar. 2010 .

type atom{. an address maps to global memory unless it falls within the local memory window or the shared memory window.f32.global.u32 only . b. i.add.s32.min.s32. Instruction Set Table 102.op. . In generic addressing. . .space = { . atom{. or.shared }. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. If an address is not properly aligned. min. perform the memory accesses using generic addressing. 32-bit operations. or [immAddr] an immediate absolute byte address.u64 .g. For atom. xor. The floating-point add.e. The floating-point operations are add. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.type d. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.b32.u32. . . Within these windows. The integer operations are add. [a].f32 }.max }. the access may proceed by silently masking off low-order address bits to achieve proper rounding. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. Addresses are zero-extended to the specified width as needed.s32. The address size may be either 32-bit or 64-bit. A register containing an address may be declared as a bit-size type or integer type.b]. and max operations are single-precision..space}. min. accesses to local memory are illegal.f32 Atomically loads the original value at location a into destination register d.u32. If no state space is given. .exch.u64.inc. max. and truncated if the register width exceeds the state space address width for the target architecture. . an address maps to the corresponding location in local or shared memory. . atom. .add. . e.. c. Operand a specifies a location in the specified state space. Description // // // // // . [a].Chapter 8. The inc and dec operations return a result in the range [0. . . i.b64 . . . b.and.b32 only .b64. min.e. . . and stores the result of the specified operation at location a.xor. . 2010 135 .or.cas. The bit-size operations are and. overwriting the original value. . . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b32. .type = { . dec. or by using atom. .op = { . cas (compare-and-swap). . The address must be naturally aligned to a multiple of the access size.dec.space}.exch to store to locations accessed by other atomic operations. January 24. a de-referenced register areg containing a byte address. and exch (exchange). or the instruction may fault. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. and max. d. . by inserting barriers between normal stores and atomic operations to a common address.op. performs a reduction operation with operand b and the value in location a. the resulting behavior is undefined. inc.u32.

s) = (r > s) ? s exch(r.f32. atom.0 Semantics atomic { d = *a.PTX ISA Version 2. 64-bit atom. c) operation(*a.global.max} are unimplemented. atom.t) = (r == s) ? t operation(*a. : r+1. s) = (r >= s) ? 0 dec(r.cas.cas.shared operations require sm_20 or later. cas(r. b.[x+4].1.add.f32 atom. : r. d. : r-1.shared.max. 2010 .my_new_val.global requires sm_11 or later.[p]. *a = (operation == cas) ? : } where inc(r.s32 atom.0.global.exch} requires sm_12 or later.my_val.[a].0.{min.b32 d.shared requires sm_12 or later. Use of generic addressing requires sm_20 or later. Introduced in PTX ISA version 1. 64-bit atom.s. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space. s) = s.add. atom. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. atom. Release Notes Examples @p 136 January 24.{add. d. atom. b).f32 requires sm_20 or later.

shared }.and.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.s32. red{. . an address maps to the corresponding location in local or shared memory. In generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. max. January 24.inc.or. overwriting the original value. If no state space is given. Instruction Set Table 103. . . Semantics *a = operation(*a. min. . A register containing an address may be declared as a bit-size type or integer type. Operand a specifies a location in the specified state space. a de-referenced register areg containing a byte address. b. . . Notes Operand a must reside in either the global or shared state space. e. .u32. . i.add.type = { . where inc(r.space}.space = { . dec.s32. by inserting barriers between normal stores and reduction operations to a common address. the resulting behavior is undefined.u32. dec(r. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .f32 }. accesses to local memory are illegal.u64. The floating-point operations are add. The bit-size operations are and.op. . inc. The address size may be either 32-bit or 64-bit. .global. .e..exch to store to locations accessed by other reduction operations. or the instruction may fault. .type [a].b32. If an address is not properly aligned. and truncated if the register width exceeds the state space address width for the target architecture. . perform the memory accesses using generic addressing. Description // // // // . 2010 137 .b]. . The floating-point add.xor. . red.u32.f32 Performs a reduction operation with operand b and the value in location a.s32. The inc and dec operations return a result in the range [0. and max. or by using atom.b64. The integer operations are add. min.max }.dec. or. Within these windows. and xor.g. . and stores the result of the specified operation at location a.e.u32 only .b32 only . i.Chapter 8.min. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. Addresses are zero-extended to the specified width as needed. The address must be naturally aligned to a multiple of the access size. For red.. or [immAddr] an immediate absolute byte address. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. min. s) = (r > s) ? s : r-1.f32. an address maps to global memory unless it falls within the local memory window or the shared memory window.add. . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. .op = { .u64 . 32-bit operations. and max operations are single-precision. b). . s) = (r >= s) ? 0 : r+1. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.

64-bit red. 64-bit red.2.global.{min.my_val.global. red. 2010 . [p].shared. red.max} are unimplemented.shared operations require sm_20 or later.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Release Notes Examples @p 138 January 24.shared requires sm_12 or later. red.1.max.add requires sm_12 or later.global requires sm_11 or later red. red.0.add.and.f32.PTX ISA Version 2.add.f32 requires sm_20 or later. Use of generic addressing requires sm_20 or later.b32 [a].s32 red. [x+4].f32 red.

vote requires sm_12 or later.uni True if source predicate has the same value in all active threads in warp.mode. // get ‘ballot’ across warp January 24.any. vote.b32 p. where the bit position corresponds to the thread’s lane id. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.uni.q.b32 requires sm_20 or later. vote. The destination predicate value is the same across all threads in the warp.all. Negate the source predicate to compute . . Instruction Set Table 104.pred d. .not_all. Description Performs a reduction of the source predicate across threads in a warp. . PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.b32 d. Negate the source predicate to compute . Negating the source predicate also computes . .q.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.2.all True if source predicate is True for all active threads in warp.none.uni. returns bitmask . vote.pred vote.pred vote. {!}a. not across an entire CTA.uni }.all.ballot.any True if source predicate is True for some active thread in warp. vote. The reduction modes are: . 2010 139 .Chapter 8.p.ballot.ballot. Note that vote applies to threads in a single warp. p. In the ‘ballot’ form. r1.ballot.mode = { . // ‘ballot’ form. {!}a. vote.

a{.PTX ISA Version 2. . extract and sign.secop = { .bsel}.b1. c.dsel = .secop d.b2.s32) is specified in the instruction type.asel}.add.btype{. .asel}. a{.s32 }.dtype. The primary operation is then performed to produce an .max }.7. c.h1 }. . .btype = { . b{. The type of each operand (. . .9.dtype = . Video Instructions All video instructions operate on 32-bit register operands. with optional data merge vop. 2. perform a scalar arithmetic operation to produce a signed 34-bit result. optionally clamp the result to the range of the destination type. or word values from its source operands. .bsel}. The source and destination operands are all 32-bit registers.dtype. b{.bsel = { . taking into account the subword destination size in the case of optional data merging. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. to produce signed 33-bit input values.btype{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. // 32-bit scalar operation.atype. 2010 . .bsel}. all combinations of dtype. The sign of the intermediate result depends on dtype. half-word. Using the atype/btype and asel/bsel specifiers. and btype are valid. the input values are extracted and signor zero. with optional secondary operation vop. atype.dtype.s34 intermediate result. 140 January 24.b3.sat} d.atype. The general format of video instructions is as follows: // 32-bit scalar operation.asel = .extended internally to . or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result.or zero-extend byte.atype = .0 8.btype{. 3.sat} d.u32 or .sat}. 4. . The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). b{.atype.s33 values.u32.dsel.min. . vop. a{. .b0.asel}.h0.

S32_MAX. tmp. S8_MAX.h0: return ((tmp & 0xffff) case .b1. Instruction Set . U32_MIN ).b0. Bool sign.s33 optMerge( Modifier dsel.b2. c). S32_MIN ). c). . as shown in the following pseudocode. .s33 c) { switch ( secop ) { . tmp. tmp. .min: return MIN(tmp. U8_MIN ). c). } } .b3: if ( sign ) return CLAMP( else return CLAMP( case . Bool sat. The sign of the c operand is based on dtype. U32_MAX. . c).s33 tmp. S16_MIN ).s33 optSecOp(Modifier secop.Chapter 8. . U16_MIN ).b2: return ((tmp & 0xff) << 16) case . S16_MAX.s33 optSaturate( .s33 tmp. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).h1: return ((tmp & 0xffff) << 16) case .max return MAX(tmp. default: return tmp.h0.s34 tmp. January 24. 2010 141 . .h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. switch ( dsel ) { case .b1: return ((tmp & 0xff) << 8) case . . c). . U8_MAX. Modifier dsel ) { if ( !sat ) return tmp. . .add: return tmp + c. tmp. tmp.s33 c ) switch ( dsel ) { case . . This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.b0: return ((tmp & 0xff) case . S8_MIN ). c). The lower 32-bits are then written to the destination operand. U16_MAX.b3: return ((tmp & 0xff) << 24) default: return tmp. c).

isSigned(dtype).atype. vsub. vmax Syntax Integer byte/half-word/word addition / subtraction.dtype. vmin. vadd. b{. // extract byte/half-word/word and sign.dtype .bsel}. c. with optional secondary operation vop. { . vabsdiff.s32.add r1. tmp = | ta – tb |. .sat vsub.sat vabsdiff.dtype. vabsdiff. .u32. a{. tb = partSelectSignExtend( b.u32. // 32-bit scalar operation.bsel}.dsel. vsub.PTX ISA Version 2. r2.vop . atype.h1 }.b2.min.atype = . Integer byte/half-word/word minimum / maximum.dsel . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. r2. taking into account destination type and merge operations tmp = optSaturate( tmp. bsel ).btype{. vmax vadd.h0.btype{. r1.s32.or zero-extend based on source operand type ta = partSelectSignExtend( a.h1.bsel}.b0.asel}. b{. r1. r3.h1.s32.atype. Video Instructions: vadd. r3.op2 d. tb ).sat}.s32.asel}.op2 Description = = = = { vadd. and optional secondary arithmetic operation or subword data merge. c ).s32. tmp.s32.s32.u32. vabsdiff. r3. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . r3. btype.sat} d.btype = { . r1. .add. vmax require sm_20 or later. c. // optional merge with c operand 142 January 24. vsub vabsdiff vmin. a{.asel}.b3. vadd.bsel = { . . tmp = ta – tb. r2. Perform scalar arithmetic operation with optional saturate. tb ).0.asel = . .dtype. c. a{. vsub. c. tmp = MAX( ta. asel ). tmp. dsel ).b1.h0. . .sat. . vmin. tmp = MIN( ta.btype{.s32.max }. r2. // optional secondary operation d = optMerge( dsel.b2. vmax }.s32. Semantics // saturate.b0. c ). vop. sat.sat} d. vmin.s32. Integer byte/half-word/word absolute value of difference.h0. with optional data merge vop.sat vmin.b0.0 Table 105. d = optSecondaryOp( op2. // 32-bit scalar operation. .atype. . 2010 . b{.s32 }.

u32 vshr. vshr vshl. if ( mode == .b1.u32. vshl: Shift a left by unsigned amount in b with optional saturate.u32{. vshl. r2. bsel ). // default is . vshl. January 24. vshr }.mode} d. .atype = { .clamp. b{. Video Instructions: vshl. Signed shift fills with the sign bit.bsel}.s32 }. 2010 143 . r1. a{.u32. vshr Syntax Integer byte/half-word/word left / right shift.h0. . Semantics // extract byte/half-word/word and sign.u32{.vop .dtype. with optional secondary operation vop.mode .0. taking into account destination type and merge operations tmp = optSaturate( tmp.wrap ) tb = tb & 0x1f.max }. { .sat}{.mode}. Left shift fills with zero.or zero-extend based on source operand type ta = partSelectSignExtend( a. vop.op2 d.h1.atype. c. c ).sat}{. . with optional data merge vop.op2 Description = = = = = { vshl.dsel. . d = optSecondaryOp( op2.atype. c ). switch ( vop ) { case vshl: tmp = ta << tb.asel}.min. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . case vshr: tmp = ta >> tb.dtype .mode} d. if ( mode == . . tmp. . r3. tmp.u32.dtype. and optional secondary arithmetic operation or subword data merge. asel ).bsel = { . // 32-bit scalar operation.bsel}. sat.b2. a{. isSigned(dtype). c. . vshr: Shift a right by unsigned amount in b with optional saturate. tb = partSelectSignExtend( b.u32. // 32-bit scalar operation.clamp .bsel}.sat}{.u32. . Instruction Set Table 106. .asel = . b{.wrap }.atype.asel}. dsel ).h1 }. b{.b3. .s32.Chapter 8. { .b0. unsigned shift fills with zero.u32. a{. // optional secondary operation d = optMerge( dsel. vshr require sm_20 or later. atype.dtype.clamp && tb > 32 ) tb = 32.wrap r1. r2.add. r3. } // saturate.asel}. . and optional secondary arithmetic operation or subword data merge.u32{.dsel .

shr7. 144 January 24. this result is sign-extended if the final result is signed.S32 // intermediate signed.scale} d.h0.u32.dtype = . (a*b) is negated if and only if exactly one of a or b is negated. “plus one” mode. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.dtype. {-}a{. The final result is unsigned if the intermediate result is unsigned and c is not negated.atype. vmad.shr15 }. Input c has the same sign as the intermediate result. the intermediate result is signed.sat}{. .po{.bsel}. final signed (S32 * U32) . Depending on the sign of the a and b operands. final signed (S32 * U32) + S32 // intermediate signed.0 Table 107. . final unsigned -(U32 * U32) + S32 // intermediate signed. . .S32 // intermediate signed. The source operands support optional negation with some restrictions. .btype{.h1 }.btype = { .asel}. final signed The intermediate result is optionally scaled via right-shift. b{. .U32 // intermediate unsigned.dtype. Description Calculate (a*b) + c.PTX ISA Version 2. {-}b{. final signed -(S32 * S32) + S32 // intermediate signed.b0. and the operand negates. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. otherwise.scale = { . Although PTX syntax allows separate negation of the a and b operands.b3. a{. That is.bsel}. The “plus one” mode (.bsel = { .atype = .atype. final signed -(U32 * S32) + S32 // intermediate signed. which is used in computing averages.s32 }.btype. . internally this is represented as negation of the product (a*b).sat}{. and scaling. .po mode. {-}c. PTX allows negation of either (a*b) or c. 2010 . final signed (U32 * S32) .asel}. . and zero-extended otherwise. final signed -(S32 * U32) + S32 // intermediate signed.S32 // intermediate signed. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. with optional operand negates. c. final signed (U32 * U32) .b2. // 32-bit scalar operation vmad.po) computes (a*b) + c + 1..b1.scale} d. final signed (S32 * S32) . .asel = . final signed (U32 * S32) + S32 // intermediate signed. final signed (S32 * S32) + S32 // intermediate signed. Source operands may not be negated in . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.

negate) || c.po ) { lsb = 1. r1.0.negate. U32_MIN). switch( scale ) { case .negate ) { c = ~c. January 24. } if ( .shr7: result = (tmp >> 7) & 0xffffffffffffffff. signedFinal = isSigned(atype) || isSigned(btype) || (a. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). -r3. r0.negate ^ b. if ( . S32_MIN). tmp = tmp + c128 + lsb. U32_MAX. r2. asel ). else result = CLAMP(result. r1.h0. } else if ( c. tb = partSelectSignExtend( b.u32. lsb = 1. vmad. 2010 145 . btype.u32. Instruction Set Semantics // extract byte/half-word/word and sign.s32. atype.sat ) { if (signedFinal) result = CLAMP(result.shr15: result = (tmp >> 15) & 0xffffffffffffffff. lsb = 1.negate ^ b. lsb = 0.sat vmad. vmad requires sm_20 or later. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bsel ).u32. case .h0. r2.Chapter 8.s32. tmp[127:0] = ta * tb. S32_MAX.u32.shr15 r0.or zero-extend based on source operand type ta = partSelectSignExtend( a. r3.negate ) { tmp = ~tmp. } else if ( a.

s32.h0.cmp .btype.btype.s32 }.cmp d. vset requires sm_20 or later.u32.lt.dsel .le. r1. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.bsel}. r2.btype.u32. { .cmp. // 32-bit scalar operation.h1 }.min. and therefore the c operand and final result are also unsigned. . tb = partSelectSignExtend( b. cmp ) ? 1 : 0. . Semantics // extract byte/half-word/word and sign.bsel}. bsel ). a{. d = optSecondaryOp( op2.atype. atype.b1. r3. The intermediate result of the comparison is always unsigned. a{. tmp. .dsel. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.op2 Description = = = = . with optional secondary operation vset.ne r1.btype = { . vset. . . r2. c ). { .asel = .op2 d.u32.cmp d. .h1.b2.ne.add.or zero-extend based on source operand type ta = partSelectSignExtend( a. tb. .atype. c.0. 146 January 24.bsel = { . Compare input values using specified comparison. c.ge }. 2010 .asel}. b{. asel ). c ).u32. b{. // 32-bit scalar operation. .atype. tmp. tmp = compare( ta. with optional secondary arithmetic operation or subword data merge.eq. . .lt vset.max }. . a{.PTX ISA Version 2. . .b0.asel}.atype .gt.0 Table 108. . with optional data merge vset.b3. vset. b{. . r3. // optional secondary operation d = optMerge( dsel.asel}.bsel}. btype.

@p pmevent 1. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. 2010 147 . numbered 0 through 15. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109.10. Table 111. Introduced in PTX ISA version 1.Chapter 8. Supported on all target architectures. brkpt requires sm_11 or later. pmevent a. Supported on all target architectures. Notes PTX ISA Notes Target ISA Notes Examples Currently. there are sixteen performance monitor events. January 24. trap Abort execution and generate an interrupt to the host CPU. trap. The relationship between events and counters is programmed via API calls from the host. Instruction Set 8. brkpt. with index specified by immediate operand a. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. Table 110. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. brkpt.0.4.7.0. brkpt Suspends execution Introduced in PTX ISA version 1. pmevent 7. Introduced in PTX ISA version 1. trap. Triggers one of a fixed number of performance monitor events.

PTX ISA Version 2.0 148 January 24. 2010 .

which are visible as special registers and accessed through mov or cvt instructions. …. %pm3 January 24. read-only variables. 2010 149 .Chapter 9. Special Registers PTX includes a number of predefined. %lanemask_gt %clock. %lanemask_ge. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %clock64 %pm0. %lanemask_le. %lanemask_lt.

u32 %r1. // thread id vector // thread id components A predefined.x.u32 %ntid.x.z.z == 1 in 2D CTAs.z.%ntid. 2010 . mov. The %tid special register contains a 1D. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.u16 %rh. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.sreg .x 0 <= %tid. .0.v4.x code Target ISA Notes Examples 150 January 24. read-only.v4 .%tid. PTX ISA Notes Introduced in PTX ISA version 1.y.u32 %r0.v4 . %tid component values range from 0 through %ntid–1 in each CTA dimension. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported.%h2.u32 %r0.sreg . Every thread in the CTA has a unique %tid.u32 %tid.0. // legacy PTX 1. Redefined as .x * %ntid. The total number of threads in a CTA is (%ntid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.x to %rh Target ISA Notes Examples // legacy PTX 1.x.y * %ntid. %tid.0 Table 112.v4. mad.z == 0 in 2D CTAs. %tid. // move tid.u32 type in PTX 2. .u32 %h1. read-only special register initialized with the number of thread ids in each CTA dimension.z PTX ISA Notes Introduced in PTX ISA version 1. Redefined as .%tid. %ntid. 2D.x.y 0 <= %tid. .z to %r2 Table 113. The fourth element is unused and always returns zero. // CTA shape vector // CTA dimensions A predefined. %ntid. mov.sreg .0.u32 %tid. CTA dimensions are non-zero.x < %ntid.y == %tid.z. It is guaranteed that: 0 <= %tid.%ntid.%tid. Supported on all target architectures.z == 0 in 1D CTAs.u16 %rh.x code accessing 16-bit component of %tid mov. mov. The number of threads in each dimension are specified by the predefined special register %ntid.%tid.u32. %ntid.y < %ntid.z == 1 in 1D CTAs. %tid.%h1. or 3D vector to match the CTA shape. the fourth element is unused and always returns zero.%r0.PTX ISA Version 2.u32 type in PTX 2. cvt. %ntid.x. Supported on all target architectures. // compute unified thread id for 2D CTA mov.x. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA. mov.z).y.y.u16 %r2.u32 %ntid. the %tid value in unused dimensions is 0.%tid.u32 %h2. %tid.x. // zero-extend tid.sreg .0.y == %ntid. .z < %ntid. per-thread special register initialized with the thread identifier within the CTA.

.3. Note that %warpid is volatile and returns the location of a thread at the moment when read. Introduced in PTX ISA version 2. January 24. Introduced in PTX ISA version 1. mov.u32 %laneid. read-only special register that returns the maximum number of warp identifiers.Chapter 9. A predefined. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. due to rescheduling of threads following preemption.sreg . The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. but its value may change during execution. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.u32 %r.u32 %warpid. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. A predefined. Supported on all target architectures. For this reason. %nwarpid. . mov. %laneid. PTX ISA Notes Target ISA Notes Examples Table 116. A predefined. The lane identifier ranges from zero to WARP_SZ-1. %nwarpid requires sm_20 or later.sreg . Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. e.0. read-only special register that returns the thread’s lane within the warp. .g. Table 115. The warp identifier will be the same for all threads within a single warp.3. Special Registers Table 114. Introduced in PTX ISA version 1.u32 %r.u32 %r. %warpid. read-only special register that returns the thread’s warp identifier.sreg . 2010 151 . Supported on all target architectures. mov.u32 %nwarpid. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.

or 3D vector.sreg . Redefined as .v4.x. mov.u16 %r0. The %ctaid special register contains a 1D.u32 mov. // CTA id vector // CTA id components A predefined. . with each element having a value of at least 1. It is guaranteed that: 1 <= %nctaid.0.x.u32 mov.v4 .x code Target ISA Notes Examples 152 January 24.x code Target ISA Notes Examples Table 118.%ctaid. // Grid shape vector // Grid dimensions A predefined.%nctaid.sreg . 2010 .y. %rh.0 Table 117.PTX ISA Version 2.%nctaid.x. Supported on all target architectures.%ctaid. %ctaid.z} < 65. 2D. %ctaid.u32 type in PTX 2.u32 %nctaid. mov. Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.y < %nctaid.y 0 <= %ctaid. Supported on all target architectures. Each vector element value is >= 0 and < 65535.z.%nctaid.z.0.u32 type in PTX 2.u32 %ctaid.0.%nctaid. %rh.u32 %ctaid.0.x 0 <= %ctaid.536 PTX ISA Notes Introduced in PTX ISA version 1. read-only special register initialized with the CTA identifier within the CTA grid.y. // legacy PTX 1. . read-only special register initialized with the number of CTAs in each grid dimension.sreg . The %nctaid special register contains a 3D grid shape vector.u32 %nctaid .x.u16 %r0.y.{x.z PTX ISA Notes Introduced in PTX ISA version 1. .z < %nctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported. depending on the shape and rank of the CTA grid.y.v4. // legacy PTX 1. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. It is guaranteed that: 0 <= %ctaid. Redefined as . The fourth element is unused and always returns zero.v4 .x. The fourth element is unused and always returns zero.x < %nctaid. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.sreg .

Introduced in PTX ISA version 2. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. Introduced in PTX ISA version 1. Notes PTX ISA Notes Target ISA Notes Examples Table 120. e.3. read-only special register initialized with the per-grid temporal grid identifier.u32 %r. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. The SM identifier numbering is not guaranteed to be contiguous. %gridid. read-only special register that returns the maximum number of SM identifiers. The SM identifier numbering is not guaranteed to be contiguous.u32 %r. where each launch starts a grid-of-CTAs. Supported on all target architectures.Chapter 9. %nsmid. Special Registers Table 119. 2010 153 . mov. PTX ISA Notes Target ISA Notes Examples January 24.u32 %gridid.sreg . . During execution. mov. Special Registers: %smid %smid Syntax (predefined) Description SM identifier. repeated launches of programs may occur. %nsmid requires sm_20 or later.sreg . so %nsmid may be larger than the physical number of SMs in the device. A predefined. The SM identifier ranges from 0 to %nsmid-1.0.u32 %smid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. This variable provides the temporal grid launch number for this context. but its value may change during execution.u32 %nsmid. // initialized at grid launch A predefined. Introduced in PTX ISA version 1. due to rescheduling of threads following preemption.sreg .u32 %r.g. . %smid. Supported on all target architectures. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. mov.0. Note that %smid is volatile and returns the location of a thread at the moment when read. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. . PTX ISA Notes Target ISA Notes Examples Table 121. A predefined.

mov. .u32 %lanemask_le. A predefined. . %lanemask_lt. Introduced in PTX ISA version 2.0 Table 122. Introduced in PTX ISA version 2. 154 January 24. mov.0. A predefined.sreg . %lanemask_eq. %lanemask_lt requires sm_20 or later. Introduced in PTX ISA version 2. Table 124. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp.u32 %r.sreg .0. Table 123.0. %lanemask_le requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later.sreg .PTX ISA Version 2.u32 %r. .u32 %r. A predefined.u32 %lanemask_lt. 2010 . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. %lanemask_le. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %lanemask_eq. mov.

%lanemask_gt. Table 126.0. %lanemask_ge. 2010 155 . Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp.sreg . .u32 %r. %lanemask_gt requires sm_20 or later. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers Table 125.u32 %lanemask_ge.u32 %r. A predefined. Introduced in PTX ISA version 2. %lanemask_ge requires sm_20 or later. .sreg . January 24. mov.0. Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.u32 %lanemask_gt. A predefined.Chapter 9. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. mov.

0 Table 127. %pm2. Special Registers: %pm0.u64 %clock64. %pm1. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters.%clock. The lower 32-bits of %clock64 are identical to %clock. Table 128. %pm1.%clock64.3. and %pm3 are unsigned 32-bit read-only performance monitor counters. Their behavior is currently undefined.u64 r1.u32 %pm0. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.PTX ISA Version 2.u32 r1. mov. . %clock64 requires sm_20 or later.%pm0. Supported on all target architectures. %pm2.sreg . …. 2010 . Special registers %pm0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. Introduced in PTX ISA version 1.sreg . %pm2.sreg . read-only 32-bit unsigned cycle counter. mov. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. %pm1. read-only 64-bit unsigned cycle counter. Supported on all target architectures. Introduced in PTX ISA version 2. 156 January 24. Introduced in PTX ISA version 1. %pm3 %pm0.0. . %pm3.0. mov. Table 129. .u32 r1.u32 %clock.

version 2.target Table 130. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.version Syntax Description Semantics PTX version number. and the target architecture for which the code was generated. . minor are integers Specifies the PTX language version number.4 January 24.version .1. .version directive.0. Each ptx file must begin with a .minor // major.Chapter 10.version major. Duplicate . Directives 10. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Increments to the major number indicate incompatible changes to PTX.version . PTX File Directives: . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. 2010 157 .version directives are allowed provided they match the original .version 1. .0 . Supported on all target architectures.version directive.

Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Requires map_f64_to_f32 if any . The following table summarizes the features in PTX that vary according to target architecture. Texturing mode introduced in PTX ISA version 1. sm_12.5.red}.global. Adds {atom. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. Requires map_f64_to_f32 if any . In general. brkpt instructions. with only half being used by instructions converted from .texref descriptor.target directive specifies a single target architecture. . where each generation adds new features and retains all features of previous generations. Adds {atom.0 Table 131. 64-bit {atom. PTX File Directives: .texmode_unified .target directive containing a target architecture and optional platform options. Texturing mode: (default is .red}.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. but subsequent . Description Specifies the set of features in the target architecture for which the current ptx code was generated. texmode_independent. including expanded rounding modifiers. Adds double-precision support.f64 instructions used. A program with multiple .shared.f32. The texturing mode is specified for an entire module and cannot be changed within the module. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. vote instructions. Note that . 158 January 24.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. texmode_unified.global. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.samplerref descriptors.f64 to . Each PTX file must begin with a .texmode_unified) . PTX features are checked against the specified target architecture. texture and sampler information is referenced with independent . Requires map_f64_to_f32 if any .f64 instructions used. and an error is generated if an unsupported feature is used. immediately followed by a . generations of SM architectures follow an “onion layer” model.version directive. Therefore. A .target .f64 storage remains as 64-bits.0. sm_13.target directives can be used to change the set of target features allowed during parsing. sm_11.f64 instructions used. Disallows use of map_f64_to_f32.PTX ISA Version 2. sm_10. Target sm_20 Description Baseline feature set for sm_20 architecture. 2010 . Introduced in PTX ISA version 1. PTX code generated for a given target can be run on later generation devices.red}.texref and . map_f64_to_f32 }. Supported on all target architectures.texmode_independent texture and sampler information is bound together and accessed via a single .target Syntax Architecture and Platform target.

texmode_independent January 24.Chapter 10.target sm_13 // supports double-precision .target sm_20.target sm_10 // baseline target architecture . 2010 159 . Directives Examples .

These parameters can only be referenced by name within texture and surface load. The shape and size of the CTA executing the kernel are available in special registers.b32 %r1. [z].param { .g.samplerref.4. . PTX ISA Notes For PTX ISA version 1. and body for the kernel function.3. Supported on all target architectures.4 and later.reg . 160 January 24. parameter variables are declared in the kernel parameter list. . store.b32 %r<99>. ld. .param. Kernel and Function Directives: . . e. In addition to normal parameters. Semantics Specify the entry point for a kernel program. parameters. %nctaid.b32 y. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. and .PTX ISA Version 2. Parameters are passed via . opaque . . … } .param instructions. At kernel launch.2.param . etc.0 through 1.b32 %r3. %ntid.5 and later. For PTX ISA versions 1.param instructions.0 through 1.param.entry kernel-name kernel-body Defines a kernel entry point name.entry cta_fft .entry .0 10.param space memory and are listed within an optional parenthesized parameter list. [y]. 2010 .texref. with optional parameters. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1. ld.param.surfref variables may be passed as parameters.entry filter ( .param .b32 z ) Target ISA Notes Examples [x]. and query instructions and cannot be accessed via ld. .entry . Parameters may be referenced by name within the kernel body and loaded into registers using ld. ld. the kernel dimensions and properties are established and made available via special registers. parameter variables are declared in the kernel body.entry kernel-name ( param-list ) kernel-body .func Table 132.entry Syntax Description Kernel entry point and body.b32 %r2. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.b32 x.

result.b32 rval) foo (. Release Notes For PTX ISA version 1.Chapter 10. Parameters in . PTX 2.x code. PTX ISA 2. Parameter passing is call-by-value.0 with target sm_20 allows parameters in the .reg . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. which may use a combination of registers and stack locations to pass parameters.func .param state space.reg .param instructions in the body.func fname (param-list) function-body . } … call (fooval). Kernel and Function Directives: . and recursion is illegal. Parameters must be base types in either the register or parameter state space. . Supported on all target architectures.b32 N.2 for a description of variadic functions. and supports recursion. dbl.b32 rval. other code. A . … use N. … Description // return value in fooval January 24. Variadic functions are represented using ellipsis following the last fixed argument. there is no stack. 2010 161 . (val0.reg .func (ret-param) fname (param-list) function-body Defines a function. foo. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. The implementation of parameter passing is left to the optimizing translator.func definition with no body provides a function prototype. The parameter lists define locally-scoped variables in the function body. val1). including input and return parameters and optional function body. ret. Variadic functions are currently unimplemented. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. . mov. if any.param space are accessed using ld. Directives Table 133.func (.b32 localVar.0.f64 dbl) { .0 with target sm_20 supports at most one return value. parameters must be in the register state space. implements an ABI with stack.func Syntax Function definition. Parameters in register state space may be referenced directly within instructions in the function body.reg .param and st. .func fname function-body .

g.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA. and the .maxntid .pragma directive is supported for passing information to the PTX backend.pragma directives may appear at module (file) scope. The interpretation of .maxnreg .maxntid directive specifies the maximum number of threads in a thread block (CTA).maxnreg.entry directive and its body.0 10.maxntid and . at entry-scope. . PTX supports the following directives.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).maxntid. Note that . registers) to increase total thread count and provide a greater opportunity to hide memory latency. Currently. which pass information to the backend optimizing compiler.minnctapersm directives may be applied per-entry and must appear between an . and the strings have no semantics within the PTX virtual machine model. to throttle the resource requirements (e. the . The directive passes a list of strings to the backend. The .3. 2010 .pragma The . . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. the .maxnreg directive specifies the maximum number of registers to be allocated to a single thread. A general .minnctapersm .PTX ISA Version 2.maxnctapersm (deprecated) . These can be used. and . for example. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. 162 January 24. The directives take precedence over any module-level constraints passed to the optimizing backend. or as statements within a kernel or device function body. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.

Directives Table 134. . Supported on all target architectures.maxntid nx.entry bar .maxntid and . for example. ny . Supported on all target architectures. Performance-Tuning Directives: .3.maxntid nx. . 2010 163 . Introduced in PTX ISA version 1.Chapter 10. . The compiler guarantees that this limit will not be exceeded.entry foo .4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. ny. Exceeding any of these limits results in a runtime error or kernel launch failure. Introduced in PTX ISA version 1.entry foo . nz Declare the maximum number of threads in the thread block (CTA). or the maximum number of registers may be further constrained by . This maximum is specified by giving the maximum extent of each dimention of the 1D. Performance-Tuning Directives: .maxntid Syntax Maximum number of threads in thread block (CTA).maxnreg . The maximum number of threads is the product of the maximum extent in each dimension.maxntid 16. The actual number of registers used may be less.16.maxnreg n Declare the maximum number of registers per thread in a CTA.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid 256 . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.3. or 3D CTA. the backend may be able to compile to fewer registers. 2D.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid nx .maxctapersm.maxntid . .

. However.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm in PTX ISA version 2. Optimizations based on . Performance-Tuning Directives: . .PTX ISA Version 2.maxntid and . . Introduced in PTX ISA version 1.maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm generally need .maxntid to be specified as well. Introduced in PTX ISA version 2.maxntid 256 . .minnctapersm 4 { … } 164 January 24. Performance-Tuning Directives: .0.entry foo . Supported on all target architectures.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxntid to be specified as well. The optimizing backend compiler uses .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. additional CTAs may be mapped to a single multiprocessor.maxntid 256 .entry foo .minnctapersm generally need . 2010 .minnctapersm .maxnctapersm. For this reason.maxnctapersm (deprecated) .0 as a replacement for .maxnctapersm has been renamed to .3.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Optimizations based on .0.0 Table 136. . if the number of registers used by the backend is sufficiently lower than this bound. Supported on all target architectures. Deprecated in PTX ISA version 2.

Performance-Tuning Directives: . or statement-level directives to the PTX backend compiler.entry foo .pragma directive may occur at module-scope. Introduced in PTX ISA version 2. entry-scoped. . Pass module-scoped. The . at entry-scope. . The interpretation of .Chapter 10. 2010 165 . or at statementlevel. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma Syntax Description Pass directives to PTX backend compiler.pragma “nounroll”. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma directive strings is implementation-specific and has no impact on PTX semantics. Directives Table 138. { … } January 24.0. Supported on all target architectures.pragma .pragma “nounroll”.pragma list-of-strings .

@@DWARF dwarf-string dwarf-string may have one of the .debug_info .x code. 0x6150736f. 0x63613031. replaced by .264-1] .section . 0x00 166 January 24.debug_pubnames.file . @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .0 but is supported for legacy PTX version 1.2. 0x00. 2010 . The @@DWARF syntax is deprecated as of PTX version 2.loc The . Introduced in PTX ISA version 1.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.section directive is new in PTX ISA verison 2.4byte . 0x00.. Deprecated as of PTX 2.byte byte-list // comma-separated hexadecimal byte values .4byte 0x000006b5.4.. @progbits .0 and replaces the @@DWARF syntax. 0x00. Supported on all target architectures. 0x00000364.byte 0x00.4byte label . “”. 0x61395a5f. 0x5f736f63 .4byte int32-list // comma-separated hexadecimal integers in range [0.section .0.byte 0x2b. 0x736d6172 .section directive.232-1] . Table 139. 0x00. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .quad int64-list // comma-separated hexadecimal integers in range [0. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x00.4byte 0x6e69616d. 0x02.0 10. 0x00 .PTX ISA Version 2.

0x00.b32 0x6e69616d.. 0x63613031.0. Directives Table 140.b8 0x2b.section section_name { dwarf-lines } dwarf-lines have the following formats: .0.debug_info .loc . replaces @@DWARF syntax.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Debugging Directives: .b32 int32-list // comma-separated list of integers in range [0. Supported on all target architectures.255] . . Supported on all target architectures.file . .debug_pubnames { .b8 0x00.0. . . 0x00. 0x00000364. 0x00. Debugging Directives: .. . } 0x02. 2010 167 .section . 0x00. 0x00. Source file location.loc line_number January 24. 0x00 0x61395a5f.section . .b32 label . Source file information. 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1..b32 0x000006b5.232-1] . Supported on all target architectures.section Syntax PTX section definition. Debugging Directives: . 0x736d6172 0x00 Table 141.b8 byte-list // comma-separated list of integers in range [0.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .b64 int64-list // comma-separated list of integers in range [0. 0x5f736f63 0x6150736f.b32 .file filename Table 142.Chapter 10.264-1] .

extern .extern . .extern . Introduced in PTX ISA version 1.0. 2010 .0 10.b32 foo. // foo will be externally visible 168 January 24.extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. Linking Directives .visible .PTX ISA Version 2. // foo is defined in another module Table 144.global . .visible identifier Declares identifier to be externally visible. Introduced in PTX ISA version 1.0.global .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures.visible .6.b32 foo.visible Table 143. Supported on all target architectures.extern identifier Declares identifier to be defined externally. . . Linking Directives: . Linking Directives: .

1 CUDA 2.1 PTX ISA 1.4 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.0 January 24.0 CUDA 1.Chapter 11.5 PTX ISA 2.1 CUDA 2.0 driver r195 PTX ISA Version PTX ISA 1. Release Notes This section describes the history of change in the PTX ISA and implementation. 2010 169 .3 PTX ISA 1.3 driver r190 CUDA 3.0 CUDA 2.0.2 PTX ISA 1. The release history is as follows. The first section describes ISA and implementation changes in the current release of PTX ISA 2. CUDA Release CUDA 1.2 CUDA 2.0 PTX ISA 1.

f32.x code and sm_1x targets.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. A single-precision fused multiply-add (fma) instruction has been added.1. These are indicated by the use of a rounding modifier and require sm_20.f32 requires sm_20. Floating-Point Extensions This section describes the floating-point changes in PTX 2.1. The changes from PTX ISA 1.f32 and mad.f32 instruction also supports .sat modifiers.f32 for sm_20 targets.ftz and .0 11.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. The fma.1.PTX ISA Version 2. mad.rp rounding modifiers for sm_20 targets. and mul now support .f32 require a rounding modifier for sm_20 targets.1. Instructions testp and copysign have been added. while maximizing backward compatibility with legacy PTX 1. rcp.and double-precision div. Single. Changes in Version 2. New Features 11.0 for sm_20 targets. and sqrt with IEEE 754 compliant rounding have been added.f32 maps to fma.1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.rn. The mad. Both fma.0 11. The . • • • • • 170 January 24. fma.rm and .ftz modifier may be used to enforce backward compatibility with sm_1x. The goal is to achieve IEEE 754 compliance wherever possible.1. When code compiled for sm_1x is executed on sm_20 devices. Single-precision add. sub. The mad. 2010 .

prefetchu. A new directive. has been added. A “find leading non-sign bit” instruction. has been added. has been added. January 24. st.section.clamp modifiers. Other new features Instructions ld. has been added. bfind.ballot.1.minnctapersm to better match its behavior and usage. has been added. ldu.{and.1. ldu.red}.Chapter 11.red.2.1.u32 and bar.clamp and .maxnctapersm directive was deprecated and replaced with .1. A “count leading zeros” instruction. Instructions {atom.shared have been extended to handle 64-bit data types for sm_20 targets.popc. Instructions bar. vote.sys. A “vote ballot” instruction. The bar instruction has been extended as follows: • • • A bar.3.lt. . has been added.g. cvta. New instructions A “load uniform” instruction. and red now support generic addressing. brev.zero. for prefetching to specified level of memory hierarchy. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. has been added. prefetch. and sust. Instruction cvta for converting global. A “population count” instruction.gt} have been added. bar now supports optional thread count and register operands.arrive instruction has been added. Bit field extract and insert instructions. atom.le. local. popc.ge. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. bfe and bfi.f32 have been implemented.red. suld. Cache operations have been added to instructions ld. e. Instruction sust now supports formatted surface stores. clz. 2010 171 . The . Release Notes 11. Video instructions (includes prmt) have been added. . Instructions prefetch and prefetchu have also been added. Instructions {atom. have been added. New special registers %nsmid. A system-level membar instruction. %clock64. isspacep.add. Surface instructions support additional . %lanemask_{eq. and shared addresses to generic address and vice-versa has been added.red}.or}. 11. membar. st.b32.pred have been added. A “bit reversal” instruction.

f32. See individual instruction descriptions for details.3. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1.f32 type is unimplemented. 172 January 24.0 11. or . Support for variadic functions and alloca are unimplemented. has been fixed.f32} atom.{min.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.PTX ISA Version 2.4 or earlier.p sust.1. . 2010 . the correct number is sixteen. 11.4 and earlier.ftz (and cvt for .1. To maintain compatibility with legacy PTX code. Formatted surface store with .p. The underlying. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.max} are not implemented.2.5. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.5 and later. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.{u32. stack-based ABI is unimplemented.u32.s32. call suld.ftz for PTX ISA versions 1.s32.version is 1. Formatted surface load is unimplemented. In PTX version 1.target sm_1x. where . if . Semantic Changes and Clarifications The errata in cvt. cvt. red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. {atom. Instruction bra.red}.

{ … } // do not unroll any loop in this function . disables unrolling of0 the loop for which the current block is the loop header. . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma “nounroll”. Descriptions of . Supported only for sm_20 targets.pragma strings defined by ptxas. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. 2010 173 . Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. disables unrolling for all loops in the entry function body.0.pragma Strings This section describes the . and statement levels. Ignored for sm_1x targets. The “nounroll” pragma is allowed at module. … @p bra L1_end.Appendix A.entry foo (…) .pragma.pragma “nounroll”. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Note that in order to have the desired effect at statement level. . The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.pragma “nounroll”. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. including loops preceding the . L1_end: … } // do not unroll this loop January 24. entry-function.func bar (…) { … L1_head: . L1_body: … L1_continue: bra L1_head. Table 145.

0 174 January 24.PTX ISA Version 2. 2010 .

” NVIDIA MAKES NO WARRANTIES. MERCHANTABILITY. IMPLIED. However. AND OTHER DOCUMENTS (TOGETHER AND SEPARATELY. EXPRESSED. Other company and product names may be trademarks of the respective companies with which they are associated. Specifications mentioned in this publication are subject to change without notice. Copyright © 2010 NVIDIA Corporation. FILES. REFERENCE BOARDS. No license is granted by implication or otherwise under any patent or patent rights of NVIDIA Corporation. . AND FITNESS FOR A PARTICULAR PURPOSE. This publication supersedes and replaces all information previously supplied. NVIDIA Corporation assumes no responsibility for the consequences of use of such information or for any infringement of patents or other rights of third parties that may result from its use. LISTS. and Tesla are trademarks or registered trademarks of NVIDIA Corporation in the United States and other countries. AND EXPRESSLY DISCLAIMS ALL IMPLIED WARRANTIES OF NONINFRINGEMENT. OR OTHERWISE WITH RESPECT TO THE MATERIALS. All rights reserved. CUDA. the NVIDIA logo. DRAWINGS.Notice ALL NVIDIA DESIGN SPECIFICATIONS. Trademarks NVIDIA. DIAGNOSTICS. “MATERIALS”) ARE BEING PROVIDED “AS IS. NVIDIA Corporation products are not authorized for use as critical components in life support devices or systems without express written approval of NVIDIA Corporation. Information furnished is believed to be accurate and reliable. STATUTORY.

Sign up to vote on this title
UsefulNot useful