NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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.........0 4......... 5............4.........1...... 44 Scalar Conversions ....... State Spaces ................ 5.......4.................................. 5................ 38 Alignment ........4...............4............................................................................... Function declarations and definitions .............. 5.......................................................................1................. 37 Vectors .............................................................. 6............. 42 Addresses as Operands ..2. Chapter 6................................................................................................. and Vectors ...................................4.................................................. Sampler................................... Types..................... 5.............................................................. 6....2..2.1... Abstracting the ABI ...........2............... 39 5....................... 5................................2........ 47 Chapter 7...............3..............3......................................................... Type Conversion..1.............4..............4.......................... 49 7............ and Surface Types .............1..................................................... 6................................... 41 Source Operands........................ 37 Variable Declarations ........................... 29 Parameter State Space ...... 27 Register State Space .......... 38 Initializers ...........1.......... 5.................... 5... and Variables ...........................1................ 33 Fundamental Types .................... 6..............................5.................................1................................3..................... 43 6............................... 5...5.....5...5.................................. 34 Variables .................................................................. 6........................1......................................... 29 Local State Space . 29 Global State Space ................................................. 37 Array Declarations .......... Operand Costs ....... 46 6................................. 41 Destination Operands .......1. Operand Type Information ......................................6............. 5...... 41 Using Addresses........... 44 Rounding Modifiers .....4........................................................................................................ 6...................................3................................................................... 5...................1...................... 30 Shared State Space............................. 2010 .................2................................4........................ 33 5.....................................................................................4...........4.......... Summary of Constant Expression Evaluation Rules . 42 Arrays as Operands .............. 5...................4...6....... 28 Constant State Space .............. Texture........................................................................... 43 Vectors as Operands ................................................ 39 Parameterized Variable Names .........................1.............................................6.........5...... 49 ii January 24...5. Arrays..... 5.............. 5...... Instruction Operands........... 41 6........................................... 27 5...........................................6....................................4.............2............................................1........4... 32 Texture State Space (deprecated) ............................................. 5........ 5................................................................................. 25 Chapter 5.....3.......................................... State Spaces.................................... Types ...2...................................................................................................................... 6................................ 32 5.........7.................. 28 Special Register State Space ............................. 6....... 43 Labels and Function Names as Operands .............................................................................1.....................................................................1..................................................................8...................1.. 33 Restricted Use of Sub-Word Sizes ......................2...................PTX ISA Version 2................................ 6........4..........................................................

........................................................................................................... 172 Unimplemented Features Remaining ..........................3.................... PTX Version and Target Directives ............................................................................................................ 8..... 59 Operand Size Exceeding Instruction-Type Size ...........4........ Instructions .......... 169 11........... 8....................................... Divergence of Threads in Control Constructs ....................................... 168 Chapter 11....................... 60 8...................... 8...............................3..x ..............3..........1............8....................... 147 8.................................................5............3...... Release Notes ....1................................................................................. 62 8...... 8. 160 Performance-Tuning Directives ........7.............................4..... 57 Manipulating Predicates ....1................................................3........... 8.5...............6................................................... Changes from PTX 1............................................................................. 10..................................................6................................................................................1.............................................7..................... 104 Data Movement and Conversion Instructions ..... 2010 iii ............. 8.. 11.........7..................................1........................2........ 8........... 162 Debugging Directives ...1...............1............... Special Registers ............................................2...6............ 157 10...............................................................................................4......... 7................ 10...............1...................7.................................................................. Chapter 9............. 170 Semantic Changes and Clarifications .................................6...........7.................0 ............ 7....................... 11.... Type Information for Instructions and Operands .... 8............................ 62 Machine-Specific Semantics of 16-bit Code .....................................2............. 170 New Features ... 62 Semantics ........................... 55 8.2........... 108 Texture and Surface Instructions . 8................................ 63 Floating-Point Instructions ...................................... 157 Specifying Kernel Entry Points and Functions ....1........................................1...... 54 Chapter 8.................3...........................................7......................................................................... 63 Integer Arithmetic Instructions .....7.......... 10.............................................................. 11.................................1................ Changes in Version 2. 55 PTX Instructions ............................... 10.... 55 Predicated Execution ...................................................................1.................... 53 Alloca .4................ 8.............................. 8...2......... 172 January 24............................................7............................. 8...... 8................ 166 Linking Directives ................... 122 Control Flow Instructions .................... 129 Parallel Synchronization and Communication Instructions ....... 81 Comparison and Selection Instructions ........................................................................................................... 8...........10.................. 8................7................. 100 Logic and Shift Instructions ..................7...............9.....................................................3.......................................................7................................................... 132 Video Instructions ........... 56 Comparisons ....................... Instruction Set ...............................................7................7...............1............................................ 58 8......................... Format and Semantics of Instruction Descriptions ............ 8..... 52 Variadic functions .................................................. 140 Miscellaneous Instructions... 149 Chapter 10..........................................2...... Directives ......................

.... Descriptions of ...........................PTX ISA Version 2.0 Appendix A......... 2010 ....................pragma Strings. 173 iv January 24......

.......................................... Table 31................................... Table 21.................................................. 58 Floating-Point Comparison Operators Testing for NaN ......................... Table 14....................... 33 Opaque Type Fields in Unified Texture Mode ............... Table 29............................... and Bit-Size Types ..... 46 Cost Estimates for Accessing State-Spaces ................................................................................... 66 Integer Arithmetic Instructions: subc ..................................... Table 10........................... Table 6...................... Table 32...................... Table 30................................................................................................... Table 27...............List of Tables Table 1.................. 70 Integer Arithmetic Instructions: sad ............................................................. 46 Integer Rounding Modifiers ..... 68 Integer Arithmetic Instructions: mul24 .............................................................. 35 Opaque Type Fields in Independent Texture Mode ............................................... Table 13................................................ Table 20........ 61 Integer Arithmetic Instructions: add ....................................... Table 3................. 71 January 24............................. Table 17............ 20 Operator Precedence .............................................. Table 28...... 27 Properties of State Spaces ...................... 19 Predefined Identifiers .......... Table 25...... Table 2.............................................................................. Table 19..... Table 23...................................... 28 Fundamental Type Specifiers .......................... 25 State Spaces ....................................................................................................cc .......... 59 Relaxed Type-checking Rules for Source Operands ..... 65 Integer Arithmetic Instructions: sub........................................... Table 11................ Table 7........................ 47 Operators for Signed Integer. Table 9........................................................... 57 Floating-Point Comparison Operators Accepting NaN .......................................................................................... Table 22.............................. 65 Integer Arithmetic Instructions: addc .. Table 24..................... Table 16.................. Table 5................ 57 Floating-Point Comparison Operators ............................................................................................................ 58 Type Checking Rules .......................................................... Table 4...... 45 Floating-Point Rounding Modifiers ..... Table 18......................................................................................................... 66 Integer Arithmetic Instructions: mul ................. PTX Directives .............................. Table 12.............................. 64 Integer Arithmetic Instructions: add................... 18 Reserved Instruction Keywords ...................... Table 8........ 35 Convert Instruction Precision and Format .................. 2010 v ........................... 69 Integer Arithmetic Instructions: mad24 ... Unsigned Integer......................................................................cc .................................................. 64 Integer Arithmetic Instructions: sub .............. Table 26..................................... Table 15........................................ 23 Constant Expression Evaluation Rules ......................... 67 Integer Arithmetic Instructions: mad ................................................................................. 60 Relaxed Type-checking Rules for Destination Operands........

. 2010 ........... 90 Floating-Point Instructions: abs ............................... Table 59.......................... 82 Floating-Point Instructions: testp ....... Table 65............................... 103 Comparison and Selection Instructions: slct .......................................... Table 61............................. 103 vi January 24.......................................... Table 46............................................ 74 Integer Arithmetic Instructions: bfind ............................................................................ Table 44.......... 101 Comparison and Selection Instructions: setp ............ Table 37......... 98 Floating-Point Instructions: ex2 .......................................... Table 47............0 Table 33........................ Table 67. Table 53.......................................................................... Table 34.................. Table 62........................................ Table 40...................... 94 Floating-Point Instructions: rsqrt .................................................... 73 Integer Arithmetic Instructions: max .............................................................................................................................................................................. 78 Integer Arithmetic Instructions: prmt .............................................................. Table 69....................... 74 Integer Arithmetic Instructions: clz ..................... 72 Integer Arithmetic Instructions: min ....................................... Table 52..................................................................................................................... 102 Comparison and Selection Instructions: selp ...................................... Table 50.... Table 49........................................................................................................................................................................................................... Table 63.... Table 42.................. 79 Summary of Floating-Point Instructions .. Table 54....................................... 95 Floating-Point Instructions: sin ............. Table 48............................................................................ 97 Floating-Point Instructions: lg2 .................. 83 Floating-Point Instructions: add .......................................................... 77 Integer Arithmetic Instructions: bfi ........... 83 Floating-Point Instructions: copysign . Integer Arithmetic Instructions: div ....................................... 72 Integer Arithmetic Instructions: neg ............................................................................................ 91 Floating-Point Instructions: neg ..................... Table 55.................... 93 Floating-Point Instructions: sqrt ................................................................................................................................... 73 Integer Arithmetic Instructions: popc ................................................................................................................... 87 Floating-Point Instructions: mad ........................................ Table 68............... Table 66................................ 84 Floating-Point Instructions: sub ........................ 99 Comparison and Selection Instructions: set ...................... Table 56............... 71 Integer Arithmetic Instructions: abs .................................. 96 Floating-Point Instructions: cos .................................................................................... 85 Floating-Point Instructions: mul ...................PTX ISA Version 2............ 92 Floating-Point Instructions: rcp ................................... Table 35......................... 92 Floating-Point Instructions: max .................... 91 Floating-Point Instructions: min ................... 75 Integer Arithmetic Instructions: brev ... 88 Floating-Point Instructions: div . Table 51....................... 71 Integer Arithmetic Instructions: rem ...................... Table 45.... Table 41........................................................................ Table 38.................................................................................... Table 57................. Table 60....................... 86 Floating-Point Instructions: fma ............................. 76 Integer Arithmetic Instructions: bfe ................. Table 36................................................. Table 58....................... Table 39.............. Table 64......... Table 43...............................

................ Table 101..... Table 88........Table 70.............. 143 January 24...... 116 Data Movement and Conversion Instructions: prefetch...... vshr .. Table 97............................................................................................................... Table 91................................. Table 98............................... 106 Logic and Shift Instructions: shl ............................................................... Table 92............. Table 75...... Table 89........................ Table 106.......................... 112 Data Movement and Conversion Instructions: ld ...................................................................... vmax .......................................... 109 Cache Operators for Memory Store Instructions ..... Table 79.. Table 85............................................................... Table 93.................................... vmin.................................. Table 72............... prefetchu . 133 Parallel Synchronization and Communication Instructions: membar ................................................... 131 Parallel Synchronization and Communication Instructions: bar ................... 119 Data Movement and Conversion Instructions: cvta ................ Table 99....... Table 78........................ vabsdiff.......... 115 Data Movement and Conversion Instructions: st ..... Table 81................................................................. Table 94.. 129 Control Flow Instructions: bra ................................ Table 73........................................ vsub................ Logic and Shift Instructions: and .................................................................................. Table 95..................... Table 105....................... Table 104........................................... 107 Cache Operators for Memory Load Instructions ....................... 123 Texture and Surface Instructions: txq ........................... 106 Logic and Shift Instructions: not ......................... 139 Video Instructions: vadd........... 111 Data Movement and Conversion Instructions: mov .......................................................................... 125 Texture and Surface Instructions: sust ... Table 102................ 129 Control Flow Instructions: @ ................................................... 120 Texture and Surface Instructions: tex ......................................................................... 130 Control Flow Instructions: ret ..... 105 Logic and Shift Instructions: or .................................................... 113 Data Movement and Conversion Instructions: ldu .... 2010 vii ......................... 131 Control Flow Instructions: exit ............................................. 124 Texture and Surface Instructions: suld ..................... 130 Control Flow Instructions: call ............................. Table 80............................................................................................... Table 82.. Table 96.............. Table 71....... Table 86............ Table 77......................... Table 83................................ 128 Control Flow Instructions: { } ... 105 Logic and Shift Instructions: xor ................................................................................................................................ 142 Video Instructions: vshl............. Table 103............ 135 Parallel Synchronization and Communication Instructions: red ........... 126 Texture and Surface Instructions: sured................................. 134 Parallel Synchronization and Communication Instructions: atom .................... 127 Texture and Surface Instructions: suq ..... Table 74............................................. 137 Parallel Synchronization and Communication Instructions: vote ..................... Table 84........... 119 Data Movement and Conversion Instructions: cvt ..................................... Table 87........................ Table 76............................... Table 100............. 110 Data Movement and Conversion Instructions: mov ............................ 107 Logic and Shift Instructions: shr ........ 106 Logic and Shift Instructions: cnot ................ 118 Data Movement and Conversion Instructions: isspacep ..... Table 90......

............................maxntid ......................0 Table 107.. 152 Special Registers: %nctaid ............... Table 137................ 166 Debugging Directives: .. %pm2... Table 109.................... 163 Performance-Tuning Directives: ................................maxnreg ........................................................ Table 143....... Table 120............................................ 156 Special Registers: %clock64 .................... Table 111...................................................... 161 Performance-Tuning Directives: ................................... Table 129...... 160 Kernel and Function Directives: ................................................... 151 Special Registers: %warpid ....................target .............................loc .......entry....................................... 154 Special Registers: %lanemask_le ... Table 139...... 153 Special Registers: %gridid ......................................... 151 Special Registers: %ctaid ..................... 150 Special Registers: %laneid .............................. Table 127.. Table 132............ Table 135........................................... Table 134..... 154 Special Registers: %lanemask_ge ...................... 150 Special Registers: %ntid .........version........ 163 Performance-Tuning Directives: ........................................................................ Table 128......................maxnctapersm (deprecated) .......................................................................................... 2010 .......................................................PTX ISA Version 2..................................... 167 Debugging Directives: ............................ Table 122............................. 153 Special Registers: %nsmid .................................................................................... Table 126.......................................................... Table 114...................................................... 151 Special Registers: %nwarpid ................................... Table 119.. 144 Video Instructions: vset................ Table 130....................................... 167 Linking Directives: ..file .. 152 Special Registers: %smid ........................................................ Table 116.................................. Table 110......... Table 140............... 155 Special Registers: %lanemask_gt ................... Table 136............................. Table 141..................... Table 142........................................ Table 138........... 147 Miscellaneous Instructions: brkpt .................................. 156 Special Registers: %pm0.................................. 165 Debugging Directives: @@DWARF ......................................................................... 146 Miscellaneous Instructions: trap .............................................................................minnctapersm .......................... Table 113..... 157 PTX File Directives: ...............................................extern.......................................... Table 123......................... 164 Performance-Tuning Directives: .......... Table 117............... 147 Miscellaneous Instructions: pmevent............................. 156 PTX File Directives: ............................................... Table 118....................section .............................................. Table 131. Table 124......................... 158 Kernel and Function Directives: ........................... Video Instructions: vmad ................................................................................................. Table 115..................................... 147 Special Registers: %tid ..........func ....... %pm3 ..... 167 Debugging Directives: .................... 154 Special Registers: %lanemask_lt ............................................ Table 125................................... 164 Performance-Tuning Directives: .................................................... %pm1........................................... 168 viii January 24.................................. Table 108.. Table 112.......pragma .............................................................................. Table 121...... 155 Special Registers: %clock ............................. Table 133......................................................................... 153 Special Registers: %lanemask_eq .........

................. 2010 ix ... 168 Pragma Strings: “nounroll” ...............visible................................................................................Table 144....... 173 January 24.................................... Linking Directives: .. Table 145...........

2010 .0 x January 24.PTX ISA Version 2.

many-core processor with tremendous computational horsepower and very high memory bandwidth. In fact. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. PTX defines a virtual machine and ISA for general purpose parallel thread execution. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. Introduction This document describes PTX. Data-parallel processing maps data elements to parallel processing threads. video encoding and decoding. from general signal processing or physics simulation to computational finance or computational biology. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture. 1. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. January 24. and pattern recognition can map image blocks and pixels to parallel processing threads. which are optimized for and translated to native target-architecture instructions.2. and because it is executed on many data elements and has high arithmetic intensity. PTX programs are translated at install time to the target hardware instruction set. Many applications that process large data sets can use a data-parallel programming model to speed up the computations.Chapter 1. stereo vision.1. PTX exposes the GPU as a data-parallel computing device. there is a lower requirement for sophisticated flow control. multithreaded. image and media processing applications such as post-processing of rendered images. 1. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. the memory access latency can be hidden with calculations instead of big data caches. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. 2010 1 . the programmable GPU has evolved into a highly parallel. image scaling. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. Similarly. Because the same program is executed for each data element. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). high-definition 3D graphics.

surface. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.f32 require a rounding modifier for sm_20 targets. Legacy PTX 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. Improved Floating-Point Support A main area of change in PTX 2.f32 for sm_20 targets.rp rounding modifiers for sm_20 targets.rm and . addition of generic addressing to facilitate the use of general-purpose pointers. Facilitate hand-coding of libraries. Provide a common source-level ISA for optimizing code generators and translators. The mad.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. • • • 2 January 24. 2010 .0 is in improved support for the IEEE 754 floating-point standard. The fma.rn. The changes from PTX ISA 1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.x. performance kernels. barrier. including integer.3.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Provide a code distribution ISA for application and middleware developers.f32 and mad.f32.3.f32 maps to fma.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations.x code will continue to run on sm_1x targets as well.0 are improved support for IEEE 754 floating-point operations. mad. fma.f32 requires sm_20. sub. The main areas of change in PTX 2.0 PTX ISA Version 2. and video instructions. When code compiled for sm_1x is executed on sm_20 devices. Single-precision add.ftz and . A single-precision fused multiply-add (fma) instruction has been added.PTX ISA Version 2. reduction. and architecture tests. Most of the new features require a sm_20 target.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. Achieve performance in compiled applications comparable to native GPU performance. PTX ISA Version 2. A “flush-to-zero” (. memory.0 is a superset of PTX 1.sat modifiers. PTX 2. Instructions marked with .x features are supported on the new sm_20 target. and the introduction of many new instructions. Provide a machine-independent ISA for C/C++ and other compilers to target.f32 instruction also supports .1.ftz) modifier may be used to enforce backward compatibility with sm_1x. 1. atomic. 1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. which map PTX to specific target machines. and all PTX 1. Both fma.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. The mad. and mul now support .

prefetchu. Instructions prefetch and prefetchu have been added. and shared state spaces.. Instructions testp and copysign have been added. local. January 24. stack layout. and vice versa.3. rcp.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. and directives are introduced in PTX 2. Instruction cvta for converting global. NOTE: The current version of PTX does not implement the underlying. 2010 3 .clamp and . local. Surface instructions support additional clamp modifiers.2. for prefetching to specified level of memory hierarchy.3. prefetch. Surface Instructions • • Instruction sust now supports formatted surface stores. • Taken as a whole. cvta. A new cvta instruction has been added to convert global. and sust.0. In PTX 2. suld. stack-based ABI.4. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. New Instructions The following new instructions. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. isspacep. PTX 2. i. 1.g. st.0 closer to full compliance with the IEEE 754 standard. e. and sqrt with IEEE 754 compliant rounding have been added.3.e. Support for an Application Binary Interface Rather than expose details of a particular calling convention. Generic Addressing Another major change is the addition of generic addressing. st. ldu. and shared addresses to generic addresses. and shared addresses to generic address and vice-versa has been added. Cache operations have been added to instructions ld.Chapter 1. These are indicated by the use of a rounding modifier and require sm_20. instructions ld. special registers.0. local. these changes bring PTX 2. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. Generic addressing unifies the global.and double-precision div.3. Introduction • Single. . an address that is the same across all threads in a warp. so recursion is not yet supported. atom. and Application Binary Interface (ABI). 1. and red now support generic addressing. allowing memory instructions to access these spaces without needing to specify the state space. 1.zero.

2010 .sys.red.arrive instruction has been added. 4 January 24.b32. %lanemask_{eq.red.le.ballot.section. A bar. New special registers %nsmid. Instructions bar.add. membar.red}.PTX ISA Version 2.red}. has been added.u32 and bar.{and. bfi bit field extract and insert popc clz Atomic.lt. A “vote ballot” instruction. vote. A new directive. . and Vote Instructions • • • New atomic and reduction instructions {atom.ge.pred have been added. %clock64.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.or}.gt} have been added. Barrier Instructions • • A system-level membar instruction. bar now supports an optional thread count and register operands.shared have been extended to handle 64-bit data types for sm_20 targets.popc. Reduction. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Other Extensions • • • Video instructions (includes prmt) have been added.f32 have been added. Instructions {atom.

Chapter 8 describes the instruction set. types. Chapter 6 describes instruction operands. Chapter 9 lists special registers. Chapter 5 describes state spaces. Chapter 4 describes the basic syntax of the PTX language. Chapter 7 describes the function and call syntax. Chapter 11 provides release notes for PTX Version 2. calling convention. 2010 5 . and PTX support for abstracting the Application Binary Interface (ABI). Chapter 10 lists the assembly directives supported in PTX.0. and variable declarations. Chapter 3 gives an overview of the PTX virtual machine model.Chapter 1.4. January 24. Introduction 1. The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.

0 6 January 24. 2010 .PTX ISA Version 2.

x.y. To that effect. or host: In other words. but independently on different data. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. a portion of an application that is executed many times. 2D. data-parallel. ntid. or CTA. and results across the threads of the CTA.x. 2. tid. A cooperative thread array.2. Programs use a data parallel decomposition to partition inputs. Threads within a CTA can communicate with each other. assign specific input and output positions.y. To coordinate the communication of the threads within the CTA. is an array of threads that execute a kernel concurrently or in parallel. and ntid.z). compute addresses. or 3D CTA. 2. The thread identifier is a three-element vector tid. More precisely. one can specify synchronization points where threads wait until all threads in the CTA have arrived.2. 2010 7 . 2D.Chapter 2. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. Each CTA thread uses its thread identifier to determine its assigned role. work. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. compute-intensive portions of applications running on the host are off-loaded onto the device. January 24. can be isolated into a kernel function that is executed on the GPU as many different threads. Each thread has a unique thread identifier within the CTA. and select work to perform. It operates as a coprocessor to the main CPU.1. (with elements tid. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. and tid. The vector ntid specifies the number of threads in each CTA dimension.1.z) that specifies the thread’s position within a 1D. Programming Model 2. or 3D shape specified by a three-element vector ntid (with elements ntid. Cooperative thread arrays (CTAs) implement CUDA thread blocks. Each CTA has a 1D.

However. multiple-thread) fashion in groups called warps. WARP_SZ. Typically. %nctaid. 2D . Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). which may be used in any instruction where an immediate operand is allowed. 2010 . because threads in different CTAs cannot communicate and synchronize with each other. %ctaid. Some applications may be able to maximize performance with knowledge of the warp size. Threads may read and use these values through predefined. CTAs that execute the same kernel can be batched together into a grid of CTAs. A warp is a maximal subset of threads from a single CTA. Each grid also has a unique temporal grid identifier (gridid). The warp size is a machine-dependent constant. depending on the platform. Threads within a warp are sequentially numbered. and %gridid.2. a warp has 32 threads. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. %ntid.PTX ISA Version 2. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. or 3D shape specified by the parameter nctaid. 2. so PTX includes a run-time immediate constant. so that the total number of threads that can be launched in a single kernel invocation is very large. read-only special registers %tid. 8 January 24.0 Threads within a CTA execute in SIMT (single-instruction. The host issues a succession of kernel invocations to the device. This comes at the expense of reduced thread communication and synchronization. such that the threads execute the same instructions at the same time. Each grid of CTAs has a 1D.2. or sequentially. Multiple CTAs may execute concurrently and in parallel.

2) Thread (4. 1) Thread (0. 0) Thread (4. 2010 9 . 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 0) Thread (3. 1) Thread (2. 0) CTA (2. 1) Thread (1. 0) Thread (1. 2) Thread (2. 1) CTA (2.Chapter 2. 0) CTA (1. 1) Thread (4. 1) CTA (1. 2) Thread (3. 0) CTA (0. 1) Thread (0. Figure 1. A grid is a set of CTAs that execute independently. 0) Thread (2. Thread Batching January 24. 1) Thread (3. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (0. 2) Thread (1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0.

constant.0 2. for some specific data formats.3. for more efficient transfer. respectively.PTX ISA Version 2. 2010 . or. referred to as host memory and device memory. The global. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. The global. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. and texture memory spaces are optimized for different memory usages. Finally. The device memory may be mapped and read or written by the host. as well as data filtering. all threads have access to the same global memory. Both the host and the device maintain their own local memory. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. constant. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. and texture memory spaces are persistent across kernel launches by the same application. 10 January 24. Each thread has a private local memory. Texture memory also offers different addressing modes.

1) Block (2. 0) Block (1. 1) Block (1. 2) Figure 2. 0) Block (2. 0) Block (0. 2) Block (1. 2010 11 . 1) Grid 1 Global memory Block (0. Memory Hierarchy January 24.Chapter 2. 1) Block (1. 0) Block (0. 0) Block (1. 1) Block (0. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0.

2010 .PTX ISA Version 2.0 12 January 24.

a cell in a grid-based computation). a voxel in a volume. new blocks are launched on the vacated multiprocessors. Parallel Thread Execution Machine Model 3. schedules. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. allowing. and executes concurrent threads in hardware with zero scheduling overhead. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). increasing thread IDs with the first warp containing thread 0. and executes threads in groups of parallel threads called warps. manages. A warp executes one common instruction at a time. disabling threads that are not on that path. and when all paths complete. different warps execute independently regardless of whether they are executing common or disjointed code paths. so full efficiency is realized when all threads of a warp agree on their execution path. When a multiprocessor is given one or more thread blocks to execute. the multiprocessor employs a new architecture we call SIMT (single-instruction.1. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp.Chapter 3. It implements a single-instruction barrier synchronization. the first parallel thread technology. The multiprocessor maps each thread to one scalar processor core. Branch divergence occurs only within a warp. A multiprocessor consists of multiple Scalar Processor (SP) cores. (This term originates from weaving. If threads of a warp diverge via a data-dependent conditional branch. the threads converge back to the same execution path. and each scalar thread executes independently with its own instruction address and register state. When a host program invokes a kernel grid. for example. The threads of a thread block execute concurrently on one multiprocessor. manages. each warp contains threads of consecutive.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. multiple-thread). Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. To manage hundreds of threads running several different programs. and on-chip shared memory. it splits them into warps that get scheduled by the SIMT unit. 2010 13 . January 24. At every instruction issue time. a multithreaded instruction unit. The way a block is split into warps is always the same. As thread blocks terminate. the warp serially executes each branch path taken. The multiprocessor SIMT unit creates. The multiprocessor creates.

each read. which is a read-only region of device memory. As illustrated by Figure 3. but the order in which they occur is undefined. 14 January 24. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. modify. which is a read-only region of device memory. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering.PTX ISA Version 2. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. as well as data-parallel code for coordinated threads. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. however. SIMT enables programmers to write thread-level parallel code for independent. In practice. whereas SIMT instructions specify the execution and branching behavior of a single thread. Vector architectures. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. the programmer can essentially ignore the SIMT behavior. modifies. A multiprocessor can execute as many as eight thread blocks concurrently. the number of serialized writes that occur to that location and the order in which they occur is undefined. A key difference is that SIMD vector organizations expose the SIMD width to the software. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. scalar threads. For the purposes of correctness. the kernel will fail to launch. If an atomic instruction executed by a warp reads. 2010 . If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. but one of the writes is guaranteed to succeed. In contrast with SIMD vector machines. require the software to coalesce loads into vectors and manage divergence manually. and writes to the same location in global memory for more than one of the threads of the warp. If there are not enough registers or shared memory available per multiprocessor to process at least one block.0 SIMT architecture is akin to SIMD (Single Instruction. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. • The local and global memory spaces are read-write regions of device memory and are not cached. write to that location occurs and they are all serialized. on the other hand.

Figure 3. 2010 15 .Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.

2010 .PTX ISA Version 2.0 16 January 24.

version directive specifying the PTX language version. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. Lines beginning with # are preprocessor directives. #endif. Comments Comments in PTX follow C/C++ syntax. 4. followed by a . The C preprocessor cpp may be used to process PTX source files. Lines are separated by the newline character (‘\n’). #if. 2010 17 . PTX is case sensitive and uses lowercase for keywords. January 24. Each PTX file must begin with a . and using // to begin a comment that extends to the end of the current line. Source Format Source files are ASCII text. Pseudo-operations specify symbol and addressing management. #else. Syntax PTX programs are a collection of text source files. #ifdef. #line.Chapter 4.2. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. #define. See Section 9 for a more information on these directives. All whitespace characters are equivalent. whitespace is ignored except for its use in separating tokens in the language. using non-nested /* and */ for comments that may span multiple lines. Comments in PTX are treated as whitespace. 4.target directive specifying the target architecture assumed. The following are common preprocessor directives: #include.1.

3. The guard predicate follows the optional label and precedes the opcode.tex . Statements begin with an optional label and end with a semicolon. r2. 2.maxnctapersm . The destination operand is first. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. where p is a predicate register.align .minnctapersm . address expressions. mov. array[r1].target . r2. Instruction keywords are listed in Table 2.sreg .b32 r1. so no conflict is possible with user-defined identifiers.0 4.const .shared . All instruction keywords are reserved tokens in PTX.f32 array[N].x.2. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.3. 2010 .global . 18 January 24. or label names. r2.func . and terminated with a semicolon. constant expressions. Directive Statements Directive keywords begin with a dot.reg . The guard predicate may be optionally negated.section . ld.global start: .local . %tid. r1.reg . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. followed by source operands. Statements A PTX statement is either a directive or an instruction.3.maxnreg .1.global.version .pragma .extern .b32 add. Table 1.maxntid .f32 r2. shl.visible 4. .b32 r1. written as @!p.PTX ISA Version 2.param .5.entry . Operands may be register variables. and is written as @p.b32 r1.loc .file PTX Directives . 0. . Examples: . Instructions have an optional guard predicate which controls conditional execution.

Syntax Table 2. 2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

between user-defined variable names and compiler-generated names. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters.PTX ISA Version 2. underscore.g. digits. listed in Table 3. Table 3.0 4.4. except that the percentage sign is not allowed. underscore. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. digits. or percentage character followed by one or more letters. PTX allows the percentage sign as the first character of an identifier. e. or they start with an underscore. Many high-level languages such as C and C++ follow similar rules for identifier names. PTX predefines one constant and a small number of special registers that begin with the percentage sign. or dollar characters. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. %pm3 WARP_SZ 20 January 24. 2010 . …. dollar. The percentage sign can be used to avoid name conflicts.

i.Chapter 4. Syntax 4. integer constants are allowed and are interpreted as in C. These constants may be used in data initialization and as operands to instructions. When used in an instruction or data initialization. Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. 4.2. or binary notation. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons. octal.5. For predicate-type data and instructions. each integer constant is converted to the appropriate size based on the data or instruction type at its use. Type checking rules remain the same for integer. i. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.5. Integer literals may be written in decimal. there is no suffix letter to specify size.u64. floating-point. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. Unlike C and C++.u64). in which case the literal is unsigned (. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. where the behavior of the operation depends on the operand types. 0[fF]{hexdigit}{8} // single-precision floating point January 24. To specify IEEE 754 doubleprecision floating point values. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.e. hexadecimal. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant.s64) unless the value cannot be fully represented in .s64 or the unsigned suffix is specified. 2010 21 . every integer constant has type ..e. Floating-point literals may be written with an optional decimal point and an optional signed exponent. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (. zero values are FALSE and non-zero values are TRUE. the constant begins with 0f or 0F followed by 8 hex digits. literals are always represented in 64-bit double-precision format. 4. the constant begins with 0d or 0D followed by 16 hex digits. and bit-size types..s64 or .1.5. the sm_1x and sm_20 targets have a WARP_SZ value of 32. To specify IEEE 754 single-precision floating point values. The syntax follows that of C. Constants PTX supports integer and floating-point constants and constant expressions.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

22

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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PTX ISA Version 2.0

Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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January 24, 2010

2010 25 .s64 .u64 .u64) (. Table 5. .5.s64.s64) + .f64 : .u64 same as 1st operand .u64 .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .s64 .f64 converted type .f64 use usual conversions .s64 .f64 integer .6.f64 integer integer integer integer integer int ?.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .u64 .f64 use usual conversions .Chapter 4. 2nd is .s64 .u64 .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.f64 integer .f64 converted type constant literal + ! ~ Cast Binary (. Syntax 4.u64 .s64 .u64. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.f64 use usual conversions .s64 .u64 . or .s64 .f64 same as source .u64 1st unchanged.

PTX ISA Version 2.0 26 January 24. 2010 .

defined per-grid. Name State Spaces Description Registers. The characteristics of a state space include its size. The list of state spaces is shown in Table 4.shared . access rights. and these resources are abstracted in PTX through state spaces and data types. Global texture memory (deprecated). Addressable memory shared between threads in 1 CTA. .1. Global memory. shared by all threads. Types.global . Shared.sreg . platform-specific. All variables reside in some state space. read-only memory. or Function or local parameters. Local memory.reg . addressability. 5. and properties of state spaces are shown in Table 5. and Variables While the specific resources available in a given target GPU will vary. State Spaces. Table 6.param . State Spaces A state space is a storage area with particular characteristics. private to each thread. the kinds of resources will be common across platforms. Kernel parameters. and level of sharing between threads. Special registers. defined per-thread. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. access speed. fast. 2010 27 .const . Read-only. pre-defined.tex January 24.Chapter 5.local .

PTX ISA Version 2.sreg . via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. Registers may be typed (signed integer. Registers differ from the other state spaces in that they are not fully addressable. 32-. or as elements of vector tuples. platform-specific registers.tex Restricted Yes No3 5.param (used in functions) .2. Register size is restricted. Device function input parameters may have their address taken via mov. 64-. unsigned integer. and performance monitoring registers.reg . it is not possible to refer to the address of a register.. floating point.0 Table 7.global . predicate) or untyped. and cvt instructions. such as grid.sreg) state space holds predefined. 28 January 24. For each architecture. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).reg state space) are fast storage locations. and will vary from platform to platform.1. 2010 .param instruction. 32-. and vector registers have a width of 16-. 16-. 1 Accessible only via the ld. or 128-bits. Register State Space Registers (. All special registers are predefined. scalar registers have a width of 8-. and thread parameters. causing changes in performance. or 64-bits.e. aside from predicate registers which are 1-bit.param and st.const . 3 Accessible only via the tex instruction. register variables will be spilled to memory.shared . When the limit is exceeded. 2 Accessible via ld. The most common use of 8-bit registers is with ld. 5.param instructions. The number of registers is limited.param (as input to kernel) . clock counters. i.local . Registers may have alignment boundaries required by multi-word loads and stores. Special Register State Space The special register (.1. the parameter is then located on the stack frame and its address is in the . Address may be taken via mov instruction. CTA.local state space. st.1.

each pointing to the start address of the specified constant bank. 2010 29 .local to access local variables. initialized by the host. an incomplete array in bank 2 is accessed as follows: .global) state space is memory that is accessible by all threads in a context. and atom.extern .global. Use ld.4.3. Threads must be able to do their work without waiting for other threads to do theirs. ld. State Spaces.local) is private memory for each thread to keep its own data.extern . bank zero is used.global to access global variables. the bank number must be provided in the state space of the load instruction. Use ld. This reiterates the kind of parallelism available in machines that run PTX. If no bank number is given. [const_buffer+4]. // load second word 5. st. Module-scoped local memory variables are stored at fixed addresses. and Variables 5.1. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.global. For example. For any thread in a context. By convention. whereas local memory variables declared January 24. To access data in contant banks 1 through 10. Banks are specified using the .Chapter 5. Consider the case where one thread executes the following two assignments: a = a + 1. Multiple incomplete array variables declared in the same bank become aliases. Threads wait at the barrier until all threads in the CTA have arrived.sync instruction are guaranteed to be visible to any reads after the barrier instruction.const[2] . where bank ranges from 0 to 10. In implementations that support a stack. It is the mechanism by which different CTAs and different grids can communicate.local and st.const) state space is a read-only memory. the store operation updating a may still be in flight.b32 const_buffer[]. Global memory is not sequentially consistent.1. Local State Space The local state space (. Types.const[bank] modifier.5. the declaration . The remaining banks may be used to implement “incomplete” constant arrays (in C. Sequential consistency is provided by the bar. the stack is in local memory. It is typically standard memory with cache. 5.b32 const_buffer[]. b = b – 1. for example). For the current devices. The constant memory is organized into fixed size banks.b32 %r1.const[2] . all addresses are in global memory are shared. For example. Global State Space The global (. results in const_buffer pointing to the start of constant bank two. Constant State Space The constant (. there are eleven 64KB banks. The size is limited. as in lock-free and wait-free style programming. If another thread sees the variable b change.const[2].1. where the size is not known at compile time. as it must be allocated on a perthread basis. bank zero is used for all statically-sized constant variables. This pointer can then be used to access the entire 64KB constant bank.sync instruction. All memory writes prior to the bar.

.6.0 within a function or kernel body are allocated on the stack. Note that PTX ISA versions 1. device function parameters were previously restricted to the register state space. [buffer].reg . all local memory variables are stored at fixed addresses and recursive function calls are not supported.b32 len ) { . PTX code should make no assumptions about the relative locations or ordering of . … Example: . in some implementations kernel parameters reside in global memory.u32 %n. … 30 January 24.u32 %ptr. ld.entry foo ( .x supports only kernel function parameters in . function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).param . These parameters are addressable.param . and (2b) to declare locally-scoped byte array variables that serve as function call arguments. 5. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.entry bar ( .b8 buffer[64] ) { .reg . per-kernel versus per-thread).param) state space is used (1) to pass input arguments from the host to the kernel.u32 %n.b32 N.u32 %ptr. For example.1. Values passed from the host to the kernel are accessed through these parameter variables using ld. The resulting address is in the . No access protection is provided between parameter and global space in this case. mov.reg . ld. Parameter State Space The parameter (.param instructions.param .param space variables. [%ptr].param space.PTX ISA Version 2.f64 %d. The kernel parameter variables are shared across all CTAs within a grid.param instructions. 2010 . read-only variables declared in the .param. . The address of a kernel parameter may be moved into a register using the mov instruction. The use of parameter state space for device function parameters is new to PTX ISA version 2.param. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. ld. Similarly. typically for passing large structures by value to a function.u32 %n.align 8 .0 and requires target architecture sm_20. Therefore. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param state space and is accessed using ld. Example: . %n.param state space. 5.param.6. [N].1.f64 %d. len.1. In implementations that do not support a stack. Note: The location of parameter space is implementation specific.

param. Aside from passing structures by value.reg . In this case.param . }. Typically.param.local state space and is accessed via ld. … See the section on function call syntax for more details. . call foo. Function input parameters may be read via ld. Note that the parameter will be copied to the stack if necessary.func foo ( . Device Function Parameters PTX ISA version 2. .6.2.s32 %y.param. This will be passed by value to a callee.f64 %d. x.b8 buffer[12] ) { .param space variable. . and so the address will be in the .param and function return parameters may be written using st. a byte array in parameter space is used. … } // code snippet from the caller // struct { double d. .reg .reg .Chapter 5. dbl. and Variables 5. ld. State Spaces.s32 %y.param formal parameter having the same size and alignment as the passed argument. is flattened.param. 2010 31 .reg . … st. Example: // pass object of type struct { double d.0 extends the use of parameter space to device function parameters. January 24.b32 N. such as C structures larger than 8 bytes.f64 dbl. mystruct).local and st.f64 [mystruct+0].align 8 . the caller will declare a locally-scoped . (4. it is illegal to write to an input parameter or read from a return parameter.s32 [mystruct+8]. which declares a .s32 x.1.align 8 . Types.param .b8 mystruct. } mystruct. In PTX. [buffer+8].param byte array variable that represents a flattened C structure or union. The most common use is for passing objects by value that do not fit within a PTX register.local instructions. [buffer]. passed to foo … .param space is also required whenever a formal parameter has its address taken within the called function. It is not possible to use mov to get the address of a return parameter or a locally-scoped . the address of a function input parameter may be moved into a register using the mov instruction. st. int y. .reg .f64 %d. int y. ld.param. .

6 for its use in texture instructions. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. a legacy PTX definitions such as . and .tex state space are equivalent to module-scoped .u32 . Texture memory is read-only. Physical texture resources are allocated on a per-module granularity. The . and programs should instead reference texture memory through variables of type .1.PTX ISA Version 2.3 for the description of the .tex directive will bind the named texture memory variable to a hardware texture identifier. Texture State Space (deprecated) The texture (.u32 .7. 5.1. tex_c.shared and st. Another is sequential access from sequential threads. is equivalent to .tex .texref type and Section 8.tex . One example is broadcast.shared to access shared variables.tex .0 5.tex directive is retained for backward compatibility. A texture’s base address is assumed to be aligned to a 16-byte boundary.texref. and variables declared in the .u32 tex_a.global state space. The . tex_d. The texture name must be of type . It is shared by all threads in a context.u32 or . An error is generated if the maximum number of physical resources is exceeded. tex_f. 32 January 24. where all threads read from the same address. An address in shared memory can be read and written by any thread in a CTA.tex .u32 .u64. Multiple names may be bound to the same physical texture identifier.texref variables in the .tex) state space is global memory accessed via the texture instruction. Shared memory typically has some optimizations to support the sharing. For example. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).7. Use ld.tex variables are required to be defined in the global scope. where texture identifiers are allocated sequentially beginning with zero. Shared State Space The shared (. See Section 5.tex . Example: .global . tex_d.8.shared) state space is a per-CTA region of memory for threads in a CTA to share data. 2010 .u32 tex_a.texref tex_a.

Restricted Use of Sub-Word Sizes The . The . st. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . . Fundamental Types In PTX.f64 types.b64 .u32. Types. and cvt instructions permit source and destination data operands to be wider than the instruction-type size.2.u8. For convenience. . the fundamental types reflect the native data types supported by the target architectures.s64 . .s16. stored.f64 types. 2010 33 .f32 and .u8. and Variables 5. .f16 floating-point type is allowed only in conversions to and from .Chapter 5.s8.b16. and cvt instructions. Types 5. so their names are intentionally short. The following table lists the fundamental type specifiers for each basic type: Table 8. .1.u64 .f32 and . .2. The bitsize type is compatible with any fundamental type having the same size.s32.f64 . but typed variables enhance program readability and allow for better operand type checking. . Signed and unsigned integer types are compatible if they have the same size. ld. Operand types and sizes are checked against instruction types for compatibility. For example. Register variables are always of a fundamental type. In principle. and instructions operate on these types.f16. and converted using regular-width registers. all variables (aside from predicates) could be declared using only bit-size types. and . . State Spaces. needed to fully specify instruction behavior. st.2. January 24.f32.s8. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. . The same typesize specifiers are used for both variable definitions and for typing instructions. .pred Most instructions have one or more type specifiers.2. . so that narrow values may be loaded. . stored.b8 instruction types are restricted to ld.b32. A fundamental type specifies both a basic type and a size. 5. Two fundamental types are compatible if they have the same basic type and are the same size.b8.u16. or converted to other types and sizes. All floating-point instructions operate only on .

3.samplerref variables. or performing pointer arithmetic will result in undefined results. Creating pointers to opaque variables using mov. Referencing textures. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type. or surfaces via texture and surface load/store instructions (tex. samplers. allowing them to be defined separately and combined at the site of usage in the program. field ordering.texref type that describe sampler properties are ignored. opaque_var. and surface descriptor variables.samplerref.. since these properties are defined by .e. and Surface Types PTX includes built-in “opaque” types for defining texture.texref. and . sust. In the unified mode.texref handle.0 5. but all information about layout. passed as a parameter to functions. For working with textures and samplers. texture and sampler information each have their own handle. Texture.u64} reg. sampler. texture and sampler information is accessed through a single . In independent mode the fields of the . accessing the pointer with ld and st instructions. hence the term “opaque”. store. sured). and de-referenced by texture and surface load. suq). 2010 . The three built-in types are .{u32. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API.PTX ISA Version 2. PTX has two modes of operation. and overall size is hidden to a PTX program. Retrieving the value of a named member via query instructions (txq. In the independent mode. These types have named fields similar to structures. Sampler.surfref. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. but the pointer cannot otherwise be treated as an address. The following tables list the named members of each type for unified and independent texture modes. . i. the resulting pointer may be stored to and loaded from memory. base address. and query instructions. suld. 34 January 24.

2010 35 . 1 ignored ignored ignored ignored . mirror. linear wrap. 1 nearest.samplerref values N/A N/A N/A N/A nearest. and Variables Table 9. clamp_to_edge. clamp_ogl.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24.texref values .surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. Types. Member width height depth Opaque Type Fields in Unified Texture Mode . State Spaces.texref values in elements in elements in elements 0. clamp_ogl. Member width height depth Opaque Type Fields in Independent Texture Mode .Chapter 5. linear wrap. mirror. clamp_to_border 0. clamp_to_edge. clamp_to_border N/A N/A N/A N/A N/A .

filter_mode = nearest }. Example: . At module scope. the types may be initialized using a list of static expressions assigning values to the named members. As kernel parameters. these variables are declared in the .global .global .param state space.global state space. . .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global .texref tex1. these variables must be in the .global .global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. 36 January 24. 2010 . When declared at module scope.surfref my_surface_name.PTX ISA Version 2.texref my_texture_name.samplerref my_sampler_name. . Example: .

v4 vector. . a variable declaration describes both the variable’s type and its state space. 1.global .reg .f32 accel. . Every variable must reside in one of the state spaces enumerated in the previous section.v2. . 0.f64 is not allowed. // a length-2 vector of unsigned ints . This is a common case for three-dimensional grids.v4 . an optional initializer. // a length-4 vector of bytes By default.4. January 24. // a length-4 vector of floats . and they may reside in the register space. its name. for example. Predicate variables may only be declared in the register state space. . Examples: .1.v3 }. and an optional fixed address for the variable.2. Types.v1.0}.u32 loc. and Variables 5.4.Chapter 5.shared . // typedef . 0}.global . State Spaces. textures. . etc. In addition to fundamental types. 0. 2010 37 .b8 v.v4 .4. Vectors cannot exceed 128-bits in length.u16 uv. PTX supports types for simple aggregate objects such as vectors and arrays.pred p. A variable declaration names the space in which the variable resides. .struct float4 { .v4 . Examples: .reg .v2 or .f32 bias[] = {-1. r. 5.f32 v0. Variable Declarations All storage for data is specified with variable declarations. vector variables are aligned to a multiple of their overall size (vector length times base-type size).reg .u8 bg[4] = {0. . Vectors Limited-length vector types are supported.0.v4. where the fourth element provides padding.global .f32 V.s32 i. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . an optional array size. 5.v4.global . to enable vector load and store instructions which require addresses aligned to a multiple of the access size.const .v2 .struct float4 coord. q. Vectors must be based on a fundamental type. its type and size. Variables In PTX.global . Three-element vectors may be handled by using a .

. or is left empty. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.global .1.4. . 38 January 24. 2010 . {0. Variables that hold addresses of variables or instructions should be of type . ..v4 . The size of the dimension is either a constant expression.PTX ISA Version 2.. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).05.. To declare an array. this can be used to statically initialize a pointer to a variable. 5. {1.u64.f32 blur_kernel[][] = {{. .u32 or . variable initialization is supported only for constant and global state spaces.f16 and .1.{. 0}.0.pred.0}.global .s32 offset[][] = { {-1.0.0}}. Initializers are allowed for all types except .s32 n = 10.0 5.0. Variable names appearing in initializers represent the address of the variable.. being determined by an array initializer.u8 rgba[3] = {{1.05. -1}.1.u16 kernel[19][19].05}. 0}. Here are some examples: .0.4. Examples: .local . {0.. where the variable name is followed by an equals sign and the initial value or values for the variable.shared . the variable name is followed with dimensional declarations similar to fixed-size array declarations in C. Array Declarations Array declarations are provided to allow the programmer to reserve space. 19*19 (361) halfwords are reserved (722 bytes).1. // address of rgba into ptr Currently.1.05}}. For the kernel declaration above.global . label names appearing in initializers represent the address of the next instruction following the label.global .global . 1} }.3. {0. .b32 ptr = rgba.0}.u8 mailbox[128].4. this can be used to initialize a jump table to be used with indirect branches or calls. The size of the array specifies how many elements should be reserved. Similarly. A scalar takes a single value.4. {0.1}..{.

6. it is quite common for a compiler frontend to generate a large number of register names.4. 2010 39 . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. nor are initializers permitted. Examples: // allocate array at 4-byte aligned address..0}.4. say one hundred. 5. . suppose a program uses a large number.0. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.0.b32 %r<100>.5. The default alignment for vector variables is to a multiple of the overall vector size.0... Array variables cannot be declared this way. For example.b8 bar[8] = {0.0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. and may be preceded by an alignment specifier.reg . State Spaces. of .const . alignment specifies the address alignment for the starting address of the entire array. %r1.0. // declare %r0. %r99. %r1. Rather than require explicit declaration of every name. For arrays.align byte-count specifier immediately following the state-space specifier. …. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. The default alignment for scalar and array variables is to a multiple of the base-type size.align 4 . Alignment is specified using an optional . . and Variables 5.Chapter 5. Parameterized Variable Names Since PTX supports virtual registers. January 24. Types. The variable will be aligned to an address which is an integer multiple of byte-count. not for individual elements. named %r0.2.b32 variables. Elements are bytes. These 100 register variables can be declared as follows: .

2010 .PTX ISA Version 2.0 40 January 24.

Instruction Operands 6. Integer types of a common size are compatible with each other. as its job is to convert from nearly any data type to any other data type (and size).1. b. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. PTX describes a load-store machine. Instructions ld and st move data from/to addressable state spaces to/from registers. January 24. so operands for ALU instructions must all be in variables declared in the . 6. Source Operands The source operands are denoted in the instruction descriptions by the names a.3. st. Each operand type must be compatible with the type determined by the instruction template and instruction type. q. The mov instruction copies data between registers. The bit-size type is compatible with every type having the same size. r. The cvt (convert) instruction takes a variety of operand types and sizes. and cvt instructions copy data from one location to another. the sizes of the operands must be consistent. The ld. There is no automatic conversion between types. The result operand is a scalar or vector variable in the register state space. Operand Type Information All operands in instructions have a known type from their declarations. mov.reg register state space. 2010 41 . Predicate operands are denoted by the names p. and c. 6.2. For most operations. and a few instructions have additional predicate source operands. s. Most instructions have an optional predicate guard that controls conditional execution. Operands having type different from but compatible with the instruction type are silently cast to the instruction type.Chapter 6. .

and Vectors Using scalar variables as operands is straightforward.4. p. address register plus byte offset.global .s32 mov. The interesting capabilities begin with addresses.v4 .const.reg . there is no support for C-style pointer arithmetic.1.PTX ISA Version 2. The syntax is similar to that used in many assembly languages. ld. .u16 r0. .s32 tbl[256]. Load and store operations move data between registers and locations in addressable state spaces. 6. tbl. q.const . . Using Addresses. and vectors.v4 .0 6. Examples include pointer arithmetic and pointer comparisons.s32 q. Here are a few examples: . W.f32 W.f32 V. [tbl+12].4.reg . All addresses and address computations are byte-based. .reg . and immediate address expressions which evaluate at compile-time to a constant address. arrays.b32 p. The address is an offset in the state space in which the variable is declared. . The mov instruction can be used to move the address of a variable into a pointer. [V]. Arrays. Address expressions include variable names.u32 42 January 24.reg .u16 ld.gloal.u16 x.shared.shared . .v4. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.[x]. address registers. 2010 .f32 ld. r0.

f32 a. The expression within square brackets is either a constant integer.w.u32 s. Here are examples: ld. A brace-enclosed list is used for pattern matching to pull apart vectors. The registers in the load/store operations can be a vector. Vector loads and stores can be used to implement wide loads and stores. Vectors as Operands Vector operands are supported by a limited subset of instructions.b. Elements in a brace-enclosed vector.u32 s. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Vectors may also be passed as arguments to called functions. Array elements can be accessed using an explicitly calculated byte address.r.4. January 24.b V.f32 {a. where the offset is a constant expression that is either added or subtracted from a register variable. .global. Examples are ld.x V.reg .d}.y V. which include mov.c. . or by indexing into the array using square-bracket notation. If more complicated indexing is desired. or a braceenclosed list of similarly typed scalars. it must be written as an address calculation prior to use.f32 ld. and in move instructions to get the address of the label or function into a register.f32 V.v4.z V. mov.c. a[0].4. Rb. ld. as well as the typical color fields .b and . Rc. a register variable.reg .u32 s. mov. 2010 43 . c.x. b. which may improve memory performance.global.z and .d}.g V.v4.a.4. .g. . [addr+offset2]. Vector elements can be extracted from the vector with the suffixes . V.3.a 6. for use in an indirect branch or call.2. The size of the array is a constant in the program.y. Rd}. a[1]. a[N-1].global. st.u32 {a. // move address of a[1] into s 6. say {Ra.w = = = = V.b. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. or a simple “register with constant offset” expression. . Instruction Operands 6.Chapter 6. and tex. V2.global.r V. and the identifier becomes an address constant in the space where the array is declared. . [addr+offset]. ld.v2. Arrays as Operands Arrays of all types can be declared.4.v4 . d.

and data movement instruction must be of the same type and size.1.u16 instruction is given a u16 source operand and s32 as a destination operand. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64. and ~131.5. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.000 for f16). 44 January 24.0 6. For example. 6. logic.PTX ISA Version 2. except for operations where changing the size and/or type is part of the definition of the instruction. if a cvt.5.s32. 2010 . Type Conversion All operands to all arithmetic. the u16 is zero-extended to s32. Operands of different sizes or types must be converted prior to the operation.

January 24. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. f2f = float-to-float.Chapter 6. cvt. Instruction Operands Table 11. The type of extension (sign or zero) is based on the destination format.s16. s2f = signed-to-float. zext = zero-extend. For example. 2010 45 . then sign-extend to 32-bits. f2u = float-to-unsigned. the result is extended to the destination register width after chopping. chop = keep only low bits that fit.u32 targeting a 32-bit register will first chop to 16-bits. u2f = unsigned-to-float. Notes 1 If the destination register is wider than the destination format. f2s = float-to-signed.

5.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.2.rz .rm . choosing even integer if source is equidistant between two integers. Rounding Modifiers Conversion instructions may specify a rounding modifier.0 6. The following tables summarize the rounding modifiers.rn .rmi .rpi Integer Rounding Modifiers Description round to nearest integer. Modifier . In PTX.PTX ISA Version 2. there are four integer rounding modifiers and four floating-point rounding modifiers. Table 12.rni .rzi . 2010 . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24. Modifier .

The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Much of the delay to memory can be hidden in a number of ways. Another way to hide latency is to issue the load instructions as early as possible. Table 14. while global memory is slowest. Table 11 gives estimates of the costs of using different kinds of memory. Instruction Operands 6. Operand Costs Operands from different state spaces affect the speed of an operation. The register in a store operation is available much more quickly. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. 2010 47 .Chapter 6. first access is high Notes January 24. Registers are fastest.6. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.

2010 .0 48 January 24.PTX ISA Version 2.

the function name. function calls. functions are declared and defined using the . support for variadic functions (“varargs”). and is represented in PTX as follows: . January 24. A function declaration specifies an optional list of return parameters. Abstracting the ABI Rather than expose details of a particular calling convention. together these specify the function’s interface. Function declarations and definitions In PTX. stack layout. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. A function definition specifies both the interface and the body of the function. In this section. Execution of the ret instruction within foo transfers control to the instruction following the call. 7. parameter passing. and return values may be placed directly into register variables.1. … Here. The simplest function has no parameters or return values. At the call. execution of the call instruction transfers control to foo. and memory allocated on the stack (“alloca”). we describe the features of PTX needed to achieve this hiding of the ABI. These include syntax for function definitions. Scalar and vector base-type input and return parameters may be represented simply as register variables. A function must be declared or defined prior to being called. and an optional list of input parameters. so recursion is not yet supported.Chapter 7. or prototype. } … call foo. stack-based ABI. NOTE: The current version of PTX does not implement the underlying. implicitly saving the return address.func foo { … ret.func directive. arguments may be register variables or constants. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. and Application Binary Interface (ABI). 2010 49 .

… Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . st. char c[4].PTX ISA Version 2. … st. (%r1. %rd. c3. } … call (%r1). … ld.param space memory. consider the following C structure. For example.func (. %rc2. … … // computation using x.reg .reg .param. st. . [y+11].param . passed by value to a function: struct { double dbl. %ptr.reg .reg space.param .b8 [py+ 9]. … In this example.s32 out) bar (. this structure will be flattened into a byte array.reg .param.b8 .param. [y+9].param state space is used to pass the structure by value: . c4.c4. %rc2.reg . st. In PTX. 2010 .param.b8 .c2.b8 [py+10].param space variables are used in two ways.u32 %ptr. [y+8].param. // scalar args in .u32 %res) inc_ptr ( .b8 c2. c2.align 8 py[12].b8 c1. bumpptr.u32 %res.b64 [py+ 0].c1. st. %rc1.f64 f1. ld. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .param. .align 8 y[12]) { .reg . ret. 50 January 24. [y+10]. %rc1. }.f64 f1.func (.param.c3.param. .b32 c1. Second.b8 c3. First. a .u32 %inc ) { add.reg .param space call (%out). ld.s32 x. note that .b8 c4.b8 [py+ 8].b8 [py+11]. byte array in .param. Since memory accesses are required to be aligned to a multiple of the access size.f1. %inc. [y+0]. inc_ptr. a . ld.f64 field are aligned. The . ld.4). py).param variable py is declared in the body of the calling function and used to set up the structure being passed to bar.param. (%x.param variable y is used in function definition bar to represent a formal parameter.0 Example: . } { .

This enables backend optimization and ensures that the .param byte array is used to collect together fields of a structure being passed by value.reg or .param arguments. . The following restrictions apply to parameter passing.reg variables. all st. the argument must also be a . Supporting the . For a callee. 4. the corresponding argument may be either a . 2.reg variables. • • • Input and return parameters may be . and alignment.param space byte array with matching type. 8. or a constant that can be represented in the type of the formal parameter.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e. or 16 bytes. Parameters in . For a caller. Note that the choice of . or a constant that can be represented in the type of the formal parameter. For .param state space is used to set values that will passed to a called function and/or to receive return values from a called function. • The . • • • For a callee. a .reg space formal parameters.reg space variable of matching type and size.param instructions used for argument passing must be contained in the basic block with the call instruction.param state space is used to receive parameter values and/or pass return values back to the caller.param memory must be aligned to a multiple of 1. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. In the case of . In the case of .param space formal parameters that are base-type scalar or vector variables. the corresponding argument may be either a .param or ..param or .param space formal parameters that are byte arrays.g. A .param variables or .param argument must be declared within the local scope of the caller.reg state space in this way provides legacy support. The .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. 2010 51 . Typically.param state space use in device functions. • • Arguments may be . In the case of . January 24.reg space variable with matching type and size. size. or constants. and alignment of parameters. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee.Chapter 7. size.param variables. • The . For a caller.reg state space can be used to receive and return base-type scalar and vector values. Abstracting the ABI The following is a conceptual way to think about the .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param and ld. The .

x In PTX ISA version 1.reg or . and there was no support for array parameters.0 7.0. Changes from PTX 1.x supports multiple return values for this purpose.1.0 restricts functions to a single return value.0 continues to support multiple return registers for sm_1x targets. For sm_2x targets. and . 52 January 24.PTX ISA Version 2.reg state space.param byte array should be used to return objects that do not fit into a register.param space parameters support arrays. PTX 2. and a . formal parameters were restricted to . PTX 2. formal parameters may be in either . Objects such as C structures were flattened and passed or returned using multiple registers.1. In PTX ISA version 2.x. PTX 1. 2010 .param state space.

Once all arguments have been processed. for %va_arg64. %va_end is called to free the variable argument list handle. 2. 2.reg . 8. along with the size and alignment of the next data value to be accessed. Variadic functions NOTE: The current version of PTX does not support variadic functions.ge p.u32 N. To support functions with a variable number of arguments. the size may be 1. max.func (. // default to MININT mov. (ap.reg . the size may be 1.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. 0.reg . ctr. %s1.func %va_end (. 0x8000000. .reg . ) { . bra Done. Abstracting the ABI 7. mov. variadic functions are declared with an ellipsis at the end of the input parameter list. %va_start. In both cases.reg . ..u32 b. This handle is then passed to the %va_arg and %va_arg64 built-in functions. } … call (%max).reg . bra Loop.reg .pred p.u32.reg . Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .b32 ctr. %s2).s32 val. call %va_end. %r2. 4). (ap).Chapter 7. maxN. .func (.u32 a. … ) .u32 align) . %va_arg.u32 sz. The function prototypes are defined as follows: .. 4. 4. PTX provides a high-level mechanism similar to the one provided by the stdarg. N. and end access to a list of variable arguments. %r1. .reg . result. (3. call (ap).reg . … %va_start returns Loop: @p Done: January 24.u32 sz.u32 align) . iteratively access.b32 result. or 16 bytes.2. val.b64 val) %va_arg64 (. . ctr.h headers in C. In PTX. (2.s32 result ) maxN ( .func baz ( .h and varargs. maxN. ret.u32 ptr. . %r3).func okay ( … ) Built-in functions are provided to initialize. 2. setp. For %va_arg. call (val). .s32 result.u32 ptr.func (. following zero or more fixed parameters: . or 8 bytes.b32 val) %va_arg (.reg .u32 ptr) %va_start .reg . the alignment may be 1. 4.reg .reg .func ( .reg .u32 ap.reg . 2010 53 . … call (%max). . or 4 bytes.reg .

local and st. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment.func ( .reg .PTX ISA Version 2. Alloca NOTE: The current version of PTX does not support alloca. 2010 . The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. To allocate memory.0 7. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack. The array is then accessed with ld.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. 54 January 24. If a particular alignment is required.reg . defined as follows: .3. a function simply calls the built-in function %alloca.local instructions.u32 ptr ) %alloca ( .

a.Chapter 8. B.s32. We use a ‘|’ symbol to separate multiple destination registers. A. opcode D. For instructions that create a result value. // p = (a < b).2. b. B. A. setp. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. opcode A.1. B. the D operand is the destination operand. the semantics are described.lt p|q. followed by some examples that attempt to show several possible instantiations of the instruction. q = !(a < b). In addition to the name and the format of the instruction. PTX Instructions PTX instructions generally have from zero to four operands. 8. A. January 24. C. opcode D. while A. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. and C are the source operands. 2010 55 . opcode D. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. For some instructions the destination operand is optional. The setp instruction writes two destination registers. Instruction Set 8.

Instructions without a guard predicate are executed unconditionally.s32 j. the following PTX instruction sequence might be used: @!p L1: setp. Predicates are most commonly set as the result of a comparison performed by the setp instruction. bra L1.pred p. predicate registers are virtual and have . i. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction.3.lt. n. This can be written in PTX as @p setp. As an example. To implement the above example as a true conditional branch. add. // p = (i < n) // if i < n. i. j.pred as the type specifier. 1. add. use a predicate to control the execution of the branch or call instructions.0 8. branch over 56 January 24.lt. Predicated Execution In PTX. 1. where p is a predicate variable.reg . 2010 .s32 p. n. … // compare i to n // if false. optionally negated. predicate registers can be declared as . add 1 to j To get a conditional branch or conditional function call.PTX ISA Version 2.s32 p. q. consider the high-level code if (i < n) j = j + 1. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. So. j.s32 j.

ne.1. lt. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. unsigned integer. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). ge. Instruction Set 8. Table 16. If either operand is NaN.2. 2010 57 . and hs (higher-or-same).Chapter 8. Unsigned Integer. Comparisons 8. ls (lower-or-same). and ge (greater-than-or-equal).3.3. The unsigned comparisons are eq. lo (lower). le.3.1. ne. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. lt (less-than). Table 15. The bit-size comparisons are eq and ne.1. The following table shows the operators for signed integer. le (less-than-or-equal).1. gt. and bitsize types. ordering comparisons are not defined for bit-size types. gt (greater-than). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. ne (not-equal). the result is false. hi (higher).

Table 18. unordered versions are included: equ. and mov.3. num returns true if both operands are numeric values (not NaN). If both operands are numeric values (not NaN). not. xor. for example: selp. setp can be used to generate a predicate from an integer. then these comparisons have the same result as their ordered counterparts. leu. and nan returns true if either operand is NaN. then the result of these comparisons is true. neu. There is no direct conversion between predicates and integer values. 2010 . Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.u32 %r1.1.0 To aid comparison operations in the presence of NaN values.%p. two operators num (numeric) and nan (isNaN) are provided. // convert predicate to 32-bit value 58 January 24. geu. However.2. and no direct way to load or store predicate register values. Table 17. or. If either operand is NaN. ltu.0. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.PTX ISA Version 2. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. gtu.

e. unsigned. Type Information for Instructions and Operands Typed instructions must have a type-size modifier. Example: . a.reg . Table 19.fX ok inv inv ok Instruction Type . b.u16 d.f32. cvt. i. // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. Floating-point types agree only if they have the same size.u16 a. and these are placed in the same order as the operands.f32 d. different sizes). It requires separate type-size modifiers for the result and source.u16 d. they must match exactly.u16 d.sX .sX ok ok ok inv . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. add.uX ok ok ok inv . // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. 2010 59 . float. and integer operands are silently cast to the instruction type if needed. the add instruction requires type and size information to properly perform the addition operation (signed. and this information must be specified as a suffix to the opcode. For example. For example: . a. For example.Chapter 8.uX .reg . a. Signed and unsigned integer types agree provided they have the same size.4. Type Checking Rules Operand Type .fX ok ok ok ok January 24. b.. . • The following table summarizes these type checking rules.bX .bX .reg . most notably the data conversion instruction cvt. Instruction Set 8.

2. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. Floating-point source registers can only be used with bit-size or floating-point instruction types. The following table summarizes the relaxed type-checking rules for source operands. the size must match exactly. and converted using regular-width registers. st. Operand Size Exceeding Instruction-Type Size For convenience.1. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. parse error. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. stored. for example.0 8. Bit-size source registers may be used with any appropriately-sized instruction type. For example. Notes 3. floating-point instruction types still require that the operand type-size matches exactly. When a source operand has a size that exceeds the instruction-type size. unless the operand is of bit-size type. When used with a floating-point instruction type. inv = invalid. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. 2010 . no conversion needed. Note that some combinations may still be invalid for a particular instruction. 60 January 24.bX instruction types. or converted to other types and sizes. Table 20. 4. so those rows are invalid for cvt. the cvt instruction does not support .4.PTX ISA Version 2. the data will be truncated. Source register size must be of equal or greater size than the instruction-type size. When used with a narrower bit-size type. ld. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. “-“ = allowed. stored. so that narrow values may be loaded. 1. The data is truncated to the instruction-type size and interpreted according to the instruction type. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize.

and is zero-extended to the destination register width otherwise. When used with a floatingpoint instruction type. Bit-size destination registers may be used with any appropriately-sized instruction type. 4. 2. Notes 3. Floating-point destination registers can only be used with bit-size or floating-point instruction types. the data is zeroextended. The data is signextended to the destination register width for signed integer instruction types. The data is sign-extended to the destination register width for signed integer instruction types. Table 21. 2010 61 . The following table summarizes the relaxed type-checking rules for destination operands. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. If the corresponding instruction type is signed integer. Destination register size must be of equal or greater size than the instruction-type size. 1. When used with a narrower bit-size instruction type. the data is sign-extended.or sign-extended to the size of the destination register. January 24. otherwise. the data will be zero-extended.Chapter 8. the destination data is zero. Instruction Set When a destination operand has a size that exceeds the instruction-type size. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. zext = zero-extend. the size must match exactly. “-“ = Allowed but no conversion needed. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. inv = Invalid. parse error.

PTX ISA Version 2. A compiler or programmer may chose to enforce portable. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. These extra precision bits can become visible at the application level. 16-bit registers in PTX are mapped to 32-bit physical registers. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. 8. using the . by a right-shift instruction.0 8. However. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path.uni suffix. until C is not expressive enough. 2010 . the semantics of 16-bit instructions in PTX is machine-specific. When executing on a 32-bit data path. for many performance-critical applications. 8. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Both situations occur often in programs. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. the threads are called uniform. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. at least in appearance. this is not desirable. the optimizing code generator automatically determines points of re-convergence. Divergence of Threads in Control Constructs Threads in a CTA execute together. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. a compiler or code author targeting PTX can ignore the issue of divergent threads. Therefore. and for many applications the difference in execution is preferable to limiting performance. At the PTX language level. so it is important to have divergent threads re-converge as soon as possible.1.6. until they come to a conditional control construct such as a conditional branch. 62 January 24. for example. If threads execute down different control flow paths. The semantics are described using C. the threads are called divergent.5. For divergent control flow.6. If all of the threads act in unison and follow a single control flow path. conditional function call. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. and 16-bit computations are “promoted” to 32-bit computations. or conditional return.

Instruction Set 8.7.1.cc. addc sub.cc. In the following descriptions. the optional guard predicate is omitted from the syntax. 2010 63 .7. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24. 8. Instructions All PTX instructions may be predicated.Chapter 8. The Integer arithmetic instructions are: add sub add.

s32 d. Description Semantics Notes Performs addition and writes the resulting value into a destination register. sub. PTX ISA Notes Target ISA Notes Examples 64 January 24. a. d = a + b.0. Supported on all target architectures.type = { .u64. Applies only to . PTX ISA Notes Target ISA Notes Examples Table 23. // .s32. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.MAXINT (no overflow) for the size of the operation.s32 type. b. Saturation modifier: .MAXINT (no overflow) for the size of the operation.s32 c. add. Applies only to .u32. . a.sat limits result to MININT. .1. .sat}. b.a.c. Introduced in PTX ISA version 1. . a. d = a – b.s32 .sat applies only to .PTX ISA Version 2.s16.. .u64. d.u32. sub.type sub{. add Syntax Integer Arithmetic Instructions: add Add two values. b.u16.0.s32 d.y. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.type = { . .s64 }. Introduced in PTX ISA version 1.s32 type. d.s64 }.sat applies only to . a.sat.s32. .b. .0 Table 22.sat limits result to MININT. Saturation modifier: . 2010 . b. Supported on all target architectures. add.z.s16.s32 c. @p add. // .u16. .s32 .sat}. .type add{..u32 x.

. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.type = {. . 2010 65 . carry-out written to CC. b.Chapter 8.2.y4. b.cc. Introduced in PTX ISA version 1.cc.CF No integer rounding modifiers.cc.cc Add two values with carry-out.type = { . if .s32 }.z1. Supported on all target architectures.cc}.b32 addc. add.b32 addc.type d. d = a + b + CC. or testing the condition code. x3. and there is no support for setting.y2.b32 x1. x4.b32 addc. Introduced in PTX ISA version 1. x3.b32 addc.b32 addc.z1.z4.s32 }. .b32 addc. clearing. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc. @p @p @p @p add. Instruction Set Instructions add. No saturation. add.cc specified. d = a + b. carry-out written to CC. Table 24. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. sub.type d.2. a.y3.cc. addc{. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. These instructions support extended-precision integer addition and subtraction. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.z3. No saturation. @p @p @p @p add. x2.cc.CF) holding carry-in/carry-out or borrowin/borrow-out.u32.z4. a.CF.b32 x1.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. Behavior is the same for unsigned and signed integers.CF No integer rounding modifiers.cc.y1.z3.u32. x4.y3. addc.cc.cc.cc.y1. Supported on all target architectures.y4. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.cc Syntax Integer Arithmetic Instructions: add.z2. x2. .z2.y2. Behavior is the same for unsigned and signed integers. No other instructions access the condition code.

PTX ISA Version 2.b32 x1. No saturation. @p @p @p @p sub.z1.cc specified. withborrow-in and optional borrow-out. sub. d = a . x3. x2. borrow-out written to CC.cc.cc.CF No integer rounding modifiers. b. subc{. a.z2.cc.z1.z4.s32 }.b32 subc. x2.CF).z4.y1. sub.cc.u32.cc.b32 subc. . 2010 .z3.y3.CF No integer rounding modifiers.cc Subract one value from another. x3.y1.3. Supported on all target architectures.y4. Introduced in PTX ISA version 1. Behavior is the same for unsigned and signed integers.type d.b32 subc. . b.y2. . Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.3.type = {. . d = a – b. borrow-out written to CC. Behavior is the same for unsigned and signed integers. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.z2. if .cc.type d.cc.0 Table 26. a.b32 subc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.type = { . x4.b32 subc.cc. No saturation.(b + CC. @p @p @p @p sub. with borrow-out. Supported on all target architectures. x4.b32 x1.cc.z3.y3.cc Syntax Integer Arithmetic Instructions: sub.s32 }. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.cc}. Introduced in PTX ISA version 1.y2.y4. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.b32 subc.u32.

then d is twice as wide as a and b to receive the full result of the multiplication.fxs.type = { . b. 2010 67 . mul Syntax Integer Arithmetic Instructions: mul Multiply two values.lo.0>. .hi. .wide is specified.s64 }. t = a * b.wide // for . Supported on all target architectures. If . . .hi or .s32 z. n = bitwidth of type. The ..u32. a. Instruction Set Table 28. creates 64 bit result January 24.u64.0.n>.wide}. mul{. mul.type d. . Description Semantics Compute the product of two values. d = t. mul.s16 fa. mul. // 16*16 bits yields 32 bits // 16*16 bits. and either the upper or lower half of the result is written to the destination register. save only the low 16 bits // 32*32 bits.s32.hi variant // for .Chapter 8. If .y.wide.fys.fys. . // for .x. d = t<n-1.fxs. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo variant Notes The type of the operation represents the types of the a and b operands.lo. d = t<2n-1. then d is the same size as a and b.lo is specified..s16 fa.and 32-bit integer types.wide.u16..s16..wide suffix is supported only for 16.

a. // for .. b. If . 68 January 24.b. The .wide // for . mad{. If .lo is specified.MAXINT (no overflow) for the size of the operation. . then d and c are twice as wide as a and b to receive the result of the multiplication.p.u32. Description Semantics Multiplies two values and adds a third. b. d.u16. @p mad.sat limits result to MININT.s32. Saturation modifier: . t<2n-1.PTX ISA Version 2.sat. and either the upper or lower half of the result is written to the destination register. .s32 r. t<n-1.c.lo variant Notes The type of the operation represents the types of the a and b operands.s16.type mad.wide}..hi.lo.hi. . c.q.hi mode.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 2010 . c.lo.r.hi variant // for . a. and then writes the resulting value into a destination register. Supported on all target architectures.0. .and 32-bit integer types. t n d d d = = = = = a * b.s64 }. a.lo. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. Applies only to ... .type = { . t + c.u64. .n> + c.0> + c.wide suffix is supported only for 16.0 Table 29.s32 d.hi or . then d and c are the same size as a and b.s32 type in .wide is specified.s32 d. mad. bitwidth of type.

// for . January 24. . d = t<47. mul24. 48bits. d = t<31. mul24.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.e. a.type = { .a.16>..hi may be less efficient on machines without hardware support for 24-bit multiply. All operands are of the same type and size..Chapter 8. and return either the high or low 32-bits of the 48-bit result.type d. Supported on all target architectures. mul24{. // low 32-bits of 24x24-bit signed multiply. Instruction Set Table 30.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result. 2010 69 .s32 d.lo}.hi variant // for . mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.hi. t = a * b.. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.u32. i.lo. mul24.b.0>.0. b.s32 }. .

d = t<31.lo}.hi.hi variant // for . mad24.s32 d. c.sat limits result of 32-bit signed addition to MININT. Description Compute the product of two 24-bit integer values held in 32-bit source registers. . Applies only to .MAXINT (no overflow). and add a third.u32. b. mad24.c.PTX ISA Version 2. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. Saturation modifier: ...16> + c.sat. d.0 Table 31.0. All operands are of the same type and size.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value.b. c. d = t<47.hi. a. 2010 . t = a * b.type = { .s32 d.a. 32-bit value to either the high or low 32-bits of the 48-bit result. // low 32-bits of 24x24-bit signed multiply. mad24. // for .. mad24.type mad24. mad24{. . b.lo. 70 January 24.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value..e. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.hi may be less efficient on machines without hardware support for 24-bit multiply.s32 }.0> + c. Supported on all target architectures. i. Return either the high or low 32-bits of the 48-bit result. a. 48bits.s32 type in .hi mode.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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clz.PTX ISA Version 2. .type = { . } Introduced in PTX ISA version 2.b64 d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. d = 0. } while (d < max && (a&mask == 0) ) { d++.b64 }.u32 Semantics 74 January 24. popc.b32 popc. a.b64 type. while (a != 0) { if (a&0x1) d++. .b32. mask = 0x8000000000000000.type == . a. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d.type d. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. a. inclusively.0. X. popc.b32.type = { . } else { max = 64.b64 d. X. a. For . // cnt is .0.u32 PTX ISA Notes Target ISA Notes Examples Table 40. // cnt is . For .0 Table 39. d = 0. 2010 . cnt. cnt. popc requires sm_20 or later.b32 clz. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. mask = 0x80000000. popc Syntax Integer Arithmetic Instructions: popc Population count. the number of leading zeros is between 0 and 64.type d.b32 type. if (.b64 }. a = a << 1.b32) { max = 32. . inclusively. clz requires sm_20 or later. clz. . the number of leading zeros is between 0 and 32. a = a >> 1.

s32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. If . for (i=msb.u32 || . Instruction Set Table 41.s64 cnt. 2010 75 . For unsigned integers.u32 January 24. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. bfind requires sm_20 or later. bfind returns 0xFFFFFFFF if no non-sign bit is found. For signed integers. a. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. .type = { .u32.s32) ? 31 : 63. X. d. break. d = -1.shiftamt is specified.shiftamt && d != -1) { d = msb . a. // cnt is .type d.u32. a.type==. i>=0.u64. bfind.shiftamt. and operand d has type .Chapter 8.s64 }. Semantics msb = (. bfind returns the bit position of the most significant “1”.shiftamt. Operand a has the instruction type.type bfind. . i--) { if (a & (1<<i)) { d = i. bfind. .type==. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.0. . bfind. Description Find the bit position of the most significant non-sign bit in a and place the result in d. } } if (.u32 d.d.

76 January 24. 2010 . Description Semantics Perform bitwise reversal of input.b32. i<=msb.b64 }.b32 d. for (i=0. a. . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { . brev.type d. msb = (.b32) ? 31 : 63.type==.PTX ISA Version 2. a. brev. brev Syntax Integer Arithmetic Instructions: brev Bit reverse. i++) { d[i] = a[msb-i].0 Table 42. brev requires sm_20 or later. .0.

pos = b. bfe.s32.s32) ? 31 : 63. otherwise If the bit field length is zero. b. Instruction Set Table 43.len. a. .Chapter 8. .u64.type==.u64 || len==0) sbit = 0.type==.0.u32 || . . 2010 77 .u32. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 d. c.msb)]. and operands b and c are type . If the start position is beyond the msb of the input.u32.u32 || .type==. else sbit = a[min(pos+len-1. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit. The destination d is padded with the sign bit of the extracted field. bfe requires sm_20 or later. . if (. Semantics msb = (. January 24. the destination d is filled with the replicated sign bit of the extracted field. . d = 0. The sign bit of the extracted field is defined as: .s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.type==. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract.type d.start.a. the result is zero.type = { . len = c. i<=msb. . and source c gives the bit field length in bits.u64: .u32.s64 }. Description Extract bit field from a and place the zero or sign-extended result in d. for (i=0.s32. Source b gives the bit field starting bit position. bfe. Operands a and d have the same type as the instruction type.

type = { . and operands c and d are type .0 Table 44.b32. If the start position is beyond the msb of the input.b32) ? 31 : 63. Semantics msb = (. i<len && pos+i<=msb.PTX ISA Version 2. . bfi. Description Align and insert a bit field from a into b. and place the result in f. Operands a. for (i=0.u32. a. pos = c.type==. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. Source c gives the starting bit position for the insertion. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. c. . bfi. b. If the bit field length is zero.type f. d.start.b32 d. 78 January 24. b. bfi requires sm_20 or later. the result is b.len. and source d gives the bit field length in bits.0. i++) { f[pos+i] = a[i]. len = d. and f have the same type as the instruction type.b. f = b. 2010 . the result is b.b64 }.a.

For each byte in the target register. Instruction Set Table 45. . the four 4-bit values fully specify an arbitrary byte permute.mode = { . In the generic form (no mode specified). The bytes in the two source registers are numbered from 0 to 7: {b. Description Pick four arbitrary bytes from two 32-bit registers. . . the permute control consists of four 4-bit selection values.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. and reassemble them into a 32-bit destination register. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. prmt. b1. msb=0 means copy the literal value. b4}. b6.Chapter 8. b2.b1 source select c[7:4] d. a. msb=1 means replicate the sign. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).f4e.b2 source select c[11:8] d. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. as a 16b permute code. .b32{. . 2010 79 .mode} d. a 4-bit selection value is defined. b5. Note that the sign extension is only performed as part of generic form.ecr. a} = {{b7. default mode index d. {b3.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d.rc8. The msb defines if the byte value should be copied.ecl. b0}}.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. c. b.b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. Thus. .b4e.b3 source select c[15:12] d.rc16 }.

tmp64 ). r1. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[2]. tmp[23:16] = ReadByte( mode. tmp64 ). ctl[2] = (c >> 8) & 0xf.0 Semantics tmp64 = (b<<32) | a. r3.f4e r1. ctl[1] = (c >> 4) & 0xf. r4. } tmp[07:00] = ReadByte( mode. prmt requires sm_20 or later. 2010 . ctl[1]. r2. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3.0.b32 prmt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp64 ). r4. ctl[3]. tmp[15:08] = ReadByte( mode. prmt. tmp[31:24] = ReadByte( mode.PTX ISA Version 2. r2. ctl[3] = (c >> 12) & 0xf. tmp64 ). 80 January 24. r3.b32. ctl[0].

Chapter 8.7. Floating-Point Instructions Floating-point instructions operate on .f64 register operands and constant immediate values.f32 and .2. The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24. 2010 81 . Instruction Set 8.

sub.f64 {sin.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.min.32 and fma. Double-precision instructions support subnormal inputs and results.rcp. with NaNs being flushed to positive zero. The optional .approx. so PTX programs should not rely on the specific single-precision NaNs being generated.full.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.0.target sm_1x No rounding modifier.rp .rnd. sub. 82 January 24. . and mad support saturation of results to the range [0. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.approx.f32 {div.mul}. mul.f64 rsqrt. .lg2.rcp.approx.f64 are the same.rnd. Single-precision add.rnd.f32 rsqrt.rnd.sub.sat Notes If no rounding modifier is specified.rnd.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. Note that future implementations may support NaN payloads for single-precision instructions.f64 div.target sm_20 mad.cos.fma}.rz .target sm_20 .f32 {div.rm . No rounding modifier. 1. Instruction Summary of Floating-Point Instructions .PTX ISA Version 2.mul}.max}.f32 .neg.neg.sqrt}.rnd.min.ex2}.f64 mad.fma}. default is .sqrt}. {add.rn .0].ftz . default is .f32 are the same.f64 and fma. {mad. 2010 .rcp.f32 {abs. but single-precision instructions return an unspecified NaN.f32 {div.0 The following table summarizes floating-point instructions in PTX.f32 {mad.f64 {abs.rn and instructions may be folded into a multiply-add.f32 {add.max}.rn and instructions may be folded into a multiply-add. Table 46.sqrt}. NaN payloads are supported for double-precision instructions. If no rounding modifier is specified.approx.

Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.finite testp.type d. testp requires sm_20 or later.f32.normal.f64 }. January 24. copysign.infinite. a. // result is .f32 copysign. testp Syntax Floating-Point Instructions: testp Test floating-point property. y. copysign requires sm_20 or later.normal testp. .f32.op. testp.infinite. X. .pred = { . not infinity) As a special case.infinite testp.number. testp. b. . true if the input is a subnormal number (not NaN. . a. 2010 83 .Chapter 8. .f64 x. positive and negative zero are considered normal numbers.finite. not infinity).notanumber. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. f0. Introduced in PTX ISA version 2.notanumber testp. B. and return the result as d.type = { . C.subnormal }. testp. . .type .0. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. A. Table 48. . z.f32 testp.f64 isnan.number testp. . Instruction Set Table 47.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.0. copysign.type = { . p.notanumber.op p. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.f64 }.

1. add. Saturation modifier: .f64 supports subnormal numbers. . . requires sm_20 Examples @p add.f32. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.f64 d.f2.ftz. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 requires sm_13 or later.sat. Rounding modifiers (default is .PTX ISA Version 2.rn. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. .f32 clamps the result to [0. d. add. b.rn. b.rm. d = a + b. sm_1x: add.f32 f1.f3. a.rnd}{. Description Semantics Notes Performs addition and writes the resulting value into a destination register. add.rp for add.rz.rz.f32 add{.f64.f32 flushes subnormal inputs and results to sign-preserving zero. An add instruction with an explicit rounding modifier treated conservatively by the code optimizer. requires sm_13 for add. 84 January 24. In particular.rm mantissa LSB rounds towards negative infinity .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz available for all targets .ftz.ftz}{.sat}. . subnormal numbers are supported. Rounding modifiers have the following target requirements: .f32 supported on all target architectures. NaN results are flushed to +0.f32 flushes subnormal inputs and results to sign-preserving zero. add.rnd}.0.rn): . . . add Syntax Floating-Point Instructions: add Add two values.rp }.0f. 2010 . a.rn mantissa LSB rounds to nearest even . add. add{.0.0].0 Table 49.rm.rnd = { .rz mantissa LSB rounds towards zero .

rz available for all targets .f3. requires sm_20 Examples sub. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. sub.f32 flushes subnormal inputs and results to sign-preserving zero. b.rm mantissa LSB rounds towards negative infinity . d.f32 supported on all target architectures.rm.0]. d = a . sub{. a.rn mantissa LSB rounds to nearest even .rn): .f32 sub{. .rnd = { .0f.Chapter 8.f2.rp }. . Rounding modifiers have the following target requirements: . sub.a.rn.ftz.f32 c. In particular.rz mantissa LSB rounds towards zero . b. sm_1x: sub.rp for sub. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. Saturation modifier: sub.rz.b. subnormal numbers are supported. . sub.rnd}.b.f64 requires sm_13 or later.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.sat}. 2010 85 .f64 d.rn.f32 flushes subnormal inputs and results to sign-preserving zero. .f32 clamps the result to [0. sub Syntax Floating-Point Instructions: sub Subtract one value from another. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sub. . NaN results are flushed to +0. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f32 f1. sub.f32.rnd}{. January 24.f64.f64 supports subnormal numbers.ftz. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_13 for sub. .0.sat.rm.0. Rounding modifiers (default is . Instruction Set Table 50. a. 1.rn.ftz}{.

d. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. subnormal numbers are supported. In particular.rn): .rnd = { . sm_1x: mul.f32.rz mantissa LSB rounds towards zero . b. all operands must be the same size.rn mantissa LSB rounds to nearest even . .0. NaN results are flushed to +0. mul Syntax Floating-Point Instructions: mul Multiply two values.0 Table 51. mul. Saturation modifier: mul.rm mantissa LSB rounds towards negative infinity .rp for mul. Rounding modifiers (default is . d = a * b.ftz. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.pi // a single-precision multiply 86 January 24. 2010 .f64 d.rnd}.f32 clamps the result to [0. .ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .0].sat.f32 circumf.f32 flushes subnormal inputs and results to sign-preserving zero.rnd}{. . requires sm_13 for mul. .f64.rn. mul{.sat}.rz available for all targets .0.rz. b. a. .f32 mul{. 1. mul. requires sm_20 Examples mul.ftz}{.f32 supported on all target architectures. For floating-point multiplication.f32 flushes subnormal inputs and results to sign-preserving zero. mul. Description Semantics Notes Compute the product of two values. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f64 requires sm_13 or later.PTX ISA Version 2. Rounding modifiers have the following target requirements: .rp }.f64 supports subnormal numbers.radius.rm. mul.rm.0f.rn. a. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device.

f32 introduced in PTX ISA version 2.f64.ftz}{. fma. .rm mantissa LSB rounds towards negative infinity . d. b. fma.f64 introduced in PTX ISA version 1. again in infinite precision. Rounding modifiers (no default): . PTX ISA Notes Target ISA Notes Examples January 24. d.rp }. 2010 87 . @p fma.rz mantissa LSB rounds towards zero .rnd.rn mantissa LSB rounds to nearest even .f64 requires sm_13 or later.rnd.z. sm_1x: fma.a. again in infinite precision.0f. The resulting value is then rounded to single precision using the rounding mode specified by .rn.4.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 computes the product of a and b to infinite precision and then adds c to this product.Chapter 8.f64 w. .ftz. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. . NaN results are flushed to +0.b.rnd{.f32 is unimplemented in sm_1x.f64 supports subnormal numbers.f32 fma.sat.c. Saturation: fma.rn.f64 is the same as mad.f32 requires sm_20 or later. fma. fma.rn. fma. b. c.y. d = a*b + c.rnd = { .rnd. c.0. The resulting value is then rounded to double precision using the rounding mode specified by .f32 flushes subnormal inputs and results to sign-preserving zero. fma. subnormal numbers are supported. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma.rz.f32 computes the product of a and b to infinite precision and then adds c to this product. a. fma.sat}. 1.ftz.x.f32 clamps the result to [0. a.f64 d.0.f32 fma. . fma. Instruction Set Table 52.0]. fma.rm.

rn mantissa LSB rounds to nearest even . b.f64 d.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. mad. a. and then writes the resulting value into a destination register.sat}. // . When JIT-compiled for SM 2. again in infinite precision.rnd = { .rnd. again in infinite precision. the treatment of subnormal inputs and output follows IEEE 754 standard.ftz.rnd{. Rounding modifiers (no default): .f64}. fma. and then the mantissa is truncated to 23 bits. mad.f64 computes the product of a and b to infinite precision and then adds c to this product.f32 flushes subnormal inputs and results to sign-preserving zero. The resulting value is then rounded to single precision using the rounding mode specified by .ftz. NaN results are flushed to +0. c.target sm_20: mad.rz mantissa LSB rounds towards zero . sm_1x: mad. 2010 .f32 computes the product of a and b to infinite precision and then adds c to this product.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. where the mantissa can be rounded and the exponent will be clamped.target sm_20 d.f64} is the same as fma.rn.0f. a.f32 flushes subnormal inputs and results to sign-preserving zero.f64 is the same as fma. b. The resulting value is then rounded to double precision using the rounding mode specified by .0 Table 53. mad{.0. The resulting value is then rounded to double precision using the rounding mode specified by .rnd.rp }.sat.rm. Saturation modifier: mad. // . Description Semantics Notes Multiplies two values and adds a third.target sm_1x d. .rnd.{f32. In this case.sat}. Note that this is different from computing the product with mul.0]. 1. . c.ftz}{. For . 88 January 24.ftz}{.f32 computes the product of a and b at double precision.f32 is when c = +/-0.{f32. d = a*b + c. mad.f64 supports subnormal numbers.0. a. c. mad.f64 computes the product of a and b to infinite precision and then adds c to this product. Unlike mad.0 devices.f32). b. // .rnd. but the exponent is preserved.rn. mad.f32 clamps the result to [0..target sm_1x: mad.target sm_13 and later .f32 mad.rz. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. The exception for mad.f32 is implemented as a fused multiply-add (i. mad. mad. subnormal numbers are supported. mad. .f64.PTX ISA Version 2. mad. again in infinite precision.f32.f32 is identical to the result computed using separate mul and add instructions. For .rm mantissa LSB rounds towards negative infinity .f32 mad.e.

Chapter 8. a rounding modifier is required for mad.rn. Legacy mad.f32 for sm_20 targets. Target ISA Notes mad.0 and later. requires sm_13 .c. Rounding modifiers have the following target requirements: .f32 supported on all target architectures.a. 2010 89 .rp for mad.rn..f64 instructions having no rounding modifier will map to mad.f32 d..f64 requires sm_13 or later. In PTX ISA versions 1.rm.rn. January 24.0.f64.f64..rz.. a rounding modifier is required for mad.f32.rz.. In PTX ISA versions 2.f64.b.4 and later.. mad. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rm.rp for mad. requires sm_20 Examples @p mad.

rn. // // // // fast. . Description Semantics Notes Divides a by b.full.rn. a. For PTX ISA version 1.f64 supports subnormal numbers.f32 div. d = a / b.f64.f32 defaults to div. a.full{.circum. subnormal numbers are supported. and rounding introduced in PTX ISA version 1.approx. div. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding .f32 div.ftz}. div.approx{.f64 introduced in PTX ISA version 1. div.f32 div. or . div.f32 flushes subnormal inputs and results to sign-preserving zero. approximate single-precision divides: div.ftz.approx. b. z.{rz. b. full-range approximation that scales operands to achieve better accuracy. the maximum ulp error is 2. . For b in [2-126. one of .rp }. b. . a.rn mantissa LSB rounds to nearest even .f64 requires sm_13 or later.f32 implements a fast approximation to divide.full.f32 implements a relatively fast.rnd{.approx.rn.approx.f64 d. but is not fully IEEE 754 compliant and does not support rounding modifiers. div.ftz.approx.approx.14159.0 through 1. and div. b. yd.f32 supported on all target architectures. div. Subnormal inputs and results are flushed to sign-preserving zero.4 and later.rm.rm.3.f32 and div. sm_1x: div. Fast. The maximum ulp error is 2 across the full range of inputs. .rp}. d. For PTX ISA versions 1.f32 div. 2126].f32 requires sm_20 or later. .full.f32. PTX ISA Notes div.rz.rm mantissa LSB rounds towards negative infinity .rnd is required. div.f64 diam.f32 and div.0 Table 54. div.ftz. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .4.f32 div. xd.rz mantissa LSB rounds towards zero . stores result in d. x. Examples 90 January 24.ftz.rn. approximate division by zero creates a value of infinity (with same sign as a). a. y.f64 defaults to div.ftz}. d.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd. d. Target ISA Notes div.PTX ISA Version 2. div.full. zd.f64 requires sm_20 or later. . 2010 . Fast.full. computed as d = a * (1/b).0. div Syntax Floating-Point Instructions: div Divide one value by another.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.rnd = { .rnd.3.ftz. Explicit modifiers .

f32 x. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. neg.f32 flushes subnormal inputs and results to sign-preserving zero. abs{. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero. Subnormal numbers: sm_20: By default. abs. sm_1x: neg. neg.Chapter 8. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate. a.f64 supports subnormal numbers. Table 56. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. d = |a|.ftz. Negate the sign of a and store the result in d.f64 requires sm_13 or later.f32 neg. January 24.0. Take the absolute value of a and store the result in d.ftz.ftz}. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Instruction Set Table 55.ftz. subnormal numbers are supported. neg{. subnormal numbers are supported.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: abs. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. a. d.f32 supported on all target architectures. NaN inputs yield an unspecified NaN. abs.f32 supported on all target architectures.0.f0. neg.f32 flushes subnormal inputs and results to sign-preserving zero. d = -a. a. abs. NaN inputs yield an unspecified NaN.f64 requires sm_13 or later.ftz. a. Subnormal numbers: sm_20: By default.ftz}. abs. neg. abs.f64 supports subnormal numbers. 2010 91 .f32 abs.f0.f32 x. d. neg.f64 d.

min.f64 f0.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. 2010 . Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b.f64 supports subnormal numbers.f32 max.x. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. Store the minimum of a and b in d. sm_1x: max.0 Table 57. @p min. min.ftz}. d. subnormal numbers are supported. a. Store the maximum of a and b in d. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. sm_1x: min. b.ftz. a.f32 min. a. max. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. a. d d d d = = = = NaN. max.f32 flushes subnormal inputs and results to sign-preserving zero. (a < b) ? a : b. a.f32 flushes subnormal inputs and results to sign-preserving zero.c. d d d d = = = = NaN.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. min. max. a.0. max.c. d.f32 max. max.b. min{.f64 supports subnormal numbers. b. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.f64 z. min.ftz. 92 January 24. (a > b) ? a : b.ftz.f64 requires sm_13 or later. b.ftz}.PTX ISA Version 2. a. b.0. b.f2. a. Table 58.f64 d.f32 supported on all target architectures. b.z. subnormal numbers are supported. max{. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 requires sm_13 or later.f32 supported on all target architectures.f1.f32 min.

ftz.rp }. rcp.rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.approx.rp}. .0 +subnormal +Inf NaN Result -0.rn.f64 d.0.approx{. xi.0 -Inf -Inf +Inf +Inf +0.f64. d = 1 / a.rm.Chapter 8.f64 introduced in PTX ISA version 1. a. xi. rcp.ftz}.f32 rcp.rn.f64 requires sm_13 or later.0.approx and .rnd{.f32 flushes subnormal inputs and results to sign-preserving zero.x.ftz. The maximum absolute error is 2-23.0 over the range 1.rnd.ftz}.f32 supported on all target architectures. rcp. 2010 93 . Input -Inf -subnormal -0. .f32 defaults to rcp.rn. a.rn.ftz were introduced in PTX ISA version 1.f64 and explicit modifiers .ftz.0 through 1.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . Description Semantics Notes Compute 1/a.f32 requires sm_20 or later.rnd is required. subnormal numbers are supported.4 and later.rm. For PTX ISA version 1. one of .x.0.f32 implements a fast approximation to reciprocal. rcp. a.4. // fast. rcp. General rounding modifiers were added in PTX ISA version 2.f64 defaults to rcp.r.f64 supports subnormal numbers. rcp. For PTX ISA versions 1.0-2. Examples January 24. d. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .{rz. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rz. PTX ISA Notes rcp. store result in d.f32 rcp. .approx or .f64 requires sm_20 or later. rcp.3.approx.f32 rcp.rnd = { . Target ISA Notes rcp. rcp. and rcp.f32 and rcp.rm mantissa LSB rounds towards negative infinity .rn.rz mantissa LSB rounds towards zero .f32 rcp. sm_1x: rcp. rcp. d.rn mantissa LSB rounds to nearest even . Instruction Set Table 59.f32.f32 flushes subnormal inputs and results to sign-preserving zero.f64 ri.0 +0.approx.approx.rnd. rcp.ftz.

0. sqrt. // fast.rn. General rounding modifiers were added in PTX ISA version 2.0 through 1.0 +0.f32 sqrt. a. r. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value. // IEEE 754 compliant rounding .f32 flushes subnormal inputs and results to sign-preserving zero.rp}. sqrt.rz.rn.f64 and explicit modifiers . r.PTX ISA Version 2.f32 and sqrt. sqrt. . Target ISA Notes sqrt. . sqrt. Input -Inf -normal -subnormal -0.rn.approx. sqrt.f64 supports subnormal numbers.ftz.ftz.f64 r.f32 is TBD. // IEEE 754 compliant rounding d.ftz}.rnd = { .f64 introduced in PTX ISA version 1. The maximum absolute error for sqrt.rp }.approx or .0 -0.x. sqrt. sqrt.ftz were introduced in PTX ISA version 1. sqrt.approx{. d = sqrt(a).f32 supported on all target architectures.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): .f64.rn mantissa LSB rounds to nearest even .rnd is required.f32 sqrt.approx and .0 +subnormal +Inf NaN Result NaN NaN -0.f64 d. approximate square root d. one of .f64 requires sm_20 or later.rm.f32 requires sm_20 or later.x.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. . subnormal numbers are supported.f64 requires sm_13 or later. sm_1x: sqrt. and sqrt. For PTX ISA versions 1.f32 defaults to sqrt.approx.{rz.approx. a.rz mantissa LSB rounds towards zero . a.f32 implements a fast approximation to square root.rm.approx. Description Semantics Notes Compute sqrt(a). For PTX ISA version 1.rn.f64 defaults to sqrt.f32 sqrt.ftz.0.rn. 2010 . store in d.rnd{.0 +0.rnd.0 Table 60.0 +0.ftz.f32 sqrt. PTX ISA Notes sqrt. sqrt.4.ftz}.3. Examples 94 January 24.rnd. sqrt.4 and later.rm mantissa LSB rounds towards negative infinity .approx.f32.rn.f32 flushes subnormal inputs and results to sign-preserving zero.x.

f64 were introduced in PTX ISA version 1.0.0.f32 is 2-22.f64 d. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.f32. The maximum absolute error for rsqrt.4 and later. ISR.0 through 1.f64 isr.f32 rsqrt.approx. a.approx{. X.f32 rsqrt. PTX ISA Notes rsqrt.f64 defaults to rsqrt. Subnormal numbers: sm_20: By default.4 over the range 1.f64 is TBD.f32 defaults to rsqrt.ftz were introduced in PTX ISA version 1.4.approx. x.f32 and rsqrt. d = 1/sqrt(a).approx. Compute 1/sqrt(a).f64. Instruction Set Table 61. the .approx and . Note that rsqrt. d. a. rsqrt. subnormal numbers are supported.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. rsqrt. Input -Inf -normal -subnormal -0. For PTX ISA version 1. rsqrt. For PTX ISA versions 1.f32 supported on all target architectures.approx. sm_1x: rsqrt. January 24.3.0-4. rsqrt.0 +0.f32 flushes subnormal inputs and results to sign-preserving zero. rsqrt.f64 requires sm_13 or later.ftz. Explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero.approx implements an approximation to the reciprocal square root.ftz. 2010 95 .ftz}.f64 is emulated in software and are relatively slow. store the result in d. Target ISA Notes Examples rsqrt.ftz.f64 supports subnormal numbers. rsqrt.approx. and rsqrt.approx modifier is required.approx.Chapter 8. rsqrt.0 NaN The maximum absolute error for rsqrt.

a.ftz introduced in PTX ISA version 1. subnormal numbers are supported.approx{. sin.ftz.approx and . For PTX ISA versions 1.PTX ISA Version 2. a. 96 January 24.ftz}.0 -0.approx modifier is required.approx.0.0 +0.approx. the .0 +0.0 +subnormal +Inf NaN Result NaN -0.ftz.9 in quadrant 00. sin. PTX ISA Notes sin.ftz.3.4.f32 introduced in PTX ISA version 1. Explicit modifiers . sin.0 through 1.f32 d. sm_1x: Subnormal inputs and results to sign-preserving zero. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.0 +0.0 NaN NaN The maximum absolute error is 2-20.f32 flushes subnormal inputs and results to sign-preserving zero. sin.f32 sa. Find the sine of the angle a (in radians).approx.f32 implements a fast approximation to sine. Input -Inf -subnormal -0. d = sin(a). Subnormal numbers: sm_20: By default. For PTX ISA version 1.f32. 2010 . sin. Target ISA Notes Examples Supported on all target architectures.4 and later.f32 defaults to sin.0 Table 62.

2010 97 .approx.0 +subnormal +Inf NaN Result NaN +1.0 +1.f32 d. Target ISA Notes Examples Supported on all target architectures. cos. cos.ftz}.0 +1.3.ftz introduced in PTX ISA version 1. For PTX ISA versions 1.approx.approx modifier is required.ftz.ftz. d = cos(a).9 in quadrant 00. cos. January 24.4 and later.f32 defaults to cos. cos. sm_1x: Subnormal inputs and results to sign-preserving zero. a.0 through 1. Find the cosine of the angle a (in radians).0.approx{.f32 ca.0 +0. Explicit modifiers . subnormal numbers are supported.4.f32. a.f32 flushes subnormal inputs and results to sign-preserving zero. cos. the .f32 introduced in PTX ISA version 1. Subnormal numbers: sm_20: By default.0 +1. Instruction Set Table 63. For PTX ISA version 1.ftz.0 NaN NaN The maximum absolute error is 2-20.approx and .approx.Chapter 8. Input -Inf -subnormal -0.f32 implements a fast approximation to cosine. PTX ISA Notes cos. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.

d = log(a) / log(2).approx. Input -Inf -subnormal -0.PTX ISA Version 2.ftz. PTX ISA Notes lg2.f32. 98 January 24.approx. 2010 .4 and later.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. lg2.0 Table 64. Target ISA Notes Examples Supported on all target architectures.f32 Determine the log2 of a.ftz.ftz introduced in PTX ISA version 1. sm_1x: Subnormal inputs and results to sign-preserving zero.approx.f32 implements a fast approximation to log2(a). Explicit modifiers . lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value. a.0 +0. a. lg2. lg2.f32 la.ftz}. subnormal numbers are supported.4. lg2.f32 defaults to lg2.approx and .3.f32 introduced in PTX ISA version 1.approx modifier is required.6 for mantissa.0 through 1.ftz. lg2. For PTX ISA version 1. The maximum absolute error is 2-22.0.f32 flushes subnormal inputs and results to sign-preserving zero.approx{. the . For PTX ISA versions 1. Subnormal numbers: sm_20: By default.

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

i. lt.CmpOp{. hi. ge. Subnormal numbers: sm_20: By default. ge.f64 }.a. To aid comparison operations in the presence of NaN values. gt. le. .dtype. leu.B) is one of: and. lt.b64. setp. respectively.s32. For unsigned values.type setp. geu.u32. setp.f64 source type requires sm_13 or later. higher. ne.u32 p|q. and higher-or-same may be used instead of lt. and nan returns true if either operand is NaN. ltu.s32 setp. leu.s64. bit-size comparisons are eq and ne. geu.ftz}.s16.f32 flushes subnormal inputs to sign-preserving zero. {!}c. c).b16. . b. . . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. @q setp.pred variables. . c). hs equ. a.ftz}. Integer Notes Floating Point Notes The ordered comparisons are eq. and can be one of: eq. ne. Semantics t = (a CmpOp b) ? 1 : 0.n. or. ls.and. le. loweror-same. ge.f64 supports subnormal numbers. lt. gt. ls. then these comparisons have the same result as their ordered counterparts. 2010 .ftz. p[|q]. num.0 Table 67. hi.u64.dtype. le.b. num returns true if both operands are numeric values (not NaN). neu. . neu.CmpOp. ltu. This result is written to the first destination operand. a. gtu. The destinations p and q must be . le. If either operand is NaN. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. If either operand is NaN. q = BoolOp(!t. gtu. b.ftz applies only to .lt. and hs for lower. the comparison operators lo. The untyped. ge.f32. ne. lo. setp. p[|q]. p = BoolOp(t. If both operands are numeric values (not NaN). the result is false.PTX ISA Version 2. unordered versions are included: equ. setp with . and (optionally) combine this result with a predicate value by applying a Boolean operator.u16. then the result of these comparisons is true. nan The Boolean operator BoolOp(A.dtype. xor.f32 comparisons. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. A related value computed using the complement of the compare result is written to the second destination operand. gt. Applies to all numeric types. . subnormal numbers are supported.type = { . Modifier . 102 January 24.0. sm_1x: setp. The comparison operator is a suffix on the instruction. . . .BoolOp{.type .eq. p. The signed and unsigned comparison operators are eq.f32 flushes subnormal inputs to sign-preserving zero. gt.b32.r.

s32 slct{.s64. a. .f32 comparisons. Subnormal numbers: sm_20: By default.u32. b.ftz applies only to . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. based on the value of the predicate source operand.b64.u16. the comparison is unordered and operand b is selected.f64 requires sm_13 or later. a is stored in d. c.f32 comparisons.ftz. slct.u32. .b32.u64.b32.x.b64.ftz}.u32.dtype.type d. subnormal numbers are supported. c.f32 flushes subnormal values of operand c to sign-preserving zero. c.ftz. d. . If operand c is NaN. If c ≥ 0. val. .Chapter 8.s64. . operand c must match the second instruction type. . . B.f32.s16. 2010 103 . Operands d. a.f32 flushes subnormal values of operand c to sign-preserving zero. Table 69. .0.f64 }.dtype. For . Description Conditional selection.g. d = (c >= 0) ? a : b.dtype = { . . slct. selp. . selp Syntax Comparison and Selection Instructions: selp Select between source operands. and b must be of the same type. .u64.s16. sm_1x: slct. and operand a is selected.xp. based on the sign of the third operand.u64. selp.p. . . .type = { .b16. a is stored in d. If c is True. slct.s32. Instruction Set Table 68.f64 requires sm_13 or later. .f32 A. negative zero equals zero. C.f32.r. . a. . slct Syntax Comparison and Selection Instructions: slct Select one source operand.s32. a. .s32 x.t. Operand c is a predicate. .dtype. d = (c == 1) ? a : b. fval. . Operands d. The selected input is copied to the output without modification. . @q selp.u16. b. Modifier . .dtype. and operand a is selected.f32 r0. y. b otherwise. slct. f0.f32 d.0. Semantics Floating Point Notes January 24. a. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection.s32 selp. Introduced in PTX ISA version 1.b16. and b are treated as a bitsize type of the same width as the first instruction type. z. b. otherwise b is stored in d. slct.f64 }.

7. provided the operands are of the same size. Instructions and. or. and not also operate on predicates. performing bit-wise operations on operands of any type.0 8. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. xor. This permits bit-wise operations on floating point values without having to define a union to access the bits. 2010 .4. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.PTX ISA Version 2.

The size of the operands must match. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b. and Syntax Logic and Shift Instructions: and Bitwise AND. .type d.b64 }.0. sign. a. b. January 24. Allowed types include predicate registers. d = a | b. . or Syntax Logic and Shift Instructions: or Bitwise OR. but not necessarily the type.r.pred p.b32 mask mask.b32. b.b16.type = { . but not necessarily the type. 2010 105 . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. Introduced in PTX ISA version 1. . Table 71.pred. . and.0x80000000. Allowed types include predicate registers.0.pred.0x00010001 or. . Supported on all target architectures.b64 }.b32 x.b32 and. The size of the operands must match. .type = { .Chapter 8.type d. . Supported on all target architectures.q. or.b16.fpvalue. a. or. d = a & b.q. Introduced in PTX ISA version 1. and. Instruction Set Table 70.b32. .r.

The size of the operands must match.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a.b32. . Supported on all target architectures.b16. b. one’s complement. . not. 2010 .b16. not.pred. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). Supported on all target architectures. Allowed types include predicate registers.b32 d.b16. xor.type d.type = { . . cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation. The size of the operands must match. not. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.type = { . 106 January 24.b32 mask. a.b64 }. but not necessarily the type.x. Table 74.a. Allowed types include predicates.0. . not Syntax Logic and Shift Instructions: not Bitwise negation. . cnot.b32. .mask.pred p. Introduced in PTX ISA version 1.type d. but not necessarily the type. xor.r. d = a ^ b.b64 }. a.q. but not necessarily the type.0.b64 }. d = (a==0) ? 1 : 0.pred.0 Table 72. Introduced in PTX ISA version 1. a. . Table 73. .type = { . d. .PTX ISA Version 2. . Introduced in PTX ISA version 1. . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b16 d. cnot. The size of the operands must match. Supported on all target architectures.type d.0x0001. d = ~a.b32 xor.q.0.

. PTX ISA Notes Target ISA Notes Examples January 24. regardless of the instruction type. . Shift amounts greater than the register width N are clamped to N.u16. but not necessarily the type. Signed shifts fill with the sign bit. Supported on all target architectures. . shl. d = a >> b. a. unsigned and untyped shifts fill with 0.b16 c. Bit-size types are included for symmetry with SHL. a.b32. Shift amounts greater than the register width N are clamped to N. The b operand must be a 32-bit value.type = { . . Introduced in PTX ISA version 1. regardless of the instruction type. The b operand must be a 32-bit value.i.0. The sizes of the destination and first source operand must match.b64.a. . . d = a << b. shl.u32. sign or zero fill on left.b32.0. shr Syntax Logic and Shift Instructions: shr Shift bits right. .b16. . b.1. shr.j.type d.u64.s32. Supported on all target architectures. Instruction Set Table 75. 2010 107 . zero-fill on right.2. PTX ISA Notes Target ISA Notes Examples Table 76.type = { .a.s64 }. The sizes of the destination and first source operand must match.2. k. but not necessarily the type.Chapter 8. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b.type d. shl Syntax Logic and Shift Instructions: shl Shift bits left. b. .i.u16 shr. . Introduced in PTX ISA version 1.s16.b64 }. . .s32 shr.b16. i.b32 q. shr.

and from state space to state space. The cvta instruction converts addresses between generic and global.7.PTX ISA Version 2. local. mov. possibly converting it from one format to another. or shared state spaces. Instructions ld. 2010 . ld.0 8. and st operate on both scalar and vector types. suld. prefetchu isspacep cvta cvt 108 January 24. ldu. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. Data Movement and Conversion Instructions These instructions copy data from place to place. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. st. and sust support optional cache operations.5.

and cache only in the L2 cache. any existing cache lines that match the requested address in L1 will be evicted. Use ld. January 24. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld.Chapter 8.ca loads cached in L1. to allow the thread program to poll a SysMem location written by the CPU.ca. not L1). As a result of this request.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. likely to be accessed again.cv to a frame buffer DRAM address is the same as ld.lu Last use. Operator . Table 77. when applied to a local address. The compiler / programmer may use ld.cs) on global addresses.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. If one thread stores to global memory via one L1 cache. the cache operators have the following definitions and behavior.1. The ld.5.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. . if the line is fully covered. evict-first.7. and a second thread loads that address via a second L1 cache with ld.lu operation. .ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. Global data is coherent at the L2 level. . 2010 109 . Instruction Set 8. bypassing the L1 cache.cs. but multiple L1 caches are not coherent for global data. likely to be accessed once. fetch again). The driver must invalidate global L1 cache lines between dependent grids of parallel threads. A ld. The default load instruction cache operation is ld.cv Cache as volatile (consider cached system memory lines stale. The ld. .cg Cache at global level (cache in L2 and below.ca. it performs the ld. When ld.lu load last use operation. The ld.cs is applied to a Local window address. invalidates (discards) the local L1 line following the load. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.lu instruction performs a load cached streaming operation (ld.cg to cache loads only globally.0 introduces optional cache operators on load and store instructions. Cache Operators PTX 2.cs Cache streaming. rather than the data stored by the first thread. the second thread may get stale L1 cache data. The cache operators require a target architecture of sm_20 or later. The ld. For sm_20 and later.

0 Table 78. likely to be accessed once. .PTX ISA Version 2. and discard any L1 lines that match.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cg Cache at global level (cache in L2 and below. st. which writes back cache lines of coherent cache levels with normal eviction policy.wt. 2010 . 110 January 24. The st. rather than get the data from L2 or memory stored by the first thread. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. Operator . Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. The driver must invalidate global L1 cache lines between dependent grids of thread arrays.wb could write-back global store data from L1.ca loads. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. Global stores bypass L1. In sm_20. and cache only in the L2 cache.ca. not L1). to allow a CPU program to poll a SysMem location written by the GPU with st. The st. . but st. The default store instruction cache operation is st. However.wt store write-through operation applied to a global System Memory address writes through the L2 cache. and a second thread in a different SM later loads from that address via a different L1 cache with ld. . Addresses not in System Memory use normal write-back. Future GPUs may have globally-coherent L1 caches. If one thread stores to global memory.cg to cache global store data only globally.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.cs Cache streaming.cg is the same as st. regardless of the cache operation. and marks local L1 lines evict-first. the second thread may get a hit on stale L1 cache data. in which case st. bypassing its L1 cache.wb for global data.wt Cache write-through (to system memory).cg to local memory uses the L1 cache. bypassing the L1 cache. Use st.wb.

s32. mov.a.local. . local. . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.v.e. ptr.s16.type = { . u. the parameter will be copied onto the stack and the address will be in the local state space. k. Write register d with the value of a. . Introduced in PTX ISA version 1. Note that if the address of a device function parameter is moved to a register. mov.f32. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. the address of the variable in its state space) into the destination register. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. Instruction Set Table 79.type mov. d = sreg. or shared state space may be taken directly using the cvta instruction. avar. Description .u32 mov.b16. d..f32 mov. local. d.u16 mov.f32 mov. d. d = &label.type mov. For variables declared in . mov places the non-generic address of the variable (i. mov. a. // address is non-generic. . ptr. // get address of variable // get address of label or function . the generic address of a variable declared in global.e. . immediate.u32. or function name. .shared state spaces.const.0. .1. i. special register. and . local. label.f64 requires sm_13 or later.b32. d = &avar. .pred. myFunc. or shared state space. label.u16. Operand a may be a register. The generic address of a variable in global. A[5]. addr. . sreg.type d.s64. Take the non-generic address of a variable in global. A. alternately.type mov. Semantics d = a. . . 2010 111 .b64.global. variable in an addressable memory space.u32 d.u64.u32 mov. .Chapter 8. within the variable’s declared state space Notes Although only predicate and bit-size types are required.0.f64 }..

hi are . d. a[32.b16.u16 %x is a double. // // // // a..y.u8 // unpack 32-bit elements from . a[8.7]. d. Description Write scalar register d with the packed value of vector register a.0 Table 80.b32 { d.x | (a..b64 { d.y..b32. %r1.z. mov.w << 48) d = a.z.w << 24) d = a. d.type d.y } = { a[0.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.{a. a[32.31]. {lo.x | (a. a[24.b32 // pack four 16-bit elements into .y } = { a[0. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. a[16.w } = { a[0. {r. %x. a. d.w have type .x.b32 mov.a}.b64 }.b16 // pack four 8-bit elements into .z << 32) | (a.y << 16) | (a.15].y << 32) // pack two 8-bit elements into .x | (a.u32 x.47].23].y << 8) | (a.b16 { d.x.b32 mov....a have type .hi}. or write vector register d with the unpacked values from scalar register a.z.%r1. a[8.y } = { a[0. d. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.y. a[16. ..31].31] } // unpack 8-bit elements from .7].b have type .z.63] } // unpack 16-bit elements from .{x. .b32 { d. a[16.. lo.15] } // unpack 8-bit elements from .z << 16) | (a.b64 mov.31] } // unpack 16-bit elements from .15].b64 { d.15]..x | (a. d. For bit-size types.. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack). d.y << 8) d = a.0.b}. d.type = { .w}.b32 %r1.PTX ISA Version 2.g...w } = { a[0.b.x..b8 r.x.x | (a.g. . Semantics d = a.b32 // pack two 16-bit elements into .x. mov.y.b64 // pack two 32-bit elements into . Supported on all target architectures.y << 16) d = a..b. 2010 . a[48. d.b64 112 January 24.

f64 }.reg state space.volatile. ld.f64 using cvt.f32.b8.vec = { .type ld{.ca.volatile introduced in PTX ISA version 1. 2010 113 . ld introduced in PTX ISA version 1.volatile{.type ld. [a].s32. . Cache operations are not permitted with ld.vec. .ss}. . and then converted to . ld{. an address maps to global memory unless it falls within the local memory window or the shared memory window. perform the load using generic addressing. an address maps to the corresponding location in local or shared memory.u32.0. . [a].f16 data may be loaded using ld. .u64.b64. In generic addressing. .u8. or [immAddr] an immediate absolute byte address (unsigned. Description Load register variable d from the location specified by the source address operand a in specified state space. .param.volatile{.const.ss}{.Chapter 8. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .cg. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. . to enforce sequential consistency between threads accessing shared memory.v2.shared }.ss}..type = { . *(a+immOff). the resulting behavior is undefined. The address must be naturally aligned to a multiple of the access size. .e.ss = { . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .type . *(immAddr).e.cop = { . // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. PTX ISA Notes January 24. . 32-bit). an integer or bit-size type register reg containing a byte address. If no state space is given. Semantics d d d d = = = = a.global and . . Addresses are zero-extended to the specified width as needed.cs. If an address is not properly aligned.const space suffix may have an optional bank number to indicate constant banks other than bank zero. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.local. ld. . or the instruction may fault.b16. The .cop}. i.lu. for example. . The addressable operand a is one of: [avar] [areg] the name of an addressable variable var. . The address size may be either 32-bit or 64-bit. . Within these windows. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. The value loaded is sign-extended to the destination register width for signed integers. i.vec. . Instruction Set Table 81. . . This may be used. d. [a]. and is zeroextended to the destination register width for unsigned and bit-size types.v4 }.b16. A destination register wider than the specified type may be used. 32-bit).u16. [a]. *a. .b32.global.s64.f32 or .type d. d.s16.s8.cv }. Generic addressing may be used with ld. Generic addressing and cache operations introduced in PTX ISA 2.shared spaces to inhibit optimization of references to volatile memory.cop}.0. . . and truncated if the register width exceeds the state space address width for the target architecture.1.ss}{.volatile may be used with . . d.volatile. .

const[4]. d. // access incomplete array x.[a]. Generic addressing requires sm_20 or later. ld.[p+-8].b32 ld.global. x. // negative offset %r. %r.[buffer+64].s32 ld.[p+4].f32.b64 ld. // load .global.b32 ld. Cache operations require sm_20 or later.v4.b32 ld.[p].local.local. // immediate address %r. 2010 .f16 d.shared.[fs].[240].%r.b16 cvt.0 Target ISA Notes ld.f64 requires sm_13 or later.f32 ld. Q.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.PTX ISA Version 2.const.

u32. the access may proceed by silently masking off low-order address bits to achieve proper rounding.f64 requires sm_13 or later. perform the load using generic addressing. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.[p]. *a. ldu{. PTX ISA Notes Target ISA Notes Examples January 24. In generic addressing.global }.v4. The data at the specified address must be read-only.global.ss = { . 32-bit).Chapter 8. 2010 115 .v4 }.f32 Q. or [immAddr] an immediate absolute byte address (unsigned. . // load from address // vec load from address .type = { . and truncated if the register width exceeds the state space address width for the target architecture.v2. Addresses are zero-extended to the specified width as needed.reg state space.b32 d.. If an address is not properly aligned.ss}.s16. . [areg] a register reg containing a byte address.type ldu{.f64 }.b32.s32. .0. where the address is guaranteed to be the same across all threads in the warp. The address size may be either 32-bit or 64-bit. . Semantics d d d d = = = = a. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .vec.e. ldu. Within these windows. . 32-bit). *(a+immOff). an address maps to the corresponding location in local or shared memory. Introduced in PTX ISA version 2. or the instruction may fault. only generic addresses that map to global memory are legal.type d. and then converted to . // state space .u8.b16. If no state space is given. *(immAddr). The address must be naturally aligned to a multiple of the access size. and is zeroextended to the destination register width for unsigned and bit-size types. . i. The addressable operand a is one of: [avar] the name of an addressable variable var. ldu.s8.e.global.global. . .f16 data may be loaded using ldu.[p+4]. A register containing an address may be declared as a bit-size type or integer type. Instruction Set Table 82. The value loaded is sign-extended to the destination register width for signed integers. . ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. . ldu.b64. . . . ldu.b8. For ldu. [a].f64 using cvt. .f32 or . d. an address maps to global memory unless it falls within the local memory window or the shared memory window.u64. the resulting behavior is undefined. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space.s64. [a].f32.ss}.f32 d.u16. i.b16.[a]. A destination register wider than the specified type may be used.vec = { .

u16. st.vec . { . Generic addressing requires sm_20 or later. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.type [a]. A source register wider than the specified type may be used.volatile.b8. to enforce sequential consistency between threads accessing shared memory.f64 requires sm_13 or later. for example. .volatile introduced in PTX ISA version 1. If no state space is given.b16.e.1.ss}.0.global and . st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable.b32.cop}. or the instruction may fault. The address must be naturally aligned to a multiple of the access size.b64.ss}. st{.type st.cop}.b16.volatile may be used with . .s32.cs. an address maps to global memory unless it falls within the local memory window or the shared memory window.local.f32.ss}{. st.volatile. i.type . // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . an integer or bit-size type register reg containing a byte address. . [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. .f16 data resulting from a cvt instruction may be stored using st.0 Table 83.shared }. The addressable operand a is one of: [var] [reg] the name of an addressable variable var.s16. . 32-bit).vec. .v2. In generic addressing. . . perform the store using generic addressing.s64. st.. Cache operations require sm_20 or later. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. . the resulting behavior is undefined.type = = = = {. [a]. Cache operations are not permitted with st.cg. . If an address is not properly aligned. .ss}{.wb. The address size may be either 32-bit or 64-bit.global. .ss . { . Semantics d = a. . Generic addressing and cache operations introduced in PTX ISA 2. the access may proceed by silently masking off low-order address bits to achieve proper rounding.cop . . *(immAddr) = a. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.vec. .u32. .f64 }. .0. . b. Addresses are zero-extended to the specified width as needed.wt }. { .shared spaces to inhibit optimization of references to volatile memory. PTX ISA Notes Target ISA Notes 116 January 24. i.PTX ISA Version 2.u64. *d = a. 2010 . and truncated if the register width exceeds the state space address width for the target architecture.reg state space. st introduced in PTX ISA version 1. . [a].type st{.v4 }. This may be used. The lower n bits corresponding to the instruction-type width are stored to memory. b. an address maps to the corresponding location in local or shared memory. . Generic addressing may be used with st. b. *(d+immOffset) = a.s8.u8. b. Within these windows.e.volatile{.volatile{. 32-bit). or [immAddr] an immediate absolute byte address (unsigned.

f16. Instruction Set Examples st. [fs].local. // immediate address %r. // negative offset [100].Chapter 8.%r.b32 st.a.v4.r7.global.Q.a.b16 [a].local.global.b. [p].s32 st. [q+4].%r.f32 st. 2010 117 . // %r is 32-bit register // store lower 16 bits January 24.f32 st.s32 cvt.local.b32 st. [q+-8].

The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. 2010 . If no state space is given. . prefetch and prefetchu require sm_20 or later.0 Table 84. i.global. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.0. an address maps to global memory unless it falls within the local memory window or the shared memory window. Within these windows.global. The address size may be either 32-bit or 64-bit. prefetch. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. in specified state space.level prefetchu. Addresses are zero-extended to the specified width as needed.L1 [addr]. 32-bit).L2 }.local }. the prefetch uses generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. A prefetch to a shared memory location performs no operation. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. prefetchu. prefetch{.L1 [ptr].level = { . . or [immAddr] an immediate absolute byte address (unsigned. [a].space = { . a register reg containing a byte address. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. an address maps to the corresponding location in local or shared memory. In generic addressing.space}. 118 January 24. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.e. and no operation occurs if the address maps to a local or shared memory location. 32-bit). // prefetch to data cache // prefetch to uniform cache .L1 [a].PTX ISA Version 2.L1. A prefetch into the uniform cache requires a generic address.

0.size p. PTX ISA Notes Target ISA Notes Examples Table 86. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise. local. Introduced in PTX ISA version 2.u32 p. // get generic address of svar cvta.local.global. Take the generic address of a variable declared in global. cvta. or shared address. Use cvt. local.to. isspacep. or shared address to a generic address. or shared address cvta. or vice-versa.local.size cvta. or vice-versa. isshrd. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.space.global isspacep. local. Instruction Set Table 85.shared }.u64 or cvt. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 2010 119 . local. // local.size = { .size . . // result is . When converting a generic address into a global.shared isglbl.u32 to truncate or zero-extend addresses.to. A program may use isspacep to guard against such incorrect behavior. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. The source address operand must be a register of type . var.pred . For variables declared in global. p. .u32 or . p.u32 p. isspacep requires sm_20 or later.Chapter 8.pred.local.local isspacep.space.shared. or shared state space.shared }. a. islcl. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window. . . a. January 24. or shared state space to generic. gptr.u32.u32 gptr. The source and destination addresses must be the same size. svar.0. Description Convert a global. local. .global. // convert to generic address // get generic address of var // convert generic address to global. cvta. sptr. a. .u64 }.lptr. cvta.space = { .genptr. the generic address of the variable may be taken using cvta. or shared state space. cvta requires sm_20 or later.global.u64.u64. isspacep. lptr.space p.space = { .u32.space. The destination register must be of type .

rpi }.sat}. .f16.f32.rni round to nearest integer. i.dtype.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. Note that saturation applies to both signed and unsigned integer types.ftz.rz.rmi. // integer rounding // fp rounding .sat}. . . a.dtype.f32 float-to-integer conversions and cvt.sat For integer destination types. For float-to-integer conversions. . . . ..rni. Integer rounding is required for float-to-integer conversions.f32. Note: In PTX ISA versions 1.ftz. Description Semantics Integer Notes Convert between different types and sizes. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.rzi.f32 float-to-integer conversions and cvt.sat is redundant. a. . the . subnormal numbers are supported. cvt{. .rzi round to nearest integer in the direction of zero .ftz modifier may be specified in these cases for clarity.0 Table 87.irnd = { . and for same-size float-tofloat conversions where the value is rounded to an integer..MAXINT for the size of the operation.f64 }. Integer rounding is illegal in all other instances.s8.frnd}{.dtype. the result is clamped to the destination range by default. .ftz}{. For cvt.rp }. d.frnd = { . . .rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. . d = convert(a). The compiler will preserve this behavior for legacy PTX code.e.s32.u8. Saturation modifier: .s16. .dtype = . i.rmi round to nearest integer in direction of negative infinity .f32 float-tofloat conversions with integer rounding. subnormal inputs are flushed to signpreserving zero. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another.atype d.ftz}{. .ftz. . 2010 .4 and earlier.irnd}{. choosing even integer if source is equidistant between two integers.f32.sat limits the result to MININT.dtype. subnormal inputs are flushed to signpreserving zero.u32.PTX ISA Version 2. The optional .u64.u16.atype cvt{. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. 120 January 24. . . .atype = { . sm_1x: For cvt.rm.ftz.rn. Integer rounding modifiers: . .s64. .f32 float-tofloat conversions with integer rounding.e.

4 or earlier. // float-to-int saturates by default cvt.f32 instructions. and . .ftz modifier may be specified in these cases for clarity.s32 f. The operands must be of the same size.r. Floating-point rounding modifiers: .version is 1.rm mantissa LSB rounds towards negative infinity . stored in floating-point format. Introduced in PTX ISA version 1.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).4 and earlier. cvt. cvt to or from . and for integer-to-float conversions.y. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. Modifier .rz mantissa LSB rounds towards zero . Floating-point rounding is illegal in all other instances. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f64 types.f32. Note: In PTX ISA versions 1.f32.f64 requires sm_13 or later. The optional .sat For floating-point destination types. 1. Specifically.f64 j. The compiler will preserve this behavior for legacy PTX code. if the PTX . . 2010 121 .0].ftz behavior for sm_1x targets January 24.f32.f16.Chapter 8.0. // round to nearest int.0.rni. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. // note .f32.f32.y.f16.i. The result is an integral value. Applies to .f16.f32 x.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f32. cvt. subnormal numbers are supported. single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.f64. Saturation modifier: .rn mantissa LSB rounds to nearest even .f32 x. NaN results are flushed to positive zero. result is fp cvt. Subnormal numbers: sm_20: By default. and cvt.s32.sat limits the result to the range [0. cvt.f32.

f32 r3.f32 r1. cvt.7.. . If no texturing mode is declared.2d.f32. PTX supports the following operations on texture. add. mul. } = clamp_to_border. sampler. The texturing mode is selected using . [tex1]. In the independent mode. In the unified mode. r3.PTX ISA Version 2. // get tex1’s txq. add. sampler. add. Ability to query fields within texture.height.entry compute_power ( . samplers.global .0 8. r4. the file is assumed to use unified mode. div. The advantage of unified mode is that it allows 128 samplers.b32 r6. r1. and surface descriptors. r5.f2}]. PTX has two modes of operation.f32 r1. Module-scope and per-entry scope definitions of texture.r3. = nearest width height tsamp1.f32 r1. 122 January 24. r2. [tex1.f32 {r1. Texture and Surface Instructions This section describes PTX instructions for accessing textures. r5. // get tex1’s tex. r5. and surface descriptors. r6. {f1. texture and sampler information each have their own handle. [tex1].texref tex1 ) { txq. and surfaces. r1.target options ‘texmode_unified’ and ‘texmode_independent’. texture and sampler information is accessed through a single .v4. . . A PTX module may declare only one texturing mode.u32 r5.f32. allowing them to be defined separately and combined at the site of usage in the program. sampler. Example: calculate an element’s power contribution as element’s power/total number of elements.6.target texmode_independent . Texturing modes For working with textures and samplers..texref handle.param . with the restriction that they correspond 1-to-1 with the 128 possible textures. but the number of samplers is greatly restricted to 16.r2. r1.u32 r5. The advantage of independent mode is that textures and samplers can be mixed and matched.width. and surface descriptors.r4}. r3.b32 r5. and surface descriptors: • • • Static initialization of texture. sampler. 2010 .samplerref tsamp1 = { addr_mode_0 filter_mode }.

1d.btype tex. b.btype d. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. If an address is not properly aligned.f4}].geom. is a two-element vector for 2d textures. .r2.dtype = { .s32 {r1.f32 {r1.r3. // Example of independent mode texturing tex.s32. . Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. d.geom.v4. // explicit sampler . Supported on all target architectures.f32 }.s32. and is a four-element vector for 3d textures.dtype.f2. [tex_a.3d }. Instruction Set These instructions provide access to texture and surface memory.5. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.u32.Chapter 8.1d. Notes For compatibility with prior versions of PTX. c].v4..v4. the sampler behavior is a property of the named texture. If no sampler is specified.f32 }. Operand c is a scalar or singleton tuple for 1d textures. [a. . tex txq suld sust sured suq Table 88.r2. The instruction always returns a four-element vector of 32-bit values. or the instruction may fault.v4.r4}. [a. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d.r3.e. c]. sampler_x. the access may proceed by silently masking off low-order address bits to achieve proper rounding.dtype.geom = { .s32. A texture base address is assumed to be aligned to a 16-byte address. the square brackets are not required and . the resulting behavior is undefined. 2010 123 . i. //Example of unified mode texturing tex. . with the extra elements being ignored. . Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. {f1. PTX ISA Notes Target ISA Notes Examples January 24.s32. where the fourth element is ignored.btype = { . [tex_a.2d.v4 coordinate vectors are allowed for any geometry. .0. tex. Unified mode texturing introduced in PTX ISA version 1. An optional texture sampler b may be specified.f3.3d.r4}. {f1}]. . Description Texture lookup using a texture coordinate vector.

texref or . txq. .width.filter_mode . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.squery = { .tquery = { .height.squery. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.addr_mode_0 .5. // unified mode // independent mode 124 January 24. .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). txq. mirror.width. linear } Integer from enum { wrap. In unified mode. addr_mode_2 }. txq.0 Table 89. Query: . Description Query an attribute of a texture or sampler.depth. .normalized_coords . . txq. txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes.b32 %r1.b32 %r1.addr_mode_1 .normalized_coords }.width .filter_mode. clamp_to_edge. 2010 .filter_mode. . Supported on all target architectures.b32 d. [a].tquery. sampler attributes are also accessed via a texref argument. [smpl_B].b32 %r1. [tex_A]. d.depth . clamp_ogl.addr_mode_0. and in independent mode sampler attributes are accessed via a separate samplerref argument.addr_mode_0. Integer from enum { nearest. Operand a is a .samplerref variable.b32 txq.height . [tex_A].PTX ISA Version 2. [a]. // texture attributes // sampler attributes . addr_mode_1.

suld. suld.v2.u32. SNORM. [surf_B.trap . or FLOAT data. .p.geom{. . then . and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. . is a two-element vector for 2d surfaces.s32.clamp. and cache operations introduced in PTX ISA version 2. then .z.b16.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.p .cg. size and type conversion is performed as needed to convert from the surface sample format to the destination type.0.trap suld.cv }. . b]. suld. suld. .. If the destination type is . suld. If an address is not properly aligned. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. where the fourth element is ignored. [a.f3.vec. then . . or .v2. i. // cache operation none. The lowest dimension coordinate represents a sample offset rather than a byte offset. Operand a is a .f32 based on the surface format as follows: If the surface format contains UNORM. Destination vector elements corresponding to components that do not appear in the surface format are not written. Instruction Set Table 90.3d }.v4. Cache operations require sm_20 or later.b . . or .b.1d.f2.geom . if the surface format contains UINT data.clamp suld.f4}. [a.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. suld. // unformatted d. the access may proceed by silently masking off low-order address bits to achieve proper rounding.cs.cop .b64 }.trap {r1.Chapter 8.p is currently unimplemented. . the resulting behavior is undefined. . .geom{.cop}. If the destination base type is . Target ISA Notes Examples January 24. additional clamp modifiers. . {f1. A surface base address is assumed to be aligned to a 16-byte address.f32.b performs an unformatted load of binary data. suld.dtype. {x.s32.u32. G. Operand b is a scalar or singleton tuple for 1d surfaces. and A components of the surface format.b64. // formatted .s32. .f32 is returned.f32. B. suld. Description Load from surface memory using a surface coordinate vector.v4.b.s32 is returned.dtype. // for suld.f32 }.p. or the instruction may fault.v4 }.cop}. .ca.p.2d.b8 . suld Syntax Texture and Surface Instructions: suld Load from surface memory.y.p requires sm_20 or later.5. Coordinate elements are of type .trap.clamp . and is a four-element vector for 3d surfaces. {x}].b32.zero }.dtype . sm_1x targets support only the .u32 is returned.dtype . . // for suld. .clamp field specifies how to handle out-of-bounds addresses: .clamp . .1d.clamp = = = = = = { { { { { { d. .trap introduced in PTX ISA version 1. if the surface format contains SINT data. .b32. the surface sample elements are converted to .s32. b].surfref variable. and the size of the data transfer matches the size of destination operand d. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. 2010 125 . [surf_A. The .b32.vec .trap clamping modifier.e.3d.w}].r2}.b. .3d requires sm_20 or later. suld.b supported on all target architectures.u32.

trap sust. The . .b.clamp field specifies how to handle out-of-bounds addresses: . [surf_B. Target ISA Notes Examples 126 January 24. sust. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. . then .f32.cg. The size of the data transfer matches the size of source operand c.5.. i.1d. the resulting behavior is undefined. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM. {r1.geom{.trap introduced in PTX ISA version 1. 2010 . sust. sust. The lowest dimension coordinate represents a sample offset rather than a byte offset. . c. // for sust. If the source base type is .cop . size and type conversions are performed as needed between the surface sample format and the destination type. additional clamp modifiers.u32 is assumed. . or FLOAT data. and cache operations introduced in PTX ISA version 2. sust.PTX ISA Version 2.p Description Store to surface memory using a surface coordinate vector.b32.wb.trap. Operand b is a scalar or singleton tuple for 1d surfaces. .0.f32.clamp.b performs an unformatted store of binary data.f4}.b32.f32 is assumed.trap clamping modifier. sust.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. Coordinate elements are of type .2d. The source data is then converted from this type to the surface sample format.b16. none.s32. A surface base address is assumed to be aligned to a 16-byte address.ctype .wt }. . The source vector elements are interpreted left-to-right as R. sust. {x}]. b].y.ctype.p.trap [surf_A.b.cs. .trap . or .f2. . Cache operations require sm_20 or later.f32} are currently unimplemented.p.w}].z. sust Syntax Texture and Surface Instructions: sust Store to surface memory.u32.b8 . . sm_1x targets support only the . c. and A surface components.vec .b64 }. If an address is not properly aligned. {x. Surface sample components that do not occur in the source vector will be written with an unpredictable value.b supported on all target architectures.clamp = = = = = = { { { { { { [a. .v4. is a two-element vector for 2d surfaces.b // for sust.clamp .s32. .s32. G. . .b.3d requires sm_20 or later. sust.geom{. . . [a.s32 is assumed.b64.p.v2. sust. sust. or the instruction may fault.3d.0 Table 91.surfref variable. {f1. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .v2. then .clamp sust. Operand a is a .e.cop}.r2}. .zero }.p performs a formatted store of a vector of 32-bit data values to a surface sample. // unformatted // formatted . if the surface format contains SINT data. if the surface format contains UINT data.geom . .vec. Source elements that do not occur in the surface sample are ignored.f3.u32. These elements are written to the corresponding surface sample components. then .ctype.p.s32. . SNORM. B. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.ctype .clamp . If the source type is . b]. where the fourth element is ignored.vec.{u32. and is a four-element vector for 3d surfaces.v4 }.b32.p requires sm_20 or later.1d.f32 }.cop}. .3d }.

p performs a reduction on sample-addressed 32-bit data.min.op. // for sured. .b]. where the fourth element is ignored.trap sured. min and max apply to . i. sured.b].ctype.b32 type.s32. the resulting behavior is undefined.geom.p.c.u64. . January 24. . Operand a is a . if the surface format contains SINT data.u32. The . or .b32.trap.p.s32 types. r1.u32.u32 and .trap . {x}].surfref variable. and . {x.y}].zero }. . // for sured.s32 types. .b32 }.2d. .b32.u32. sured. // byte addressing sured.0.geom = { . sured requires sm_20 or later.or }.add. . then .u32 is assumed. .max.e.p .c.min.2d.clamp . the access may proceed by silently masking off low-order address bits to achieve proper rounding. If an address is not properly aligned. or the instruction may fault. sured. The lowest dimension coordinate represents a sample offset rather than a byte offset.op = { . .u32. then . sured.clamp field specifies how to handle out-of-bounds addresses: . . // sample addressing .s32. Reduction to surface memory using a surface coordinate vector. .clamp [a. .b .ctype = { . operations and and or apply to .3d }. Operations add applies to .zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b performs an unformatted reduction on . sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. Coordinate elements are of type .s32.clamp [a.ctype. A surface base address is assumed to be aligned to a 16-byte address.ctype = { . .op.trap [surf_A. and the data is interpreted as . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. r1. .b32.clamp = { .clamp. 2010 127 .add. [surf_B.1d.. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.b32 }. Instruction Set Table 92.1d.u64 data. and is a four-element vector for 3d surfaces.Chapter 8.u64. .b. is a two-element vector for 2d surfaces. Operand b is a scalar or singleton tuple for 1d surfaces.s32 or .geom.and. .b.u32 based on the surface sample format as follows: if the surface format contains UINT data.s32 is assumed. The instruction type is restricted to .

.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.0 Table 93. . [surf_A].width .height. suq Syntax Texture and Surface Instructions: suq Query a surface attribute.width. Description Query an attribute of a surface.width. .query.height .surfref variable.b32 %r1. suq. [a].depth }. suq.query = { . 2010 .PTX ISA Version 2. Supported on all target architectures. 128 January 24.b32 d. Query: . Operand a is a .5.

setp. @{!}p instruction. { add.b.a. mov. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.Chapter 8. ratio. {} Syntax Description Control Flow Instructions: { } Instruction grouping.0.s32 d. 2010 129 . Threads with a false guard predicate do nothing.y.f32 @q bra L23.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24.0. Introduced in PTX ISA version 1. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. } PTX ISA Notes Target ISA Notes Examples Table 95. If {!}p then instruction Introduced in PTX ISA version 1.f32 @!p div. used primarily for defining a function body. Supported on all target architectures.eq. Execute an instruction or instruction block for threads that have the guard predicate true.7. { instructionList } The curly braces create a group of instructions.x. Supported on all target architectures. Instruction Set 8. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94.0. p.c.7.s32 a.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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cta.sync and bar. Operand b specifies the number of threads participating in the barrier. the waiting threads are restarted without delay. Description Performs barrier synchronization and communication within a CTA.and).or }.u32. bar.red. and then safely read values stored by other threads prior to the barrier.red are population-count (.sync or bar. Since barriers are executed on a per-warp basis. a.red delays the executing threads (similar to bar. and bar.arrive. If no thread count is specified. All threads in the warp are stalled until the barrier completes. bar. The barrier instructions signal the arrival of the executing threads at the named barrier.red performs a reduction operation across threads.sync) until the barrier count is met. while .red.red performs a predicate reduction across the threads participating in the barrier. Instruction Set Table 100. the bar.. The result of . thread count. In addition to signaling its arrival at the barrier. bar.red should not be intermixed with bar.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. a{.version 2. Barriers are executed on a per-warp basis as if all the threads in a warp are active.arrive does not cause any waiting by the executing threads.sync or bar. Thus. it is as if all the threads in the warp have executed the bar instruction. Once the barrier count is reached.red} introduced in PTX . b. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. The reduction operations for bar.arrive using the same active barrier. threads within a CTA that wish to communicate via memory can store to memory. and any-thread-true (. Note that a non-zero thread count is required for bar. bar.red} require sm_20 or later.sync 0. and the barrier is reinitialized so that it can be immediately reused.sync without a thread count introduced in PTX ISA 1. and bar.arrive a{. if any thread in a warp executes a bar instruction.pred .and and . bar. When a barrier completes.popc. bar. Register operands.red instruction.op = { . a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). execute a bar.or). January 24. bar. all-threads-true (. a{. d. operands p and c are predicates. bar.sync and bar.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.op. . Register operands. b}.popc is the number of threads with a true predicate. it simply marks a thread's arrival at the barrier.Chapter 8. p. all threads in the CTA participate in the barrier.0.sync with an immediate barrier number is supported for sm_1x targets.red also guarantee memory ordering among threads identical to membar. thread count. and d have type . Only bar.15. b}. the final value is written to the destination register in all threads waiting at the barrier. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. Execution in this case is unpredictable. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).{arrive. b}. bar. PTX ISA Notes Target ISA Notes Examples bar.and. {!}c. Operands a.sync bar. Each CTA instance has sixteen barriers numbered 0. b.popc). In conditionally executed code. the optional thread count must be a multiple of the warp size.u32 bar.0. Thus. {!}c.{arrive. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. 2010 133 .

.gl. . A memory write (e.{cta. membar. membar. membar. 134 January 24.sys }. or system memory level. when the previous value can no longer be read. by st. membar.0. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier.sys will typically have much longer latency than membar. membar.version 1. . This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.gl will typically have a longer latency than membar. and memory reads by this thread can no longer be affected by other thread writes. this is the appropriate level of membar. that is.gl.sys.cta. membar.0 Table 101. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.cta Waits until all prior memory writes are visible to other threads in the same CTA.4.PTX ISA Version 2.gl} supported on all target architectures.gl} introduced in PTX .sys requires sm_20 or later. 2010 .sys introduced in PTX . including thoses communicating via PCI-E such as system and peer-to-peer memory.level. membar.version 2.cta.sys Waits until all prior memory requests have been performed with respect to all clients. level describes the scope of other clients for which membar is an ordering event. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.g.{cta. membar.g. global. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar. membar.cta.level = { . A memory read (e. For communication between threads in different CTAs or even different SMs. membar.gl. Waits until prior memory reads have been performed with respect to other threads in the CTA. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. PTX ISA Notes Target ISA Notes Examples membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.

b64 . .s32. If an address is not properly aligned.max }.add. by inserting barriers between normal stores and atomic operations to a common address. or by using atom. . the access may proceed by silently masking off low-order address bits to achieve proper rounding. i. overwriting the original value. atom{.f32 }. xor.u32.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. The floating-point add. January 24.type d. performs a reduction operation with operand b and the value in location a. . . max. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.space = { . perform the memory accesses using generic addressing. an address maps to global memory unless it falls within the local memory window or the shared memory window.u64 . .s32.op. and stores the result of the specified operation at location a. Instruction Set Table 102. .dec. The address size may be either 32-bit or 64-bit. . a de-referenced register areg containing a byte address.b32 only . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. c.b32. the resulting behavior is undefined. or [immAddr] an immediate absolute byte address. [a].f32.op. For atom. and max. .xor. i. . The floating-point operations are add. .f32 Atomically loads the original value at location a into destination register d. dec. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.. or the instruction may fault.cas. and exch (exchange).exch to store to locations accessed by other atomic operations.e.exch. atom.space}.u64. . and max operations are single-precision.shared }. Operand a specifies a location in the specified state space. Description // // // // // .u32 only .add. . .Chapter 8. . an address maps to the corresponding location in local or shared memory. d. A register containing an address may be declared as a bit-size type or integer type. . e. Addresses are zero-extended to the specified width as needed. The integer operations are add. inc. ..e.type = { .g. . min. . The bit-size operations are and. The inc and dec operations return a result in the range [0.u32. . cas (compare-and-swap).b32. Within these windows.global. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. b.type atom{. . b.space}. accesses to local memory are illegal.b64. 32-bit operations.and. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.s32. and truncated if the register width exceeds the state space address width for the target architecture.b]. The address must be naturally aligned to a multiple of the access size. [a]. In generic addressing. . .min. min.or.inc.op = { . 2010 135 .u32. . If no state space is given. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. or. min. .

b).s32 atom.f32 atom.b32 d. cas(r. s) = (r >= s) ? 0 dec(r. b. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.exch} requires sm_12 or later.[x+4]. : r-1.0.f32 requires sm_20 or later.s. 2010 .max.[a].cas.0 Semantics atomic { d = *a.{add.1. : r. *a = (operation == cas) ? : } where inc(r. Release Notes Examples @p 136 January 24. 64-bit atom. atom.global.add. : r+1. atom.max} are unimplemented.shared. atom. c) operation(*a. 64-bit atom.PTX ISA Version 2. atom. atom. d. Introduced in PTX ISA version 1. s) = s. Use of generic addressing requires sm_20 or later.global requires sm_11 or later.0.cas.shared requires sm_12 or later.global.shared operations require sm_20 or later.my_new_val.t) = (r == s) ? t operation(*a. s) = (r > s) ? s exch(r.f32.{min.[p].my_val. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.add. d.

xor. the access may proceed by silently masking off low-order address bits to achieve proper rounding. and max. e. by inserting barriers between normal stores and reduction operations to a common address.max }. 2010 137 . The bit-size operations are and.b32 only . dec. overwriting the original value. an address maps to global memory unless it falls within the local memory window or the shared memory window. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.e. January 24. . . . and truncated if the register width exceeds the state space address width for the target architecture. If no state space is given. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. min. min.u32. Operand a specifies a location in the specified state space. and max operations are single-precision. b).min. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. or.add.f32. The inc and dec operations return a result in the range [0. max. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.s32.u64.Chapter 8.b32. dec(r. The address size may be either 32-bit or 64-bit. .shared }.s32. . Description // // // // .u64 . i. or the instruction may fault.. The floating-point add. 32-bit operations. a de-referenced register areg containing a byte address.g.u32.s32.f32 }.space}. . an address maps to the corresponding location in local or shared memory. Notes Operand a must reside in either the global or shared state space. perform the memory accesses using generic addressing. . For red. i. . inc. and xor.add. . or by using atom. Instruction Set Table 103. s) = (r > s) ? s : r-1.and.op. The floating-point operations are add. where inc(r.u32 only .space = { .type = { . . A register containing an address may be declared as a bit-size type or integer type. . and stores the result of the specified operation at location a.exch to store to locations accessed by other reduction operations. Within these windows. s) = (r >= s) ? 0 : r+1. the resulting behavior is undefined. b. red.or. .op = { . or [immAddr] an immediate absolute byte address..e. . . The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.type [a]. min. Addresses are zero-extended to the specified width as needed.inc. If an address is not properly aligned.f32 Performs a reduction operation with operand b and the value in location a. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. . . . . .dec.u32. red{. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.global. The integer operations are add. The address must be naturally aligned to a multiple of the access size.b]. Semantics *a = operation(*a. accesses to local memory are illegal.b64. In generic addressing.

add.1.PTX ISA Version 2.my_val.{min.global.shared requires sm_12 or later. 64-bit red.0.and. Release Notes Examples @p 138 January 24.add. 64-bit red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.b32 [a].add requires sm_12 or later. [p]. red.s32 red.shared operations require sm_20 or later. red.2.f32 red.f32 requires sm_20 or later.max} are unimplemented. [x+4]. red.global.max. red. Use of generic addressing requires sm_20 or later.f32.shared. 2010 .global requires sm_11 or later red.

any True if source predicate is True for some active thread in warp. In the ‘ballot’ form.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.p. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. where the bit position corresponds to the thread’s lane id. vote requires sm_12 or later. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.all.ballot.ballot. vote. vote. Negate the source predicate to compute .mode = { .all True if source predicate is True for all active threads in warp. not across an entire CTA. Note that vote applies to threads in a single warp. Negating the source predicate also computes .not_all. The reduction modes are: . returns bitmask .uni }. Description Performs a reduction of the source predicate across threads in a warp. {!}a. Instruction Set Table 104.b32 requires sm_20 or later.pred d.uni. r1. p. {!}a. 2010 139 .Chapter 8. The destination predicate value is the same across all threads in the warp.mode.all. vote. vote.q.ballot.ballot. .b32 p.2.pred vote. // get ‘ballot’ across warp January 24. .uni. .q.any. . Negate the source predicate to compute .uni True if source predicate has the same value in all active threads in warp. vote.pred vote.b32 d.none. // ‘ballot’ form.

extended internally to . 3. taking into account the subword destination size in the case of optional data merging.secop = { . . 2010 .bsel = { .btype{. .dtype.h0.PTX ISA Version 2. c.sat} d. with optional secondary operation vop.s32) is specified in the instruction type. .b1.b2. all combinations of dtype. .or zero-extend byte. half-word.add.s34 intermediate result. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. and btype are valid. . The type of each operand (.sat}. . a{. 140 January 24.asel}.dsel = .secop d. b{.btype{. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1.s32 }. 4.btype{. a{. . . .9.atype.atype. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned). c. The general format of video instructions is as follows: // 32-bit scalar operation.7. or word values from its source operands.dsel. atype. the input values are extracted and signor zero. The primary operation is then performed to produce an . // 32-bit scalar operation. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. 2. a{. with optional data merge vop. . The source and destination operands are all 32-bit registers.s33 values.asel = .b3.asel}.bsel}.dtype = .h1 }. The sign of the intermediate result depends on dtype. Using the atype/btype and asel/bsel specifiers.max }.b0.dtype.btype = { . b{. vop.bsel}.asel}.u32 or . perform a scalar arithmetic operation to produce a signed 34-bit result. to produce signed 33-bit input values. Video Instructions All video instructions operate on 32-bit register operands.bsel}. b{.atype = .0 8. extract and sign.u32.min.dtype. optionally clamp the result to the range of the destination type.sat} d. .atype.

U16_MAX.h1: return ((tmp & 0xffff) << 16) case . U8_MAX.s34 tmp. switch ( dsel ) { case . c). Instruction Set . tmp. .b0. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).s33 optSaturate( .add: return tmp + c.b3: if ( sign ) return CLAMP( else return CLAMP( case . . U8_MIN ). S8_MAX.s33 c) { switch ( secop ) { . U32_MAX.s33 tmp. .s33 optSecOp(Modifier secop. c).b2: return ((tmp & 0xff) << 16) case . U16_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp. tmp.b2. S8_MIN ). .min: return MIN(tmp. Modifier dsel ) { if ( !sat ) return tmp.s33 c ) switch ( dsel ) { case . default: return tmp. . tmp.Chapter 8.s33 tmp. c). The sign of the c operand is based on dtype. Bool sat. S32_MIN ). tmp. 2010 141 . . . The lower 32-bits are then written to the destination operand. S16_MIN ).h0: return ((tmp & 0xffff) case . .s33 optMerge( Modifier dsel. . c).b1: return ((tmp & 0xff) << 8) case . . January 24. c).h0.max return MAX(tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. as shown in the following pseudocode. S32_MAX. } } . tmp. U32_MIN ). Bool sign.b0: return ((tmp & 0xff) case . S16_MAX. c). .b1. c). This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.

bsel}. d = optSecondaryOp( op2. .atype = . r3. vsub vabsdiff vmin.PTX ISA Version 2. tmp. vmax require sm_20 or later. tb ).max }.h1. .btype = { .btype{. asel ). atype. // 32-bit scalar operation. c ).asel}. vmax }. tmp = MAX( ta. vsub.b3. a{.u32. vabsdiff. tmp. tmp = MIN( ta. Semantics // saturate.b2.s32.h0.sat} d.sat} d. . isSigned(dtype).u32. tmp = | ta – tb |. Video Instructions: vadd. c ).s32.add r1. . bsel ). r1. b{.dtype . vmin. btype.atype.s32.h1 }. r2. r3. dsel ).dtype. r3.b0.h0. b{. with optional data merge vop. Integer byte/half-word/word minimum / maximum. .b0.b2. vadd.h0. vop. r2.atype.atype. . c.b1. a{.bsel}. r3.sat}.btype{.btype{.op2 d. Perform scalar arithmetic operation with optional saturate. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. tb ). // extract byte/half-word/word and sign.s32.sat. vmax Syntax Integer byte/half-word/word addition / subtraction.dtype. vadd.dsel.s32 }.s32.sat vsub. with optional secondary operation vop. r2.bsel = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. vabsdiff. . b{. c. sat. r1.sat vabsdiff.u32. // optional merge with c operand 142 January 24. // 32-bit scalar operation.bsel}. and optional secondary arithmetic operation or subword data merge.asel}. r2.asel}. 2010 . .h1. .sat vmin. Integer byte/half-word/word absolute value of difference.0 Table 105.s32.add.s32. vsub.or zero-extend based on source operand type ta = partSelectSignExtend( a. tb = partSelectSignExtend( b. .asel = .s32.op2 Description = = = = { vadd.vop . { .dsel .min. .0. vmin. vsub. a{. // optional secondary operation d = optMerge( dsel. vmax vadd. taking into account destination type and merge operations tmp = optSaturate( tmp. vabsdiff. r1.s32.dtype.s32. vmin.b0. c. c. tmp = ta – tb.

c ). if ( mode == .mode} d.0.add. vshr Syntax Integer byte/half-word/word left / right shift. Signed shift fills with the sign bit.u32{. . . tb = partSelectSignExtend( b.or zero-extend based on source operand type ta = partSelectSignExtend( a.clamp .u32{. and optional secondary arithmetic operation or subword data merge.h1 }.b2. b{.max }.mode . . b{.bsel}. vop.op2 Description = = = = = { vshl.b1.asel = . a{. a{. switch ( vop ) { case vshl: tmp = ta << tb. and optional secondary arithmetic operation or subword data merge.b3. vshr: Shift a right by unsigned amount in b with optional saturate. Instruction Set Table 106. .h1.dtype. .dtype.min. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat}{. . vshr }. vshl: Shift a left by unsigned amount in b with optional saturate.h0. with optional secondary operation vop. // 32-bit scalar operation. January 24. } // saturate. Semantics // extract byte/half-word/word and sign.mode} d. { .clamp && tb > 32 ) tb = 32.u32. 2010 143 . case vshr: tmp = ta >> tb.s32 }.atype. .asel}. Video Instructions: vshl. bsel ). asel ). r2. // 32-bit scalar operation. Left shift fills with zero.mode}. vshl. sat. r3.wrap }. r1.s32.bsel = { . vshl. .wrap r1.atype. d = optSecondaryOp( op2. a{.clamp. r2. dsel ).op2 d. tmp. isSigned(dtype). if ( mode == . // optional secondary operation d = optMerge( dsel.bsel}. with optional data merge vop. .sat}{. b{.b0.u32. .u32.u32 vshr. c.atype = { .wrap ) tb = tb & 0x1f. c ).u32.atype.u32. taking into account destination type and merge operations tmp = optSaturate( tmp. // default is . { .u32{.dtype.u32.vop . c. .dtype . vshr require sm_20 or later.sat}{. atype.Chapter 8.asel}.dsel. vshr vshl. . r3.asel}.dsel . tmp. unsigned shift fills with zero.bsel}.

c.po) computes (a*b) + c + 1.sat}{. .h0. . vmad.scale} d.btype. final signed -(U32 * S32) + S32 // intermediate signed. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. .asel}. final signed (S32 * U32) + S32 // intermediate signed.U32 // intermediate unsigned. final signed The intermediate result is optionally scaled via right-shift.s32 }.dtype. .0 Table 107.S32 // intermediate signed.asel}. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate.bsel}.atype = . .u32. which is used in computing averages. The “plus one” mode (.. Description Calculate (a*b) + c. the intermediate result is signed. a{.h1 }.shr7.sat}{.b1. b{. internally this is represented as negation of the product (a*b).bsel = { .S32 // intermediate signed. {-}a{. The source operands support optional negation with some restrictions. .dtype = . 144 January 24. That is. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. final signed -(S32 * U32) + S32 // intermediate signed. final signed (S32 * S32) . // 32-bit scalar operation vmad. final signed (U32 * U32) . {-}b{. Although PTX syntax allows separate negation of the a and b operands.btype{. 2010 .scale} d.b0.po mode.po{.b2. final signed -(S32 * S32) + S32 // intermediate signed. final signed (S32 * U32) . .PTX ISA Version 2. final signed (U32 * S32) .atype. this result is sign-extended if the final result is signed. “plus one” mode. final signed (U32 * S32) + S32 // intermediate signed. final signed (S32 * S32) + S32 // intermediate signed. . PTX allows negation of either (a*b) or c.bsel}.dtype. Source operands may not be negated in . .shr15 }. final unsigned -(U32 * U32) + S32 // intermediate signed. .asel = . and the operand negates.scale = { . {-}c. and zero-extended otherwise. The final result is unsigned if the intermediate result is unsigned and c is not negated. Input c has the same sign as the intermediate result. Depending on the sign of the a and b operands. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.b3. and scaling. with optional operand negates.S32 // intermediate signed. (a*b) is negated if and only if exactly one of a or b is negated.btype = { .atype. otherwise.

bsel ). S32_MAX.u32. vmad.shr15: result = (tmp >> 15) & 0xffffffffffffffff. vmad requires sm_20 or later.or zero-extend based on source operand type ta = partSelectSignExtend( a. case .shr7: result = (tmp >> 7) & 0xffffffffffffffff.u32. r3.u32. January 24. } else if ( c. } if ( . signedFinal = isSigned(atype) || isSigned(btype) || (a. asel ). U32_MAX. else result = CLAMP(result. btype. r1. if ( . switch( scale ) { case .0.sat ) { if (signedFinal) result = CLAMP(result.po ) { lsb = 1.Chapter 8.negate ^ b.negate ) { c = ~c.h0.negate ^ b. U32_MIN).s32. lsb = 0.negate. tb = partSelectSignExtend( b.s32. } else if ( a. tmp = tmp + c128 + lsb.shr15 r0.negate) || c. 2010 145 . r2.u32. atype. r2. r1. lsb = 1.sat vmad. lsb = 1.negate ) { tmp = ~tmp. r0.h0. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). S32_MIN). tmp[127:0] = ta * tb. Instruction Set Semantics // extract byte/half-word/word and sign. -r3. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.

tb.b3. . .u32.h0.bsel}. a{. . asel ). with optional data merge vset. r1. r3.btype. tmp. and therefore the c operand and final result are also unsigned.atype.add.asel}. b{.ne. .PTX ISA Version 2.btype. cmp ) ? 1 : 0. r2. vset requires sm_20 or later.0 Table 108.b2. vset. . with optional secondary arithmetic operation or subword data merge.le. .op2 d.u32. with optional secondary operation vset. The intermediate result of the comparison is always unsigned. { .ge }. Semantics // extract byte/half-word/word and sign.atype.b1. c. tmp.bsel}. 146 January 24.cmp d.cmp .ne r1.or zero-extend based on source operand type ta = partSelectSignExtend( a. . b{. b{.op2 Description = = = = .max }. . c. .atype. r3. .asel = . // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.u32. // 32-bit scalar operation. .atype .0.eq. btype. c ).bsel}.btype = { . atype.cmp d. 2010 .s32 }. .dsel . vset. tb = partSelectSignExtend( b.s32. a{. // 32-bit scalar operation. .h1 }. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.cmp. d = optSecondaryOp( op2.lt vset. a{.lt. bsel ).h1.min. .b0.asel}. r2.bsel = { . { . .btype. Compare input values using specified comparison.u32. // optional secondary operation d = optMerge( dsel.asel}.dsel. tmp = compare( ta.gt. c ).

Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. trap. Triggers one of a fixed number of performance monitor events. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation.10.Chapter 8.7. The relationship between events and counters is programmed via API calls from the host. pmevent 7.4. Notes PTX ISA Notes Target ISA Notes Examples Currently. @p pmevent 1. Introduced in PTX ISA version 1. Supported on all target architectures. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event.0. Table 110. Supported on all target architectures. with index specified by immediate operand a. brkpt requires sm_11 or later. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Introduced in PTX ISA version 1. pmevent a. 2010 147 . Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. trap Abort execution and generate an interrupt to the host CPU. January 24. numbered 0 through 15.0. there are sixteen performance monitor events. brkpt. Table 111. brkpt. Instruction Set 8. brkpt Suspends execution Introduced in PTX ISA version 1. trap.

2010 .0 148 January 24.PTX ISA Version 2.

%lanemask_gt %clock. %clock64 %pm0. %pm3 January 24. which are visible as special registers and accessed through mov or cvt instructions. 2010 149 .Chapter 9. …. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. %lanemask_lt. read-only variables. %lanemask_ge. %lanemask_le. Special Registers PTX includes a number of predefined.

per-thread special register initialized with the thread identifier within the CTA. 2010 . Supported on all target architectures. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.v4. %tid.x * %ntid.z. .0. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. %ntid. Redefined as .x to %rh Target ISA Notes Examples // legacy PTX 1.z == 0 in 1D CTAs. // compute unified thread id for 2D CTA mov. . The number of threads in each dimension are specified by the predefined special register %ntid.y.z).%h2. mov.sreg .u32 %r1. mov.x. The fourth element is unused and always returns zero. .z == 0 in 2D CTAs. It is guaranteed that: 0 <= %tid. %ntid.%ntid. %tid. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.v4. %ntid.u32 %ntid. Redefined as .u32 type in PTX 2.%tid. cvt.0.x. // zero-extend tid.0. read-only special register initialized with the number of thread ids in each CTA dimension.u32 %tid.z < %ntid. // CTA shape vector // CTA dimensions A predefined.u16 %r2.x.v4 . Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. %ntid.u32 %r0. or 3D vector to match the CTA shape.y. mov.x 0 <= %tid.z.sreg . the %tid value in unused dimensions is 0.y < %ntid.y.%ntid.u16 %rh.x.%tid.u32 %r0.z.x code Target ISA Notes Examples 150 January 24. // move tid.%tid.u16 %rh.%r0. The %tid special register contains a 1D.0 Table 112.y == %tid. %tid component values range from 0 through %ntid–1 in each CTA dimension.z to %r2 Table 113.u32. PTX ISA Notes Introduced in PTX ISA version 1. // legacy PTX 1.x.sreg .y == %ntid. mov.x code accessing 16-bit component of %tid mov. %tid.u32 type in PTX 2.sreg . The total number of threads in a CTA is (%ntid. .u32 %h1.u32 %tid. Every thread in the CTA has a unique %tid. // thread id vector // thread id components A predefined.u32 %h2.x < %ntid.%tid. the fourth element is unused and always returns zero.PTX ISA Version 2.y 0 <= %tid.y * %ntid.v4 .x. %tid. read-only.z PTX ISA Notes Introduced in PTX ISA version 1.%h1. Supported on all target architectures.x. mad. 2D.%tid.z == 1 in 2D CTAs.u32 %ntid.0. CTA dimensions are non-zero.z == 1 in 1D CTAs.

mov. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code. %laneid. Introduced in PTX ISA version 2. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. A predefined. Supported on all target architectures.Chapter 9.sreg .u32 %warpid. but its value may change during execution. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier.u32 %laneid.u32 %r. .3. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. The lane identifier ranges from zero to WARP_SZ-1. due to rescheduling of threads following preemption. %warpid. %nwarpid requires sm_20 or later. PTX ISA Notes Target ISA Notes Examples Table 116. Table 115. mov. The warp identifier will be the same for all threads within a single warp. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. Supported on all target architectures. January 24.u32 %r.u32 %r.sreg .sreg . Special Registers Table 114. For this reason. %nwarpid. . 2010 151 . . read-only special register that returns the thread’s lane within the warp.u32 %nwarpid. read-only special register that returns the maximum number of warp identifiers. Note that %warpid is volatile and returns the location of a thread at the moment when read.3.0. mov. A predefined. Introduced in PTX ISA version 1.g. e. A predefined. read-only special register that returns the thread’s warp identifier. Introduced in PTX ISA version 1. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid.

The %ctaid special register contains a 1D. It is guaranteed that: 0 <= %ctaid.0. .v4.sreg . . Redefined as .u32 %nctaid.u32 %ctaid.y.y. Each vector element value is >= 0 and < 65535.u32 mov.x < %nctaid.x 0 <= %ctaid. depending on the shape and rank of the CTA grid.0.u32 type in PTX 2. The %nctaid special register contains a 3D grid shape vector. %ctaid.x code Target ISA Notes Examples Table 118.%nctaid.u16 %r0. The fourth element is unused and always returns zero. .sreg . read-only special register initialized with the CTA identifier within the CTA grid. %rh. mov.sreg .%nctaid.%ctaid.x. mov.v4.z} < 65. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. // Grid shape vector // Grid dimensions A predefined. // legacy PTX 1. with each element having a value of at least 1. The fourth element is unused and always returns zero.x code Target ISA Notes Examples 152 January 24. %rh.u32 mov. Redefined as . It is guaranteed that: 1 <= %nctaid.u32 type in PTX 2.0.sreg .u32 %ctaid. %ctaid. 2D.%ctaid.PTX ISA Version 2.u32 %nctaid .536 PTX ISA Notes Introduced in PTX ISA version 1.z.0 Table 117.z < %nctaid.x. read-only special register initialized with the number of CTAs in each grid dimension.v4 .y.x. // legacy PTX 1. Supported on all target architectures.y < %nctaid.{x.0.u16 %r0.z PTX ISA Notes Introduced in PTX ISA version 1.%nctaid. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.x.y 0 <= %ctaid. // CTA id vector // CTA id components A predefined.%nctaid. or 3D vector. 2010 .v4 . Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.z.x.y. Supported on all target architectures. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.

PTX ISA Notes Target ISA Notes Examples January 24. This variable provides the temporal grid launch number for this context. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. %smid.g. where each launch starts a grid-of-CTAs. Supported on all target architectures. Introduced in PTX ISA version 2. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids.u32 %r.u32 %r. The SM identifier numbering is not guaranteed to be contiguous. mov.0. Special Registers Table 119. . A predefined.3. due to rescheduling of threads following preemption.sreg . %gridid. but its value may change during execution.u32 %smid.u32 %gridid. . Note that %smid is volatile and returns the location of a thread at the moment when read.sreg . .sreg .u32 %r. e. read-only special register initialized with the per-grid temporal grid identifier. The SM identifier numbering is not guaranteed to be contiguous. // initialized at grid launch A predefined. %nsmid requires sm_20 or later. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.Chapter 9. During execution.u32 %nsmid. A predefined. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. mov. 2010 153 . PTX ISA Notes Target ISA Notes Examples Table 121.0. %nsmid. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. so %nsmid may be larger than the physical number of SMs in the device. Supported on all target architectures. The SM identifier ranges from 0 to %nsmid-1. Introduced in PTX ISA version 1. Introduced in PTX ISA version 1. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. read-only special register that returns the maximum number of SM identifiers. repeated launches of programs may occur. mov. Notes PTX ISA Notes Target ISA Notes Examples Table 120.

Table 124. %lanemask_eq. A predefined.0 Table 122. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp.0. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. %lanemask_le. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %r.sreg .u32 %r. %lanemask_le requires sm_20 or later. Table 123. %lanemask_lt requires sm_20 or later. . read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. . 154 January 24.u32 %lanemask_eq. .u32 %r.PTX ISA Version 2.0. Introduced in PTX ISA version 2. mov. Introduced in PTX ISA version 2. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. A predefined.0. %lanemask_lt. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. 2010 .sreg .sreg . Introduced in PTX ISA version 2.u32 %lanemask_le.u32 %lanemask_lt. %lanemask_eq requires sm_20 or later. A predefined. mov. mov.

u32 %lanemask_ge. A predefined. %lanemask_ge requires sm_20 or later. %lanemask_gt requires sm_20 or later.u32 %lanemask_gt. January 24. mov. . 2010 155 . . Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg . Table 126. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2.0. A predefined. mov. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. %lanemask_ge. %lanemask_gt.Chapter 9. Introduced in PTX ISA version 2.u32 %r.0. Special Registers Table 125.u32 %r. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp.sreg .

sreg .sreg . %pm1. read-only 64-bit unsigned cycle counter.0. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined. 2010 . Supported on all target architectures.u32 %pm0. The lower 32-bits of %clock64 are identical to %clock.u64 %clock64. %pm3. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently.u32 r1. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.%pm0.%clock. mov. .u32 r1. 156 January 24.3. %pm1. %pm3 %pm0.%clock64. .0. …. read-only 32-bit unsigned cycle counter. and %pm3 are unsigned 32-bit read-only performance monitor counters. Introduced in PTX ISA version 1. Special Registers: %pm0. Supported on all target architectures.u32 %clock. Special registers %pm0. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. %pm2.sreg . Their behavior is currently undefined. %pm2. %pm1. . %clock64 requires sm_20 or later.u64 r1. Introduced in PTX ISA version 1. Introduced in PTX ISA version 2.0 Table 127. Table 129. Table 128. mov. %pm2. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. mov.PTX ISA Version 2.

.version directive.version 1. . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.0 .version directive. Directives 10.version directives are allowed provided they match the original . minor are integers Specifies the PTX language version number. Increments to the major number indicate incompatible changes to PTX. PTX File Directives: .target Table 130.4 January 24.Chapter 10.0.minor // major.version . Duplicate . Each ptx file must begin with a . and the target architecture for which the code was generated.1. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version Syntax Description Semantics PTX version number. . Supported on all target architectures. 2010 157 .version 2.version major.version .

texref descriptor. Texturing mode introduced in PTX ISA version 1.target directive containing a target architecture and optional platform options. brkpt instructions.f32. generations of SM architectures follow an “onion layer” model. In general. and an error is generated if an unsupported feature is used. but subsequent . A program with multiple .target directive specifies a single target architecture. Target sm_20 Description Baseline feature set for sm_20 architecture. Therefore. Description Specifies the set of features in the target architecture for which the current ptx code was generated.texmode_unified . Adds {atom. The texturing mode is specified for an entire module and cannot be changed within the module. 64-bit {atom.texmode_unified) . Note that .0. PTX code generated for a given target can be run on later generation devices.version directive. This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.PTX ISA Version 2. sm_10. 158 January 24. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Disallows use of map_f64_to_f32. map_f64_to_f32 }.f64 storage remains as 64-bits. Introduced in PTX ISA version 1. texture and sampler information is referenced with independent .0 Table 131. The following table summarizes the features in PTX that vary according to target architecture. Requires map_f64_to_f32 if any . PTX File Directives: . map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.target Syntax Architecture and Platform target.texref and .f64 to . Requires map_f64_to_f32 if any . vote instructions. Texturing mode: (default is .f64 instructions used.target .target directives can be used to change the set of target features allowed during parsing. A . . sm_11.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program.samplerref descriptors. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. texmode_unified. 2010 .f64 instructions used. Requires map_f64_to_f32 if any .red}.global. Adds double-precision support.f64 instructions used. PTX features are checked against the specified target architecture. where each generation adds new features and retains all features of previous generations.5. Adds {atom.shared. sm_12. with only half being used by instructions converted from .red}. immediately followed by a . sm_13.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.texmode_independent texture and sampler information is bound together and accessed via a single .global. texmode_independent. Supported on all target architectures. Each PTX file must begin with a .red}. including expanded rounding modifiers.

target sm_20.Chapter 10.target sm_13 // supports double-precision . 2010 159 . Directives Examples . texmode_independent January 24.target sm_10 // baseline target architecture .

entry . ld. At kernel launch.func Table 132.2. [y]. parameter variables are declared in the kernel body.b32 %r1.entry .surfref variables may be passed as parameters. %ntid. store. ld.entry kernel-name kernel-body Defines a kernel entry point name. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. %nctaid.b32 %r3. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.b32 x.4. Supported on all target architectures. Kernel and Function Directives: .g.entry Syntax Description Kernel entry point and body.param instructions. Semantics Specify the entry point for a kernel program. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.b32 %r2. parameters.0 10. and body for the kernel function. etc.param { . .param .param.reg .texref. . parameter variables are declared in the kernel parameter list. ld.b32 %r<99>.param instructions. opaque .b32 z ) Target ISA Notes Examples [x]. Parameters are passed via .entry cta_fft . PTX ISA Notes For PTX ISA version 1.PTX ISA Version 2.3. Parameters may be referenced by name within the kernel body and loaded into registers using ld. .b32 y. The shape and size of the CTA executing the kernel are available in special registers.5 and later. In addition to normal parameters.0 through 1. These parameters can only be referenced by name within texture and surface load. the kernel dimensions and properties are established and made available via special registers. … } .param space memory and are listed within an optional parenthesized parameter list.4 and later. . 2010 . with optional parameters.param. 160 January 24. [z]. For PTX ISA versions 1.param . . e. and .0 through 1.entry kernel-name ( param-list ) kernel-body .samplerref. and query instructions and cannot be accessed via ld. .param.entry filter ( .

reg .0.reg . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. implements an ABI with stack. mov. dbl. (val0. Supported on all target architectures.b32 rval.reg . A .func fname function-body . and recursion is illegal.result.Chapter 10. foo. PTX 2.param and st. . … use N. The parameter lists define locally-scoped variables in the function body. Parameters in register state space may be referenced directly within instructions in the function body.func fname (param-list) function-body .func (. Parameters must be base types in either the register or parameter state space.b32 localVar.func definition with no body provides a function prototype. there is no stack.2 for a description of variadic functions. Parameters in .func Syntax Function definition. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7. … Description // return value in fooval January 24. Directives Table 133.param space are accessed using ld. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. . Parameter passing is call-by-value. Variadic functions are represented using ellipsis following the last fixed argument. and supports recursion. including input and return parameters and optional function body. other code.b32 N. Variadic functions are currently unimplemented.f64 dbl) { . which may use a combination of registers and stack locations to pass parameters. if any.0 with target sm_20 supports at most one return value.func . val1). ret. } … call (fooval).b32 rval) foo (. PTX ISA 2. parameters must be in the register state space.func (ret-param) fname (param-list) function-body Defines a function. .reg .x code.param instructions in the body. Kernel and Function Directives: . Release Notes For PTX ISA version 1.param state space.0 with target sm_20 allows parameters in the . The implementation of parameter passing is left to the optimizing translator. 2010 161 .

g. The interpretation of .maxnreg. and . and the strings have no semantics within the PTX virtual machine model. The directive passes a list of strings to the backend.0 10. Performance-Tuning Directives To provide a mechanism for low-level performance tuning. and the . 162 January 24. The directives take precedence over any module-level constraints passed to the optimizing backend.pragma directives may appear at module (file) scope.minnctapersm . . Currently. for example. to throttle the resource requirements (e. A general .pragma The . . PTX supports the following directives. The .3.minnctapersm directives may be applied per-entry and must appear between an . the .maxntid directive specifies the maximum number of threads in a thread block (CTA).pragma directive is supported for passing information to the PTX backend. the .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM). A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.maxntid.maxnctapersm (deprecated) .maxnreg directive specifies the maximum number of registers to be allocated to a single thread.maxntid . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. which pass information to the backend optimizing compiler.maxnreg . These can be used.entry directive and its body. Note that . registers) to increase total thread count and provide a greater opportunity to hide memory latency.PTX ISA Version 2. at entry-scope.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. 2010 . or as statements within a kernel or device function body.maxntid and .

The maximum number of threads is the product of the maximum extent in each dimension.entry foo . Supported on all target architectures. Performance-Tuning Directives: .maxntid and .3.maxntid 256 .maxntid .maxntid Syntax Maximum number of threads in thread block (CTA). The actual number of registers used may be less.3.entry bar . . nz Declare the maximum number of threads in the thread block (CTA). Directives Table 134.maxnreg . for example. The compiler guarantees that this limit will not be exceeded.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.maxnreg n Declare the maximum number of registers per thread in a CTA.maxntid nx. or 3D CTA. the backend may be able to compile to fewer registers. . ny. . 2010 163 .entry foo .Chapter 10.16.maxctapersm.maxntid 16. This maximum is specified by giving the maximum extent of each dimention of the 1D. The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears. Supported on all target architectures. 2D. . Introduced in PTX ISA version 1. Exceeding any of these limits results in a runtime error or kernel launch failure. ny . Performance-Tuning Directives: . Introduced in PTX ISA version 1. or the maximum number of registers may be further constrained by .maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.maxntid nx.maxntid nx .

minnctapersm 4 { … } 164 January 24. additional CTAs may be mapped to a single multiprocessor.minnctapersm in PTX ISA version 2. Optimizations based on .PTX ISA Version 2. Introduced in PTX ISA version 2. . 2010 .0.maxntid to be specified as well. .3.maxntid and .maxntid to be specified as well. Deprecated in PTX ISA version 2.minnctapersm generally need .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Introduced in PTX ISA version 1. if the number of registers used by the backend is sufficiently lower than this bound. Supported on all target architectures.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor. Performance-Tuning Directives: . .maxnctapersm.maxnctapersm generally need .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. The optimizing backend compiler uses . For this reason. Optimizations based on .minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137. Performance-Tuning Directives: . .0 Table 136. However.0 as a replacement for .maxnctapersm (deprecated) .0.entry foo . Supported on all target architectures.maxntid 256 .maxntid 256 .maxnctapersm has been renamed to .entry foo .minnctapersm .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM). .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).

Introduced in PTX ISA version 2.pragma list-of-strings .pragma “nounroll”. 2010 165 .Chapter 10. Pass module-scoped.pragma directive may occur at module-scope.0. Supported on all target architectures.entry foo . entry-scoped.pragma “nounroll”. The . Directives Table 138. or statement-level directives to the PTX backend compiler. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . . The interpretation of . See Appendix A for descriptions of the pragma strings defined in ptxas. Performance-Tuning Directives: .pragma directive strings is implementation-specific and has no impact on PTX semantics.pragma Syntax Description Pass directives to PTX backend compiler. . or at statementlevel.pragma . { … } January 24. at entry-scope.

264-1] . 2010 . 0x00 . 0x00. Introduced in PTX ISA version 1.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.232-1] .PTX ISA Version 2. @@DWARF dwarf-string dwarf-string may have one of the .section . 0x5f736f63 .. Deprecated as of PTX 2.4byte 0x000006b5.4byte label . 0x61395a5f.4byte .quad int64-list // comma-separated hexadecimal integers in range [0.byte byte-list // comma-separated hexadecimal byte values . 0x00.0 but is supported for legacy PTX version 1. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . 0x00000364. 0x00.4byte int32-list // comma-separated hexadecimal integers in range [0.section directive. Supported on all target architectures. 0x00.file . The @@DWARF syntax is deprecated as of PTX version 2. replaced by .debug_info .byte 0x00.0. 0x00. 0x63613031.4byte 0x6e69616d. 0x02.4. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.. “”.2. @progbits .section directive is new in PTX ISA verison 2. 0x00 166 January 24.byte 0x2b. 0x00. Table 139.0 10. 0x736d6172 .loc The .x code.0 and replaces the @@DWARF syntax.debug_pubnames. 0x6150736f.section .

Debugging Directives: .b8 0x2b.b8 0x00.255] .loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. } 0x02. 0x00.b32 int32-list // comma-separated list of integers in range [0. 0x63613031.. 2010 167 . 0x00000364.debug_pubnames { . 0x00.264-1] .0. Supported on all target architectures. Debugging Directives: .loc line_number January 24.section Syntax PTX section definition. .b32 0x6e69616d.Chapter 10. .232-1] . Source file information.b32 0x000006b5. 0x736d6172 0x00 Table 141.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32 label . . Supported on all target architectures. 0x5f736f63 0x6150736f. Supported on all target architectures.section . 0x00.b64 int64-list // comma-separated list of integers in range [0. replaces @@DWARF syntax. .section .debug_info .0. Directives Table 140. Debugging Directives: .b8 byte-list // comma-separated list of integers in range [0. .section section_name { dwarf-lines } dwarf-lines have the following formats: .file . 0x00 0x61395a5f.. 0x00.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Source file location.loc .0.. 0x00. . . 0x00.b32 .file filename Table 142.

PTX ISA Version 2. Introduced in PTX ISA version 1. // foo is defined in another module Table 144.0 10. Supported on all target architectures. .global . Linking Directives: .6. .extern .visible . .extern identifier Declares identifier to be defined externally.visible Table 143.extern .0.0. 2010 .visible . // foo will be externally visible 168 January 24. Linking Directives . Linking Directives: . Introduced in PTX ISA version 1. .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures.b32 foo.visible identifier Declares identifier to be externally visible.extern .b32 foo.global .

0 January 24. Release Notes This section describes the history of change in the PTX ISA and implementation. CUDA Release CUDA 1.5 PTX ISA 2.1 CUDA 2.1 CUDA 2.2 PTX ISA 1.3 driver r190 CUDA 3. The release history is as follows.3 PTX ISA 1.1 PTX ISA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0.0 driver r195 PTX ISA Version PTX ISA 1.4 PTX ISA 1.0 CUDA 1.0 CUDA 2. 2010 169 .0 PTX ISA 1. and the remaining sections provide a record of changes in previous releases.2 CUDA 2.Chapter 11.

ftz modifier may be used to enforce backward compatibility with sm_1x.f32 maps to fma. • • • • • 170 January 24.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.0 11.and double-precision div. The fma. and sqrt with IEEE 754 compliant rounding have been added.f32 instruction also supports .rp rounding modifiers for sm_20 targets.1.0 11.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.1.f32 require a rounding modifier for sm_20 targets. sub.1.x code and sm_1x targets. fma. Instructions testp and copysign have been added. mad.f32 requires sm_20. while maximizing backward compatibility with legacy PTX 1.f32. 2010 .1. When code compiled for sm_1x is executed on sm_20 devices.rm and .PTX ISA Version 2. rcp. New Features 11. Floating-Point Extensions This section describes the floating-point changes in PTX 2.rn.1. These are indicated by the use of a rounding modifier and require sm_20.ftz and . The mad. Single-precision add. and mul now support . Changes in Version 2. The mad.f32 for sm_20 targets.sat modifiers. The goal is to achieve IEEE 754 compliance wherever possible. The .1.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.0 for sm_20 targets. Both fma.f32 and mad. The changes from PTX ISA 1. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Single. A single-precision fused multiply-add (fma) instruction has been added.

red}. Surface instructions support additional . and red now support generic addressing. . e. Instructions {atom. for prefetching to specified level of memory hierarchy. Instructions {atom.ballot.1.shared have been extended to handle 64-bit data types for sm_20 targets.b32.clamp and . A “count leading zeros” instruction. 11.clamp modifiers.u32 and bar.3. isspacep. ldu. st. Instruction sust now supports formatted surface stores. A system-level membar instruction.add.arrive instruction has been added.f32 have been implemented.1. Instructions bar. Cache operations have been added to instructions ld.red}. 2010 171 . vote. and shared addresses to generic address and vice-versa has been added. A “population count” instruction. Instructions prefetch and prefetchu have also been added.g. has been added.ge. ldu. brev. A “find leading non-sign bit” instruction.zero. A “vote ballot” instruction.pred have been added. New instructions A “load uniform” instruction.le. local.lt. The . Release Notes 11. membar. prefetchu. and sust. cvta. atom. Other new features Instructions ld. has been added.gt} have been added. prefetch. New special registers %nsmid. bfe and bfi. suld. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added.2. Instruction cvta for converting global.Chapter 11.red. %clock64. January 24.1. Bit field extract and insert instructions.or}. The bar instruction has been extended as follows: • • • A bar. A “bit reversal” instruction. bfind.maxnctapersm directive was deprecated and replaced with . .popc.sys. popc. st. has been added. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. have been added. Video instructions (includes prmt) have been added. has been added. has been added. bar now supports optional thread count and register operands.section. A new directive.minnctapersm to better match its behavior and usage. has been added. has been added. %lanemask_{eq. clz.red.1.{and.

red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. call suld. . has been fixed.target sm_1x. stack-based ABI is unimplemented.u32.f32.5. {atom.version is 1.1.f32} atom.2.max} are not implemented. 11. In PTX version 1.ftz for PTX ISA versions 1. To maintain compatibility with legacy PTX code. the correct number is sixteen.red}.4 and earlier.f32 type is unimplemented.ftz (and cvt for .s32. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. Formatted surface store with . where . Instruction bra. 172 January 24.3. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. if . where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.s32.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.{min. Semantic Changes and Clarifications The errata in cvt. The underlying. Support for variadic functions and alloca are unimplemented. See individual instruction descriptions for details. Formatted surface load is unimplemented.p.1.p sust. 2010 . cvt.0 11.4 or earlier.{u32.PTX ISA Version 2. or .5 and later.

and statement levels. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge. Descriptions of .Appendix A. Supported only for sm_20 targets. . The “nounroll” pragma is allowed at module. disables unrolling of0 the loop for which the current block is the loop header. … @p bra L1_end.pragma “nounroll”. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored.0. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler.pragma. L1_body: … L1_continue: bra L1_head. Note that in order to have the desired effect at statement level. including loops preceding the .func bar (…) { … L1_head: .pragma strings defined by ptxas. Ignored for sm_1x targets. . disables unrolling for all loops in the entry function body. { … } // do not unroll any loop in this function . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.pragma Strings This section describes the .pragma “nounroll”. entry-function. 2010 173 . Table 145.pragma “nounroll”.entry foo (…) . L1_end: … } // do not unroll this loop January 24. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler.

0 174 January 24. 2010 .PTX ISA Version 2.

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