NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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............2............. 42 Arrays as Operands .............................................................................................................................. 37 Vectors ..............................5.............. Texture. 5........1..................1.....2................................ and Variables .............................................. Summary of Constant Expression Evaluation Rules ............................................4...........4............................................4....... 33 5................................. 37 Variable Declarations ...................2..... 6....................................................................... 49 7............. 43 6........................................................................... State Spaces ...............................5.............................................2....................................... 5....6..... 28 Constant State Space ...1........................1..... 49 ii January 24................................................... Abstracting the ABI ....... 25 Chapter 5.......................2. 46 6................................................................................................1........................ and Surface Types .. 38 Alignment ............................................................ 6....................1.................PTX ISA Version 2..................................................... and Vectors ..... 5..............................................................................................6........... 5....................... 41 Source Operands.....4. 27 Register State Space ...................................................4........................7................................. 5.................................................... 37 Array Declarations ...............................................1...............................2.....3........................................................... 43 Labels and Function Names as Operands .........1.............. 41 6.............................4........................3............0 4..................................................5................................... 6.........4. Function declarations and definitions .. 32 5..................... Chapter 6.................. 38 Initializers . 34 Variables . 5. 6............ 32 Texture State Space (deprecated) .....1..... 5......... 29 Local State Space .......................... 5............... 39 Parameterized Variable Names ............................. 39 5...................................................................... 6......................................................................... 5...1.. Operand Type Information .......... 47 Chapter 7.......... 5............. 28 Special Register State Space ... 27 5.......................................... Arrays.............1................................................. 5......................................................... 2010 ........... 6...............................1..........3............................. Sampler......4. Types.......................................................... Types ................... 5............6.......... 5................................................................ Instruction Operands............... 29 Parameter State Space ......................................................................................................... 5..................8....................................................................3.................4....................................................4.......................................2................ 5..... 44 Scalar Conversions ............................4..........3....... State Spaces..................................................................................... 29 Global State Space .. 30 Shared State Space.......1...... 6.......................1................ 41 Destination Operands ................ Type Conversion....................... 6................ 44 Rounding Modifiers ............................5....................................4.........2........................4..........4.......................5......2......... Operand Costs ..................................... 43 Vectors as Operands ............................................. 42 Addresses as Operands .1........1..... 5.................................. 33 Restricted Use of Sub-Word Sizes .............5............. 6........ 33 Fundamental Types ........................ 41 Using Addresses......................................4............................................6...

...................................................2..................1...............6...................................4.............................. 169 11..... 122 Control Flow Instructions ................. 8...........................................2............................................................7................................. Instruction Set ....... 2010 iii ..........7.. 147 8............... 59 Operand Size Exceeding Instruction-Type Size ...........................7........................... PTX Version and Target Directives ..1....6......................... 8................................. 149 Chapter 10...1.............................. 8.. 10.................................... 62 8..................................3........1........ 172 Unimplemented Features Remaining ................. Directives ............................................... 10............................................ 132 Video Instructions ............................................. 140 Miscellaneous Instructions. 8....2............... 162 Debugging Directives ................................................................ Changes in Version 2......2.6....... Release Notes ........... 62 Machine-Specific Semantics of 16-bit Code .. 166 Linking Directives .0 ................................................................................. 8.............................. 168 Chapter 11..................... 62 Semantics ........................ 10.....1.....4........................... 8........................................................ 60 8.......... Chapter 9....... 8........7................. 11.........9.....................................7............ 170 Semantic Changes and Clarifications ............................. 53 Alloca ......... 157 Specifying Kernel Entry Points and Functions ..2.................................................. Special Registers ...........................3............. 104 Data Movement and Conversion Instructions ........................ 10...................3...................................................6........................ 8...........1.......... 8..... 58 8.1...............5.................... Instructions ......3....................................................7... 8..........................7.............................. 55 Predicated Execution .....................................4. 63 Floating-Point Instructions ...................................... 8......... 55 8.............................................................................3..........1......................... 54 Chapter 8................. 52 Variadic functions .....1......................... 160 Performance-Tuning Directives .......... 8........................... 8...................................................................................................... 172 January 24.....4............. 57 Manipulating Predicates .................................7..........10........................................................... Divergence of Threads in Control Constructs ...................................... 129 Parallel Synchronization and Communication Instructions ..............1.....................8..........................1................................................................................ 56 Comparisons ...................................... 7.................................................................................................................5..................................................................................... Type Information for Instructions and Operands .......................2................ 55 PTX Instructions ........................ 81 Comparison and Selection Instructions ........... 11........................3................................................ Format and Semantics of Instruction Descriptions .............. 170 New Features ............................. 8............................ 8.................................1. 8................7...........7.................................................... 7.......................7............................... 11..................................................................x ..................... 108 Texture and Surface Instructions ........ Changes from PTX 1............................................................................. 63 Integer Arithmetic Instructions ... 100 Logic and Shift Instructions .................. 157 10.......7.........7...........3.....................1.

............0 Appendix A...................pragma Strings..PTX ISA Version 2..... 2010 ....................... 173 iv January 24... Descriptions of ....

............................................................. Table 7......................... 70 Integer Arithmetic Instructions: sad ...............List of Tables Table 1.................................................. 71 January 24........................................ 47 Operators for Signed Integer................... Table 15................................................................ 67 Integer Arithmetic Instructions: mad ........ 27 Properties of State Spaces .......................................................................................... Table 28.......................... PTX Directives ......................................................................................... Table 10............................................................................ 58 Type Checking Rules .. Table 12..................................... Unsigned Integer. Table 5... 33 Opaque Type Fields in Unified Texture Mode ............................................ 58 Floating-Point Comparison Operators Testing for NaN ....... Table 27................................................ Table 8....... 35 Opaque Type Fields in Independent Texture Mode ........ Table 32.... 66 Integer Arithmetic Instructions: mul ............................................ 57 Floating-Point Comparison Operators Accepting NaN ................... Table 4........................................................ Table 30.................................................................. Table 2................. 65 Integer Arithmetic Instructions: addc ............................................................. 25 State Spaces ....................................................................... 68 Integer Arithmetic Instructions: mul24 ......................................... 20 Operator Precedence .... 46 Cost Estimates for Accessing State-Spaces .................................................................................... Table 13................................. Table 23........... 19 Predefined Identifiers ................. Table 29................................................... Table 14............................... Table 20............................. 2010 v ........ 64 Integer Arithmetic Instructions: sub .. Table 21................... 18 Reserved Instruction Keywords .................................................................... 65 Integer Arithmetic Instructions: sub... Table 16..................................................................... 60 Relaxed Type-checking Rules for Destination Operands.... 69 Integer Arithmetic Instructions: mad24 ..............................cc ........................................cc ........... Table 22..... 66 Integer Arithmetic Instructions: subc ............. 46 Integer Rounding Modifiers .......................................................................... Table 24....................................................................................... 57 Floating-Point Comparison Operators ... Table 17........................................................................................................ 64 Integer Arithmetic Instructions: add... 61 Integer Arithmetic Instructions: add ............................................................. Table 31..................... 45 Floating-Point Rounding Modifiers .................................. 28 Fundamental Type Specifiers ........................................................... Table 18............... 23 Constant Expression Evaluation Rules . Table 25............................................. and Bit-Size Types ................................ Table 26............ Table 6.. 35 Convert Instruction Precision and Format ..................................... Table 3.......................... Table 9.............................. Table 11............. Table 19....................................... 59 Relaxed Type-checking Rules for Source Operands .

................... 101 Comparison and Selection Instructions: setp ................................ Table 66............................................................................. 88 Floating-Point Instructions: div ............................ 74 Integer Arithmetic Instructions: bfind ............................................................................................................................................................ 98 Floating-Point Instructions: ex2 ............................... Table 34................................................... Table 35.................................... 86 Floating-Point Instructions: fma ........................ 91 Floating-Point Instructions: min ........... Table 36.0 Table 33................................................................................ 84 Floating-Point Instructions: sub .................. 74 Integer Arithmetic Instructions: clz ............................... Table 41............................................................... Table 42................................................................ Table 56......................................................... 73 Integer Arithmetic Instructions: popc ........................................ Table 38.................................................................. Table 47......................................................................................... Table 63.......................................... Table 49..................... 79 Summary of Floating-Point Instructions ..... 94 Floating-Point Instructions: rsqrt ................................................................................ 77 Integer Arithmetic Instructions: bfi . 75 Integer Arithmetic Instructions: brev ................................................................................................................... 95 Floating-Point Instructions: sin ............. Table 59.. 83 Floating-Point Instructions: add ............................................. 93 Floating-Point Instructions: sqrt ................................................. 102 Comparison and Selection Instructions: selp ........... Table 53................................................................................ Table 37.. Table 51........................................................................................... Table 44............................................................................................................................................. 76 Integer Arithmetic Instructions: bfe .................................................................................................... 103 vi January 24......... 83 Floating-Point Instructions: copysign ................ Table 50.................................................... 71 Integer Arithmetic Instructions: abs ............. Table 67.................................... Table 64.................... Table 45.. 85 Floating-Point Instructions: mul ......... Table 40....... 91 Floating-Point Instructions: neg . Table 55............................... 96 Floating-Point Instructions: cos ............... 90 Floating-Point Instructions: abs .............................. Table 46.................. 71 Integer Arithmetic Instructions: rem ..................................... Table 48....................... Table 57.............. Table 61........ Table 58.... 92 Floating-Point Instructions: rcp ...................... Table 43..................................... 99 Comparison and Selection Instructions: set ......... 82 Floating-Point Instructions: testp .. Table 60................... Table 54................PTX ISA Version 2........... 103 Comparison and Selection Instructions: slct .......................................... Table 68.................. 72 Integer Arithmetic Instructions: min ............................................... 87 Floating-Point Instructions: mad ..... 78 Integer Arithmetic Instructions: prmt .... Table 52.... 97 Floating-Point Instructions: lg2 ..................... 73 Integer Arithmetic Instructions: max ............................................................................................................................................................................... Table 69..................................... Integer Arithmetic Instructions: div ................................. Table 62..................................................................... Table 65............................... 72 Integer Arithmetic Instructions: neg .................. Table 39............ 92 Floating-Point Instructions: max ................................ 2010 ...............................

.................................. 115 Data Movement and Conversion Instructions: st .... 119 Data Movement and Conversion Instructions: cvta .......................................................................................................................... Table 85...... vmax ..................................................................................... 134 Parallel Synchronization and Communication Instructions: atom ...... 130 Control Flow Instructions: ret .................... Table 75.................Table 70............... Table 81................................ Table 84........................................ vmin... Table 86....................... Table 80................ Table 73...... 118 Data Movement and Conversion Instructions: isspacep ....................................... 105 Logic and Shift Instructions: or .................................... Table 97. Table 90............ Table 92..................... 133 Parallel Synchronization and Communication Instructions: membar ............................................ Table 91........................... 106 Logic and Shift Instructions: cnot ........... Table 88.................. 139 Video Instructions: vadd.................................................. Table 100............................ 129 Control Flow Instructions: @ ..... Table 82.. 126 Texture and Surface Instructions: sured......................... Table 71.... 129 Control Flow Instructions: bra ........... 113 Data Movement and Conversion Instructions: ldu .... Table 77................................................................................ 137 Parallel Synchronization and Communication Instructions: vote ..... 119 Data Movement and Conversion Instructions: cvt ....... 142 Video Instructions: vshl.......................................... vabsdiff....................................................... Table 95. 105 Logic and Shift Instructions: xor ................................. 106 Logic and Shift Instructions: shl ...................................................... Table 72.................. 125 Texture and Surface Instructions: sust .................... Table 103...... 130 Control Flow Instructions: call .................. 106 Logic and Shift Instructions: not ................................................................................. Table 94........................ 131 Parallel Synchronization and Communication Instructions: bar . 107 Cache Operators for Memory Load Instructions ................ 120 Texture and Surface Instructions: tex ..... 135 Parallel Synchronization and Communication Instructions: red ............ Table 105.................. Table 74......................... Table 87.......................................... Table 101........................................... Table 78........................................... Table 89........................................................ 127 Texture and Surface Instructions: suq ........................................ Table 106......................................... Table 102. Table 96................. 2010 vii ...................................................... 109 Cache Operators for Memory Store Instructions ................... Table 93................ 123 Texture and Surface Instructions: txq ................................ prefetchu .......................................................................................... Table 76.................................... Table 98. 111 Data Movement and Conversion Instructions: mov ....................................... Table 79........................ Table 99..................................................... vshr ..................................... 128 Control Flow Instructions: { } ..... Table 104....................... 107 Logic and Shift Instructions: shr ......................................... 112 Data Movement and Conversion Instructions: ld ............ 143 January 24................... 124 Texture and Surface Instructions: suld ............. vsub............................. 131 Control Flow Instructions: exit ....... Table 83............ 110 Data Movement and Conversion Instructions: mov ..................................................................................... 116 Data Movement and Conversion Instructions: prefetch.. Logic and Shift Instructions: and .........

Table 142............. Table 143....... 167 Debugging Directives: .......... Table 117. 144 Video Instructions: vset.......maxnreg ....................................... 164 Performance-Tuning Directives: ............................................................... Table 110....... 154 Special Registers: %lanemask_le ............................................... 153 Special Registers: %lanemask_eq .......................................................................................................... Table 134.... Table 132.......................................... 146 Miscellaneous Instructions: trap ....................................................................................................... Table 126.... Table 114....................................................................... 153 Special Registers: %nsmid ..................... Table 116............ 161 Performance-Tuning Directives: ............................................................maxnctapersm (deprecated) ................................................ 151 Special Registers: %warpid .................... Table 129............................................................................................................ Table 108....................... Table 109.......................... 157 PTX File Directives: ........................................................................................................ Table 141.......... 150 Special Registers: %ntid ........ Table 123......... 154 Special Registers: %lanemask_lt .......... Table 119....................... %pm2..................... 167 Linking Directives: ............... Table 127................. 151 Special Registers: %nwarpid ................maxntid .................. 163 Performance-Tuning Directives: ............ 167 Debugging Directives: ................. 153 Special Registers: %gridid .......................................... Table 131................. Table 125.......................................................extern............. 166 Debugging Directives: ............................................... Table 122................................. Table 115........ 160 Kernel and Function Directives: ......... 147 Miscellaneous Instructions: pmevent............................... Table 128............ 164 Performance-Tuning Directives: ..func .................................... 158 Kernel and Function Directives: ................ 154 Special Registers: %lanemask_ge .............entry.......................PTX ISA Version 2................................................. Table 140.....................................section ....................................................... 151 Special Registers: %ctaid .................................... Table 135. 168 viii January 24......... 155 Special Registers: %clock .......... Table 136................................................. 156 PTX File Directives: ........target ............................minnctapersm . Table 121.....................pragma ..................................................................................................0 Table 107................................................................ Table 139..... Table 137... Table 120.............file ... Table 130.......................................................... 156 Special Registers: %pm0.......... 152 Special Registers: %nctaid .. %pm3 ................................. 147 Miscellaneous Instructions: brkpt ............................ Table 124..... 152 Special Registers: %smid .......................................................................................... 165 Debugging Directives: @@DWARF ...... 2010 ..... 156 Special Registers: %clock64 .................................... %pm1..................................... Table 133......................................................... 150 Special Registers: %laneid ....................................................................... 163 Performance-Tuning Directives: .... Table 138......................................................................loc .......................................... 147 Special Registers: %tid ...........................................version...... 155 Special Registers: %lanemask_gt ..... Table 113.................... Table 112......................................................................................... Video Instructions: vmad ......... Table 111................................. Table 118............

............. Table 145..................................................................... 2010 ix ... 173 January 24...................................................... 168 Pragma Strings: “nounroll” .Table 144.......... Linking Directives: ..visible...................

2010 .PTX ISA Version 2.0 x January 24.

there is a lower requirement for sophisticated flow control. a low-level parallel thread execution virtual machine and instruction set architecture (ISA).1. Similarly. many-core processor with tremendous computational horsepower and very high memory bandwidth.Chapter 1. Data-parallel processing maps data elements to parallel processing threads. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time. from general signal processing or physics simulation to computational finance or computational biology. which are optimized for and translated to native target-architecture instructions. the memory access latency can be hidden with calculations instead of big data caches. and pattern recognition can map image blocks and pixels to parallel processing threads. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. PTX exposes the GPU as a data-parallel computing device. 1. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. image and media processing applications such as post-processing of rendered images. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture.2. PTX programs are translated at install time to the target hardware instruction set. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. stereo vision. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. video encoding and decoding. In fact. image scaling. the programmable GPU has evolved into a highly parallel. 1. Because the same program is executed for each data element. PTX defines a virtual machine and ISA for general purpose parallel thread execution. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. multithreaded. high-definition 3D graphics. Introduction This document describes PTX. and because it is executed on many data elements and has high arithmetic intensity. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. 2010 1 . January 24. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers.

A “flush-to-zero” (. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Single-precision add. sub. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. When code compiled for sm_1x is executed on sm_20 devices. 2010 .0 is in improved support for the IEEE 754 floating-point standard. Legacy PTX 1. The main areas of change in PTX 2. which map PTX to specific target machines. addition of generic addressing to facilitate the use of general-purpose pointers. 1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. Provide a machine-independent ISA for C/C++ and other compilers to target. Improved Floating-Point Support A main area of change in PTX 2. The fma.f32 requires sm_20.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. and mul now support . and all PTX 1. Provide a code distribution ISA for application and middleware developers. barrier.0 are improved support for IEEE 754 floating-point operations. Achieve performance in compiled applications comparable to native GPU performance.0 is a superset of PTX 1. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units. Instructions marked with . memory.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets. fma. The mad.f32 maps to fma. The changes from PTX ISA 1. The mad.ftz) modifier may be used to enforce backward compatibility with sm_1x.3.f32 for sm_20 targets.f32 and mad.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.x features are supported on the new sm_20 target.x code will continue to run on sm_1x targets as well.x.rn. A single-precision fused multiply-add (fma) instruction has been added.ftz and .f32.sat modifiers. atomic. Provide a common source-level ISA for optimizing code generators and translators.rm and . Most of the new features require a sm_20 target. and architecture tests. PTX 2. 1. PTX ISA Version 2.3.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero.PTX ISA Version 2. including integer. • • • 2 January 24.f32 instruction also supports . Both fma.rp rounding modifiers for sm_20 targets. surface. Facilitate hand-coding of libraries. and the introduction of many new instructions. reduction.f32 require a rounding modifier for sm_20 targets. and video instructions.0 PTX ISA Version 2.1. mad. performance kernels.

allowing memory instructions to access these spaces without needing to specify the state space. i. Generic addressing unifies the global. NOTE: The current version of PTX does not implement the underlying. cvta. local. prefetch.3. and shared state spaces.4.e. stack layout. 2010 3 .and double-precision div.3. Cache operations have been added to instructions ld. Surface instructions support additional clamp modifiers.0. In PTX 2. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. special registers. Instructions testp and copysign have been added.. for prefetching to specified level of memory hierarchy.0 provides a slightly higher-level abstraction and supports multiple ABI implementations. and directives are introduced in PTX 2. an address that is the same across all threads in a warp.3.zero. Generic Addressing Another major change is the addition of generic addressing. These are indicated by the use of a rounding modifier and require sm_20.Chapter 1. New Instructions The following new instructions. 1. isspacep.g. e.3.clamp and . ldu. 1. suld. and vice versa. Surface Instructions • • Instruction sust now supports formatted surface stores. 1. these changes bring PTX 2.0 closer to full compliance with the IEEE 754 standard. . so recursion is not yet supported. and sqrt with IEEE 754 compliant rounding have been added. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Instructions prefetch and prefetchu have been added. st. • Taken as a whole. prefetchu. and shared addresses to generic address and vice-versa has been added. Support for an Application Binary Interface Rather than expose details of a particular calling convention. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. Instruction cvta for converting global. January 24. and Application Binary Interface (ABI). and shared addresses to generic addresses. local. instructions ld.0. atom. PTX 2. rcp. and sust. and red now support generic addressing. Introduction • Single.2. st. stack-based ABI. A new cvta instruction has been added to convert global. local.

PTX ISA Version 2.red.shared have been extended to handle 64-bit data types for sm_20 targets. 2010 . 4 January 24. Instructions {atom. %lanemask_{eq.{and.add.red}.red}.le.section.b32.u32 and bar.ge.sys.arrive instruction has been added. Instructions bar. Barrier Instructions • • A system-level membar instruction.red. Reduction.ballot. has been added. A “vote ballot” instruction.pred have been added. and Vote Instructions • • • New atomic and reduction instructions {atom.f32 have been added. has been added. New special registers %nsmid.popc. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. A new directive. bfi bit field extract and insert popc clz Atomic. vote. membar. A bar. %clock64.gt} have been added. . Other Extensions • • • Video instructions (includes prmt) have been added.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.lt. bar now supports an optional thread count and register operands.or}.

The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model. Chapter 4 describes the basic syntax of the PTX language. and variable declarations. January 24. Chapter 11 provides release notes for PTX Version 2. Chapter 3 gives an overview of the PTX virtual machine model. Chapter 6 describes instruction operands. Chapter 7 describes the function and call syntax. types. Chapter 8 describes the instruction set. Introduction 1. 2010 5 . Chapter 10 lists the assembly directives supported in PTX. Chapter 5 describes state spaces. and PTX support for abstracting the Application Binary Interface (ABI).0. calling convention.Chapter 1.4. Chapter 9 lists special registers.

PTX ISA Version 2.0 6 January 24. 2010 .

(with elements tid. A cooperative thread array.2. tid. and select work to perform. Each CTA has a 1D. a portion of an application that is executed many times.y. or 3D CTA. It operates as a coprocessor to the main CPU. The thread identifier is a three-element vector tid. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension. To coordinate the communication of the threads within the CTA. ntid. can be isolated into a kernel function that is executed on the GPU as many different threads. work. Cooperative thread arrays (CTAs) implement CUDA thread blocks. Each CTA thread uses its thread identifier to determine its assigned role.1. compute addresses.2. Threads within a CTA can communicate with each other. To that effect. 2D.Chapter 2. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. but independently on different data. compute-intensive portions of applications running on the host are off-loaded onto the device. 2010 7 . 2. 2. Programs use a data parallel decomposition to partition inputs.1.x. and ntid. or CTA. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel. The vector ntid specifies the number of threads in each CTA dimension. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1. January 24.x. or host: In other words. assign specific input and output positions.y. Programming Model 2. data-parallel. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set.z). and tid. More precisely. and results across the threads of the CTA.z) that specifies the thread’s position within a 1D. or 3D shape specified by a three-element vector ntid (with elements ntid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. 2D. Each thread has a unique thread identifier within the CTA. is an array of threads that execute a kernel concurrently or in parallel.

Typically. Each grid also has a unique temporal grid identifier (gridid).2.PTX ISA Version 2. %ntid. depending on the platform. WARP_SZ. 2D . multiple-thread) fashion in groups called warps. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. so that the total number of threads that can be launched in a single kernel invocation is very large.2. because threads in different CTAs cannot communicate and synchronize with each other. %ctaid. or 3D shape specified by the parameter nctaid. 2.0 Threads within a CTA execute in SIMT (single-instruction. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. However. Multiple CTAs may execute concurrently and in parallel. such that the threads execute the same instructions at the same time. so PTX includes a run-time immediate constant. Threads may read and use these values through predefined. Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). The warp size is a machine-dependent constant. Threads within a warp are sequentially numbered. The host issues a succession of kernel invocations to the device. This comes at the expense of reduced thread communication and synchronization. read-only special registers %tid. and %gridid. 2010 . a warp has 32 threads. A warp is a maximal subset of threads from a single CTA. 8 January 24. which may be used in any instruction where an immediate operand is allowed. or sequentially. CTAs that execute the same kernel can be batched together into a grid of CTAs. %nctaid. Some applications may be able to maximize performance with knowledge of the warp size. Each grid of CTAs has a 1D.

1) Thread (1.Chapter 2. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 2) Thread (3. 2) Thread (1. 2010 9 . 2) Thread (4. A grid is a set of CTAs that execute independently. 0) Thread (4. Figure 1. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 0) Thread (3. 0) CTA (1. 0) CTA (0. 1) CTA (2. 0) Thread (1. 0) CTA (2. 0) Thread (2. 1) Thread (0. 1) Thread (3. 2) Thread (2. 1) Thread (2. 0) Thread (0. 1) CTA (1. 1) Thread (4. 1) Thread (0. Thread Batching January 24. 1) Grid 2 Kernel 2 CTA (1.

10 January 24. copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. and texture memory spaces are optimized for different memory usages. The device memory may be mapped and read or written by the host. Each thread has a private local memory. all threads have access to the same global memory.0 2. respectively. Finally. Both the host and the device maintain their own local memory. Texture memory also offers different addressing modes. constant. for more efficient transfer. for some specific data formats. or.PTX ISA Version 2. and texture memory spaces are persistent across kernel launches by the same application. 2010 . The global. The global. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. constant. as well as data filtering. referred to as host memory and device memory. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block.3.

Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (2. 0) Block (0. 2) Block (1. 1) Grid 1 Global memory Block (0.Chapter 2. Memory Hierarchy January 24. 0) Block (1. 1) Block (1. 1) Block (0. 2) Figure 2. 2010 11 . 1) Block (2. 1) Block (1. 0) Block (1. 0) Block (0.

PTX ISA Version 2.0 12 January 24. 2010 .

for example. Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. the multiprocessor employs a new architecture we call SIMT (single-instruction. a voxel in a volume. As thread blocks terminate. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. (This term originates from weaving. If threads of a warp diverge via a data-dependent conditional branch. allowing. the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. Branch divergence occurs only within a warp. To manage hundreds of threads running several different programs. manages.1. the warp serially executes each branch path taken. It implements a single-instruction barrier synchronization. the first parallel thread technology. The multiprocessor creates. Parallel Thread Execution Machine Model 3. 2010 13 . The multiprocessor maps each thread to one scalar processor core. The way a block is split into warps is always the same. and each scalar thread executes independently with its own instruction address and register state. When a multiprocessor is given one or more thread blocks to execute.Chapter 3. a cell in a grid-based computation). so full efficiency is realized when all threads of a warp agree on their execution path. The threads of a thread block execute concurrently on one multiprocessor. it splits them into warps that get scheduled by the SIMT unit. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). schedules. new blocks are launched on the vacated multiprocessors. A warp executes one common instruction at a time. multiple-thread). a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image. and on-chip shared memory. increasing thread IDs with the first warp containing thread 0. disabling threads that are not on that path. At every instruction issue time. different warps execute independently regardless of whether they are executing common or disjointed code paths.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. manages. a multithreaded instruction unit. the threads converge back to the same execution path. and executes concurrent threads in hardware with zero scheduling overhead. The multiprocessor SIMT unit creates. and when all paths complete. A multiprocessor consists of multiple Scalar Processor (SP) cores. January 24. and executes threads in groups of parallel threads called warps. When a host program invokes a kernel grid. each warp contains threads of consecutive.

modifies. on the other hand. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. A multiprocessor can execute as many as eight thread blocks concurrently.0 SIMT architecture is akin to SIMD (Single Instruction. which is a read-only region of device memory. the number of serialized writes that occur to that location and the order in which they occur is undefined. In contrast with SIMD vector machines. 14 January 24. as well as data-parallel code for coordinated threads. but one of the writes is guaranteed to succeed. If an atomic instruction executed by a warp reads. but the order in which they occur is undefined. which is a read-only region of device memory. modify. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. If there are not enough registers or shared memory available per multiprocessor to process at least one block. each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor. SIMT enables programmers to write thread-level parallel code for independent. A key difference is that SIMD vector organizations expose the SIMD width to the software. scalar threads. 2010 . require the software to coalesce loads into vectors and manage divergence manually. the kernel will fail to launch. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. In practice.PTX ISA Version 2. For the purposes of correctness. and writes to the same location in global memory for more than one of the threads of the warp. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. Vector architectures. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. As illustrated by Figure 3. • The local and global memory spaces are read-write regions of device memory and are not cached. whereas SIMT instructions specify the execution and branching behavior of a single thread. however. the programmer can essentially ignore the SIMT behavior. each read. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. write to that location occurs and they are all serialized.

Chapter 3. 2010 15 . Figure 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory. Hardware Model January 24.

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The C preprocessor cpp may be used to process PTX source files. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. PTX is case sensitive and uses lowercase for keywords. Comments Comments in PTX follow C/C++ syntax. #ifdef. whitespace is ignored except for its use in separating tokens in the language. #endif.2. 2010 17 .1. #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Lines beginning with # are preprocessor directives. 4.version directive specifying the PTX language version. #line. Lines are separated by the newline character (‘\n’). Each PTX file must begin with a . #if. using non-nested /* and */ for comments that may span multiple lines. Source Format Source files are ASCII text. See Section 9 for a more information on these directives. January 24. 4. Comments in PTX are treated as whitespace. and using // to begin a comment that extends to the end of the current line. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files.target directive specifying the target architecture assumed. #define. Syntax PTX programs are a collection of text source files. followed by a .Chapter 4. The following are common preprocessor directives: #include. All whitespace characters are equivalent. #else. Pseudo-operations specify symbol and addressing management.

visible 4.version . %tid.maxnctapersm .b32 r1. followed by source operands. . // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. address expressions.extern .0 4.file PTX Directives .maxnreg . The guard predicate follows the optional label and precedes the opcode.minnctapersm . Operands may be register variables. The destination operand is first.2. Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands. mov.f32 array[N]. Statements A PTX statement is either a directive or an instruction. Directive Statements Directive keywords begin with a dot.global start: . constant expressions. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. Examples: .reg . Statements begin with an optional label and end with a semicolon. so no conflict is possible with user-defined identifiers.shared . 2.3. array[r1].entry .maxntid . The guard predicate may be optionally negated.func . ld.global. or label names. where p is a predicate register.x.b32 r1.tex . 0. 18 January 24.f32 r2. written as @!p. Instructions have an optional guard predicate which controls conditional execution. . 2010 .PTX ISA Version 2.b32 add.section .loc .align . r1.pragma .3.5. shl.param .sreg .local .b32 r1. and terminated with a semicolon. Instruction keywords are listed in Table 2.const .1. and is written as @p. Table 1.reg . r2. r2.3.global .target . All instruction keywords are reserved tokens in PTX. r2.

Syntax Table 2.Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24. 2010 19 .

Many high-level languages such as C and C++ follow similar rules for identifier names. between user-defined variable names and compiler-generated names. except that the percentage sign is not allowed. dollar. …. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. underscore. underscore. digits. or dollar characters. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. The percentage sign can be used to avoid name conflicts. %pm3 WARP_SZ 20 January 24. digits. PTX predefines one constant and a small number of special registers that begin with the percentage sign. e. PTX allows the percentage sign as the first character of an identifier.4. or percentage character followed by one or more letters.PTX ISA Version 2. Table 3. 2010 .g.0 4. listed in Table 3. or they start with an underscore.

Type checking rules remain the same for integer. hexadecimal.u64). the constant begins with 0d or 0D followed by 16 hex digits. Floating-point literals may be written with an optional decimal point and an optional signed exponent. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. The syntax follows that of C.s64 or . i. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. zero values are FALSE and non-zero values are TRUE. integer constants are allowed and are interpreted as in C. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform.e.5.2. such values retain their exact 32-bit single-precision value and may not be used in constant expressions.5.s64) unless the value cannot be fully represented in . literals are always represented in 64-bit double-precision format. 2010 21 . Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. and bit-size types.. Integer literals may be written in decimal. octal. each integer constant is converted to the appropriate size based on the data or instruction type at its use.e. For predicate-type data and instructions. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. where the behavior of the operation depends on the operand types. floating-point. 0[fF]{hexdigit}{8} // single-precision floating point January 24. the sm_1x and sm_20 targets have a WARP_SZ value of 32. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. These constants may be used in data initialization and as operands to instructions. 4. Syntax 4. in which case the literal is unsigned (.. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.s64 or the unsigned suffix is specified. When used in an instruction or data initialization.Chapter 4. i. the constant begins with 0f or 0F followed by 8 hex digits. or binary notation.1. To specify IEEE 754 single-precision floating point values. 4. Constants PTX supports integer and floating-point constants and constant expressions. To specify IEEE 754 doubleprecision floating point values. Unlike C and C++. there is no suffix letter to specify size.u64. every integer constant has type . Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.5. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

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u64 .s64.s64 . Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .5.u64) (.u64 .f64 integer .s64 . 2nd is . Table 5.u64 same as 1st operand .f64 use usual conversions .f64 same as source .s64 .f64 : .f64 integer integer integer integer integer int ?.u64 .f64 use usual conversions . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64 .s64 .6.f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero .f64 converted type constant literal + ! ~ Cast Binary (. .u64 . 2010 25 .f64 converted type .u64 .s64 .f64 use usual conversions .u64.Chapter 4.s64) + .f64 integer .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.s64 . or . Syntax 4.u64 1st unchanged.u64 .s64 .

2010 .0 26 January 24.PTX ISA Version 2.

Local memory. The characteristics of a state space include its size. private to each thread. Types. shared by all threads. Kernel parameters. and these resources are abstracted in PTX through state spaces and data types. and Variables While the specific resources available in a given target GPU will vary. read-only memory.param . All variables reside in some state space. and properties of state spaces are shown in Table 5. and level of sharing between threads. addressability.const .local . Shared. Name State Spaces Description Registers.sreg . Special registers. defined per-grid.reg . fast.global . State Spaces. State Spaces A state space is a storage area with particular characteristics. or Function or local parameters. platform-specific.shared . Global texture memory (deprecated). defined per-thread. the kinds of resources will be common across platforms. Addressable memory shared between threads in 1 CTA. access speed. The list of state spaces is shown in Table 4.1.tex January 24. . pre-defined. The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. access rights.Chapter 5. Table 6. 2010 27 . Read-only. 5. Global memory.

there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).param instruction. 5.param and st.PTX ISA Version 2.1.1.reg state space) are fast storage locations. causing changes in performance. or 64-bits. CTA. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. Registers may have alignment boundaries required by multi-word loads and stores. scalar registers have a width of 8-. The number of registers is limited. and cvt instructions. and will vary from platform to platform.local .param instructions. 32-. st. Device function input parameters may have their address taken via mov. 64-. 3 Accessible only via the tex instruction. platform-specific registers. and performance monitoring registers. or 128-bits. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context .const .param (used in functions) . such as grid. or as elements of vector tuples.2. 1 Accessible only via the ld. 28 January 24.tex Restricted Yes No3 5. floating point.sreg) state space holds predefined.0 Table 7.reg . 16-.1.shared . the parameter is then located on the stack frame and its address is in the . The most common use of 8-bit registers is with ld. Registers differ from the other state spaces in that they are not fully addressable.global . All special registers are predefined. 2010 . For each architecture. predicate) or untyped. and vector registers have a width of 16-.local state space. i. When the limit is exceeded. Registers may be typed (signed integer. 32-.. unsigned integer. Register size is restricted. and thread parameters. it is not possible to refer to the address of a register. 2 Accessible via ld. aside from predicate registers which are 1-bit. clock counters. Register State Space Registers (. Special Register State Space The special register (.param (as input to kernel) . Address may be taken via mov instruction. register variables will be spilled to memory.sreg .e.

The size is limited.local and st.1.local) is private memory for each thread to keep its own data. Local State Space The local state space (. For any thread in a context. It is typically standard memory with cache. for example). the stack is in local memory.const[2] .sync instruction are guaranteed to be visible to any reads after the barrier instruction. Banks are specified using the . If no bank number is given. // load second word 5.1. 2010 29 . whereas local memory variables declared January 24.b32 const_buffer[].global. [const_buffer+4]. The remaining banks may be used to implement “incomplete” constant arrays (in C. For the current devices. where the size is not known at compile time. the declaration . For example.3. Use ld. bank zero is used for all statically-sized constant variables. In implementations that support a stack.global) state space is memory that is accessible by all threads in a context. Module-scoped local memory variables are stored at fixed addresses. Global State Space The global (. Global memory is not sequentially consistent. and Variables 5. the bank number must be provided in the state space of the load instruction.global to access global variables. 5.b32 %r1. initialized by the host. By convention.extern . ld. Threads wait at the barrier until all threads in the CTA have arrived. This reiterates the kind of parallelism available in machines that run PTX.local to access local variables. each pointing to the start address of the specified constant bank. Types.global. the store operation updating a may still be in flight.5. Constant State Space The constant (. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown.4. Use ld. st. Multiple incomplete array variables declared in the same bank become aliases. where bank ranges from 0 to 10. If another thread sees the variable b change. bank zero is used. as in lock-free and wait-free style programming. Consider the case where one thread executes the following two assignments: a = a + 1. To access data in contant banks 1 through 10. Threads must be able to do their work without waiting for other threads to do theirs. This pointer can then be used to access the entire 64KB constant bank. results in const_buffer pointing to the start of constant bank two. The constant memory is organized into fixed size banks.1.sync instruction.const) state space is a read-only memory.Chapter 5. and atom. State Spaces.const[2]. For example. as it must be allocated on a perthread basis. b = b – 1.const[bank] modifier. Sequential consistency is provided by the bar. All memory writes prior to the bar. It is the mechanism by which different CTAs and different grids can communicate. an incomplete array in bank 2 is accessed as follows: .extern . all addresses are in global memory are shared. there are eleven 64KB banks.b32 const_buffer[].const[2] .

param space variables.b32 N.entry foo ( . ld.align 8 . Similarly. No access protection is provided between parameter and global space in this case. mov. [buffer].reg . The kernel parameter variables are shared across all CTAs within a grid.f64 %d.param . (2a) to declare formal input and return parameters for device functions called from within kernel execution.0 within a function or kernel body are allocated on the stack.param state space and is accessed using ld. . %n. [%ptr].x supports only kernel function parameters in .reg .u32 %ptr. Note that PTX ISA versions 1. For example.param.u32 %n.param . Note: The location of parameter space is implementation specific.PTX ISA Version 2. The resulting address is in the . Example: . Values passed from the host to the kernel are accessed through these parameter variables using ld.param state space. read-only variables declared in the . Parameter State Space The parameter (.param space.param.1. ld. len. 5. and (2b) to declare locally-scoped byte array variables that serve as function call arguments. … 30 January 24.reg . . typically for passing large structures by value to a function. ld. 2010 .param .6. 5. in some implementations kernel parameters reside in global memory. Therefore.1.param.b32 len ) { .1.param instructions. The use of parameter state space for device function parameters is new to PTX ISA version 2. … Example: . Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write. PTX code should make no assumptions about the relative locations or ordering of . all local memory variables are stored at fixed addresses and recursive function calls are not supported. Kernel Function Parameters Each kernel function definition includes an optional list of parameters. [N].0 and requires target architecture sm_20.param instructions.entry bar ( .6.u32 %ptr. per-kernel versus per-thread). These parameters are addressable. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI).u32 %n.param) state space is used (1) to pass input arguments from the host to the kernel.f64 %d. In implementations that do not support a stack.b8 buffer[64] ) { .u32 %n. device function parameters were previously restricted to the register state space. The address of a kernel parameter may be moved into a register using the mov instruction.

0 extends the use of parameter space to device function parameters. the caller will declare a locally-scoped .param. a byte array in parameter space is used. ld. State Spaces.b8 mystruct. . } mystruct.f64 %d.reg . dbl.param.1.b32 N. }.param . passed to foo … .reg .f64 %d.align 8 . and Variables 5. Note that the parameter will be copied to the stack if necessary. and so the address will be in the . x. such as C structures larger than 8 bytes. [buffer]. st.param. int y.param . .s32 %y.local instructions. it is illegal to write to an input parameter or read from a return parameter. In PTX.param.Chapter 5. mystruct). call foo. Aside from passing structures by value.s32 x.param byte array variable that represents a flattened C structure or union.reg . 2010 31 . .s32 %y. January 24.param space is also required whenever a formal parameter has its address taken within the called function.align 8 .func foo ( . which declares a .2. ld.b8 buffer[12] ) { . (4. int y. … See the section on function call syntax for more details. This will be passed by value to a callee. … st. Types.param space variable. [buffer+8]. . Typically.6.s32 [mystruct+8].f64 dbl.param and function return parameters may be written using st. Device Function Parameters PTX ISA version 2.local and st. is flattened. In this case. … } // code snippet from the caller // struct { double d.param. The most common use is for passing objects by value that do not fit within a PTX register. . It is not possible to use mov to get the address of a return parameter or a locally-scoped . Example: // pass object of type struct { double d. .reg . the address of a function input parameter may be moved into a register using the mov instruction.param formal parameter having the same size and alignment as the passed argument.reg . Function input parameters may be read via ld.local state space and is accessed via ld.f64 [mystruct+0].

Physical texture resources are allocated on a per-module granularity. 32 January 24.tex variables are required to be defined in the global scope. a legacy PTX definitions such as . tex_c. The .tex . tex_d.PTX ISA Version 2. Texture State Space (deprecated) The texture (. and programs should instead reference texture memory through variables of type . and .8.tex directive will bind the named texture memory variable to a hardware texture identifier. See Section 5. A texture’s base address is assumed to be aligned to a 16-byte boundary.u32 tex_a.texref.1.tex .0 5.global . 2010 . Multiple names may be bound to the same physical texture identifier.texref type and Section 8.u32 .texref variables in the .u32 or .u32 . The .texref tex_a. The texture name must be of type . tex_f. and variables declared in the .7. Another is sequential access from sequential threads.tex .tex directive is retained for backward compatibility.tex state space are equivalent to module-scoped . 5.global state space. Shared State Space The shared (.7. tex_d.u32 . Example: .6 for its use in texture instructions. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128). An address in shared memory can be read and written by any thread in a CTA.3 for the description of the .shared and st. Use ld. An error is generated if the maximum number of physical resources is exceeded.u64.u32 tex_a. For example. One example is broadcast. Texture memory is read-only. where texture identifiers are allocated sequentially beginning with zero. Shared memory typically has some optimizations to support the sharing.tex .shared to access shared variables.tex . It is shared by all threads in a context.1.tex) state space is global memory accessed via the texture instruction.shared) state space is a per-CTA region of memory for threads in a CTA to share data. is equivalent to . where all threads read from the same address. // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated.

pred Most instructions have one or more type specifiers.Chapter 5.s16.b8.b64 . .2. . so their names are intentionally short. All floating-point instructions operate only on .u8. Operand types and sizes are checked against instruction types for compatibility.f32 and . A fundamental type specifies both a basic type and a size. The . For example. Signed and unsigned integer types are compatible if they have the same size.f64 .b32. so that narrow values may be loaded.2. .s8. Two fundamental types are compatible if they have the same basic type and are the same size. . The same typesize specifiers are used for both variable definitions and for typing instructions.s8. and Variables 5. needed to fully specify instruction behavior.u32. and converted using regular-width registers.1.u8.2. Register variables are always of a fundamental type. and instructions operate on these types. . ld. and cvt instructions. Types.b16. Fundamental Types In PTX. stored. 5. st. State Spaces.u64 .f32 and . Restricted Use of Sub-Word Sizes The . The bitsize type is compatible with any fundamental type having the same size. but typed variables enhance program readability and allow for better operand type checking.2. . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. . all variables (aside from predicates) could be declared using only bit-size types. Types 5. or converted to other types and sizes.f16. In principle. 2010 33 . . . Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . the fundamental types reflect the native data types supported by the target architectures. For convenience. and . stored. st. The following table lists the fundamental type specifiers for each basic type: Table 8.f16 floating-point type is allowed only in conversions to and from .u16. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.s64 .f64 types.s32. . . January 24.f32.b8 instruction types are restricted to ld.f64 types. .

and query instructions. or performing pointer arithmetic will result in undefined results. and surface descriptor variables. Referencing textures.samplerref variables. and .texref type that describe sampler properties are ignored. Texture. Retrieving the value of a named member via query instructions (txq. In the unified mode. opaque_var. samplers. These types have named fields similar to structures.0 5. PTX has two modes of operation. the resulting pointer may be stored to and loaded from memory. . but all information about layout. and de-referenced by texture and surface load. or surfaces via texture and surface load/store instructions (tex. and overall size is hidden to a PTX program.samplerref. accessing the pointer with ld and st instructions. store. In the independent mode. but the pointer cannot otherwise be treated as an address. These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. The following tables list the named members of each type for unified and independent texture modes. hence the term “opaque”.texref handle. Creating pointers to opaque variables using mov.u64} reg. sampler. For working with textures and samplers. passed as a parameter to functions. texture and sampler information each have their own handle.texref. sured). 2010 .PTX ISA Version 2.e. base address. field ordering. The three built-in types are . suld. allowing them to be defined separately and combined at the site of usage in the program. Sampler. suq). and Surface Types PTX includes built-in “opaque” types for defining texture. since these properties are defined by . sust. i. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists.. 34 January 24.surfref.{u32. texture and sampler information is accessed through a single .3. In independent mode the fields of the . Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.

clamp_ogl. clamp_to_edge. and Variables Table 9. Member width height depth Opaque Type Fields in Unified Texture Mode .Chapter 5.texref values in elements in elements in elements 0.samplerref values N/A N/A N/A N/A nearest. mirror. Types. 2010 35 .texref values . linear wrap. clamp_to_edge.surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. Member width height depth Opaque Type Fields in Independent Texture Mode . clamp_ogl. linear wrap. clamp_to_border 0. State Spaces. clamp_to_border N/A N/A N/A N/A N/A . 1 ignored ignored ignored ignored . 1 nearest.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. mirror.

texref my_texture_name.global .global .param state space.samplerref my_sampler_name. these variables must be in the .surfref my_surface_name. Example: . .global .global .texref tex1. the types may be initialized using a list of static expressions assigning values to the named members. 36 January 24. . . 2010 .global . When declared at module scope. Example: . these variables are declared in the .PTX ISA Version 2.samplerref tsamp1 = { addr_mode_0 = clamp_to_border. At module scope.global state space. filter_mode = nearest }. As kernel parameters.0 Variables using these types may be declared at module scope or within kernel entry parameter lists.

reg .f32 accel. State Spaces.u16 uv.2.v2 or . // a length-4 vector of floats .4.v4.global . .v3 }.Chapter 5.reg . vector variables are aligned to a multiple of their overall size (vector length times base-type size).v4 . 0. . 0. an optional initializer. 0}.v4 . and Variables 5. Examples: .4.v4.pred p.v1. its name.v4 vector.0. // a length-4 vector of bytes By default. PTX supports types for simple aggregate objects such as vectors and arrays.v2 . for example.4.u32 loc. etc. Vectors cannot exceed 128-bits in length. // typedef . . to enable vector load and store instructions which require addresses aligned to a multiple of the access size. Types. This is a common case for three-dimensional grids. . 2010 37 . // a length-2 vector of unsigned ints .1.const . Examples: .v4 .f32 V. an optional array size.b8 v. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . A variable declaration names the space in which the variable resides. its type and size. January 24. Variable Declarations All storage for data is specified with variable declarations.global . Predicate variables may only be declared in the register state space. Vectors must be based on a fundamental type. Three-element vectors may be handled by using a .v2. textures. 5. 5.u8 bg[4] = {0. Every variable must reside in one of the state spaces enumerated in the previous section.f32 bias[] = {-1.f64 is not allowed. a variable declaration describes both the variable’s type and its state space.struct float4 coord. In addition to fundamental types. .0}. Vectors Limited-length vector types are supported. 1. .s32 i.global .global .reg . . r. where the fourth element provides padding. and they may reside in the register space.struct float4 { .shared . Variables In PTX.f32 v0.global . and an optional fixed address for the variable. q.

. {1. 1} }. 0}.shared . label names appearing in initializers represent the address of the next instruction following the label.u8 rgba[3] = {{1. 2010 .0.local .1}.0}.3. {0. {0.0}}. where the variable name is followed by an equals sign and the initial value or values for the variable.u32 or .0 5.global . 38 January 24. Variables that hold addresses of variables or instructions should be of type .1. . Examples: .0}.u8 mailbox[128].05}.05. 19*19 (361) halfwords are reserved (722 bytes).0. .f32 blur_kernel[][] = {{. A scalar takes a single value.global .global .. The size of the dimension is either a constant expression. being determined by an array initializer. . variable initialization is supported only for constant and global state spaces.s32 offset[][] = { {-1.4.4..0.b32 ptr = rgba. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration). -1}. Here are some examples: .. 0}. this can be used to statically initialize a pointer to a variable.. To declare an array. {0.u16 kernel[19][19].4.u64.f16 and . {0.1. Similarly. For the kernel declaration above. .{. 5. The size of the array specifies how many elements should be reserved. this can be used to initialize a jump table to be used with indirect branches or calls. // address of rgba into ptr Currently.1.global .05}}.s32 n = 10..4.v4 . or is left empty. Initializers Declared variables may specify an initial value using a syntax similar to C/C++.05. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.1. Array Declarations Array declarations are provided to allow the programmer to reserve space.1.0. Variable names appearing in initializers represent the address of the variable.global .pred. .PTX ISA Version 2. Initializers are allowed for all types except .{.

2.. Parameterized Variable Names Since PTX supports virtual registers. Rather than require explicit declaration of every name. alignment specifies the address alignment for the starting address of the entire array. For example.0. it is quite common for a compiler frontend to generate a large number of register names. not for individual elements.0.b32 %r<100>. January 24. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes.b8 bar[8] = {0.align 4 . .4. The default alignment for scalar and array variables is to a multiple of the base-type size. Examples: // allocate array at 4-byte aligned address. suppose a program uses a large number. of . 5. Array variables cannot be declared this way.6. Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. 2010 39 . nor are initializers permitted.0. named %r0. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. For arrays.4. and Variables 5. .Chapter 5. // declare %r0.b32 variables. %r1.align byte-count specifier immediately following the state-space specifier.. These 100 register variables can be declared as follows: . Types. Elements are bytes.5.const . …. Alignment is specified using an optional .reg . say one hundred. and may be preceded by an alignment specifier.0}. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. %r99. %r1. The default alignment for vector variables is to a multiple of the overall vector size. The variable will be aligned to an address which is an integer multiple of byte-count. State Spaces.0..0.

2010 .PTX ISA Version 2.0 40 January 24.

Predicate operands are denoted by the names p. and c. The cvt (convert) instruction takes a variety of operand types and sizes. mov. s. The result operand is a scalar or vector variable in the register state space. There is no automatic conversion between types. as its job is to convert from nearly any data type to any other data type (and size). Integer types of a common size are compatible with each other.2. r. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. Most instructions have an optional predicate guard that controls conditional execution. 6.reg register state space.3. 6. q. Each operand type must be compatible with the type determined by the instruction template and instruction type. Source Operands The source operands are denoted in the instruction descriptions by the names a. st. 2010 41 . January 24. . so operands for ALU instructions must all be in variables declared in the .Chapter 6. Instructions ld and st move data from/to addressable state spaces to/from registers. PTX describes a load-store machine. b.1. and a few instructions have additional predicate source operands. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. The ld. Operand Type Information All operands in instructions have a known type from their declarations. Instruction Operands 6. The bit-size type is compatible with every type having the same size. For most operations. The mov instruction copies data between registers. the sizes of the operands must be consistent. and cvt instructions copy data from one location to another.

v4 . address registers.u32 42 January 24.reg . The syntax is similar to that used in many assembly languages.b32 p. ld. . and Vectors Using scalar variables as operands is straightforward. 6. W. The address is an offset in the state space in which the variable is declared.global .s32 tbl[256].u16 x.reg . . p.f32 ld. .gloal. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions.reg .0 6. Arrays. Address expressions include variable names.u16 r0. . [tbl+12]. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.reg .1. and vectors. 2010 . r0. Using Addresses. [V]. q. The interesting capabilities begin with addresses. and immediate address expressions which evaluate at compile-time to a constant address.f32 V. address register plus byte offset.s32 mov. there is no support for C-style pointer arithmetic.f32 W.v4.const .PTX ISA Version 2. .4. All addresses and address computations are byte-based.v4 .u16 ld. Load and store operations move data between registers and locations in addressable state spaces. tbl. Examples include pointer arithmetic and pointer comparisons.s32 q. Here are a few examples: .shared . arrays. The mov instruction can be used to move the address of a variable into a pointer.shared. .[x].4.const.

reg . If more complicated indexing is desired. January 24. The registers in the load/store operations can be a vector.4.c.v4. a[1]. V2.d}.w = = = = V. a[N-1]. and the identifier becomes an address constant in the space where the array is declared. Rc.z and . ld. a[0]. and tex.global. . and in move instructions to get the address of the label or function into a register. Vector elements can be extracted from the vector with the suffixes .u32 s. or a braceenclosed list of similarly typed scalars. Vector loads and stores can be used to implement wide loads and stores. The expression within square brackets is either a constant integer.4. st.f32 V. where the offset is a constant expression that is either added or subtracted from a register variable. or by indexing into the array using square-bracket notation. Arrays as Operands Arrays of all types can be declared.reg .4. a register variable.4.f32 ld. Array elements can be accessed using an explicitly calculated byte address.a 6. Vectors may also be passed as arguments to called functions.u32 s. . V. The size of the array is a constant in the program.u32 {a.x V. which include mov. b.global. mov.a.w.d}. Rd}. [addr+offset].r V.v4 . // move address of a[1] into s 6. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions.global.v2. Elements in a brace-enclosed vector.z V.x.b.r. Here are examples: ld.g V. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V.f32 a. . as well as the typical color fields .c. which may improve memory performance. mov.u32 s. Vectors as Operands Vector operands are supported by a limited subset of instructions. ld. for use in an indirect branch or call.global.v4. or a simple “register with constant offset” expression. . say {Ra. 2010 43 . . d. [addr+offset2].3. it must be written as an address calculation prior to use.2.b and . c.Chapter 6.y. Instruction Operands 6.g. Rb. .f32 {a.b.y V.b V. A brace-enclosed list is used for pattern matching to pull apart vectors. Examples are ld.

Type Conversion All operands to all arithmetic. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.0 6. For example. the u16 is zero-extended to s32. 44 January 24. and ~131.1. logic. and data movement instruction must be of the same type and size. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types.5. except for operations where changing the size and/or type is part of the definition of the instruction.000 for f16).5. 2010 .u16 instruction is given a u16 source operand and s32 as a destination operand. 6.s32.PTX ISA Version 2. Operands of different sizes or types must be converted prior to the operation. if a cvt.

For example. chop = keep only low bits that fit. cvt.Chapter 6. 2010 45 .u32 targeting a 32-bit register will first chop to 16-bits. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. s2f = signed-to-float. zext = zero-extend. Instruction Operands Table 11. Notes 1 If the destination register is wider than the destination format. January 24.s16. f2f = float-to-float. f2u = float-to-unsigned. then sign-extend to 32-bits. The type of extension (sign or zero) is based on the destination format. f2s = float-to-signed. u2f = unsigned-to-float. the result is extended to the destination register width after chopping.

choosing even integer if source is equidistant between two integers.rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rz . round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.rzi . In PTX. Modifier .rn .rm . The following tables summarize the rounding modifiers.PTX ISA Version 2.rpi Integer Rounding Modifiers Description round to nearest integer. Modifier .0 6.rni .rmi . there are four integer rounding modifiers and four floating-point rounding modifiers. Rounding Modifiers Conversion instructions may specify a rounding modifier.5. Table 12. 2010 .2.

The register in a store operation is available much more quickly. Much of the delay to memory can be hidden in a number of ways. while global memory is slowest. Another way to hide latency is to issue the load instructions as early as possible. The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. Table 11 gives estimates of the costs of using different kinds of memory. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low.6. first access is high Notes January 24. Instruction Operands 6. Table 14. Registers are fastest. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. Operand Costs Operands from different state spaces affect the speed of an operation.Chapter 6. 2010 47 .

0 48 January 24. 2010 .PTX ISA Version 2.

1. Abstracting the ABI Rather than expose details of a particular calling convention. function calls. the function name. arguments may be register variables or constants. functions are declared and defined using the .Chapter 7. 7. Scalar and vector base-type input and return parameters may be represented simply as register variables. or prototype.func foo { … ret. … Here. A function must be declared or defined prior to being called. and return values may be placed directly into register variables. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. Execution of the ret instruction within foo transfers control to the instruction following the call. } … call foo. NOTE: The current version of PTX does not implement the underlying. so recursion is not yet supported. together these specify the function’s interface. execution of the call instruction transfers control to foo. A function definition specifies both the interface and the body of the function. implicitly saving the return address. The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. stack layout. In this section.func directive. The simplest function has no parameters or return values. 2010 49 . support for variadic functions (“varargs”). and memory allocated on the stack (“alloca”). and an optional list of input parameters. and Application Binary Interface (ABI). Function declarations and definitions In PTX. These include syntax for function definitions. and is represented in PTX as follows: . January 24. At the call. A function declaration specifies an optional list of return parameters. we describe the features of PTX needed to achieve this hiding of the ABI. stack-based ABI. parameter passing.

st.f64 f1.reg . // scalar args in .b64 [py+ 0].reg space. consider the following C structure.f1.param space memory. the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the . 2010 . [y+10].param.c4. ld.align 8 py[12].b8 [py+ 9]. inc_ptr.u32 %ptr.reg . passed by value to a function: struct { double dbl.param.reg .PTX ISA Version 2. byte array in . In PTX. %rc1. First. bumpptr. 50 January 24. [y+8].reg .b8 [py+ 8].param space variables are used in two ways.u32 %res) inc_ptr ( . For example. %ptr.s32 out) bar (. … In this example.u32 %inc ) { add.param.s32 x. c2.param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. [y+9]. }.b8 . Second. ret.0 Example: . %rc2. ld.b32 c1.c1.reg . The . … … // computation using x. … ld. a . } { . [y+0].func (. . note that .b8 c4. … st.b8 [py+10].param. [y+11]. ld.func (. st.reg . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . %rc1.b8 c2.param.param state space is used to pass the structure by value: .f64 f1.4).u32 %res. char c[4]. %rd. (%r1. .c3.param. this structure will be flattened into a byte array.align 8 y[12]) { .b8 c3.b8 . py).param.param. ld.param space call (%out). %rc2.reg . } … call (%r1).b8 [py+11]. a . c3. Since memory accesses are required to be aligned to a multiple of the access size.param. . st.param .c2.f64 field are aligned. %inc.param . c4. (%x.param variable y is used in function definition bar to represent a formal parameter.param.b8 c1. st.

reg space formal parameters. For .reg variables. In the case of .param memory must be aligned to a multiple of 1.param variables. size. or 16 bytes. Note that the choice of .reg or .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack. For a caller. or constants. 8. • The . Typically.reg state space can be used to receive and return base-type scalar and vector values. Abstracting the ABI The following is a conceptual way to think about the .param state space is used to receive parameter values and/or pass return values back to the caller. 2. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee..param space byte array with matching type.reg space variable with matching type and size. In the case of . the argument must also be a . The following restrictions apply to parameter passing. and alignment. 4. the corresponding argument may be either a . For a caller.param space formal parameters that are base-type scalar or vector variables. • • • Input and return parameters may be . This enables backend optimization and ensures that the . • • • For a callee.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.reg space variable of matching type and size. size. and alignment of parameters.param arguments. For a callee. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. The .param instructions used for argument passing must be contained in the basic block with the call instruction.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. The . • The .param state space use in device functions. the corresponding argument may be either a .Chapter 7. or a constant that can be represented in the type of the formal parameter.param or . • • Arguments may be .param space formal parameters that are byte arrays. all st. Parameters in .reg state space in this way provides legacy support. or a constant that can be represented in the type of the formal parameter.param and ld. a . January 24.param or . Supporting the . A . .reg variables.param byte array is used to collect together fields of a structure being passed by value.param variables or . 2010 51 . In the case of .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param argument must be declared within the local scope of the caller.g.

param state space. PTX 2. and .0 restricts functions to a single return value. and a . Objects such as C structures were flattened and passed or returned using multiple registers. In PTX ISA version 2.param byte array should be used to return objects that do not fit into a register.PTX ISA Version 2.reg state space. formal parameters were restricted to .0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays.1.reg or .0 7. formal parameters may be in either . 2010 . PTX 1. and there was no support for array parameters. For sm_2x targets. PTX 2.x In PTX ISA version 1. 52 January 24.x.x supports multiple return values for this purpose.1. Changes from PTX 1.0.

(2. . %r1. variadic functions are declared with an ellipsis at the end of the input parameter list. … ) .func (.u32. } … call (%max). 2.reg .h headers in C. call (val). .func baz ( .s32 result. call %va_end.reg .Chapter 7. The function prototypes are defined as follows: .reg . mov. PTX provides a high-level mechanism similar to the one provided by the stdarg. … call (%max). Abstracting the ABI 7.s32 result ) maxN ( .u32 N.u32 ap. the alignment may be 1. 4). 4. max. 0. along with the size and alignment of the next data value to be accessed. ) { . Once all arguments have been processed.reg .s32 val.reg . or 4 bytes.reg .func okay ( … ) Built-in functions are provided to initialize.reg .reg . val.u32 align) . (ap.u32 ptr.u32 a. ret.b32 ctr. (3.func (. 2010 53 .b32 val) %va_arg (. 0x8000000.u32 ptr.u32 ptr) %va_start . … %va_start returns Loop: @p Done: January 24. 8. following zero or more fixed parameters: . the size may be 1. 2. %r3).func %va_end (. ctr. result. (ap). %s1.b64 val) %va_arg64 (. 2.u32 sz. maxN. bra Done.reg . ctr. .reg . . bra Loop.b32 result. maxN..reg .. setp. %r2. .u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. the size may be 1.reg .2. Variadic functions NOTE: The current version of PTX does not support variadic functions. or 8 bytes. %va_arg. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .pred p. iteratively access. %va_end is called to free the variable argument list handle. 4. for %va_arg64. 4.func (.func ( . or 16 bytes. // default to MININT mov.ge p. For %va_arg.u32 align) .reg . N.reg . In both cases. .u32 sz. %va_start.u32 b. In PTX. . This handle is then passed to the %va_arg and %va_arg64 built-in functions. To support functions with a variable number of arguments.reg .reg . call (ap).reg .h and varargs. %s2). . and end access to a list of variable arguments.

2010 .local instructions.reg . defined as follows: .local and st. To allocate memory. Alloca NOTE: The current version of PTX does not support alloca.reg .func ( . PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.PTX ISA Version 2. it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. a function simply calls the built-in function %alloca. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer. If a particular alignment is required. The array is then accessed with ld.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory.0 7.u32 ptr ) %alloca ( .3. 54 January 24.

and C are the source operands. A.lt p|q. b. q = !(a < b). B. setp. the D operand is the destination operand. while A. opcode D.Chapter 8. A. // p = (a < b). For instructions that create a result value. In addition to the name and the format of the instruction.1. A. B. followed by some examples that attempt to show several possible instantiations of the instruction.2. the semantics are described.s32. January 24. opcode D. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. 8. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. a. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. The setp instruction writes two destination registers. PTX Instructions PTX instructions generally have from zero to four operands. Instruction Set 8. opcode A. C. 2010 55 . B. For some instructions the destination operand is optional. We use a ‘|’ symbol to separate multiple destination registers. opcode D.

s32 p. // p = (i < n) // if i < n.3. add. branch over 56 January 24. add. n.s32 j. predicate registers can be declared as .reg . where p is a predicate variable. the following PTX instruction sequence might be used: @!p L1: setp. add 1 to j To get a conditional branch or conditional function call. consider the high-level code if (i < n) j = j + 1.s32 j. To implement the above example as a true conditional branch. predicate registers are virtual and have . Predicates are most commonly set as the result of a comparison performed by the setp instruction. This can be written in PTX as @p setp.0 8. optionally negated.lt.pred p.s32 p. As an example. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. bra L1. use a predicate to control the execution of the branch or call instructions. j. 2010 . … // compare i to n // if false. 1.pred as the type specifier. Instructions without a guard predicate are executed unconditionally.PTX ISA Version 2. 1. q. n. i. Predicated Execution In PTX.lt. j. i. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. So.

If either operand is NaN. Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). and hs (higher-or-same). and ge (greater-than-or-equal). The unsigned comparisons are eq. gt (greater-than). unsigned integer. ne. lt (less-than). Table 15. ne. 2010 57 . ge. ne (not-equal).1.1. The bit-size comparisons are eq and ne. and bitsize types. ls (lower-or-same). the result is false. Comparisons 8. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer.Chapter 8.2.1. Instruction Set 8. Unsigned Integer. Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. le.3. gt. le (less-than-or-equal). ordering comparisons are not defined for bit-size types. lo (lower). Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8.1. Table 16. lt.3. hi (higher).3. The following table shows the operators for signed integer.

gtu. unordered versions are included: equ. then the result of these comparisons is true. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate. and mov. Table 18. num returns true if both operands are numeric values (not NaN). If either operand is NaN. neu. 2010 .3. and no direct way to load or store predicate register values. However. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. // convert predicate to 32-bit value 58 January 24.u32 %r1. ltu. Table 17.2. If both operands are numeric values (not NaN). not. or. and nan returns true if either operand is NaN. geu. for example: selp.PTX ISA Version 2. then these comparisons have the same result as their ordered counterparts. leu.0.0 To aid comparison operations in the presence of NaN values. setp can be used to generate a predicate from an integer.%p. There is no direct conversion between predicates and integer values. xor. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. two operators num (numeric) and nan (isNaN) are provided.1.

Signed and unsigned integer types agree provided they have the same size. and these are placed in the same order as the operands. Type Checking Rules Operand Type .sX ok ok ok inv . Instruction Set 8.fX ok inv inv ok Instruction Type .f32 d.u16 d. . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers.u16 a. The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size.u16 d. and integer operands are silently cast to the instruction type if needed.. a. Floating-point types agree only if they have the same size. unsigned. Example: . float. • The following table summarizes these type checking rules. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier. the add instruction requires type and size information to properly perform the addition operation (signed. an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction. cvt.bX .bX .uX . add. It requires separate type-size modifiers for the result and source.Chapter 8.sX . they must match exactly. 2010 59 .reg . a. a. b. Type Information for Instructions and Operands Typed instructions must have a type-size modifier.4.fX ok ok ok ok January 24.uX ok ok ok inv . and this information must be specified as a suffix to the opcode.f32.reg . different sizes). b. For example. Table 19. For example.u16 d.reg .e. i. For example: . most notably the data conversion instruction cvt.

“-“ = allowed. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type. the size must match exactly. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type.4. so those rows are invalid for cvt. Note that some combinations may still be invalid for a particular instruction. For example. When a source operand has a size that exceeds the instruction-type size. the cvt instruction does not support . When used with a floating-point instruction type. floating-point instruction types still require that the operand type-size matches exactly.0 8.bX instruction types. Bit-size source registers may be used with any appropriately-sized instruction type. or converted to other types and sizes. parse error. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit.1. 2. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. the data will be truncated. Operand Size Exceeding Instruction-Type Size For convenience. The data is truncated to the instruction-type size and interpreted according to the instruction type. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. st. no conversion needed. and converted using regular-width registers. 4. unless the operand is of bit-size type. Notes 3. ld. The following table summarizes the relaxed type-checking rules for source operands.PTX ISA Version 2. for example. 60 January 24. inv = invalid. Floating-point source registers can only be used with bit-size or floating-point instruction types. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. When used with a narrower bit-size type. stored. 1. stored. 2010 . the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. so that narrow values may be loaded. Table 20. Source register size must be of equal or greater size than the instruction-type size.

Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. the data is zeroextended. “-“ = Allowed but no conversion needed. the size must match exactly. the data is sign-extended. Notes 3. inv = Invalid. 4. 1. and is zero-extended to the destination register width otherwise. 2. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. Instruction Set When a destination operand has a size that exceeds the instruction-type size. zext = zero-extend. January 24. 2010 61 .or sign-extended to the size of the destination register. The following table summarizes the relaxed type-checking rules for destination operands. When used with a floatingpoint instruction type.Chapter 8. When used with a narrower bit-size instruction type. Bit-size destination registers may be used with any appropriately-sized instruction type. Table 21. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. The data is sign-extended to the destination register width for signed integer instruction types. the destination data is zero. Destination register size must be of equal or greater size than the instruction-type size. parse error. the data will be zero-extended. The data is signextended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer. otherwise. Floating-point destination registers can only be used with bit-size or floating-point instruction types.

one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. and 16-bit computations are “promoted” to 32-bit computations. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path. a compiler or code author targeting PTX can ignore the issue of divergent threads. the semantics of 16-bit instructions in PTX is machine-specific. conditional function call. The semantics are described using C. at least in appearance. Divergence of Threads in Control Constructs Threads in a CTA execute together. the optimizing code generator automatically determines points of re-convergence. or conditional return. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. and for many applications the difference in execution is preferable to limiting performance. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. this is not desirable. the threads are called uniform. until they come to a conditional control construct such as a conditional branch.PTX ISA Version 2. Therefore. by a right-shift instruction.0 8. However. If all of the threads act in unison and follow a single control flow path.1. A compiler or programmer may chose to enforce portable. using the . for many performance-critical applications. For divergent control flow. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. 8.6. 16-bit registers in PTX are mapped to 32-bit physical registers. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads.uni suffix. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. 62 January 24. the threads are called divergent. so it is important to have divergent threads re-converge as soon as possible. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. At the PTX language level. for example.5. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. When executing on a 32-bit data path. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path. Both situations occur often in programs. 8.6. 2010 . but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. These extra precision bits can become visible at the application level. If threads execute down different control flow paths. until C is not expressive enough.

subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.7. 2010 63 . the optional guard predicate is omitted from the syntax.cc. In the following descriptions.Chapter 8. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.7. 8. Instruction Set 8. Instructions All PTX instructions may be predicated.1. The Integer arithmetic instructions are: add sub add.cc. addc sub.

MAXINT (no overflow) for the size of the operation. // . PTX ISA Notes Target ISA Notes Examples Table 23.u32 x. Saturation modifier: .sat}. a. ..s32 c. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. 2010 . add Syntax Integer Arithmetic Instructions: add Add two values. Introduced in PTX ISA version 1. b.s64 }.y.b..sat limits result to MININT. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another.s32.sat applies only to .type = { .u32.s32 .u16.type sub{. PTX ISA Notes Target ISA Notes Examples 64 January 24.MAXINT (no overflow) for the size of the operation.type = { . Saturation modifier: .s32 c.s64 }. d.u16.type add{. .s32 d. Description Semantics Notes Performs addition and writes the resulting value into a destination register. . Introduced in PTX ISA version 1.1.0.u64. d = a – b. sub.s32 type. . b. .s16. // . . a. Applies only to . d = a + b.sat applies only to . . add.sat limits result to MININT.s32 type. d.s32 .s32.0 Table 22. Supported on all target architectures. Applies only to .sat.z.0.s32 d.s16. a. @p add. . sub.c. .u64.a.sat}.u32. . b. a. b. Supported on all target architectures. add.PTX ISA Version 2.

Behavior is the same for unsigned and signed integers.b32 addc. x4. No saturation. d = a + b.z2.2.type d.CF. carry-out written to CC.y3.type = { . No other instructions access the condition code.cc.u32.y1.cc.y1.y3. and there is no support for setting.y2.cc.type = {. addc{.z3.b32 addc.cc.cc. .u32. Supported on all target architectures. Introduced in PTX ISA version 1.z1. These instructions support extended-precision integer addition and subtraction.type d. Introduced in PTX ISA version 1. x3. x2.CF No integer rounding modifiers. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.z2. x4.b32 x1. . x2.z4. d = a + b + CC.CF) holding carry-in/carry-out or borrowin/borrow-out.cc. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24. add. carry-out written to CC.cc}.s32 }.b32 x1. add. b.b32 addc. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register.cc. x3. 2010 65 .cc Syntax Integer Arithmetic Instructions: add. a. .z3. or testing the condition code. Instruction Set Instructions add.b32 addc.cc.z4. @p @p @p @p add. a. Behavior is the same for unsigned and signed integers. sub.2.y4.b32 addc.cc.cc specified.b32 addc.CF No integer rounding modifiers. No saturation.cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC.Chapter 8.y4. clearing. Supported on all target architectures. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction.cc. b.y2. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25.s32 }.cc Add two values with carry-out. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. . @p @p @p @p add.z1. addc. Table 24. if .

cc Syntax Integer Arithmetic Instructions: sub.z4. . // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24. No saturation. Introduced in PTX ISA version 1. Supported on all target architectures. borrow-out written to CC.cc.PTX ISA Version 2. a.y4.cc Subract one value from another.cc. d = a – b. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another. if .b32 x1.cc}.b32 subc.cc. subc{.(b + CC. .z2.y2. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.b32 subc. @p @p @p @p sub.CF No integer rounding modifiers. d = a .b32 subc. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register.y4.z4. x3.cc.3.z3.z1.cc specified.cc.z1.cc. withborrow-in and optional borrow-out.y3. Supported on all target architectures.cc. x2. x4.y2. @p @p @p @p sub.s32 }.z2.CF No integer rounding modifiers. sub.b32 subc.3.type d.cc.b32 subc.y1.type d. with borrow-out. No saturation. x2. Behavior is the same for unsigned and signed integers.u32.y1.u32.z3. sub. borrow-out written to CC.type = {. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27. Behavior is the same for unsigned and signed integers. b. x3.0 Table 26.type = { . b. .y3. Introduced in PTX ISA version 1. x4.CF). 2010 .b32 subc. a.s32 }. .b32 x1.cc.

u32. and either the upper or lower half of the result is written to the destination register.lo. // 16*16 bits yields 32 bits // 16*16 bits. mul. . Instruction Set Table 28. then d is the same size as a and b. // for . mul{.s64 }.x.wide. d = t. creates 64 bit result January 24..fxs.u16.u64.wide suffix is supported only for 16. mul Syntax Integer Arithmetic Instructions: mul Multiply two values. .wide.wide // for . t = a * b.0>. save only the low 16 bits // 32*32 bits..type = { .wide is specified. then d is twice as wide as a and b to receive the full result of the multiplication.. a.hi or .s16 fa. mul.s32. mul. If .s32 z.0.fys.hi variant // for .wide}.y. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.lo variant Notes The type of the operation represents the types of the a and b operands. . The .type d. n = bitwidth of type. Supported on all target architectures. .lo is specified. b. . . d = t<2n-1.and 32-bit integer types.lo. 2010 67 .fxs.s16. d = t<n-1.fys.. If .hi.Chapter 8.s16 fa. Description Semantics Compute the product of two values.n>.

p.lo is specified.lo.type = { ..s32.MAXINT (no overflow) for the size of the operation. b. b. Saturation modifier: .s16.0> + c..s64 }.b.u16. c. 2010 . and either the upper or lower half of the result is written to the destination register. d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.s32 type in .q. then d and c are twice as wide as a and b to receive the result of the multiplication.type mad. c. a. t<2n-1. Supported on all target architectures.s32 r. bitwidth of type.wide is specified.r.lo variant Notes The type of the operation represents the types of the a and b operands. @p mad. .hi. and then writes the resulting value into a destination register. . a.and 32-bit integer types. t n d d d = = = = = a * b. . Description Semantics Multiplies two values and adds a third. 68 January 24.s32 d.wide suffix is supported only for 16. Applies only to .wide}. .a.sat limits result to MININT. .wide // for .hi variant // for .n> + c. mad{.sat.hi mode. mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value. then d and c are the same size as a and b. // for .lo..u32. t<n-1.hi..0.PTX ISA Version 2..c.lo.0 Table 29. mad.s32 d. t + c.hi or .u64. . The . If . If .

. All operands are of the same type and size.b. mul24.type = { . mul24.hi.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.type d.0>... mul24.s32 }. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mul24.u32.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.lo}.hi may be less efficient on machines without hardware support for 24-bit multiply. and return either the high or low 32-bits of the 48-bit result.lo.Chapter 8. 2010 69 . . mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.s32 d. Supported on all target architectures.a. 48bits. .hi variant // for . Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers.16>.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands.0. d = t<31. January 24. // for .e. Instruction Set Table 30. d = t<47. t = a * b. b. i. a. mul24{. // low 32-bits of 24x24-bit signed multiply.

u32. a. mad24.0> + c.hi may be less efficient on machines without hardware support for 24-bit multiply. 48bits.PTX ISA Version 2.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. 2010 .s32 }. mad24. . d = t<47. c. // low 32-bits of 24x24-bit signed multiply.type = { .hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.hi mode. mad24.s32 type in .s32 d. // for . Supported on all target architectures. a.hi.s32 d.. i.c. Return either the high or low 32-bits of the 48-bit result. mad24..lo}.hi variant // for . 32-bit value to either the high or low 32-bits of the 48-bit result.0. d.. b. . 70 January 24.a. d = t<31..16> + c. Applies only to . mad24{.e.sat limits result of 32-bit signed addition to MININT. b. Saturation modifier: . c. t = a * b. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.MAXINT (no overflow). and add a third.type mad24.0 Table 31.hi.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands. All operands are of the same type and size.b. Description Compute the product of two 24-bit integer values held in 32-bit source registers.sat.lo.

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. popc Syntax Integer Arithmetic Instructions: popc Population count.b32 popc. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.type = { .b64 }. .b64 }. // cnt is .b64 d. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d.b64 type.type = { .0. cnt. d = 0. .u32 PTX ISA Notes Target ISA Notes Examples Table 40. while (a != 0) { if (a&0x1) d++. the number of leading zeros is between 0 and 64. a = a << 1. mask = 0x8000000000000000. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. popc requires sm_20 or later. inclusively. clz.b32. popc. For .0. cnt.b32) { max = 32.b64 d. a. a.b32. X. clz. a = a >> 1. the number of leading zeros is between 0 and 32. clz requires sm_20 or later. 2010 . if (. } else { max = 64.u32 Semantics 74 January 24.PTX ISA Version 2. // cnt is . } while (d < max && (a&mask == 0) ) { d++.b32 clz. } Introduced in PTX ISA version 2.type == . . .type d.b32 type. mask = 0x80000000. a. d = 0. inclusively. a. popc.type d. For .0 Table 39. X.

d = -1.s32. break. i--) { if (a & (1<<i)) { d = i.type bfind.u32 d. Instruction Set Table 41. // cnt is . .u32. a. bfind returns 0xFFFFFFFF if no non-sign bit is found. and operand d has type .d.type==.u32 || . For unsigned integers.shiftamt is specified. a. i>=0. bfind. for (i=msb.s64 }. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind.type d. bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position. .s32) ? 31 : 63. For signed integers. Semantics msb = (. d. .shiftamt.s64 cnt. bfind requires sm_20 or later.u64. a. If . } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. bfind.u32.type==.0.shiftamt. Operand a has the instruction type. bfind returns the bit position of the most significant “1”. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit.type = { . . 2010 75 . Description Find the bit position of the most significant non-sign bit in a and place the result in d.shiftamt && d != -1) { d = msb . } } if (.u32 January 24. X.Chapter 8.

0. brev.b32.b32 d.b64 }. 2010 .type = { .PTX ISA Version 2. for (i=0.type d. msb = (. i++) { d[i] = a[msb-i]. Description Semantics Perform bitwise reversal of input. a. i<=msb.b32) ? 31 : 63. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.type==. brev requires sm_20 or later. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0 Table 42. brev. . 76 January 24. a. .

Operands a and d have the same type as the instruction type. pos = b.type d.type==. for (i=0.type = { . i<=msb. b. bfe. the result is zero.u32. if (. len = c. Description Extract bit field from a and place the zero or sign-extended result in d. Instruction Set Table 43.u64: . bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.type==. else sbit = a[min(pos+len-1.s32.a.0.start. If the start position is beyond the msb of the input. 2010 77 .u32 || . . . . bfe requires sm_20 or later.u32.type==.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.len. January 24.type==.b32 d. . Semantics msb = (. the destination d is filled with the replicated sign bit of the extracted field.msb)].u64 || len==0) sbit = 0.s32. Source b gives the bit field starting bit position. The sign bit of the extracted field is defined as: . a.u64. d = 0.Chapter 8. bfe. c. The destination d is padded with the sign bit of the extracted field.u32 || . .u32.s64 }. . and source c gives the bit field length in bits. otherwise If the bit field length is zero. and operands b and c are type .s32) ? 31 : 63.

and operands c and d are type . pos = c. the result is b. bfi. f = b. bfi requires sm_20 or later. 2010 .u32. If the bit field length is zero. . for (i=0.0.type f. Description Align and insert a bit field from a into b.type = { .PTX ISA Version 2. a. Operands a. b.b32) ? 31 : 63. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert.start. b.b64 }. Semantics msb = (. If the start position is beyond the msb of the input. len = d. the result is b. bfi. d. i<len && pos+i<=msb.a. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. and source d gives the bit field length in bits. 78 January 24. .0 Table 44. Source c gives the starting bit position for the insertion.b.len.type==. c. and f have the same type as the instruction type.b32 d. and place the result in f. i++) { f[pos+i] = a[i].

or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value). The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position.Chapter 8.rc8. as a 16b permute code. . c.rc16 }. the four 4-bit values fully specify an arbitrary byte permute. For each byte in the target register. a} = {{b7. b0}}. b1.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. default mode index d. and reassemble them into a 32-bit destination register. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. .b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. b2. .b4e. msb=0 means copy the literal value.b2 source select c[11:8] d.mode} d. b6. . b4}.mode = { . a.b1 source select c[7:4] d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. The bytes in the two source registers are numbered from 0 to 7: {b. .b3 source select c[15:12] d.ecr.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. prmt. {b3. In the generic form (no mode specified). msb=1 means replicate the sign. the permute control consists of four 4-bit selection values. The msb defines if the byte value should be copied.ecl. 2010 79 . b5.b32{. b. Description Pick four arbitrary bytes from two 32-bit registers.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. Thus. Note that the sign extension is only performed as part of generic form.f4e. . a 4-bit selection value is defined. Instruction Set Table 45.

tmp[15:08] = ReadByte( mode. r1. tmp64 ). ctl[1].f4e r1. r4. tmp64 ). tmp64 ). r3. tmp[23:16] = ReadByte( mode. tmp[31:24] = ReadByte( mode. prmt requires sm_20 or later. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. r4. tmp64 ). prmt. ctl[3]. 80 January 24.0. ctl[0]. ctl[3] = (c >> 12) & 0xf.PTX ISA Version 2. 2010 . ctl[2] = (c >> 8) & 0xf. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. ctl[1] = (c >> 4) & 0xf. } tmp[07:00] = ReadByte( mode. r2. r2.b32. r3.0 Semantics tmp64 = (b<<32) | a.b32 prmt. ctl[2]. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3.

f32 and .Chapter 8. Instruction Set 8.f64 register operands and constant immediate values. 2010 81 .2.7. Floating-Point Instructions Floating-point instructions operate on . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.

f64 div. The optional .f32 are the same.f32 {mad.cos.sat Notes If no rounding modifier is specified.rnd. default is .fma}.rcp.0 The following table summarizes floating-point instructions in PTX. mul.f32 {div.rnd.f32 {add.target sm_20 .rp . 82 January 24.rnd.rnd.target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant.32 and fma.approx.0.min.f64 are the same.f64 and fma. so PTX programs should not rely on the specific single-precision NaNs being generated.rcp.f64 {abs.rm .full. {mad.PTX ISA Version 2.rn . sub.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.fma}. 1. default is . with NaNs being flushed to positive zero.mul}.approx.target sm_1x No rounding modifier.neg.sqrt}. and mad support saturation of results to the range [0. {add.max}.ftz .0]. NaN payloads are supported for double-precision instructions.max}.approx. Table 46.sqrt}.mul}. Single-precision add.rn and instructions may be folded into a multiply-add. Note that future implementations may support NaN payloads for single-precision instructions. No rounding modifier. If no rounding modifier is specified.f32 .f32 rsqrt. Instruction Summary of Floating-Point Instructions .f64 rsqrt.f64 {sin.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.f32 {div.approx.sqrt}.min.f32 {abs.rnd.sub.rnd.neg. but single-precision instructions return an unspecified NaN.f64 mad.ex2}. Double-precision instructions support subnormal inputs and results. 2010 . Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets.rn and instructions may be folded into a multiply-add. . .lg2.target sm_20 mad.rcp.rz .f32 {div.sub.

pred = { .op. // result is . testp. testp. testp Syntax Floating-Point Instructions: testp Test floating-point property. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False.number testp.notanumber.f64 isnan. .0.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. f0. and return the result as d. A.f64 x. b.f32 testp. .f64 }. Table 48.f32 copysign. January 24.number.f64 }. X.f32.notanumber. copysign requires sm_20 or later.Chapter 8.infinite. 2010 83 .infinite. z. C.op p.infinite testp. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b.notanumber testp. copysign. true if the input is a subnormal number (not NaN. copysign. . testp.f32.finite testp.type d. not infinity). .type . a. .subnormal }. . B. Instruction Set Table 47. . y. testp requires sm_20 or later.type = { . Introduced in PTX ISA version 2.normal.normal testp. positive and negative zero are considered normal numbers. a. p.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN. copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another. .finite.0. not infinity) As a special case. .

0.rz. requires sm_20 Examples @p add.rn.f32 f1.rn): . b.sat. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 supports subnormal numbers. a. Saturation modifier: .f32 add{. add. In particular. a.0f. add Syntax Floating-Point Instructions: add Add two values. add{. add. .ftz}{.rm.rnd = { .rn mantissa LSB rounds to nearest even .rn.rm. .rnd}{. 2010 .f32. . 84 January 24. requires sm_13 for add.sat}.rnd}. sm_1x: add. Description Semantics Notes Performs addition and writes the resulting value into a destination register. .f32 supported on all target architectures.PTX ISA Version 2. Rounding modifiers have the following target requirements: . d = a + b.0. add. d. add.0 Table 49. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. b. . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.f32 flushes subnormal inputs and results to sign-preserving zero.rz. 1.f3.f64 requires sm_13 or later. Rounding modifiers (default is .rp for add. add.rz available for all targets .rp }.ftz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. NaN results are flushed to +0.f32 clamps the result to [0.rm mantissa LSB rounds towards negative infinity .f64.rz mantissa LSB rounds towards zero . .f32 flushes subnormal inputs and results to sign-preserving zero.ftz. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.0].f2. subnormal numbers are supported.f64 d.

ftz. .rp for sub.f32 clamps the result to [0.rnd}{. sub. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. .f64 requires sm_13 or later. b.a. .sat}. .rm.f32.b. d. sub{. subnormal numbers are supported. a.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.f3.0f.f64 d.rn): .0.f2. sub.f64. In particular.sat. 2010 85 .f32 supported on all target architectures.rz mantissa LSB rounds towards zero .f32 sub{. sub.f32 f1.Chapter 8. Rounding modifiers have the following target requirements: .rnd = { .rz available for all targets . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. sub.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Instruction Set Table 50.rn.0].rn. 1. requires sm_20 Examples sub.rz.rp }. . . d = a .0. Rounding modifiers (default is . NaN results are flushed to +0.f32 c. Description Semantics Notes Performs subtraction and writes the resulting value into a destination register.rn.rm mantissa LSB rounds towards negative infinity . January 24. a.rnd}. b.rn mantissa LSB rounds to nearest even .ftz}{. sm_1x: sub.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sub. requires sm_13 for sub. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Saturation modifier: sub. sub Syntax Floating-Point Instructions: sub Subtract one value from another. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer.rm.b.

PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.ftz}{. d = a * b.f32 mul{. In particular.f32 circumf.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. mul. b.rm. all operands must be the same size. b. requires sm_13 for mul. mul Syntax Floating-Point Instructions: mul Multiply two values. For floating-point multiplication.sat}.pi // a single-precision multiply 86 January 24. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rz available for all targets .f32.0.rn mantissa LSB rounds to nearest even . Saturation modifier: mul. NaN results are flushed to +0. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. a. Rounding modifiers have the following target requirements: .radius. 1. mul.f64 supports subnormal numbers.ftz. .rn. mul{.0.PTX ISA Version 2. requires sm_20 Examples mul.0]. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. subnormal numbers are supported.0f.rm mantissa LSB rounds towards negative infinity .rn. . Description Semantics Notes Compute the product of two values. a.rn): .f64. mul.rnd}. . .f32 supported on all target architectures.rz.rnd = { .rnd}{.rz mantissa LSB rounds towards zero .f32 clamps the result to [0. d.f64 d. .sat.rm.f64 requires sm_13 or later. 2010 .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 flushes subnormal inputs and results to sign-preserving zero. mul. Rounding modifiers (default is .rp for mul.rp }. sm_1x: mul. .0 Table 51.

f64 introduced in PTX ISA version 1.f64 computes the product of a and b to infinite precision and then adds c to this product. a. fma. 2010 87 .f64.a.y. .0.rnd.f32 requires sm_20 or later.f64 is the same as mad. again in infinite precision. b. fma. d = a*b + c. sm_1x: fma. b.rn.f64 w. c.z.rn mantissa LSB rounds to nearest even .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. 1.rz mantissa LSB rounds towards zero . fma.f32 introduced in PTX ISA version 2.rn. fma. @p fma. NaN results are flushed to +0.rnd.rz. .rm.Chapter 8. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. c.ftz}{. a. . fma.f32 is unimplemented in sm_1x. Rounding modifiers (no default): .rnd.f64 d.ftz. subnormal numbers are supported.sat}. Instruction Set Table 52. fma.sat.x.4.0].f32 fma. again in infinite precision.b. PTX ISA Notes Target ISA Notes Examples January 24.f64 supports subnormal numbers.rnd = { .f64 requires sm_13 or later. fma.0f. Saturation: fma.ftz. . d. fma. fma Syntax Floating-Point Instructions: fma Fused multiply-add. fma.c. The resulting value is then rounded to single precision using the rounding mode specified by .f32 computes the product of a and b to infinite precision and then adds c to this product.0.f32 flushes subnormal inputs and results to sign-preserving zero.rnd{.f32 fma.rn.f32 clamps the result to [0. fma. The resulting value is then rounded to double precision using the rounding mode specified by .rm mantissa LSB rounds towards negative infinity . d.rp }.

rn. d = a*b + c. mad.sat}. again in infinite precision. // .f32 is implemented as a fused multiply-add (i. and then the mantissa is truncated to 23 bits.rz mantissa LSB rounds towards zero .f64. .ftz.f32 clamps the result to [0.0]. The exception for mad. .0.f64 d. For .sat}. The resulting value is then rounded to single precision using the rounding mode specified by . mad.target sm_1x: mad.rnd. 1.0 devices.f32. the treatment of subnormal inputs and output follows IEEE 754 standard.rm. b.rnd. subnormal numbers are supported.f32 is when c = +/-0.0 Table 53.sat.rp }.target sm_20: mad.f64 computes the product of a and b to infinite precision and then adds c to this product. When JIT-compiled for SM 2.rz.e. a.rnd.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. For .f64} is the same as fma. 2010 . c. again in infinite precision.f64}. c.target sm_1x d. .target sm_13 and later . NaN results are flushed to +0.f32 mad. Note that this is different from computing the product with mul. // . a.rm mantissa LSB rounds towards negative infinity . a. 88 January 24. mad. b.{f32. The resulting value is then rounded to double precision using the rounding mode specified by . c. mad.f32 is identical to the result computed using separate mul and add instructions. sm_1x: mad.rn.PTX ISA Version 2. where the mantissa can be rounded and the exponent will be clamped.ftz. mad. mad. mad{.f64 supports subnormal numbers. mad.f32 computes the product of a and b at double precision..rnd.0. but the exponent is preserved.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.0f.f32 computes the product of a and b to infinite precision and then adds c to this product. Rounding modifiers (no default): .rnd{. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value. The resulting value is then rounded to double precision using the rounding mode specified by .target sm_20 d.f64 is the same as fma.f64 computes the product of a and b to infinite precision and then adds c to this product. Unlike mad. In this case.ftz}{.rnd = { . mad.ftz}{. b.f32).f32 mad. // .{f32. and then writes the resulting value into a destination register.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case. Description Semantics Notes Multiplies two values and adds a third. fma.rn mantissa LSB rounds to nearest even . again in infinite precision. Saturation modifier: mad. mad.

f32 for sm_20 targets.f64.4 and later.f64.rm. a rounding modifier is required for mad. mad.b. In PTX ISA versions 2. In PTX ISA versions 1.rp for mad.rm.0 and later.rn..f64 instructions having no rounding modifier will map to mad.f32. 2010 89 ... January 24..f64 requires sm_13 or later.rz..rp for mad.f32 supported on all target architectures..c. Rounding modifiers have the following target requirements: .f32 d.rz. a rounding modifier is required for mad.Chapter 8. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1.rn. requires sm_20 Examples @p mad.rn.0.f64. Legacy mad. Target ISA Notes mad. requires sm_13 .a.

subnormal numbers are supported. For b in [2-126.0 Table 54.ftz. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .ftz}. Examples 90 January 24. a.rn.ftz}.rz mantissa LSB rounds towards zero . .rnd = { .f32 div.f32 and div. and div. For PTX ISA versions 1.ftz}.rnd.f64 diam. Target ISA Notes div.f64. zd.3. div. a.full. // // // // fast.f32 div. For PTX ISA version 1. one of .rm mantissa LSB rounds towards negative infinity .ftz.approx. div. div. .rz. d. approximate division by zero creates a value of infinity (with same sign as a). . The maximum ulp error is 2 across the full range of inputs. stores result in d.circum.14159.approx. .full. div.4. div.f32 supported on all target architectures. approximate single-precision divides: div.PTX ISA Version 2. b. div.full. y.f64 supports subnormal numbers.approx{.f64 defaults to div.rp }.f32 defaults to div.f64 d.f32.full. Fast.ftz.f64 requires sm_20 or later.approx. xd. 2010 . div Syntax Floating-Point Instructions: div Divide one value by another.f32 div.0 through 1. but is not fully IEEE 754 compliant and does not support rounding modifiers. b. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . .rm. and rounding introduced in PTX ISA version 1. a. full-range approximation that scales operands to achieve better accuracy.f32 requires sm_20 or later.rp}. d. or .f32 implements a relatively fast. .f32 div. Fast.rn mantissa LSB rounds to nearest even .rnd is required.rn. PTX ISA Notes div. z.approx.f64 introduced in PTX ISA version 1. div. 2126].full. x.3.4 and later. computed as d = a * (1/b).rn.rn. d.rnd{.f64 requires sm_13 or later. b.f32 implements a fast approximation to divide. Description Semantics Notes Divides a by b.f32 flushes subnormal inputs and results to sign-preserving zero. the maximum ulp error is 2. sm_1x: div.f32 div.ftz. d = a / b.ftz. Subnormal inputs and results are flushed to sign-preserving zero.rnd.{rz. a.f32 flushes subnormal inputs and results to sign-preserving zero. b.approx.approx.full{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.0. div. yd.rm. Explicit modifiers .f32 and div. div.

f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero. Table 56. January 24. sm_1x: abs. abs{. neg{.ftz.f32 abs. Subnormal numbers: sm_20: By default. neg. a.f64 d. abs. neg.f64 requires sm_13 or later.f0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.ftz}.f32 supported on all target architectures.Chapter 8.f64 requires sm_13 or later. a.ftz.f32 x.f64 supports subnormal numbers. subnormal numbers are supported. Take the absolute value of a and store the result in d. NaN inputs yield an unspecified NaN. abs. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value. sm_1x: neg. abs. d.ftz. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. abs.f0.f64 supports subnormal numbers.0. Instruction Set Table 55.f64 d.0.ftz}.f32 x.f32 neg. d = |a|. d = -a. subnormal numbers are supported. NaN inputs yield an unspecified NaN. Subnormal numbers: sm_20: By default. a. neg. a. abs. 2010 91 . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. d. neg. Negate the sign of a and store the result in d.f32 flushes subnormal inputs and results to sign-preserving zero.

d.f32 supported on all target architectures.f1.f32 flushes subnormal inputs and results to sign-preserving zero. min.f32 max.ftz. sm_1x: min.f32 max. max. subnormal numbers are supported. sm_1x: max. max. subnormal numbers are supported. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values. d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Table 58. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values. b.z. a. min{. d d d d = = = = NaN. max.f64 requires sm_13 or later.f64 d.0. a. a. a.f64 z.f32 flushes subnormal inputs and results to sign-preserving zero.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. b.f64 requires sm_13 or later. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. b.c. Store the minimum of a and b in d. a.ftz. d d d d = = = = NaN. min.b. b.f32 min.f64 supports subnormal numbers.c. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.x. (a < b) ? a : b. @p min.f2. max. 2010 .0. a.f64 supports subnormal numbers. b. max. min.ftz. min.PTX ISA Version 2.ftz}.f32 supported on all target architectures. Store the maximum of a and b in d.0 Table 57. a.f32 flushes subnormal inputs and results to sign-preserving zero. a.f64 f0.b. max{. 92 January 24.ftz}.f32 min. (a > b) ? a : b.f64 d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. b.

xi. Target ISA Notes rcp.ftz}. rcp.f32.rz.0.Chapter 8.f64 d. and rcp. General rounding modifiers were added in PTX ISA version 2. subnormal numbers are supported.f32 rcp.f64 ri. rcp.f32 supported on all target architectures.rn.rn. // fast.ftz.ftz were introduced in PTX ISA version 1.ftz}.approx. sm_1x: rcp.0 through 1.0 +0.x. PTX ISA Notes rcp.rnd is required.f32 rcp.0 +subnormal +Inf NaN Result -0. d = 1 / a. .approx and .approx. rcp. For PTX ISA version 1. rcp.rp}.rn. Input -Inf -subnormal -0.f32 flushes subnormal inputs and results to sign-preserving zero. xi.ftz.r.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. a.rnd. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value.rnd.f32 requires sm_20 or later.f64 supports subnormal numbers.f32 rcp.f32 and rcp. The maximum absolute error is 2-23.f64 requires sm_20 or later.0.rm mantissa LSB rounds towards negative infinity .f64.f32 implements a fast approximation to reciprocal. rcp. store result in d.approx or .0-2.x.approx{.rn.0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . rcp.rm.f32 flushes subnormal inputs and results to sign-preserving zero.rnd = { . approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .0.f64 and explicit modifiers . rcp.ftz. For PTX ISA versions 1. d. . . Instruction Set Table 59. d.f32 defaults to rcp. a.rn mantissa LSB rounds to nearest even .f64 defaults to rcp.f64 requires sm_13 or later.approx.rz mantissa LSB rounds towards zero .f32 rcp.rn.ftz. rcp. Description Semantics Notes Compute 1/a. rcp. one of .4.f64 introduced in PTX ISA version 1.0 over the range 1. Examples January 24.rnd{.{rz.approx.3.4 and later. 2010 93 . a.rn.0 -Inf -Inf +Inf +Inf +0. rcp.rm.rp }.

0 +0.rn.rm mantissa LSB rounds towards negative infinity . Target ISA Notes sqrt. r.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. Examples 94 January 24. store in d.rnd = { .rn.f32 sqrt.f32 is TBD.ftz.f32 sqrt. sqrt.rn. a. subnormal numbers are supported.approx.ftz. . 2010 .approx.0 Table 60. sqrt. General rounding modifiers were added in PTX ISA version 2. sqrt.rnd is required.f32 and sqrt.approx. Input -Inf -normal -subnormal -0.approx and .rz mantissa LSB rounds towards zero .rn.f64 introduced in PTX ISA version 1.f32 requires sm_20 or later.f64 and explicit modifiers .f32 sqrt. The maximum absolute error for sqrt.4 and later. one of .rn.rm. // IEEE 754 compliant rounding .approx or . For PTX ISA versions 1.approx{. sqrt. // fast.rnd. a.ftz were introduced in PTX ISA version 1.x. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.f64 d.ftz.0. sqrt. sm_1x: sqrt.f32 supported on all target architectures.ftz}.f32 sqrt.f64 r.f64 supports subnormal numbers.0 +0. For PTX ISA version 1.f32.{rz.PTX ISA Version 2.approx.x.x.4.rn. PTX ISA Notes sqrt.f32 implements a fast approximation to square root.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . and sqrt. sqrt.f64 requires sm_13 or later.f64 requires sm_20 or later.rnd{.rm. sqrt.approx.0. sqrt.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. sqrt. approximate square root d.0 +0.f32 flushes subnormal inputs and results to sign-preserving zero. sqrt.rnd. // IEEE 754 compliant rounding d. d = sqrt(a).3. .0 +subnormal +Inf NaN Result NaN NaN -0.0 through 1.rn mantissa LSB rounds to nearest even . a.f64.0 -0.rz.f64 defaults to sqrt.ftz}. r.f32 defaults to sqrt. .rp }.rp}. Description Semantics Notes Compute sqrt(a).

a. rsqrt.f32 defaults to rsqrt.f32 rsqrt.approx. ISR.approx implements an approximation to the reciprocal square root.approx.0 NaN The maximum absolute error for rsqrt. rsqrt.0.f32. subnormal numbers are supported.0 +0.f64 requires sm_13 or later.0-4. Instruction Set Table 61.4.approx. store the result in d. PTX ISA Notes rsqrt.ftz were introduced in PTX ISA version 1.ftz}.ftz.f32 and rsqrt. The maximum absolute error for rsqrt.approx modifier is required. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value. sm_1x: rsqrt. January 24. the .4 over the range 1.approx.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f64 defaults to rsqrt.f32 supported on all target architectures. x.approx.4 and later. For PTX ISA version 1.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0.f32 flushes subnormal inputs and results to sign-preserving zero.ftz. a. Note that rsqrt.approx. rsqrt.0.f64 isr. rsqrt.f64.Chapter 8.0 through 1.approx and .f64 were introduced in PTX ISA version 1. Input -Inf -normal -subnormal -0.f64 is TBD. and rsqrt. rsqrt. rsqrt. X. Compute 1/sqrt(a).f64 d.approx{. d = 1/sqrt(a).f32 rsqrt. For PTX ISA versions 1. 2010 95 . Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.f32 is 2-22. rsqrt.3. d.f64 is emulated in software and are relatively slow. Explicit modifiers . Target ISA Notes Examples rsqrt.

PTX ISA Version 2.0.0 +0. PTX ISA Notes sin.0 Table 62.0 +subnormal +Inf NaN Result NaN -0. the .approx{. sin. 2010 .approx modifier is required.approx. d = sin(a).ftz}.ftz.0 +0.4 and later. a. 96 January 24.9 in quadrant 00.ftz.0 -0. Input -Inf -subnormal -0. Target ISA Notes Examples Supported on all target architectures.4. Find the sine of the angle a (in radians). sm_1x: Subnormal inputs and results to sign-preserving zero.ftz introduced in PTX ISA version 1.f32 flushes subnormal inputs and results to sign-preserving zero.f32 introduced in PTX ISA version 1.0 through 1.f32 sa. sin. sin.f32 implements a fast approximation to sine.0 +0. sin. For PTX ISA versions 1.f32. For PTX ISA version 1.ftz.approx and .3.f32 d. sin.0 NaN NaN The maximum absolute error is 2-20. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value. Subnormal numbers: sm_20: By default.approx. Explicit modifiers . a.approx. subnormal numbers are supported.f32 defaults to sin.

sm_1x: Subnormal inputs and results to sign-preserving zero. subnormal numbers are supported.f32 defaults to cos. Explicit modifiers .f32 ca.Chapter 8. Find the cosine of the angle a (in radians).approx.0 +1. PTX ISA Notes cos.approx and .approx. cos.3.ftz}.0 +1.0. cos.ftz.approx{. a.9 in quadrant 00.0 NaN NaN The maximum absolute error is 2-20. Instruction Set Table 63. the .f32 implements a fast approximation to cosine.f32 d. Input -Inf -subnormal -0.f32 flushes subnormal inputs and results to sign-preserving zero. a.0 through 1.ftz introduced in PTX ISA version 1.4 and later. January 24. Target ISA Notes Examples Supported on all target architectures. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value. For PTX ISA version 1.4. cos.ftz.ftz. cos.f32.0 +0.0 +1. Subnormal numbers: sm_20: By default. d = cos(a). 2010 97 . cos.approx. For PTX ISA versions 1.f32 introduced in PTX ISA version 1.approx modifier is required.0 +subnormal +Inf NaN Result NaN +1.

a. 98 January 24.f32 flushes subnormal inputs and results to sign-preserving zero.ftz.4 and later. lg2.3.0 +0. Input -Inf -subnormal -0. lg2. For PTX ISA versions 1.f32 introduced in PTX ISA version 1.approx modifier is required. 2010 .f32 la.approx.ftz introduced in PTX ISA version 1.f32 implements a fast approximation to log2(a).approx.ftz. For PTX ISA version 1.0 through 1. sm_1x: Subnormal inputs and results to sign-preserving zero. The maximum absolute error is 2-22. d = log(a) / log(2).PTX ISA Version 2.approx{. a. PTX ISA Notes lg2.0 Table 64.f32.6 for mantissa.f32 Determine the log2 of a.0.0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Subnormal numbers: sm_20: By default.4.approx.ftz. Explicit modifiers . lg2. lg2.approx and . lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.ftz}. Target ISA Notes Examples Supported on all target architectures. subnormal numbers are supported. lg2.f32 defaults to lg2. the .

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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This result is written to the first destination operand. and (optionally) combine this result with a predicate value by applying a Boolean operator.B) is one of: and. A related value computed using the complement of the compare result is written to the second destination operand. hs equ. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. gtu.f64 source type requires sm_13 or later. c). then these comparisons have the same result as their ordered counterparts. If either operand is NaN. .eq. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. For unsigned values. hi.f64 supports subnormal numbers. 2010 .BoolOp{. Applies to all numeric types. setp. lt.ftz}. gt.u32. The comparison operator is a suffix on the instruction.b. or. nan The Boolean operator BoolOp(A.s64.s32. setp.CmpOp.a. loweror-same.pred variables.0 Table 67. b.ftz applies only to . b.dtype. higher. and higher-or-same may be used instead of lt.i. and nan returns true if either operand is NaN. setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator. p = BoolOp(t. . {!}c. ge.b32. ge.f64 }. ls.u32 p|q. The untyped.CmpOp{. ge. subnormal numbers are supported. ltu. . . geu.s32 setp.r. geu. ls. num. The signed and unsigned comparison operators are eq. If both operands are numeric values (not NaN). @q setp. lt.f32. unordered versions are included: equ. To aid comparison operations in the presence of NaN values. and can be one of: eq. setp. the result is false.ftz}. ne. a. then the result of these comparisons is true.u64. . q = BoolOp(!t. and hs for lower.dtype. leu.0.lt. . p[|q]. respectively. the comparison operators lo. bit-size comparisons are eq and ne. leu.b16.f32 flushes subnormal inputs to sign-preserving zero. Integer Notes Floating Point Notes The ordered comparisons are eq. gt.u16. 102 January 24. xor. le. ltu. sm_1x: setp. num returns true if both operands are numeric values (not NaN).f32 flushes subnormal inputs to sign-preserving zero. p[|q].s16.f32 comparisons. . le. neu.PTX ISA Version 2. Semantics t = (a CmpOp b) ? 1 : 0.dtype. Modifier . c). p. gt.b64.type . . a. hi. lt. ne. ne.ftz. .type = { .n.and. neu. gt. lo. setp with . If either operand is NaN.type setp. le. . ge. Subnormal numbers: sm_20: By default. The destinations p and q must be . le. gtu.

ftz}. and operand a is selected. slct.b64.b64. negative zero equals zero. Instruction Set Table 68. .u16.s16.f64 requires sm_13 or later. d = (c >= 0) ? a : b.b32. a is stored in d. Description Conditional selection. .s64. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. and operand a is selected.xp.f32 A. B. a. and b are treated as a bitsize type of the same width as the first instruction type.t. . c.type d. .dtype. .b16.f32. . . a is stored in d. Operands d. d = (c == 1) ? a : b. a. the comparison is unordered and operand b is selected. .u32. f0.f64 requires sm_13 or later. z. C.ftz.dtype. b. val.g.b32. .u32. If c ≥ 0.0. based on the sign of the third operand. b. Introduced in PTX ISA version 1. .s32.ftz. .u16.f32 flushes subnormal values of operand c to sign-preserving zero. Modifier . The selected input is copied to the output without modification.r. For . b. slct. @q selp. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . .dtype.dtype. otherwise b is stored in d.f32 comparisons. fval.f32 d. Semantics Floating Point Notes January 24.x.b16. .f32 flushes subnormal values of operand c to sign-preserving zero. b otherwise. a. Operand c is a predicate.u64. If c is True. selp. slct. .s32.f64 }. . a.ftz applies only to . slct Syntax Comparison and Selection Instructions: slct Select one source operand. Table 69. and b must be of the same type.Chapter 8.s16.s32 x. If operand c is NaN.type = { . .f32 r0. subnormal numbers are supported. d.s64. sm_1x: slct.f32. based on the value of the predicate source operand. . c. .s32 slct{. 2010 103 .s32 selp.f32 comparisons. c. . y. a. Subnormal numbers: sm_20: By default. .u64. slct. selp.f64 }. Operands d.p. slct.u32. selp Syntax Comparison and Selection Instructions: selp Select between source operands.0.dtype = { . operand c must match the second instruction type. .u64.

and not also operate on predicates. or. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped.4. This permits bit-wise operations on floating point values without having to define a union to access the bits. 2010 . Instructions and.7. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. provided the operands are of the same size.PTX ISA Version 2. xor.0 8. performing bit-wise operations on operands of any type.

. b.fpvalue. . . . Allowed types include predicate registers. . or. or Syntax Logic and Shift Instructions: or Bitwise OR.pred p.0x80000000. Introduced in PTX ISA version 1.b32. and.r. The size of the operands must match. and Syntax Logic and Shift Instructions: and Bitwise AND.q. and.type = { . but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.b32 mask mask. Supported on all target architectures. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b.b64 }. Table 71. sign. Allowed types include predicate registers. January 24.type d. .0.b32 and.type d.pred.q. d = a & b.pred. Instruction Set Table 70. a. b.b16. The size of the operands must match. or. a. d = a | b.0x00010001 or. 2010 105 .b32. Introduced in PTX ISA version 1.0. .b64 }.type = { . Supported on all target architectures.r. . but not necessarily the type.b32 x.Chapter 8.b16.

The size of the operands must match. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.b32 mask.q. . xor. but not necessarily the type. Allowed types include predicates.b64 }. Introduced in PTX ISA version 1.b16. Allowed types include predicate registers. The size of the operands must match.type = { . . one’s complement.b16.x.type = { . d = ~a.q.PTX ISA Version 2.0x0001. . cnot. Introduced in PTX ISA version 1. d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.type d. xor. a. .b16.b32 xor. Supported on all target architectures. 106 January 24.type = { . . .a.b64 }. .b32. a. Introduced in PTX ISA version 1.0. The size of the operands must match. but not necessarily the type. not. not Syntax Logic and Shift Instructions: not Bitwise negation. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics.0.0.0 Table 72. Table 74. . .b32. Supported on all target architectures.b64 }.r. 2010 .b32 d. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. Table 73. cnot. .b16 d.mask.b32.pred. not. a.type d. . d = (a==0) ? 1 : 0. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality).pred.pred p. d = a ^ b. not. but not necessarily the type. Supported on all target architectures.type d. b.

Instruction Set Table 75. Shift amounts greater than the register width N are clamped to N. Shift amounts greater than the register width N are clamped to N.b16. . a. .j. shr. .type = { . . PTX ISA Notes Target ISA Notes Examples January 24. regardless of the instruction type. a. shl. Bit-size types are included for symmetry with SHL.b32 q. . unsigned and untyped shifts fill with 0.2.s32 shr. 2010 107 . . . k. d = a << b.b16 c. zero-fill on right. shl Syntax Logic and Shift Instructions: shl Shift bits left.u64. Introduced in PTX ISA version 1.2.b16. but not necessarily the type.i. shr Syntax Logic and Shift Instructions: shr Shift bits right. The b operand must be a 32-bit value.s64 }. The b operand must be a 32-bit value.a. . Signed shifts fill with the sign bit.u16 shr.s16.u32.b64 }.i.0. PTX ISA Notes Target ISA Notes Examples Table 76. . shr. Introduced in PTX ISA version 1. . The sizes of the destination and first source operand must match.0.type = { .s32.b32. .a. sign or zero fill on left.b32. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b.type d. but not necessarily the type.u16. i. Supported on all target architectures.1. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. b. shl. .type d. regardless of the instruction type. d = a >> b.Chapter 8. b. The sizes of the destination and first source operand must match.b64. Supported on all target architectures.

possibly converting it from one format to another. and from state space to state space. and sust support optional cache operations. Data Movement and Conversion Instructions These instructions copy data from place to place. mov. prefetchu isspacep cvta cvt 108 January 24. ldu.0 8.PTX ISA Version 2. suld. or shared state spaces. Instructions ld. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. The Data Movement and Conversion Instructions are: mov ld ldu st prefetch.7. ld. and st operate on both scalar and vector types. 2010 .5. st. local. The cvta instruction converts addresses between generic and global.

ca.lu operation. When ld.cs Cache streaming. The compiler / programmer may use ld. when applied to a local address. If one thread stores to global memory via one L1 cache.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels. . which allocates cache lines in all levels (L1 and L2) with normal eviction policy.cs is applied to a Local window address.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again.ca loads cached in L1.Chapter 8. the second thread may get stale L1 cache data.0 introduces optional cache operators on load and store instructions. evict-first. and a second thread loads that address via a second L1 cache with ld. to allow the thread program to poll a SysMem location written by the CPU. .cs.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load.7. Instruction Set 8. January 24. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. Use ld. For sm_20 and later. and cache only in the L2 cache.1.lu instruction performs a load cached streaming operation (ld. if the line is fully covered. rather than the data stored by the first thread.ca. it performs the ld. Operator . not L1). likely to be accessed once. bypassing the L1 cache. The ld.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. The ld. Cache Operators PTX 2. the cache operators have the following definitions and behavior.cv Cache as volatile (consider cached system memory lines stale. A ld. The ld. Global data is coherent at the L2 level.lu load last use operation. fetch again). As a result of this request. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. . Table 77.cg to cache loads only globally. likely to be accessed again. The default load instruction cache operation is ld.cs) on global addresses. 2010 109 .lu Last use.5.cv to a frame buffer DRAM address is the same as ld.cg Cache at global level (cache in L2 and below. The ld. any existing cache lines that match the requested address in L1 will be evicted. but multiple L1 caches are not coherent for global data. invalidates (discards) the local L1 line following the load. . The cache operators require a target architecture of sm_20 or later.

and discard any L1 lines that match.wb could write-back global store data from L1.wb for global data. The default store instruction cache operation is st. Use st. Data stored to local per-thread memory is cached in L1 and L2 with with write-back. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. The st.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data.wt. . rather than get the data from L2 or memory stored by the first thread.cg to local memory uses the L1 cache.wt Cache write-through (to system memory). However.PTX ISA Version 2. In sm_20.ca.wt store write-through operation applied to a global System Memory address writes through the L2 cache.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.cs Cache streaming. .ca loads.cg Cache at global level (cache in L2 and below. Addresses not in System Memory use normal write-back. . Future GPUs may have globally-coherent L1 caches. and cache only in the L2 cache. likely to be accessed once. bypassing the L1 cache. in which case st.cg to cache global store data only globally.cg is the same as st. to allow a CPU program to poll a SysMem location written by the GPU with st.wb. but st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. bypassing its L1 cache. If one thread stores to global memory. 110 January 24. not L1). The st. which writes back cache lines of coherent cache levels with normal eviction policy. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld. regardless of the cache operation.0 Table 78. Operator . 2010 . and a second thread in a different SM later loads from that address via a different L1 cache with ld. the second thread may get a hit on stale L1 cache data. st. and marks local L1 lines evict-first. Global stores bypass L1.

Take the non-generic address of a variable in global. d = &avar.u32 mov.type d. immediate.const. special register. mov. Note that if the address of a device function parameter is moved to a register.type = { .local.type mov. variable in an addressable memory space. label. .. mov.e. d.u16 mov.. mov.v.type mov. A[5]. d.u32 d.f32. . Semantics d = a.0.b32. local.s32. alternately. a. label. or shared state space may be taken directly using the cvta instruction.u64. and . we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. Introduced in PTX ISA version 1. .e. .0. For variables declared in . k. d = &label. mov places the non-generic address of the variable (i.f32 mov. .pred. or shared state space.s64. . the generic address of a variable declared in global.f64 requires sm_13 or later. local. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction. ptr.u32.global. 2010 111 . ptr. within the variable’s declared state space Notes Although only predicate and bit-size types are required. sreg. .a. addr. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value.b16.u16. . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.f64 }.s16.Chapter 8.u32 mov. i.shared state spaces. The generic address of a variable in global. d. avar. Instruction Set Table 79.type mov. . or function name. . u. . myFunc. // get address of variable // get address of label or function . the address of the variable in its state space) into the destination register. the parameter will be copied onto the stack and the address will be in the local state space. Description . d = sreg. Operand a may be a register.f32 mov. // address is non-generic. . local. Write register d with the value of a.b64.1. A.

hi}..a have type .. mov. d. %x.{x.b32 %r1.x.b64 mov. For bit-size types.x.15].15]. 2010 .0.0 Table 80.z << 32) | (a.type d.b64 112 January 24. d.b16.63] } // unpack 16-bit elements from . %r1.15] } // unpack 8-bit elements from .b32.z.y.23]..y << 8) d = a..x.y.%r1.b have type .y.y << 8) | (a.b32 mov.hi are .. lo. Semantics d = a. Supported on all target architectures.b}.b64 { d.. a.x | (a.type = { . // // // // a. Description Write scalar register d with the packed value of vector register a.z. a[24.b.y } = { a[0.z.b. .z.y << 32) // pack two 8-bit elements into .u8 // unpack 32-bit elements from ..x.z << 16) | (a.w have type .y } = { a[0. a[32.b64 // pack two 32-bit elements into . .b32 // pack two 16-bit elements into . d.31] } // unpack 16-bit elements from .w}.x | (a. {r..b32 // pack four 16-bit elements into .u32 x.u16 %x is a double. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).{a.w } = { a[0.a}.31].x. Both the overall size of the vector and the size of the scalar must match the size of the instruction type.w } = { a[0. d.x | (a. a[8.31] } // unpack 8-bit elements from .x | (a.g..y << 16) d = a.x | (a.7].b32 mov. a[32.b32 { d. mov. a[16..b64 { d.31].15].PTX ISA Version 2. a[48. a[16.b16 { d. {lo.b8 r. d. d. a[16.y << 16) | (a.w << 24) d = a.. .y.g.b32 { d.63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.y } = { a[0. d.w << 48) d = a. d. or write vector register d with the unpacked values from scalar register a.7]..b64 }. a[8.47].. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. d.b16 // pack four 8-bit elements into ..

0. the resulting behavior is undefined. The address must be naturally aligned to a multiple of the access size.f32 or . . Semantics d d d d = = = = a. d.ss = { . The value loaded is sign-extended to the destination register width for signed integers. [a]. . .cop = { .u8. . .ss}.s32.type ld{.type d. ld.volatile. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld.vec. The address size may be either 32-bit or 64-bit. for example. *(a+immOff).Chapter 8. an address maps to the corresponding location in local or shared memory.f16 data may be loaded using ld. ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. . This may be used.e. *a.cs.v4 }.b32. Cache operations are not permitted with ld. .shared }. d.b64.s8. d. PTX ISA Notes January 24.cop}. . . ld introduced in PTX ISA version 1. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b8.f32.global and .type = { . . Instruction Set Table 81. i.ss}{. Generic addressing and cache operations introduced in PTX ISA 2. .u32.u16. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the .reg state space. [a].volatile. .b16.b16.f64 using cvt.e.volatile may be used with . In generic addressing. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.cop}. A destination register wider than the specified type may be used. If an address is not properly aligned.u64. the access may proceed by silently masking off low-order address bits to achieve proper rounding. an address maps to global memory unless it falls within the local memory window or the shared memory window.. 2010 113 . and then converted to .s16. ld{. 32-bit). . . and truncated if the register width exceeds the state space address width for the target architecture.type . . . .ss}. *(immAddr). If no state space is given.v2.volatile introduced in PTX ISA version 1.ss}{. i. .volatile{.type ld. . .vec. . The . [a]. [a]. Generic addressing may be used with ld. . Addresses are zero-extended to the specified width as needed.s64. . to enforce sequential consistency between threads accessing shared memory.cg.vec = { .lu.const space suffix may have an optional bank number to indicate constant banks other than bank zero.1. an integer or bit-size type register reg containing a byte address. . [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. .shared spaces to inhibit optimization of references to volatile memory. ld. Description Load register variable d from the location specified by the source address operand a in specified state space.volatile{. or the instruction may fault. perform the load using generic addressing. and is zeroextended to the destination register width for unsigned and bit-size types.0.cv }.f64 }. 32-bit).param.ca.global. .const.local. or [immAddr] an immediate absolute byte address (unsigned. Within these windows.

Generic addressing requires sm_20 or later. Q. // immediate address %r.[p+4].[p].b16 cvt. ld.[240]. // negative offset %r. %r. d. x.shared.global.PTX ISA Version 2.const[4].[buffer+64].[a].[fs].local.b32 ld. 2010 .f16 d.global.%r. // load .b64 ld.local.f32 ld.[p+-8]. Cache operations require sm_20 or later.b32 ld.b32 ld.f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24.f32.0 Target ISA Notes ld.v4.s32 ld.f64 requires sm_13 or later. // access incomplete array x.const.

global }. and truncated if the register width exceeds the state space address width for the target architecture. ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. and then converted to .vec = { . an address maps to global memory unless it falls within the local memory window or the shared memory window. .type ldu{. *a. 32-bit).f32 or .u16. ldu.type d. If an address is not properly aligned. and is zeroextended to the destination register width for unsigned and bit-size types. only generic addresses that map to global memory are legal.u32. ldu{.b8. . ldu.vec. Semantics d d d d = = = = a. A register containing an address may be declared as a bit-size type or integer type.s64. [a]. . [a]. The address size may be either 32-bit or 64-bit. [areg] a register reg containing a byte address.f64 }. The value loaded is sign-extended to the destination register width for signed integers.f32 d. or [immAddr] an immediate absolute byte address (unsigned. an address maps to the corresponding location in local or shared memory. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. .reg state space.b32 d.e.f64 requires sm_13 or later.global. .ss}. 2010 115 .b16. ..Chapter 8.s8.f16 data may be loaded using ldu. . A destination register wider than the specified type may be used.b32. In generic addressing. // state space . . the access may proceed by silently masking off low-order address bits to achieve proper rounding. Instruction Set Table 82. The data at the specified address must be read-only. where the address is guaranteed to be the same across all threads in the warp.0. PTX ISA Notes Target ISA Notes Examples January 24. // load from address // vec load from address .[a]. perform the load using generic addressing. Introduced in PTX ISA version 2. *(a+immOff).v4. If no state space is given.s16. . .v4 }. . // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.f32 Q.s32.global. the resulting behavior is undefined.type = { . ldu. .[p]. d.u64.e. For ldu.f64 using cvt. The address must be naturally aligned to a multiple of the access size. ldu.ss = { .ss}. Within these windows. *(immAddr). [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. . Addresses are zero-extended to the specified width as needed. 32-bit).v2. .f32.b64.[p+4]. .global. The addressable operand a is one of: [avar] the name of an addressable variable var. or the instruction may fault. .u8. i.b16. i.

b8.volatile introduced in PTX ISA version 1. . 32-bit).volatile{. b. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the .type .wt }. Generic addressing requires sm_20 or later. . or the instruction may fault.vec .f64 }. The address must be naturally aligned to a multiple of the access size. i. .e. If an address is not properly aligned. . A source register wider than the specified type may be used.s32. { .b16.vec.. *d = a.volatile.wb.type st{.PTX ISA Version 2. b.ss}{. b.ss}.1.cg.f32.ss}{.u16. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. Semantics d = a. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. b. Cache operations require sm_20 or later. .ss .b64. . *(immAddr) = a.e. 2010 .type [a]. Generic addressing may be used with st. [a]. The lower n bits corresponding to the instruction-type width are stored to memory. Description Store the value of register variable b in the location specified by the destination address operand a in specified state space.cs. Generic addressing and cache operations introduced in PTX ISA 2.b16. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. [a]. .f16 data resulting from a cvt instruction may be stored using st.volatile may be used with .shared spaces to inhibit optimization of references to volatile memory. [a].shared }. .u32. an integer or bit-size type register reg containing a byte address.vec. Cache operations are not permitted with st. If no state space is given. The address size may be either 32-bit or 64-bit.type = = = = {. st{. { . to enforce sequential consistency between threads accessing shared memory. and truncated if the register width exceeds the state space address width for the target architecture.volatile. . Addresses are zero-extended to the specified width as needed.v4 }. st introduced in PTX ISA version 1. i.u64. . . . In generic addressing. . . . .s8. { . .0. This may be used.ss}. perform the store using generic addressing. or [immAddr] an immediate absolute byte address (unsigned. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st. . . for example.f64 requires sm_13 or later.global and .global. Within these windows.b32. PTX ISA Notes Target ISA Notes 116 January 24.v2. the resulting behavior is undefined. .volatile{. an address maps to global memory unless it falls within the local memory window or the shared memory window. st.cop . *(d+immOffset) = a.local. an address maps to the corresponding location in local or shared memory.0 Table 83. st.reg state space.type st.u8. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed. the access may proceed by silently masking off low-order address bits to achieve proper rounding.0.s64.s16.cop}. 32-bit).cop}. st.

[fs].local.s32 st. // immediate address %r.f32 st.Q. // %r is 32-bit register // store lower 16 bits January 24.global.f16.b16 [a].%r.b32 st.local.a.b. // negative offset [100].global.r7. [q+4]. Instruction Set Examples st.s32 cvt.f32 st.v4.local. [p].a.b32 st.Chapter 8. [q+-8]. 2010 117 .%r.

L1 [addr]. prefetch and prefetchu require sm_20 or later. .L1. Within these windows. Addresses are zero-extended to the specified width as needed.L1 [ptr]. and no operation occurs if the address maps to a local or shared memory location. the prefetch uses generic addressing.global. prefetch{. A prefetch into the uniform cache requires a generic address. In generic addressing. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level.e.L1 [a]. prefetch. If no state space is given. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.0 Table 84.space = { . in specified state space. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. A prefetch to a shared memory location performs no operation.PTX ISA Version 2. 118 January 24.global. i. an address maps to the corresponding location in local or shared memory. // prefetch to data cache // prefetch to uniform cache . or [immAddr] an immediate absolute byte address (unsigned.space}. . . The address size may be either 32-bit or 64-bit. an address maps to global memory unless it falls within the local memory window or the shared memory window. [a]. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.L2 }. 32-bit).0. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.local }.level = { . a register reg containing a byte address. 32-bit). 2010 .level prefetchu. prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. and truncated if the register width exceeds the state space address width for the target architecture. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. prefetchu.

p.size p. var.0.u32 p.space. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.size cvta. isshrd.size . the generic address of the variable may be taken using cvta. or shared address to a generic address. cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global. islcl.u32 p.local. A program may use isspacep to guard against such incorrect behavior. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. local. local.u64. Take the generic address of a variable declared in global. .lptr. svar. . 2010 119 .u64 or cvt. a. isspacep. Introduced in PTX ISA version 2.space p. a. isspacep. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.genptr.u32. // local. PTX ISA Notes Target ISA Notes Examples Table 86.global. The source address operand must be a register of type . For variables declared in global. Use cvt.shared.size = { .space. cvta. or vice-versa.shared isglbl.local. or shared state space. a. cvta requires sm_20 or later.u32 gptr.0.u64 }. .u32 to truncate or zero-extend addresses. The destination register must be of type . sptr. .to. // result is .local isspacep.to. . // convert to generic address // get generic address of var // convert generic address to global. local. or shared address.global.u32 or . isspacep requires sm_20 or later. cvta. Description Convert a global. local. cvta. or shared address cvta.local.pred. . or shared state space to generic. gptr. January 24.space = { . When converting a generic address into a global.space. Instruction Set Table 85. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space. local. lptr.Chapter 8.shared }. or shared state space. or vice-versa. // get generic address of svar cvta.global isspacep. p. The source and destination addresses must be the same size.shared }.u32.u64.global.space = { .pred .

. Integer rounding is illegal in all other instances. . .rn.f32. a. subnormal inputs are flushed to signpreserving zero.s16. . Description Semantics Integer Notes Convert between different types and sizes.dtype. . .irnd = { .u32.frnd = { .irnd}{. Note that saturation applies to both signed and unsigned integer types.ftz}{.rni. .dtype = .atype d. .sat For integer destination types.ftz}{.frnd}{. a..f32 float-tofloat conversions with integer rounding. .u8. Saturation modifier: .4 and earlier. 2010 .sat modifier is illegal in cases where saturation is not possible based on the source and destination types. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. . The optional . . Note: In PTX ISA versions 1.. the result is clamped to the destination range by default.ftz.u64. . . subnormal inputs are flushed to signpreserving zero.rmi round to nearest integer in direction of negative infinity . // integer rounding // fp rounding .PTX ISA Version 2.e.u16. subnormal numbers are supported. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. choosing even integer if source is equidistant between two integers.rmi. .rp }.f32.MAXINT for the size of the operation.rpi }. the .ftz. The compiler will preserve this behavior for legacy PTX code. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits.sat}.sat is redundant.rzi round to nearest integer in the direction of zero .f32 float-to-integer conversions and cvt.dtype. sm_1x: For cvt.f32 float-to-integer conversions and cvt. For cvt. For float-to-integer conversions. .rzi.ftz modifier may be specified in these cases for clarity. i. and for same-size float-tofloat conversions where the value is rounded to an integer.s8.dtype.e.f32.rm. Integer rounding modifiers: .atype = { .f16.rni round to nearest integer.0 Table 87.s32. i. 120 January 24. . . d.f64 }.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default.atype cvt{.ftz.sat limits the result to MININT.sat}.s64. .ftz.dtype. .rz. . d = convert(a). .f32 float-tofloat conversions with integer rounding. cvt{. Integer rounding is required for float-to-integer conversions.

Note: In PTX ISA versions 1.0]. Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used.4 and earlier. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. Modifier . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt.i. cvt.f64.f64 requires sm_13 or later. Floating-point rounding modifiers: .ftz modifier may be specified in these cases for clarity.0.version is 1. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision.f32.f64 types.ftz behavior for sm_1x targets January 24. Applies to . The result is an integral value. // round to nearest int.f32.f16. stored in floating-point format.f16.f64 j. Saturation modifier: .f32 x. if the PTX . 2010 121 .s32 f. 1. and cvt.rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes). .f32.sat limits the result to the range [0. Floating-point rounding is illegal in all other instances.f32 x.Chapter 8.f32. The optional .s32. .f16. The compiler will preserve this behavior for legacy PTX code.rz mantissa LSB rounds towards zero .sat For floating-point destination types. cvt.rni. and .y.rm mantissa LSB rounds towards negative infinity .r. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was .f32.0. NaN results are flushed to positive zero. // float-to-int saturates by default cvt. Specifically.rn mantissa LSB rounds to nearest even .f32. // note . cvt. and for integer-to-float conversions. cvt to or from . Subnormal numbers: sm_20: By default. The operands must be of the same size. subnormal numbers are supported.f32 instructions.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero.f32. Introduced in PTX ISA version 1. result is fp cvt.4 or earlier.y.

u32 r5. {f1.b32 r5. PTX supports the following operations on texture.f32 r3. add.. r2. If no texturing mode is declared.target options ‘texmode_unified’ and ‘texmode_independent’. r5. add.2d. sampler. Texturing modes For working with textures and samplers.0 8. and surface descriptors.f32 r1. and surfaces. . r1. and surface descriptors.width.. = nearest width height tsamp1. and surface descriptors. add. Ability to query fields within texture.6. but the number of samplers is greatly restricted to 16.global .b32 r6.f32. div.r2. } = clamp_to_border. r3. sampler. [tex1]. PTX has two modes of operation. r5. sampler. samplers.r3. mul. Module-scope and per-entry scope definitions of texture.texref tex1 ) { txq.samplerref tsamp1 = { addr_mode_0 filter_mode }.texref handle.entry compute_power ( . texture and sampler information each have their own handle. r5. // get tex1’s tex. r4. The advantage of independent mode is that textures and samplers can be mixed and matched. r6. // get tex1’s txq. sampler. allowing them to be defined separately and combined at the site of usage in the program. In the unified mode. 122 January 24. with the restriction that they correspond 1-to-1 with the 128 possible textures. Texture and Surface Instructions This section describes PTX instructions for accessing textures. The texturing mode is selected using .f32 r1.f32. Example: calculate an element’s power contribution as element’s power/total number of elements.f2}]. and surface descriptors: • • • Static initialization of texture.target texmode_independent .r4}.v4. r3. r1. 2010 .f32 {r1. [tex1]. A PTX module may declare only one texturing mode. The advantage of unified mode is that it allows 128 samplers. . r1. .height. cvt.f32 r1. the file is assumed to use unified mode.param . [tex1.u32 r5. texture and sampler information is accessed through a single . In the independent mode.7.PTX ISA Version 2.

If an address is not properly aligned.geom = { .3d. The instruction always returns a four-element vector of 32-bit values. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1. //Example of unified mode texturing tex. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form.r3. Operand c is a scalar or singleton tuple for 1d textures.geom. or the instruction may fault.5. .e. If no sampler is specified. with the extra elements being ignored.Chapter 8. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. Supported on all target architectures.2d.f32 {r1.u32.r2.r4}.r4}. where the fourth element is ignored. The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. Notes For compatibility with prior versions of PTX. .1d. PTX ISA Notes Target ISA Notes Examples January 24.f32 }. the resulting behavior is undefined. tex. .s32. [tex_a. [tex_a.v4. // explicit sampler ..dtype.s32.f4}]. b.v4.s32 {r1.f3. c]. tex txq suld sust sured suq Table 88. 2010 123 . the sampler behavior is a property of the named texture.dtype. A texture base address is assumed to be aligned to a 16-byte address. {f1.s32. d.btype tex. . .0.v4 coordinate vectors are allowed for any geometry.btype d.f32 }. Description Texture lookup using a texture coordinate vector. .1d. {f1}].btype = { . the square brackets are not required and . Unified mode texturing introduced in PTX ISA version 1.v4. . sampler_x. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. An optional texture sampler b may be specified.3d }. [a. [a. // Example of independent mode texturing tex. and is a four-element vector for 3d textures. the access may proceed by silently masking off low-order address bits to achieve proper rounding.geom.s32. is a two-element vector for 2d textures.dtype = { .r3. Instruction Set These instructions provide access to texture and surface memory. c]. i.f2.r2.v4.

normalized_coords .tquery. Operand a is a . addr_mode_1.normalized_coords }.width.width . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. 2010 . Supported on all target architectures. . Integer from enum { nearest. d.depth .b32 %r1.addr_mode_1 .squery = { . Description Query an attribute of a texture or sampler.tquery = { . clamp_to_edge. [tex_A]. Query: . [a]. .height.filter_mode.squery. txq.PTX ISA Version 2.texref or . [a]. // unified mode // independent mode 124 January 24. clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.addr_mode_0. txq.addr_mode_2 Returns: value in elements 1 (true) or 0 (false).b32 %r1. .b32 txq. clamp_ogl.5.depth. mirror. linear } Integer from enum { wrap. txq. and in independent mode sampler attributes are accessed via a separate samplerref argument. .filter_mode. [smpl_B]. addr_mode_2 }. sampler attributes are also accessed via a texref argument.height . // texture attributes // sampler attributes .0 Table 89.width. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 %r1. In unified mode.samplerref variable. txq. [tex_A]. .addr_mode_0.b32 d.addr_mode_0 .filter_mode .

v4.geom . B. 2010 125 . [a.u32.dtype. . is a two-element vector for 2d surfaces.b supported on all target architectures. {x. Target ISA Notes Examples January 24.clamp.p.s32. . .cop}.b.b32.ca. and A components of the surface format. If an address is not properly aligned. suld.b32. . additional clamp modifiers. .2d.b64.e.b8 .trap clamping modifier.u32. or the instruction may fault. . then .b . // for suld.3d }. suld.1d. .3d requires sm_20 or later.surfref variable.3d. // cache operation none.u32. suld.cop}. . suld.geom{.z. [surf_B.dtype . {f1.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. . Description Load from surface memory using a surface coordinate vector.dtype.s32. then . where the fourth element is ignored. size and type conversion is performed as needed to convert from the surface sample format to the destination type.cg. .w}]. // formatted . the resulting behavior is undefined. suld Syntax Texture and Surface Instructions: suld Load from surface memory.p is currently unimplemented. . If the destination type is . then . The lowest dimension coordinate represents a sample offset rather than a byte offset.zero }. Destination vector elements corresponding to components that do not appear in the surface format are not written.b32.vec.cs. G.f4}. .. // unformatted d.trap introduced in PTX ISA version 1. If the destination base type is . the surface sample elements are converted to .5. b]. suld.f32 }. sm_1x targets support only the . or .clamp suld. . b].p . and the size of the data transfer matches the size of destination operand d.cop . The .clamp . .f32.p requires sm_20 or later.b.b. . Cache operations require sm_20 or later.b16.s32.v2.b performs an unformatted load of binary data. Instruction Set Table 90.f32.dtype . . [surf_A.b64 }. Operand a is a . The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d.v4 }.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld. Coordinate elements are of type .p.trap {r1. suld.clamp . or FLOAT data. .Chapter 8. The lowest dimension coordinate represents a byte offset into the surface and is not scaled. suld. or .trap .u32 is returned. Operand b is a scalar or singleton tuple for 1d surfaces.p. i.r2}. and is a four-element vector for 3d surfaces.f3. SNORM.1d. . A surface base address is assumed to be aligned to a 16-byte address. if the surface format contains UINT data. suld.cv }.f32 based on the surface format as follows: If the surface format contains UNORM.trap suld. [a. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. and cache operations introduced in PTX ISA version 2.f2.s32 is returned. suld.geom{. if the surface format contains SINT data.clamp field specifies how to handle out-of-bounds addresses: .v2.trap.v4. {x}].f32 is returned.y. .vec .0. the access may proceed by silently masking off low-order address bits to achieve proper rounding.clamp = = = = = = { { { { { { d.s32. // for suld.

. {x}]. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. .v2. .2d. The source vector elements are interpreted left-to-right as R.clamp field specifies how to handle out-of-bounds addresses: .clamp. [a.b. Target ISA Notes Examples 126 January 24. sust.ctype.1d.b8 .trap. the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.v4 }. [surf_B.b64 }.s32. .b supported on all target architectures. if the surface format contains UINT data.{u32. . A surface base address is assumed to be aligned to a 16-byte address.p requires sm_20 or later. the resulting behavior is undefined. .f32 is assumed.b. . . If the source type is . is a two-element vector for 2d surfaces.s32.b32. . // for sust. Source elements that do not occur in the surface sample are ignored.clamp .3d.clamp sust.u32. sust. sust.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust.u32.r2}. i. none.p performs a formatted store of a vector of 32-bit data values to a surface sample. b].1d.geom . sust.y.p Description Store to surface memory using a surface coordinate vector.b16.3d requires sm_20 or later. sust.v4.trap introduced in PTX ISA version 1.f4}.b64.wt }. // unformatted // formatted . sust. If an address is not properly aligned.trap .z. or the instruction may fault.5.cg. b]. The source data is then converted from this type to the surface sample format.. . B.trap sust.cop}. Cache operations require sm_20 or later.f3.geom{.f32. Surface sample components that do not occur in the source vector will be written with an unpredictable value.cop}. G. additional clamp modifiers. .trap clamping modifier. Operand a is a . . . or FLOAT data. and A surface components. sust.s32. .s32 is assumed.trap [surf_A.surfref variable.w}].3d }.e.f32 }.clamp .vec. .b32. sm_1x targets support only the . .zero }. where the fourth element is ignored. or .cop . .f2.PTX ISA Version 2.geom{.vec . If the source base type is . and is a four-element vector for 3d surfaces.p. 2010 . size and type conversions are performed as needed between the surface sample format and the destination type.s32. if the surface format contains SINT data.f32} are currently unimplemented.p.f32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size.p.b. SNORM. sust. c. sust Syntax Texture and Surface Instructions: sust Store to surface memory.b performs an unformatted store of binary data. {x.clamp = = = = = = { { { { { { [a.ctype . c. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.v2. The lowest dimension coordinate represents a sample offset rather than a byte offset.p. The size of the data transfer matches the size of source operand c. then .ctype.cs. Coordinate elements are of type . then . then . sust.u32 is assumed. These elements are written to the corresponding surface sample components. .wb. {r1.ctype .0. and cache operations introduced in PTX ISA version 2.0 Table 91. Operand b is a scalar or singleton tuple for 1d surfaces.b32.b // for sust. the access may proceed by silently masking off low-order address bits to achieve proper rounding. {f1.vec. The . .

where the fourth element is ignored.e.and.s32 or . . .u32. sured.b. [surf_B.u64 data.op.add.clamp [a.. 2010 127 .b performs an unformatted reduction on . Operand a is a .u64.2d. Operations add applies to .p. .u32 and . and the data is interpreted as .b .p performs a reduction on sample-addressed 32-bit data.1d. or .clamp [a. .geom = { . A surface base address is assumed to be aligned to a 16-byte address. Operand b is a scalar or singleton tuple for 1d surfaces. and is a four-element vector for 3d surfaces. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b.c. sured.ctype. . operations and and or apply to . {x}]. The lowest dimension coordinate represents a sample offset rather than a byte offset.u32. r1.Chapter 8.add.b32. i.op. r1. // for sured.clamp field specifies how to handle out-of-bounds addresses: .max.c.trap . The lowest dimension coordinate represents a byte offset into the surface and is not scaled.s32.s32 is assumed.u32 is assumed.s32.y}]. .clamp .s32 types. {x.s32 types.b.b]. . .b32 }. .trap sured. .1d. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. If an address is not properly aligned.trap.u32. // byte addressing sured.clamp.3d }. Instruction Set Table 92. // for sured. and . the resulting behavior is undefined. if the surface format contains SINT data. sured. the access may proceed by silently masking off low-order address bits to achieve proper rounding. .geom. then .geom.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .zero }.or }.u32 based on the surface sample format as follows: if the surface format contains UINT data.trap [surf_A. then . sured. The instruction type is restricted to . Reduction to surface memory using a surface coordinate vector. The .ctype.ctype = { .b32 type. Coordinate elements are of type . min and max apply to . . is a two-element vector for 2d surfaces. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory. sured requires sm_20 or later.0.p.op = { .b32. . .ctype = { .b].min.s32.u32.b32 }.p .u64. // sample addressing .clamp = { .surfref variable.2d. January 24.b32.min. . or the instruction may fault.

height.0 Table 93. [surf_A].b32 d.query = { .width.width . suq. suq.surfref variable.width. 128 January 24. . . . Supported on all target architectures.PTX ISA Version 2.b32 %r1. Operand a is a .query.depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1. 2010 . Query: . suq Syntax Texture and Surface Instructions: suq Query a surface attribute.height . [a]. Description Query an attribute of a surface.5.depth }.

0. setp. Threads with a false guard predicate do nothing.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Instruction Set 8.f32 @q bra L23. Supported on all target architectures.s32 d. { add.a.s32 a. { instructionList } The curly braces create a group of instructions. p. 2010 129 .7. Execute an instruction or instruction block for threads that have the guard predicate true. @{!}p instruction. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.c.eq.y. used primarily for defining a function body. Supported on all target architectures. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope.f32 @!p div.b. ratio.0. } PTX ISA Notes Target ISA Notes Examples Table 95.Chapter 8. {} Syntax Description Control Flow Instructions: { } Instruction grouping.0.x.7. mov. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. Introduced in PTX ISA version 1. If {!}p then instruction Introduced in PTX ISA version 1.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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sync without a thread count introduced in PTX ISA 1.or indicate if all the threads had a true predicate or if any of the threads had a true predicate. bar.popc is the number of threads with a true predicate. bar.red instruction. and then safely read values stored by other threads prior to the barrier. b. Once the barrier count is reached.or).red. {!}c.version 2.red performs a predicate reduction across the threads participating in the barrier. execute a bar. it is as if all the threads in the warp have executed the bar instruction.u32 bar. all-threads-true (.and. Thus. Since barriers are executed on a per-warp basis.popc). In conditionally executed code. and any-thread-true (.sync and bar. bar. thread count.and and .red} introduced in PTX .and).red} require sm_20 or later. The result of . a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge). the bar.. b}. When a barrier completes. Operands a.sync and bar. while .sync 0. bar. All threads in the warp are stalled until the barrier completes. the final value is written to the destination register in all threads waiting at the barrier.sync or bar. a{.red. 2010 133 .popc. The barrier instructions signal the arrival of the executing threads at the named barrier.sync bar. and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp). it simply marks a thread's arrival at the barrier. the waiting threads are restarted without delay. Description Performs barrier synchronization and communication within a CTA. The reduction operations for bar. b}.cta. .15. Register operands. all threads in the CTA participate in the barrier. the optional thread count must be a multiple of the warp size. Operand b specifies the number of threads participating in the barrier. p.arrive does not cause any waiting by the executing threads. If no thread count is specified. a{. Barriers are executed on a per-warp basis as if all the threads in a warp are active. Execution in this case is unpredictable.red performs a reduction operation across threads. January 24. and the barrier is reinitialized so that it can be immediately reused. {!}c. b.red are population-count (. Note that a non-zero thread count is required for bar.pred .or }.arrive using the same active barrier. In addition to signaling its arrival at the barrier.red should not be intermixed with bar. Only bar. threads within a CTA that wish to communicate via memory can store to memory. d.sync with an immediate barrier number is supported for sm_1x targets.sync or bar. b}. Thus. Each CTA instance has sixteen barriers numbered 0. bar. a. if any thread in a warp executes a bar instruction.u32. bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15.0. thread count.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution.arrive a{. PTX ISA Notes Target ISA Notes Examples bar.{arrive.arrive. bar.Chapter 8. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads.op.red also guarantee memory ordering among threads identical to membar.op = { . and bar. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator.sync) until the barrier count is met. Register operands.0. and d have type . bar. Instruction Set Table 100. operands p and c are predicates. bar. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization.red delays the executing threads (similar to bar.{arrive. and bar.

membar.version 2. that is. membar.gl will typically have a longer latency than membar. membar.PTX ISA Version 2. A memory write (e. Waits until prior memory reads have been performed with respect to other threads in the CTA.cta Waits until all prior memory writes are visible to other threads in the same CTA. level describes the scope of other clients for which membar is an ordering event. . when the previous value can no longer be read.4.gl} supported on all target architectures.{cta.gl} introduced in PTX . membar.gl. membar. membar.level. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level. membar.cta. 2010 . or system memory level.cta.level = { . and memory reads by this thread can no longer be affected by other thread writes. this is the appropriate level of membar.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU.sys requires sm_20 or later.sys introduced in PTX .g. . membar.version 1.{cta.0 Table 101. global.sys Waits until all prior memory requests have been performed with respect to all clients. membar.cta. red or atom) has been performed when the value written has become visible to other clients at the specified level. membar.sys }. . membar. For communication between threads in different CTAs or even different SMs. including thoses communicating via PCI-E such as system and peer-to-peer memory. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.0. 134 January 24. A memory read (e.g. PTX ISA Notes Target ISA Notes Examples membar. membar.sys will typically have much longer latency than membar. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. by st.sys.gl.gl. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA.

and exch (exchange).b32. Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.space = { . It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions. b. . an address maps to the corresponding location in local or shared memory. . and truncated if the register width exceeds the state space address width for the target architecture.s32. . or.type d. . accesses to local memory are illegal.shared }. c. and max. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.u32.Chapter 8.xor. .cas. atom. . the resulting behavior is undefined.f32. an address maps to global memory unless it falls within the local memory window or the shared memory window. January 24.max }. The address must be naturally aligned to a multiple of the access size.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. . performs a reduction operation with operand b and the value in location a. .f32 }.b32 only . . dec. cas (compare-and-swap).add. The floating-point operations are add.u64 . . Addresses are zero-extended to the specified width as needed. min.u32. . b.b32.type atom{.and. .e. .u64. min. overwriting the original value.exch to store to locations accessed by other atomic operations.u32. xor. atom{. If an address is not properly aligned. . In generic addressing. . If no state space is given. .e.s32.f32 Atomically loads the original value at location a into destination register d. i.b]. d. The bit-size operations are and. and stores the result of the specified operation at location a.. . i.type = { . Within these windows. Instruction Set Table 102. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar. The floating-point add.op = { . e. .. perform the memory accesses using generic addressing. The inc and dec operations return a result in the range [0. 2010 135 .min. .space}. max.exch.add. Description // // // // // . min.s32.or. A register containing an address may be declared as a bit-size type or integer type.op. . .dec. . The integer operations are add. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. [a].b64 . or the instruction may fault. 32-bit operations.op.space}.global. Operand a specifies a location in the specified state space.b64.inc. or by using atom.u32 only . inc. The address size may be either 32-bit or 64-bit. or [immAddr] an immediate absolute byte address. by inserting barriers between normal stores and atomic operations to a common address. and max operations are single-precision. For atom. [a].g. . [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. . a de-referenced register areg containing a byte address. the access may proceed by silently masking off low-order address bits to achieve proper rounding.

my_val.t) = (r == s) ? t operation(*a.0. atom.exch} requires sm_12 or later.0 Semantics atomic { d = *a. atom. c) operation(*a.global.max} are unimplemented.cas.global requires sm_11 or later. Introduced in PTX ISA version 1.[p]. Use of generic addressing requires sm_20 or later.s32 atom. Release Notes Examples @p 136 January 24. 64-bit atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.s.shared. 64-bit atom. d.b32 d.f32 requires sm_20 or later. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’. cas(r. s) = (r >= s) ? 0 dec(r.cas.f32. b. : r.1.shared operations require sm_20 or later.add. atom. atom. s) = s. : r-1. d. atom.PTX ISA Version 2.0.[a].my_new_val. b). s) = (r > s) ? s exch(r.shared requires sm_12 or later.add.f32 atom. 2010 .{min.[x+4].max.{add.global. : r+1. *a = (operation == cas) ? : } where inc(r.

The floating-point operations are add. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. an address maps to global memory unless it falls within the local memory window or the shared memory window.b32. . overwriting the original value.f32 }. or.min. For red. s) = (r > s) ? s : r-1. dec(r. e. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. . . perform the memory accesses using generic addressing. and max operations are single-precision.b32 only .exch to store to locations accessed by other reduction operations. or [immAddr] an immediate absolute byte address. red{. . . an address maps to the corresponding location in local or shared memory. Operand a specifies a location in the specified state space.u64. min. Semantics *a = operation(*a.type = { . . b).. the resulting behavior is undefined.f32 Performs a reduction operation with operand b and the value in location a. . dec.or.g. The floating-point add.b].add.u32 only . i. a de-referenced register areg containing a byte address.u32. min. where inc(r.f32. January 24. .shared }.op = { .xor. Notes Operand a must reside in either the global or shared state space. The bit-size operations are and. . . max.and. If no state space is given. .u32.b64..s32. the access may proceed by silently masking off low-order address bits to achieve proper rounding. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. inc. The integer operations are add. Addresses are zero-extended to the specified width as needed. or the instruction may fault.space}.inc.op.u64 . i.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.e.e.global. 2010 137 . . If an address is not properly aligned. s) = (r >= s) ? 0 : r+1. . Instruction Set Table 103.dec. . and truncated if the register width exceeds the state space address width for the target architecture. . . . or by using atom. The address size may be either 32-bit or 64-bit. . accesses to local memory are illegal. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.s32.s32. . . and xor. and stores the result of the specified operation at location a. red. A register containing an address may be declared as a bit-size type or integer type. In generic addressing.space = { . Description // // // // . 32-bit operations. The inc and dec operations return a result in the range [0. min.u32. Within these windows.Chapter 8.add. The address must be naturally aligned to a multiple of the access size. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. . and max.max }.type [a]. b. by inserting barriers between normal stores and reduction operations to a common address.

f32. Use of generic addressing requires sm_20 or later.PTX ISA Version 2. [p].{min. 64-bit red. red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.f32 requires sm_20 or later.s32 red.shared requires sm_12 or later. red.2.global.max.and.my_val.add. red.shared operations require sm_20 or later.b32 [a]. 2010 . red.shared.global requires sm_11 or later red.0.max} are unimplemented.1.global.f32 red. [x+4]. 64-bit red. Release Notes Examples @p 138 January 24.add requires sm_12 or later.add.

uni.q. . returns bitmask .p. In the ‘ballot’ form. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group. {!}a. . 2010 139 . vote.ballot. vote.any True if source predicate is True for some active thread in warp. The reduction modes are: .ballot.any. . Description Performs a reduction of the source predicate across threads in a warp. Instruction Set Table 104. vote. vote. where the bit position corresponds to the thread’s lane id.q.uni }.ballot.all True if source predicate is True for all active threads in warp.all. Negate the source predicate to compute .b32 p. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1. Negating the source predicate also computes .uni True if source predicate has the same value in all active threads in warp.Chapter 8. vote requires sm_12 or later. Negate the source predicate to compute .uni. // ‘ballot’ form.pred d.ballot.b32 d.b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.all.2.mode. r1.none. .pred vote.mode = { .b32 requires sm_20 or later. // get ‘ballot’ across warp January 24. {!}a. p. The destination predicate value is the same across all threads in the warp. not across an entire CTA.not_all. Note that vote applies to threads in a single warp. vote.pred vote.

atype. a{.s34 intermediate result. to produce signed 33-bit input values. .min. . c.extended internally to .bsel}. . or word values from its source operands.secop = { . and btype are valid.0 8.asel}.9. extract and sign. half-word.btype{.sat}.bsel = { . .dtype.atype.btype{. b{. 3.sat} d.b1.bsel}. vop. Using the atype/btype and asel/bsel specifiers.dtype.b0.dtype. The source and destination operands are all 32-bit registers.u32 or .sat} d. .dsel. a{. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).7.bsel}.dsel = .s32) is specified in the instruction type. . c.or zero-extend byte.s32 }. a{. // 32-bit scalar operation. optionally clamp the result to the range of the destination type.secop d. The sign of the intermediate result depends on dtype. Video Instructions All video instructions operate on 32-bit register operands. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. the input values are extracted and signor zero. 4.atype = .asel}.h1 }.b2.atype.h0.asel}. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. with optional data merge vop.dtype = . 2010 . . The type of each operand (. taking into account the subword destination size in the case of optional data merging. .asel = . . 2.b3.btype{.PTX ISA Version 2. all combinations of dtype. . b{.btype = { .max }.add.s33 values. with optional secondary operation vop.u32. The general format of video instructions is as follows: // 32-bit scalar operation. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. . perform a scalar arithmetic operation to produce a signed 34-bit result. The primary operation is then performed to produce an . 140 January 24. b{.atype.

s33 tmp.h0: return ((tmp & 0xffff) case .max return MAX(tmp. U32_MIN ).h1: return ((tmp & 0xffff) << 16) case . switch ( dsel ) { case . as shown in the following pseudocode. .s33 tmp. . c). U32_MAX. . U16_MAX. U8_MIN ).s33 optSecOp(Modifier secop. c).s33 c) { switch ( secop ) { . 2010 141 . default: return tmp.s33 optMerge( Modifier dsel. The sign of the c operand is based on dtype. c). .b1: return ((tmp & 0xff) << 8) case .min: return MIN(tmp. tmp. tmp. Bool sign.b0: return ((tmp & 0xff) case . . c). The lower 32-bits are then written to the destination operand.b2.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge. . January 24. c).add: return tmp + c.s33 optSaturate( . .s34 tmp. S32_MIN ).b3: return ((tmp & 0xff) << 24) default: return tmp.Chapter 8. tmp. Instruction Set . U8_MAX. S8_MIN ). . U16_MIN ).s33 c ) switch ( dsel ) { case .b0. } } .b2: return ((tmp & 0xff) << 16) case . S32_MAX. } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c). c). c).b3: if ( sign ) return CLAMP( else return CLAMP( case . Modifier dsel ) { if ( !sat ) return tmp. . . tmp. Bool sat. S8_MAX.b1. . S16_MIN ). tmp.h0. S16_MAX.

s32. 2010 .bsel}. // optional secondary operation d = optMerge( dsel. tmp = | ta – tb |.h1. .s32. vmax require sm_20 or later.asel}. vop.u32. r3. r3.dtype.dtype. vmin.b1.sat}. tb = partSelectSignExtend( b. . .s32 }. btype. r2. // 32-bit scalar operation. vsub vabsdiff vmin. c.asel}. with optional data merge vop.sat vmin. c ).sat} d. tmp = MAX( ta.h0. // optional merge with c operand 142 January 24. a{. vabsdiff. tmp. r1.b0. .s32.s32. b{. r3. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. r3. vmax Syntax Integer byte/half-word/word addition / subtraction.sat vabsdiff.s32. { . vsub.add r1.b3. . sat.s32.asel}. r2.op2 d. tmp. Semantics // saturate. a{. Video Instructions: vadd. vabsdiff.s32.btype{. vsub.sat vsub. vsub. // extract byte/half-word/word and sign. vadd.asel = .dsel. r2. .s32. r1.b0.bsel}.min.vop .h1. vmin.0. atype. .bsel}. vmax vadd. c.PTX ISA Version 2. . dsel ). // 32-bit scalar operation. tb ). b{. r2. Integer byte/half-word/word minimum / maximum. b{.op2 Description = = = = { vadd.h1 }.or zero-extend based on source operand type ta = partSelectSignExtend( a. Perform scalar arithmetic operation with optional saturate. Integer byte/half-word/word absolute value of difference.0 Table 105.btype = { . vmin.u32.b2. tb ). .s32. tmp = ta – tb. taking into account destination type and merge operations tmp = optSaturate( tmp.h0. isSigned(dtype).max }.s32.sat. with optional secondary operation vop. vmax }.dtype. c.atype.atype = .u32. c ).btype{.add. tmp = MIN( ta.atype. a{.btype{. switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. asel ). r1. and optional secondary arithmetic operation or subword data merge.h0.dsel . c. . bsel ). . vabsdiff.bsel = { . vadd.b0. d = optSecondaryOp( op2.atype.b2.dtype .sat} d.

bsel}.u32{. if ( mode == . r2. Video Instructions: vshl. b{.h1. r2. tb = partSelectSignExtend( b.u32.or zero-extend based on source operand type ta = partSelectSignExtend( a.dtype. vshl.u32{. a{. vshl: Shift a left by unsigned amount in b with optional saturate. and optional secondary arithmetic operation or subword data merge. // 32-bit scalar operation.op2 d.wrap }.dtype.h0.asel}. b{. bsel ).dsel . atype. and optional secondary arithmetic operation or subword data merge. . c.dtype .atype = { .asel}.wrap ) tb = tb & 0x1f. . with optional secondary operation vop. vop. . .mode} d.mode}. with optional data merge vop.add. isSigned(dtype).0.min. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp.op2 Description = = = = = { vshl. January 24.dtype. d = optSecondaryOp( op2.u32 vshr. vshr: Shift a right by unsigned amount in b with optional saturate.bsel}.asel = .atype. Semantics // extract byte/half-word/word and sign. .clamp. // default is . unsigned shift fills with zero. tmp. .b0.atype. . . c ). taking into account destination type and merge operations tmp = optSaturate( tmp. vshr require sm_20 or later. . vshr Syntax Integer byte/half-word/word left / right shift. r3.mode} d.sat}{. Instruction Set Table 106. a{.u32. vshr vshl.dsel. { .bsel}. . // 32-bit scalar operation.vop .h1 }.mode . vshl. Signed shift fills with the sign bit.atype. c ).u32.sat}{. . dsel ).max }. if ( mode == .b1.bsel = { . a{.wrap r1.u32. // optional secondary operation d = optMerge( dsel. c. switch ( vop ) { case vshl: tmp = ta << tb. b{. asel ). r3. { .sat}{.clamp .u32. Left shift fills with zero.clamp && tb > 32 ) tb = 32. } // saturate.s32 }.s32. vshr }. .u32{.u32. 2010 143 .b3.Chapter 8.b2. case vshr: tmp = ta >> tb.asel}. sat. r1.

with optional operand negates. The source operands support optional negation with some restrictions.asel}.atype.h0. Description Calculate (a*b) + c. “plus one” mode. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result. final signed -(S32 * U32) + S32 // intermediate signed.po{. PTX allows negation of either (a*b) or c. .b2. final signed (U32 * U32) . The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.. . this result is sign-extended if the final result is signed. . Source operands may not be negated in . vmad. The final result is unsigned if the intermediate result is unsigned and c is not negated. final signed -(U32 * S32) + S32 // intermediate signed.sat}{.bsel = { . . 144 January 24.PTX ISA Version 2.scale = { .S32 // intermediate signed.scale} d. . final signed (S32 * U32) . . .po mode.bsel}. final signed (U32 * S32) + S32 // intermediate signed. . That is.atype = .0 Table 107. . final signed (S32 * S32) .s32 }. otherwise. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. {-}b{.shr7.atype. Depending on the sign of the a and b operands. {-}c.po) computes (a*b) + c + 1. and scaling. internally this is represented as negation of the product (a*b).scale} d.U32 // intermediate unsigned. which is used in computing averages. c.b1. final unsigned -(U32 * U32) + S32 // intermediate signed. the intermediate result is signed. final signed (S32 * S32) + S32 // intermediate signed.sat}{. . final signed (U32 * S32) . final signed -(S32 * S32) + S32 // intermediate signed.bsel}. {-}a{.b0. Although PTX syntax allows separate negation of the a and b operands.dtype. The “plus one” mode (.shr15 }.btype{.h1 }.btype. final signed (S32 * U32) + S32 // intermediate signed. final signed The intermediate result is optionally scaled via right-shift. a{. 2010 .dtype. b{. and zero-extended otherwise. and the operand negates.S32 // intermediate signed.u32.asel = . // 32-bit scalar operation vmad.S32 // intermediate signed. the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned. Input c has the same sign as the intermediate result.b3.asel}.dtype = .btype = { . (a*b) is negated if and only if exactly one of a or b is negated.

} PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.negate ) { tmp = ~tmp.or zero-extend based on source operand type ta = partSelectSignExtend( a. S32_MIN). } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ). lsb = 0.u32. } else if ( c. else result = CLAMP(result.u32.shr15 r0. Instruction Set Semantics // extract byte/half-word/word and sign. vmad requires sm_20 or later. r1. vmad. January 24.Chapter 8.s32. tmp = tmp + c128 + lsb.h0. r2. r3.negate) || c. btype. U32_MAX. r0. tmp[127:0] = ta * tb. r2. r1. U32_MIN).negate ^ b.s32.u32. case . bsel ).negate ^ b.sat ) { if (signedFinal) result = CLAMP(result.shr15: result = (tmp >> 15) & 0xffffffffffffffff. switch( scale ) { case . S32_MAX.negate. atype.h0. if ( . -r3.0.u32.negate ) { c = ~c.po ) { lsb = 1. signedFinal = isSigned(atype) || isSigned(btype) || (a. lsb = 1.sat vmad.shr7: result = (tmp >> 7) & 0xffffffffffffffff. tb = partSelectSignExtend( b. 2010 145 . lsb = 1. asel ). } if ( . } else if ( a.

atype. // 32-bit scalar operation. Semantics // extract byte/half-word/word and sign. .b3. . asel ). tb. a{.bsel}.bsel = { .op2 d.op2 Description = = = = .bsel}. bsel ).dsel . tmp. tmp = compare( ta.eq. . r3. c.lt vset.PTX ISA Version 2. . .cmp .asel = .asel}. 2010 .ne. vset requires sm_20 or later. . . { .dsel.b2. and therefore the c operand and final result are also unsigned. b{. vset. a{.0.s32.h1 }. // 32-bit scalar operation. c. c ). tb = partSelectSignExtend( b. . { .u32. .h1.u32.ge }.u32. d = optSecondaryOp( op2.btype. . vset. . r1.btype. cmp ) ? 1 : 0. .max }. btype.or zero-extend based on source operand type ta = partSelectSignExtend( a. r3. atype. // optional secondary operation d = optMerge( dsel. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.lt.asel}.gt.0 Table 108. a{. with optional secondary arithmetic operation or subword data merge.s32 }.atype . Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.bsel}.cmp d. r2.min. The intermediate result of the comparison is always unsigned. . with optional data merge vset.b1.btype = { .add. . c ).asel}. r2.atype.u32. tmp.btype.atype. b{.cmp d.le. b{. . with optional secondary operation vset.cmp. 146 January 24. Compare input values using specified comparison.ne r1.h0.b0.

January 24. Instruction Set 8. @p pmevent 1. pmevent a. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. 2010 147 . trap Abort execution and generate an interrupt to the host CPU. brkpt requires sm_11 or later. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. numbered 0 through 15. Notes PTX ISA Notes Target ISA Notes Examples Currently. Table 110. pmevent 7. Introduced in PTX ISA version 1.0. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. there are sixteen performance monitor events. with index specified by immediate operand a. Supported on all target architectures. Triggers one of a fixed number of performance monitor events. trap.7. brkpt. trap. brkpt. Introduced in PTX ISA version 1. The relationship between events and counters is programmed via API calls from the host.Chapter 8. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Table 111.0. brkpt Suspends execution Introduced in PTX ISA version 1. Supported on all target architectures.10.4.

0 148 January 24. 2010 .PTX ISA Version 2.

%clock64 %pm0. Special Registers PTX includes a number of predefined. 2010 149 . %lanemask_lt. %lanemask_ge. %lanemask_gt %clock. %lanemask_le. which are visible as special registers and accessed through mov or cvt instructions. %pm3 January 24. The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. ….Chapter 9. read-only variables.

Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported.%tid. %tid.z.u32 %ntid. mov.z == 0 in 2D CTAs. CTA dimensions are non-zero. // zero-extend tid.0.%h1. // legacy PTX 1.x. Supported on all target architectures.u32 %h1. the %tid value in unused dimensions is 0.x.y == %tid. The %tid special register contains a 1D.u32 %r1. It is guaranteed that: 0 <= %tid. mad.%ntid.z == 1 in 1D CTAs. 2010 . 2D.x. The number of threads in each dimension are specified by the predefined special register %ntid. Redefined as . .%tid. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. mov.y 0 <= %tid.u32. . Every thread in the CTA has a unique %tid.y. The total number of threads in a CTA is (%ntid. %tid.0 Table 112. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions.x.z < %ntid.x code accessing 16-bit component of %tid mov.z to %r2 Table 113.u32 %h2.u32 type in PTX 2.x * %ntid.v4 . PTX ISA Notes Introduced in PTX ISA version 1. the fourth element is unused and always returns zero.v4.z).x code Target ISA Notes Examples 150 January 24. %ntid. // move tid.u32 %ntid.%h2.z.z == 0 in 1D CTAs. %ntid. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA.z == 1 in 2D CTAs.%r0. %tid. %tid component values range from 0 through %ntid–1 in each CTA dimension. Redefined as .sreg .u32 type in PTX 2. .y < %ntid.%tid.x.u16 %rh. // thread id vector // thread id components A predefined.x 0 <= %tid. cvt. The fourth element is unused and always returns zero.%tid.sreg .x < %ntid.x to %rh Target ISA Notes Examples // legacy PTX 1.%ntid.z. or 3D vector to match the CTA shape. read-only.sreg .u32 %tid. // compute unified thread id for 2D CTA mov.y == %ntid. .x.z PTX ISA Notes Introduced in PTX ISA version 1.y. Supported on all target architectures.y. mov.u32 %r0.u16 %rh. %ntid. per-thread special register initialized with the thread identifier within the CTA.v4.0.u32 %r0.y * %ntid.u32 %tid.x.%tid.0.0.PTX ISA Version 2. // CTA shape vector // CTA dimensions A predefined. read-only special register initialized with the number of thread ids in each CTA dimension.sreg . %ntid.u16 %r2. mov.v4 . %tid. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.

A predefined.u32 %laneid. Note that %warpid is volatile and returns the location of a thread at the moment when read. read-only special register that returns the thread’s lane within the warp. Introduced in PTX ISA version 2. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. . %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.Chapter 9. Supported on all target architectures.u32 %warpid.3. The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Supported on all target architectures. but its value may change during execution. Table 115. %nwarpid requires sm_20 or later.sreg .u32 %r. read-only special register that returns the maximum number of warp identifiers. January 24. e. 2010 151 .u32 %nwarpid. The lane identifier ranges from zero to WARP_SZ-1. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. The warp identifier will be the same for all threads within a single warp. Introduced in PTX ISA version 1. %warpid.3. For this reason. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier.sreg .g. mov. mov.sreg . %laneid. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. mov. read-only special register that returns the thread’s warp identifier.u32 %r.0. PTX ISA Notes Target ISA Notes Examples Table 116.u32 %r. Introduced in PTX ISA version 1. A predefined. %nwarpid. due to rescheduling of threads following preemption. Special Registers Table 114. A predefined. . .

Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.x < %nctaid. // CTA id vector // CTA id components A predefined. read-only special register initialized with the number of CTAs in each grid dimension.u32 type in PTX 2.x. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported.0.sreg .y 0 <= %ctaid.u32 %ctaid.u32 %nctaid.sreg . Each vector element value is >= 0 and < 65535.z.u16 %r0.x.z. .x code Target ISA Notes Examples Table 118.x. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.v4 .sreg .y.u16 %r0.x.z} < 65.y.y.%nctaid.y < %nctaid. Redefined as . mov. It is guaranteed that: 1 <= %nctaid.x code Target ISA Notes Examples 152 January 24. read-only special register initialized with the CTA identifier within the CTA grid.u32 mov.0 Table 117. 2D.x. %rh.z PTX ISA Notes Introduced in PTX ISA version 1.0. depending on the shape and rank of the CTA grid.u32 %nctaid . // legacy PTX 1. mov.%nctaid. Redefined as .u32 mov.{x.y.%nctaid. with each element having a value of at least 1. %ctaid. The %nctaid special register contains a 3D grid shape vector.%nctaid.536 PTX ISA Notes Introduced in PTX ISA version 1.sreg .PTX ISA Version 2.%ctaid. %ctaid. or 3D vector.%ctaid.v4. // legacy PTX 1.u32 %ctaid. The %ctaid special register contains a 1D.0. Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid. 2010 . %rh.v4. // Grid shape vector // Grid dimensions A predefined.z < %nctaid. Supported on all target architectures. It is guaranteed that: 0 <= %ctaid. The fourth element is unused and always returns zero. The fourth element is unused and always returns zero. .x 0 <= %ctaid. . Supported on all target architectures.u32 type in PTX 2.0.v4 .

The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. A predefined. read-only special register that returns the maximum number of SM identifiers.u32 %gridid. 2010 153 .Chapter 9.sreg . mov.u32 %r. Introduced in PTX ISA version 1. %nsmid requires sm_20 or later. Note that %smid is volatile and returns the location of a thread at the moment when read.g. PTX ISA Notes Target ISA Notes Examples Table 121. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. . so %nsmid may be larger than the physical number of SMs in the device.sreg . %nsmid. // initialized at grid launch A predefined. Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier.u32 %r. Special Registers: %smid %smid Syntax (predefined) Description SM identifier.u32 %nsmid. Special Registers Table 119.u32 %smid. but its value may change during execution. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. The SM identifier numbering is not guaranteed to be contiguous. Notes PTX ISA Notes Target ISA Notes Examples Table 120. The SM identifier numbering is not guaranteed to be contiguous. A predefined. read-only special register initialized with the per-grid temporal grid identifier. Supported on all target architectures.sreg . due to rescheduling of threads following preemption. . mov. Introduced in PTX ISA version 1. During execution.0. PTX ISA Notes Target ISA Notes Examples January 24.u32 %r. read-only special register that returns the processor (SM) identifier on which a particular thread is executing. %gridid.0. repeated launches of programs may occur. Supported on all target architectures. mov. %smid.3. The SM identifier ranges from 0 to %nsmid-1. . e. Introduced in PTX ISA version 2. This variable provides the temporal grid launch number for this context. where each launch starts a grid-of-CTAs.

%lanemask_eq. 154 January 24.u32 %lanemask_eq.sreg .sreg .u32 %lanemask_le.u32 %r. read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. mov. A predefined. mov. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_le. Introduced in PTX ISA version 2.0 Table 122. mov.0. %lanemask_le requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. %lanemask_lt requires sm_20 or later. Introduced in PTX ISA version 2.0.PTX ISA Version 2. %lanemask_eq requires sm_20 or later. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp.u32 %r. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. Table 123.sreg . Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. . %lanemask_lt. Introduced in PTX ISA version 2.u32 %r. 2010 . Table 124. A predefined. A predefined.0. . .u32 %lanemask_lt.

u32 %lanemask_gt. %lanemask_gt. January 24. Special Registers Table 125.u32 %lanemask_ge.0. Introduced in PTX ISA version 2.u32 %r. .u32 %r. %lanemask_gt requires sm_20 or later.sreg .0. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. A predefined. mov. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. mov. Table 126. %lanemask_ge requires sm_20 or later. 2010 155 .sreg .Chapter 9. read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. . A predefined. %lanemask_ge. Introduced in PTX ISA version 2.

%pm1. The lower 32-bits of %clock64 are identical to %clock. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.u32 %clock. Introduced in PTX ISA version 2. .sreg . Introduced in PTX ISA version 1.0.u32 %pm0. Introduced in PTX ISA version 1.sreg .PTX ISA Version 2. %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined.u64 %clock64. %clock64 requires sm_20 or later. .3. Supported on all target architectures.u32 r1. %pm2. Table 129.sreg .u64 r1. 156 January 24.0. Special registers %pm0.%pm0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. …. Table 128. %pm2. and %pm3 are unsigned 32-bit read-only performance monitor counters. %pm3 %pm0. Special Registers: %pm0. mov. read-only 32-bit unsigned cycle counter. mov. %pm3. mov. Their behavior is currently undefined.%clock. %pm1. . %pm2.%clock64.u32 r1. Supported on all target architectures. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently. read-only 64-bit unsigned cycle counter. 2010 . %pm1.0 Table 127.

1. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file. .version 1. Duplicate .Chapter 10.version directives are allowed provided they match the original .version directive.minor // major. Supported on all target architectures.version 2.version .target Table 130.version major. . Directives 10.0. 2010 157 . and the target architecture for which the code was generated.version .version directive.4 January 24. Increments to the major number indicate incompatible changes to PTX. minor are integers Specifies the PTX language version number. . PTX File Directives: .0 .version Syntax Description Semantics PTX version number. Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number. Each ptx file must begin with a . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.

f64 instructions used. Adds {atom. 2010 . Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets. Therefore. Each PTX file must begin with a .red}. Disallows use of map_f64_to_f32. sm_10. Requires map_f64_to_f32 if any .version directive.samplerref descriptors. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture. brkpt instructions.target directives can be used to change the set of target features allowed during parsing. A .f64 storage remains as 64-bits. texmode_independent. Supported on all target architectures.texmode_unified) . including expanded rounding modifiers.texmode_unified . Introduced in PTX ISA version 1. but subsequent .PTX ISA Version 2.red}.target Syntax Architecture and Platform target. .f64 to .texmode_independent texture and sampler information is bound together and accessed via a single . Target sm_20 Description Baseline feature set for sm_20 architecture.global.target directive specifies a single target architecture.shared. immediately followed by a . sm_13.red}.5. Adds {atom. generations of SM architectures follow an “onion layer” model. A program with multiple .global. texmode_unified.f64 instructions used. PTX File Directives: .0.target directive containing a target architecture and optional platform options. Note that . The texturing mode is specified for an entire module and cannot be changed within the module. 158 January 24.target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. where each generation adds new features and retains all features of previous generations. PTX features are checked against the specified target architecture. with only half being used by instructions converted from . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations.0 Table 131. Requires map_f64_to_f32 if any . Texturing mode: (default is .f32.texref descriptor. sm_11. sm_12. In general. 64-bit {atom. Adds double-precision support. The following table summarizes the features in PTX that vary according to target architecture. Texturing mode introduced in PTX ISA version 1. Requires map_f64_to_f32 if any . Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Description Specifies the set of features in the target architecture for which the current ptx code was generated. map_f64_to_f32 }. PTX code generated for a given target can be run on later generation devices.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20.texref and . vote instructions. texture and sampler information is referenced with independent . and an error is generated if an unsupported feature is used.target .f64 instructions used.

2010 159 .target sm_13 // supports double-precision . texmode_independent January 24. Directives Examples .target sm_10 // baseline target architecture .Chapter 10.target sm_20.

param . Parameters may be referenced by name within the kernel body and loaded into registers using ld.0 through 1. Parameters are passed via . [z].texref. For PTX ISA versions 1. These parameters can only be referenced by name within texture and surface load.b32 x.surfref variables may be passed as parameters.param { .4 and later. parameters. and query instructions and cannot be accessed via ld. and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.3.entry Syntax Description Kernel entry point and body.0 through 1.b32 %r2. parameter variables are declared in the kernel parameter list. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions. Supported on all target architectures.b32 %r1. %ntid.b32 %r<99>.entry . Kernel and Function Directives: .4. . 2010 .0 10.5 and later. ld.entry kernel-name ( param-list ) kernel-body . Semantics Specify the entry point for a kernel program. . … } .samplerref. The shape and size of the CTA executing the kernel are available in special registers. and . .param instructions. the kernel dimensions and properties are established and made available via special registers. . In addition to normal parameters.entry filter ( .b32 z ) Target ISA Notes Examples [x].reg .param . At kernel launch. opaque . and body for the kernel function. 160 January 24. %nctaid. with optional parameters.param instructions.entry kernel-name kernel-body Defines a kernel entry point name.param. .b32 y. e. [y]. parameter variables are declared in the kernel body. etc.PTX ISA Version 2.b32 %r3. store. The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.g. .func Table 132.param.entry cta_fft . PTX ISA Notes For PTX ISA version 1. ld.param.entry .param space memory and are listed within an optional parenthesized parameter list. ld.2.

Directives Table 133.param and st. 2010 161 .reg . A .b32 rval) foo (.f64 dbl) { . Parameter passing is call-by-value.param space are accessed using ld. implements an ABI with stack. (val0. dbl. ret. Supported on all target architectures. there is no stack.reg .func Syntax Function definition. Variadic functions are currently unimplemented. The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.param instructions in the body.func . Parameters must be base types in either the register or parameter state space.func fname (param-list) function-body .Chapter 10. Semantics The PTX syntax hides all details of the underlying calling convention and ABI. Release Notes For PTX ISA version 1.0 with target sm_20 allows parameters in the . foo. } … call (fooval). PTX ISA 2. … use N.x code. Kernel and Function Directives: .b32 localVar. The parameter lists define locally-scoped variables in the function body.func (ret-param) fname (param-list) function-body Defines a function.reg . … Description // return value in fooval January 24. Variadic functions are represented using ellipsis following the last fixed argument.b32 N.0. if any. which may use a combination of registers and stack locations to pass parameters.func fname function-body . Parameters in . Parameters in register state space may be referenced directly within instructions in the function body. val1). mov. .2 for a description of variadic functions. and recursion is illegal.func (. .0 with target sm_20 supports at most one return value. including input and return parameters and optional function body.b32 rval. The implementation of parameter passing is left to the optimizing translator.reg .param state space. and supports recursion. . other code. parameters must be in the register state space.result.func definition with no body provides a function prototype. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. PTX 2.

The . PTX supports the following directives. or as statements within a kernel or device function body. Performance-Tuning Directives To provide a mechanism for low-level performance tuning.pragma directive is supported for passing information to the PTX backend.minnctapersm .maxntid . . These can be used. This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM. registers) to increase total thread count and provide a greater opportunity to hide memory latency. The directive passes a list of strings to the backend.maxnctapersm (deprecated) .maxntid directive specifies the maximum number of threads in a thread block (CTA).maxnreg directive specifies the maximum number of registers to be allocated to a single thread. and the strings have no semantics within the PTX virtual machine model.maxntid and . The directives take precedence over any module-level constraints passed to the optimizing backend. 162 January 24. Note that . at entry-scope. the .PTX ISA Version 2. A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device. .maxnreg. and .minnctapersm directives may be applied per-entry and must appear between an . A general . for example.minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers.pragma The . and the . to throttle the resource requirements (e.maxnreg .minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).maxntid.0 10. 2010 .pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.3.pragma directives may appear at module (file) scope. which pass information to the backend optimizing compiler. Currently.g. the .entry directive and its body. The interpretation of .

entry foo . Directives Table 134. or 3D CTA.3. ny. nz Declare the maximum number of threads in the thread block (CTA). Exceeding any of these limits results in a runtime error or kernel launch failure.maxnreg .maxntid Syntax Maximum number of threads in thread block (CTA). Introduced in PTX ISA version 1.maxntid nx. The compiler guarantees that this limit will not be exceeded.maxctapersm.maxntid . Performance-Tuning Directives: . for example. Supported on all target architectures. .maxntid and . Performance-Tuning Directives: .Chapter 10. The actual number of registers used may be less.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread. 2D.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24. ny . or the maximum number of registers may be further constrained by . .maxntid 256 . Supported on all target architectures.entry foo . 2010 163 . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.3. Introduced in PTX ISA version 1.maxnreg n Declare the maximum number of registers per thread in a CTA.maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135. This maximum is specified by giving the maximum extent of each dimention of the 1D. the backend may be able to compile to fewer registers.entry bar .maxntid nx. The maximum number of threads is the product of the maximum extent in each dimension.maxntid nx .maxntid 16. .16. .

.minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.maxnctapersm. additional CTAs may be mapped to a single multiprocessor. Supported on all target architectures.0 as a replacement for .maxnctapersm has been renamed to .3.0 Table 136. 2010 .minnctapersm . Optimizations based on .0.maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. .minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).entry foo .minnctapersm generally need .maxntid to be specified as well. For this reason.maxnctapersm (deprecated) . Supported on all target architectures. Introduced in PTX ISA version 2. However.maxntid and . Optimizations based on .maxntid to be specified as well. Performance-Tuning Directives: . The optimizing backend compiler uses . .maxnctapersm generally need .maxntid 256 .minnctapersm 4 { … } 164 January 24.PTX ISA Version 2.0. .minnctapersm in PTX ISA version 2. Introduced in PTX ISA version 1. .entry foo . Deprecated in PTX ISA version 2. if the number of registers used by the backend is sufficiently lower than this bound. Performance-Tuning Directives: .maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM.maxntid 256 .

.pragma “nounroll”.pragma directive may occur at module-scope.pragma directive strings is implementation-specific and has no impact on PTX semantics. Directives Table 138. Introduced in PTX ISA version 2. or at statementlevel.pragma Syntax Description Pass directives to PTX backend compiler. See Appendix A for descriptions of the pragma strings defined in ptxas.pragma . at entry-scope. The interpretation of . The .entry foo . Performance-Tuning Directives: . or statement-level directives to the PTX backend compiler. . entry-scoped.0. { … } January 24. Supported on all target architectures.pragma “nounroll”.pragma list-of-strings .Chapter 10. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel . Pass module-scoped. 2010 165 .

2. “”. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF .0.section ..4. Supported on all target architectures.0 and replaces the @@DWARF syntax.4byte . 0x00000364.x code.section directive is new in PTX ISA verison 2.byte 0x2b.4byte 0x6e69616d.section directive.4byte label .4byte int32-list // comma-separated hexadecimal integers in range [0. 2010 . 0x00.264-1] . @@DWARF dwarf-string dwarf-string may have one of the .file . The @@DWARF syntax is deprecated as of PTX version 2. @progbits . 0x00.0 but is supported for legacy PTX version 1.byte 0x00.debug_info . 0x00 166 January 24.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser. 0x02.loc The ..debug_pubnames. 0x00 .quad int64-list // comma-separated hexadecimal integers in range [0. 0x63613031. replaced by . 0x00.PTX ISA Version 2. 0x00. Table 139. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF . 0x00.byte byte-list // comma-separated hexadecimal byte values .232-1] . 0x736d6172 .4byte 0x000006b5.0 10. Introduced in PTX ISA version 1. 0x5f736f63 . Deprecated as of PTX 2. 0x00. Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information. 0x6150736f. 0x61395a5f.section .

Supported on all target architectures. 0x00. 0x00.b32 int32-list // comma-separated list of integers in range [0.b8 0x00. 0x00 0x61395a5f. . 2010 167 . 0x00.232-1] .255] .b8 0x2b. .b32 0x6e69616d.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . Debugging Directives: ..debug_pubnames { . 0x00.section . Debugging Directives: . 0x00.file filename Table 142.b8 byte-list // comma-separated list of integers in range [0..file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 0x5f736f63 0x6150736f.section .section section_name { dwarf-lines } dwarf-lines have the following formats: .debug_info .0. Source file information. 0x00000364. Debugging Directives: .0. Source file location.b32 0x000006b5.loc line_number January 24..264-1] .loc .b64 int64-list // comma-separated list of integers in range [0. .0. Supported on all target architectures. 0x736d6172 0x00 Table 141.file . 0x63613031.Chapter 10.b32 .b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.section Syntax PTX section definition. Directives Table 140. Supported on all target architectures. . replaces @@DWARF syntax. .b32 label . 0x00. . } 0x02.

extern . .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration. . Linking Directives .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration. Supported on all target architectures.extern .global .b32 foo.visible .0.0 10.0.b32 foo. Introduced in PTX ISA version 1.6.global .extern . // foo will be externally visible 168 January 24.PTX ISA Version 2. 2010 .visible Table 143. .extern identifier Declares identifier to be defined externally. Introduced in PTX ISA version 1. Linking Directives: .visible identifier Declares identifier to be externally visible.visible . . Supported on all target architectures. // foo is defined in another module Table 144. Linking Directives: .

0 CUDA 2.0.1 CUDA 2.1 CUDA 2.0 CUDA 1.3 PTX ISA 1.2 CUDA 2.1 PTX ISA 1. The release history is as follows.5 PTX ISA 2.0 PTX ISA 1.2 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1.0 January 24. CUDA Release CUDA 1. The first section describes ISA and implementation changes in the current release of PTX ISA 2. and the remaining sections provide a record of changes in previous releases. Release Notes This section describes the history of change in the PTX ISA and implementation.Chapter 11. 2010 169 .3 driver r190 CUDA 3.4 PTX ISA 1.

0 for sm_20 targets. The goal is to achieve IEEE 754 compliance wherever possible. Single-precision add.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.rp rounding modifiers for sm_20 targets. rcp. and sqrt with IEEE 754 compliant rounding have been added. Changes in Version 2.f32 for sm_20 targets. Both fma. Floating-Point Extensions This section describes the floating-point changes in PTX 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets.1.and double-precision div. The fma.f32 require a rounding modifier for sm_20 targets.f32 maps to fma. and mul now support .rm and .1. The . 2010 . with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers.0 11. The mad. while maximizing backward compatibility with legacy PTX 1.ftz modifier may be used to enforce backward compatibility with sm_1x.x code and sm_1x targets.PTX ISA Version 2. • • • • • 170 January 24. The changes from PTX ISA 1. The mad.ftz and .1.f32 and mad.1.0 11. New Features 11. fma. When code compiled for sm_1x is executed on sm_20 devices. mad.1. These are indicated by the use of a rounding modifier and require sm_20.f32. Instructions testp and copysign have been added.f32 instruction also supports . A single-precision fused multiply-add (fma) instruction has been added.rn. sub.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma.sat modifiers. Single.1.f32 requires sm_20.

1. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. . Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. The bar instruction has been extended as follows: • • • A bar. bfe and bfi. has been added.{and.shared have been extended to handle 64-bit data types for sm_20 targets. for prefetching to specified level of memory hierarchy. Instructions {atom.maxnctapersm directive was deprecated and replaced with . has been added. atom.clamp and .Chapter 11. prefetchu.ballot.1. A “vote ballot” instruction.clamp modifiers. ldu. Release Notes 11. st. isspacep.arrive instruction has been added. has been added.zero. popc. st. cvta. suld. %clock64.2.b32. Video instructions (includes prmt) have been added. .red}. has been added.pred have been added. Instructions {atom. A “population count” instruction.le.u32 and bar.f32 have been implemented.1. membar. bar now supports optional thread count and register operands.red}. Cache operations have been added to instructions ld. A system-level membar instruction. has been added. Surface instructions support additional . A “find leading non-sign bit” instruction. e.sys.3. January 24.popc. and red now support generic addressing. A “bit reversal” instruction. has been added. New special registers %nsmid. Instructions prefetch and prefetchu have also been added.gt} have been added. has been added. The . A new directive. 11.minnctapersm to better match its behavior and usage. Instructions bar.ge.red. 2010 171 . clz. bfind.red.g.add. and shared addresses to generic address and vice-versa has been added.section. have been added. %lanemask_{eq. vote. Instruction sust now supports formatted surface stores. local. ldu. Bit field extract and insert instructions. New instructions A “load uniform” instruction.lt. prefetch. A “count leading zeros” instruction. Other new features Instructions ld.or}.1. and sust. Instruction cvta for converting global. brev.

p. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.target sm_1x. single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits. cvt.ftz (and cvt for . where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits.red}. 172 January 24.{u32. Formatted surface store with .ftz for PTX ISA versions 1. See individual instruction descriptions for details. Semantic Changes and Clarifications The errata in cvt.2.f32} atom. Formatted surface load is unimplemented.5 and later.version is 1.{min.5. .PTX ISA Version 2.u32. if . the correct number is sixteen. or .s32. has been fixed.f32.3. Instruction bra.0 11.4 and earlier. where . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. 2010 . call suld. To maintain compatibility with legacy PTX code. {atom.1.f32 type is unimplemented.s32. The underlying.4 or earlier. Support for variadic functions and alloca are unimplemented. stack-based ABI is unimplemented.max} are not implemented. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. 11.1. In PTX version 1.p sust.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.

. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module.func bar (…) { … L1_head: .pragma strings defined by ptxas. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. including loops preceding the . L1_end: … } // do not unroll this loop January 24.pragma.Appendix A. Supported only for sm_20 targets. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. { … } // do not unroll any loop in this function .pragma “nounroll”. disables unrolling for all loops in the entry function body. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. … @p bra L1_end. Table 145. Ignored for sm_1x targets. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.pragma Strings This section describes the . and statement levels.entry foo (…) . 2010 173 .pragma “nounroll”. The “nounroll” pragma is allowed at module.pragma “nounroll”. Note that in order to have the desired effect at statement level. Descriptions of . . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop.0. L1_body: … L1_continue: bra L1_head. entry-function. disables unrolling of0 the loop for which the current block is the loop header.

0 174 January 24. 2010 .PTX ISA Version 2.

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