NVIDIA Compute

PTX: Parallel Thread Execution ISA Version 2.0

January 24, 2010

PTX ISA Version 2.0

January 24, 2010

Table of Contents

PTX: Parallel Thread Execution ISA Version 2.0 ............................................................. 1 Chapter 1. Introduction .................................................................................................... 1
1.1. 1.2. 1.3. Scalable Data-Parallel Computing Using GPUs .............................................................. 1 Goals of PTX ................................................................................................................... 1 PTX ISA Version 2.0 ........................................................................................................ 2 Improved Floating-Point Support ............................................................................. 2 Generic Addressing ................................................................................................. 3 Support for an Application Binary Interface ............................................................. 3 New Instructions ...................................................................................................... 3

1.3.1. 1.3.2. 1.3.3. 1.3.4. 1.4.

The Document’s Structure ............................................................................................... 5

Chapter 2. Programming Model ...................................................................................... 7
2.1. 2.2. A Highly Multithreaded Coprocessor ............................................................................... 7 Thread Hierarchy ............................................................................................................. 7 Cooperative Thread Arrays ..................................................................................... 7 Grid of Cooperative Thread Arrays .......................................................................... 8

2.2.1. 2.2.2. 2.3.

Memory Hierarchy ......................................................................................................... 10

Chapter 3. Parallel Thread Execution Machine Model ................................................... 13
3.1. A Set of SIMT Multiprocessors with On-Chip Shared Memory ..................................... 13

Chapter 4. Syntax ......................................................................................................... 17
4.1. 4.2. 4.3. Source Format ............................................................................................................... 17 Comments ..................................................................................................................... 17 Statements ..................................................................................................................... 18 Directive Statements.............................................................................................. 18 Instruction Statements ........................................................................................... 18

4.3.1. 4.3.2. 4.4. 4.5.

Identifiers ....................................................................................................................... 20 Constants ....................................................................................................................... 21 Integer Constants .................................................................................................. 21 Floating-Point Constants ....................................................................................... 21 Predicate Constants .............................................................................................. 22 Constant Expressions ............................................................................................ 22 Integer Constant Expression Evaluation ............................................................... 23

4.5.1. 4.5.2. 4.5.3. 4.5.4. 4.5.5.

January 24, 2010

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........................................................3..........3.................................. Operand Type Information .................................. 5................................................................................... 5...................... 5...................... 5............................. 38 Alignment ....8..................4....... Function declarations and definitions .......................... 5..................... 5........... 25 Chapter 5..........................................4.................................................. and Vectors .. 28 Constant State Space .................... 5.............................. 44 Rounding Modifiers ...............4....................... 42 Addresses as Operands ..................................................... 6..............2...........................2......................................5...................... 41 Using Addresses.....6........................................................................... 2010 . 39 5......... 28 Special Register State Space ...........5..........................................6.1................6... 5......... 30 Shared State Space....................................................4............................................................... 37 Array Declarations ......... 44 Scalar Conversions .......................................... 6................2.............................................. Types .................................... Arrays..... 5...................1..1.......................3..............5....... 6...........4..................... 43 6.................... 29 Parameter State Space .4...6.1............................. 32 5........ 5.........4..........4................................................. 34 Variables ......................................... 33 5............................................ 5........... 49 7............. Sampler........... 6..........7.................................................... 29 Global State Space ............. 5........................1...... 46 6............................ 43 Labels and Function Names as Operands ............................1....2............ 38 Initializers ..................................1...................................................................................................4..1.......4.........1...............0 4....... 33 Restricted Use of Sub-Word Sizes .................................... 5................. 5...... 27 5............................... 6..................................... 37 Vectors ..................1.......1......... Summary of Constant Expression Evaluation Rules ................... 39 Parameterized Variable Names .................. and Variables ............. State Spaces ...................... 5.................. 6................PTX ISA Version 2.................... State Spaces................... 43 Vectors as Operands ......... 6.................... 41 6.....................4.............3.....1..................................................................... Chapter 6..................................................................1............. 33 Fundamental Types ........................................... 41 Source Operands................ 47 Chapter 7.4..............1............................4......................................................................................... Abstracting the ABI ...................... and Surface Types ............................. Texture..1.......... 6.......5................................................................................................... 41 Destination Operands .........................................5........4..................................................................................................................... 32 Texture State Space (deprecated) ....................... 27 Register State Space ............................... 5............................................2...5............1...2............................................................3....2............ Types........................................................................................ 42 Arrays as Operands ............... 37 Variable Declarations .............................................................................. Type Conversion..................2............ 29 Local State Space ......... 49 ii January 24.. 6.......................................................... Operand Costs .2......................................4..................................... Instruction Operands...............................................

......1......... Changes from PTX 1....7......6.......... 58 8............................... 11......2.............7.. 63 Floating-Point Instructions ....................... 52 Variadic functions .............................................1......................................... 166 Linking Directives ...................................................................... 129 Parallel Synchronization and Communication Instructions ..................... 8.... 132 Video Instructions ................1............................... Changes in Version 2.. 8................................ 81 Comparison and Selection Instructions ..........................................................3........8........................3.................................. 162 Debugging Directives ............ 57 Manipulating Predicates ....................................................... 60 8............................. 170 Semantic Changes and Clarifications .......4....... 169 11.....7........................3..............................................................................................7. 7..7................................. 10......10............2......................................1....1........................................... 62 Machine-Specific Semantics of 16-bit Code ......................................... 55 8............................ 55 PTX Instructions .......... 8............................ 10...... Release Notes ............................................................................. 140 Miscellaneous Instructions.. 10...................................3..... Divergence of Threads in Control Constructs ...........................................3....... 2010 iii .................................... 55 Predicated Execution ...................... Directives .....1............. PTX Version and Target Directives .........................................................4.. 8................................................................... 122 Control Flow Instructions ............................................2................................6............................... 11..2..............1.................. 8..... 168 Chapter 11.....................................6..............................................7.......................................... 56 Comparisons ............................7...................4....................................................................7.................................................................. Special Registers ................ 53 Alloca ................................. 160 Performance-Tuning Directives ................2.........3.. 7................................ 8.. 108 Texture and Surface Instructions .............................................. 8.................1................................................0 ... 170 New Features ................................1..4..3.................................x ..........................1..... 157 Specifying Kernel Entry Points and Functions ............................................................................................................................................... 63 Integer Arithmetic Instructions ........ 8...............................5......... 100 Logic and Shift Instructions ............................................ 10...... Type Information for Instructions and Operands .... Format and Semantics of Instruction Descriptions ... 8....1........... Instructions ....................................... 157 10.. 8.................................................................7................... 8..................7.......................................1... 147 8.......................................7...7......... 8...... 149 Chapter 10......................................................................................................2....... 54 Chapter 8..................................................................... 11...................................7. Instruction Set ..........9.................................................................... 172 January 24........................................ Chapter 9..................... 62 8.........1................5.............. 8.............. 8......... 172 Unimplemented Features Remaining ............................................... 8........ 8......................6.. 62 Semantics ................................ 104 Data Movement and Conversion Instructions ..... 59 Operand Size Exceeding Instruction-Type Size .

pragma Strings.... 2010 ...................0 Appendix A...... 173 iv January 24...... Descriptions of ....................PTX ISA Version 2.............

.................... Table 11......................................... 67 Integer Arithmetic Instructions: mad ................................................................................................. 59 Relaxed Type-checking Rules for Source Operands ........................ 57 Floating-Point Comparison Operators Accepting NaN ............................ Table 28.............................................. 65 Integer Arithmetic Instructions: sub.................................................. 57 Floating-Point Comparison Operators ... 65 Integer Arithmetic Instructions: addc ................................................................... Table 6.............. 60 Relaxed Type-checking Rules for Destination Operands....... Table 4....cc .......... 58 Type Checking Rules ................ Table 30.. 70 Integer Arithmetic Instructions: sad ......................... 20 Operator Precedence ............................................. Table 12.................................................... Table 17................................................ 33 Opaque Type Fields in Unified Texture Mode ................................. Table 20......... 18 Reserved Instruction Keywords ..................................................List of Tables Table 1.......................................................................................................... 27 Properties of State Spaces ................... Table 15..................................... Table 2...................................................................................... Table 13...... 64 Integer Arithmetic Instructions: sub ...................................... Table 8........... 23 Constant Expression Evaluation Rules ............................................................ 2010 v ....................... Table 9.................... Table 31..... and Bit-Size Types ............... Table 27................................................................................................................................... Table 23.............................................................................................................................................. Unsigned Integer................................................................. PTX Directives ......... 47 Operators for Signed Integer.................. Table 25..... Table 7...... 64 Integer Arithmetic Instructions: add.......................................... 71 January 24.................... Table 18........................................ 28 Fundamental Type Specifiers ........ Table 16............................................cc .......................................... 61 Integer Arithmetic Instructions: add ....................................................................... 66 Integer Arithmetic Instructions: mul .......................... 45 Floating-Point Rounding Modifiers ....... 19 Predefined Identifiers ..... Table 14......................... 66 Integer Arithmetic Instructions: subc ..................... Table 19................................................. Table 3.......... Table 21............... 25 State Spaces .......................... Table 22..... 68 Integer Arithmetic Instructions: mul24 ......................... 69 Integer Arithmetic Instructions: mad24 ............................................................ 35 Convert Instruction Precision and Format .. 46 Integer Rounding Modifiers ..................................................... 35 Opaque Type Fields in Independent Texture Mode ................................... Table 24..... Table 32................................................... Table 29......... Table 26..................................... Table 5........ 46 Cost Estimates for Accessing State-Spaces .............................................................. Table 10................................. 58 Floating-Point Comparison Operators Testing for NaN .

.............. Table 51......................................................................... 83 Floating-Point Instructions: copysign ............ 85 Floating-Point Instructions: mul ................. Table 54.... Table 52..................................................................................................................................................... Table 36. 103 vi January 24................................. 87 Floating-Point Instructions: mad .................................................................................................. 84 Floating-Point Instructions: sub ... Table 43.. Table 38................................................................................ Table 67............ Table 65........................ 77 Integer Arithmetic Instructions: bfi ........... Table 69........................... Table 47.................................................. 72 Integer Arithmetic Instructions: neg ....... 90 Floating-Point Instructions: abs ............................................. Table 56....................................... Table 53................................................ 86 Floating-Point Instructions: fma ......................................................................................................... 102 Comparison and Selection Instructions: selp ..... Table 58........................................................................................................ Table 46.................................................... 83 Floating-Point Instructions: add .............. Table 44...................................... Table 49.............................0 Table 33........ 92 Floating-Point Instructions: rcp .................... 2010 ............................................................................................. 93 Floating-Point Instructions: sqrt ............................... 99 Comparison and Selection Instructions: set ........................................................ Table 55.......................................... 71 Integer Arithmetic Instructions: rem ......................................................................... Table 45.............................. Table 62.............. 74 Integer Arithmetic Instructions: bfind ............................................................................................................. 79 Summary of Floating-Point Instructions ............. 96 Floating-Point Instructions: cos ......... 92 Floating-Point Instructions: max .................... 97 Floating-Point Instructions: lg2 .................................................................................................. 75 Integer Arithmetic Instructions: brev .................................... Table 63.... 91 Floating-Point Instructions: min ........... Table 41.... Table 50......................... 95 Floating-Point Instructions: sin .................... Table 64... Table 42..... 72 Integer Arithmetic Instructions: min ............................................ Integer Arithmetic Instructions: div ................... Table 40.....................................................................PTX ISA Version 2............................................... 103 Comparison and Selection Instructions: slct ...................................................................................... 88 Floating-Point Instructions: div .............................................. 74 Integer Arithmetic Instructions: clz .................... Table 35............................ Table 60............................................................................................................ Table 61.................................... Table 57.......................... Table 37......... 78 Integer Arithmetic Instructions: prmt .......... 71 Integer Arithmetic Instructions: abs ...................... Table 48..... Table 59..... Table 39.................................................. 73 Integer Arithmetic Instructions: popc ................................ 101 Comparison and Selection Instructions: setp ............................................................................ Table 34................................................ 82 Floating-Point Instructions: testp . Table 66............................................................................................ 94 Floating-Point Instructions: rsqrt ... 98 Floating-Point Instructions: ex2 ....................................... Table 68.............. 73 Integer Arithmetic Instructions: max ... 91 Floating-Point Instructions: neg ................. 76 Integer Arithmetic Instructions: bfe .....................................

................................................... Table 96... 2010 vii .............. 119 Data Movement and Conversion Instructions: cvt ............................................................ vshr ..... 118 Data Movement and Conversion Instructions: isspacep ..................... 120 Texture and Surface Instructions: tex .......................... Table 95............................................................................... 130 Control Flow Instructions: ret .................... 106 Logic and Shift Instructions: shl ......... Table 83................ 105 Logic and Shift Instructions: or .................................................................. Table 86.... 119 Data Movement and Conversion Instructions: cvta ....... vsub.......................................................................................................................... 110 Data Movement and Conversion Instructions: mov ........................................................................ 126 Texture and Surface Instructions: sured......... Table 72............................ Table 100........................... Table 99....... 139 Video Instructions: vadd........ Table 92............................................. vmax ................................................... Table 94................................. Table 98..... 116 Data Movement and Conversion Instructions: prefetch......... Table 90.................................... 107 Logic and Shift Instructions: shr ........................................ Table 97................ 129 Control Flow Instructions: @ ...... Table 85............................................................. prefetchu .. Table 71............. Table 73........................................................................ Table 105.............................................................Table 70........................................ Table 88.......... 109 Cache Operators for Memory Store Instructions .............. 131 Parallel Synchronization and Communication Instructions: bar .................................................... 106 Logic and Shift Instructions: not ...................................................................... Logic and Shift Instructions: and .................... 127 Texture and Surface Instructions: suq ................................................ 113 Data Movement and Conversion Instructions: ldu ... Table 106........ 133 Parallel Synchronization and Communication Instructions: membar ........................ 105 Logic and Shift Instructions: xor ............... Table 103............... 111 Data Movement and Conversion Instructions: mov ........................................................... 123 Texture and Surface Instructions: txq ............................................. Table 78................ Table 102.................................................................... Table 101. Table 89............................... Table 77..................................................................... Table 79................ Table 76........................... Table 104.. 112 Data Movement and Conversion Instructions: ld ........................... Table 91...................................... Table 87...... 135 Parallel Synchronization and Communication Instructions: red ................. Table 84.............. 125 Texture and Surface Instructions: sust ......................................... 130 Control Flow Instructions: call ....................................... 143 January 24.... 142 Video Instructions: vshl............. 107 Cache Operators for Memory Load Instructions ........ 131 Control Flow Instructions: exit .................... Table 74.......... Table 81... 134 Parallel Synchronization and Communication Instructions: atom ...... Table 82. 106 Logic and Shift Instructions: cnot ................ Table 80........................... vmin....... 128 Control Flow Instructions: { } ....... Table 93..... 124 Texture and Surface Instructions: suld .. Table 75......................................................... 129 Control Flow Instructions: bra ........................ 115 Data Movement and Conversion Instructions: st ....................................................................... 137 Parallel Synchronization and Communication Instructions: vote ...... vabsdiff...

................................................... Table 132........ 150 Special Registers: %ntid ................................................... 167 Debugging Directives: ............................................ Table 136. Video Instructions: vmad ................................................ Table 108.................................................. %pm1............................................pragma ............. 163 Performance-Tuning Directives: . Table 135..................... 155 Special Registers: %lanemask_gt ............................ 156 PTX File Directives: ................................................................................................ Table 133................................section .................................. 165 Debugging Directives: @@DWARF ............. 2010 ...................................................................... 156 Special Registers: %clock64 ..................................... Table 142..................................... 146 Miscellaneous Instructions: trap ....... 153 Special Registers: %nsmid .......................... 153 Special Registers: %lanemask_eq ............................. Table 137........ %pm3 ...... Table 126... Table 141.................. Table 121.... 154 Special Registers: %lanemask_ge ........................... 154 Special Registers: %lanemask_le ............... Table 125..........................maxnctapersm (deprecated) .... Table 131... 144 Video Instructions: vset.............................entry.... 163 Performance-Tuning Directives: ................... Table 138.................. Table 113............................................................. Table 128.................................... Table 119............................................................................maxnreg ..................target ...................... Table 127................................................. Table 117.func ............................. 152 Special Registers: %nctaid ....loc .... Table 120....................................................................... Table 139.... Table 134..................................................................................................................... Table 112.............................................. 155 Special Registers: %clock ..................... Table 111...................... Table 140................................................... 161 Performance-Tuning Directives: .................................................... 156 Special Registers: %pm0.............................. 151 Special Registers: %nwarpid ........................................ 147 Special Registers: %tid .............. 152 Special Registers: %smid ..........................................minnctapersm ....................................................... Table 122................. 164 Performance-Tuning Directives: ...................................................................... 147 Miscellaneous Instructions: pmevent.... Table 123.......................... 164 Performance-Tuning Directives: ... Table 118.... Table 124.... Table 109... Table 114......... 147 Miscellaneous Instructions: brkpt ............ %pm2............................................. 158 Kernel and Function Directives: .......................................................... 157 PTX File Directives: ... 151 Special Registers: %warpid ....... 151 Special Registers: %ctaid ...... 154 Special Registers: %lanemask_lt ..................... 168 viii January 24........................ 160 Kernel and Function Directives: ............................................... 150 Special Registers: %laneid ................................... Table 115..........0 Table 107................ Table 116.......................................................................................PTX ISA Version 2......................................................................................................................................................version. Table 130............................................................. Table 129..........extern.................................................... Table 143...................... 166 Debugging Directives: .....file ....... 167 Linking Directives: ...............................................maxntid . 167 Debugging Directives: ......... 153 Special Registers: %gridid ....... Table 110...................................................................

.............................visible........ Linking Directives: ...Table 144.............. Table 145. 168 Pragma Strings: “nounroll” ................................... 2010 ix .............................................................................. 173 January 24...

2010 .PTX ISA Version 2.0 x January 24.

image and media processing applications such as post-processing of rendered images. In fact.1. video encoding and decoding. 1. PTX programs are translated at install time to the target hardware instruction set. Introduction This document describes PTX. Many applications that process large data sets can use a data-parallel programming model to speed up the computations. In 3D rendering large sets of pixels and vertices are mapped to parallel threads. multithreaded. high-definition 3D graphics. Scalable Data-Parallel Computing Using GPUs Driven by the insatiable market demand for real-time.2. High level language compilers for languages such as CUDA and C/C++ generate PTX instructions. a low-level parallel thread execution virtual machine and instruction set architecture (ISA). many-core processor with tremendous computational horsepower and very high memory bandwidth. It is designed to be efficient on NVIDIA GPUs supporting the computation features defined by the NVIDIA Tesla architecture.Chapter 1. The PTX-toGPU translator and driver enable NVIDIA GPUs to be used as programmable parallel computers. the memory access latency can be hidden with calculations instead of big data caches. January 24. many algorithms outside the field of image rendering and processing are accelerated by dataparallel processing. Similarly. Goals of PTX PTX provides a stable programming model and instruction set for general purpose parallel programming. and pattern recognition can map image blocks and pixels to parallel processing threads. and because it is executed on many data elements and has high arithmetic intensity. from general signal processing or physics simulation to computational finance or computational biology. there is a lower requirement for sophisticated flow control. 1. Data-parallel processing maps data elements to parallel processing threads. PTX defines a virtual machine and ISA for general purpose parallel thread execution. PTX exposes the GPU as a data-parallel computing device. image scaling. Because the same program is executed for each data element. stereo vision. The GPU is especially well-suited to address problems that can be expressed as data-parallel computations – the same program is executed on many data elements in parallel – with high arithmetic intensity – the ratio of arithmetic operations to memory operations. 2010 1 . the programmable GPU has evolved into a highly parallel. which are optimized for and translated to native target-architecture instructions.

1.3. sub. Most of the new features require a sm_20 target.0 is in improved support for the IEEE 754 floating-point standard. A “flush-to-zero” (.0 are improved support for IEEE 754 floating-point operations.ftz and .x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32 require a rounding modifier for sm_20 targets. When code compiled for sm_1x is executed on sm_20 devices.PTX ISA Version 2. 1. Provide a code distribution ISA for application and middleware developers.f32 requires sm_20. addition of generic addressing to facilitate the use of general-purpose pointers.x features are supported on the new sm_20 target. Improved Floating-Point Support A main area of change in PTX 2.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Facilitate hand-coding of libraries. fma.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. and all PTX 1. PTX 2. Provide a scalable programming model that spans GPU sizes from a single unit to many parallel units.1.f32.f32 maps to fma. The mad. Legacy PTX 1.sat modifiers. The main areas of change in PTX 2. and the introduction of many new instructions.0 introduces a number of new features corresponding to new capabilities of the sm_20 target architecture. A single-precision fused multiply-add (fma) instruction has been added.0 is a superset of PTX 1. performance kernels. including integer.rn. and architecture tests.3. reduction. mad. and mul now support . Provide a machine-independent ISA for C/C++ and other compilers to target. The fma.f32 for sm_20 targets. extensions to the function parameter and call syntax to support an Application Binary Interface and stack-allocation of local variables.0 PTX ISA Version 2. Both fma. The changes from PTX ISA 1. PTX ISA Version 2. and video instructions.ftz treat single-precision subnormal inputs as sign-preserving zero and flush single-precision subnormal results to sign-preserving zero. 2010 .0 The goals for PTX include the following: Provide a stable ISA that spans multiple GPU generations. Provide a common source-level ISA for optimizing code generators and translators. surface. • • • 2 January 24. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. Achieve performance in compiled applications comparable to native GPU performance. atomic. memory.x.rm and . The mad.ftz) modifier may be used to enforce backward compatibility with sm_1x. Single-precision add. barrier.f32 and mad. which map PTX to specific target machines.x code will continue to run on sm_1x targets as well. Instructions marked with .rp rounding modifiers for sm_20 targets.f32 instruction also supports .

special registers. Instruction cvta for converting global.4. Generic Addressing Another major change is the addition of generic addressing.zero. for prefetching to specified level of memory hierarchy. These are indicated by the use of a rounding modifier and require sm_20. A new cvta instruction has been added to convert global.2. prefetch. See Section 7 for details of the function definition and call syntax needed to abstract the ABI. rcp. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. ldu. Instructions testp and copysign have been added. local. and sust. these changes bring PTX 2. Support for an Application Binary Interface Rather than expose details of a particular calling convention. suld. stack layout. Cache operations have been added to instructions ld. Memory Instructions • • • • • Instruction ldu supports efficient loads from a “uniform” address. • Taken as a whole. 2010 3 . Generic addressing unifies the global..0.g. e. NOTE: The current version of PTX does not implement the underlying. allowing memory instructions to access these spaces without needing to specify the state space. 1. and vice versa. New Instructions The following new instructions. so recursion is not yet supported. prefetchu. 1. isspacep. and red now support generic addressing.3. Instructions prefetch and prefetchu have been added. local.0 provides a slightly higher-level abstraction and supports multiple ABI implementations.Chapter 1. and shared addresses to generic addresses. local.3. i.clamp and .and double-precision div. and sqrt with IEEE 754 compliant rounding have been added.0 closer to full compliance with the IEEE 754 standard. atom. stack-based ABI.e. and Application Binary Interface (ABI). st. and directives are introduced in PTX 2. . Surface instructions support additional clamp modifiers. 1.0. an address that is the same across all threads in a warp. Introduction • Single. cvta. PTX 2. Surface Instructions • • Instruction sust now supports formatted surface stores. In PTX 2. January 24. and shared addresses to generic address and vice-versa has been added. instructions ld.3. st.3. and shared state spaces.

A bar. 4 January 24.red. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. Instructions {atom.shared have been extended to handle 64-bit data types for sm_20 targets.section. %lanemask_{eq.sys.arrive instruction has been added. New special registers %nsmid.f32 have been added. Instructions bar.lt. and Vote Instructions • • • New atomic and reduction instructions {atom.pred have been added. bfi bit field extract and insert popc clz Atomic.{and.red}. bar now supports an optional thread count and register operands. has been added. A new directive. Reduction.red.0 Integer Instructions • • • • • population count count leading zeros bfind find leading non-sign bit brev bit reversal bfe.ge. has been added. . Other Extensions • • • Video instructions (includes prmt) have been added. A “vote ballot” instruction.gt} have been added.le. 2010 .or}.PTX ISA Version 2. membar.popc.ballot. Barrier Instructions • • A system-level membar instruction.u32 and bar.b32.add. vote. %clock64.red}.

Chapter 6 describes instruction operands. Chapter 5 describes state spaces. January 24.4. types. Chapter 4 describes the basic syntax of the PTX language. Chapter 11 provides release notes for PTX Version 2. Chapter 8 describes the instruction set. Chapter 7 describes the function and call syntax.0. calling convention. Introduction 1. Chapter 10 lists the assembly directives supported in PTX. Chapter 9 lists special registers. Chapter 3 gives an overview of the PTX virtual machine model. and variable declarations. 2010 5 . The Document’s Structure The information in this document is organized into the following Chapters: Chapter 2 outlines the programming model.Chapter 1. and PTX support for abstracting the Application Binary Interface (ABI).

0 6 January 24. 2010 .PTX ISA Version 2.

a portion of an application that is executed many times. A Highly Multithreaded Coprocessor The GPU is a compute device capable of executing a very large number of threads in parallel.y. Cooperative Thread Arrays The Parallel Thread Execution (PTX) programming model is explicitly parallel: a PTX program specifies the execution of a given thread of a parallel thread array. or 3D CTA.2. assign specific input and output positions. 2. 2D. A cooperative thread array.x. or host: In other words.1. More precisely. Each CTA has a 1D. Thread Hierarchy The batch of threads that executes a kernel is organized as a grid of cooperative thread arrays as described in this section and illustrated in Figure 1.1. (with elements tid. tid. compute addresses. Programming Model 2. Each CTA thread uses its thread identifier to determine its assigned role. and select work to perform. but independently on different data. and ntid. ntid.x. or CTA. compute-intensive portions of applications running on the host are off-loaded onto the device. and tid. such a function is compiled to the PTX instruction set and the resulting kernel is translated at install time to the target GPU instruction set. It operates as a coprocessor to the main CPU. work.z) that specifies the thread’s position within a 1D. is an array of threads that execute a kernel concurrently or in parallel. or 3D shape specified by a three-element vector ntid (with elements ntid. data-parallel.Chapter 2. To that effect. January 24. The thread identifier is a three-element vector tid. one can specify synchronization points where threads wait until all threads in the CTA have arrived. Each thread has a unique thread identifier within the CTA. 2. and results across the threads of the CTA. 2D.y.z). Cooperative thread arrays (CTAs) implement CUDA thread blocks. can be isolated into a kernel function that is executed on the GPU as many different threads. The vector ntid specifies the number of threads in each CTA dimension. Each thread identifier component ranges from zero up to the number of thread ids in that CTA dimension.2. 2010 7 . Programs use a data parallel decomposition to partition inputs. To coordinate the communication of the threads within the CTA. Threads within a CTA can communicate with each other.

Each kernel is executed as a batch of threads organized as a grid of CTAs (Figure 1). or 3D shape specified by the parameter nctaid. Each grid of CTAs has a 1D. %ctaid.2. 2. However. Each CTA has a unique CTA identifier (ctaid) within a grid of CTAs. or sequentially. Grid of Cooperative Thread Arrays There is a maximum number of threads that a CTA can contain. so that the total number of threads that can be launched in a single kernel invocation is very large. The host issues a succession of kernel invocations to the device. Threads within a warp are sequentially numbered. such that the threads execute the same instructions at the same time. so PTX includes a run-time immediate constant. CTAs that execute the same kernel can be batched together into a grid of CTAs. Some applications may be able to maximize performance with knowledge of the warp size. which may be used in any instruction where an immediate operand is allowed. Threads may read and use these values through predefined. 2010 . %nctaid. read-only special registers %tid. 8 January 24. because threads in different CTAs cannot communicate and synchronize with each other.0 Threads within a CTA execute in SIMT (single-instruction. Typically. Multiple CTAs may execute concurrently and in parallel. and %gridid. %ntid. The warp size is a machine-dependent constant. depending on the platform. 2D . A warp is a maximal subset of threads from a single CTA. This comes at the expense of reduced thread communication and synchronization. WARP_SZ. a warp has 32 threads.PTX ISA Version 2. Each grid also has a unique temporal grid identifier (gridid).2. multiple-thread) fashion in groups called warps.

0) Thread (1. Thread Batching January 24. 1) CTA (2. 1) Thread (1. 1) CTA (1. 0) Thread (4. 1) Thread (0. 0) CTA (2. 0) Thread (0. 0) CTA (0. Programming Model Host GPU Grid 1 Kernel 1 CTA (0. 2010 9 . 0) Thread (2. 2) Thread (3. 2) Thread (1. 1) Thread (0. 1) Thread (3. A grid is a set of CTAs that execute independently. 1) Grid 2 Kernel 2 CTA (1. 0) Thread (3. 1) Thread (2.Chapter 2. 2) Thread (4. 2) A cooperative thread array (CTA) is a set of concurrent threads that execute the same kernel program. 1) Thread (4. 0) CTA (1. 2) Thread (2. Figure 1.

and texture memory spaces are persistent across kernel launches by the same application. Each thread has a private local memory. Both the host and the device maintain their own local memory. all threads have access to the same global memory. for some specific data formats. Memory Hierarchy PTX threads may access data from multiple memory spaces during their execution as illustrated by Figure 2. and texture memory spaces are optimized for different memory usages.PTX ISA Version 2. 2010 . copied from the host memory through optimized API calls that utilize the device’s high-performance Direct Memory Access (DMA) engine. There are also two additional read-only memory spaces accessible by all threads: the constant and texture memory spaces. as well as data filtering. constant. respectively.0 2. The global. constant. for more efficient transfer. Each thread block (CTA) has a shared memory visible to all threads of the block and with the same lifetime as the block. Finally.3. referred to as host memory and device memory. The global. 10 January 24. Texture memory also offers different addressing modes. The device memory may be mapped and read or written by the host. or.

1) Block (0.Chapter 2. 1) Block (2. 1) Block (1. 1) Block (1. Programming Model Thread Per-thread local memory Thread Block Per-block shared memory Grid 0 Block (0. 0) Block (1. 2) Figure 2. 2) Block (1. 0) Block (0. Memory Hierarchy January 24. 0) Block (0. 2010 11 . 0) Block (2. 0) Block (1. 1) Grid 1 Global memory Block (0.

PTX ISA Version 2. 2010 .0 12 January 24.

the blocks of the grid are enumerated and distributed to multiprocessors with available execution capacity. The multiprocessor creates. The way a block is split into warps is always the same. a cell in a grid-based computation). The threads of a thread block execute concurrently on one multiprocessor. and executes threads in groups of parallel threads called warps. manages. The multiprocessor SIMT unit creates. A Set of SIMT Multiprocessors with On-Chip Shared Memory The NVIDIA Tesla architecture is built around a scalable array of multithreaded Streaming Multiprocessors (SMs). it splits them into warps that get scheduled by the SIMT unit. the multiprocessor employs a new architecture we call SIMT (single-instruction.1. When a multiprocessor is given one or more thread blocks to execute. (This term originates from weaving. It implements a single-instruction barrier synchronization. 2010 13 . different warps execute independently regardless of whether they are executing common or disjointed code paths. Branch divergence occurs only within a warp. At every instruction issue time. January 24. As thread blocks terminate. When a host program invokes a kernel grid. so full efficiency is realized when all threads of a warp agree on their execution path. and executes concurrent threads in hardware with zero scheduling overhead. a multithreaded instruction unit.) Individual threads composing a SIMT warp start together at the same program address but are otherwise free to branch and execute independently. and when all paths complete. Parallel Thread Execution Machine Model 3. the first parallel thread technology. A warp executes one common instruction at a time. The multiprocessor maps each thread to one scalar processor core. the SIMT unit selects a warp that is ready to execute and issues the next instruction to the active threads of the warp. If threads of a warp diverge via a data-dependent conditional branch. schedules. allowing. To manage hundreds of threads running several different programs. increasing thread IDs with the first warp containing thread 0. a voxel in a volume. disabling threads that are not on that path. for example. and each scalar thread executes independently with its own instruction address and register state. A multiprocessor consists of multiple Scalar Processor (SP) cores. the warp serially executes each branch path taken. new blocks are launched on the vacated multiprocessors. manages. the threads converge back to the same execution path.Chapter 3. each warp contains threads of consecutive. and on-chip shared memory. multiple-thread). Fast barrier synchronization together with lightweight thread creation and zero-overhead thread scheduling efficiently support very fine-grained parallelism. a low granularity decomposition of problems by assigning one thread to each data element (such as a pixel in an image.

each multiprocessor has on-chip memory of the four following types: • • • One set of local 32-bit registers per processor.0 SIMT architecture is akin to SIMD (Single Instruction. Multiple Data) vector organizations in that a single instruction controls multiple processing elements. the number of serialized writes that occur to that location and the order in which they occur is undefined. whereas SIMT instructions specify the execution and branching behavior of a single thread. but the order in which they occur is undefined. 2010 . which is a read-only region of device memory. require the software to coalesce loads into vectors and manage divergence manually.PTX ISA Version 2. this is analogous to the role of cache lines in traditional code: Cache line size can be safely ignored when designing for correctness but must be considered in the code structure when designing for peak performance. modifies. SIMT enables programmers to write thread-level parallel code for independent. and writes to the same location in global memory for more than one of the threads of the warp. however. write to that location occurs and they are all serialized. but one of the writes is guaranteed to succeed. A multiprocessor can execute as many as eight thread blocks concurrently. As illustrated by Figure 3. For the purposes of correctness. 14 January 24. If an atomic instruction executed by a warp reads. which is a read-only region of device memory. A key difference is that SIMD vector organizations expose the SIMD width to the software. the programmer can essentially ignore the SIMT behavior. each read. In practice. Vector architectures. as well as data-parallel code for coordinated threads. How many blocks a multiprocessor can process at once depends on how many registers per thread and how much shared memory per block are required for a given kernel since the multiprocessor’s registers and shared memory are split among all the threads of the batch of blocks. scalar threads. A read-only texture cache that is shared by all scalar processor cores and speeds up reads from the texture memory space. If a non-atomic instruction executed by a warp writes to the same location in global or shared memory for more than one of the threads of the warp. • The local and global memory spaces are read-write regions of device memory and are not cached. modify. on the other hand. In contrast with SIMD vector machines. A parallel data cache or shared memory that is shared by all scalar processor cores and is where the shared memory space resides. substantial performance improvements can be realized by taking care that the code seldom requires threads in a warp to diverge. each multiprocessor accesses the texture cache via a texture unit that implements the various addressing modes and data filtering. If there are not enough registers or shared memory available per multiprocessor to process at least one block. A read-only constant cache that is shared by all scalar processor cores and speeds up reads from the constant memory space. the kernel will fail to launch.

Figure 3. Hardware Model January 24. 2010 15 .Chapter 3. Parallel Thread Execution Machine Model Device Multiprocessor N Multiprocessor 2 Multiprocessor 1 Shared Memory Registers Registers Registers Processor 1 Processor 2 … Instruction Unit Processor M Constant Cache Texture Cache Device Memory A set of SIMT multiprocessors with on-chip shared memory.

2010 .PTX ISA Version 2.0 16 January 24.

#if.1. whitespace is ignored except for its use in separating tokens in the language. and using // to begin a comment that extends to the end of the current line.2. #define.version directive specifying the PTX language version. The ptxas optimizing backend compiler optimizes and assembles PTX source files to produce corresponding binary object files. PTX is case sensitive and uses lowercase for keywords. using non-nested /* and */ for comments that may span multiple lines. #line. Comments Comments in PTX follow C/C++ syntax. Lines beginning with # are preprocessor directives. PTX source files have an assemblylanguage style syntax with instruction operation codes and operands. The C preprocessor cpp may be used to process PTX source files.target directive specifying the target architecture assumed. Comments in PTX are treated as whitespace. Source Format Source files are ASCII text. 4. 2010 17 . #file C: A Reference Manual by Harbison and Steele provides a good description of the C preprocessor. Pseudo-operations specify symbol and addressing management. 4. January 24. See Section 9 for a more information on these directives.Chapter 4. #endif. #ifdef. #else. Each PTX file must begin with a . The following are common preprocessor directives: #include. Syntax PTX programs are a collection of text source files. followed by a . Lines are separated by the newline character (‘\n’). All whitespace characters are equivalent.

and is written as @p.2.maxnctapersm .loc .sreg .local .reg . Directive Statements Directive keywords begin with a dot.x. so no conflict is possible with user-defined identifiers. constant expressions. followed by source operands.extern .target .entry . or label names. written as @!p. address expressions. r2. 2010 .const .visible 4.param . Statements begin with an optional label and end with a semicolon. r2.minnctapersm .maxnreg .pragma . All instruction keywords are reserved tokens in PTX. .1. // shift thread id by 2 bits // thread[tid] gets array[tid] // add 1/2 4. 2. mov. where p is a predicate register.0 4. and terminated with a semicolon.f32 array[N].f32 r2.3. The destination operand is first. ld.3.5. 18 January 24. %tid. shl. Statements A PTX statement is either a directive or an instruction.func .reg .version . Instruction Statements Instructions are formed from an instruction opcode followed by a comma-separated list of zero or more operands.PTX ISA Version 2. . r1.b32 r1.b32 add.section .global.shared .global . The guard predicate may be optionally negated.b32 r1. Instruction keywords are listed in Table 2.global start: . Instructions have an optional guard predicate which controls conditional execution.align . r2.3.maxntid . Operands may be register variables.file PTX Directives .b32 r1. Table 1.tex . array[r1]. Examples: . The guard predicate follows the optional label and precedes the opcode. The directives in PTX are listed in Table 1 and described in Chapter 5 and Chapter 10. 0.

Syntax Table 2. 2010 19 .Chapter 4. abs add addc and atom bar bfe bfi bfind bra brev brkpt call clz cnot cos cvt cvta Reserved Instruction Keywords div ex2 exit fma isspacep ld ldu lg2 mad mad24 max membar min mov mul mul24 neg not or pmevent popc prefetch prefetchu prmt rcp red rem ret rsqrt sad selp set setp shl shr sin slct sqrt st sub subc suld sured sust suq tex txq trap vabsdiff vadd vmad vmax vmin vset vshl vshr vsub vote xor January 24.

PTX allows the percentage sign as the first character of an identifier. or they start with an underscore. between user-defined variable names and compiler-generated names. %pm3 WARP_SZ 20 January 24. %tid %ntid %warpid %nwarpid Predefined Identifiers %ctaid %nctaaid %smid %nsmid %laneid %gridid %lanemask_eq %lanemask_le %laneid_lt %laneid_ge %laneid_gt %clock %clock64 %pm0.g. Identifiers User-defined identifiers follow extended C++ rules: they either start with a letter followed by zero or more letters. digits. listed in Table 3. or dollar characters: followsym: identifier: [a-zA-Z0-9_$] [a-zA-Z]{followsym}* | {[_$%]{followsym}+ PTX does not specify a maximum length for identifiers and suggests that all implementations support a minimum length of at least 1024 characters. PTX predefines one constant and a small number of special registers that begin with the percentage sign. underscore. The percentage sign can be used to avoid name conflicts.4. 2010 . …. digits. except that the percentage sign is not allowed. e.0 4. underscore.PTX ISA Version 2. or percentage character followed by one or more letters. Many high-level languages such as C and C++ follow similar rules for identifier names. dollar. Table 3. or dollar characters.

floating-point.s64) unless the value cannot be fully represented in . Unlike C and C++.e. 4. in which case the literal is unsigned (. every integer constant has type ..2. 2010 21 .u64. Integer literals may be followed immediately by the letter ‘U’ to indicate that the literal is unsigned. the constant begins with 0d or 0D followed by 16 hex digits. The syntax follows that of C. When used in an instruction or data initialization.5.1. 4.5. The only exception is the 32-bit hex notation for expressing an exact single-precision floating-point value. 0[fF]{hexdigit}{8} // single-precision floating point January 24. hexadecimal literal: octal literal: binary literal: decimal literal 0[xX]{hexdigit}+U? 0{octal digit}+U? 0[bB]{bit}+U? {nonzero-digit}{digit}*U? Integer literals are non-negative and have a type determined by their magnitude and optional type suffix as follows: literals are signed (.. there is no suffix letter to specify size.s64 or the unsigned suffix is specified. Floating-point literals may be written with an optional decimal point and an optional signed exponent. Type checking rules remain the same for integer. literals are always represented in 64-bit double-precision format. or binary notation.e.Chapter 4. For predicate-type data and instructions. i. To specify IEEE 754 doubleprecision floating point values. Each 64-bit floating-point constant is converted to the appropriate floating-point size based on the data or instruction type at its use. and bit-size types.5. each integer constant is converted to the appropriate size based on the data or instruction type at its use. PTX includes a second representation of floating-point constants for specifying the exact machine representation using a hexadecimal constant. i. integer constants are allowed and are interpreted as in C. and all floatingpoint constant expressions are evaluated using 64-bit double precision arithmetic. zero values are FALSE and non-zero values are TRUE. Constants PTX supports integer and floating-point constants and constant expressions. Integer literals may be written in decimal. To specify IEEE 754 single-precision floating point values. Syntax 4. octal. These constants may be used in data initialization and as operands to instructions. The signed/unsigned nature of an integer constant is needed to correctly evaluate constant expressions containing operations such as division and ordered comparisons.u64). the sm_1x and sm_20 targets have a WARP_SZ value of 32. hexadecimal.s64 or . Integer Constants Integer constants are 64-bits in size and are either signed or unsigned. The predefined integer constant WARP_SZ specifies the number of threads per warp for the target platform. where the behavior of the operation depends on the operand types. such values retain their exact 32-bit single-precision value and may not be used in constant expressions. the constant begins with 0f or 0F followed by 8 hex digits. Floating-Point Constants Floating-point constants are represented as 64-bit double-precision values.

PTX ISA Version 2.0

0[dD]{hexdigit}{16}

// double-precision floating point

Example:
mov.f32 $f3, 0F3f800000; // 1.0

4.5.3. Predicate Constants
In PTX, integer constants may be used as predicates. For predicate-type data initializers and instruction operands, integer constants are interpreted as in C, i.e., zero values are FALSE and non-zero values are TRUE.

4.5.4. Constant Expressions
In PTX, constant expressions are formed using operators as in C and are evaluated using rules similar to those in C, but simplified by restricting types and sizes, removing most casts, and defining full semantics to eliminate cases where expression evaluation in C is implementation dependent. Constant expressions are formed from constant literals, unary plus and minus, basic arithmetic operators (addition, subtraction, multiplication, division), comparison operators, the conditional ternary operator ( ? : ), and parentheses. Integer constant expressions also allow unary logical negation (!), bitwise complement (~), remainder (%), shift operators (<< and >>), bit-type operators (&, |, and ^), and logical operators (&&, ||). Constant expressions in ptx do not support casts between integer and floating-point. Constant expressions are evaluated using the same operator precedence as in C. The following table gives operator precedence and associativity. Operator precedence is highest for unary operators and decreases with each line in the chart. Operators on the same line have the same precedence and are evaluated right-to-left for unary operators and left-to-right for binary operators.

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Chapter 4. Syntax

Table 4.
Kind

Operator Precedence
Operator Symbols () + - ! ~ (.s64) (.u64) Operator Names parenthesis plus, minus, negation, complement casts multiplication, division, remainder addition, subtraction shifts ordered comparisons equal, not equal bitwise AND bitwise XOR bitwise OR logical AND logical OR conditional right Associates n/a right right left

Primary Unary Binary

* / % + >> << < > <= >= == != & ^ | && ||

Ternary

?:

4.5.5. Integer Constant Expression Evaluation
Integer constant expressions are evaluated at compile time according to a set of rules that determine the type (signed .s64 versus unsigned .u64) of each sub-expression. These rules are based on the rules in C, but they’ve been simplified to apply only to 64-bit integers, and behavior is fully defined in all cases (specifically, for remainder and shift operators).

Literals are signed unless unsigned is needed to prevent overflow, or unless the literal uses a ‘U’ suffix. Example: 42, 0x1234, 0123 are signed. Example: 0xFABC123400000000, 42U, 0x1234U are unsigned. Unary plus and minus preserve the type of the input operand. Example: +123, -1, -(-42) are signed Example: -1U, -0xFABC123400000000 are unsigned. Unary logical negation (!) produces a signed result with value 0 or 1. Unary bitwise complement (~) interprets the source operand as unsigned and produces an unsigned result. Some binary operators require normalization of source operands. This normalization is known as the usual arithmetic conversions and simply converts both operands to unsigned type if either operand is unsigned. Addition, subtraction, multiplication, and division perform the usual arithmetic conversions and produce a result with the same type as the converted operands. That is, the operands and result are unsigned if either source operand is unsigned, and is otherwise signed.

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Remainder (%) interprets the operands as unsigned. Note that this differs from C, which allows a negative divisor but defines the behavior to be implementation dependent. Left and right shift interpret the second operand as unsigned and produce a result with the same type as the first operand. Note that the behavior of right-shift is determined by the type of the first operand: right shift of a signed value is arithmetic and preserves the sign, and right shift of an unsigned value is logical and shifts in a zero bit. AND (&), OR (|), and XOR (^) perform the usual arithmetic conversions and produce a result with the same type as the converted operands. AND_OP (&&), OR_OP (||), Equal (==), and Not_Equal (!=) produce a signed result. The result value is 0 or 1. Ordered comparisons (<, <=, >, >=) perform the usual arithmetic conversions on source operands and produce a signed result. The result value is 0 or 1. Casting of expressions to signed or unsigned is supported using (.s64) and (.u64) casts. For the conditional operator ( ? : ) , the first operand must be an integer, and the second and third operands are either both integers or both floating-point. The usual arithmetic conversions are performed on the second and third operands, and the result type is the same as the converted type.

• • • • •

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Chapter 4. 2nd is .s64 .u64 .f64 integer .f64 integer integer integer integer integer int ?.s64 .s64 .f64 use usual conversions .* / < > <= >= == != % >> << & | ^ && || Ternary ?: January 24.u64 .s64 .u64 .u64.s64) + .s64 .f64 use usual conversions .u64 1st unchanged.6. Kind Primary Unary () Constant Expression Evaluation Rules Operator Operand Types any type n/a any type integer integer integer integer .5.s64 . or . .u64 same as 1st operand .u64 .f64 use usual conversions .f64 converted type constant literal + ! ~ Cast Binary (.u64 zero or non-zero same as sources use usual conversions Result Type same as source .s64.f64 : .f64 same as source .f64 int ? int : int Operand Interpretation same as source n/a same as source zero or non-zero . 2010 25 .s64 .f64 integer .s64 .u64 . Syntax 4.f64 converted type .u64 . Summary of Constant Expression Evaluation Rules These rules are summarized in the following table.u64) (. Table 5.

0 26 January 24. 2010 .PTX ISA Version 2.

addressability. and level of sharing between threads. Types.Chapter 5. Global texture memory (deprecated). or Function or local parameters. shared by all threads. 2010 27 .const . Table 6. State Spaces A state space is a storage area with particular characteristics.shared .local .sreg . All variables reside in some state space. Special registers. Kernel parameters. Shared. and Variables While the specific resources available in a given target GPU will vary.tex January 24.global . platform-specific. access rights.reg . The state spaces defined in PTX are a byproduct of parallel programming and graphics programming. 5. access speed. The characteristics of a state space include its size. and these resources are abstracted in PTX through state spaces and data types.param . the kinds of resources will be common across platforms. The list of state spaces is shown in Table 4. State Spaces. read-only memory. Local memory. Addressable memory shared between threads in 1 CTA. fast. private to each thread. defined per-thread. . Global memory.1. pre-defined. and properties of state spaces are shown in Table 5. defined per-grid. Read-only. Name State Spaces Description Registers.

CTA.param (used in functions) . or 128-bits. 28 January 24. The number of registers is limited. 64-.global . causing changes in performance. Registers may have alignment boundaries required by multi-word loads and stores. For each architecture.local . st.param instructions. 16-. the parameter is then located on the stack frame and its address is in the .shared . and vector registers have a width of 16-. 1 Accessible only via the ld.PTX ISA Version 2. and thread parameters.2. and performance monitoring registers. register variables will be spilled to memory. Address may be taken via mov instruction. i. via driver Access R/W RO RO R/W R/W RO R/W R/W RO Sharing per-thread per-CTA per-grid Context per-thread per-grid per-thread per-CTA Context . 3 Accessible only via the tex instruction. predicate) or untyped. 2 Accessible via ld. or 64-bits.1.sreg .const . it is not possible to refer to the address of a register. Name Properties of State Spaces Addressable No No Yes Yes Yes Yes 1 2 Initializable No No Yes Yes No No No No Yes. The most common use of 8-bit registers is with ld. Device function input parameters may have their address taken via mov. Special Register State Space The special register (. Registers differ from the other state spaces in that they are not fully addressable.local state space. 32-.tex Restricted Yes No3 5.reg state space) are fast storage locations. there is a recommended maximum number of registers to use (see the “CUDA Programming Guide” for details).1. floating point.0 Table 7. 32-. aside from predicate registers which are 1-bit. Register State Space Registers (. 5.param and st.param instruction. Registers may be typed (signed integer. platform-specific registers. scalar registers have a width of 8-. When the limit is exceeded.sreg) state space holds predefined. clock counters.param (as input to kernel) . Register size is restricted. or as elements of vector tuples. All special registers are predefined. such as grid.1. 2010 . and will vary from platform to platform.. and cvt instructions.reg . unsigned integer.e.

Sequential consistency is provided by the bar. For example. 5.extern . For any thread in a context.const[2]. the declaration . State Spaces. Note that statically-sized variables cannot be declared in the same bank as an incomplete array since the size of the array is unknown. This pointer can then be used to access the entire 64KB constant bank. Use ld. b = b – 1. ld. Global memory is not sequentially consistent. as it must be allocated on a perthread basis. Local State Space The local state space (.global) state space is memory that is accessible by all threads in a context.sync instruction are guaranteed to be visible to any reads after the barrier instruction.const[2] . bank zero is used. 2010 29 . It is the mechanism by which different CTAs and different grids can communicate.b32 %r1. Module-scoped local memory variables are stored at fixed addresses. each pointing to the start address of the specified constant bank.const[bank] modifier.4.const) state space is a read-only memory. the bank number must be provided in the state space of the load instruction. In implementations that support a stack.b32 const_buffer[]. Consider the case where one thread executes the following two assignments: a = a + 1. All memory writes prior to the bar. To access data in contant banks 1 through 10. the stack is in local memory. st. // load second word 5.5.local and st.sync instruction. For example. This reiterates the kind of parallelism available in machines that run PTX.global.b32 const_buffer[]. initialized by the host. results in const_buffer pointing to the start of constant bank two. where bank ranges from 0 to 10. all addresses are in global memory are shared. Constant State Space The constant (.local) is private memory for each thread to keep its own data. Threads wait at the barrier until all threads in the CTA have arrived. The remaining banks may be used to implement “incomplete” constant arrays (in C. [const_buffer+4]. For the current devices.local to access local variables.extern . as in lock-free and wait-free style programming. It is typically standard memory with cache. If no bank number is given.Chapter 5.const[2] .global to access global variables. By convention. The constant memory is organized into fixed size banks.3. bank zero is used for all statically-sized constant variables.1. there are eleven 64KB banks. Types. Threads must be able to do their work without waiting for other threads to do theirs. whereas local memory variables declared January 24. Banks are specified using the . the store operation updating a may still be in flight. Global State Space The global (. an incomplete array in bank 2 is accessed as follows: . where the size is not known at compile time. and Variables 5.global.1. for example). The size is limited. Multiple incomplete array variables declared in the same bank become aliases. and atom.1. Use ld. If another thread sees the variable b change.

Note: The location of parameter space is implementation specific.x supports only kernel function parameters in . These parameters are addressable.0 and requires target architecture sm_20. (2a) to declare formal input and return parameters for device functions called from within kernel execution.param . [%ptr]. In implementations that do not support a stack.0 within a function or kernel body are allocated on the stack. … 30 January 24.u32 %ptr. No access protection is provided between parameter and global space in this case. 5. Example: .6.param . read-only variables declared in the . The use of parameter state space for device function parameters is new to PTX ISA version 2.f64 %d.b32 N.PTX ISA Version 2. in some implementations kernel parameters reside in global memory. PTX code should make no assumptions about the relative locations or ordering of .entry foo ( .b8 buffer[64] ) { . Therefore. The resulting address is in the . Parameter State Space The parameter (. [N]. [buffer].u32 %n.u32 %ptr.1.entry bar ( . 2010 .param.b32 len ) { . .u32 %n.f64 %d. Kernel Function Parameters Each kernel function definition includes an optional list of parameters.param instructions. For example. … Example: . Values passed from the host to the kernel are accessed through these parameter variables using ld.param. Kernel function parameters differ from device function parameters in terms of access and sharing (read-only versus read-write.align 8 .reg .param state space.reg . len. %n. ld. Similarly.param) state space is used (1) to pass input arguments from the host to the kernel.param state space and is accessed using ld. all local memory variables are stored at fixed addresses and recursive function calls are not supported. mov.6. and (2b) to declare locally-scoped byte array variables that serve as function call arguments.param. The address of a kernel parameter may be moved into a register using the mov instruction.u32 %n.1. 5.param space variables. per-kernel versus per-thread). ld. ld. function parameters are mapped to parameter passing registers and/or stack locations based on the function calling conventions of the Application Binary Interface (ABI). Note that PTX ISA versions 1. device function parameters were previously restricted to the register state space.param . .param instructions. typically for passing large structures by value to a function.1. The kernel parameter variables are shared across all CTAs within a grid.param space.reg .

param space is also required whenever a formal parameter has its address taken within the called function. 2010 31 . a byte array in parameter space is used. and so the address will be in the . … } // code snippet from the caller // struct { double d. (4. It is not possible to use mov to get the address of a return parameter or a locally-scoped .local and st.f64 dbl. mystruct).param. such as C structures larger than 8 bytes.f64 %d.6.f64 [mystruct+0]. which declares a .param .param.b8 mystruct. [buffer]. int y.s32 %y. the address of a function input parameter may be moved into a register using the mov instruction. Typically.reg . . . State Spaces.0 extends the use of parameter space to device function parameters.param . In PTX. Note that the parameter will be copied to the stack if necessary. } mystruct.param. Device Function Parameters PTX ISA version 2. . . passed to foo … .reg . Function input parameters may be read via ld. This will be passed by value to a callee.param.align 8 . int y. Aside from passing structures by value. the caller will declare a locally-scoped .s32 x. ld.param formal parameter having the same size and alignment as the passed argument.b32 N.reg . st. call foo.2. The most common use is for passing objects by value that do not fit within a PTX register.local state space and is accessed via ld. and Variables 5. x.param byte array variable that represents a flattened C structure or union.reg . January 24.func foo ( . }. ld. is flattened.s32 %y. .param. it is illegal to write to an input parameter or read from a return parameter. Example: // pass object of type struct { double d.align 8 . … See the section on function call syntax for more details.b8 buffer[12] ) { .reg . [buffer+8].Chapter 5.1.local instructions. In this case. … st.param space variable. Types. dbl.s32 [mystruct+8]. .param and function return parameters may be written using st.f64 %d.

tex_c. tex_f. Shared State Space The shared (.shared and st.u64. An error is generated if the maximum number of physical resources is exceeded. and . Example: .u32 .3 for the description of the .8. The texture name must be of type . An address in shared memory can be read and written by any thread in a CTA.tex variables are required to be defined in the global scope.global state space. The .tex state space are equivalent to module-scoped .tex directive will bind the named texture memory variable to a hardware texture identifier.6 for its use in texture instructions.tex directive is retained for backward compatibility.tex .texref variables in the .u32 .shared) state space is a per-CTA region of memory for threads in a CTA to share data.tex . 32 January 24. where texture identifiers are allocated sequentially beginning with zero. tex_d.u32 tex_a. Physical texture resources are allocated on a per-module granularity. See Section 5. 2010 . is equivalent to . // // // // bound to physical texture 0 both bound to physical texture 1 bound to physical texture 2 bound to physical texture 3 Note: use of the texture state space is deprecated. The .u32 or . Texture State Space (deprecated) The texture (. Texture memory is read-only. 5.global .u32 tex_a.7.7. For example.tex .tex . Shared memory typically has some optimizations to support the sharing.1. and programs should instead reference texture memory through variables of type . A texture’s base address is assumed to be aligned to a 16-byte boundary.texref. Multiple names may be bound to the same physical texture identifier. The GPU hardware has a fixed number of texture bindings that can be accessed within a single program (typically 128).shared to access shared variables.u32 .1. It is shared by all threads in a context. where all threads read from the same address. Use ld. One example is broadcast. a legacy PTX definitions such as .texref tex_a.tex . and variables declared in the .0 5. Another is sequential access from sequential threads.tex) state space is global memory accessed via the texture instruction. tex_d.PTX ISA Version 2.texref type and Section 8.

s32. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded.2.b16.f64 .2.u8.f32 and . stored. Fundamental Types In PTX. State Spaces.f16. The bitsize type is compatible with any fundamental type having the same size. Basic Type Signed integer Unsigned integer Floating-point Bits (untyped) Predicate Fundamental Type Specifiers Fundamental Type Specifiers . or converted to other types and sizes. All floating-point instructions operate only on .f64 types. A fundamental type specifies both a basic type and a size. the fundamental types reflect the native data types supported by the target architectures. and . . stored.s64 . . and cvt instructions permit source and destination data operands to be wider than the instruction-type size. . The following table lists the fundamental type specifiers for each basic type: Table 8. .u64 . needed to fully specify instruction behavior. and Variables 5. st. st. and cvt instructions.2. all variables (aside from predicates) could be declared using only bit-size types. Restricted Use of Sub-Word Sizes The .s8.f32 and . so that narrow values may be loaded.b32.f32.pred Most instructions have one or more type specifiers.1.f16 floating-point type is allowed only in conversions to and from . January 24. 2010 33 . 5. but typed variables enhance program readability and allow for better operand type checking. . .2. For convenience.s16. . . ld.s8.b8 instruction types are restricted to ld. and converted using regular-width registers. .u32. so their names are intentionally short. Register variables are always of a fundamental type. and instructions operate on these types.u16.u8. .Chapter 5. Two fundamental types are compatible if they have the same basic type and are the same size.b64 . Types. Types 5. . Signed and unsigned integer types are compatible if they have the same size. For example. In principle. The . Operand types and sizes are checked against instruction types for compatibility. .b8.f64 types. The same typesize specifiers are used for both variable definitions and for typing instructions.

The three built-in types are . or performing pointer arithmetic will result in undefined results.samplerref.{u32. Retrieving the value of a named member via query instructions (txq.texref handle. samplers. These types have named fields similar to structures. suld. sampler. sust. and de-referenced by texture and surface load.u64} reg. The following tables list the named members of each type for unified and independent texture modes. . Texture. allowing them to be defined separately and combined at the site of usage in the program.3. PTX has two modes of operation. and .PTX ISA Version 2.. or surfaces via texture and surface load/store instructions (tex. base address. Creating pointers to opaque variables using mov. Static initialization of module-scope variables using comma-delimited static assignment expressions for the named members of the type.texref. In the unified mode.surfref.texref type that describe sampler properties are ignored.samplerref variables. and Surface Types PTX includes built-in “opaque” types for defining texture. field ordering.0 5. passed as a parameter to functions. and query instructions. texture and sampler information each have their own handle. and surface descriptor variables. since these properties are defined by .e. the resulting pointer may be stored to and loaded from memory. In independent mode the fields of the . 2010 . but the pointer cannot otherwise be treated as an address. texture and sampler information is accessed through a single . These members and their values have precise mappings to methods and values defined in the texture HW class as well as exposed values via the API. i. In the independent mode. Referencing textures. but all information about layout. accessing the pointer with ld and st instructions. The use of these opaque types is limited to: • • • • • Variable definition within global (module) scope and in kernel entry parameter lists. 34 January 24. suq). For working with textures and samplers. hence the term “opaque”. store. opaque_var. and overall size is hidden to a PTX program. sured). Sampler.

clamp_ogl. mirror. Types. linear wrap.samplerref values N/A N/A N/A N/A nearest. Member width height depth Opaque Type Fields in Unified Texture Mode .surfref values in elements in elements in elements N/A N/A N/A N/A N/A normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 January 24. clamp_ogl. and Variables Table 9.Chapter 5. State Spaces. clamp_to_border N/A N/A N/A N/A N/A . mirror. clamp_to_border 0. 2010 35 . 1 nearest. clamp_to_edge. 1 ignored ignored ignored ignored . Member width height depth Opaque Type Fields in Independent Texture Mode . linear wrap.surfref values normalized_coords filter_mode addr_mode_0 addr_mode_1 addr_mode_2 Table 10. clamp_to_edge.texref values in elements in elements in elements 0.texref values .

global .samplerref my_sampler_name.global .texref tex1.surfref my_surface_name.global .0 Variables using these types may be declared at module scope or within kernel entry parameter lists. 2010 . these variables must be in the . Example: .param state space. At module scope. 36 January 24.PTX ISA Version 2. Example: . . As kernel parameters. . these variables are declared in the .samplerref tsamp1 = { addr_mode_0 = clamp_to_border.global state space.global . When declared at module scope.global .texref my_texture_name. . filter_mode = nearest }. the types may be initialized using a list of static expressions assigning values to the named members.

global . where the fourth element provides padding.4. 5. Every variable must reside in one of the state spaces enumerated in the previous section.b8 v.const . an optional array size.f64 is not allowed.v4.u8 bg[4] = {0. // typedef . // a length-4 vector of bytes By default.v4 . Variable Declarations All storage for data is specified with variable declarations. etc. PTX supports types for simple aggregate objects such as vectors and arrays.struct float4 coord.v4 .v2 or .u16 uv. for example. Variables In PTX. 2010 37 . Vectors cannot exceed 128-bits in length.struct float4 { . 1. // a length-2 vector of unsigned ints . Three-element vectors may be handled by using a . .u32 loc.global . This is a common case for three-dimensional grids. State Spaces. Examples: .reg .v3 }. 0.Chapter 5.global . Vectors must be based on a fundamental type. and Variables 5. January 24.v4 .1. 0. 5.f32 accel. Predicate variables may only be declared in the register state space.0}. its name. 0}.pred p. and an optional fixed address for the variable. textures. // a length-4 vector of floats .4. an optional initializer.4.v2 .reg .v2.s32 i.shared .v4 vector. .0. Types.2. Examples: . . . In addition to fundamental types. its type and size.v4.f32 v0.global . and they may reside in the register space. .f32 bias[] = {-1.f32 V. r. a variable declaration describes both the variable’s type and its state space. Vectors Limited-length vector types are supported.v1. Vectors of length 2 and 4 of any non-predicate fundamental type can be declared by prefixing the type with . .global . to enable vector load and store instructions which require addresses aligned to a multiple of the access size. vector variables are aligned to a multiple of their overall size (vector length times base-type size). q.reg . . A variable declaration names the space in which the variable resides.

0.global .f16 and .0}}. ..s32 offset[][] = { {-1.1. . Array Declarations Array declarations are provided to allow the programmer to reserve space.PTX ISA Version 2.0. while vectors and arrays take nested lists of values inside of curly braces (the nesting matches the dimensionality of the declaration).0}. For the kernel declaration above. this can be used to initialize a jump table to be used with indirect branches or calls. {0. 1} }. .u8 mailbox[128]. Here are some examples: .f32 blur_kernel[][] = {{.05.1.0 5. 5.pred.4.05}. where the variable name is followed by an equals sign and the initial value or values for the variable. -1}.0..4.1}..global .{.1. Initializers are allowed for all types except . A scalar takes a single value. The size of the array specifies how many elements should be reserved. . Variable names appearing in initializers represent the address of the variable. the variable name is followed with dimensional declarations similar to fixed-size array declarations in C.0. The size of the dimension is either a constant expression. {0.global .{. Initializers Declared variables may specify an initial value using a syntax similar to C/C++. variable initialization is supported only for constant and global state spaces. label names appearing in initializers represent the address of the next instruction following the label.local .1. 0}. {1.u32 or .u64.global . Variables that hold addresses of variables or instructions should be of type .1.05.05}}. . // address of rgba into ptr Currently. 2010 . {0.. this can be used to statically initialize a pointer to a variable.s32 n = 10.u8 rgba[3] = {{1.b32 ptr = rgba. 19*19 (361) halfwords are reserved (722 bytes).global . 38 January 24.0}. 0}.4.u16 kernel[19][19].4. being determined by an array initializer.. Similarly.shared . {0..v4 .3. or is left empty. Examples: . To declare an array.

Alignment is specified using an optional .Chapter 5.const . The default alignment for scalar and array variables is to a multiple of the base-type size.align byte-count specifier immediately following the state-space specifier. %r99 This shorthand syntax may be used with any of the fundamental types and with any state space. it is quite common for a compiler frontend to generate a large number of register names. Parameterized Variable Names Since PTX supports virtual registers. not for individual elements.6.5.0.0}. and may be preceded by an alignment specifier.. These 100 register variables can be declared as follows: .0. 5.2. 2010 39 .0. of . Elements are bytes. // declare %r0. The default alignment for vector variables is to a multiple of the overall vector size. . The variable will be aligned to an address which is an integer multiple of byte-count.b8 bar[8] = {0.4.0. Array variables cannot be declared this way. say one hundred.b32 %r<100>. %r1. %r99. and Variables 5.. For arrays. .b32 variables.4. suppose a program uses a large number. Types.reg . Alignment Byte alignment of storage for all addressable variables can be specified in the variable declaration. %r1. alignment specifies the address alignment for the starting address of the entire array. Examples: // allocate array at 4-byte aligned address..align 4 .0. Note that all PTX instructions that access memory require that the address be aligned to a multiple of the transfer size. named %r0. Rather than require explicit declaration of every name. State Spaces. January 24. nor are initializers permitted. PTX supports a syntax for creating a set of variables having a common prefix string appended with integer suffixes. For example. ….

2010 .PTX ISA Version 2.0 40 January 24.

mov. The bit-size type is compatible with every type having the same size. and cvt instructions copy data from one location to another. Most instructions have an optional predicate guard that controls conditional execution. January 24. Each operand type must be compatible with the type determined by the instruction template and instruction type. and c.3. Operands having type different from but compatible with the instruction type are silently cast to the instruction type. . For most operations. PTX describes a load-store machine.reg register state space. The cvt (convert) instruction takes a variety of operand types and sizes.1. and a few instructions have additional predicate source operands. Destination Operands PTX instructions that produce a single result store the result in the field denoted by d (for destination) in the instruction descriptions. st. Integer types of a common size are compatible with each other. Instructions ld and st move data from/to addressable state spaces to/from registers. s.2. 6. The mov instruction copies data between registers. The result operand is a scalar or vector variable in the register state space. r. 6. Source Operands The source operands are denoted in the instruction descriptions by the names a. Instruction Operands 6. The ld. as its job is to convert from nearly any data type to any other data type (and size). 2010 41 . There is no automatic conversion between types. the sizes of the operands must be consistent.Chapter 6. Predicate operands are denoted by the names p. q. Operand Type Information All operands in instructions have a known type from their declarations. b. so operands for ALU instructions must all be in variables declared in the .

q. . there is no support for C-style pointer arithmetic. Address expressions include variable names.f32 ld.u16 r0.v4 .f32 W. The syntax is similar to that used in many assembly languages. Arrays.0 6.[x]. 6. address registers. . Examples include pointer arithmetic and pointer comparisons.shared.s32 mov.b32 p.shared . All addresses and address computations are byte-based. The address is an offset in the state space in which the variable is declared. . Here are a few examples: .reg .reg . .u16 ld.1. [tbl+12]. r0. .4. and vectors. Load and store operations move data between registers and locations in addressable state spaces. ld.v4.gloal. and Vectors Using scalar variables as operands is straightforward.4.s32 q. and immediate address expressions which evaluate at compile-time to a constant address.const.u16 x. The mov instruction can be used to move the address of a variable into a pointer.reg . [V].const .s32 tbl[256]. where scalar variables are simply named and addresses are de-referenced by enclosing the address expression in square brackets.PTX ISA Version 2.u32 42 January 24.f32 V. The interesting capabilities begin with addresses. 2010 . address register plus byte offset. Addresses as Operands Address arithmetic is performed using integer arithmetic and logical instructions. tbl. W.v4 . Using Addresses.reg .global . . arrays. p.

st.x V. The registers in the load/store operations can be a vector.u32 s. ld. a[0]. A brace-enclosed list is used for pattern matching to pull apart vectors.x. or by indexing into the array using square-bracket notation. d.4.4. Examples are ld.global.z V. c. V2.f32 a. .u32 s. and tex. say {Ra.2. V. Vectors may also be passed as arguments to called functions. .d}.3.f32 {a. as well as the typical color fields . [addr+offset]. ld.global. where the offset is a constant expression that is either added or subtracted from a register variable.4. If more complicated indexing is desired. Vector loads and stores can be used to implement wide loads and stores.y V.w.global. Rc.v4.v4 . 2010 43 .b and . Here are examples: ld. [addr+offset2]. and the identifier becomes an address constant in the space where the array is declared.b.b.f32 ld.d}. or a braceenclosed list of similarly typed scalars. mov. The size of the array is a constant in the program.g. which include mov.c.v4. The expression within square brackets is either a constant integer.reg .v2. Rd}.4.u32 s. a[N-1]. for use in an indirect branch or call.y. it must be written as an address calculation prior to use.a. a[1].c.Chapter 6.u32 {a. mov.f32 V. January 24. Elements in a brace-enclosed vector. .z and . and in move instructions to get the address of the label or function into a register. . Rb. Vector elements can be extracted from the vector with the suffixes . which may improve memory performance.r V. .g V. .global. a register variable. Labels and Function Names as Operands Labels and function names can be used only in branch and call instructions. or a simple “register with constant offset” expression. b.b V.r. Instruction Operands 6.a 6.reg . Vectors as Operands Vector operands are supported by a limited subset of instructions.w = = = = V. Arrays as Operands Arrays of all types can be declared. // move address of a[1] into s 6. correspond to extracted elements as follows: Ra Rb Rc Rd = = = = V. Array elements can be accessed using an explicitly calculated byte address.

000 for f16).s32. Operands of different sizes or types must be converted prior to the operation. Scalar Conversions Table 6 shows what precision and format the cvt instruction uses given operands of differing types. the u16 is zero-extended to s32.u16 instruction is given a u16 source operand and s32 as a destination operand.5. 6.0 6. except for operations where changing the size and/or type is part of the definition of the instruction. Type Conversion All operands to all arithmetic. For example. if a cvt. Conversions to floating-point that are beyond the range of floating-point numbers are represented with the maximum floating-point value (IEEE 754 Inf for f32 and f64.1. 2010 . and ~131. logic. and data movement instruction must be of the same type and size.5.PTX ISA Version 2. 44 January 24.

January 24. f2f = float-to-float.Chapter 6. For example. then sign-extend to 32-bits. s2f = signed-to-float.u32 targeting a 32-bit register will first chop to 16-bits. u2f = unsigned-to-float. Instruction Operands Table 11. cvt. Notes 1 If the destination register is wider than the destination format. chop = keep only low bits that fit. f2s = float-to-signed.s16. s8 s8 s16 s32 s64 Source Format u8 u16 u32 u64 f16 f32 f64 chop chop chop - Convert Instruction Precision and Format Destination Format s16 sext 1 1 1 s32 sext sext 1 1 s64 sext sext sext zext zext zext f2s f2s f2s u8 chop chop 1 1 1 u16 sext chop chop zext chop chop f2u f2u f2u 1 1 1 1 u32 sext sext chop zext zext chop f2u f2u f2u u64 sext sext sext zext zext zext f2u f2u f2u f16 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f32 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f f64 s2f s2f s2f s2f u2f u2f u2f u2f f2f f2f - chop chop zext chop chop f2s f2s f2s 1 1 chop zext zext chop f2s f2s f2s chop - chop1 chop chop f2s f2s f2s 1 1 chop1 chop chop f2u f2u f2u 1 1 sext = sign extend. 2010 45 . f2u = float-to-unsigned. the result is extended to the destination register width after chopping. The type of extension (sign or zero) is based on the destination format. zext = zero-extend.

rm . In PTX.0 6.2.PTX ISA Version 2. round to nearest integer in the direction of zero round to nearest integer in direction of negative infinity round to nearest integer in direction of positive infinity 46 January 24.5. there are four integer rounding modifiers and four floating-point rounding modifiers.rz . choosing even integer if source is equidistant between two integers. Modifier . Table 12. 2010 .rzi .rp Floating-Point Rounding Modifiers Description mantissa LSB rounds to nearest even mantissa LSB rounds towards zero mantissa LSB rounds towards negative infinity mantissa LSB rounds towards positive infinity Table 13.rmi .rn .rni . Modifier .rpi Integer Rounding Modifiers Description round to nearest integer. The following tables summarize the rounding modifiers. Rounding Modifiers Conversion instructions may specify a rounding modifier.

2010 47 . The first is to have multiple threads of execution so that the hardware can issue a memory operation and then switch to other execution. The register in a store operation is available much more quickly. Much of the delay to memory can be hidden in a number of ways. Table 11 gives estimates of the costs of using different kinds of memory.Chapter 6. as execution is not blocked until the desired result is used in a subsequent (in time) instruction. first access is high Notes January 24. Table 14. Space Register Shared Constant Local Parameter Immediate Global Texture Surface Cost Estimates for Accessing State-Spaces Time 0 0 0 > 100 clocks 0 0 > 100 clocks > 100 clocks > 100 clocks Amortized cost is low. Another way to hide latency is to issue the load instructions as early as possible. Instruction Operands 6. Registers are fastest. Operand Costs Operands from different state spaces affect the speed of an operation.6. while global memory is slowest.

PTX ISA Version 2.0 48 January 24. 2010 .

1. together these specify the function’s interface. A function definition specifies both the interface and the body of the function. and is represented in PTX as follows: . so recursion is not yet supported. and an optional list of input parameters. support for variadic functions (“varargs”). The arguments and return variables at the call must have type and size that match the callee’s corresponding formal parameters. In this section. These include syntax for function definitions. A function must be declared or defined prior to being called. A function declaration specifies an optional list of return parameters. Execution of the ret instruction within foo transfers control to the instruction following the call. function calls. we describe the features of PTX needed to achieve this hiding of the ABI. and return values may be placed directly into register variables. The simplest function has no parameters or return values. 7. and memory allocated on the stack (“alloca”). } … call foo. 2010 49 .func foo { … ret. implicitly saving the return address. … Here.func directive. Abstracting the ABI Rather than expose details of a particular calling convention. parameter passing. NOTE: The current version of PTX does not implement the underlying. the function name. stack-based ABI. functions are declared and defined using the . arguments may be register variables or constants. or prototype.Chapter 7. PTX provides a slightly higher-level abstraction and supports multiple ABI implementations. Scalar and vector base-type input and return parameters may be represented simply as register variables. stack layout. January 24. and Application Binary Interface (ABI). execution of the call instruction transfers control to foo. At the call. Function declarations and definitions In PTX.

b32 c1. byte array in . } { .f1. }. c2.reg .param.PTX ISA Version 2. a . st.param. … In this example. note that . this structure will be flattened into a byte array. [y+11].func (. a .param. ld. Since memory accesses are required to be aligned to a multiple of the access size.param state space is used to pass the structure by value: . the structure in this example will be a 12 byte array with 8 byte alignment so that accesses to the .s32 out) bar (.reg .reg . … ld.f64 f1.param space memory.reg space. … … // computation using x. First.param . [y+0].reg .param.s32 x. [y+8]. ld.param . bumpptr.b64 [py+ 0]. Second.b8 c3. . (%x.reg .b8 [py+ 9]. %rd.u32 %ptr.c3. %rc2. %rc2. [y+10].u32 %res.u32 %res) inc_ptr ( . In PTX.param.c4.b8 [py+10]. %ptr.b8 [py+11].param. . 50 January 24.b8 c1. } … call (%r1). %rc1.b8 . c3. (%r1. st.func (. %inc.u32 %inc ) { add. For example. The .b8 [py+ 8]. st. … st. // scalar args in .param variable y is used in function definition bar to represent a formal parameter.align 8 y[12]) { .reg . st. ld.param.c2.param.param.f64 field are aligned. [y+9].b8 . 2010 . %rc1.b8 c2. . ld.param space variables are used in two ways.c1.4).align 8 py[12].param.reg . … Objects such as C structures and unions are flattened into registers or byte arrays in PTX and are represented using . passed by value to a function: struct { double dbl. c4.f64 f1. consider the following C structure.0 Example: .param space call (%out).b8 c4. py).param variable py is declared in the body of the calling function and used to set up the structure being passed to bar. inc_ptr. ret. char c[4].

param space formal parameters that are base-type scalar or vector variables. or a constant that can be represented in the type of the formal parameter. The . and alignment of parameters. In the case of .param arguments. The following restrictions apply to parameter passing. and alignment. • The . Abstracting the ABI The following is a conceptual way to think about the .Chapter 7.param space formal parameters that are byte arrays.reg space variable with matching type and size.param variables.reg variables. A .param or .param byte array is used to collect together fields of a structure being passed by value. or a constant that can be represented in the type of the formal parameter.param variable simply allows a mapping to be made at the call site between data that may be in multiple locations (e.param space byte array with matching type.param memory must be aligned to a multiple of 1. size. or 16 bytes. For a callee. The mapping of parameters to physical registers and stack locations depends on the ABI definition and the order. January 24. • • Arguments may be . . the corresponding argument may be either a . 2. 8. structure being manipulated by caller is located in registers and memory) to something that can be passed as a parameter or return value to the callee. the corresponding argument may be either a .reg space variable of matching type and size. or constants. • The .reg or . Note that the choice of . For a caller. This enables backend optimization and ensures that the .param state space use in device functions.reg variables.param or .g.param instructions used for argument passing must be contained in the basic block with the call instruction.param variables or .reg space formal parameters. The .param argument must be declared within the local scope of the caller.param and ld. In the case of .param variable does not consume extra space in the caller’s frame beyond that needed by the ABI.param state space is used to receive parameter values and/or pass return values back to the caller.reg state space in this way provides legacy support. the argument must also be a .param state space for parameter passing has no impact on whether the parameter is ultimately passed in physical registers or on the stack.param state space is used to set values that will passed to a called function and/or to receive return values from a called function. For . • • • Input and return parameters may be . a . Supporting the . size.reg state space can be used to receive and return base-type scalar and vector values. 4. 2010 51 . all st. In the case of . Parameters in . Typically. For a caller.. • • • For a callee.

52 January 24.0. PTX 1.param byte array should be used to return objects that do not fit into a register.reg state space. Objects such as C structures were flattened and passed or returned using multiple registers.1. In PTX ISA version 2. and a . and .PTX ISA Version 2.reg or . For sm_2x targets.0 restricts functions to a single return value.0 7.param state space. formal parameters were restricted to .x In PTX ISA version 1. Changes from PTX 1. 2010 . PTX 2. formal parameters may be in either .1. and there was no support for array parameters.x supports multiple return values for this purpose. PTX 2.x.0 continues to support multiple return registers for sm_1x targets.param space parameters support arrays.

4).reg .reg .reg . 2010 53 . %r1.u32. 2.u32 ptr) %va_start .func okay ( … ) Built-in functions are provided to initialize. and end access to a list of variable arguments. %va_start.Chapter 7. iteratively access.reg . call (ap). the alignment may be 1. … ) .reg . or 16 bytes. val.u32 a.ge p. . Abstracting the ABI 7. For %va_arg. %r2. mov.u32 N.u32 ptr) a handle to whatever structure is used by the ABI to support variable argument lists. ctr. ) { . 0x8000000.2.u32 b. … call (%max). 2. or 8 bytes.h and varargs.reg .u32 align) . The function prototypes are defined as follows: . 4. 4. ret.reg . . call (val). (2. Variadic functions NOTE: The current version of PTX does not support variadic functions.b32 val) %va_arg (.func %va_end (.u32 sz. . %va_arg.. call %va_end. (3. .u32 sz.s32 result ) maxN ( . maxN. for %va_arg64.pred p.reg .reg .reg .reg . (ap). (ap. PTX provides a high-level mechanism similar to the one provided by the stdarg. . … %va_start returns Loop: @p Done: January 24. bra Loop. %s2). N.h headers in C. or 4 bytes.u32 ptr. Once all arguments have been processed.b64 val) %va_arg64 (.func (.reg .reg . 0. along with the size and alignment of the next data value to be accessed.func baz ( . result.b32 result.s32 result. In both cases. To support functions with a variable number of arguments. %s1.u32 align) . the size may be 1. max. Here’s an example PTX program using the built-in functions to support a variable number of arguments: // compute max over N signed integers .reg . 4. . In PTX. %r3). maxN. the size may be 1.u32 ptr.func ( . %va_end is called to free the variable argument list handle. bra Done. 2. This handle is then passed to the %va_arg and %va_arg64 built-in functions.b32 ctr..s32 val.func (.reg . setp. following zero or more fixed parameters: .reg . .func (. 8. ctr. . } … call (%max).reg . // default to MININT mov.u32 ap. variadic functions are declared with an ellipsis at the end of the input parameter list.

0 7.func ( . it is the responsibility of the user program to allocate additional space and adjust the base pointer to achieve the desired alignment. defined as follows: . If a particular alignment is required. a function simply calls the built-in function %alloca.PTX ISA Version 2. The built-in %alloca function is guaranteed only to return a 4-byte aligned pointer.local and st. 2010 . Alloca NOTE: The current version of PTX does not support alloca. The array is then accessed with ld.reg .local instructions. 54 January 24.u32 ptr ) %alloca ( . To allocate memory.reg .3.u32 size ) The resulting pointer is to the base address in local memory of the allocated memory. PTX provides another built-in function for allocating storage at runtime on the per-thread local memory stack.

January 24. opcode D. setp.1. q = !(a < b). B. The setp instruction writes two destination registers. PTX Instructions PTX instructions generally have from zero to four operands. In addition to the name and the format of the instruction.s32.2. opcode D. 2010 55 . followed by some examples that attempt to show several possible instantiations of the instruction. and C are the source operands. opcode D.Chapter 8. A “bit bucket” operand denoted with an underscore (‘_’) may be used in place of a destination register. opcode A. Instruction Set 8. A. a. 8. b. B. C.lt p|q. A. Format and Semantics of Instruction Descriptions This section describes each PTX instruction. For instructions that create a result value. plus an optional guard predicate appearing after an ‘@’ symbol to the left of the opcode: @P @P @P @P @P opcode. We use a ‘|’ symbol to separate multiple destination registers. For some instructions the destination operand is optional. the semantics are described. while A. the D operand is the destination operand. A. // p = (a < b). B.

add 1 to j To get a conditional branch or conditional function call.s32 j.s32 p. r All instructions have an optional “guard predicate” which controls conditional execution of the instruction. use a predicate to control the execution of the branch or call instructions.s32 p. // p = (i < n) // if i < n. As an example. optionally negated.pred p. add. q. predicate registers are virtual and have . n. … // compare i to n // if false.PTX ISA Version 2. branch over 56 January 24.reg . Predicates are most commonly set as the result of a comparison performed by the setp instruction. the following PTX instruction sequence might be used: @!p L1: setp. 2010 . predicate registers can be declared as .pred as the type specifier. consider the high-level code if (i < n) j = j + 1. This can be written in PTX as @p setp. j. j. where p is a predicate variable.0 8.3. 1.s32 j. Instructions without a guard predicate are executed unconditionally. The syntax to specify conditional execution is to prefix an instruction with “@{!}p”. bra L1.lt.lt. To implement the above example as a true conditional branch. n. 1. i. Predicated Execution In PTX. add. i. So.

ne (not-equal).1.1. ne. le (less-than-or-equal). Table 15. and BitSize Types Signed Operator EQ NE LT LE GT GE Unsigned Operator EQ NE LO LS HI HS Bit-Size Operator EQ NE 8. Meaning a == b a != b a<b a <= b a>b a >= b Operators for Signed Integer. the result is false.Chapter 8.2. The following table shows the operators for signed integer. 2010 57 . If either operand is NaN. hi (higher). The unsigned comparisons are eq. Instruction Set 8. and hs (higher-or-same). le. ls (lower-or-same).3. Meaning a == b && !isNaN(a) && !isNaN(b) a != b && !isNaN(a) && !isNaN(b) a < b && !isNaN(a) && !isNaN(b) a <= b && !isNaN(a) && !isNaN(b) a > b && !isNaN(a) && !isNaN(b) a >= b && !isNaN(a) && !isNaN(b) January 24. The bit-size comparisons are eq and ne. and bitsize types. Unsigned Integer.3.3. ge. ordering comparisons are not defined for bit-size types. lt.1. lt (less-than). Floating-Point Comparisons Floating-Point Comparison Operators Floating-Point Operator EQ NE LT LE GT GE The ordered comparisons are eq. and ge (greater-than-or-equal). Integer and Bit-Size Comparisons The signed integer comparisons are the traditional eq (equal). lo (lower). unsigned integer. gt (greater-than). gt. ne. Table 16. Comparisons 8.1.

2. and nan returns true if either operand is NaN.0 To aid comparison operations in the presence of NaN values. If both operands are numeric values (not NaN). Table 18. If either operand is NaN. xor. not. then the result of these comparisons is true. gtu.0. Table 17. and no direct way to load or store predicate register values.1. Meaning Floating-Point Comparison Operators Accepting NaN Floating-Point Operator EQU NEU LTU LEU GTU GEU a == b || isNaN(a) || isNaN(b) a != b || isNaN(a) || isNaN(b) a < b || isNaN(a) || isNaN(b) a <= b || isNaN(a) || isNaN(b) a > b || isNaN(a) || isNaN(b) a >= b || isNaN(a) || isNaN(b) To test for NaN values. two operators num (numeric) and nan (isNaN) are provided.PTX ISA Version 2. setp can be used to generate a predicate from an integer. Meaning Floating-Point Comparison Operators Testing for NaN Floating-Point Operator NUM NAN !isNaN(a) && !isNaN(b) isNaN(a) || isNaN(b) 8. num returns true if both operands are numeric values (not NaN). and mov. However. unordered versions are included: equ. // convert predicate to 32-bit value 58 January 24. Manipulating Predicates Predicate values may be computed and manipulated using the following instructions: and.3. neu. geu. or.u32 %r1. leu. There is no direct conversion between predicates and integer values. ltu. for example: selp. then these comparisons have the same result as their ordered counterparts. and the predicate-based select (selp) instruction can be used to generate an integer value based on the value of a predicate.%p. 2010 .

2010 59 . add.f32 d. It requires separate type-size modifiers for the result and source. Instruction Set 8. For example. and integer operands are silently cast to the instruction type if needed. a. .uX ok ok ok inv . The rules for operand and instruction type conformance are as follows: • • Bit-size types agree with any type of the same size. For example. cvt.reg .f32. Floating-point types agree only if they have the same size. Table 19.reg .sX ok ok ok inv . Type Information for Instructions and Operands Typed instructions must have a type-size modifier.u16 d.uX . // perform a 16-bit unsigned add Some instructions require multiple type-size modifiers. b. b.fX ok inv inv ok Instruction Type . an unsigned integer operand used in a signed integer instruction will be treated as a signed integer by the instruction.reg . unsigned.bX .u16 a.4.u16 d.e. i. a. For example: . a..sX . • The following table summarizes these type checking rules. different sizes). Example: .Chapter 8. float.fX ok ok ok ok January 24. they must match exactly. and this information must be specified as a suffix to the opcode. most notably the data conversion instruction cvt. Signed and unsigned integer types agree provided they have the same size. Type Checking Rules Operand Type .u16 d. and these are placed in the same order as the operands.bX . the add instruction requires type and size information to properly perform the addition operation (signed. // convert 16-bit unsigned to 32-bit float Each operand’s type must agree with the corresponding instruction-type modifier.

stored. Integer source registers may be used with any appropriately-sized bit-size or integer instruction type.4. When a source operand has a size that exceeds the instruction-type size. unless the operand is of bit-size type. 1. so those rows are invalid for cvt. 2. Operand Size Exceeding Instruction-Type Size For convenience. parse error. When used with a floating-point instruction type. Floating-point source registers can only be used with bit-size or floating-point instruction types. 2010 . for example. ld. the size must match exactly. st. Notes 3. the source data is truncated (“chopped”) to the appropriate number of bits specified by the instruction typesize. The data is truncated to the instruction-type size and interpreted according to the instruction type.PTX ISA Version 2. “-“ = allowed.1. so that narrow values may be loaded. 60 January 24.0 8. When used with a narrower bit-size type. the cvt instruction does not support . Bit-size source registers may be used with any appropriately-sized instruction type. For example. no conversion needed. stored. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 chop inv inv chop inv inv chop inv inv inv inv b32 Relaxed Type-checking Rules for Source Operands Source Operand Type b64 chop chop chop chop chop chop chop chop chop chop chop s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 chop inv inv chop inv inv chop inv inv inv inv inv s32 chop chop inv chop chop inv chop chop inv inv inv inv s64 chop chop chop chop chop chop chop chop chop inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 chop inv inv chop inv inv chop inv inv inv inv inv u32 chop chop inv chop chop inv chop chop inv inv inv inv u64 chop chop chop chop chop chop chop chop chop inv inv inv f16 chop inv inv inv inv inv inv inv inv inv inv inv inv f32 chop chop inv inv inv inv inv inv inv inv inv inv inv f64 chop chop chop inv inv inv inv inv inv inv inv inv inv - chop chop inv chop chop inv chop chop inv chop inv chop = keep only low bits that fit. and cvt instructions permit source and destination data operands to be wider than the instruction-type size. 4. or converted to other types and sizes. The operand type checking rules are relaxed for bit-size and integer (signed and unsigned) instruction types. Table 20.bX instruction types. Source register size must be of equal or greater size than the instruction-type size. floating-point instruction types still require that the operand type-size matches exactly. the data will be truncated. and converted using regular-width registers. 8-bit or 16-bit values may be held directly in 32-bit or 64-bit registers when being loaded. The data is truncated (“chopped”) to the instruction-type size and interpreted according to the instruction type. Note that some combinations may still be invalid for a particular instruction. The following table summarizes the relaxed type-checking rules for source operands. inv = invalid.

Destination register size must be of equal or greater size than the instruction-type size. Bit-size destination registers may be used with any appropriately-sized instruction type. the data will be zero-extended. 2010 61 . Table 21. Floating-point destination registers can only be used with bit-size or floating-point instruction types.Chapter 8. the data is sign-extended. January 24. The data is signextended to the destination register width for signed integer instruction types. Notes 3. zext = zero-extend. otherwise. The data is sign-extended to the destination register width for signed integer instruction types. If the corresponding instruction type is signed integer. the data is zeroextended. When used with a floatingpoint instruction type. inv = Invalid. 4. parse error. When used with a narrower bit-size instruction type. 1. Integer destination registers may be used with any appropriately-sized bit-size or integer instruction type. and is zero-extended to the destination register width otherwise. the size must match exactly. b8 b8 b16 b32 b64 s8 Instruction Type s16 s32 s64 u8 u16 u32 u64 f16 f32 f64 inv inv inv inv inv inv inv inv inv inv inv inv b16 zext inv inv sext inv inv zext inv inv inv inv b32 Relaxed Type-checking Rules for Destination Operands Destination Operand Type b64 zext zext zext sext sext sext zext zext zext zext zext s8 inv inv inv inv inv inv inv inv inv inv inv inv s16 zext inv inv sext inv inv zext inv inv inv inv inv s32 zext zext inv sext sext inv zext zext inv inv inv inv s64 zext zext zext sext sext sext zext zext zext inv inv inv u8 inv inv inv inv inv inv inv inv inv inv inv inv u16 zext inv inv sext inv inv zext inv inv inv inv inv u32 zext zext inv sext sext inv zext zext inv inv inv inv u64 zext zext zext sext sext sext zext zext zext inv inv inv f16 zext inv inv inv inv inv inv inv inv inv inv inv inv f32 zext zext inv inv inv inv inv inv inv inv inv inv inv f64 zext zext zext inv inv inv inv inv inv inv inv inv inv - zext zext inv sext sext inv zext zext inv zext inv sext = sign extend. 2. and is zeroextended to the destination register width for bit-size and unsigned integer instruction types. The following table summarizes the relaxed type-checking rules for destination operands. the destination data is zero. “-“ = Allowed but no conversion needed.or sign-extended to the size of the destination register. Instruction Set When a destination operand has a size that exceeds the instruction-type size.

1. A compiler or programmer may chose to enforce portable. 62 January 24. until C is not expressive enough. the optimizing code generator automatically determines points of re-convergence. Therefore. All control constructs are assumed to be divergent points unless the control-flow instruction is marked as uniform. If all of the threads act in unison and follow a single control flow path. 16-bit registers in PTX are mapped to 32-bit physical registers. These extra precision bits can become visible at the application level. at least in appearance. a compiler or code author targeting PTX can ignore the issue of divergent threads. Semantics The goal of the semantic description of an instruction is to describe the results in all cases in as simple language as possible. At the PTX language level.PTX ISA Version 2. 2010 .6. since the translated code would require many additional masking instructions to suppress extra precision bits in the highorder half-word of 32-bit registers. This approach introduces a performance penalty for 16-bit code executing on a 32-bit data path.5.0 8. the threads are called divergent. by a right-shift instruction. A CTA with divergent threads may have lower performance than a CTA with uniformly executing threads. Rather than introduce a performance penalty for 16-bit code running on 32-bit GPUs. When executing on a 32-bit data path. 8. For divergent control flow. 8. so it is important to have divergent threads re-converge as soon as possible. the threads are called uniform. since the “promoted” computation may have bits in the high-order half-word of registers that are not present in 16-bit physical registers. using the . conditional function call. Both situations occur often in programs. Machine-Specific Semantics of 16-bit Code A PTX program may execute on a GPU with either a 16-bit or a 32-bit data path.6. but has the opportunity to improve performance by marking branch points as uniform when the compiler or author can guarantee that the branch point is non-divergent. and 16-bit computations are “promoted” to 32-bit computations. this is not desirable. one solution would be to define semantics for 16-bit code that is consistent with execution on a 16-bit data path. Divergence of Threads in Control Constructs Threads in a CTA execute together. the semantics of 16-bit instructions in PTX is machine-specific. and for many applications the difference in execution is preferable to limiting performance. for many performance-critical applications. If threads execute down different control flow paths. machine-independent 16-bit semantics by adding explicit conversions to 16-bit values at appropriate points in the program to guarantee portability of the code. However. This can lead to computational differences between code run on a 16-bit machine versus the same code run on a 32-bit machine. The semantics are described using C. until they come to a conditional control construct such as a conditional branch. or conditional return. for example.uni suffix.

8. 2010 63 . Instruction Set 8. The Integer arithmetic instructions are: add sub add.7. Instructions All PTX instructions may be predicated.7.cc. the optional guard predicate is omitted from the syntax.Chapter 8. In the following descriptions. Integer Arithmetic Instructions Integer arithmetic instructions operate on the integer types in register and constant immediate forms.cc. addc sub. subc mul mad mul24 mad24 sad div rem abs neg min max popc clz bfind brev bfe bfi prmt January 24.1.

s32 c.0 Table 22.s32.b.s16.sat applies only to .s32 type.s32 c. . d = a – b.y. sub. Description Semantics Notes Performs addition and writes the resulting value into a destination register.type sub{.z.u32.0.sat.u64. PTX ISA Notes Target ISA Notes Examples Table 23. // . @p add. Introduced in PTX ISA version 1.s32 . . . . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. 2010 . d. d. Saturation modifier: . . Saturation modifier: . Supported on all target architectures.u16.MAXINT (no overflow) for the size of the operation.s64 }. d = a + b.MAXINT (no overflow) for the size of the operation.s32. a.s32 d. .s32 . b. // . a. Introduced in PTX ISA version 1. . add Syntax Integer Arithmetic Instructions: add Add two values. b.a. Supported on all target architectures.1.sat limits result to MININT. .sat limits result to MININT.type = { . add.sat}.s32 type.s32 d. a. b. sub Syntax Integer Arithmetic Instructions: sub Subtract one value from another..type add{.u16.s64 }. sub. PTX ISA Notes Target ISA Notes Examples 64 January 24. Applies only to . Applies only to . b.u64.0. a.sat applies only to .PTX ISA Version 2. add.u32.s16. .u32 x.type = { .c.sat}. ..

cc and subc reference an implicitly specified condition code register (CC) having a single carry flag bit (CC. clearing. No saturation.cc Add two values with carry-out. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 25. b. @p @p @p @p add. Behavior is the same for unsigned and signed integers.cc.s32 }. x3.y4. add.u32.cc.z1. sub.y1.y4. Description Semantics Notes Performs 32-bit integer addition and writes the carry-out value into the condition code register. Supported on all target architectures.cc.z4.type d.cc specified. Introduced in PTX ISA version 1.b32 addc.b32 addc.z3.2. Behavior is the same for unsigned and signed integers. carry-out written to CC.cc Syntax Integer Arithmetic Instructions: add.y1.u32. d = a + b + CC.cc}. The condition code register is not preserved across branches or calls and therefore should only be used in straight-line code sequences for computing extended-precision integer addition and subtraction. add. . These instructions support extended-precision integer addition and subtraction.cc. No other instructions access the condition code. x4. addc Syntax Integer Arithmetic Instructions: addc Add two values with carry-in and optional carry-out. if .Chapter 8. Description Semantics Notes Performs 32-bit integer addition with carry-in and optionally writes the carry-out value into the condition code register.cc.z2. x2. @p @p @p @p add. Table 24. .CF No integer rounding modifiers. x4.y2.y2.type = {.type = { . x3.b32 addc.cc. addc{.CF. d = a + b.y3. // extended-precision addition of // two 128-bit values PTX ISA Notes Target ISA Notes Examples January 24.z1.cc.cc.s32 }.b32 addc.z3.CF No integer rounding modifiers. 2010 65 .z4.2.b32 addc. Introduced in PTX ISA version 1. No saturation.cc.b32 x1. x2. carry-out written to CC. addc.CF) holding carry-in/carry-out or borrowin/borrow-out.b32 addc.type d. a.y3. . Instruction Set Instructions add.b32 x1. b. and there is no support for setting. .z2. or testing the condition code. a. Supported on all target architectures.cc.

sub.3.CF No integer rounding modifiers. No saturation. d = a – b.b32 x1. Description Semantics Notes Performs 32-bit integer subtraction with borrow-in and optionally writes the borrow-out value into the condition code register. withborrow-in and optional borrow-out.u32. .cc. with borrow-out. No saturation. .b32 subc. a.y3. Description Semantics Notes Performs 32-bit integer subtraction and writes the borrow-out value into the condition code register.y1.type = {. 2010 .type d.cc.y3.b32 subc. d = a . x2. // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples Table 27.CF). // extended-precision subtraction // of two 128-bit values PTX ISA Notes Target ISA Notes Examples 66 January 24.0 Table 26.y4. Supported on all target architectures. sub. Introduced in PTX ISA version 1.z4. Behavior is the same for unsigned and signed integers.PTX ISA Version 2.cc. subc Syntax Integer Arithmetic Instructions: subc Subtract one value from another.(b + CC. x4. Behavior is the same for unsigned and signed integers.cc.s32 }. .y2.z3.cc.b32 subc.cc.y2.b32 subc. x3.z1.y4.cc}.type d. b. borrow-out written to CC.b32 x1.z2. x2.3.b32 subc.cc.b32 subc. @p @p @p @p sub. Introduced in PTX ISA version 1.CF No integer rounding modifiers. x4. @p @p @p @p sub.cc.cc Syntax Integer Arithmetic Instructions: sub.u32. borrow-out written to CC. a. . Supported on all target architectures.z4.y1.z2.cc specified. subc{. x3.z1. if . b.s32 }.type = { .z3.cc.cc Subract one value from another.

mul. save only the low 16 bits // 32*32 bits. // 16*16 bits yields 32 bits // 16*16 bits.fys.x..Chapter 8.0.wide is specified.wide suffix is supported only for 16.s64 }. and either the upper or lower half of the result is written to the destination register.lo variant Notes The type of the operation represents the types of the a and b operands.hi or .type d.fxs.u32. d = t<2n-1.hi.lo.u16. .s16 fa. If . . . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. If . then d is twice as wide as a and b to receive the full result of the multiplication.hi variant // for . .. d = t<n-1..lo.lo is specified. . d = t.y. a.wide.. Description Semantics Compute the product of two values. mul{. mul.u64.0>.fys. // for .s16 fa.type = { . n = bitwidth of type.wide}.fxs. b.wide // for .wide. mul Syntax Integer Arithmetic Instructions: mul Multiply two values.s32 z. 2010 67 .s16. creates 64 bit result January 24.and 32-bit integer types.s32. mul. Supported on all target architectures. The . Instruction Set Table 28.n>. then d is the same size as a and b. t = a * b. .

0> + c.sat limits result to MININT. ..s32 r. bitwidth of type. mad. t<2n-1. a.s32 d. Supported on all target architectures.s16. c.a. b.wide suffix is supported only for 16.PTX ISA Version 2. c.0. 68 January 24.s32 type in . If .type mad. If .q.0 Table 29. t<n-1..hi or .c. t + c. t n d d d = = = = = a * b. Saturation modifier: .type = { . then d and c are twice as wide as a and b to receive the result of the multiplication. and then writes the resulting value into a destination register.lo.s32 d.u64. d.lo variant Notes The type of the operation represents the types of the a and b operands.lo. Applies only to .b.u32.hi variant // for .u16. The .wide // for . a. 2010 . mad Syntax Integer Arithmetic Instructions: mad Multiply two values and add a third value.p.n> + c..r.hi. @p mad. .hi. b.lo.s64 }.lo is specified.s32.and 32-bit integer types. Description Semantics Multiplies two values and adds a third. and either the upper or lower half of the result is written to the destination register. . . mad{.sat.MAXINT (no overflow) for the size of the operation..wide is specified. then d and c are the same size as a and b..hi mode. . // for . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.wide}. .

// low 32-bits of 24x24-bit signed multiply.s32 }. mul24. i. b. mul24.a.hi may be less efficient on machines without hardware support for 24-bit multiply. mul24.Chapter 8. Instruction Set Table 30.0. All operands are of the same type and size. mul24 Syntax Integer Arithmetic Instructions: mul24 Multiply two 24-bit integer values.0>. Description Semantics Compute the product of two 24-bit integer values held in 32-bit source registers. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. 48bits.type = { . // for ..lo}.16>. d = t<47. 2010 69 . d = t<31.hi performs a 24x24-bit multiply and returns the high 32 bits of the 48-bit result.hi variant // for . and return either the high or low 32-bits of the 48-bit result. t = a * b.type d. mul24{. . Supported on all target architectures. mul24.s32 d.b.hi.e. a.lo variant Notes Integer multiplication yields a result that is twice the size of the input operands. ...lo.lo performs a 24x24-bit multiply and returns the low 32 bits of the 48-bit result.u32. January 24.

. 32-bit value to either the high or low 32-bits of the 48-bit result.0> + c. d = t<31. mad24.sat limits result of 32-bit signed addition to MININT.0 Table 31.s32 d.u32.hi. i. Applies only to .16> + c. and add a third.type mad24. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mad24.MAXINT (no overflow). 48bits. d = t<47..0.type = { . Return either the high or low 32-bits of the 48-bit result.c.s32 }. Saturation modifier: . c. mad24.hi may be less efficient on machines without hardware support for 24-bit multiply. mad24. a. . b. a. Supported on all target architectures.lo performs a 24x24-bit multiply and adds the low 32 bits of the 48-bit result to a third value..hi. mad24{.s32 d. Description Compute the product of two 24-bit integer values held in 32-bit source registers.a. // for . .PTX ISA Version 2.lo}.e.hi mode. 2010 . t = a * b.lo.b. 70 January 24. mad24 Syntax Integer Arithmetic Instructions: mad24 Multiply two 24-bit integer values and add a third value. d. b.lo variant Semantics Notes Integer multiplication yields a result that is twice the size of the input operands.sat.hi performs a 24x24-bit multiply and adds the high 32 bits of the 48-bit result to a third value.s32 type in .. // low 32-bits of 24x24-bit signed multiply. All operands are of the same type and size. c.hi variant // for .

Chapter 8. Instruction Set

Table 32.
sad Syntax

Integer Arithmetic Instructions: sad
Sum of absolute differences. sad.type d, a, b, c;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics PTX ISA Notes Target ISA Notes Examples Adds the absolute value of a-b to c and writes the resulting value into a destination register. d = c + ((a<b) ? b-a : a-b); Introduced in PTX ISA version 1.0. Supported on all target architectures. sad.s32 sad.u32 d,a,b,c; d,a,b,d; // running sum

Table 33.
div Syntax

Integer Arithmetic Instructions: div
Divide one value by another. div.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, stores result in d. d = a / b; Division by zero yields an unspecified, machine-specific value. Introduced in PTX ISA version 1.0. Supported on all target architectures. div.s32 b,n,i;

Table 34.
rem Syntax

Integer Arithmetic Instructions: rem
The remainder of integer division. rem.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Divides a by b, store the remainder in d. d = a % b; The behavior for negative numbers is machine-dependent and depends on whether divide rounds towards zero or negative infinity. Introduced in PTX ISA version 1.0. Supported on all target architectures. rem.s32 x,x,8; // x = x%8;

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PTX ISA Version 2.0

Table 35.
abs Syntax

Integer Arithmetic Instructions: abs
Absolute value. abs.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Take the absolute value of a and store it in d. d = |a|; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. abs.s32 r0,a;

Table 36.
neg Syntax

Integer Arithmetic Instructions: neg
Arithmetic negate. neg.type d, a;

.type = { .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Negate the sign of a and store the result in d. d = -a; Only for signed integers. Introduced in PTX ISA version 1.0. Supported on all target architectures. neg.s32 r0,a;

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Chapter 8. Instruction Set

Table 37.
min Syntax

Integer Arithmetic Instructions: min
Find the minimum of two values. min.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples @p Store the minimum of a and b in d. d = (a < b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. min.s32 min.u16 r0,a,b; h,i,j; // Integer (signed and unsigned)

Table 38.
max Syntax

Integer Arithmetic Instructions: max
Find the maximum of two values. max.type d, a, b;

.type = { .u16, .u32, .u64, .s16, .s32, .s64 }; Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Store the maximum of a and b in d. d = (a > b) ? a : b; Signed and unsigned differ. Introduced in PTX ISA version 1.0. Supported on all target architectures. max.u32 max.s32 d,a,b; q,q,0; // Integer (signed and unsigned)

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b32 type. X. d = 0.b64 }. the number of leading zeros is between 0 and 32. a. clz requires sm_20 or later.type d.b32) { max = 32.type d.b64 d. clz Syntax Integer Arithmetic Instructions: clz Count leading zeros. cnt. a. } Introduced in PTX ISA version 2. mask = 0x8000000000000000. inclusively. Description Count the number of leading zeros in a starting with the most-significant bit and place the result in 32-bit destination register d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . while (a != 0) { if (a&0x1) d++. the number of leading zeros is between 0 and 64. inclusively. // cnt is . For . cnt. Description Semantics Count the number of one bits in a and place the resulting ‘population count’ in 32-bit destination register d. if (. d = 0.b32. } else { max = 64. For .u32 Semantics 74 January 24.type = { .type == .0.b32. . 2010 .PTX ISA Version 2. a = a << 1.b32 popc. a = a >> 1. X.b64 }. popc. . mask = 0x80000000. a.0 Table 39.0.b32 clz. popc. popc requires sm_20 or later. } while (d < max && (a&mask == 0) ) { d++.type = { . // cnt is . clz. clz.u32 PTX ISA Notes Target ISA Notes Examples Table 40.b64 d. a.b64 type. . popc Syntax Integer Arithmetic Instructions: popc Population count.

i>=0. a. X.u32.shiftamt is specified. d = -1.type==. For signed integers.type==.d.0. bfind returns the bit position of the most significant “1”.s32) ? 31 : 63. bfind requires sm_20 or later. // cnt is . bfind.s32. . a.u32 d.u64. bfind returns 0xFFFFFFFF if no non-sign bit is found. Semantics msb = (. for (i=msb. . bfind returns the shift amount needed to left-shift the found bit into the most-significant bit position.shiftamt.shiftamt && d != -1) { d = msb .s64 }. 2010 75 . } } if (.Chapter 8.u32 January 24.type bfind. bfind returns the bit position of the most significant “0” for negative inputs and the most significant “1” for non-negative inputs. bfind. Instruction Set Table 41. bfind Syntax Integer Arithmetic Instructions: bfind Find most significant non-sign bit. a. and operand d has type .type = { . i--) { if (a & (1<<i)) { d = i.u32 || . For unsigned integers. break. .u32. . If . Description Find the bit position of the most significant non-sign bit in a and place the result in d.s64 cnt.type d. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Operand a has the instruction type.shiftamt. bfind. d.

b32 d.type==. brev requires sm_20 or later. 2010 .b32) ? 31 : 63. 76 January 24. .PTX ISA Version 2. for (i=0. .type = { . i<=msb. brev. Description Semantics Perform bitwise reversal of input. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. i++) { d[i] = a[msb-i]. a. brev Syntax Integer Arithmetic Instructions: brev Bit reverse.b64 }.b32.0. a.type d. brev.0 Table 42. msb = (.

start. b. the destination d is filled with the replicated sign bit of the extracted field. else sbit = a[min(pos+len-1. if (.u32 || . otherwise If the bit field length is zero.len. If the start position is beyond the msb of the input.u32 || . The destination d is padded with the sign bit of the extracted field. Operands a and d have the same type as the instruction type.type==. . . bfe. for (i=0. bfe requires sm_20 or later. . . Semantics msb = (. . c. and source c gives the bit field length in bits.type = { .s64 }.u32. The sign bit of the extracted field is defined as: .u64.u64 || len==0) sbit = 0.type==. len = c. bfe. January 24. Description Extract bit field from a and place the zero or sign-extended result in d. bfe Syntax Integer Arithmetic Instructions: bfe Bit Field Extract. and operands b and c are type . a.b32 d. pos = b.s64: zero msb of input a if the extracted field extends beyond the msb of a msb of extracted field.u64: . i<=msb.Chapter 8. Instruction Set Table 43.type d. d = 0.type==. 2010 77 .a.s32.u32. Source b gives the bit field starting bit position.s32. the result is zero. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.0.type==. i++) { d[i] = (i<len && pos+i<=msb) ? a[pos+i] : sbit.msb)].u32. .s32) ? 31 : 63.

2010 . for (i=0. b. . and source d gives the bit field length in bits.u32. and place the result in f. pos = c.b. If the start position is beyond the msb of the input. Operands a.0.type f. } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. and operands c and d are type . bfi. b.type==.0 Table 44.b32 d. and f have the same type as the instruction type.b64 }. bfi Syntax Integer Arithmetic Instructions: bfi Bit Field Insert. d. c.b32) ? 31 : 63. Semantics msb = (.a.len. a. If the bit field length is zero. the result is b. bfi requires sm_20 or later.PTX ISA Version 2. bfi. i<len && pos+i<=msb. . 78 January 24.start.type = { . Description Align and insert a bit field from a into b.b32. i++) { f[pos+i] = a[i]. Source c gives the starting bit position for the insertion. len = d. f = b. the result is b.

rc8. c. or if the sign (msb of the byte) should be replicated over all 8 bits of the target position (sign extend of the byte value).b3 source 3 4 5 6 5 6 7 0 0 1 2 3 3 3 3 3 0 1 2 3 1 3 1 3 d. Instruction Set Table 45. The msb defines if the byte value should be copied.f4e.mode = { . a 4-bit selection value is defined. {b3. and reassemble them into a 32-bit destination register. 2010 79 . . .Chapter 8. b0}}.b1 source select c[7:4] d. mode f4e (forward 4 extract) selector c[1:0] 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 d.b4e.b32{.ecl. b.b0 source 0 1 2 3 0 1 2 3 0 1 2 3 0 0 0 0 0 0 0 0 0 2 0 2 b4e (backward 4 extract) rc8 (replicate 8) ecl (edge clamp left) ecr (edge clamp right) rc16 (replicate 16) January 24. the permute control consists of four 4-bit selection values. Thus. as a 16b permute code. Note that the sign extension is only performed as part of generic form. The 3 lsbs of the selection value specify which of the 8 source bytes should be moved into the target position. b4}. msb=1 means replicate the sign. b6.b2 source select c[11:8] d.b1 source 1 2 3 4 7 0 1 2 0 1 2 3 1 1 1 1 0 1 1 1 1 3 1 3 d. In the generic form (no mode specified).b2 source 2 3 4 5 6 7 0 1 0 1 2 3 2 2 2 2 0 1 2 2 0 2 0 2 d. . Description Pick four arbitrary bytes from two 32-bit registers. the four 4-bit values fully specify an arbitrary byte permute.ecr. . b5. default mode index d. The bytes in the two source registers are numbered from 0 to 7: {b.b3 source select c[15:12] d. . b1. prmt. b2.b0 source select c[3:0] The more specialized form of the permute control uses the two lsb's of operand c (which is typically an address pointer) to control the byte extraction. . a} = {{b7. msb=0 means copy the literal value. prmt Syntax Integer Arithmetic Instructions: prmt Permute bytes from register pair. For each byte in the target register. a.mode} d.rc16 }.

ctl[3] = (c >> 12) & 0xf.PTX ISA Version 2. r3. r2. ctl[0]. prmt requires sm_20 or later. } else { ctl[0] = ctl[1] = ctl[2] = ctl[3] = (c >> 0) & 0x3. r3. r2.0. 80 January 24.b32 prmt. // create 8 byte source if ( ! mode ) { ctl[0] = (c >> 0) & 0xf. ctl[3]. ctl[1] = (c >> 4) & 0xf. } tmp[07:00] = ReadByte( mode. ctl[1]. tmp64 ).f4e r1. tmp[23:16] = ReadByte( mode. tmp[15:08] = ReadByte( mode. tmp64 ). ctl[2] = (c >> 8) & 0xf. r1. 2010 . r4. tmp64 ). prmt. ctl[2].0 Semantics tmp64 = (b<<32) | a. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.b32. tmp64 ). r4. tmp[31:24] = ReadByte( mode.

7.f64 register operands and constant immediate values. Floating-Point Instructions Floating-point instructions operate on . Instruction Set 8. 2010 81 . The floating-point instructions are: testp copysign add sub mul fma mad div abs neg min max rcp sqrt rsqrt sin cos lg2 ex2 January 24.Chapter 8.f32 and .2.

with NaNs being flushed to positive zero. NaN payloads are supported for double-precision instructions.f32 n/a n/a n/a n/a n/a n/a n/a n/a mad.rn .PTX ISA Version 2.f32 {abs.ftz .rnd. and mad support saturation of results to the range [0.max}. so PTX programs should not rely on the specific single-precision NaNs being generated.32 and fma.f64 div.f32 {div.sub.min.rnd.f64 {sin.rnd.f32 {mad.approx. default is .approx. {mad.0. {add.sat Notes If no rounding modifier is specified. Double-precision instructions support subnormal inputs and results.rn and instructions may be folded into a multiply-add.max}.rn and instructions may be folded into a multiply-add.mul}.0 The following table summarizes floating-point instructions in PTX. Single-precision instructions support subnormal inputs and results by default for sm_20 targets and flush subnormal inputs and results to sign-preserving zero for sm_1x targets. Instruction Summary of Floating-Point Instructions .0].rnd. default is . . sub.f32 are the same. The optional .fma}.sqrt}.sub.target sm_20 mad.mul}.min. .rm .rp .sqrt}.target sm_20 . 2010 .target sm_20 Instructions that support rounding modifiers are IEEE-754 compliant. 1.lg2.f32 {div.cos.f32 rsqrt.approx. 82 January 24. No rounding modifier.f64 {abs.f32 .fma}.neg. Table 46.rcp.rcp.f64 mad. If no rounding modifier is specified.neg.rnd.ex2}.target sm_1x No rounding modifier. mul.sqrt}.ftz modifier on singleprecision instructions provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.approx.f32 {div.f64 are the same.full.f64 rsqrt.rz .rcp.f64 and fma. Single-precision add. but single-precision instructions return an unspecified NaN. Note that future implementations may support NaN payloads for single-precision instructions.rnd.f32 {add.

type = { . January 24. A.f64 }. Description PTX ISA Notes Target ISA Notes Examples Copy sign bit of a into value of b. copysign. copysign requires sm_20 or later. B.normal.op. positive and negative zero are considered normal numbers. Introduced in PTX ISA version 2.notanumber testp. p.Chapter 8. a.f32 copysign.type . not infinity). .number testp.notanumber. . b. y. // result is . . 2010 83 . testp. X. . C. .f64 x. testp.normal testp.number.subnormal true if the input is not infinite or NaN true if the input is positive or negative infinity true if the input is not NaN true if the input is NaN true if the input is a normal number (not NaN.0. true if the input is a subnormal number (not NaN.type = { . testp requires sm_20 or later.infinite testp.finite. z.0. .infinite.subnormal }. not infinity) As a special case.f32 testp.type d. .notanumber.finite testp. a. .f64 isnan.op p.infinite. Instruction Set Table 47.f32. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. . and return the result as d. copysign. testp Syntax Floating-Point Instructions: testp Test floating-point property. testp. f0.pred = { . copysign Syntax Floating-Point Instructions: copysign Copy sign of one input to another.f32.f64 }. Description testp tests common properties of floating-point numbers and returns a predicate value of 1 if True and 0 if False. Table 48.

sat}.0.rp }.0]. 2010 . An add instruction with an explicit rounding modifier treated conservatively by the code optimizer.rnd}{. In particular. NaN results are flushed to +0. .f3.f32. sm_1x: add. Rounding modifiers have the following target requirements: .PTX ISA Version 2. mul/add sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device.f64 d.0f.f32 add{.f32 flushes subnormal inputs and results to sign-preserving zero. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. b.rn.0 Table 49.f64.rp for add.f2.rn): .0. .f32 clamps the result to [0.f32 flushes subnormal inputs and results to sign-preserving zero. .rm. add{.ftz.rn mantissa LSB rounds to nearest even . b. d. requires sm_13 for add. 84 January 24. .ftz}{. .rn.f32 f1.sat.rz available for all targets .rnd}. add. Saturation modifier: .f64 supports subnormal numbers. 1.rz. add.rm mantissa LSB rounds towards negative infinity . add. . subnormal numbers are supported.rz. add.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. d = a + b.ftz.f64 requires sm_13 or later.rnd = { . a. add. Description Semantics Notes Performs addition and writes the resulting value into a destination register.rm. add Syntax Floating-Point Instructions: add Add two values. requires sm_20 Examples @p add.rz mantissa LSB rounds towards zero .f32 supported on all target architectures. An add instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. Rounding modifiers (default is . a.

f3. a.b.f32 flushes subnormal inputs and results to sign-preserving zero.0.rz available for all targets .rz mantissa LSB rounds towards zero .f32.rnd}. requires sm_20 Examples sub. sub. NaN results are flushed to +0.rm. Instruction Set Table 50. . sub.sat. b. a.rp for sub.Chapter 8.f32 f1. Rounding modifiers have the following target requirements: .f2. . PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. 2010 85 .rnd = { . sub Syntax Floating-Point Instructions: sub Subtract one value from another.f32 clamps the result to [0.rn): .f64 supports subnormal numbers. mul/sub sequences with no rounding modifiers may be optimized to use fused-multiply-add instructions on the target device. A sub instruction with an explicit rounding modifier treated conservatively by the code optimizer. . Description Semantics Notes Performs subtraction and writes the resulting value into a destination register. sub. Saturation modifier: sub. . sub{.rz.0f.f64 d.ftz. 1.f32 supported on all target architectures.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. A sub instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer. requires sm_13 for sub. In particular.ftz}{. . sub.sat}. d = a .ftz.f64 requires sm_13 or later.a.f32 c.rn mantissa LSB rounds to nearest even .0].rn. subnormal numbers are supported.b. January 24.rn.0. . sm_1x: sub.f32 flushes subnormal inputs and results to sign-preserving zero.rn. sub. Rounding modifiers (default is .f32 sub{.rm.rp }.rm mantissa LSB rounds towards negative infinity . b. d.f64.rnd}{.

rn.PTX ISA Version 2.0f. For floating-point multiplication.rp for mul.ftz.f32 flushes subnormal inputs and results to sign-preserving zero.f32 mul{.pi // a single-precision multiply 86 January 24.rm mantissa LSB rounds towards negative infinity .rz. all operands must be the same size. A mul instruction with no rounding modifier defaults to round-to-nearesteven and may be optimized aggressively by the code optimizer.ftz}{. 1. mul/add and mul/sub sequences with no rounding modifiers may be optimized to use fusedmultiply-add instructions on the target device. requires sm_13 for mul. Rounding modifiers have the following target requirements: .rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.rz available for all targets .radius. mul.sat}.rn mantissa LSB rounds to nearest even . . .f32 supported on all target architectures. . subnormal numbers are supported. 2010 . d.rnd}{.f64 d.0. mul. PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1.rz mantissa LSB rounds towards zero .rn. mul. a.0.0 Table 51.rp }. d = a * b. Description Semantics Notes Compute the product of two values.f32 circumf.rn): . a. b. In particular.rnd = { . .0]. .f64. sm_1x: mul. b. mul Syntax Floating-Point Instructions: mul Multiply two values. . NaN results are flushed to +0.sat.f64 requires sm_13 or later. mul{. A mul instruction with an explicit rounding modifier treated conservatively by the code optimizer.rm.rnd}.f32 clamps the result to [0.ftz. requires sm_20 Examples mul. Rounding modifiers (default is . mul.f32.rm. Saturation modifier: mul.

x. d = a*b + c.rnd. b. sm_1x: fma. . fma Syntax Floating-Point Instructions: fma Fused multiply-add.f64 is the same as mad. PTX ISA Notes Target ISA Notes Examples January 24.y.ftz}{.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rz mantissa LSB rounds towards zero . b. fma. again in infinite precision. Description Semantics Notes Performs a fused multiply-add with no loss of precision in the intermediate product and addition. fma.sat.f64 supports subnormal numbers.rn. fma.rp }. fma. Saturation: fma.f32 flushes subnormal inputs and results to sign-preserving zero. fma.f32 requires sm_20 or later.0f.a.f32 introduced in PTX ISA version 2.f32 clamps the result to [0. 1.Chapter 8.f32 fma.f32 is unimplemented in sm_1x.0. The resulting value is then rounded to double precision using the rounding mode specified by . .f64 computes the product of a and b to infinite precision and then adds c to this product. d. c.rnd{.f64 requires sm_13 or later. subnormal numbers are supported.rn. again in infinite precision. a. NaN results are flushed to +0.rn.b. @p fma.f64 introduced in PTX ISA version 1. fma.sat}.f64.0.rnd.0].4. The resulting value is then rounded to single precision using the rounding mode specified by . fma.rm mantissa LSB rounds towards negative infinity . d.rz. fma.rm.rnd. . a.ftz.rn mantissa LSB rounds to nearest even .ftz. fma. Instruction Set Table 52. Rounding modifiers (no default): . .f32 computes the product of a and b to infinite precision and then adds c to this product. c. fma.f64 w. 2010 87 .c.f32 fma.rnd = { .z.f64 d.

f32.f64 computes the product of a and b to infinite precision and then adds c to this product. Description Semantics Notes Multiplies two values and adds a third.rnd.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f64}. // .f32 mad.0]. Note that this is different from computing the product with mul. mad. c. mad. sm_1x: mad. again in infinite precision.sat}.target sm_1x: mad.rm mantissa LSB rounds towards negative infinity . mad{. but the exponent is preserved. NaN results are flushed to +0.f32 computes the product of a and b at double precision.f64. The exception for mad. a. b.target sm_20: mad.rn mantissa LSB rounds to nearest even .rz mantissa LSB rounds towards zero . For . c.0.0 Table 53. 2010 . mad.f64 is the same as fma. mad. // . 1. Saturation modifier: mad. mad Syntax Floating-Point Instructions: mad Multiply two values and add a third value.target sm_1x d.f32 can produce slightly different numeric results and backward compatibility is not guaranteed in this case.f32 is identical to the result computed using separate mul and add instructions.ftz. a.{f32. b. a. mad. mad. // . For . d = a*b + c. b. and then the mantissa is truncated to 23 bits. subnormal numbers are supported.rnd. again in infinite precision.rm. When JIT-compiled for SM 2.f32).e.f32 is implemented as a fused multiply-add (i.rn.f64 d. fma. The resulting value is then rounded to double precision using the rounding mode specified by .rnd = { .ftz. The resulting value is then rounded to single precision using the rounding mode specified by .target sm_20 d.target sm_13 and later .PTX ISA Version 2. The resulting value is then rounded to double precision using the rounding mode specified by .f64 computes the product of a and b to infinite precision and then adds c to this product.rn.f32 is when c = +/-0. mad. the treatment of subnormal inputs and output follows IEEE 754 standard.rnd{. 88 January 24.{f32.f32 clamps the result to [0.f64} is the same as fma. Unlike mad. where the mantissa can be rounded and the exponent will be clamped. . mad. mad.rz.f32 computes the product of a and b to infinite precision and then adds c to this product.f32 mad.sat. again in infinite precision.ftz}{.ftz}{.0f. c. .0 devices. .rnd.0..f64 supports subnormal numbers.f32 flushes subnormal inputs and results to sign-preserving zero.rp }. Rounding modifiers (no default): .f32 flushes subnormal inputs and results to sign-preserving zero. In this case. and then writes the resulting value into a destination register.rnd.sat}.

f64. a rounding modifier is required for mad. requires sm_13 . In PTX ISA versions 1.f64 instructions having no rounding modifier will map to mad..f32 for sm_20 targets.f32.rp for mad. In PTX ISA versions 2.rz.f32 supported on all target architectures. Instruction Set PTX ISA Notes Introduced in PTX ISA version 1. Rounding modifiers have the following target requirements: .rp for mad.rn.rm.rm.rn..f64 requires sm_13 or later.4 and later..f64.0 and later.rn.rz.. requires sm_20 Examples @p mad.c.a. a rounding modifier is required for mad.0.f64. mad.b.. 2010 89 . Legacy mad.Chapter 8. January 24. Target ISA Notes mad..f32 d.

ftz}. and rounding introduced in PTX ISA version 1. div. Target ISA Notes div. Fast. y.rz.ftz. b.3. one of . full-range approximation that scales operands to achieve better accuracy.approx.rn.f64. subnormal numbers are supported.f32 and div.f32 flushes subnormal inputs and results to sign-preserving zero. d = a / b.f32 requires sm_20 or later.rnd. For b in [2-126.rnd. . div.full.full{. d.14159.rn. .rnd is required. d. Description Semantics Notes Divides a by b.ftz.f64 defaults to div.{rz.0. div.f32 div. div. Subnormal inputs and results are flushed to sign-preserving zero.f32 div.f64 requires sm_20 or later.ftz}.full.rm.rn. a. PTX ISA Notes div.ftz.full.full.approx. .f64 introduced in PTX ISA version 1. approximate divide full-range approximate divide IEEE 754 compliant rounding IEEE 754 compliant rounding . For PTX ISA version 1.f32. approximate single-precision divides: div. div.f64 diam.approx{.rm. yd. div.rnd = { . . .4. // // // // fast. For PTX ISA versions 1. or . xd.full. div Syntax Floating-Point Instructions: div Divide one value by another. sm_1x: div. 2126]. div.f32 div.rm mantissa LSB rounds towards negative infinity . and div. Examples 90 January 24. 2010 .4 and later. Explicit modifiers .approx.3.approx.ftz}.rp}. b.f64 d.0 Table 54. a. b. div.f32 defaults to div.rz mantissa LSB rounds towards zero . a.f64 supports subnormal numbers. zd.f64 requires sm_13 or later. b.rnd{. The maximum ulp error is 2 across the full range of inputs. but is not fully IEEE 754 compliant and does not support rounding modifiers.f32 flushes subnormal inputs and results to sign-preserving zero. a.circum.ftz. z. approximate division by zero creates a value of infinity (with same sign as a).f32 div. Divide with IEEE 754 compliant rounding: Rounding modifiers (no default): .f32 implements a relatively fast. x.f32 supported on all target architectures.rn mantissa LSB rounds to nearest even .rp }.f32 and div. stores result in d. computed as d = a * (1/b). .rn.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.f32 div. Fast. div. the maximum ulp error is 2. d.PTX ISA Version 2.approx.0 through 1.f32 implements a fast approximation to divide.approx.ftz.

neg{. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit. Take the absolute value of a and store the result in d.f64 supports subnormal numbers. January 24.f32 supported on all target architectures.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers. abs.f0.f32 flushes subnormal inputs and results to sign-preserving zero. neg. Future implementations may comply with the IEEE 754 standard by preserving payload and modifying only the sign bit.f32 supported on all target architectures. Subnormal numbers: sm_20: By default. Instruction Set Table 55.f32 neg.ftz. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. subnormal numbers are supported. neg.f64 d. neg Syntax Description Semantics Notes Floating-Point Instructions: neg Arithmetic negate.0. Negate the sign of a and store the result in d.Chapter 8. neg.ftz.ftz}. d. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. neg. a.f64 d.f32 flushes subnormal inputs and results to sign-preserving zero. NaN inputs yield an unspecified NaN.ftz. d = |a|. abs Syntax Description Semantics Notes Floating-Point Instructions: abs Absolute value.f32 abs. Subnormal numbers: sm_20: By default. a. abs.0.ftz}. abs. 2010 91 . d = -a.f64 requires sm_13 or later. subnormal numbers are supported.ftz.f64 requires sm_13 or later. a. sm_1x: abs.f32 x.f32 flushes subnormal inputs and results to sign-preserving zero.f32 x. NaN inputs yield an unspecified NaN. a. abs{. sm_1x: neg. abs. Table 56. d. abs.f0. neg.

if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default. sm_1x: min. min. max{. Store the minimum of a and b in d.f32 supported on all target architectures. b. (a < b) ? a : b. d.f64 supports subnormal numbers. a. b.f32 flushes subnormal inputs and results to sign-preserving zero. (a > b) ? a : b. b. min. Table 58. a.ftz.0.f32 min. max. d d d d = = = = NaN. min Syntax Description Semantics Floating-Point Instructions: min Find the minimum of two values.ftz.f32 max.f32 supported on all target architectures.f64 supports subnormal numbers. min. 92 January 24.f1. max. a. a.f32 flushes subnormal inputs and results to sign-preserving zero. a.f2.f64 d. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.ftz.f64 requires sm_13 or later. a.ftz}. max. b.f32 flushes subnormal inputs and results to sign-preserving zero. b. sm_1x: max. if (isNaN(a) && isNaN(b)) else if (isNaN(a)) else if (isNaN(b)) else Subnormal numbers: sm_20: By default.b. a.0.z. min. min{.f32 flushes subnormal inputs and results to sign-preserving zero. 2010 .c.b. subnormal numbers are supported. subnormal numbers are supported.f32 min.c. Notes PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.f64 f0. Store the maximum of a and b in d.f64 d.f32 max. max. d d d d = = = = NaN.PTX ISA Version 2. @p min.ftz}. d.0 Table 57. max Syntax Description Semantics Floating-Point Instructions: max Find the maximum of two values.ftz. max.x.f64 z. b.f64 requires sm_13 or later.

rnd.approx. General rounding modifiers were added in PTX ISA version 2.approx. subnormal numbers are supported.f64 supports subnormal numbers.rz mantissa LSB rounds towards zero .approx.f32 supported on all target architectures. d. Instruction Set Table 59. rcp Syntax Floating-Point Instructions: rcp Take the reciprocal of a value. For PTX ISA versions 1.0. approximate reciprocal // IEEE 754 compliant rounding // IEEE 754 compliant rounding .0 NaN Reciprocal with IEEE 754 compliant rounding: Rounding modifiers (no default): . The maximum absolute error is 2-23.rp }.rnd is required. xi.f32 flushes subnormal inputs and results to sign-preserving zero. rcp. a.approx.0 +subnormal +Inf NaN Result -0.rn.rn.0 -Inf -Inf +Inf +Inf +0. rcp. . . a.f32 implements a fast approximation to reciprocal.rm mantissa LSB rounds towards negative infinity . rcp.approx{.4. Description Semantics Notes Compute 1/a. a.f64 and explicit modifiers .f32 flushes subnormal inputs and results to sign-preserving zero.f32 rcp. // fast. For PTX ISA version 1.ftz}.rn mantissa LSB rounds to nearest even . 2010 93 .0-2. rcp.Chapter 8. rcp.approx or . Target ISA Notes rcp.f32 rcp.ftz.rn.f32 defaults to rcp. rcp.{rz.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default.rnd = { .3. sm_1x: rcp. rcp.rp}.0 +0.ftz were introduced in PTX ISA version 1.rn. d.rm.f64 requires sm_13 or later.f32 rcp. one of . .ftz.0.0.f32 and rcp.rz.rn. xi. rcp. and rcp.rn. rcp.ftz. rcp.rnd{.rnd.x.0 through 1. d = 1 / a.r.ftz}.4 and later.f64 ri.f32 rcp.f64 introduced in PTX ISA version 1.rm.f32.f64 requires sm_20 or later.f64.x.f32 requires sm_20 or later.f64 defaults to rcp.0 over the range 1.ftz.approx and . PTX ISA Notes rcp. store result in d.f64 d. Examples January 24. Input -Inf -subnormal -0.

4.0 Table 60.f32 and sqrt.ftz were introduced in PTX ISA version 1. r.rn.0 +Inf NaN Square root with IEEE 754 compliant rounding: Rounding modifiers (no default): . // IEEE 754 compliant rounding d.f64 requires sm_13 or later.0 +0.0 +0.f32 defaults to sqrt.f64 and explicit modifiers .f32 sqrt. approximate square root d. sqrt. General rounding modifiers were added in PTX ISA version 2. and sqrt.0 through 1.rn.rnd{.f32 implements a fast approximation to square root.rp mantissa LSB rounds towards positive infinity Subnormal numbers: sm_20: By default. .0.rz mantissa LSB rounds towards zero .rn.ftz.f32 sqrt.f64 r. The maximum absolute error for sqrt.rm.rm.f32 supported on all target architectures.rz. . Input -Inf -normal -subnormal -0. sqrt.rp }. a. subnormal numbers are supported. one of .0 +0. sqrt. sqrt.approx{. For PTX ISA version 1.approx. d = sqrt(a).rn. sqrt Syntax Floating-Point Instructions: sqrt Take the square root of a value.approx and . sm_1x: sqrt.PTX ISA Version 2.rnd = { .f32 flushes subnormal inputs and results to sign-preserving zero. .rn.f32 sqrt.0.f32 sqrt.x.rnd.0 -0.rn.f64.f32 requires sm_20 or later. a. // fast.approx. Target ISA Notes sqrt.x.4 and later.f64 supports subnormal numbers. For PTX ISA versions 1.f64 requires sm_20 or later.rp}.3. sqrt. store in d.ftz.rm mantissa LSB rounds towards negative infinity .{rz. PTX ISA Notes sqrt.approx or .approx. sqrt.x.f64 defaults to sqrt. sqrt. 2010 .rn mantissa LSB rounds to nearest even .0 +subnormal +Inf NaN Result NaN NaN -0.ftz. a. sqrt. sqrt.rnd is required.f32 is TBD.ftz}. Examples 94 January 24. sqrt.f32. r.rnd.approx.ftz}. Description Semantics Notes Compute sqrt(a).f32 flushes subnormal inputs and results to sign-preserving zero.ftz.f64 introduced in PTX ISA version 1.approx.f64 d. // IEEE 754 compliant rounding .

f32. a. The maximum absolute error for rsqrt.ftz.f32 rsqrt. Input -Inf -normal -subnormal -0.0 NaN The maximum absolute error for rsqrt. January 24.0 +0.f32 defaults to rsqrt.f64 defaults to rsqrt. X.ftz. Explicit modifiers .approx. Target ISA Notes Examples rsqrt.0-4. subnormal numbers are supported. rsqrt.f64 were introduced in PTX ISA version 1.f64 is TBD. a.f64 is emulated in software and are relatively slow. Instruction Set Table 61.approx. rsqrt. sm_1x: rsqrt. store the result in d.approx.approx implements an approximation to the reciprocal square root. PTX ISA Notes rsqrt.f32 supported on all target architectures. rsqrt. rsqrt. For PTX ISA version 1.f64.Chapter 8.f64 requires sm_13 or later.0 +subnormal +Inf NaN Result NaN NaN -Inf -Inf +Inf +Inf +0. x. ISR.approx{.0. d. rsqrt.0.4. d = 1/sqrt(a). 2010 95 .approx modifier is required.ftz}.f64 d.f32 and rsqrt.ftz.f32 is 2-22. Compute 1/sqrt(a).approx. and rsqrt. For PTX ISA versions 1. rsqrt Syntax Description Semantics Notes Floating-Point Instructions: rsqrt Take the reciprocal of the square root of a value.0 through 1.4 over the range 1. the .f64 isr.ftz were introduced in PTX ISA version 1.approx and .approx.f32 rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero. Note that rsqrt.approx.3. rsqrt. Subnormal numbers: sm_20: By default. rsqrt.f32 flushes subnormal inputs and results to sign-preserving zero.f64 supports subnormal numbers.4 and later.

ftz introduced in PTX ISA version 1.f32 defaults to sin. For PTX ISA version 1. a. d = sin(a). subnormal numbers are supported. sin.0 NaN NaN The maximum absolute error is 2-20.0 -0.approx and . sin.4.f32 introduced in PTX ISA version 1.ftz.0 Table 62.3.ftz}.4 and later. sin.f32. Subnormal numbers: sm_20: By default.approx.0 +0.ftz. 96 January 24. sin. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 sa.0 +subnormal +Inf NaN Result NaN -0. 2010 .0 through 1.PTX ISA Version 2. Explicit modifiers . the .f32 d. For PTX ISA versions 1. PTX ISA Notes sin. a.0 +0.f32 flushes subnormal inputs and results to sign-preserving zero.approx modifier is required.ftz.0 +0. Input -Inf -subnormal -0.approx.f32 implements a fast approximation to sine. Find the sine of the angle a (in radians).approx. Target ISA Notes Examples Supported on all target architectures.0.approx{. sin Syntax Description Semantics Floating-Point Notes Floating-Point Instructions: sin Find the sine of a value.9 in quadrant 00. sin.

f32 flushes subnormal inputs and results to sign-preserving zero. cos Syntax Description Semantics Notes Floating-Point Instructions: cos Find the cosine of a value.0 +0.0 NaN NaN The maximum absolute error is 2-20. January 24. a. sm_1x: Subnormal inputs and results to sign-preserving zero.f32 implements a fast approximation to cosine.approx modifier is required. Target ISA Notes Examples Supported on all target architectures.ftz. Explicit modifiers .Chapter 8.f32 ca.ftz. For PTX ISA version 1.approx. cos.f32 d. Find the cosine of the angle a (in radians).0 +1.approx{.0 through 1.f32 defaults to cos.ftz}. d = cos(a).3. Instruction Set Table 63. Subnormal numbers: sm_20: By default.0 +1. cos. the . PTX ISA Notes cos. cos.approx. For PTX ISA versions 1. 2010 97 . Input -Inf -subnormal -0. a.0 +subnormal +Inf NaN Result NaN +1.approx and .4 and later.ftz.0 +1.f32 introduced in PTX ISA version 1.approx.ftz introduced in PTX ISA version 1. cos.9 in quadrant 00. subnormal numbers are supported.0. cos.4.f32.

The maximum absolute error is 2-22. lg2.f32 introduced in PTX ISA version 1.f32 la. Subnormal numbers: sm_20: By default. subnormal numbers are supported. lg2. For PTX ISA version 1.approx.ftz}.approx and .0 through 1.approx. d = log(a) / log(2).approx. lg2. 2010 .ftz.approx{. lg2. lg2.4 and later. sm_1x: Subnormal inputs and results to sign-preserving zero.approx modifier is required. For PTX ISA versions 1.ftz introduced in PTX ISA version 1.3.PTX ISA Version 2. 98 January 24.0.ftz.f32.f32 flushes subnormal inputs and results to sign-preserving zero. the .0 +subnormal +Inf NaN Result NaN -Inf -Inf -Inf -Inf +Inf NaN d. Target ISA Notes Examples Supported on all target architectures.0 Table 64.f32 Determine the log2 of a.ftz. Input -Inf -subnormal -0. a. a.4.6 for mantissa.0 +0. lg2 Syntax Description Semantics Notes Floating-Point Instructions: lg2 Find the base-2 logarithm of a value.f32 implements a fast approximation to log2(a).f32 defaults to lg2. PTX ISA Notes lg2. Explicit modifiers .

Chapter 8. Instruction Set

Table 65.
ex2 Syntax Description Semantics Notes

Floating-Point Instructions: ex2
Find the base-2 exponential of a value. ex2.approx{.ftz}.f32 Raise 2 to the power a. d = 2 ^ a; ex2.approx.f32 implements a fast approximation to 2a. Input -Inf -subnormal -0.0 +0.0 +subnormal +Inf NaN Result +0.0 +1.0 +1.0 +1.0 +1.0 +Inf NaN d, a;

The maximum absolute error is 2-22.5 for fraction in the primary range. Subnormal numbers: sm_20: By default, subnormal numbers are supported. ex2.ftz.f32 flushes subnormal inputs and results to sign-preserving zero. sm_1x: Subnormal inputs and results to sign-preserving zero. PTX ISA Notes ex2.f32 introduced in PTX ISA version 1.0. Explicit modifiers .approx and .ftz introduced in PTX ISA version 1.4. For PTX ISA version 1.4 and later, the .approx modifier is required. For PTX ISA versions 1.0 through 1.3, ex2.f32 defaults to ex2.approx.ftz.f32. Target ISA Notes Examples Supported on all target architectures. ex2.approx.ftz.f32 xa, a;

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PTX ISA Version 2.0

8.7.3. Comparison and Selection Instructions
The comparison select instructions are:
set setp selp slct

As with single-precision floating-point instructions, the set, setp, and slct instructions support subnormal numbers for sm_20 targets and flush single-precision subnormal inputs to sign-preserving zero for sm_1x targets. The optional .ftz modifier provides backward compatibility with sm_1x targets by flushing subnormal inputs and results to sign-preserving zero regardless of the target architecture.

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Chapter 8. Instruction Set

Table 66. Comparison and Selection Instructions: set
set Syntax Compare two numeric values with a relational operator, and optionally combine this result with a predicate value by applying a Boolean operator. set.CmpOp{.ftz}.dtype.stype set.CmpOp.BoolOp{.ftz}.dtype.stype .dtype = { .u32, .s32, .stype = { .b16, .b32, .u16, .u32, .s16, .s32, .f32, Description .f32 }; .b64, .u64, .s64, .f64 }; d, a, b; d, a, b, {!}c;

Compares two numeric values and optionally combines the result with another predicate value by applying a Boolean operator. If this result is True, 1.0f is written for floating-point destination types, and 0xFFFFFFFF is written for integer destination types. Otherwise, 0x00000000 is written. The comparison operator is a suffix on the instruction, and can be one of: eq, ne, lt, le, gt, ge, lo, ls, hi, hs equ, neu, ltu, leu, gtu, geu, num, nan The Boolean operator BoolOp(A,B) is one of: and, or, xor.

Semantics

t = (a CmpOp b) ? 1 : 0; if (isFloat(dtype)) d = BoolOp(t, c) ? 1.0f : 0x00000000; else d = BoolOp(t, c) ? 0xFFFFFFFF : 0x00000000; The signed and unsigned comparison operators are eq, ne, lt, le, gt, ge. For unsigned values, the comparison operators lo, ls, hi, and hs for lower, lower-orsame, higher, and higher-or-same may be used instead of lt, le, gt, ge, respectively. The untyped, bit-size comparisons are eq and ne.

Integer Notes

Floating Point Notes

The ordered comparisons are eq, ne, lt, le, gt, ge. If either operand is NaN, the result is false. To aid comparison operations in the presence of NaN values, unordered versions are included: equ, neu, ltu, leu, gtu, geu. If both operands are numeric values (not NaN), then these comparisons have the same result as their ordered counterparts. If either operand is NaN, then the result of these comparisons is true. num returns true if both operands are numeric values (not NaN), and nan returns true if either operand is NaN. Subnormal numbers: sm_20: By default, subnormal numbers are supported. set.ftz.dtype.f32 flushes subnormal inputs to sign-preserving zero. sm_1x: set.dtype.f64 supports subnormal numbers. set.dtype.f32 flushes subnormal inputs to sign-preserving zero. Modifier .ftz applies only to .f32 comparisons.

PTX ISA Notes Target ISA Notes Examples

Introduced in PTX ISA version 1.0. set with .f64 source type requires sm_13. @p set.lt.and.f32.s32 set.eq.u32.u32 d,a,b,r; d,i,n;

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101

. .s32 setp. and higher-or-same may be used instead of lt. gt. p = BoolOp(t. lo. Applies to all numeric types.f32 flushes subnormal inputs to sign-preserving zero. ne. Semantics t = (a CmpOp b) ? 1 : 0. setp.f64 }. ltu. ge. .CmpOp. {!}c.ftz.b32. ge. Subnormal numbers: sm_20: By default.dtype.type setp. nan The Boolean operator BoolOp(A.r.ftz}. leu. le. and can be one of: eq. subnormal numbers are supported. lt. le.f64 source type requires sm_13 or later.B) is one of: and.0.type = { .BoolOp{.eq. gtu.lt. leu. The untyped. ne. unordered versions are included: equ. ge. ls. The signed and unsigned comparison operators are eq. num. Description Compares two values and combines the result with another predicate value by applying a Boolean operator. neu. le. setp with .ftz}. Modifier . and nan returns true if either operand is NaN. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. a.and. higher. lt. num returns true if both operands are numeric values (not NaN). setp Syntax Comparison and Selection Instructions: setp Compare two numeric values with a relational operator.u16. This result is written to the first destination operand. le. sm_1x: setp. the comparison operators lo. loweror-same. lt. bit-size comparisons are eq and ne. a. The destinations p and q must be .b.a.ftz applies only to .u32.f32 flushes subnormal inputs to sign-preserving zero. hi.u32 p|q.0 Table 67. xor.type . ltu. setp. . gt.b64. c). respectively. gtu. then the result of these comparisons is true. setp. p[|q].f64 supports subnormal numbers.s32. If both operands are numeric values (not NaN). ls. A related value computed using the complement of the compare result is written to the second destination operand. ge. or. 102 January 24. For unsigned values. 2010 . .n.b16. If either operand is NaN. .dtype.PTX ISA Version 2. . b.u64. . . @q setp. . and (optionally) combine this result with a predicate value by applying a Boolean operator. the result is false. gt.dtype. Integer Notes Floating Point Notes The ordered comparisons are eq. neu. q = BoolOp(!t.f32. b. and hs for lower.s64. geu. ne.s16. p.pred variables. then these comparisons have the same result as their ordered counterparts. p[|q]. hi. gt.i. c). To aid comparison operations in the presence of NaN values. The comparison operator is a suffix on the instruction. If either operand is NaN. hs equ.CmpOp{.f32 comparisons. geu.

dtype. a. . If c ≥ 0. .u32. . 2010 103 . otherwise b is stored in d.b64. selp Syntax Comparison and Selection Instructions: selp Select between source operands.s32. a. Subnormal numbers: sm_20: By default.g.ftz. Description Conditional selection. val.u32. Introduced in PTX ISA version 1. Modifier . slct.s16. sm_1x: slct.f32 comparisons.type = { . PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. . . b. If c is True. .ftz applies only to . slct. .r.Chapter 8. and b are treated as a bitsize type of the same width as the first instruction type. a is stored in d.dtype.s64.s32 x. f0.f32 flushes subnormal values of operand c to sign-preserving zero. Operand c is a predicate.0. B. d. and operand a is selected. The selected input is copied to the output without modification. operand c must match the second instruction type. . . .ftz. z.u64. Semantics Floating Point Notes January 24. Description Semantics PTX ISA Notes Target ISA Notes Examples Conditional selection. c. b otherwise. . . .f32 flushes subnormal values of operand c to sign-preserving zero. . b.s32 selp. . . selp. Operands d. d = (c >= 0) ? a : b. a is stored in d.0.u16.u64.f64 }. .f32 r0. based on the sign of the third operand.f64 requires sm_13 or later. the comparison is unordered and operand b is selected.xp. .b16. selp.f64 requires sm_13 or later. slct. .x. d = (c == 1) ? a : b.dtype. b.f32. fval.s32 slct{. If operand c is NaN.b64. .u32.f32 A. and operand a is selected.t. slct.s64. @q selp.p. subnormal numbers are supported. based on the value of the predicate source operand.f64 }. c.u64.ftz}.f32.b32. y.b32.type d.f32 d. a. negative zero equals zero. Instruction Set Table 68.dtype = { .u16. c.b16.f32 comparisons.s16. a. Operands d. For . .dtype. Table 69. a. C. slct Syntax Comparison and Selection Instructions: slct Select one source operand.s32. and b must be of the same type. slct. .

xor. 2010 .0 8.PTX ISA Version 2. performing bit-wise operations on operands of any type. Logic and Shift Instructions The logic and shift instructions are fundamentally untyped. Instructions and. or. The logical shift instructions are: and or xor not cnot shl shr 104 January 24. provided the operands are of the same size. and not also operate on predicates.7. This permits bit-wise operations on floating point values without having to define a union to access the bits.4.

0x80000000. January 24. and Syntax Logic and Shift Instructions: and Bitwise AND.type d. or. Instruction Set Table 70. . Supported on all target architectures.b32.b32 mask mask. d = a & b. but not necessarily the type. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise or operation for the bits in a and b.0. . .type d. but not necessarily the type. Supported on all target architectures.0. . Allowed types include predicate registers. sign.b32. Introduced in PTX ISA version 1.r. and. The size of the operands must match. . or.type = { .b16. Introduced in PTX ISA version 1.b64 }. . Allowed types include predicate registers.b64 }. b.type = { . 2010 105 . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise and operation for the bits in a and b. The size of the operands must match. or Syntax Logic and Shift Instructions: or Bitwise OR.pred. .b32 x. b. Table 71.r. and.b16.0x00010001 or. a.b32 and.Chapter 8.q.fpvalue.pred p. a. . d = a | b.q.pred.

b16. xor. xor Syntax Logic and Shift Instructions: xor Bitwise exclusive-OR (inequality). d = ~a. xor. not. cnot Syntax Logic and Shift Instructions: cnot C/C++ style logical negation.PTX ISA Version 2.type d.pred. cnot.0x0001. Introduced in PTX ISA version 1.b32 d. Supported on all target architectures.q. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the logical negation using C/C++ semantics. but not necessarily the type. a. . The size of the operands must match.type = { . . Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Invert the bits in a. .b32.b16.r. . .type = { . not Syntax Logic and Shift Instructions: not Bitwise negation.b16. Introduced in PTX ISA version 1.b32. Description Semantics Notes PTX ISA Notes Target ISA Notes Examples Compute the bit-wise exclusive-or operation for the bits in a and b.b64 }. cnot.type d.b16 d. Table 74. 2010 . Supported on all target architectures. The size of the operands must match. but not necessarily the type. not. .0.0. d. but not necessarily the type. not. a. . Introduced in PTX ISA version 1.a.b64 }.0 Table 72.pred p.type d. b.b32 xor. . Allowed types include predicate registers. .b32. Table 73. d = a ^ b. 106 January 24. Allowed types include predicates. . Supported on all target architectures.type = { .x. The size of the operands must match.b32 mask.mask. one’s complement. a.q. d = (a==0) ? 1 : 0.pred. .b64 }.0.

regardless of the instruction type.type d.a. zero-fill on right.Chapter 8.i. shr. i. . a. shr Syntax Logic and Shift Instructions: shr Shift bits right.1. .u16.s32. .b32. sign or zero fill on left.0. The sizes of the destination and first source operand must match.b32 q. Bit-size types are included for symmetry with SHL.b16 c.s32 shr. Introduced in PTX ISA version 1.s64 }. . The b operand must be a 32-bit value. Supported on all target architectures.type = { . b.b16. .j.2.a. shl Syntax Logic and Shift Instructions: shl Shift bits left.b32. k. Description Semantics Notes Shift a left by the amount specified by unsigned 32-bit value in b. Signed shifts fill with the sign bit. Supported on all target architectures. regardless of the instruction type. PTX ISA Notes Target ISA Notes Examples Table 76.2. 2010 107 . . b. d = a >> b.b16. unsigned and untyped shifts fill with 0.type d. .u16 shr. . shr. Shift amounts greater than the register width N are clamped to N.i. shl.u64. d = a << b.s16.b64 }. but not necessarily the type. Introduced in PTX ISA version 1. Instruction Set Table 75. a. . but not necessarily the type. Shift amounts greater than the register width N are clamped to N. PTX ISA Notes Target ISA Notes Examples January 24. Description Semantics Notes Shift a right by the amount specified by unsigned 32-bit value in b. shl. .0. . .b64. The sizes of the destination and first source operand must match.u32.type = { . The b operand must be a 32-bit value.

suld. and from state space to state space.5. possibly converting it from one format to another. mov.7. and st operate on both scalar and vector types. ld. The cvta instruction converts addresses between generic and global. Instructions ld. prefetchu isspacep cvta cvt 108 January 24. The isspacep instruction is provided to query whether a generic address falls within a particular state space window. local.0 8. or shared state spaces. and sust support optional cache operations.PTX ISA Version 2. Data Movement and Conversion Instructions These instructions copy data from place to place. 2010 . The Data Movement and Conversion Instructions are: mov ld ldu st prefetch. st. ldu.

cg to cache loads only globally. to allow the thread program to poll a SysMem location written by the CPU. As a result of this request. which allocates cache lines in all levels (L1 and L2) with normal eviction policy.cv Cache as volatile (consider cached system memory lines stale. Instruction Set 8.Chapter 8. not L1). Cache Operators PTX 2. The ld. The default load instruction cache operation is ld.lu operation.cs Cache streaming. Operator . . fetch again).7. it performs the ld. Use ld. The driver must invalidate global L1 cache lines between dependent grids of parallel threads. likely to be accessed again.cv to a frame buffer DRAM address is the same as ld. if the line is fully covered. bypassing the L1 cache.ca loads cached in L1. Stores by the first grid program are then correctly fetched by the second grid program issuing default ld. the second thread may get stale L1 cache data. but multiple L1 caches are not coherent for global data. . The compiler / programmer may use ld.ca. evict-first.0 introduces optional cache operators on load and store instructions.ca. The ld. any existing cache lines that match the requested address in L1 will be evicted.lu load last use operation.cg Cache at global level (cache in L2 and below.5. the cache operators have the following definitions and behavior. when applied to a local address.lu instruction performs a load cached streaming operation (ld.lu when restoring spilled registers and popping function stack frames to avoid needless write-backs of lines that will not be used again. likely to be accessed once.cs) on global addresses.cs load cached streaming operation allocates global lines with evict-first policy in L1 and L2 to limit cache pollution by temporary streaming data that may be accessed once or twice. For sm_20 and later. . A ld. rather than the data stored by the first thread. 2010 109 . The cache operators require a target architecture of sm_20 or later.lu Last use. and a second thread loads that address via a second L1 cache with ld. and cache only in the L2 cache.1. Table 77. January 24. When ld. Global data is coherent at the L2 level. .cs is applied to a Local window address.cv load cached volatile operation applied to a global System Memory address invalidates (discards) a matching L2 line and re-fetches the line on each new load. The ld. The ld.ca Cache Operators for Memory Load Instructions Meaning Cache at all levels.cs. invalidates (discards) the local L1 line following the load. If one thread stores to global memory via one L1 cache.

and a second thread in a different SM later loads from that address via a different L1 cache with ld.ca. Future GPUs may have globally-coherent L1 caches. regardless of the cache operation.wb could write-back global store data from L1. sm_20 does NOT cache global store data in L1 because multiple L1 caches are not coherent for global data. bypassing the L1 cache. The st. Stores by the first grid program are then correctly missed in L1 and fetched by the second grid program issuing default ld.cs Cache streaming. and cache only in the L2 cache. 2010 .ca loads. st.wt store write-through operation applied to a global System Memory address writes through the L2 cache. Data stored to local per-thread memory is cached in L1 and L2 with with write-back.wt Cache write-through (to system memory). The st. likely to be accessed once. Use st.wb Cache Operators for Memory Store Instructions Meaning Cache write-back all coherent levels.wb for global data. .cg Cache at global level (cache in L2 and below. to allow a CPU program to poll a SysMem location written by the GPU with st.wb.PTX ISA Version 2. and discard any L1 lines that match. . and marks local L1 lines evict-first. 110 January 24. In sm_20.0 Table 78. However. If one thread stores to global memory.cs store cached-streaming operation allocates cache lines with evict-first policy in L2 (and L1 if Local) to limit cache pollution by streaming output data. . not L1). The default store instruction cache operation is st.wt. bypassing its L1 cache.cg is the same as st. The driver must invalidate global L1 cache lines between dependent grids of thread arrays. Addresses not in System Memory use normal write-back.cg to local memory uses the L1 cache. Operator . in which case st. but st. Global stores bypass L1. rather than get the data from L2 or memory stored by the first thread.cg to cache global store data only globally. the second thread may get a hit on stale L1 cache data. which writes back cache lines of coherent cache levels with normal eviction policy.

type mov.a. A[5]. or shared state space. ptr. .e. . and . A. 2010 111 . d. we include the arithmetic types for the programmer’s convenience: their use enhances program readability and allows additional type checking. mov places the non-generic address of the variable (i.f64 requires sm_13 or later.0.f64 }.type d.type = { . d = sreg.shared state spaces. Operand a may be a register.pred. addr. a. mov.. variable in an addressable memory space.local. label. d. . the parameter will be copied onto the stack and the address will be in the local state space.1. local. i.u32 mov.e. or function name. sreg.b64.Chapter 8. local.f32. myFunc.b16. special register. Instruction Set Table 79. local.b32.s64. k.. // get address of variable // get address of label or function . .type mov. immediate.f32 mov. Take the non-generic address of a variable in global.s16. Write register d with the value of a. u. within the variable’s declared state space Notes Although only predicate and bit-size types are required. . . avar.type mov. Introduced in PTX ISA version 1.global. . ptr.u32 d. The generic address of a variable in global.u32 mov. or shared state space may be taken directly using the cvta instruction.u16. . PTX ISA Notes Target ISA Notes Examples // move address of A into ptr // move address of A[5] into ptr // get address of myFunc January 24.s32. // address is non-generic. or shared state space may be generated by first taking the address within the state space with mov and then converting it to a generic address using the cvta instruction.v. d = &avar.u32. . d = &label.0. mov. . mov.u64. the address of the variable in its state space) into the destination register. . d. the generic address of a variable declared in global. mov Syntax Data Movement and Conversion Instructions: mov Set a register variable with the value of a register variable or an immediate value. label. . For variables declared in .u16 mov. alternately. Description .f32 mov. Note that if the address of a device function parameter is moved to a register.const. Semantics d = a.

63] } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 mov.hi are .type = { .15].x | (a.b64 { d.31] } // unpack 8-bit elements from . d..x.. Description Write scalar register d with the packed value of vector register a.y << 16) | (a.hi}.w have type . {r. . a[32.b16 // pack four 8-bit elements into .b8 r.y.w << 48) d = a..y } = { a[0. a[8.b32 { d. mov may be used to pack vector elements into a scalar register or unpack sub-fields of a scalar register into a vector. d. %r1.b32 mov.b have type .x | (a.x | (a. a.31].y << 8) | (a.x | (a. d.7].w << 24) d = a. .w } = { a[0. Both the overall size of the vector and the size of the scalar must match the size of the instruction type. d.31].x.0 Table 80.63] } // unpack 16-bit elements from . a[16. d. mov.... 2010 .. // // // // a.b}.b..b64 { d.w } = { a[0. Semantics d = a.23].b32.z.b64 }. .7].%r1.y } = { a[0. {lo. a[32.z.u8 // unpack 32-bit elements from .a}.x.type d. For bit-size types.{a.z << 16) | (a.31] } // unpack 16-bit elements from . d.a have type ..u32 x.x.b64 112 January 24.y.g. a[16.. a[8.b32 %r1.y.b32 // pack two 16-bit elements into .b.x | (a.b32 // pack four 16-bit elements into . lo.z.0.15].b64 // pack two 32-bit elements into ...y << 8) d = a.x. a[24. Supported on all target architectures. d.{x.y } = { a[0..u16 %x is a double.15].b32 { d. mov Syntax Data Movement and Conversion Instructions: mov Move vector-to-scalar (pack) or scalar-to-vector (unpack).PTX ISA Version 2.y << 16) d = a.. or write vector register d with the unpacked values from scalar register a.y. d.15] } // unpack 8-bit elements from .y << 32) // pack two 8-bit elements into .g.w}. a[16. a[48.b16 { d.z.47].b16. %x. d.b64 mov.z << 32) | (a. mov.

// // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . . 32-bit). The address must be naturally aligned to a multiple of the access size. 2010 113 . and is zeroextended to the destination register width for unsigned and bit-size types. d. i. or [immAddr] an immediate absolute byte address (unsigned. .cop}. Semantics d d d d = = = = a.ss}.b16.vec = { . ld. .vec.1.f64 using cvt.f64 }. .param. perform the load using generic addressing. // load from address // vector load from addr // load from address // vector load from addr // state space // cache operation ld. i. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.type ld{. an address maps to the corresponding location in local or shared memory. A destination register wider than the specified type may be used.shared }. .lu. This may be used.f16 data may be loaded using ld.u8. The . ld{. . ld Syntax Data Movement and Conversion Instructions: ld Load a register variable from an addressable state space variable. In generic addressing.volatile may be used with . d.Chapter 8.cg. Within these windows. . .b64. 32-bit).cop}..cv }. The address size may be either 32-bit or 64-bit.ss = { . .s16. . Generic addressing and cache operations introduced in PTX ISA 2. Generic addressing may be used with ld.s32. [a].ss}{.local.volatile. or the instruction may fault. an integer or bit-size type register reg containing a byte address. *a. If no state space is given.volatile.type ld.ss}.s8.v4 }. .reg state space. ld.b8.volatile{.ss}{. . *(a+immOff).cop = { .0. Description Load register variable d from the location specified by the source address operand a in specified state space.0.s64.u32. to enforce sequential consistency between threads accessing shared memory.v2. an address maps to global memory unless it falls within the local memory window or the shared memory window. [a]. ld introduced in PTX ISA version 1. for example. .cs.u16.volatile introduced in PTX ISA version 1.u64. . the access may proceed by silently masking off low-order address bits to achieve proper rounding.global and .shared spaces to inhibit optimization of references to volatile memory. . .type d. The value loaded is sign-extended to the destination register width for signed integers. Instruction Set Table 81. If an address is not properly aligned.volatile{.type .ca. .type = { . and truncated if the register width exceeds the state space address width for the target architecture. Cache operations are not permitted with ld. d.const. . [a]. *(immAddr).f32 or .e. . the resulting behavior is undefined.e. . .vec.b16. .global. The addressable operand a is one of: [avar] [areg] the name of an addressable variable var.const space suffix may have an optional bank number to indicate constant banks other than bank zero. PTX ISA Notes January 24. . [a]. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.b32. Addresses are zero-extended to the specified width as needed. .f32. . and then converted to . .

local. 2010 . // access incomplete array x.global.[p+4]. // load .const[4].f16 data into 32-bit reg // up-convert f16 data to f32 Examples 114 January 24. d.b32 ld. // immediate address %r. Q.[p].[240].b64 ld.f32 ld. ld.const. x.f16 d. Cache operations require sm_20 or later.s32 ld.PTX ISA Version 2.v4.f32.local.[fs].shared.%r. Generic addressing requires sm_20 or later.b32 ld.[buffer+64].0 Target ISA Notes ld. // negative offset %r.b32 ld.f64 requires sm_13 or later. %r.[a].b16 cvt.[p+-8].global.

b32 d. Semantics d d d d = = = = a. *(immAddr).ss}.u32.f64 requires sm_13 or later.b32. ldu. // // // // named variable a register register-plus-offset immediate address Notes Destination d must be in the . The data at the specified address must be read-only. .b8. *a. 2010 115 . an address maps to global memory unless it falls within the local memory window or the shared memory window.v4. .f32 d. i. Addresses are zero-extended to the specified width as needed. Introduced in PTX ISA version 2. In generic addressing.u8.[p+4].v2. 32-bit). i. Description Load read-only data into register variable d from the location specified by the source address operand a in the global state space. perform the load using generic addressing. and truncated if the register width exceeds the state space address width for the target architecture. only generic addresses that map to global memory are legal.v4 }. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. and then converted to .s32.ss}.s64. . ldu.vec.e.b16.f16 data may be loaded using ldu. or the instruction may fault. If no state space is given. PTX ISA Notes Target ISA Notes Examples January 24. .f32 Q. [areg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.b16. Instruction Set Table 82. The value loaded is sign-extended to the destination register width for signed integers.b64.0. .s16. // state space .vec = { .f64 }. .global. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding.reg state space. ldu{. d. . ldu.global }. an address maps to the corresponding location in local or shared memory. Within these windows..e. 32-bit). For ldu. The address must be naturally aligned to a multiple of the access size.type = { . .Chapter 8. If an address is not properly aligned. ldu. . . The address size may be either 32-bit or 64-bit. [a].[a].f64 using cvt. . [areg] a register reg containing a byte address. where the address is guaranteed to be the same across all threads in the warp.f32. .ss = { .s8. The addressable operand a is one of: [avar] the name of an addressable variable var.u64. . A destination register wider than the specified type may be used.global. // load from address // vec load from address .u16. *(a+immOff).f32 or . .global. A register containing an address may be declared as a bit-size type or integer type. . and is zeroextended to the destination register width for unsigned and bit-size types.type ldu{.[p]. [a]. . ldu Syntax Data Movement and Conversion Instructions: ldu Load read-only data from an address that is common across threads in the warp. or [immAddr] an immediate absolute byte address (unsigned.type d.

. . Description Store the value of register variable b in the location specified by the destination address operand a in specified state space. st Syntax Data Movement and Conversion Instructions: st Store a register variable to an addressable state space variable. . The address size may be either 32-bit or 64-bit.reg state space. Generic addressing and cache operations introduced in PTX ISA 2. The lower n bits corresponding to the instruction-type width are stored to memory.global and . . The addressable operand a is one of: [var] [reg] the name of an addressable variable var. an address maps to global memory unless it falls within the local memory window or the shared memory window. b.f64 }.cop . Cache operations require sm_20 or later. .. . . The address must be naturally aligned to a multiple of the access size. Addresses are zero-extended to the specified width as needed. st.volatile introduced in PTX ISA version 1.ss .b32.b16. b. Semantics d = a.cg.0.v4 }.volatile may be used with . st{. the resulting behavior is undefined.u8. .u16.e. . an address maps to the corresponding location in local or shared memory. b. . st introduced in PTX ISA version 1.b8. . [a]. Cache operations are not permitted with st. In generic addressing.cs.0. 2010 . an integer or bit-size type register reg containing a byte address. the access may proceed by silently masking off low-order address bits to achieve proper rounding.global. i. { .type [a].type st. A source register wider than the specified type may be used. 32-bit). .1.type st{. . Within these windows.f32. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space.e. i.s8.b16.local. . .f16 data resulting from a cvt instruction may be stored using st.shared }.vec. // // // // named variable d register register-plus-offset immediate address Notes Operand b must be in the . *(d+immOffset) = a. [a].u64.s32.ss}. .vec .v2.s16.type = = = = {. Generic addressing may be used with st. for example.volatile{.type .volatile. { . 32-bit).volatile{.PTX ISA Version 2. . Generic addressing requires sm_20 or later. and truncated if the register width exceeds the state space address width for the target architecture. to enforce sequential consistency between threads accessing shared memory.ss}. perform the store using generic addressing.cop}. This may be used. or the instruction may fault. *(immAddr) = a. . { . If no state space is given. [a]. st. or [immAddr] an immediate absolute byte address (unsigned. If an address is not properly aligned.ss}{.wt }. // store to address // vector store to addr // store to address // vector store to addr // state space // cache operation st.vec. st.ss}{.f64 requires sm_13 or later.shared spaces to inhibit optimization of references to volatile memory.volatile. . PTX ISA Notes Target ISA Notes 116 January 24.0 Table 83.s64. b. .cop}. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.wb.u32.b64. *d = a.

[fs].r7. [p].b32 st.%r.a.f16. // immediate address %r.f32 st.b.global.a.s32 st.s32 cvt.%r. // %r is 32-bit register // store lower 16 bits January 24.b16 [a].b32 st.Q.Chapter 8. [q+4]. [q+-8].local.local.local. Instruction Set Examples st. 2010 117 .global.f32 st. // negative offset [100].v4.

an address maps to the corresponding location in local or shared memory.L1.level prefetchu. [a]. prefetch{. in specified state space. If no state space is given. 32-bit). prefetch prefetchu Syntax Data Movement and Conversion Instructions: prefetch. . to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. prefetchu Prefetch line containing generic address at specified level of memory hierarchy.global. A prefetch into the uniform cache requires a generic address.0. prefetch and prefetchu require sm_20 or later. .global. 118 January 24. Description The prefetch instruction brings the cache line containing the specified address in global or local memory state space into the specified cache level. In generic addressing. prefetchu. Within these windows. and truncated if the register width exceeds the state space address width for the target architecture. // prefetch to data cache // prefetch to uniform cache . .L1 [ptr]. the prefetch uses generic addressing.space}. i. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. [reg+immOff] a sum of register reg containing a byte address plus a constant integer byte offset (signed.0 Table 84. and no operation occurs if the address maps to a local or shared memory location.e. The addressable operand a is one of: [var] [reg] the name of an addressable variable var. 2010 .space = { .L2 }. The prefetchu instruction brings the cache line containing the specified generic address into the specified uniform cache level. or [immAddr] an immediate absolute byte address (unsigned.L1 [a].local }. A prefetch to a shared memory location performs no operation.PTX ISA Version 2. 32-bit). The address size may be either 32-bit or 64-bit.L1 [addr]. a register reg containing a byte address. prefetch.level = { . Addresses are zero-extended to the specified width as needed. an address maps to global memory unless it falls within the local memory window or the shared memory window.

local. isspacep requires sm_20 or later. . p. The destination register must be of type . or vice-versa. PTX ISA Notes Target ISA Notes Examples Table 86. local.global. svar.global isspacep.pred . or shared state space to generic. var. or shared address to a generic address. Introduced in PTX ISA version 2.space = { .u64 }. January 24. isshrd. Instruction Set Table 85.space. cvta requires sm_20 or later.shared }. // get generic address of svar cvta.u32. // local. Use cvt. a. The source and destination addresses must be the same size.space = { . the generic address of the variable may be taken using cvta.u64. gptr. // result is . or vice-versa. local.pred.lptr.u32 gptr. Description Convert a global. Take the generic address of a variable declared in global. . cvta. a.0. or shared state space. or shared state space. Description Write register p with 1 if generic address a falls within the specified state space window and with 0 otherwise.Chapter 8. sptr. cvta.genptr.to. cvta. isspacep.local.shared.space. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. .space p. or shared address cvta.u32 p. local.0. .space.shared }.shared isglbl. lptr.size p. p.size cvta. The source address operand must be a register of type .u32 to truncate or zero-extend addresses. 2010 119 . A program may use isspacep to guard against such incorrect behavior. the resulting address is undefined in cases where the generic address does not fall within the address window of the specified state space.u32.local.local isspacep.global. // convert to generic address // get generic address of var // convert generic address to global. local.global.local.u32 p. isspacep Syntax Data Movement and Conversion Instructions: isspacep Query whether a generic address falls within a specified state space window.u32 or . islcl.size = { . or shared address. When converting a generic address into a global. a. For variables declared in global.size . .u64 or cvt. isspacep.to. . cvta Syntax Data Movement and Conversion Instructions: cvta Convert address from global.u64.

ftz}{. Integer rounding modifiers: .ftz}{.PTX ISA Version 2. i.ftz modifier may be specified in these cases for clarity. .dtype = . . . .sat is redundant.0 Table 87.rp }.f32 float-to-integer conversions and cvt.ftz.rz. Note that saturation applies to both signed and unsigned integer types. subnormal inputs are flushed to signpreserving zero.frnd = { .u16.sat For integer destination types. The optional .s64.sat limits the result to MININT.frnd}{.f32 float-to-integer conversions and cvt. and for same-size float-tofloat conversions where the value is rounded to an integer. The saturation modifier is allowed only in cases where the destination type’s value range is not a superset of the source type’s value range. For cvt.s8.rzi.rm.sat}.rni round to nearest integer.sat}. .atype = { . Note: In PTX ISA versions 1.irnd}{. .rpi }.f32. For float-to-integer conversions. .rzi round to nearest integer in the direction of zero . a. subnormal inputs are flushed to signpreserving zero.. Integer rounding is illegal in all other instances.f16. sm_1x: For cvt.rni. Description Semantics Integer Notes Convert between different types and sizes.u8. .f32 float-tofloat conversions with integer rounding.u64.dtype. . The compiler will preserve this behavior for legacy PTX code. the cvt instruction did not flush single-precision subnormal inputs or results to zero if the destination type size was 64-bits. a.f32 float-tofloat conversions with integer rounding.f32.rpi round to nearest integer in direction of positive infinity Subnormal numbers: sm_20: By default. d. d = convert(a). . subnormal numbers are supported.ftz.dtype. .f32. cvt{. 2010 . .irnd = { . .e.e. the result is clamped to the destination range by default. . .f64 }.rmi.4 and earlier.dtype. . Integer rounding is required for float-to-integer conversions. .ftz.dtype. . 120 January 24.atype cvt{.sat modifier is illegal in cases where saturation is not possible based on the source and destination types. .s32. .MAXINT for the size of the operation. i. .rn.ftz. cvt Syntax Data Movement and Conversion Instructions: cvt Convert a value from one type to another. the .atype d.. Saturation modifier: . // integer rounding // fp rounding .s16.rmi round to nearest integer in direction of negative infinity .u32. choosing even integer if source is equidistant between two integers.

f16.f32 instructions.f64 j. and . .0. cvt to or from . Notes PTX ISA Notes Target ISA Notes Examples Registers wider than the specified source or destination types may be used. NaN results are flushed to positive zero. Modifier .Chapter 8.f32.f32.rni. // float-to-int saturates by default cvt.sat limits the result to the range [0.f64. Specifically.f16.f64 types. sm_1x: Single-precision subnormal inputs and results are flushed to sign-preserving zero. Subnormal numbers: sm_20: By default.s32 f. cvt. Floating-point rounding is illegal in all other instances.version is 1. if the PTX .rp mantissa LSB rounds towards positive infinity A floating-point value may be rounded to an integral value using the integer rounding modifiers (see Integer Notes).f32 x.i. cvt. Saturation modifier: .4 or earlier.f32.0]. Instruction Set Floating Point Notes Floating-point rounding is required for float-to-float conversions that result in loss of precision. // note .y. Introduced in PTX ISA version 1. Floating-point rounding modifiers: . .4 and earlier.r.f32 x.f32. 1.ftz modifier may be specified in these cases for clarity. The result is an integral value. The compiler will preserve this behavior for legacy PTX code. result is fp cvt. stored in floating-point format. The optional .s32. the cvt instruction did not flush single-precision subnormal inputs or results to zero if either source or destination type was . The operands must be of the same size.ftz behavior for sm_1x targets January 24.y.rz mantissa LSB rounds towards zero .rm mantissa LSB rounds towards negative infinity .f64 requires sm_13 or later.sat For floating-point destination types.rn mantissa LSB rounds to nearest even . single-precision subnormal inputs and results are flushed to sign-preserving zero only for cvt. Applies to . 2010 121 .f32.f16. and cvt.f32.ftz may be specified to flush single-precision subnormal inputs and results to sign-preserving zero. // round to nearest int. cvt. Note: In PTX ISA versions 1. subnormal numbers are supported. and for integer-to-float conversions.f32.0.

width. mul. sampler.v4. [tex1]. = nearest width height tsamp1. r3. and surface descriptors: • • • Static initialization of texture.2d.f32 r1. A PTX module may declare only one texturing mode.r3.u32 r5. div.PTX ISA Version 2.target texmode_independent . r1. sampler. 122 January 24. r5.f32 r1. The advantage of independent mode is that textures and samplers can be mixed and matched. add. The texturing mode is selected using . // get tex1’s txq. r5.f32 r1. // get tex1’s tex. cvt.7.f32. the file is assumed to use unified mode. In the unified mode. but the number of samplers is greatly restricted to 16. PTX supports the following operations on texture. If no texturing mode is declared.texref handle. {f1. r6. [tex1].f32.f32 {r1. Ability to query fields within texture.texref tex1 ) { txq. r5.u32 r5. add. Example: calculate an element’s power contribution as element’s power/total number of elements. allowing them to be defined separately and combined at the site of usage in the program. . . and surface descriptors. . samplers.height. texture and sampler information is accessed through a single .6.global .param .entry compute_power ( . r1. PTX has two modes of operation. r2. } = clamp_to_border.. Texturing modes For working with textures and samplers..f32 r3.b32 r6. with the restriction that they correspond 1-to-1 with the 128 possible textures.samplerref tsamp1 = { addr_mode_0 filter_mode }. add. Module-scope and per-entry scope definitions of texture.r2. r1. In the independent mode. The advantage of unified mode is that it allows 128 samplers. [tex1.0 8.f2}].target options ‘texmode_unified’ and ‘texmode_independent’. Texture and Surface Instructions This section describes PTX instructions for accessing textures.r4}. and surfaces. sampler. sampler. texture and sampler information each have their own handle. 2010 . r4. r3. and surface descriptors. and surface descriptors.b32 r5.

s32 {r1. {f1. or the instruction may fault. Operand c is a scalar or singleton tuple for 1d textures. tex Syntax Texture and Surface Instructions: tex Perform a texture memory lookup. //Example of unified mode texturing tex.v4. {f1}].1d. An optional texture sampler b may be specified. . .f32 {r1.3d. tex. c].s32.geom. [tex_a.f3. If an address is not properly aligned. c]. Description Texture lookup using a texture coordinate vector. Extension using opaque texref and samplerref types and independent mode texturing introduced in PTX ISA version 1.f2.dtype = { .btype = { . The instruction loads data from the texture named by operand a at coordinates given by operand c into destination d. tex txq suld sust sured suq Table 88. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. If no sampler is specified. . Instruction Set These instructions provide access to texture and surface memory. is a two-element vector for 2d textures. [tex_a. i.r4}.r2.f32 }.v4. 2010 123 .f32 }.. // Example of independent mode texturing tex. Notes For compatibility with prior versions of PTX. d. .v4.v4 coordinate vectors are allowed for any geometry. Coordinates may be given in either signed 32-bit integer or 32-bit floating point form. where the fourth element is ignored. the square brackets are not required and . b.r3. // explicit sampler .s32. [a. The instruction always returns a four-element vector of 32-bit values.geom. the resulting behavior is undefined. the access may proceed by silently masking off low-order address bits to achieve proper rounding.dtype.v4.3d }.r2.u32. Supported on all target architectures. A texture base address is assumed to be aligned to a 16-byte address.f4}].r4}.1d.0. .Chapter 8. PTX ISA Notes Target ISA Notes Examples January 24. Unified mode texturing introduced in PTX ISA version 1.e.btype d. with the extra elements being ignored. sampler_x.geom = { .s32.s32.2d. [a.5. . . and is a four-element vector for 3d textures.dtype.r3. the sampler behavior is a property of the named texture.btype tex.

addr_mode_1 . txq.b32 txq. addr_mode_2 }.squery. clamp_ogl. . txq Syntax Texture and Surface Instructions: txq Query texture and sampler attributes. . [smpl_B]. . Operand a is a . clamp_to_edge. addr_mode_1.addr_mode_0.addr_mode_0 . .width. d.width . [a].filter_mode.addr_mode_0.normalized_coords .tquery. txq. 2010 .samplerref variable. [tex_A].texref or .height . Description Query an attribute of a texture or sampler. txq.depth .tquery = { . and in independent mode sampler attributes are accessed via a separate samplerref argument. linear } Integer from enum { wrap.0 Table 89.b32 d.depth.filter_mode. Supported on all target architectures. In unified mode. // unified mode // independent mode 124 January 24.PTX ISA Version 2.b32 %r1. .b32 %r1.b32 %r1.squery = { .addr_mode_2 Returns: value in elements 1 (true) or 0 (false). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. mirror.width. Query: . Integer from enum { nearest. [a].normalized_coords }. sampler attributes are also accessed via a texref argument. txq. [tex_A].height.5. // texture attributes // sampler attributes .filter_mode . clamp_to_border } Texture attributes are queried by supplying a texref argument to txq.

.p.trap.v4. . Operand a is a .f32.v4 }.geom .b performs an unformatted load of binary data.f3. suld.clamp. .b64.w}].cop .b8 . suld.geom{..cv }. A surface base address is assumed to be aligned to a 16-byte address. 2010 125 . i. . . .u32. b]. suld. or .v4. {x}]. . suld.b64 }.p. and is a four-element vector for 3d surfaces.0. Cache operations require sm_20 or later.r2}. or FLOAT data. If the destination base type is .cg.b . size and type conversion is performed as needed to convert from the surface sample format to the destination type.u32 is returned.b32. suld. .e.s32. [surf_A.v2.b.b.p .vec. is a two-element vector for 2d surfaces. Coordinate elements are of type .ca.1d. suld.s32. {x.1d. then . the surface sample elements are converted to . . b].s32. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. // cache operation none.s32.b16. suld. if the surface format contains SINT data.u32.zero causes an execution trap on out-of-bounds addresses loads data at the nearest surface location (sized appropriately) loads zero for out-of-bounds addresses PTX ISA Notes suld.clamp . {f1. SNORM. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.Chapter 8.trap suld.v2. then .f32 based on the surface format as follows: If the surface format contains UNORM.f32. . .geom{. [surf_B. additional clamp modifiers.trap introduced in PTX ISA version 1.3d. If the destination type is . the resulting behavior is undefined.trap {r1.3d }. [a.clamp suld. If an address is not properly aligned. suld.f32 is returned.clamp field specifies how to handle out-of-bounds addresses: . The . The lowest dimension coordinate represents a sample offset rather than a byte offset.trap clamping modifier. the access may proceed by silently masking off low-order address bits to achieve proper rounding.vec .3d requires sm_20 or later. // unformatted d. Description Load from surface memory using a surface coordinate vector. . Operand b is a scalar or singleton tuple for 1d surfaces.f2. Destination vector elements corresponding to components that do not appear in the surface format are not written. . . B.cs. and A components of the surface format.trap .s32 is returned.surfref variable.clamp . . // formatted . suld. or the instruction may fault.5.p requires sm_20 or later.p performs a formatted load of a surface sample and returns a four-element vector of 32-bit values corresponding to R. [a. The instruction loads data from the surface named by operand a at coordinates given by operand b into destination d. Instruction Set Table 90.b32.clamp = = = = = = { { { { { { d. sm_1x targets support only the .2d.zero }. .dtype .cop}.dtype .b.u32. .cop}.y.dtype.f4}.p. and cache operations introduced in PTX ISA version 2. then . suld Syntax Texture and Surface Instructions: suld Load from surface memory. .b supported on all target architectures.p is currently unimplemented.f32 }.dtype. Target ISA Notes Examples January 24. or .b32. // for suld. G. and the size of the data transfer matches the size of destination operand d. // for suld. if the surface format contains UINT data.z. . where the fourth element is ignored.

cs. Cache operations require sm_20 or later.geom{.u32.b performs an unformatted store of binary data. [a.v4.p requires sm_20 or later. Source elements that do not occur in the surface sample are ignored. .5.p performs a formatted store of a vector of 32-bit data values to a surface sample. .3d requires sm_20 or later. .clamp .b16.b.zero }. If the source base type is . the source data interpretation is based on the surface sample format as follows: If the surface format contains UNORM.geom .w}].z. .PTX ISA Version 2. c. The instruction stores data from operand c to the surface named by operand a at coordinates given by operand b. . sust. then .wt }.s32. If the source type is . A surface base address is assumed to be aligned to a 16-byte address. . then .b supported on all target architectures.f32 is assumed.cop .v2. // for sust.r2}. . The source data is then converted from this type to the surface sample format. or the instruction may fault. Coordinate elements are of type . b]. and A surface components.b64. Operand b is a scalar or singleton tuple for 1d surfaces. .y. sust. . sust.trap.0 Table 91.s32. Target ISA Notes Examples 126 January 24.ctype.1d.geom{.surfref variable. and cache operations introduced in PTX ISA version 2.b32. SNORM.vec. size and type conversions are performed as needed between the surface sample format and the destination type.clamp . .s32.f32} are currently unimplemented. The .clamp = = = = = = { { { { { { [a. none.vec . If an address is not properly aligned. if the surface format contains UINT data.{u32. sm_1x targets support only the .trap . // unformatted // formatted . sust.trap sust. and is a four-element vector for 3d surfaces. .ctype . sust.zero causes an execution trap on out-of-bounds addresses stores data at the nearest surface location (sized appropriately) drops stores to out-of-bounds addresses PTX ISA Notes sust. b]. These elements are written to the corresponding surface sample components. 2010 . is a two-element vector for 2d surfaces. {x}].3d }.b32. [surf_B.ctype. sust.ctype .v4 }. c. {x. .f2.b8 . additional clamp modifiers.. .u32 is assumed. The lowest dimension coordinate represents a byte offset into the surface and is not scaled.1d.trap [surf_A. . .3d.p Description Store to surface memory using a surface coordinate vector. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. {f1. . sust Syntax Texture and Surface Instructions: sust Store to surface memory. sust.trap clamping modifier. then .cg.b. Operand a is a . sust. sust.2d. where the fourth element is ignored.b.p.v2.f32.trap introduced in PTX ISA version 1.wb.p. if the surface format contains SINT data. {r1.e.p.clamp. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32.f3.s32.b64 }.s32 is assumed. B.f32 }. .cop}. i.f32. . . Surface sample components that do not occur in the source vector will be written with an unpredictable value. or FLOAT data.vec.b // for sust. the resulting behavior is undefined.b32.p. The source vector elements are interpreted left-to-right as R. The lowest dimension coordinate represents a sample offset rather than a byte offset. or .clamp sust. G.cop}.clamp field specifies how to handle out-of-bounds addresses: .0. . The size of the data transfer matches the size of source operand c.f4}.

Coordinate elements are of type . If an address is not properly aligned. or .ctype = { .b. The .u64 data. The lowest dimension coordinate represents a sample offset rather than a byte offset. if the surface format contains SINT data.s32 or . i.2d.e.add. .u32 based on the surface sample format as follows: if the surface format contains UINT data.b]. .trap [surf_A. Reduction to surface memory using a surface coordinate vector. . The lowest dimension coordinate represents a byte offset into the surface and is not scaled. is a two-element vector for 2d surfaces.0. .trap .p. [surf_B. Operations add applies to . A surface base address is assumed to be aligned to a 16-byte address. sured requires sm_20 or later. 2010 127 . sured.b32.ctype = { .u64.ctype. or the instruction may fault.p performs a reduction on sample-addressed 32-bit data. the resulting behavior is undefined. r1. sured.s32. .Chapter 8.min. then .zero }. . {x}]. . and .c. where the fourth element is ignored.clamp field specifies how to handle out-of-bounds addresses: . .max.trap sured. .b performs an unformatted reduction on . then .b32 type. January 24.b . // byte addressing sured. . sured.ctype.u32 is assumed. sured.op.u32.b32 }. and the address given by the coordinate vector must be naturally aligned to a multiple of the access size. The instruction type is restricted to . the access may proceed by silently masking off low-order address bits to achieve proper rounding.zero causes an execution trap on out-of-bounds addresses performs reduction at the nearest surface location (sized appropriately) drops operations to out-of-bounds addresses Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. sured Syntax Texture and Surface Instructions: sured Reduction in surface memory.clamp [a. {x.3d }.op.c.surfref variable. min and max apply to . .geom. and the data is interpreted as .and. .clamp = { .clamp [a. .min. The instruction performs a reduction operation with data from operand c to the surface named by operand a at coordinates given by operand b. Operand b is a scalar or singleton tuple for 1d surfaces..p .b.1d.2d. // for sured. operations and and or apply to .u32.add.b32.trap.y}].op = { . and is a four-element vector for 3d surfaces. . Instruction Set Table 92.or }. // for sured. r1.1d.s32 is assumed.p.geom = { . // sample addressing .clamp . Operand a is a .s32.b32. . .s32.b].s32 types.geom.u32.b32 }.u32 and .u64.u32.s32 types.clamp.

Operand a is a .height . [a].height.width.b32 %r1. 128 January 24.b32 d.depth }. 2010 .query.width . suq Syntax Texture and Surface Instructions: suq Query a surface attribute. .PTX ISA Version 2. [surf_A].depth PTX ISA Notes Target ISA Notes Examples Returns: value in elements Introduced in PTX ISA version 1.surfref variable. Query: .5. . suq. Description Query an attribute of a surface. .0 Table 93.query = { . Supported on all target architectures.width. suq.

Supported on all target architectures.s32 d.c. 2010 129 . ratio. @ Syntax Description Semantics PTX ISA Notes Control Flow Instructions: @ Predicated execution.y // is y zero? // avoid division by zero // conditional branch Target ISA Notes Examples January 24. Supported on all target architectures.0.Chapter 8. Control Flow Instructions {} @ bra call ret exit The following PTX instructions and syntax are for controlling execution in a PTX program: Table 94. { add. { instructionList } The curly braces create a group of instructions. setp. mov.7.b. used primarily for defining a function body.eq. Introduced in PTX ISA version 1.x. p.0. {} Syntax Description Control Flow Instructions: { } Instruction grouping. The curly braces also provide a mechanism for determining the scope of a variable: any variable declared within a scope is not available outside the scope. Threads with a false guard predicate do nothing. @{!}p instruction.f32 @q bra L23.7. If {!}p then instruction Introduced in PTX ISA version 1.0.s32 a.y.a. } PTX ISA Notes Target ISA Notes Examples Table 95.f32 @!p div. Execute an instruction or instruction block for threads that have the guard predicate true. Instruction Set 8.

PTX ISA Version 2.0

Table 96.
bra Syntax Description

Control Flow Instructions: bra
Branch to a target and continue execution there. @p bra{.uni} bra{.uni} tgt; tgt; // direct branch, tgt is a label // unconditional branch

Continue execution at the target. Conditional branches are specified by using a guard predicate. The branch target must be a label. bra.uni is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and branch target. Indirect branch via a register is not supported.

Semantics

if (p) { pc = tgt; } Direct branch introduced in PTX ISA version 1.0. Supported on all target architectures. @q bra.uni bra L_exit; L23; // uniform unconditional jump // conditional branch

PTX ISA Notes Target ISA Notes Examples

Table 97.
call Syntax

Control Flow Instructions: call
Call a function, recording the return location. // direct call to named function, func is a symbol call{.uni} (ret-param), func, (param-list); call{.uni} func, (param-list); call{.uni} func; The call instruction stores the address of the next instruction, so execution can resume at that point after executing a ret instruction. A call is assumed to be divergent unless the .uni suffix is present, indicating that the call is guaranteed to be non-divergent, meaning that all threads in a warp have identical values for the guard predicate and call target. The called location func must be a symbolic function name; indirect call via a register is not supported. Input arguments and return values are optional. Arguments may be registers, immediate constants, or variables in .param space. Arguments are pass-by-value.

Description

Notes PTX ISA Notes Target ISA Notes Examples

In the current ptx release, parameters are passed through statically allocated registers; i.e., there is no support for recursive calls. Direct call introduced in PTX ISA version 1.0. Supported on all target architectures. call init; // call function ‘init’ call.uni g, (a); // call function ‘g’ with parameter ‘a’ call (d), h, (a, b); // return value into register d

@p

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Chapter 8. Instruction Set

Table 98.
ret Syntax Description

Control Flow Instructions: ret
Return from function to instruction after call. ret{.uni}; Return execution to caller’s environment. A divergent return suspends threads until all threads are ready to return to the caller. This allows multiple divergent ret instructions. A ret is assumed to be divergent unless the .uni suffix is present, indicating that the return is guaranteed to be non-divergent. Any values returned from a function should be moved into the return parameter variables prior to executing the ret instruction. A return instruction executed in a top-level entry routine will terminate thread execution. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p ret; ret;

PTX ISA Notes Target ISA Notes Examples

Table 99.
exit Syntax Description PTX ISA Notes

Control Flow Instructions: exit
Terminate a thread. exit; Ends execution of a thread. Introduced in PTX ISA version 1.0. Supported on all target architectures. @p exit; exit;

Target ISA Notes Examples

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131

PTX ISA Version 2.0

8.7.8. Parallel Synchronization and Communication Instructions
These instructions are:
bar membar atom red vote

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Since barriers are executed on a per-warp basis.and and .sync and bar. b. Operand b specifies the number of threads participating in the barrier. and d have type . and the arrival count for the barrier is incremented by the warp size (not the number of active threads in the warp).u32. a{. In addition to signaling its arrival at the barrier.or }. b. thread count.popc. Parallel Synchronization and Communication Instructions: bar bar Syntax Barrier synchronization. bar. thread count. bar.red performs a predicate reduction across the threads participating in the barrier. operands p and c are predicates.popc). and then safely read values stored by other threads prior to the barrier.red.sync and bar. b}. . January 24. bar. Register operands.cta. Instruction Set Table 100. a bar instruction should only be used if it is known that all threads evaluate the condition identically (the warp does not diverge).sync 0. bar. the waiting threads are restarted without delay. p. Each CTA instance has sixteen barriers numbered 0. The c predicate (or its complement) from all threads in the CTA are combined using the specified reduction operator. a.arrive. The barrier instructions signal the arrival of the executing threads at the named barrier. {!}c. and any-thread-true (. 2010 133 .sync bar. Register operands.{arrive. The result of . Thus.pred . When a barrier completes. All threads in the warp are stalled until the barrier completes.red instructions cause the executing thread to wait until all or a specified number of threads in the CTA arrive at the barrier before resuming execution. b}.red} require sm_20 or later. bar. bar. while . In conditionally executed code.arrive a{.or indicate if all the threads had a true predicate or if any of the threads had a true predicate.{arrive. {!}c. the bar. if any thread in a warp executes a bar instruction. d.sync with an immediate barrier number is supported for sm_1x targets.op = { .arrive using the same active barrier.and). execute a bar. Source operand a specifies a logical barrier resource as an immediate constant or register with value 0 through 15. a{.red instruction. Operands a.Chapter 8.popc is the number of threads with a true predicate. and the barrier is reinitialized so that it can be immediately reused.. Barriers are executed on a per-warp basis as if all the threads in a warp are active.version 2. the final value is written to the destination register in all threads waiting at the barrier. and bar. it is as if all the threads in the warp have executed the bar instruction.sync or bar. bar. Once the barrier count is reached.15. Cooperative thread arrays use the bar instruction for barrier synchronization and communication between threads. Execution in this case is unpredictable. all-threads-true (. b}.arrive does not cause any waiting by the executing threads. Note that a non-zero thread count is required for bar. PTX ISA Notes Target ISA Notes Examples bar. If no thread count is specified.red delays the executing threads (similar to bar.red should not be intermixed with bar.sync without a thread count introduced in PTX ISA 1. bar. all threads in the CTA participate in the barrier.u32 bar.sync) until the barrier count is met. the optional thread count must be a multiple of the warp size. Description Performs barrier synchronization and communication within a CTA.0. it simply marks a thread's arrival at the barrier. The reduction operations for bar.0. threads within a CTA that wish to communicate via memory can store to memory.and.red.op.red also guarantee memory ordering among threads identical to membar.red} introduced in PTX . Only bar.red performs a reduction operation across threads. bar.or).sync or bar. and bar.red are population-count (. Thus.

membar.gl.gl will typically have a longer latency than membar. Waits until prior memory reads have been performed with respect to other threads in the CTA.sys.g. or system memory level. This level of membar is required to insure performance with respect to a host CPU or other PCI-E peers.g. membar. . membar.level = { .gl. membar. and memory reads by this thread can no longer be affected by other thread writes. by ld or atom) has been performed when the value read has been transmitted from memory and cannot be modified by another thread at the indicated level.gl. . A memory write (e.version 1.0 Table 101.version 2. Thread execution resumes after a membar when the thread's prior memory writes are visible to other threads at the specified level. membar. Parallel Synchronization and Communication Instructions: membar membar Syntax Memory barrier. membar. by st.sys will typically have much longer latency than membar. A memory read (e. 2010 .gl} introduced in PTX . level describes the scope of other clients for which membar is an ordering event. .PTX ISA Version 2. this is the appropriate level of membar. membar.cta. membar.sys introduced in PTX . For communication between threads in different CTAs or even different SMs.cta Waits until all prior memory writes are visible to other threads in the same CTA. membar.{cta. that is.gl Waits until all prior memory requests have been performed with respect to all other threads in the GPU. red or atom) has been performed when the value written has become visible to other clients at the specified level.0.level.gl} supported on all target architectures. membar. membar. PTX ISA Notes Target ISA Notes Examples membar. global.cta.sys requires sm_20 or later. Description Waits for all prior memory accesses requested by this thread to be performed at the CTA. including thoses communicating via PCI-E such as system and peer-to-peer memory. 134 January 24.4. when the previous value can no longer be read.sys }.{cta. membar.cta.sys Waits until all prior memory requests have been performed with respect to all clients.

op = { . d. Addresses are zero-extended to the specified width as needed.global. inc. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. cas (compare-and-swap). b. . For atom. . The inc and dec operations return a result in the range [0. Operand a specifies a location in the specified state space.type atom{. min.xor. and truncated if the register width exceeds the state space address width for the target architecture. . . A register containing an address may be declared as a bit-size type or integer type. 32-bit operations.e. . . and exch (exchange).op. atom.op. i. by inserting barriers between normal stores and atomic operations to a common address.b32 only . and max operations are single-precision. [a]. e. . . The bit-size operations are and.cas.type = { .g. Instruction Set Table 102. .Chapter 8.f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero. Atomic operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address. min.. . The address size may be either 32-bit or 64-bit. an address maps to global memory unless it falls within the local memory window or the shared memory window. the resulting behavior is undefined. overwriting the original value. accesses to local memory are illegal. [a]. c. . In generic addressing.e. The address must be naturally aligned to a multiple of the access size. . Parallel Synchronization and Communication Instructions: atom atom Syntax Atomic reduction operations for thread-to-thread communication.s32. The floating-point add.u32 only . .s32.dec. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.u32.space}.u64 . .b32. .add. perform the memory accesses using generic addressing. . . Description // // // // // .b64.shared }.. or the instruction may fault.add. min.b64 .f32 Atomically loads the original value at location a into destination register d. i. and max. . The integer operations are add.or.inc. Within these windows. performs a reduction operation with operand b and the value in location a. the access may proceed by silently masking off low-order address bits to achieve proper rounding.u32. a de-referenced register areg containing a byte address. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory atomic instructions.b32.and. . January 24. dec.b].min. max.type d. xor. . or. or by using atom.u64. The floating-point operations are add. 2010 135 . and stores the result of the specified operation at location a. . . If an address is not properly aligned. b. atom{.f32.exch.f32 }.max }. If no state space is given.exch to store to locations accessed by other atomic operations.space = { .u32. . .space}. an address maps to the corresponding location in local or shared memory.s32. or [immAddr] an immediate absolute byte address.

0.add. Simple reductions may be specified by using the “bit bucket” destination operand ‘_’.shared requires sm_12 or later. 64-bit atom. s) = s. Release Notes Examples @p 136 January 24.exch} requires sm_12 or later. 2010 . d. 64-bit atom.0. b.cas.shared operations require sm_20 or later.s.s32 atom.f32. Introduced in PTX ISA version 1. c) operation(*a. s) = (r >= s) ? 0 dec(r.[p]. : r-1.[x+4].my_new_val.add.shared.max. : r. Use of generic addressing requires sm_20 or later.f32 atom.1.{min. *a = (operation == cas) ? : } where inc(r. atom.PTX ISA Version 2.max} are unimplemented. atom.global requires sm_11 or later.global.0 Semantics atomic { d = *a.f32 requires sm_20 or later. atom.b32 d.t) = (r == s) ? t operation(*a.[a]. : r+1. atom. Notes PTX ISA Notes Target ISA Notes Operand a must reside in either the global or shared state space.global. atom. b). d.my_val. cas(r.cas.{add. s) = (r > s) ? s exch(r.

s) = (r >= s) ? 0 : r+1. In generic addressing. For red. or. . an address maps to global memory unless it falls within the local memory window or the shared memory window. Description // // // // . . b).inc.space = { . . inc. A register containing an address may be declared as a bit-size type or integer type.u64 . by inserting barriers between normal stores and reduction operations to a common address. .type = { . max. Parallel Synchronization and Communication Instructions: red red Syntax Reduction operations on global and shared memory. perform the memory accesses using generic addressing. The addressable operand a is one of: [avar] [areg] the name of an addressable variable avar.add.b]. The integer operations are add. . a de-referenced register areg containing a byte address. and max. dec. .global. and max operations are single-precision.dec. where inc(r. . and stores the result of the specified operation at location a. . If no state space is given.f32 }. and truncated if the register width exceeds the state space address width for the target architecture. to the address formed by subtracting the window base from the generic address to form the offset in the implied state space. January 24. It is the programmer’s responsibility to guarantee correctness of programs that use shared memory reduction instructions. .b32.b64. Notes Operand a must reside in either the global or shared state space. . i. .op..and.g. . an address maps to the corresponding location in local or shared memory. accesses to local memory are illegal. The floating-point add.e. The address size may be either 32-bit or 64-bit. red{. Semantics *a = operation(*a. min. .f32 rounds to nearest even and flushes subnormal inputs and results to sign-preserving zero.u64. Instruction Set Table 103. Operand a specifies a location in the specified state space.e. dec(r.xor. .min. .u32 only . or the instruction may fault.u32. red.shared }. Within these windows. and xor. . overwriting the original value. 32-bit operations. e. min. . i.. The bit-size operations are and. .add. Addresses are zero-extended to the specified width as needed.exch to store to locations accessed by other reduction operations.s32. . . 2010 137 .f32. b. If an address is not properly aligned.type [a].f32 Performs a reduction operation with operand b and the value in location a. Reduction operations on shared memory locations do not guarantee atomicity with respect to normal store instructions to the same address.space}.s32. the resulting behavior is undefined. The address must be naturally aligned to a multiple of the access size. s) = (r > s) ? s : r-1.op = { . the access may proceed by silently masking off low-order address bits to achieve proper rounding. or by using atom. [areg+immOff] a de-referenced sum of register areg containing a byte address plus a constant integer byte offset.b32 only .u32. The inc and dec operations return a result in the range [0.u32. min.or.Chapter 8. or [immAddr] an immediate absolute byte address. The floating-point operations are add.s32. .max }.

max} are unimplemented.{min.b32 [a].s32 red.global requires sm_11 or later red.0 PTX ISA Notes Target ISA Notes Introduced in PTX ISA version 1. Use of generic addressing requires sm_20 or later.max. 64-bit red.2. red.shared operations require sm_20 or later. [p].shared requires sm_12 or later.and.f32.PTX ISA Version 2. Release Notes Examples @p 138 January 24.global. red.f32 requires sm_20 or later. [x+4].1. red. 2010 . 64-bit red.global.add requires sm_12 or later.0. red.shared.f32 red.my_val.add.add.

vote.Chapter 8. // get ‘ballot’ across warp January 24. .uni True if source predicate has the same value in all active threads in warp.q. . The reduction modes are: . p. 2010 139 . vote.pred d. not across an entire CTA.q.any True if source predicate is True for some active thread in warp. .b32 p.2.mode.uni }. Description Performs a reduction of the source predicate across threads in a warp.b32 requires sm_20 or later. returns bitmask .all.any.pred vote.ballot.all True if source predicate is True for all active threads in warp. vote. Instruction Set Table 104. In the ‘ballot’ form. Negate the source predicate to compute . {!}a. {!}a. . Negate the source predicate to compute .uni. Parallel Synchronization and Communication Instructions: vote vote Syntax Vote across thread group.ballot. Note that vote applies to threads in a single warp. // ‘ballot’ form. where the bit position corresponds to the thread’s lane id.none. r1. vote requires sm_12 or later. Negating the source predicate also computes .b32 simply copies the predicate from each thread in a warp into the corresponding bit position of destination register d.uni.all.mode = { .not_all. vote. PTX ISA Notes Target ISA Notes Release Notes Examples Introduced in PTX ISA version 1.b32 d.pred vote.ballot. vote. The destination predicate value is the same across all threads in the warp.p.ballot.

asel}. half-word. taking into account the subword destination size in the case of optional data merging.sat} d.sat}. perform a scalar arithmetic operation to produce a signed 34-bit result. .atype.or zero-extend byte.dsel. the input values are extracted and signor zero. The intermediate result is optionally clamped to the range of the destination type (signed or unsigned).btype = { . The type of each operand (. 3.btype{.asel}.bsel = { .s34 intermediate result. c. and btype are valid.atype = . .b2.dtype = . . atype. The video instructions are: vadd vsub vabsdiff vmin vmax vshl vshr vmad vset The video instructions execute the following stages: 1. b{. to produce signed 33-bit input values.0 8. // 32-bit scalar operation. .s32 }. 2. . .dsel = .h1 }.b0.b3.s32) is specified in the instruction type.extended internally to .atype.9.max }. 140 January 24.dtype.asel}.sat} d. The source and destination operands are all 32-bit registers.btype{.bsel}.PTX ISA Version 2. . c.min.dtype. . with optional data merge vop. The general format of video instructions is as follows: // 32-bit scalar operation.7. a{. or b) truncate the intermediate result to a byte or half-word value and merge into a specified position in the third operand to produce the final result. with optional secondary operation vop.h0. all combinations of dtype. a{. The sign of the intermediate result depends on dtype. Video Instructions All video instructions operate on 32-bit register operands.secop = { .dtype. b{.bsel}. . 2010 . a{. optionally perform one of the following: a) apply a second operation to the intermediate result and a third operand. or word values from its source operands.asel = . .bsel}. 4.b1. The primary operation is then performed to produce an .u32 or .btype{.add.u32. extract and sign. optionally clamp the result to the range of the destination type. b{.atype.s33 values. Using the atype/btype and asel/bsel specifiers. vop.secop d. .

default: return tmp. U32_MAX.s33 optSaturate( . tmp.h1: if ( sign ) return CLAMP( else return CLAMP( default: if ( sign ) return CLAMP( else return CLAMP( } } tmp. . U16_MIN ). Bool sign. tmp.s33 optSecOp(Modifier secop. This intermediate result is then optionally combined with the third source operand using a secondary arithmetic operation or subword data merge.s33 optMerge( Modifier dsel. c).h1: return ((tmp & 0xffff) << 16) case .add: return tmp + c. U32_MIN ). c). . . } } { | | | | | | (0xffff0000 (0x0000ffff (0xffffff00 (0xffff00ff (0xff00ffff (0x00ffffff & & & & & & c).b0: return ((tmp & 0xff) case . tmp. U16_MAX.b2: return ((tmp & 0xff) << 16) case . . c). S32_MAX. } } . c). tmp.b1. Instruction Set . switch ( dsel ) { case . as shown in the following pseudocode.s33 tmp. The sign of the c operand is based on dtype. Modifier dsel ) { if ( !sat ) return tmp.b1: return ((tmp & 0xff) << 8) case . S16_MAX.s33 c) { switch ( secop ) { .s33 tmp. S16_MIN ).b2.max return MAX(tmp. . S32_MIN ). January 24.b3: if ( sign ) return CLAMP( else return CLAMP( case . Bool sat.h0. . The lower 32-bits are then written to the destination operand.b3: return ((tmp & 0xff) << 24) default: return tmp. . U8_MIN ).min: return MIN(tmp. 2010 141 .s33 c ) switch ( dsel ) { case . S8_MAX. S8_MIN ).s34 tmp.b0. tmp.h0: return ((tmp & 0xffff) case . .Chapter 8. . c). . c). c). U8_MAX. .

bsel}. 2010 . and optional secondary arithmetic operation or subword data merge. a{. tb = partSelectSignExtend( b. b{.btype = { .0 Table 105. tmp = ta – tb.sat vabsdiff. atype. c. .b3. bsel ).vop . tmp. tmp = | ta – tb |.asel}.b0.sat vmin. vsub. .bsel}.dtype. . . // 32-bit scalar operation.dtype.u32.btype{.s32. // 32-bit scalar operation. r3. . tmp = MAX( ta.s32. Integer byte/half-word/word minimum / maximum.dtype .b2. vmax Syntax Integer byte/half-word/word addition / subtraction.min.s32 }. .bsel}. vabsdiff. vadd. c ). PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.atype = .s32. // optional merge with c operand 142 January 24. r3. c. // extract byte/half-word/word and sign. vsub vabsdiff vmin. c. vop. vmin. r2.h0.s32.sat vsub.s32.s32. sat.dsel . vadd. r2.PTX ISA Version 2. Perform scalar arithmetic operation with optional saturate. tb ).b2. c ).sat} d. c.sat} d.max }. .dsel.h1 }. . switch ( vop ) { case vadd: case vsub: case vabsdiff: case vmin: case vmax: } tmp = ta + tb. vabsdiff.s32. d = optSecondaryOp( op2.h1.sat}. taking into account destination type and merge operations tmp = optSaturate( tmp.b0. with optional data merge vop.b1.atype. Semantics // saturate.btype{.b0. btype.add r1. tmp = MIN( ta.s32. r3. asel ). vsub. dsel ).0.op2 Description = = = = { vadd.u32. r1.op2 d. r3.asel}. r1.atype.asel}.sat.s32. with optional secondary operation vop.dtype. . . vmin. b{.bsel = { . r2. tb ).u32. tmp. isSigned(dtype).btype{.asel = . b{. vmax }.h1. vmax require sm_20 or later.or zero-extend based on source operand type ta = partSelectSignExtend( a. . // optional secondary operation d = optMerge( dsel.s32. a{. r1.h0.atype. r2. vmax vadd. vsub. a{. vmin. vabsdiff. Integer byte/half-word/word absolute value of difference.add.h0. { . Video Instructions: vadd.

vop. vshl: Shift a left by unsigned amount in b with optional saturate.asel = .clamp.sat}{. and optional secondary arithmetic operation or subword data merge.wrap r1.u32.bsel = { .dtype.0. { .asel}.u32{. // default is . .mode}. dsel ). vshr vshl.h0. vshr Syntax Integer byte/half-word/word left / right shift. tb = partSelectSignExtend( b.b0. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2.sat}{. Signed shift fills with the sign bit. unsigned shift fills with zero.min. b{. b{. tmp. and optional secondary arithmetic operation or subword data merge. bsel ). Video Instructions: vshl. . with optional data merge vop. a{.mode} d.clamp && tb > 32 ) tb = 32.vop . case vshr: tmp = ta >> tb.h1. .wrap }. .s32 }.op2 Description = = = = = { vshl.b2.atype.b1. atype. r3.u32. sat.b3.u32. taking into account destination type and merge operations tmp = optSaturate( tmp. isSigned(dtype). Instruction Set Table 106.u32{. vshr }.atype = { . 2010 143 .u32. c.bsel}. if ( mode == . } // saturate.asel}. Left shift fills with zero.add.atype. // 32-bit scalar operation.mode} d. if ( mode == . Semantics // extract byte/half-word/word and sign.max }. .op2 d.dtype . . r1. vshr require sm_20 or later.Chapter 8.asel}. d = optSecondaryOp( op2. // optional secondary operation d = optMerge( dsel.clamp . // 32-bit scalar operation.bsel}.s32. .dsel .u32. asel ). .bsel}.mode . vshl. c. b{.u32.dsel. with optional secondary operation vop. a{. r3. January 24. c ).atype. a{.or zero-extend based on source operand type ta = partSelectSignExtend( a. r2. . vshr: Shift a right by unsigned amount in b with optional saturate.sat}{.wrap ) tb = tb & 0x1f.dtype.u32{. . { . .h1 }.dtype. c ). vshl.u32 vshr. switch ( vop ) { case vshl: tmp = ta << tb. tmp. r2. .

The final result is unsigned if the intermediate result is unsigned and c is not negated. otherwise. PTX allows negation of either (a*b) or c.b0.bsel = { . final signed -(U32 * S32) + S32 // intermediate signed.sat}{. The source operands support optional negation with some restrictions. vmad.scale} d.btype{. final signed (S32 * S32) . final unsigned -(U32 * U32) + S32 // intermediate signed.asel}. final signed -(S32 * U32) + S32 // intermediate signed. and scaling.atype = .h1 }. b{. final signed (S32 * U32) .btype. . final signed -(S32 * S32) + S32 // intermediate signed.U32 // intermediate unsigned. final signed (U32 * S32) + S32 // intermediate signed. Depending on the sign of the a and b operands.dtype = .s32 }. Video Instructions: vmad vmad Syntax Integer byte/half-word/word multiply-accumulate. The “plus one” mode (.b3. final signed (S32 * U32) + S32 // intermediate signed. c. “plus one” mode. That is. {-}b{.po{.S32 // intermediate signed. . .S32 // intermediate signed.sat}{.PTX ISA Version 2. the intermediate result is signed.u32.h0. 144 January 24. . {-}c. final signed (U32 * S32) . .dtype. . the following combinations of operands are supported for VMAD: (U32 * U32) + U32 // intermediate unsigned.shr15 }. // 32-bit scalar operation vmad.asel = . .. Input c has the same sign as the intermediate result. final signed (S32 * S32) + S32 // intermediate signed. a{.scale} d. and zero-extended otherwise.asel}.b1.b2.shr7.S32 // intermediate signed.bsel}.po mode. this result is sign-extended if the final result is signed.scale = { . .btype = { . and the operand negates.bsel}. 2010 . (a*b) is negated if and only if exactly one of a or b is negated.atype. Description Calculate (a*b) + c. which is used in computing averages. internally this is represented as negation of the product (a*b). Source operands may not be negated in .0 Table 107.dtype.po) computes (a*b) + c + 1. final signed The intermediate result is optionally scaled via right-shift. . {-}a{. final signed (U32 * U32) . . Although PTX syntax allows separate negation of the a and b operands. with optional operand negates. The intermediate result of (a*b) is unsigned if atype and btype are unsigned and the product (a*b) is not negated.atype. The final result is optionally saturated to the appropriate 32-bit range based on the type (signed or unsigned) of the final result.

Instruction Set Semantics // extract byte/half-word/word and sign. } c128[127:0] = (signedFinal) sext32( c ) : zext ( c ).0. bsel ).or zero-extend based on source operand type ta = partSelectSignExtend( a. lsb = 0. else result = CLAMP(result.negate ^ b. signedFinal = isSigned(atype) || isSigned(btype) || (a. 2010 145 . } else if ( a. -r3. r2. switch( scale ) { case . asel ). } PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. January 24.po ) { lsb = 1. if ( . vmad. vmad requires sm_20 or later. r1. r2. r0. U32_MAX.negate.negate) || c. U32_MIN). tb = partSelectSignExtend( b. lsb = 1. } else if ( c.negate ^ b.shr15: result = (tmp >> 15) & 0xffffffffffffffff.sat vmad. btype. r1. tmp[127:0] = ta * tb.sat ) { if (signedFinal) result = CLAMP(result.Chapter 8. S32_MIN).u32.u32.shr15 r0. S32_MAX.s32.shr7: result = (tmp >> 7) & 0xffffffffffffffff.negate ) { tmp = ~tmp.u32. case . atype. lsb = 1.h0.h0.u32. r3. } if ( .negate ) { c = ~c. tmp = tmp + c128 + lsb.s32.

dsel.btype.h1 }. .lt vset. r2. . b{. with optional secondary arithmetic operation or subword data merge. c ). tmp.eq.0 Table 108. c.atype. a{. .le. c. and therefore the c operand and final result are also unsigned.ne. // optional secondary operation d = optMerge( dsel.bsel}. 2010 .bsel}. r3. b{.op2 d. tb = partSelectSignExtend( b. bsel ).or zero-extend based on source operand type ta = partSelectSignExtend( a.min. . b{.b0. btype. with optional secondary operation vset. .0.ge }. vset requires sm_20 or later. Compare input values using specified comparison.u32.asel}. { .btype. .dsel .h0.cmp d.u32. The intermediate result of the comparison is always unsigned.lt. a{.max }. cmp ) ? 1 : 0.cmp .atype.bsel = { . Semantics // extract byte/half-word/word and sign.cmp. .s32 }.btype.b2. // 32-bit scalar operation. // optional merge with c operand PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. tmp.gt.op2 Description = = = = . c ). tmp = compare( ta. tb. a{.cmp d. vset.bsel}.asel}. r3. with optional data merge vset. r2. . // 32-bit scalar operation.PTX ISA Version 2. vset. 146 January 24. d = optSecondaryOp( op2. . . . .btype = { . . r1.b3.atype . .asel = .s32.u32.ne r1.atype. atype.asel}. asel ).u32.b1. .add. Video Instructions: vset vset Syntax Integer byte/half-word/word comparison.h1. { .

Notes PTX ISA Notes Target ISA Notes Examples Currently. pmevent a.10.0. brkpt. Miscellaneous Instructions The Miscellaneous instructions are: trap brkpt pmevent Table 109. Instruction Set 8. Introduced in PTX ISA version 1. Table 110. Programmatic performance moniter events may be combined with other hardware events using Boolean functions to increment one of the four performance counters. Supported on all target architectures.Chapter 8. Supported on all target architectures. The relationship between events and counters is programmed via API calls from the host. Table 111. trap. there are sixteen performance monitor events. numbered 0 through 15. brkpt requires sm_11 or later. pmevent 7. brkpt Suspends execution Introduced in PTX ISA version 1. Miscellaneous Instructions: pmevent pmevent Syntax Description Performance Monitor event. Miscellaneous Instructions: trap trap Syntax Description PTX ISA Notes Target ISA Notes Examples @p Perform trap operation. trap Abort execution and generate an interrupt to the host CPU. January 24.7. brkpt. Introduced in PTX ISA version 1. Triggers one of a fixed number of performance monitor events.0.4. Miscellaneous Instructions: brkpt brkpt Syntax Description PTX ISA Notes Target ISA Notes Examples @p Breakpoint. with index specified by immediate operand a. trap. @p pmevent 1. 2010 147 .

PTX ISA Version 2. 2010 .0 148 January 24.

%lanemask_lt. %lanemask_ge. …. %clock64 %pm0. %lanemask_le. Special Registers PTX includes a number of predefined.Chapter 9. %pm3 January 24. which are visible as special registers and accessed through mov or cvt instructions. 2010 149 . The special registers are: %tid %ntid %laneid %warpid %nwarpid %ctaid %nctaid %smid %nsmid %gridid %lanemask_eq. read-only variables. %lanemask_gt %clock.

%tid. %tid. The total number of threads in a CTA is (%ntid.0 Table 112. .u16 %rh.x.%tid.u32 %h2. Legacy PTX code that accesses %ntid using 16-bit mov and cvt instructions are supported. Supported on all target architectures. %ntid. // compute unified thread id for 2D CTA mov. %tid component values range from 0 through %ntid–1 in each CTA dimension.v4 .z. // legacy PTX 1.v4 .x. // zero-extend tid.y.x. The %ntid special register contains a 3D CTA shape vector that holds the CTA dimensions. The %tid special register contains a 1D.z == 1 in 1D CTAs. // move tid. . Redefined as .%tid.0. mad.sreg . the fourth element is unused and always returns zero.z == 0 in 1D CTAs.u32 %r1. // CTA shape vector // CTA dimensions A predefined.u32 %r0. The fourth element is unused and always returns zero. Special Registers: %tid %tid Syntax (predefined) Description Thread identifier within a CTA. PTX ISA Notes Introduced in PTX ISA version 1. // thread id vector // thread id components A predefined.%tid.0.z to %r2 Table 113.z == 0 in 2D CTAs. mov.x < %ntid. %ntid.u32 %ntid. The number of threads in each dimension are specified by the predefined special register %ntid.sreg . Redefined as . %tid. CTA dimensions are non-zero. .x.u32 type in PTX 2. mov. per-thread special register initialized with the thread identifier within the CTA.x to %rh Target ISA Notes Examples // legacy PTX 1.y < %ntid. 2D.x. .x code accessing 16-bit component of %tid mov.z).x. the %tid value in unused dimensions is 0. It is guaranteed that: 0 <= %tid. %ntid.z. Special Registers: %ntid %ntid Syntax (predefined) Description Number of thread IDs per CTA.u32 type in PTX 2.z.u32 %h1.y == %ntid. %tid.z PTX ISA Notes Introduced in PTX ISA version 1.u32 %tid.v4. Legacy PTX code that accesses %tid using 16bit mov and cvt instructions are supported. Every thread in the CTA has a unique %tid.%h2. mov.sreg .y.x code Target ISA Notes Examples 150 January 24.u32 %r0. or 3D vector to match the CTA shape.y == %tid. read-only special register initialized with the number of thread ids in each CTA dimension.u32 %tid.x * %ntid.u16 %r2.PTX ISA Version 2.z == 1 in 2D CTAs.u32 %ntid. read-only. %tid.%h1.y * %ntid.y 0 <= %tid.x.%ntid.%tid. %ntid.0. cvt. 2010 . mov.0. Supported on all target architectures.%r0.v4.u16 %rh.%ntid.y.z < %ntid.x 0 <= %tid.sreg .u32.

read-only special register that returns the maximum number of warp identifiers.u32 %laneid. 2010 151 .g. read-only special register that returns the thread’s warp identifier. The warp identifier will be the same for all threads within a single warp.Chapter 9.u32 %r. Introduced in PTX ISA version 1. due to rescheduling of threads following preemption.u32 %warpid. A predefined. Special Registers: %laneid %laneid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Lane Identifier. Special Registers: %warpid %warpid Syntax (predefined) Description Warp Identifier. Table 115. Note that %warpid is volatile and returns the location of a thread at the moment when read.u32 %nwarpid. mov. For this reason. . The warp identifier provides a unique warp number within a CTA but not across CTAs within a grid. Supported on all target architectures. mov. Special Registers: %nwarpid %nwarpid Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples Number of warp identifiers. Special Registers Table 114. January 24. . PTX ISA Notes Target ISA Notes Examples Table 116. Supported on all target architectures. A predefined.sreg . %warpid. mov. The lane identifier ranges from zero to WARP_SZ-1. Introduced in PTX ISA version 1.u32 %r.3. %warpid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution.sreg . . A predefined. %nwarpid requires sm_20 or later. e. read-only special register that returns the thread’s lane within the warp. %nwarpid.3. Introduced in PTX ISA version 2.sreg . but its value may change during execution. %laneid.0.u32 %r. %ctaid and %tid should be used to compute a virtual warp index if such a value is needed in kernel code.

0. Redefined as .sreg .u32 mov.{x.z < %nctaid. // legacy PTX 1. Supported on all target architectures. Legacy PTX code that accesses %nctaid using 16-bit mov and cvt instructions are supported.u16 %r0.u16 %r0. 2010 .u32 %nctaid.0 Table 117.x code Target ISA Notes Examples Table 118.z} < 65.x.z PTX ISA Notes Introduced in PTX ISA version 1.0. %ctaid.u32 %ctaid. with each element having a value of at least 1. It is guaranteed that: 1 <= %nctaid.x < %nctaid.v4. . Special Registers: %ctaid %ctaid Syntax (predefined) Description CTA identifier within a grid.0. // CTA id vector // CTA id components A predefined. mov.sreg .u32 mov.%nctaid. Redefined as . . Special Registers: %nctaid %nctaid Syntax (predefined) Description Number of CTA ids per grid.x.%nctaid. Each vector element value is >= 0 and < 65535.PTX ISA Version 2.z.x code Target ISA Notes Examples 152 January 24. read-only special register initialized with the CTA identifier within the CTA grid. mov.u32 type in PTX 2.x.%ctaid.y 0 <= %ctaid. // Grid shape vector // Grid dimensions A predefined. 2D.sreg .y.%ctaid. The fourth element is unused and always returns zero. Legacy PTX code that accesses %ctaid using 16-bit mov and cvt instructions are supported. %rh.x 0 <= %ctaid. The %nctaid special register contains a 3D grid shape vector. The fourth element is unused and always returns zero. It is guaranteed that: 0 <= %ctaid.536 PTX ISA Notes Introduced in PTX ISA version 1.x.y. depending on the shape and rank of the CTA grid.u32 type in PTX 2.x.z.0. Supported on all target architectures.y.v4. read-only special register initialized with the number of CTAs in each grid dimension.y < %nctaid.v4 .%nctaid. %rh.u32 %ctaid.u32 %nctaid .sreg .%nctaid. or 3D vector. The %ctaid special register contains a 1D.y.v4 . . %ctaid. // legacy PTX 1.

mov. Supported on all target architectures.u32 %nsmid. %nsmid. read-only special register that returns the maximum number of SM identifiers.u32 %r. %gridid.sreg .0. Introduced in PTX ISA version 1.3.u32 %r. . PTX ISA Notes Target ISA Notes Examples Table 121. A predefined. %nsmid requires sm_20 or later. Introduced in PTX ISA version 1. but its value may change during execution. Special Registers: %nsmid %nsmid Syntax (predefined) Description Number of SM identifiers. The SM identifier ranges from 0 to %nsmid-1. Introduced in PTX ISA version 2. %smid. mov. . Special Registers: %gridid %gridid Syntax (predefined) Description Grid identifier. e. so %nsmid may be larger than the physical number of SMs in the device.sreg .sreg . repeated launches of programs may occur. %smid is intended mainly to enable profiling and diagnostic code to sample and log information such as work place mapping and load distribution. The %gridid is used by debuggers to distinguish CTAs within concurrent (small) CTA grids. This variable provides the temporal grid launch number for this context. where each launch starts a grid-of-CTAs. read-only special register initialized with the per-grid temporal grid identifier. mov.g. During execution.0. // initialized at grid launch A predefined.u32 %smid. A predefined.u32 %r. The SM identifier numbering is not guaranteed to be contiguous. Notes PTX ISA Notes Target ISA Notes Examples Table 120. due to rescheduling of threads following preemption.u32 %gridid. Note that %smid is volatile and returns the location of a thread at the moment when read. 2010 153 . read-only special register that returns the processor (SM) identifier on which a particular thread is executing. . Special Registers: %smid %smid Syntax (predefined) Description SM identifier. Special Registers Table 119. PTX ISA Notes Target ISA Notes Examples January 24. Supported on all target architectures.Chapter 9. The SM identifier numbering is not guaranteed to be contiguous.

Introduced in PTX ISA version 2.u32 %r. Special Registers: %lanemask_le %lanemask_le Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Special Registers: %lanemask_lt %lanemask_lt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions less than the thread’s lane number in the warp.u32 %lanemask_le. A predefined. read-only special register initialized with a 32-bit mask with bits set in positions less than or equal to the thread’s lane number in the warp. Introduced in PTX ISA version 2. %lanemask_le. %lanemask_eq. %lanemask_le requires sm_20 or later. %lanemask_lt requires sm_20 or later. 154 January 24. mov. mov. . mov.sreg . read-only special register initialized with a 32-bit mask with a bit set in the position equal to the thread’s lane number in the warp. Table 123.0 Table 122.u32 %r. A predefined.u32 %lanemask_lt. %lanemask_lt.u32 %lanemask_eq. Table 124.sreg .sreg . . . read-only special register initialized with a 32-bit mask with bits set in positions less than the thread’s lane number in the warp. Special Registers: %lanemask_eq %lanemask_eq Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bit set in position equal to the thread’s lane number in the warp. %lanemask_eq requires sm_20 or later. Introduced in PTX ISA version 2.0. A predefined.u32 %r. 2010 .0.PTX ISA Version 2.0.

A predefined. Introduced in PTX ISA version 2.0. Special Registers: %lanemask_gt %lanemask_gt Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. Special Registers: %lanemask_ge %lanemask_ge Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. A predefined. .sreg . read-only special register initialized with a 32-bit mask with bits set in positions greater than or equal to the thread’s lane number in the warp. Table 126. . Introduced in PTX ISA version 2. read-only special register initialized with a 32-bit mask with bits set in positions greater than the thread’s lane number in the warp. %lanemask_gt requires sm_20 or later.Chapter 9.u32 %lanemask_gt. %lanemask_ge requires sm_20 or later. Special Registers Table 125. %lanemask_gt. January 24.sreg .u32 %r. %lanemask_ge. 2010 155 .u32 %r. mov. mov.u32 %lanemask_ge.0.

0 Table 127. .%pm0. Supported on all target architectures.%clock. Table 129. read-only 32-bit unsigned cycle counter. . Special Registers: %clock %clock Syntax (predefined) Description PTX ISA Notes Target ISA Notes Examples A predefined. .u32 r1.u32 %pm0. %clock64 requires sm_20 or later.sreg . %pm3 %pm0.sreg .u32 %clock.PTX ISA Version 2.0. %pm2. %pm1.u64 r1. %pm3. mov.u32 r1. read-only 64-bit unsigned cycle counter. mov. %pm1. Special register %clock is an unsigned 32-bit read-only cycle counter that wraps silently.0. Special register %clock64 is an unsigned 64-bit read-only cycle counter that wraps silently. Table 128. %pm1. Introduced in PTX ISA version 1. 2010 . %pm3 Syntax Description PTX ISA Notes Target ISA Notes Examples Performance monitoring counters. and %pm3 are unsigned 32-bit read-only performance monitor counters. Introduced in PTX ISA version 1. mov. …. 156 January 24. Special Registers: %clock64 %clock Syntax (predefined) Description Notes PTX ISA Notes Target ISA Notes Examples A predefined.sreg . Special Registers: %pm0. %pm2. Their behavior is currently undefined. Supported on all target architectures. %pm2.3.u64 %clock64. Introduced in PTX ISA version 2.%clock64. Special registers %pm0. The lower 32-bits of %clock64 are identical to %clock.

. minor are integers Specifies the PTX language version number.version major. and the target architecture for which the code was generated. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.version .4 January 24. Directives 10.minor // major.0 . PTX File Directives: .version 1. . 2010 157 . Indicates that this file must be compiled with tools having the same major version number and an equal or greater minor version number.version directive.version .version directive. .target Table 130.Chapter 10.version directives are allowed provided they match the original . Duplicate . Supported on all target architectures. Increments to the major number indicate incompatible changes to PTX.1.version 2. Each ptx file must begin with a .0.version Syntax Description Semantics PTX version number. PTX Version and Target Directives The following directives declare the PTX ISA version of the code in the file.

version directive.texref and .target .0 Table 131. sm_11. Adds {atom. 64-bit {atom.f64 storage remains as 64-bits. vote instructions.0. Notes PTX ISA Notes Target ISA Notes Targets of the form ‘compute_xx’ are also accepted as synonyms for ‘sm_xx’ targets.red}. texmode_unified. texmode_independent. generations of SM architectures follow an “onion layer” model.texmode_unified . sm_13. Requires map_f64_to_f32 if any . In general.f64 instructions used. map_f64_to_f32 indicates that all double-precision instructions map to singleprecision regardless of the target architecture.f64 to . Requires map_f64_to_f32 if any . sm_10.texmode_unified) . texture and sampler information is referenced with independent .shared.red}.red}. Introduced in PTX ISA version 1. and an error is generated if an unsupported feature is used. A .samplerref descriptors.target directives can be used to change the set of target features allowed during parsing. Texturing mode: (default is . . The texturing mode is specified for an entire module and cannot be changed within the module. but subsequent .texref descriptor.f64 instructions used. Supported on all target architectures.5. map_f64_to_f32 }. 158 January 24. brkpt instructions.target Syntax Architecture and Platform target. Description Specifies the set of features in the target architecture for which the current ptx code was generated.global.target directive containing a target architecture and optional platform options.target stringlist // comma separated list of target specifiers // sm_2x target architectures // sm_1x target architectures // texturing mode // platform option string = { sm_20. Target sm_20 Description Baseline feature set for sm_20 architecture. sm_12.f64 instructions used. Therefore. Note that . This enables high-level language compilers to compile programs containing type double to target device that do not support double-precision operations. Semantics Target sm_10 sm_11 sm_12 sm_13 Description Baseline feature set. Adds double-precision support.f32. immediately followed by a . Each PTX file must begin with a .texmode_independent texture and sampler information is bound together and accessed via a single .target directives will compile and run only on devices that support all features of the highest-numbered architecture listed in the program. with only half being used by instructions converted from . PTX features are checked against the specified target architecture. PTX code generated for a given target can be run on later generation devices. where each generation adds new features and retains all features of previous generations. PTX File Directives: .target directive specifies a single target architecture. including expanded rounding modifiers. Requires map_f64_to_f32 if any .global. 2010 . Texturing mode introduced in PTX ISA version 1.PTX ISA Version 2. Adds {atom. A program with multiple . Disallows use of map_f64_to_f32. The following table summarizes the features in PTX that vary according to target architecture.

texmode_independent January 24. 2010 159 .target sm_10 // baseline target architecture .target sm_20. Directives Examples .target sm_13 // supports double-precision .Chapter 10.

with optional parameters.b32 y.param.entry .b32 %r2. etc. %ntid. and query instructions and cannot be accessed via ld.texref.samplerref.entry .entry cta_fft . The total memory available for normal (non-opaque type) parameters is limited to 256 bytes for PTX ISA versions 1.entry filter ( . . ld. e. 2010 . store.b32 %r3. .param instructions. At kernel launch. Supported on all target architectures.func Table 132.param space memory and are listed within an optional parenthesized parameter list.PTX ISA Version 2. .param . opaque . 160 January 24.surfref variables may be passed as parameters. [y]. and body for the kernel function.entry kernel-name kernel-body Defines a kernel entry point name.4. Specifying Kernel Entry Points and Functions The following directives specify kernel entry points and functions.2. The shape and size of the CTA executing the kernel are available in special registers. parameter variables are declared in the kernel body. the kernel dimensions and properties are established and made available via special registers. parameters.param. %nctaid. … } .entry Syntax Description Kernel entry point and body. PTX ISA Notes For PTX ISA version 1. [z].5 and later.param instructions. These parameters can only be referenced by name within texture and surface load. ld.g. ld.4 and later. .param { . For PTX ISA versions 1. Parameters may be referenced by name within the kernel body and loaded into registers using ld.b32 %r1. Kernel and Function Directives: .param.b32 %r<99>. parameter variables are declared in the kernel parameter list.0 10. Parameters are passed via . and is extended by 4096 bytes to a limit of 4352 bytes for PTX ISA versions 1.0 through 1.3.b32 z ) Target ISA Notes Examples [x]. . .entry kernel-name ( param-list ) kernel-body .0 through 1. Semantics Specify the entry point for a kernel program.reg . and .b32 x. In addition to normal parameters.param .

param and st. Semantics The PTX syntax hides all details of the underlying calling convention and ABI.x code. (val0. other code.b32 N.0 with target sm_20 allows parameters in the .Chapter 10.reg .reg . and supports recursion. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1.b32 rval.reg . implements an ABI with stack. val1).0.0 with target sm_20 supports at most one return value.f64 dbl) { . . which may use a combination of registers and stack locations to pass parameters. PTX 2. ret. . Parameters in . A . The implementation of parameter passing is left to the optimizing translator. . and recursion is illegal. Kernel and Function Directives: .param state space. foo. Parameters in register state space may be referenced directly within instructions in the function body. } … call (fooval). including input and return parameters and optional function body.func definition with no body provides a function prototype.2 for a description of variadic functions. PTX ISA 2. parameters must be in the register state space. Release Notes For PTX ISA version 1.param space are accessed using ld. 2010 161 . The following built-in functions are provided for accessing the list of variable arguments: %va_start %va_arg %va_arg64 %va_end See Section 7.param instructions in the body. The parameter lists define locally-scoped variables in the function body. Supported on all target architectures. dbl. Variadic functions are currently unimplemented.func fname function-body .func (.func (ret-param) fname (param-list) function-body Defines a function. mov. … Description // return value in fooval January 24. there is no stack.reg .result.b32 rval) foo (. Variadic functions are represented using ellipsis following the last fixed argument.func .func Syntax Function definition.b32 localVar. Directives Table 133. … use N. Parameters must be base types in either the register or parameter state space. if any.func fname (param-list) function-body . Parameter passing is call-by-value.

Note that .minnctapersm directives can be used together to trade-off registers–per-thread against multiprocessor utilization without needed to directly specify a maximum number of registers. 2010 .PTX ISA Version 2.pragma directives may appear at module (file) scope. for example. and .minnctapersm directives may be applied per-entry and must appear between an . registers) to increase total thread count and provide a greater opportunity to hide memory latency. . A warning message is generated if the directives’ constraints are inconsistent or cannot be met for the specified target device.minnctapersm . at entry-scope. to throttle the resource requirements (e.entry directive and its body.maxnctapersm (deprecated) . The directive passes a list of strings to the backend.maxnreg . Currently.pragma values is determined by the backend implementation and is beyond the scope of the PTX ISA.0 10. which pass information to the backend optimizing compiler.maxntid.maxnreg directive specifies the maximum number of registers to be allocated to a single thread. The directives take precedence over any module-level constraints passed to the optimizing backend.g.pragma The . the . 162 January 24. A general . PTX supports the following directives. and the strings have no semantics within the PTX virtual machine model. or as statements within a kernel or device function body. the .pragma directive is supported for passing information to the PTX backend. The .maxntid . These can be used. and the . .maxnreg.maxntid and .3.maxntid directive specifies the maximum number of threads in a thread block (CTA). Performance-Tuning Directives To provide a mechanism for low-level performance tuning. The interpretation of . This may achieve better performance when compiling PTX for multiple devices having different numbers of registers per SM.minnctapersm directive specifies a minimum number of thread blocks to be scheduled on a single multiprocessor (SM).

maxntid Syntax Maximum number of threads in thread block (CTA). .entry bar . The maximum size of each CTA dimension is guaranteed not to be exceeded in any invocation of the kernel in which this directive appears.maxctapersm. Performance-Tuning Directives: . ny.Chapter 10. 2D. 2010 163 . the backend may be able to compile to fewer registers. nz Declare the maximum number of threads in the thread block (CTA).maxntid nx .maxnreg 16 { … } // max regs per thread = 16 PTX ISA Notes Target ISA Notes Examples Table 135.maxntid nx.maxnreg n Declare the maximum number of registers per thread in a CTA. This maximum is specified by giving the maximum extent of each dimention of the 1D.maxntid nx.maxntid 16.3. . The actual number of registers used may be less. ny . Exceeding any of these limits results in a runtime error or kernel launch failure. .entry foo .16. Introduced in PTX ISA version 1.3. or 3D CTA. Supported on all target architectures. or the maximum number of registers may be further constrained by . The maximum number of threads is the product of the maximum extent in each dimension. Supported on all target architectures. . Introduced in PTX ISA version 1. Performance-Tuning Directives: .maxntid 256 .maxntid . Directives Table 134. for example.maxnreg Syntax Description Semantics Maximum number of registers that can be allocated per thread.4 { … } { … } // max threads = 256 // max threads = 1024 Description Semantics PTX ISA Notes Target ISA Notes Examples January 24.entry foo .maxntid and . The compiler guarantees that this limit will not be exceeded.maxnreg .

maxntid 256 . For this reason. Performance-Tuning Directives: .0.maxntid 256 .maxnctapersm Syntax Description Notes Maximum number of CTAs per SM. Supported on all target architectures. Performance-Tuning Directives: .entry foo .minnctapersm 4 { … } 164 January 24.minnctapersm ncta Declare the minimum number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).maxnctapersm ncta Declare the number of CTAs from the kernel’s grid to be mapped to a single multiprocessor (SM).minnctapersm 4 { … } PTX ISA Notes Target ISA Notes Examples Table 137.maxnctapersm. 2010 .PTX ISA Version 2.maxnctapersm to compute an upper-bound on per-thread register usage so that the specified number of CTAs can be mapped to a single multiprocessor.3.maxnctapersm has been renamed to . However.entry foo .minnctapersm in PTX ISA version 2. . The optimizing backend compiler uses .maxntid and . . Deprecated in PTX ISA version 2. Supported on all target architectures.0 as a replacement for . .0.maxnctapersm generally need . if the number of registers used by the backend is sufficiently lower than this bound. .maxnctapersm (deprecated) .maxntid to be specified as well. Introduced in PTX ISA version 2. Optimizations based on . Introduced in PTX ISA version 1.0 Table 136.maxntid to be specified as well. .minnctapersm generally need . Optimizations based on .minnctapersm .minnctapersm Syntax Description Notes PTX ISA Notes Target ISA Notes Examples Minimum number of CTAs per SM. additional CTAs may be mapped to a single multiprocessor.

at entry-scope.0. The interpretation of . . Performance-Tuning Directives: . See Appendix A for descriptions of the pragma strings defined in ptxas. entry-scoped. // disable unrolling in backend Semantics PTX ISA Notes Target ISA Notes Examples // disable unrolling for current kernel .pragma directive may occur at module-scope. Introduced in PTX ISA version 2.pragma Syntax Description Pass directives to PTX backend compiler. 2010 165 .pragma list-of-strings .pragma “nounroll”. .pragma . Directives Table 138. Pass module-scoped.pragma directive strings is implementation-specific and has no impact on PTX semantics.entry foo .pragma “nounroll”. Supported on all target architectures.Chapter 10. { … } January 24. or at statementlevel. The . or statement-level directives to the PTX backend compiler.

Supported on all target architectures.264-1] .section directive.section . 0x6150736f. Deprecated as of PTX 2. Introduced in PTX ISA version 1.x code..byte byte-list // comma-separated hexadecimal byte values .232-1] . 0x00. replaced by . 0x5f736f63 .0 10.4byte 0x6e69616d.quad int64-list // comma-separated hexadecimal integers in range [0.quad label Notes PTX ISA Notes Target ISA Notes Examples The dwarf string is treated as a comment by the PTX parser.0 and replaces the @@DWARF syntax. 0x02.4byte 0x000006b5. 0x00.section . 0x00 166 January 24.2. Table 139.debug_pubnames. 0x63613031.4byte label .byte 0x00.0. The @@DWARF syntax is deprecated as of PTX version 2.PTX ISA Version 2. “”. 0x00 . 2010 . 0x00. 0x00.section directive is new in PTX ISA verison 2. 0x736d6172 .4. @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF @@DWARF .debug_info .4byte .0 but is supported for legacy PTX version 1. @@DWARF dwarf-string dwarf-string may have one of the . @progbits . 0x61395a5f.loc The . 0x00. 0x00000364. 0x00.file .4byte int32-list // comma-separated hexadecimal integers in range [0. Debugging Directives Dwarf-format debug information is passed through PTX files using the following directives: @@DWARF . Debugging Directives: @@DWARF @@DWARF Syntax Dwarf-format information.byte 0x2b..

b32 label . . .264-1] . Source file location.file ..b8 byte-list // comma-separated list of integers in range [0. Debugging Directives: .0.b8 0x2b.section . 0x5f736f63 0x6150736f. 0x00.232-1] . . .b8 0x00.0.debug_pubnames { . 0x00. 0x00 0x61395a5f. Supported on all target architectures. Directives Table 140. Debugging Directives: .section .b32 0x6e69616d.debug_info .255] .b32 0x000006b5.loc Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. Supported on all target architectures.b64 int64-list // comma-separated list of integers in range [0.b64 label PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. 0x736d6172 0x00 Table 141.loc .b32 . replaces @@DWARF syntax. Debugging Directives: . Source file information. .file filename Table 142.file Syntax Description PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 1. } 0x02. 0x00. 0x00.Chapter 10.section Syntax PTX section definition. .. 0x00. 0x63613031. Supported on all target architectures.b32 int32-list // comma-separated list of integers in range [0.0.loc line_number January 24. 2010 167 .section section_name { dwarf-lines } dwarf-lines have the following formats: . . 0x00.. 0x00000364.

b32 foo. . . Supported on all target architectures. . Introduced in PTX ISA version 1. // foo will be externally visible 168 January 24.extern .visible identifier Declares identifier to be externally visible. Linking Directives: . // foo is defined in another module Table 144.extern .visible .extern Syntax Description PTX ISA Notes Target ISA Notes Examples External symbol declaration.extern .visible Syntax Description PTX ISA Notes Target ISA Notes Examples Visible (externally) symbol declaration.visible .global .b32 foo. Linking Directives .0.visible Table 143. Introduced in PTX ISA version 1.6. Linking Directives: . 2010 .0. . Supported on all target architectures.0 10.global .extern identifier Declares identifier to be defined externally.PTX ISA Version 2.

4 PTX ISA 1.5 PTX ISA 2.Chapter 11. CUDA Release CUDA 1.1 CUDA 2.0 CUDA 2.2 CUDA 2.0.1 CUDA 2.0 PTX ISA 1.2 PTX ISA 1. The release history is as follows.1 PTX ISA 1.3 PTX ISA 1.0 driver r195 PTX ISA Version PTX ISA 1. 2010 169 .3 driver r190 CUDA 3. and the remaining sections provide a record of changes in previous releases.0 CUDA 1. Release Notes This section describes the history of change in the PTX ISA and implementation. The first section describes ISA and implementation changes in the current release of PTX ISA 2.0 January 24.

Instructions testp and copysign have been added. 2010 .f32 and mad. These are indicated by the use of a rounding modifier and require sm_20. • • • • • 170 January 24.ftz and . fma.rp rounding modifiers for sm_20 targets. New Features 11.1.1.f32 instruction has been extended with rounding modifiers so that it’s synonymous with fma. and mul now support . The changes from PTX ISA 1.f32 require a rounding modifier for sm_20 targets.ftz modifier may be used to enforce backward compatibility with sm_1x.f32 for sm_20 targets.rn. mad.f32 instruction without rounding is retained so that compilers can generate code for sm_1x targets. Single.f32 maps to fma. A single-precision fused multiply-add (fma) instruction has been added.1.f32 requires sm_20.1. Floating-Point Extensions This section describes the floating-point changes in PTX 2. Changes in Version 2. rcp.and double-precision div. The mad.rm and . The fma.0 11.x code and sm_1x targets. The goal is to achieve IEEE 754 compliance wherever possible. Single-precision add.0 11.0 for sm_20 targets.x are as follows: • Single-precision instructions support subnormal numbers by default for sm_20 targets.f32. and sqrt with IEEE 754 compliant rounding have been added. while maximizing backward compatibility with legacy PTX 1.1.f32 instruction also supports . The . Both fma.PTX ISA Version 2. The mad. with support for IEEE 754 compliant rounding modifiers and support for subnormal numbers. When code compiled for sm_1x is executed on sm_20 devices.1.sat modifiers. sub.

1. suld. Other new features Instructions ld.arrive instruction has been added. bar now supports optional thread count and register operands.2. January 24.red}. Release Notes 11.pred have been added.le.gt} have been added.or}.shared have been extended to handle 64-bit data types for sm_20 targets.red}.section. e. and red now support generic addressing. %lanemask_{eq. has been added. and sust. brev. The .clamp and . cvta. bfind.minnctapersm to better match its behavior and usage.red. Instructions prefetch and prefetchu have also been added. A “count leading zeros” instruction. Instructions {atom. has been added. %clock64.1. The bar instruction has been extended as follows: • • • A bar. Instructions {atom. Cache operations have been added to instructions ld. Instruction cvta for converting global. Instruction isspacep for querying whether a generic address falls within a specified state space window has been added. Video instructions (includes prmt) have been added. has been added.3. clz.add.ge.u32 and bar. has been added. ldu. has been added.f32 have been implemented. . and shared addresses to generic address and vice-versa has been added. st. atom. st.b32. vote.zero.1.clamp modifiers.sys. local. ldu. popc. New instructions A “load uniform” instruction. membar. . has been added. isspacep. A “bit reversal” instruction. A system-level membar instruction.red.popc. prefetch.Chapter 11. bfe and bfi. has been added to replace the @@DWARF syntax for passing dwarf-format debugging information through PTX. prefetchu.g. have been added. 11.lt. A “find leading non-sign bit” instruction. Instructions bar. A “vote ballot” instruction. New special registers %nsmid. 2010 171 . Instruction sust now supports formatted surface stores. Bit field extract and insert instructions. has been added.maxnctapersm directive was deprecated and replaced with .ballot. Surface instructions support additional .{and. A new directive. A “population count” instruction. for prefetching to specified level of memory hierarchy.1.

single-precision subnormal inputs and results are flushed to sign-preserving zero only when neither source nor destination type size is 64-bits.0 11.ftz (and cvt for . Instruction bra. The number of samplers available in independent texturing mode was incorrectly listed as thirty-two in PTX ISA version 1. the correct number is sixteen. cvt.{min. call suld.1. where single-precision subnormal inputs and results were not flushed to zero if either source or destination type size was 64bits. 172 January 24. Support for variadic functions and alloca are unimplemented.4 or earlier. {atom.{u32. has been fixed.5.ftz is implied) instructions flush single-precision subnormal inputs and results to signpreserving zero for all combinations of floating-point instruction types.ftz for PTX ISA versions 1.s32. Unimplemented Features Remaining The following table summarizes unimplemented instruction features.2. 2010 . or .f32} atom.p sust.u32.red}.max} are not implemented.f32.target sm_1x. Formatted surface load is unimplemented.s32. In PTX version 1.p.f32 type is unimplemented. 11. where . red Application Binary Interface Unimplemented features Indirect branch and call via register are not implemented. See individual instruction descriptions for details. . if .1.5 and later. The underlying.4 and earlier. stack-based ABI is unimplemented. To maintain compatibility with legacy PTX code. Formatted surface store with .PTX ISA Version 2.version is 1.3. Semantic Changes and Clarifications The errata in cvt.

2010 173 .Appendix A. PTX ISA Notes Target ISA Notes Examples Introduced in PTX ISA version 2. Pragma Strings: “nounroll” “nounroll” Syntax Description Disable loop unrolling in optimizing backend compiler. entry-function. and statement levels.0. Supported only for sm_20 targets. Ignored for sm_1x targets. with the following meanings: module scope entry-function scope statement-level pragma disables unrolling for all loops in module. Table 145. Statement-level “nounroll” directives appearing outside of loop header blocks are silently ignored. The loop header block is defined as the block that dominates all blocks in the loop body and is the target of the loop backedge.func bar (…) { … L1_head: .pragma “nounroll”.pragma. .entry foo (…) . disables unrolling of0 the loop for which the current block is the loop header. L1_end: … } // do not unroll this loop January 24. The “nounroll” pragma is allowed at module. L1_body: … L1_continue: bra L1_head. … @p bra L1_end. The “nounroll” pragma is a directive to disable loop unrolling in the optimizing backend compiler. { … } // do not unroll any loop in this function . including loops preceding the .pragma “nounroll”. disables unrolling for all loops in the entry function body.pragma “nounroll”. Descriptions of . Note that in order to have the desired effect at statement level.pragma Strings This section describes the . the “nounroll” directive must appear before any instruction statements in the loop header basic block for the desired loop. .pragma strings defined by ptxas.

0 174 January 24. 2010 .PTX ISA Version 2.

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